initial big import of all of the 4.14 ltsi -rc1 patchesv4.14.70-ltsi-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1796 files changed, 260029 insertions, 0 deletions

diff --git a/patches/0001-drm-bridge-adv7511-Properly-update-EDID-when-no-EDID.patch b/patches/0001-drm-bridge-adv7511-Properly-update-EDID-when-no-EDID.patch
new file mode 100644
index 00000000000000..8aeac1e8073f2e
--- /dev/null
+++ b/patches/0001-drm-bridge-adv7511-Properly-update-EDID-when-no-EDID.patch
@@ -0,0 +1,42 @@
+From 7cdbad6f0040a7cf4449abc309466201849c55a2 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Tue, 5 Sep 2017 14:10:15 +0200
+Subject: [PATCH 0001/1795] drm/bridge: adv7511: Properly update EDID when no
+ EDID was found
+
+Currently adv7511_get_modes() bails out early when no EDID could be
+retrieved. This leaves the previous EDID in place, which is typically not
+the intended behavior and might confuse applications. Instead the EDID
+should be cleared when no EDID could be retrieved.
+
+All functions that are called after the EDID check handle the case where
+the EDID is NULL just fine and exhibit the expected behavior, so just drop
+the check.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Tested-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170905121018.11477-1-lars@metafoo.de
+(cherry picked from commit 6f39ed4f0939e6bef722f0096894c1a986da9c9a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index f5091827628a..13542940056b 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -603,8 +603,6 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
+ 
+ 	kfree(adv7511->edid);
+ 	adv7511->edid = edid;
+-	if (!edid)
+-		return 0;
+ 
+ 	drm_mode_connector_update_edid_property(connector, edid);
+ 	count = drm_add_edid_modes(connector, edid);
+-- 
+2.19.0
+
diff --git a/patches/0002-drm-bridge-adv7511-Remove-private-copy-of-the-EDID.patch b/patches/0002-drm-bridge-adv7511-Remove-private-copy-of-the-EDID.patch
new file mode 100644
index 00000000000000..9e3fcfd5185784
--- /dev/null
+++ b/patches/0002-drm-bridge-adv7511-Remove-private-copy-of-the-EDID.patch
@@ -0,0 +1,97 @@
+From fc1071f9c776f223219b1ddc6fbafe4155fd23be Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Tue, 5 Sep 2017 14:10:16 +0200
+Subject: [PATCH 0002/1795] drm/bridge: adv7511: Remove private copy of the
+ EDID
+
+The adv7511 driver keeps a private copy of the EDID in its driver state
+struct. But this copy is only used in adv7511_get_modes() where it is also
+retrieved, so there is no need to keep this extra copy around.
+
+If a need to access the EDID elsewhere in the driver ever arises the copy
+that is stored in the connector can be used. This copy is accessible
+through drm_connector_get_edid().
+
+Note, this patch removes the NULL check of the EDID before passing it to
+drm_detect_hdmi_monitor(), but that is fine since the function correctly
+handles the case where the EDID is NULL.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Tested-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170905121018.11477-2-lars@metafoo.de
+(cherry picked from commit fcb4c5eee79ea17e1fbc5b3ebbd575d56714fabe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511.h     |  2 --
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 16 ++++++----------
+ 2 files changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+index fe18a5d2d84b..12ef2d8ee110 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+@@ -328,8 +328,6 @@ struct adv7511 {
+ 	enum adv7511_sync_polarity hsync_polarity;
+ 	bool rgb;
+ 
+-	struct edid *edid;
+-
+ 	struct gpio_desc *gpio_pd;
+ 
+ 	struct regulator_bulk_data *supplies;
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 13542940056b..e928c804586e 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -199,17 +199,14 @@ static const uint16_t adv7511_csc_ycbcr_to_rgb[] = {
+ 
+ static void adv7511_set_config_csc(struct adv7511 *adv7511,
+ 				   struct drm_connector *connector,
+-				   bool rgb)
++				   bool rgb, bool hdmi_mode)
+ {
+ 	struct adv7511_video_config config;
+ 	bool output_format_422, output_format_ycbcr;
+ 	unsigned int mode;
+ 	uint8_t infoframe[17];
+ 
+-	if (adv7511->edid)
+-		config.hdmi_mode = drm_detect_hdmi_monitor(adv7511->edid);
+-	else
+-		config.hdmi_mode = false;
++	config.hdmi_mode = hdmi_mode;
+ 
+ 	hdmi_avi_infoframe_init(&config.avi_infoframe);
+ 
+@@ -601,13 +598,14 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
+ 	if (!adv7511->powered)
+ 		__adv7511_power_off(adv7511);
+ 
+-	kfree(adv7511->edid);
+-	adv7511->edid = edid;
+ 
+ 	drm_mode_connector_update_edid_property(connector, edid);
+ 	count = drm_add_edid_modes(connector, edid);
+ 
+-	adv7511_set_config_csc(adv7511, connector, adv7511->rgb);
++	adv7511_set_config_csc(adv7511, connector, adv7511->rgb,
++			       drm_detect_hdmi_monitor(edid));
++
++	kfree(edid);
+ 
+ 	return count;
+ }
+@@ -1168,8 +1166,6 @@ static int adv7511_remove(struct i2c_client *i2c)
+ 
+ 	i2c_unregister_device(adv7511->i2c_edid);
+ 
+-	kfree(adv7511->edid);
+-
+ 	return 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0003-drm-bridge-adv7511-Enable-connector-polling-when-no-.patch b/patches/0003-drm-bridge-adv7511-Enable-connector-polling-when-no-.patch
new file mode 100644
index 00000000000000..72689f1d38f7b3
--- /dev/null
+++ b/patches/0003-drm-bridge-adv7511-Enable-connector-polling-when-no-.patch
@@ -0,0 +1,41 @@
+From 9dcfe6f802ed056ea4e0af187371bbeeaaf17da8 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Tue, 5 Sep 2017 14:10:17 +0200
+Subject: [PATCH 0003/1795] drm/bridge: adv7511: Enable connector polling when
+ no interrupt is specified
+
+Fall back to polling the connector for connect and disconnect events when
+no interrupt is specified. Otherwise these events will not be noticed and
+monitor hotplug does not work.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Tested-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170905121018.11477-3-lars@metafoo.de
+(cherry picked from commit 2f47f1c106d99f367f2924ce35741050fb87e081)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index e928c804586e..37524035486f 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -841,7 +841,11 @@ static int adv7511_bridge_attach(struct drm_bridge *bridge)
+ 		return -ENODEV;
+ 	}
+ 
+-	adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
++	if (adv->i2c_main->irq)
++		adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
++	else
++		adv->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
++				DRM_CONNECTOR_POLL_DISCONNECT;
+ 
+ 	ret = drm_connector_init(bridge->dev, &adv->connector,
+ 				 &adv7511_connector_funcs,
+-- 
+2.19.0
+
diff --git a/patches/0004-drm-bridge-adv7511-Constify-HDMI-CODEC-platform-data.patch b/patches/0004-drm-bridge-adv7511-Constify-HDMI-CODEC-platform-data.patch
new file mode 100644
index 00000000000000..6e8f70213f9877
--- /dev/null
+++ b/patches/0004-drm-bridge-adv7511-Constify-HDMI-CODEC-platform-data.patch
@@ -0,0 +1,37 @@
+From 9049bcc42b52eebd5db97a4f359833be11cb48e2 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Tue, 5 Sep 2017 14:10:18 +0200
+Subject: [PATCH 0004/1795] drm/bridge: adv7511: Constify HDMI CODEC platform
+ data
+
+The HDMI codec platform data is global driver state shared by all
+instances. As such it should not be modified (and is not), to make this
+explicit declare it as const.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Tested-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170905121018.11477-4-lars@metafoo.de
+(cherry picked from commit 1591017442ffb6b0a735abe4f611a203fb632501)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_audio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c b/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c
+index 67469c26bae8..1b4783d45c53 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c
+@@ -210,7 +210,7 @@ static const struct hdmi_codec_ops adv7511_codec_ops = {
+ 	.get_dai_id	= adv7511_hdmi_i2s_get_dai_id,
+ };
+ 
+-static struct hdmi_codec_pdata codec_data = {
++static const struct hdmi_codec_pdata codec_data = {
+ 	.ops = &adv7511_codec_ops,
+ 	.max_i2s_channels = 2,
+ 	.i2s = 1,
+-- 
+2.19.0
+
diff --git a/patches/0005-drm-adv7511-33-add-HDMI-CEC-support.patch b/patches/0005-drm-adv7511-33-add-HDMI-CEC-support.patch
new file mode 100644
index 00000000000000..225bb3f748197d
--- /dev/null
+++ b/patches/0005-drm-adv7511-33-add-HDMI-CEC-support.patch
@@ -0,0 +1,760 @@
+From cd4adaf0b54ed6f4d40e70a50004871467f87dd9 Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hans.verkuil@cisco.com>
+Date: Sat, 7 Oct 2017 12:46:58 +0200
+Subject: [PATCH 0005/1795] drm: adv7511/33: add HDMI CEC support
+
+Add support for HDMI CEC to the drm adv7511/adv7533 drivers.
+
+The CEC registers that we need to use are identical for both drivers,
+but they appear at different offsets in the register map.
+
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171007104658.14528-3-hverkuil@xs4all.nl
+(cherry picked from commit 3b1b975003e4a3da4b93ab032487a3ae4afca7b5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/Kconfig       |   8 +
+ drivers/gpu/drm/bridge/adv7511/Makefile      |   1 +
+ drivers/gpu/drm/bridge/adv7511/adv7511.h     |  43 ++-
+ drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 337 +++++++++++++++++++
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 116 ++++++-
+ drivers/gpu/drm/bridge/adv7511/adv7533.c     |  38 +--
+ 6 files changed, 485 insertions(+), 58 deletions(-)
+ create mode 100644 drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/Kconfig b/drivers/gpu/drm/bridge/adv7511/Kconfig
+index 2fed567f9943..592b9d2ec034 100644
+--- a/drivers/gpu/drm/bridge/adv7511/Kconfig
++++ b/drivers/gpu/drm/bridge/adv7511/Kconfig
+@@ -21,3 +21,11 @@ config DRM_I2C_ADV7533
+ 	default y
+ 	help
+ 	  Support for the Analog Devices ADV7533 DSI to HDMI encoder.
++
++config DRM_I2C_ADV7511_CEC
++	bool "ADV7511/33 HDMI CEC driver"
++	depends on DRM_I2C_ADV7511
++	select CEC_CORE
++	default y
++	help
++	  When selected the HDMI transmitter will support the CEC feature.
+diff --git a/drivers/gpu/drm/bridge/adv7511/Makefile b/drivers/gpu/drm/bridge/adv7511/Makefile
+index 5ba675534f6e..5bb384938a71 100644
+--- a/drivers/gpu/drm/bridge/adv7511/Makefile
++++ b/drivers/gpu/drm/bridge/adv7511/Makefile
+@@ -1,4 +1,5 @@
+ adv7511-y := adv7511_drv.o
+ adv7511-$(CONFIG_DRM_I2C_ADV7511_AUDIO) += adv7511_audio.o
++adv7511-$(CONFIG_DRM_I2C_ADV7511_CEC) += adv7511_cec.o
+ adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
+ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+index 12ef2d8ee110..b4efcbabf7f7 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+@@ -195,6 +195,25 @@
+ #define ADV7511_PACKET_GM(x)	    ADV7511_PACKET(5, x)
+ #define ADV7511_PACKET_SPARE(x)	    ADV7511_PACKET(6, x)
+ 
++#define ADV7511_REG_CEC_TX_FRAME_HDR	0x00
++#define ADV7511_REG_CEC_TX_FRAME_DATA0	0x01
++#define ADV7511_REG_CEC_TX_FRAME_LEN	0x10
++#define ADV7511_REG_CEC_TX_ENABLE	0x11
++#define ADV7511_REG_CEC_TX_RETRY	0x12
++#define ADV7511_REG_CEC_TX_LOW_DRV_CNT	0x14
++#define ADV7511_REG_CEC_RX_FRAME_HDR	0x15
++#define ADV7511_REG_CEC_RX_FRAME_DATA0	0x16
++#define ADV7511_REG_CEC_RX_FRAME_LEN	0x25
++#define ADV7511_REG_CEC_RX_ENABLE	0x26
++#define ADV7511_REG_CEC_RX_BUFFERS	0x4a
++#define ADV7511_REG_CEC_LOG_ADDR_MASK	0x4b
++#define ADV7511_REG_CEC_LOG_ADDR_0_1	0x4c
++#define ADV7511_REG_CEC_LOG_ADDR_2	0x4d
++#define ADV7511_REG_CEC_CLK_DIV		0x4e
++#define ADV7511_REG_CEC_SOFT_RESET	0x50
++
++#define ADV7533_REG_CEC_OFFSET		0x70
++
+ enum adv7511_input_clock {
+ 	ADV7511_INPUT_CLOCK_1X,
+ 	ADV7511_INPUT_CLOCK_2X,
+@@ -297,6 +316,8 @@ enum adv7511_type {
+ 	ADV7533,
+ };
+ 
++#define ADV7511_MAX_ADDRS 3
++
+ struct adv7511 {
+ 	struct i2c_client *i2c_main;
+ 	struct i2c_client *i2c_edid;
+@@ -341,15 +362,27 @@ struct adv7511 {
+ 
+ 	enum adv7511_type type;
+ 	struct platform_device *audio_pdev;
++
++	struct cec_adapter *cec_adap;
++	u8   cec_addr[ADV7511_MAX_ADDRS];
++	u8   cec_valid_addrs;
++	bool cec_enabled_adap;
++	struct clk *cec_clk;
++	u32 cec_clk_freq;
+ };
+ 
++#ifdef CONFIG_DRM_I2C_ADV7511_CEC
++int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
++		     unsigned int offset);
++void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
++#endif
++
+ #ifdef CONFIG_DRM_I2C_ADV7533
+ void adv7533_dsi_power_on(struct adv7511 *adv);
+ void adv7533_dsi_power_off(struct adv7511 *adv);
+ void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
+ int adv7533_patch_registers(struct adv7511 *adv);
+-void adv7533_uninit_cec(struct adv7511 *adv);
+-int adv7533_init_cec(struct adv7511 *adv);
++int adv7533_patch_cec_registers(struct adv7511 *adv);
+ int adv7533_attach_dsi(struct adv7511 *adv);
+ void adv7533_detach_dsi(struct adv7511 *adv);
+ int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
+@@ -372,11 +405,7 @@ static inline int adv7533_patch_registers(struct adv7511 *adv)
+ 	return -ENODEV;
+ }
+ 
+-static inline void adv7533_uninit_cec(struct adv7511 *adv)
+-{
+-}
+-
+-static inline int adv7533_init_cec(struct adv7511 *adv)
++static inline int adv7533_patch_cec_registers(struct adv7511 *adv)
+ {
+ 	return -ENODEV;
+ }
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+new file mode 100644
+index 000000000000..b33d730e4d73
+--- /dev/null
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+@@ -0,0 +1,337 @@
++/*
++ * adv7511_cec.c - Analog Devices ADV7511/33 cec driver
++ *
++ * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++
++#include <media/cec.h>
++
++#include "adv7511.h"
++
++#define ADV7511_INT1_CEC_MASK \
++	(ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \
++	 ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1)
++
++static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_status)
++{
++	unsigned int offset = adv7511->type == ADV7533 ?
++					ADV7533_REG_CEC_OFFSET : 0;
++	unsigned int val;
++
++	if (regmap_read(adv7511->regmap_cec,
++			ADV7511_REG_CEC_TX_ENABLE + offset, &val))
++		return;
++
++	if ((val & 0x01) == 0)
++		return;
++
++	if (tx_raw_status & ADV7511_INT1_CEC_TX_ARBIT_LOST) {
++		cec_transmit_attempt_done(adv7511->cec_adap,
++					  CEC_TX_STATUS_ARB_LOST);
++		return;
++	}
++	if (tx_raw_status & ADV7511_INT1_CEC_TX_RETRY_TIMEOUT) {
++		u8 status;
++		u8 err_cnt = 0;
++		u8 nack_cnt = 0;
++		u8 low_drive_cnt = 0;
++		unsigned int cnt;
++
++		/*
++		 * We set this status bit since this hardware performs
++		 * retransmissions.
++		 */
++		status = CEC_TX_STATUS_MAX_RETRIES;
++		if (regmap_read(adv7511->regmap_cec,
++			    ADV7511_REG_CEC_TX_LOW_DRV_CNT + offset, &cnt)) {
++			err_cnt = 1;
++			status |= CEC_TX_STATUS_ERROR;
++		} else {
++			nack_cnt = cnt & 0xf;
++			if (nack_cnt)
++				status |= CEC_TX_STATUS_NACK;
++			low_drive_cnt = cnt >> 4;
++			if (low_drive_cnt)
++				status |= CEC_TX_STATUS_LOW_DRIVE;
++		}
++		cec_transmit_done(adv7511->cec_adap, status,
++				  0, nack_cnt, low_drive_cnt, err_cnt);
++		return;
++	}
++	if (tx_raw_status & ADV7511_INT1_CEC_TX_READY) {
++		cec_transmit_attempt_done(adv7511->cec_adap, CEC_TX_STATUS_OK);
++		return;
++	}
++}
++
++void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1)
++{
++	unsigned int offset = adv7511->type == ADV7533 ?
++					ADV7533_REG_CEC_OFFSET : 0;
++	const u32 irq_tx_mask = ADV7511_INT1_CEC_TX_READY |
++				ADV7511_INT1_CEC_TX_ARBIT_LOST |
++				ADV7511_INT1_CEC_TX_RETRY_TIMEOUT;
++	struct cec_msg msg = {};
++	unsigned int len;
++	unsigned int val;
++	u8 i;
++
++	if (irq1 & irq_tx_mask)
++		adv_cec_tx_raw_status(adv7511, irq1);
++
++	if (!(irq1 & ADV7511_INT1_CEC_RX_READY1))
++		return;
++
++	if (regmap_read(adv7511->regmap_cec,
++			ADV7511_REG_CEC_RX_FRAME_LEN + offset, &len))
++		return;
++
++	msg.len = len & 0x1f;
++
++	if (msg.len > 16)
++		msg.len = 16;
++
++	if (!msg.len)
++		return;
++
++	for (i = 0; i < msg.len; i++) {
++		regmap_read(adv7511->regmap_cec,
++			    i + ADV7511_REG_CEC_RX_FRAME_HDR + offset, &val);
++		msg.msg[i] = val;
++	}
++
++	/* toggle to re-enable rx 1 */
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_RX_BUFFERS + offset, 1);
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
++	cec_received_msg(adv7511->cec_adap, &msg);
++}
++
++static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
++{
++	struct adv7511 *adv7511 = cec_get_drvdata(adap);
++	unsigned int offset = adv7511->type == ADV7533 ?
++					ADV7533_REG_CEC_OFFSET : 0;
++
++	if (adv7511->i2c_cec == NULL)
++		return -EIO;
++
++	if (!adv7511->cec_enabled_adap && enable) {
++		/* power up cec section */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_CLK_DIV + offset,
++				   0x03, 0x01);
++		/* legacy mode and clear all rx buffers */
++		regmap_write(adv7511->regmap_cec,
++			     ADV7511_REG_CEC_RX_BUFFERS + offset, 0x07);
++		regmap_write(adv7511->regmap_cec,
++			     ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
++		/* initially disable tx */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_TX_ENABLE + offset, 1, 0);
++		/* enabled irqs: */
++		/* tx: ready */
++		/* tx: arbitration lost */
++		/* tx: retry timeout */
++		/* rx: ready 1 */
++		regmap_update_bits(adv7511->regmap,
++				   ADV7511_REG_INT_ENABLE(1), 0x3f,
++				   ADV7511_INT1_CEC_MASK);
++	} else if (adv7511->cec_enabled_adap && !enable) {
++		regmap_update_bits(adv7511->regmap,
++				   ADV7511_REG_INT_ENABLE(1), 0x3f, 0);
++		/* disable address mask 1-3 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
++				   0x70, 0x00);
++		/* power down cec section */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_CLK_DIV + offset,
++				   0x03, 0x00);
++		adv7511->cec_valid_addrs = 0;
++	}
++	adv7511->cec_enabled_adap = enable;
++	return 0;
++}
++
++static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
++{
++	struct adv7511 *adv7511 = cec_get_drvdata(adap);
++	unsigned int offset = adv7511->type == ADV7533 ?
++					ADV7533_REG_CEC_OFFSET : 0;
++	unsigned int i, free_idx = ADV7511_MAX_ADDRS;
++
++	if (!adv7511->cec_enabled_adap)
++		return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
++
++	if (addr == CEC_LOG_ADDR_INVALID) {
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
++				   0x70, 0);
++		adv7511->cec_valid_addrs = 0;
++		return 0;
++	}
++
++	for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
++		bool is_valid = adv7511->cec_valid_addrs & (1 << i);
++
++		if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
++			free_idx = i;
++		if (is_valid && adv7511->cec_addr[i] == addr)
++			return 0;
++	}
++	if (i == ADV7511_MAX_ADDRS) {
++		i = free_idx;
++		if (i == ADV7511_MAX_ADDRS)
++			return -ENXIO;
++	}
++	adv7511->cec_addr[i] = addr;
++	adv7511->cec_valid_addrs |= 1 << i;
++
++	switch (i) {
++	case 0:
++		/* enable address mask 0 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
++				   0x10, 0x10);
++		/* set address for mask 0 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
++				   0x0f, addr);
++		break;
++	case 1:
++		/* enable address mask 1 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
++				   0x20, 0x20);
++		/* set address for mask 1 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
++				   0xf0, addr << 4);
++		break;
++	case 2:
++		/* enable address mask 2 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
++				   0x40, 0x40);
++		/* set address for mask 1 */
++		regmap_update_bits(adv7511->regmap_cec,
++				   ADV7511_REG_CEC_LOG_ADDR_2 + offset,
++				   0x0f, addr);
++		break;
++	}
++	return 0;
++}
++
++static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
++				     u32 signal_free_time, struct cec_msg *msg)
++{
++	struct adv7511 *adv7511 = cec_get_drvdata(adap);
++	unsigned int offset = adv7511->type == ADV7533 ?
++					ADV7533_REG_CEC_OFFSET : 0;
++	u8 len = msg->len;
++	unsigned int i;
++
++	/*
++	 * The number of retries is the number of attempts - 1, but retry
++	 * at least once. It's not clear if a value of 0 is allowed, so
++	 * let's do at least one retry.
++	 */
++	regmap_update_bits(adv7511->regmap_cec,
++			   ADV7511_REG_CEC_TX_RETRY + offset,
++			   0x70, max(1, attempts - 1) << 4);
++
++	/* blocking, clear cec tx irq status */
++	regmap_update_bits(adv7511->regmap, ADV7511_REG_INT(1), 0x38, 0x38);
++
++	/* write data */
++	for (i = 0; i < len; i++)
++		regmap_write(adv7511->regmap_cec,
++			     i + ADV7511_REG_CEC_TX_FRAME_HDR + offset,
++			     msg->msg[i]);
++
++	/* set length (data + header) */
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_TX_FRAME_LEN + offset, len);
++	/* start transmit, enable tx */
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_TX_ENABLE + offset, 0x01);
++	return 0;
++}
++
++static const struct cec_adap_ops adv7511_cec_adap_ops = {
++	.adap_enable = adv7511_cec_adap_enable,
++	.adap_log_addr = adv7511_cec_adap_log_addr,
++	.adap_transmit = adv7511_cec_adap_transmit,
++};
++
++static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
++{
++	adv7511->cec_clk = devm_clk_get(dev, "cec");
++	if (IS_ERR(adv7511->cec_clk)) {
++		int ret = PTR_ERR(adv7511->cec_clk);
++
++		adv7511->cec_clk = NULL;
++		return ret;
++	}
++	clk_prepare_enable(adv7511->cec_clk);
++	adv7511->cec_clk_freq = clk_get_rate(adv7511->cec_clk);
++	return 0;
++}
++
++int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
++		     unsigned int offset)
++{
++	int ret = adv7511_cec_parse_dt(dev, adv7511);
++
++	if (ret)
++		return ret;
++
++	adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
++		adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
++	if (IS_ERR(adv7511->cec_adap))
++		return PTR_ERR(adv7511->cec_adap);
++
++	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
++	/* cec soft reset */
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_SOFT_RESET + offset, 0x01);
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_SOFT_RESET + offset, 0x00);
++
++	/* legacy mode */
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_RX_BUFFERS + offset, 0x00);
++
++	regmap_write(adv7511->regmap_cec,
++		     ADV7511_REG_CEC_CLK_DIV + offset,
++		     ((adv7511->cec_clk_freq / 750000) - 1) << 2);
++
++	ret = cec_register_adapter(adv7511->cec_adap, dev);
++	if (ret) {
++		cec_delete_adapter(adv7511->cec_adap);
++		adv7511->cec_adap = NULL;
++	}
++	return ret;
++}
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 37524035486f..8da5af390e75 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -11,12 +11,15 @@
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+ #include <linux/slab.h>
++#include <linux/clk.h>
+ 
+ #include <drm/drmP.h>
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_edid.h>
+ 
++#include <media/cec.h>
++
+ #include "adv7511.h"
+ 
+ /* ADI recommended values for proper operation. */
+@@ -336,8 +339,10 @@ static void __adv7511_power_on(struct adv7511 *adv7511)
+ 		 */
+ 		regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
+ 			     ADV7511_INT0_EDID_READY | ADV7511_INT0_HPD);
+-		regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
+-			     ADV7511_INT1_DDC_ERROR);
++		regmap_update_bits(adv7511->regmap,
++				   ADV7511_REG_INT_ENABLE(1),
++				   ADV7511_INT1_DDC_ERROR,
++				   ADV7511_INT1_DDC_ERROR);
+ 	}
+ 
+ 	/*
+@@ -373,6 +378,9 @@ static void __adv7511_power_off(struct adv7511 *adv7511)
+ 	regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
+ 			   ADV7511_POWER_POWER_DOWN,
+ 			   ADV7511_POWER_POWER_DOWN);
++	regmap_update_bits(adv7511->regmap,
++			   ADV7511_REG_INT_ENABLE(1),
++			   ADV7511_INT1_DDC_ERROR, 0);
+ 	regcache_mark_dirty(adv7511->regmap);
+ }
+ 
+@@ -435,6 +443,8 @@ static void adv7511_hpd_work(struct work_struct *work)
+ 
+ 	if (adv7511->connector.status != status) {
+ 		adv7511->connector.status = status;
++		if (status == connector_status_disconnected)
++			cec_phys_addr_invalidate(adv7511->cec_adap);
+ 		drm_kms_helper_hotplug_event(adv7511->connector.dev);
+ 	}
+ }
+@@ -465,6 +475,10 @@ static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd)
+ 			wake_up_all(&adv7511->wq);
+ 	}
+ 
++#ifdef CONFIG_DRM_I2C_ADV7511_CEC
++	adv7511_cec_irq_process(adv7511, irq1);
++#endif
++
+ 	return 0;
+ }
+ 
+@@ -607,6 +621,8 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
+ 
+ 	kfree(edid);
+ 
++	cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
++
+ 	return count;
+ }
+ 
+@@ -931,6 +947,65 @@ static void adv7511_uninit_regulators(struct adv7511 *adv)
+ 	regulator_bulk_disable(adv->num_supplies, adv->supplies);
+ }
+ 
++static bool adv7511_cec_register_volatile(struct device *dev, unsigned int reg)
++{
++	struct i2c_client *i2c = to_i2c_client(dev);
++	struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
++
++	if (adv7511->type == ADV7533)
++		reg -= ADV7533_REG_CEC_OFFSET;
++
++	switch (reg) {
++	case ADV7511_REG_CEC_RX_FRAME_HDR:
++	case ADV7511_REG_CEC_RX_FRAME_DATA0...
++		ADV7511_REG_CEC_RX_FRAME_DATA0 + 14:
++	case ADV7511_REG_CEC_RX_FRAME_LEN:
++	case ADV7511_REG_CEC_RX_BUFFERS:
++	case ADV7511_REG_CEC_TX_LOW_DRV_CNT:
++		return true;
++	}
++
++	return false;
++}
++
++static const struct regmap_config adv7511_cec_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++
++	.max_register = 0xff,
++	.cache_type = REGCACHE_RBTREE,
++	.volatile_reg = adv7511_cec_register_volatile,
++};
++
++static int adv7511_init_cec_regmap(struct adv7511 *adv)
++{
++	int ret;
++
++	adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
++				     adv->i2c_main->addr - 1);
++	if (!adv->i2c_cec)
++		return -ENOMEM;
++	i2c_set_clientdata(adv->i2c_cec, adv);
++
++	adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
++					&adv7511_cec_regmap_config);
++	if (IS_ERR(adv->regmap_cec)) {
++		ret = PTR_ERR(adv->regmap_cec);
++		goto err;
++	}
++
++	if (adv->type == ADV7533) {
++		ret = adv7533_patch_cec_registers(adv);
++		if (ret)
++			goto err;
++	}
++
++	return 0;
++err:
++	i2c_unregister_device(adv->i2c_cec);
++	return ret;
++}
++
+ static int adv7511_parse_dt(struct device_node *np,
+ 			    struct adv7511_link_config *config)
+ {
+@@ -1021,6 +1096,7 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	struct device *dev = &i2c->dev;
+ 	unsigned int main_i2c_addr = i2c->addr << 1;
+ 	unsigned int edid_i2c_addr = main_i2c_addr + 4;
++	unsigned int offset;
+ 	unsigned int val;
+ 	int ret;
+ 
+@@ -1104,11 +1180,9 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 		goto uninit_regulators;
+ 	}
+ 
+-	if (adv7511->type == ADV7533) {
+-		ret = adv7533_init_cec(adv7511);
+-		if (ret)
+-			goto err_i2c_unregister_edid;
+-	}
++	ret = adv7511_init_cec_regmap(adv7511);
++	if (ret)
++		goto err_i2c_unregister_edid;
+ 
+ 	INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
+ 
+@@ -1123,10 +1197,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 			goto err_unregister_cec;
+ 	}
+ 
+-	/* CEC is unused for now */
+-	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
+-		     ADV7511_CEC_CTRL_POWER_DOWN);
+-
+ 	adv7511_power_off(adv7511);
+ 
+ 	i2c_set_clientdata(i2c, adv7511);
+@@ -1141,10 +1211,23 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 
+ 	adv7511_audio_init(dev, adv7511);
+ 
++	offset = adv7511->type == ADV7533 ? ADV7533_REG_CEC_OFFSET : 0;
++
++#ifdef CONFIG_DRM_I2C_ADV7511_CEC
++	ret = adv7511_cec_init(dev, adv7511, offset);
++	if (ret)
++		goto err_unregister_cec;
++#else
++	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
++		     ADV7511_CEC_CTRL_POWER_DOWN);
++#endif
++
+ 	return 0;
+ 
+ err_unregister_cec:
+-	adv7533_uninit_cec(adv7511);
++	i2c_unregister_device(adv7511->i2c_cec);
++	if (adv7511->cec_clk)
++		clk_disable_unprepare(adv7511->cec_clk);
+ err_i2c_unregister_edid:
+ 	i2c_unregister_device(adv7511->i2c_edid);
+ uninit_regulators:
+@@ -1157,10 +1240,11 @@ static int adv7511_remove(struct i2c_client *i2c)
+ {
+ 	struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
+ 
+-	if (adv7511->type == ADV7533) {
++	if (adv7511->type == ADV7533)
+ 		adv7533_detach_dsi(adv7511);
+-		adv7533_uninit_cec(adv7511);
+-	}
++	i2c_unregister_device(adv7511->i2c_cec);
++	if (adv7511->cec_clk)
++		clk_disable_unprepare(adv7511->cec_clk);
+ 
+ 	adv7511_uninit_regulators(adv7511);
+ 
+@@ -1168,6 +1252,8 @@ static int adv7511_remove(struct i2c_client *i2c)
+ 
+ 	adv7511_audio_exit(adv7511);
+ 
++	cec_unregister_adapter(adv7511->cec_adap);
++
+ 	i2c_unregister_device(adv7511->i2c_edid);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c b/drivers/gpu/drm/bridge/adv7511/adv7533.c
+index ac804f81e2f6..185b6d842166 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7533.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
+@@ -32,14 +32,6 @@ static const struct reg_sequence adv7533_cec_fixed_registers[] = {
+ 	{ 0x05, 0xc8 },
+ };
+ 
+-static const struct regmap_config adv7533_cec_regmap_config = {
+-	.reg_bits = 8,
+-	.val_bits = 8,
+-
+-	.max_register = 0xff,
+-	.cache_type = REGCACHE_RBTREE,
+-};
+-
+ static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
+ {
+ 	struct mipi_dsi_device *dsi = adv->dsi;
+@@ -145,37 +137,11 @@ int adv7533_patch_registers(struct adv7511 *adv)
+ 				     ARRAY_SIZE(adv7533_fixed_registers));
+ }
+ 
+-void adv7533_uninit_cec(struct adv7511 *adv)
+-{
+-	i2c_unregister_device(adv->i2c_cec);
+-}
+-
+-int adv7533_init_cec(struct adv7511 *adv)
++int adv7533_patch_cec_registers(struct adv7511 *adv)
+ {
+-	int ret;
+-
+-	adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
+-				     adv->i2c_main->addr - 1);
+-	if (!adv->i2c_cec)
+-		return -ENOMEM;
+-
+-	adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
+-					&adv7533_cec_regmap_config);
+-	if (IS_ERR(adv->regmap_cec)) {
+-		ret = PTR_ERR(adv->regmap_cec);
+-		goto err;
+-	}
+-
+-	ret = regmap_register_patch(adv->regmap_cec,
++	return regmap_register_patch(adv->regmap_cec,
+ 				    adv7533_cec_fixed_registers,
+ 				    ARRAY_SIZE(adv7533_cec_fixed_registers));
+-	if (ret)
+-		goto err;
+-
+-	return 0;
+-err:
+-	adv7533_uninit_cec(adv);
+-	return ret;
+ }
+ 
+ int adv7533_attach_dsi(struct adv7511 *adv)
+-- 
+2.19.0
+
diff --git a/patches/0006-drm-bridge-adv7511-Fix-a-use-after-free.patch b/patches/0006-drm-bridge-adv7511-Fix-a-use-after-free.patch
new file mode 100644
index 00000000000000..905c828886b4fc
--- /dev/null
+++ b/patches/0006-drm-bridge-adv7511-Fix-a-use-after-free.patch
@@ -0,0 +1,38 @@
+From bdc69185e329743c878beb02e060d3ac0a0dc4e7 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 17 Oct 2017 23:43:43 +0300
+Subject: [PATCH 0006/1795] drm/bridge: adv7511: Fix a use after free
+
+We free "edid", then use it again on the next line.
+
+Fixes: 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171017204343.zctliubjkq7imudi@mwanda
+(cherry picked from commit 8b32948690946e89c198e44f8a1252295473f348)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 8da5af390e75..a85d16f20581 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -619,10 +619,10 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
+ 	adv7511_set_config_csc(adv7511, connector, adv7511->rgb,
+ 			       drm_detect_hdmi_monitor(edid));
+ 
+-	kfree(edid);
+-
+ 	cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
+ 
++	kfree(edid);
++
+ 	return count;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0007-drm-bridge-adv7511-33-Fix-adv7511_cec_init-failure-h.patch b/patches/0007-drm-bridge-adv7511-33-Fix-adv7511_cec_init-failure-h.patch
new file mode 100644
index 00000000000000..0fe8024b118abb
--- /dev/null
+++ b/patches/0007-drm-bridge-adv7511-33-Fix-adv7511_cec_init-failure-h.patch
@@ -0,0 +1,171 @@
+From 351510bc84f79b52e86236dc6a48829ede3fd3fe Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hverkuil@xs4all.nl>
+Date: Tue, 21 Nov 2017 09:17:43 +0100
+Subject: [PATCH 0007/1795] drm/bridge: adv7511/33: Fix adv7511_cec_init()
+ failure handling
+
+If the device tree for a board did not specify a cec clock, then
+adv7511_cec_init would return an error, which would cause adv7511_probe()
+to fail and thus there is no HDMI output.
+
+There is no need to have adv7511_probe() fail if the CEC initialization
+fails, so just change adv7511_cec_init() to a void function. In addition,
+adv7511_cec_init() should just return silently if the cec clock isn't
+found and show a message for any other errors.
+
+An otherwise correct cleanup patch from Dan Carpenter turned this broken
+failure handling into a kernel Oops, so bisection points to commit
+7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead of NULL") rather
+than 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support").
+
+Based on earlier patches from Arnd and John.
+
+Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org>
+Cc: Xinliang Liu <xinliang.liu@linaro.org>
+Cc: Dan Carpenter <dan.carpenter@oracle.com>
+Cc: Sean Paul <seanpaul@chromium.org>
+Cc: Archit Taneja <architt@codeaurora.org>
+Cc: John Stultz <john.stultz@linaro.org>
+Link: https://bugs.linaro.org/show_bug.cgi?id=3345
+Link: https://lkft.validation.linaro.org/scheduler/job/48017#L3551
+Fixes: 7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead of NULL")
+Fixes: 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support")
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Tested-by: Hans Verkuil <hans.verkuil@cisco.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Tested-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/9097b2a4-b6b9-5fca-e039-0a17694b1143@xs4all.nl
+(cherry picked from commit 1b6fba458c0a2e8513071330972c4c587b7d28cc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511.h     | 13 ++++++--
+ drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 32 ++++++++++++++------
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 17 +++--------
+ 3 files changed, 37 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+index b4efcbabf7f7..d034b2cb5eee 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+@@ -372,9 +372,18 @@ struct adv7511 {
+ };
+ 
+ #ifdef CONFIG_DRM_I2C_ADV7511_CEC
+-int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
+-		     unsigned int offset);
++int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
+ void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
++#else
++static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
++{
++	unsigned int offset = adv7511->type == ADV7533 ?
++						ADV7533_REG_CEC_OFFSET : 0;
++
++	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
++		     ADV7511_CEC_CTRL_POWER_DOWN);
++	return 0;
++}
+ #endif
+ 
+ #ifdef CONFIG_DRM_I2C_ADV7533
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+index b33d730e4d73..a20a45c0b353 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+@@ -300,18 +300,21 @@ static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
+ 	return 0;
+ }
+ 
+-int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
+-		     unsigned int offset)
++int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
+ {
++	unsigned int offset = adv7511->type == ADV7533 ?
++						ADV7533_REG_CEC_OFFSET : 0;
+ 	int ret = adv7511_cec_parse_dt(dev, adv7511);
+ 
+ 	if (ret)
+-		return ret;
++		goto err_cec_parse_dt;
+ 
+ 	adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
+ 		adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
+-	if (IS_ERR(adv7511->cec_adap))
+-		return PTR_ERR(adv7511->cec_adap);
++	if (IS_ERR(adv7511->cec_adap)) {
++		ret = PTR_ERR(adv7511->cec_adap);
++		goto err_cec_alloc;
++	}
+ 
+ 	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
+ 	/* cec soft reset */
+@@ -329,9 +332,18 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
+ 		     ((adv7511->cec_clk_freq / 750000) - 1) << 2);
+ 
+ 	ret = cec_register_adapter(adv7511->cec_adap, dev);
+-	if (ret) {
+-		cec_delete_adapter(adv7511->cec_adap);
+-		adv7511->cec_adap = NULL;
+-	}
+-	return ret;
++	if (ret)
++		goto err_cec_register;
++	return 0;
++
++err_cec_register:
++	cec_delete_adapter(adv7511->cec_adap);
++	adv7511->cec_adap = NULL;
++err_cec_alloc:
++	dev_info(dev, "Initializing CEC failed with error %d, disabling CEC\n",
++		 ret);
++err_cec_parse_dt:
++	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
++		     ADV7511_CEC_CTRL_POWER_DOWN);
++	return ret == -EPROBE_DEFER ? ret : 0;
+ }
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index a85d16f20581..95066350a2b0 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -1096,7 +1096,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	struct device *dev = &i2c->dev;
+ 	unsigned int main_i2c_addr = i2c->addr << 1;
+ 	unsigned int edid_i2c_addr = main_i2c_addr + 4;
+-	unsigned int offset;
+ 	unsigned int val;
+ 	int ret;
+ 
+@@ -1204,24 +1203,16 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	if (adv7511->type == ADV7511)
+ 		adv7511_set_link_config(adv7511, &link_config);
+ 
++	ret = adv7511_cec_init(dev, adv7511);
++	if (ret)
++		goto err_unregister_cec;
++
+ 	adv7511->bridge.funcs = &adv7511_bridge_funcs;
+ 	adv7511->bridge.of_node = dev->of_node;
+ 
+ 	drm_bridge_add(&adv7511->bridge);
+ 
+ 	adv7511_audio_init(dev, adv7511);
+-
+-	offset = adv7511->type == ADV7533 ? ADV7533_REG_CEC_OFFSET : 0;
+-
+-#ifdef CONFIG_DRM_I2C_ADV7511_CEC
+-	ret = adv7511_cec_init(dev, adv7511, offset);
+-	if (ret)
+-		goto err_unregister_cec;
+-#else
+-	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
+-		     ADV7511_CEC_CTRL_POWER_DOWN);
+-#endif
+-
+ 	return 0;
+ 
+ err_unregister_cec:
+-- 
+2.19.0
+
diff --git a/patches/0008-arm_arch_timer-Expose-event-stream-status.patch b/patches/0008-arm_arch_timer-Expose-event-stream-status.patch
new file mode 100644
index 00000000000000..9610caf32226e2
--- /dev/null
+++ b/patches/0008-arm_arch_timer-Expose-event-stream-status.patch
@@ -0,0 +1,154 @@
+From 419c8ec298950d2cdc08b3677a3368b84289ac33 Mon Sep 17 00:00:00 2001
+From: Julien Thierry <julien.thierry@arm.com>
+Date: Fri, 13 Oct 2017 14:32:55 +0100
+Subject: [PATCH 0008/1795] arm_arch_timer: Expose event stream status
+
+The arch timer configuration for a CPU might get reset after suspending
+said CPU.
+
+In order to reliably use the event stream in the kernel (e.g. for delays),
+we keep track of the state where we can safely consider the event stream as
+properly configured. After writing to cntkctl, we issue an ISB to ensure
+that subsequent delay loops can rely on the event stream being enabled.
+
+Signed-off-by: Julien Thierry <julien.thierry@arm.com>
+Acked-by: Mark Rutland <mark.rutland@arm.com>
+Cc: Marc Zyngier <marc.zyngier@arm.com>
+Cc: Russell King <linux@armlinux.org.uk>
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+(cherry picked from commit ec5c8e429d07737ee94ee1fd2ae5029547484194)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/include/asm/arch_timer.h    |  1 +
+ arch/arm64/include/asm/arch_timer.h  |  1 +
+ drivers/clocksource/arm_arch_timer.c | 25 ++++++++++++++++++++++---
+ include/clocksource/arm_arch_timer.h |  6 ++++++
+ 4 files changed, 30 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
+index 9327e3a101dc..0a8d7bba2cb0 100644
+--- a/arch/arm/include/asm/arch_timer.h
++++ b/arch/arm/include/asm/arch_timer.h
+@@ -107,6 +107,7 @@ static inline u32 arch_timer_get_cntkctl(void)
+ static inline void arch_timer_set_cntkctl(u32 cntkctl)
+ {
+ 	asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
++	isb();
+ }
+ 
+ #endif
+diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
+index a652ce0a5cb2..bdedd8f748d1 100644
+--- a/arch/arm64/include/asm/arch_timer.h
++++ b/arch/arm64/include/asm/arch_timer.h
+@@ -144,6 +144,7 @@ static inline u32 arch_timer_get_cntkctl(void)
+ static inline void arch_timer_set_cntkctl(u32 cntkctl)
+ {
+ 	write_sysreg(cntkctl, cntkctl_el1);
++	isb();
+ }
+ 
+ static inline u64 arch_counter_get_cntpct(void)
+diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
+index 14e2419063e9..a926e62444b0 100644
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -77,6 +77,7 @@ static bool arch_timer_mem_use_virtual;
+ static bool arch_counter_suspend_stop;
+ static bool vdso_default = true;
+ 
++static cpumask_t evtstrm_available = CPU_MASK_NONE;
+ static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
+ 
+ static int __init early_evtstrm_cfg(char *buf)
+@@ -740,6 +741,7 @@ static void arch_timer_evtstrm_enable(int divider)
+ #ifdef CONFIG_COMPAT
+ 	compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
+ #endif
++	cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
+ }
+ 
+ static void arch_timer_configure_evtstream(void)
+@@ -864,6 +866,16 @@ u32 arch_timer_get_rate(void)
+ 	return arch_timer_rate;
+ }
+ 
++bool arch_timer_evtstrm_available(void)
++{
++	/*
++	 * We might get called from a preemptible context. This is fine
++	 * because availability of the event stream should be always the same
++	 * for a preemptible context and context where we might resume a task.
++	 */
++	return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
++}
++
+ static u64 arch_counter_get_cntvct_mem(void)
+ {
+ 	u32 vct_lo, vct_hi, tmp_hi;
+@@ -929,6 +941,8 @@ static int arch_timer_dying_cpu(unsigned int cpu)
+ {
+ 	struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
+ 
++	cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
++
+ 	arch_timer_stop(clk);
+ 	return 0;
+ }
+@@ -938,10 +952,16 @@ static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
+ static int arch_timer_cpu_pm_notify(struct notifier_block *self,
+ 				    unsigned long action, void *hcpu)
+ {
+-	if (action == CPU_PM_ENTER)
++	if (action == CPU_PM_ENTER) {
+ 		__this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
+-	else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
++
++		cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
++	} else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
+ 		arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
++
++		if (elf_hwcap & HWCAP_EVTSTRM)
++			cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
++	}
+ 	return NOTIFY_OK;
+ }
+ 
+@@ -1017,7 +1037,6 @@ static int __init arch_timer_register(void)
+ 	if (err)
+ 		goto out_unreg_notify;
+ 
+-
+ 	/* Register and immediately configure the timer on the boot CPU */
+ 	err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
+ 				"clockevents/arm/arch_timer:starting",
+diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
+index cc805b72994a..4e28283e2ec6 100644
+--- a/include/clocksource/arm_arch_timer.h
++++ b/include/clocksource/arm_arch_timer.h
+@@ -93,6 +93,7 @@ struct arch_timer_mem {
+ extern u32 arch_timer_get_rate(void);
+ extern u64 (*arch_timer_read_counter)(void);
+ extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
++extern bool arch_timer_evtstrm_available(void);
+ 
+ #else
+ 
+@@ -106,6 +107,11 @@ static inline u64 arch_timer_read_counter(void)
+ 	return 0;
+ }
+ 
++static inline bool arch_timer_evtstrm_available(void)
++{
++	return false;
++}
++
+ #endif
+ 
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0009-dt-bindings-display-renesas-dw-hdmi-Drop-bogus-node-.patch b/patches/0009-dt-bindings-display-renesas-dw-hdmi-Drop-bogus-node-.patch
new file mode 100644
index 00000000000000..c43caecd4d1958
--- /dev/null
+++ b/patches/0009-dt-bindings-display-renesas-dw-hdmi-Drop-bogus-node-.patch
@@ -0,0 +1,35 @@
+From fc990cb3f0c7be846f6fb90c6e9997af3c8c8844 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 30 Aug 2017 11:53:01 +0200
+Subject: [PATCH 0009/1795] dt-bindings: display: renesas: dw-hdmi: Drop bogus
+ node name suffix
+
+Node names should not use numerical suffixes if the nodes can be
+distinguished by unit-address.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8ac491a5d0934bf1a77db155d759c682ab790c45)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/display/bridge/renesas,dw-hdmi.txt      | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+index b1a8929c2536..3a72a103a18a 100644
+--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
++++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+@@ -37,7 +37,7 @@ Optional properties:
+ 
+ Example:
+ 
+-	hdmi0: hdmi0@fead0000 {
++	hdmi0: hdmi@fead0000 {
+ 		compatible = "renesas,r8a7795-dw-hdmi";
+ 		reg = <0 0xfead0000 0 0x10000>;
+ 		interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0010-drm-bridge-synopsys-dw-hdmi-Enable-cec-clock.patch b/patches/0010-drm-bridge-synopsys-dw-hdmi-Enable-cec-clock.patch
new file mode 100644
index 00000000000000..dd01849b334969
--- /dev/null
+++ b/patches/0010-drm-bridge-synopsys-dw-hdmi-Enable-cec-clock.patch
@@ -0,0 +1,93 @@
+From 46d5f742d13f01c4437253587a916c3954b5de64 Mon Sep 17 00:00:00 2001
+From: Pierre-Hugues Husson <phh@phh.me>
+Date: Sat, 25 Nov 2017 21:18:44 +0100
+Subject: [PATCH 0010/1795] drm/bridge: synopsys/dw-hdmi: Enable cec clock
+
+Support the "cec" optional clock. The documentation already mentions "cec"
+optional clock and it is used by several boards, but currently the driver
+doesn't enable it, thus preventing cec from working on those boards.
+
+And even worse: a /dev/cecX device will appear for those boards, but it
+won't be functioning without configuring this clock.
+
+Changes:
+v4:
+- Change commit message to stress the importance of this patch
+
+v3:
+- Drop useless braces
+
+v2:
+- Separate ENOENT errors from others
+- Propagate other errors (especially -EPROBE_DEFER)
+
+Signed-off-by: Pierre-Hugues Husson <phh@phh.me>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171125201844.11353-1-phh@phh.me
+(cherry picked from commit ebe32c3e282a62974b190b9d514864fc0d56716e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 25 +++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 4db31b89507c..994f16727458 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -138,6 +138,7 @@ struct dw_hdmi {
+ 	struct device *dev;
+ 	struct clk *isfr_clk;
+ 	struct clk *iahb_clk;
++	struct clk *cec_clk;
+ 	struct dw_hdmi_i2c *i2c;
+ 
+ 	struct hdmi_data_info hdmi_data;
+@@ -2385,6 +2386,26 @@ __dw_hdmi_probe(struct platform_device *pdev,
+ 		goto err_isfr;
+ 	}
+ 
++	hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
++	if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
++		hdmi->cec_clk = NULL;
++	} else if (IS_ERR(hdmi->cec_clk)) {
++		ret = PTR_ERR(hdmi->cec_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
++				ret);
++
++		hdmi->cec_clk = NULL;
++		goto err_iahb;
++	} else {
++		ret = clk_prepare_enable(hdmi->cec_clk);
++		if (ret) {
++			dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
++				ret);
++			goto err_iahb;
++		}
++	}
++
+ 	/* Product and revision IDs */
+ 	hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
+ 		      | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
+@@ -2521,6 +2542,8 @@ __dw_hdmi_probe(struct platform_device *pdev,
+ 		cec_notifier_put(hdmi->cec_notifier);
+ 
+ 	clk_disable_unprepare(hdmi->iahb_clk);
++	if (hdmi->cec_clk)
++		clk_disable_unprepare(hdmi->cec_clk);
+ err_isfr:
+ 	clk_disable_unprepare(hdmi->isfr_clk);
+ err_res:
+@@ -2544,6 +2567,8 @@ static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
+ 
+ 	clk_disable_unprepare(hdmi->iahb_clk);
+ 	clk_disable_unprepare(hdmi->isfr_clk);
++	if (hdmi->cec_clk)
++		clk_disable_unprepare(hdmi->cec_clk);
+ 
+ 	if (hdmi->i2c)
+ 		i2c_del_adapter(&hdmi->i2c->adap);
+-- 
+2.19.0
+
diff --git a/patches/0011-ASoC-fsi-Use-of_device_get_match_data-helper.patch b/patches/0011-ASoC-fsi-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..84d6eebe188b34
--- /dev/null
+++ b/patches/0011-ASoC-fsi-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,42 @@
+From e134bb048352c78db1fdbf498a4ea05992c4ca35 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:28:30 +0200
+Subject: [PATCH 0011/1795] ASoC: fsi: Use of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+Note that when used with DT, there's always a valid match.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b48cc1d9c3a93b239700198f69b1a49b23d95b83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/fsi.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c
+index 6d3c7706d93f..c3aaf4788557 100644
+--- a/sound/soc/sh/fsi.c
++++ b/sound/soc/sh/fsi.c
+@@ -1932,14 +1932,9 @@ static int fsi_probe(struct platform_device *pdev)
+ 
+ 	core = NULL;
+ 	if (np) {
+-		const struct of_device_id *of_id;
+-
+-		of_id = of_match_device(fsi_of_match, &pdev->dev);
+-		if (of_id) {
+-			core = of_id->data;
+-			fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
+-			fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
+-		}
++		core = of_device_get_match_data(&pdev->dev);
++		fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
++		fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
+ 	} else {
+ 		const struct platform_device_id	*id_entry = pdev->id_entry;
+ 		if (id_entry)
+-- 
+2.19.0
+
diff --git a/patches/0012-arm64-defconfig-Enable-Renesas-R8A77995-SoC.patch b/patches/0012-arm64-defconfig-Enable-Renesas-R8A77995-SoC.patch
new file mode 100644
index 00000000000000..58f8d405b44a38
--- /dev/null
+++ b/patches/0012-arm64-defconfig-Enable-Renesas-R8A77995-SoC.patch
@@ -0,0 +1,31 @@
+From 64150c3156048cbf048fff81413039df82cd39ff Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 17 Aug 2017 13:32:11 +0200
+Subject: [PATCH 0012/1795] arm64: defconfig: Enable Renesas R8A77995 SoC
+
+Enable support for the Renesas R-Car D3 SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0ed626d35ea2ec744826b3ebcb1d190a6c670d56)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index b05796578e7a..dd77931df8bb 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y
+ CONFIG_ARCH_RENESAS=y
+ CONFIG_ARCH_R8A7795=y
+ CONFIG_ARCH_R8A7796=y
++CONFIG_ARCH_R8A77995=y
+ CONFIG_ARCH_STRATIX10=y
+ CONFIG_ARCH_TEGRA=y
+ CONFIG_ARCH_SPRD=y
+-- 
+2.19.0
+
diff --git a/patches/0013-ARM-shmobile-Document-R-Car-V3M-SoC-DT-bindings.patch b/patches/0013-ARM-shmobile-Document-R-Car-V3M-SoC-DT-bindings.patch
new file mode 100644
index 00000000000000..ec1310fde8f010
--- /dev/null
+++ b/patches/0013-ARM-shmobile-Document-R-Car-V3M-SoC-DT-bindings.patch
@@ -0,0 +1,31 @@
+From 9524224245997dadbfb3314716507108fa542338 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 25 Aug 2017 14:56:49 +0200
+Subject: [PATCH 0013/1795] ARM: shmobile: Document R-Car V3M SoC DT bindings
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 443c1631172a7a6dc19c1657425354327858a548)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index ae75cb3b1331..a1f06711a4dd 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -39,6 +39,8 @@ SoCs:
+     compatible = "renesas,r8a7795"
+   - R-Car M3-W (R8A77960)
+     compatible = "renesas,r8a7796"
++  - R-Car V3M (R8A77970)
++    compatible = "renesas,r8a77970"
+   - R-Car D3 (R8A77995)
+     compatible = "renesas,r8a77995"
+ 
+-- 
+2.19.0
+
diff --git a/patches/0014-arm64-dts-renesas-r8a7795-es1-Drop-extra-zero-from-u.patch b/patches/0014-arm64-dts-renesas-r8a7795-es1-Drop-extra-zero-from-u.patch
new file mode 100644
index 00000000000000..18e1e3e82fe8d2
--- /dev/null
+++ b/patches/0014-arm64-dts-renesas-r8a7795-es1-Drop-extra-zero-from-u.patch
@@ -0,0 +1,38 @@
+From f5c9f3f261a0b807f9f13a08f5136ee2e4d7d494 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 17 Aug 2017 13:29:14 +0200
+Subject: [PATCH 0014/1795] arm64: dts: renesas: r8a7795-es1: Drop extra zero
+ from usb unit address
+
+With W=1:
+
+    arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/usb@ee0400000 simple-bus unit address format error, expected "ee040000"
+    arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/usb@ee0400000 simple-bus unit address format error, expected "ee040000"
+
+Fixes: 291e0c4994d0813f ("arm64: dts: r8a7795: Add support for R-Car H3 ES2.0")
+Fixes: 171f2ef82284f61b ("arm64: dts: r8a7795: Add USB3.0 host device nodes")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0e0f4d47288a8e56ed2586699b89573afcb1bf72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index aaa5e67a963e..655dd30639c5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -11,7 +11,7 @@
+ #include "r8a7795.dtsi"
+ 
+ &soc {
+-	xhci1: usb@ee0400000 {
++	xhci1: usb@ee040000 {
+ 		compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
+ 		reg = <0 0xee040000 0 0xc00>;
+ 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0015-arm64-dts-renesas-r8a7796-Add-FDP1-instance.patch b/patches/0015-arm64-dts-renesas-r8a7796-Add-FDP1-instance.patch
new file mode 100644
index 00000000000000..8e50aac043b272
--- /dev/null
+++ b/patches/0015-arm64-dts-renesas-r8a7796-Add-FDP1-instance.patch
@@ -0,0 +1,42 @@
+From 39e6b59e4eb8ce49c6045629dfb91231fdd87e34 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 13 Jul 2017 14:21:10 +0300
+Subject: [PATCH 0015/1795] arm64: dts: renesas: r8a7796: Add FDP1 instance
+
+The r8a7796 has a single FDP1 instance.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8ef7512a68f4cd559af5d5f0be3ee2e89f0769ec)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 369092e17e34..16da83458f18 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1659,6 +1659,16 @@
+ 			/* placeholder */
+ 		};
+ 
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			resets = <&cpg 119>;
++			renesas,fcp = <&fcpf0>;
++		};
++
+ 		fcpf0: fcp@fe950000 {
+ 			compatible = "renesas,fcpf";
+ 			reg = <0 0xfe950000 0 0x200>;
+-- 
+2.19.0
+
diff --git a/patches/0016-arm64-dts-renesas-r8a77995-update-PFC-node-name-to-p.patch b/patches/0016-arm64-dts-renesas-r8a77995-update-PFC-node-name-to-p.patch
new file mode 100644
index 00000000000000..267a170d1d8143
--- /dev/null
+++ b/patches/0016-arm64-dts-renesas-r8a77995-update-PFC-node-name-to-p.patch
@@ -0,0 +1,37 @@
+From d0a7e2a95a05befba54ac3c88330feb9ad060ec0 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 29 Aug 2017 16:35:59 +0900
+Subject: [PATCH 0016/1795] arm64: dts: renesas: r8a77995: update PFC node name
+ to pin-controller
+
+This patch changes the name from from e6060000.pfc and pfc@e6060000 to
+e6060000.pin-controller and pin-controller@e6060000 like other Renesas
+SoCs.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5a979972b6cb799944423f00c4e269d826c6d2c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index d0f95b78c022..72c303362b16 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -122,7 +122,7 @@
+ 			reg = <0 0xe6160000 0 0x0200>;
+ 		};
+ 
+-		pfc: pfc@e6060000 {
++		pfc: pin-controller@e6060000 {
+ 			compatible = "renesas,pfc-r8a77995";
+ 			reg = <0 0xe6060000 0 0x508>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0017-arm64-dts-renesas-ulcb-Enable-display-output.patch b/patches/0017-arm64-dts-renesas-ulcb-Enable-display-output.patch
new file mode 100644
index 00000000000000..e13987e2752831
--- /dev/null
+++ b/patches/0017-arm64-dts-renesas-ulcb-Enable-display-output.patch
@@ -0,0 +1,35 @@
+From e0cd57cb4a496f98adf25af47bd33546e7877d14 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 22 Aug 2017 17:23:26 +0300
+Subject: [PATCH 0017/1795] arm64: dts: renesas: ulcb: Enable display output
+
+The DU is already wired up to the HDMI encoder, all we need to do is
+enable it.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7da2ed12da2c81b782ee4c3b4b0b87098048aae8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index e95d99265af9..f630a8340b37 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -156,6 +156,10 @@
+ 	};
+ };
+ 
++&du {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0018-arm64-dts-renesas-r8a7795-Drop-bogus-HDMI-node-names.patch b/patches/0018-arm64-dts-renesas-r8a7795-Drop-bogus-HDMI-node-names.patch
new file mode 100644
index 00000000000000..5cedf5fd31abd2
--- /dev/null
+++ b/patches/0018-arm64-dts-renesas-r8a7795-Drop-bogus-HDMI-node-names.patch
@@ -0,0 +1,44 @@
+From ebceaf848008d7b8529c36b8c0a0e5f7615a4877 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 30 Aug 2017 12:03:17 +0200
+Subject: [PATCH 0018/1795] arm64: dts: renesas: r8a7795: Drop bogus HDMI node
+ names suffixes
+
+Node names should not use numerical suffixes if the nodes can be
+distinguished by unit-address.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6b5ac2f1cb1162679662f3be891978d32b345b6f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 2938195b9571..5d5174d8635d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2014,7 +2014,7 @@
+ 			renesas,fcp = <&fcpf1>;
+ 		};
+ 
+-		hdmi0: hdmi0@fead0000 {
++		hdmi0: hdmi@fead0000 {
+ 			compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ 			reg = <0 0xfead0000 0 0x10000>;
+ 			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+@@ -2039,7 +2039,7 @@
+ 			};
+ 		};
+ 
+-		hdmi1: hdmi1@feae0000 {
++		hdmi1: hdmi@feae0000 {
+ 			compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ 			reg = <0 0xfeae0000 0 0x10000>;
+ 			interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0019-arm64-dts-renesas-r8a77995-Use-r8a7795-sysc-binding-.patch b/patches/0019-arm64-dts-renesas-r8a77995-Use-r8a7795-sysc-binding-.patch
new file mode 100644
index 00000000000000..8fe57877ba6324
--- /dev/null
+++ b/patches/0019-arm64-dts-renesas-r8a77995-Use-r8a7795-sysc-binding-.patch
@@ -0,0 +1,76 @@
+From 6af8fcdbd4b809f00f61ef9742a14e5ab20a81c1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 20 Jul 2017 14:54:36 +0200
+Subject: [PATCH 0019/1795] arm64: dts: renesas: r8a77995: Use r8a7795-sysc
+ binding definitions
+
+Replace the hardcoded power domain indices by R8A77995_PD_* symbols.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9066b042b4502f711c5207662ec0d26be1732aff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 72c303362b16..a5b769b840e9 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -11,6 +11,7 @@
+ 
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/power/r8a77995-sysc.h>
+ 
+ / {
+ 	compatible = "renesas,r8a77995";
+@@ -30,14 +31,14 @@
+ 			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x0>;
+ 			device_type = "cpu";
+-			power-domains = <&sysc 5>;
++			power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
+ 		};
+ 
+ 		L2_CA53: cache-controller-1 {
+ 			compatible = "cache";
+-			power-domains = <&sysc 21>;
++			power-domains = <&sysc R8A77995_PD_CA53_SCU>;
+ 			cache-unified;
+ 			cache-level = <2>;
+ 		};
+@@ -76,7 +77,7 @@
+ 					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 408>;
+ 		};
+ 
+@@ -97,7 +98,7 @@
+ 				     "renesas,rcar-gen3-wdt";
+ 			reg = <0 0xe6020000 0 0x0c>;
+ 			clocks = <&cpg CPG_MOD 402>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 402>;
+ 			status = "disabled";
+ 		};
+@@ -147,7 +148,7 @@
+ 				 <&cpg CPG_CORE 16>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 310>;
+ 			status = "disabled";
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0020-arm64-dts-renesas-r8a77995-Use-r8a7795-cpg-mssr-bind.patch b/patches/0020-arm64-dts-renesas-r8a77995-Use-r8a7795-cpg-mssr-bind.patch
new file mode 100644
index 00000000000000..a3ddc6798e011c
--- /dev/null
+++ b/patches/0020-arm64-dts-renesas-r8a77995-Use-r8a7795-cpg-mssr-bind.patch
@@ -0,0 +1,42 @@
+From cd8bd1d558c5f50392bad847663b83cdaf3b8b86 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 20 Jul 2017 14:54:37 +0200
+Subject: [PATCH 0020/1795] arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr
+ binding definitions
+
+Replace the hardcoded clock indices by R8A77995_CLK_* symbols.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5889ded170cd5b6f5a9449956288d069074b20c4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index a5b769b840e9..84b6bd58eafb 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -9,7 +9,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a77995-sysc.h>
+ 
+@@ -145,7 +145,7 @@
+ 			reg = <0 0xe6e88000 0 64>;
+ 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 310>,
+-				 <&cpg CPG_CORE 16>,
++				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/0021-arm64-dts-renesas-r8a77995-add-GPIO-device-nodes.patch b/patches/0021-arm64-dts-renesas-r8a77995-add-GPIO-device-nodes.patch
new file mode 100644
index 00000000000000..2f23d40017e866
--- /dev/null
+++ b/patches/0021-arm64-dts-renesas-r8a77995-add-GPIO-device-nodes.patch
@@ -0,0 +1,144 @@
+From 2521a068e9e30dc8ad64844dce2c215d4ac1b919 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Sep 2017 19:33:59 +0900
+Subject: [PATCH 0021/1795] arm64: dts: renesas: r8a77995: add GPIO device
+ nodes
+
+This patch adds GPIO device nodes for r8a77995.
+
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 11581f5d52a81fe32fb1bb1c71fb22fb9192ee01)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 112 ++++++++++++++++++++++
+ 1 file changed, 112 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 84b6bd58eafb..d7756256d2a6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -139,6 +139,118 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 9>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
++
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
++
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
++
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 10>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
++
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
++
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 21>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
++
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 14>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 906>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 906>;
++		};
++
+ 		scif2: serial@e6e88000 {
+ 			compatible = "renesas,scif-r8a77995",
+ 				     "renesas,rcar-gen3-scif", "renesas,scif";
+-- 
+2.19.0
+
diff --git a/patches/0022-arm64-dts-renesas-r8a77995-Add-EthernetAVB-device-no.patch b/patches/0022-arm64-dts-renesas-r8a77995-Add-EthernetAVB-device-no.patch
new file mode 100644
index 00000000000000..a2a1c55f4b9846
--- /dev/null
+++ b/patches/0022-arm64-dts-renesas-r8a77995-Add-EthernetAVB-device-no.patch
@@ -0,0 +1,77 @@
+From 1dbcd1eb493a757444f904aac5b6f558b7def69e Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Sep 2017 21:18:38 +0900
+Subject: [PATCH 0022/1795] arm64: dts: renesas: r8a77995: Add EthernetAVB
+ device node
+
+This patch adds EthernetAVB device node for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f9ba0c4cfe6169b7cc9a2f9653c76b05316f0508)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 45 +++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index d7756256d2a6..72d04d7337be 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -251,6 +251,51 @@
+ 			resets = <&cpg 906>;
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77995",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii-txid";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		scif2: serial@e6e88000 {
+ 			compatible = "renesas,scif-r8a77995",
+ 				     "renesas,rcar-gen3-scif", "renesas,scif";
+-- 
+2.19.0
+
diff --git a/patches/0023-arm64-dts-renesas-initial-R8A77970-SoC-device-tree.patch b/patches/0023-arm64-dts-renesas-initial-R8A77970-SoC-device-tree.patch
new file mode 100644
index 00000000000000..059145ccd4d2c0
--- /dev/null
+++ b/patches/0023-arm64-dts-renesas-initial-R8A77970-SoC-device-tree.patch
@@ -0,0 +1,158 @@
+From 54b42f135cf32911d2318dab5e86db00466ec9be Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:20 +0300
+Subject: [PATCH 0023/1795] arm64: dts: renesas: initial R8A77970 SoC device
+ tree
+
+The initial R8A77970 SoC device tree including Cortex-A53 CPU, GIC, timer,
+CPG, RST, and SYSC.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 41f4345a6111056341346742942df3f5d5be535d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 125 ++++++++++++++++++++++
+ 1 file changed, 125 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77970.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+new file mode 100644
+index 000000000000..dec3492cd7dc
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -0,0 +1,125 @@
++/*
++ * Device Tree Source for the r8a77970 SoC
++ *
++ * Copyright (C) 2016-2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/ {
++	compatible = "renesas,r8a77970";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		a53_0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53", "arm,armv8";
++			reg = <0>;
++			clocks = <&cpg CPG_CORE 0>;
++			power-domains = <&sysc 5>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++		};
++
++		L2_CA53: cache-controller {
++			compatible = "cache";
++			power-domains = <&sysc 21>;
++			cache-unified;
++			cache-level = <2>;
++		};
++	};
++
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	extalr_clk: extalr {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1010000 0 0x1000>,
++			      <0 0xf1020000 0 0x20000>,
++			      <0 0xf1040000 0 0x20000>,
++			      <0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
++				      IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
++		};
++
++		timer {
++			compatible = "arm,armv8-timer";
++			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
++						  IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
++						  IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
++						  IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
++						  IRQ_TYPE_LEVEL_LOW)>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77970-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77970-rst";
++			reg = <0 0xe6160000 0 0x200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77970-sysc";
++			reg = <0 0xe6180000 0 0x440>;
++			#power-domain-cells = <1>;
++		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0024-arm64-dts-renesas-r8a77970-add-SYS-DMAC-support.patch b/patches/0024-arm64-dts-renesas-r8a77970-add-SYS-DMAC-support.patch
new file mode 100644
index 00000000000000..7aaf9716a34d1c
--- /dev/null
+++ b/patches/0024-arm64-dts-renesas-r8a77970-add-SYS-DMAC-support.patch
@@ -0,0 +1,82 @@
+From e9b0e4ffed3b9d1d8659be90c75281030a29f4fc Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:21 +0300
+Subject: [PATCH 0024/1795] arm64: dts: renesas: r8a77970: add SYS-DMAC support
+
+Describe SYS-DMAC1/2 in the R8A77970 device tree.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bd746e70d3fce2cb1719fd2c085cd57a872575fe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 48 +++++++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index dec3492cd7dc..a2a438a91b3f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -121,5 +121,53 @@
+ 			compatible = "renesas,prr";
+ 			reg = <0 0xfff00044 0 4>;
+ 		};
++
++		dmac1: dma-controller@e7300000 {
++			compatible = "renesas,dmac-r8a77970",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++		};
++
++		dmac2: dma-controller@e7310000 {
++			compatible = "renesas,dmac-r8a77970",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 217>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 217>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0025-arm64-dts-renesas-r8a77970-add-H-SCIF-support.patch b/patches/0025-arm64-dts-renesas-r8a77970-add-H-SCIF-support.patch
new file mode 100644
index 00000000000000..a297c98f65a5c8
--- /dev/null
+++ b/patches/0025-arm64-dts-renesas-r8a77970-add-H-SCIF-support.patch
@@ -0,0 +1,190 @@
+From d2dea25968cf965cb6e71962e8571cca3c68df5a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:22 +0300
+Subject: [PATCH 0025/1795] arm64: dts: renesas: r8a77970: add [H]SCIF support
+
+Describe [H]SCIF ports in the R8A77970 device tree.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 38dbb6fc972e53110f0bc308057822d73c063903)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 149 ++++++++++++++++++++++
+ 1 file changed, 149 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index a2a438a91b3f..04ec0e459686 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -59,6 +59,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	/* External SCIF clock - to be overridden by boards that provide it */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -169,5 +176,147 @@
+ 			#dma-cells = <1>;
+ 			dma-channels = <8>;
+ 		};
++
++		hscif0: serial@e6540000 {
++			compatible = "renesas,hscif-r8a77970",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6540000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 520>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
++			       <&dmac2 0x31>, <&dmac2 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 520>;
++			status = "disabled";
++		};
++
++		hscif1: serial@e6550000 {
++			compatible = "renesas,hscif-r8a77970",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6550000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 519>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
++			       <&dmac2 0x33>, <&dmac2 0x32>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 519>;
++			status = "disabled";
++		};
++
++		hscif2: serial@e6560000 {
++			compatible = "renesas,hscif-r8a77970",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6560000 0 96>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 518>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
++			       <&dmac2 0x35>, <&dmac2 0x34>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 518>;
++			status = "disabled";
++		};
++
++		hscif3: serial@e66a0000 {
++			compatible = "renesas,hscif-r8a77970",
++				     "renesas,rcar-gen3-hscif", "renesas,hscif";
++			reg = <0 0xe66a0000 0 96>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 517>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
++			       <&dmac2 0x37>, <&dmac2 0x36>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 517>;
++			status = "disabled";
++		};
++
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a77970",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a77970",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
++
++		scif3: serial@e6c50000 {
++			compatible = "renesas,scif-r8a77970",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
++			       <&dmac2 0x57>, <&dmac2 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
++
++		scif4: serial@e6c40000 {
++			compatible = "renesas,scif-r8a77970",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>,
++				 <&cpg CPG_CORE 9>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
++			       <&dmac2 0x59>, <&dmac2 0x58>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0026-arm64-dts-renesas-r8a77970-add-EtherAVB-support.patch b/patches/0026-arm64-dts-renesas-r8a77970-add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..c7ae2f63fee7d9
--- /dev/null
+++ b/patches/0026-arm64-dts-renesas-r8a77970-add-EtherAVB-support.patch
@@ -0,0 +1,78 @@
+From 93338b398d7f5f258678d743f5e08517b4b8ee32 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:23 +0300
+Subject: [PATCH 0026/1795] arm64: dts: renesas: r8a77970: add EtherAVB support
+
+Define the generic R8A77970 part of the EtherAVB device node.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bea2ab136eaacec2d14613a3ab89557298fa9748)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 44 +++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 04ec0e459686..aa9032d34189 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -318,5 +318,49 @@
+ 			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
++
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77970",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii-id";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0027-arm64-dts-draak-Add-serial-console-pins.patch b/patches/0027-arm64-dts-draak-Add-serial-console-pins.patch
new file mode 100644
index 00000000000000..46134bd2747b29
--- /dev/null
+++ b/patches/0027-arm64-dts-draak-Add-serial-console-pins.patch
@@ -0,0 +1,42 @@
+From 36604b1b641c6a33c316ec30324ce63d1e9af646 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 28 Aug 2017 11:26:10 +0200
+Subject: [PATCH 0027/1795] arm64: dts: draak: Add serial console pins
+
+Add pin control for SCIF2.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ea203404fb2f0b3b4cc24917044f7bd72fef12c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index d144370051d5..19c5462d8b67 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -36,7 +36,18 @@
+ 	clock-frequency = <48000000>;
+ };
+ 
++&pfc {
++	scif2_pins: scif2 {
++		groups = "scif2_data";
++		function = "scif2";
++	};
++
++};
++
+ &scif2 {
++	pinctrl-0 = <&scif2_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0028-arm64-defconfig-enable-thermal-driver-for-Renesas-R-.patch b/patches/0028-arm64-defconfig-enable-thermal-driver-for-Renesas-R-.patch
new file mode 100644
index 00000000000000..918f857ee05054
--- /dev/null
+++ b/patches/0028-arm64-defconfig-enable-thermal-driver-for-Renesas-R-.patch
@@ -0,0 +1,32 @@
+From 77fca15b0d05389f17e2e0519790eed9e88bd260 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Sep 2017 20:31:13 +0200
+Subject: [PATCH 0028/1795] arm64: defconfig: enable thermal driver for Renesas
+ R-Car Gen3
+
+We want this driver to detect critical temperatures in time.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 86f0a075111d16e3b48d79b44858e141ea86cad7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index dd77931df8bb..4b2230b45003 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -318,6 +318,7 @@ CONFIG_CPU_THERMAL=y
+ CONFIG_THERMAL_EMULATION=y
+ CONFIG_BRCMSTB_THERMAL=m
+ CONFIG_EXYNOS_THERMAL=y
++CONFIG_RCAR_GEN3_THERMAL=y
+ CONFIG_ROCKCHIP_THERMAL=m
+ CONFIG_WATCHDOG=y
+ CONFIG_S3C2410_WATCHDOG=y
+-- 
+2.19.0
+
diff --git a/patches/0029-arm64-defconfig-enable-the-Marvell-10G-PHY-as-a-modu.patch b/patches/0029-arm64-defconfig-enable-the-Marvell-10G-PHY-as-a-modu.patch
new file mode 100644
index 00000000000000..d1cc3125d654e2
--- /dev/null
+++ b/patches/0029-arm64-defconfig-enable-the-Marvell-10G-PHY-as-a-modu.patch
@@ -0,0 +1,33 @@
+From ae1f0b4e40a662d55ed30ff4acd441d0f5fe7068 Mon Sep 17 00:00:00 2001
+From: Antoine Tenart <antoine.tenart@free-electrons.com>
+Date: Mon, 18 Sep 2017 09:58:06 +0200
+Subject: [PATCH 0029/1795] arm64: defconfig: enable the Marvell 10G PHY as a
+ module
+
+The Marvell 10G PHY is present on mvebu platforms. Enable it as a module
+so that the network works on these platforms.
+
+Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+(cherry picked from commit 6dee349e8c618a0dbb7e7dd0cf31da1a3eadd31a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 4b2230b45003..9024f4979b3c 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -205,6 +205,7 @@ CONFIG_STMMAC_ETH=m
+ CONFIG_MDIO_BUS_MUX_MMIOREG=y
+ CONFIG_AT803X_PHY=m
+ CONFIG_MARVELL_PHY=m
++CONFIG_MARVELL_10G_PHY=m
+ CONFIG_MESON_GXL_PHY=m
+ CONFIG_MICREL_PHY=y
+ CONFIG_REALTEK_PHY=m
+-- 
+2.19.0
+
diff --git a/patches/0030-arm64-defconfig-enable-Marvell-CP110-comphy.patch b/patches/0030-arm64-defconfig-enable-Marvell-CP110-comphy.patch
new file mode 100644
index 00000000000000..174897ad500814
--- /dev/null
+++ b/patches/0030-arm64-defconfig-enable-Marvell-CP110-comphy.patch
@@ -0,0 +1,34 @@
+From 673e0e9f8fb42a249ec7525d20a479135423f338 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Mon, 18 Sep 2017 09:58:07 +0200
+Subject: [PATCH 0030/1795] arm64: defconfig: enable Marvell CP110 comphy
+
+The comphy is an hardware block giving access to common PHYs that can be
+used by various other engines (Network, SATA, ...). This is used on
+Marvell 7k/8k platforms for now. Enable the corresponding driver.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+(cherry picked from commit a18615b7ef8d35c799a055013b9af1ec69cf244d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 9024f4979b3c..6b5f0235fdab 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -539,6 +539,7 @@ CONFIG_PWM_TEGRA=m
+ CONFIG_PHY_RCAR_GEN3_USB2=y
+ CONFIG_PHY_HI6220_USB=y
+ CONFIG_PHY_SUN4I_USB=y
++CONFIG_PHY_MVEBU_CP110_COMPHY=y
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+ CONFIG_PHY_ROCKCHIP_EMMC=y
+ CONFIG_PHY_ROCKCHIP_PCIE=m
+-- 
+2.19.0
+
diff --git a/patches/0031-arm-shmobile-Document-Kingfisher-board-DT-bindings.patch b/patches/0031-arm-shmobile-Document-Kingfisher-board-DT-bindings.patch
new file mode 100644
index 00000000000000..051024cc7ac839
--- /dev/null
+++ b/patches/0031-arm-shmobile-Document-Kingfisher-board-DT-bindings.patch
@@ -0,0 +1,37 @@
+From 3547dff6f0edcb8035ccbb7d2a77af5a5d223ae2 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Sat, 16 Sep 2017 21:48:47 +0300
+Subject: [PATCH 0031/1795] arm: shmobile: Document Kingfisher board DT
+ bindings
+
+Add Kingfisher Device tree bindings Documentation, listing it as a
+supported board.
+Kingfisher is the H3ULCB/M3ULCB extension board.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5418a9004126992aa2bbd07d79e8305659cb0dc9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index a1f06711a4dd..e9bd3091dcf6 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -78,6 +78,8 @@ Boards:
+     compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
+   - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
+     compatible = "iwave,g20m", "renesas,r8a7743"
++  - Kingfisher (SBEV-RCAR-KF-M03)
++    compatible = "shimafuji,kingfisher"
+   - Koelsch (RTP0RC7791SEB00010S)
+     compatible = "renesas,koelsch", "renesas,r8a7791"
+   - Kyoto Microcomputer Co. KZM-A9-Dual
+-- 
+2.19.0
+
diff --git a/patches/0032-arm64-dts-renesas-r8a77995-Add-USB2.0-PHY-device-nod.patch b/patches/0032-arm64-dts-renesas-r8a77995-Add-USB2.0-PHY-device-nod.patch
new file mode 100644
index 00000000000000..65c466d9643003
--- /dev/null
+++ b/patches/0032-arm64-dts-renesas-r8a77995-Add-USB2.0-PHY-device-nod.patch
@@ -0,0 +1,43 @@
+From ab99b5cb29c16ab14ba2a65bebe1c8e4f39c63e7 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 19:30:40 +0900
+Subject: [PATCH 0032/1795] arm64: dts: renesas: r8a77995: Add USB2.0 PHY
+ device node
+
+This patch adds USB2.0 PHY device node for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a0ea7fe8d34cbede9928b44e9a6b1dcd3f0150d1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 72d04d7337be..59ed1303bd93 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -309,5 +309,17 @@
+ 			resets = <&cpg 310>;
+ 			status = "disabled";
+ 		};
++
++		usb2_phy0: usb-phy@ee080200 {
++			compatible = "renesas,usb2-phy-r8a77995",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee080200 0 0x700>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0033-arm64-dts-renesas-r8a77995-add-USB2.0-Host-EHCI-OHCI.patch b/patches/0033-arm64-dts-renesas-r8a77995-add-USB2.0-Host-EHCI-OHCI.patch
new file mode 100644
index 00000000000000..bb81bc37d88710
--- /dev/null
+++ b/patches/0033-arm64-dts-renesas-r8a77995-add-USB2.0-Host-EHCI-OHCI.patch
@@ -0,0 +1,57 @@
+From 3d3c3ed6b4f68150d9cd39af94a16f31d4fe1c34 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 19:30:41 +0900
+Subject: [PATCH 0033/1795] arm64: dts: renesas: r8a77995: add USB2.0 Host
+ (EHCI/OHCI) device node
+
+This patch adds USB2.0 Host (EHCI/OHCI) device node for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 423254a1799bc7ea1f81db0b5e0c7eb1494c13f1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 25 +++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 59ed1303bd93..56e42921e879 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -310,6 +310,31 @@
+ 			status = "disabled";
+ 		};
+ 
++		ehci0: usb@ee080100 {
++			compatible = "generic-ehci";
++			reg = <0 0xee080100 0 0x100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			companion = <&ohci0>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++		};
++
++		ohci0: usb@ee080000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee080000 0 0x100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++		};
++
+ 		usb2_phy0: usb-phy@ee080200 {
+ 			compatible = "renesas,usb2-phy-r8a77995",
+ 				     "renesas,rcar-gen3-usb2-phy";
+-- 
+2.19.0
+
diff --git a/patches/0034-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-PHY.patch b/patches/0034-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-PHY.patch
new file mode 100644
index 00000000000000..05ff012a994717
--- /dev/null
+++ b/patches/0034-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-PHY.patch
@@ -0,0 +1,50 @@
+From ff1519dd02f520869d0782381b9fedf920523e58 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 19:30:42 +0900
+Subject: [PATCH 0034/1795] arm64: dts: renesas: r8a77995: draak: enable USB2.0
+ PHY
+
+This patch enables USB2.0 PHY for R-Car D3 draak board.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 34f058b2731bd8c06237ea5725a557edba687ff4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 19c5462d8b67..454658ac6efc 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -42,6 +42,10 @@
+ 		function = "scif2";
+ 	};
+ 
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
+ };
+ 
+ &scif2 {
+@@ -51,6 +55,13 @@
+ 	status = "okay";
+ };
+ 
++&usb2_phy0 {
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &rwdt {
+ 	timeout-sec = <60>;
+ 	status = "okay";
+-- 
+2.19.0
+
diff --git a/patches/0035-arm64-renesas-document-Eagle-board-bindings.patch b/patches/0035-arm64-renesas-document-Eagle-board-bindings.patch
new file mode 100644
index 00000000000000..0d4c207cab3824
--- /dev/null
+++ b/patches/0035-arm64-renesas-document-Eagle-board-bindings.patch
@@ -0,0 +1,37 @@
+From 11637031d62244c91f1559e3559e67a97c19e3dd Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:24 +0300
+Subject: [PATCH 0035/1795] arm64: renesas: document Eagle board bindings
+
+Document the Eagle device tree bindings, listing it as a supported board.
+
+This allows to use checkpatch.pl to validate .dts files referring to the
+Eagle board.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e22b36bd75ad57fdf1010ce7d6d92df96311947b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index e9bd3091dcf6..4fa984ada912 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -59,6 +59,8 @@ Boards:
+     compatible = "renesas,bockw", "renesas,r8a7778"
+   - Draak (RTP0RC77995SEB0010S)
+     compatible = "renesas,draak", "renesas,r8a77995"
++  - Eagle (RTP0RC77970SEB0010S)
++    compatible = "renesas,eagle", "renesas,r8a77970"
+   - Genmai (RTK772100BC00000BR)
+     compatible = "renesas,genmai", "renesas,r7s72100"
+   - GR-Peach (X28A-M01-E/F)
+-- 
+2.19.0
+
diff --git a/patches/0036-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-Host-.patch b/patches/0036-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-Host-.patch
new file mode 100644
index 00000000000000..c1f2084f9d572c
--- /dev/null
+++ b/patches/0036-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-Host-.patch
@@ -0,0 +1,40 @@
+From e6a36effc238a85c9f64855870613ba4cbde883c Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 19:30:43 +0900
+Subject: [PATCH 0036/1795] arm64: dts: renesas: r8a77995: draak: enable USB2.0
+ Host (EHCI/OHCI)
+
+This patch enables USB2.0 Host (EHCI/OHCI) for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 607c73c38e8492677da02a999eabd669e96f6d88)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 454658ac6efc..7b776cb7e928 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -48,6 +48,14 @@
+ 	};
+ };
+ 
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
+ &scif2 {
+ 	pinctrl-0 = <&scif2_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0037-ARM-shmobile-remove-inconsistent-from-documentation.patch b/patches/0037-ARM-shmobile-remove-inconsistent-from-documentation.patch
new file mode 100644
index 00000000000000..84461adf927875
--- /dev/null
+++ b/patches/0037-ARM-shmobile-remove-inconsistent-from-documentation.patch
@@ -0,0 +1,57 @@
+From dd3d9b496b34df460f7f3fb7efb70aaef18e2973 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 21 Sep 2017 11:44:59 +0200
+Subject: [PATCH 0037/1795] ARM: shmobile: remove inconsistent ; from
+ documentation
+
+Consistently do not suffix compat string documentation with a ';'
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 2e931b06de97d762ef139bffbbe75e1483735734)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 4fa984ada912..020d758fc0c5 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -69,7 +69,7 @@ Boards:
+     compatible = "renesas,gose", "renesas,r8a7793"
+   - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
+     H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
+-    compatible = "renesas,h3ulcb", "renesas,r8a7795";
++    compatible = "renesas,h3ulcb", "renesas,r8a7795"
+   - Henninger
+     compatible = "renesas,henninger", "renesas,r8a7791"
+   - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+@@ -91,7 +91,7 @@ Boards:
+   - Lager (RTP0RC7790SEB00010S)
+     compatible = "renesas,lager", "renesas,r8a7790"
+   - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
+-    compatible = "renesas,m3ulcb", "renesas,r8a7796";
++    compatible = "renesas,m3ulcb", "renesas,r8a7796"
+   - Marzen (R0P7779A00010S)
+     compatible = "renesas,marzen", "renesas,r8a7779"
+   - Porter (M2-LCDP)
+@@ -99,11 +99,11 @@ Boards:
+   - RSKRZA1 (YR0K77210C000BE)
+     compatible = "renesas,rskrza1", "renesas,r7s72100"
+   - Salvator-X (RTP0RC7795SIPB0010S)
+-    compatible = "renesas,salvator-x", "renesas,r8a7795";
++    compatible = "renesas,salvator-x", "renesas,r8a7795"
+   - Salvator-X (RTP0RC7796SIPB0011S)
+-    compatible = "renesas,salvator-x", "renesas,r8a7796";
++    compatible = "renesas,salvator-x", "renesas,r8a7796"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+-    compatible = "renesas,salvator-xs", "renesas,r8a7795";
++    compatible = "renesas,salvator-xs", "renesas,r8a7795"
+   - SILK (RTP0RC7794LCB00011S)
+     compatible = "renesas,silk", "renesas,r8a7794"
+   - SK-RZG1E (YR8A77450S000BE)
+-- 
+2.19.0
+
diff --git a/patches/0038-arm64-dts-renesas-r8a77995-draak-enable-EthernetAVB.patch b/patches/0038-arm64-dts-renesas-r8a77995-draak-enable-EthernetAVB.patch
new file mode 100644
index 00000000000000..b7a45fbf2d6d68
--- /dev/null
+++ b/patches/0038-arm64-dts-renesas-r8a77995-draak-enable-EthernetAVB.patch
@@ -0,0 +1,78 @@
+From e677c9dc0ee3578c5a6e66ac4e63e197be02f031 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Sep 2017 21:18:39 +0900
+Subject: [PATCH 0038/1795] arm64: dts: renesas: r8a77995: draak: enable
+ EthernetAVB
+
+This patch enables EthernetAVB for R-Car D3 draak board.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4503b50eac08f472e8690ec61f4d144e62cbdc55)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77995-draak.dts | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 7b776cb7e928..96b7ff5cc321 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -11,6 +11,7 @@
+ 
+ /dts-v1/;
+ #include "r8a77995.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	model = "Renesas Draak board based on r8a77995";
+@@ -18,6 +19,7 @@
+ 
+ 	aliases {
+ 		serial0 = &scif2;
++		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+@@ -37,6 +39,14 @@
+ };
+ 
+ &pfc {
++	avb0_pins: avb {
++		mux {
++			groups = "avb0_link", "avb0_phy_int", "avb0_mdc",
++				 "avb0_mii";
++			function = "avb0";
++		};
++	};
++
+ 	scif2_pins: scif2 {
+ 		groups = "scif2_data";
+ 		function = "scif2";
+@@ -56,6 +66,21 @@
+ 	status = "okay";
+ };
+ 
++&avb {
++	pinctrl-0 = <&avb0_pins>;
++	pinctrl-names = "default";
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++		interrupt-parent = <&gpio5>;
++		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
++	};
++};
++
+ &scif2 {
+ 	pinctrl-0 = <&scif2_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0039-arm64-dts-renesas-r8a7795-add-USB3.0-peripheral-devi.patch b/patches/0039-arm64-dts-renesas-r8a7795-add-USB3.0-peripheral-devi.patch
new file mode 100644
index 00000000000000..e9c5bf4a8a8c29
--- /dev/null
+++ b/patches/0039-arm64-dts-renesas-r8a7795-add-USB3.0-peripheral-devi.patch
@@ -0,0 +1,43 @@
+From 27cb3d576b51704b1b19fe272afac48e326957f1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 21 Sep 2017 14:31:25 +0900
+Subject: [PATCH 0039/1795] arm64: dts: renesas: r8a7795: add USB3.0 peripheral
+ device node
+
+This patch adds USB3.0 peripheral channel 0 device node for r8a7795.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3bdba1b26771496ad8db8cd948ce144fc1ce1ca2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 5d5174d8635d..d5cfd1a1c539 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1471,6 +1471,17 @@
+ 			status = "disabled";
+ 		};
+ 
++		usb3_peri0: usb@ee020000 {
++			compatible = "renesas,r8a7795-usb3-peri",
++				     "renesas,rcar-gen3-usb3-peri";
++			reg = <0 0xee020000 0 0x400>;
++			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
+ 		usb_dmac0: dma-controller@e65a0000 {
+ 			compatible = "renesas,r8a7795-usb-dmac",
+ 				     "renesas,usb-dmac";
+-- 
+2.19.0
+
diff --git a/patches/0040-arm64-dts-renesas-r8a7796-add-USB3.0-peripheral-devi.patch b/patches/0040-arm64-dts-renesas-r8a7796-add-USB3.0-peripheral-devi.patch
new file mode 100644
index 00000000000000..773f678882de3c
--- /dev/null
+++ b/patches/0040-arm64-dts-renesas-r8a7796-add-USB3.0-peripheral-devi.patch
@@ -0,0 +1,43 @@
+From 0b8fbf5b5064146d87a6bfaee4cc3926ff3b530a Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 21 Sep 2017 14:31:26 +0900
+Subject: [PATCH 0040/1795] arm64: dts: renesas: r8a7796: add USB3.0 peripheral
+ device node
+
+This patch adds USB3.0 peripheral channel 0 device node for r8a7796.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2affee619d48d101831e83e74cadeb7c5200d9cb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 16da83458f18..57ac5ca6ed98 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1279,6 +1279,17 @@
+ 			status = "disabled";
+ 		};
+ 
++		usb3_peri0: usb@ee020000 {
++			compatible = "renesas,r8a7796-usb3-peri",
++				     "renesas,rcar-gen3-usb3-peri";
++			reg = <0 0xee020000 0 0x400>;
++			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
+ 		ohci0: usb@ee080000 {
+ 			compatible = "generic-ohci";
+ 			reg = <0 0xee080000 0 0x100>;
+-- 
+2.19.0
+
diff --git a/patches/0041-arm64-defconfig-enable-R8A77970-SoC.patch b/patches/0041-arm64-defconfig-enable-R8A77970-SoC.patch
new file mode 100644
index 00000000000000..47a28eec97d33d
--- /dev/null
+++ b/patches/0041-arm64-defconfig-enable-R8A77970-SoC.patch
@@ -0,0 +1,33 @@
+From 3b4778c8bff033b366996035c92ecb86caa53782 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 23 Sep 2017 00:36:25 +0300
+Subject: [PATCH 0041/1795] arm64: defconfig: enable R8A77970 SoC
+
+Enable the Renesas R-Car V3M (R8A77970) SoC in the ARM64 defconfig.
+
+Suggested-by: Simon Horman <horms@verge.net.au>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bb58b29899ff9c6d1e97727ec05b500e832ebd7d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 6b5f0235fdab..fd65b621180d 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y
+ CONFIG_ARCH_RENESAS=y
+ CONFIG_ARCH_R8A7795=y
+ CONFIG_ARCH_R8A7796=y
++CONFIG_ARCH_R8A77970=y
+ CONFIG_ARCH_R8A77995=y
+ CONFIG_ARCH_STRATIX10=y
+ CONFIG_ARCH_TEGRA=y
+-- 
+2.19.0
+
diff --git a/patches/0042-arm64-defconfig-enable-NAND-on-Armada-7K-8K-SoCs.patch b/patches/0042-arm64-defconfig-enable-NAND-on-Armada-7K-8K-SoCs.patch
new file mode 100644
index 00000000000000..bd1a6cdee11fcc
--- /dev/null
+++ b/patches/0042-arm64-defconfig-enable-NAND-on-Armada-7K-8K-SoCs.patch
@@ -0,0 +1,31 @@
+From a36bad101bc0287fd8effcd564e861fe6ef4853e Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Date: Wed, 27 Sep 2017 17:58:22 +0200
+Subject: [PATCH 0042/1795] arm64: defconfig: enable NAND on Armada 7K/8K SoCs
+
+The PXA3xx NAND driver supports also the NAND controller found on the
+Armada 7K/8K SoCs, so enable it.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+(cherry picked from commit 5fe74e0a72474eb48fa8abe1eb49dedb16b2537b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index fd65b621180d..dfb60597d412 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -158,6 +158,7 @@ CONFIG_MTD_BLOCK=y
+ CONFIG_MTD_M25P80=y
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_DENALI_DT=y
++CONFIG_MTD_NAND_PXA3xx=y
+ CONFIG_MTD_SPI_NOR=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_NBD=m
+-- 
+2.19.0
+
diff --git a/patches/0043-arm64-dts-renesas-salvator-common-drop-avb_phy_int-f.patch b/patches/0043-arm64-dts-renesas-salvator-common-drop-avb_phy_int-f.patch
new file mode 100644
index 00000000000000..00f92523541500
--- /dev/null
+++ b/patches/0043-arm64-dts-renesas-salvator-common-drop-avb_phy_int-f.patch
@@ -0,0 +1,40 @@
+From 7e655071b784cb4c3d88a3d7cfdce22092755dc1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 13:57:11 +0900
+Subject: [PATCH 0043/1795] arm64: dts: renesas: salvator-common: drop
+ "avb_phy_int" from avb_pins
+
+Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
+and it will be handled by a phy driver as a gpio pin, this patch
+removes the "avb_phy_int" from the avb_pins node.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Fixes: 7d73a4da2681 ("arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins")
+Fixes: 4903987033be ("arm64: dts: r8a7796: salvator-x: Set drive-strength for ravb pins")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 86b93a2dff65ab6e22ffd28bb132a2c3970b6e68)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 26a978616071..cfb79cb3dd87 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -380,8 +380,7 @@
+ 
+ 	avb_pins: avb {
+ 		mux {
+-			groups = "avb_link", "avb_phy_int", "avb_mdc",
+-				 "avb_mii";
++			groups = "avb_link", "avb_mdc", "avb_mii";
+ 			function = "avb";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0044-arm64-dts-renesas-ulcb-drop-avb_phy_int-from-avb_pin.patch b/patches/0044-arm64-dts-renesas-ulcb-drop-avb_phy_int-from-avb_pin.patch
new file mode 100644
index 00000000000000..895a2cbaa01854
--- /dev/null
+++ b/patches/0044-arm64-dts-renesas-ulcb-drop-avb_phy_int-from-avb_pin.patch
@@ -0,0 +1,39 @@
+From 2347831c74555a8b5d02aefbc80849b8d5c1b349 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 13:57:12 +0900
+Subject: [PATCH 0044/1795] arm64: dts: renesas: ulcb: drop "avb_phy_int" from
+ avb_pins
+
+Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
+and it will be handled by a phy driver as a gpio pin, this patch
+removes the "avb_phy_int" from the avb_pins node.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Fixes: 133ace3f3804 ("arm64: dts: ulcb: Set drive-strength for ravb pins")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bc04ba36fb1b6c7ebe1df6011da8679e2a5b90bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index f630a8340b37..d32d876156b1 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -253,8 +253,7 @@
+ 
+ 	avb_pins: avb {
+ 		mux {
+-			groups = "avb_link", "avb_phy_int", "avb_mdc",
+-				 "avb_mii";
++			groups = "avb_link", "avb_mdc", "avb_mii";
+ 			function = "avb";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0045-arm64-dts-renesas-r8a77995-draak-drop-avb_phy_int-fr.patch b/patches/0045-arm64-dts-renesas-r8a77995-draak-drop-avb_phy_int-fr.patch
new file mode 100644
index 00000000000000..985458902c3105
--- /dev/null
+++ b/patches/0045-arm64-dts-renesas-r8a77995-draak-drop-avb_phy_int-fr.patch
@@ -0,0 +1,39 @@
+From 9e8b99005aa3d914c8b8d5cbd6bf12b7976ea46f Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 13:57:13 +0900
+Subject: [PATCH 0045/1795] arm64: dts: renesas: r8a77995: draak: drop
+ "avb_phy_int" from avb_pins
+
+Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
+and it will be handled by a phy driver as a gpio pin, this patch
+removes the "avb_phy_int" from the avb_pins node.
+
+Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Fixes: 4503b50eac08 ("arm64: dts: renesas: r8a77995: draak: enable EthernetAVB")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 12bb361979b523bbae00542c17cda8f3f0048860)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 96b7ff5cc321..fac58be83383 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -41,8 +41,7 @@
+ &pfc {
+ 	avb0_pins: avb {
+ 		mux {
+-			groups = "avb0_link", "avb0_phy_int", "avb0_mdc",
+-				 "avb0_mii";
++			groups = "avb0_link", "avb0_mdc", "avb0_mii";
+ 			function = "avb0";
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0046-arm64-dts-renesas-initial-Eagle-board-device-tree.patch b/patches/0046-arm64-dts-renesas-initial-Eagle-board-device-tree.patch
new file mode 100644
index 00000000000000..5858b5323f57b6
--- /dev/null
+++ b/patches/0046-arm64-dts-renesas-initial-Eagle-board-device-tree.patch
@@ -0,0 +1,91 @@
+From 9be74f7b4509ece6faf3a22cfc36f529a997dfef Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:37:26 +0300
+Subject: [PATCH 0046/1795] arm64: dts: renesas: initial Eagle board device
+ tree
+
+Add the initial device  tree for  the R8A77970 SoC based Eagle board.
+The board has 1 debug serial port (SCIF0); include support for it,
+so that the serial console can work.
+
+Based on the original (and large) patch by Vladimir Barinov
+<vladimir.barinov@cogentembedded.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1a48290edf6f78962b1d96008aea954b7b3e5969)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 45 +++++++++++++++++++
+ 2 files changed, 46 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index d417701640bd..3c2332a60f4e 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
++dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+ always		:= $(dtb-y)
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+new file mode 100644
+index 000000000000..a4d1d4f24675
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -0,0 +1,45 @@
++/*
++ * Device Tree Source for the Eagle board
++ *
++ * Copyright (C) 2016-2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a77970.dtsi"
++
++/ {
++	model = "Renesas Eagle board based on r8a77970";
++	compatible = "renesas,eagle", "renesas,r8a77970";
++
++	aliases {
++		serial0 = &scif0;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel";
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x38000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <16666666>;
++};
++
++&extalr_clk {
++	clock-frequency = <32768>;
++};
++
++&scif0 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0047-arm64-dts-renesas-salvator-common-add-pfc-node-for-U.patch b/patches/0047-arm64-dts-renesas-salvator-common-add-pfc-node-for-U.patch
new file mode 100644
index 00000000000000..778df205425225
--- /dev/null
+++ b/patches/0047-arm64-dts-renesas-salvator-common-add-pfc-node-for-U.patch
@@ -0,0 +1,49 @@
+From 4ae8a817fe18a8f592cdb51833917c2447e2d5d1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 17:01:12 +0900
+Subject: [PATCH 0047/1795] arm64: dts: renesas: salvator-common: add pfc node
+ for USB3.0 channel 0
+
+Since a R-Car Gen3 bootloader enables the PFC of USB3.0 channel 0,
+the USB3.0 host controller works without this setting on the kernel.
+But, this setting should have salvator-common.dtsi. So, this patch
+adds the pfc node for USB3.0 channel 0.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 73de4b8847892fa7d6fffd14139c5083a3fd1580)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index cfb79cb3dd87..3525b6dfff68 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -494,6 +494,11 @@
+ 			bias-pull-down;
+ 		};
+ 	};
++
++	usb30_pins: usb30 {
++		groups = "usb30";
++		function = "usb30";
++	};
+ };
+ 
+ &pwm1 {
+@@ -637,5 +642,8 @@
+ };
+ 
+ &xhci0 {
++	pinctrl-0 = <&usb30_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0048-arm64-dts-renesas-r8a77995-add-PWM-device-nodes.patch b/patches/0048-arm64-dts-renesas-r8a77995-add-PWM-device-nodes.patch
new file mode 100644
index 00000000000000..4a00fde6928a2b
--- /dev/null
+++ b/patches/0048-arm64-dts-renesas-r8a77995-add-PWM-device-nodes.patch
@@ -0,0 +1,71 @@
+From 8a7b33ea06a085b1f6452048e8a43db6675f1b22 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 4 Oct 2017 19:27:30 +0900
+Subject: [PATCH 0048/1795] arm64: dts: renesas: r8a77995: add PWM device nodes
+
+This patch adds PWM device nodes for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d40a434746bf2d6dbcc01bb1a14575c11e933cc3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 40 +++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 56e42921e879..bcc4d132f827 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -310,6 +310,46 @@
+ 			status = "disabled";
+ 		};
+ 
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 0x8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 0x8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 0x8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 0x8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			status = "disabled";
++		};
++
+ 		ehci0: usb@ee080100 {
+ 			compatible = "generic-ehci";
+ 			reg = <0 0xee080100 0 0x100>;
+-- 
+2.19.0
+
diff --git a/patches/0049-arm64-dts-renesas-r8a77995-draak-enable-PWM-channel-.patch b/patches/0049-arm64-dts-renesas-r8a77995-draak-enable-PWM-channel-.patch
new file mode 100644
index 00000000000000..68912251c21929
--- /dev/null
+++ b/patches/0049-arm64-dts-renesas-r8a77995-draak-enable-PWM-channel-.patch
@@ -0,0 +1,64 @@
+From 79b05be8e0203fbee6fcfc17f5b7e7032417697f Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 4 Oct 2017 19:27:31 +0900
+Subject: [PATCH 0049/1795] arm64: dts: renesas: r8a77995: draak: enable PWM
+ channel 0 and 1
+
+This patch enables PWM channel 0 and 1 on the draak. Each channel
+connects to LTC2644 for brightness control.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b35334447513c14a4dd55a67c269a743d4a4824b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77995-draak.dts | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index fac58be83383..09de73b11db8 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -46,6 +46,16 @@
+ 		};
+ 	};
+ 
++	pwm0_pins: pwm0 {
++		groups = "pwm0_c";
++		function = "pwm0";
++	};
++
++	pwm1_pins: pwm1 {
++		groups = "pwm1_c";
++		function = "pwm1";
++	};
++
+ 	scif2_pins: scif2 {
+ 		groups = "scif2_data";
+ 		function = "scif2";
+@@ -94,6 +104,20 @@
+ 	status = "okay";
+ };
+ 
++&pwm0 {
++	pinctrl-0 = <&pwm0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&pwm1 {
++	pinctrl-0 = <&pwm1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &rwdt {
+ 	timeout-sec = <60>;
+ 	status = "okay";
+-- 
+2.19.0
+
diff --git a/patches/0050-arm64-dts-ulcb-kf-initial-device-tree.patch b/patches/0050-arm64-dts-ulcb-kf-initial-device-tree.patch
new file mode 100644
index 00000000000000..e6188e0d39bd80
--- /dev/null
+++ b/patches/0050-arm64-dts-ulcb-kf-initial-device-tree.patch
@@ -0,0 +1,62 @@
+From 4c77fb2d761509cc8110fac944d26fb324a021a3 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 6 Oct 2017 20:55:56 +0300
+Subject: [PATCH 0050/1795] arm64: dts: ulcb-kf: initial device tree
+
+Add the initial common dtsi file for Kingfisher infotainment board (R-Car
+Starter Kit extension)
+
+This commit supports the following peripherals:
+- HSCIF0
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 52cb66073d4358644f6adb83221e4432decb28bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 31 ++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+new file mode 100644
+index 000000000000..849f8b102c67
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -0,0 +1,31 @@
++/*
++ * Device Tree Source for the Kingfisher (ULCB extension) board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/ {
++	aliases {
++		serial1 = &hscif0;
++	};
++};
++
++&hscif0 {
++	pinctrl-0 = <&hscif0_pins>;
++	pinctrl-names = "default";
++	uart-has-rtscts;
++
++	status = "okay";
++};
++
++&pfc {
++	hscif0_pins: hscif0 {
++		groups = "hscif0_data", "hscif0_ctrl";
++		function = "hscif0";
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0051-arm64-dts-m3ulcb-kf-initial-device-tree.patch b/patches/0051-arm64-dts-m3ulcb-kf-initial-device-tree.patch
new file mode 100644
index 00000000000000..8f925626978722
--- /dev/null
+++ b/patches/0051-arm64-dts-m3ulcb-kf-initial-device-tree.patch
@@ -0,0 +1,60 @@
+From 22b1e62ab747b002770e7df89a78579c1a66bf4d Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:18:52 +0300
+Subject: [PATCH 0051/1795] arm64: dts: m3ulcb-kf: initial device tree
+
+Add the initial device tree for the M3ULCB with Kingfisher extension
+infotainment board.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eded6a4d16c40879540e1073581e0679e9684bdb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../boot/dts/renesas/r8a7796-m3ulcb-kf.dts    | 19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 3c2332a60f4e..683984a7928e 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
+new file mode 100644
+index 000000000000..de2390f009e7
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
+@@ -0,0 +1,19 @@
++/*
++ * Device Tree Source for the M3ULCB Kingfisher board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7796-m3ulcb.dts"
++#include "ulcb-kf.dtsi"
++
++/ {
++	model = "Renesas M3ULCB Kingfisher board based on r8a7796";
++	compatible = "shimafuji,kingfisher", "renesas,m3ulcb",
++		     "renesas,r8a7796";
++};
+-- 
+2.19.0
+
diff --git a/patches/0052-arm64-dts-h3ulcb-kf-ES1.x-SoC-initial-device-tree.patch b/patches/0052-arm64-dts-h3ulcb-kf-ES1.x-SoC-initial-device-tree.patch
new file mode 100644
index 00000000000000..da252801e35fd1
--- /dev/null
+++ b/patches/0052-arm64-dts-h3ulcb-kf-ES1.x-SoC-initial-device-tree.patch
@@ -0,0 +1,60 @@
+From 76f3281bc1265429371d990675fb8270d2e19496 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:18:58 +0300
+Subject: [PATCH 0052/1795] arm64: dts: h3ulcb-kf: ES1.x SoC initial device
+ tree
+
+Add the initial device tree for the H3ULCB ES1.x SoC with Kingfisher
+extension infotainment board.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d90e97dfe16610542bb83590a81081a47018ba89)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../dts/renesas/r8a7795-es1-h3ulcb-kf.dts     | 19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 683984a7928e..2b48424ddf2d 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -2,6 +2,7 @@
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
+new file mode 100644
+index 000000000000..009cb1cb0dde
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
+@@ -0,0 +1,19 @@
++/*
++ * Device Tree Source for the H3ULCB Kingfisher board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-es1-h3ulcb.dts"
++#include "ulcb-kf.dtsi"
++
++/ {
++	model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES1.x";
++	compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
++		     "renesas,r8a7795";
++};
+-- 
+2.19.0
+
diff --git a/patches/0053-arm64-dts-h3ulcb-kf-ES2.0-SoC-initial-device-tree.patch b/patches/0053-arm64-dts-h3ulcb-kf-ES2.0-SoC-initial-device-tree.patch
new file mode 100644
index 00000000000000..b41c4aad3bc429
--- /dev/null
+++ b/patches/0053-arm64-dts-h3ulcb-kf-ES2.0-SoC-initial-device-tree.patch
@@ -0,0 +1,59 @@
+From 7ea5331f53fb20800857a12282253a9ff84b8d20 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:19:06 +0300
+Subject: [PATCH 0053/1795] arm64: dts: h3ulcb-kf: ES2.0+ SoC initial device
+ tree
+
+Add the initial device tree for the H3ULCB ES2.0+ SoC with Kingfisher
+extension infotainment board.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 20913f7e923ca87921f9ef9ee3dea65de0bc6a18)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../boot/dts/renesas/r8a7795-h3ulcb-kf.dts    | 19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 2b48424ddf2d..842f5884d437 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
+new file mode 100644
+index 000000000000..4403227c0f97
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
+@@ -0,0 +1,19 @@
++/*
++ * Device Tree Source for the H3ULCB Kingfisher board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-h3ulcb.dts"
++#include "ulcb-kf.dtsi"
++
++/ {
++	model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES2.0+";
++	compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
++		     "renesas,r8a7795";
++};
+-- 
+2.19.0
+
diff --git a/patches/0054-arm64-dts-ulcb-kf-enable-SCIF1.patch b/patches/0054-arm64-dts-ulcb-kf-enable-SCIF1.patch
new file mode 100644
index 00000000000000..59a2a6a7412a74
--- /dev/null
+++ b/patches/0054-arm64-dts-ulcb-kf-enable-SCIF1.patch
@@ -0,0 +1,50 @@
+From 13f80e0d6d7b331893c1653df83a385fb1cde5ee Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 6 Oct 2017 05:43:51 +0300
+Subject: [PATCH 0054/1795] arm64: dts: ulcb-kf: enable SCIF1
+
+This supports SCIF1 on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c6c816e22bc89ea4ebfcf04772b4623b573dadc7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 849f8b102c67..885878a4822c 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -12,6 +12,7 @@
+ / {
+ 	aliases {
+ 		serial1 = &hscif0;
++		serial2 = &scif1;
+ 	};
+ };
+ 
+@@ -28,4 +29,17 @@
+ 		groups = "hscif0_data", "hscif0_ctrl";
+ 		function = "hscif0";
+ 	};
++
++	scif1_pins: scif1 {
++		groups = "scif1_data_b", "scif1_ctrl";
++		function = "scif1";
++	};
++};
++
++&scif1 {
++	pinctrl-0 = <&scif1_pins>;
++	pinctrl-names = "default";
++	uart-has-rtscts;
++
++	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0055-arm64-dts-ulcb-kf-enable-CAN0-1.patch b/patches/0055-arm64-dts-ulcb-kf-enable-CAN0-1.patch
new file mode 100644
index 00000000000000..e0b4e050efdf13
--- /dev/null
+++ b/patches/0055-arm64-dts-ulcb-kf-enable-CAN0-1.patch
@@ -0,0 +1,60 @@
+From 7fb9f0541e1da5148cc220198ea6de13c09ce94a Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:19:13 +0300
+Subject: [PATCH 0055/1795] arm64: dts: ulcb-kf: enable CAN0/1
+
+This supports CAN0/1 on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ba915c12fa1f8a8b9c4b875199b489936ddeccac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 885878a4822c..a2cb7363e5ed 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -16,6 +16,18 @@
+ 	};
+ };
+ 
++&can0 {
++	pinctrl-0 = <&can0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&can1 {
++	pinctrl-0 = <&can1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &hscif0 {
+ 	pinctrl-0 = <&hscif0_pins>;
+ 	pinctrl-names = "default";
+@@ -25,6 +37,16 @@
+ };
+ 
+ &pfc {
++	can0_pins: can0 {
++		groups = "can0_data_a";
++		function = "can0";
++	};
++
++	can1_pins: can1 {
++		groups = "can1_data";
++		function = "can1";
++	};
++
+ 	hscif0_pins: hscif0 {
+ 		groups = "hscif0_data", "hscif0_ctrl";
+ 		function = "hscif0";
+-- 
+2.19.0
+
diff --git a/patches/0056-arm64-dts-ulcb-kf-enable-HSUSB.patch b/patches/0056-arm64-dts-ulcb-kf-enable-HSUSB.patch
new file mode 100644
index 00000000000000..793398b0419aaf
--- /dev/null
+++ b/patches/0056-arm64-dts-ulcb-kf-enable-HSUSB.patch
@@ -0,0 +1,35 @@
+From c2cf7cc2de2129d655453cc342b55fdbfcf9f0e3 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 7 Sep 2017 01:36:25 +0300
+Subject: [PATCH 0056/1795] arm64: dts: ulcb-kf: enable HSUSB
+
+This supports HSUSB on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit da9c3629085000730fdbc02fd533efb26fcf6382)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index a2cb7363e5ed..aab51d0b9a50 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -36,6 +36,10 @@
+ 	status = "okay";
+ };
+ 
++&hsusb {
++	status = "okay";
++};
++
+ &pfc {
+ 	can0_pins: can0 {
+ 		groups = "can0_data_a";
+-- 
+2.19.0
+
diff --git a/patches/0057-arm64-dts-ulcb-kf-enable-USB2.0-Host-channel-0.patch b/patches/0057-arm64-dts-ulcb-kf-enable-USB2.0-Host-channel-0.patch
new file mode 100644
index 00000000000000..8a7a2f5e3a6075
--- /dev/null
+++ b/patches/0057-arm64-dts-ulcb-kf-enable-USB2.0-Host-channel-0.patch
@@ -0,0 +1,46 @@
+From 1f29b975465738c65c32e8c3cac1ed04f34e14f0 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 7 Sep 2017 01:36:32 +0300
+Subject: [PATCH 0057/1795] arm64: dts: ulcb-kf: enable USB2.0 Host channel 0
+
+This supports USB2.0 Host channel 0 on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 36bd8e3e34f2cd0b9a074df22327719d8d34b3a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index aab51d0b9a50..83284eace174 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -28,6 +28,10 @@
+ 	status = "okay";
+ };
+ 
++&ehci0 {
++	status = "okay";
++};
++
+ &hscif0 {
+ 	pinctrl-0 = <&hscif0_pins>;
+ 	pinctrl-names = "default";
+@@ -40,6 +44,10 @@
+ 	status = "okay";
+ };
+ 
++&ohci0 {
++	status = "okay";
++};
++
+ &pfc {
+ 	can0_pins: can0 {
+ 		groups = "can0_data_a";
+-- 
+2.19.0
+
diff --git a/patches/0058-arm64-dts-ulcb-kf-enable-PCIE0-1.patch b/patches/0058-arm64-dts-ulcb-kf-enable-PCIE0-1.patch
new file mode 100644
index 00000000000000..2a587f9f3b706d
--- /dev/null
+++ b/patches/0058-arm64-dts-ulcb-kf-enable-PCIE0-1.patch
@@ -0,0 +1,43 @@
+From b2c2d51c4efb8cf132a559b035b5c7f9cb5efaf0 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 6 Oct 2017 05:43:59 +0300
+Subject: [PATCH 0058/1795] arm64: dts: ulcb-kf: enable PCIE0/1
+
+This supports PCIE0/1 on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e0304a365bf07b4a0bb2d56ece5b52f3347d5a01)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 83284eace174..ae970da51fa1 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -48,6 +48,18 @@
+ 	status = "okay";
+ };
+ 
++&pcie_bus_clk {
++	clock-frequency = <100000000>;
++};
++
++&pciec0 {
++	status = "okay";
++};
++
++&pciec1 {
++	status = "okay";
++};
++
+ &pfc {
+ 	can0_pins: can0 {
+ 		groups = "can0_data_a";
+-- 
+2.19.0
+
diff --git a/patches/0059-arm64-dts-ulcb-kf-enable-USB3.0-Host.patch b/patches/0059-arm64-dts-ulcb-kf-enable-USB3.0-Host.patch
new file mode 100644
index 00000000000000..2f65a3dd1a2cd8
--- /dev/null
+++ b/patches/0059-arm64-dts-ulcb-kf-enable-USB3.0-Host.patch
@@ -0,0 +1,32 @@
+From fdf5ddd69b24c33c8854b0405c00e82772f2923c Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 7 Sep 2017 01:36:48 +0300
+Subject: [PATCH 0059/1795] arm64: dts: ulcb-kf: enable USB3.0 Host
+
+This supports USB3.0 Host on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit af75811605f6358dd6c6f34043d3826a31a57e60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index ae970da51fa1..27657fec9696 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -89,3 +89,7 @@
+ 
+ 	status = "okay";
+ };
++
++&xhci0 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0060-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C2.patch b/patches/0060-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C2.patch
new file mode 100644
index 00000000000000..4fdfe3310d864f
--- /dev/null
+++ b/patches/0060-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C2.patch
@@ -0,0 +1,53 @@
+From 7d1149d6815e3339bc16e17263c83966b4ccbba3 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 6 Oct 2017 05:44:05 +0300
+Subject: [PATCH 0060/1795] arm64: dts: ulcb-kf: enable TCA9539 on I2C2
+
+This supports TCA9539 gpio expanders on I2C2 bus on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1189d1d4e3f97775e4e51571aa1dfbc33e0638bb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 27657fec9696..80444aee7bcb 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -44,6 +44,28 @@
+ 	status = "okay";
+ };
+ 
++&i2c2 {
++	gpio_exp_74: gpio@74 {
++		compatible = "ti,tca9539";
++		reg = <0x74>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		interrupt-parent = <&gpio6>;
++		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
++	};
++
++	gpio_exp_75: gpio@75 {
++		compatible = "ti,tca9539";
++		reg = <0x75>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		interrupt-parent = <&gpio6>;
++		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
++	};
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0061-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C4.patch b/patches/0061-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C4.patch
new file mode 100644
index 00000000000000..6966e9aee417fc
--- /dev/null
+++ b/patches/0061-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C4.patch
@@ -0,0 +1,53 @@
+From 88f91e49fe90d699a8e94bde2a6d2cc6c4cd6791 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 6 Oct 2017 05:44:11 +0300
+Subject: [PATCH 0061/1795] arm64: dts: ulcb-kf: enable TCA9539 on I2C4
+
+This supports TCA9539 gpio expanders on I2C4 bus on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0f9c47b2446beb4ea90ba90870cbe72b6419d03b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 80444aee7bcb..a6c2343e23cb 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -66,6 +66,28 @@
+ 	};
+ };
+ 
++&i2c4 {
++	gpio_exp_76: gpio@76 {
++		compatible = "ti,tca9539";
++		reg = <0x76>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		interrupt-parent = <&gpio7>;
++		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
++	};
++
++	gpio_exp_77: gpio@77 {
++		compatible = "ti,tca9539";
++		reg = <0x77>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		interrupt-parent = <&gpio5>;
++		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
++	};
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0062-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C2.patch b/patches/0062-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C2.patch
new file mode 100644
index 00000000000000..886ef42625368a
--- /dev/null
+++ b/patches/0062-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C2.patch
@@ -0,0 +1,39 @@
+From 35950f31f2bb725bcb2ada173891d0b2f8c0c835 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:19:34 +0300
+Subject: [PATCH 0062/1795] arm64: dts: ulcb-kf: enable PCA9548 on I2C2
+
+This supports PCA9548 I2C switch on I2C2 bus on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c6f9cbe364322ac168d8299f49cb54c6143f8e07)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index a6c2343e23cb..3dfd3381e8f7 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -64,6 +64,14 @@
+ 		interrupt-parent = <&gpio6>;
+ 		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ 	};
++
++	i2cswitch2: i2c-switch@71 {
++		compatible = "nxp,pca9548";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x71>;
++		reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
++	};
+ };
+ 
+ &i2c4 {
+-- 
+2.19.0
+
diff --git a/patches/0063-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C4.patch b/patches/0063-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C4.patch
new file mode 100644
index 00000000000000..5a002885883f90
--- /dev/null
+++ b/patches/0063-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C4.patch
@@ -0,0 +1,39 @@
+From c72a304e6637dc1552bf8b1ae8ab91beef6b94a4 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 14 Sep 2017 17:19:48 +0300
+Subject: [PATCH 0063/1795] arm64: dts: ulcb-kf: enable PCA9548 on I2C4
+
+This supports PCA9548 I2C switch on I2C4 bus on ULCB Kingfisher board
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6d5fcdd39f413d0dae466c9f18e6ecd2b6b68362)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 3dfd3381e8f7..1923e5b8ee86 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -94,6 +94,14 @@
+ 		interrupt-parent = <&gpio5>;
+ 		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ 	};
++
++	i2cswitch4: i2c-switch@71 {
++		compatible = "nxp,pca9548";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x71>;
++		reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
++	};
+ };
+ 
+ &ohci0 {
+-- 
+2.19.0
+
diff --git a/patches/0064-arm64-dts-ulcb-kf-hog-USB3-hub-control-gpios.patch b/patches/0064-arm64-dts-ulcb-kf-hog-USB3-hub-control-gpios.patch
new file mode 100644
index 00000000000000..c380922ea926e4
--- /dev/null
+++ b/patches/0064-arm64-dts-ulcb-kf-hog-USB3-hub-control-gpios.patch
@@ -0,0 +1,46 @@
+From 943dae87c27462ff29b9a4edb91e2ca6e75e3818 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 7 Sep 2017 01:37:24 +0300
+Subject: [PATCH 0064/1795] arm64: dts: ulcb-kf: hog USB3 hub control gpios
+
+This adds gpio hogs for USB3 hub on ULCB Kingfisher board to power up and
+remove from reset the hub
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4339306acef642af151ae9c7ec4c39d0cae28497)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 1923e5b8ee86..657ad1041965 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -53,6 +53,20 @@
+ 		interrupt-controller;
+ 		interrupt-parent = <&gpio6>;
+ 		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
++
++		hub_pwen {
++			gpio-hog;
++			gpios = <6 GPIO_ACTIVE_HIGH>;
++			output-high;
++			line-name = "HUB pwen";
++		};
++
++		hub_rst {
++			gpio-hog;
++			gpios = <7 GPIO_ACTIVE_HIGH>;
++			output-high;
++			line-name = "HUB rst";
++		};
+ 	};
+ 
+ 	gpio_exp_75: gpio@75 {
+-- 
+2.19.0
+
diff --git a/patches/0065-arm64-dts-r8a7796-Add-INTC-EX-device-node.patch b/patches/0065-arm64-dts-r8a7796-Add-INTC-EX-device-node.patch
new file mode 100644
index 00000000000000..93dee0e51435f9
--- /dev/null
+++ b/patches/0065-arm64-dts-r8a7796-Add-INTC-EX-device-node.patch
@@ -0,0 +1,47 @@
+From 37604f2917f385f273c0d0f5441882f25094220a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 6 Oct 2017 14:05:51 +0200
+Subject: [PATCH 0065/1795] arm64: dts: r8a7796: Add INTC-EX device node
+
+Add a device node for the Interrupt Controller for External Devices
+(INTC-EX) on R-Car M3-W, which serves external IRQ pins IRQ[0-5].
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fdceea3c2ade76d929725fdd6211feb52bdf705a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 57ac5ca6ed98..8085fd91811e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -383,6 +383,22 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		intc_ex: interrupt-controller@e61c0000 {
++			compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
++
+ 		i2c_dvfs: i2c@e60b0000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/0066-arm64-dts-r8a77970-Add-INTC-EX-device-node.patch b/patches/0066-arm64-dts-r8a77970-Add-INTC-EX-device-node.patch
new file mode 100644
index 00000000000000..acda7568700f03
--- /dev/null
+++ b/patches/0066-arm64-dts-r8a77970-Add-INTC-EX-device-node.patch
@@ -0,0 +1,47 @@
+From 40ddd54ce44b8b5b65b53c5315913d2e762ef6f9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 6 Oct 2017 14:05:52 +0200
+Subject: [PATCH 0066/1795] arm64: dts: r8a77970: Add INTC-EX device node
+
+Add a device node for the Interrupt Controller for External Devices
+(INTC-EX) on R-Car V3M, which serves external IRQ pins IRQ[0-5].
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c6a7fd98966015df742fe15d5a01827262f4fc41)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index aa9032d34189..97e6981938e7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -124,6 +124,22 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		intc_ex: interrupt-controller@e61c0000 {
++			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 407>;
++		};
++
+ 		prr: chipid@fff00044 {
+ 			compatible = "renesas,prr";
+ 			reg = <0 0xfff00044 0 4>;
+-- 
+2.19.0
+
diff --git a/patches/0067-arm64-dts-r8a77995-Add-INTC-EX-device-node.patch b/patches/0067-arm64-dts-r8a77995-Add-INTC-EX-device-node.patch
new file mode 100644
index 00000000000000..c59eba4fa50a76
--- /dev/null
+++ b/patches/0067-arm64-dts-r8a77995-Add-INTC-EX-device-node.patch
@@ -0,0 +1,47 @@
+From ea07acb66de85979af5119f3f6dd407ec3f319ad Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 6 Oct 2017 14:05:53 +0200
+Subject: [PATCH 0067/1795] arm64: dts: r8a77995: Add INTC-EX device node
+
+Add a device node for the Interrupt Controller for External Devices
+(INTC-EX) on R-Car D3, which serves external IRQ pins IRQ[0-5].
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eb5a5078358771ae24b82acd772dfd5ae52fcd34)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index bcc4d132f827..788e3afae6e3 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -139,6 +139,22 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		intc_ex: interrupt-controller@e61c0000 {
++			compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a77995",
+ 				     "renesas,rcar-gen3-gpio",
+-- 
+2.19.0
+
diff --git a/patches/0068-arm64-dts-renesas-eagle-add-EtherAVB-support.patch b/patches/0068-arm64-dts-renesas-eagle-add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..03e6de20379612
--- /dev/null
+++ b/patches/0068-arm64-dts-renesas-eagle-add-EtherAVB-support.patch
@@ -0,0 +1,56 @@
+From 40068b443ee16910608564ddc1d7c2b493caafd0 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 15 Sep 2017 22:43:26 +0300
+Subject: [PATCH 0068/1795] arm64: dts: renesas: eagle: add EtherAVB support
+
+Define the Eagle board  dependent part of the EtherAVB device node.
+Enable DHCP  and NFS root for the kernel booting.
+
+Based  on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 38525608952ae5793a58c1ef4e447f45593d2ee1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index a4d1d4f24675..a711e77cc6a5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -18,10 +18,11 @@
+ 
+ 	aliases {
+ 		serial0 = &scif0;
++		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+-		bootargs = "ignore_loglevel";
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
+@@ -43,3 +44,14 @@
+ &scif0 {
+ 	status = "okay";
+ };
++
++&avb {
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0069-arm64-defconfig-Enable-hisilicon-hibmc-drm-driver.patch b/patches/0069-arm64-defconfig-Enable-hisilicon-hibmc-drm-driver.patch
new file mode 100644
index 00000000000000..0120f1a22612b7
--- /dev/null
+++ b/patches/0069-arm64-defconfig-Enable-hisilicon-hibmc-drm-driver.patch
@@ -0,0 +1,31 @@
+From 8d3e5b30329ced149851334092e404dac96db21b Mon Sep 17 00:00:00 2001
+From: Kefeng Wang <wangkefeng.wang@huawei.com>
+Date: Tue, 22 Aug 2017 21:20:56 +0800
+Subject: [PATCH 0069/1795] arm64: defconfig: Enable hisilicon hibmc drm driver
+
+Enable DRM_HISI_HIBMC as module for Hisilicon D03/D05 board.
+
+Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+(cherry picked from commit f9a3da591d4bf5ad28eb9ffabc823dee9e4254f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index dfb60597d412..58fbf74e858b 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -393,6 +393,7 @@ CONFIG_DRM_TEGRA=m
+ CONFIG_DRM_PANEL_SIMPLE=m
+ CONFIG_DRM_I2C_ADV7511=m
+ CONFIG_DRM_VC4=m
++CONFIG_DRM_HISI_HIBMC=m
+ CONFIG_DRM_HISI_KIRIN=m
+ CONFIG_DRM_MESON=m
+ CONFIG_FB=y
+-- 
+2.19.0
+
diff --git a/patches/0070-arm64-defconfig-Enable-QCOM_IOMMU.patch b/patches/0070-arm64-defconfig-Enable-QCOM_IOMMU.patch
new file mode 100644
index 00000000000000..8b54889fe0d8fa
--- /dev/null
+++ b/patches/0070-arm64-defconfig-Enable-QCOM_IOMMU.patch
@@ -0,0 +1,34 @@
+From dd02d2abb6eadcf3748481883cb4b9a0727434f5 Mon Sep 17 00:00:00 2001
+From: Nicolas Dechesne <nicolas.dechesne@linaro.org>
+Date: Wed, 11 Oct 2017 17:19:25 +0200
+Subject: [PATCH 0070/1795] arm64: defconfig: Enable QCOM_IOMMU
+
+Enable QCOM IOMMU driver for 'B' family devices, such as APQ8016 found on the
+Dragonboard 410c. With this change, graphics console and GPU are working
+fine (using mesa/freedreno for GPU driver).
+
+Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit de11c4de1fbbe1f48ac2ec9b38f1a4618d53d35f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 58fbf74e858b..a9e710db5098 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -518,6 +518,7 @@ CONFIG_HI6220_MBOX=y
+ CONFIG_ROCKCHIP_IOMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
++CONFIG_QCOM_IOMMU=y
+ CONFIG_RPMSG_QCOM_SMD=y
+ CONFIG_RASPBERRYPI_POWER=y
+ CONFIG_QCOM_SMEM=y
+-- 
+2.19.0
+
diff --git a/patches/0071-arm64-defconfig-enable-RTC-on-Armada-7K-8K-SoCs.patch b/patches/0071-arm64-defconfig-enable-RTC-on-Armada-7K-8K-SoCs.patch
new file mode 100644
index 00000000000000..299145141e701a
--- /dev/null
+++ b/patches/0071-arm64-defconfig-enable-RTC-on-Armada-7K-8K-SoCs.patch
@@ -0,0 +1,31 @@
+From 75db402ebc6638fff402b16d272e2f39dce85ec4 Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Date: Mon, 2 Oct 2017 17:44:16 +0200
+Subject: [PATCH 0071/1795] arm64: defconfig: enable RTC on Armada 7K/8K SoCs
+
+The Armada 38x RTC driver supports also the RTC controller found on the
+Armada 7K/8K SoCs, so enable it.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+(cherry picked from commit f5bdfbe66ae7c64ef3bd64c742e34111eb0e3164)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index a9e710db5098..e6d995696079 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -478,6 +478,7 @@ CONFIG_RTC_DRV_EFI=y
+ CONFIG_RTC_DRV_S3C=y
+ CONFIG_RTC_DRV_PL031=y
+ CONFIG_RTC_DRV_SUN6I=y
++CONFIG_RTC_DRV_ARMADA38X=y
+ CONFIG_RTC_DRV_TEGRA=y
+ CONFIG_RTC_DRV_XGENE=y
+ CONFIG_DMADEVICES=y
+-- 
+2.19.0
+
diff --git a/patches/0072-arm64-renesas-salvator-common-fixup-audio_clkout.patch b/patches/0072-arm64-renesas-salvator-common-fixup-audio_clkout.patch
new file mode 100644
index 00000000000000..233c645df90237
--- /dev/null
+++ b/patches/0072-arm64-renesas-salvator-common-fixup-audio_clkout.patch
@@ -0,0 +1,40 @@
+From a3e92f12336203147c98612248aed2801371afcf Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 13 Oct 2017 05:56:58 +0000
+Subject: [PATCH 0072/1795] arm64: renesas: salvator-common: fixup audio_clkout
+
+"audio_clkout" is dummy clock of <&rcar_sound 0> to avoid clock loop
+which invites probe conflict. Thus <&rcar_sound 0> and "audio_clkout"
+should be same value.
+
+On commit 5e2feac33095 ("arm64: renesas: salvator-common: sound
+clock-frequency needs descending order") exchanged <&rcar_sound 0>,
+but it didn't modify "audio_clkout".
+This patch fixup it.
+
+Fixes: 5e2feac33095 ("arm64: renesas: salvator-common: sound clock-frequency needs descending order")
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 64097f4c158199f520c483af0380cb58b23dff0a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 3525b6dfff68..e297f86cabf9 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -52,7 +52,7 @@
+ 		 */
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+-		clock-frequency = <11289600>;
++		clock-frequency = <12288000>;
+ 	};
+ 
+ 	backlight: backlight {
+-- 
+2.19.0
+
diff --git a/patches/0073-arm64-renesas-ulcb-fixup-audio_clkout.patch b/patches/0073-arm64-renesas-ulcb-fixup-audio_clkout.patch
new file mode 100644
index 00000000000000..33a1b602451400
--- /dev/null
+++ b/patches/0073-arm64-renesas-ulcb-fixup-audio_clkout.patch
@@ -0,0 +1,40 @@
+From 456d1845075570be5129cdeb41dd972ea4a61b4e Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 13 Oct 2017 05:57:18 +0000
+Subject: [PATCH 0073/1795] arm64: renesas: ulcb: fixup audio_clkout
+
+"audio_clkout" is dummy clock of <&rcar_sound 0> to avoid clock loop
+which invites probe conflict. Thus <&rcar_sound 0> and "audio_clkout"
+should be same value.
+
+On commit 2752660a37ae ("arm64: dts: renesas: ulcb: sound
+clock-frequency needs descending order") exchanged <&rcar_sound 0>,
+but it didn't modify "audio_clkout".
+This patch fixup it.
+
+Fixes: 2752660a37ae ("arm64: dts: renesas: ulcb: sound clock-frequency needs descending order")
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 822cecb1bef2bf41663d6c4e7786d9e159f72674)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index d32d876156b1..73439cf48659 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -31,7 +31,7 @@
+ 		 */
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+-		clock-frequency = <11289600>;
++		clock-frequency = <12288000>;
+ 	};
+ 
+ 	hdmi0-out {
+-- 
+2.19.0
+
diff --git a/patches/0074-arm64-dts-r8a7795-Use-R-Car-GPIO-Gen3-fallback-compa.patch b/patches/0074-arm64-dts-r8a7795-Use-R-Car-GPIO-Gen3-fallback-compa.patch
new file mode 100644
index 00000000000000..71dfb9d180739f
--- /dev/null
+++ b/patches/0074-arm64-dts-r8a7795-Use-R-Car-GPIO-Gen3-fallback-compa.patch
@@ -0,0 +1,101 @@
+From 8ec27b3d3d5de5c7bd2bfc900cde930e5f5263f6 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:10 +0200
+Subject: [PATCH 0074/1795] arm64: dts: r8a7795: Use R-Car GPIO Gen3 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen3 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7795 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit d6d7037cb2f8d33cae5384eeaea9b5248fb383ae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index d5cfd1a1c539..15ef292a8d9f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -220,7 +220,7 @@
+ 
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6050000 0 0x50>;
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -235,7 +235,7 @@
+ 
+ 		gpio1: gpio@e6051000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6051000 0 0x50>;
+ 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -250,7 +250,7 @@
+ 
+ 		gpio2: gpio@e6052000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6052000 0 0x50>;
+ 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -265,7 +265,7 @@
+ 
+ 		gpio3: gpio@e6053000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6053000 0 0x50>;
+ 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -280,7 +280,7 @@
+ 
+ 		gpio4: gpio@e6054000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6054000 0 0x50>;
+ 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -295,7 +295,7 @@
+ 
+ 		gpio5: gpio@e6055000 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055000 0 0x50>;
+ 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -310,7 +310,7 @@
+ 
+ 		gpio6: gpio@e6055400 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055400 0 0x50>;
+ 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -325,7 +325,7 @@
+ 
+ 		gpio7: gpio@e6055800 {
+ 			compatible = "renesas,gpio-r8a7795",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055800 0 0x50>;
+ 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0075-arm64-dts-r8a7796-Use-R-Car-GPIO-Gen3-fallback-compa.patch b/patches/0075-arm64-dts-r8a7796-Use-R-Car-GPIO-Gen3-fallback-compa.patch
new file mode 100644
index 00000000000000..cf3529c22a182a
--- /dev/null
+++ b/patches/0075-arm64-dts-r8a7796-Use-R-Car-GPIO-Gen3-fallback-compa.patch
@@ -0,0 +1,101 @@
+From 3d568aee4b07a687a153cfb40953b1219efa292c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:11 +0200
+Subject: [PATCH 0075/1795] arm64: dts: r8a7796: Use R-Car GPIO Gen3 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen3 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7796 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c8ee880415894e75b5289618dc2b8108bdd96a23)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 8085fd91811e..f2b2e40c655e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -214,7 +214,7 @@
+ 
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6050000 0 0x50>;
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -229,7 +229,7 @@
+ 
+ 		gpio1: gpio@e6051000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6051000 0 0x50>;
+ 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -244,7 +244,7 @@
+ 
+ 		gpio2: gpio@e6052000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6052000 0 0x50>;
+ 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -259,7 +259,7 @@
+ 
+ 		gpio3: gpio@e6053000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6053000 0 0x50>;
+ 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -274,7 +274,7 @@
+ 
+ 		gpio4: gpio@e6054000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6054000 0 0x50>;
+ 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -289,7 +289,7 @@
+ 
+ 		gpio5: gpio@e6055000 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055000 0 0x50>;
+ 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -304,7 +304,7 @@
+ 
+ 		gpio6: gpio@e6055400 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055400 0 0x50>;
+ 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -319,7 +319,7 @@
+ 
+ 		gpio7: gpio@e6055800 {
+ 			compatible = "renesas,gpio-r8a7796",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen3-gpio";
+ 			reg = <0 0xe6055800 0 0x50>;
+ 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0076-arm64-defconfig-re-enable-Qualcomm-DB410c-USB.patch b/patches/0076-arm64-defconfig-re-enable-Qualcomm-DB410c-USB.patch
new file mode 100644
index 00000000000000..3894af9b3c7fc4
--- /dev/null
+++ b/patches/0076-arm64-defconfig-re-enable-Qualcomm-DB410c-USB.patch
@@ -0,0 +1,54 @@
+From db879c856e35944f67183628195d1d09376b1a8f Mon Sep 17 00:00:00 2001
+From: Alex Elder <elder@linaro.org>
+Date: Mon, 16 Oct 2017 09:22:57 -0500
+Subject: [PATCH 0076/1795] arm64: defconfig: re-enable Qualcomm DB410c USB
+
+Stephen Boyd reworked some Qualcomm USB code earlier this year.
+The result requires a few different config options to be enabled
+in order for the USB on the DragonBoard 410c to continue working,
+but these were never added to arm64 "defconfig".  As a result, USB
+on that board stopped working during the v4.13-rc1 merge window.
+
+Re-enable this functionality by setting the needed config options
+in the arm64 "defconfig" file.
+
+Signed-off-by: Alex Elder <elder@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit b8eb03a7cf1b767c339771201f9cb974cea1145a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index e6d995696079..2113a685de76 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -431,6 +431,7 @@ CONFIG_USB_DWC2=y
+ CONFIG_USB_CHIPIDEA=y
+ CONFIG_USB_CHIPIDEA_UDC=y
+ CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_CHIPIDEA_ULPI=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_HSIC_USB3503=y
+ CONFIG_NOP_USB_XCEIV=y
+@@ -439,6 +440,7 @@ CONFIG_USB_QCOM_8X16_PHY=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_RENESAS_USBHS_UDC=m
++CONFIG_USB_ULPI_BUS=y
+ CONFIG_MMC=y
+ CONFIG_MMC_BLOCK_MINORS=32
+ CONFIG_MMC_ARMMMCI=y
+@@ -543,6 +545,7 @@ CONFIG_PWM_SAMSUNG=y
+ CONFIG_PWM_TEGRA=m
+ CONFIG_PHY_RCAR_GEN3_USB2=y
+ CONFIG_PHY_HI6220_USB=y
++CONFIG_PHY_QCOM_USB_HS=y
+ CONFIG_PHY_SUN4I_USB=y
+ CONFIG_PHY_MVEBU_CP110_COMPHY=y
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+-- 
+2.19.0
+
diff --git a/patches/0077-arm64-defconfig-Enable-Tegra-PCI-controller.patch b/patches/0077-arm64-defconfig-Enable-Tegra-PCI-controller.patch
new file mode 100644
index 00000000000000..ddf0a49a3a7cb6
--- /dev/null
+++ b/patches/0077-arm64-defconfig-Enable-Tegra-PCI-controller.patch
@@ -0,0 +1,32 @@
+From af04d31bbab2f596065c756385a7cdd95ab625d7 Mon Sep 17 00:00:00 2001
+From: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+Date: Wed, 18 Oct 2017 17:46:20 +0300
+Subject: [PATCH 0077/1795] arm64: defconfig: Enable Tegra PCI controller
+
+The driver has supported the 64-bit Tegra210 for a while now, so enable
+it in the defconfig.
+
+Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+(cherry picked from commit a9e6753c1c92ae7d2c0c99b420c5c7dd5ebfc37d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 2113a685de76..6e8eced66e43 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -74,6 +74,7 @@ CONFIG_PCIE_QCOM=y
+ CONFIG_PCIE_KIRIN=y
+ CONFIG_PCIE_ARMADA_8K=y
+ CONFIG_PCI_AARDVARK=y
++CONFIG_PCI_TEGRA=y
+ CONFIG_PCIE_RCAR=y
+ CONFIG_PCIE_ROCKCHIP=m
+ CONFIG_PCI_HOST_GENERIC=y
+-- 
+2.19.0
+
diff --git a/patches/0078-arm64-Add-ThunderX-drivers-to-defconfig.patch b/patches/0078-arm64-Add-ThunderX-drivers-to-defconfig.patch
new file mode 100644
index 00000000000000..566586e7a107e5
--- /dev/null
+++ b/patches/0078-arm64-Add-ThunderX-drivers-to-defconfig.patch
@@ -0,0 +1,41 @@
+From 99459a8949c2f21b6ea76226cd0733c03cf8e5d0 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Wed, 11 Oct 2017 16:15:41 +0100
+Subject: [PATCH 0078/1795] arm64: Add ThunderX drivers to defconfig
+
+ThunderX needs its PCI host drivers to do anything useful, and
+it's probably helpful to have networking by default too.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 0454c9212d25bcf963810db9e4cb6311d666c0d5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 6e8eced66e43..e5ce0ff06023 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -79,6 +79,8 @@ CONFIG_PCIE_RCAR=y
+ CONFIG_PCIE_ROCKCHIP=m
+ CONFIG_PCI_HOST_GENERIC=y
+ CONFIG_PCI_XGENE=y
++CONFIG_PCI_HOST_THUNDER_PEM=y
++CONFIG_PCI_HOST_THUNDER_ECAM=y
+ CONFIG_ARM64_VA_BITS_48=y
+ CONFIG_SCHED_MC=y
+ CONFIG_NUMA=y
+@@ -192,6 +194,7 @@ CONFIG_VIRTIO_NET=y
+ CONFIG_AMD_XGBE=y
+ CONFIG_NET_XGENE=y
+ CONFIG_MACB=y
++CONFIG_THUNDER_NIC_PF=y
+ CONFIG_HNS_DSAF=y
+ CONFIG_HNS_ENET=y
+ CONFIG_E1000E=y
+-- 
+2.19.0
+
diff --git a/patches/0079-arm64-dts-renesas-salvator-common-add-dr_mode-proper.patch b/patches/0079-arm64-dts-renesas-salvator-common-add-dr_mode-proper.patch
new file mode 100644
index 00000000000000..bd888506ef7dcf
--- /dev/null
+++ b/patches/0079-arm64-dts-renesas-salvator-common-add-dr_mode-proper.patch
@@ -0,0 +1,50 @@
+From 6b0d58d81695bc11e318accdceeee6bb37ac4f8d Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 12 Oct 2017 18:23:30 +0900
+Subject: [PATCH 0079/1795] arm64: dts: renesas: salvator-common: add dr_mode
+ property for USB2.0 channel 0
+
+Since Salvator-X[S] have a USB2.0 dual-role channel (CN9), this patch
+adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB)
+as "otg".
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e9ce35386b215d3f5d0fbab3cc24b69b8d57d7e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index e297f86cabf9..eab44b9bdaa7 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -275,6 +275,7 @@
+ };
+ 
+ &ehci0 {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+@@ -287,6 +288,7 @@
+ };
+ 
+ &hsusb {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+@@ -355,6 +357,7 @@
+ };
+ 
+ &ohci0 {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0080-arm64-defconfig-enable-CONFIG_GPIO_UNIPHIER.patch b/patches/0080-arm64-defconfig-enable-CONFIG_GPIO_UNIPHIER.patch
new file mode 100644
index 00000000000000..02a77c72b820e1
--- /dev/null
+++ b/patches/0080-arm64-defconfig-enable-CONFIG_GPIO_UNIPHIER.patch
@@ -0,0 +1,31 @@
+From f6758393aa7276482f320b49e3d99d6eef5479d1 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Mon, 30 Oct 2017 19:00:52 +0900
+Subject: [PATCH 0080/1795] arm64: defconfig: enable CONFIG_GPIO_UNIPHIER
+
+Enable the GPIO controller driver used for UniPhier SoC family.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit d0e470e0db7ead4e5dc43057b8ede78451d0dd6b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index e5ce0ff06023..cad81b1723d8 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -305,6 +305,7 @@ CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+ CONFIG_GPIO_DWAPB=y
+ CONFIG_GPIO_PL061=y
+ CONFIG_GPIO_RCAR=y
++CONFIG_GPIO_UNIPHIER=y
+ CONFIG_GPIO_XGENE=y
+ CONFIG_GPIO_XGENE_SB=y
+ CONFIG_GPIO_PCA953X=y
+-- 
+2.19.0
+
diff --git a/patches/0081-kbuild-clean-up-.dtb-and-.dtb.S-patterns-from-top-le.patch b/patches/0081-kbuild-clean-up-.dtb-and-.dtb.S-patterns-from-top-le.patch
new file mode 100644
index 00000000000000..591731b8b959a2
--- /dev/null
+++ b/patches/0081-kbuild-clean-up-.dtb-and-.dtb.S-patterns-from-top-le.patch
@@ -0,0 +1,583 @@
+From 08989bcf1c6e94a1b3cf0212839b26a8a34f8099 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 2 Nov 2017 11:51:25 +0900
+Subject: [PATCH 0081/1795] kbuild: clean up *.dtb and *.dtb.S patterns from
+ top-level Makefile
+
+We need to add "clean-files" in Makfiles to clean up DT blobs, but we
+often miss to do so.
+
+Since there are no source files that end with .dtb or .dtb.S, so we
+can clean-up those files from the top-level Makefile.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 74ce1896c6c65b2f8cccbf59162d542988835835)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/kbuild/makefiles.txt               | 1 -
+ Makefile                                         | 2 +-
+ arch/arc/boot/dts/Makefile                       | 1 -
+ arch/arm/boot/dts/Makefile                       | 1 -
+ arch/arm64/boot/dts/actions/Makefile             | 1 -
+ arch/arm64/boot/dts/al/Makefile                  | 1 -
+ arch/arm64/boot/dts/allwinner/Makefile           | 1 -
+ arch/arm64/boot/dts/altera/Makefile              | 1 -
+ arch/arm64/boot/dts/amd/Makefile                 | 1 -
+ arch/arm64/boot/dts/amlogic/Makefile             | 1 -
+ arch/arm64/boot/dts/apm/Makefile                 | 1 -
+ arch/arm64/boot/dts/arm/Makefile                 | 1 -
+ arch/arm64/boot/dts/broadcom/Makefile            | 1 -
+ arch/arm64/boot/dts/broadcom/northstar2/Makefile | 1 -
+ arch/arm64/boot/dts/broadcom/stingray/Makefile   | 1 -
+ arch/arm64/boot/dts/cavium/Makefile              | 1 -
+ arch/arm64/boot/dts/exynos/Makefile              | 1 -
+ arch/arm64/boot/dts/freescale/Makefile           | 1 -
+ arch/arm64/boot/dts/hisilicon/Makefile           | 1 -
+ arch/arm64/boot/dts/lg/Makefile                  | 1 -
+ arch/arm64/boot/dts/marvell/Makefile             | 1 -
+ arch/arm64/boot/dts/mediatek/Makefile            | 1 -
+ arch/arm64/boot/dts/nvidia/Makefile              | 1 -
+ arch/arm64/boot/dts/qcom/Makefile                | 1 -
+ arch/arm64/boot/dts/realtek/Makefile             | 1 -
+ arch/arm64/boot/dts/renesas/Makefile             | 1 -
+ arch/arm64/boot/dts/rockchip/Makefile            | 1 -
+ arch/arm64/boot/dts/socionext/Makefile           | 1 -
+ arch/arm64/boot/dts/sprd/Makefile                | 1 -
+ arch/arm64/boot/dts/xilinx/Makefile              | 1 -
+ arch/arm64/boot/dts/zte/Makefile                 | 1 -
+ arch/c6x/boot/dts/Makefile                       | 2 --
+ arch/cris/boot/dts/Makefile                      | 2 --
+ arch/h8300/boot/dts/Makefile                     | 1 -
+ arch/metag/boot/dts/Makefile                     | 1 -
+ arch/microblaze/boot/Makefile                    | 2 +-
+ arch/mips/boot/dts/Makefile                      | 1 -
+ arch/mips/boot/dts/brcm/Makefile                 | 1 -
+ arch/mips/boot/dts/cavium-octeon/Makefile        | 1 -
+ arch/mips/boot/dts/img/Makefile                  | 1 -
+ arch/mips/boot/dts/ingenic/Makefile              | 1 -
+ arch/mips/boot/dts/lantiq/Makefile               | 1 -
+ arch/mips/boot/dts/mti/Makefile                  | 1 -
+ arch/mips/boot/dts/netlogic/Makefile             | 1 -
+ arch/mips/boot/dts/ni/Makefile                   | 1 -
+ arch/mips/boot/dts/pic32/Makefile                | 1 -
+ arch/mips/boot/dts/qca/Makefile                  | 1 -
+ arch/mips/boot/dts/ralink/Makefile               | 1 -
+ arch/mips/boot/dts/xilfpga/Makefile              | 1 -
+ arch/nios2/boot/Makefile                         | 2 --
+ arch/openrisc/boot/dts/Makefile                  | 2 --
+ arch/powerpc/boot/Makefile                       | 2 +-
+ arch/sh/boot/dts/Makefile                        | 2 --
+ arch/xtensa/boot/dts/Makefile                    | 2 --
+ 54 files changed, 3 insertions(+), 60 deletions(-)
+
+diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
+index f6f80380dff2..71e9feefb63c 100644
+--- a/Documentation/kbuild/makefiles.txt
++++ b/Documentation/kbuild/makefiles.txt
+@@ -1158,7 +1158,6 @@ When kbuild executes, the following steps are followed (roughly):
+ 
+ 	Example:
+ 		targets += $(dtb-y)
+-		clean-files += *.dtb
+ 		DTC_FLAGS ?= -p 1024
+ 
+ --- 6.8 Custom kbuild commands
+diff --git a/Makefile b/Makefile
+index aa458afa7fa2..f5caf45de28b 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1573,7 +1573,7 @@ clean: $(clean-dirs)
+ 	$(call cmd,rmfiles)
+ 	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+ 		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
+-		-o -name '*.ko.*' \
++		-o -name '*.ko.*' -o -name '*.dtb' -o -name '*.dtb.S' \
+ 		-o -name '*.dwo'  \
+ 		-o -name '*.su'  \
+ 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+diff --git a/arch/arc/boot/dts/Makefile b/arch/arc/boot/dts/Makefile
+index 83c9e076ef63..f3c1fe958367 100644
+--- a/arch/arc/boot/dts/Makefile
++++ b/arch/arc/boot/dts/Makefile
+@@ -15,4 +15,3 @@ dtstree		:= $(srctree)/$(src)
+ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+ 
+ always := $(dtb-y)
+-clean-files := *.dtb  *.dtb.S
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index eff87a344566..300f441698fb 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -1075,4 +1075,3 @@ dtstree		:= $(srctree)/$(src)
+ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+ 
+ always		:= $(dtb-y)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile
+index 62922d688ce3..89bb1b534492 100644
+--- a/arch/arm64/boot/dts/actions/Makefile
++++ b/arch/arm64/boot/dts/actions/Makefile
+@@ -2,4 +2,3 @@ dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/al/Makefile b/arch/arm64/boot/dts/al/Makefile
+index 8a6cde4f9b23..8606a57e567f 100644
+--- a/arch/arm64/boot/dts/al/Makefile
++++ b/arch/arm64/boot/dts/al/Makefile
+@@ -2,4 +2,3 @@ dtb-$(CONFIG_ARCH_ALPINE)	+= alpine-v2-evp.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index ff35e184e422..5859798a766d 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -12,4 +12,3 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile
+index d7a641698d77..7511b51d9b4a 100644
+--- a/arch/arm64/boot/dts/altera/Makefile
++++ b/arch/arm64/boot/dts/altera/Makefile
+@@ -2,4 +2,3 @@ dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
+index f9963d63006d..2bd7b0aefce8 100644
+--- a/arch/arm64/boot/dts/amd/Makefile
++++ b/arch/arm64/boot/dts/amd/Makefile
+@@ -5,4 +5,3 @@ dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
+index 543416b8dff5..ce9244937953 100644
+--- a/arch/arm64/boot/dts/amlogic/Makefile
++++ b/arch/arm64/boot/dts/amlogic/Makefile
+@@ -23,4 +23,3 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/apm/Makefile b/arch/arm64/boot/dts/apm/Makefile
+index a10fbdb34229..ab6f2da36265 100644
+--- a/arch/arm64/boot/dts/apm/Makefile
++++ b/arch/arm64/boot/dts/apm/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
+index 470378addca4..e516bf1fe1a1 100644
+--- a/arch/arm64/boot/dts/arm/Makefile
++++ b/arch/arm64/boot/dts/arm/Makefile
+@@ -6,4 +6,3 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
+index 3df2db7f8878..b3e7e7b447ee 100644
+--- a/arch/arm64/boot/dts/broadcom/Makefile
++++ b/arch/arm64/boot/dts/broadcom/Makefile
+@@ -5,4 +5,3 @@ dts-dirs	+= northstar2
+ dts-dirs	+= stingray
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile
+index e01a1485b813..c589b9b55da8 100644
+--- a/arch/arm64/boot/dts/broadcom/northstar2/Makefile
++++ b/arch/arm64/boot/dts/broadcom/northstar2/Makefile
+@@ -3,4 +3,3 @@ dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/broadcom/stingray/Makefile b/arch/arm64/boot/dts/broadcom/stingray/Makefile
+index 04bb302f3233..fce39a6c2e56 100644
+--- a/arch/arm64/boot/dts/broadcom/stingray/Makefile
++++ b/arch/arm64/boot/dts/broadcom/stingray/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile
+index 9f68c277302b..a7b62eb76cdf 100644
+--- a/arch/arm64/boot/dts/cavium/Makefile
++++ b/arch/arm64/boot/dts/cavium/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
+index 6914b2cbd397..c1b199e6213d 100644
+--- a/arch/arm64/boot/dts/exynos/Makefile
++++ b/arch/arm64/boot/dts/exynos/Makefile
+@@ -6,4 +6,3 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index dc02e82aba7c..a537b2fff41e 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -16,4 +16,3 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
+index 521ed484a5d1..ea696896acb3 100644
+--- a/arch/arm64/boot/dts/hisilicon/Makefile
++++ b/arch/arm64/boot/dts/hisilicon/Makefile
+@@ -8,4 +8,3 @@ dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile
+index e345b8e58efe..cfde42d55cd8 100644
+--- a/arch/arm64/boot/dts/lg/Makefile
++++ b/arch/arm64/boot/dts/lg/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
+index 5633676fa9d0..11debddd9dfd 100644
+--- a/arch/arm64/boot/dts/marvell/Makefile
++++ b/arch/arm64/boot/dts/marvell/Makefile
+@@ -13,4 +13,3 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
+index 1d05d1824fa9..75aa07a89e3c 100644
+--- a/arch/arm64/boot/dts/mediatek/Makefile
++++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -8,4 +8,3 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
+index 6bc0c6ab4b7f..90a34e66048b 100644
+--- a/arch/arm64/boot/dts/nvidia/Makefile
++++ b/arch/arm64/boot/dts/nvidia/Makefile
+@@ -7,4 +7,3 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
+ 
+ always		:= $(dtb-y)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
+index e7b25bee3f1e..08841488d9df 100644
+--- a/arch/arm64/boot/dts/qcom/Makefile
++++ b/arch/arm64/boot/dts/qcom/Makefile
+@@ -9,4 +9,3 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile
+index 8521e921e59a..88cb515f7b21 100644
+--- a/arch/arm64/boot/dts/realtek/Makefile
++++ b/arch/arm64/boot/dts/realtek/Makefile
+@@ -2,4 +2,3 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 842f5884d437..ebb836b2d9e9 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -10,4 +10,3 @@ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+ always		:= $(dtb-y)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 84801892ee61..4e84ef9baec4 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -14,4 +14,3 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
+index 72dbe8acd9fd..1844c004d075 100644
+--- a/arch/arm64/boot/dts/socionext/Makefile
++++ b/arch/arm64/boot/dts/socionext/Makefile
+@@ -7,4 +7,3 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ 	uniphier-pxs3-ref.dtb
+ 
+ always		:= $(dtb-y)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
+index d7188be103c5..ae157b3542b4 100644
+--- a/arch/arm64/boot/dts/sprd/Makefile
++++ b/arch/arm64/boot/dts/sprd/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
+index ae16427f6a4a..74e195650f04 100644
+--- a/arch/arm64/boot/dts/xilinx/Makefile
++++ b/arch/arm64/boot/dts/xilinx/Makefile
+@@ -2,4 +2,3 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile
+index d86c4def6bc9..71e07089cde0 100644
+--- a/arch/arm64/boot/dts/zte/Makefile
++++ b/arch/arm64/boot/dts/zte/Makefile
+@@ -3,4 +3,3 @@ dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb
+diff --git a/arch/c6x/boot/dts/Makefile b/arch/c6x/boot/dts/Makefile
+index 7368838c6e71..b212d278ebc4 100644
+--- a/arch/c6x/boot/dts/Makefile
++++ b/arch/c6x/boot/dts/Makefile
+@@ -17,5 +17,3 @@ $(obj)/builtin.dtb: $(obj)/$(DTB).dtb
+ 	$(call if_changed,cp)
+ 
+ $(obj)/linked_dtb.o: $(obj)/builtin.dtb
+-
+-clean-files := *.dtb
+diff --git a/arch/cris/boot/dts/Makefile b/arch/cris/boot/dts/Makefile
+index 3318c630caa2..118fe990a173 100644
+--- a/arch/cris/boot/dts/Makefile
++++ b/arch/cris/boot/dts/Makefile
+@@ -3,5 +3,3 @@ BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
+ ifneq ($(CONFIG_BUILTIN_DTB),"")
+ obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+ endif
+-
+-clean-files := *.dtb.S
+diff --git a/arch/h8300/boot/dts/Makefile b/arch/h8300/boot/dts/Makefile
+index 14593b51b2b2..e9f70611c86f 100644
+--- a/arch/h8300/boot/dts/Makefile
++++ b/arch/h8300/boot/dts/Makefile
+@@ -13,4 +13,3 @@ dtstree		:= $(srctree)/$(src)
+ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+ 
+ always	    := $(dtb-y)
+-clean-files := *.dtb.S *.dtb
+diff --git a/arch/metag/boot/dts/Makefile b/arch/metag/boot/dts/Makefile
+index ad5dde558db1..fbd7fc4c481d 100644
+--- a/arch/metag/boot/dts/Makefile
++++ b/arch/metag/boot/dts/Makefile
+@@ -19,4 +19,3 @@ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dts
+ .SECONDARY: $(obj)/$(builtindtb-y).dtb.S
+ 
+ always += $(dtb-y)
+-clean-files += *.dtb *.dtb.S
+diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
+index 7c2f52d4a0e4..600e5a198bd2 100644
+--- a/arch/microblaze/boot/Makefile
++++ b/arch/microblaze/boot/Makefile
+@@ -37,4 +37,4 @@ $(obj)/simpleImage.%: vmlinux FORCE
+ 	$(call if_changed,strip,.strip)
+ 	@echo 'Kernel: $(UIMAGE_OUT) is ready' ' (#'`cat .version`')'
+ 
+-clean-files += simpleImage.*.unstrip linux.bin.ub dts/*.dtb
++clean-files += simpleImage.*.unstrip linux.bin.ub
+diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
+index e0a4e939f843..b3f2ee149d8e 100644
+--- a/arch/mips/boot/dts/Makefile
++++ b/arch/mips/boot/dts/Makefile
+@@ -19,4 +19,3 @@ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(foreach d,$(dt
+ 
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+-clean-files	:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/brcm/Makefile b/arch/mips/boot/dts/brcm/Makefile
+index 398994312361..80fdad463531 100644
+--- a/arch/mips/boot/dts/brcm/Makefile
++++ b/arch/mips/boot/dts/brcm/Makefile
+@@ -40,4 +40,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/cavium-octeon/Makefile b/arch/mips/boot/dts/cavium-octeon/Makefile
+index 35300e091573..c0223497009e 100644
+--- a/arch/mips/boot/dts/cavium-octeon/Makefile
++++ b/arch/mips/boot/dts/cavium-octeon/Makefile
+@@ -7,4 +7,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile
+index 139bcd887b86..519178305ce9 100644
+--- a/arch/mips/boot/dts/img/Makefile
++++ b/arch/mips/boot/dts/img/Makefile
+@@ -8,4 +8,3 @@ obj-$(CONFIG_MACH_PISTACHIO)	+= pistachio_marduk.dtb.o
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/ingenic/Makefile b/arch/mips/boot/dts/ingenic/Makefile
+index 7798262570da..e2db1e4b5448 100644
+--- a/arch/mips/boot/dts/ingenic/Makefile
++++ b/arch/mips/boot/dts/ingenic/Makefile
+@@ -8,4 +8,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/lantiq/Makefile b/arch/mips/boot/dts/lantiq/Makefile
+index 0c50e3246a63..58f9c11f12a0 100644
+--- a/arch/mips/boot/dts/lantiq/Makefile
++++ b/arch/mips/boot/dts/lantiq/Makefile
+@@ -7,4 +7,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
+index 5ee06f73c348..8a306abde117 100644
+--- a/arch/mips/boot/dts/mti/Makefile
++++ b/arch/mips/boot/dts/mti/Makefile
+@@ -8,4 +8,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/netlogic/Makefile b/arch/mips/boot/dts/netlogic/Makefile
+index 1cb2fdbd8949..ef7e73f20961 100644
+--- a/arch/mips/boot/dts/netlogic/Makefile
++++ b/arch/mips/boot/dts/netlogic/Makefile
+@@ -11,4 +11,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
+index 66cfdffc51c2..094da7219905 100644
+--- a/arch/mips/boot/dts/ni/Makefile
++++ b/arch/mips/boot/dts/ni/Makefile
+@@ -4,4 +4,3 @@ dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445)	+= 169445.dtb
+ obj-					+= dummy.o
+ 
+ always					:= $(dtb-y)
+-clean-files				:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/pic32/Makefile b/arch/mips/boot/dts/pic32/Makefile
+index a86ddd289cfd..3482cad52849 100644
+--- a/arch/mips/boot/dts/pic32/Makefile
++++ b/arch/mips/boot/dts/pic32/Makefile
+@@ -10,4 +10,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
+index eabd94eb59db..b44eabcdb4b0 100644
+--- a/arch/mips/boot/dts/qca/Makefile
++++ b/arch/mips/boot/dts/qca/Makefile
+@@ -10,4 +10,3 @@ dtb-$(CONFIG_ATH79)			+= ar9331_tl_mr3020.dtb
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
+index a80eeeecf613..f38c5956953f 100644
+--- a/arch/mips/boot/dts/ralink/Makefile
++++ b/arch/mips/boot/dts/ralink/Makefile
+@@ -12,4 +12,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files			:= *.dtb *.dtb.S
+diff --git a/arch/mips/boot/dts/xilfpga/Makefile b/arch/mips/boot/dts/xilfpga/Makefile
+index 498ac081e2fe..0afeee033f1b 100644
+--- a/arch/mips/boot/dts/xilfpga/Makefile
++++ b/arch/mips/boot/dts/xilfpga/Makefile
+@@ -7,4 +7,3 @@ obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+ obj-				+= dummy.o
+ 
+ always				:= $(dtb-y)
+-clean-files	:= *.dtb *.dtb.S
+diff --git a/arch/nios2/boot/Makefile b/arch/nios2/boot/Makefile
+index c899876320df..2ba23a679732 100644
+--- a/arch/nios2/boot/Makefile
++++ b/arch/nios2/boot/Makefile
+@@ -53,7 +53,5 @@ $(obj)/%.dtb: $(src)/dts/%.dts FORCE
+ 
+ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
+ 
+-clean-files := *.dtb
+-
+ install:
+ 	sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
+diff --git a/arch/openrisc/boot/dts/Makefile b/arch/openrisc/boot/dts/Makefile
+index 792ce7143c3a..17dd791a833f 100644
+--- a/arch/openrisc/boot/dts/Makefile
++++ b/arch/openrisc/boot/dts/Makefile
+@@ -6,6 +6,4 @@ BUILTIN_DTB :=
+ endif
+ obj-y += $(BUILTIN_DTB)
+ 
+-clean-files := *.dtb.S
+-
+ #DTC_FLAGS ?= -p 1024
+diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
+index b479926f0167..f257925fa490 100644
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -441,7 +441,7 @@ zInstall: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
+ clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
+ 	zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
+ 	zImage.miboot zImage.pmac zImage.pseries \
+-	zImage.maple simpleImage.* otheros.bld *.dtb
++	zImage.maple simpleImage.* otheros.bld
+ 
+ # clean up files cached by wrapper
+ clean-kernel-base := vmlinux.strip vmlinux.bin
+diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile
+index e5ce3a0de7f4..715def00a436 100644
+--- a/arch/sh/boot/dts/Makefile
++++ b/arch/sh/boot/dts/Makefile
+@@ -1,3 +1 @@
+ obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
+-
+-clean-files := *.dtb.S
+diff --git a/arch/xtensa/boot/dts/Makefile b/arch/xtensa/boot/dts/Makefile
+index a15e241c9153..c62dd6ca1f82 100644
+--- a/arch/xtensa/boot/dts/Makefile
++++ b/arch/xtensa/boot/dts/Makefile
+@@ -16,5 +16,3 @@ dtstree := $(srctree)/$(src)
+ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+ 
+ always += $(dtb-y)
+-clean-files += *.dtb *.dtb.S
+-
+-- 
+2.19.0
+
diff --git a/patches/0082-arm64-dts-renesas-salvator-x-Remove-renesas-no-ether.patch b/patches/0082-arm64-dts-renesas-salvator-x-Remove-renesas-no-ether.patch
new file mode 100644
index 00000000000000..9eee2bea307cfd
--- /dev/null
+++ b/patches/0082-arm64-dts-renesas-salvator-x-Remove-renesas-no-ether.patch
@@ -0,0 +1,62 @@
+From 3a5de1e1b611ccb39f700b41656a6d44b75a0dfa Mon Sep 17 00:00:00 2001
+From: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
+Date: Thu, 21 Dec 2017 17:18:58 +0200
+Subject: [PATCH 0082/1795] arm64: dts: renesas: salvator-x: Remove renesas,
+ no-ether-link property
+
+The present change is a bug fix for AVB link iteratively up/down.
+
+Steps to reproduce:
+- start AVB TX stream (Using aplay via MSE),
+- disconnect+reconnect the eth cable,
+- after a reconnection the eth connection goes iteratively up/down
+  without user interaction,
+- this may heal after some seconds or even stay for minutes.
+
+As the documentation specifies, the "renesas,no-ether-link" option
+should be used when a board does not provide a proper AVB_LINK signal.
+There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS
+and ULCB starter kits since the AVB_LINK is correctly handled by HW.
+
+Choosing to keep or remove the "renesas,no-ether-link" option will
+have impact on the code flow in the following ways:
+- keeping this option enabled may lead to unexpected behavior since
+  the RX & TX are enabled/disabled directly from adjust_link function
+  without any HW interrogation,
+- removing this option, the RX & TX will only be enabled/disabled after
+  HW interrogation. The HW check is made through the LMON pin in PSR
+  register which specifies AVB_LINK signal value (0 - at low level;
+  1 - at high level).
+
+In conclusion, the present change is also a safety improvement because
+it removes the "renesas,no-ether-link" option leading to a proper way
+of detecting the link state based on HW interrogation and not on
+software heuristic.
+
+Fixes: dc36965a8905 ("arm64: dts: r8a7796: salvator-x: Enable EthernetAVB")
+Fixes: 6fa501c549aa ("arm64: dts: r8a7795: enable EthernetAVB on Salvator-X")
+Signed-off-by: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 87c059e9c39dae20b8b9bd19d9ec55a6d6c10468)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index eab44b9bdaa7..8a2bcc73d5f0 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -247,7 +247,6 @@
+ &avb {
+ 	pinctrl-0 = <&avb_pins>;
+ 	pinctrl-names = "default";
+-	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
+ 	status = "okay";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0083-pinctrl-gpio-Unify-namespace-for-cross-calls.patch b/patches/0083-pinctrl-gpio-Unify-namespace-for-cross-calls.patch
new file mode 100644
index 00000000000000..ce21ac20b601c7
--- /dev/null
+++ b/patches/0083-pinctrl-gpio-Unify-namespace-for-cross-calls.patch
@@ -0,0 +1,532 @@
+From ba6388cb9360489bc594e4493a87531ce1b969e5 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 22 Sep 2017 11:02:10 +0200
+Subject: [PATCH 0083/1795] pinctrl/gpio: Unify namespace for cross-calls
+
+The pinctrl_request_gpio() and pinctrl_free_gpio() break the nice
+namespacing in the other cross-calls like pinctrl_gpio_foo().
+Just rename them and all references so we have one namespace
+with all cross-calls under pinctrl_gpio_*().
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit a9a1d2a7827c9cf780966d0879c73ef5a91380e9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/pinctl.rst       |  6 +++---
+ Documentation/gpio/gpio-legacy.txt        | 10 +++++-----
+ Documentation/translations/zh_CN/gpio.txt |  6 +++---
+ drivers/gpio/gpio-aspeed.c                |  4 ++--
+ drivers/gpio/gpio-em.c                    |  4 ++--
+ drivers/gpio/gpio-pxa.c                   |  4 ++--
+ drivers/gpio/gpio-rcar.c                  |  4 ++--
+ drivers/gpio/gpio-tegra.c                 |  4 ++--
+ drivers/gpio/gpio-tz1090.c                |  4 ++--
+ drivers/gpio/gpiolib.c                    |  4 ++--
+ drivers/pinctrl/bcm/pinctrl-iproc-gpio.c  |  4 ++--
+ drivers/pinctrl/bcm/pinctrl-nsp-gpio.c    |  4 ++--
+ drivers/pinctrl/core.c                    | 12 ++++++------
+ drivers/pinctrl/core.h                    |  2 +-
+ drivers/pinctrl/meson/pinctrl-meson.c     |  4 ++--
+ drivers/pinctrl/sh-pfc/gpio.c             |  4 ++--
+ drivers/pinctrl/sirf/pinctrl-atlas7.c     |  4 ++--
+ drivers/pinctrl/sirf/pinctrl-sirf.c       |  4 ++--
+ drivers/pinctrl/spear/pinctrl-plgpio.c    |  6 +++---
+ drivers/pinctrl/stm32/pinctrl-stm32.c     |  4 ++--
+ include/linux/pinctrl/consumer.h          |  8 ++++----
+ 21 files changed, 53 insertions(+), 53 deletions(-)
+
+diff --git a/Documentation/driver-api/pinctl.rst b/Documentation/driver-api/pinctl.rst
+index 48f15b4f9d3e..6cb68d67fa75 100644
+--- a/Documentation/driver-api/pinctl.rst
++++ b/Documentation/driver-api/pinctl.rst
+@@ -757,8 +757,8 @@ that your datasheet calls "GPIO mode", but actually is just an electrical
+ configuration for a certain device. See the section below named
+ "GPIO mode pitfalls" for more details on this scenario.
+ 
+-The public pinmux API contains two functions named pinctrl_request_gpio()
+-and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
++The public pinmux API contains two functions named pinctrl_gpio_request()
++and pinctrl_gpio_free(). These two functions shall *ONLY* be called from
+ gpiolib-based drivers as part of their gpio_request() and
+ gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
+ shall only be called from within respective gpio_direction_[input|output]
+@@ -790,7 +790,7 @@ gpiolib driver and the affected GPIO range, pin offset and desired direction
+ will be passed along to this function.
+ 
+ Alternatively to using these special functions, it is fully allowed to use
+-named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
++named functions for each GPIO pin, the pinctrl_gpio_request() will attempt to
+ obtain the function "gpioN" where "N" is the global GPIO pin number if no
+ special GPIO-handler is registered.
+ 
+diff --git a/Documentation/gpio/gpio-legacy.txt b/Documentation/gpio/gpio-legacy.txt
+index 5eacc147ea87..8356d0e78f67 100644
+--- a/Documentation/gpio/gpio-legacy.txt
++++ b/Documentation/gpio/gpio-legacy.txt
+@@ -273,8 +273,8 @@ easily, gating off unused clocks.
+ 
+ For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
+ be informed of their use; a gpiolib driver's .request() operation may call
+-pinctrl_request_gpio(), and a gpiolib driver's .free() operation may call
+-pinctrl_free_gpio(). The pinctrl subsystem allows a pinctrl_request_gpio()
++pinctrl_gpio_request(), and a gpiolib driver's .free() operation may call
++pinctrl_gpio_free(). The pinctrl subsystem allows a pinctrl_gpio_request()
+ to succeed concurrently with a pin or pingroup being "owned" by a device for
+ pin multiplexing.
+ 
+@@ -448,8 +448,8 @@ together with an optional gpio feature. We have already covered the
+ case where e.g. a GPIO controller need to reserve a pin or set the
+ direction of a pin by calling any of:
+ 
+-pinctrl_request_gpio()
+-pinctrl_free_gpio()
++pinctrl_gpio_request()
++pinctrl_gpio_free()
+ pinctrl_gpio_direction_input()
+ pinctrl_gpio_direction_output()
+ 
+@@ -466,7 +466,7 @@ gpio (under gpiolib) is still maintained by gpio drivers. It may happen
+ that different pin ranges in a SoC is managed by different gpio drivers.
+ 
+ This makes it logical to let gpio drivers announce their pin ranges to
+-the pin ctrl subsystem before it will call 'pinctrl_request_gpio' in order
++the pin ctrl subsystem before it will call 'pinctrl_gpio_request' in order
+ to request the corresponding pin to be prepared by the pinctrl subsystem
+ before any gpio usage.
+ 
+diff --git a/Documentation/translations/zh_CN/gpio.txt b/Documentation/translations/zh_CN/gpio.txt
+index bce972521065..4f8bf30a41dc 100644
+--- a/Documentation/translations/zh_CN/gpio.txt
++++ b/Documentation/translations/zh_CN/gpio.txt
+@@ -257,9 +257,9 @@ GPIO 值的命令需要等待其信息排到队首才发送命令，再获得其
+ 简单地关闭未使用时钟)。
+ 
+ 对于 GPIO 使用 pinctrl 子系统已知的引脚，子系统应该被告知其使用情况；
+-一个 gpiolib 驱动的 .request()操作应调用 pinctrl_request_gpio()，
+-而 gpiolib 驱动的 .free()操作应调用 pinctrl_free_gpio()。pinctrl
+-子系统允许 pinctrl_request_gpio()在某个引脚或引脚组以复用形式“属于”
++一个 gpiolib 驱动的 .request()操作应调用 pinctrl_gpio_request()，
++而 gpiolib 驱动的 .free()操作应调用 pinctrl_gpio_free()。pinctrl
++子系统允许 pinctrl_gpio_request()在某个引脚或引脚组以复用形式“属于”
+ 一个设备时都成功返回。
+ 
+ 任何须将 GPIO 信号导向适当引脚的引脚复用硬件的编程应该发生在 GPIO
+diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
+index f03fe916eb9d..bf34b5eae705 100644
+--- a/drivers/gpio/gpio-aspeed.c
++++ b/drivers/gpio/gpio-aspeed.c
+@@ -536,12 +536,12 @@ static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
+ 	if (!have_gpio(gpiochip_get_data(chip), offset))
+ 		return -ENODEV;
+ 
+-	return pinctrl_request_gpio(chip->base + offset);
++	return pinctrl_gpio_request(chip->base + offset);
+ }
+ 
+ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
+ {
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ }
+ 
+ static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
+diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
+index 8d32ccc980d9..b86e09e1b13b 100644
+--- a/drivers/gpio/gpio-em.c
++++ b/drivers/gpio/gpio-em.c
+@@ -239,12 +239,12 @@ static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
+ 
+ static int em_gio_request(struct gpio_chip *chip, unsigned offset)
+ {
+-	return pinctrl_request_gpio(chip->base + offset);
++	return pinctrl_gpio_request(chip->base + offset);
+ }
+ 
+ static void em_gio_free(struct gpio_chip *chip, unsigned offset)
+ {
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ 
+ 	/* Set the GPIO as an input to ensure that the next GPIO request won't
+ 	* drive the GPIO pin as an output.
+diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
+index 6029899789f3..da68d6cbc1e4 100644
+--- a/drivers/gpio/gpio-pxa.c
++++ b/drivers/gpio/gpio-pxa.c
+@@ -332,12 +332,12 @@ static int pxa_gpio_of_xlate(struct gpio_chip *gc,
+ 
+ static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
+ {
+-	return pinctrl_request_gpio(chip->base + offset);
++	return pinctrl_gpio_request(chip->base + offset);
+ }
+ 
+ static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
+ {
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ }
+ 
+ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index 1f0871553fd2..43b51045aa47 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -249,7 +249,7 @@ static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
+ 	if (error < 0)
+ 		return error;
+ 
+-	error = pinctrl_request_gpio(chip->base + offset);
++	error = pinctrl_gpio_request(chip->base + offset);
+ 	if (error)
+ 		pm_runtime_put(&p->pdev->dev);
+ 
+@@ -260,7 +260,7 @@ static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
+ {
+ 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
+ 
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ 
+ 	/*
+ 	 * Set the GPIO as an input to ensure that the next GPIO request won't
+diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
+index fbaf974277df..8db47f671708 100644
+--- a/drivers/gpio/gpio-tegra.c
++++ b/drivers/gpio/gpio-tegra.c
+@@ -141,14 +141,14 @@ static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
+ 
+ static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
+ {
+-	return pinctrl_request_gpio(offset);
++	return pinctrl_gpio_request(offset);
+ }
+ 
+ static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
+ {
+ 	struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
+ 
+-	pinctrl_free_gpio(offset);
++	pinctrl_gpio_free(offset);
+ 	tegra_gpio_disable(tgi, offset);
+ }
+ 
+diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c
+index 22c5be65051f..0bb9bb583889 100644
+--- a/drivers/gpio/gpio-tz1090.c
++++ b/drivers/gpio/gpio-tz1090.c
+@@ -232,7 +232,7 @@ static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
+ 	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
+ 	int ret;
+ 
+-	ret = pinctrl_request_gpio(chip->base + offset);
++	ret = pinctrl_gpio_request(chip->base + offset);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -246,7 +246,7 @@ static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
+ {
+ 	struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
+ 
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ 
+ 	tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
+ }
+diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
+index 7e0bfd7347f6..99d0b3510b54 100644
+--- a/drivers/gpio/gpiolib.c
++++ b/drivers/gpio/gpiolib.c
+@@ -1863,7 +1863,7 @@ static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
+  */
+ int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset)
+ {
+-	return pinctrl_request_gpio(chip->gpiodev->base + offset);
++	return pinctrl_gpio_request(chip->gpiodev->base + offset);
+ }
+ EXPORT_SYMBOL_GPL(gpiochip_generic_request);
+ 
+@@ -1874,7 +1874,7 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_request);
+  */
+ void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset)
+ {
+-	pinctrl_free_gpio(chip->gpiodev->base + offset);
++	pinctrl_gpio_free(chip->gpiodev->base + offset);
+ }
+ EXPORT_SYMBOL_GPL(gpiochip_generic_free);
+ 
+diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+index 85a8c97d9dfe..5d08d989b1d0 100644
+--- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
++++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+@@ -311,7 +311,7 @@ static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
+ 	if (!chip->pinmux_is_supported)
+ 		return 0;
+ 
+-	return pinctrl_request_gpio(gpio);
++	return pinctrl_gpio_request(gpio);
+ }
+ 
+ static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
+@@ -322,7 +322,7 @@ static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
+ 	if (!chip->pinmux_is_supported)
+ 		return;
+ 
+-	pinctrl_free_gpio(gpio);
++	pinctrl_gpio_free(gpio);
+ }
+ 
+ static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
+diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+index 1cfe45fd391f..c1887072936e 100644
+--- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
++++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+@@ -282,14 +282,14 @@ static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
+ {
+ 	unsigned gpio = gc->base + offset;
+ 
+-	return pinctrl_request_gpio(gpio);
++	return pinctrl_gpio_request(gpio);
+ }
+ 
+ static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
+ {
+ 	unsigned gpio = gc->base + offset;
+ 
+-	pinctrl_free_gpio(gpio);
++	pinctrl_gpio_free(gpio);
+ }
+ 
+ static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
+diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
+index c55517312485..2c0dbfcff3e6 100644
+--- a/drivers/pinctrl/core.c
++++ b/drivers/pinctrl/core.c
+@@ -733,14 +733,14 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
+ }
+ 
+ /**
+- * pinctrl_request_gpio() - request a single pin to be used as GPIO
++ * pinctrl_gpio_request() - request a single pin to be used as GPIO
+  * @gpio: the GPIO pin number from the GPIO subsystem number space
+  *
+  * This function should *ONLY* be used from gpiolib-based GPIO drivers,
+  * as part of their gpio_request() semantics, platforms and individual drivers
+  * shall *NOT* request GPIO pins to be muxed in.
+  */
+-int pinctrl_request_gpio(unsigned gpio)
++int pinctrl_gpio_request(unsigned gpio)
+ {
+ 	struct pinctrl_dev *pctldev;
+ 	struct pinctrl_gpio_range *range;
+@@ -765,17 +765,17 @@ int pinctrl_request_gpio(unsigned gpio)
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL_GPL(pinctrl_request_gpio);
++EXPORT_SYMBOL_GPL(pinctrl_gpio_request);
+ 
+ /**
+- * pinctrl_free_gpio() - free control on a single pin, currently used as GPIO
++ * pinctrl_gpio_free() - free control on a single pin, currently used as GPIO
+  * @gpio: the GPIO pin number from the GPIO subsystem number space
+  *
+  * This function should *ONLY* be used from gpiolib-based GPIO drivers,
+  * as part of their gpio_free() semantics, platforms and individual drivers
+  * shall *NOT* request GPIO pins to be muxed out.
+  */
+-void pinctrl_free_gpio(unsigned gpio)
++void pinctrl_gpio_free(unsigned gpio)
+ {
+ 	struct pinctrl_dev *pctldev;
+ 	struct pinctrl_gpio_range *range;
+@@ -795,7 +795,7 @@ void pinctrl_free_gpio(unsigned gpio)
+ 
+ 	mutex_unlock(&pctldev->mutex);
+ }
+-EXPORT_SYMBOL_GPL(pinctrl_free_gpio);
++EXPORT_SYMBOL_GPL(pinctrl_gpio_free);
+ 
+ static int pinctrl_gpio_direction(unsigned gpio, bool input)
+ {
+diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
+index 7880c3adc450..8cf2eba17c8c 100644
+--- a/drivers/pinctrl/core.h
++++ b/drivers/pinctrl/core.h
+@@ -154,7 +154,7 @@ struct pinctrl_setting {
+  *	or pin, and each of these will increment the @usecount.
+  * @mux_owner: The name of device that called pinctrl_get().
+  * @mux_setting: The most recent selected mux setting for this pin, if any.
+- * @gpio_owner: If pinctrl_request_gpio() was called for this pin, this is
++ * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is
+  *	the name of the GPIO that "owns" this pin.
+  */
+ struct pin_desc {
+diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
+index 66ed70c12733..e6e12a7b21e0 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson.c
++++ b/drivers/pinctrl/meson/pinctrl-meson.c
+@@ -412,14 +412,14 @@ static const struct pinconf_ops meson_pinconf_ops = {
+ 
+ static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
+ {
+-	return pinctrl_request_gpio(chip->base + gpio);
++	return pinctrl_gpio_request(chip->base + gpio);
+ }
+ 
+ static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
+ {
+ 	struct meson_pinctrl *pc = gpiochip_get_data(chip);
+ 
+-	pinctrl_free_gpio(pc->data->pin_base + gpio);
++	pinctrl_gpio_free(pc->data->pin_base + gpio);
+ }
+ 
+ static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
+index 6b5422766f13..946d9be50b62 100644
+--- a/drivers/pinctrl/sh-pfc/gpio.c
++++ b/drivers/pinctrl/sh-pfc/gpio.c
+@@ -139,12 +139,12 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
+ 	if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
+ 		return -EINVAL;
+ 
+-	return pinctrl_request_gpio(offset);
++	return pinctrl_gpio_request(offset);
+ }
+ 
+ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
+ {
+-	return pinctrl_free_gpio(offset);
++	return pinctrl_gpio_free(offset);
+ }
+ 
+ static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
+diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
+index 4db9323251e3..f4b192b493a0 100644
+--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
++++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
+@@ -5860,7 +5860,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	if (pinctrl_request_gpio(chip->base + gpio))
++	if (pinctrl_gpio_request(chip->base + gpio))
+ 		return -ENODEV;
+ 
+ 	raw_spin_lock_irqsave(&a7gc->lock, flags);
+@@ -5890,7 +5890,7 @@ static void atlas7_gpio_free(struct gpio_chip *chip,
+ 
+ 	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
+ 
+-	pinctrl_free_gpio(chip->base + gpio);
++	pinctrl_gpio_free(chip->base + gpio);
+ }
+ 
+ static int atlas7_gpio_direction_input(struct gpio_chip *chip,
+diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
+index d3ef05973901..d64add0b84cc 100644
+--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
++++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
+@@ -614,7 +614,7 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
+ 	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
+ 	unsigned long flags;
+ 
+-	if (pinctrl_request_gpio(chip->base + offset))
++	if (pinctrl_gpio_request(chip->base + offset))
+ 		return -ENODEV;
+ 
+ 	spin_lock_irqsave(&bank->lock, flags);
+@@ -644,7 +644,7 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
+ 
+ 	spin_unlock_irqrestore(&bank->lock, flags);
+ 
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ }
+ 
+ static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
+index cf6d68c7345b..7a33e2e1e3e7 100644
+--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
++++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
+@@ -204,7 +204,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset)
+ 	if (offset >= chip->ngpio)
+ 		return -EINVAL;
+ 
+-	ret = pinctrl_request_gpio(gpio);
++	ret = pinctrl_gpio_request(gpio);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -242,7 +242,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset)
+ 	if (!IS_ERR(plgpio->clk))
+ 		clk_disable(plgpio->clk);
+ err0:
+-	pinctrl_free_gpio(gpio);
++	pinctrl_gpio_free(gpio);
+ 	return ret;
+ }
+ 
+@@ -273,7 +273,7 @@ static void plgpio_free(struct gpio_chip *chip, unsigned offset)
+ 	if (!IS_ERR(plgpio->clk))
+ 		clk_disable(plgpio->clk);
+ 
+-	pinctrl_free_gpio(gpio);
++	pinctrl_gpio_free(gpio);
+ }
+ 
+ /* PLGPIO IRQ */
+diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
+index 50299ad96659..a954d25bac4e 100644
+--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
++++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
+@@ -150,12 +150,12 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
+ 		return -EINVAL;
+ 	}
+ 
+-	return pinctrl_request_gpio(chip->base + offset);
++	return pinctrl_gpio_request(chip->base + offset);
+ }
+ 
+ static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
+ {
+-	pinctrl_free_gpio(chip->base + offset);
++	pinctrl_gpio_free(chip->base + offset);
+ }
+ 
+ static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
+diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
+index a0f2aba72fa9..0412cc9833e9 100644
+--- a/include/linux/pinctrl/consumer.h
++++ b/include/linux/pinctrl/consumer.h
+@@ -25,8 +25,8 @@ struct device;
+ #ifdef CONFIG_PINCTRL
+ 
+ /* External interface to pin control */
+-extern int pinctrl_request_gpio(unsigned gpio);
+-extern void pinctrl_free_gpio(unsigned gpio);
++extern int pinctrl_gpio_request(unsigned gpio);
++extern void pinctrl_gpio_free(unsigned gpio);
+ extern int pinctrl_gpio_direction_input(unsigned gpio);
+ extern int pinctrl_gpio_direction_output(unsigned gpio);
+ extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config);
+@@ -62,12 +62,12 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev)
+ 
+ #else /* !CONFIG_PINCTRL */
+ 
+-static inline int pinctrl_request_gpio(unsigned gpio)
++static inline int pinctrl_gpio_request(unsigned gpio)
+ {
+ 	return 0;
+ }
+ 
+-static inline void pinctrl_free_gpio(unsigned gpio)
++static inline void pinctrl_gpio_free(unsigned gpio)
+ {
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0084-Input-gpio-keys-convert-timers-to-use-timer_setup.patch b/patches/0084-Input-gpio-keys-convert-timers-to-use-timer_setup.patch
new file mode 100644
index 00000000000000..85d3f93204bc7a
--- /dev/null
+++ b/patches/0084-Input-gpio-keys-convert-timers-to-use-timer_setup.patch
@@ -0,0 +1,48 @@
+From 6e5a4b3b9d1f814b27f1cab927ffaf2b0a61ea9f Mon Sep 17 00:00:00 2001
+From: stephen lu <lumotuwe@gmail.com>
+Date: Mon, 23 Oct 2017 14:43:53 -0700
+Subject: [PATCH 0084/1795] Input: gpio-keys - convert timers to use
+ timer_setup()
+
+In preparation for unconditionally passing the struct timer_list pointer to
+all timer callbacks, switch to using the new timer_setup() and from_timer()
+to pass the timer pointer explicitly.
+
+Signed-off-by: Stephen Lu <lumotuwe@gmail.com>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+(cherry picked from commit 82565a120544b2bdfaf602d9f5e7b9ab9a342ae8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/input/keyboard/gpio_keys.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
+index e9f0ebf3267a..87e613dc33b8 100644
+--- a/drivers/input/keyboard/gpio_keys.c
++++ b/drivers/input/keyboard/gpio_keys.c
+@@ -419,9 +419,9 @@ static irqreturn_t gpio_keys_gpio_isr(int irq, void *dev_id)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static void gpio_keys_irq_timer(unsigned long _data)
++static void gpio_keys_irq_timer(struct timer_list *t)
+ {
+-	struct gpio_button_data *bdata = (struct gpio_button_data *)_data;
++	struct gpio_button_data *bdata = from_timer(bdata, t, release_timer);
+ 	struct input_dev *input = bdata->input;
+ 	unsigned long flags;
+ 
+@@ -582,8 +582,7 @@ static int gpio_keys_setup_key(struct platform_device *pdev,
+ 		}
+ 
+ 		bdata->release_delay = button->debounce_interval;
+-		setup_timer(&bdata->release_timer,
+-			    gpio_keys_irq_timer, (unsigned long)bdata);
++		timer_setup(&bdata->release_timer, gpio_keys_irq_timer, 0);
+ 
+ 		isr = gpio_keys_irq_isr;
+ 		irqflags = 0;
+-- 
+2.19.0
+
diff --git a/patches/0085-gpio-rcar-Use-of_device_get_match_data-helper.patch b/patches/0085-gpio-rcar-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..0c420800a98c42
--- /dev/null
+++ b/patches/0085-gpio-rcar-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,52 @@
+From 3460162ad1de35498cdca4bc7b8a1109eb77afdb Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:16:16 +0200
+Subject: [PATCH 0085/1795] gpio: rcar: Use of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+Note that the gpio-rcar driver is used with DT only, so there's always a
+valid match.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit f9f2a6fe1399d1fab38b6c1d0639928a52b67a79)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-rcar.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index 43b51045aa47..3d0a2a7dd631 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -24,6 +24,7 @@
+ #include <linux/irq.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+@@ -393,16 +394,11 @@ MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
+ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
+ {
+ 	struct device_node *np = p->pdev->dev.of_node;
+-	const struct of_device_id *match;
+ 	const struct gpio_rcar_info *info;
+ 	struct of_phandle_args args;
+ 	int ret;
+ 
+-	match = of_match_node(gpio_rcar_of_table, np);
+-	if (!match)
+-		return -EINVAL;
+-
+-	info = match->data;
++	info = of_device_get_match_data(&p->pdev->dev);
+ 
+ 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
+ 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
+-- 
+2.19.0
+
diff --git a/patches/0086-gpio-rcar-document-R8A77970-bindings.patch b/patches/0086-gpio-rcar-document-R8A77970-bindings.patch
new file mode 100644
index 00000000000000..9b08cba59c46f1
--- /dev/null
+++ b/patches/0086-gpio-rcar-document-R8A77970-bindings.patch
@@ -0,0 +1,32 @@
+From 373fc5dbe6c7de59d38c12b3553ba4c1534fb8f6 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 11 Oct 2017 22:51:59 +0300
+Subject: [PATCH 0086/1795] gpio-rcar: document R8A77970 bindings
+
+Renesas R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible GPIO
+controllers, so document the SoC specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit f76a2d9d7f9524c54dfd9c7b49ed26e488c4cf6c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index 51c86f69995e..41137a1cc099 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -14,6 +14,7 @@ Required Properties:
+     - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
+     - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
+     - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
++    - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
+     - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+     - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+     - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/0087-gpio-rcar-use-devm_ioremap_resource.patch b/patches/0087-gpio-rcar-use-devm_ioremap_resource.patch
new file mode 100644
index 00000000000000..a615f15ae4b565
--- /dev/null
+++ b/patches/0087-gpio-rcar-use-devm_ioremap_resource.patch
@@ -0,0 +1,57 @@
+From c736bdac71f78a4de06b667febbe7bb51efbd027 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 13 Oct 2017 00:08:14 +0300
+Subject: [PATCH 0087/1795] gpio-rcar: use devm_ioremap_resource()
+
+Using devm_ioremap_resource() has several advantages over devm_ioremap():
+- it checks the passed resource's validity;
+- it calls devm_request_mem_region() to check for the resource overlap;
+- it prints an error message in case of error.
+
+We can call devm_ioremap_resource() instead of devm_ioremap_nocache()
+as ioremap() and ioremap_nocache()  are implemented identically on ARM.
+Doing this saves 2 LoCs and 80 bytes (AArch64 gcc 4.8.5).
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 5a24d4b601561da08a70c065d4630bd9fadb37e8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-rcar.c | 14 ++++++--------
+ 1 file changed, 6 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index 3d0a2a7dd631..2cf5f458928b 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -452,19 +452,17 @@ static int gpio_rcar_probe(struct platform_device *pdev)
+ 
+ 	pm_runtime_enable(dev);
+ 
+-	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+-
+-	if (!io || !irq) {
+-		dev_err(dev, "missing IRQ or IOMEM\n");
++	if (!irq) {
++		dev_err(dev, "missing IRQ\n");
+ 		ret = -EINVAL;
+ 		goto err0;
+ 	}
+ 
+-	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
+-	if (!p->base) {
+-		dev_err(dev, "failed to remap I/O memory\n");
+-		ret = -ENXIO;
++	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	p->base = devm_ioremap_resource(dev, io);
++	if (IS_ERR(p->base)) {
++		ret = PTR_ERR(p->base);
+ 		goto err0;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0088-gpio-rcar-Add-r8a77995-R-Car-D3-support.patch b/patches/0088-gpio-rcar-Add-r8a77995-R-Car-D3-support.patch
new file mode 100644
index 00000000000000..f7078ca1c64d74
--- /dev/null
+++ b/patches/0088-gpio-rcar-Add-r8a77995-R-Car-D3-support.patch
@@ -0,0 +1,36 @@
+From d4aa420547e39a34eb1b257a2b4e40e6a625ab73 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 9 Nov 2017 11:39:20 +0100
+Subject: [PATCH 0088/1795] gpio: rcar: Add r8a77995 (R-Car D3) support
+
+This patch adds binding for r8a77995 (R-Car D3). This SoC can use
+"renesas,rcar-gen3-gpio" fallback compatibility. So, this patch
+doesn't modify the gpio-rcar driver.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 924d4db29f1237f9fe90a7439d2ee81837d282bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index 41137a1cc099..a7ac460ad657 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -15,6 +15,7 @@ Required Properties:
+     - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
+     - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
+     - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
++    - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
+     - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+     - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+     - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/0089-i2c-rcar-document-R8A77970-bindings.patch b/patches/0089-i2c-rcar-document-R8A77970-bindings.patch
new file mode 100644
index 00000000000000..b298efee9d2460
--- /dev/null
+++ b/patches/0089-i2c-rcar-document-R8A77970-bindings.patch
@@ -0,0 +1,34 @@
+From 325ddbfee76fc57d47acccce210370d67b622b43 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 13 Oct 2017 15:23:55 +0300
+Subject: [PATCH 0089/1795] i2c: rcar: document R8A77970 bindings
+
+R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible I2C controller,
+so document  the SoC specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit db6b78073ac135bb68cae77bb873371d0fe0efa6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+index cad39aee9f73..a777477e4547 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+@@ -13,6 +13,7 @@ Required properties:
+ 	"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
+ 	"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
+ 	"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
++	"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+ 	"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+ 	"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ 				device.
+-- 
+2.19.0
+
diff --git a/patches/0090-i2c-riic-remove-clock-and-frequency-restrictions.patch b/patches/0090-i2c-riic-remove-clock-and-frequency-restrictions.patch
new file mode 100644
index 00000000000000..a798a13cfb01e5
--- /dev/null
+++ b/patches/0090-i2c-riic-remove-clock-and-frequency-restrictions.patch
@@ -0,0 +1,196 @@
+From 15da4a93a1cfb4a61cae50dcc0750c62e71a439d Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Fri, 27 Oct 2017 10:37:56 -0500
+Subject: [PATCH 0090/1795] i2c: riic: remove clock and frequency restrictions
+
+Remove the restriction that the parent clock has to be a specific frequency
+and also allow any speed to be supported.
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit d982d66514192cdbe74eababa63d0a69be4b0ce1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-riic.c | 115 ++++++++++++++++++++++++----------
+ 1 file changed, 81 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
+index c811af4c8d81..95c2f1ce3cad 100644
+--- a/drivers/i2c/busses/i2c-riic.c
++++ b/drivers/i2c/busses/i2c-riic.c
+@@ -84,12 +84,7 @@
+ 
+ #define ICSR2_NACKF	0x10
+ 
+-/* ICBRx (@ PCLK 33MHz) */
+ #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
+-#define ICBRL_SP100K	(19 | ICBR_RESERVED)
+-#define ICBRH_SP100K	(16 | ICBR_RESERVED)
+-#define ICBRL_SP400K	(21 | ICBR_RESERVED)
+-#define ICBRH_SP400K	(9 | ICBR_RESERVED)
+ 
+ #define RIIC_INIT_MSG	-1
+ 
+@@ -288,48 +283,99 @@ static const struct i2c_algorithm riic_algo = {
+ 	.functionality	= riic_func,
+ };
+ 
+-static int riic_init_hw(struct riic_dev *riic, u32 spd)
++static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
+ {
+ 	int ret;
+ 	unsigned long rate;
++	int total_ticks, cks, brl, brh;
+ 
+ 	ret = clk_prepare_enable(riic->clk);
+ 	if (ret)
+ 		return ret;
+ 
++	if (t->bus_freq_hz > 400000) {
++		dev_err(&riic->adapter.dev,
++			"unsupported bus speed (%dHz). 400000 max\n",
++			t->bus_freq_hz);
++		clk_disable_unprepare(riic->clk);
++		return -EINVAL;
++	}
++
++	rate = clk_get_rate(riic->clk);
++
+ 	/*
+-	 * TODO: Implement formula to calculate the timing values depending on
+-	 * variable parent clock rate and arbitrary bus speed
++	 * Assume the default register settings:
++	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
++	 *  FER.NFE = 1 (noise circuit enabled)
++	 *  MR3.NF = 0 (1 cycle of noise filtered out)
++	 *
++	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
++	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
+ 	 */
+-	rate = clk_get_rate(riic->clk);
+-	if (rate != 33325000) {
+-		dev_err(&riic->adapter.dev,
+-			"invalid parent clk (%lu). Must be 33325000Hz\n", rate);
++
++	/*
++	 * Determine reference clock rate. We must be able to get the desired
++	 * frequency with only 62 clock ticks max (31 high, 31 low).
++	 * Aim for a duty of 60% LOW, 40% HIGH.
++	 */
++	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
++
++	for (cks = 0; cks < 7; cks++) {
++		/*
++		 * 60% low time must be less than BRL + 2 + 1
++		 * BRL max register value is 0x1F.
++		 */
++		brl = ((total_ticks * 6) / 10);
++		if (brl <= (0x1F + 3))
++			break;
++
++		total_ticks /= 2;
++		rate /= 2;
++	}
++
++	if (brl > (0x1F + 3)) {
++		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
++			(unsigned long)t->bus_freq_hz);
+ 		clk_disable_unprepare(riic->clk);
+ 		return -EINVAL;
+ 	}
+ 
++	brh = total_ticks - brl;
++
++	/* Remove automatic clock ticks for sync circuit and NF */
++	if (cks == 0) {
++		brl -= 4;
++		brh -= 4;
++	} else {
++		brl -= 3;
++		brh -= 3;
++	}
++
++	/*
++	 * Remove clock ticks for rise and fall times. Convert ns to clock
++	 * ticks.
++	 */
++	brl -= t->scl_fall_ns / (1000000000 / rate);
++	brh -= t->scl_rise_ns / (1000000000 / rate);
++
++	/* Adjust for min register values for when SCLE=1 and NFE=1 */
++	if (brl < 1)
++		brl = 1;
++	if (brh < 1)
++		brh = 1;
++
++	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
++		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
++		 t->scl_fall_ns / (1000000000 / rate),
++		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
++
+ 	/* Changing the order of accessing IICRST and ICE may break things! */
+ 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
+ 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
+ 
+-	switch (spd) {
+-	case 100000:
+-		writeb(ICMR1_CKS(3), riic->base + RIIC_ICMR1);
+-		writeb(ICBRH_SP100K, riic->base + RIIC_ICBRH);
+-		writeb(ICBRL_SP100K, riic->base + RIIC_ICBRL);
+-		break;
+-	case 400000:
+-		writeb(ICMR1_CKS(1), riic->base + RIIC_ICMR1);
+-		writeb(ICBRH_SP400K, riic->base + RIIC_ICBRH);
+-		writeb(ICBRL_SP400K, riic->base + RIIC_ICBRL);
+-		break;
+-	default:
+-		dev_err(&riic->adapter.dev,
+-			"unsupported bus speed (%dHz). Use 100000 or 400000\n", spd);
+-		clk_disable_unprepare(riic->clk);
+-		return -EINVAL;
+-	}
++	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
++	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
++	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
+ 
+ 	writeb(0, riic->base + RIIC_ICSER);
+ 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
+@@ -351,11 +397,10 @@ static struct riic_irq_desc riic_irqs[] = {
+ 
+ static int riic_i2c_probe(struct platform_device *pdev)
+ {
+-	struct device_node *np = pdev->dev.of_node;
+ 	struct riic_dev *riic;
+ 	struct i2c_adapter *adap;
+ 	struct resource *res;
+-	u32 bus_rate = 0;
++	struct i2c_timings i2c_t;
+ 	int i, ret;
+ 
+ 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
+@@ -396,8 +441,9 @@ static int riic_i2c_probe(struct platform_device *pdev)
+ 
+ 	init_completion(&riic->msg_done);
+ 
+-	of_property_read_u32(np, "clock-frequency", &bus_rate);
+-	ret = riic_init_hw(riic, bus_rate);
++	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
++
++	ret = riic_init_hw(riic, &i2c_t);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -408,7 +454,8 @@ static int riic_i2c_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, riic);
+ 
+-	dev_info(&pdev->dev, "registered with %dHz bus speed\n", bus_rate);
++	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
++		 i2c_t.bus_freq_hz);
+ 	return 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0091-i2c-sh_mobile-Use-of_device_get_match_data-helper.patch b/patches/0091-i2c-sh_mobile-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..b9dfb2570907a7
--- /dev/null
+++ b/patches/0091-i2c-sh_mobile-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,47 @@
+From 57dce3e1f66ecd5c5429ea0746cfa7d369a3041b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:17:05 +0200
+Subject: [PATCH 0091/1795] i2c: sh_mobile: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit ad59c5ea7fa88284b68721c08faf15f0e77abc0d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 6f2aaeb7c4fa..c03acdf71397 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -881,7 +881,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	struct sh_mobile_i2c_data *pd;
+ 	struct i2c_adapter *adap;
+ 	struct resource *res;
+-	const struct of_device_id *match;
++	const struct sh_mobile_dt_config *config;
+ 	int ret;
+ 	u32 bus_speed;
+ 
+@@ -913,10 +913,8 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
+ 	pd->clks_per_count = 1;
+ 
+-	match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
+-	if (match) {
+-		const struct sh_mobile_dt_config *config = match->data;
+-
++	config = of_device_get_match_data(&dev->dev);
++	if (config) {
+ 		pd->clks_per_count = config->clks_per_count;
+ 
+ 		if (config->setup)
+-- 
+2.19.0
+
diff --git a/patches/0092-iommu-io-pgtable-arm-Convert-to-IOMMU-API-TLB-sync.patch b/patches/0092-iommu-io-pgtable-arm-Convert-to-IOMMU-API-TLB-sync.patch
new file mode 100644
index 00000000000000..eb948c157dc939
--- /dev/null
+++ b/patches/0092-iommu-io-pgtable-arm-Convert-to-IOMMU-API-TLB-sync.patch
@@ -0,0 +1,182 @@
+From 3f621158aee6b5f054f52a56d58a6824e9fb8723 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Thu, 28 Sep 2017 15:55:01 +0100
+Subject: [PATCH 0092/1795] iommu/io-pgtable-arm: Convert to IOMMU API TLB sync
+
+Now that the core API issues its own post-unmap TLB sync call, push that
+operation out from the io-pgtable-arm internals into the users. For now,
+we leave the invalidation implicit in the unmap operation, since none of
+the current users would benefit much from any change to that.
+
+CC: Magnus Damm <damm+renesas@opensource.se>
+CC: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+(cherry picked from commit 32b124492bdf974f68eaef1bde80dc8058aef002)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/arm-smmu-v3.c    | 10 ++++++++++
+ drivers/iommu/arm-smmu.c       | 20 +++++++++++++++-----
+ drivers/iommu/io-pgtable-arm.c |  7 +------
+ drivers/iommu/ipmmu-vmsa.c     | 10 ++++++++++
+ 4 files changed, 36 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
+index 8f7a3c00b6cf..193f8c860010 100644
+--- a/drivers/iommu/arm-smmu-v3.c
++++ b/drivers/iommu/arm-smmu-v3.c
+@@ -1752,6 +1752,14 @@ arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
+ 	return ops->unmap(ops, iova, size);
+ }
+ 
++static void arm_smmu_iotlb_sync(struct iommu_domain *domain)
++{
++	struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu;
++
++	if (smmu)
++		__arm_smmu_tlb_sync(smmu);
++}
++
+ static phys_addr_t
+ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
+ {
+@@ -1972,6 +1980,8 @@ static struct iommu_ops arm_smmu_ops = {
+ 	.map			= arm_smmu_map,
+ 	.unmap			= arm_smmu_unmap,
+ 	.map_sg			= default_iommu_map_sg,
++	.flush_iotlb_all	= arm_smmu_iotlb_sync,
++	.iotlb_sync		= arm_smmu_iotlb_sync,
+ 	.iova_to_phys		= arm_smmu_iova_to_phys,
+ 	.add_device		= arm_smmu_add_device,
+ 	.remove_device		= arm_smmu_remove_device,
+diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
+index 2c436376f13e..335bcc18b97a 100644
+--- a/drivers/iommu/arm-smmu.c
++++ b/drivers/iommu/arm-smmu.c
+@@ -250,6 +250,7 @@ enum arm_smmu_domain_stage {
+ struct arm_smmu_domain {
+ 	struct arm_smmu_device		*smmu;
+ 	struct io_pgtable_ops		*pgtbl_ops;
++	const struct iommu_gather_ops	*tlb_ops;
+ 	struct arm_smmu_cfg		cfg;
+ 	enum arm_smmu_domain_stage	stage;
+ 	struct mutex			init_mutex; /* Protects smmu pointer */
+@@ -735,7 +736,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
+ 	enum io_pgtable_fmt fmt;
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+-	const struct iommu_gather_ops *tlb_ops;
+ 
+ 	mutex_lock(&smmu_domain->init_mutex);
+ 	if (smmu_domain->smmu)
+@@ -813,7 +813,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
+ 			ias = min(ias, 32UL);
+ 			oas = min(oas, 32UL);
+ 		}
+-		tlb_ops = &arm_smmu_s1_tlb_ops;
++		smmu_domain->tlb_ops = &arm_smmu_s1_tlb_ops;
+ 		break;
+ 	case ARM_SMMU_DOMAIN_NESTED:
+ 		/*
+@@ -833,9 +833,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
+ 			oas = min(oas, 40UL);
+ 		}
+ 		if (smmu->version == ARM_SMMU_V2)
+-			tlb_ops = &arm_smmu_s2_tlb_ops_v2;
++			smmu_domain->tlb_ops = &arm_smmu_s2_tlb_ops_v2;
+ 		else
+-			tlb_ops = &arm_smmu_s2_tlb_ops_v1;
++			smmu_domain->tlb_ops = &arm_smmu_s2_tlb_ops_v1;
+ 		break;
+ 	default:
+ 		ret = -EINVAL;
+@@ -863,7 +863,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
+ 		.pgsize_bitmap	= smmu->pgsize_bitmap,
+ 		.ias		= ias,
+ 		.oas		= oas,
+-		.tlb		= tlb_ops,
++		.tlb		= smmu_domain->tlb_ops,
+ 		.iommu_dev	= smmu->dev,
+ 	};
+ 
+@@ -1259,6 +1259,14 @@ static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
+ 	return ops->unmap(ops, iova, size);
+ }
+ 
++static void arm_smmu_iotlb_sync(struct iommu_domain *domain)
++{
++	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
++
++	if (smmu_domain->tlb_ops)
++		smmu_domain->tlb_ops->tlb_sync(smmu_domain);
++}
++
+ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
+ 					      dma_addr_t iova)
+ {
+@@ -1562,6 +1570,8 @@ static struct iommu_ops arm_smmu_ops = {
+ 	.map			= arm_smmu_map,
+ 	.unmap			= arm_smmu_unmap,
+ 	.map_sg			= default_iommu_map_sg,
++	.flush_iotlb_all	= arm_smmu_iotlb_sync,
++	.iotlb_sync		= arm_smmu_iotlb_sync,
+ 	.iova_to_phys		= arm_smmu_iova_to_phys,
+ 	.add_device		= arm_smmu_add_device,
+ 	.remove_device		= arm_smmu_remove_device,
+diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
+index e8018a308868..51e5c43caed1 100644
+--- a/drivers/iommu/io-pgtable-arm.c
++++ b/drivers/iommu/io-pgtable-arm.c
+@@ -609,7 +609,6 @@ static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
+ static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
+ 			  size_t size)
+ {
+-	size_t unmapped;
+ 	struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ 	arm_lpae_iopte *ptep = data->pgd;
+ 	int lvl = ARM_LPAE_START_LVL(data);
+@@ -617,11 +616,7 @@ static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
+ 	if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
+ 		return 0;
+ 
+-	unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
+-	if (unmapped)
+-		io_pgtable_tlb_sync(&data->iop);
+-
+-	return unmapped;
++	return __arm_lpae_unmap(data, iova, size, lvl, ptep);
+ }
+ 
+ static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 195d6e93ac71..af8140054273 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -619,6 +619,14 @@ static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
+ 	return domain->iop->unmap(domain->iop, iova, size);
+ }
+ 
++static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
++{
++	struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
++
++	if (domain->mmu)
++		ipmmu_tlb_flush_all(domain);
++}
++
+ static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
+ 				      dma_addr_t iova)
+ {
+@@ -876,6 +884,8 @@ static const struct iommu_ops ipmmu_ops = {
+ 	.detach_dev = ipmmu_detach_device,
+ 	.map = ipmmu_map,
+ 	.unmap = ipmmu_unmap,
++	.flush_iotlb_all = ipmmu_iotlb_sync,
++	.iotlb_sync = ipmmu_iotlb_sync,
+ 	.map_sg = default_iommu_map_sg,
+ 	.iova_to_phys = ipmmu_iova_to_phys,
+ 	.add_device = ipmmu_add_device_dma,
+-- 
+2.19.0
+
diff --git a/patches/0093-dt-bindings-iommu-ipmmu-vmsa-Use-generic-node-name.patch b/patches/0093-dt-bindings-iommu-ipmmu-vmsa-Use-generic-node-name.patch
new file mode 100644
index 00000000000000..22680c8c99b040
--- /dev/null
+++ b/patches/0093-dt-bindings-iommu-ipmmu-vmsa-Use-generic-node-name.patch
@@ -0,0 +1,34 @@
+From 7bfb70fd780532b9f9cf256db6d8f01dfb106e2f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:33:08 +0200
+Subject: [PATCH 0093/1795] dt-bindings: iommu: ipmmu-vmsa: Use generic node
+ name
+
+Use the preferred generic node name in the example.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit d67ac3ae3a3ce464b4fec854c4c85407a99e8e2c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+index 3ed027cfca95..857df929a654 100644
+--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
++++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+@@ -53,7 +53,7 @@ Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
+ 		#iommu-cells = <1>;
+ 	};
+ 
+-	vsp1@fe928000 {
++	vsp@fe928000 {
+ 		...
+ 		iommus = <&ipmmu_mx 13>;
+ 		...
+-- 
+2.19.0
+
diff --git a/patches/0094-iommu-ipmmu-vmsa-Fix-return-value-check-in-ipmmu_fin.patch b/patches/0094-iommu-ipmmu-vmsa-Fix-return-value-check-in-ipmmu_fin.patch
new file mode 100644
index 00000000000000..d480ccbabdf1b5
--- /dev/null
+++ b/patches/0094-iommu-ipmmu-vmsa-Fix-return-value-check-in-ipmmu_fin.patch
@@ -0,0 +1,36 @@
+From 3c12fd8faabdd37bb5ce9f1b475f86b88e37d268 Mon Sep 17 00:00:00 2001
+From: "weiyongjun (A)" <weiyongjun1@huawei.com>
+Date: Tue, 17 Oct 2017 12:11:22 +0000
+Subject: [PATCH 0094/1795] iommu/ipmmu-vmsa: Fix return value check in
+ ipmmu_find_group_dma()
+
+In case of error, the function iommu_group_get() returns NULL pointer
+not ERR_PTR(). The IS_ERR() test in the return value check should be
+replaced with NULL test.
+
+Fixes: 3ae47292024f ("iommu/ipmmu-vmsa: Add new IOMMU_DOMAIN_DMA ops")
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 105a004e2187609a74f75d55fd0f9a054b49d60a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index af8140054273..00e88a88ee3a 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -871,7 +871,7 @@ static struct iommu_group *ipmmu_find_group_dma(struct device *dev)
+ 	sibling = ipmmu_find_sibling_device(dev);
+ 	if (sibling)
+ 		group = iommu_group_get(sibling);
+-	if (!sibling || IS_ERR(group))
++	if (!sibling || !group)
+ 		group = generic_device_group(dev);
+ 
+ 	return group;
+-- 
+2.19.0
+
diff --git a/patches/0095-iommu-ipmmu-vmsa-Unify-domain-alloc-free.patch b/patches/0095-iommu-ipmmu-vmsa-Unify-domain-alloc-free.patch
new file mode 100644
index 00000000000000..422371309c61a5
--- /dev/null
+++ b/patches/0095-iommu-ipmmu-vmsa-Unify-domain-alloc-free.patch
@@ -0,0 +1,131 @@
+From d8005d5db3a8438883a970ac10b651cd269147b7 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Fri, 13 Oct 2017 19:23:39 +0100
+Subject: [PATCH 0095/1795] iommu/ipmmu-vmsa: Unify domain alloc/free
+
+We have two implementations for ipmmu_ops->alloc depending on
+CONFIG_IOMMU_DMA, the difference being whether they accept the
+IOMMU_DOMAIN_DMA type or not. However, iommu_dma_get_cookie() is
+guaranteed to return an error when !CONFIG_IOMMU_DMA, so if
+ipmmu_domain_alloc_dma() was actually checking and handling the return
+value correctly, it would behave the same as ipmmu_domain_alloc()
+anyway.
+
+Similarly for freeing; iommu_put_dma_cookie() is robust by design.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 1c7e7c0278df968221a5edb1a293423e13b13814)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 65 ++++++++++++++------------------------
+ 1 file changed, 24 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 00e88a88ee3a..37154075c00a 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -528,6 +528,27 @@ static struct iommu_domain *__ipmmu_domain_alloc(unsigned type)
+ 	return &domain->io_domain;
+ }
+ 
++static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
++{
++	struct iommu_domain *io_domain = NULL;
++
++	switch (type) {
++	case IOMMU_DOMAIN_UNMANAGED:
++		io_domain = __ipmmu_domain_alloc(type);
++		break;
++
++	case IOMMU_DOMAIN_DMA:
++		io_domain = __ipmmu_domain_alloc(type);
++		if (io_domain && iommu_get_dma_cookie(io_domain)) {
++			kfree(io_domain);
++			io_domain = NULL;
++		}
++		break;
++	}
++
++	return io_domain;
++}
++
+ static void ipmmu_domain_free(struct iommu_domain *io_domain)
+ {
+ 	struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
+@@ -536,6 +557,7 @@ static void ipmmu_domain_free(struct iommu_domain *io_domain)
+ 	 * Free the domain resources. We assume that all devices have already
+ 	 * been detached.
+ 	 */
++	iommu_put_dma_cookie(io_domain);
+ 	ipmmu_domain_destroy_context(domain);
+ 	free_io_pgtable_ops(domain->iop);
+ 	kfree(domain);
+@@ -671,14 +693,6 @@ static int ipmmu_of_xlate(struct device *dev,
+ 
+ #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+ 
+-static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
+-{
+-	if (type != IOMMU_DOMAIN_UNMANAGED)
+-		return NULL;
+-
+-	return __ipmmu_domain_alloc(type);
+-}
+-
+ static int ipmmu_add_device(struct device *dev)
+ {
+ 	struct ipmmu_vmsa_device *mmu = NULL;
+@@ -779,37 +793,6 @@ static const struct iommu_ops ipmmu_ops = {
+ static DEFINE_SPINLOCK(ipmmu_slave_devices_lock);
+ static LIST_HEAD(ipmmu_slave_devices);
+ 
+-static struct iommu_domain *ipmmu_domain_alloc_dma(unsigned type)
+-{
+-	struct iommu_domain *io_domain = NULL;
+-
+-	switch (type) {
+-	case IOMMU_DOMAIN_UNMANAGED:
+-		io_domain = __ipmmu_domain_alloc(type);
+-		break;
+-
+-	case IOMMU_DOMAIN_DMA:
+-		io_domain = __ipmmu_domain_alloc(type);
+-		if (io_domain)
+-			iommu_get_dma_cookie(io_domain);
+-		break;
+-	}
+-
+-	return io_domain;
+-}
+-
+-static void ipmmu_domain_free_dma(struct iommu_domain *io_domain)
+-{
+-	switch (io_domain->type) {
+-	case IOMMU_DOMAIN_DMA:
+-		iommu_put_dma_cookie(io_domain);
+-		/* fall-through */
+-	default:
+-		ipmmu_domain_free(io_domain);
+-		break;
+-	}
+-}
+-
+ static int ipmmu_add_device_dma(struct device *dev)
+ {
+ 	struct iommu_group *group;
+@@ -878,8 +861,8 @@ static struct iommu_group *ipmmu_find_group_dma(struct device *dev)
+ }
+ 
+ static const struct iommu_ops ipmmu_ops = {
+-	.domain_alloc = ipmmu_domain_alloc_dma,
+-	.domain_free = ipmmu_domain_free_dma,
++	.domain_alloc = ipmmu_domain_alloc,
++	.domain_free = ipmmu_domain_free,
+ 	.attach_dev = ipmmu_attach_device,
+ 	.detach_dev = ipmmu_detach_device,
+ 	.map = ipmmu_map,
+-- 
+2.19.0
+
diff --git a/patches/0096-iommu-ipmmu-vmsa-Simplify-group-allocation.patch b/patches/0096-iommu-ipmmu-vmsa-Simplify-group-allocation.patch
new file mode 100644
index 00000000000000..5ce044fdb0a6cb
--- /dev/null
+++ b/patches/0096-iommu-ipmmu-vmsa-Simplify-group-allocation.patch
@@ -0,0 +1,135 @@
+From e6378f334e411675a80aaa4cbea7ee5c9309d1a9 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Fri, 13 Oct 2017 19:23:40 +0100
+Subject: [PATCH 0096/1795] iommu/ipmmu-vmsa: Simplify group allocation
+
+We go through quite the merry dance in order to find masters behind the
+same IPMMU instance, so that we can ensure they are grouped together.
+None of which is really necessary, since the master's private data
+already points to the particular IPMMU it is associated with, and that
+IPMMU instance data is the perfect place to keep track of a per-instance
+group directly.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit b354c73edc7eb8d6ee643866e9e4de7842213b06)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 53 +++++++-------------------------------
+ 1 file changed, 9 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 37154075c00a..6e6a86f3c375 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -43,6 +43,7 @@ struct ipmmu_vmsa_device {
+ 	DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
+ 	struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
+ 
++	struct iommu_group *group;
+ 	struct dma_iommu_mapping *mapping;
+ };
+ 
+@@ -59,8 +60,6 @@ struct ipmmu_vmsa_domain {
+ 
+ struct ipmmu_vmsa_iommu_priv {
+ 	struct ipmmu_vmsa_device *mmu;
+-	struct device *dev;
+-	struct list_head list;
+ };
+ 
+ static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
+@@ -674,7 +673,6 @@ static int ipmmu_init_platform_device(struct device *dev,
+ 		return -ENOMEM;
+ 
+ 	priv->mmu = platform_get_drvdata(ipmmu_pdev);
+-	priv->dev = dev;
+ 	dev->iommu_fwspec->iommu_priv = priv;
+ 	return 0;
+ }
+@@ -790,9 +788,6 @@ static const struct iommu_ops ipmmu_ops = {
+ 
+ #ifdef CONFIG_IOMMU_DMA
+ 
+-static DEFINE_SPINLOCK(ipmmu_slave_devices_lock);
+-static LIST_HEAD(ipmmu_slave_devices);
+-
+ static int ipmmu_add_device_dma(struct device *dev)
+ {
+ 	struct iommu_group *group;
+@@ -807,55 +802,25 @@ static int ipmmu_add_device_dma(struct device *dev)
+ 	if (IS_ERR(group))
+ 		return PTR_ERR(group);
+ 
+-	spin_lock(&ipmmu_slave_devices_lock);
+-	list_add(&to_priv(dev)->list, &ipmmu_slave_devices);
+-	spin_unlock(&ipmmu_slave_devices_lock);
+ 	return 0;
+ }
+ 
+ static void ipmmu_remove_device_dma(struct device *dev)
+ {
+-	struct ipmmu_vmsa_iommu_priv *priv = to_priv(dev);
+-
+-	spin_lock(&ipmmu_slave_devices_lock);
+-	list_del(&priv->list);
+-	spin_unlock(&ipmmu_slave_devices_lock);
+-
+ 	iommu_group_remove_device(dev);
+ }
+ 
+-static struct device *ipmmu_find_sibling_device(struct device *dev)
++static struct iommu_group *ipmmu_find_group(struct device *dev)
+ {
+ 	struct ipmmu_vmsa_iommu_priv *priv = to_priv(dev);
+-	struct ipmmu_vmsa_iommu_priv *sibling_priv = NULL;
+-	bool found = false;
+-
+-	spin_lock(&ipmmu_slave_devices_lock);
+-
+-	list_for_each_entry(sibling_priv, &ipmmu_slave_devices, list) {
+-		if (priv == sibling_priv)
+-			continue;
+-		if (sibling_priv->mmu == priv->mmu) {
+-			found = true;
+-			break;
+-		}
+-	}
+-
+-	spin_unlock(&ipmmu_slave_devices_lock);
+-
+-	return found ? sibling_priv->dev : NULL;
+-}
+-
+-static struct iommu_group *ipmmu_find_group_dma(struct device *dev)
+-{
+ 	struct iommu_group *group;
+-	struct device *sibling;
+ 
+-	sibling = ipmmu_find_sibling_device(dev);
+-	if (sibling)
+-		group = iommu_group_get(sibling);
+-	if (!sibling || !group)
+-		group = generic_device_group(dev);
++	if (priv->mmu->group)
++		return iommu_group_ref_get(priv->mmu->group);
++
++	group = iommu_group_alloc();
++	if (!IS_ERR(group))
++		priv->mmu->group = group;
+ 
+ 	return group;
+ }
+@@ -873,7 +838,7 @@ static const struct iommu_ops ipmmu_ops = {
+ 	.iova_to_phys = ipmmu_iova_to_phys,
+ 	.add_device = ipmmu_add_device_dma,
+ 	.remove_device = ipmmu_remove_device_dma,
+-	.device_group = ipmmu_find_group_dma,
++	.device_group = ipmmu_find_group,
+ 	.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
+ 	.of_xlate = ipmmu_of_xlate,
+ };
+-- 
+2.19.0
+
diff --git a/patches/0097-iommu-ipmmu-vmsa-Clean-up-struct-ipmmu_vmsa_iommu_pr.patch b/patches/0097-iommu-ipmmu-vmsa-Clean-up-struct-ipmmu_vmsa_iommu_pr.patch
new file mode 100644
index 00000000000000..dbac6fc9a00a7b
--- /dev/null
+++ b/patches/0097-iommu-ipmmu-vmsa-Clean-up-struct-ipmmu_vmsa_iommu_pr.patch
@@ -0,0 +1,145 @@
+From 90d20f74d386ac9881000b6f9d7e2a3088ca41e6 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Fri, 13 Oct 2017 19:23:41 +0100
+Subject: [PATCH 0097/1795] iommu/ipmmu-vmsa: Clean up struct
+ ipmmu_vmsa_iommu_priv
+
+Now that the IPMMU instance pointer is the only thing remaining in the
+private data structure, we no longer need the extra level of indirection
+and can simply stash that directlty in the fwspec.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit e4efe4a9a2ace658a36b5a4f515c11d4d36400a8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 36 ++++++++++++------------------------
+ 1 file changed, 12 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 6e6a86f3c375..fd05a5f5a47e 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -58,16 +58,12 @@ struct ipmmu_vmsa_domain {
+ 	spinlock_t lock;			/* Protects mappings */
+ };
+ 
+-struct ipmmu_vmsa_iommu_priv {
+-	struct ipmmu_vmsa_device *mmu;
+-};
+-
+ static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
+ {
+ 	return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
+ }
+ 
+-static struct ipmmu_vmsa_iommu_priv *to_priv(struct device *dev)
++static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
+ {
+ 	return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL;
+ }
+@@ -565,15 +561,14 @@ static void ipmmu_domain_free(struct iommu_domain *io_domain)
+ static int ipmmu_attach_device(struct iommu_domain *io_domain,
+ 			       struct device *dev)
+ {
+-	struct ipmmu_vmsa_iommu_priv *priv = to_priv(dev);
+ 	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
+-	struct ipmmu_vmsa_device *mmu = priv->mmu;
++	struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
+ 	struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
+ 	unsigned long flags;
+ 	unsigned int i;
+ 	int ret = 0;
+ 
+-	if (!priv || !priv->mmu) {
++	if (!mmu) {
+ 		dev_err(dev, "Cannot attach to IPMMU\n");
+ 		return -ENXIO;
+ 	}
+@@ -662,18 +657,12 @@ static int ipmmu_init_platform_device(struct device *dev,
+ 				      struct of_phandle_args *args)
+ {
+ 	struct platform_device *ipmmu_pdev;
+-	struct ipmmu_vmsa_iommu_priv *priv;
+ 
+ 	ipmmu_pdev = of_find_device_by_node(args->np);
+ 	if (!ipmmu_pdev)
+ 		return -ENODEV;
+ 
+-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	priv->mmu = platform_get_drvdata(ipmmu_pdev);
+-	dev->iommu_fwspec->iommu_priv = priv;
++	dev->iommu_fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev);
+ 	return 0;
+ }
+ 
+@@ -683,7 +672,7 @@ static int ipmmu_of_xlate(struct device *dev,
+ 	iommu_fwspec_add_ids(dev, spec->args, 1);
+ 
+ 	/* Initialize once - xlate() will call multiple times */
+-	if (to_priv(dev))
++	if (to_ipmmu(dev))
+ 		return 0;
+ 
+ 	return ipmmu_init_platform_device(dev, spec);
+@@ -693,14 +682,14 @@ static int ipmmu_of_xlate(struct device *dev,
+ 
+ static int ipmmu_add_device(struct device *dev)
+ {
+-	struct ipmmu_vmsa_device *mmu = NULL;
++	struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
+ 	struct iommu_group *group;
+ 	int ret;
+ 
+ 	/*
+ 	 * Only let through devices that have been verified in xlate()
+ 	 */
+-	if (!to_priv(dev))
++	if (!mmu)
+ 		return -ENODEV;
+ 
+ 	/* Create a device group and add the device to it. */
+@@ -729,7 +718,6 @@ static int ipmmu_add_device(struct device *dev)
+ 	 * - Make the mapping size configurable ? We currently use a 2GB mapping
+ 	 *   at a 1GB offset to ensure that NULL VAs will fault.
+ 	 */
+-	mmu = to_priv(dev)->mmu;
+ 	if (!mmu->mapping) {
+ 		struct dma_iommu_mapping *mapping;
+ 
+@@ -795,7 +783,7 @@ static int ipmmu_add_device_dma(struct device *dev)
+ 	/*
+ 	 * Only let through devices that have been verified in xlate()
+ 	 */
+-	if (!to_priv(dev))
++	if (!to_ipmmu(dev))
+ 		return -ENODEV;
+ 
+ 	group = iommu_group_get_for_dev(dev);
+@@ -812,15 +800,15 @@ static void ipmmu_remove_device_dma(struct device *dev)
+ 
+ static struct iommu_group *ipmmu_find_group(struct device *dev)
+ {
+-	struct ipmmu_vmsa_iommu_priv *priv = to_priv(dev);
++	struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
+ 	struct iommu_group *group;
+ 
+-	if (priv->mmu->group)
+-		return iommu_group_ref_get(priv->mmu->group);
++	if (mmu->group)
++		return iommu_group_ref_get(mmu->group);
+ 
+ 	group = iommu_group_alloc();
+ 	if (!IS_ERR(group))
+-		priv->mmu->group = group;
++		mmu->group = group;
+ 
+ 	return group;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0098-iommu-ipmmu-vmsa-Unify-ipmmu_ops.patch b/patches/0098-iommu-ipmmu-vmsa-Unify-ipmmu_ops.patch
new file mode 100644
index 00000000000000..4a3c1b0a089780
--- /dev/null
+++ b/patches/0098-iommu-ipmmu-vmsa-Unify-ipmmu_ops.patch
@@ -0,0 +1,173 @@
+From fb81bdcd8c1d96edb0bce62324c06dc90aa36b36 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Fri, 13 Oct 2017 19:23:42 +0100
+Subject: [PATCH 0098/1795] iommu/ipmmu-vmsa: Unify ipmmu_ops
+
+The remaining difference between the ARM-specific and iommu-dma ops is
+in the {add,remove}_device implementations, but even those have some
+overlap and duplication. By stubbing out the few arm_iommu_*() calls,
+we can get rid of the rest of the inline #ifdeffery to both simplify the
+code and improve build coverage.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 49c875f030523d676a508e53f7dc3e592e9439d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 69 +++++++++++---------------------------
+ 1 file changed, 19 insertions(+), 50 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index fd05a5f5a47e..f6d2e8e650be 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -27,6 +27,11 @@
+ #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+ #include <asm/dma-iommu.h>
+ #include <asm/pgalloc.h>
++#else
++#define arm_iommu_create_mapping(...)	NULL
++#define arm_iommu_attach_device(...)	-ENODEV
++#define arm_iommu_release_mapping(...)	do {} while (0)
++#define arm_iommu_detach_device(...)	do {} while (0)
+ #endif
+ 
+ #include "io-pgtable.h"
+@@ -678,26 +683,17 @@ static int ipmmu_of_xlate(struct device *dev,
+ 	return ipmmu_init_platform_device(dev, spec);
+ }
+ 
+-#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+-
+-static int ipmmu_add_device(struct device *dev)
++static int ipmmu_init_arm_mapping(struct device *dev)
+ {
+ 	struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
+ 	struct iommu_group *group;
+ 	int ret;
+ 
+-	/*
+-	 * Only let through devices that have been verified in xlate()
+-	 */
+-	if (!mmu)
+-		return -ENODEV;
+-
+ 	/* Create a device group and add the device to it. */
+ 	group = iommu_group_alloc();
+ 	if (IS_ERR(group)) {
+ 		dev_err(dev, "Failed to allocate IOMMU group\n");
+-		ret = PTR_ERR(group);
+-		goto error;
++		return PTR_ERR(group);
+ 	}
+ 
+ 	ret = iommu_group_add_device(group, dev);
+@@ -705,8 +701,7 @@ static int ipmmu_add_device(struct device *dev)
+ 
+ 	if (ret < 0) {
+ 		dev_err(dev, "Failed to add device to IPMMU group\n");
+-		group = NULL;
+-		goto error;
++		return ret;
+ 	}
+ 
+ 	/*
+@@ -742,41 +737,14 @@ static int ipmmu_add_device(struct device *dev)
+ 	return 0;
+ 
+ error:
+-	if (mmu)
++	iommu_group_remove_device(dev);
++	if (mmu->mapping)
+ 		arm_iommu_release_mapping(mmu->mapping);
+ 
+-	if (!IS_ERR_OR_NULL(group))
+-		iommu_group_remove_device(dev);
+-
+ 	return ret;
+ }
+ 
+-static void ipmmu_remove_device(struct device *dev)
+-{
+-	arm_iommu_detach_device(dev);
+-	iommu_group_remove_device(dev);
+-}
+-
+-static const struct iommu_ops ipmmu_ops = {
+-	.domain_alloc = ipmmu_domain_alloc,
+-	.domain_free = ipmmu_domain_free,
+-	.attach_dev = ipmmu_attach_device,
+-	.detach_dev = ipmmu_detach_device,
+-	.map = ipmmu_map,
+-	.unmap = ipmmu_unmap,
+-	.map_sg = default_iommu_map_sg,
+-	.iova_to_phys = ipmmu_iova_to_phys,
+-	.add_device = ipmmu_add_device,
+-	.remove_device = ipmmu_remove_device,
+-	.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
+-	.of_xlate = ipmmu_of_xlate,
+-};
+-
+-#endif /* !CONFIG_ARM && CONFIG_IOMMU_DMA */
+-
+-#ifdef CONFIG_IOMMU_DMA
+-
+-static int ipmmu_add_device_dma(struct device *dev)
++static int ipmmu_add_device(struct device *dev)
+ {
+ 	struct iommu_group *group;
+ 
+@@ -786,15 +754,20 @@ static int ipmmu_add_device_dma(struct device *dev)
+ 	if (!to_ipmmu(dev))
+ 		return -ENODEV;
+ 
++	if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
++		return ipmmu_init_arm_mapping(dev);
++
+ 	group = iommu_group_get_for_dev(dev);
+ 	if (IS_ERR(group))
+ 		return PTR_ERR(group);
+ 
++	iommu_group_put(group);
+ 	return 0;
+ }
+ 
+-static void ipmmu_remove_device_dma(struct device *dev)
++static void ipmmu_remove_device(struct device *dev)
+ {
++	arm_iommu_detach_device(dev);
+ 	iommu_group_remove_device(dev);
+ }
+ 
+@@ -824,15 +797,13 @@ static const struct iommu_ops ipmmu_ops = {
+ 	.iotlb_sync = ipmmu_iotlb_sync,
+ 	.map_sg = default_iommu_map_sg,
+ 	.iova_to_phys = ipmmu_iova_to_phys,
+-	.add_device = ipmmu_add_device_dma,
+-	.remove_device = ipmmu_remove_device_dma,
++	.add_device = ipmmu_add_device,
++	.remove_device = ipmmu_remove_device,
+ 	.device_group = ipmmu_find_group,
+ 	.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
+ 	.of_xlate = ipmmu_of_xlate,
+ };
+ 
+-#endif /* CONFIG_IOMMU_DMA */
+-
+ /* -----------------------------------------------------------------------------
+  * Probe/remove and init
+  */
+@@ -929,9 +900,7 @@ static int ipmmu_remove(struct platform_device *pdev)
+ 	iommu_device_sysfs_remove(&mmu->iommu);
+ 	iommu_device_unregister(&mmu->iommu);
+ 
+-#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+ 	arm_iommu_release_mapping(mmu->mapping);
+-#endif
+ 
+ 	ipmmu_device_reset(mmu);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0099-iommu-ipmmu-vmsa-Introduce-features-break-out-alias.patch b/patches/0099-iommu-ipmmu-vmsa-Introduce-features-break-out-alias.patch
new file mode 100644
index 00000000000000..63521f8834703f
--- /dev/null
+++ b/patches/0099-iommu-ipmmu-vmsa-Introduce-features-break-out-alias.patch
@@ -0,0 +1,105 @@
+From 5a02eb587adad058b3538ff9c9464a972a14cc92 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:29:25 +0900
+Subject: [PATCH 0099/1795] iommu/ipmmu-vmsa: Introduce features, break out
+ alias
+
+Introduce struct ipmmu_features to track various hardware
+and software implementation changes inside the driver for
+different kinds of IPMMU hardware. Add use_ns_alias_offset
+as a first example of a feature to control if the secure
+register bank offset should be used or not.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 33f3ac9b511612153bae1d328b0c84c0367cd08d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 31 ++++++++++++++++++++++++-------
+ 1 file changed, 24 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index f6d2e8e650be..5ce7879cb58d 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -19,6 +19,7 @@
+ #include <linux/iommu.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/sizes.h>
+@@ -38,11 +39,15 @@
+ 
+ #define IPMMU_CTX_MAX 1
+ 
++struct ipmmu_features {
++	bool use_ns_alias_offset;
++};
++
+ struct ipmmu_vmsa_device {
+ 	struct device *dev;
+ 	void __iomem *base;
+ 	struct iommu_device iommu;
+-
++	const struct ipmmu_features *features;
+ 	unsigned int num_utlbs;
+ 	spinlock_t lock;			/* Protects ctx and domains[] */
+ 	DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
+@@ -817,6 +822,21 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
+ 		ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
+ }
+ 
++static const struct ipmmu_features ipmmu_features_default = {
++	.use_ns_alias_offset = true,
++};
++
++static const struct of_device_id ipmmu_of_ids[] = {
++	{
++		.compatible = "renesas,ipmmu-vmsa",
++		.data = &ipmmu_features_default,
++	}, {
++		/* Terminator */
++	},
++};
++
++MODULE_DEVICE_TABLE(of, ipmmu_of_ids);
++
+ static int ipmmu_probe(struct platform_device *pdev)
+ {
+ 	struct ipmmu_vmsa_device *mmu;
+@@ -834,6 +854,7 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 	mmu->num_utlbs = 32;
+ 	spin_lock_init(&mmu->lock);
+ 	bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
++	mmu->features = of_device_get_match_data(&pdev->dev);
+ 
+ 	/* Map I/O memory and request IRQ. */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -853,7 +874,8 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 	 * Offset the registers base unconditionally to point to the non-secure
+ 	 * alias space for now.
+ 	 */
+-	mmu->base += IM_NS_ALIAS_OFFSET;
++	if (mmu->features->use_ns_alias_offset)
++		mmu->base += IM_NS_ALIAS_OFFSET;
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0) {
+@@ -907,11 +929,6 @@ static int ipmmu_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
+-static const struct of_device_id ipmmu_of_ids[] = {
+-	{ .compatible = "renesas,ipmmu-vmsa", },
+-	{ }
+-};
+-
+ static struct platform_driver ipmmu_driver = {
+ 	.driver = {
+ 		.name = "ipmmu-vmsa",
+-- 
+2.19.0
+
diff --git a/patches/0100-iommu-ipmmu-vmsa-Add-optional-root-device-feature.patch b/patches/0100-iommu-ipmmu-vmsa-Add-optional-root-device-feature.patch
new file mode 100644
index 00000000000000..d0fe7fe11169ba
--- /dev/null
+++ b/patches/0100-iommu-ipmmu-vmsa-Add-optional-root-device-feature.patch
@@ -0,0 +1,189 @@
+From 943e6dd529212c6868cdb032f982ab824e6aceab Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:29:36 +0900
+Subject: [PATCH 0100/1795] iommu/ipmmu-vmsa: Add optional root device feature
+
+Add root device handling to the IPMMU driver by allowing certain
+DT compat strings to enable has_cache_leaf_nodes that in turn will
+support both root devices with interrupts and leaf devices that
+face the actual IPMMU consumer devices.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit fd5140e29a59e04a6c3e8cc56536bda3e60bbf49)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 90 +++++++++++++++++++++++++++++++-------
+ 1 file changed, 73 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 5ce7879cb58d..5db853b92d3b 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -41,12 +41,14 @@
+ 
+ struct ipmmu_features {
+ 	bool use_ns_alias_offset;
++	bool has_cache_leaf_nodes;
+ };
+ 
+ struct ipmmu_vmsa_device {
+ 	struct device *dev;
+ 	void __iomem *base;
+ 	struct iommu_device iommu;
++	struct ipmmu_vmsa_device *root;
+ 	const struct ipmmu_features *features;
+ 	unsigned int num_utlbs;
+ 	spinlock_t lock;			/* Protects ctx and domains[] */
+@@ -198,6 +200,36 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
+ #define IMUASID_ASID0_MASK		(0xff << 0)
+ #define IMUASID_ASID0_SHIFT		0
+ 
++/* -----------------------------------------------------------------------------
++ * Root device handling
++ */
++
++static struct platform_driver ipmmu_driver;
++
++static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
++{
++	return mmu->root == mmu;
++}
++
++static int __ipmmu_check_device(struct device *dev, void *data)
++{
++	struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
++	struct ipmmu_vmsa_device **rootp = data;
++
++	if (ipmmu_is_root(mmu))
++		*rootp = mmu;
++
++	return 0;
++}
++
++static struct ipmmu_vmsa_device *ipmmu_find_root(void)
++{
++	struct ipmmu_vmsa_device *root = NULL;
++
++	return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
++				      __ipmmu_check_device) == 0 ? root : NULL;
++}
++
+ /* -----------------------------------------------------------------------------
+  * Read/Write Access
+  */
+@@ -215,13 +247,15 @@ static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
+ 
+ static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
+ {
+-	return ipmmu_read(domain->mmu, domain->context_id * IM_CTX_SIZE + reg);
++	return ipmmu_read(domain->mmu->root,
++			  domain->context_id * IM_CTX_SIZE + reg);
+ }
+ 
+ static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
+ 			    u32 data)
+ {
+-	ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, data);
++	ipmmu_write(domain->mmu->root,
++		    domain->context_id * IM_CTX_SIZE + reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -369,12 +403,12 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 	 * TODO: Add support for coherent walk through CCI with DVM and remove
+ 	 * cache handling. For now, delegate it to the io-pgtable code.
+ 	 */
+-	domain->cfg.iommu_dev = domain->mmu->dev;
++	domain->cfg.iommu_dev = domain->mmu->root->dev;
+ 
+ 	/*
+ 	 * Find an unused context.
+ 	 */
+-	ret = ipmmu_domain_allocate_context(domain->mmu, domain);
++	ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
+ 	if (ret == IPMMU_CTX_MAX)
+ 		return -EBUSY;
+ 
+@@ -383,7 +417,8 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 	domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
+ 					   domain);
+ 	if (!domain->iop) {
+-		ipmmu_domain_free_context(domain->mmu, domain->context_id);
++		ipmmu_domain_free_context(domain->mmu->root,
++					  domain->context_id);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -437,7 +472,7 @@ static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
+ 	 */
+ 	ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
+ 	ipmmu_tlb_sync(domain);
+-	ipmmu_domain_free_context(domain->mmu, domain->context_id);
++	ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -824,6 +859,7 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
+ 
+ static const struct ipmmu_features ipmmu_features_default = {
+ 	.use_ns_alias_offset = true,
++	.has_cache_leaf_nodes = false,
+ };
+ 
+ static const struct of_device_id ipmmu_of_ids[] = {
+@@ -878,19 +914,39 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 		mmu->base += IM_NS_ALIAS_OFFSET;
+ 
+ 	irq = platform_get_irq(pdev, 0);
+-	if (irq < 0) {
+-		dev_err(&pdev->dev, "no IRQ found\n");
+-		return irq;
+-	}
+ 
+-	ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
+-			       dev_name(&pdev->dev), mmu);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
+-		return ret;
+-	}
++	/*
++	 * Determine if this IPMMU instance is a root device by checking for
++	 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
++	 */
++	if (!mmu->features->has_cache_leaf_nodes ||
++	    !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
++		mmu->root = mmu;
++	else
++		mmu->root = ipmmu_find_root();
+ 
+-	ipmmu_device_reset(mmu);
++	/*
++	 * Wait until the root device has been registered for sure.
++	 */
++	if (!mmu->root)
++		return -EPROBE_DEFER;
++
++	/* Root devices have mandatory IRQs */
++	if (ipmmu_is_root(mmu)) {
++		if (irq < 0) {
++			dev_err(&pdev->dev, "no IRQ found\n");
++			return irq;
++		}
++
++		ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
++				       dev_name(&pdev->dev), mmu);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
++			return ret;
++		}
++
++		ipmmu_device_reset(mmu);
++	}
+ 
+ 	ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
+ 				     dev_name(&pdev->dev));
+-- 
+2.19.0
+
diff --git a/patches/0101-iommu-ipmmu-vmsa-Enable-multi-context-support.patch b/patches/0101-iommu-ipmmu-vmsa-Enable-multi-context-support.patch
new file mode 100644
index 00000000000000..3cd6fa35dfe64c
--- /dev/null
+++ b/patches/0101-iommu-ipmmu-vmsa-Enable-multi-context-support.patch
@@ -0,0 +1,125 @@
+From 8eaee8d0fcde4bd505126f104b43545dea09b9f3 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:29:46 +0900
+Subject: [PATCH 0101/1795] iommu/ipmmu-vmsa: Enable multi context support
+
+Add support for up to 8 contexts. Each context is mapped to one
+domain. One domain is assigned one or more slave devices. Contexts
+are allocated dynamically and slave devices are grouped together
+based on which IPMMU device they are connected to. This makes slave
+devices tied to the same IPMMU device share the same IOVA space.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 5fd163416fb7b6592521c39f867d5ae6360e7924)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 30 ++++++++++++++++++++++--------
+ 1 file changed, 22 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 5db853b92d3b..c70efd80f740 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -37,11 +37,12 @@
+ 
+ #include "io-pgtable.h"
+ 
+-#define IPMMU_CTX_MAX 1
++#define IPMMU_CTX_MAX 8
+ 
+ struct ipmmu_features {
+ 	bool use_ns_alias_offset;
+ 	bool has_cache_leaf_nodes;
++	unsigned int number_of_contexts;
+ };
+ 
+ struct ipmmu_vmsa_device {
+@@ -51,6 +52,7 @@ struct ipmmu_vmsa_device {
+ 	struct ipmmu_vmsa_device *root;
+ 	const struct ipmmu_features *features;
+ 	unsigned int num_utlbs;
++	unsigned int num_ctx;
+ 	spinlock_t lock;			/* Protects ctx and domains[] */
+ 	DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
+ 	struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
+@@ -352,11 +354,12 @@ static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
+ 
+ 	spin_lock_irqsave(&mmu->lock, flags);
+ 
+-	ret = find_first_zero_bit(mmu->ctx, IPMMU_CTX_MAX);
+-	if (ret != IPMMU_CTX_MAX) {
++	ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
++	if (ret != mmu->num_ctx) {
+ 		mmu->domains[ret] = domain;
+ 		set_bit(ret, mmu->ctx);
+-	}
++	} else
++		ret = -EBUSY;
+ 
+ 	spin_unlock_irqrestore(&mmu->lock, flags);
+ 
+@@ -409,8 +412,8 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 	 * Find an unused context.
+ 	 */
+ 	ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
+-	if (ret == IPMMU_CTX_MAX)
+-		return -EBUSY;
++	if (ret < 0)
++		return ret;
+ 
+ 	domain->context_id = ret;
+ 
+@@ -539,7 +542,7 @@ static irqreturn_t ipmmu_irq(int irq, void *dev)
+ 	/*
+ 	 * Check interrupts for all active contexts.
+ 	 */
+-	for (i = 0; i < IPMMU_CTX_MAX; i++) {
++	for (i = 0; i < mmu->num_ctx; i++) {
+ 		if (!mmu->domains[i])
+ 			continue;
+ 		if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
+@@ -624,6 +627,13 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain,
+ 		/* The domain hasn't been used yet, initialize it. */
+ 		domain->mmu = mmu;
+ 		ret = ipmmu_domain_init_context(domain);
++		if (ret < 0) {
++			dev_err(dev, "Unable to initialize IPMMU context\n");
++			domain->mmu = NULL;
++		} else {
++			dev_info(dev, "Using IPMMU context %u\n",
++				 domain->context_id);
++		}
+ 	} else if (domain->mmu != mmu) {
+ 		/*
+ 		 * Something is wrong, we can't attach two devices using
+@@ -853,13 +863,14 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
+ 	unsigned int i;
+ 
+ 	/* Disable all contexts. */
+-	for (i = 0; i < 4; ++i)
++	for (i = 0; i < mmu->num_ctx; ++i)
+ 		ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
+ }
+ 
+ static const struct ipmmu_features ipmmu_features_default = {
+ 	.use_ns_alias_offset = true,
+ 	.has_cache_leaf_nodes = false,
++	.number_of_contexts = 1, /* software only tested with one context */
+ };
+ 
+ static const struct of_device_id ipmmu_of_ids[] = {
+@@ -913,6 +924,9 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 	if (mmu->features->use_ns_alias_offset)
+ 		mmu->base += IM_NS_ALIAS_OFFSET;
+ 
++	mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX,
++			     mmu->features->number_of_contexts);
++
+ 	irq = platform_get_irq(pdev, 0);
+ 
+ 	/*
+-- 
+2.19.0
+
diff --git a/patches/0102-iommu-ipmmu-vmsa-Make-use-of-IOMMU_OF_DECLARE.patch b/patches/0102-iommu-ipmmu-vmsa-Make-use-of-IOMMU_OF_DECLARE.patch
new file mode 100644
index 00000000000000..d9e62ea56e6b3c
--- /dev/null
+++ b/patches/0102-iommu-ipmmu-vmsa-Make-use-of-IOMMU_OF_DECLARE.patch
@@ -0,0 +1,114 @@
+From 4e758c6bbbc3ba79dad00069f40b0f99f5c70d19 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:29:57 +0900
+Subject: [PATCH 0102/1795] iommu/ipmmu-vmsa: Make use of IOMMU_OF_DECLARE()
+
+Hook up IOMMU_OF_DECLARE() support in case CONFIG_IOMMU_DMA
+is enabled. The only current supported case for 32-bit ARM
+is disabled, however for 64-bit ARM usage of OF is required.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit cda52fcd999f389c6f24f079910a62e53912d411)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 50 +++++++++++++++++++++++++++++++-------
+ 1 file changed, 41 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index c70efd80f740..9cde61970bb5 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -20,6 +20,7 @@
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/of_iommu.h>
+ #include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/sizes.h>
+@@ -962,17 +963,30 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 		ipmmu_device_reset(mmu);
+ 	}
+ 
+-	ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
+-				     dev_name(&pdev->dev));
+-	if (ret)
+-		return ret;
++	/*
++	 * Register the IPMMU to the IOMMU subsystem in the following cases:
++	 * - R-Car Gen2 IPMMU (all devices registered)
++	 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
++	 */
++	if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
++		ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
++					     dev_name(&pdev->dev));
++		if (ret)
++			return ret;
+ 
+-	iommu_device_set_ops(&mmu->iommu, &ipmmu_ops);
+-	iommu_device_set_fwnode(&mmu->iommu, &pdev->dev.of_node->fwnode);
++		iommu_device_set_ops(&mmu->iommu, &ipmmu_ops);
++		iommu_device_set_fwnode(&mmu->iommu,
++					&pdev->dev.of_node->fwnode);
+ 
+-	ret = iommu_device_register(&mmu->iommu);
+-	if (ret)
+-		return ret;
++		ret = iommu_device_register(&mmu->iommu);
++		if (ret)
++			return ret;
++
++#if defined(CONFIG_IOMMU_DMA)
++		if (!iommu_present(&platform_bus_type))
++			bus_set_iommu(&platform_bus_type, &ipmmu_ops);
++#endif
++	}
+ 
+ 	/*
+ 	 * We can't create the ARM mapping here as it requires the bus to have
+@@ -1010,15 +1024,22 @@ static struct platform_driver ipmmu_driver = {
+ 
+ static int __init ipmmu_init(void)
+ {
++	static bool setup_done;
+ 	int ret;
+ 
++	if (setup_done)
++		return 0;
++
+ 	ret = platform_driver_register(&ipmmu_driver);
+ 	if (ret < 0)
+ 		return ret;
+ 
++#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+ 	if (!iommu_present(&platform_bus_type))
+ 		bus_set_iommu(&platform_bus_type, &ipmmu_ops);
++#endif
+ 
++	setup_done = true;
+ 	return 0;
+ }
+ 
+@@ -1030,6 +1051,17 @@ static void __exit ipmmu_exit(void)
+ subsys_initcall(ipmmu_init);
+ module_exit(ipmmu_exit);
+ 
++#ifdef CONFIG_IOMMU_DMA
++static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np)
++{
++	ipmmu_init();
++	return 0;
++}
++
++IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa",
++		 ipmmu_vmsa_iommu_of_setup);
++#endif
++
+ MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
+ MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
+ MODULE_LICENSE("GPL v2");
+-- 
+2.19.0
+
diff --git a/patches/0103-iommu-ipmmu-vmsa-IPMMU-device-is-40-bit-bus-master.patch b/patches/0103-iommu-ipmmu-vmsa-IPMMU-device-is-40-bit-bus-master.patch
new file mode 100644
index 00000000000000..eee64a88615877
--- /dev/null
+++ b/patches/0103-iommu-ipmmu-vmsa-IPMMU-device-is-40-bit-bus-master.patch
@@ -0,0 +1,34 @@
+From cecfc76f8f5e54e14e51ff99f649acdf75a0056e Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:30:07 +0900
+Subject: [PATCH 0103/1795] iommu/ipmmu-vmsa: IPMMU device is 40-bit bus master
+
+The r8a7795 IPMMU supports 40-bit bus mastering. Both
+the coherent DMA mask and the streaming DMA mask are
+set to unlock the 40-bit address space for coherent
+allocations and streaming operations.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 1c894225bf5b1cdffac0c6ef935b61273203d7d5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 9cde61970bb5..6b74ec62f4b4 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -903,6 +903,7 @@ static int ipmmu_probe(struct platform_device *pdev)
+ 	spin_lock_init(&mmu->lock);
+ 	bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
+ 	mmu->features = of_device_get_match_data(&pdev->dev);
++	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
+ 
+ 	/* Map I/O memory and request IRQ. */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-- 
+2.19.0
+
diff --git a/patches/0104-iommu-ipmmu-vmsa-Write-IMCTR-twice.patch b/patches/0104-iommu-ipmmu-vmsa-Write-IMCTR-twice.patch
new file mode 100644
index 00000000000000..045b9f1093031e
--- /dev/null
+++ b/patches/0104-iommu-ipmmu-vmsa-Write-IMCTR-twice.patch
@@ -0,0 +1,171 @@
+From 76b5706b45a6e41d53cb081f051783df71db9fcb Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:30:18 +0900
+Subject: [PATCH 0104/1795] iommu/ipmmu-vmsa: Write IMCTR twice
+
+Write IMCTR both in the root device and the leaf node.
+
+To allow access of IMCTR introduce the following function:
+ - ipmmu_ctx_write_all()
+
+While at it also rename context functions:
+ - ipmmu_ctx_read() -> ipmmu_ctx_read_root()
+ - ipmmu_ctx_write() -> ipmmu_ctx_write_root()
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit d574893aee991efa67fefa849347c49de5df8108)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 56 ++++++++++++++++++++++++--------------
+ 1 file changed, 35 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 6b74ec62f4b4..7587017972b0 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -248,19 +248,31 @@ static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
+ 	iowrite32(data, mmu->base + offset);
+ }
+ 
+-static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
++static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
++			       unsigned int reg)
+ {
+ 	return ipmmu_read(domain->mmu->root,
+ 			  domain->context_id * IM_CTX_SIZE + reg);
+ }
+ 
+-static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
+-			    u32 data)
++static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
++				 unsigned int reg, u32 data)
+ {
+ 	ipmmu_write(domain->mmu->root,
+ 		    domain->context_id * IM_CTX_SIZE + reg, data);
+ }
+ 
++static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
++				unsigned int reg, u32 data)
++{
++	if (domain->mmu != domain->mmu->root)
++		ipmmu_write(domain->mmu,
++			    domain->context_id * IM_CTX_SIZE + reg, data);
++
++	ipmmu_write(domain->mmu->root,
++		    domain->context_id * IM_CTX_SIZE + reg, data);
++}
++
+ /* -----------------------------------------------------------------------------
+  * TLB and microTLB Management
+  */
+@@ -270,7 +282,7 @@ static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
+ {
+ 	unsigned int count = 0;
+ 
+-	while (ipmmu_ctx_read(domain, IMCTR) & IMCTR_FLUSH) {
++	while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
+ 		cpu_relax();
+ 		if (++count == TLB_LOOP_TIMEOUT) {
+ 			dev_err_ratelimited(domain->mmu->dev,
+@@ -285,9 +297,9 @@ static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
+ {
+ 	u32 reg;
+ 
+-	reg = ipmmu_ctx_read(domain, IMCTR);
++	reg = ipmmu_ctx_read_root(domain, IMCTR);
+ 	reg |= IMCTR_FLUSH;
+-	ipmmu_ctx_write(domain, IMCTR, reg);
++	ipmmu_ctx_write_all(domain, IMCTR, reg);
+ 
+ 	ipmmu_tlb_sync(domain);
+ }
+@@ -428,31 +440,32 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 
+ 	/* TTBR0 */
+ 	ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
+-	ipmmu_ctx_write(domain, IMTTLBR0, ttbr);
+-	ipmmu_ctx_write(domain, IMTTUBR0, ttbr >> 32);
++	ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
++	ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
+ 
+ 	/*
+ 	 * TTBCR
+ 	 * We use long descriptors with inner-shareable WBWA tables and allocate
+ 	 * the whole 32-bit VA space to TTBR0.
+ 	 */
+-	ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE |
+-			IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
+-			IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
++	ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
++			     IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
++			     IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
+ 
+ 	/* MAIR0 */
+-	ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]);
++	ipmmu_ctx_write_root(domain, IMMAIR0,
++			     domain->cfg.arm_lpae_s1_cfg.mair[0]);
+ 
+ 	/* IMBUSCR */
+-	ipmmu_ctx_write(domain, IMBUSCR,
+-			ipmmu_ctx_read(domain, IMBUSCR) &
+-			~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
++	ipmmu_ctx_write_root(domain, IMBUSCR,
++			     ipmmu_ctx_read_root(domain, IMBUSCR) &
++			     ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
+ 
+ 	/*
+ 	 * IMSTR
+ 	 * Clear all interrupt flags.
+ 	 */
+-	ipmmu_ctx_write(domain, IMSTR, ipmmu_ctx_read(domain, IMSTR));
++	ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
+ 
+ 	/*
+ 	 * IMCTR
+@@ -461,7 +474,8 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 	 * software management as we have no use for it. Flush the TLB as
+ 	 * required when modifying the context registers.
+ 	 */
+-	ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
++	ipmmu_ctx_write_all(domain, IMCTR,
++			    IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
+ 
+ 	return 0;
+ }
+@@ -474,7 +488,7 @@ static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
+ 	 *
+ 	 * TODO: Is TLB flush really needed ?
+ 	 */
+-	ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
++	ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
+ 	ipmmu_tlb_sync(domain);
+ 	ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
+ }
+@@ -490,11 +504,11 @@ static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
+ 	u32 status;
+ 	u32 iova;
+ 
+-	status = ipmmu_ctx_read(domain, IMSTR);
++	status = ipmmu_ctx_read_root(domain, IMSTR);
+ 	if (!(status & err_mask))
+ 		return IRQ_NONE;
+ 
+-	iova = ipmmu_ctx_read(domain, IMEAR);
++	iova = ipmmu_ctx_read_root(domain, IMEAR);
+ 
+ 	/*
+ 	 * Clear the error status flags. Unlike traditional interrupt flag
+@@ -502,7 +516,7 @@ static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
+ 	 * seems to require 0. The error address register must be read before,
+ 	 * otherwise its value will be 0.
+ 	 */
+-	ipmmu_ctx_write(domain, IMSTR, 0);
++	ipmmu_ctx_write_root(domain, IMSTR, 0);
+ 
+ 	/* Log fatal errors. */
+ 	if (status & IMSTR_MHIT)
+-- 
+2.19.0
+
diff --git a/patches/0105-iommu-ipmmu-vmsa-Make-IMBUSCTR-setup-optional.patch b/patches/0105-iommu-ipmmu-vmsa-Make-IMBUSCTR-setup-optional.patch
new file mode 100644
index 00000000000000..2609ec0f591d37
--- /dev/null
+++ b/patches/0105-iommu-ipmmu-vmsa-Make-IMBUSCTR-setup-optional.patch
@@ -0,0 +1,54 @@
+From c91b5ab334d8239ff2f760392a0befe6eb32fbb1 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:30:28 +0900
+Subject: [PATCH 0105/1795] iommu/ipmmu-vmsa: Make IMBUSCTR setup optional
+
+Introduce a feature to allow opt-out of setting up
+IMBUSCR. The default case is unchanged.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit f5c858912acd2b17059ebe6f34abac183bdfbf80)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 7587017972b0..49f2c697b108 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -44,6 +44,7 @@ struct ipmmu_features {
+ 	bool use_ns_alias_offset;
+ 	bool has_cache_leaf_nodes;
+ 	unsigned int number_of_contexts;
++	bool setup_imbuscr;
+ };
+ 
+ struct ipmmu_vmsa_device {
+@@ -457,9 +458,10 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 			     domain->cfg.arm_lpae_s1_cfg.mair[0]);
+ 
+ 	/* IMBUSCR */
+-	ipmmu_ctx_write_root(domain, IMBUSCR,
+-			     ipmmu_ctx_read_root(domain, IMBUSCR) &
+-			     ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
++	if (domain->mmu->features->setup_imbuscr)
++		ipmmu_ctx_write_root(domain, IMBUSCR,
++				     ipmmu_ctx_read_root(domain, IMBUSCR) &
++				     ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
+ 
+ 	/*
+ 	 * IMSTR
+@@ -886,6 +888,7 @@ static const struct ipmmu_features ipmmu_features_default = {
+ 	.use_ns_alias_offset = true,
+ 	.has_cache_leaf_nodes = false,
+ 	.number_of_contexts = 1, /* software only tested with one context */
++	.setup_imbuscr = true,
+ };
+ 
+ static const struct of_device_id ipmmu_of_ids[] = {
+-- 
+2.19.0
+
diff --git a/patches/0106-iommu-ipmmu-vmsa-Allow-two-bit-SL0.patch b/patches/0106-iommu-ipmmu-vmsa-Allow-two-bit-SL0.patch
new file mode 100644
index 00000000000000..be2e95bd74b020
--- /dev/null
+++ b/patches/0106-iommu-ipmmu-vmsa-Allow-two-bit-SL0.patch
@@ -0,0 +1,75 @@
+From a80a7e3d2c7510bbf5c4300ddb30eb9604efdd35 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:30:39 +0900
+Subject: [PATCH 0106/1795] iommu/ipmmu-vmsa: Allow two bit SL0
+
+Introduce support for two bit SL0 bitfield in IMTTBCR
+by using a separate feature flag.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit c295f504fb5a38abbb4094e687ee333a75613a0c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 49f2c697b108..65ad6910cb70 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -45,6 +45,7 @@ struct ipmmu_features {
+ 	bool has_cache_leaf_nodes;
+ 	unsigned int number_of_contexts;
+ 	bool setup_imbuscr;
++	bool twobit_imttbcr_sl0;
+ };
+ 
+ struct ipmmu_vmsa_device {
+@@ -144,6 +145,10 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
+ #define IMTTBCR_TSZ0_MASK		(7 << 0)
+ #define IMTTBCR_TSZ0_SHIFT		O
+ 
++#define IMTTBCR_SL0_TWOBIT_LVL_3	(0 << 6)
++#define IMTTBCR_SL0_TWOBIT_LVL_2	(1 << 6)
++#define IMTTBCR_SL0_TWOBIT_LVL_1	(2 << 6)
++
+ #define IMBUSCR				0x000c
+ #define IMBUSCR_DVM			(1 << 2)
+ #define IMBUSCR_BUSSEL_SYS		(0 << 0)
+@@ -396,6 +401,7 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
+ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ {
+ 	u64 ttbr;
++	u32 tmp;
+ 	int ret;
+ 
+ 	/*
+@@ -449,9 +455,14 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ 	 * We use long descriptors with inner-shareable WBWA tables and allocate
+ 	 * the whole 32-bit VA space to TTBR0.
+ 	 */
++	if (domain->mmu->features->twobit_imttbcr_sl0)
++		tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
++	else
++		tmp = IMTTBCR_SL0_LVL_1;
++
+ 	ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
+ 			     IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
+-			     IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
++			     IMTTBCR_IRGN0_WB_WA | tmp);
+ 
+ 	/* MAIR0 */
+ 	ipmmu_ctx_write_root(domain, IMMAIR0,
+@@ -889,6 +900,7 @@ static const struct ipmmu_features ipmmu_features_default = {
+ 	.has_cache_leaf_nodes = false,
+ 	.number_of_contexts = 1, /* software only tested with one context */
+ 	.setup_imbuscr = true,
++	.twobit_imttbcr_sl0 = false,
+ };
+ 
+ static const struct of_device_id ipmmu_of_ids[] = {
+-- 
+2.19.0
+
diff --git a/patches/0107-iommu-ipmmu-vmsa-Hook-up-r8a7795-DT-matching-code.patch b/patches/0107-iommu-ipmmu-vmsa-Hook-up-r8a7795-DT-matching-code.patch
new file mode 100644
index 00000000000000..9caa4cc51ee1f8
--- /dev/null
+++ b/patches/0107-iommu-ipmmu-vmsa-Hook-up-r8a7795-DT-matching-code.patch
@@ -0,0 +1,88 @@
+From 834eb971ccfc690bbb2c27ed298e23c4f2df72d4 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 16 Oct 2017 21:30:50 +0900
+Subject: [PATCH 0107/1795] iommu/ipmmu-vmsa: Hook up r8a7795 DT matching code
+
+Tie in r8a7795 features and update the IOMMU_OF_DECLARE
+compat string to include the updated compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 58b8e8bf409236cdea379b8a3ab5d7b85a003d22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 29 +++++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 65ad6910cb70..8dce3a9de9d8 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -25,6 +25,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/sizes.h>
+ #include <linux/slab.h>
++#include <linux/sys_soc.h>
+ 
+ #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
+ #include <asm/dma-iommu.h>
+@@ -749,9 +750,24 @@ static int ipmmu_init_platform_device(struct device *dev,
+ 	return 0;
+ }
+ 
++static bool ipmmu_slave_whitelist(struct device *dev)
++{
++	/* By default, do not allow use of IPMMU */
++	return false;
++}
++
++static const struct soc_device_attribute soc_r8a7795[] = {
++	{ .soc_id = "r8a7795", },
++	{ /* sentinel */ }
++};
++
+ static int ipmmu_of_xlate(struct device *dev,
+ 			  struct of_phandle_args *spec)
+ {
++	/* For R-Car Gen3 use a white list to opt-in slave devices */
++	if (soc_device_match(soc_r8a7795) && !ipmmu_slave_whitelist(dev))
++		return -ENODEV;
++
+ 	iommu_fwspec_add_ids(dev, spec->args, 1);
+ 
+ 	/* Initialize once - xlate() will call multiple times */
+@@ -903,10 +919,21 @@ static const struct ipmmu_features ipmmu_features_default = {
+ 	.twobit_imttbcr_sl0 = false,
+ };
+ 
++static const struct ipmmu_features ipmmu_features_r8a7795 = {
++	.use_ns_alias_offset = false,
++	.has_cache_leaf_nodes = true,
++	.number_of_contexts = 8,
++	.setup_imbuscr = false,
++	.twobit_imttbcr_sl0 = true,
++};
++
+ static const struct of_device_id ipmmu_of_ids[] = {
+ 	{
+ 		.compatible = "renesas,ipmmu-vmsa",
+ 		.data = &ipmmu_features_default,
++	}, {
++		.compatible = "renesas,ipmmu-r8a7795",
++		.data = &ipmmu_features_r8a7795,
+ 	}, {
+ 		/* Terminator */
+ 	},
+@@ -1090,6 +1117,8 @@ static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np)
+ 
+ IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa",
+ 		 ipmmu_vmsa_iommu_of_setup);
++IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795",
++		 ipmmu_vmsa_iommu_of_setup);
+ #endif
+ 
+ MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
+-- 
+2.19.0
+
diff --git a/patches/0108-irqchip-gic-Deal-with-broken-firmware-exposing-only-.patch b/patches/0108-irqchip-gic-Deal-with-broken-firmware-exposing-only-.patch
new file mode 100644
index 00000000000000..a26b3a33e29907
--- /dev/null
+++ b/patches/0108-irqchip-gic-Deal-with-broken-firmware-exposing-only-.patch
@@ -0,0 +1,158 @@
+From adde40ad18b5dcbeb2ec4acd09b347842b41e707 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Fri, 27 Oct 2017 10:34:22 +0200
+Subject: [PATCH 0108/1795] irqchip/gic: Deal with broken firmware exposing
+ only 4kB of GICv2 CPU interface
+
+There is a lot of broken firmware out there that don't really
+expose the information the kernel requires when it comes with dealing
+with GICv2:
+
+(1) Firmware that only describes the first 4kB of GICv2
+(2) Firmware that describe 128kB of CPU interface, while
+    the usable portion of the address space is between
+    60 and 68kB
+
+So far, we only deal with (2). But we have platforms exhibiting
+behaviour (1), resulting in two sub-cases:
+(a) The GIC is occupying 8kB, as required by the GICv2 architecture
+(b) It is actually spread 128kB, and this is likely to be a version
+    of (2)
+
+This patch tries to work around both (a) and (b) by poking at
+the outside of the described memory region, and try to work out
+what is actually there. This is of course unsafe, and should
+only be enabled if there is no way to otherwise fix the DT provided
+by the firmware (we provide a "irqchip.gicv2_force_probe" option
+to that effect).
+
+Note that for the time being, we restrict ourselves to GICv2
+implementations provided by ARM, since there I have no knowledge
+of an alternative implementations. This could be relaxed if such
+an implementation comes to light on a broken platform.
+
+Reviewed-by: Christoffer Dall <cdall@linaro.org>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit 0962289b1cd91534f7111e763d3e6a17dcd47ecb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../admin-guide/kernel-parameters.txt         |  7 ++
+ drivers/irqchip/irq-gic.c                     | 71 ++++++++++++++++---
+ 2 files changed, 69 insertions(+), 9 deletions(-)
+
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 9841bad6f271..900c83e10d4d 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -1713,6 +1713,13 @@
+ 	irqaffinity=	[SMP] Set the default irq affinity mask
+ 			The argument is a cpu list, as described above.
+ 
++	irqchip.gicv2_force_probe=
++			[ARM, ARM64]
++			Format: <bool>
++			Force the kernel to look for the second 4kB page
++			of a GICv2 controller even if the memory range
++			exposed by the device tree is too small.
++
+ 	irqfixup	[HW]
+ 			When an interrupt is not handled search all handlers
+ 			for it. Intended to get systems with badly broken
+diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
+index 651d726e8b12..f641e8e2c78d 100644
+--- a/drivers/irqchip/irq-gic.c
++++ b/drivers/irqchip/irq-gic.c
+@@ -1256,6 +1256,19 @@ static void gic_teardown(struct gic_chip_data *gic)
+ 
+ #ifdef CONFIG_OF
+ static int gic_cnt __initdata;
++static bool gicv2_force_probe;
++
++static int __init gicv2_force_probe_cfg(char *buf)
++{
++	return strtobool(buf, &gicv2_force_probe);
++}
++early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
++
++static bool gic_check_gicv2(void __iomem *base)
++{
++	u32 val = readl_relaxed(base + GIC_CPU_IDENT);
++	return (val & 0xff0fff) == 0x02043B;
++}
+ 
+ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
+ {
+@@ -1265,20 +1278,60 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
+ 
+ 	if (!is_hyp_mode_available())
+ 		return false;
+-	if (resource_size(&cpuif_res) < SZ_8K)
+-		return false;
+-	if (resource_size(&cpuif_res) == SZ_128K) {
+-		u32 val_low, val_high;
++	if (resource_size(&cpuif_res) < SZ_8K) {
++		void __iomem *alt;
++		/*
++		 * Check for a stupid firmware that only exposes the
++		 * first page of a GICv2.
++		 */
++		if (!gic_check_gicv2(*base))
++			return false;
+ 
++		if (!gicv2_force_probe) {
++			pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
++			return false;
++		}
++
++		alt = ioremap(cpuif_res.start, SZ_8K);
++		if (!alt)
++			return false;
++		if (!gic_check_gicv2(alt + SZ_4K)) {
++			/*
++			 * The first page was that of a GICv2, and
++			 * the second was *something*. Let's trust it
++			 * to be a GICv2, and update the mapping.
++			 */
++			pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
++				&cpuif_res.start);
++			iounmap(*base);
++			*base = alt;
++			return true;
++		}
++
++		/*
++		 * We detected *two* initial GICv2 pages in a
++		 * row. Could be a GICv2 aliased over two 64kB
++		 * pages. Update the resource, map the iospace, and
++		 * pray.
++		 */
++		iounmap(alt);
++		alt = ioremap(cpuif_res.start, SZ_128K);
++		if (!alt)
++			return false;
++		pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
++			&cpuif_res.start);
++		cpuif_res.end = cpuif_res.start + SZ_128K -1;
++		iounmap(*base);
++		*base = alt;
++	}
++	if (resource_size(&cpuif_res) == SZ_128K) {
+ 		/*
+-		 * Verify that we have the first 4kB of a GIC400
++		 * Verify that we have the first 4kB of a GICv2
+ 		 * aliased over the first 64kB by checking the
+ 		 * GICC_IIDR register on both ends.
+ 		 */
+-		val_low = readl_relaxed(*base + GIC_CPU_IDENT);
+-		val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
+-		if ((val_low & 0xffff0fff) != 0x0202043B ||
+-		    val_low != val_high)
++		if (!gic_check_gicv2(*base) ||
++		    !gic_check_gicv2(*base + 0xf000))
+ 			return false;
+ 
+ 		/*
+-- 
+2.19.0
+
diff --git a/patches/0109-KVM-arm-arm64-Check-that-system-supports-split-eoi-d.patch b/patches/0109-KVM-arm-arm64-Check-that-system-supports-split-eoi-d.patch
new file mode 100644
index 00000000000000..80ccc34bda8fa2
--- /dev/null
+++ b/patches/0109-KVM-arm-arm64-Check-that-system-supports-split-eoi-d.patch
@@ -0,0 +1,79 @@
+From 3ef51abc406abb6dba35604cd012afe200d20fe8 Mon Sep 17 00:00:00 2001
+From: Christoffer Dall <cdall@linaro.org>
+Date: Tue, 6 Dec 2016 22:00:52 +0100
+Subject: [PATCH 0109/1795] KVM: arm/arm64: Check that system supports split
+ eoi/deactivate
+
+Some systems without proper firmware and/or hardware description data
+don't support the split EOI and deactivate operation.
+
+On such systems, we cannot leave the physical interrupt active after the
+timer handler on the host has run, so we cannot support KVM with an
+in-kernel GIC with the timer changes we are about to introduce.
+
+This patch makes sure that trying to initialize the KVM GIC code will
+fail on such systems.
+
+Acked-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Christoffer Dall <cdall@linaro.org>
+(cherry picked from commit d33a3c8c48c3264419a683885a27a5c85df35f12)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-gic-v3.c | 8 ++++++--
+ drivers/irqchip/irq-gic.c    | 6 ++++--
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
+index 3d7374655587..2437497eaf4d 100644
+--- a/drivers/irqchip/irq-gic-v3.c
++++ b/drivers/irqchip/irq-gic-v3.c
+@@ -1231,7 +1231,9 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
+ 		goto out_unmap_rdist;
+ 
+ 	gic_populate_ppi_partitions(node);
+-	gic_of_setup_kvm_info(node);
++
++	if (static_key_true(&supports_deactivate))
++		gic_of_setup_kvm_info(node);
+ 	return 0;
+ 
+ out_unmap_rdist:
+@@ -1531,7 +1533,9 @@ gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
+ 		goto out_fwhandle_free;
+ 
+ 	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+-	gic_acpi_setup_kvm_info();
++
++	if (static_key_true(&supports_deactivate))
++		gic_acpi_setup_kvm_info();
+ 
+ 	return 0;
+ 
+diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
+index f641e8e2c78d..121af5cf688f 100644
+--- a/drivers/irqchip/irq-gic.c
++++ b/drivers/irqchip/irq-gic.c
+@@ -1420,7 +1420,8 @@ static void __init gic_of_setup_kvm_info(struct device_node *node)
+ 	if (ret)
+ 		return;
+ 
+-	gic_set_kvm_info(&gic_v2_kvm_info);
++	if (static_key_true(&supports_deactivate))
++		gic_set_kvm_info(&gic_v2_kvm_info);
+ }
+ 
+ int __init
+@@ -1652,7 +1653,8 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
+ 	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
+ 		gicv2m_init(NULL, gic_data[0].domain);
+ 
+-	gic_acpi_setup_kvm_info();
++	if (static_key_true(&supports_deactivate))
++		gic_acpi_setup_kvm_info();
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0110-irqchip-renesas-intc-irqpin-Use-of_device_get_match_.patch b/patches/0110-irqchip-renesas-intc-irqpin-Use-of_device_get_match_.patch
new file mode 100644
index 00000000000000..ce9b7c175c156c
--- /dev/null
+++ b/patches/0110-irqchip-renesas-intc-irqpin-Use-of_device_get_match_.patch
@@ -0,0 +1,51 @@
+From 448d24fe5279a114c233776bb1ed9b48f06811a7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:17:58 +0200
+Subject: [PATCH 0110/1795] irqchip/renesas-intc-irqpin: Use
+ of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit 42a5968c0ae8f19906e16fa34ea9bdb6f5095166)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-renesas-intc-irqpin.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
+index 713177d97c7a..06f29cf5018a 100644
+--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
+@@ -389,9 +389,8 @@ MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
+ 
+ static int intc_irqpin_probe(struct platform_device *pdev)
+ {
+-	const struct intc_irqpin_config *config = NULL;
++	const struct intc_irqpin_config *config;
+ 	struct device *dev = &pdev->dev;
+-	const struct of_device_id *of_id;
+ 	struct intc_irqpin_priv *p;
+ 	struct intc_irqpin_iomem *i;
+ 	struct resource *io[INTC_IRQPIN_REG_NR];
+@@ -422,11 +421,9 @@ static int intc_irqpin_probe(struct platform_device *pdev)
+ 	p->pdev = pdev;
+ 	platform_set_drvdata(pdev, p);
+ 
+-	of_id = of_match_device(intc_irqpin_dt_ids, dev);
+-	if (of_id && of_id->data) {
+-		config = of_id->data;
++	config = of_device_get_match_data(dev);
++	if (config)
+ 		p->needs_clk = config->needs_clk;
+-	}
+ 
+ 	p->clk = devm_clk_get(dev, NULL);
+ 	if (IS_ERR(p->clk)) {
+-- 
+2.19.0
+
diff --git a/patches/0111-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-W.patch b/patches/0111-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-W.patch
new file mode 100644
index 00000000000000..62ac8c425d0caa
--- /dev/null
+++ b/patches/0111-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-W.patch
@@ -0,0 +1,39 @@
+From 4cd3f709290d6723d6ef6f3c3a74f0ecfb52cc5d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 6 Oct 2017 13:51:32 +0200
+Subject: [PATCH 0111/1795] dt-bindings: irqchip: renesas-irqc: Document R-Car
+ M3-W, V3M, D3 support
+
+Document support for the Interrupt Controller for Externel Devices
+(INTC-EX) in the Renesas M3-W (r8a7796), V3M (r8a77970), and D3
+(r8a77995) SoCs.
+
+No driver update is needed.
+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit bea173e5acd73d536dd234b34328cd52c1cadaab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/interrupt-controller/renesas,irqc.txt  | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+index e3f052d8c11a..33c9a10fdc91 100644
+--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
++++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+@@ -13,6 +13,9 @@ Required properties:
+     - "renesas,irqc-r8a7793" (R-Car M2-N)
+     - "renesas,irqc-r8a7794" (R-Car E2)
+     - "renesas,intc-ex-r8a7795" (R-Car H3)
++    - "renesas,intc-ex-r8a7796" (R-Car M3-W)
++    - "renesas,intc-ex-r8a77970" (R-Car V3M)
++    - "renesas,intc-ex-r8a77995" (R-Car D3)
+ - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+   interrupts.txt in this directory
+ - clocks: Must contain a reference to the functional clock.
+-- 
+2.19.0
+
diff --git a/patches/0112-mtd-spi-nor-Add-support-for-mr25h128.patch b/patches/0112-mtd-spi-nor-Add-support-for-mr25h128.patch
new file mode 100644
index 00000000000000..6b6ce0430baabf
--- /dev/null
+++ b/patches/0112-mtd-spi-nor-Add-support-for-mr25h128.patch
@@ -0,0 +1,57 @@
+From 41668e64c5392e0b02acd4e85bcf65b7f8897950 Mon Sep 17 00:00:00 2001
+From: Philipp Puschmann <pp@emlix.com>
+Date: Thu, 19 Oct 2017 10:12:47 +0200
+Subject: [PATCH 0112/1795] mtd: spi-nor: Add support for mr25h128
+
+Add Everspin mr25h128 16KB MRAM to the list of supported chips.
+
+Signed-off-by: Philipp Puschmann <pp@emlix.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+(cherry picked from commit 282e45dc64d1832c9b51d2c6f6eb0a634c924fa7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 1 +
+ drivers/mtd/devices/m25p80.c                            | 1 +
+ drivers/mtd/spi-nor/spi-nor.c                           | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+index 9ce35af8507c..956bb046e599 100644
+--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
++++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+@@ -13,6 +13,7 @@ Required properties:
+                  at25df321a
+                  at25df641
+                  at26df081a
++                 mr25h128
+                  mr25h256
+                  mr25h10
+                  mr25h40
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index 00eea6fd379c..dbe6a1de2bb8 100644
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -359,6 +359,7 @@ static const struct spi_device_id m25p_ids[] = {
+ 	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},
+ 
+ 	/* Everspin MRAMs (non-JEDEC) */
++	{ "mr25h128" }, /* 128 Kib, 40 MHz */
+ 	{ "mr25h256" }, /* 256 Kib, 40 MHz */
+ 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
+ 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
+diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index 19c000722cbc..52056198f457 100644
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -964,6 +964,7 @@ static const struct flash_info spi_nor_ids[] = {
+ 	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
+ 
+ 	/* Everspin */
++	{ "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ 	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ 	{ "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ 	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+-- 
+2.19.0
+
diff --git a/patches/0113-net-phy-micrel-check-return-code-in-flp-center-funct.patch b/patches/0113-net-phy-micrel-check-return-code-in-flp-center-funct.patch
new file mode 100644
index 00000000000000..0bb9fdf1330bb0
--- /dev/null
+++ b/patches/0113-net-phy-micrel-check-return-code-in-flp-center-funct.patch
@@ -0,0 +1,45 @@
+From b055902a4ba6a0a334604285cf9700ae9f96527b Mon Sep 17 00:00:00 2001
+From: Max Uvarov <muvarov@gmail.com>
+Date: Thu, 30 Nov 2017 13:08:29 +0300
+Subject: [PATCH 0113/1795] net: phy-micrel: check return code in flp center
+ function
+
+Fix obvious typo that first return value is set but not checked.
+
+Signed-off-by: Max Uvarov <muvarov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit a0da456bbf95d2a9294799bb05c61bfb24736bb7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/micrel.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index 6c45ff650ec7..422ff6333c52 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -496,16 +496,18 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev,
+ 	return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
+ }
+ 
++/* Center KSZ9031RNX FLP timing at 16ms. */
+ static int ksz9031_center_flp_timing(struct phy_device *phydev)
+ {
+ 	int result;
+ 
+-	/* Center KSZ9031RNX FLP timing at 16ms. */
+ 	result = ksz9031_extended_write(phydev, OP_DATA, 0,
+ 					MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
++	if (result)
++		return result;
++
+ 	result = ksz9031_extended_write(phydev, OP_DATA, 0,
+ 					MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+-
+ 	if (result)
+ 		return result;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0114-phy-rcar-gen2-Add-r8a7743-5-support.patch b/patches/0114-phy-rcar-gen2-Add-r8a7743-5-support.patch
new file mode 100644
index 00000000000000..d04fd9ed62aa26
--- /dev/null
+++ b/patches/0114-phy-rcar-gen2-Add-r8a7743-5-support.patch
@@ -0,0 +1,43 @@
+From 1adef86be1c8d335cf1ddace3fb5c0da38bd967f Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 11:22:23 +0100
+Subject: [PATCH 0114/1795] phy: rcar-gen2: Add r8a7743/5 support
+
+Add USB PHY support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5)
+USB PHY is identical to the R-Car Gen2 family.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit f7da4e6d29539bad2c29dd8ccb4ac628fe19f82b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
+index 91da947ae9b6..eeb9e1874ea6 100644
+--- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
++++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
+@@ -4,10 +4,13 @@ This file provides information on what the device node for the R-Car generation
+ 2 USB PHY contains.
+ 
+ Required properties:
+-- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
++- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
++	      "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
++	      "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+ 	      "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
+ 	      "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
+-	      "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 compatible device.
++	      "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or
++					  RZ/G1 compatible device.
+ 
+ 	      When compatible with the generic version, nodes must list the
+ 	      SoC-specific version corresponding to the platform first
+-- 
+2.19.0
+
diff --git a/patches/0115-phy-rcar-gen3-usb2-select-USB_COMMON.patch b/patches/0115-phy-rcar-gen3-usb2-select-USB_COMMON.patch
new file mode 100644
index 00000000000000..1c5ce8cbe9d63b
--- /dev/null
+++ b/patches/0115-phy-rcar-gen3-usb2-select-USB_COMMON.patch
@@ -0,0 +1,42 @@
+From d164b3a815f713ec83339d9c5c141726fb21f5ea Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 2 Nov 2017 12:56:36 +0100
+Subject: [PATCH 0115/1795] phy: rcar-gen3-usb2: select USB_COMMON
+
+When USB is disabled, we get a link error for this driver
+because of the added OTG support
+
+drivers/phy/renesas/phy-rcar-gen3-usb2.o: In function `rcar_gen3_phy_usb2_probe':
+phy-rcar-gen3-usb2.c:(.text+0x250): undefined reference to `of_usb_get_dr_mode_by_phy'
+
+Other phy drivers select USB_COMMON for this, so let's do the same
+here.
+
+Fixes: 7e0540f41332 ("phy: rcar-gen3-usb2: check dr_mode for otg mode")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 2b88212c4cc67ff33dec5bb4d690044b97a5f979)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/phy/renesas/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
+index cb09245e9b4c..c845facacb06 100644
+--- a/drivers/phy/renesas/Kconfig
++++ b/drivers/phy/renesas/Kconfig
+@@ -12,7 +12,9 @@ config PHY_RCAR_GEN3_USB2
+ 	tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
+ 	depends on ARCH_RENESAS
+ 	depends on EXTCON
++	depends on USB_SUPPORT
+ 	select GENERIC_PHY
++	select USB_COMMON
+ 	help
+ 	  Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs.
+ 
+-- 
+2.19.0
+
diff --git a/patches/0116-extcon-Split-out-extcon-header-file-for-consumer-and.patch b/patches/0116-extcon-Split-out-extcon-header-file-for-consumer-and.patch
new file mode 100644
index 00000000000000..ee27c39e65b344
--- /dev/null
+++ b/patches/0116-extcon-Split-out-extcon-header-file-for-consumer-and.patch
@@ -0,0 +1,724 @@
+From 811e26d8f942680e9f9faed1b6bb91bd8702cdcc Mon Sep 17 00:00:00 2001
+From: Chanwoo Choi <cw00.choi@samsung.com>
+Date: Thu, 21 Sep 2017 12:11:24 +0900
+Subject: [PATCH 0116/1795] extcon: Split out extcon header file for consumer
+ and provider device
+
+The extcon has two type of extcon devices as following.
+- 'extcon provider deivce' adds new extcon device and detect the
+   state/properties of external connector. Also, it notifies the
+   state/properties to the extcon consumer device.
+- 'extcon consumer device' gets the change state/properties
+   from extcon provider device.
+Prior to that, include/linux/extcon.h contains all exported API for
+both provider and consumer device driver. To clarify the meaning of
+header file and to remove the wrong use-case on consumer device,
+this patch separates into extcon.h and extcon-provider.h.
+
+[Description for include/linux/{extcon.h|extcon-provider.h}]
+- extcon.h includes the extcon API and data structure for extcon consumer
+  device driver. This header file contains the following APIs:
+  : Register/unregister the notifier to catch the change of extcon device
+  : Get the extcon device instance
+  : Get the extcon device name
+  : Get the state of each external connector
+  : Get the property value of each external connector
+  : Get the property capability of each external connector
+
+- extcon-provider.h includes the extcon API and data structure for extcon
+  provider device driver. This header file contains the following APIs:
+  : Include 'include/linux/extcon.h'
+  : Allocate the memory for extcon device instance
+  : Register/unregister extcon device
+  : Set the state of each external connector
+  : Set the property value of each external connector
+  : Set the property capability of each external connector
+
+Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
+Acked-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 176aa36012135d172394a928a03fb03dfecd83f9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/extcon/extcon-adc-jack.c              |   2 +-
+ drivers/extcon/extcon-arizona.c               |   2 +-
+ drivers/extcon/extcon-axp288.c                |   2 +-
+ drivers/extcon/extcon-gpio.c                  |   2 +-
+ drivers/extcon/extcon-intel-cht-wc.c          |   2 +-
+ drivers/extcon/extcon-intel-int3496.c         |   2 +-
+ drivers/extcon/extcon-max14577.c              |   2 +-
+ drivers/extcon/extcon-max3355.c               |   2 +-
+ drivers/extcon/extcon-max77693.c              |   2 +-
+ drivers/extcon/extcon-max77843.c              |   2 +-
+ drivers/extcon/extcon-max8997.c               |   2 +-
+ drivers/extcon/extcon-qcom-spmi-misc.c        |   2 +-
+ drivers/extcon/extcon-rt8973a.c               |   2 +-
+ drivers/extcon/extcon-sm5502.c                |   2 +-
+ drivers/extcon/extcon-usb-gpio.c              |   2 +-
+ drivers/extcon/extcon-usbc-cros-ec.c          |   2 +-
+ drivers/extcon/extcon.h                       |   2 +-
+ drivers/phy/allwinner/phy-sun4i-usb.c         |   2 +-
+ drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c     |   2 +-
+ drivers/phy/renesas/phy-rcar-gen3-usb2.c      |   2 +-
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c |   2 +-
+ drivers/power/supply/qcom_smbb.c              |   2 +-
+ drivers/usb/gadget/udc/renesas_usb3.c         |   2 +-
+ drivers/usb/phy/phy-tahvo.c                   |   2 +-
+ include/linux/extcon-provider.h               | 142 ++++++++++++++++++
+ include/linux/extcon.h                        | 109 +-------------
+ include/linux/mfd/palmas.h                    |   2 +-
+ 27 files changed, 172 insertions(+), 129 deletions(-)
+ create mode 100644 include/linux/extcon-provider.h
+
+diff --git a/drivers/extcon/extcon-adc-jack.c b/drivers/extcon/extcon-adc-jack.c
+index 6f6537ab0a79..3877d86c746a 100644
+--- a/drivers/extcon/extcon-adc-jack.c
++++ b/drivers/extcon/extcon-adc-jack.c
+@@ -26,7 +26,7 @@
+ #include <linux/workqueue.h>
+ #include <linux/iio/consumer.h>
+ #include <linux/extcon/extcon-adc-jack.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ /**
+  * struct adc_jack_data - internal data for adc_jack device driver
+diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c
+index f84da4a17724..da0e9bc4262f 100644
+--- a/drivers/extcon/extcon-arizona.c
++++ b/drivers/extcon/extcon-arizona.c
+@@ -27,7 +27,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/property.h>
+ #include <linux/regulator/consumer.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ #include <sound/soc.h>
+ 
+diff --git a/drivers/extcon/extcon-axp288.c b/drivers/extcon/extcon-axp288.c
+index f4fd03e58e37..981fba56bc18 100644
+--- a/drivers/extcon/extcon-axp288.c
++++ b/drivers/extcon/extcon-axp288.c
+@@ -22,7 +22,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/property.h>
+ #include <linux/notifier.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/regmap.h>
+ #include <linux/gpio.h>
+ #include <linux/gpio/consumer.h>
+diff --git a/drivers/extcon/extcon-gpio.c b/drivers/extcon/extcon-gpio.c
+index ebed22f22d75..ab770adcca7e 100644
+--- a/drivers/extcon/extcon-gpio.c
++++ b/drivers/extcon/extcon-gpio.c
+@@ -17,7 +17,7 @@
+  * GNU General Public License for more details.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/extcon/extcon-gpio.h>
+ #include <linux/gpio.h>
+ #include <linux/gpio/consumer.h>
+diff --git a/drivers/extcon/extcon-intel-cht-wc.c b/drivers/extcon/extcon-intel-cht-wc.c
+index 60baaf693103..b7e9ea377d70 100644
+--- a/drivers/extcon/extcon-intel-cht-wc.c
++++ b/drivers/extcon/extcon-intel-cht-wc.c
+@@ -15,7 +15,7 @@
+  * more details.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+ #include <linux/mfd/intel_soc_pmic.h>
+diff --git a/drivers/extcon/extcon-intel-int3496.c b/drivers/extcon/extcon-intel-int3496.c
+index a6661097b2f9..191e99f06a9a 100644
+--- a/drivers/extcon/extcon-intel-int3496.c
++++ b/drivers/extcon/extcon-intel-int3496.c
+@@ -19,7 +19,7 @@
+  */
+ 
+ #include <linux/acpi.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/gpio.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+diff --git a/drivers/extcon/extcon-max14577.c b/drivers/extcon/extcon-max14577.c
+index f6414b7fa5bc..6c2c9996eb71 100644
+--- a/drivers/extcon/extcon-max14577.c
++++ b/drivers/extcon/extcon-max14577.c
+@@ -23,7 +23,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/mfd/max14577.h>
+ #include <linux/mfd/max14577-private.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ #define	DELAY_MS_DEFAULT		17000		/* unit: millisecond */
+ 
+diff --git a/drivers/extcon/extcon-max3355.c b/drivers/extcon/extcon-max3355.c
+index 533e16a952b8..0aa410836f4e 100644
+--- a/drivers/extcon/extcon-max3355.c
++++ b/drivers/extcon/extcon-max3355.c
+@@ -9,7 +9,7 @@
+  * may be copied, distributed, and modified under those terms.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/gpio.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/interrupt.h>
+diff --git a/drivers/extcon/extcon-max77693.c b/drivers/extcon/extcon-max77693.c
+index 7a5856809047..643411066ad9 100644
+--- a/drivers/extcon/extcon-max77693.c
++++ b/drivers/extcon/extcon-max77693.c
+@@ -26,7 +26,7 @@
+ #include <linux/mfd/max77693.h>
+ #include <linux/mfd/max77693-common.h>
+ #include <linux/mfd/max77693-private.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/regmap.h>
+ #include <linux/irqdomain.h>
+ 
+diff --git a/drivers/extcon/extcon-max77843.c b/drivers/extcon/extcon-max77843.c
+index 6e722d552cf1..28f251ff0fa2 100644
+--- a/drivers/extcon/extcon-max77843.c
++++ b/drivers/extcon/extcon-max77843.c
+@@ -11,7 +11,7 @@
+  * (at your option) any later version.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/i2c.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/extcon/extcon-max8997.c b/drivers/extcon/extcon-max8997.c
+index 4a0612fb9c07..8152790d72e1 100644
+--- a/drivers/extcon/extcon-max8997.c
++++ b/drivers/extcon/extcon-max8997.c
+@@ -25,7 +25,7 @@
+ #include <linux/kobject.h>
+ #include <linux/mfd/max8997.h>
+ #include <linux/mfd/max8997-private.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/irqdomain.h>
+ 
+ #define	DEV_NAME			"max8997-muic"
+diff --git a/drivers/extcon/extcon-qcom-spmi-misc.c b/drivers/extcon/extcon-qcom-spmi-misc.c
+index b8cde096a808..660bbf163bf5 100644
+--- a/drivers/extcon/extcon-qcom-spmi-misc.c
++++ b/drivers/extcon/extcon-qcom-spmi-misc.c
+@@ -15,7 +15,7 @@
+  * GNU General Public License for more details.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/extcon/extcon-rt8973a.c b/drivers/extcon/extcon-rt8973a.c
+index eaa355e7d9e4..e059bd5f2041 100644
+--- a/drivers/extcon/extcon-rt8973a.c
++++ b/drivers/extcon/extcon-rt8973a.c
+@@ -20,7 +20,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/slab.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ #include "extcon-rt8973a.h"
+ 
+diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c
+index 106ef0297b53..0cfb5a3efdf6 100644
+--- a/drivers/extcon/extcon-sm5502.c
++++ b/drivers/extcon/extcon-sm5502.c
+@@ -19,7 +19,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/slab.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ #include "extcon-sm5502.h"
+ 
+diff --git a/drivers/extcon/extcon-usb-gpio.c b/drivers/extcon/extcon-usb-gpio.c
+index 9c925b05b7aa..53762864a9f7 100644
+--- a/drivers/extcon/extcon-usb-gpio.c
++++ b/drivers/extcon/extcon-usb-gpio.c
+@@ -14,7 +14,7 @@
+  * GNU General Public License for more details.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/gpio.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/init.h>
+diff --git a/drivers/extcon/extcon-usbc-cros-ec.c b/drivers/extcon/extcon-usbc-cros-ec.c
+index 598956f1dcae..6187f731b29d 100644
+--- a/drivers/extcon/extcon-usbc-cros-ec.c
++++ b/drivers/extcon/extcon-usbc-cros-ec.c
+@@ -14,7 +14,7 @@
+  * GNU General Public License for more details.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/kernel.h>
+ #include <linux/mfd/cros_ec.h>
+ #include <linux/module.h>
+diff --git a/drivers/extcon/extcon.h b/drivers/extcon/extcon.h
+index 61358479bfcc..93b5e0306966 100644
+--- a/drivers/extcon/extcon.h
++++ b/drivers/extcon/extcon.h
+@@ -2,7 +2,7 @@
+ #ifndef __LINUX_EXTCON_INTERNAL_H__
+ #define __LINUX_EXTCON_INTERNAL_H__
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ 
+ /**
+  * struct extcon_dev - An extcon device represents one external connector.
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index afedb8cd1990..263e2562de3b 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -24,7 +24,7 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/io.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
+index d099a0c8cee5..7ceea5ae2704 100644
+--- a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
++++ b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
+@@ -12,7 +12,7 @@
+  */
+ 
+ #include <linux/delay.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/gpio.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/init.h>
+diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+index 54c34298a000..b33e2994ccce 100644
+--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
++++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+@@ -12,7 +12,7 @@
+  * published by the Free Software Foundation.
+  */
+ 
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+index ee7ce5ee53f9..5049dac79bd0 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -17,7 +17,7 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/delay.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/gpio/consumer.h>
+diff --git a/drivers/power/supply/qcom_smbb.c b/drivers/power/supply/qcom_smbb.c
+index f6a0d245731d..11de691b9a71 100644
+--- a/drivers/power/supply/qcom_smbb.c
++++ b/drivers/power/supply/qcom_smbb.c
+@@ -34,7 +34,7 @@
+ #include <linux/power_supply.h>
+ #include <linux/regmap.h>
+ #include <linux/slab.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/regulator/driver.h>
+ 
+ #define SMBB_CHG_VMAX		0x040
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index c12a1a6554ba..8de7d72b130b 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -12,7 +12,7 @@
+ #include <linux/delay.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/err.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c
+index 1ec00eae339a..bf2c364867a0 100644
+--- a/drivers/usb/phy/phy-tahvo.c
++++ b/drivers/usb/phy/phy-tahvo.c
+@@ -23,7 +23,7 @@
+ #include <linux/io.h>
+ #include <linux/clk.h>
+ #include <linux/usb.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/usb/otg.h>
+diff --git a/include/linux/extcon-provider.h b/include/linux/extcon-provider.h
+new file mode 100644
+index 000000000000..2feca5881fa7
+--- /dev/null
++++ b/include/linux/extcon-provider.h
+@@ -0,0 +1,142 @@
++/*
++ * External Connector (extcon) framework
++ * - linux/include/linux/extcon-provider.h for extcon provider device driver.
++ *
++ * Copyright (C) 2017 Samsung Electronics
++ * Author: Chanwoo Choi <cw00.choi@samsung.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __LINUX_EXTCON_PROVIDER_H__
++#define __LINUX_EXTCON_PROVIDER_H__
++
++#include <linux/extcon.h>
++
++struct extcon_dev;
++
++#if IS_ENABLED(CONFIG_EXTCON)
++
++/* Following APIs register/unregister the extcon device. */
++extern int extcon_dev_register(struct extcon_dev *edev);
++extern void extcon_dev_unregister(struct extcon_dev *edev);
++extern int devm_extcon_dev_register(struct device *dev,
++				struct extcon_dev *edev);
++extern void devm_extcon_dev_unregister(struct device *dev,
++				struct extcon_dev *edev);
++
++/* Following APIs allocate/free the memory of the extcon device. */
++extern struct extcon_dev *extcon_dev_allocate(const unsigned int *cable);
++extern void extcon_dev_free(struct extcon_dev *edev);
++extern struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
++				const unsigned int *cable);
++extern void devm_extcon_dev_free(struct device *dev, struct extcon_dev *edev);
++
++/* Synchronize the state and property value for each external connector. */
++extern int extcon_sync(struct extcon_dev *edev, unsigned int id);
++
++/*
++ * Following APIs set the connected state of each external connector.
++ * The 'id' argument indicates the defined external connector.
++ */
++extern int extcon_set_state(struct extcon_dev *edev, unsigned int id,
++				bool state);
++extern int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id,
++				bool state);
++
++/*
++ * Following APIs set the property of each external connector.
++ * The 'id' argument indicates the defined external connector
++ * and the 'prop' indicates the extcon property.
++ *
++ * And extcon_set_property_capability() set the capability of the property
++ * for each external connector. They are used to set the capability of the
++ * property of each external connector based on the id and property.
++ */
++extern int extcon_set_property(struct extcon_dev *edev, unsigned int id,
++				unsigned int prop,
++				union extcon_property_value prop_val);
++extern int extcon_set_property_sync(struct extcon_dev *edev, unsigned int id,
++				unsigned int prop,
++				union extcon_property_value prop_val);
++extern int extcon_set_property_capability(struct extcon_dev *edev,
++				unsigned int id, unsigned int prop);
++
++#else /* CONFIG_EXTCON */
++static inline int extcon_dev_register(struct extcon_dev *edev)
++{
++	return 0;
++}
++
++static inline void extcon_dev_unregister(struct extcon_dev *edev) { }
++
++static inline int devm_extcon_dev_register(struct device *dev,
++				struct extcon_dev *edev)
++{
++	return -EINVAL;
++}
++
++static inline void devm_extcon_dev_unregister(struct device *dev,
++				struct extcon_dev *edev) { }
++
++static inline struct extcon_dev *extcon_dev_allocate(const unsigned int *cable)
++{
++	return ERR_PTR(-ENOSYS);
++}
++
++static inline void extcon_dev_free(struct extcon_dev *edev) { }
++
++static inline struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
++				const unsigned int *cable)
++{
++	return ERR_PTR(-ENOSYS);
++}
++
++static inline void devm_extcon_dev_free(struct extcon_dev *edev) { }
++
++
++static inline int extcon_set_state(struct extcon_dev *edev, unsigned int id,
++				bool state)
++{
++	return 0;
++}
++
++static inline int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id,
++				bool state)
++{
++	return 0;
++}
++
++static inline int extcon_sync(struct extcon_dev *edev, unsigned int id)
++{
++	return 0;
++}
++
++static inline int extcon_set_property(struct extcon_dev *edev, unsigned int id,
++				unsigned int prop,
++				union extcon_property_value prop_val)
++{
++	return 0;
++}
++
++static inline int extcon_set_property_sync(struct extcon_dev *edev,
++				unsigned int id, unsigned int prop,
++				union extcon_property_value prop_val)
++{
++	return 0;
++}
++
++static inline int extcon_set_property_capability(struct extcon_dev *edev,
++				unsigned int id, unsigned int prop)
++{
++	return 0;
++}
++#endif /* CONFIG_EXTCON */
++#endif /* __LINUX_EXTCON_PROVIDER_H__ */
+diff --git a/include/linux/extcon.h b/include/linux/extcon.h
+index 744d60ca80c3..6d94e82c8ad9 100644
+--- a/include/linux/extcon.h
++++ b/include/linux/extcon.h
+@@ -1,5 +1,6 @@
+ /*
+  * External Connector (extcon) framework
++ * - linux/include/linux/extcon.h for extcon consumer device driver.
+  *
+  * Copyright (C) 2015 Samsung Electronics
+  * Author: Chanwoo Choi <cw00.choi@samsung.com>
+@@ -170,61 +171,29 @@ union extcon_property_value {
+ 	int intval;	/* type : integer (intval) */
+ };
+ 
+-struct extcon_cable;
+ struct extcon_dev;
+ 
+ #if IS_ENABLED(CONFIG_EXTCON)
+-
+-/* Following APIs register/unregister the extcon device. */
+-extern int extcon_dev_register(struct extcon_dev *edev);
+-extern void extcon_dev_unregister(struct extcon_dev *edev);
+-extern int devm_extcon_dev_register(struct device *dev,
+-				struct extcon_dev *edev);
+-extern void devm_extcon_dev_unregister(struct device *dev,
+-				struct extcon_dev *edev);
+-
+-/* Following APIs allocate/free the memory of the extcon device. */
+-extern struct extcon_dev *extcon_dev_allocate(const unsigned int *cable);
+-extern void extcon_dev_free(struct extcon_dev *edev);
+-extern struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
+-				const unsigned int *cable);
+-extern void devm_extcon_dev_free(struct device *dev, struct extcon_dev *edev);
+-
+-/* Synchronize the state and property value for each external connector. */
+-extern int extcon_sync(struct extcon_dev *edev, unsigned int id);
+-
+ /*
+- * Following APIs get/set the connected state of each external connector.
++ * Following APIs get the connected state of each external connector.
+  * The 'id' argument indicates the defined external connector.
+  */
+ extern int extcon_get_state(struct extcon_dev *edev, unsigned int id);
+-extern int extcon_set_state(struct extcon_dev *edev, unsigned int id,
+-				bool state);
+-extern int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id,
+-				bool state);
+ 
+ /*
+- * Following APIs get/set the property of each external connector.
++ * Following APIs get the property of each external connector.
+  * The 'id' argument indicates the defined external connector
+  * and the 'prop' indicates the extcon property.
+  *
+- * And extcon_get/set_property_capability() set the capability of the property
+- * for each external connector. They are used to set the capability of the
++ * And extcon_get_property_capability() get the capability of the property
++ * for each external connector. They are used to get the capability of the
+  * property of each external connector based on the id and property.
+  */
+ extern int extcon_get_property(struct extcon_dev *edev, unsigned int id,
+ 				unsigned int prop,
+ 				union extcon_property_value *prop_val);
+-extern int extcon_set_property(struct extcon_dev *edev, unsigned int id,
+-				unsigned int prop,
+-				union extcon_property_value prop_val);
+-extern int extcon_set_property_sync(struct extcon_dev *edev, unsigned int id,
+-				unsigned int prop,
+-				union extcon_property_value prop_val);
+ extern int extcon_get_property_capability(struct extcon_dev *edev,
+ 				unsigned int id, unsigned int prop);
+-extern int extcon_set_property_capability(struct extcon_dev *edev,
+-				unsigned int id, unsigned int prop);
+ 
+ /*
+  * Following APIs register the notifier block in order to detect
+@@ -268,79 +237,17 @@ extern struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev,
+ extern const char *extcon_get_edev_name(struct extcon_dev *edev);
+ 
+ #else /* CONFIG_EXTCON */
+-static inline int extcon_dev_register(struct extcon_dev *edev)
+-{
+-	return 0;
+-}
+-
+-static inline void extcon_dev_unregister(struct extcon_dev *edev) { }
+-
+-static inline int devm_extcon_dev_register(struct device *dev,
+-				struct extcon_dev *edev)
+-{
+-	return -EINVAL;
+-}
+-
+-static inline void devm_extcon_dev_unregister(struct device *dev,
+-				struct extcon_dev *edev) { }
+-
+-static inline struct extcon_dev *extcon_dev_allocate(const unsigned int *cable)
+-{
+-	return ERR_PTR(-ENOSYS);
+-}
+-
+-static inline void extcon_dev_free(struct extcon_dev *edev) { }
+-
+-static inline struct extcon_dev *devm_extcon_dev_allocate(struct device *dev,
+-				const unsigned int *cable)
+-{
+-	return ERR_PTR(-ENOSYS);
+-}
+-
+-static inline void devm_extcon_dev_free(struct extcon_dev *edev) { }
+-
+-
+ static inline int extcon_get_state(struct extcon_dev *edev, unsigned int id)
+ {
+ 	return 0;
+ }
+ 
+-static inline int extcon_set_state(struct extcon_dev *edev, unsigned int id,
+-				bool state)
+-{
+-	return 0;
+-}
+-
+-static inline int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id,
+-				bool state)
+-{
+-	return 0;
+-}
+-
+-static inline int extcon_sync(struct extcon_dev *edev, unsigned int id)
+-{
+-	return 0;
+-}
+-
+ static inline int extcon_get_property(struct extcon_dev *edev, unsigned int id,
+ 				unsigned int prop,
+ 				union extcon_property_value *prop_val)
+ {
+ 	return 0;
+ }
+-static inline int extcon_set_property(struct extcon_dev *edev, unsigned int id,
+-				unsigned int prop,
+-				union extcon_property_value prop_val)
+-{
+-	return 0;
+-}
+-
+-static inline int extcon_set_property_sync(struct extcon_dev *edev,
+-				unsigned int id, unsigned int prop,
+-				union extcon_property_value prop_val)
+-{
+-	return 0;
+-}
+ 
+ static inline int extcon_get_property_capability(struct extcon_dev *edev,
+ 				unsigned int id, unsigned int prop)
+@@ -348,12 +255,6 @@ static inline int extcon_get_property_capability(struct extcon_dev *edev,
+ 	return 0;
+ }
+ 
+-static inline int extcon_set_property_capability(struct extcon_dev *edev,
+-				unsigned int id, unsigned int prop)
+-{
+-	return 0;
+-}
+-
+ static inline int extcon_register_notifier(struct extcon_dev *edev,
+ 				unsigned int id, struct notifier_block *nb)
+ {
+diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
+index 6dec43826303..3c8568aa82a5 100644
+--- a/include/linux/mfd/palmas.h
++++ b/include/linux/mfd/palmas.h
+@@ -20,7 +20,7 @@
+ #include <linux/leds.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/driver.h>
+-#include <linux/extcon.h>
++#include <linux/extcon-provider.h>
+ #include <linux/of_gpio.h>
+ #include <linux/usb/phy_companion.h>
+ 
+-- 
+2.19.0
+
diff --git a/patches/0117-phy-rcar-gen3-usb2-check-dr_mode-for-otg-mode.patch b/patches/0117-phy-rcar-gen3-usb2-check-dr_mode-for-otg-mode.patch
new file mode 100644
index 00000000000000..943b180702eeaa
--- /dev/null
+++ b/patches/0117-phy-rcar-gen3-usb2-check-dr_mode-for-otg-mode.patch
@@ -0,0 +1,66 @@
+From 65e4bd402be9b3c6456ad68d428938b1f6e433c1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 12 Oct 2017 15:34:45 +0900
+Subject: [PATCH 0117/1795] phy: rcar-gen3-usb2: check dr_mode for otg mode
+
+The previous code assumed a channel has otg capability if a channel
+has interrupt property. But, it is not good because:
+ - Battery charging feature also needs interrupt property.
+ - Some R-Car Gen3 SoCs (e.g. R-Car D3) don't have OTG capability.
+
+So, this patch checks whether usb 2.0 host node has dr_mode property or
+not. If it has 'dr_mode = "otg";', this driver enables otg capability.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 7e0540f41332cb07055c5fe6629dc83c71974c82)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+index b33e2994ccce..cc70dca47212 100644
+--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
++++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+@@ -1,7 +1,7 @@
+ /*
+  * Renesas R-Car Gen3 for USB2.0 PHY driver
+  *
+- * Copyright (C) 2015 Renesas Electronics Corporation
++ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+  *
+  * This is based on the phy-rcar-gen2 driver:
+  * Copyright (C) 2014 Renesas Solutions Corp.
+@@ -22,6 +22,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/usb/of.h>
+ #include <linux/workqueue.h>
+ 
+ /******* USB2.0 Host registers (original offset is +0x200) *******/
+@@ -415,13 +416,16 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
+ 	/* call request_irq for OTG */
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq >= 0) {
+-		int ret;
+-
+ 		INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
+ 		irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
+ 				       IRQF_SHARED, dev_name(dev), channel);
+ 		if (irq < 0)
+ 			dev_err(dev, "No irq handler (%d)\n", irq);
++	}
++
++	if (of_usb_get_dr_mode_by_phy(dev->of_node, 0) == USB_DR_MODE_OTG) {
++		int ret;
++
+ 		channel->has_otg = true;
+ 		channel->extcon = devm_extcon_dev_allocate(dev,
+ 							rcar_gen3_phy_cable);
+-- 
+2.19.0
+
diff --git a/patches/0118-phy-rcar-gen3-usb2-use-enum-phy_mode-in-the-role_sto.patch b/patches/0118-phy-rcar-gen3-usb2-use-enum-phy_mode-in-the-role_sto.patch
new file mode 100644
index 00000000000000..f355edf2583b9c
--- /dev/null
+++ b/patches/0118-phy-rcar-gen3-usb2-use-enum-phy_mode-in-the-role_sto.patch
@@ -0,0 +1,78 @@
+From 915e2b2c574fa47b88bbff81a8ed18ac8c5b3b51 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 12 Oct 2017 15:34:46 +0900
+Subject: [PATCH 0118/1795] phy: rcar-gen3-usb2: use enum phy_mode in the
+ role_store()
+
+This patch modifies the role_store() to use "enum phy_mode" instead
+of the local "bool" for host/device mode selection.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit b56acc82f9719d6aa1c1003ac7e34391da85a824)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 29 +++++++++++++++---------
+ 1 file changed, 18 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+index cc70dca47212..e77bc50bfc26 100644
+--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
++++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+@@ -219,33 +219,40 @@ static bool rcar_gen3_is_host(struct rcar_gen3_chan *ch)
+ 	return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI);
+ }
+ 
++static enum phy_mode rcar_gen3_get_phy_mode(struct rcar_gen3_chan *ch)
++{
++	if (rcar_gen3_is_host(ch))
++		return PHY_MODE_USB_HOST;
++
++	return PHY_MODE_USB_DEVICE;
++}
++
+ static ssize_t role_store(struct device *dev, struct device_attribute *attr,
+ 			  const char *buf, size_t count)
+ {
+ 	struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
+-	bool is_b_device, is_host, new_mode_is_host;
++	bool is_b_device;
++	enum phy_mode cur_mode, new_mode;
+ 
+ 	if (!ch->has_otg || !ch->phy->init_count)
+ 		return -EIO;
+ 
+-	/*
+-	 * is_b_device: true is B-Device. false is A-Device.
+-	 * If {new_mode_}is_host: true is Host mode. false is Peripheral mode.
+-	 */
+-	is_b_device = rcar_gen3_check_id(ch);
+-	is_host = rcar_gen3_is_host(ch);
+ 	if (!strncmp(buf, "host", strlen("host")))
+-		new_mode_is_host = true;
++		new_mode = PHY_MODE_USB_HOST;
+ 	else if (!strncmp(buf, "peripheral", strlen("peripheral")))
+-		new_mode_is_host = false;
++		new_mode = PHY_MODE_USB_DEVICE;
+ 	else
+ 		return -EINVAL;
+ 
++	/* is_b_device: true is B-Device. false is A-Device. */
++	is_b_device = rcar_gen3_check_id(ch);
++	cur_mode = rcar_gen3_get_phy_mode(ch);
++
+ 	/* If current and new mode is the same, this returns the error */
+-	if (is_host == new_mode_is_host)
++	if (cur_mode == new_mode)
+ 		return -EINVAL;
+ 
+-	if (new_mode_is_host) {		/* And is_host must be false */
++	if (new_mode == PHY_MODE_USB_HOST) { /* And is_host must be false */
+ 		if (!is_b_device)	/* A-Peripheral */
+ 			rcar_gen3_init_from_a_peri_to_a_host(ch);
+ 		else			/* B-Peripheral */
+-- 
+2.19.0
+
diff --git a/patches/0119-phy-rcar-gen3-usb2-add-SoC-specific-parameter-for-de.patch b/patches/0119-phy-rcar-gen3-usb2-add-SoC-specific-parameter-for-de.patch
new file mode 100644
index 00000000000000..d268903a881b35
--- /dev/null
+++ b/patches/0119-phy-rcar-gen3-usb2-add-SoC-specific-parameter-for-de.patch
@@ -0,0 +1,130 @@
+From 6b9daa7867c82371d4105f4b8dca8ba3ebc88c11 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 12 Oct 2017 15:34:47 +0900
+Subject: [PATCH 0119/1795] phy: rcar-gen3-usb2: add SoC-specific parameter for
+ dedicated pins
+
+This patch adds SoC-specific parameter to avoid reading/writing
+specific registers wrongly if this driver runs on a SoC which doesn't
+have dedicated pins (e.g. R-Car D3). This patch also changes the
+value "has_otg" to "has_otg_pins" for slightly easier reading of
+the code.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 9adaaa9e4517afb8c5cb8931cc4ea0f81f54d396)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 31 ++++++++++++++++--------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+index e77bc50bfc26..9c90e7d67e0a 100644
+--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
++++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+@@ -18,6 +18,7 @@
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
++#include <linux/of_device.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+@@ -80,6 +81,8 @@
+ #define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
+ #define USB2_ADPCTRL_DRVVBUS		BIT(4)
+ 
++#define RCAR_GEN3_PHY_HAS_DEDICATED_PINS	1
++
+ struct rcar_gen3_chan {
+ 	void __iomem *base;
+ 	struct extcon_dev *extcon;
+@@ -87,7 +90,7 @@ struct rcar_gen3_chan {
+ 	struct regulator *vbus;
+ 	struct work_struct work;
+ 	bool extcon_host;
+-	bool has_otg;
++	bool has_otg_pins;
+ };
+ 
+ static void rcar_gen3_phy_usb2_work(struct work_struct *work)
+@@ -234,7 +237,7 @@ static ssize_t role_store(struct device *dev, struct device_attribute *attr,
+ 	bool is_b_device;
+ 	enum phy_mode cur_mode, new_mode;
+ 
+-	if (!ch->has_otg || !ch->phy->init_count)
++	if (!ch->has_otg_pins || !ch->phy->init_count)
+ 		return -EIO;
+ 
+ 	if (!strncmp(buf, "host", strlen("host")))
+@@ -272,7 +275,7 @@ static ssize_t role_show(struct device *dev, struct device_attribute *attr,
+ {
+ 	struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
+ 
+-	if (!ch->has_otg || !ch->phy->init_count)
++	if (!ch->has_otg_pins || !ch->phy->init_count)
+ 		return -EIO;
+ 
+ 	return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" :
+@@ -311,7 +314,7 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
+ 	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
+ 
+ 	/* Initialize otg part */
+-	if (channel->has_otg)
++	if (channel->has_otg_pins)
+ 		rcar_gen3_init_otg(channel);
+ 
+ 	return 0;
+@@ -385,9 +388,17 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
+ }
+ 
+ static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
+-	{ .compatible = "renesas,usb2-phy-r8a7795" },
+-	{ .compatible = "renesas,usb2-phy-r8a7796" },
+-	{ .compatible = "renesas,rcar-gen3-usb2-phy" },
++	{
++		.compatible = "renesas,usb2-phy-r8a7795",
++		.data = (void *)RCAR_GEN3_PHY_HAS_DEDICATED_PINS,
++	},
++	{
++		.compatible = "renesas,usb2-phy-r8a7796",
++		.data = (void *)RCAR_GEN3_PHY_HAS_DEDICATED_PINS,
++	},
++	{
++		.compatible = "renesas,rcar-gen3-usb2-phy",
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
+@@ -433,7 +444,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
+ 	if (of_usb_get_dr_mode_by_phy(dev->of_node, 0) == USB_DR_MODE_OTG) {
+ 		int ret;
+ 
+-		channel->has_otg = true;
++		channel->has_otg_pins = (uintptr_t)of_device_get_match_data(dev);
+ 		channel->extcon = devm_extcon_dev_allocate(dev,
+ 							rcar_gen3_phy_cable);
+ 		if (IS_ERR(channel->extcon))
+@@ -475,7 +486,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
+ 		dev_err(dev, "Failed to register PHY provider\n");
+ 		ret = PTR_ERR(provider);
+ 		goto error;
+-	} else if (channel->has_otg) {
++	} else if (channel->has_otg_pins) {
+ 		int ret;
+ 
+ 		ret = device_create_file(dev, &dev_attr_role);
+@@ -495,7 +506,7 @@ static int rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
+ {
+ 	struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
+ 
+-	if (channel->has_otg)
++	if (channel->has_otg_pins)
+ 		device_remove_file(&pdev->dev, &dev_attr_role);
+ 
+ 	pm_runtime_disable(&pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0120-phy-rcar-gen3-usb2-add-binding-for-r8a77995.patch b/patches/0120-phy-rcar-gen3-usb2-add-binding-for-r8a77995.patch
new file mode 100644
index 00000000000000..3f2fdef95ad40e
--- /dev/null
+++ b/patches/0120-phy-rcar-gen3-usb2-add-binding-for-r8a77995.patch
@@ -0,0 +1,38 @@
+From a4520dd0632c61b1367f8fbaca8328999e9557d8 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 12 Oct 2017 15:34:48 +0900
+Subject: [PATCH 0120/1795] phy: rcar-gen3-usb2: add binding for r8a77995
+
+This patch adds binding for r8a77995 (R-Car D3). Since r8a77995 doesn't
+have dedicated pins (ID, VBUS), this will match against the generic
+fallback on R-Car D3.
+
+For now, this driver doesn't support usb role swap for r8a77995.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 6100ef093ba7b99efbb8b6c62b6af3c72fc82ddb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+index ace9cce2704a..99b651b33110 100644
+--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
++++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+@@ -8,6 +8,8 @@ Required properties:
+ 	      SoC.
+ 	      "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
+ 	      SoC.
++	      "renesas,usb2-phy-r8a77995" if the device is a part of an
++	      R8A77995 SoC.
+ 	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
+ 
+ 	      When compatible with the generic version, nodes must list the
+-- 
+2.19.0
+
diff --git a/patches/0121-dt-bindings-pwm-Add-R-Car-D3-device-tree-bindings.patch b/patches/0121-dt-bindings-pwm-Add-R-Car-D3-device-tree-bindings.patch
new file mode 100644
index 00000000000000..4d3fa3fbf2a767
--- /dev/null
+++ b/patches/0121-dt-bindings-pwm-Add-R-Car-D3-device-tree-bindings.patch
@@ -0,0 +1,33 @@
+From 663c5d382d9ce7d3f58031ebcc8478dee7d685b2 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 4 Oct 2017 19:10:38 +0900
+Subject: [PATCH 0121/1795] dt-bindings: pwm: Add R-Car D3 device tree bindings
+
+Add device tree bindings for the PWM controller found on R-Car D3 SoCs.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit ccb4e74aebb6fbd56fc6783f4d5c6ded48bc2f5d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+index 7e94b802395d..74c118015980 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+@@ -9,6 +9,7 @@ Required Properties:
+  - "renesas,pwm-r8a7794": for R-Car E2
+  - "renesas,pwm-r8a7795": for R-Car H3
+  - "renesas,pwm-r8a7796": for R-Car M3-W
++ - "renesas,pwm-r8a77995": for R-Car D3
+ - reg: base address and length of the registers block for the PWM.
+ - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+   the cells format.
+-- 
+2.19.0
+
diff --git a/patches/0122-ravb-document-R8A77970-bindings.patch b/patches/0122-ravb-document-R8A77970-bindings.patch
new file mode 100644
index 00000000000000..ef9f45822ed7e0
--- /dev/null
+++ b/patches/0122-ravb-document-R8A77970-bindings.patch
@@ -0,0 +1,43 @@
+From 7d2c95da8aa6b9262313b280a3e7bb09cfe598da Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:02:08 +0300
+Subject: [PATCH 0122/1795] ravb: document R8A77970 bindings
+
+R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible EtherAVB
+device, so document  the SoC specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 785ec87483d1e24a012ecf642ee7d07c4118f142)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index 16723535e1aa..2689211d324c 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -17,6 +17,7 @@ Required properties:
+ 
+       - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+       - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
++      - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
+       - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ 		R-Car Gen3 devices.
+ 
+@@ -40,7 +41,7 @@ Optional properties:
+ - interrupt-parent: the phandle for the interrupt controller that services
+ 		    interrupts for this device.
+ - interrupt-names: A list of interrupt names.
+-		   For the R8A779[56] SoCs this property is mandatory;
++		   For the R-Car Gen 3 SoCs this property is mandatory;
+ 		   it should include one entry per channel, named "ch%u",
+ 		   where %u is the channel number ranging from 0 to 24.
+ 		   For other SoCs this property is optional; if present
+-- 
+2.19.0
+
diff --git a/patches/0123-dt-bindings-net-renesas-ravb-Add-support-for-R8A7799.patch b/patches/0123-dt-bindings-net-renesas-ravb-Add-support-for-R8A7799.patch
new file mode 100644
index 00000000000000..954dc11952d4ef
--- /dev/null
+++ b/patches/0123-dt-bindings-net-renesas-ravb-Add-support-for-R8A7799.patch
@@ -0,0 +1,35 @@
+From 5075f1be625364ba3f2618d3ffd86818ffcee05b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 09:06:38 +0900
+Subject: [PATCH 0123/1795] dt-bindings: net: renesas-ravb: Add support for
+ R8A77995 RAVB
+
+Add a new compatible string for the R8A77995 (R-Car D3) RAVB.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit f231c4178a655b09c1fe4dce4b09de7b867c20af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index 2689211d324c..c902261893b9 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -18,6 +18,7 @@ Required properties:
+       - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+       - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+       - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
++      - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
+       - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ 		R-Car Gen3 devices.
+ 
+-- 
+2.19.0
+
diff --git a/patches/0124-ravb-RX-checksum-offload.patch b/patches/0124-ravb-RX-checksum-offload.patch
new file mode 100644
index 00000000000000..b23e91f0863771
--- /dev/null
+++ b/patches/0124-ravb-RX-checksum-offload.patch
@@ -0,0 +1,194 @@
+From ba2d31b8fd93bc2a7bd5787aa89e33038709a107 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 4 Oct 2017 09:54:27 +0200
+Subject: [PATCH 0124/1795] ravb: RX checksum offload
+
+Add support for RX checksum offload. This is enabled by default and
+may be disabled and re-enabled using ethtool:
+
+ # ethtool -K eth0 rx off
+ # ethtool -K eth0 rx on
+
+The RAVB provides a simple checksumming scheme which appears to be
+completely compatible with CHECKSUM_COMPLETE: sum of all packet data after
+the L2 header is appended to packet data; this may be trivially read by the
+driver and used to update the skb accordingly.
+
+In terms of performance throughput is close to gigabit line-rate both with
+and without RX checksum offload enabled. Perf output, however, appears to
+indicate that significantly less time is spent in do_csum(). This is as
+expected.
+
+Test results with RX checksum offload enabled:
+ # /usr/bin/perf_3.16 record -o /run/perf.data -a netperf -t TCP_MAERTS -H 10.4.3.162
+ MIGRATED TCP MAERTS TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 10.4.3.162 () port 0 AF_INET : demo
+ enable_enobufs failed: getprotobyname
+ Recv   Send    Send
+ Socket Socket  Message  Elapsed
+ Size   Size    Size     Time     Throughput
+ bytes  bytes   bytes    secs.    10^6bits/sec
+
+  87380  16384  16384    10.00     937.54
+
+ Summary of output of perf report:
+    18.28%      ksoftirqd/0  [kernel.kallsyms]  [k] _raw_spin_unlock_irqrestore
+    10.34%      ksoftirqd/0  [kernel.kallsyms]  [k] __pi_memcpy
+     9.83%      ksoftirqd/0  [kernel.kallsyms]  [k] ravb_poll
+     7.89%      ksoftirqd/0  [kernel.kallsyms]  [k] skb_put
+     4.01%      ksoftirqd/0  [kernel.kallsyms]  [k] dev_gro_receive
+     3.37%          netperf  [kernel.kallsyms]  [k] __arch_copy_to_user
+     3.17%          swapper  [kernel.kallsyms]  [k] arch_cpu_idle
+     2.55%          swapper  [kernel.kallsyms]  [k] tick_nohz_idle_enter
+     2.04%      ksoftirqd/0  [kernel.kallsyms]  [k] __pi___inval_dcache_area
+     2.03%          swapper  [kernel.kallsyms]  [k] _raw_spin_unlock_irq
+     1.96%      ksoftirqd/0  [kernel.kallsyms]  [k] __netdev_alloc_skb
+     1.59%      ksoftirqd/0  [kernel.kallsyms]  [k] __slab_alloc.isra.83
+
+Test results without RX checksum offload enabled:
+ # /usr/bin/perf_3.16 record -o /run/perf.data -a netperf -t TCP_MAERTS -H 10.4.3.162
+ MIGRATED TCP MAERTS TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 10.4.3.162 () port 0 AF_INET : demo
+ enable_enobufs failed: getprotobyname
+ Recv   Send    Send
+ Socket Socket  Message  Elapsed
+ Size   Size    Size     Time     Throughput
+ bytes  bytes   bytes    secs.    10^6bits/sec
+
+  87380  16384  16384    10.00     940.20
+
+ Summary of output of perf report:
+    17.10%    ksoftirqd/0  [kernel.kallsyms]  [k] _raw_spin_unlock_irqrestore
+    10.99%    ksoftirqd/0  [kernel.kallsyms]  [k] __pi_memcpy
+     8.87%    ksoftirqd/0  [kernel.kallsyms]  [k] ravb_poll
+     8.16%    ksoftirqd/0  [kernel.kallsyms]  [k] skb_put
+     7.42%    ksoftirqd/0  [kernel.kallsyms]  [k] do_csum
+     3.91%    ksoftirqd/0  [kernel.kallsyms]  [k] dev_gro_receive
+     2.31%        swapper  [kernel.kallsyms]  [k] arch_cpu_idle
+     2.16%    ksoftirqd/0  [kernel.kallsyms]  [k] __pi___inval_dcache_area
+     2.14%    ksoftirqd/0  [kernel.kallsyms]  [k] __netdev_alloc_skb
+     1.93%        netperf  [kernel.kallsyms]  [k] __arch_copy_to_user
+     1.79%        swapper  [kernel.kallsyms]  [k] tick_nohz_idle_enter
+     1.63%    ksoftirqd/0  [kernel.kallsyms]  [k] __slab_alloc.isra.83
+
+Above results collected on an R-Car Gen 3 Salvator-X/r8a7796 ES1.0.
+Also tested on a R-Car Gen 3 Salvator-X/r8a7795 ES1.0.
+
+By inspection this also appears to be compatible with the ravb found
+on R-Car Gen 2 SoCs, however, this patch is currently untested on such
+hardware.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4d86d38186271438ef002c5ae6e04836f01bf8bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 55 +++++++++++++++++++++++-
+ 1 file changed, 54 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index e87a779bfcfe..28b6a9f599bf 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -403,8 +403,9 @@ static void ravb_emac_init(struct net_device *ndev)
+ 	/* Receive frame limit set register */
+ 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
+ 
+-	/* PAUSE prohibition */
++	/* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
+ 	ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
++		   (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
+ 		   ECMR_TE | ECMR_RE, ECMR);
+ 
+ 	ravb_set_rate(ndev);
+@@ -520,6 +521,19 @@ static void ravb_get_tx_tstamp(struct net_device *ndev)
+ 	}
+ }
+ 
++static void ravb_rx_csum(struct sk_buff *skb)
++{
++	u8 *hw_csum;
++
++	/* The hardware checksum is 2 bytes appended to packet data */
++	if (unlikely(skb->len < 2))
++		return;
++	hw_csum = skb_tail_pointer(skb) - 2;
++	skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
++	skb->ip_summed = CHECKSUM_COMPLETE;
++	skb_trim(skb, skb->len - 2);
++}
++
+ /* Packet receive function for Ethernet AVB */
+ static bool ravb_rx(struct net_device *ndev, int *quota, int q)
+ {
+@@ -587,8 +601,11 @@ static bool ravb_rx(struct net_device *ndev, int *quota, int q)
+ 				ts.tv_nsec = le32_to_cpu(desc->ts_n);
+ 				shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
+ 			}
++
+ 			skb_put(skb, pkt_len);
+ 			skb->protocol = eth_type_trans(skb, ndev);
++			if (ndev->features & NETIF_F_RXCSUM)
++				ravb_rx_csum(skb);
+ 			napi_gro_receive(&priv->napi[q], skb);
+ 			stats->rx_packets++;
+ 			stats->rx_bytes += pkt_len;
+@@ -1818,6 +1835,38 @@ static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+ 	return phy_mii_ioctl(phydev, req, cmd);
+ }
+ 
++static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
++{
++	struct ravb_private *priv = netdev_priv(ndev);
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	/* Disable TX and RX */
++	ravb_rcv_snd_disable(ndev);
++
++	/* Modify RX Checksum setting */
++	ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
++
++	/* Enable TX and RX */
++	ravb_rcv_snd_enable(ndev);
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static int ravb_set_features(struct net_device *ndev,
++			     netdev_features_t features)
++{
++	netdev_features_t changed = ndev->features ^ features;
++
++	if (changed & NETIF_F_RXCSUM)
++		ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
++
++	ndev->features = features;
++
++	return 0;
++}
++
+ static const struct net_device_ops ravb_netdev_ops = {
+ 	.ndo_open		= ravb_open,
+ 	.ndo_stop		= ravb_close,
+@@ -1829,6 +1878,7 @@ static const struct net_device_ops ravb_netdev_ops = {
+ 	.ndo_do_ioctl		= ravb_do_ioctl,
+ 	.ndo_validate_addr	= eth_validate_addr,
+ 	.ndo_set_mac_address	= eth_mac_addr,
++	.ndo_set_features	= ravb_set_features,
+ };
+ 
+ /* MDIO bus init function */
+@@ -1980,6 +2030,9 @@ static int ravb_probe(struct platform_device *pdev)
+ 	if (!ndev)
+ 		return -ENOMEM;
+ 
++	ndev->features = NETIF_F_RXCSUM;
++	ndev->hw_features = NETIF_F_RXCSUM;
++
+ 	pm_runtime_enable(&pdev->dev);
+ 	pm_runtime_get_sync(&pdev->dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0125-ravb-Consolidate-clock-handling.patch b/patches/0125-ravb-Consolidate-clock-handling.patch
new file mode 100644
index 00000000000000..7d7b2d5f544a73
--- /dev/null
+++ b/patches/0125-ravb-Consolidate-clock-handling.patch
@@ -0,0 +1,108 @@
+From d390b94ad08a6a4112c25be438d9e21173a689c0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 10:24:53 +0200
+Subject: [PATCH 0125/1795] ravb: Consolidate clock handling
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The module clock is used for two purposes:
+  - Wake-on-LAN (WoL), which is optional,
+  - gPTP Timer Increment (GTI) configuration, which is mandatory.
+
+As the clock is needed for GTI configuration anyway, WoL is always
+available.  Hence remove duplication and repeated obtaining of the clock
+by making GTI use the stored clock for WoL use.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit ab104615e01c2c4cbe9ea4073a430d51f6547dd2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 35 +++++++-----------------
+ 1 file changed, 10 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 28b6a9f599bf..9297fbbab0fe 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1330,20 +1330,15 @@ static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ {
+ 	struct ravb_private *priv = netdev_priv(ndev);
+ 
+-	wol->supported = 0;
+-	wol->wolopts = 0;
+-
+-	if (priv->clk) {
+-		wol->supported = WAKE_MAGIC;
+-		wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
+-	}
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
+ }
+ 
+ static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ {
+ 	struct ravb_private *priv = netdev_priv(ndev);
+ 
+-	if (!priv->clk || wol->wolopts & ~WAKE_MAGIC)
++	if (wol->wolopts & ~WAKE_MAGIC)
+ 		return -EOPNOTSUPP;
+ 
+ 	priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
+@@ -1938,22 +1933,12 @@ MODULE_DEVICE_TABLE(of, ravb_match_table);
+ 
+ static int ravb_set_gti(struct net_device *ndev)
+ {
+-
++	struct ravb_private *priv = netdev_priv(ndev);
+ 	struct device *dev = ndev->dev.parent;
+-	struct device_node *np = dev->of_node;
+ 	unsigned long rate;
+-	struct clk *clk;
+ 	uint64_t inc;
+ 
+-	clk = of_clk_get(np, 0);
+-	if (IS_ERR(clk)) {
+-		dev_err(dev, "could not get clock\n");
+-		return PTR_ERR(clk);
+-	}
+-
+-	rate = clk_get_rate(clk);
+-	clk_put(clk);
+-
++	rate = clk_get_rate(priv->clk);
+ 	if (!rate)
+ 		return -EINVAL;
+ 
+@@ -2102,10 +2087,11 @@ static int ravb_probe(struct platform_device *pdev)
+ 
+ 	priv->chip_id = chip_id;
+ 
+-	/* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
+ 	priv->clk = devm_clk_get(&pdev->dev, NULL);
+-	if (IS_ERR(priv->clk))
+-		priv->clk = NULL;
++	if (IS_ERR(priv->clk)) {
++		error = PTR_ERR(priv->clk);
++		goto out_release;
++	}
+ 
+ 	/* Set function */
+ 	ndev->netdev_ops = &ravb_netdev_ops;
+@@ -2173,8 +2159,7 @@ static int ravb_probe(struct platform_device *pdev)
+ 	if (error)
+ 		goto out_napi_del;
+ 
+-	if (priv->clk)
+-		device_set_wakeup_capable(&pdev->dev, 1);
++	device_set_wakeup_capable(&pdev->dev, 1);
+ 
+ 	/* Print device information */
+ 	netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
+-- 
+2.19.0
+
diff --git a/patches/0126-Revert-ravb-add-workaround-for-clock-when-resuming-w.patch b/patches/0126-Revert-ravb-add-workaround-for-clock-when-resuming-w.patch
new file mode 100644
index 00000000000000..6396b58f3a6fed
--- /dev/null
+++ b/patches/0126-Revert-ravb-add-workaround-for-clock-when-resuming-w.patch
@@ -0,0 +1,67 @@
+From 245dbeb37ce16ca73a8710adbf9fcf843fefc654 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Dec 2017 09:54:09 +0100
+Subject: [PATCH 0126/1795] Revert "ravb: add workaround for clock when
+ resuming with WoL enabled"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit fbf3d034f2ff6264183cfa6845770e8cc2a986c8.
+
+As of commit 560869100b99a3da ("clk: renesas: cpg-mssr: Restore module
+clocks during resume"), the workaround is no longer needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 6b782f43d34974c7909306fd9af06241d658a1f7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 27 ++----------------------
+ 1 file changed, 2 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 9297fbbab0fe..98e82669d41d 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -2284,32 +2284,9 @@ static int __maybe_unused ravb_resume(struct device *dev)
+ 	struct ravb_private *priv = netdev_priv(ndev);
+ 	int ret = 0;
+ 
+-	if (priv->wol_enabled) {
+-		/* Reduce the usecount of the clock to zero and then
+-		 * restore it to its original value. This is done to force
+-		 * the clock to be re-enabled which is a workaround
+-		 * for renesas-cpg-mssr driver which do not enable clocks
+-		 * when resuming from PSCI suspend/resume.
+-		 *
+-		 * Without this workaround the driver fails to communicate
+-		 * with the hardware if WoL was enabled when the system
+-		 * entered PSCI suspend. This is due to that if WoL is enabled
+-		 * we explicitly keep the clock from being turned off when
+-		 * suspending, but in PSCI sleep power is cut so the clock
+-		 * is disabled anyhow, the clock driver is not aware of this
+-		 * so the clock is not turned back on when resuming.
+-		 *
+-		 * TODO: once the renesas-cpg-mssr suspend/resume is working
+-		 *       this clock dance should be removed.
+-		 */
+-		clk_disable(priv->clk);
+-		clk_disable(priv->clk);
+-		clk_enable(priv->clk);
+-		clk_enable(priv->clk);
+-
+-		/* Set reset mode to rearm the WoL logic */
++	/* If WoL is enabled set reset mode to rearm the WoL logic */
++	if (priv->wol_enabled)
+ 		ravb_write(ndev, CCC_OPC_RESET, CCC);
+-	}
+ 
+ 	/* All register have been reset to default values.
+ 	 * Restore all registers which where setup at probe time and
+-- 
+2.19.0
+
diff --git a/patches/0127-drm-rcar-du-Use-drm_gem_fb_create.patch b/patches/0127-drm-rcar-du-Use-drm_gem_fb_create.patch
new file mode 100644
index 00000000000000..d7d9d4924856d7
--- /dev/null
+++ b/patches/0127-drm-rcar-du-Use-drm_gem_fb_create.patch
@@ -0,0 +1,46 @@
+From 2b15e6a044cc08dfb821cbd8c98753f3229fc6c5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
+Date: Sun, 24 Sep 2017 14:26:21 +0200
+Subject: [PATCH 0127/1795] drm/rcar-du: Use drm_gem_fb_create()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+drm_fb_cma_create() is just a wrapper around drm_gem_fb_create() now,
+so use the function directly.
+
+Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Link: https://patchwork.freedesktop.org/patch/msgid/1506255985-61113-7-git-send-email-noralf@tronnes.org
+(cherry picked from commit 365c38517827b8efd4009b5221fff320775a5f83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index 7278b9703c15..566d1a948c8f 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -18,6 +18,7 @@
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
++#include <drm/drm_gem_framebuffer_helper.h>
+ 
+ #include <linux/of_graph.h>
+ #include <linux/wait.h>
+@@ -213,7 +214,7 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
+ 		}
+ 	}
+ 
+-	return drm_fb_cma_create(dev, file_priv, mode_cmd);
++	return drm_gem_fb_create(dev, file_priv, mode_cmd);
+ }
+ 
+ static void rcar_du_output_poll_changed(struct drm_device *dev)
+-- 
+2.19.0
+
diff --git a/patches/0128-media-drivers-remove-from-non-kernel-doc-comments.patch b/patches/0128-media-drivers-remove-from-non-kernel-doc-comments.patch
new file mode 100644
index 00000000000000..f3686ae3687caf
--- /dev/null
+++ b/patches/0128-media-drivers-remove-from-non-kernel-doc-comments.patch
@@ -0,0 +1,498 @@
+From 1d3b8f82b671f5096bc11894de40d9546af05886 Mon Sep 17 00:00:00 2001
+From: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+Date: Wed, 29 Nov 2017 08:33:45 -0500
+Subject: [PATCH 0128/1795] media: drivers: remove "/**" from non-kernel-doc
+ comments
+
+Several comments are wrongly tagged as kernel-doc, causing
+those warnings:
+
+  drivers/media/rc/st_rc.c:98: warning: No description found for parameter 'irq'
+  drivers/media/rc/st_rc.c:98: warning: No description found for parameter 'data'
+  drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'solo_dev'
+  drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'ch'
+  drivers/media/pci/solo6x10/solo6x10-enc.c:183: warning: No description found for parameter 'qp'
+  drivers/media/usb/pwc/pwc-dec23.c:652: warning: Cannot understand  *
+   on line 652 - I thought it was a doc line
+  drivers/media/usb/dvb-usb/cinergyT2-fe.c:40: warning: No description found for parameter 'op'
+  drivers/media/usb/dvb-usb/friio-fe.c:301: warning: Cannot understand  * (reg, val) commad list to initialize this module.
+   on line 301 - I thought it was a doc line
+  drivers/media/rc/streamzap.c:201: warning: No description found for parameter 'urb'
+  drivers/media/rc/streamzap.c:333: warning: No description found for parameter 'intf'
+  drivers/media/rc/streamzap.c:333: warning: No description found for parameter 'id'
+  drivers/media/rc/streamzap.c:464: warning: No description found for parameter 'interface'
+  drivers/media/i2c/ov5647.c:432: warning: Cannot understand  * @short Subdev core operations registration
+   on line 432 - I thought it was a doc line
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'd'
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'addr'
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'wbuf'
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'wlen'
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'rbuf'
+  drivers/media/usb/dvb-usb/friio.c:35: warning: No description found for parameter 'rlen'
+  drivers/media/platform/vim2m.c:350: warning: No description found for parameter 'priv'
+  drivers/media/dvb-frontends/tua6100.c:34: warning: cannot understand function prototype: 'struct tua6100_priv '
+  drivers/media/platform/sti/hva/hva-h264.c:140: warning: cannot understand function prototype: 'struct hva_h264_stereo_video_sei '
+  drivers/media/platform/sti/hva/hva-h264.c:150: warning: Cannot understand  * @frame_width: width in pixels of the buffer containing the input frame
+   on line 150 - I thought it was a doc line
+  drivers/media/platform/sti/hva/hva-h264.c:356: warning: Cannot understand  * @ slice_size: slice size
+   on line 356 - I thought it was a doc line
+  drivers/media/platform/sti/hva/hva-h264.c:369: warning: Cannot understand  * @ bitstream_size: bitstream size
+   on line 369 - I thought it was a doc line
+  drivers/media/platform/sti/hva/hva-h264.c:395: warning: Cannot understand  * @seq_info:  sequence information buffer
+   on line 395 - I thought it was a doc line
+  drivers/media/dvb-frontends/sp887x.c:137: warning: No description found for parameter 'fe'
+  drivers/media/dvb-frontends/sp887x.c:137: warning: No description found for parameter 'fw'
+  drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'n'
+  drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'd'
+  drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'quotient_i'
+  drivers/media/dvb-frontends/sp887x.c:287: warning: No description found for parameter 'quotient_f'
+  drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c:83: warning: cannot understand function prototype: 'struct ttusb '
+  drivers/media/platform/sh_veu.c:277: warning: No description found for parameter 'priv'
+  drivers/media/dvb-frontends/zl10036.c:33: warning: cannot understand function prototype: 'int zl10036_debug; '
+  drivers/media/dvb-frontends/zl10036.c:179: warning: No description found for parameter 'state'
+  drivers/media/dvb-frontends/zl10036.c:179: warning: No description found for parameter 'frequency'
+  drivers/media/platform/rcar_fdp1.c:1139: warning: No description found for parameter 'priv'
+  drivers/media/platform/ti-vpe/vpe.c:933: warning: No description found for parameter 'priv'
+  drivers/media/usb/gspca/ov519.c:36: warning: No description found for parameter 'fmt'
+  drivers/media/usb/dvb-usb/dib0700_devices.c:3367: warning: No description found for parameter 'adap'
+
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit cba862dc7301d62f90393f2bbb181834a3125308)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/dvb-frontends/sp887x.c           |  6 +++---
+ drivers/media/dvb-frontends/tua6100.c          |  2 +-
+ drivers/media/dvb-frontends/zl10036.c          |  8 ++++----
+ drivers/media/i2c/ov5647.c                     |  4 ++--
+ drivers/media/pci/solo6x10/solo6x10-enc.c      |  2 +-
+ drivers/media/platform/rcar_fdp1.c             |  2 +-
+ drivers/media/platform/sh_veu.c                |  2 +-
+ drivers/media/platform/sti/hva/hva-h264.c      | 18 +++++++++++++-----
+ drivers/media/platform/ti-vpe/vpe.c            |  2 +-
+ drivers/media/platform/vim2m.c                 |  2 +-
+ drivers/media/rc/st_rc.c                       |  6 +++---
+ drivers/media/rc/streamzap.c                   |  6 +++---
+ drivers/media/usb/dvb-usb/cinergyT2-fe.c       |  2 +-
+ drivers/media/usb/dvb-usb/dib0700_devices.c    |  8 ++++----
+ drivers/media/usb/dvb-usb/friio-fe.c           |  2 +-
+ drivers/media/usb/dvb-usb/friio.c              |  2 +-
+ drivers/media/usb/gspca/ov519.c                |  2 +-
+ drivers/media/usb/pwc/pwc-dec23.c              |  7 +++----
+ .../media/usb/ttusb-budget/dvb-ttusb-budget.c  |  6 +++---
+ 19 files changed, 48 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/media/dvb-frontends/sp887x.c b/drivers/media/dvb-frontends/sp887x.c
+index 7c511c3cd4ca..d2c402b52c6e 100644
+--- a/drivers/media/dvb-frontends/sp887x.c
++++ b/drivers/media/dvb-frontends/sp887x.c
+@@ -57,7 +57,7 @@ static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data)
+ 	int ret;
+ 
+ 	if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) {
+-		/**
++		/*
+ 		 *  in case of soft reset we ignore ACK errors...
+ 		 */
+ 		if (!(reg == 0xf1a && data == 0x000 &&
+@@ -130,7 +130,7 @@ static void sp887x_setup_agc (struct sp887x_state* state)
+ 
+ #define BLOCKSIZE 30
+ #define FW_SIZE 0x4000
+-/**
++/*
+  *  load firmware and setup MPEG interface...
+  */
+ static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw)
+@@ -279,7 +279,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
+ 	return 0;
+ }
+ 
+-/**
++/*
+  *  estimates division of two 24bit numbers,
+  *  derived from the ves1820/stv0299 driver code
+  */
+diff --git a/drivers/media/dvb-frontends/tua6100.c b/drivers/media/dvb-frontends/tua6100.c
+index 18e6d4c5be21..1d41abd47f04 100644
+--- a/drivers/media/dvb-frontends/tua6100.c
++++ b/drivers/media/dvb-frontends/tua6100.c
+@@ -1,4 +1,4 @@
+-/**
++/*
+  * Driver for Infineon tua6100 pll.
+  *
+  * (c) 2006 Andrew de Quincey
+diff --git a/drivers/media/dvb-frontends/zl10036.c b/drivers/media/dvb-frontends/zl10036.c
+index 062282739ce5..89dd65ae88ad 100644
+--- a/drivers/media/dvb-frontends/zl10036.c
++++ b/drivers/media/dvb-frontends/zl10036.c
+@@ -1,4 +1,4 @@
+-/**
++/*
+  * Driver for Zarlink zl10036 DVB-S silicon tuner
+  *
+  * Copyright (C) 2006 Tino Reichardt
+@@ -157,7 +157,7 @@ static int zl10036_sleep(struct dvb_frontend *fe)
+ 	return ret;
+ }
+ 
+-/**
++/*
+  * register map of the ZL10036/ZL10038
+  *
+  * reg[default] content
+@@ -219,7 +219,7 @@ static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
+ 	if (fbw <= 28820) {
+ 		br = _BR_MAXIMUM;
+ 	} else {
+-		/**
++		/*
+ 		 *  f(bw)=34,6MHz f(xtal)=10.111MHz
+ 		 *  br = (10111/34600) * 63 * 1/K = 14;
+ 		 */
+@@ -315,7 +315,7 @@ static int zl10036_set_params(struct dvb_frontend *fe)
+ 	||  (frequency > fe->ops.info.frequency_max))
+ 		return -EINVAL;
+ 
+-	/**
++	/*
+ 	 * alpha = 1.35 for dvb-s
+ 	 * fBW = (alpha*symbolrate)/(2*0.8)
+ 	 * 1.35 / (2*0.8) = 27 / 32
+diff --git a/drivers/media/i2c/ov5647.c b/drivers/media/i2c/ov5647.c
+index 95ce90fdb876..210aa822399c 100644
+--- a/drivers/media/i2c/ov5647.c
++++ b/drivers/media/i2c/ov5647.c
+@@ -407,8 +407,8 @@ static int ov5647_sensor_set_register(struct v4l2_subdev *sd,
+ }
+ #endif
+ 
+-/**
+- * @short Subdev core operations registration
++/*
++ * Subdev core operations registration
+  */
+ static const struct v4l2_subdev_core_ops ov5647_subdev_core_ops = {
+ 	.s_power		= ov5647_sensor_power,
+diff --git a/drivers/media/pci/solo6x10/solo6x10-enc.c b/drivers/media/pci/solo6x10/solo6x10-enc.c
+index d28211bb9674..58d6b5131dd0 100644
+--- a/drivers/media/pci/solo6x10/solo6x10-enc.c
++++ b/drivers/media/pci/solo6x10/solo6x10-enc.c
+@@ -175,7 +175,7 @@ int solo_osd_print(struct solo_enc_dev *solo_enc)
+ 	return 0;
+ }
+ 
+-/**
++/*
+  * Set channel Quality Profile (0-3).
+  */
+ void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
+diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c
+index 3245bc45f4a0..b13dec3081e5 100644
+--- a/drivers/media/platform/rcar_fdp1.c
++++ b/drivers/media/platform/rcar_fdp1.c
+@@ -1132,7 +1132,7 @@ static int fdp1_device_process(struct fdp1_ctx *ctx)
+  * mem2mem callbacks
+  */
+ 
+-/**
++/*
+  * job_ready() - check whether an instance is ready to be scheduled to run
+  */
+ static int fdp1_m2m_job_ready(void *priv)
+diff --git a/drivers/media/platform/sh_veu.c b/drivers/media/platform/sh_veu.c
+index 15a562af13c7..dedc1b024f6f 100644
+--- a/drivers/media/platform/sh_veu.c
++++ b/drivers/media/platform/sh_veu.c
+@@ -267,7 +267,7 @@ static void sh_veu_process(struct sh_veu_dev *veu,
+ 	sh_veu_reg_write(veu, VEU_EIER, 1); /* enable interrupt in VEU */
+ }
+ 
+-/**
++/*
+  * sh_veu_device_run() - prepares and starts the device
+  *
+  * This will be called by the framework when it decides to schedule a particular
+diff --git a/drivers/media/platform/sti/hva/hva-h264.c b/drivers/media/platform/sti/hva/hva-h264.c
+index e6f247a983c7..d69c58211107 100644
+--- a/drivers/media/platform/sti/hva/hva-h264.c
++++ b/drivers/media/platform/sti/hva/hva-h264.c
+@@ -134,7 +134,7 @@ enum hva_h264_sei_payload_type {
+ 	SEI_FRAME_PACKING_ARRANGEMENT = 45
+ };
+ 
+-/**
++/*
+  * stereo Video Info struct
+  */
+ struct hva_h264_stereo_video_sei {
+@@ -146,7 +146,9 @@ struct hva_h264_stereo_video_sei {
+ 	u8 right_view_self_contained_flag;
+ };
+ 
+-/**
++/*
++ * struct hva_h264_td
++ *
+  * @frame_width: width in pixels of the buffer containing the input frame
+  * @frame_height: height in pixels of the buffer containing the input frame
+  * @frame_num: the parameter to be written in the slice header
+@@ -352,7 +354,9 @@ struct hva_h264_td {
+ 	u32 addr_brc_in_out_parameter;
+ };
+ 
+-/**
++/*
++ * struct hva_h264_slice_po
++ *
+  * @ slice_size: slice size
+  * @ slice_start_time: start time
+  * @ slice_stop_time: stop time
+@@ -365,7 +369,9 @@ struct hva_h264_slice_po {
+ 	u32 slice_num;
+ };
+ 
+-/**
++/*
++ * struct hva_h264_po
++ *
+  * @ bitstream_size: bitstream size
+  * @ dct_bitstream_size: dtc bitstream size
+  * @ stuffing_bits: number of stuffing bits inserted by the encoder
+@@ -391,7 +397,9 @@ struct hva_h264_task {
+ 	struct hva_h264_po po;
+ };
+ 
+-/**
++/*
++ * struct hva_h264_ctx
++ *
+  * @seq_info:  sequence information buffer
+  * @ref_frame: reference frame buffer
+  * @rec_frame: reconstructed frame buffer
+diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c
+index 45bd10544189..e395aa85c8ad 100644
+--- a/drivers/media/platform/ti-vpe/vpe.c
++++ b/drivers/media/platform/ti-vpe/vpe.c
+@@ -926,7 +926,7 @@ static struct vpe_ctx *file2ctx(struct file *file)
+  * mem2mem callbacks
+  */
+ 
+-/**
++/*
+  * job_ready() - check whether an instance is ready to be scheduled to run
+  */
+ static int job_ready(void *priv)
+diff --git a/drivers/media/platform/vim2m.c b/drivers/media/platform/vim2m.c
+index b01fba020d5f..0592f40b23f3 100644
+--- a/drivers/media/platform/vim2m.c
++++ b/drivers/media/platform/vim2m.c
+@@ -343,7 +343,7 @@ static void schedule_irq(struct vim2m_dev *dev, int msec_timeout)
+  * mem2mem callbacks
+  */
+ 
+-/**
++/*
+  * job_ready() - check whether an instance is ready to be scheduled to run
+  */
+ static int job_ready(void *priv)
+diff --git a/drivers/media/rc/st_rc.c b/drivers/media/rc/st_rc.c
+index a8e39c635f34..d2efd7b2c3bc 100644
+--- a/drivers/media/rc/st_rc.c
++++ b/drivers/media/rc/st_rc.c
+@@ -49,7 +49,7 @@ struct st_rc_device {
+ #define IRB_RX_NOISE_SUPPR      0x5c	/* noise suppression  */
+ #define IRB_RX_POLARITY_INV     0x68	/* polarity inverter  */
+ 
+-/**
++/*
+  * IRQ set: Enable full FIFO                 1  -> bit  3;
+  *          Enable overrun IRQ               1  -> bit  2;
+  *          Enable last symbol IRQ           1  -> bit  1:
+@@ -72,7 +72,7 @@ static void st_rc_send_lirc_timeout(struct rc_dev *rdev)
+ 	ir_raw_event_store(rdev, &ev);
+ }
+ 
+-/**
++/*
+  * RX graphical example to better understand the difference between ST IR block
+  * output and standard definition used by LIRC (and most of the world!)
+  *
+@@ -317,7 +317,7 @@ static int st_rc_probe(struct platform_device *pdev)
+ 	device_init_wakeup(dev, true);
+ 	dev_pm_set_wake_irq(dev, rc_dev->irq);
+ 
+-	/**
++	/*
+ 	 * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW
+ 	 * lircd expects a long space first before a signal train to sync.
+ 	 */
+diff --git a/drivers/media/rc/streamzap.c b/drivers/media/rc/streamzap.c
+index f03a174ddf9d..0fdcab8ca1b0 100644
+--- a/drivers/media/rc/streamzap.c
++++ b/drivers/media/rc/streamzap.c
+@@ -191,7 +191,7 @@ static void sz_push_half_space(struct streamzap_ir *sz,
+ 	sz_push_full_space(sz, value & SZ_SPACE_MASK);
+ }
+ 
+-/**
++/*
+  * streamzap_callback - usb IRQ handler callback
+  *
+  * This procedure is invoked on reception of data from
+@@ -321,7 +321,7 @@ static struct rc_dev *streamzap_init_rc_dev(struct streamzap_ir *sz)
+ 	return NULL;
+ }
+ 
+-/**
++/*
+  *	streamzap_probe
+  *
+  *	Called by usb-core to associated with a candidate device
+@@ -450,7 +450,7 @@ static int streamzap_probe(struct usb_interface *intf,
+ 	return retval;
+ }
+ 
+-/**
++/*
+  * streamzap_disconnect
+  *
+  * Called by the usb core when the device is removed from the system.
+diff --git a/drivers/media/usb/dvb-usb/cinergyT2-fe.c b/drivers/media/usb/dvb-usb/cinergyT2-fe.c
+index f9772ad0a2a5..5a2f81311fb7 100644
+--- a/drivers/media/usb/dvb-usb/cinergyT2-fe.c
++++ b/drivers/media/usb/dvb-usb/cinergyT2-fe.c
+@@ -26,7 +26,7 @@
+ #include "cinergyT2.h"
+ 
+ 
+-/**
++/*
+  *  convert linux-dvb frontend parameter set into TPS.
+  *  See ETSI ETS-300744, section 4.6.2, table 9 for details.
+  *
+diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c
+index 9be1e658ef47..a9968fb1e8e4 100644
+--- a/drivers/media/usb/dvb-usb/dib0700_devices.c
++++ b/drivers/media/usb/dvb-usb/dib0700_devices.c
+@@ -1678,10 +1678,10 @@ static int dib8096_set_param_override(struct dvb_frontend *fe)
+ 		return -EINVAL;
+ 	}
+ 
+-	/** Update PLL if needed ratio **/
++	/* Update PLL if needed ratio */
+ 	state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
+ 
+-	/** Get optimize PLL ratio to remove spurious **/
++	/* Get optimize PLL ratio to remove spurious */
+ 	pll_ratio = dib8090_compute_pll_parameters(fe);
+ 	if (pll_ratio == 17)
+ 		timf = 21387946;
+@@ -1692,7 +1692,7 @@ static int dib8096_set_param_override(struct dvb_frontend *fe)
+ 	else
+ 		timf = 18179756;
+ 
+-	/** Update ratio **/
++	/* Update ratio */
+ 	state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio);
+ 
+ 	state->dib8000_ops.ctrl_timf(fe, DEMOD_TIMF_SET, timf);
+@@ -3358,7 +3358,7 @@ static int novatd_sleep_override(struct dvb_frontend* fe)
+ 	return state->sleep(fe);
+ }
+ 
+-/**
++/*
+  * novatd_frontend_attach - Nova-TD specific attach
+  *
+  * Nova-TD has GPIO0, 1 and 2 for LEDs. So do not fiddle with them except for
+diff --git a/drivers/media/usb/dvb-usb/friio-fe.c b/drivers/media/usb/dvb-usb/friio-fe.c
+index 0251a4e91d47..0b108071197a 100644
+--- a/drivers/media/usb/dvb-usb/friio-fe.c
++++ b/drivers/media/usb/dvb-usb/friio-fe.c
+@@ -319,7 +319,7 @@ static int jdvbt90502_set_frontend(struct dvb_frontend *fe)
+ }
+ 
+ 
+-/**
++/*
+  * (reg, val) commad list to initialize this module.
+  *  captured on a Windows box.
+  */
+diff --git a/drivers/media/usb/dvb-usb/friio.c b/drivers/media/usb/dvb-usb/friio.c
+index 62abe6c43a32..16875945e662 100644
+--- a/drivers/media/usb/dvb-usb/friio.c
++++ b/drivers/media/usb/dvb-usb/friio.c
+@@ -21,7 +21,7 @@ MODULE_PARM_DESC(debug,
+ 
+ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+ 
+-/**
++/*
+  * Indirect I2C access to the PLL via FE.
+  * whole I2C protocol data to the PLL is sent via the FE's I2C register.
+  * This is done by a control msg to the FE with the I2C data accompanied, and
+diff --git a/drivers/media/usb/gspca/ov519.c b/drivers/media/usb/gspca/ov519.c
+index cdb79c5f0c38..cb0afbf0aae7 100644
+--- a/drivers/media/usb/gspca/ov519.c
++++ b/drivers/media/usb/gspca/ov519.c
+@@ -1,4 +1,4 @@
+-/**
++/*
+  * OV519 driver
+  *
+  * Copyright (C) 2008-2011 Jean-François Moine <moinejf@free.fr>
+diff --git a/drivers/media/usb/pwc/pwc-dec23.c b/drivers/media/usb/pwc/pwc-dec23.c
+index 3792fedff951..1283b3bd9800 100644
+--- a/drivers/media/usb/pwc/pwc-dec23.c
++++ b/drivers/media/usb/pwc/pwc-dec23.c
+@@ -649,11 +649,10 @@ static void DecompressBand23(struct pwc_dec23_private *pdec,
+ }
+ 
+ /**
+- *
+  * Uncompress a pwc23 buffer.
+- *
+- * src: raw data
+- * dst: image output
++ * @pdev: pointer to pwc device's internal struct
++ * @src: raw data
++ * @dst: image output
+  */
+ void pwc_dec23_decompress(struct pwc_device *pdev,
+ 			  const void *src,
+diff --git a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
+index b842f367249f..a142b9dc0feb 100644
+--- a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
++++ b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
+@@ -76,7 +76,7 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+ #define TTUSB_REV_2_2	0x22
+ #define TTUSB_BUDGET_NAME "ttusb_stc_fw"
+ 
+-/**
++/*
+  *  since we're casting (struct ttusb*) <-> (struct dvb_demux*) around
+  *  the dvb_demux field must be the first in struct!!
+  */
+@@ -713,7 +713,7 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len)
+ 					}
+ 				}
+ 
+-			/**
++			/*
+ 			 * if length is valid and we reached the end:
+ 			 * goto next muxpack
+ 			 */
+@@ -729,7 +729,7 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len)
+ 					/* maximum bytes, until we know the length */
+ 					ttusb->muxpack_len = 2;
+ 
+-				/**
++				/*
+ 				 * no muxpacks left?
+ 				 * return to search-sync state
+ 				 */
+-- 
+2.19.0
+
diff --git a/patches/0129-thermal-rcar_gen3_thermal-fix-initialization-sequenc.patch b/patches/0129-thermal-rcar_gen3_thermal-fix-initialization-sequenc.patch
new file mode 100644
index 00000000000000..ed334780051088
--- /dev/null
+++ b/patches/0129-thermal-rcar_gen3_thermal-fix-initialization-sequenc.patch
@@ -0,0 +1,125 @@
+From e6a76653eb3d349480e589c019912df66f7b1475 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 17 Oct 2017 13:36:13 +0200
+Subject: [PATCH 0129/1795] thermal: rcar_gen3_thermal: fix initialization
+ sequence for H3 ES2.0
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The initialization sequence for H3 (r8a7795) ES1.x and ES2.0 is
+different. H3 ES2.0 and later uses the same sequence as M3 (r8a7796)
+ES1.0. Fix this by not looking at compatible strings and instead
+defaulting to the r8a7796 initialization sequence and use
+soc_device_match() to check for H3 ES1.x.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit d668c807aa6ef3c3eef57b4e9e785ec0cfab4f6d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_gen3_thermal.c | 34 +++++++++++++----------------
+ 1 file changed, 15 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index 203aca44a2bb..561a0a332208 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -24,6 +24,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/spinlock.h>
++#include <linux/sys_soc.h>
+ #include <linux/thermal.h>
+ 
+ #include "thermal_core.h"
+@@ -90,10 +91,6 @@ struct rcar_gen3_thermal_priv {
+ 	struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM];
+ 	unsigned int num_tscs;
+ 	spinlock_t lock; /* Protect interrupts on and off */
+-	const struct rcar_gen3_thermal_data *data;
+-};
+-
+-struct rcar_gen3_thermal_data {
+ 	void (*thermal_init)(struct rcar_gen3_thermal_tsc *tsc);
+ };
+ 
+@@ -278,7 +275,12 @@ static irqreturn_t rcar_gen3_thermal_irq_thread(int irq, void *data)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static void r8a7795_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
++static const struct soc_device_attribute r8a7795es1[] = {
++	{ .soc_id = "r8a7795", .revision = "ES1.*" },
++	{ /* sentinel */ }
++};
++
++static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_tsc *tsc)
+ {
+ 	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,  CTSR_THBGR);
+ 	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,  0x0);
+@@ -303,7 +305,7 @@ static void r8a7795_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
+ 	usleep_range(1000, 2000);
+ }
+ 
+-static void r8a7796_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
++static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
+ {
+ 	u32 reg_val;
+ 
+@@ -324,17 +326,9 @@ static void r8a7796_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
+ 	usleep_range(1000, 2000);
+ }
+ 
+-static const struct rcar_gen3_thermal_data r8a7795_data = {
+-	.thermal_init = r8a7795_thermal_init,
+-};
+-
+-static const struct rcar_gen3_thermal_data r8a7796_data = {
+-	.thermal_init = r8a7796_thermal_init,
+-};
+-
+ static const struct of_device_id rcar_gen3_thermal_dt_ids[] = {
+-	{ .compatible = "renesas,r8a7795-thermal", .data = &r8a7795_data},
+-	{ .compatible = "renesas,r8a7796-thermal", .data = &r8a7796_data},
++	{ .compatible = "renesas,r8a7795-thermal", },
++	{ .compatible = "renesas,r8a7796-thermal", },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids);
+@@ -371,7 +365,9 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	priv->data = of_device_get_match_data(dev);
++	priv->thermal_init = rcar_gen3_thermal_init;
++	if (soc_device_match(r8a7795es1))
++		priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1;
+ 
+ 	spin_lock_init(&priv->lock);
+ 
+@@ -423,7 +419,7 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
+ 
+ 		priv->tscs[i] = tsc;
+ 
+-		priv->data->thermal_init(tsc);
++		priv->thermal_init(tsc);
+ 		rcar_gen3_thermal_calc_coefs(&tsc->coef, ptat, thcode[i]);
+ 
+ 		zone = devm_thermal_zone_of_sensor_register(dev, i, tsc,
+@@ -476,7 +472,7 @@ static int __maybe_unused rcar_gen3_thermal_resume(struct device *dev)
+ 	for (i = 0; i < priv->num_tscs; i++) {
+ 		struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
+ 
+-		priv->data->thermal_init(tsc);
++		priv->thermal_init(tsc);
+ 		rcar_gen3_thermal_set_trips(tsc, tsc->low, tsc->high);
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0130-iio-adc-drop-assign-iio_info.driver_module-and-iio_t.patch b/patches/0130-iio-adc-drop-assign-iio_info.driver_module-and-iio_t.patch
new file mode 100644
index 00000000000000..6b85867c32b83a
--- /dev/null
+++ b/patches/0130-iio-adc-drop-assign-iio_info.driver_module-and-iio_t.patch
@@ -0,0 +1,1092 @@
+From ab188ca421d52db4c756f1d2ffa4964b0b2942e7 Mon Sep 17 00:00:00 2001
+From: Jonathan Cameron <jic23@kernel.org>
+Date: Sun, 23 Jul 2017 17:25:47 +0100
+Subject: [PATCH 0130/1795] iio:adc: drop assign iio_info.driver_module and
+ iio_trigger_ops.owner
+
+The equivalent of both of these are now done via macro magic when
+the relevant register calls are made.  The actual structure
+elements will shortly go away.
+
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
+(cherry picked from commit 52b31bcc9372f2925f4898d179c655687c4aa179)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iio/adc/ad7266.c            | 1 -
+ drivers/iio/adc/ad7291.c            | 1 -
+ drivers/iio/adc/ad7298.c            | 1 -
+ drivers/iio/adc/ad7476.c            | 1 -
+ drivers/iio/adc/ad7766.c            | 2 --
+ drivers/iio/adc/ad7791.c            | 2 --
+ drivers/iio/adc/ad7793.c            | 2 --
+ drivers/iio/adc/ad7887.c            | 1 -
+ drivers/iio/adc/ad7923.c            | 1 -
+ drivers/iio/adc/ad799x.c            | 3 ---
+ drivers/iio/adc/ad_sigma_delta.c    | 1 -
+ drivers/iio/adc/aspeed_adc.c        | 1 -
+ drivers/iio/adc/at91-sama5d2_adc.c  | 2 --
+ drivers/iio/adc/at91_adc.c          | 2 --
+ drivers/iio/adc/axp20x_adc.c        | 2 --
+ drivers/iio/adc/axp288_adc.c        | 1 -
+ drivers/iio/adc/bcm_iproc_adc.c     | 1 -
+ drivers/iio/adc/berlin2-adc.c       | 1 -
+ drivers/iio/adc/cc10001_adc.c       | 1 -
+ drivers/iio/adc/cpcap-adc.c         | 1 -
+ drivers/iio/adc/da9150-gpadc.c      | 1 -
+ drivers/iio/adc/dln2-adc.c          | 6 ------
+ drivers/iio/adc/envelope-detector.c | 1 -
+ drivers/iio/adc/exynos_adc.c        | 1 -
+ drivers/iio/adc/hi8435.c            | 1 -
+ drivers/iio/adc/hx711.c             | 1 -
+ drivers/iio/adc/imx7d_adc.c         | 1 -
+ drivers/iio/adc/ina2xx-adc.c        | 2 --
+ drivers/iio/adc/lp8788_adc.c        | 1 -
+ drivers/iio/adc/lpc18xx_adc.c       | 1 -
+ drivers/iio/adc/lpc32xx_adc.c       | 1 -
+ drivers/iio/adc/ltc2471.c           | 1 -
+ drivers/iio/adc/ltc2485.c           | 1 -
+ drivers/iio/adc/ltc2497.c           | 1 -
+ drivers/iio/adc/max1027.c           | 2 --
+ drivers/iio/adc/max11100.c          | 1 -
+ drivers/iio/adc/max1118.c           | 1 -
+ drivers/iio/adc/max1363.c           | 2 --
+ drivers/iio/adc/max9611.c           | 1 -
+ drivers/iio/adc/mcp320x.c           | 1 -
+ drivers/iio/adc/mcp3422.c           | 1 -
+ drivers/iio/adc/men_z188_adc.c      | 1 -
+ drivers/iio/adc/meson_saradc.c      | 1 -
+ drivers/iio/adc/mt6577_auxadc.c     | 1 -
+ drivers/iio/adc/mxs-lradc-adc.c     | 2 --
+ drivers/iio/adc/nau7802.c           | 1 -
+ drivers/iio/adc/palmas_gpadc.c      | 1 -
+ drivers/iio/adc/qcom-pm8xxx-xoadc.c | 1 -
+ drivers/iio/adc/qcom-spmi-iadc.c    | 1 -
+ drivers/iio/adc/qcom-spmi-vadc.c    | 1 -
+ drivers/iio/adc/rcar-gyroadc.c      | 1 -
+ drivers/iio/adc/rockchip_saradc.c   | 1 -
+ drivers/iio/adc/spear_adc.c         | 1 -
+ drivers/iio/adc/stm32-adc.c         | 1 -
+ drivers/iio/adc/stx104.c            | 1 -
+ drivers/iio/adc/sun4i-gpadc-iio.c   | 1 -
+ drivers/iio/adc/ti-adc081c.c        | 1 -
+ drivers/iio/adc/ti-adc0832.c        | 1 -
+ drivers/iio/adc/ti-adc084s021.c     | 1 -
+ drivers/iio/adc/ti-adc108s102.c     | 1 -
+ drivers/iio/adc/ti-adc12138.c       | 1 -
+ drivers/iio/adc/ti-adc128s052.c     | 1 -
+ drivers/iio/adc/ti-adc161s626.c     | 1 -
+ drivers/iio/adc/ti-ads1015.c        | 2 --
+ drivers/iio/adc/ti-ads7950.c        | 1 -
+ drivers/iio/adc/ti-ads8688.c        | 1 -
+ drivers/iio/adc/ti-tlc4541.c        | 1 -
+ drivers/iio/adc/ti_am335x_adc.c     | 1 -
+ drivers/iio/adc/twl4030-madc.c      | 1 -
+ drivers/iio/adc/twl6030-gpadc.c     | 1 -
+ drivers/iio/adc/vf610_adc.c         | 1 -
+ drivers/iio/adc/viperboard_adc.c    | 1 -
+ drivers/iio/adc/xilinx-xadc-core.c  | 2 --
+ 73 files changed, 92 deletions(-)
+
+diff --git a/drivers/iio/adc/ad7266.c b/drivers/iio/adc/ad7266.c
+index b8d5cfd57ec4..605eb5e7e829 100644
+--- a/drivers/iio/adc/ad7266.c
++++ b/drivers/iio/adc/ad7266.c
+@@ -280,7 +280,6 @@ static AD7266_DECLARE_DIFF_CHANNELS_FIXED(u, 'u');
+ static const struct iio_info ad7266_info = {
+ 	.read_raw = &ad7266_read_raw,
+ 	.update_scan_mode = &ad7266_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const unsigned long ad7266_available_scan_masks[] = {
+diff --git a/drivers/iio/adc/ad7291.c b/drivers/iio/adc/ad7291.c
+index 1d90b02732bb..a862b5d8fb4b 100644
+--- a/drivers/iio/adc/ad7291.c
++++ b/drivers/iio/adc/ad7291.c
+@@ -461,7 +461,6 @@ static const struct iio_info ad7291_info = {
+ 	.write_event_config = &ad7291_write_event_config,
+ 	.read_event_value = &ad7291_read_event_value,
+ 	.write_event_value = &ad7291_write_event_value,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ad7291_probe(struct i2c_client *client,
+diff --git a/drivers/iio/adc/ad7298.c b/drivers/iio/adc/ad7298.c
+index e399bf04c73a..2b20c6c8ec7f 100644
+--- a/drivers/iio/adc/ad7298.c
++++ b/drivers/iio/adc/ad7298.c
+@@ -280,7 +280,6 @@ static int ad7298_read_raw(struct iio_dev *indio_dev,
+ static const struct iio_info ad7298_info = {
+ 	.read_raw = &ad7298_read_raw,
+ 	.update_scan_mode = ad7298_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ad7298_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c
+index b7ecf9aab90f..b7706bf10ffe 100644
+--- a/drivers/iio/adc/ad7476.c
++++ b/drivers/iio/adc/ad7476.c
+@@ -195,7 +195,6 @@ static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
+ };
+ 
+ static const struct iio_info ad7476_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &ad7476_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/ad7766.c b/drivers/iio/adc/ad7766.c
+index ce45037295d8..3ae14fc8c649 100644
+--- a/drivers/iio/adc/ad7766.c
++++ b/drivers/iio/adc/ad7766.c
+@@ -185,7 +185,6 @@ static const struct iio_buffer_setup_ops ad7766_buffer_setup_ops = {
+ };
+ 
+ static const struct iio_info ad7766_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &ad7766_read_raw,
+ };
+ 
+@@ -208,7 +207,6 @@ static int ad7766_set_trigger_state(struct iio_trigger *trig, bool enable)
+ }
+ 
+ static const struct iio_trigger_ops ad7766_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.set_trigger_state = ad7766_set_trigger_state,
+ 	.validate_device = iio_trigger_validate_own_device,
+ };
+diff --git a/drivers/iio/adc/ad7791.c b/drivers/iio/adc/ad7791.c
+index 677f812f372a..03a5f7d6cb0c 100644
+--- a/drivers/iio/adc/ad7791.c
++++ b/drivers/iio/adc/ad7791.c
+@@ -259,13 +259,11 @@ static const struct iio_info ad7791_info = {
+ 	.read_raw = &ad7791_read_raw,
+ 	.attrs = &ad7791_attribute_group,
+ 	.validate_trigger = ad_sd_validate_trigger,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct iio_info ad7791_no_filter_info = {
+ 	.read_raw = &ad7791_read_raw,
+ 	.validate_trigger = ad_sd_validate_trigger,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ad7791_setup(struct ad7791_state *st,
+diff --git a/drivers/iio/adc/ad7793.c b/drivers/iio/adc/ad7793.c
+index 07246a6037e3..d4bbe5b53318 100644
+--- a/drivers/iio/adc/ad7793.c
++++ b/drivers/iio/adc/ad7793.c
+@@ -536,7 +536,6 @@ static const struct iio_info ad7793_info = {
+ 	.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
+ 	.attrs = &ad7793_attribute_group,
+ 	.validate_trigger = ad_sd_validate_trigger,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct iio_info ad7797_info = {
+@@ -545,7 +544,6 @@ static const struct iio_info ad7797_info = {
+ 	.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
+ 	.attrs = &ad7793_attribute_group,
+ 	.validate_trigger = ad_sd_validate_trigger,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
+diff --git a/drivers/iio/adc/ad7887.c b/drivers/iio/adc/ad7887.c
+index 7a483bfbd70c..205c0f1761aa 100644
+--- a/drivers/iio/adc/ad7887.c
++++ b/drivers/iio/adc/ad7887.c
+@@ -229,7 +229,6 @@ static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
+ 
+ static const struct iio_info ad7887_info = {
+ 	.read_raw = &ad7887_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ad7887_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c
+index 77a675e11ebb..ffb7e089969c 100644
+--- a/drivers/iio/adc/ad7923.c
++++ b/drivers/iio/adc/ad7923.c
+@@ -262,7 +262,6 @@ static int ad7923_read_raw(struct iio_dev *indio_dev,
+ static const struct iio_info ad7923_info = {
+ 	.read_raw = &ad7923_read_raw,
+ 	.update_scan_mode = ad7923_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ad7923_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ad799x.c b/drivers/iio/adc/ad799x.c
+index 22426ae4af97..e1da67d5ee22 100644
+--- a/drivers/iio/adc/ad799x.c
++++ b/drivers/iio/adc/ad799x.c
+@@ -526,13 +526,11 @@ static const struct attribute_group ad799x_event_attrs_group = {
+ 
+ static const struct iio_info ad7991_info = {
+ 	.read_raw = &ad799x_read_raw,
+-	.driver_module = THIS_MODULE,
+ 	.update_scan_mode = ad799x_update_scan_mode,
+ };
+ 
+ static const struct iio_info ad7993_4_7_8_noirq_info = {
+ 	.read_raw = &ad799x_read_raw,
+-	.driver_module = THIS_MODULE,
+ 	.update_scan_mode = ad799x_update_scan_mode,
+ };
+ 
+@@ -543,7 +541,6 @@ static const struct iio_info ad7993_4_7_8_irq_info = {
+ 	.write_event_config = &ad799x_write_event_config,
+ 	.read_event_value = &ad799x_read_event_value,
+ 	.write_event_value = &ad799x_write_event_value,
+-	.driver_module = THIS_MODULE,
+ 	.update_scan_mode = ad799x_update_scan_mode,
+ };
+ 
+diff --git a/drivers/iio/adc/ad_sigma_delta.c b/drivers/iio/adc/ad_sigma_delta.c
+index 22c4c17cd996..cf1b048b0665 100644
+--- a/drivers/iio/adc/ad_sigma_delta.c
++++ b/drivers/iio/adc/ad_sigma_delta.c
+@@ -463,7 +463,6 @@ int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig)
+ EXPORT_SYMBOL_GPL(ad_sd_validate_trigger);
+ 
+ static const struct iio_trigger_ops ad_sd_trigger_ops = {
+-	.owner = THIS_MODULE,
+ };
+ 
+ static int ad_sd_probe_trigger(struct iio_dev *indio_dev)
+diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
+index c02b23d675cb..8a958d5f1905 100644
+--- a/drivers/iio/adc/aspeed_adc.c
++++ b/drivers/iio/adc/aspeed_adc.c
+@@ -165,7 +165,6 @@ static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info aspeed_adc_iio_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = aspeed_adc_read_raw,
+ 	.write_raw = aspeed_adc_write_raw,
+ 	.debugfs_reg_access = aspeed_adc_reg_access,
+diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
+index a70ef7fec95f..755a493c2a2c 100644
+--- a/drivers/iio/adc/at91-sama5d2_adc.c
++++ b/drivers/iio/adc/at91-sama5d2_adc.c
+@@ -348,7 +348,6 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig)
+ }
+ 
+ static const struct iio_trigger_ops at91_adc_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.set_trigger_state = &at91_adc_configure_trigger,
+ 	.try_reenable = &at91_adc_reenable_trigger,
+ };
+@@ -584,7 +583,6 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev,
+ static const struct iio_info at91_adc_info = {
+ 	.read_raw = &at91_adc_read_raw,
+ 	.write_raw = &at91_adc_write_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static void at91_adc_hw_init(struct at91_adc_state *st)
+diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c
+index 15109728cae7..3836d4222a3e 100644
+--- a/drivers/iio/adc/at91_adc.c
++++ b/drivers/iio/adc/at91_adc.c
+@@ -594,7 +594,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
+ }
+ 
+ static const struct iio_trigger_ops at91_adc_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.set_trigger_state = &at91_adc_configure_trigger,
+ };
+ 
+@@ -976,7 +975,6 @@ static int at91_adc_probe_pdata(struct at91_adc_state *st,
+ }
+ 
+ static const struct iio_info at91_adc_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &at91_adc_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index 11e177180ea0..a30a97245e91 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -464,12 +464,10 @@ static int axp20x_write_raw(struct iio_dev *indio_dev,
+ static const struct iio_info axp20x_adc_iio_info = {
+ 	.read_raw = axp20x_read_raw,
+ 	.write_raw = axp20x_write_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct iio_info axp22x_adc_iio_info = {
+ 	.read_raw = axp22x_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int axp20x_adc_rate(int rate)
+diff --git a/drivers/iio/adc/axp288_adc.c b/drivers/iio/adc/axp288_adc.c
+index 462a99c13e7a..60c9e853dd81 100644
+--- a/drivers/iio/adc/axp288_adc.c
++++ b/drivers/iio/adc/axp288_adc.c
+@@ -183,7 +183,6 @@ static int axp288_adc_set_state(struct regmap *regmap)
+ 
+ static const struct iio_info axp288_adc_iio_info = {
+ 	.read_raw = &axp288_adc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int axp288_adc_probe(struct platform_device *pdev)
+diff --git a/drivers/iio/adc/bcm_iproc_adc.c b/drivers/iio/adc/bcm_iproc_adc.c
+index 7f4f9c4150e3..7af59a4bbd8d 100644
+--- a/drivers/iio/adc/bcm_iproc_adc.c
++++ b/drivers/iio/adc/bcm_iproc_adc.c
+@@ -492,7 +492,6 @@ static int iproc_adc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info iproc_adc_iio_info = {
+ 	.read_raw = &iproc_adc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define IPROC_ADC_CHANNEL(_index, _id) {                \
+diff --git a/drivers/iio/adc/berlin2-adc.c b/drivers/iio/adc/berlin2-adc.c
+index 71c806ecc722..72d8fa94ab31 100644
+--- a/drivers/iio/adc/berlin2-adc.c
++++ b/drivers/iio/adc/berlin2-adc.c
+@@ -277,7 +277,6 @@ static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
+ }
+ 
+ static const struct iio_info berlin2_adc_info = {
+-	.driver_module	= THIS_MODULE,
+ 	.read_raw	= berlin2_adc_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/cc10001_adc.c b/drivers/iio/adc/cc10001_adc.c
+index 91636c0ba5b5..707d8b24b072 100644
+--- a/drivers/iio/adc/cc10001_adc.c
++++ b/drivers/iio/adc/cc10001_adc.c
+@@ -262,7 +262,6 @@ static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info cc10001_adc_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &cc10001_adc_read_raw,
+ 	.update_scan_mode = &cc10001_update_scan_mode,
+ };
+diff --git a/drivers/iio/adc/cpcap-adc.c b/drivers/iio/adc/cpcap-adc.c
+index f153e02686a0..9ad60421d360 100644
+--- a/drivers/iio/adc/cpcap-adc.c
++++ b/drivers/iio/adc/cpcap-adc.c
+@@ -932,7 +932,6 @@ static int cpcap_adc_read(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info cpcap_adc_info = {
+ 	.read_raw = &cpcap_adc_read,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ /*
+diff --git a/drivers/iio/adc/da9150-gpadc.c b/drivers/iio/adc/da9150-gpadc.c
+index 3445107e10b7..0a5d9ce79164 100644
+--- a/drivers/iio/adc/da9150-gpadc.c
++++ b/drivers/iio/adc/da9150-gpadc.c
+@@ -249,7 +249,6 @@ static int da9150_gpadc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info da9150_gpadc_info = {
+ 	.read_raw = &da9150_gpadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info,	\
+diff --git a/drivers/iio/adc/dln2-adc.c b/drivers/iio/adc/dln2-adc.c
+index ab8d6aed5085..c64c6675cae6 100644
+--- a/drivers/iio/adc/dln2-adc.c
++++ b/drivers/iio/adc/dln2-adc.c
+@@ -479,7 +479,6 @@ static const struct iio_info dln2_adc_info = {
+ 	.read_raw = dln2_adc_read_raw,
+ 	.write_raw = dln2_adc_write_raw,
+ 	.update_scan_mode = dln2_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
+@@ -604,10 +603,6 @@ static void dln2_adc_event(struct platform_device *pdev, u16 echo,
+ 	iio_trigger_poll(dln2->trig);
+ }
+ 
+-static const struct iio_trigger_ops dln2_adc_trigger_ops = {
+-	.owner = THIS_MODULE,
+-};
+-
+ static int dln2_adc_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -665,7 +660,6 @@ static int dln2_adc_probe(struct platform_device *pdev)
+ 		dev_err(dev, "failed to allocate trigger\n");
+ 		return -ENOMEM;
+ 	}
+-	dln2->trig->ops = &dln2_adc_trigger_ops;
+ 	iio_trigger_set_drvdata(dln2->trig, dln2);
+ 	devm_iio_trigger_register(dev, dln2->trig);
+ 	iio_trigger_set_immutable(indio_dev, dln2->trig);
+diff --git a/drivers/iio/adc/envelope-detector.c b/drivers/iio/adc/envelope-detector.c
+index fef15c0d7c9c..4ebda8ab54fe 100644
+--- a/drivers/iio/adc/envelope-detector.c
++++ b/drivers/iio/adc/envelope-detector.c
+@@ -322,7 +322,6 @@ static const struct iio_chan_spec envelope_detector_iio_channel = {
+ 
+ static const struct iio_info envelope_detector_info = {
+ 	.read_raw = &envelope_detector_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int envelope_detector_probe(struct platform_device *pdev)
+diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
+index 6c5a7be9f8c1..f10443f92e4c 100644
+--- a/drivers/iio/adc/exynos_adc.c
++++ b/drivers/iio/adc/exynos_adc.c
+@@ -657,7 +657,6 @@ static int exynos_adc_reg_access(struct iio_dev *indio_dev,
+ static const struct iio_info exynos_adc_iio_info = {
+ 	.read_raw = &exynos_read_raw,
+ 	.debugfs_reg_access = &exynos_adc_reg_access,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define ADC_CHANNEL(_index, _id) {			\
+diff --git a/drivers/iio/adc/hi8435.c b/drivers/iio/adc/hi8435.c
+index adf7dc712937..6f6c9a348158 100644
+--- a/drivers/iio/adc/hi8435.c
++++ b/drivers/iio/adc/hi8435.c
+@@ -408,7 +408,6 @@ static const struct iio_chan_spec hi8435_channels[] = {
+ };
+ 
+ static const struct iio_info hi8435_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = hi8435_read_raw,
+ 	.read_event_config = hi8435_read_event_config,
+ 	.write_event_config = hi8435_write_event_config,
+diff --git a/drivers/iio/adc/hx711.c b/drivers/iio/adc/hx711.c
+index 27005d84ed73..d10b9f13d557 100644
+--- a/drivers/iio/adc/hx711.c
++++ b/drivers/iio/adc/hx711.c
+@@ -374,7 +374,6 @@ static const struct attribute_group hx711_attribute_group = {
+ };
+ 
+ static const struct iio_info hx711_iio_info = {
+-	.driver_module		= THIS_MODULE,
+ 	.read_raw		= hx711_read_raw,
+ 	.write_raw		= hx711_write_raw,
+ 	.write_raw_get_fmt	= hx711_write_raw_get_fmt,
+diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c
+index 254b29a68b9d..cfab31162845 100644
+--- a/drivers/iio/adc/imx7d_adc.c
++++ b/drivers/iio/adc/imx7d_adc.c
+@@ -412,7 +412,6 @@ static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info imx7d_adc_iio_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &imx7d_adc_read_raw,
+ 	.debugfs_reg_access = &imx7d_adc_reg_access,
+ };
+diff --git a/drivers/iio/adc/ina2xx-adc.c b/drivers/iio/adc/ina2xx-adc.c
+index 59f99b3a180d..3976da23ec3f 100644
+--- a/drivers/iio/adc/ina2xx-adc.c
++++ b/drivers/iio/adc/ina2xx-adc.c
+@@ -786,7 +786,6 @@ static const struct attribute_group ina226_attribute_group = {
+ };
+ 
+ static const struct iio_info ina219_info = {
+-	.driver_module = THIS_MODULE,
+ 	.attrs = &ina219_attribute_group,
+ 	.read_raw = ina2xx_read_raw,
+ 	.write_raw = ina2xx_write_raw,
+@@ -794,7 +793,6 @@ static const struct iio_info ina219_info = {
+ };
+ 
+ static const struct iio_info ina226_info = {
+-	.driver_module = THIS_MODULE,
+ 	.attrs = &ina226_attribute_group,
+ 	.read_raw = ina2xx_read_raw,
+ 	.write_raw = ina2xx_write_raw,
+diff --git a/drivers/iio/adc/lp8788_adc.c b/drivers/iio/adc/lp8788_adc.c
+index 152cfc8e1c7b..3bc4df916420 100644
+--- a/drivers/iio/adc/lp8788_adc.c
++++ b/drivers/iio/adc/lp8788_adc.c
+@@ -125,7 +125,6 @@ static int lp8788_adc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info lp8788_adc_info = {
+ 	.read_raw = &lp8788_adc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define LP8788_CHAN(_id, _type) {				\
+diff --git a/drivers/iio/adc/lpc18xx_adc.c b/drivers/iio/adc/lpc18xx_adc.c
+index 3ef18f4b27f0..041dc4a3f66c 100644
+--- a/drivers/iio/adc/lpc18xx_adc.c
++++ b/drivers/iio/adc/lpc18xx_adc.c
+@@ -116,7 +116,6 @@ static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info lpc18xx_adc_info = {
+ 	.read_raw = lpc18xx_adc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int lpc18xx_adc_probe(struct platform_device *pdev)
+diff --git a/drivers/iio/adc/lpc32xx_adc.c b/drivers/iio/adc/lpc32xx_adc.c
+index 6a5b9a9bc662..20b36690fa4f 100644
+--- a/drivers/iio/adc/lpc32xx_adc.c
++++ b/drivers/iio/adc/lpc32xx_adc.c
+@@ -104,7 +104,6 @@ static int lpc32xx_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info lpc32xx_adc_iio_info = {
+ 	.read_raw = &lpc32xx_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define LPC32XX_ADC_CHANNEL(_index) {			\
+diff --git a/drivers/iio/adc/ltc2471.c b/drivers/iio/adc/ltc2471.c
+index 29b7ed60cdb0..b88102b751cf 100644
+--- a/drivers/iio/adc/ltc2471.c
++++ b/drivers/iio/adc/ltc2471.c
+@@ -98,7 +98,6 @@ static const struct iio_chan_spec ltc2473_channel[] = {
+ 
+ static const struct iio_info ltc2471_info = {
+ 	.read_raw = ltc2471_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ltc2471_i2c_probe(struct i2c_client *client,
+diff --git a/drivers/iio/adc/ltc2485.c b/drivers/iio/adc/ltc2485.c
+index eab91f12454a..b24c14037fd4 100644
+--- a/drivers/iio/adc/ltc2485.c
++++ b/drivers/iio/adc/ltc2485.c
+@@ -90,7 +90,6 @@ static const struct iio_chan_spec ltc2485_channel[] = {
+ 
+ static const struct iio_info ltc2485_info = {
+ 	.read_raw = ltc2485_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ltc2485_probe(struct i2c_client *client,
+diff --git a/drivers/iio/adc/ltc2497.c b/drivers/iio/adc/ltc2497.c
+index 5bf8011dcde9..f1f7cdf66fbd 100644
+--- a/drivers/iio/adc/ltc2497.c
++++ b/drivers/iio/adc/ltc2497.c
+@@ -186,7 +186,6 @@ static const struct iio_chan_spec ltc2497_channel[] = {
+ 
+ static const struct iio_info ltc2497_info = {
+ 	.read_raw = ltc2497_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int ltc2497_probe(struct i2c_client *client,
+diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c
+index ebc715927e63..375da6491499 100644
+--- a/drivers/iio/adc/max1027.c
++++ b/drivers/iio/adc/max1027.c
+@@ -381,13 +381,11 @@ static irqreturn_t max1027_trigger_handler(int irq, void *private)
+ }
+ 
+ static const struct iio_trigger_ops max1027_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.validate_device = &iio_trigger_validate_own_device,
+ 	.set_trigger_state = &max1027_set_trigger_state,
+ };
+ 
+ static const struct iio_info max1027_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &max1027_read_raw,
+ 	.validate_trigger = &max1027_validate_trigger,
+ 	.debugfs_reg_access = &max1027_debugfs_reg_access,
+diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c
+index 1180bcc22ff1..af59ab2e650c 100644
+--- a/drivers/iio/adc/max11100.c
++++ b/drivers/iio/adc/max11100.c
+@@ -100,7 +100,6 @@ static int max11100_read_raw(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info max11100_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = max11100_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/max1118.c b/drivers/iio/adc/max1118.c
+index 2e9648a078c4..49db9e9ae625 100644
+--- a/drivers/iio/adc/max1118.c
++++ b/drivers/iio/adc/max1118.c
+@@ -155,7 +155,6 @@ static int max1118_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info max1118_info = {
+ 	.read_raw = max1118_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t max1118_trigger_handler(int irq, void *p)
+diff --git a/drivers/iio/adc/max1363.c b/drivers/iio/adc/max1363.c
+index 80eada4886b3..7f1848dac9bf 100644
+--- a/drivers/iio/adc/max1363.c
++++ b/drivers/iio/adc/max1363.c
+@@ -1029,7 +1029,6 @@ static int max1363_update_scan_mode(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info max1238_info = {
+ 	.read_raw = &max1363_read_raw,
+-	.driver_module = THIS_MODULE,
+ 	.update_scan_mode = &max1363_update_scan_mode,
+ };
+ 
+@@ -1040,7 +1039,6 @@ static const struct iio_info max1363_info = {
+ 	.write_event_config = &max1363_write_event_config,
+ 	.read_raw = &max1363_read_raw,
+ 	.update_scan_mode = &max1363_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ 	.event_attrs = &max1363_event_attribute_group,
+ };
+ 
+diff --git a/drivers/iio/adc/max9611.c b/drivers/iio/adc/max9611.c
+index b1dd17cbce58..9edfbabf4e4d 100644
+--- a/drivers/iio/adc/max9611.c
++++ b/drivers/iio/adc/max9611.c
+@@ -460,7 +460,6 @@ static const struct attribute_group max9611_attribute_group = {
+ };
+ 
+ static const struct iio_info indio_info = {
+-	.driver_module	= THIS_MODULE,
+ 	.read_raw	= max9611_read_raw,
+ 	.attrs		= &max9611_attribute_group,
+ };
+diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c
+index 071dd23a33d9..49e80b959089 100644
+--- a/drivers/iio/adc/mcp320x.c
++++ b/drivers/iio/adc/mcp320x.c
+@@ -248,7 +248,6 @@ static const struct iio_chan_spec mcp3208_channels[] = {
+ 
+ static const struct iio_info mcp320x_info = {
+ 	.read_raw = mcp320x_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
+diff --git a/drivers/iio/adc/mcp3422.c b/drivers/iio/adc/mcp3422.c
+index 63de705086ed..819f26011500 100644
+--- a/drivers/iio/adc/mcp3422.c
++++ b/drivers/iio/adc/mcp3422.c
+@@ -327,7 +327,6 @@ static const struct iio_info mcp3422_info = {
+ 	.write_raw = mcp3422_write_raw,
+ 	.write_raw_get_fmt = mcp3422_write_raw_get_fmt,
+ 	.attrs = &mcp3422_attribute_group,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int mcp3422_probe(struct i2c_client *client,
+diff --git a/drivers/iio/adc/men_z188_adc.c b/drivers/iio/adc/men_z188_adc.c
+index 8f3606de4eaf..c80261748d8f 100644
+--- a/drivers/iio/adc/men_z188_adc.c
++++ b/drivers/iio/adc/men_z188_adc.c
+@@ -80,7 +80,6 @@ static int z188_iio_read_raw(struct iio_dev *iio_dev,
+ 
+ static const struct iio_info z188_adc_info = {
+ 	.read_raw = &z188_iio_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static void men_z188_config_channels(void __iomem *addr)
+diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
+index 11484cb38b84..0d237fd69769 100644
+--- a/drivers/iio/adc/meson_saradc.c
++++ b/drivers/iio/adc/meson_saradc.c
+@@ -864,7 +864,6 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev)
+ 
+ static const struct iio_info meson_sar_adc_iio_info = {
+ 	.read_raw = meson_sar_adc_iio_info_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
+diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
+index 414cf44bf19d..a2a23958c2a2 100644
+--- a/drivers/iio/adc/mt6577_auxadc.c
++++ b/drivers/iio/adc/mt6577_auxadc.c
+@@ -180,7 +180,6 @@ static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info mt6577_auxadc_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &mt6577_auxadc_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/mxs-lradc-adc.c b/drivers/iio/adc/mxs-lradc-adc.c
+index d32b34638c2f..c627513d9f0f 100644
+--- a/drivers/iio/adc/mxs-lradc-adc.c
++++ b/drivers/iio/adc/mxs-lradc-adc.c
+@@ -382,7 +382,6 @@ static const struct attribute_group mxs_lradc_adc_attribute_group = {
+ };
+ 
+ static const struct iio_info mxs_lradc_adc_iio_info = {
+-	.driver_module		= THIS_MODULE,
+ 	.read_raw		= mxs_lradc_adc_read_raw,
+ 	.write_raw		= mxs_lradc_adc_write_raw,
+ 	.write_raw_get_fmt	= mxs_lradc_adc_write_raw_get_fmt,
+@@ -455,7 +454,6 @@ static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
+ }
+ 
+ static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.set_trigger_state = &mxs_lradc_adc_configure_trigger,
+ };
+ 
+diff --git a/drivers/iio/adc/nau7802.c b/drivers/iio/adc/nau7802.c
+index 08f446695f97..8997e74a8847 100644
+--- a/drivers/iio/adc/nau7802.c
++++ b/drivers/iio/adc/nau7802.c
+@@ -402,7 +402,6 @@ static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info nau7802_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &nau7802_read_raw,
+ 	.write_raw = &nau7802_write_raw,
+ 	.write_raw_get_fmt = nau7802_write_raw_get_fmt,
+diff --git a/drivers/iio/adc/palmas_gpadc.c b/drivers/iio/adc/palmas_gpadc.c
+index 7d61b566e148..69b9affeef1e 100644
+--- a/drivers/iio/adc/palmas_gpadc.c
++++ b/drivers/iio/adc/palmas_gpadc.c
+@@ -430,7 +430,6 @@ static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info palmas_gpadc_iio_info = {
+ 	.read_raw = palmas_gpadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info)	\
+diff --git a/drivers/iio/adc/qcom-pm8xxx-xoadc.c b/drivers/iio/adc/qcom-pm8xxx-xoadc.c
+index cea8f1fb444a..b093ecddf1a8 100644
+--- a/drivers/iio/adc/qcom-pm8xxx-xoadc.c
++++ b/drivers/iio/adc/qcom-pm8xxx-xoadc.c
+@@ -728,7 +728,6 @@ static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info pm8xxx_xoadc_info = {
+-	.driver_module = THIS_MODULE,
+ 	.of_xlate = pm8xxx_of_xlate,
+ 	.read_raw = pm8xxx_read_raw,
+ };
+diff --git a/drivers/iio/adc/qcom-spmi-iadc.c b/drivers/iio/adc/qcom-spmi-iadc.c
+index fabd24edc2a1..3f062cd61aba 100644
+--- a/drivers/iio/adc/qcom-spmi-iadc.c
++++ b/drivers/iio/adc/qcom-spmi-iadc.c
+@@ -356,7 +356,6 @@ static int iadc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info iadc_info = {
+ 	.read_raw = iadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t iadc_isr(int irq, void *dev_id)
+diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
+index 9e600bfd1765..3680e0d47412 100644
+--- a/drivers/iio/adc/qcom-spmi-vadc.c
++++ b/drivers/iio/adc/qcom-spmi-vadc.c
+@@ -506,7 +506,6 @@ static int vadc_of_xlate(struct iio_dev *indio_dev,
+ static const struct iio_info vadc_info = {
+ 	.read_raw = vadc_read_raw,
+ 	.of_xlate = vadc_of_xlate,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ struct vadc_channels {
+diff --git a/drivers/iio/adc/rcar-gyroadc.c b/drivers/iio/adc/rcar-gyroadc.c
+index 27a318164619..2cb5397ceeea 100644
+--- a/drivers/iio/adc/rcar-gyroadc.c
++++ b/drivers/iio/adc/rcar-gyroadc.c
+@@ -277,7 +277,6 @@ static int rcar_gyroadc_reg_access(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info rcar_gyroadc_iio_info = {
+-	.driver_module		= THIS_MODULE,
+ 	.read_raw		= rcar_gyroadc_read_raw,
+ 	.debugfs_reg_access	= rcar_gyroadc_reg_access,
+ };
+diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
+index 5f612d694b33..1f98566d5b3c 100644
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -125,7 +125,6 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
+ 
+ static const struct iio_info rockchip_saradc_iio_info = {
+ 	.read_raw = rockchip_saradc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define ADC_CHANNEL(_index, _id) {				\
+diff --git a/drivers/iio/adc/spear_adc.c b/drivers/iio/adc/spear_adc.c
+index 5dd61f6a57b9..b1da2c46107c 100644
+--- a/drivers/iio/adc/spear_adc.c
++++ b/drivers/iio/adc/spear_adc.c
+@@ -254,7 +254,6 @@ static int spear_adc_configure(struct spear_adc_state *st)
+ static const struct iio_info spear_adc_info = {
+ 	.read_raw = &spear_adc_read_raw,
+ 	.write_raw = &spear_adc_write_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int spear_adc_probe(struct platform_device *pdev)
+diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
+index 04be8bd951be..2c9903d3396d 100644
+--- a/drivers/iio/adc/stm32-adc.c
++++ b/drivers/iio/adc/stm32-adc.c
+@@ -1387,7 +1387,6 @@ static const struct iio_info stm32_adc_iio_info = {
+ 	.update_scan_mode = stm32_adc_update_scan_mode,
+ 	.debugfs_reg_access = stm32_adc_debugfs_reg_access,
+ 	.of_xlate = stm32_adc_of_xlate,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 2da741d27540..17b021f33180 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -172,7 +172,6 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info stx104_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = stx104_read_raw,
+ 	.write_raw = stx104_write_raw
+ };
+diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
+index 137f577d9432..a146160d9966 100644
+--- a/drivers/iio/adc/sun4i-gpadc-iio.c
++++ b/drivers/iio/adc/sun4i-gpadc-iio.c
+@@ -352,7 +352,6 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info sun4i_gpadc_iio_info = {
+ 	.read_raw = sun4i_gpadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id)
+diff --git a/drivers/iio/adc/ti-adc081c.c b/drivers/iio/adc/ti-adc081c.c
+index 319172cf7da8..405e3779c0c5 100644
+--- a/drivers/iio/adc/ti-adc081c.c
++++ b/drivers/iio/adc/ti-adc081c.c
+@@ -124,7 +124,6 @@ static struct adcxx1c_model adcxx1c_models[] = {
+ 
+ static const struct iio_info adc081c_info = {
+ 	.read_raw = adc081c_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t adc081c_trigger_handler(int irq, void *p)
+diff --git a/drivers/iio/adc/ti-adc0832.c b/drivers/iio/adc/ti-adc0832.c
+index e952e94a14af..188dae705bf7 100644
+--- a/drivers/iio/adc/ti-adc0832.c
++++ b/drivers/iio/adc/ti-adc0832.c
+@@ -195,7 +195,6 @@ static int adc0832_read_raw(struct iio_dev *iio,
+ 
+ static const struct iio_info adc0832_info = {
+ 	.read_raw = adc0832_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static irqreturn_t adc0832_trigger_handler(int irq, void *p)
+diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c
+index a355121c11a4..25504640e126 100644
+--- a/drivers/iio/adc/ti-adc084s021.c
++++ b/drivers/iio/adc/ti-adc084s021.c
+@@ -186,7 +186,6 @@ static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev)
+ 
+ static const struct iio_info adc084s021_info = {
+ 	.read_raw = adc084s021_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = {
+diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c
+index de4e5ac98c6e..841203edaac5 100644
+--- a/drivers/iio/adc/ti-adc108s102.c
++++ b/drivers/iio/adc/ti-adc108s102.c
+@@ -220,7 +220,6 @@ static int adc108s102_read_raw(struct iio_dev *indio_dev,
+ static const struct iio_info adc108s102_info = {
+ 	.read_raw		= &adc108s102_read_raw,
+ 	.update_scan_mode	= &adc108s102_update_scan_mode,
+-	.driver_module		= THIS_MODULE,
+ };
+ 
+ static int adc108s102_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ti-adc12138.c b/drivers/iio/adc/ti-adc12138.c
+index 072f03bfe6a0..bf890244789a 100644
+--- a/drivers/iio/adc/ti-adc12138.c
++++ b/drivers/iio/adc/ti-adc12138.c
+@@ -277,7 +277,6 @@ static int adc12138_read_raw(struct iio_dev *iio,
+ 
+ static const struct iio_info adc12138_info = {
+ 	.read_raw = adc12138_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int adc12138_init(struct adc12138 *adc)
+diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c
+index 89dfbd31be5c..7cf39b3e2416 100644
+--- a/drivers/iio/adc/ti-adc128s052.c
++++ b/drivers/iio/adc/ti-adc128s052.c
+@@ -130,7 +130,6 @@ static const struct adc128_configuration adc128_config[] = {
+ 
+ static const struct iio_info adc128_info = {
+ 	.read_raw = adc128_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int adc128_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c
+index 4836a0d7aef5..10fa7677ac4b 100644
+--- a/drivers/iio/adc/ti-adc161s626.c
++++ b/drivers/iio/adc/ti-adc161s626.c
+@@ -173,7 +173,6 @@ static int ti_adc_read_raw(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info ti_adc_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = ti_adc_read_raw,
+ };
+ 
+diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c
+index 9ac2fb032df6..344b768a5c49 100644
+--- a/drivers/iio/adc/ti-ads1015.c
++++ b/drivers/iio/adc/ti-ads1015.c
+@@ -822,7 +822,6 @@ static const struct attribute_group ads1115_attribute_group = {
+ };
+ 
+ static const struct iio_info ads1015_info = {
+-	.driver_module	= THIS_MODULE,
+ 	.read_raw	= ads1015_read_raw,
+ 	.write_raw	= ads1015_write_raw,
+ 	.read_event_value = ads1015_read_event,
+@@ -833,7 +832,6 @@ static const struct iio_info ads1015_info = {
+ };
+ 
+ static const struct iio_info ads1115_info = {
+-	.driver_module	= THIS_MODULE,
+ 	.read_raw	= ads1015_read_raw,
+ 	.write_raw	= ads1015_write_raw,
+ 	.read_event_value = ads1015_read_event,
+diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c
+index a376190914ad..0225c1b333ab 100644
+--- a/drivers/iio/adc/ti-ads7950.c
++++ b/drivers/iio/adc/ti-ads7950.c
+@@ -372,7 +372,6 @@ static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
+ static const struct iio_info ti_ads7950_info = {
+ 	.read_raw		= &ti_ads7950_read_raw,
+ 	.update_scan_mode	= ti_ads7950_update_scan_mode,
+-	.driver_module		= THIS_MODULE,
+ };
+ 
+ static int ti_ads7950_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c
+index 4a163496d9e4..ff4756352ac1 100644
+--- a/drivers/iio/adc/ti-ads8688.c
++++ b/drivers/iio/adc/ti-ads8688.c
+@@ -369,7 +369,6 @@ static const struct iio_info ads8688_info = {
+ 	.write_raw = &ads8688_write_raw,
+ 	.write_raw_get_fmt = &ads8688_write_raw_get_fmt,
+ 	.attrs = &ads8688_attribute_group,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
+diff --git a/drivers/iio/adc/ti-tlc4541.c b/drivers/iio/adc/ti-tlc4541.c
+index 78d91a069ea4..2290024c89fc 100644
+--- a/drivers/iio/adc/ti-tlc4541.c
++++ b/drivers/iio/adc/ti-tlc4541.c
+@@ -157,7 +157,6 @@ static int tlc4541_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info tlc4541_info = {
+ 	.read_raw = &tlc4541_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int tlc4541_probe(struct spi_device *spi)
+diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c
+index 6cbed7eb118a..b3e573cc6f5f 100644
+--- a/drivers/iio/adc/ti_am335x_adc.c
++++ b/drivers/iio/adc/ti_am335x_adc.c
+@@ -533,7 +533,6 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
+ 
+ static const struct iio_info tiadc_info = {
+ 	.read_raw = &tiadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int tiadc_request_dma(struct platform_device *pdev,
+diff --git a/drivers/iio/adc/twl4030-madc.c b/drivers/iio/adc/twl4030-madc.c
+index e3cfb91bffc6..8c019bb6625f 100644
+--- a/drivers/iio/adc/twl4030-madc.c
++++ b/drivers/iio/adc/twl4030-madc.c
+@@ -212,7 +212,6 @@ static int twl4030_madc_read(struct iio_dev *iio_dev,
+ 
+ static const struct iio_info twl4030_madc_iio_info = {
+ 	.read_raw = &twl4030_madc_read,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ #define TWL4030_ADC_CHANNEL(_channel, _type, _name) {	\
+diff --git a/drivers/iio/adc/twl6030-gpadc.c b/drivers/iio/adc/twl6030-gpadc.c
+index bc0e60b9da45..dc83f8f6c3d3 100644
+--- a/drivers/iio/adc/twl6030-gpadc.c
++++ b/drivers/iio/adc/twl6030-gpadc.c
+@@ -843,7 +843,6 @@ static const struct iio_chan_spec twl6032_gpadc_iio_channels[] = {
+ 
+ static const struct iio_info twl6030_gpadc_iio_info = {
+ 	.read_raw = &twl6030_gpadc_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct twl6030_gpadc_platform_data twl6030_pdata = {
+diff --git a/drivers/iio/adc/vf610_adc.c b/drivers/iio/adc/vf610_adc.c
+index c168e0db329a..bbcb7a4d7edf 100644
+--- a/drivers/iio/adc/vf610_adc.c
++++ b/drivers/iio/adc/vf610_adc.c
+@@ -799,7 +799,6 @@ static int vf610_adc_reg_access(struct iio_dev *indio_dev,
+ }
+ 
+ static const struct iio_info vf610_adc_iio_info = {
+-	.driver_module = THIS_MODULE,
+ 	.read_raw = &vf610_read_raw,
+ 	.write_raw = &vf610_write_raw,
+ 	.debugfs_reg_access = &vf610_adc_reg_access,
+diff --git a/drivers/iio/adc/viperboard_adc.c b/drivers/iio/adc/viperboard_adc.c
+index 3be2e35721cc..53eb5a4136fe 100644
+--- a/drivers/iio/adc/viperboard_adc.c
++++ b/drivers/iio/adc/viperboard_adc.c
+@@ -107,7 +107,6 @@ static int vprbrd_iio_read_raw(struct iio_dev *iio_dev,
+ 
+ static const struct iio_info vprbrd_adc_iio_info = {
+ 	.read_raw = &vprbrd_iio_read_raw,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static int vprbrd_adc_probe(struct platform_device *pdev)
+diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
+index 4a60497a1f19..d4f21d1be6c8 100644
+--- a/drivers/iio/adc/xilinx-xadc-core.c
++++ b/drivers/iio/adc/xilinx-xadc-core.c
+@@ -675,7 +675,6 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
+ }
+ 
+ static const struct iio_trigger_ops xadc_trigger_ops = {
+-	.owner = THIS_MODULE,
+ 	.set_trigger_state = &xadc_trigger_set_state,
+ };
+ 
+@@ -1028,7 +1027,6 @@ static const struct iio_info xadc_info = {
+ 	.read_event_value = &xadc_read_event_value,
+ 	.write_event_value = &xadc_write_event_value,
+ 	.update_scan_mode = &xadc_update_scan_mode,
+-	.driver_module = THIS_MODULE,
+ };
+ 
+ static const struct of_device_id xadc_of_match_table[] = {
+-- 
+2.19.0
+
diff --git a/patches/0131-iio-adc-rcar-gyroadc-Cast-pointer-to-uintptr_t-to-fi.patch b/patches/0131-iio-adc-rcar-gyroadc-Cast-pointer-to-uintptr_t-to-fi.patch
new file mode 100644
index 00000000000000..bef29a44ffb767
--- /dev/null
+++ b/patches/0131-iio-adc-rcar-gyroadc-Cast-pointer-to-uintptr_t-to-fi.patch
@@ -0,0 +1,41 @@
+From 787344999da34444daf2e84b09842d9727455785 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:08:24 +0200
+Subject: [PATCH 0131/1795] iio: adc: rcar-gyroadc: Cast pointer to uintptr_t
+ to fix warning on 64-bit
+
+On 64-bit:
+
+    drivers/iio/adc/rcar-gyroadc.c: In function 'rcar_gyroadc_parse_subdevs':
+    drivers/iio/adc/rcar-gyroadc.c:352:15: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
+       childmode = (unsigned int)of_id->data;
+		   ^
+
+Cast the pointer to uintptr_t instead of unsigned int to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+(cherry picked from commit 2a35734564bd2dc4f73c9e230ff55892290a130f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iio/adc/rcar-gyroadc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/iio/adc/rcar-gyroadc.c b/drivers/iio/adc/rcar-gyroadc.c
+index 2cb5397ceeea..0098c66a1957 100644
+--- a/drivers/iio/adc/rcar-gyroadc.c
++++ b/drivers/iio/adc/rcar-gyroadc.c
+@@ -348,7 +348,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev)
+ 			continue;
+ 		}
+ 
+-		childmode = (unsigned int)of_id->data;
++		childmode = (uintptr_t)of_id->data;
+ 		switch (childmode) {
+ 		case RCAR_GYROADC_MODE_SELECT_1_MB88101A:
+ 			sample_width = 12;
+-- 
+2.19.0
+
diff --git a/patches/0132-iio-adc-rcar-gyroadc-Use-of_device_get_match_data-he.patch b/patches/0132-iio-adc-rcar-gyroadc-Use-of_device_get_match_data-he.patch
new file mode 100644
index 00000000000000..d0e09ae5c302a5
--- /dev/null
+++ b/patches/0132-iio-adc-rcar-gyroadc-Use-of_device_get_match_data-he.patch
@@ -0,0 +1,46 @@
+From d10899cae0b09f10acd2528d3c93ebe25f9453d8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:08:26 +0200
+Subject: [PATCH 0132/1795] iio: adc: rcar-gyroadc: Use
+ of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+Note that the rcar-gyroadc driver is used with DT only, so there's
+always a valid match.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+(cherry picked from commit fb942f8ce6cdbacc087b808d89d09ff138c25bbe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iio/adc/rcar-gyroadc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/iio/adc/rcar-gyroadc.c b/drivers/iio/adc/rcar-gyroadc.c
+index 0098c66a1957..dcb50172186f 100644
+--- a/drivers/iio/adc/rcar-gyroadc.c
++++ b/drivers/iio/adc/rcar-gyroadc.c
+@@ -487,8 +487,6 @@ static int rcar_gyroadc_init_supplies(struct iio_dev *indio_dev)
+ 
+ static int rcar_gyroadc_probe(struct platform_device *pdev)
+ {
+-	const struct of_device_id *of_id =
+-		of_match_device(rcar_gyroadc_match, &pdev->dev);
+ 	struct device *dev = &pdev->dev;
+ 	struct rcar_gyroadc *priv;
+ 	struct iio_dev *indio_dev;
+@@ -525,7 +523,8 @@ static int rcar_gyroadc_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	priv->model = (enum rcar_gyroadc_model)of_id->data;
++	priv->model = (enum rcar_gyroadc_model)
++		of_device_get_match_data(&pdev->dev);
+ 
+ 	platform_set_drvdata(pdev, indio_dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0133-media-rcar_jpu-fix-two-kernel-doc-markups.patch b/patches/0133-media-rcar_jpu-fix-two-kernel-doc-markups.patch
new file mode 100644
index 00000000000000..c47a3456e64448
--- /dev/null
+++ b/patches/0133-media-rcar_jpu-fix-two-kernel-doc-markups.patch
@@ -0,0 +1,44 @@
+From 75d162a9a6afd91b698d8826c6d4f4f082f0b175 Mon Sep 17 00:00:00 2001
+From: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+Date: Wed, 29 Nov 2017 10:15:53 -0500
+Subject: [PATCH 0133/1795] media: rcar_jpu: fix two kernel-doc markups
+
+On kernel-doc, struct declarations should be declared as "struct foo".
+
+Fix the following warnings:
+	drivers/media/platform/rcar_jpu.c:265: warning: cannot understand function prototype: 'struct jpu_q_data '
+	drivers/media/platform/rcar_jpu.c:281: warning: cannot understand function prototype: 'struct jpu_ctx '
+
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 538cf6437af951f84cc816d63aafeafc61eb40c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar_jpu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/rcar_jpu.c b/drivers/media/platform/rcar_jpu.c
+index 2e2b8c409150..8b44a849ab41 100644
+--- a/drivers/media/platform/rcar_jpu.c
++++ b/drivers/media/platform/rcar_jpu.c
+@@ -257,7 +257,7 @@ struct jpu_fmt {
+ };
+ 
+ /**
+- * jpu_q_data - parameters of one queue
++ * struct jpu_q_data - parameters of one queue
+  * @fmtinfo: driver-specific format of this queue
+  * @format: multiplanar format of this queue
+  * @sequence: sequence number
+@@ -269,7 +269,7 @@ struct jpu_q_data {
+ };
+ 
+ /**
+- * jpu_ctx - the device context data
++ * struct jpu_ctx - the device context data
+  * @jpu: JPEG IP device for this context
+  * @encoder: compression (encode) operation or decompression (decode)
+  * @compr_quality: destination image quality in compression (encode) mode
+-- 
+2.19.0
+
diff --git a/patches/0134-soc-renesas-rcar-rst-add-R8A77970-support.patch b/patches/0134-soc-renesas-rcar-rst-add-R8A77970-support.patch
new file mode 100644
index 00000000000000..9c35461e3aebc6
--- /dev/null
+++ b/patches/0134-soc-renesas-rcar-rst-add-R8A77970-support.patch
@@ -0,0 +1,61 @@
+From 59eb5c3fb0fa6544972800f0ee7b9bf0d566a16a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:37:18 +0300
+Subject: [PATCH 0134/1795] soc: renesas: rcar-rst: add R8A77970 support
+
+Add support for R-Car V3M (R8A77970) to the R-Car RST driver -- this driver
+is  needed  for the clock driver to work.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 17760376ae31e06f66b3c3b8981f5978d4c53150)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
+ drivers/soc/renesas/Kconfig                             | 3 ++-
+ drivers/soc/renesas/rcar-rst.c                          | 1 +
+ 3 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+index e5a03ffe04fb..a8014f3ab8ba 100644
+--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
++++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+@@ -26,6 +26,7 @@ Required properties:
+ 		  - "renesas,r8a7794-rst" (R-Car E2)
+ 		  - "renesas,r8a7795-rst" (R-Car H3)
+ 		  - "renesas,r8a7796-rst" (R-Car M3-W)
++		  - "renesas,r8a77970-rst" (R-Car V3M)
+ 		  - "renesas,r8a77995-rst" (R-Car D3)
+   - reg: Address start and address range for the device.
+ 
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 567414cb42ba..f0d562a7c4d3 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -3,7 +3,8 @@ config SOC_RENESAS
+ 	default y if ARCH_RENESAS
+ 	select SOC_BUS
+ 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
+-			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77995
++			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \
++			   ARCH_R8A77995
+ 	select SYSC_R8A7743 if ARCH_R8A7743
+ 	select SYSC_R8A7745 if ARCH_R8A7745
+ 	select SYSC_R8A7779 if ARCH_R8A7779
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index baa47014e96b..3316b028f231 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -41,6 +41,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	/* R-Car Gen3 is handled like R-Car Gen2 */
+ 	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
++	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
+ 	{ /* sentinel */ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/0135-ASoC-rsnd-add-rsnd_dma_alloc.patch b/patches/0135-ASoC-rsnd-add-rsnd_dma_alloc.patch
new file mode 100644
index 00000000000000..4720ad03d2fe86
--- /dev/null
+++ b/patches/0135-ASoC-rsnd-add-rsnd_dma_alloc.patch
@@ -0,0 +1,124 @@
+From 08111dfc9f889edfd792570969ec80b6aef9b225 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 20 Sep 2017 06:28:44 +0000
+Subject: [PATCH 0135/1795] ASoC: rsnd: add rsnd_dma_alloc()
+
+R-Car sound DMA will be used from SSI/SRC.
+dma.c doesn't alloc DMA handler in .probe timing, because we don't
+know what kind of DMA transfer will be used then.
+Thus, SSI/SRC have *rsnd_mod for DMA. rsnd_dma_attach() will allocate
+it and attach it to system.
+It will be PIO mode if it can't alloc DMA handler.
+
+In case of MIX is used, rsnd_dma_attach() will be called twice from SSI.
+To avoid duplicate allocation, current rsnd_dma_attach() is checking
+allocated DMA handler. This DMA related operation is a little bit
+difficult to understand.
+This patch adds new rsnd_dma_alloc() and separates allocation and attach
+for readable code.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 81cb71240e202a8086bda0755d9d78bd3decd0aa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/dma.c | 60 ++++++++++++++++++++++-------------------
+ 1 file changed, 33 insertions(+), 27 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 041ec1080d52..17220c946ff0 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -753,14 +753,15 @@ static void rsnd_dma_of_path(struct rsnd_mod *this,
+ 	}
+ }
+ 
+-int rsnd_dma_attach(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
+-		    struct rsnd_mod **dma_mod)
++static int rsnd_dma_alloc(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
++			  struct rsnd_mod **dma_mod)
+ {
+ 	struct rsnd_mod *mod_from = NULL;
+ 	struct rsnd_mod *mod_to = NULL;
+ 	struct rsnd_priv *priv = rsnd_io_to_priv(io);
+ 	struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
+ 	struct device *dev = rsnd_priv_to_dev(priv);
++	struct rsnd_dma *dma;
+ 	struct rsnd_mod_ops *ops;
+ 	enum rsnd_mod_type type;
+ 	int (*attach)(struct rsnd_dai_stream *io, struct rsnd_dma *dma,
+@@ -800,40 +801,45 @@ int rsnd_dma_attach(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
+ 		type	= RSND_MOD_AUDMA;
+ 	}
+ 
+-	if (!(*dma_mod)) {
+-		struct rsnd_dma *dma;
++	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
++	if (!dma)
++		return -ENOMEM;
+ 
+-		dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
+-		if (!dma)
+-			return -ENOMEM;
++	*dma_mod = rsnd_mod_get(dma);
+ 
+-		*dma_mod = rsnd_mod_get(dma);
++	ret = rsnd_mod_init(priv, *dma_mod, ops, NULL,
++			    rsnd_mod_get_status, type, dma_id);
++	if (ret < 0)
++		return ret;
+ 
+-		ret = rsnd_mod_init(priv, *dma_mod, ops, NULL,
+-				    rsnd_mod_get_status, type, dma_id);
+-		if (ret < 0)
+-			return ret;
++	dev_dbg(dev, "%s[%d] %s[%d] -> %s[%d]\n",
++		rsnd_mod_name(*dma_mod), rsnd_mod_id(*dma_mod),
++		rsnd_mod_name(mod_from), rsnd_mod_id(mod_from),
++		rsnd_mod_name(mod_to),   rsnd_mod_id(mod_to));
++
++	ret = attach(io, dma, mod_from, mod_to);
++	if (ret < 0)
++		return ret;
+ 
+-		dev_dbg(dev, "%s[%d] %s[%d] -> %s[%d]\n",
+-			rsnd_mod_name(*dma_mod), rsnd_mod_id(*dma_mod),
+-			rsnd_mod_name(mod_from), rsnd_mod_id(mod_from),
+-			rsnd_mod_name(mod_to),   rsnd_mod_id(mod_to));
++	dma->src_addr = rsnd_dma_addr(io, mod_from, is_play, 1);
++	dma->dst_addr = rsnd_dma_addr(io, mod_to,   is_play, 0);
++	dma->mod_from = mod_from;
++	dma->mod_to   = mod_to;
++
++	return 0;
++}
++
++int rsnd_dma_attach(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
++		    struct rsnd_mod **dma_mod)
++{
++	if (!(*dma_mod)) {
++		int ret = rsnd_dma_alloc(io, mod, dma_mod);
+ 
+-		ret = attach(io, dma, mod_from, mod_to);
+ 		if (ret < 0)
+ 			return ret;
+-
+-		dma->src_addr = rsnd_dma_addr(io, mod_from, is_play, 1);
+-		dma->dst_addr = rsnd_dma_addr(io, mod_to,   is_play, 0);
+-		dma->mod_from = mod_from;
+-		dma->mod_to   = mod_to;
+ 	}
+ 
+-	ret = rsnd_dai_connect(*dma_mod, io, type);
+-	if (ret < 0)
+-		return ret;
+-
+-	return 0;
++	return rsnd_dai_connect(*dma_mod, io, (*dma_mod)->type);
+ }
+ 
+ int rsnd_dma_probe(struct rsnd_priv *priv)
+-- 
+2.19.0
+
diff --git a/patches/0136-ASoC-rcar-skip-disabled-SSI-nodes.patch b/patches/0136-ASoC-rcar-skip-disabled-SSI-nodes.patch
new file mode 100644
index 00000000000000..02c9b718c06cc0
--- /dev/null
+++ b/patches/0136-ASoC-rcar-skip-disabled-SSI-nodes.patch
@@ -0,0 +1,47 @@
+From 88596adc617181ff2bd238bdf090b5a1ebef085b Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 2 Oct 2017 07:37:32 +0000
+Subject: [PATCH 0136/1795] ASoC: rcar: skip disabled-SSI nodes
+
+The current device tree representation of the R-Car SSI assumes that they
+are numbered consecutively, starting from 0. Alas, this is not the case
+with the R8A77995 (D3) SoC which SSI1/SSI2 aren't present. In order to
+keep the existing device trees working, I'm suggesting to use a disabled
+node for SSI0/SSI1. Teach the SSI probe to just skip disabled nodes.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 9e9e95df06433b4f89cfeef0003af091ee0ebc86)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index f0fb85fda42d..fa2469042876 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -1121,6 +1121,9 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
+ 
+ 	i = 0;
+ 	for_each_child_of_node(node, np) {
++		if (!of_device_is_available(np))
++			goto skip;
++
+ 		ssi = rsnd_ssi_get(priv, i);
+ 
+ 		snprintf(name, RSND_SSI_NAME_SIZE, "%s.%d",
+@@ -1157,7 +1160,7 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
+ 			of_node_put(np);
+ 			goto rsnd_ssi_probe_done;
+ 		}
+-
++skip:
+ 		i++;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0137-ASoC-rsnd-add-generic-rsnd_flags_xxx-macro.patch b/patches/0137-ASoC-rsnd-add-generic-rsnd_flags_xxx-macro.patch
new file mode 100644
index 00000000000000..6a15cca1b962a9
--- /dev/null
+++ b/patches/0137-ASoC-rsnd-add-generic-rsnd_flags_xxx-macro.patch
@@ -0,0 +1,141 @@
+From 38f0b4611e000c59db9c86d7d2eb5ddb7c8daf55 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:47:50 +0000
+Subject: [PATCH 0137/1795] ASoC: rsnd: add generic rsnd_flags_xxx() macro
+
+SSI is using rsnd_ssi_flags_xxx() macro to control flags.
+But it is useful macro not only for SSI. This patch replace it
+to more generic rsnd_flags_xxx().
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 429919890e22431bc350ecf47b31866bb27631b2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/rsnd.h |  4 ++++
+ sound/soc/sh/rcar/ssi.c  | 27 ++++++++++++---------------
+ 2 files changed, 16 insertions(+), 15 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index c5de71f2dc8c..beffbec42404 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -601,6 +601,10 @@ struct rsnd_priv {
+ #define rsnd_is_gen1(priv)	(((priv)->flags & RSND_GEN_MASK) == RSND_GEN1)
+ #define rsnd_is_gen2(priv)	(((priv)->flags & RSND_GEN_MASK) == RSND_GEN2)
+ 
++#define rsnd_flags_has(p, f) ((p)->flags & (f))
++#define rsnd_flags_set(p, f) ((p)->flags |= (f))
++#define rsnd_flags_del(p, f) ((p)->flags &= ~(f))
++
+ /*
+  *	rsnd_kctrl
+  */
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index fa2469042876..d64abbbe1a98 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -101,9 +101,6 @@ struct rsnd_ssi {
+ #define rsnd_ssi_get(priv, id) ((struct rsnd_ssi *)(priv->ssi) + id)
+ #define rsnd_ssi_nr(priv) ((priv)->ssi_nr)
+ #define rsnd_mod_to_ssi(_mod) container_of((_mod), struct rsnd_ssi, mod)
+-#define rsnd_ssi_flags_has(p, f) ((p)->flags & f)
+-#define rsnd_ssi_flags_set(p, f) ((p)->flags |= f)
+-#define rsnd_ssi_flags_del(p, f) ((p)->flags = ((p)->flags & ~f))
+ #define rsnd_ssi_is_parent(ssi, io) ((ssi) == rsnd_io_to_mod_ssip(io))
+ #define rsnd_ssi_is_multi_slave(mod, io) \
+ 	(rsnd_ssi_multi_slaves(io) & (1 << rsnd_mod_id(mod)))
+@@ -116,10 +113,10 @@ int rsnd_ssi_hdmi_port(struct rsnd_dai_stream *io)
+ 	struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
+ 	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
+ 
+-	if (rsnd_ssi_flags_has(ssi, RSND_SSI_HDMI0))
++	if (rsnd_flags_has(ssi, RSND_SSI_HDMI0))
+ 		return RSND_SSI_HDMI_PORT0;
+ 
+-	if (rsnd_ssi_flags_has(ssi, RSND_SSI_HDMI1))
++	if (rsnd_flags_has(ssi, RSND_SSI_HDMI1))
+ 		return RSND_SSI_HDMI_PORT1;
+ 
+ 	return 0;
+@@ -134,7 +131,7 @@ int rsnd_ssi_use_busif(struct rsnd_dai_stream *io)
+ 	if (!rsnd_ssi_is_dma_mode(mod))
+ 		return 0;
+ 
+-	if (!(rsnd_ssi_flags_has(ssi, RSND_SSI_NO_BUSIF)))
++	if (!(rsnd_flags_has(ssi, RSND_SSI_NO_BUSIF)))
+ 		use_busif = 1;
+ 	if (rsnd_io_to_mod_src(io))
+ 		use_busif = 1;
+@@ -802,13 +799,13 @@ static int rsnd_ssi_common_probe(struct rsnd_mod *mod,
+ 	 * But it don't need to call request_irq() many times.
+ 	 * Let's control it by RSND_SSI_PROBED flag.
+ 	 */
+-	if (!rsnd_ssi_flags_has(ssi, RSND_SSI_PROBED)) {
++	if (!rsnd_flags_has(ssi, RSND_SSI_PROBED)) {
+ 		ret = request_irq(ssi->irq,
+ 				  rsnd_ssi_interrupt,
+ 				  IRQF_SHARED,
+ 				  dev_name(dev), mod);
+ 
+-		rsnd_ssi_flags_set(ssi, RSND_SSI_PROBED);
++		rsnd_flags_set(ssi, RSND_SSI_PROBED);
+ 	}
+ 
+ 	return ret;
+@@ -826,10 +823,10 @@ static int rsnd_ssi_common_remove(struct rsnd_mod *mod,
+ 		return 0;
+ 
+ 	/* PIO will request IRQ again */
+-	if (rsnd_ssi_flags_has(ssi, RSND_SSI_PROBED)) {
++	if (rsnd_flags_has(ssi, RSND_SSI_PROBED)) {
+ 		free_irq(ssi->irq, mod);
+ 
+-		rsnd_ssi_flags_del(ssi, RSND_SSI_PROBED);
++		rsnd_flags_del(ssi, RSND_SSI_PROBED);
+ 	}
+ 
+ 	return 0;
+@@ -1012,13 +1009,13 @@ static void __rsnd_ssi_parse_hdmi_connection(struct rsnd_priv *priv,
+ 	ssi  = rsnd_mod_to_ssi(mod);
+ 
+ 	if (strstr(remote_ep->full_name, "hdmi0")) {
+-		rsnd_ssi_flags_set(ssi, RSND_SSI_HDMI0);
++		rsnd_flags_set(ssi, RSND_SSI_HDMI0);
+ 		dev_dbg(dev, "%s[%d] connected to HDMI0\n",
+ 			 rsnd_mod_name(mod), rsnd_mod_id(mod));
+ 	}
+ 
+ 	if (strstr(remote_ep->full_name, "hdmi1")) {
+-		rsnd_ssi_flags_set(ssi, RSND_SSI_HDMI1);
++		rsnd_flags_set(ssi, RSND_SSI_HDMI1);
+ 		dev_dbg(dev, "%s[%d] connected to HDMI1\n",
+ 			rsnd_mod_name(mod), rsnd_mod_id(mod));
+ 	}
+@@ -1051,7 +1048,7 @@ int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod)
+ {
+ 	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
+ 
+-	return !!(rsnd_ssi_flags_has(ssi, RSND_SSI_CLK_PIN_SHARE));
++	return !!(rsnd_flags_has(ssi, RSND_SSI_CLK_PIN_SHARE));
+ }
+ 
+ static u32 *rsnd_ssi_get_status(struct rsnd_dai_stream *io,
+@@ -1137,10 +1134,10 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
+ 		}
+ 
+ 		if (of_get_property(np, "shared-pin", NULL))
+-			rsnd_ssi_flags_set(ssi, RSND_SSI_CLK_PIN_SHARE);
++			rsnd_flags_set(ssi, RSND_SSI_CLK_PIN_SHARE);
+ 
+ 		if (of_get_property(np, "no-busif", NULL))
+-			rsnd_ssi_flags_set(ssi, RSND_SSI_NO_BUSIF);
++			rsnd_flags_set(ssi, RSND_SSI_NO_BUSIF);
+ 
+ 		ssi->irq = irq_of_parse_and_map(np, 0);
+ 		if (!ssi->irq) {
+-- 
+2.19.0
+
diff --git a/patches/0138-ASoC-rsnd-use-generic-rsnd_flags_xxx-macro-on-ADG.patch b/patches/0138-ASoC-rsnd-use-generic-rsnd_flags_xxx-macro-on-ADG.patch
new file mode 100644
index 00000000000000..46c773d53028e0
--- /dev/null
+++ b/patches/0138-ASoC-rsnd-use-generic-rsnd_flags_xxx-macro-on-ADG.patch
@@ -0,0 +1,73 @@
+From d668328c39d03d5f5d3452f1d5855963edcb4f64 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:48:12 +0000
+Subject: [PATCH 0138/1795] ASoC: rsnd: use generic rsnd_flags_xxx() macro on
+ ADG
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit d0cf7fc948159a3eab9ad2e959cce7f06f2333df)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/adg.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c
+index e28edb1f7263..f21179f29b6c 100644
+--- a/sound/soc/sh/rcar/adg.c
++++ b/sound/soc/sh/rcar/adg.c
+@@ -44,7 +44,6 @@ struct rsnd_adg {
+ 
+ #define LRCLK_ASYNC	(1 << 0)
+ #define AUDIO_OUT_48	(1 << 1)
+-#define adg_mode_flags(adg)	(adg->flags)
+ 
+ #define for_each_rsnd_clk(pos, adg, i)		\
+ 	for (i = 0;				\
+@@ -366,8 +365,8 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
+ 
+ 	rsnd_adg_set_ssi_clk(ssi_mod, data);
+ 
+-	if (adg_mode_flags(adg) & LRCLK_ASYNC) {
+-		if (adg_mode_flags(adg) & AUDIO_OUT_48)
++	if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
++		if (rsnd_flags_has(adg, AUDIO_OUT_48))
+ 			ckr = 0x80000000;
+ 	} else {
+ 		if (0 == (rate % 8000))
+@@ -479,10 +478,10 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
+ 	}
+ 
+ 	if (req_rate[0] % 48000 == 0)
+-		adg->flags |= AUDIO_OUT_48;
++		rsnd_flags_set(adg, AUDIO_OUT_48);
+ 
+ 	if (of_get_property(np, "clkout-lr-asynchronous", NULL))
+-		adg->flags |= LRCLK_ASYNC;
++		rsnd_flags_set(adg, LRCLK_ASYNC);
+ 
+ 	/*
+ 	 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
+@@ -512,7 +511,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
+ 				adg->rbga_rate_for_441khz = rate / div;
+ 				ckr |= brg_table[i] << 20;
+ 				if (req_441kHz_rate &&
+-				    !(adg_mode_flags(adg) & AUDIO_OUT_48))
++				    !rsnd_flags_has(adg, AUDIO_OUT_48))
+ 					parent_clk_name = __clk_get_name(clk);
+ 			}
+ 		}
+@@ -528,7 +527,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
+ 				adg->rbgb_rate_for_48khz = rate / div;
+ 				ckr |= brg_table[i] << 16;
+ 				if (req_48kHz_rate &&
+-				    (adg_mode_flags(adg) & AUDIO_OUT_48))
++				    rsnd_flags_has(adg, AUDIO_OUT_48))
+ 					parent_clk_name = __clk_get_name(clk);
+ 			}
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/0139-ASoC-rsnd-DVC-kctrl-sets-once.patch b/patches/0139-ASoC-rsnd-DVC-kctrl-sets-once.patch
new file mode 100644
index 00000000000000..40bd654f0fb46f
--- /dev/null
+++ b/patches/0139-ASoC-rsnd-DVC-kctrl-sets-once.patch
@@ -0,0 +1,63 @@
+From 1b2cc117f049d4b30c5ce3801b5f841a48268da8 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:48:29 +0000
+Subject: [PATCH 0139/1795] ASoC: rsnd: DVC kctrl sets once
+
+Same DVC might be used few times if system/platform is using MIX.
+For example below case.
+
+	DAI0 playback = <&src0 &ctu02 &mix0 &dvc0 &ssi0>;
+	DAI1 playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>;
+
+This case, ALSA will have DVC,0 and DVC,1 kcontrol interfaces,
+but these are same DVC. This is confusing.
+This patch adds new flags and avoid such case.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b918f1bc7f1ce463d6fbb6ebf3db36bd302bded8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/dvc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c
+index 1743ade3cc55..bb22850e8fe6 100644
+--- a/sound/soc/sh/rcar/dvc.c
++++ b/sound/soc/sh/rcar/dvc.c
+@@ -44,8 +44,11 @@ struct rsnd_dvc {
+ 	struct rsnd_kctrl_cfg_s ren;	/* Ramp Enable */
+ 	struct rsnd_kctrl_cfg_s rup;	/* Ramp Rate Up */
+ 	struct rsnd_kctrl_cfg_s rdown;	/* Ramp Rate Down */
++	u32 flags;
+ };
+ 
++#define KCTRL_INITIALIZED	(1 << 0)
++
+ #define rsnd_dvc_get(priv, id) ((struct rsnd_dvc *)(priv->dvc) + id)
+ #define rsnd_dvc_nr(priv) ((priv)->dvc_nr)
+ 
+@@ -254,6 +257,9 @@ static int rsnd_dvc_pcm_new(struct rsnd_mod *mod,
+ 	int channels = rsnd_rdai_channels_get(rdai);
+ 	int ret;
+ 
++	if (rsnd_flags_has(dvc, KCTRL_INITIALIZED))
++		return 0;
++
+ 	/* Volume */
+ 	ret = rsnd_kctrl_new_m(mod, io, rtd,
+ 			is_play ?
+@@ -307,6 +313,8 @@ static int rsnd_dvc_pcm_new(struct rsnd_mod *mod,
+ 	if (ret < 0)
+ 		return ret;
+ 
++	rsnd_flags_set(dvc, KCTRL_INITIALIZED);
++
+ 	return 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0140-ASoC-rsnd-CTU-kctrl-sets-once.patch b/patches/0140-ASoC-rsnd-CTU-kctrl-sets-once.patch
new file mode 100644
index 00000000000000..557cb04ca170a4
--- /dev/null
+++ b/patches/0140-ASoC-rsnd-CTU-kctrl-sets-once.patch
@@ -0,0 +1,63 @@
+From d672412e3dff1da5870e1f6c97050eabc1be8bb7 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:48:46 +0000
+Subject: [PATCH 0140/1795] ASoC: rsnd: CTU kctrl sets once
+
+Same CTU might be used few times if system/platform is using MIX.
+For example below case.
+
+	DAI0 playback = <&src0 &ctu02 &mix0 &dvc0 &ssi0>;
+	DAI1 playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>;
+
+This case, ALSA will have CTU,0 and CTU,1 kcontrol interfaces,
+but these are same CTU. This is confusing.
+This patch adds new flags and avoid such case.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 99dc79d0600849ff878a38d9884e76f5bebd3228)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ctu.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c
+index e7f53f44165d..ad07ba8c3720 100644
+--- a/sound/soc/sh/rcar/ctu.c
++++ b/sound/soc/sh/rcar/ctu.c
+@@ -81,8 +81,11 @@ struct rsnd_ctu {
+ 	struct rsnd_kctrl_cfg_m sv3;
+ 	struct rsnd_kctrl_cfg_s reset;
+ 	int channels;
++	u32 flags;
+ };
+ 
++#define KCTRL_INITIALIZED	(1 << 0)
++
+ #define rsnd_ctu_nr(priv) ((priv)->ctu_nr)
+ #define for_each_rsnd_ctu(pos, priv, i)					\
+ 	for ((i) = 0;							\
+@@ -277,6 +280,9 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
+ 	struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
+ 	int ret;
+ 
++	if (rsnd_flags_has(ctu, KCTRL_INITIALIZED))
++		return 0;
++
+ 	/* CTU Pass */
+ 	ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU Pass",
+ 			       rsnd_kctrl_accept_anytime,
+@@ -326,6 +332,8 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
+ 			       rsnd_ctu_value_reset,
+ 			       &ctu->reset, 1);
+ 
++	rsnd_flags_set(ctu, KCTRL_INITIALIZED);
++
+ 	return ret;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0141-ASoC-rsnd-makes-volume-ramp-rate-list-generic.patch b/patches/0141-ASoC-rsnd-makes-volume-ramp-rate-list-generic.patch
new file mode 100644
index 00000000000000..31cb28c884ed83
--- /dev/null
+++ b/patches/0141-ASoC-rsnd-makes-volume-ramp-rate-list-generic.patch
@@ -0,0 +1,140 @@
+From 5da97aa1b64e106d34c4d8686043b2723cfdddd8 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:49:03 +0000
+Subject: [PATCH 0141/1795] ASoC: rsnd: makes volume ramp rate list generic
+
+DVC is supporting Volume Ramp Rate, and MIX has Volume Ramp
+but not yet supported. To support MIX Volume Ramp, we want to
+share Rate List since DVC/MIX are using almost same list.
+This patch move DVC specific Volume Ramp Rate List to core.c.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit f3c26ac61c09862f0037fe484a98da0364f02ec3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 27 +++++++++++++++++++++++++++
+ sound/soc/sh/rcar/dvc.c  | 33 ++++-----------------------------
+ sound/soc/sh/rcar/rsnd.h |  7 +++++--
+ 3 files changed, 36 insertions(+), 31 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 107133297e8d..2d94b3d4519c 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1242,6 +1242,33 @@ struct rsnd_kctrl_cfg *rsnd_kctrl_init_s(struct rsnd_kctrl_cfg_s *cfg)
+ 	return &cfg->cfg;
+ }
+ 
++const char * const volume_ramp_rate[] = {
++	"128 dB/1 step",	 /* 00000 */
++	"64 dB/1 step",		 /* 00001 */
++	"32 dB/1 step",		 /* 00010 */
++	"16 dB/1 step",		 /* 00011 */
++	"8 dB/1 step",		 /* 00100 */
++	"4 dB/1 step",		 /* 00101 */
++	"2 dB/1 step",		 /* 00110 */
++	"1 dB/1 step",		 /* 00111 */
++	"0.5 dB/1 step",	 /* 01000 */
++	"0.25 dB/1 step",	 /* 01001 */
++	"0.125 dB/1 step",	 /* 01010 */
++	"0.125 dB/2 steps",	 /* 01011 */
++	"0.125 dB/4 steps",	 /* 01100 */
++	"0.125 dB/8 steps",	 /* 01101 */
++	"0.125 dB/16 steps",	 /* 01110 */
++	"0.125 dB/32 steps",	 /* 01111 */
++	"0.125 dB/64 steps",	 /* 10000 */
++	"0.125 dB/128 steps",	 /* 10001 */
++	"0.125 dB/256 steps",	 /* 10010 */
++	"0.125 dB/512 steps",	 /* 10011 */
++	"0.125 dB/1024 steps",	 /* 10100 */
++	"0.125 dB/2048 steps",	 /* 10101 */
++	"0.125 dB/4096 steps",	 /* 10110 */
++	"0.125 dB/8192 steps",	 /* 10111 = VOLUME_RAMP_MAX_DVC */
++};
++
+ int rsnd_kctrl_new(struct rsnd_mod *mod,
+ 		   struct rsnd_dai_stream *io,
+ 		   struct snd_soc_pcm_runtime *rtd,
+diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c
+index bb22850e8fe6..4ef318ac73d5 100644
+--- a/sound/soc/sh/rcar/dvc.c
++++ b/sound/soc/sh/rcar/dvc.c
+@@ -61,33 +61,6 @@ struct rsnd_dvc {
+ 	     ((pos) = (struct rsnd_dvc *)(priv)->dvc + i);	\
+ 	     i++)
+ 
+-static const char * const dvc_ramp_rate[] = {
+-	"128 dB/1 step",	 /* 00000 */
+-	"64 dB/1 step",		 /* 00001 */
+-	"32 dB/1 step",		 /* 00010 */
+-	"16 dB/1 step",		 /* 00011 */
+-	"8 dB/1 step",		 /* 00100 */
+-	"4 dB/1 step",		 /* 00101 */
+-	"2 dB/1 step",		 /* 00110 */
+-	"1 dB/1 step",		 /* 00111 */
+-	"0.5 dB/1 step",	 /* 01000 */
+-	"0.25 dB/1 step",	 /* 01001 */
+-	"0.125 dB/1 step",	 /* 01010 */
+-	"0.125 dB/2 steps",	 /* 01011 */
+-	"0.125 dB/4 steps",	 /* 01100 */
+-	"0.125 dB/8 steps",	 /* 01101 */
+-	"0.125 dB/16 steps",	 /* 01110 */
+-	"0.125 dB/32 steps",	 /* 01111 */
+-	"0.125 dB/64 steps",	 /* 10000 */
+-	"0.125 dB/128 steps",	 /* 10001 */
+-	"0.125 dB/256 steps",	 /* 10010 */
+-	"0.125 dB/512 steps",	 /* 10011 */
+-	"0.125 dB/1024 steps",	 /* 10100 */
+-	"0.125 dB/2048 steps",	 /* 10101 */
+-	"0.125 dB/4096 steps",	 /* 10110 */
+-	"0.125 dB/8192 steps",	 /* 10111 */
+-};
+-
+ static void rsnd_dvc_activation(struct rsnd_mod *mod)
+ {
+ 	rsnd_mod_write(mod, DVC_SWRSR, 0);
+@@ -298,7 +271,8 @@ static int rsnd_dvc_pcm_new(struct rsnd_mod *mod,
+ 			rsnd_kctrl_accept_anytime,
+ 			rsnd_dvc_volume_update,
+ 			&dvc->rup,
+-			dvc_ramp_rate);
++			volume_ramp_rate,
++			VOLUME_RAMP_MAX_DVC);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -308,7 +282,8 @@ static int rsnd_dvc_pcm_new(struct rsnd_mod *mod,
+ 			rsnd_kctrl_accept_anytime,
+ 			rsnd_dvc_volume_update,
+ 			&dvc->rdown,
+-			dvc_ramp_rate);
++			volume_ramp_rate,
++			VOLUME_RAMP_MAX_DVC);
+ 
+ 	if (ret < 0)
+ 		return ret;
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index beffbec42404..9d66a15000fa 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -656,9 +656,12 @@ int rsnd_kctrl_new(struct rsnd_mod *mod,
+ 	rsnd_kctrl_new(mod, io, rtd, name, accept, update, rsnd_kctrl_init_s(cfg), \
+ 		       NULL, 1, max)
+ 
+-#define rsnd_kctrl_new_e(mod, io, rtd, name, accept, update, cfg, texts)	\
++#define rsnd_kctrl_new_e(mod, io, rtd, name, accept, update, cfg, texts, size) \
+ 	rsnd_kctrl_new(mod, io, rtd, name, accept, update, rsnd_kctrl_init_s(cfg), \
+-		       texts, 1, ARRAY_SIZE(texts))
++		       texts, 1, size)
++
++extern const char * const volume_ramp_rate[];
++#define VOLUME_RAMP_MAX_DVC	(0x17 + 1)
+ 
+ /*
+  *	R-Car SSI
+-- 
+2.19.0
+
diff --git a/patches/0142-ASoC-rsnd-add-MIX-Volume-Ramp-support.patch b/patches/0142-ASoC-rsnd-add-MIX-Volume-Ramp-support.patch
new file mode 100644
index 00000000000000..ec0788ffed0c95
--- /dev/null
+++ b/patches/0142-ASoC-rsnd-add-MIX-Volume-Ramp-support.patch
@@ -0,0 +1,269 @@
+From e22d997e419e05cc57fbeed7c9ce099edec6ceea Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Sun, 1 Oct 2017 23:49:18 +0000
+Subject: [PATCH 0142/1795] ASoC: rsnd: add MIX Volume Ramp support
+
+Both DVC/MIX have Volume Ramp Control. This patch supprts MIX
+Volume Ramp. One note is that main purpose of MIX Volume Ramp
+is to reduce noise, thus, MIX Ramp range is very few if you
+compare to DVC Volume Ramp (DVC = 5bit, MIX = 4bit).
+
+You can use MIX Volume Ranp like below
+	amixer set "MIX Ramp Up Rate"   "0.125 dB/1 step"
+	amixer set "MIX Ramp Down Rate" "0.125 dB/1 step"
+	amixer set "MIX Ramp" on
+	aplay xxx.wav &
+	amixer set "MIX",0  80%  // DAI0 Volume Down
+	amixer set "MIX",1 100%  // DAI1 Volume Up
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 3e3c9ee1e4b3d0ef1f68f2037752196e7260bad9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c |   2 +-
+ sound/soc/sh/rcar/mix.c  | 158 +++++++++++++++++++++++++++++++++++++--
+ sound/soc/sh/rcar/rsnd.h |   1 +
+ 3 files changed, 154 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 2d94b3d4519c..e9b0b0f5f0ee 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1253,7 +1253,7 @@ const char * const volume_ramp_rate[] = {
+ 	"1 dB/1 step",		 /* 00111 */
+ 	"0.5 dB/1 step",	 /* 01000 */
+ 	"0.25 dB/1 step",	 /* 01001 */
+-	"0.125 dB/1 step",	 /* 01010 */
++	"0.125 dB/1 step",	 /* 01010 = VOLUME_RAMP_MAX_MIX */
+ 	"0.125 dB/2 steps",	 /* 01011 */
+ 	"0.125 dB/4 steps",	 /* 01100 */
+ 	"0.125 dB/8 steps",	 /* 01101 */
+diff --git a/sound/soc/sh/rcar/mix.c b/sound/soc/sh/rcar/mix.c
+index 6c4826c189a4..912cfec49038 100644
+--- a/sound/soc/sh/rcar/mix.c
++++ b/sound/soc/sh/rcar/mix.c
+@@ -7,6 +7,33 @@
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
++
++/*
++ *		    CTUn	MIXn
++ *		    +------+	+------+
++ * [SRC3 / SRC6] -> |CTU n0| ->	[MIX n0| ->
++ * [SRC4 / SRC9] -> |CTU n1| ->	[MIX n1| ->
++ * [SRC0 / SRC1] -> |CTU n2| ->	[MIX n2| ->
++ * [SRC2 / SRC5] -> |CTU n3| ->	[MIX n3| ->
++ *		    +------+	+------+
++ *
++ * ex)
++ *	DAI0 : playback = <&src0 &ctu02 &mix0 &dvc0 &ssi0>;
++ *	DAI1 : playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>;
++ *
++ * MIX Volume
++ *	amixer set "MIX",0  100%  // DAI0 Volume
++ *	amixer set "MIX",1  100%  // DAI1 Volume
++ *
++ * Volume Ramp
++ *	amixer set "MIX Ramp Up Rate"   "0.125 dB/1 step"
++ *	amixer set "MIX Ramp Down Rate" "4 dB/1 step"
++ *	amixer set "MIX Ramp" on
++ *	aplay xxx.wav &
++ *	amixer set "MIX",0  80%  // DAI0 Volume Down
++ *	amixer set "MIX",1 100%  // DAI1 Volume Up
++ */
++
+ #include "rsnd.h"
+ 
+ #define MIX_NAME_SIZE	16
+@@ -14,8 +41,27 @@
+ 
+ struct rsnd_mix {
+ 	struct rsnd_mod mod;
++	struct rsnd_kctrl_cfg_s volumeA; /* MDBAR */
++	struct rsnd_kctrl_cfg_s volumeB; /* MDBBR */
++	struct rsnd_kctrl_cfg_s volumeC; /* MDBCR */
++	struct rsnd_kctrl_cfg_s volumeD; /* MDBDR */
++	struct rsnd_kctrl_cfg_s ren;	/* Ramp Enable */
++	struct rsnd_kctrl_cfg_s rup;	/* Ramp Rate Up */
++	struct rsnd_kctrl_cfg_s rdw;	/* Ramp Rate Down */
++	u32 flags;
+ };
+ 
++#define ONCE_KCTRL_INITIALIZED		(1 << 0)
++#define HAS_VOLA			(1 << 1)
++#define HAS_VOLB			(1 << 2)
++#define HAS_VOLC			(1 << 3)
++#define HAS_VOLD			(1 << 4)
++
++#define VOL_MAX				0x3ff
++
++#define rsnd_mod_to_mix(_mod)	\
++	container_of((_mod), struct rsnd_mix, mod)
++
+ #define rsnd_mix_get(priv, id) ((struct rsnd_mix *)(priv->mix) + id)
+ #define rsnd_mix_nr(priv) ((priv)->mix_nr)
+ #define for_each_rsnd_mix(pos, priv, i)					\
+@@ -36,26 +82,43 @@ static void rsnd_mix_halt(struct rsnd_mod *mod)
+ 	rsnd_mod_write(mod, MIX_SWRSR, 0);
+ }
+ 
++#define rsnd_mix_get_vol(mix, X) \
++	rsnd_flags_has(mix, HAS_VOL##X) ? \
++		(VOL_MAX - mix->volume##X.cfg.val[0]) : 0
+ static void rsnd_mix_volume_parameter(struct rsnd_dai_stream *io,
+ 				      struct rsnd_mod *mod)
+ {
+-	rsnd_mod_write(mod, MIX_MDBAR, 0);
+-	rsnd_mod_write(mod, MIX_MDBBR, 0);
+-	rsnd_mod_write(mod, MIX_MDBCR, 0);
+-	rsnd_mod_write(mod, MIX_MDBDR, 0);
++	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
++	struct device *dev = rsnd_priv_to_dev(priv);
++	struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
++	u32 volA = rsnd_mix_get_vol(mix, A);
++	u32 volB = rsnd_mix_get_vol(mix, B);
++	u32 volC = rsnd_mix_get_vol(mix, C);
++	u32 volD = rsnd_mix_get_vol(mix, D);
++
++	dev_dbg(dev, "MIX A/B/C/D = %02x/%02x/%02x/%02x\n",
++		volA, volB, volC, volD);
++
++	rsnd_mod_write(mod, MIX_MDBAR, volA);
++	rsnd_mod_write(mod, MIX_MDBBR, volB);
++	rsnd_mod_write(mod, MIX_MDBCR, volC);
++	rsnd_mod_write(mod, MIX_MDBDR, volD);
+ }
+ 
+ static void rsnd_mix_volume_init(struct rsnd_dai_stream *io,
+ 				 struct rsnd_mod *mod)
+ {
++	struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
++
+ 	rsnd_mod_write(mod, MIX_MIXIR, 1);
+ 
+ 	/* General Information */
+ 	rsnd_mod_write(mod, MIX_ADINR, rsnd_runtime_channel_after_ctu(io));
+ 
+ 	/* volume step */
+-	rsnd_mod_write(mod, MIX_MIXMR, 0);
+-	rsnd_mod_write(mod, MIX_MVPDR, 0);
++	rsnd_mod_write(mod, MIX_MIXMR, mix->ren.cfg.val[0]);
++	rsnd_mod_write(mod, MIX_MVPDR, mix->rup.cfg.val[0] << 8 |
++				       mix->rdw.cfg.val[0]);
+ 
+ 	/* common volume parameter */
+ 	rsnd_mix_volume_parameter(io, mod);
+@@ -109,11 +172,94 @@ static int rsnd_mix_quit(struct rsnd_mod *mod,
+ 	return 0;
+ }
+ 
++static int rsnd_mix_pcm_new(struct rsnd_mod *mod,
++			    struct rsnd_dai_stream *io,
++			    struct snd_soc_pcm_runtime *rtd)
++{
++	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
++	struct device *dev = rsnd_priv_to_dev(priv);
++	struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
++	struct rsnd_mod *src_mod = rsnd_io_to_mod_src(io);
++	struct rsnd_kctrl_cfg_s *volume;
++	int ret;
++
++	switch (rsnd_mod_id(src_mod)) {
++	case 3:
++	case 6:	/* MDBAR */
++		volume = &mix->volumeA;
++		rsnd_flags_set(mix, HAS_VOLA);
++		break;
++	case 4:
++	case 9:	/* MDBBR */
++		volume = &mix->volumeB;
++		rsnd_flags_set(mix, HAS_VOLB);
++		break;
++	case 0:
++	case 1:	/* MDBCR */
++		volume = &mix->volumeC;
++		rsnd_flags_set(mix, HAS_VOLC);
++		break;
++	case 2:
++	case 5:	/* MDBDR */
++		volume = &mix->volumeD;
++		rsnd_flags_set(mix, HAS_VOLD);
++		break;
++	default:
++		dev_err(dev, "unknown SRC is connected\n");
++		return -EINVAL;
++	}
++
++	/* Volume */
++	ret = rsnd_kctrl_new_s(mod, io, rtd,
++			       "MIX Playback Volume",
++			       rsnd_kctrl_accept_anytime,
++			       rsnd_mix_volume_update,
++			       volume, VOL_MAX);
++	if (ret < 0)
++		return ret;
++	volume->cfg.val[0] = VOL_MAX;
++
++	if (rsnd_flags_has(mix, ONCE_KCTRL_INITIALIZED))
++		return ret;
++
++	/* Ramp */
++	ret = rsnd_kctrl_new_s(mod, io, rtd,
++			       "MIX Ramp Switch",
++			       rsnd_kctrl_accept_anytime,
++			       rsnd_mix_volume_update,
++			       &mix->ren, 1);
++	if (ret < 0)
++		return ret;
++
++	ret = rsnd_kctrl_new_e(mod, io, rtd,
++			       "MIX Ramp Up Rate",
++			       rsnd_kctrl_accept_anytime,
++			       rsnd_mix_volume_update,
++			       &mix->rup,
++			       volume_ramp_rate,
++			       VOLUME_RAMP_MAX_MIX);
++	if (ret < 0)
++		return ret;
++
++	ret = rsnd_kctrl_new_e(mod, io, rtd,
++			       "MIX Ramp Down Rate",
++			       rsnd_kctrl_accept_anytime,
++			       rsnd_mix_volume_update,
++			       &mix->rdw,
++			       volume_ramp_rate,
++			       VOLUME_RAMP_MAX_MIX);
++
++	rsnd_flags_set(mix, ONCE_KCTRL_INITIALIZED);
++
++	return ret;
++}
++
+ static struct rsnd_mod_ops rsnd_mix_ops = {
+ 	.name		= MIX_NAME,
+ 	.probe		= rsnd_mix_probe_,
+ 	.init		= rsnd_mix_init,
+ 	.quit		= rsnd_mix_quit,
++	.pcm_new	= rsnd_mix_pcm_new,
+ };
+ 
+ struct rsnd_mod *rsnd_mix_mod_get(struct rsnd_priv *priv, int id)
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 9d66a15000fa..0d9f9c3343da 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -662,6 +662,7 @@ int rsnd_kctrl_new(struct rsnd_mod *mod,
+ 
+ extern const char * const volume_ramp_rate[];
+ #define VOLUME_RAMP_MAX_DVC	(0x17 + 1)
++#define VOLUME_RAMP_MAX_MIX	(0x0a + 1)
+ 
+ /*
+  *	R-Car SSI
+-- 
+2.19.0
+
diff --git a/patches/0143-ASoC-rsnd-add-rsnd_kctrl_xxx-macro.patch b/patches/0143-ASoC-rsnd-add-rsnd_kctrl_xxx-macro.patch
new file mode 100644
index 00000000000000..21d2980e037b93
--- /dev/null
+++ b/patches/0143-ASoC-rsnd-add-rsnd_kctrl_xxx-macro.patch
@@ -0,0 +1,246 @@
+From 687afbcc6d83aadcaf4947e5b589e75258c542f7 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 11 Oct 2017 04:42:34 +0000
+Subject: [PATCH 0143/1795] ASoC: rsnd: add rsnd_kctrl_xxx() macro
+
+Current CTU/MIX/DVC are directly using rsnd_kctrl_cfg_m/s to control
+val etc, but it is difficult to read/understand.
+And there was no uniformity in access method.
+This patch adds new rsnd_kctrl_xxx() and implements uniformed access
+method.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 3a9fa27be507b19107a8b3fe03a67e8145aea88c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ctu.c  | 80 ++++++++++++++++++++--------------------
+ sound/soc/sh/rcar/dvc.c  | 19 +++++-----
+ sound/soc/sh/rcar/mix.c  | 10 ++---
+ sound/soc/sh/rcar/rsnd.h |  4 ++
+ 4 files changed, 59 insertions(+), 54 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c
+index ad07ba8c3720..d201d551866d 100644
+--- a/sound/soc/sh/rcar/ctu.c
++++ b/sound/soc/sh/rcar/ctu.c
+@@ -133,7 +133,7 @@ static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
+ 	int i;
+ 
+ 	for (i = 0; i < RSND_MAX_CHANNELS; i++) {
+-		u32 val = ctu->pass.val[i];
++		u32 val = rsnd_kctrl_valm(ctu->pass, i);
+ 
+ 		cpmdr |= val << (28 - (i * 4));
+ 
+@@ -150,44 +150,44 @@ static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
+ 	rsnd_mod_write(mod, CTU_SCMDR, scmdr);
+ 
+ 	if (scmdr > 0) {
+-		rsnd_mod_write(mod, CTU_SV00R, ctu->sv0.val[0]);
+-		rsnd_mod_write(mod, CTU_SV01R, ctu->sv0.val[1]);
+-		rsnd_mod_write(mod, CTU_SV02R, ctu->sv0.val[2]);
+-		rsnd_mod_write(mod, CTU_SV03R, ctu->sv0.val[3]);
+-		rsnd_mod_write(mod, CTU_SV04R, ctu->sv0.val[4]);
+-		rsnd_mod_write(mod, CTU_SV05R, ctu->sv0.val[5]);
+-		rsnd_mod_write(mod, CTU_SV06R, ctu->sv0.val[6]);
+-		rsnd_mod_write(mod, CTU_SV07R, ctu->sv0.val[7]);
++		rsnd_mod_write(mod, CTU_SV00R, rsnd_kctrl_valm(ctu->sv0, 0));
++		rsnd_mod_write(mod, CTU_SV01R, rsnd_kctrl_valm(ctu->sv0, 1));
++		rsnd_mod_write(mod, CTU_SV02R, rsnd_kctrl_valm(ctu->sv0, 2));
++		rsnd_mod_write(mod, CTU_SV03R, rsnd_kctrl_valm(ctu->sv0, 3));
++		rsnd_mod_write(mod, CTU_SV04R, rsnd_kctrl_valm(ctu->sv0, 4));
++		rsnd_mod_write(mod, CTU_SV05R, rsnd_kctrl_valm(ctu->sv0, 5));
++		rsnd_mod_write(mod, CTU_SV06R, rsnd_kctrl_valm(ctu->sv0, 6));
++		rsnd_mod_write(mod, CTU_SV07R, rsnd_kctrl_valm(ctu->sv0, 7));
+ 	}
+ 	if (scmdr > 1) {
+-		rsnd_mod_write(mod, CTU_SV10R, ctu->sv1.val[0]);
+-		rsnd_mod_write(mod, CTU_SV11R, ctu->sv1.val[1]);
+-		rsnd_mod_write(mod, CTU_SV12R, ctu->sv1.val[2]);
+-		rsnd_mod_write(mod, CTU_SV13R, ctu->sv1.val[3]);
+-		rsnd_mod_write(mod, CTU_SV14R, ctu->sv1.val[4]);
+-		rsnd_mod_write(mod, CTU_SV15R, ctu->sv1.val[5]);
+-		rsnd_mod_write(mod, CTU_SV16R, ctu->sv1.val[6]);
+-		rsnd_mod_write(mod, CTU_SV17R, ctu->sv1.val[7]);
++		rsnd_mod_write(mod, CTU_SV10R, rsnd_kctrl_valm(ctu->sv1, 0));
++		rsnd_mod_write(mod, CTU_SV11R, rsnd_kctrl_valm(ctu->sv1, 1));
++		rsnd_mod_write(mod, CTU_SV12R, rsnd_kctrl_valm(ctu->sv1, 2));
++		rsnd_mod_write(mod, CTU_SV13R, rsnd_kctrl_valm(ctu->sv1, 3));
++		rsnd_mod_write(mod, CTU_SV14R, rsnd_kctrl_valm(ctu->sv1, 4));
++		rsnd_mod_write(mod, CTU_SV15R, rsnd_kctrl_valm(ctu->sv1, 5));
++		rsnd_mod_write(mod, CTU_SV16R, rsnd_kctrl_valm(ctu->sv1, 6));
++		rsnd_mod_write(mod, CTU_SV17R, rsnd_kctrl_valm(ctu->sv1, 7));
+ 	}
+ 	if (scmdr > 2) {
+-		rsnd_mod_write(mod, CTU_SV20R, ctu->sv2.val[0]);
+-		rsnd_mod_write(mod, CTU_SV21R, ctu->sv2.val[1]);
+-		rsnd_mod_write(mod, CTU_SV22R, ctu->sv2.val[2]);
+-		rsnd_mod_write(mod, CTU_SV23R, ctu->sv2.val[3]);
+-		rsnd_mod_write(mod, CTU_SV24R, ctu->sv2.val[4]);
+-		rsnd_mod_write(mod, CTU_SV25R, ctu->sv2.val[5]);
+-		rsnd_mod_write(mod, CTU_SV26R, ctu->sv2.val[6]);
+-		rsnd_mod_write(mod, CTU_SV27R, ctu->sv2.val[7]);
++		rsnd_mod_write(mod, CTU_SV20R, rsnd_kctrl_valm(ctu->sv2, 0));
++		rsnd_mod_write(mod, CTU_SV21R, rsnd_kctrl_valm(ctu->sv2, 1));
++		rsnd_mod_write(mod, CTU_SV22R, rsnd_kctrl_valm(ctu->sv2, 2));
++		rsnd_mod_write(mod, CTU_SV23R, rsnd_kctrl_valm(ctu->sv2, 3));
++		rsnd_mod_write(mod, CTU_SV24R, rsnd_kctrl_valm(ctu->sv2, 4));
++		rsnd_mod_write(mod, CTU_SV25R, rsnd_kctrl_valm(ctu->sv2, 5));
++		rsnd_mod_write(mod, CTU_SV26R, rsnd_kctrl_valm(ctu->sv2, 6));
++		rsnd_mod_write(mod, CTU_SV27R, rsnd_kctrl_valm(ctu->sv2, 7));
+ 	}
+ 	if (scmdr > 3) {
+-		rsnd_mod_write(mod, CTU_SV30R, ctu->sv3.val[0]);
+-		rsnd_mod_write(mod, CTU_SV31R, ctu->sv3.val[1]);
+-		rsnd_mod_write(mod, CTU_SV32R, ctu->sv3.val[2]);
+-		rsnd_mod_write(mod, CTU_SV33R, ctu->sv3.val[3]);
+-		rsnd_mod_write(mod, CTU_SV34R, ctu->sv3.val[4]);
+-		rsnd_mod_write(mod, CTU_SV35R, ctu->sv3.val[5]);
+-		rsnd_mod_write(mod, CTU_SV36R, ctu->sv3.val[6]);
+-		rsnd_mod_write(mod, CTU_SV37R, ctu->sv3.val[7]);
++		rsnd_mod_write(mod, CTU_SV30R, rsnd_kctrl_valm(ctu->sv3, 0));
++		rsnd_mod_write(mod, CTU_SV31R, rsnd_kctrl_valm(ctu->sv3, 1));
++		rsnd_mod_write(mod, CTU_SV32R, rsnd_kctrl_valm(ctu->sv3, 2));
++		rsnd_mod_write(mod, CTU_SV33R, rsnd_kctrl_valm(ctu->sv3, 3));
++		rsnd_mod_write(mod, CTU_SV34R, rsnd_kctrl_valm(ctu->sv3, 4));
++		rsnd_mod_write(mod, CTU_SV35R, rsnd_kctrl_valm(ctu->sv3, 5));
++		rsnd_mod_write(mod, CTU_SV36R, rsnd_kctrl_valm(ctu->sv3, 6));
++		rsnd_mod_write(mod, CTU_SV37R, rsnd_kctrl_valm(ctu->sv3, 7));
+ 	}
+ 
+ 	rsnd_mod_write(mod, CTU_CTUIR, 0);
+@@ -199,17 +199,17 @@ static void rsnd_ctu_value_reset(struct rsnd_dai_stream *io,
+ 	struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
+ 	int i;
+ 
+-	if (!ctu->reset.val)
++	if (!rsnd_kctrl_vals(ctu->reset))
+ 		return;
+ 
+ 	for (i = 0; i < RSND_MAX_CHANNELS; i++) {
+-		ctu->pass.val[i] = 0;
+-		ctu->sv0.val[i] = 0;
+-		ctu->sv1.val[i] = 0;
+-		ctu->sv2.val[i] = 0;
+-		ctu->sv3.val[i] = 0;
++		rsnd_kctrl_valm(ctu->pass, i) = 0;
++		rsnd_kctrl_valm(ctu->sv0,  i) = 0;
++		rsnd_kctrl_valm(ctu->sv1,  i) = 0;
++		rsnd_kctrl_valm(ctu->sv2,  i) = 0;
++		rsnd_kctrl_valm(ctu->sv3,  i) = 0;
+ 	}
+-	ctu->reset.val = 0;
++	rsnd_kctrl_vals(ctu->reset) = 0;
+ }
+ 
+ static int rsnd_ctu_init(struct rsnd_mod *mod,
+diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c
+index 4ef318ac73d5..dbe54f024d68 100644
+--- a/sound/soc/sh/rcar/dvc.c
++++ b/sound/soc/sh/rcar/dvc.c
+@@ -73,8 +73,9 @@ static void rsnd_dvc_halt(struct rsnd_mod *mod)
+ 	rsnd_mod_write(mod, DVC_SWRSR, 0);
+ }
+ 
+-#define rsnd_dvc_get_vrpdr(dvc) (dvc->rup.val << 8 | dvc->rdown.val)
+-#define rsnd_dvc_get_vrdbr(dvc) (0x3ff - (dvc->volume.val[0] >> 13))
++#define rsnd_dvc_get_vrpdr(dvc) (rsnd_kctrl_vals(dvc->rup) << 8 | \
++				 rsnd_kctrl_vals(dvc->rdown))
++#define rsnd_dvc_get_vrdbr(dvc) (0x3ff - (rsnd_kctrl_valm(dvc->volume, 0) >> 13))
+ 
+ static void rsnd_dvc_volume_parameter(struct rsnd_dai_stream *io,
+ 					      struct rsnd_mod *mod)
+@@ -84,12 +85,12 @@ static void rsnd_dvc_volume_parameter(struct rsnd_dai_stream *io,
+ 	int i;
+ 
+ 	/* Enable Ramp */
+-	if (dvc->ren.val)
++	if (rsnd_kctrl_vals(dvc->ren))
+ 		for (i = 0; i < RSND_MAX_CHANNELS; i++)
+-			val[i] = dvc->volume.cfg.max;
++			val[i] = rsnd_kctrl_max(dvc->volume);
+ 	else
+ 		for (i = 0; i < RSND_MAX_CHANNELS; i++)
+-			val[i] = dvc->volume.val[i];
++			val[i] = rsnd_kctrl_valm(dvc->volume, i);
+ 
+ 	/* Enable Digital Volume */
+ 	rsnd_mod_write(mod, DVC_VOL0R, val[0]);
+@@ -119,7 +120,7 @@ static void rsnd_dvc_volume_init(struct rsnd_dai_stream *io,
+ 	dvucr |= 0x101;
+ 
+ 	/* Enable Ramp */
+-	if (dvc->ren.val) {
++	if (rsnd_kctrl_vals(dvc->ren)) {
+ 		dvucr |= 0x10;
+ 
+ 		/*
+@@ -161,10 +162,10 @@ static void rsnd_dvc_volume_update(struct rsnd_dai_stream *io,
+ 	u32 vrdbr = 0;
+ 	int i;
+ 
+-	for (i = 0; i < dvc->mute.cfg.size; i++)
+-		zcmcr |= (!!dvc->mute.cfg.val[i]) << i;
++	for (i = 0; i < rsnd_kctrl_size(dvc->mute); i++)
++		zcmcr |= (!!rsnd_kctrl_valm(dvc->mute, i)) << i;
+ 
+-	if (dvc->ren.val) {
++	if (rsnd_kctrl_vals(dvc->ren)) {
+ 		vrpdr = rsnd_dvc_get_vrpdr(dvc);
+ 		vrdbr = rsnd_dvc_get_vrdbr(dvc);
+ 	}
+diff --git a/sound/soc/sh/rcar/mix.c b/sound/soc/sh/rcar/mix.c
+index 912cfec49038..7998380766f6 100644
+--- a/sound/soc/sh/rcar/mix.c
++++ b/sound/soc/sh/rcar/mix.c
+@@ -84,7 +84,7 @@ static void rsnd_mix_halt(struct rsnd_mod *mod)
+ 
+ #define rsnd_mix_get_vol(mix, X) \
+ 	rsnd_flags_has(mix, HAS_VOL##X) ? \
+-		(VOL_MAX - mix->volume##X.cfg.val[0]) : 0
++		(VOL_MAX - rsnd_kctrl_vals(mix->volume##X)) : 0
+ static void rsnd_mix_volume_parameter(struct rsnd_dai_stream *io,
+ 				      struct rsnd_mod *mod)
+ {
+@@ -116,9 +116,9 @@ static void rsnd_mix_volume_init(struct rsnd_dai_stream *io,
+ 	rsnd_mod_write(mod, MIX_ADINR, rsnd_runtime_channel_after_ctu(io));
+ 
+ 	/* volume step */
+-	rsnd_mod_write(mod, MIX_MIXMR, mix->ren.cfg.val[0]);
+-	rsnd_mod_write(mod, MIX_MVPDR, mix->rup.cfg.val[0] << 8 |
+-				       mix->rdw.cfg.val[0]);
++	rsnd_mod_write(mod, MIX_MIXMR, rsnd_kctrl_vals(mix->ren));
++	rsnd_mod_write(mod, MIX_MVPDR, rsnd_kctrl_vals(mix->rup) << 8 |
++				       rsnd_kctrl_vals(mix->rdw));
+ 
+ 	/* common volume parameter */
+ 	rsnd_mix_volume_parameter(io, mod);
+@@ -217,7 +217,7 @@ static int rsnd_mix_pcm_new(struct rsnd_mod *mod,
+ 			       volume, VOL_MAX);
+ 	if (ret < 0)
+ 		return ret;
+-	volume->cfg.val[0] = VOL_MAX;
++	rsnd_kctrl_vals(*volume) = VOL_MAX;
+ 
+ 	if (rsnd_flags_has(mix, ONCE_KCTRL_INITIALIZED))
+ 		return ret;
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 0d9f9c3343da..2a224fa639cb 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -631,6 +631,10 @@ struct rsnd_kctrl_cfg_s {
+ 	struct rsnd_kctrl_cfg cfg;
+ 	u32 val;
+ };
++#define rsnd_kctrl_size(x)	((x).cfg.size)
++#define rsnd_kctrl_max(x)	((x).cfg.max)
++#define rsnd_kctrl_valm(x, i)	((x).val[i])	/* = (x).cfg.val[i] */
++#define rsnd_kctrl_vals(x)	((x).val)	/* = (x).cfg.val[0] */
+ 
+ int rsnd_kctrl_accept_anytime(struct rsnd_dai_stream *io);
+ int rsnd_kctrl_accept_runtime(struct rsnd_dai_stream *io);
+-- 
+2.19.0
+
diff --git a/patches/0144-ASoC-rsnd-more-clear-ADG-clock-debug-info.patch b/patches/0144-ASoC-rsnd-more-clear-ADG-clock-debug-info.patch
new file mode 100644
index 00000000000000..b0266364099294
--- /dev/null
+++ b/patches/0144-ASoC-rsnd-more-clear-ADG-clock-debug-info.patch
@@ -0,0 +1,158 @@
+From b64621c44042653a0a8ae8eb70e23cc2d17e7f6f Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 13 Oct 2017 06:03:06 +0000
+Subject: [PATCH 0144/1795] ASoC: rsnd: more clear ADG clock debug info
+
+ADG inputs clock from CLK{A,B,C,I} and outputs clock from
+CLKOUT{0,1,2,3} which is selected by BRG{A,B}.
+Now, ADG is assuming BRGA is for 44100Hz related clocks,
+BRGB is for 48000Hz related clocks.
+
+Clock related debug is very difficult/confusable.
+This patch cleanups clock related debug info.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 6cba3fa98cdd045e020f096bb8888225d3906895)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/adg.c | 59 ++++++++++++++++++++++++++++-------------
+ 1 file changed, 41 insertions(+), 18 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c
+index f21179f29b6c..4672688cac32 100644
+--- a/sound/soc/sh/rcar/adg.c
++++ b/sound/soc/sh/rcar/adg.c
+@@ -57,6 +57,13 @@ struct rsnd_adg {
+ 	     i++)
+ #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
+ 
++static const char * const clk_name[] = {
++	[CLKA]	= "clk_a",
++	[CLKB]	= "clk_b",
++	[CLKC]	= "clk_c",
++	[CLKI]	= "clk_i",
++};
++
+ static u32 rsnd_adg_calculate_rbgx(unsigned long div)
+ {
+ 	int i, ratio;
+@@ -279,6 +286,7 @@ static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
+ 	struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
+ 	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ 	struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
++	struct device *dev = rsnd_priv_to_dev(priv);
+ 	int id = rsnd_mod_id(ssi_mod);
+ 	int shift = (id % 4) * 8;
+ 	u32 mask = 0xFF << shift;
+@@ -305,12 +313,13 @@ static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
+ 		rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
+ 		break;
+ 	}
++
++	dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
+ }
+ 
+ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
+ {
+ 	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+-	struct device *dev = rsnd_priv_to_dev(priv);
+ 	struct clk *clk;
+ 	int i;
+ 	int sel_table[] = {
+@@ -320,8 +329,6 @@ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
+ 		[CLKI] = 0x0,
+ 	};
+ 
+-	dev_dbg(dev, "request clock = %d\n", rate);
+-
+ 	/*
+ 	 * find suitable clock from
+ 	 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
+@@ -377,9 +384,10 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
+ 	rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
+ 	rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
+ 
+-	dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
+-		rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
+-		data, rate);
++	dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
++		(ckr) ? 'B' : 'A',
++		(ckr) ?	adg->rbgb_rate_for_48khz :
++			adg->rbga_rate_for_441khz);
+ 
+ 	return 0;
+ }
+@@ -408,21 +416,12 @@ static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
+ {
+ 	struct device *dev = rsnd_priv_to_dev(priv);
+ 	struct clk *clk;
+-	static const char * const clk_name[] = {
+-		[CLKA]	= "clk_a",
+-		[CLKB]	= "clk_b",
+-		[CLKC]	= "clk_c",
+-		[CLKI]	= "clk_i",
+-	};
+ 	int i;
+ 
+ 	for (i = 0; i < CLKMAX; i++) {
+ 		clk = devm_clk_get(dev, clk_name[i]);
+ 		adg->clk[i] = IS_ERR(clk) ? NULL : clk;
+ 	}
+-
+-	for_each_rsnd_clk(clk, adg, i)
+-		dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
+ }
+ 
+ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
+@@ -571,12 +570,35 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
+ 	adg->ckr = ckr;
+ 	adg->rbga = rbga;
+ 	adg->rbgb = rbgb;
++}
++
++#ifdef DEBUG
++static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
++{
++	struct device *dev = rsnd_priv_to_dev(priv);
++	struct clk *clk;
++	int i;
++
++	for_each_rsnd_clk(clk, adg, i)
++		dev_dbg(dev, "%s    : %p : %ld\n",
++			clk_name[i], clk, clk_get_rate(clk));
+ 
+-	for_each_rsnd_clkout(clk, adg, i)
+-		dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
+ 	dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
+-		ckr, rbga, rbgb);
++		adg->ckr, adg->rbga, adg->rbgb);
++	dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
++	dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
++
++	/*
++	 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
++	 * by BRGCKR::BRGCKR_31
++	 */
++	for_each_rsnd_clkout(clk, adg, i)
++		dev_dbg(dev, "clkout %d : %p : %ld\n", i,
++			clk, clk_get_rate(clk));
+ }
++#else
++#define rsnd_adg_clk_dbg_info(priv, adg)
++#endif
+ 
+ int rsnd_adg_probe(struct rsnd_priv *priv)
+ {
+@@ -595,6 +617,7 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
+ 
+ 	rsnd_adg_get_clkin(priv, adg);
+ 	rsnd_adg_get_clkout(priv, adg);
++	rsnd_adg_clk_dbg_info(priv, adg);
+ 
+ 	priv->adg = adg;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0145-ASoC-rsnd-don-t-use-io-mod-directly.patch b/patches/0145-ASoC-rsnd-don-t-use-io-mod-directly.patch
new file mode 100644
index 00000000000000..41a2bd13ab11b5
--- /dev/null
+++ b/patches/0145-ASoC-rsnd-don-t-use-io-mod-directly.patch
@@ -0,0 +1,32 @@
+From caa430bc903329012f547ea1e8bdc9fdad7704e8 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 31 Oct 2017 00:38:09 +0000
+Subject: [PATCH 0145/1795] ASoC: rsnd: don't use io->mod[] directly
+
+We have rsnd_io_to_mod() macro. Let's use it
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 138f878647f2ac0d7700f669b860cb130306e062)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index e9b0b0f5f0ee..b338c0009506 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -407,7 +407,7 @@ struct rsnd_mod *rsnd_mod_next(int *iterator,
+ 
+ 	for (; *iterator < max; (*iterator)++) {
+ 		type = (array) ? array[*iterator] : *iterator;
+-		mod = io->mod[type];
++		mod = rsnd_io_to_mod(io, type);
+ 		if (!mod)
+ 			continue;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0146-ASoC-rsnd-tidyup-rsnd_mod_next-for-loop-method.patch b/patches/0146-ASoC-rsnd-tidyup-rsnd_mod_next-for-loop-method.patch
new file mode 100644
index 00000000000000..9da674e731e44c
--- /dev/null
+++ b/patches/0146-ASoC-rsnd-tidyup-rsnd_mod_next-for-loop-method.patch
@@ -0,0 +1,36 @@
+From cf9350bbf1368ac62ab014e6af91261dee3f2178 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 31 Oct 2017 00:38:36 +0000
+Subject: [PATCH 0146/1795] ASoC: rsnd: tidyup rsnd_mod_next() for loop method
+
+Let's remove point less "continue"
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b12f1e3a798e19727ca632d92abe619b418ad0d0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index b338c0009506..8fc3bf2b20f5 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -408,10 +408,8 @@ struct rsnd_mod *rsnd_mod_next(int *iterator,
+ 	for (; *iterator < max; (*iterator)++) {
+ 		type = (array) ? array[*iterator] : *iterator;
+ 		mod = rsnd_io_to_mod(io, type);
+-		if (!mod)
+-			continue;
+-
+-		return mod;
++		if (mod)
++			return mod;
+ 	}
+ 
+ 	return NULL;
+-- 
+2.19.0
+
diff --git a/patches/0147-ASoC-rsnd-NULL-check-is-not-needed-for-clk_unprepare.patch b/patches/0147-ASoC-rsnd-NULL-check-is-not-needed-for-clk_unprepare.patch
new file mode 100644
index 00000000000000..63b4895617ea23
--- /dev/null
+++ b/patches/0147-ASoC-rsnd-NULL-check-is-not-needed-for-clk_unprepare.patch
@@ -0,0 +1,35 @@
+From 166660873df9bf634c8552d8e0ed8cf7dbcb4033 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 31 Oct 2017 00:39:17 +0000
+Subject: [PATCH 0147/1795] ASoC: rsnd: NULL check is not needed for
+ clk_unprepare()
+
+clk_unprepare() is checking parameter by IS_ERR_OR_NULL().
+clk NULL check is not needed on rsnd_mod_quit()
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit ed3ac14ca90074d51f365dba5ed535e76ea155ea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 8fc3bf2b20f5..0216d3f53097 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -172,8 +172,7 @@ int rsnd_mod_init(struct rsnd_priv *priv,
+ 
+ void rsnd_mod_quit(struct rsnd_mod *mod)
+ {
+-	if (mod->clk)
+-		clk_unprepare(mod->clk);
++	clk_unprepare(mod->clk);
+ 	mod->clk = NULL;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0148-ASoC-rsnd-use-snd_pcm_running-in-rsnd_io_is_working.patch b/patches/0148-ASoC-rsnd-use-snd_pcm_running-in-rsnd_io_is_working.patch
new file mode 100644
index 00000000000000..caa0c49be303b2
--- /dev/null
+++ b/patches/0148-ASoC-rsnd-use-snd_pcm_running-in-rsnd_io_is_working.patch
@@ -0,0 +1,36 @@
+From 156acab36df13f9ebf962e4309284bd0dd124f58 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 31 Oct 2017 00:39:45 +0000
+Subject: [PATCH 0148/1795] ASoC: rsnd: use snd_pcm_running() in
+ rsnd_io_is_working()
+
+Let's use more common style to checking running/working
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 8fce974bc4d5478d4ddee2443a3e268532ab35a8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 0216d3f53097..b36832ef7342 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -199,7 +199,10 @@ void rsnd_mod_interrupt(struct rsnd_mod *mod,
+ int rsnd_io_is_working(struct rsnd_dai_stream *io)
+ {
+ 	/* see rsnd_dai_stream_init/quit() */
+-	return !!io->substream;
++	if (io->substream)
++		return snd_pcm_running(io->substream);
++
++	return 0;
+ }
+ 
+ int rsnd_runtime_channel_original(struct rsnd_dai_stream *io)
+-- 
+2.19.0
+
diff --git a/patches/0149-ASoC-rsnd-Don-t-check-SSISR-DIRQ-when-Capture.patch b/patches/0149-ASoC-rsnd-Don-t-check-SSISR-DIRQ-when-Capture.patch
new file mode 100644
index 00000000000000..feb81f6c9b26eb
--- /dev/null
+++ b/patches/0149-ASoC-rsnd-Don-t-check-SSISR-DIRQ-when-Capture.patch
@@ -0,0 +1,51 @@
+From 9c4947b2704667ba94e4ec58b91cf3a1e1403ee0 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 31 Oct 2017 00:40:32 +0000
+Subject: [PATCH 0149/1795] ASoC: rsnd: Don't check SSISR::DIRQ when Capture
+
+When stop case, it was Playback, it need to check all data were
+completely sent. But in Capture case, it might not receive data
+anymore. SSISR::DIRQ check is not need for Capture case.
+
+Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit ce548931207c0d0059bd90171e2c458f897354d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index d64abbbe1a98..cbf3bf312d23 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -607,15 +607,18 @@ static int rsnd_ssi_stop(struct rsnd_mod *mod,
+ 	if (rsnd_ssi_is_parent(mod, io))
+ 		return 0;
+ 
+-	/*
+-	 * disable all IRQ,
+-	 * and, wait all data was sent
+-	 */
+ 	cr  =	ssi->cr_own	|
+ 		ssi->cr_clk;
+ 
+-	rsnd_mod_write(mod, SSICR, cr | EN);
+-	rsnd_ssi_status_check(mod, DIRQ);
++	/*
++	 * disable all IRQ,
++	 * Playback: Wait all data was sent
++	 * Capture:  It might not receave data. Do nothing
++	 */
++	if (rsnd_io_is_play(io)) {
++		rsnd_mod_write(mod, SSICR, cr | EN);
++		rsnd_ssi_status_check(mod, DIRQ);
++	}
+ 
+ 	/*
+ 	 * disable SSI,
+-- 
+2.19.0
+
diff --git a/patches/0150-ASoC-rsnd-remove-NULL-check-from-rsnd_mod_name-rsnd_.patch b/patches/0150-ASoC-rsnd-remove-NULL-check-from-rsnd_mod_name-rsnd_.patch
new file mode 100644
index 00000000000000..b6e3639df31f9a
--- /dev/null
+++ b/patches/0150-ASoC-rsnd-remove-NULL-check-from-rsnd_mod_name-rsnd_.patch
@@ -0,0 +1,164 @@
+From 34c0647ebbc0ba28e42ca16c134b9c8c6b56da05 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 1 Nov 2017 07:17:34 +0000
+Subject: [PATCH 0150/1795] ASoC: rsnd: remove NULL check from
+ rsnd_mod_name()/rsnd_mod_id()
+
+Current rsnd driver has rsnd_mod_id() which returns mod ID,
+and it returns -1 if mod was NULL.
+In the same time, this driver has rsnd_mod_name() which returns mod
+name, and it returns "unknown" if mod or mod->ops was NULL.
+
+Basically these "mod" never be NULL, but the reason why rsnd driver
+has such behavior is that DMA path finder is assuming memory as
+"mod == NULL".
+Thus, current DMA path debug code prints like below.
+Here "unknown[-1]" means it was memory.
+
+	...
+	rcar_sound ec500000.sound:   unknown[-1] from
+	rcar_sound ec500000.sound:   src[0] to
+	rcar_sound ec500000.sound:   ctu[2]
+	rcar_sound ec500000.sound:   mix[0]
+	rcar_sound ec500000.sound:   dvc[0]
+	rcar_sound ec500000.sound:   ssi[0]
+	rcar_sound ec500000.sound: audmac[0] unknown[-1] -> src[0]
+	...
+
+1st issue is that it is confusable for user.
+2nd issue is rsnd driver has something like below code.
+
+	mask |= 1 << rsnd_mod_id(mod);
+
+Because of this kind of code, some statically code checker will
+reports "Shifting by a negative value is undefined behaviour".
+
+But this "mod" never be NULL, thus negative shift never happen.
+To avoid these issues, this patch adds new dummy "mem" to
+indicate memory, and use it to indicate debug information,
+and, remove unneeded "NULL mod" behavior from rsnd_mod_id() and
+rsnd_mod_name().
+
+The debug information will be like below by this patch
+	...
+	rcar_sound ec500000.sound:   mem[0] from
+	rcar_sound ec500000.sound:   src[0] to
+	rcar_sound ec500000.sound:   ctu[2]
+	rcar_sound ec500000.sound:   mix[0]
+	rcar_sound ec500000.sound:   dvc[0]
+	rcar_sound ec500000.sound:   ssi[0]
+	rcar_sound ec500000.sound: audmac[0] mem[0] -> src[0]
+	...
+
+Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 9b6ea25066b05c4b8bc4ea69037741bd67649cd1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c |  8 --------
+ sound/soc/sh/rcar/dma.c  | 24 ++++++++++++++++++------
+ sound/soc/sh/rcar/rsnd.h |  6 +++---
+ 3 files changed, 21 insertions(+), 17 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index b36832ef7342..c70eb2097816 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -121,14 +121,6 @@ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type)
+ 	}
+ }
+ 
+-char *rsnd_mod_name(struct rsnd_mod *mod)
+-{
+-	if (!mod || !mod->ops)
+-		return "unknown";
+-
+-	return mod->ops->name;
+-}
+-
+ struct dma_chan *rsnd_mod_dma_req(struct rsnd_dai_stream *io,
+ 				  struct rsnd_mod *mod)
+ {
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 17220c946ff0..5bc9ec16813c 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -60,6 +60,14 @@ struct rsnd_dma_ctrl {
+ #define rsnd_dma_to_dmaen(dma)	(&(dma)->dma.en)
+ #define rsnd_dma_to_dmapp(dma)	(&(dma)->dma.pp)
+ 
++/* for DEBUG */
++static struct rsnd_mod_ops mem_ops = {
++	.name = "mem",
++};
++
++static struct rsnd_mod mem = {
++};
++
+ /*
+  *		Audio DMAC
+  */
+@@ -747,9 +755,10 @@ static void rsnd_dma_of_path(struct rsnd_mod *this,
+ 		rsnd_mod_name(this), rsnd_mod_id(this));
+ 	for (i = 0; i <= idx; i++) {
+ 		dev_dbg(dev, "  %s[%d]%s\n",
+-		       rsnd_mod_name(mod[i]), rsnd_mod_id(mod[i]),
+-		       (mod[i] == *mod_from) ? " from" :
+-		       (mod[i] == *mod_to)   ? " to" : "");
++			rsnd_mod_name(mod[i] ? mod[i] : &mem),
++			rsnd_mod_id  (mod[i] ? mod[i] : &mem),
++			(mod[i] == *mod_from) ? " from" :
++			(mod[i] == *mod_to)   ? " to" : "");
+ 	}
+ }
+ 
+@@ -814,8 +823,10 @@ static int rsnd_dma_alloc(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
+ 
+ 	dev_dbg(dev, "%s[%d] %s[%d] -> %s[%d]\n",
+ 		rsnd_mod_name(*dma_mod), rsnd_mod_id(*dma_mod),
+-		rsnd_mod_name(mod_from), rsnd_mod_id(mod_from),
+-		rsnd_mod_name(mod_to),   rsnd_mod_id(mod_to));
++		rsnd_mod_name(mod_from ? mod_from : &mem),
++		rsnd_mod_id  (mod_from ? mod_from : &mem),
++		rsnd_mod_name(mod_to   ? mod_to   : &mem),
++		rsnd_mod_id  (mod_to   ? mod_to   : &mem));
+ 
+ 	ret = attach(io, dma, mod_from, mod_to);
+ 	if (ret < 0)
+@@ -872,5 +883,6 @@ int rsnd_dma_probe(struct rsnd_priv *priv)
+ 
+ 	priv->dma = dmac;
+ 
+-	return 0;
++	/* dummy mem mod for debug */
++	return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, NULL, 0, 0);
+ }
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 2a224fa639cb..57cd2bc773c2 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -355,8 +355,9 @@ struct rsnd_mod {
+ #define __rsnd_mod_call_nolock_start	0
+ #define __rsnd_mod_call_nolock_stop	1
+ 
+-#define rsnd_mod_to_priv(mod) ((mod)->priv)
+-#define rsnd_mod_id(mod) ((mod) ? (mod)->id : -1)
++#define rsnd_mod_to_priv(mod)	((mod)->priv)
++#define rsnd_mod_name(mod)	((mod)->ops->name)
++#define rsnd_mod_id(mod)	((mod)->id)
+ #define rsnd_mod_power_on(mod)	clk_enable((mod)->clk)
+ #define rsnd_mod_power_off(mod)	clk_disable((mod)->clk)
+ #define rsnd_mod_get(ip)	(&(ip)->mod)
+@@ -371,7 +372,6 @@ int rsnd_mod_init(struct rsnd_priv *priv,
+ 		  enum rsnd_mod_type type,
+ 		  int id);
+ void rsnd_mod_quit(struct rsnd_mod *mod);
+-char *rsnd_mod_name(struct rsnd_mod *mod);
+ struct dma_chan *rsnd_mod_dma_req(struct rsnd_dai_stream *io,
+ 				  struct rsnd_mod *mod);
+ void rsnd_mod_interrupt(struct rsnd_mod *mod,
+-- 
+2.19.0
+
diff --git a/patches/0151-ASoC-rsnd-return-EIO-if-rsnd_dmaen_request_channel-f.patch b/patches/0151-ASoC-rsnd-return-EIO-if-rsnd_dmaen_request_channel-f.patch
new file mode 100644
index 00000000000000..c22ac3c0b8e698
--- /dev/null
+++ b/patches/0151-ASoC-rsnd-return-EIO-if-rsnd_dmaen_request_channel-f.patch
@@ -0,0 +1,45 @@
+From fc8221dca3960255017b26a05a2501aced0c7073 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 6 Nov 2017 01:07:27 +0000
+Subject: [PATCH 0151/1795] ASoC: rsnd: return -EIO if
+ rsnd_dmaen_request_channel() failed
+
+PTR_ERR(NULL) is success. Normally when a function returns both NULL
+and error pointers, it means that NULL is not a error.
+But, rsnd_dmaen_request_channel() returns NULL if requested resource
+was failed.
+Let's return -EIO if rsnd_dmaen_request_channel() was failed on
+rsnd_dmaen_nolock_start().
+This patch fixes commit edce5c496c6a ("ASoC: rsnd: Request/Release DMA
+channel eachtime")
+
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit c409c2a963475f0288ba3bb47a10f04f6441ffb9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/dma.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 5bc9ec16813c..fd557abfe390 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -219,11 +219,9 @@ static int rsnd_dmaen_nolock_start(struct rsnd_mod *mod,
+ 						 dma->mod_from,
+ 						 dma->mod_to);
+ 	if (IS_ERR_OR_NULL(dmaen->chan)) {
+-		int ret = PTR_ERR(dmaen->chan);
+-
+ 		dmaen->chan = NULL;
+ 		dev_err(dev, "can't get dma channel\n");
+-		return ret;
++		return -EIO;
+ 	}
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0152-ASoC-rcar-revert-IOMMU-support-so-far.patch b/patches/0152-ASoC-rcar-revert-IOMMU-support-so-far.patch
new file mode 100644
index 00000000000000..27664895225f2a
--- /dev/null
+++ b/patches/0152-ASoC-rcar-revert-IOMMU-support-so-far.patch
@@ -0,0 +1,197 @@
+From 3ce920f730d19c733eeba1f805afe597d6c3a8d6 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Thu, 16 Nov 2017 04:36:51 +0000
+Subject: [PATCH 0152/1795] ASoC: rcar: revert IOMMU support so far
+
+commit 4821d914fe74 ("ASoC: rsnd: use dma_sync_single_for_xxx() for
+IOMMU") had supported IOMMU, but it breaks normal sound "recorde"
+and both PulseAudio's "playback/recorde". The sound will be noisy.
+
+That commit was using dma_sync_single_for_xxx(), and driver should
+make sure memory is protected during CPU or Device are using it.
+But if driver returns current "residue" data size correctly on pointer
+function, player/recorder will access to protected memory.
+
+IOMMU feature should be supported, but I don't know how to handle it
+without memory cache problem at this point.
+Thus, this patch simply revert it to avoid current noisy sound.
+
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit c20c6704bf2dafaba0d90c8310ef9e919fe4d2e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c |  4 +-
+ sound/soc/sh/rcar/dma.c  | 86 +++-------------------------------------
+ 2 files changed, 8 insertions(+), 82 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index c70eb2097816..f12a88a21dfa 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1332,8 +1332,8 @@ static int rsnd_pcm_new(struct snd_soc_pcm_runtime *rtd)
+ 
+ 	return snd_pcm_lib_preallocate_pages_for_all(
+ 		rtd->pcm,
+-		SNDRV_DMA_TYPE_CONTINUOUS,
+-		snd_dma_continuous_data(GFP_KERNEL),
++		SNDRV_DMA_TYPE_DEV,
++		rtd->card->snd_card->dev,
+ 		PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
+ }
+ 
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index fd557abfe390..4d750bdf8e24 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -26,10 +26,7 @@
+ struct rsnd_dmaen {
+ 	struct dma_chan		*chan;
+ 	dma_cookie_t		cookie;
+-	dma_addr_t		dma_buf;
+ 	unsigned int		dma_len;
+-	unsigned int		dma_period;
+-	unsigned int		dma_cnt;
+ };
+ 
+ struct rsnd_dmapp {
+@@ -71,38 +68,10 @@ static struct rsnd_mod mem = {
+ /*
+  *		Audio DMAC
+  */
+-#define rsnd_dmaen_sync(dmaen, io, i)	__rsnd_dmaen_sync(dmaen, io, i, 1)
+-#define rsnd_dmaen_unsync(dmaen, io, i)	__rsnd_dmaen_sync(dmaen, io, i, 0)
+-static void __rsnd_dmaen_sync(struct rsnd_dmaen *dmaen, struct rsnd_dai_stream *io,
+-			      int i, int sync)
+-{
+-	struct device *dev = dmaen->chan->device->dev;
+-	enum dma_data_direction dir;
+-	int is_play = rsnd_io_is_play(io);
+-	dma_addr_t buf;
+-	int len, max;
+-	size_t period;
+-
+-	len	= dmaen->dma_len;
+-	period	= dmaen->dma_period;
+-	max	= len / period;
+-	i	= i % max;
+-	buf	= dmaen->dma_buf + (period * i);
+-
+-	dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+-
+-	if (sync)
+-		dma_sync_single_for_device(dev, buf, period, dir);
+-	else
+-		dma_sync_single_for_cpu(dev, buf, period, dir);
+-}
+-
+ static void __rsnd_dmaen_complete(struct rsnd_mod *mod,
+ 				  struct rsnd_dai_stream *io)
+ {
+ 	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
+-	struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
+-	struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
+ 	bool elapsed = false;
+ 	unsigned long flags;
+ 
+@@ -115,22 +84,9 @@ static void __rsnd_dmaen_complete(struct rsnd_mod *mod,
+ 	 */
+ 	spin_lock_irqsave(&priv->lock, flags);
+ 
+-	if (rsnd_io_is_working(io)) {
+-		rsnd_dmaen_unsync(dmaen, io, dmaen->dma_cnt);
+-
+-		/*
+-		 * Next period is already started.
+-		 * Let's sync Next Next period
+-		 * see
+-		 *	rsnd_dmaen_start()
+-		 */
+-		rsnd_dmaen_sync(dmaen, io, dmaen->dma_cnt + 2);
+-
++	if (rsnd_io_is_working(io))
+ 		elapsed = true;
+ 
+-		dmaen->dma_cnt++;
+-	}
+-
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	if (elapsed)
+@@ -165,14 +121,8 @@ static int rsnd_dmaen_stop(struct rsnd_mod *mod,
+ 	struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
+ 	struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
+ 
+-	if (dmaen->chan) {
+-		int is_play = rsnd_io_is_play(io);
+-
++	if (dmaen->chan)
+ 		dmaengine_terminate_all(dmaen->chan);
+-		dma_unmap_single(dmaen->chan->device->dev,
+-				 dmaen->dma_buf, dmaen->dma_len,
+-				 is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+-	}
+ 
+ 	return 0;
+ }
+@@ -237,11 +187,7 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod,
+ 	struct device *dev = rsnd_priv_to_dev(priv);
+ 	struct dma_async_tx_descriptor *desc;
+ 	struct dma_slave_config cfg = {};
+-	dma_addr_t buf;
+-	size_t len;
+-	size_t period;
+ 	int is_play = rsnd_io_is_play(io);
+-	int i;
+ 	int ret;
+ 
+ 	cfg.direction	= is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
+@@ -258,19 +204,10 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	len	= snd_pcm_lib_buffer_bytes(substream);
+-	period	= snd_pcm_lib_period_bytes(substream);
+-	buf	= dma_map_single(dmaen->chan->device->dev,
+-				 substream->runtime->dma_area,
+-				 len,
+-				 is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+-	if (dma_mapping_error(dmaen->chan->device->dev, buf)) {
+-		dev_err(dev, "dma map failed\n");
+-		return -EIO;
+-	}
+-
+ 	desc = dmaengine_prep_dma_cyclic(dmaen->chan,
+-					 buf, len, period,
++					 substream->runtime->dma_addr,
++					 snd_pcm_lib_buffer_bytes(substream),
++					 snd_pcm_lib_period_bytes(substream),
+ 					 is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
+ 					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 
+@@ -282,18 +219,7 @@ static int rsnd_dmaen_start(struct rsnd_mod *mod,
+ 	desc->callback		= rsnd_dmaen_complete;
+ 	desc->callback_param	= rsnd_mod_get(dma);
+ 
+-	dmaen->dma_buf		= buf;
+-	dmaen->dma_len		= len;
+-	dmaen->dma_period	= period;
+-	dmaen->dma_cnt		= 0;
+-
+-	/*
+-	 * synchronize this and next period
+-	 * see
+-	 *	__rsnd_dmaen_complete()
+-	 */
+-	for (i = 0; i < 2; i++)
+-		rsnd_dmaen_sync(dmaen, io, i);
++	dmaen->dma_len		= snd_pcm_lib_buffer_bytes(substream);
+ 
+ 	dmaen->cookie = dmaengine_submit(desc);
+ 	if (dmaen->cookie < 0) {
+-- 
+2.19.0
+
diff --git a/patches/0153-ASoC-rsnd-ssiu-clear-SSI_MODE-for-non-TDM-Extended-m.patch b/patches/0153-ASoC-rsnd-ssiu-clear-SSI_MODE-for-non-TDM-Extended-m.patch
new file mode 100644
index 00000000000000..64e997edae72c9
--- /dev/null
+++ b/patches/0153-ASoC-rsnd-ssiu-clear-SSI_MODE-for-non-TDM-Extended-m.patch
@@ -0,0 +1,52 @@
+From f9bc536ea61a4f343d3bd0fe40879dc282ec90e0 Mon Sep 17 00:00:00 2001
+From: Jiada Wang <jiada_wang@mentor.com>
+Date: Tue, 28 Nov 2017 16:05:13 +0900
+Subject: [PATCH 0153/1795] ASoC: rsnd: ssiu: clear SSI_MODE for non TDM
+ Extended modes
+
+register SSI_MODE is set when SSI works in TDM Extended,
+but it isn't reset when SSI starts to work in other modes,
+thus causes issues.
+
+This patch clearss SSI_MODE register when SSI works in modes
+other than TDM Extended.
+
+Fixes: 186fadc132f0 ("ASoC: rsnd: add TDM Extend Mode support")
+Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit a91d7fb97092d6b840af5899ded3b389603fd7f1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssiu.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/ssiu.c b/sound/soc/sh/rcar/ssiu.c
+index 4d948757d300..6ff8a36c2c82 100644
+--- a/sound/soc/sh/rcar/ssiu.c
++++ b/sound/soc/sh/rcar/ssiu.c
+@@ -125,6 +125,7 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod,
+ {
+ 	int hdmi = rsnd_ssi_hdmi_port(io);
+ 	int ret;
++	u32 mode = 0;
+ 
+ 	ret = rsnd_ssiu_init(mod, io, priv);
+ 	if (ret < 0)
+@@ -136,9 +137,11 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod,
+ 		 * see
+ 		 *	rsnd_ssi_config_init()
+ 		 */
+-		rsnd_mod_write(mod, SSI_MODE, 0x1);
++		mode = 0x1;
+ 	}
+ 
++	rsnd_mod_write(mod, SSI_MODE, mode);
++
+ 	if (rsnd_ssi_use_busif(io)) {
+ 		rsnd_mod_write(mod, SSI_BUSIF_ADINR,
+ 			       rsnd_get_adinr_bit(mod, io) |
+-- 
+2.19.0
+
diff --git a/patches/0154-dt-bindings-mmc-renesas_sdhi-provide-example-in-bind.patch b/patches/0154-dt-bindings-mmc-renesas_sdhi-provide-example-in-bind.patch
new file mode 100644
index 00000000000000..e0dbb270dc2d55
--- /dev/null
+++ b/patches/0154-dt-bindings-mmc-renesas_sdhi-provide-example-in-bind.patch
@@ -0,0 +1,89 @@
+From fd0bc6d92f4f6c07ae18e3ea30a50f8914ed2719 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:00:21 +0200
+Subject: [PATCH 0154/1795] dt-bindings: mmc: renesas_sdhi: provide example in
+ bindings documentation
+
+Provide an example of the usage of the DT bindings for TMIO
+in their documentation. The example given is for the r8a7790 (R-Car H2).
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 95e91ade6900547a74ac8e3ce35213aacfbdd0d3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/mmc/tmio_mmc.txt      | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index 54ef642f23a0..b63392d9cc47 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -43,3 +43,61 @@ Optional properties:
+ - pinctrl-names: should be "default", "state_uhs"
+ - pinctrl-0: should contain default/high speed pin ctrl
+ - pinctrl-1: should contain uhs mode pin ctrl
++
++Example: R8A7790 (R-Car H2) SDHI controller nodes
++
++	sdhi0: sd@ee100000 {
++		compatible = "renesas,sdhi-r8a7790";
++		reg = <0 0xee100000 0 0x328>;
++		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 314>;
++		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++		       <&dmac1 0xcd>, <&dmac1 0xce>;
++		dma-names = "tx", "rx", "tx", "rx";
++		max-frequency = <195000000>;
++		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 314>;
++		status = "disabled";
++	};
++
++	sdhi1: sd@ee120000 {
++		compatible = "renesas,sdhi-r8a7790";
++		reg = <0 0xee120000 0 0x328>;
++		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 313>;
++		dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
++		       <&dmac1 0xc9>, <&dmac1 0xca>;
++		dma-names = "tx", "rx", "tx", "rx";
++		max-frequency = <195000000>;
++		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 313>;
++		status = "disabled";
++	};
++
++	sdhi2: sd@ee140000 {
++		compatible = "renesas,sdhi-r8a7790";
++		reg = <0 0xee140000 0 0x100>;
++		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 312>;
++		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++		       <&dmac1 0xc1>, <&dmac1 0xc2>;
++		dma-names = "tx", "rx", "tx", "rx";
++		max-frequency = <97500000>;
++		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 312>;
++		status = "disabled";
++	};
++
++	sdhi3: sd@ee160000 {
++		compatible = "renesas,sdhi-r8a7790";
++		reg = <0 0xee160000 0 0x100>;
++		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 311>;
++		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++		       <&dmac1 0xd3>, <&dmac1 0xd4>;
++		dma-names = "tx", "rx", "tx", "rx";
++		max-frequency = <97500000>;
++		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 311>;
++		status = "disabled";
++	};
+-- 
+2.19.0
+
diff --git a/patches/0155-dt-bindings-mmc-renesas_sdhi-add-R-Car-Gen-123-fallb.patch b/patches/0155-dt-bindings-mmc-renesas_sdhi-add-R-Car-Gen-123-fallb.patch
new file mode 100644
index 00000000000000..38a16a704bd254
--- /dev/null
+++ b/patches/0155-dt-bindings-mmc-renesas_sdhi-add-R-Car-Gen-123-fallb.patch
@@ -0,0 +1,102 @@
+From f11faa2b406316de504a4c940196913f7ec3d320 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:00:22 +0200
+Subject: [PATCH 0155/1795] dt-bindings: mmc: renesas_sdhi: add R-Car Gen[123]
+ fallback compatibility strings
+
+Add fallback compatibility strings for R-Car Gen 1, 2 and 3.
+
+In the case of Renesas R-Car hardware we know that there are generations of
+SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
+between IP blocks might be. For example, I believe that r8a7790 is older
+than r8a7791 but that doesn't imply that the latter is a descendant of the
+former or vice versa.
+
+We can, however, by examining the documentation and behaviour of the
+hardware at run-time observe that the current driver implementation appears
+to be compatible with the IP blocks on SoCs within a given generation.
+
+For the above reasons and convenience when enabling new SoCs a
+per-generation fallback compatibility string scheme is being adopted for
+drivers for Renesas SoCs.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 54839d012d5f98cde2fa102fdcd22e1da661d138)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/mmc/tmio_mmc.txt      | 20 ++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index b63392d9cc47..3c6762430fd9 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -10,7 +10,7 @@ described in mmc.txt, can be used. Additionally the following tmio_mmc-specific
+ optional bindings can be used.
+ 
+ Required properties:
+-- compatible:	"renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
++- compatible: should contain one or more of the following:
+ 		"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
+ 		"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
+ 		"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
+@@ -26,6 +26,16 @@ Required properties:
+ 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
+ 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
+ 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
++		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
++		"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
++		"renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 or RZ/G1
++					   SDHI controller
++		"renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 SDHI controller
++
++
++		When compatible with the generic version, nodes must list
++		the SoC-specific version corresponding to the platform
++		first followed by the generic version.
+ 
+ - clocks: Most controllers only have 1 clock source per channel. However, on
+ 	  some variations of this controller, the internal card detection
+@@ -47,7 +57,7 @@ Optional properties:
+ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 
+ 	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 314>;
+@@ -61,7 +71,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 	};
+ 
+ 	sdhi1: sd@ee120000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee120000 0 0x328>;
+ 		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 313>;
+@@ -75,7 +85,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 	};
+ 
+ 	sdhi2: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 312>;
+@@ -89,7 +99,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 	};
+ 
+ 	sdhi3: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0156-mmc-renesas_sdhi-implement-R-Car-Gen-123-fallback-co.patch b/patches/0156-mmc-renesas_sdhi-implement-R-Car-Gen-123-fallback-co.patch
new file mode 100644
index 00000000000000..55b77731b3c75d
--- /dev/null
+++ b/patches/0156-mmc-renesas_sdhi-implement-R-Car-Gen-123-fallback-co.patch
@@ -0,0 +1,76 @@
+From 04a1dad22f8de8e5bf6754c6d8dd2e9824cc1c92 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:00:23 +0200
+Subject: [PATCH 0156/1795] mmc: renesas_sdhi: implement R-Car Gen[123]
+ fallback compatibility strings
+
+Implement fallback compatibility strings for R-Car Gen 1, 2 and 3.
+
+In the case of Renesas R-Car hardware we know that there are generations of
+SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
+between IP blocks might be. For example, I believe that r8a7790 is older
+than r8a7791 but that doesn't imply that the latter is a descendant of the
+former or vice versa.
+
+We can, however, by examining the documentation and behaviour of the
+hardware at run-time observe that the current driver implementation appears
+to be compatible with the IP blocks on SoCs within a given generation.
+
+For the above reasons and convenience when enabling new SoCs a
+per-generation fallback compatibility string scheme is being adopted for
+drivers for Renesas SoCs.
+
+Also, improve readability by listing the shmobile fallback compatibility
+string after the more-specific compatibility strings they provide a
+fallback for.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit d6dc425ae595e14026beac3720e43edd70215dc8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 5 ++++-
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 713658be6661..4c20d368f515 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -88,6 +88,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
+ 	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
+ 	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
++	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index df4465439e13..9ab10436e4b8 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -91,7 +91,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ };
+ 
+ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
+-	{ .compatible = "renesas,sdhi-shmobile" },
+ 	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
+ 	{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
+ 	{ .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
+@@ -107,6 +106,10 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
+ 	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
+ 	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
+ 	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
++	{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
++	{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
++	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
++	{ .compatible = "renesas,sdhi-shmobile" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
+-- 
+2.19.0
+
diff --git a/patches/0157-mmc-tmio-Use-common-error-handling-code-in-tmio_mmc_.patch b/patches/0157-mmc-tmio-Use-common-error-handling-code-in-tmio_mmc_.patch
new file mode 100644
index 00000000000000..282276c9daa1e9
--- /dev/null
+++ b/patches/0157-mmc-tmio-Use-common-error-handling-code-in-tmio_mmc_.patch
@@ -0,0 +1,62 @@
+From 25eaa9309036453b683e612694309cab701a3fbb Mon Sep 17 00:00:00 2001
+From: Markus Elfring <elfring@users.sourceforge.net>
+Date: Fri, 27 Oct 2017 19:09:17 +0200
+Subject: [PATCH 0157/1795] mmc: tmio: Use common error handling code in
+ tmio_mmc_host_probe()
+
+* Add a jump target so that a bit of exception handling can be better
+  reused at the end of this function.
+
+* Adjust condition checks.
+
+This issue was detected by using the Coccinelle software.
+
+Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 7f8e446b032bd6bbcec7c2f068d0a4f2d5929249)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index de1562f27fdb..788f11c0ea38 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1302,23 +1302,24 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	pm_runtime_enable(&pdev->dev);
+ 
+ 	ret = mmc_add_host(mmc);
+-	if (ret < 0) {
+-		tmio_mmc_host_remove(_host);
+-		return ret;
+-	}
++	if (ret)
++		goto remove_host;
+ 
+ 	dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
+ 
+ 	if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
+ 		ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
+-		if (ret < 0) {
+-			tmio_mmc_host_remove(_host);
+-			return ret;
+-		}
++		if (ret)
++			goto remove_host;
++
+ 		mmc_gpiod_request_cd_irq(mmc);
+ 	}
+ 
+ 	return 0;
++
++remove_host:
++	tmio_mmc_host_remove(_host);
++	return ret;
+ }
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_probe);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0158-mmc-tmio-Replace-msleep-of-20ms-or-less-with-usleep_.patch b/patches/0158-mmc-tmio-Replace-msleep-of-20ms-or-less-with-usleep_.patch
new file mode 100644
index 00000000000000..1abd2e5c1d3037
--- /dev/null
+++ b/patches/0158-mmc-tmio-Replace-msleep-of-20ms-or-less-with-usleep_.patch
@@ -0,0 +1,87 @@
+From e02729fd0f49ccf4033459ef91f825a23d317920 Mon Sep 17 00:00:00 2001
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Date: Fri, 3 Nov 2017 10:36:28 +0100
+Subject: [PATCH 0158/1795] mmc: tmio: Replace msleep() of 20ms or less with
+ usleep_range()
+
+As documented in Documentation/timers/timers-howto.txt
+as follows, replace msleep() with usleep_range().
+
+msleep(1~20) may not do what the caller intends, and
+will often sleep longer (~20 ms actual sleep for any
+value given in the 1~20ms range). In many cases this
+is not the desired behavior.
+
+Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 1f27ddf0b50b45eaf0f95565125cf10f9c821746)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 788f11c0ea38..62217afb51d6 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -167,11 +167,11 @@ static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
+ 
+ 	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
+ 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+-		msleep(10);
++		usleep_range(10000, 11000);
+ 
+ 	if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
+ 		sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
+-		msleep(10);
++		usleep_range(10000, 11000);
+ 	}
+ }
+ 
+@@ -179,7 +179,7 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
+ {
+ 	if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
+ 		sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
+-		msleep(10);
++		usleep_range(10000, 11000);
+ 	}
+ 
+ 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
+@@ -187,7 +187,7 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
+ 
+ 	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
+ 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+-		msleep(10);
++		usleep_range(10000, 11000);
+ }
+ 
+ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
+@@ -219,7 +219,7 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
+ 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+ 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
+ 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+-		msleep(10);
++		usleep_range(10000, 11000);
+ 
+ 	tmio_mmc_clk_start(host);
+ }
+@@ -230,11 +230,11 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
+ 	sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
+ 	if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
+ 		sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
+-	msleep(10);
++	usleep_range(10000, 11000);
+ 	sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
+ 	if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
+ 		sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
+-	msleep(10);
++	usleep_range(10000, 11000);
+ 
+ 	if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
+ 		sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
+-- 
+2.19.0
+
diff --git a/patches/0159-soc-renesas-identify-R-Car-V3M.patch b/patches/0159-soc-renesas-identify-R-Car-V3M.patch
new file mode 100644
index 00000000000000..43c08ec30a1e00
--- /dev/null
+++ b/patches/0159-soc-renesas-identify-R-Car-V3M.patch
@@ -0,0 +1,46 @@
+From 1ccfd2d5fbe828e645d62fa89b5defe9907549c8 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:37:17 +0300
+Subject: [PATCH 0159/1795] soc: renesas: identify R-Car V3M
+
+Add support for identifying the R-Car V3M (R8A77970) SoC.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bb0030752f288a2e2d27cc110d6d4139fe7a948d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 90d6b7a4340a..9f4ee2567c72 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -144,6 +144,11 @@ static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
+ 	.id	= 0x52,
+ };
+ 
++static const struct renesas_soc soc_rcar_v3m __initconst __maybe_unused = {
++	.family	= &fam_rcar_gen3,
++	.id	= 0x54,
++};
++
+ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
+ 	.family	= &fam_rcar_gen3,
+ 	.id	= 0x58,
+@@ -204,6 +209,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
+ #ifdef CONFIG_ARCH_R8A7796
+ 	{ .compatible = "renesas,r8a7796",	.data = &soc_rcar_m3_w },
+ #endif
++#ifdef CONFIG_ARCH_R8A77970
++	{ .compatible = "renesas,r8a77970",	.data = &soc_rcar_v3m },
++#endif
+ #ifdef CONFIG_ARCH_R8A77995
+ 	{ .compatible = "renesas,r8a77995",	.data = &soc_rcar_d3 },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0160-spi-rspi-Add-r8a7743-5-to-the-compatible-list.patch b/patches/0160-spi-rspi-Add-r8a7743-5-to-the-compatible-list.patch
new file mode 100644
index 00000000000000..9575bc9997c58a
--- /dev/null
+++ b/patches/0160-spi-rspi-Add-r8a7743-5-to-the-compatible-list.patch
@@ -0,0 +1,39 @@
+From b6a5ca983ac4324129fc0d34b9921f8f79e94248 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 8 Sep 2017 09:07:15 +0100
+Subject: [PATCH 0160/1795] spi: rspi: Add r8a7743/5 to the compatible list
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 10c1705eced11d6ad710fddcdb57aaa9f85a6f98)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/spi/spi-rspi.txt | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt
+index 8f4169f63936..3b02b3a7cfb2 100644
+--- a/Documentation/devicetree/bindings/spi/spi-rspi.txt
++++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt
+@@ -5,11 +5,14 @@ Required properties:
+ 		     "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
+ 		     For Renesas Serial Peripheral Interface on RZ/A1H:
+ 		     "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
+-		     For Quad Serial Peripheral Interface on R-Car Gen2:
++		     For Quad Serial Peripheral Interface on R-Car Gen2 and
++		     RZ/G1 devices:
+ 		     "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
+ 		     Examples with soctypes are:
+ 		        - "renesas,rspi-sh7757" (SH)
+ 			- "renesas,rspi-r7s72100" (RZ/A1H)
++			- "renesas,qspi-r8a7743" (RZ/G1M)
++			- "renesas,qspi-r8a7745" (RZ/G1E)
+ 			- "renesas,qspi-r8a7790" (R-Car H2)
+ 			- "renesas,qspi-r8a7791" (R-Car M2-W)
+ 			- "renesas,qspi-r8a7792" (R-Car V2H)
+-- 
+2.19.0
+
diff --git a/patches/0161-spi-rspi-Use-of_device_get_match_data-helper.patch b/patches/0161-spi-rspi-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..91eef02994f9b1
--- /dev/null
+++ b/patches/0161-spi-rspi-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,43 @@
+From 7f92da97669bbcb0297241761574cd2eb43241a8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:19:53 +0200
+Subject: [PATCH 0161/1795] spi: rspi: Use of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 219a7bc577e6024cd6f84571d93d939b3517aafe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-rspi.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
+index 2a10b3f94ff7..2ce875764ca6 100644
+--- a/drivers/spi/spi-rspi.c
++++ b/drivers/spi/spi-rspi.c
+@@ -1221,7 +1221,6 @@ static int rspi_probe(struct platform_device *pdev)
+ 	struct spi_master *master;
+ 	struct rspi_data *rspi;
+ 	int ret;
+-	const struct of_device_id *of_id;
+ 	const struct rspi_plat_data *rspi_pd;
+ 	const struct spi_ops *ops;
+ 
+@@ -1229,9 +1228,8 @@ static int rspi_probe(struct platform_device *pdev)
+ 	if (master == NULL)
+ 		return -ENOMEM;
+ 
+-	of_id = of_match_device(rspi_of_match, &pdev->dev);
+-	if (of_id) {
+-		ops = of_id->data;
++	ops = of_device_get_match_data(&pdev->dev);
++	if (ops) {
+ 		ret = rspi_parse_dt(&pdev->dev, master);
+ 		if (ret)
+ 			goto error1;
+-- 
+2.19.0
+
diff --git a/patches/0162-spi-rspi-Do-not-set-SPCR_SPE-in-qspi_set_config_regi.patch b/patches/0162-spi-rspi-Do-not-set-SPCR_SPE-in-qspi_set_config_regi.patch
new file mode 100644
index 00000000000000..cf1eb082b63188
--- /dev/null
+++ b/patches/0162-spi-rspi-Do-not-set-SPCR_SPE-in-qspi_set_config_regi.patch
@@ -0,0 +1,46 @@
+From 92c10528525804e8d66057a3796dca497ab0476b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 7 Dec 2017 11:09:21 +0100
+Subject: [PATCH 0162/1795] spi: rspi: Do not set SPCR_SPE in
+ qspi_set_config_register()
+
+The R-Car Gen2 Hardware User Manual Rev. 2.00 states:
+
+    If the master/slave mode select bit (MSTR) is modified while the SPI
+    function enable bit (SPE) is set to 1 (that is, this module is
+    enabled), the subsequent operation cannot be guaranteed.
+
+Hence do not set SPCR_SPE when setting SPCR_MSTR, just like the
+.set_config_register() implementations for other RSPI variants do.
+
+Note that when booted from QSPI, the boot loader will have set SPCR_MSTR
+already, hence usually the bit is never modified by the Linux driver.
+
+Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b458a3490e46dddd5b63f59b458c9b6d2284a63f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-rspi.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
+index 2ce875764ca6..0835a8d88fb8 100644
+--- a/drivers/spi/spi-rspi.c
++++ b/drivers/spi/spi-rspi.c
+@@ -377,8 +377,8 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
+ 	/* Sets SPCMD */
+ 	rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
+ 
+-	/* Enables SPI function in master mode */
+-	rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
++	/* Sets RSPI mode */
++	rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0163-pinctrl-rza1-Add-support-for-RZ-A1L.patch b/patches/0163-pinctrl-rza1-Add-support-for-RZ-A1L.patch
new file mode 100644
index 00000000000000..67306c46069df4
--- /dev/null
+++ b/patches/0163-pinctrl-rza1-Add-support-for-RZ-A1L.patch
@@ -0,0 +1,176 @@
+From 6f025204ccddfb6b222574720e0ab03abb770813 Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Wed, 4 Oct 2017 16:07:23 -0500
+Subject: [PATCH 0163/1795] pinctrl: rza1: Add support for RZ/A1L
+
+Aspects like the number of ports and the location where peripherals are
+brought out differ between the RZ/A1H and RZ/A1L.
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 039bc58e73b77723029fb5147a9d62da9d2ec22d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/pinctrl-rza1.c | 134 +++++++++++++++++++++++++++++++++
+ 1 file changed, 134 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
+index 04d058706b80..717c0f4449a0 100644
+--- a/drivers/pinctrl/pinctrl-rza1.c
++++ b/drivers/pinctrl/pinctrl-rza1.c
+@@ -302,6 +302,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = {
+ 	.swio_entries	= rza1h_swio_entries,
+ };
+ 
++/* ----------------------------------------------------------------------------
++ * RZ/A1L (r7s72102) pinmux flags
++ */
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
++	{ .pin = 0, .func = 1 },
++	{ .pin = 1, .func = 1 },
++	{ .pin = 2, .func = 1 },
++	{ .pin = 3, .func = 1 },
++	{ .pin = 4, .func = 1 },
++	{ .pin = 5, .func = 1 },
++	{ .pin = 6, .func = 1 },
++	{ .pin = 7, .func = 1 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
++	{ .pin = 0, .func = 2 },
++	{ .pin = 1, .func = 2 },
++	{ .pin = 2, .func = 2 },
++	{ .pin = 4, .func = 2 },
++	{ .pin = 5, .func = 2 },
++	{ .pin = 10, .func = 2 },
++	{ .pin = 11, .func = 2 },
++	{ .pin = 12, .func = 2 },
++	{ .pin = 13, .func = 2 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
++	{ .pin = 1, .func = 4 },
++	{ .pin = 2, .func = 2 },
++	{ .pin = 3, .func = 2 },
++	{ .pin = 6, .func = 2 },
++	{ .pin = 7, .func = 2 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
++	{ .pin = 0, .func = 1 },
++	{ .pin = 1, .func = 1 },
++	{ .pin = 2, .func = 1 },
++	{ .pin = 3, .func = 1 },
++	{ .pin = 4, .func = 1 },
++	{ .pin = 5, .func = 1 },
++	{ .pin = 6, .func = 1 },
++	{ .pin = 7, .func = 1 },
++	{ .pin = 8, .func = 1 },
++	{ .pin = 9, .func = 1 },
++	{ .pin = 10, .func = 1 },
++	{ .pin = 11, .func = 1 },
++	{ .pin = 12, .func = 1 },
++	{ .pin = 13, .func = 1 },
++	{ .pin = 14, .func = 1 },
++	{ .pin = 15, .func = 1 },
++	{ .pin = 0, .func = 2 },
++	{ .pin = 1, .func = 2 },
++	{ .pin = 2, .func = 2 },
++	{ .pin = 3, .func = 2 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
++	{ .pin = 0, .func = 1 },
++	{ .pin = 1, .func = 1 },
++	{ .pin = 2, .func = 1 },
++	{ .pin = 3, .func = 1 },
++	{ .pin = 4, .func = 1 },
++	{ .pin = 5, .func = 1 },
++	{ .pin = 6, .func = 1 },
++	{ .pin = 7, .func = 1 },
++	{ .pin = 8, .func = 1 },
++	{ .pin = 9, .func = 1 },
++	{ .pin = 10, .func = 1 },
++	{ .pin = 11, .func = 1 },
++	{ .pin = 12, .func = 1 },
++	{ .pin = 13, .func = 1 },
++	{ .pin = 14, .func = 1 },
++	{ .pin = 15, .func = 1 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
++	{ .pin = 2, .func = 2 },
++	{ .pin = 3, .func = 2 },
++	{ .pin = 5, .func = 2 },
++	{ .pin = 6, .func = 2 },
++	{ .pin = 7, .func = 2 },
++	{ .pin = 2, .func = 3 },
++	{ .pin = 3, .func = 3 },
++	{ .pin = 5, .func = 3 },
++	{ .pin = 6, .func = 3 },
++	{ .pin = 7, .func = 3 },
++};
++
++static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
++	{ .pin = 1, .func = 2 },
++	{ .pin = 0, .func = 3 },
++	{ .pin = 1, .func = 3 },
++	{ .pin = 3, .func = 3 },
++	{ .pin = 4, .func = 3 },
++	{ .pin = 5, .func = 3 },
++};
++
++static const struct rza1_swio_pin rza1l_swio_pins[] = {
++	{ .port = 2, .pin = 8, .func = 2, .input = 0 },
++	{ .port = 5, .pin = 6, .func = 3, .input = 0 },
++	{ .port = 6, .pin = 6, .func = 3, .input = 0 },
++	{ .port = 6, .pin = 10, .func = 3, .input = 0 },
++	{ .port = 7, .pin = 10, .func = 2, .input = 0 },
++	{ .port = 8, .pin = 2, .func = 3, .input = 0 },
++};
++
++static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
++	[1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
++	[3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
++	[4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
++	[5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
++	[6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
++	[7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
++	[9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
++};
++
++static const struct rza1_swio_entry rza1l_swio_entries[] = {
++	[0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
++};
++
++/* RZ/A1L (r7s72102x) pinmux flags table */
++static const struct rza1_pinmux_conf rza1l_pmx_conf = {
++	.bidir_entries	= rza1l_bidir_entries,
++	.swio_entries	= rza1l_swio_entries,
++};
++
+ /* ----------------------------------------------------------------------------
+  * RZ/A1 types
+  */
+@@ -1283,9 +1411,15 @@ static int rza1_pinctrl_probe(struct platform_device *pdev)
+ 
+ static const struct of_device_id rza1_pinctrl_of_match[] = {
+ 	{
++		/* RZ/A1H, RZ/A1M */
+ 		.compatible	= "renesas,r7s72100-ports",
+ 		.data		= &rza1h_pmx_conf,
+ 	},
++	{
++		/* RZ/A1L */
++		.compatible	= "renesas,r7s72102-ports",
++		.data		= &rza1l_pmx_conf,
++	},
+ 	{ }
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0164-dt-bindings-pinctrl-Add-support-for-RZ-A1M-and-RZ-A1.patch b/patches/0164-dt-bindings-pinctrl-Add-support-for-RZ-A1M-and-RZ-A1.patch
new file mode 100644
index 00000000000000..0c2560048c06b7
--- /dev/null
+++ b/patches/0164-dt-bindings-pinctrl-Add-support-for-RZ-A1M-and-RZ-A1.patch
@@ -0,0 +1,37 @@
+From d600c9db5c3f97ee195930d49898bde675f49988 Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Wed, 4 Oct 2017 16:07:24 -0500
+Subject: [PATCH 0164/1795] dt-bindings: pinctrl: Add support for RZ/A1M and
+ RZ/A1L
+
+Describe how to specify RZ/A1M and RZ/A1L devices.
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4a9cfe47b8ea3f7b8c551a365184f4aec993ee5d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt    | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
+index 43e21474528a..fd3696eb36bf 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
+@@ -12,8 +12,10 @@ Pin controller node
+ -------------------
+ 
+ Required properties:
+-  - compatible
+-    this shall be "renesas,r7s72100-ports".
++  - compatible: should be:
++    - "renesas,r7s72100-ports": for RZ/A1H
++    - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
++    - "renesas,r7s72102-ports": for RZ/A1L
+ 
+   - reg
+     address base and length of the memory area where the pin controller
+-- 
+2.19.0
+
diff --git a/patches/0165-ata-sata_rcar-Use-of_device_get_match_data-helper.patch b/patches/0165-ata-sata_rcar-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..9da1ed2dbb8661
--- /dev/null
+++ b/patches/0165-ata-sata_rcar-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,48 @@
+From a0d3bcb027cb51689adcbaea48cee311b2158970 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:13:07 +0200
+Subject: [PATCH 0165/1795] ata: sata_rcar: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+Note that the sata_rcar driver is used with DT only, so there's always a
+valid match.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+(cherry picked from commit 03b623fbc5d8d24d45d4e8cd4ba245b0170891f3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/ata/sata_rcar.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
+index 537d11869069..80ee2f2a50d0 100644
+--- a/drivers/ata/sata_rcar.c
++++ b/drivers/ata/sata_rcar.c
+@@ -872,7 +872,6 @@ MODULE_DEVICE_TABLE(of, sata_rcar_match);
+ 
+ static int sata_rcar_probe(struct platform_device *pdev)
+ {
+-	const struct of_device_id *of_id;
+ 	struct ata_host *host;
+ 	struct sata_rcar_priv *priv;
+ 	struct resource *mem;
+@@ -888,11 +887,7 @@ static int sata_rcar_probe(struct platform_device *pdev)
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	of_id = of_match_device(sata_rcar_match, &pdev->dev);
+-	if (!of_id)
+-		return -ENODEV;
+-
+-	priv->type = (enum sata_rcar_type)of_id->data;
++	priv->type = (enum sata_rcar_type)of_device_get_match_data(&pdev->dev);
+ 	priv->clk = devm_clk_get(&pdev->dev, NULL);
+ 	if (IS_ERR(priv->clk)) {
+ 		dev_err(&pdev->dev, "failed to get access to sata clock\n");
+-- 
+2.19.0
+
diff --git a/patches/0166-tty-add-SPDX-identifiers-to-all-remaining-files-in-d.patch b/patches/0166-tty-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
new file mode 100644
index 00000000000000..0b9d7745960ac8
--- /dev/null
+++ b/patches/0166-tty-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
@@ -0,0 +1,1909 @@
+From c7565903d250f7e3c020a76e97dfd7e75140b451 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 18:11:51 +0100
+Subject: [PATCH 0166/1795] tty: add SPDX identifiers to all remaining files in
+ drivers/tty/
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's good to have SPDX identifiers in all files to make it easier to
+audit the kernel tree for correct licenses.
+
+Update the drivers/tty files files with the correct SPDX license
+identifier based on the license text in the file itself.  The SPDX
+identifier is a legally binding shorthand, which can be used instead of
+the full boiler plate text.
+
+This work is based on a script and data from Thomas Gleixner, Philippe
+Ombredanne, and Kate Stewart.
+
+Cc: Jiri Slaby <jslaby@suse.com>
+Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Cc: Paul Mackerras <paulus@samba.org>
+Cc: Michael Ellerman <mpe@ellerman.id.au>
+Cc: Chris Metcalf <cmetcalf@mellanox.com>
+Cc: Jiri Kosina <jikos@kernel.org>
+Cc: David Sterba <dsterba@suse.com>
+Cc: James Hogan <jhogan@kernel.org>
+Cc: Rob Herring <robh@kernel.org>
+Cc: Eric Anholt <eric@anholt.net>
+Cc: Stefan Wahren <stefan.wahren@i2se.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Ray Jui <rjui@broadcom.com>
+Cc: Scott Branden <sbranden@broadcom.com>
+Cc: bcm-kernel-feedback-list@broadcom.com
+Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
+Cc: Helge Deller <deller@gmx.de>
+Cc: Joachim Eastwood <manabian@gmail.com>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Tobias Klauser <tklauser@distanz.ch>
+Cc: Russell King <linux@armlinux.org.uk>
+Cc: Vineet Gupta <vgupta@synopsys.com>
+Cc: Richard Genoud <richard.genoud@gmail.com>
+Cc: Alexander Shiyan <shc_work@mail.ru>
+Cc: Baruch Siach <baruch@tkos.co.il>
+Cc: "Maciej W. Rozycki" <macro@linux-mips.org>
+Cc: "Uwe Kleine-König" <kernel@pengutronix.de>
+Cc: Pat Gefre <pfg@sgi.com>
+Cc: "Guilherme G. Piccoli" <gpiccoli@linux.vnet.ibm.com>
+Cc: Jason Wessel <jason.wessel@windriver.com>
+Cc: Vladimir Zapolskiy <vz@mleia.com>
+Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
+Cc: Carlo Caione <carlo@caione.org>
+Cc: Kevin Hilman <khilman@baylibre.com>
+Cc: Liviu Dudau <liviu.dudau@arm.com>
+Cc: Sudeep Holla <sudeep.holla@arm.com>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Andy Gross <andy.gross@linaro.org>
+Cc: David Brown <david.brown@linaro.org>
+Cc: "Andreas Färber" <afaerber@suse.de>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Cc: Laxman Dewangan <ldewangan@nvidia.com>
+Cc: Thierry Reding <thierry.reding@gmail.com>
+Cc: Jonathan Hunter <jonathanh@nvidia.com>
+Cc: Barry Song <baohua@kernel.org>
+Cc: Patrice Chotard <patrice.chotard@st.com>
+Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+Cc: Alexandre Torgue <alexandre.torgue@st.com>
+Cc: "David S. Miller" <davem@davemloft.net>
+Cc: Peter Korsgaard <jacmet@sunsite.dk>
+Cc: Timur Tabi <timur@tabi.org>
+Cc: Tony Prisk <linux@prisktech.co.nz>
+Cc: Michal Simek <michal.simek@xilinx.com>
+Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Kate Stewart <kstewart@linuxfoundation.org>
+Cc: Philippe Ombredanne <pombredanne@nexb.com>
+Cc: Jiri Slaby <jslaby@suse.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit e3b3d0f549c1d19b94e6ac55c66643166ea649ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/amiserial.c                      | 1 +
+ drivers/tty/bfin_jtag_comm.c                 | 1 +
+ drivers/tty/cyclades.c                       | 1 +
+ drivers/tty/ehv_bytechan.c                   | 1 +
+ drivers/tty/goldfish.c                       | 1 +
+ drivers/tty/hvc/hvc_bfin_jtag.c              | 1 +
+ drivers/tty/hvc/hvc_console.c                | 1 +
+ drivers/tty/hvc/hvc_console.h                | 1 +
+ drivers/tty/hvc/hvc_dcc.c                    | 1 +
+ drivers/tty/hvc/hvc_opal.c                   | 1 +
+ drivers/tty/hvc/hvc_rtas.c                   | 1 +
+ drivers/tty/hvc/hvc_tile.c                   | 1 +
+ drivers/tty/hvc/hvc_udbg.c                   | 1 +
+ drivers/tty/hvc/hvc_vio.c                    | 1 +
+ drivers/tty/hvc/hvc_xen.c                    | 1 +
+ drivers/tty/hvc/hvcs.c                       | 1 +
+ drivers/tty/hvc/hvsi.c                       | 1 +
+ drivers/tty/ipwireless/main.c                | 1 +
+ drivers/tty/isicom.c                         | 1 +
+ drivers/tty/metag_da.c                       | 1 +
+ drivers/tty/mips_ejtag_fdc.c                 | 1 +
+ drivers/tty/moxa.c                           | 1 +
+ drivers/tty/mxser.c                          | 1 +
+ drivers/tty/n_gsm.c                          | 1 +
+ drivers/tty/n_hdlc.c                         | 1 +
+ drivers/tty/n_null.c                         | 1 +
+ drivers/tty/n_r3964.c                        | 1 +
+ drivers/tty/n_tracerouter.c                  | 1 +
+ drivers/tty/n_tracesink.c                    | 1 +
+ drivers/tty/n_tracesink.h                    | 1 +
+ drivers/tty/n_tty.c                          | 1 +
+ drivers/tty/nozomi.c                         | 1 +
+ drivers/tty/rocket.c                         | 1 +
+ drivers/tty/serdev/core.c                    | 1 +
+ drivers/tty/serdev/serdev-ttyport.c          | 1 +
+ drivers/tty/serial/21285.c                   | 1 +
+ drivers/tty/serial/8250/8250.h               | 1 +
+ drivers/tty/serial/8250/8250_accent.c        | 1 +
+ drivers/tty/serial/8250/8250_acorn.c         | 1 +
+ drivers/tty/serial/8250/8250_aspeed_vuart.c  | 1 +
+ drivers/tty/serial/8250/8250_bcm2835aux.c    | 1 +
+ drivers/tty/serial/8250/8250_boca.c          | 1 +
+ drivers/tty/serial/8250/8250_core.c          | 1 +
+ drivers/tty/serial/8250/8250_dma.c           | 1 +
+ drivers/tty/serial/8250/8250_dw.c            | 1 +
+ drivers/tty/serial/8250/8250_early.c         | 1 +
+ drivers/tty/serial/8250/8250_em.c            | 1 +
+ drivers/tty/serial/8250/8250_exar.c          | 1 +
+ drivers/tty/serial/8250/8250_exar_st16c554.c | 1 +
+ drivers/tty/serial/8250/8250_fintek.c        | 1 +
+ drivers/tty/serial/8250/8250_fourport.c      | 1 +
+ drivers/tty/serial/8250/8250_fsl.c           | 1 +
+ drivers/tty/serial/8250/8250_gsc.c           | 1 +
+ drivers/tty/serial/8250/8250_hp300.c         | 1 +
+ drivers/tty/serial/8250/8250_hub6.c          | 1 +
+ drivers/tty/serial/8250/8250_ingenic.c       | 1 +
+ drivers/tty/serial/8250/8250_lpc18xx.c       | 1 +
+ drivers/tty/serial/8250/8250_lpss.c          | 1 +
+ drivers/tty/serial/8250/8250_mid.c           | 1 +
+ drivers/tty/serial/8250/8250_moxa.c          | 1 +
+ drivers/tty/serial/8250/8250_mtk.c           | 1 +
+ drivers/tty/serial/8250/8250_of.c            | 1 +
+ drivers/tty/serial/8250/8250_omap.c          | 1 +
+ drivers/tty/serial/8250/8250_pci.c           | 1 +
+ drivers/tty/serial/8250/8250_pnp.c           | 1 +
+ drivers/tty/serial/8250/8250_port.c          | 1 +
+ drivers/tty/serial/8250/8250_pxa.c           | 1 +
+ drivers/tty/serial/8250/8250_uniphier.c      | 1 +
+ drivers/tty/serial/8250/serial_cs.c          | 1 +
+ drivers/tty/serial/altera_jtaguart.c         | 1 +
+ drivers/tty/serial/altera_uart.c             | 1 +
+ drivers/tty/serial/amba-pl010.c              | 1 +
+ drivers/tty/serial/amba-pl011.c              | 1 +
+ drivers/tty/serial/apbuart.c                 | 1 +
+ drivers/tty/serial/ar933x_uart.c             | 1 +
+ drivers/tty/serial/arc_uart.c                | 1 +
+ drivers/tty/serial/atmel_serial.c            | 1 +
+ drivers/tty/serial/atmel_serial.h            | 1 +
+ drivers/tty/serial/bcm63xx_uart.c            | 1 +
+ drivers/tty/serial/bfin_sport_uart.c         | 1 +
+ drivers/tty/serial/bfin_sport_uart.h         | 1 +
+ drivers/tty/serial/bfin_uart.c               | 1 +
+ drivers/tty/serial/clps711x.c                | 1 +
+ drivers/tty/serial/cpm_uart/cpm_uart.h       | 1 +
+ drivers/tty/serial/cpm_uart/cpm_uart_core.c  | 1 +
+ drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c  | 1 +
+ drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c  | 1 +
+ drivers/tty/serial/digicolor-usart.c         | 1 +
+ drivers/tty/serial/dz.c                      | 1 +
+ drivers/tty/serial/earlycon-arm-semihost.c   | 1 +
+ drivers/tty/serial/earlycon.c                | 1 +
+ drivers/tty/serial/efm32-uart.c              | 1 +
+ drivers/tty/serial/fsl_lpuart.c              | 1 +
+ drivers/tty/serial/icom.c                    | 1 +
+ drivers/tty/serial/icom.h                    | 1 +
+ drivers/tty/serial/ifx6x60.c                 | 1 +
+ drivers/tty/serial/ifx6x60.h                 | 1 +
+ drivers/tty/serial/imx.c                     | 1 +
+ drivers/tty/serial/ioc3_serial.c             | 1 +
+ drivers/tty/serial/ioc4_serial.c             | 1 +
+ drivers/tty/serial/ip22zilog.c               | 1 +
+ drivers/tty/serial/jsm/jsm.h                 | 1 +
+ drivers/tty/serial/jsm/jsm_cls.c             | 1 +
+ drivers/tty/serial/jsm/jsm_driver.c          | 1 +
+ drivers/tty/serial/jsm/jsm_neo.c             | 1 +
+ drivers/tty/serial/jsm/jsm_tty.c             | 1 +
+ drivers/tty/serial/kgdb_nmi.c                | 1 +
+ drivers/tty/serial/kgdboc.c                  | 1 +
+ drivers/tty/serial/lantiq.c                  | 1 +
+ drivers/tty/serial/lpc32xx_hs.c              | 1 +
+ drivers/tty/serial/m32r_sio.c                | 1 +
+ drivers/tty/serial/m32r_sio_reg.h            | 1 +
+ drivers/tty/serial/max3100.c                 | 1 +
+ drivers/tty/serial/max310x.c                 | 1 +
+ drivers/tty/serial/mcf.c                     | 1 +
+ drivers/tty/serial/men_z135_uart.c           | 1 +
+ drivers/tty/serial/meson_uart.c              | 1 +
+ drivers/tty/serial/mpc52xx_uart.c            | 1 +
+ drivers/tty/serial/mps2-uart.c               | 1 +
+ drivers/tty/serial/mpsc.c                    | 1 +
+ drivers/tty/serial/msm_serial.c              | 1 +
+ drivers/tty/serial/mux.c                     | 1 +
+ drivers/tty/serial/mvebu-uart.c              | 1 +
+ drivers/tty/serial/mxs-auart.c               | 1 +
+ drivers/tty/serial/netx-serial.c             | 1 +
+ drivers/tty/serial/omap-serial.c             | 1 +
+ drivers/tty/serial/owl-uart.c                | 1 +
+ drivers/tty/serial/pch_uart.c                | 1 +
+ drivers/tty/serial/pic32_uart.c              | 1 +
+ drivers/tty/serial/pic32_uart.h              | 1 +
+ drivers/tty/serial/pmac_zilog.c              | 1 +
+ drivers/tty/serial/pnx8xxx_uart.c            | 1 +
+ drivers/tty/serial/pxa.c                     | 1 +
+ drivers/tty/serial/rp2.c                     | 1 +
+ drivers/tty/serial/sa1100.c                  | 1 +
+ drivers/tty/serial/samsung.c                 | 1 +
+ drivers/tty/serial/samsung.h                 | 1 +
+ drivers/tty/serial/sb1250-duart.c            | 1 +
+ drivers/tty/serial/sc16is7xx.c               | 1 +
+ drivers/tty/serial/sccnxp.c                  | 1 +
+ drivers/tty/serial/serial-tegra.c            | 1 +
+ drivers/tty/serial/serial_core.c             | 1 +
+ drivers/tty/serial/serial_ks8695.c           | 1 +
+ drivers/tty/serial/serial_mctrl_gpio.c       | 1 +
+ drivers/tty/serial/serial_mctrl_gpio.h       | 1 +
+ drivers/tty/serial/serial_txx9.c             | 1 +
+ drivers/tty/serial/sh-sci.c                  | 1 +
+ drivers/tty/serial/sirfsoc_uart.c            | 1 +
+ drivers/tty/serial/sirfsoc_uart.h            | 1 +
+ drivers/tty/serial/sprd_serial.c             | 1 +
+ drivers/tty/serial/st-asc.c                  | 1 +
+ drivers/tty/serial/stm32-usart.c             | 1 +
+ drivers/tty/serial/stm32-usart.h             | 1 +
+ drivers/tty/serial/suncore.c                 | 1 +
+ drivers/tty/serial/sunhv.c                   | 1 +
+ drivers/tty/serial/sunsab.c                  | 1 +
+ drivers/tty/serial/sunsu.c                   | 1 +
+ drivers/tty/serial/sunzilog.c                | 1 +
+ drivers/tty/serial/tilegx.c                  | 1 +
+ drivers/tty/serial/timbuart.c                | 1 +
+ drivers/tty/serial/timbuart.h                | 1 +
+ drivers/tty/serial/uartlite.c                | 1 +
+ drivers/tty/serial/ucc_uart.c                | 1 +
+ drivers/tty/serial/vr41xx_siu.c              | 1 +
+ drivers/tty/serial/vt8500_serial.c           | 1 +
+ drivers/tty/serial/xilinx_uartps.c           | 1 +
+ drivers/tty/serial/zs.c                      | 1 +
+ drivers/tty/synclink.c                       | 1 +
+ drivers/tty/synclink_gt.c                    | 1 +
+ drivers/tty/synclinkmp.c                     | 1 +
+ drivers/tty/tty_audit.c                      | 1 +
+ drivers/tty/tty_baudrate.c                   | 1 +
+ drivers/tty/tty_buffer.c                     | 1 +
+ drivers/tty/tty_io.c                         | 1 +
+ drivers/tty/tty_ioctl.c                      | 1 +
+ drivers/tty/tty_jobctrl.c                    | 1 +
+ drivers/tty/tty_ldisc.c                      | 1 +
+ drivers/tty/tty_ldsem.c                      | 1 +
+ drivers/tty/tty_port.c                       | 1 +
+ drivers/tty/vt/consolemap.c                  | 1 +
+ drivers/tty/vt/keyboard.c                    | 1 +
+ drivers/tty/vt/vt.c                          | 1 +
+ 182 files changed, 182 insertions(+)
+
+diff --git a/drivers/tty/amiserial.c b/drivers/tty/amiserial.c
+index 9820e20993db..32d7ce430b02 100644
+--- a/drivers/tty/amiserial.c
++++ b/drivers/tty/amiserial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Serial driver for the amiga builtin port.
+  *
+diff --git a/drivers/tty/bfin_jtag_comm.c b/drivers/tty/bfin_jtag_comm.c
+index ce24182f8514..d569692b3bea 100644
+--- a/drivers/tty/bfin_jtag_comm.c
++++ b/drivers/tty/bfin_jtag_comm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * TTY over Blackfin JTAG Communication
+  *
+diff --git a/drivers/tty/cyclades.c b/drivers/tty/cyclades.c
+index d272bc4e7fb5..b646a1dc801b 100644
+--- a/drivers/tty/cyclades.c
++++ b/drivers/tty/cyclades.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #undef	BLOCKMOVE
+ #define	Z_WAKE
+ #undef	Z_EXT_CHARS_IN_BUFFER
+diff --git a/drivers/tty/ehv_bytechan.c b/drivers/tty/ehv_bytechan.c
+index a1c7125cb968..9637f343deaf 100644
+--- a/drivers/tty/ehv_bytechan.c
++++ b/drivers/tty/ehv_bytechan.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* ePAPR hypervisor byte channel device driver
+  *
+  * Copyright 2009-2011 Freescale Semiconductor, Inc.
+diff --git a/drivers/tty/goldfish.c b/drivers/tty/goldfish.c
+index 85a500ddbcaa..4b5c0e3dd242 100644
+--- a/drivers/tty/goldfish.c
++++ b/drivers/tty/goldfish.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2007 Google, Inc.
+  * Copyright (C) 2012 Intel, Inc.
+diff --git a/drivers/tty/hvc/hvc_bfin_jtag.c b/drivers/tty/hvc/hvc_bfin_jtag.c
+index 31d6cc6a77af..24ff4c468e6d 100644
+--- a/drivers/tty/hvc/hvc_bfin_jtag.c
++++ b/drivers/tty/hvc/hvc_bfin_jtag.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Console via Blackfin JTAG Communication
+  *
+diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
+index a8d399188242..fed03a676f07 100644
+--- a/drivers/tty/hvc/hvc_console.c
++++ b/drivers/tty/hvc/hvc_console.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
+  * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
+diff --git a/drivers/tty/hvc/hvc_console.h b/drivers/tty/hvc/hvc_console.h
+index 798c48d0d32c..74c9a20489db 100644
+--- a/drivers/tty/hvc/hvc_console.h
++++ b/drivers/tty/hvc/hvc_console.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * hvc_console.h
+  * Copyright (C) 2005 IBM Corporation
+diff --git a/drivers/tty/hvc/hvc_dcc.c b/drivers/tty/hvc/hvc_dcc.c
+index 82f240fb98f0..3e4fb8736d10 100644
+--- a/drivers/tty/hvc/hvc_dcc.c
++++ b/drivers/tty/hvc/hvc_dcc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved.
+  *
+  * This program is free software; you can redistribute it and/or modify
+diff --git a/drivers/tty/hvc/hvc_opal.c b/drivers/tty/hvc/hvc_opal.c
+index 9da8474fe50a..237bd4fee07a 100644
+--- a/drivers/tty/hvc/hvc_opal.c
++++ b/drivers/tty/hvc/hvc_opal.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * opal driver interface to hvc_console.c
+  *
+diff --git a/drivers/tty/hvc/hvc_rtas.c b/drivers/tty/hvc/hvc_rtas.c
+index 08c87920b74a..c168bd5ffc26 100644
+--- a/drivers/tty/hvc/hvc_rtas.c
++++ b/drivers/tty/hvc/hvc_rtas.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * IBM RTAS driver interface to hvc_console.c
+  *
+diff --git a/drivers/tty/hvc/hvc_tile.c b/drivers/tty/hvc/hvc_tile.c
+index 9da1e842bbe9..cdd8fa774b56 100644
+--- a/drivers/tty/hvc/hvc_tile.c
++++ b/drivers/tty/hvc/hvc_tile.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2010 Tilera Corporation. All Rights Reserved.
+  *
+diff --git a/drivers/tty/hvc/hvc_udbg.c b/drivers/tty/hvc/hvc_udbg.c
+index 9cf573d06a29..d32929b0ce41 100644
+--- a/drivers/tty/hvc/hvc_udbg.c
++++ b/drivers/tty/hvc/hvc_udbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * udbg interface to hvc_console.c
+  *
+diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
+index a1d272ac82bb..287ccf682c84 100644
+--- a/drivers/tty/hvc/hvc_vio.c
++++ b/drivers/tty/hvc/hvc_vio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vio driver interface to hvc_console.c
+  *
+diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
+index 5e87e4866bcb..e38a50dc58b2 100644
+--- a/drivers/tty/hvc/hvc_xen.c
++++ b/drivers/tty/hvc/hvc_xen.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * xen console driver interface to hvc_console.c
+  *
+diff --git a/drivers/tty/hvc/hvcs.c b/drivers/tty/hvc/hvcs.c
+index 63c29fe9d21f..fc5a12e56276 100644
+--- a/drivers/tty/hvc/hvcs.c
++++ b/drivers/tty/hvc/hvcs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * IBM eServer Hypervisor Virtual Console Server Device Driver
+  * Copyright (C) 2003, 2004 IBM Corp.
+diff --git a/drivers/tty/hvc/hvsi.c b/drivers/tty/hvc/hvsi.c
+index 2e578d6433af..63ebc73565fc 100644
+--- a/drivers/tty/hvc/hvsi.c
++++ b/drivers/tty/hvc/hvsi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2004 Hollis Blanchard <hollisb@us.ibm.com>, IBM
+  *
+diff --git a/drivers/tty/ipwireless/main.c b/drivers/tty/ipwireless/main.c
+index 655c7948261c..3475e841ef5c 100644
+--- a/drivers/tty/ipwireless/main.c
++++ b/drivers/tty/ipwireless/main.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * IPWireless 3G PCMCIA Network Driver
+  *
+diff --git a/drivers/tty/isicom.c b/drivers/tty/isicom.c
+index 61ecdd6b2fc2..a598f79ee3fa 100644
+--- a/drivers/tty/isicom.c
++++ b/drivers/tty/isicom.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	This program is free software; you can redistribute it and/or
+  *	modify it under the terms of the GNU General Public License
+diff --git a/drivers/tty/metag_da.c b/drivers/tty/metag_da.c
+index 25ccef2fe748..278265e24e89 100644
+--- a/drivers/tty/metag_da.c
++++ b/drivers/tty/metag_da.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  dashtty.c - tty driver for Dash channels interface.
+  *
+diff --git a/drivers/tty/mips_ejtag_fdc.c b/drivers/tty/mips_ejtag_fdc.c
+index a2dab3fb8751..bbadd927b036 100644
+--- a/drivers/tty/mips_ejtag_fdc.c
++++ b/drivers/tty/mips_ejtag_fdc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * TTY driver for MIPS EJTAG Fast Debug Channels.
+  *
+diff --git a/drivers/tty/moxa.c b/drivers/tty/moxa.c
+index 7f3d4cb0341b..8223960abb68 100644
+--- a/drivers/tty/moxa.c
++++ b/drivers/tty/moxa.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*****************************************************************************/
+ /*
+  *           moxa.c  -- MOXA Intellio family multiport serial driver.
+diff --git a/drivers/tty/mxser.c b/drivers/tty/mxser.c
+index 7dd38047ba23..22f4f35f295f 100644
+--- a/drivers/tty/mxser.c
++++ b/drivers/tty/mxser.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *          mxser.c  -- MOXA Smartio/Industio family multiport serial driver.
+  *
+diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
+index f46bd1af7a10..a572be56dc1f 100644
+--- a/drivers/tty/n_gsm.c
++++ b/drivers/tty/n_gsm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * n_gsm.c GSM 0710 tty multiplexor
+  * Copyright (c) 2009/10 Intel Corporation
+diff --git a/drivers/tty/n_hdlc.c b/drivers/tty/n_hdlc.c
+index 7b2a466616d6..e2af7b1161f6 100644
+--- a/drivers/tty/n_hdlc.c
++++ b/drivers/tty/n_hdlc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /* generic HDLC line discipline for Linux
+  *
+  * Written by Paul Fulghum paulkf@microgate.com
+diff --git a/drivers/tty/n_null.c b/drivers/tty/n_null.c
+index d63261c36e42..cf6dc0fa401a 100644
+--- a/drivers/tty/n_null.c
++++ b/drivers/tty/n_null.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/types.h>
+ #include <linux/errno.h>
+ #include <linux/tty.h>
+diff --git a/drivers/tty/n_r3964.c b/drivers/tty/n_r3964.c
+index 305b6490d405..d18411500b1a 100644
+--- a/drivers/tty/n_r3964.c
++++ b/drivers/tty/n_r3964.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /* r3964 linediscipline for linux
+  *
+  * -----------------------------------------------------------
+diff --git a/drivers/tty/n_tracerouter.c b/drivers/tty/n_tracerouter.c
+index ac5716979bc1..717d0c111b72 100644
+--- a/drivers/tty/n_tracerouter.c
++++ b/drivers/tty/n_tracerouter.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  n_tracerouter.c - Trace data router through tty space
+  *
+diff --git a/drivers/tty/n_tracesink.c b/drivers/tty/n_tracesink.c
+index 4616870a6b1b..f90709495c2f 100644
+--- a/drivers/tty/n_tracesink.c
++++ b/drivers/tty/n_tracesink.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  n_tracesink.c - Trace data router and sink path through tty space.
+  *
+diff --git a/drivers/tty/n_tracesink.h b/drivers/tty/n_tracesink.h
+index a68bb44f1ef5..2c9efd32f41b 100644
+--- a/drivers/tty/n_tracesink.h
++++ b/drivers/tty/n_tracesink.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  n_tracesink.h - Kernel driver API to route trace data in kernel space.
+  *
+diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
+index 0475f9685a41..ac53ffd746ad 100644
+--- a/drivers/tty/n_tty.c
++++ b/drivers/tty/n_tty.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * n_tty.c --- implements the N_TTY line discipline.
+  *
+diff --git a/drivers/tty/nozomi.c b/drivers/tty/nozomi.c
+index 39b3723a32a6..ec3e1b26b616 100644
+--- a/drivers/tty/nozomi.c
++++ b/drivers/tty/nozomi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * nozomi.c  -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
+  *
+diff --git a/drivers/tty/rocket.c b/drivers/tty/rocket.c
+index 20d79a6007d5..59cd4b218218 100644
+--- a/drivers/tty/rocket.c
++++ b/drivers/tty/rocket.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * RocketPort device driver for Linux
+  *
+diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
+index ae2564ecddcd..4c9c83c3015f 100644
+--- a/drivers/tty/serdev/core.c
++++ b/drivers/tty/serdev/core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2016-2017 Linaro Ltd., Rob Herring <robh@kernel.org>
+  *
+diff --git a/drivers/tty/serdev/serdev-ttyport.c b/drivers/tty/serdev/serdev-ttyport.c
+index 69fc6d9ab490..1c433cc293fa 100644
+--- a/drivers/tty/serdev/serdev-ttyport.c
++++ b/drivers/tty/serdev/serdev-ttyport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2016-2017 Linaro Ltd., Rob Herring <robh@kernel.org>
+  *
+diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
+index 804632b4a929..32b3acf8150a 100644
+--- a/drivers/tty/serial/21285.c
++++ b/drivers/tty/serial/21285.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
+  *
+diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
+index b2bdc35f7495..36e9ae190fc0 100644
+--- a/drivers/tty/serial/8250/8250.h
++++ b/drivers/tty/serial/8250/8250.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for 8250/16550-type serial ports
+  *
+diff --git a/drivers/tty/serial/8250/8250_accent.c b/drivers/tty/serial/8250/8250_accent.c
+index 522aeae05192..2c11bc1f49c2 100644
+--- a/drivers/tty/serial/8250/8250_accent.c
++++ b/drivers/tty/serial/8250/8250_accent.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+diff --git a/drivers/tty/serial/8250/8250_acorn.c b/drivers/tty/serial/8250/8250_acorn.c
+index 402dfdd4940e..5395343fcf15 100644
+--- a/drivers/tty/serial/8250/8250_acorn.c
++++ b/drivers/tty/serial/8250/8250_acorn.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  linux/drivers/serial/acorn.c
+  *
+diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
+index 33a801353114..c468bcc4e638 100644
+--- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
++++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Serial Port driver for Aspeed VUART device
+  *
+diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c b/drivers/tty/serial/8250/8250_bcm2835aux.c
+index a23c7da42ea8..242ec1883768 100644
+--- a/drivers/tty/serial/8250/8250_bcm2835aux.c
++++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Serial port driver for BCM2835AUX UART
+  *
+diff --git a/drivers/tty/serial/8250/8250_boca.c b/drivers/tty/serial/8250/8250_boca.c
+index a63b5998e383..4123eb887020 100644
+--- a/drivers/tty/serial/8250/8250_boca.c
++++ b/drivers/tty/serial/8250/8250_boca.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
+index d29b512a7d9f..3975281fd66f 100644
+--- a/drivers/tty/serial/8250/8250_core.c
++++ b/drivers/tty/serial/8250/8250_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Universal/legacy driver for 8250/16550-type serial ports
+  *
+diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c
+index 26f17456b0d7..fe9259330886 100644
+--- a/drivers/tty/serial/8250/8250_dma.c
++++ b/drivers/tty/serial/8250/8250_dma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * 8250_dma.c - DMA Engine API support for 8250.c
+  *
+diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
+index 27c5b2b46b8d..e4426c3d78aa 100644
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Synopsys DesignWare 8250 driver.
+  *
+diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c
+index f135c1846477..bfa3dcc238ac 100644
+--- a/drivers/tty/serial/8250/8250_early.c
++++ b/drivers/tty/serial/8250/8250_early.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Early serial console for 8250/16550 devices
+  *
+diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c
+index 0b6381214917..36355b365c51 100644
+--- a/drivers/tty/serial/8250/8250_em.c
++++ b/drivers/tty/serial/8250/8250_em.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Renesas Emma Mobile 8250 driver
+  *
+diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c
+index 411b4b03457b..3268d3e27107 100644
+--- a/drivers/tty/serial/8250/8250_exar.c
++++ b/drivers/tty/serial/8250/8250_exar.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Probe module for 8250/16550-type Exar chips PCI serial ports.
+  *
+diff --git a/drivers/tty/serial/8250/8250_exar_st16c554.c b/drivers/tty/serial/8250/8250_exar_st16c554.c
+index 3a7cb8262bb9..0b1318b38cdf 100644
+--- a/drivers/tty/serial/8250/8250_exar_st16c554.c
++++ b/drivers/tty/serial/8250/8250_exar_st16c554.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
+  *  Based on 8250_boca.
+diff --git a/drivers/tty/serial/8250/8250_fintek.c b/drivers/tty/serial/8250/8250_fintek.c
+index ba4af5434b91..3b2ebff7bef0 100644
+--- a/drivers/tty/serial/8250/8250_fintek.c
++++ b/drivers/tty/serial/8250/8250_fintek.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Probe for F81216A LPC to 4 UART
+  *
+diff --git a/drivers/tty/serial/8250/8250_fourport.c b/drivers/tty/serial/8250/8250_fourport.c
+index 4045180a8cfc..1d8e936a18b4 100644
+--- a/drivers/tty/serial/8250/8250_fourport.c
++++ b/drivers/tty/serial/8250/8250_fourport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+diff --git a/drivers/tty/serial/8250/8250_fsl.c b/drivers/tty/serial/8250/8250_fsl.c
+index 910bfee5a88b..dafe7aa081b3 100644
+--- a/drivers/tty/serial/8250/8250_fsl.c
++++ b/drivers/tty/serial/8250/8250_fsl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/serial_reg.h>
+ #include <linux/serial_8250.h>
+ 
+diff --git a/drivers/tty/serial/8250/8250_gsc.c b/drivers/tty/serial/8250/8250_gsc.c
+index df2931e1e086..8eea662d6987 100644
+--- a/drivers/tty/serial/8250/8250_gsc.c
++++ b/drivers/tty/serial/8250/8250_gsc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	Serial Device Initialisation for Lasi/Asp/Wax/Dino
+  *
+diff --git a/drivers/tty/serial/8250/8250_hp300.c b/drivers/tty/serial/8250/8250_hp300.c
+index 115190b7962a..3012ea03d22c 100644
+--- a/drivers/tty/serial/8250/8250_hp300.c
++++ b/drivers/tty/serial/8250/8250_hp300.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the 98626/98644/internal serial interface on hp300/hp400
+  * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
+diff --git a/drivers/tty/serial/8250/8250_hub6.c b/drivers/tty/serial/8250/8250_hub6.c
+index 27124e21eb96..f75c89ec7ebc 100644
+--- a/drivers/tty/serial/8250/8250_hub6.c
++++ b/drivers/tty/serial/8250/8250_hub6.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
+index 464389b28900..5c993a3af653 100644
+--- a/drivers/tty/serial/8250/8250_ingenic.c
++++ b/drivers/tty/serial/8250/8250_ingenic.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
+  * Copyright (C) 2015 Imagination Technologies
+diff --git a/drivers/tty/serial/8250/8250_lpc18xx.c b/drivers/tty/serial/8250/8250_lpc18xx.c
+index 99cd478851ff..e34011535a6a 100644
+--- a/drivers/tty/serial/8250/8250_lpc18xx.c
++++ b/drivers/tty/serial/8250/8250_lpc18xx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Serial port driver for NXP LPC18xx/43xx UART
+  *
+diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c
+index 7dddd7e6a01c..f4b596da0a3d 100644
+--- a/drivers/tty/serial/8250/8250_lpss.c
++++ b/drivers/tty/serial/8250/8250_lpss.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
+  *
+diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c
+index ec957cce8c9a..174a95778935 100644
+--- a/drivers/tty/serial/8250/8250_mid.c
++++ b/drivers/tty/serial/8250/8250_mid.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * 8250_mid.c - Driver for UART on Intel Penwell and various other Intel SOCs
+  *
+diff --git a/drivers/tty/serial/8250/8250_moxa.c b/drivers/tty/serial/8250/8250_moxa.c
+index d5069b2d4d79..da18dd62e608 100644
+--- a/drivers/tty/serial/8250/8250_moxa.c
++++ b/drivers/tty/serial/8250/8250_moxa.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * 8250_moxa.c - MOXA Smartio/Industio MUE multiport serial driver.
+  *
+diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
+index fb45770d47aa..1e3d983ac483 100644
+--- a/drivers/tty/serial/8250/8250_mtk.c
++++ b/drivers/tty/serial/8250/8250_mtk.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Mediatek 8250 driver.
+  *
+diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
+index 3613a6aabfb3..28118c5630ac 100644
+--- a/drivers/tty/serial/8250/8250_of.c
++++ b/drivers/tty/serial/8250/8250_of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Serial Port driver for Open Firmware platform devices
+  *
+diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
+index da04ba1ecf68..9d2e7392f24b 100644
+--- a/drivers/tty/serial/8250/8250_omap.c
++++ b/drivers/tty/serial/8250/8250_omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * 8250-core based driver for the OMAP internal UART
+  *
+diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
+index 4986b4aebe80..ead29f3c03e0 100644
+--- a/drivers/tty/serial/8250/8250_pci.c
++++ b/drivers/tty/serial/8250/8250_pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Probe module for 8250/16550-type PCI serial ports.
+  *
+diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8250_pnp.c
+index 34f05ed78b68..b556f37b9ba9 100644
+--- a/drivers/tty/serial/8250/8250_pnp.c
++++ b/drivers/tty/serial/8250/8250_pnp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Probe for 8250/16550-type ISAPNP serial ports.
+  *
+diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
+index ecf3d631bc09..a8f760ea1282 100644
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Base port operations for 8250/16550-type serial ports
+  *
+diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c
+index 4d68731af534..5ca660c04a9d 100644
+--- a/drivers/tty/serial/8250/8250_pxa.c
++++ b/drivers/tty/serial/8250/8250_pxa.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
+  *  Copyright:	(C) 2013 Sergei Ianovich <ynvich@gmail.com>
+diff --git a/drivers/tty/serial/8250/8250_uniphier.c b/drivers/tty/serial/8250/8250_uniphier.c
+index c206f173f912..752fad67c3fe 100644
+--- a/drivers/tty/serial/8250/8250_uniphier.c
++++ b/drivers/tty/serial/8250/8250_uniphier.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+  *
+diff --git a/drivers/tty/serial/8250/serial_cs.c b/drivers/tty/serial/8250/serial_cs.c
+index 933c2688dd7e..9963a766dcfb 100644
+--- a/drivers/tty/serial/8250/serial_cs.c
++++ b/drivers/tty/serial/8250/serial_cs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
+ /*======================================================================
+ 
+     A driver for PCMCIA serial devices
+diff --git a/drivers/tty/serial/altera_jtaguart.c b/drivers/tty/serial/altera_jtaguart.c
+index 0475f5d261ce..ef444aff77c5 100644
+--- a/drivers/tty/serial/altera_jtaguart.c
++++ b/drivers/tty/serial/altera_jtaguart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * altera_jtaguart.c -- Altera JTAG UART driver
+  *
+diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c
+index 59cb62de236b..69d9c2fd5f85 100644
+--- a/drivers/tty/serial/altera_uart.c
++++ b/drivers/tty/serial/altera_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * altera_uart.c -- Altera UART driver
+  *
+diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
+index 9ec4b8d2879f..a64a20c8e28b 100644
+--- a/drivers/tty/serial/amba-pl010.c
++++ b/drivers/tty/serial/amba-pl010.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for AMBA serial ports
+  *
+diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
+index c9f701aca677..51e7060599f7 100644
+--- a/drivers/tty/serial/amba-pl011.c
++++ b/drivers/tty/serial/amba-pl011.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for AMBA serial ports
+  *
+diff --git a/drivers/tty/serial/apbuart.c b/drivers/tty/serial/apbuart.c
+index dd60ed96a0ad..60cd133ffbbc 100644
+--- a/drivers/tty/serial/apbuart.c
++++ b/drivers/tty/serial/apbuart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Driver for GRLIB serial ports (APBUART)
+  *
+diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c
+index decc7f3c1ab2..15cd1a3ea6bf 100644
+--- a/drivers/tty/serial/ar933x_uart.c
++++ b/drivers/tty/serial/ar933x_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Atheros AR933X SoC built-in UART driver
+  *
+diff --git a/drivers/tty/serial/arc_uart.c b/drivers/tty/serial/arc_uart.c
+index 71e37abb6bcb..0a8b80fa09cd 100644
+--- a/drivers/tty/serial/arc_uart.c
++++ b/drivers/tty/serial/arc_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ARC On-Chip(fpga) UART Driver
+  *
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 2286e9d73115..6dbbecde955a 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for Atmel AT91 Serial ports
+  *  Copyright (C) 2003 Rick Bronson
+diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
+index bd2560502f3c..b4e0e57a0a79 100644
+--- a/drivers/tty/serial/atmel_serial.h
++++ b/drivers/tty/serial/atmel_serial.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * include/linux/atmel_serial.h
+  *
+diff --git a/drivers/tty/serial/bcm63xx_uart.c b/drivers/tty/serial/bcm63xx_uart.c
+index 8c48c3784831..474652d26c71 100644
+--- a/drivers/tty/serial/bcm63xx_uart.c
++++ b/drivers/tty/serial/bcm63xx_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * This file is subject to the terms and conditions of the GNU General Public
+  * License.  See the file "COPYING" in the main directory of this archive
+diff --git a/drivers/tty/serial/bfin_sport_uart.c b/drivers/tty/serial/bfin_sport_uart.c
+index 6b03fb12cd19..abd0f6cf1bba 100644
+--- a/drivers/tty/serial/bfin_sport_uart.c
++++ b/drivers/tty/serial/bfin_sport_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Blackfin On-Chip Sport Emulated UART Driver
+  *
+diff --git a/drivers/tty/serial/bfin_sport_uart.h b/drivers/tty/serial/bfin_sport_uart.h
+index e4510ea135ce..6d9237bb7192 100644
+--- a/drivers/tty/serial/bfin_sport_uart.h
++++ b/drivers/tty/serial/bfin_sport_uart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Blackfin On-Chip Sport Emulated UART Driver
+  *
+diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
+index 293ecbb00684..7fc639c47534 100644
+--- a/drivers/tty/serial/bfin_uart.c
++++ b/drivers/tty/serial/bfin_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Blackfin On-Chip Serial Driver
+  *
+diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
+index ac1328629baa..64d58f2765cc 100644
+--- a/drivers/tty/serial/clps711x.c
++++ b/drivers/tty/serial/clps711x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for CLPS711x serial ports
+  *
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart.h b/drivers/tty/serial/cpm_uart/cpm_uart.h
+index 0ad027b95873..79f1d1128c5a 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart.h
++++ b/drivers/tty/serial/cpm_uart/cpm_uart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Driver for CPM (SCC/SMC) serial ports
+  *
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+index 9ac142cfc1f1..a98d3ab37fac 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for CPM (SCC/SMC) serial ports; core driver
+  *
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
+index 6d3b22e93246..31e952fd98d0 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
+  *
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
+index f46d2ca87209..84f7c8d32ab3 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
+  *
+diff --git a/drivers/tty/serial/digicolor-usart.c b/drivers/tty/serial/digicolor-usart.c
+index 02ad6953b167..c38a16381ff3 100644
+--- a/drivers/tty/serial/digicolor-usart.c
++++ b/drivers/tty/serial/digicolor-usart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for Conexant Digicolor serial ports (USART)
+  *
+diff --git a/drivers/tty/serial/dz.c b/drivers/tty/serial/dz.c
+index ff465ff43577..7b57e840e255 100644
+--- a/drivers/tty/serial/dz.c
++++ b/drivers/tty/serial/dz.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * dz.c: Serial port driver for DECstations equipped
+  *       with the DZ chipset.
+diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
+index 6bbeb699777c..84780c17a889 100644
+--- a/drivers/tty/serial/earlycon-arm-semihost.c
++++ b/drivers/tty/serial/earlycon-arm-semihost.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2012 ARM Ltd.
+  * Author: Marc Zyngier <marc.zyngier@arm.com>
+diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
+index ac667b47f199..57144c78518f 100644
+--- a/drivers/tty/serial/earlycon.c
++++ b/drivers/tty/serial/earlycon.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Linaro Ltd.
+  * Author: Rob Herring <robh@kernel.org>
+diff --git a/drivers/tty/serial/efm32-uart.c b/drivers/tty/serial/efm32-uart.c
+index 9fff25be87f9..d6b5e5463746 100644
+--- a/drivers/tty/serial/efm32-uart.c
++++ b/drivers/tty/serial/efm32-uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+ #define SUPPORT_SYSRQ
+ #endif
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index 7a3db9378fa3..d0c072d5c709 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Freescale lpuart serial port driver
+  *
+diff --git a/drivers/tty/serial/icom.c b/drivers/tty/serial/icom.c
+index fe92d74f4ea5..a8fd690fbf29 100644
+--- a/drivers/tty/serial/icom.c
++++ b/drivers/tty/serial/icom.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+   * icom.c
+   *
+diff --git a/drivers/tty/serial/icom.h b/drivers/tty/serial/icom.h
+index c8029e0025c9..da6a38967d2f 100644
+--- a/drivers/tty/serial/icom.h
++++ b/drivers/tty/serial/icom.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * icom.h
+  *
+diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
+index f190a84a0246..fe670f9fcbd9 100644
+--- a/drivers/tty/serial/ifx6x60.c
++++ b/drivers/tty/serial/ifx6x60.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /****************************************************************************
+  *
+  * Driver for the IFX 6x60 spi modem.
+diff --git a/drivers/tty/serial/ifx6x60.h b/drivers/tty/serial/ifx6x60.h
+index 4fbddc297839..a5346e7672c0 100644
+--- a/drivers/tty/serial/ifx6x60.h
++++ b/drivers/tty/serial/ifx6x60.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /****************************************************************************
+  *
+  * Driver for the IFX spi modem.
+diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
+index 8deaf2ad8b34..13085ac31f05 100644
+--- a/drivers/tty/serial/imx.c
++++ b/drivers/tty/serial/imx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Motorola/Freescale IMX serial ports
+  *
+diff --git a/drivers/tty/serial/ioc3_serial.c b/drivers/tty/serial/ioc3_serial.c
+index 906ee770ff4a..fcc4bc85dab4 100644
+--- a/drivers/tty/serial/ioc3_serial.c
++++ b/drivers/tty/serial/ioc3_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * This file is subject to the terms and conditions of the GNU General Public
+  * License.  See the file "COPYING" in the main directory of this archive
+diff --git a/drivers/tty/serial/ioc4_serial.c b/drivers/tty/serial/ioc4_serial.c
+index 43d7d32eb150..8804faad5294 100644
+--- a/drivers/tty/serial/ioc4_serial.c
++++ b/drivers/tty/serial/ioc4_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * This file is subject to the terms and conditions of the GNU General Public
+  * License.  See the file "COPYING" in the main directory of this archive
+diff --git a/drivers/tty/serial/ip22zilog.c b/drivers/tty/serial/ip22zilog.c
+index 7ddddb4c3844..8c810733df3d 100644
+--- a/drivers/tty/serial/ip22zilog.c
++++ b/drivers/tty/serial/ip22zilog.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for Zilog serial chips found on SGI workstations and
+  * servers.  This driver could actually be made more generic.
+diff --git a/drivers/tty/serial/jsm/jsm.h b/drivers/tty/serial/jsm/jsm.h
+index 0b79b87df47d..588080b05b07 100644
+--- a/drivers/tty/serial/jsm/jsm.h
++++ b/drivers/tty/serial/jsm/jsm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  * Copyright 2003 Digi International (www.digi.com)
+  *
+diff --git a/drivers/tty/serial/jsm/jsm_cls.c b/drivers/tty/serial/jsm/jsm_cls.c
+index 4eb12a9cae76..74793234e002 100644
+--- a/drivers/tty/serial/jsm/jsm_cls.c
++++ b/drivers/tty/serial/jsm/jsm_cls.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2003 Digi International (www.digi.com)
+  *	Scott H Kilau <Scott_Kilau at digi dot com>
+diff --git a/drivers/tty/serial/jsm/jsm_driver.c b/drivers/tty/serial/jsm/jsm_driver.c
+index 102d499814ac..0ede8673f5be 100644
+--- a/drivers/tty/serial/jsm/jsm_driver.c
++++ b/drivers/tty/serial/jsm/jsm_driver.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  * Copyright 2003 Digi International (www.digi.com)
+  *
+diff --git a/drivers/tty/serial/jsm/jsm_neo.c b/drivers/tty/serial/jsm/jsm_neo.c
+index c6fdd6369534..b28a0a478d64 100644
+--- a/drivers/tty/serial/jsm/jsm_neo.c
++++ b/drivers/tty/serial/jsm/jsm_neo.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  * Copyright 2003 Digi International (www.digi.com)
+  *
+diff --git a/drivers/tty/serial/jsm/jsm_tty.c b/drivers/tty/serial/jsm/jsm_tty.c
+index ec7d8383900f..7753d5b364b5 100644
+--- a/drivers/tty/serial/jsm/jsm_tty.c
++++ b/drivers/tty/serial/jsm/jsm_tty.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  * Copyright 2003 Digi International (www.digi.com)
+  *
+diff --git a/drivers/tty/serial/kgdb_nmi.c b/drivers/tty/serial/kgdb_nmi.c
+index 117df151627d..b908d4a24de5 100644
+--- a/drivers/tty/serial/kgdb_nmi.c
++++ b/drivers/tty/serial/kgdb_nmi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * KGDB NMI serial console
+  *
+diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c
+index a260cde743e2..62d162ae7610 100644
+--- a/drivers/tty/serial/kgdboc.c
++++ b/drivers/tty/serial/kgdboc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Based on the same principle as kgdboe using the NETPOLL api, this
+  * driver uses a console polling api to implement a gdb serial inteface
+diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
+index 22df94f107e5..868abff3db32 100644
+--- a/drivers/tty/serial/lantiq.c
++++ b/drivers/tty/serial/lantiq.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c
+index cea57ff32c33..8b58256ec776 100644
+--- a/drivers/tty/serial/lpc32xx_hs.c
++++ b/drivers/tty/serial/lpc32xx_hs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * High Speed Serial Ports on NXP LPC32xx SoC
+  *
+diff --git a/drivers/tty/serial/m32r_sio.c b/drivers/tty/serial/m32r_sio.c
+index 5b3bd9511993..1e44f2e6c5f7 100644
+--- a/drivers/tty/serial/m32r_sio.c
++++ b/drivers/tty/serial/m32r_sio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  m32r_sio.c
+  *
+diff --git a/drivers/tty/serial/m32r_sio_reg.h b/drivers/tty/serial/m32r_sio_reg.h
+index 4671473793e3..0fd9727edec3 100644
+--- a/drivers/tty/serial/m32r_sio_reg.h
++++ b/drivers/tty/serial/m32r_sio_reg.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * m32r_sio_reg.h
+  *
+diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c
+index ace82645b123..d5e4a5336095 100644
+--- a/drivers/tty/serial/max3100.c
++++ b/drivers/tty/serial/max3100.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *
+  *  Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
+diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
+index 9dfedbe6c071..bd626ec325d5 100644
+--- a/drivers/tty/serial/max310x.c
++++ b/drivers/tty/serial/max310x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
+  *
+diff --git a/drivers/tty/serial/mcf.c b/drivers/tty/serial/mcf.c
+index 02eb32217685..9c779768bd16 100644
+--- a/drivers/tty/serial/mcf.c
++++ b/drivers/tty/serial/mcf.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /****************************************************************************/
+ 
+ /*
+diff --git a/drivers/tty/serial/men_z135_uart.c b/drivers/tty/serial/men_z135_uart.c
+index e72ea61c70db..9387b2c745a0 100644
+--- a/drivers/tty/serial/men_z135_uart.c
++++ b/drivers/tty/serial/men_z135_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MEN 16z135 High Speed UART
+  *
+diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
+index 07c0f98be3ac..d4875ea65a53 100644
+--- a/drivers/tty/serial/meson_uart.c
++++ b/drivers/tty/serial/meson_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Based on meson_uart.c, by AMLOGIC, INC.
+  *
+diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
+index 791c4c74f6d6..1c1febdf60ce 100644
+--- a/drivers/tty/serial/mpc52xx_uart.c
++++ b/drivers/tty/serial/mpc52xx_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
+  *
+diff --git a/drivers/tty/serial/mps2-uart.c b/drivers/tty/serial/mps2-uart.c
+index 492ec4b375a0..5d789b584bc5 100644
+--- a/drivers/tty/serial/mps2-uart.c
++++ b/drivers/tty/serial/mps2-uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MPS2 UART driver
+  *
+diff --git a/drivers/tty/serial/mpsc.c b/drivers/tty/serial/mpsc.c
+index 67ffecc50e42..21b28d8e3c02 100644
+--- a/drivers/tty/serial/mpsc.c
++++ b/drivers/tty/serial/mpsc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
+  * GT64260, MV64340, MV64360, GT96100, ... ).
+diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
+index 1db79ee8a886..76649fea8f6f 100644
+--- a/drivers/tty/serial/msm_serial.c
++++ b/drivers/tty/serial/msm_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for msm7k serial device and console
+  *
+diff --git a/drivers/tty/serial/mux.c b/drivers/tty/serial/mux.c
+index 2bff69e70e4b..44f503ea54d2 100644
+--- a/drivers/tty/serial/mux.c
++++ b/drivers/tty/serial/mux.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+ ** mux.c:
+ **	serial driver for the Mux console found in some PA-RISC servers.
+diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
+index 45b57c294d13..09e7da6eab97 100644
+--- a/drivers/tty/serial/mvebu-uart.c
++++ b/drivers/tty/serial/mvebu-uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+ * ***************************************************************************
+ * Marvell Armada-3700 Serial Driver
+diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
+index 673c8fd7e34f..588e08274233 100644
+--- a/drivers/tty/serial/mxs-auart.c
++++ b/drivers/tty/serial/mxs-auart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Application UART driver for:
+  *	Freescale STMP37XX/STMP378X
+diff --git a/drivers/tty/serial/netx-serial.c b/drivers/tty/serial/netx-serial.c
+index 207a0a032ed1..4201938e8aa3 100644
+--- a/drivers/tty/serial/netx-serial.c
++++ b/drivers/tty/serial/netx-serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+  *
+diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
+index 26a22b100df1..f25544e8228d 100644
+--- a/drivers/tty/serial/omap-serial.c
++++ b/drivers/tty/serial/omap-serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for OMAP-UART controller.
+  * Based on drivers/serial/8250.c
+diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
+index b9c859365334..93fa3095a775 100644
+--- a/drivers/tty/serial/owl-uart.c
++++ b/drivers/tty/serial/owl-uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Actions Semi Owl family serial console
+  *
+diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
+index d9123f995705..e2c04a3334da 100644
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+  *
+diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
+index 00a33eb859d3..9f55c30d1aa6 100644
+--- a/drivers/tty/serial/pic32_uart.c
++++ b/drivers/tty/serial/pic32_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * PIC32 Integrated Serial Driver.
+  *
+diff --git a/drivers/tty/serial/pic32_uart.h b/drivers/tty/serial/pic32_uart.h
+index ec379da55ebb..43dc168dffd7 100644
+--- a/drivers/tty/serial/pic32_uart.h
++++ b/drivers/tty/serial/pic32_uart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * PIC32 Integrated Serial Driver.
+  *
+diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
+index 6ccdd018fb45..3afba70022b4 100644
+--- a/drivers/tty/serial/pmac_zilog.c
++++ b/drivers/tty/serial/pmac_zilog.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for PowerMac Z85c30 based ESCC cell found in the
+  * "macio" ASICs of various PowerMac models
+diff --git a/drivers/tty/serial/pnx8xxx_uart.c b/drivers/tty/serial/pnx8xxx_uart.c
+index dab2668d3879..a61fb04cca24 100644
+--- a/drivers/tty/serial/pnx8xxx_uart.c
++++ b/drivers/tty/serial/pnx8xxx_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * UART driver for PNX8XXX SoCs
+  *
+diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
+index 905631df1f8b..dd82ecb7c25d 100644
+--- a/drivers/tty/serial/pxa.c
++++ b/drivers/tty/serial/pxa.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Based on drivers/serial/8250.c by Russell King.
+  *
+diff --git a/drivers/tty/serial/rp2.c b/drivers/tty/serial/rp2.c
+index 056f91b3a4ca..2108bf34ff90 100644
+--- a/drivers/tty/serial/rp2.c
++++ b/drivers/tty/serial/rp2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
+  *
+diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
+index fd3d1329d48c..125558fa2ce9 100644
+--- a/drivers/tty/serial/sa1100.c
++++ b/drivers/tty/serial/sa1100.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for SA11x0 serial ports
+  *
+diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
+index 57baa84ccf86..9a30b12ac352 100644
+--- a/drivers/tty/serial/samsung.c
++++ b/drivers/tty/serial/samsung.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver core for Samsung SoC onboard UARTs.
+  *
+diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
+index 965199b6c16f..b0461c096d0a 100644
+--- a/drivers/tty/serial/samsung.h
++++ b/drivers/tty/serial/samsung.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #ifndef __SAMSUNG_H
+ #define __SAMSUNG_H
+ 
+diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c
+index 041625cc24bb..f3d5b4ebb9d5 100644
+--- a/drivers/tty/serial/sb1250-duart.c
++++ b/drivers/tty/serial/sb1250-duart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	Support for the asynchronous serial interface (DUART) included
+  *	in the BCM1250 and derived System-On-a-Chip (SOC) devices.
+diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
+index ca54ce074a5f..f1e216e714ee 100644
+--- a/drivers/tty/serial/sc16is7xx.c
++++ b/drivers/tty/serial/sc16is7xx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
+  * Author: Jon Ringle <jringle@gridpoint.com>
+diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c
+index b9c7a904c1ea..8c580d7dd2fe 100644
+--- a/drivers/tty/serial/sccnxp.c
++++ b/drivers/tty/serial/sccnxp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  NXP (Philips) SCC+++(SCN+++) serial driver
+  *
+diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
+index cf9b736f26f8..fae65e76a9f3 100644
+--- a/drivers/tty/serial/serial-tegra.c
++++ b/drivers/tty/serial/serial-tegra.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * serial_tegra.c
+  *
+diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
+index 6db8844ef3ec..1cd0cb292ff9 100644
+--- a/drivers/tty/serial/serial_core.c
++++ b/drivers/tty/serial/serial_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver core for serial ports
+  *
+diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
+index 57f152394af5..9a894e899876 100644
+--- a/drivers/tty/serial/serial_ks8695.c
++++ b/drivers/tty/serial/serial_ks8695.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for KS8695 serial ports
+  *
+diff --git a/drivers/tty/serial/serial_mctrl_gpio.c b/drivers/tty/serial/serial_mctrl_gpio.c
+index d2da6aa7f27d..302dda18fcbd 100644
+--- a/drivers/tty/serial/serial_mctrl_gpio.c
++++ b/drivers/tty/serial/serial_mctrl_gpio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Helpers for controlling modem lines via GPIO
+  *
+diff --git a/drivers/tty/serial/serial_mctrl_gpio.h b/drivers/tty/serial/serial_mctrl_gpio.h
+index fa000bcff217..219eba0223bb 100644
+--- a/drivers/tty/serial/serial_mctrl_gpio.h
++++ b/drivers/tty/serial/serial_mctrl_gpio.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Helpers for controlling modem lines via GPIO
+  *
+diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
+index f80fead6c5fc..256c61d1c6a6 100644
+--- a/drivers/tty/serial/serial_txx9.c
++++ b/drivers/tty/serial/serial_txx9.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Derived from many drivers using generic_serial interface,
+  * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 8bc8fe2b75f7..eae806bd3555 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
+  *
+diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
+index 684cb8dd8050..3e3ea07c54c0 100644
+--- a/drivers/tty/serial/sirfsoc_uart.c
++++ b/drivers/tty/serial/sirfsoc_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for CSR SiRFprimaII onboard UARTs.
+  *
+diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h
+index 43756bd9111c..6d6251526631 100644
+--- a/drivers/tty/serial/sirfsoc_uart.h
++++ b/drivers/tty/serial/sirfsoc_uart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Drivers for CSR SiRFprimaII onboard UARTs.
+  *
+diff --git a/drivers/tty/serial/sprd_serial.c b/drivers/tty/serial/sprd_serial.c
+index e902494ebbd5..a06d50f52ea8 100644
+--- a/drivers/tty/serial/sprd_serial.c
++++ b/drivers/tty/serial/sprd_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
+  *
+diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c
+index b313a792b149..1f51eef68c85 100644
+--- a/drivers/tty/serial/st-asc.c
++++ b/drivers/tty/serial/st-asc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * st-asc.c: ST Asynchronous serial controller (ASC) driver
+  *
+diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
+index 03a583264d9e..007ad0274ed0 100644
+--- a/drivers/tty/serial/stm32-usart.c
++++ b/drivers/tty/serial/stm32-usart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) Maxime Coquelin 2015
+  * Copyright (C) STMicroelectronics SA 2017
+diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
+index ffc0c5285e51..174be6141cef 100644
+--- a/drivers/tty/serial/stm32-usart.h
++++ b/drivers/tty/serial/stm32-usart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) Maxime Coquelin 2015
+  * Copyright (C) STMicroelectronics SA 2017
+diff --git a/drivers/tty/serial/suncore.c b/drivers/tty/serial/suncore.c
+index 127472bd6a7c..70a4ea4eaa6e 100644
+--- a/drivers/tty/serial/suncore.c
++++ b/drivers/tty/serial/suncore.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* suncore.c
+  *
+  * Common SUN serial routines.  Based entirely
+diff --git a/drivers/tty/serial/sunhv.c b/drivers/tty/serial/sunhv.c
+index 46e46894e918..63e34d868de8 100644
+--- a/drivers/tty/serial/sunhv.c
++++ b/drivers/tty/serial/sunhv.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* sunhv.c: Serial driver for SUN4V hypervisor console.
+  *
+  * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
+diff --git a/drivers/tty/serial/sunsab.c b/drivers/tty/serial/sunsab.c
+index 653a076d89d3..b93d0225f8c9 100644
+--- a/drivers/tty/serial/sunsab.c
++++ b/drivers/tty/serial/sunsab.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
+  *
+  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
+diff --git a/drivers/tty/serial/sunsu.c b/drivers/tty/serial/sunsu.c
+index 95d34d7565c9..6cf3e9b0728f 100644
+--- a/drivers/tty/serial/sunsu.c
++++ b/drivers/tty/serial/sunsu.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
+  *
+diff --git a/drivers/tty/serial/sunzilog.c b/drivers/tty/serial/sunzilog.c
+index 252cea49c068..bc7af8b08a72 100644
+--- a/drivers/tty/serial/sunzilog.c
++++ b/drivers/tty/serial/sunzilog.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* sunzilog.c: Zilog serial driver for Sparc systems.
+  *
+  * Driver for Zilog serial chips found on Sun workstations and
+diff --git a/drivers/tty/serial/tilegx.c b/drivers/tty/serial/tilegx.c
+index 453215f5420d..311eea391f57 100644
+--- a/drivers/tty/serial/tilegx.c
++++ b/drivers/tty/serial/tilegx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2013 Tilera Corporation. All Rights Reserved.
+  *
+diff --git a/drivers/tty/serial/timbuart.c b/drivers/tty/serial/timbuart.c
+index 5da7fe40e391..cdbc23fc85e3 100644
+--- a/drivers/tty/serial/timbuart.c
++++ b/drivers/tty/serial/timbuart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * timbuart.c timberdale FPGA UART driver
+  * Copyright (c) 2009 Intel Corporation
+diff --git a/drivers/tty/serial/timbuart.h b/drivers/tty/serial/timbuart.h
+index 7e566766bc43..6c642e99abcf 100644
+--- a/drivers/tty/serial/timbuart.h
++++ b/drivers/tty/serial/timbuart.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * timbuart.c timberdale FPGA GPIO driver
+  * Copyright (c) 2009 Intel Corporation
+diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
+index c9b8d702dadc..5bf19bca480d 100644
+--- a/drivers/tty/serial/uartlite.c
++++ b/drivers/tty/serial/uartlite.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * uartlite.c: Serial driver for Xilinx uartlite serial controller
+  *
+diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
+index 55b702775786..b01772712c1d 100644
+--- a/drivers/tty/serial/ucc_uart.c
++++ b/drivers/tty/serial/ucc_uart.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Freescale QUICC Engine UART device driver
+  *
+diff --git a/drivers/tty/serial/vr41xx_siu.c b/drivers/tty/serial/vr41xx_siu.c
+index 439057e8107a..fc100ea7eded 100644
+--- a/drivers/tty/serial/vr41xx_siu.c
++++ b/drivers/tty/serial/vr41xx_siu.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  Driver for NEC VR4100 series Serial Interface Unit.
+  *
+diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
+index 435a6f3260be..334f0f4e20f5 100644
+--- a/drivers/tty/serial/vt8500_serial.c
++++ b/drivers/tty/serial/vt8500_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+  *
+diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
+index 21c35ad72b99..09926355b7f2 100644
+--- a/drivers/tty/serial/xilinx_uartps.c
++++ b/drivers/tty/serial/xilinx_uartps.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Cadence UART driver (found in Xilinx Zynq)
+  *
+diff --git a/drivers/tty/serial/zs.c b/drivers/tty/serial/zs.c
+index d32bd499d684..b03d3e458ea2 100644
+--- a/drivers/tty/serial/zs.c
++++ b/drivers/tty/serial/zs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * zs.c: Serial port driver for IOASIC DECstations.
+  *
+diff --git a/drivers/tty/synclink.c b/drivers/tty/synclink.c
+index 3be981101297..5c930835e8d1 100644
+--- a/drivers/tty/synclink.c
++++ b/drivers/tty/synclink.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
+  *
+diff --git a/drivers/tty/synclink_gt.c b/drivers/tty/synclink_gt.c
+index 636b8ae29b46..da9f2e56ee50 100644
+--- a/drivers/tty/synclink_gt.c
++++ b/drivers/tty/synclink_gt.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Device driver for Microgate SyncLink GT serial adapters.
+  *
+diff --git a/drivers/tty/synclinkmp.c b/drivers/tty/synclinkmp.c
+index 4fed9e7b281f..4cc73be504e3 100644
+--- a/drivers/tty/synclinkmp.c
++++ b/drivers/tty/synclinkmp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
+  *
+diff --git a/drivers/tty/tty_audit.c b/drivers/tty/tty_audit.c
+index df2d735338e2..30b92c461dea 100644
+--- a/drivers/tty/tty_audit.c
++++ b/drivers/tty/tty_audit.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Creating audit events from TTY input.
+  *
+diff --git a/drivers/tty/tty_baudrate.c b/drivers/tty/tty_baudrate.c
+index 5c33fd25676d..6ff8cdfc9d2a 100644
+--- a/drivers/tty/tty_baudrate.c
++++ b/drivers/tty/tty_baudrate.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
+  */
+diff --git a/drivers/tty/tty_buffer.c b/drivers/tty/tty_buffer.c
+index 677fa99b7747..c996b6859c5e 100644
+--- a/drivers/tty/tty_buffer.c
++++ b/drivers/tty/tty_buffer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Tty buffer allocation management
+  */
+diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
+index 562d31073f9a..495686cd0086 100644
+--- a/drivers/tty/tty_io.c
++++ b/drivers/tty/tty_io.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 1991, 1992  Linus Torvalds
+  */
+diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c
+index efa96e6c4c1b..d9b561d89432 100644
+--- a/drivers/tty/tty_ioctl.c
++++ b/drivers/tty/tty_ioctl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
+  *
+diff --git a/drivers/tty/tty_jobctrl.c b/drivers/tty/tty_jobctrl.c
+index e7032309ee87..c4ecd66fafef 100644
+--- a/drivers/tty/tty_jobctrl.c
++++ b/drivers/tty/tty_jobctrl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 1991, 1992  Linus Torvalds
+  */
+diff --git a/drivers/tty/tty_ldisc.c b/drivers/tty/tty_ldisc.c
+index ca656ef8de64..0fd18f5fa67d 100644
+--- a/drivers/tty/tty_ldisc.c
++++ b/drivers/tty/tty_ldisc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/types.h>
+ #include <linux/errno.h>
+ #include <linux/kmod.h>
+diff --git a/drivers/tty/tty_ldsem.c b/drivers/tty/tty_ldsem.c
+index 52b7baef4f7a..3b403406d6f3 100644
+--- a/drivers/tty/tty_ldsem.c
++++ b/drivers/tty/tty_ldsem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Ldisc rw semaphore
+  *
+diff --git a/drivers/tty/tty_port.c b/drivers/tty/tty_port.c
+index 6b137194069f..52be647c3a74 100644
+--- a/drivers/tty/tty_port.c
++++ b/drivers/tty/tty_port.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Tty port functions
+  */
+diff --git a/drivers/tty/vt/consolemap.c b/drivers/tty/vt/consolemap.c
+index a5f88cf0f61d..722a6690c70d 100644
+--- a/drivers/tty/vt/consolemap.c
++++ b/drivers/tty/vt/consolemap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * consolemap.c
+  *
+diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
+index f4166263bb3a..749e5a5521e6 100644
+--- a/drivers/tty/vt/keyboard.c
++++ b/drivers/tty/vt/keyboard.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Written for linux by Johan Myreen as a translation from
+  * the assembly version by Linus (with diacriticals added)
+diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
+index e77421e7bf46..984a56b697db 100644
+--- a/drivers/tty/vt/vt.c
++++ b/drivers/tty/vt/vt.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Copyright (C) 1991, 1992  Linus Torvalds
+  */
+-- 
+2.19.0
+
diff --git a/patches/0167-tty-serial-Remove-redundant-license-text.patch b/patches/0167-tty-serial-Remove-redundant-license-text.patch
new file mode 100644
index 00000000000000..d548ffd9cb2137
--- /dev/null
+++ b/patches/0167-tty-serial-Remove-redundant-license-text.patch
@@ -0,0 +1,2348 @@
+From 7ac4fed00d0879a50ab71c1607f830d61113dccd Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 18:11:52 +0100
+Subject: [PATCH 0167/1795] tty: serial: Remove redundant license text
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Now that the SPDX tag is in all tty files, that identifies the license
+in a specific and legally-defined manner.  So the extra GPL text wording
+can be removed as it is no longer needed at all.
+
+This is done on a quest to remove the 700+ different ways that files in
+the kernel describe the GPL license text.  And there's unneeded stuff
+like the address (sometimes incorrect) for the FSF which is never
+needed.
+
+No copyright headers or other non-license-description text was removed.
+
+Cc: Jiri Slaby <jslaby@suse.com>
+Cc: Eric Anholt <eric@anholt.net>
+Cc: Stefan Wahren <stefan.wahren@i2se.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Ray Jui <rjui@broadcom.com>
+Cc: Scott Branden <sbranden@broadcom.com>
+Cc: bcm-kernel-feedback-list@broadcom.com
+Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
+Cc: Helge Deller <deller@gmx.de>
+Cc: Joachim Eastwood <manabian@gmail.com>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Tobias Klauser <tklauser@distanz.ch>
+Cc: Russell King <linux@armlinux.org.uk>
+Cc: Vineet Gupta <vgupta@synopsys.com>
+Cc: Richard Genoud <richard.genoud@gmail.com>
+Cc: Alexander Shiyan <shc_work@mail.ru>
+Cc: Baruch Siach <baruch@tkos.co.il>
+Cc: Pat Gefre <pfg@sgi.com>
+Cc: "Guilherme G. Piccoli" <gpiccoli@linux.vnet.ibm.com>
+Cc: Jason Wessel <jason.wessel@windriver.com>
+Cc: Vladimir Zapolskiy <vz@mleia.com>
+Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
+Cc: Carlo Caione <carlo@caione.org>
+Cc: Kevin Hilman <khilman@baylibre.com>
+Cc: Liviu Dudau <liviu.dudau@arm.com>
+Cc: Sudeep Holla <sudeep.holla@arm.com>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Andy Gross <andy.gross@linaro.org>
+Cc: David Brown <david.brown@linaro.org>
+Cc: "Andreas Färber" <afaerber@suse.de>
+Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Cc: Paul Mackerras <paulus@samba.org>
+Cc: Michael Ellerman <mpe@ellerman.id.au>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Cc: Laxman Dewangan <ldewangan@nvidia.com>
+Cc: Thierry Reding <thierry.reding@gmail.com>
+Cc: Jonathan Hunter <jonathanh@nvidia.com>
+Cc: Barry Song <baohua@kernel.org>
+Cc: Patrice Chotard <patrice.chotard@st.com>
+Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+Cc: Alexandre Torgue <alexandre.torgue@st.com>
+Cc: Chris Metcalf <cmetcalf@mellanox.com>
+Cc: Peter Korsgaard <jacmet@sunsite.dk>
+Cc: Timur Tabi <timur@tabi.org>
+Cc: Tony Prisk <linux@prisktech.co.nz>
+Cc: Michal Simek <michal.simek@xilinx.com>
+Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 4793f2ebff1c890386a514998606205a2948011c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/8250/8250.h               |  5 -----
+ drivers/tty/serial/8250/8250_accent.c        |  4 ----
+ drivers/tty/serial/8250/8250_acorn.c         |  4 ----
+ drivers/tty/serial/8250/8250_aspeed_vuart.c  |  5 -----
+ drivers/tty/serial/8250/8250_bcm2835aux.c    |  5 -----
+ drivers/tty/serial/8250/8250_boca.c          |  4 ----
+ drivers/tty/serial/8250/8250_core.c          |  5 -----
+ drivers/tty/serial/8250/8250_dma.c           |  5 -----
+ drivers/tty/serial/8250/8250_dw.c            |  5 -----
+ drivers/tty/serial/8250/8250_early.c         |  4 ----
+ drivers/tty/serial/8250/8250_em.c            | 13 -------------
+ drivers/tty/serial/8250/8250_exar.c          |  4 ----
+ drivers/tty/serial/8250/8250_exar_st16c554.c |  4 ----
+ drivers/tty/serial/8250/8250_fintek.c        |  5 -----
+ drivers/tty/serial/8250/8250_fourport.c      |  4 ----
+ drivers/tty/serial/8250/8250_fsl.c           |  4 ----
+ drivers/tty/serial/8250/8250_gsc.c           |  5 -----
+ drivers/tty/serial/8250/8250_hub6.c          |  4 ----
+ drivers/tty/serial/8250/8250_ingenic.c       |  9 ---------
+ drivers/tty/serial/8250/8250_lpc18xx.c       |  5 -----
+ drivers/tty/serial/8250/8250_lpss.c          |  4 ----
+ drivers/tty/serial/8250/8250_mid.c           |  4 ----
+ drivers/tty/serial/8250/8250_moxa.c          |  4 ----
+ drivers/tty/serial/8250/8250_mtk.c           | 10 ----------
+ drivers/tty/serial/8250/8250_of.c            |  6 ------
+ drivers/tty/serial/8250/8250_pci.c           |  4 ----
+ drivers/tty/serial/8250/8250_pnp.c           |  4 ----
+ drivers/tty/serial/8250/8250_port.c          |  5 -----
+ drivers/tty/serial/8250/8250_pxa.c           |  6 ------
+ drivers/tty/serial/8250/8250_uniphier.c      | 10 ----------
+ drivers/tty/serial/altera_jtaguart.c         |  5 -----
+ drivers/tty/serial/altera_uart.c             |  5 -----
+ drivers/tty/serial/amba-pl010.c              | 14 --------------
+ drivers/tty/serial/amba-pl011.c              | 14 --------------
+ drivers/tty/serial/ar933x_uart.c             |  4 ----
+ drivers/tty/serial/arc_uart.c                |  4 ----
+ drivers/tty/serial/atmel_serial.c            | 15 ---------------
+ drivers/tty/serial/atmel_serial.h            |  5 -----
+ drivers/tty/serial/bcm63xx_uart.c            |  4 ----
+ drivers/tty/serial/bfin_sport_uart.c         |  2 --
+ drivers/tty/serial/bfin_sport_uart.h         |  2 --
+ drivers/tty/serial/bfin_uart.c               |  2 --
+ drivers/tty/serial/clps711x.c                |  5 -----
+ drivers/tty/serial/cpm_uart/cpm_uart.h       |  5 -----
+ drivers/tty/serial/cpm_uart/cpm_uart_core.c  | 15 ---------------
+ drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c  | 15 ---------------
+ drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c  | 15 ---------------
+ drivers/tty/serial/digicolor-usart.c         |  5 -----
+ drivers/tty/serial/earlycon-arm-semihost.c   | 12 ------------
+ drivers/tty/serial/earlycon.c                |  4 ----
+ drivers/tty/serial/fsl_lpuart.c              |  5 -----
+ drivers/tty/serial/icom.c                    | 15 ---------------
+ drivers/tty/serial/icom.h                    | 14 --------------
+ drivers/tty/serial/ifx6x60.c                 | 14 --------------
+ drivers/tty/serial/ifx6x60.h                 | 17 -----------------
+ drivers/tty/serial/imx.c                     | 10 ----------
+ drivers/tty/serial/ioc3_serial.c             |  4 ----
+ drivers/tty/serial/ioc4_serial.c             |  4 ----
+ drivers/tty/serial/jsm/jsm.h                 | 10 ----------
+ drivers/tty/serial/jsm/jsm_cls.c             | 10 ----------
+ drivers/tty/serial/jsm/jsm_driver.c          | 10 ----------
+ drivers/tty/serial/jsm/jsm_neo.c             | 10 ----------
+ drivers/tty/serial/jsm/jsm_tty.c             | 10 ----------
+ drivers/tty/serial/kgdb_nmi.c                |  4 ----
+ drivers/tty/serial/kgdboc.c                  |  4 ----
+ drivers/tty/serial/lantiq.c                  | 13 -------------
+ drivers/tty/serial/lpc32xx_hs.c              | 10 ----------
+ drivers/tty/serial/m32r_sio.c                |  5 -----
+ drivers/tty/serial/m32r_sio_reg.h            |  3 ---
+ drivers/tty/serial/max3100.c                 |  6 ------
+ drivers/tty/serial/max310x.c                 |  5 -----
+ drivers/tty/serial/mcf.c                     |  5 -----
+ drivers/tty/serial/men_z135_uart.c           |  4 ----
+ drivers/tty/serial/meson_uart.c              | 10 ----------
+ drivers/tty/serial/mpc52xx_uart.c            |  4 ----
+ drivers/tty/serial/mps2-uart.c               |  4 ----
+ drivers/tty/serial/mpsc.c                    |  5 +----
+ drivers/tty/serial/msm_serial.c              |  9 ---------
+ drivers/tty/serial/mux.c                     |  5 -----
+ drivers/tty/serial/mvebu-uart.c              | 12 ------------
+ drivers/tty/serial/mxs-auart.c               |  4 ----
+ drivers/tty/serial/netx-serial.c             | 13 -------------
+ drivers/tty/serial/omap-serial.c             |  5 -----
+ drivers/tty/serial/owl-uart.c                | 13 -------------
+ drivers/tty/serial/pch_uart.c                | 13 -------------
+ drivers/tty/serial/pic32_uart.c              |  2 --
+ drivers/tty/serial/pic32_uart.h              |  2 --
+ drivers/tty/serial/pmac_zilog.c              | 14 --------------
+ drivers/tty/serial/pnx8xxx_uart.c            |  5 -----
+ drivers/tty/serial/pxa.c                     |  5 -----
+ drivers/tty/serial/rp2.c                     |  4 ----
+ drivers/tty/serial/sa1100.c                  | 14 --------------
+ drivers/tty/serial/samsung.c                 |  4 ----
+ drivers/tty/serial/samsung.h                 |  4 ----
+ drivers/tty/serial/sb1250-duart.c            |  5 -----
+ drivers/tty/serial/sc16is7xx.c               |  6 ------
+ drivers/tty/serial/sccnxp.c                  |  5 -----
+ drivers/tty/serial/serial-tegra.c            | 12 ------------
+ drivers/tty/serial/serial_core.c             | 14 --------------
+ drivers/tty/serial/serial_ks8695.c           |  6 ------
+ drivers/tty/serial/serial_mctrl_gpio.c       | 10 ----------
+ drivers/tty/serial/serial_mctrl_gpio.h       | 11 -----------
+ drivers/tty/serial/serial_txx9.c             |  4 ----
+ drivers/tty/serial/sh-sci.c                  |  4 ----
+ drivers/tty/serial/sirfsoc_uart.c            |  2 --
+ drivers/tty/serial/sirfsoc_uart.h            |  2 --
+ drivers/tty/serial/sn_console.c              | 19 -------------------
+ drivers/tty/serial/sprd_serial.c             |  9 ---------
+ drivers/tty/serial/st-asc.c                  |  6 ------
+ drivers/tty/serial/stm32-usart.c             |  1 -
+ drivers/tty/serial/stm32-usart.h             |  1 -
+ drivers/tty/serial/tilegx.c                  | 10 ----------
+ drivers/tty/serial/timbuart.c                | 13 -------------
+ drivers/tty/serial/timbuart.h                | 13 -------------
+ drivers/tty/serial/uartlite.c                |  4 ----
+ drivers/tty/serial/ucc_uart.c                |  5 +----
+ drivers/tty/serial/vr41xx_siu.c              | 14 --------------
+ drivers/tty/serial/vt8500_serial.c           |  9 ---------
+ drivers/tty/serial/xilinx_uartps.c           |  6 ------
+ 119 files changed, 2 insertions(+), 844 deletions(-)
+
+diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
+index 36e9ae190fc0..ebfb0bd5bef5 100644
+--- a/drivers/tty/serial/8250/8250.h
++++ b/drivers/tty/serial/8250/8250.h
+@@ -5,11 +5,6 @@
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+  *  Copyright (C) 2001 Russell King.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/serial_8250.h>
+diff --git a/drivers/tty/serial/8250/8250_accent.c b/drivers/tty/serial/8250/8250_accent.c
+index 2c11bc1f49c2..1691f1a57f89 100644
+--- a/drivers/tty/serial/8250/8250_accent.c
++++ b/drivers/tty/serial/8250/8250_accent.c
+@@ -2,10 +2,6 @@
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/init.h>
+diff --git a/drivers/tty/serial/8250/8250_acorn.c b/drivers/tty/serial/8250/8250_acorn.c
+index 5395343fcf15..758c4aa203ab 100644
+--- a/drivers/tty/serial/8250/8250_acorn.c
++++ b/drivers/tty/serial/8250/8250_acorn.c
+@@ -3,10 +3,6 @@
+  *  linux/drivers/serial/acorn.c
+  *
+  *  Copyright (C) 1996-2003 Russell King.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/types.h>
+diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
+index c468bcc4e638..74a408d9db24 100644
+--- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
++++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
+@@ -4,11 +4,6 @@
+  *
+  *    Copyright (C) 2016 Jeremy Kerr <jk@ozlabs.org>, IBM Corp.
+  *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
+- *
+- *  This program is free software; you can redistribute it and/or
+- *  modify it under the terms of the GNU General Public License
+- *  as published by the Free Software Foundation; either version
+- *  2 of the License, or (at your option) any later version.
+  */
+ #include <linux/device.h>
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c b/drivers/tty/serial/8250/8250_bcm2835aux.c
+index 242ec1883768..bd53661103eb 100644
+--- a/drivers/tty/serial/8250/8250_bcm2835aux.c
++++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
+@@ -6,11 +6,6 @@
+  *
+  * Based on 8250_lpc18xx.c:
+  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/8250/8250_boca.c b/drivers/tty/serial/8250/8250_boca.c
+index 4123eb887020..a9b97c034653 100644
+--- a/drivers/tty/serial/8250/8250_boca.c
++++ b/drivers/tty/serial/8250/8250_boca.c
+@@ -2,10 +2,6 @@
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/init.h>
+diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
+index 3975281fd66f..1a58e3ff8201 100644
+--- a/drivers/tty/serial/8250/8250_core.c
++++ b/drivers/tty/serial/8250/8250_core.c
+@@ -12,11 +12,6 @@
+  *	      userspace-configurable "phantom" ports
+  *	      "serial8250" platform devices
+  *	      serial8250_register_8250_port() ports
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c
+index fe9259330886..bfa1a857f3ff 100644
+--- a/drivers/tty/serial/8250/8250_dma.c
++++ b/drivers/tty/serial/8250/8250_dma.c
+@@ -3,11 +3,6 @@
+  * 8250_dma.c - DMA Engine API support for 8250.c
+  *
+  * Copyright (C) 2013 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #include <linux/tty.h>
+ #include <linux/tty_flip.h>
+diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
+index e4426c3d78aa..8ea6e33f72d2 100644
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -5,11 +5,6 @@
+  * Copyright 2011 Picochip, Jamie Iles.
+  * Copyright 2013 Intel Corporation
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
+  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
+  * raised, the LCR needs to be rewritten and the uart status register read.
+diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c
+index bfa3dcc238ac..ae6a256524d8 100644
+--- a/drivers/tty/serial/8250/8250_early.c
++++ b/drivers/tty/serial/8250/8250_early.c
+@@ -5,10 +5,6 @@
+  * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
+  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
+  * and on early_printk.c by Andi Kleen.
+  *
+diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c
+index 36355b365c51..f6a86f2bc4e5 100644
+--- a/drivers/tty/serial/8250/8250_em.c
++++ b/drivers/tty/serial/8250/8250_em.c
+@@ -3,19 +3,6 @@
+  * Renesas Emma Mobile 8250 driver
+  *
+  *  Copyright (C) 2012 Magnus Damm
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c
+index 3268d3e27107..a951511f04cf 100644
+--- a/drivers/tty/serial/8250/8250_exar.c
++++ b/drivers/tty/serial/8250/8250_exar.c
+@@ -5,10 +5,6 @@
+  *  Based on drivers/tty/serial/8250/8250_pci.c,
+  *
+  *  Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License.
+  */
+ #include <linux/acpi.h>
+ #include <linux/dmi.h>
+diff --git a/drivers/tty/serial/8250/8250_exar_st16c554.c b/drivers/tty/serial/8250/8250_exar_st16c554.c
+index 0b1318b38cdf..933811ebfaac 100644
+--- a/drivers/tty/serial/8250/8250_exar_st16c554.c
++++ b/drivers/tty/serial/8250/8250_exar_st16c554.c
+@@ -5,10 +5,6 @@
+  *
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/init.h>
+diff --git a/drivers/tty/serial/8250/8250_fintek.c b/drivers/tty/serial/8250/8250_fintek.c
+index 3b2ebff7bef0..3cf93cb1fd20 100644
+--- a/drivers/tty/serial/8250/8250_fintek.c
++++ b/drivers/tty/serial/8250/8250_fintek.c
+@@ -3,11 +3,6 @@
+  *  Probe for F81216A LPC to 4 UART
+  *
+  *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
+- *
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License.
+  */
+ #include <linux/module.h>
+ #include <linux/pci.h>
+diff --git a/drivers/tty/serial/8250/8250_fourport.c b/drivers/tty/serial/8250/8250_fourport.c
+index 1d8e936a18b4..3215b9b7afde 100644
+--- a/drivers/tty/serial/8250/8250_fourport.c
++++ b/drivers/tty/serial/8250/8250_fourport.c
+@@ -2,10 +2,6 @@
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/init.h>
+diff --git a/drivers/tty/serial/8250/8250_fsl.c b/drivers/tty/serial/8250/8250_fsl.c
+index dafe7aa081b3..6640a4c7ddd1 100644
+--- a/drivers/tty/serial/8250/8250_fsl.c
++++ b/drivers/tty/serial/8250/8250_fsl.c
+@@ -7,10 +7,6 @@
+ /*
+  * Freescale 16550 UART "driver", Copyright (C) 2011 Paul Gortmaker.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  * This isn't a full driver; it just provides an alternate IRQ
+  * handler to deal with an errata.  Everything else is just
+  * using the bog standard 8250 support.
+diff --git a/drivers/tty/serial/8250/8250_gsc.c b/drivers/tty/serial/8250/8250_gsc.c
+index 8eea662d6987..0809ae2aa9b1 100644
+--- a/drivers/tty/serial/8250/8250_gsc.c
++++ b/drivers/tty/serial/8250/8250_gsc.c
+@@ -3,11 +3,6 @@
+  *	Serial Device Initialisation for Lasi/Asp/Wax/Dino
+  *
+  *	(c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
+- *
+- *	This program is free software; you can redistribute it and/or modify
+- *	it under the terms of the GNU General Public License as published by
+- *      the Free Software Foundation; either version 2 of the License, or
+- *      (at your option) any later version.
+  */
+ 
+ #include <linux/errno.h>
+diff --git a/drivers/tty/serial/8250/8250_hub6.c b/drivers/tty/serial/8250/8250_hub6.c
+index f75c89ec7ebc..273f59b9bca5 100644
+--- a/drivers/tty/serial/8250/8250_hub6.c
++++ b/drivers/tty/serial/8250/8250_hub6.c
+@@ -2,10 +2,6 @@
+ /*
+  *  Copyright (C) 2005 Russell King.
+  *  Data taken from include/asm-i386/serial.h
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/module.h>
+ #include <linux/init.h>
+diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
+index 5c993a3af653..6af84900870e 100644
+--- a/drivers/tty/serial/8250/8250_ingenic.c
++++ b/drivers/tty/serial/8250/8250_ingenic.c
+@@ -4,15 +4,6 @@
+  * Copyright (C) 2015 Imagination Technologies
+  *
+  * Ingenic SoC UART support
+- *
+- * This program is free software; you can redistribute	 it and/or modify it
+- * under  the terms of	 the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the	License, or (at your
+- * option) any later version.
+- *
+- * You should have received a copy of the  GNU General Public License along
+- * with this program; if not, write  to the Free Software Foundation, Inc.,
+- * 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/8250/8250_lpc18xx.c b/drivers/tty/serial/8250/8250_lpc18xx.c
+index e34011535a6a..eddf119374e1 100644
+--- a/drivers/tty/serial/8250/8250_lpc18xx.c
++++ b/drivers/tty/serial/8250/8250_lpc18xx.c
+@@ -7,11 +7,6 @@
+  * Based on 8250_mtk.c:
+  * Copyright (c) 2014 MundoReader S.L.
+  * Matthias Brugger <matthias.bgg@gmail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c
+index f4b596da0a3d..98dbc796353f 100644
+--- a/drivers/tty/serial/8250/8250_lpss.c
++++ b/drivers/tty/serial/8250/8250_lpss.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2016 Intel Corporation
+  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #include <linux/bitops.h>
+diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c
+index 174a95778935..82d0a13b75cb 100644
+--- a/drivers/tty/serial/8250/8250_mid.c
++++ b/drivers/tty/serial/8250/8250_mid.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2015 Intel Corporation
+  * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #include <linux/bitops.h>
+diff --git a/drivers/tty/serial/8250/8250_moxa.c b/drivers/tty/serial/8250/8250_moxa.c
+index da18dd62e608..1ee4cd94d4fa 100644
+--- a/drivers/tty/serial/8250/8250_moxa.c
++++ b/drivers/tty/serial/8250/8250_moxa.c
+@@ -3,10 +3,6 @@
+  * 8250_moxa.c - MOXA Smartio/Industio MUE multiport serial driver.
+  *
+  * Author: Mathieu OTHACEHE <m.othacehe@gmail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
+index 1e3d983ac483..b1a3be655fb0 100644
+--- a/drivers/tty/serial/8250/8250_mtk.c
++++ b/drivers/tty/serial/8250/8250_mtk.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (c) 2014 MundoReader S.L.
+  * Author: Matthias Brugger <matthias.bgg@gmail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ #include <linux/clk.h>
+ #include <linux/io.h>
+diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
+index 28118c5630ac..9835b1c1cbe1 100644
+--- a/drivers/tty/serial/8250/8250_of.c
++++ b/drivers/tty/serial/8250/8250_of.c
+@@ -3,12 +3,6 @@
+  *  Serial Port driver for Open Firmware platform devices
+  *
+  *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
+- *
+- *  This program is free software; you can redistribute it and/or
+- *  modify it under the terms of the GNU General Public License
+- *  as published by the Free Software Foundation; either version
+- *  2 of the License, or (at your option) any later version.
+- *
+  */
+ #include <linux/console.h>
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
+index ead29f3c03e0..4346e21e50db 100644
+--- a/drivers/tty/serial/8250/8250_pci.c
++++ b/drivers/tty/serial/8250/8250_pci.c
+@@ -5,10 +5,6 @@
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+  *  Copyright (C) 2001 Russell King, All Rights Reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License.
+  */
+ #undef DEBUG
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8250_pnp.c
+index b556f37b9ba9..431e69a5a6a0 100644
+--- a/drivers/tty/serial/8250/8250_pnp.c
++++ b/drivers/tty/serial/8250/8250_pnp.c
+@@ -7,10 +7,6 @@
+  *  Copyright (C) 2001 Russell King, All Rights Reserved.
+  *
+  *  Ported to the Linux PnP Layer - (C) Adam Belay.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License.
+  */
+ #include <linux/module.h>
+ #include <linux/pci.h>
+diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
+index a8f760ea1282..2351fe829440 100644
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -5,11 +5,6 @@
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  * A note about mapbase / membase
+  *
+  *  mapbase is the physical address of the IO port.
+diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c
+index 5ca660c04a9d..b9bcbe20a2be 100644
+--- a/drivers/tty/serial/8250/8250_pxa.c
++++ b/drivers/tty/serial/8250/8250_pxa.c
+@@ -8,12 +8,6 @@
+  *  Copyright:	(C) 2003 Monta Vista Software, Inc.
+  *
+  *  Based on drivers/serial/8250.c by Russell King.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/tty/serial/8250/8250_uniphier.c b/drivers/tty/serial/8250/8250_uniphier.c
+index 752fad67c3fe..28d88ccf5a0c 100644
+--- a/drivers/tty/serial/8250/8250_uniphier.c
++++ b/drivers/tty/serial/8250/8250_uniphier.c
+@@ -1,16 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/altera_jtaguart.c b/drivers/tty/serial/altera_jtaguart.c
+index ef444aff77c5..c90e503d6b57 100644
+--- a/drivers/tty/serial/altera_jtaguart.c
++++ b/drivers/tty/serial/altera_jtaguart.c
+@@ -7,11 +7,6 @@
+  * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
+  * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
+  * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c
+index 69d9c2fd5f85..594f2af81fbc 100644
+--- a/drivers/tty/serial/altera_uart.c
++++ b/drivers/tty/serial/altera_uart.c
+@@ -7,11 +7,6 @@
+  * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
+  * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
+  * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
+index a64a20c8e28b..2c37d11726ab 100644
+--- a/drivers/tty/serial/amba-pl010.c
++++ b/drivers/tty/serial/amba-pl010.c
+@@ -7,20 +7,6 @@
+  *  Copyright 1999 ARM Limited
+  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  * This is a generic driver for ARM AMBA-type serial ports.  They
+  * have a lot of 16550-like features, but are not register compatible.
+  * Note that although they do have CTS, DCD and DSR inputs, they do
+diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
+index 51e7060599f7..13364e170d19 100644
+--- a/drivers/tty/serial/amba-pl011.c
++++ b/drivers/tty/serial/amba-pl011.c
+@@ -8,20 +8,6 @@
+  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+  *  Copyright (C) 2010 ST-Ericsson SA
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  * This is a generic driver for ARM AMBA-type serial ports.  They
+  * have a lot of 16550-like features, but are not register compatible.
+  * Note that although they do have CTS, DCD and DSR inputs, they do
+diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c
+index 15cd1a3ea6bf..db5df3d54818 100644
+--- a/drivers/tty/serial/ar933x_uart.c
++++ b/drivers/tty/serial/ar933x_uart.c
+@@ -5,10 +5,6 @@
+  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+  *
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+- *
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/arc_uart.c b/drivers/tty/serial/arc_uart.c
+index 0a8b80fa09cd..d904a3a345e7 100644
+--- a/drivers/tty/serial/arc_uart.c
++++ b/drivers/tty/serial/arc_uart.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  * vineetg: July 10th 2012
+  *  -Decoupled the driver from arch/arc
+  *    +Using platform_get_resource() for irq/membase (thx to bfin_uart.c)
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 6dbbecde955a..d2755fd81224 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -7,21 +7,6 @@
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+  *  DMA support added by Chip Coldwell.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  */
+ #include <linux/tty.h>
+ #include <linux/ioport.h>
+diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
+index b4e0e57a0a79..ba3a2437cde4 100644
+--- a/drivers/tty/serial/atmel_serial.h
++++ b/drivers/tty/serial/atmel_serial.h
+@@ -7,11 +7,6 @@
+  *
+  * USART registers.
+  * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef ATMEL_SERIAL_H
+diff --git a/drivers/tty/serial/bcm63xx_uart.c b/drivers/tty/serial/bcm63xx_uart.c
+index 474652d26c71..9d1b7bf7378c 100644
+--- a/drivers/tty/serial/bcm63xx_uart.c
++++ b/drivers/tty/serial/bcm63xx_uart.c
+@@ -1,9 +1,5 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+  * Derived from many drivers using generic_serial interface.
+  *
+  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+diff --git a/drivers/tty/serial/bfin_sport_uart.c b/drivers/tty/serial/bfin_sport_uart.c
+index abd0f6cf1bba..704da91b106d 100644
+--- a/drivers/tty/serial/bfin_sport_uart.c
++++ b/drivers/tty/serial/bfin_sport_uart.c
+@@ -5,8 +5,6 @@
+  * Copyright 2006-2009 Analog Devices Inc.
+  *
+  * Enter bugs at http://blackfin.uclinux.org/
+- *
+- * Licensed under the GPL-2 or later.
+  */
+ 
+ /*
+diff --git a/drivers/tty/serial/bfin_sport_uart.h b/drivers/tty/serial/bfin_sport_uart.h
+index 6d9237bb7192..4b12f45d6580 100644
+--- a/drivers/tty/serial/bfin_sport_uart.h
++++ b/drivers/tty/serial/bfin_sport_uart.h
+@@ -5,8 +5,6 @@
+  * Copyright 2006-2008 Analog Devices Inc.
+  *
+  * Enter bugs at http://blackfin.uclinux.org/
+- *
+- * Licensed under the GPL-2 or later.
+  */
+ 
+ /*
+diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
+index 7fc639c47534..f23290267456 100644
+--- a/drivers/tty/serial/bfin_uart.c
++++ b/drivers/tty/serial/bfin_uart.c
+@@ -5,8 +5,6 @@
+  * Copyright 2006-2011 Analog Devices Inc.
+  *
+  * Enter bugs at http://blackfin.uclinux.org/
+- *
+- * Licensed under the GPL-2 or later.
+  */
+ 
+ #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
+index 64d58f2765cc..98f193a83392 100644
+--- a/drivers/tty/serial/clps711x.c
++++ b/drivers/tty/serial/clps711x.c
+@@ -6,11 +6,6 @@
+  *
+  *  Copyright 1999 ARM Limited
+  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart.h b/drivers/tty/serial/cpm_uart/cpm_uart.h
+index 79f1d1128c5a..9f175a92fb5d 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart.h
++++ b/drivers/tty/serial/cpm_uart/cpm_uart.h
+@@ -6,11 +6,6 @@
+  *
+  *  2006 (c) MontaVista Software, Inc.
+  *	Vitaly Bordug <vbordug@ru.mvista.com>
+- *
+- * This file is licensed under the terms of the GNU General Public License
+- * version 2. This program is licensed "as is" without any warranty of any
+- * kind, whether express or implied.
+- *
+  */
+ #ifndef CPM_UART_H
+ #define CPM_UART_H
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+index a98d3ab37fac..24a5f05e769b 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+@@ -13,21 +13,6 @@
+  *            (C) 2004 Intracom, S.A.
+  *            (C) 2005-2006 MontaVista Software, Inc.
+  *		Vitaly Bordug <vbordug@ru.mvista.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
+index 31e952fd98d0..4eba17f3d293 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
+@@ -9,21 +9,6 @@
+  *            (C) 2004 Intracom, S.A.
+  *            (C) 2006 MontaVista Software, Inc.
+  *		Vitaly Bordug <vbordug@ru.mvista.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
+index 84f7c8d32ab3..e3bff068dc3c 100644
+--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
++++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
+@@ -9,21 +9,6 @@
+  *            (C) 2004 Intracom, S.A.
+  *            (C) 2006 MontaVista Software, Inc.
+  *		Vitaly Bordug <vbordug@ru.mvista.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/digicolor-usart.c b/drivers/tty/serial/digicolor-usart.c
+index c38a16381ff3..f460cca139e2 100644
+--- a/drivers/tty/serial/digicolor-usart.c
++++ b/drivers/tty/serial/digicolor-usart.c
+@@ -5,11 +5,6 @@
+  * Author: Baruch Siach <baruch@tkos.co.il>
+  *
+  * Copyright (C) 2014 Paradox Innovation Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
+index 84780c17a889..fa096c10b591 100644
+--- a/drivers/tty/serial/earlycon-arm-semihost.c
++++ b/drivers/tty/serial/earlycon-arm-semihost.c
+@@ -6,18 +6,6 @@
+  * Adapted for ARM and earlycon:
+  * Copyright (C) 2014 Linaro Ltd.
+  * Author: Rob Herring <robh@kernel.org>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/kernel.h>
+ #include <linux/console.h>
+diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
+index 57144c78518f..e20540dab7fb 100644
+--- a/drivers/tty/serial/earlycon.c
++++ b/drivers/tty/serial/earlycon.c
+@@ -6,10 +6,6 @@
+  * Based on 8250 earlycon:
+  * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
+  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
+index d0c072d5c709..63dc1d7669f9 100644
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -3,11 +3,6 @@
+  *  Freescale lpuart serial port driver
+  *
+  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/icom.c b/drivers/tty/serial/icom.c
+index a8fd690fbf29..ad374f7c476d 100644
+--- a/drivers/tty/serial/icom.c
++++ b/drivers/tty/serial/icom.c
+@@ -7,21 +7,6 @@
+   * Serial device driver.
+   *
+   * Based on code from serial.c
+-  *
+-  * This program is free software; you can redistribute it and/or modify
+-  * it under the terms of the GNU General Public License as published by
+-  * the Free Software Foundation; either version 2 of the License, or
+-  * (at your option) any later version.
+-  *
+-  * This program is distributed in the hope that it will be useful,
+-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-  * GNU General Public License for more details.
+-  *
+-  * You should have received a copy of the GNU General Public License
+-  * along with this program; if not, write to the Free Software
+-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+-  *
+   */
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/tty/serial/icom.h b/drivers/tty/serial/icom.h
+index da6a38967d2f..8a77e739b333 100644
+--- a/drivers/tty/serial/icom.h
++++ b/drivers/tty/serial/icom.h
+@@ -5,20 +5,6 @@
+  * Copyright (C) 2001 Michael Anderson, IBM Corporation
+  *
+  * Serial device driver include file.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+  */
+ 
+ #include <linux/serial_core.h>
+diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
+index fe670f9fcbd9..f0d096b94c3f 100644
+--- a/drivers/tty/serial/ifx6x60.c
++++ b/drivers/tty/serial/ifx6x60.c
+@@ -11,20 +11,6 @@
+  * Copyright (C) 2009, 2010 Intel Corp
+  * Russ Gorby <russ.gorby@intel.com>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
+- * USA
+- *
+  * Driver modified by Intel from Option gtm501l_spi.c
+  *
+  * Notes
+diff --git a/drivers/tty/serial/ifx6x60.h b/drivers/tty/serial/ifx6x60.h
+index a5346e7672c0..c5a2514212ff 100644
+--- a/drivers/tty/serial/ifx6x60.h
++++ b/drivers/tty/serial/ifx6x60.h
+@@ -6,23 +6,6 @@
+  * Copyright (C) 2009, 2010 Intel Corp
+  * Jim Stanley <jim.stanley@intel.com>
+  *
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
+- * USA
+- *
+- *
+- *
+  *****************************************************************************/
+ #ifndef _IFX6X60_H
+ #define _IFX6X60_H
+diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
+index 13085ac31f05..ef39a7bb48b1 100644
+--- a/drivers/tty/serial/imx.c
++++ b/drivers/tty/serial/imx.c
+@@ -6,16 +6,6 @@
+  *
+  * Author: Sascha Hauer <sascha@saschahauer.de>
+  * Copyright (C) 2004 Pengutronix
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/ioc3_serial.c b/drivers/tty/serial/ioc3_serial.c
+index fcc4bc85dab4..d8a1cdd6a53d 100644
+--- a/drivers/tty/serial/ioc3_serial.c
++++ b/drivers/tty/serial/ioc3_serial.c
+@@ -1,9 +1,5 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+  * Copyright (C) 2005 Silicon Graphics, Inc.  All Rights Reserved.
+  */
+ 
+diff --git a/drivers/tty/serial/ioc4_serial.c b/drivers/tty/serial/ioc4_serial.c
+index 8804faad5294..db5b979e5a0c 100644
+--- a/drivers/tty/serial/ioc4_serial.c
++++ b/drivers/tty/serial/ioc4_serial.c
+@@ -1,9 +1,5 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+  * Copyright (C) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
+  */
+ 
+diff --git a/drivers/tty/serial/jsm/jsm.h b/drivers/tty/serial/jsm/jsm.h
+index 588080b05b07..7a128aaa3a66 100644
+--- a/drivers/tty/serial/jsm/jsm.h
++++ b/drivers/tty/serial/jsm/jsm.h
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2004 IBM Corporation. All rights reserved.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2, or (at your option)
+- * any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
+- * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+- * PURPOSE.  See the GNU General Public License for more details.
+- *
+  * Contact Information:
+  * Scott H Kilau <Scott_Kilau@digi.com>
+  * Wendy Xiong   <wendyx@us.ibm.com>
+diff --git a/drivers/tty/serial/jsm/jsm_cls.c b/drivers/tty/serial/jsm/jsm_cls.c
+index 74793234e002..c061a7b7bd23 100644
+--- a/drivers/tty/serial/jsm/jsm_cls.c
++++ b/drivers/tty/serial/jsm/jsm_cls.c
+@@ -3,16 +3,6 @@
+  * Copyright 2003 Digi International (www.digi.com)
+  *	Scott H Kilau <Scott_Kilau at digi dot com>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2, or (at your option)
+- * any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
+- * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+- * PURPOSE.  See the GNU General Public License for more details.
+- *
+  *	NOTE TO LINUX KERNEL HACKERS:  DO NOT REFORMAT THIS CODE!
+  *
+  *	This is shared code between Digi's CVS archive and the
+diff --git a/drivers/tty/serial/jsm/jsm_driver.c b/drivers/tty/serial/jsm/jsm_driver.c
+index 0ede8673f5be..592e51d8944e 100644
+--- a/drivers/tty/serial/jsm/jsm_driver.c
++++ b/drivers/tty/serial/jsm/jsm_driver.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2004 IBM Corporation. All rights reserved.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2, or (at your option)
+- * any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
+- * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+- * PURPOSE.  See the GNU General Public License for more details.
+- *
+  * Contact Information:
+  * Scott H Kilau <Scott_Kilau@digi.com>
+  * Wendy Xiong   <wendyx@us.ibm.com>
+diff --git a/drivers/tty/serial/jsm/jsm_neo.c b/drivers/tty/serial/jsm/jsm_neo.c
+index b28a0a478d64..4718560b8fdc 100644
+--- a/drivers/tty/serial/jsm/jsm_neo.c
++++ b/drivers/tty/serial/jsm/jsm_neo.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2004 IBM Corporation. All rights reserved.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2, or (at your option)
+- * any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
+- * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+- * PURPOSE.  See the GNU General Public License for more details.
+- *
+  * Contact Information:
+  * Scott H Kilau <Scott_Kilau@digi.com>
+  * Wendy Xiong   <wendyx@us.ibm.com>
+diff --git a/drivers/tty/serial/jsm/jsm_tty.c b/drivers/tty/serial/jsm/jsm_tty.c
+index 7753d5b364b5..84658ada4ad4 100644
+--- a/drivers/tty/serial/jsm/jsm_tty.c
++++ b/drivers/tty/serial/jsm/jsm_tty.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2004 IBM Corporation. All rights reserved.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2, or (at your option)
+- * any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
+- * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+- * PURPOSE.  See the GNU General Public License for more details.
+- *
+  * Contact Information:
+  * Scott H Kilau <Scott_Kilau@digi.com>
+  * Ananda Venkatarman <mansarov@us.ibm.com>
+diff --git a/drivers/tty/serial/kgdb_nmi.c b/drivers/tty/serial/kgdb_nmi.c
+index b908d4a24de5..ed2b03058627 100644
+--- a/drivers/tty/serial/kgdb_nmi.c
++++ b/drivers/tty/serial/kgdb_nmi.c
+@@ -7,10 +7,6 @@
+  *		  Colin Cross <ccross@android.com>
+  * Copyright 2012 Linaro Ltd.
+  *		  Anton Vorontsov <anton.vorontsov@linaro.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c
+index 62d162ae7610..ddb46fa2d07f 100644
+--- a/drivers/tty/serial/kgdboc.c
++++ b/drivers/tty/serial/kgdboc.c
+@@ -7,10 +7,6 @@
+  * Maintainer: Jason Wessel <jason.wessel@windriver.com>
+  *
+  * 2007-2008 (c) Jason Wessel - Wind River Systems, Inc.
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ #include <linux/kernel.h>
+ #include <linux/ctype.h>
+diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
+index 868abff3db32..044128277248 100644
+--- a/drivers/tty/serial/lantiq.c
++++ b/drivers/tty/serial/lantiq.c
+@@ -2,19 +2,6 @@
+ /*
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  * Copyright (C) 2004 Infineon IFAP DC COM CPE
+  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+  * Copyright (C) 2007 John Crispin <john@phrozen.org>
+diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c
+index 8b58256ec776..d1d73261575b 100644
+--- a/drivers/tty/serial/lpc32xx_hs.c
++++ b/drivers/tty/serial/lpc32xx_hs.c
+@@ -7,16 +7,6 @@
+  *
+  * Copyright (C) 2010 NXP Semiconductors
+  * Copyright (C) 2012 Roland Stigge
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/m32r_sio.c b/drivers/tty/serial/m32r_sio.c
+index 1e44f2e6c5f7..44ae777ff035 100644
+--- a/drivers/tty/serial/m32r_sio.c
++++ b/drivers/tty/serial/m32r_sio.c
+@@ -9,11 +9,6 @@
+  *
+  *  Copyright (C) 2001  Russell King.
+  *  Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ /*
+diff --git a/drivers/tty/serial/m32r_sio_reg.h b/drivers/tty/serial/m32r_sio_reg.h
+index 0fd9727edec3..6eed48828f94 100644
+--- a/drivers/tty/serial/m32r_sio_reg.h
++++ b/drivers/tty/serial/m32r_sio_reg.h
+@@ -5,9 +5,6 @@
+  * Copyright (C) 1992, 1994 by Theodore Ts'o.
+  * Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
+  *
+- * Redistribution of this file is permitted under the terms of the GNU
+- * Public License (GPL)
+- *
+  * These are the UART port assignments, expressed as offsets from the base
+  * register.  These assignments should hold for any serial port based on
+  * a 8250, 16450, or 16550(A).
+diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c
+index d5e4a5336095..16d34fab895f 100644
+--- a/drivers/tty/serial/max3100.c
++++ b/drivers/tty/serial/max3100.c
+@@ -3,12 +3,6 @@
+  *
+  *  Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- *
+  * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
+  * to use polling for flow control. TX empty IRQ is unusable, since
+  * writing conf clears FIFO buffer and we cannot have this interrupt
+diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
+index bd626ec325d5..ecb6513a6505 100644
+--- a/drivers/tty/serial/max310x.c
++++ b/drivers/tty/serial/max310x.c
+@@ -7,11 +7,6 @@
+  *  Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
+  *  Based on max3110.c, by Feng Tang <feng.tang@intel.com>
+  *  Based on max3107.c, by Aavamobile
+- *
+- *  This program is free software; you can redistribute it and/or modify
+- *  it under the terms of the GNU General Public License as published by
+- *  the Free Software Foundation; either version 2 of the License, or
+- *  (at your option) any later version.
+  */
+ 
+ #include <linux/bitops.h>
+diff --git a/drivers/tty/serial/mcf.c b/drivers/tty/serial/mcf.c
+index 9c779768bd16..7dbfb4cde124 100644
+--- a/drivers/tty/serial/mcf.c
++++ b/drivers/tty/serial/mcf.c
+@@ -5,11 +5,6 @@
+  *	mcf.c -- Freescale ColdFire UART driver
+  *
+  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ /****************************************************************************/
+diff --git a/drivers/tty/serial/men_z135_uart.c b/drivers/tty/serial/men_z135_uart.c
+index 9387b2c745a0..ef89534dd760 100644
+--- a/drivers/tty/serial/men_z135_uart.c
++++ b/drivers/tty/serial/men_z135_uart.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
+  * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the Free
+- * Software Foundation; version 2 of the License.
+  */
+ #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
+ 
+diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
+index d4875ea65a53..ef714f779712 100644
+--- a/drivers/tty/serial/meson_uart.c
++++ b/drivers/tty/serial/meson_uart.c
+@@ -3,16 +3,6 @@
+  *  Based on meson_uart.c, by AMLOGIC, INC.
+  *
+  * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
+index 1c1febdf60ce..3a75ee08d619 100644
+--- a/drivers/tty/serial/mpc52xx_uart.c
++++ b/drivers/tty/serial/mpc52xx_uart.c
+@@ -24,10 +24,6 @@
+  *                    Grant Likely <grant.likely@secretlab.ca>
+  * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
+  * Copyright (C) 2003 MontaVista, Software, Inc.
+- *
+- * This file is licensed under the terms of the GNU General Public License
+- * version 2. This program is licensed "as is" without any warranty of any
+- * kind, whether express or implied.
+  */
+ 
+ #undef DEBUG
+diff --git a/drivers/tty/serial/mps2-uart.c b/drivers/tty/serial/mps2-uart.c
+index 5d789b584bc5..9f8f63719126 100644
+--- a/drivers/tty/serial/mps2-uart.c
++++ b/drivers/tty/serial/mps2-uart.c
+@@ -6,10 +6,6 @@
+  *
+  * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  * TODO: support for SysRq
+  */
+ 
+diff --git a/drivers/tty/serial/mpsc.c b/drivers/tty/serial/mpsc.c
+index 21b28d8e3c02..1f60d6fe4ff2 100644
+--- a/drivers/tty/serial/mpsc.c
++++ b/drivers/tty/serial/mpsc.c
+@@ -11,10 +11,7 @@
+  * taken from PPCBoot (now U-Boot).  Also based on drivers/serial/8250.c
+  * by Russell King.
+  *
+- * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
+- * the terms of the GNU General Public License version 2.  This program
+- * is licensed "as is" without any warranty of any kind, whether express
+- * or implied.
++ * 2004 (c) MontaVista, Software, Inc.
+  */
+ /*
+  * The MPSC interface is much like a typical network controller's interface.
+diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
+index 76649fea8f6f..ee96cf0d0057 100644
+--- a/drivers/tty/serial/msm_serial.c
++++ b/drivers/tty/serial/msm_serial.c
+@@ -5,15 +5,6 @@
+  * Copyright (C) 2007 Google, Inc.
+  * Author: Robert Love <rlove@google.com>
+  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/mux.c b/drivers/tty/serial/mux.c
+index 44f503ea54d2..c164843bc32a 100644
+--- a/drivers/tty/serial/mux.c
++++ b/drivers/tty/serial/mux.c
+@@ -6,11 +6,6 @@
+ **	(c) Copyright 2002 Ryan Bradetich
+ **	(c) Copyright 2002 Hewlett-Packard Company
+ **
+-** This program is free software; you can redistribute it and/or modify
+-** it under the terms of the GNU General Public License as published by
+-** the Free Software Foundation; either version 2 of the License, or
+-** (at your option) any later version.
+-**
+ ** This Driver currently only supports the console (port 0) on the MUX.
+ ** Additional work will be needed on this driver to enable the full
+ ** functionality of the MUX.
+diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
+index 09e7da6eab97..b1aff6346166 100644
+--- a/drivers/tty/serial/mvebu-uart.c
++++ b/drivers/tty/serial/mvebu-uart.c
+@@ -5,18 +5,6 @@
+ * Author: Wilson Ding <dingwei@marvell.com>
+ * Copyright (C) 2015 Marvell International Ltd.
+ * ***************************************************************************
+-* This program is free software: you can redistribute it and/or modify it
+-* under the terms of the GNU General Public License as published by the Free
+-* Software Foundation, either version 2 of the License, or any later version.
+-*
+-* This program is distributed in the hope that it will be useful,
+-* but WITHOUT ANY WARRANTY; without even the implied warranty of
+-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-* GNU General Public License for more details.
+-*
+-* You should have received a copy of the GNU General Public License
+-* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-* ***************************************************************************
+ */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
+index 588e08274233..4fefec8700b9 100644
+--- a/drivers/tty/serial/mxs-auart.c
++++ b/drivers/tty/serial/mxs-auart.c
+@@ -10,10 +10,6 @@
+  *	Provide Alphascale ASM9260 support.
+  * Copyright 2008-2010 Freescale Semiconductor, Inc.
+  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+- *
+- * The code contained herein is licensed under the GNU General Public
+- * License. You may obtain a copy of the GNU General Public License
+- * Version 2 or later at the following locations:
+  */
+ 
+ #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/netx-serial.c b/drivers/tty/serial/netx-serial.c
+index 4201938e8aa3..b3556863491f 100644
+--- a/drivers/tty/serial/netx-serial.c
++++ b/drivers/tty/serial/netx-serial.c
+@@ -1,19 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2
+- * as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
+index f25544e8228d..366567ca2abb 100644
+--- a/drivers/tty/serial/omap-serial.c
++++ b/drivers/tty/serial/omap-serial.c
+@@ -9,11 +9,6 @@
+  *	Govindraj R	<govindraj.raja@ti.com>
+  *	Thara Gopinath	<thara@ti.com>
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  * Note: This driver is made separate from 8250 driver as we cannot
+  * over load 8250 driver with omap platform specific configuration for
+  * features like DMA, it makes easier to implement features like DMA and
+diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
+index 93fa3095a775..29a6dc6a8d23 100644
+--- a/drivers/tty/serial/owl-uart.c
++++ b/drivers/tty/serial/owl-uart.c
+@@ -6,19 +6,6 @@
+  * Author: Actions Semi, Inc.
+  *
+  * Copyright (c) 2016-2017 Andreas Färber
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
+index e2c04a3334da..760d5dd0aada 100644
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -1,19 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+- *
+- *This program is free software; you can redistribute it and/or modify
+- *it under the terms of the GNU General Public License as published by
+- *the Free Software Foundation; version 2 of the License.
+- *
+- *This program is distributed in the hope that it will be useful,
+- *but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *GNU General Public License for more details.
+- *
+- *You should have received a copy of the GNU General Public License
+- *along with this program; if not, write to the Free Software
+- *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
+  */
+ #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+ #define SUPPORT_SYSRQ
+diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
+index 9f55c30d1aa6..fd80d999308d 100644
+--- a/drivers/tty/serial/pic32_uart.c
++++ b/drivers/tty/serial/pic32_uart.c
+@@ -6,8 +6,6 @@
+  *
+  * Authors:
+  *   Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
+- *
+- * Licensed under GPLv2 or later.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/tty/serial/pic32_uart.h b/drivers/tty/serial/pic32_uart.h
+index 43dc168dffd7..2f2b56927dc6 100644
+--- a/drivers/tty/serial/pic32_uart.h
++++ b/drivers/tty/serial/pic32_uart.h
+@@ -6,8 +6,6 @@
+  *
+  * Authors:
+  *   Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
+- *
+- * Licensed under GPLv2 or later.
+  */
+ #ifndef __DT_PIC32_UART_H__
+ #define __DT_PIC32_UART_H__
+diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
+index 3afba70022b4..3d21790d961e 100644
+--- a/drivers/tty/serial/pmac_zilog.c
++++ b/drivers/tty/serial/pmac_zilog.c
+@@ -14,20 +14,6 @@
+  * and once done, I expect that driver to remain fairly stable in
+  * the long term, unless we change the driver model again...
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- *
+  * 2004-08-06 Harald Welte <laforge@gnumonks.org>
+  *	- Enable BREAK interrupt
+  *	- Add support for sysreq
+diff --git a/drivers/tty/serial/pnx8xxx_uart.c b/drivers/tty/serial/pnx8xxx_uart.c
+index a61fb04cca24..8073de35e56c 100644
+--- a/drivers/tty/serial/pnx8xxx_uart.c
++++ b/drivers/tty/serial/pnx8xxx_uart.c
+@@ -8,11 +8,6 @@
+  *
+  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  * Copyright (C) 2000 Deep Blue Solutions Ltd.
+- *
+- * This file is licensed under the terms of the GNU General Public License
+- * version 2. This program is licensed "as is" without any warranty of
+- * any kind, whether express or implied.
+- *
+  */
+ 
+ #if defined(CONFIG_SERIAL_PNX8XXX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
+index dd82ecb7c25d..baf552944d56 100644
+--- a/drivers/tty/serial/pxa.c
++++ b/drivers/tty/serial/pxa.c
+@@ -6,11 +6,6 @@
+  *  Created:	Feb 20, 2003
+  *  Copyright:	(C) 2003 Monta Vista Software, Inc.
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  * Note 1: This driver is made separate from the already too overloaded
+  * 8250.c because it needs some kirks of its own and that'll make it
+  * easier to add DMA support.
+diff --git a/drivers/tty/serial/rp2.c b/drivers/tty/serial/rp2.c
+index 2108bf34ff90..520b43b23543 100644
+--- a/drivers/tty/serial/rp2.c
++++ b/drivers/tty/serial/rp2.c
+@@ -11,10 +11,6 @@
+  *
+  *   rocketport_infinity_express-linux-1.20.tar.gz
+  *     Copyright (C) 2004-2011 Comtrol, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+  */
+ 
+ #include <linux/bitops.h>
+diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
+index 125558fa2ce9..82ad3e31e73a 100644
+--- a/drivers/tty/serial/sa1100.c
++++ b/drivers/tty/serial/sa1100.c
+@@ -5,20 +5,6 @@
+  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+  *
+  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
+index 9a30b12ac352..64e96926f1ad 100644
+--- a/drivers/tty/serial/samsung.c
++++ b/drivers/tty/serial/samsung.c
+@@ -4,10 +4,6 @@
+  *
+  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
+  *	http://armlinux.simtec.co.uk/
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+ */
+ 
+ /* Hote on 2410 error handling
+diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
+index b0461c096d0a..f93022113f59 100644
+--- a/drivers/tty/serial/samsung.h
++++ b/drivers/tty/serial/samsung.h
+@@ -7,10 +7,6 @@
+  *
+  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
+  *	http://armlinux.simtec.co.uk/
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+ */
+ 
+ #include <linux/dmaengine.h>
+diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c
+index f3d5b4ebb9d5..329aced26bd8 100644
+--- a/drivers/tty/serial/sb1250-duart.c
++++ b/drivers/tty/serial/sb1250-duart.c
+@@ -10,11 +10,6 @@
+  *
+  *	Copyright (c) 2000, 2001, 2002, 2003, 2004  Broadcom Corporation
+  *
+- *	This program is free software; you can redistribute it and/or
+- *	modify it under the terms of the GNU General Public License
+- *	as published by the Free Software Foundation; either version
+- *	2 of the License, or (at your option) any later version.
+- *
+  *	References:
+  *
+  *	"BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
+diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
+index f1e216e714ee..65792a3539d0 100644
+--- a/drivers/tty/serial/sc16is7xx.c
++++ b/drivers/tty/serial/sc16is7xx.c
+@@ -4,12 +4,6 @@
+  * Author: Jon Ringle <jringle@gridpoint.com>
+  *
+  *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  */
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c
+index 8c580d7dd2fe..149e1b53948f 100644
+--- a/drivers/tty/serial/sccnxp.c
++++ b/drivers/tty/serial/sccnxp.c
+@@ -5,11 +5,6 @@
+  *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+  *
+  *  Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
+index fae65e76a9f3..af2a29cfbbe9 100644
+--- a/drivers/tty/serial/serial-tegra.c
++++ b/drivers/tty/serial/serial-tegra.c
+@@ -7,18 +7,6 @@
+  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+  *
+  * Author: Laxman Dewangan <ldewangan@nvidia.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
+index 1cd0cb292ff9..e93df3b6092d 100644
+--- a/drivers/tty/serial/serial_core.c
++++ b/drivers/tty/serial/serial_core.c
+@@ -6,20 +6,6 @@
+  *
+  *  Copyright 1999 ARM Limited
+  *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ #include <linux/module.h>
+ #include <linux/tty.h>
+diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
+index 9a894e899876..b461d791188c 100644
+--- a/drivers/tty/serial/serial_ks8695.c
++++ b/drivers/tty/serial/serial_ks8695.c
+@@ -5,12 +5,6 @@
+  *  Based on drivers/serial/serial_amba.c, by Kam Lee.
+  *
+  *  Copyright 2002-2005 Micrel Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  */
+ #include <linux/module.h>
+ #include <linux/tty.h>
+diff --git a/drivers/tty/serial/serial_mctrl_gpio.c b/drivers/tty/serial/serial_mctrl_gpio.c
+index 302dda18fcbd..1c06325beaca 100644
+--- a/drivers/tty/serial/serial_mctrl_gpio.c
++++ b/drivers/tty/serial/serial_mctrl_gpio.c
+@@ -3,16 +3,6 @@
+  * Helpers for controlling modem lines via GPIO
+  *
+  * Copyright (C) 2014 Paratronic S.A.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #include <linux/err.h>
+diff --git a/drivers/tty/serial/serial_mctrl_gpio.h b/drivers/tty/serial/serial_mctrl_gpio.h
+index 219eba0223bb..b7d3cca48ede 100644
+--- a/drivers/tty/serial/serial_mctrl_gpio.h
++++ b/drivers/tty/serial/serial_mctrl_gpio.h
+@@ -3,17 +3,6 @@
+  * Helpers for controlling modem lines via GPIO
+  *
+  * Copyright (C) 2014 Paratronic S.A.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #ifndef __SERIAL_MCTRL_GPIO__
+diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
+index 256c61d1c6a6..1b4008d022bf 100644
+--- a/drivers/tty/serial/serial_txx9.c
++++ b/drivers/tty/serial/serial_txx9.c
+@@ -9,10 +9,6 @@
+  *  Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
+  *  Copyright (C) 2000-2002 Toshiba Corporation
+  *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  *  Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
+  */
+ 
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index eae806bd3555..5d33bc1a0e09 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -14,10 +14,6 @@
+  *   Modified to support SecureEdge. David McCullough (2002)
+  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
+  *   Removed SH7300 support (Jul 2007).
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+  */
+ #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+ #define SUPPORT_SYSRQ
+diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
+index 3e3ea07c54c0..9925b00a9777 100644
+--- a/drivers/tty/serial/sirfsoc_uart.c
++++ b/drivers/tty/serial/sirfsoc_uart.c
+@@ -3,8 +3,6 @@
+  * Driver for CSR SiRFprimaII onboard UARTs.
+  *
+  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+- *
+- * Licensed under GPLv2 or later.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h
+index 6d6251526631..004ca684d3ae 100644
+--- a/drivers/tty/serial/sirfsoc_uart.h
++++ b/drivers/tty/serial/sirfsoc_uart.h
+@@ -3,8 +3,6 @@
+  * Drivers for CSR SiRFprimaII onboard UARTs.
+  *
+  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+- *
+- * Licensed under GPLv2 or later.
+  */
+ #include <linux/bitops.h>
+ #include <linux/log2.h>
+diff --git a/drivers/tty/serial/sn_console.c b/drivers/tty/serial/sn_console.c
+index 9e0e6586c698..23c9d1fa5e33 100644
+--- a/drivers/tty/serial/sn_console.c
++++ b/drivers/tty/serial/sn_console.c
+@@ -8,25 +8,6 @@
+  *
+  * Copyright (c) 2004-2006 Silicon Graphics, Inc.  All Rights Reserved.
+  *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of version 2 of the GNU General Public License
+- * as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it would be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+- *
+- * Further, this software is distributed without any warranty that it is
+- * free of the rightful claim of any third person regarding infringement
+- * or the like.  Any license provided herein, whether implied or
+- * otherwise, applies only to this software file.  Patent licenses, if
+- * any, provided herein do not apply to combinations of this program with
+- * other software, or any other product whatsoever.
+- *
+- * You should have received a copy of the GNU General Public
+- * License along with this program; if not, write the Free Software
+- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+- *
+  * Contact information:  Silicon Graphics, Inc., 1500 Crittenden Lane,
+  * Mountain View, CA  94043, or:
+  *
+diff --git a/drivers/tty/serial/sprd_serial.c b/drivers/tty/serial/sprd_serial.c
+index a06d50f52ea8..828f1143859c 100644
+--- a/drivers/tty/serial/sprd_serial.c
++++ b/drivers/tty/serial/sprd_serial.c
+@@ -1,15 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #if defined(CONFIG_SERIAL_SPRD_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c
+index 1f51eef68c85..c763253514e9 100644
+--- a/drivers/tty/serial/st-asc.c
++++ b/drivers/tty/serial/st-asc.c
+@@ -3,12 +3,6 @@
+  * st-asc.c: ST Asynchronous serial controller (ASC) driver
+  *
+  * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+  */
+ 
+ #if defined(CONFIG_SERIAL_ST_ASC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
+index 007ad0274ed0..f9f3da329daa 100644
+--- a/drivers/tty/serial/stm32-usart.c
++++ b/drivers/tty/serial/stm32-usart.c
+@@ -4,7 +4,6 @@
+  * Copyright (C) STMicroelectronics SA 2017
+  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+  *	     Gerald Baeza <gerald.baeza@st.com>
+- * License terms:  GNU General Public License (GPL), version 2
+  *
+  * Inspired by st-asc.c from STMicroelectronics (c)
+  */
+diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
+index 174be6141cef..8a5ff54d0f42 100644
+--- a/drivers/tty/serial/stm32-usart.h
++++ b/drivers/tty/serial/stm32-usart.h
+@@ -4,7 +4,6 @@
+  * Copyright (C) STMicroelectronics SA 2017
+  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+  *	     Gerald Baeza <gerald_baeza@yahoo.fr>
+- * License terms:  GNU General Public License (GPL), version 2
+  */
+ 
+ #define DRIVER_NAME "stm32-usart"
+diff --git a/drivers/tty/serial/tilegx.c b/drivers/tty/serial/tilegx.c
+index 311eea391f57..f0a3ae57f881 100644
+--- a/drivers/tty/serial/tilegx.c
++++ b/drivers/tty/serial/tilegx.c
+@@ -2,16 +2,6 @@
+ /*
+  * Copyright 2013 Tilera Corporation. All Rights Reserved.
+  *
+- *   This program is free software; you can redistribute it and/or
+- *   modify it under the terms of the GNU General Public License
+- *   as published by the Free Software Foundation, version 2.
+- *
+- *   This program is distributed in the hope that it will be useful, but
+- *   WITHOUT ANY WARRANTY; without even the implied warranty of
+- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+- *   NON INFRINGEMENT.  See the GNU General Public License for
+- *   more details.
+- *
+  * TILEGx UART driver.
+  */
+ 
+diff --git a/drivers/tty/serial/timbuart.c b/drivers/tty/serial/timbuart.c
+index cdbc23fc85e3..19d38b504e27 100644
+--- a/drivers/tty/serial/timbuart.c
++++ b/drivers/tty/serial/timbuart.c
+@@ -2,19 +2,6 @@
+ /*
+  * timbuart.c timberdale FPGA UART driver
+  * Copyright (c) 2009 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ /* Supports:
+diff --git a/drivers/tty/serial/timbuart.h b/drivers/tty/serial/timbuart.h
+index 6c642e99abcf..fb00b172117d 100644
+--- a/drivers/tty/serial/timbuart.h
++++ b/drivers/tty/serial/timbuart.h
+@@ -2,19 +2,6 @@
+ /*
+  * timbuart.c timberdale FPGA GPIO driver
+  * Copyright (c) 2009 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ /* Supports:
+diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
+index 5bf19bca480d..67917622aaf3 100644
+--- a/drivers/tty/serial/uartlite.c
++++ b/drivers/tty/serial/uartlite.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
+  * Copyright (C) 2007 Secret Lab Technologies Ltd.
+- *
+- * This file is licensed under the terms of the GNU General Public License
+- * version 2.  This program is licensed "as is" without any warranty of any
+- * kind, whether express or implied.
+  */
+ 
+ #include <linux/platform_device.h>
+diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
+index b01772712c1d..2b6376e6e5ad 100644
+--- a/drivers/tty/serial/ucc_uart.c
++++ b/drivers/tty/serial/ucc_uart.c
+@@ -4,10 +4,7 @@
+  *
+  * Author: Timur Tabi <timur@freescale.com>
+  *
+- * Copyright 2007 Freescale Semiconductor, Inc.  This file is licensed under
+- * the terms of the GNU General Public License version 2.  This program
+- * is licensed "as is" without any warranty of any kind, whether express
+- * or implied.
++ * Copyright 2007 Freescale Semiconductor, Inc.
+  *
+  * This driver adds support for UART devices via Freescale's QUICC Engine
+  * found on some Freescale SOCs.
+diff --git a/drivers/tty/serial/vr41xx_siu.c b/drivers/tty/serial/vr41xx_siu.c
+index fc100ea7eded..6d106e33f842 100644
+--- a/drivers/tty/serial/vr41xx_siu.c
++++ b/drivers/tty/serial/vr41xx_siu.c
+@@ -5,20 +5,6 @@
+  *  Copyright (C) 2004-2008  Yoichi Yuasa <yuasa@linux-mips.org>
+  *
+  *  Based on drivers/serial/8250.c, by Russell King.
+- *
+- *  This program is free software; you can redistribute it and/or modify
+- *  it under the terms of the GNU General Public License as published by
+- *  the Free Software Foundation; either version 2 of the License, or
+- *  (at your option) any later version.
+- *
+- *  This program is distributed in the hope that it will be useful,
+- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *  GNU General Public License for more details.
+- *
+- *  You should have received a copy of the GNU General Public License
+- *  along with this program; if not, write to the Free Software
+- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
+index 334f0f4e20f5..3d58e9b34553 100644
+--- a/drivers/tty/serial/vt8500_serial.c
++++ b/drivers/tty/serial/vt8500_serial.c
+@@ -5,15 +5,6 @@
+  * Based on msm_serial.c, which is:
+  * Copyright (C) 2007 Google, Inc.
+  * Author: Robert Love <rlove@google.com>
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
+index 09926355b7f2..69702d3eaf55 100644
+--- a/drivers/tty/serial/xilinx_uartps.c
++++ b/drivers/tty/serial/xilinx_uartps.c
+@@ -4,12 +4,6 @@
+  *
+  * 2011 - 2014 (C) Xilinx Inc.
+  *
+- * This program is free software; you can redistribute it
+- * and/or modify it under the terms of the GNU General Public
+- * License as published by the Free Software Foundation;
+- * either version 2 of the License, or (at your option) any
+- * later version.
+- *
+  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
+  * still shows in the naming of this file, the kconfig symbols and some symbols
+  * in the code.
+-- 
+2.19.0
+
diff --git a/patches/0168-clocksource-drivers-sh_cmt-Use-0x3f-mask-for-SH_CMT_.patch b/patches/0168-clocksource-drivers-sh_cmt-Use-0x3f-mask-for-SH_CMT_.patch
new file mode 100644
index 00000000000000..d0aa59d5498ffb
--- /dev/null
+++ b/patches/0168-clocksource-drivers-sh_cmt-Use-0x3f-mask-for-SH_CMT_.patch
@@ -0,0 +1,66 @@
+From fefd0395d34b151629d6cc717b62bb91206a0f73 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 18 Sep 2017 15:46:42 +0200
+Subject: [PATCH 0168/1795] clocksource/drivers/sh_cmt: Use 0x3f mask for
+ SH_CMT_48BIT case
+
+Always use 0x3f as channel mask for the SH_CMT_48BIT type of devices.
+Once this patch is applied the "renesas,channels-mask" property will
+be ignored by the driver for older devices matching SH_CMT_48BIT. In
+the future when all CMT types store channel mask in the driver then
+we will be able to deprecate and remove "renesas,channels-mask" from DTS.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit 464eed841f54b56df35132434497235f06b154f6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index e09e8bf0bb9b..c104c80424c8 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -74,6 +74,8 @@ enum sh_cmt_model {
+ struct sh_cmt_info {
+ 	enum sh_cmt_model model;
+ 
++	unsigned int channels_mask;
++
+ 	unsigned long width; /* 16 or 32 bit version of hardware block */
+ 	unsigned long overflow_bit;
+ 	unsigned long clear_bits;
+@@ -212,6 +214,7 @@ static const struct sh_cmt_info sh_cmt_info[] = {
+ 	},
+ 	[SH_CMT_48BIT] = {
+ 		.model = SH_CMT_48BIT,
++		.channels_mask = 0x3f,
+ 		.width = 32,
+ 		.overflow_bit = SH_CMT32_CMCSR_CMF,
+ 		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
+@@ -966,9 +969,14 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
+ 		id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
+ 		cmt->info = id->data;
+ 
+-		ret = sh_cmt_parse_dt(cmt);
+-		if (ret < 0)
+-			return ret;
++		/* prefer in-driver channel configuration over DT */
++		if (cmt->info->channels_mask) {
++			cmt->hw_channels = cmt->info->channels_mask;
++		} else {
++			ret = sh_cmt_parse_dt(cmt);
++			if (ret < 0)
++				return ret;
++		}
+ 	} else if (pdev->dev.platform_data) {
+ 		struct sh_timer_config *cfg = pdev->dev.platform_data;
+ 		const struct platform_device_id *id = pdev->id_entry;
+-- 
+2.19.0
+
diff --git a/patches/0169-clocksource-drivers-sh_cmt-Support-separate-R-Car-Ge.patch b/patches/0169-clocksource-drivers-sh_cmt-Support-separate-R-Car-Ge.patch
new file mode 100644
index 00000000000000..dc8512e4422fd4
--- /dev/null
+++ b/patches/0169-clocksource-drivers-sh_cmt-Support-separate-R-Car-Ge.patch
@@ -0,0 +1,128 @@
+From 0d38d7f30c5416e258936dc2a11ccabfba61ca0f Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 18 Sep 2017 15:46:43 +0200
+Subject: [PATCH 0169/1795] clocksource/drivers/sh_cmt: Support separate R-Car
+ Gen2 CMT0/1
+
+Add support for the new R-Car Gen2 CMT0 and CMT1 bindings. Support
+for the old DT binding is still kept around, however devices using
+such binding will be treated as a low-feature CMT0 device. If users
+want to make use of CMT1-specific features then they need to update
+their DTBs. No special CMT1-specific features are however implemented
+by his patch, only DT bindings are redone as groundwork for future
+feature patches.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit 83c79a6d8d7f4821ba0712da57f2f51326f0c447)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 38 +++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index c104c80424c8..45af436483f3 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -39,16 +39,16 @@ struct sh_cmt_device;
+  * SoC but also on the particular instance. The following table lists the main
+  * characteristics of those flavours.
+  *
+- *			16B	32B	32B-F	48B	48B-2
++ *			16B	32B	32B-F	48B	R-Car Gen2
+  * -----------------------------------------------------------------------------
+  * Channels		2	1/4	1	6	2/8
+  * Control Width	16	16	16	16	32
+  * Counter Width	16	32	32	32/48	32/48
+  * Shared Start/Stop	Y	Y	Y	Y	N
+  *
+- * The 48-bit gen2 version has a per-channel start/stop register located in the
+- * channel registers block. All other versions have a shared start/stop register
+- * located in the global space.
++ * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
++ * located in the channel registers block. All other versions have a shared
++ * start/stop register located in the global space.
+  *
+  * Channels are indexed from 0 to N-1 in the documentation. The channel index
+  * infers the start/stop bit position in the control register and the channel
+@@ -68,7 +68,8 @@ enum sh_cmt_model {
+ 	SH_CMT_32BIT,
+ 	SH_CMT_32BIT_FAST,
+ 	SH_CMT_48BIT,
+-	SH_CMT_48BIT_GEN2,
++	SH_CMT0_RCAR_GEN2,
++	SH_CMT1_RCAR_GEN2,
+ };
+ 
+ struct sh_cmt_info {
+@@ -223,8 +224,20 @@ static const struct sh_cmt_info sh_cmt_info[] = {
+ 		.read_count = sh_cmt_read32,
+ 		.write_count = sh_cmt_write32,
+ 	},
+-	[SH_CMT_48BIT_GEN2] = {
+-		.model = SH_CMT_48BIT_GEN2,
++	[SH_CMT0_RCAR_GEN2] = {
++		.model = SH_CMT0_RCAR_GEN2,
++		.channels_mask = 0x60,
++		.width = 32,
++		.overflow_bit = SH_CMT32_CMCSR_CMF,
++		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
++		.read_control = sh_cmt_read32,
++		.write_control = sh_cmt_write32,
++		.read_count = sh_cmt_read32,
++		.write_count = sh_cmt_write32,
++	},
++	[SH_CMT1_RCAR_GEN2] = {
++		.model = SH_CMT1_RCAR_GEN2,
++		.channels_mask = 0xff,
+ 		.width = 32,
+ 		.overflow_bit = SH_CMT32_CMCSR_CMF,
+ 		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
+@@ -862,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
+ 	ch->cmt = cmt;
+ 	ch->index = index;
+ 	ch->hwidx = hwidx;
++	ch->timer_bit = hwidx;
+ 
+ 	/*
+ 	 * Compute the address of the channel control register block. For the
+@@ -883,9 +897,11 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
+ 		 */
+ 		ch->ioctrl = cmt->mapbase + 0x40;
+ 		break;
+-	case SH_CMT_48BIT_GEN2:
++	case SH_CMT0_RCAR_GEN2:
++	case SH_CMT1_RCAR_GEN2:
+ 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
+ 		ch->ioctrl = ch->iostart + 0x10;
++		ch->timer_bit = 0;
+ 		break;
+ 	}
+ 
+@@ -897,8 +913,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
+ 	ch->match_value = ch->max_match_value;
+ 	raw_spin_lock_init(&ch->lock);
+ 
+-	ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
+-
+ 	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
+ 			      clockevent, clocksource);
+ 	if (ret) {
+@@ -941,7 +955,9 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
+ 	{ .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] },
+ 	{ .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] },
+ 	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
+-	{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] },
++	{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
++	{ .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
++	{ .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
+-- 
+2.19.0
+
diff --git a/patches/0170-clocksource-drivers-sh_cmt-Remove-support-for-renesa.patch b/patches/0170-clocksource-drivers-sh_cmt-Remove-support-for-renesa.patch
new file mode 100644
index 00000000000000..0746698c5b88d5
--- /dev/null
+++ b/patches/0170-clocksource-drivers-sh_cmt-Remove-support-for-renesa.patch
@@ -0,0 +1,78 @@
+From 2193b7a6980eff2a546da074244e5ca01847421b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 18 Sep 2017 15:46:44 +0200
+Subject: [PATCH 0170/1795] clocksource/drivers/sh_cmt: Remove support for
+ "renesas,cmt-32*"
+
+Remove driver matching support for the unused "renesas,cmt-32" and
+"renesas,cmt-32-fast" compatible values, cfr. commit 203bb3479958c48a
+("devicetree: bindings: Remove unused 32-bit CMT bindings").
+
+As this removes the last user of SH_CMT_32BIT_FAST, all support for this
+variant is removed from the driver.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit f11fb6df3c1924e3623d1afd1db23ea16c68fbb5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 20 --------------------
+ 1 file changed, 20 deletions(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index 45af436483f3..8546736e3bc8 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -66,7 +66,6 @@ struct sh_cmt_device;
+ enum sh_cmt_model {
+ 	SH_CMT_16BIT,
+ 	SH_CMT_32BIT,
+-	SH_CMT_32BIT_FAST,
+ 	SH_CMT_48BIT,
+ 	SH_CMT0_RCAR_GEN2,
+ 	SH_CMT1_RCAR_GEN2,
+@@ -203,16 +202,6 @@ static const struct sh_cmt_info sh_cmt_info[] = {
+ 		.read_count = sh_cmt_read32,
+ 		.write_count = sh_cmt_write32,
+ 	},
+-	[SH_CMT_32BIT_FAST] = {
+-		.model = SH_CMT_32BIT_FAST,
+-		.width = 32,
+-		.overflow_bit = SH_CMT32_CMCSR_CMF,
+-		.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
+-		.read_control = sh_cmt_read16,
+-		.write_control = sh_cmt_write16,
+-		.read_count = sh_cmt_read32,
+-		.write_count = sh_cmt_write32,
+-	},
+ 	[SH_CMT_48BIT] = {
+ 		.model = SH_CMT_48BIT,
+ 		.channels_mask = 0x3f,
+@@ -890,13 +879,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
+ 	case SH_CMT_48BIT:
+ 		ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
+ 		break;
+-	case SH_CMT_32BIT_FAST:
+-		/*
+-		 * The 32-bit "fast" timer has a single channel at hwidx 5 but
+-		 * is located at offset 0x40 instead of 0x60 for some reason.
+-		 */
+-		ch->ioctrl = cmt->mapbase + 0x40;
+-		break;
+ 	case SH_CMT0_RCAR_GEN2:
+ 	case SH_CMT1_RCAR_GEN2:
+ 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
+@@ -952,8 +934,6 @@ static const struct platform_device_id sh_cmt_id_table[] = {
+ MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
+ 
+ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
+-	{ .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] },
+-	{ .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] },
+ 	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
+ 	{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
+ 	{ .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
+-- 
+2.19.0
+
diff --git a/patches/0171-clocksource-drivers-sh_cmt-Mark-renesas-cmt-48-gen2-.patch b/patches/0171-clocksource-drivers-sh_cmt-Mark-renesas-cmt-48-gen2-.patch
new file mode 100644
index 00000000000000..12fdb20975419e
--- /dev/null
+++ b/patches/0171-clocksource-drivers-sh_cmt-Mark-renesas-cmt-48-gen2-.patch
@@ -0,0 +1,41 @@
+From 377bf1d1537ffda132e25391f7c18903e7eec2ec Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 18 Sep 2017 15:46:45 +0200
+Subject: [PATCH 0171/1795] clocksource/drivers/sh_cmt: Mark
+ "renesas,cmt-48-gen2" deprecated
+
+Document in the driver that "renesas,cmt-48-gen2" is deprecated, but
+still supported for backward compatibility with old DTBs, cfr. commit
+4e18111ff38f0664 ("devicetree: bindings: Remove deprecated
+properties").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit 8d50e9476bb4aea53fca12637e71d950deafdf37)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index 8546736e3bc8..61a922509706 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -935,7 +935,11 @@ MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
+ 
+ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
+ 	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
+-	{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
++	{
++		/* deprecated, preserved for backward compatibility */
++		.compatible = "renesas,cmt-48-gen2",
++		.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
++	},
+ 	{ .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
+ 	{ .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
+ 	{ }
+-- 
+2.19.0
+
diff --git a/patches/0172-clocksource-drivers-sh_cmt-Remove-unused-renesas-cha.patch b/patches/0172-clocksource-drivers-sh_cmt-Remove-unused-renesas-cha.patch
new file mode 100644
index 00000000000000..f4cc2b094894cf
--- /dev/null
+++ b/patches/0172-clocksource-drivers-sh_cmt-Remove-unused-renesas-cha.patch
@@ -0,0 +1,62 @@
+From e71ce5c82311947f74c8634b4d4804048d695ba5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 18 Sep 2017 15:46:46 +0200
+Subject: [PATCH 0172/1795] clocksource/drivers/sh_cmt: Remove unused "renesas,
+ channels-mask" handling
+
+The in-driver channel configuration in sh_cmt_info.channels_mask is now
+always set for all CMT devices instantiated from DT.
+
+Hence the "renesas,channels-mask" property is no longer checked, and its
+handling can be removed, cfr. commit 4e18111ff38f0664 ("devicetree:
+bindings: Remove deprecated properties").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit d1d285972e24b63eeee8118359dcd4c451b295c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 18 +-----------------
+ 1 file changed, 1 insertion(+), 17 deletions(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index 61a922509706..89c514cf59a4 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -946,14 +946,6 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
+ };
+ MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
+ 
+-static int sh_cmt_parse_dt(struct sh_cmt_device *cmt)
+-{
+-	struct device_node *np = cmt->pdev->dev.of_node;
+-
+-	return of_property_read_u32(np, "renesas,channels-mask",
+-				    &cmt->hw_channels);
+-}
+-
+ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
+ {
+ 	unsigned int mask;
+@@ -968,15 +960,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
+ 
+ 		id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
+ 		cmt->info = id->data;
+-
+-		/* prefer in-driver channel configuration over DT */
+-		if (cmt->info->channels_mask) {
+-			cmt->hw_channels = cmt->info->channels_mask;
+-		} else {
+-			ret = sh_cmt_parse_dt(cmt);
+-			if (ret < 0)
+-				return ret;
+-		}
++		cmt->hw_channels = cmt->info->channels_mask;
+ 	} else if (pdev->dev.platform_data) {
+ 		struct sh_timer_config *cfg = pdev->dev.platform_data;
+ 		const struct platform_device_id *id = pdev->id_entry;
+-- 
+2.19.0
+
diff --git a/patches/0173-clocksource-drivers-sh_cmt-Use-of_device_get_match_d.patch b/patches/0173-clocksource-drivers-sh_cmt-Use-of_device_get_match_d.patch
new file mode 100644
index 00000000000000..9567c9d15efdbf
--- /dev/null
+++ b/patches/0173-clocksource-drivers-sh_cmt-Use-of_device_get_match_d.patch
@@ -0,0 +1,46 @@
+From 2e7ffb5bb7c54f689598c62d7be72a4aa8ac75b4 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 18 Sep 2017 15:46:47 +0200
+Subject: [PATCH 0173/1795] clocksource/drivers/sh_cmt: Use
+ of_device_get_match_data() helper
+
+Use the existing of_device_get_match_data() helper instead of
+open-coding its functionality.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+(cherry picked from commit 2d1d5172bf843fb44fcc7d3ff61501e9a6601e74)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clocksource/sh_cmt.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
+index 89c514cf59a4..70b3cf8e23d0 100644
+--- a/drivers/clocksource/sh_cmt.c
++++ b/drivers/clocksource/sh_cmt.c
+@@ -25,6 +25,7 @@
+ #include <linux/irq.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_runtime.h>
+@@ -956,10 +957,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
+ 	raw_spin_lock_init(&cmt->lock);
+ 
+ 	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
+-		const struct of_device_id *id;
+-
+-		id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
+-		cmt->info = id->data;
++		cmt->info = of_device_get_match_data(&pdev->dev);
+ 		cmt->hw_channels = cmt->info->channels_mask;
+ 	} else if (pdev->dev.platform_data) {
+ 		struct sh_timer_config *cfg = pdev->dev.platform_data;
+-- 
+2.19.0
+
diff --git a/patches/0174-sh-make-dma_cache_sync-a-no-op.patch b/patches/0174-sh-make-dma_cache_sync-a-no-op.patch
new file mode 100644
index 00000000000000..bc28c9e77d0f89
--- /dev/null
+++ b/patches/0174-sh-make-dma_cache_sync-a-no-op.patch
@@ -0,0 +1,176 @@
+From 6a0e135d500c5cfc1676464d1db13ea44385a7f9 Mon Sep 17 00:00:00 2001
+From: Christoph Hellwig <hch@lst.de>
+Date: Sun, 27 Aug 2017 10:35:40 +0200
+Subject: [PATCH 0174/1795] sh: make dma_cache_sync a no-op
+
+sh does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't
+make any sense to do any work in dma_cache_sync given that it
+must be a no-op when dma_alloc_attrs returns coherent memory.
+
+On the other hand sh uses dma_cache_sync internally in the dma_ops
+implementation and for the maple bus that does not use the DMA API,
+so a the old functionality for dma_cache_sync is still provided under
+the name sh_sync_dma_for_device, and without the redundant dev
+argument.  While at it two of the syncing dma_ops also go the proper
+_for_device postfix.
+
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Reviewed-by: Robin Murphy <robin.murphy@arm.com>
+(cherry picked from commit e0c6584df9c414b50de17e1abc1099f7501bbb60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/sh/include/asm/dma-mapping.h |  9 +++++++--
+ arch/sh/kernel/dma-nommu.c        | 17 +++++++++--------
+ arch/sh/mm/consistent.c           |  6 +++---
+ drivers/sh/maple/maple.c          |  5 ++---
+ 4 files changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h
+index 68c1536b3aab..edd8d7210c93 100644
+--- a/arch/sh/include/asm/dma-mapping.h
++++ b/arch/sh/include/asm/dma-mapping.h
+@@ -10,8 +10,10 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+ 	return dma_ops;
+ }
+ 
+-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+-		    enum dma_data_direction dir);
++static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
++		    enum dma_data_direction dir)
++{
++}
+ 
+ /* arch/sh/mm/consistent.c */
+ extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
+@@ -21,4 +23,7 @@ extern void dma_generic_free_coherent(struct device *dev, size_t size,
+ 				      void *vaddr, dma_addr_t dma_handle,
+ 				      unsigned long attrs);
+ 
++void sh_sync_dma_for_device(void *vaddr, size_t size,
++	    enum dma_data_direction dir);
++
+ #endif /* __ASM_SH_DMA_MAPPING_H */
+diff --git a/arch/sh/kernel/dma-nommu.c b/arch/sh/kernel/dma-nommu.c
+index d24c707b2181..62b485107eae 100644
+--- a/arch/sh/kernel/dma-nommu.c
++++ b/arch/sh/kernel/dma-nommu.c
+@@ -9,6 +9,7 @@
+  */
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
++#include <asm/cacheflush.h>
+ 
+ static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
+ 				 unsigned long offset, size_t size,
+@@ -20,7 +21,7 @@ static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
+ 	WARN_ON(size == 0);
+ 
+ 	if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+-		dma_cache_sync(dev, page_address(page) + offset, size, dir);
++		sh_sync_dma_for_device(page_address(page) + offset, size, dir);
+ 
+ 	return addr;
+ }
+@@ -38,7 +39,7 @@ static int nommu_map_sg(struct device *dev, struct scatterlist *sg,
+ 		BUG_ON(!sg_page(s));
+ 
+ 		if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+-			dma_cache_sync(dev, sg_virt(s), s->length, dir);
++			sh_sync_dma_for_device(sg_virt(s), s->length, dir);
+ 
+ 		s->dma_address = sg_phys(s);
+ 		s->dma_length = s->length;
+@@ -48,20 +49,20 @@ static int nommu_map_sg(struct device *dev, struct scatterlist *sg,
+ }
+ 
+ #ifdef CONFIG_DMA_NONCOHERENT
+-static void nommu_sync_single(struct device *dev, dma_addr_t addr,
++static void nommu_sync_single_for_device(struct device *dev, dma_addr_t addr,
+ 			      size_t size, enum dma_data_direction dir)
+ {
+-	dma_cache_sync(dev, phys_to_virt(addr), size, dir);
++	sh_sync_dma_for_device(phys_to_virt(addr), size, dir);
+ }
+ 
+-static void nommu_sync_sg(struct device *dev, struct scatterlist *sg,
++static void nommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+ 			  int nelems, enum dma_data_direction dir)
+ {
+ 	struct scatterlist *s;
+ 	int i;
+ 
+ 	for_each_sg(sg, s, nelems, i)
+-		dma_cache_sync(dev, sg_virt(s), s->length, dir);
++		sh_sync_dma_for_device(sg_virt(s), s->length, dir);
+ }
+ #endif
+ 
+@@ -71,8 +72,8 @@ const struct dma_map_ops nommu_dma_ops = {
+ 	.map_page		= nommu_map_page,
+ 	.map_sg			= nommu_map_sg,
+ #ifdef CONFIG_DMA_NONCOHERENT
+-	.sync_single_for_device	= nommu_sync_single,
+-	.sync_sg_for_device	= nommu_sync_sg,
++	.sync_single_for_device	= nommu_sync_single_for_device,
++	.sync_sg_for_device	= nommu_sync_sg_for_device,
+ #endif
+ 	.is_phys		= 1,
+ };
+diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
+index d1275adfa0ef..6ea3aab508f2 100644
+--- a/arch/sh/mm/consistent.c
++++ b/arch/sh/mm/consistent.c
+@@ -49,7 +49,7 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
+ 	 * Pages from the page allocator may have data present in
+ 	 * cache. So flush the cache before using uncached memory.
+ 	 */
+-	dma_cache_sync(dev, ret, size, DMA_BIDIRECTIONAL);
++	sh_sync_dma_for_device(ret, size, DMA_BIDIRECTIONAL);
+ 
+ 	ret_nocache = (void __force *)ioremap_nocache(virt_to_phys(ret), size);
+ 	if (!ret_nocache) {
+@@ -78,7 +78,7 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
+ 	iounmap(vaddr);
+ }
+ 
+-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
++void sh_sync_dma_for_device(void *vaddr, size_t size,
+ 		    enum dma_data_direction direction)
+ {
+ 	void *addr;
+@@ -100,7 +100,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+ 		BUG();
+ 	}
+ }
+-EXPORT_SYMBOL(dma_cache_sync);
++EXPORT_SYMBOL(sh_sync_dma_for_device);
+ 
+ static int __init memchunk_setup(char *str)
+ {
+diff --git a/drivers/sh/maple/maple.c b/drivers/sh/maple/maple.c
+index bec81c2404f7..7525039d812c 100644
+--- a/drivers/sh/maple/maple.c
++++ b/drivers/sh/maple/maple.c
+@@ -300,7 +300,7 @@ static void maple_send(void)
+ 	mutex_unlock(&maple_wlist_lock);
+ 	if (maple_packets > 0) {
+ 		for (i = 0; i < (1 << MAPLE_DMA_PAGES); i++)
+-			dma_cache_sync(0, maple_sendbuf + i * PAGE_SIZE,
++			sh_sync_dma_for_device(maple_sendbuf + i * PAGE_SIZE,
+ 				       PAGE_SIZE, DMA_BIDIRECTIONAL);
+ 	}
+ 
+@@ -642,8 +642,7 @@ static void maple_dma_handler(struct work_struct *work)
+ 		list_for_each_entry_safe(mq, nmq, &maple_sentq, list) {
+ 			mdev = mq->dev;
+ 			recvbuf = mq->recvbuf->buf;
+-			dma_cache_sync(&mdev->dev, recvbuf, 0x400,
+-				DMA_FROM_DEVICE);
++			sh_sync_dma_for_device(recvbuf, 0x400, DMA_FROM_DEVICE);
+ 			code = recvbuf[0];
+ 			kfree(mq->sendbuf);
+ 			list_del_init(&mq->list);
+-- 
+2.19.0
+
diff --git a/patches/0175-dt-bindings-net-sh_eth-add-R-Car-Gen-12-fallback-com.patch b/patches/0175-dt-bindings-net-sh_eth-add-R-Car-Gen-12-fallback-com.patch
new file mode 100644
index 00000000000000..e2f29dcc405b52
--- /dev/null
+++ b/patches/0175-dt-bindings-net-sh_eth-add-R-Car-Gen-12-fallback-com.patch
@@ -0,0 +1,79 @@
+From 6f927274a3091de07f06affdd564a16545a326a7 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:21:26 +0200
+Subject: [PATCH 0175/1795] dt-bindings: net: sh_eth: add R-Car Gen[12]
+ fallback compatibility strings
+
+Add fallback compatibility strings for R-Car Gen 1 and 2.
+
+In the case of Renesas R-Car hardware we know that there are generations of
+SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
+between IP blocks might be. For example, I believe that r8a7790 is older
+than r8a7791 but that doesn't imply that the latter is a descendant of the
+former or vice versa.
+
+We can, however, by examining the documentation and behaviour of the
+hardware at run-time observe that the current driver implementation appears
+to be compatible with the IP blocks on SoCs within a given generation.
+
+For the above reasons and convenience when enabling new SoCs a
+per-generation fallback compatibility string scheme is being adopted for
+drivers for Renesas SoCs.
+
+Note that R-Car Gen2 and RZ/G1 have many compatible IP blocks.  The
+approach that has been consistently taken for other IP blocks is to name
+common code, compatibility strings and so on after R-Car Gen2.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 87d9fa647020fb65985ec08826f6c77b9b4084af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/sh_eth.txt | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt
+index 0115c85a2425..5172799a7f1a 100644
+--- a/Documentation/devicetree/bindings/net/sh_eth.txt
++++ b/Documentation/devicetree/bindings/net/sh_eth.txt
+@@ -4,7 +4,8 @@ This file provides information on what the device node for the SH EtherMAC
+ interface contains.
+ 
+ Required properties:
+-- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
++- compatible: Must contain one or more of the following:
++	      "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
+ 	      "renesas,ether-r8a7743"  if the device is a part of R8A7743 SoC.
+ 	      "renesas,ether-r8a7745"  if the device is a part of R8A7745 SoC.
+ 	      "renesas,ether-r8a7778"  if the device is a part of R8A7778 SoC.
+@@ -14,6 +15,14 @@ Required properties:
+ 	      "renesas,ether-r8a7793"  if the device is a part of R8A7793 SoC.
+ 	      "renesas,ether-r8a7794"  if the device is a part of R8A7794 SoC.
+ 	      "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
++	      "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
++	      "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
++	                                device.
++
++	      When compatible with the generic version, nodes must list
++	      the SoC-specific version corresponding to the platform
++	      first followed by the generic version.
++
+ - reg: offset and length of (1) the E-DMAC/feLic register block (required),
+        (2) the TSU register block (optional).
+ - interrupts: interrupt specifier for the sole interrupt.
+@@ -36,7 +45,8 @@ Optional properties:
+ Example (Lager board):
+ 
+ 	ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7790";
++		compatible = "renesas,ether-r8a7790",
++		             "renesas,rcar-gen2-ether";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupt-parent = <&gic>;
+ 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0176-net-sh_eth-rename-name-structures-as-rcar_gen-12-_.patch b/patches/0176-net-sh_eth-rename-name-structures-as-rcar_gen-12-_.patch
new file mode 100644
index 00000000000000..a4ce0199dff9b9
--- /dev/null
+++ b/patches/0176-net-sh_eth-rename-name-structures-as-rcar_gen-12-_.patch
@@ -0,0 +1,99 @@
+From 97a6de8ceef89fec74e4a999f9d1260e1654d501 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:21:27 +0200
+Subject: [PATCH 0176/1795] net: sh_eth: rename name structures as
+ rcar_gen[12]_*
+
+Rename structures describing R-Car SoCs as rcar_gen[12]_*
+rather than r8a77[79]x_*. This seems a little easier on the
+eyes. And will make things slightly cleaner in a follow-up
+patch that adds fallback-compatibility strings for these SoCs.
+
+Note that R-Car Gen2 and RZ/G1 have many compatible IP blocks.  The
+approach that has been consistently taken for other IP blocks is to name
+common code, compatibility strings and so on after R-Car Gen2.
+
+Also rename sh_eth_set_rate_r8a777x as sh_eth_set_rate_rcar as
+it it is used by the R-Car generations supported by the driver.
+
+This patch should have no run-time effect and
+is compile-tested only.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 6c4b2f7e675cf11587182f51adcf0e129005e2f9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 30 +++++++++++++--------------
+ 1 file changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index abfb9faadbc4..eee9a6ee349c 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -594,7 +594,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
+ };
+ 
+ /* There is CPU dependent code */
+-static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
++static void sh_eth_set_rate_rcar(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+ 
+@@ -608,10 +608,10 @@ static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
+ 	}
+ }
+ 
+-/* R8A7778/9 */
+-static struct sh_eth_cpu_data r8a777x_data = {
++/* R-Car Gen1 */
++static struct sh_eth_cpu_data rcar_gen1_data = {
+ 	.set_duplex	= sh_eth_set_duplex,
+-	.set_rate	= sh_eth_set_rate_r8a777x,
++	.set_rate	= sh_eth_set_rate_rcar,
+ 
+ 	.register_type	= SH_ETH_REG_FAST_RCAR,
+ 
+@@ -635,10 +635,10 @@ static struct sh_eth_cpu_data r8a777x_data = {
+ 	.hw_swap	= 1,
+ };
+ 
+-/* R8A7790/1 */
+-static struct sh_eth_cpu_data r8a779x_data = {
++/* R-Car Gen2 and RZ/G1 */
++static struct sh_eth_cpu_data rcar_gen2_data = {
+ 	.set_duplex	= sh_eth_set_duplex,
+-	.set_rate	= sh_eth_set_rate_r8a777x,
++	.set_rate	= sh_eth_set_rate_rcar,
+ 
+ 	.register_type	= SH_ETH_REG_FAST_RCAR,
+ 
+@@ -3063,14 +3063,14 @@ static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
+ 
+ static const struct of_device_id sh_eth_match_table[] = {
+ 	{ .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
+-	{ .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
+-	{ .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
+-	{ .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
+-	{ .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
+-	{ .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
+-	{ .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
+-	{ .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
+-	{ .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
++	{ .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
++	{ .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
++	{ .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
+ 	{ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/0177-net-sh_eth-implement-R-Car-Gen-12-fallback-compatibi.patch b/patches/0177-net-sh_eth-implement-R-Car-Gen-12-fallback-compatibi.patch
new file mode 100644
index 00000000000000..615d433178dda4
--- /dev/null
+++ b/patches/0177-net-sh_eth-implement-R-Car-Gen-12-fallback-compatibi.patch
@@ -0,0 +1,53 @@
+From c488f818341a4ade580282bc627c18fe99cb2aad Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:21:28 +0200
+Subject: [PATCH 0177/1795] net: sh_eth: implement R-Car Gen[12] fallback
+ compatibility strings
+
+Implement fallback compatibility strings for R-Car Gen 1 and 2.
+
+In the case of Renesas R-Car hardware we know that there are generations of
+SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
+between IP blocks might be. For example, I believe that r8a7790 is older
+than r8a7791 but that doesn't imply that the latter is a descendant of the
+former or vice versa.
+
+We can, however, by examining the documentation and behaviour of the
+hardware at run-time observe that the current driver implementation appears
+to be compatible with the IP blocks on SoCs within a given generation.
+
+For the above reasons and convenience when enabling new SoCs a
+per-generation fallback compatibility string scheme is being adopted for
+drivers for Renesas SoCs.
+
+Note that R-Car Gen2 and RZ/G1 have many compatible IP blocks.  The
+approach that has been consistently taken for other IP blocks is to name
+common code, compatibility strings and so on after R-Car Gen2.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit b4804e0c71c144b673b6c53ca4acfcac6eb98704)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index eee9a6ee349c..987d10c2c36c 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -3072,6 +3072,8 @@ static const struct of_device_id sh_eth_match_table[] = {
+ 	{ .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
++	{ .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
++	{ .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sh_eth_match_table);
+-- 
+2.19.0
+
diff --git a/patches/0178-net-sh_eth-use-correct-struct-device-when-calling-DM.patch b/patches/0178-net-sh_eth-use-correct-struct-device-when-calling-DM.patch
new file mode 100644
index 00000000000000..f3fd63d48eaa82
--- /dev/null
+++ b/patches/0178-net-sh_eth-use-correct-struct-device-when-calling-DM.patch
@@ -0,0 +1,104 @@
+From 4930f3fef598df1a9e14750dbbd6a893bea77f5d Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Mon, 4 Dec 2017 14:33:26 +0100
+Subject: [PATCH 0178/1795] net: sh_eth: use correct "struct device" when
+ calling DMA mapping functions
+
+There are two types of "struct device": the one representing the
+physical device on its physical bus (platform, SPI, PCI, etc.), and
+the one representing the logical device in its device class (net,
+etc.).
+
+The DMA mapping API expects to receive as argument a "struct device"
+representing the physical device, as the "struct device" contains
+information about the bus that the DMA API needs.
+
+However, the sh_eth driver mistakenly uses the "struct device"
+representing the logical device (embedded in "struct net_device")
+rather than the "struct device" representing the physical device on
+its bus.
+
+This commit fixes that by adjusting all calls to the DMA mapping API.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 22c1aed4093a605b120d6e566620364843a318ed)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 987d10c2c36c..31d8f943383d 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1153,7 +1153,8 @@ static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
+ 			   entry, le32_to_cpu(txdesc->status));
+ 		/* Free the original skb. */
+ 		if (mdp->tx_skbuff[entry]) {
+-			dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
++			dma_unmap_single(&mdp->pdev->dev,
++					 le32_to_cpu(txdesc->addr),
+ 					 le32_to_cpu(txdesc->len) >> 16,
+ 					 DMA_TO_DEVICE);
+ 			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
+@@ -1183,7 +1184,7 @@ static void sh_eth_ring_free(struct net_device *ndev)
+ 			if (mdp->rx_skbuff[i]) {
+ 				struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
+ 
+-				dma_unmap_single(&ndev->dev,
++				dma_unmap_single(&mdp->pdev->dev,
+ 						 le32_to_cpu(rxdesc->addr),
+ 						 ALIGN(mdp->rx_buf_sz, 32),
+ 						 DMA_FROM_DEVICE);
+@@ -1249,9 +1250,9 @@ static void sh_eth_ring_format(struct net_device *ndev)
+ 
+ 		/* The size of the buffer is a multiple of 32 bytes. */
+ 		buf_len = ALIGN(mdp->rx_buf_sz, 32);
+-		dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
++		dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
+ 					  DMA_FROM_DEVICE);
+-		if (dma_mapping_error(&ndev->dev, dma_addr)) {
++		if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
+ 			kfree_skb(skb);
+ 			break;
+ 		}
+@@ -1531,7 +1532,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
+ 			mdp->rx_skbuff[entry] = NULL;
+ 			if (mdp->cd->rpadir)
+ 				skb_reserve(skb, NET_IP_ALIGN);
+-			dma_unmap_single(&ndev->dev, dma_addr,
++			dma_unmap_single(&mdp->pdev->dev, dma_addr,
+ 					 ALIGN(mdp->rx_buf_sz, 32),
+ 					 DMA_FROM_DEVICE);
+ 			skb_put(skb, pkt_len);
+@@ -1559,9 +1560,9 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
+ 			if (skb == NULL)
+ 				break;	/* Better luck next round. */
+ 			sh_eth_set_receive_align(skb);
+-			dma_addr = dma_map_single(&ndev->dev, skb->data,
++			dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
+ 						  buf_len, DMA_FROM_DEVICE);
+-			if (dma_mapping_error(&ndev->dev, dma_addr)) {
++			if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
+ 				kfree_skb(skb);
+ 				break;
+ 			}
+@@ -2418,9 +2419,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+ 	/* soft swap. */
+ 	if (!mdp->cd->hw_swap)
+ 		sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
+-	dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
++	dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
+ 				  DMA_TO_DEVICE);
+-	if (dma_mapping_error(&ndev->dev, dma_addr)) {
++	if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
+ 		kfree_skb(skb);
+ 		return NETDEV_TX_OK;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/0179-net-sh_eth-don-t-use-NULL-as-struct-device-for-the-D.patch b/patches/0179-net-sh_eth-don-t-use-NULL-as-struct-device-for-the-D.patch
new file mode 100644
index 00000000000000..eb983c6f8f2031
--- /dev/null
+++ b/patches/0179-net-sh_eth-don-t-use-NULL-as-struct-device-for-the-D.patch
@@ -0,0 +1,69 @@
+From e315e56ee98299a3fc510d920c823938efba23e8 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Mon, 4 Dec 2017 14:33:27 +0100
+Subject: [PATCH 0179/1795] net: sh_eth: don't use NULL as "struct device" for
+ the DMA mapping API
+
+Using NULL as argument for the DMA mapping API is bogus, as the DMA
+mapping API may use information from the "struct device" to perform
+the DMA mapping operation. Therefore, pass the appropriate "struct
+device".
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 573500dbf0f2756947517c1d4f942767dbf16dcc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 31d8f943383d..158ebe520505 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1191,7 +1191,7 @@ static void sh_eth_ring_free(struct net_device *ndev)
+ 			}
+ 		}
+ 		ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
+-		dma_free_coherent(NULL, ringsize, mdp->rx_ring,
++		dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
+ 				  mdp->rx_desc_dma);
+ 		mdp->rx_ring = NULL;
+ 	}
+@@ -1208,7 +1208,7 @@ static void sh_eth_ring_free(struct net_device *ndev)
+ 		sh_eth_tx_free(ndev, false);
+ 
+ 		ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
+-		dma_free_coherent(NULL, ringsize, mdp->tx_ring,
++		dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
+ 				  mdp->tx_desc_dma);
+ 		mdp->tx_ring = NULL;
+ 	}
+@@ -1328,8 +1328,8 @@ static int sh_eth_ring_init(struct net_device *ndev)
+ 
+ 	/* Allocate all Rx descriptors. */
+ 	rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
+-	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
+-					  GFP_KERNEL);
++	mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
++					  &mdp->rx_desc_dma, GFP_KERNEL);
+ 	if (!mdp->rx_ring)
+ 		goto ring_free;
+ 
+@@ -1337,8 +1337,8 @@ static int sh_eth_ring_init(struct net_device *ndev)
+ 
+ 	/* Allocate all Tx descriptors. */
+ 	tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
+-	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
+-					  GFP_KERNEL);
++	mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
++					  &mdp->tx_desc_dma, GFP_KERNEL);
+ 	if (!mdp->tx_ring)
+ 		goto ring_free;
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0180-net-sh_eth-do-not-advertise-Gigabit-capabilities-whe.patch b/patches/0180-net-sh_eth-do-not-advertise-Gigabit-capabilities-whe.patch
new file mode 100644
index 00000000000000..38b24356586603
--- /dev/null
+++ b/patches/0180-net-sh_eth-do-not-advertise-Gigabit-capabilities-whe.patch
@@ -0,0 +1,51 @@
+From 0ba20eabb7ad1b40df3d547b787700a1dcbd71d3 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 8 Dec 2017 16:35:40 +0100
+Subject: [PATCH 0180/1795] net: sh_eth: do not advertise Gigabit capabilities
+ when not available
+
+Not all variants of the sh_eth hardware have Gigabit
+support. Unfortunately, the current driver doesn't tell the PHY about
+the limited MAC capabilities. Due to this, if you have a Gigabit
+capable PHY, the PHY will advertise its Gigabit capability and
+establish a link at 1Gbit/s, even though the MAC doesn't support it.
+
+In order to avoid this, we use the recently introduced
+phy_set_max_speed() to tell the PHY to not advertise speed higher than
+100 MBit/s.
+
+Tested on a SH7786 platform, with a Gigabit PHY.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 2aab6b40b03154a263463a5d992ddd7d122a016a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 158ebe520505..00e2c2bc4693 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1906,6 +1906,16 @@ static int sh_eth_phy_init(struct net_device *ndev)
+ 		return PTR_ERR(phydev);
+ 	}
+ 
++	/* mask with MAC supported features */
++	if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
++		int err = phy_set_max_speed(phydev, SPEED_100);
++		if (err) {
++			netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
++			phy_disconnect(phydev);
++			return err;
++		}
++	}
++
+ 	phy_attached_info(phydev);
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0181-sh_eth-fix-TXALCR1-offsets.patch b/patches/0181-sh_eth-fix-TXALCR1-offsets.patch
new file mode 100644
index 00000000000000..6e8565e46000b9
--- /dev/null
+++ b/patches/0181-sh_eth-fix-TXALCR1-offsets.patch
@@ -0,0 +1,44 @@
+From 3cb67542dc391e5f5300572f3eba1327d56256cc Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 7 Jan 2018 00:26:47 +0300
+Subject: [PATCH 0181/1795] sh_eth: fix TXALCR1 offsets
+
+The  TXALCR1 offsets are incorrect in the register offset tables, most
+probably due to copy&paste error.  Luckily, the driver never uses this
+register. :-)
+
+Fixes: 4a55530f38e4 ("net: sh_eth: modify the definitions of register")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 50f3d740d376f664f6accc7e86c9afd8f1c7e1e4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 00e2c2bc4693..4721130d6cd3 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -147,7 +147,7 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[FWNLCR0]	= 0x0090,
+ 	[FWALCR0]	= 0x0094,
+ 	[TXNLCR1]	= 0x00a0,
+-	[TXALCR1]	= 0x00a0,
++	[TXALCR1]	= 0x00a4,
+ 	[RXNLCR1]	= 0x00a8,
+ 	[RXALCR1]	= 0x00ac,
+ 	[FWNLCR1]	= 0x00b0,
+@@ -399,7 +399,7 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[FWNLCR0]	= 0x0090,
+ 	[FWALCR0]	= 0x0094,
+ 	[TXNLCR1]	= 0x00a0,
+-	[TXALCR1]	= 0x00a0,
++	[TXALCR1]	= 0x00a4,
+ 	[RXNLCR1]	= 0x00a8,
+ 	[RXALCR1]	= 0x00ac,
+ 	[FWNLCR1]	= 0x00b0,
+-- 
+2.19.0
+
diff --git a/patches/0182-sh_eth-fix-dumping-ARSTR.patch b/patches/0182-sh_eth-fix-dumping-ARSTR.patch
new file mode 100644
index 00000000000000..492fffa7624975
--- /dev/null
+++ b/patches/0182-sh_eth-fix-dumping-ARSTR.patch
@@ -0,0 +1,37 @@
+From 7f8dd42b9ccb3011aefca6b1d043fdd771217776 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 13 Jan 2018 20:22:01 +0300
+Subject: [PATCH 0182/1795] sh_eth: fix dumping ARSTR
+
+ARSTR  is always located at the start of the TSU register region, thus
+using add_reg()  instead of add_tsu_reg() in __sh_eth_get_regs() to dump it
+causes EDMR or EDSR (depending on the register layout) to be dumped instead
+of ARSTR.  Use the correct condition/macro there...
+
+Fixes: 6b4b4fead342 ("sh_eth: Implement ethtool register dump operations")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 17d0fb0caa68f2bfd8aaa8125ff15abebfbfa1d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 4721130d6cd3..007f54b5766b 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2074,8 +2074,8 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
+ 		add_reg(CSMR);
+ 	if (cd->select_mii)
+ 		add_reg(RMII_MII);
+-	add_reg(ARSTR);
+ 	if (cd->tsu) {
++		add_tsu_reg(ARSTR);
+ 		add_tsu_reg(TSU_CTRST);
+ 		add_tsu_reg(TSU_FWEN0);
+ 		add_tsu_reg(TSU_FWEN1);
+-- 
+2.19.0
+
diff --git a/patches/0183-mtd-nand-sh_flctl-Use-of_device_get_match_data-helpe.patch b/patches/0183-mtd-nand-sh_flctl-Use-of_device_get_match_data-helpe.patch
new file mode 100644
index 00000000000000..12628db967cb6b
--- /dev/null
+++ b/patches/0183-mtd-nand-sh_flctl-Use-of_device_get_match_data-helpe.patch
@@ -0,0 +1,43 @@
+From 3abf36472ac08f2fbec6d7145e9be3050608486c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:19:03 +0200
+Subject: [PATCH 0183/1795] mtd: nand: sh_flctl: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+While at it, make config const so the cast can be dropped.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+(cherry picked from commit b8640c5b8bef7e24fe54d2713f4c91b563a65c55)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mtd/nand/sh_flctl.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
+index e7f3c98487e6..3c5008a4f5f3 100644
+--- a/drivers/mtd/nand/sh_flctl.c
++++ b/drivers/mtd/nand/sh_flctl.c
+@@ -1094,14 +1094,11 @@ MODULE_DEVICE_TABLE(of, of_flctl_match);
+ 
+ static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
+ {
+-	const struct of_device_id *match;
+-	struct flctl_soc_config *config;
++	const struct flctl_soc_config *config;
+ 	struct sh_flctl_platform_data *pdata;
+ 
+-	match = of_match_device(of_flctl_match, dev);
+-	if (match)
+-		config = (struct flctl_soc_config *)match->data;
+-	else {
++	config = of_device_get_match_data(dev);
++	if (!config) {
+ 		dev_err(dev, "%s: no OF configuration attached\n", __func__);
+ 		return NULL;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/0184-spi-sh-msiof-Add-compatible-strings-for-r8a774-35.patch b/patches/0184-spi-sh-msiof-Add-compatible-strings-for-r8a774-35.patch
new file mode 100644
index 00000000000000..67e0eb3d93fd22
--- /dev/null
+++ b/patches/0184-spi-sh-msiof-Add-compatible-strings-for-r8a774-35.patch
@@ -0,0 +1,31 @@
+From ea1a5b10fb87e748a5bbd4f86a5c77964c58de46 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 25 Sep 2017 09:54:19 +0100
+Subject: [PATCH 0184/1795] spi: sh-msiof: Add compatible strings for
+ r8a774[35]
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit bdacfc7b6216dd30d07c10732fd4c0a660c62853)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-sh-msiof.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index 0fea18ab970e..aa34f5ef53f7 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -1047,6 +1047,8 @@ static const struct sh_msiof_chipdata rcar_gen3_data = {
+ 
+ static const struct of_device_id sh_msiof_match[] = {
+ 	{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
++	{ .compatible = "renesas,msiof-r8a7743",   .data = &rcar_gen2_data },
++	{ .compatible = "renesas,msiof-r8a7745",   .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,msiof-r8a7790",   .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,msiof-r8a7791",   .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,msiof-r8a7792",   .data = &rcar_gen2_data },
+-- 
+2.19.0
+
diff --git a/patches/0185-spi-sh-msiof-Add-r8a774-35-to-the-compatible-list.patch b/patches/0185-spi-sh-msiof-Add-r8a774-35-to-the-compatible-list.patch
new file mode 100644
index 00000000000000..43f2556b9e8c23
--- /dev/null
+++ b/patches/0185-spi-sh-msiof-Add-r8a774-35-to-the-compatible-list.patch
@@ -0,0 +1,43 @@
+From 67bd6ef78195fed562d14ec70a22d9463c81aced Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 25 Sep 2017 09:54:20 +0100
+Subject: [PATCH 0185/1795] spi: sh-msiof: Add r8a774[35] to the compatible
+ list
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 4702f4b23a2fc6196abacf515a959e69176da40e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/spi/sh-msiof.txt | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
+index e865855726a2..bdd83959019c 100644
+--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
++++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
+@@ -1,7 +1,9 @@
+ Renesas MSIOF spi controller
+ 
+ Required properties:
+-- compatible           : "renesas,msiof-r8a7790" (R-Car H2)
++- compatible           : "renesas,msiof-r8a7743" (RZ/G1M)
++			 "renesas,msiof-r8a7745" (RZ/G1E)
++			 "renesas,msiof-r8a7790" (R-Car H2)
+ 			 "renesas,msiof-r8a7791" (R-Car M2-W)
+ 			 "renesas,msiof-r8a7792" (R-Car V2H)
+ 			 "renesas,msiof-r8a7793" (R-Car M2-N)
+@@ -10,7 +12,7 @@ Required properties:
+ 			 "renesas,msiof-r8a7796" (R-Car M3-W)
+ 			 "renesas,msiof-sh73a0" (SH-Mobile AG5)
+ 			 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
+-			 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
++			 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
+ 			 "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
+ 			 "renesas,sh-msiof"      (deprecated)
+ 
+-- 
+2.19.0
+
diff --git a/patches/0186-spi-sh-msiof-Use-of_device_get_match_data-helper.patch b/patches/0186-spi-sh-msiof-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..db948783f681ca
--- /dev/null
+++ b/patches/0186-spi-sh-msiof-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,42 @@
+From b0e0fa15176857c986e87d38c2f45a4bbf495b5a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:20:27 +0200
+Subject: [PATCH 0186/1795] spi: sh-msiof: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit ecb1596aa27856a256b0698a93d7be06ce041e73)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-sh-msiof.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index aa34f5ef53f7..a6e0c9cee35d 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -1237,15 +1237,13 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
+ 	struct resource	*r;
+ 	struct spi_master *master;
+ 	const struct sh_msiof_chipdata *chipdata;
+-	const struct of_device_id *of_id;
+ 	struct sh_msiof_spi_info *info;
+ 	struct sh_msiof_spi_priv *p;
+ 	int i;
+ 	int ret;
+ 
+-	of_id = of_match_device(sh_msiof_match, &pdev->dev);
+-	if (of_id) {
+-		chipdata = of_id->data;
++	chipdata = of_device_get_match_data(&pdev->dev);
++	if (chipdata) {
+ 		info = sh_msiof_spi_parse_dt(&pdev->dev);
+ 	} else {
+ 		chipdata = (const void *)pdev->id_entry->driver_data;
+-- 
+2.19.0
+
diff --git a/patches/0187-spi-sh-msiof-remove-redundant-pointer-dev.patch b/patches/0187-spi-sh-msiof-remove-redundant-pointer-dev.patch
new file mode 100644
index 00000000000000..673eb6fa97e32c
--- /dev/null
+++ b/patches/0187-spi-sh-msiof-remove-redundant-pointer-dev.patch
@@ -0,0 +1,40 @@
+From c4729360f48c1d6fa951886b6be638a1d106c37d Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 3 Nov 2017 13:58:29 +0000
+Subject: [PATCH 0187/1795] spi: sh-msiof: remove redundant pointer dev
+
+The pointer dev is assigned but never read, hence it is redundant
+and can be removed. Cleans up clang warning:
+
+drivers/spi/spi-sh-msiof.c:1198:2: warning: Value stored to 'dev'
+is never read
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 6ae6678344af52cf1c05475ff3ec2f43b8b532ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-sh-msiof.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index a6e0c9cee35d..e607e224bb7c 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -1216,12 +1216,10 @@ static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
+ static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
+ {
+ 	struct spi_master *master = p->master;
+-	struct device *dev;
+ 
+ 	if (!master->dma_tx)
+ 		return;
+ 
+-	dev = &p->pdev->dev;
+ 	dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
+ 			 PAGE_SIZE, DMA_FROM_DEVICE);
+ 	dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
+-- 
+2.19.0
+
diff --git a/patches/0188-pinctrl-sh-pfc-r8a7795-Add-SDHI0-3-support.patch b/patches/0188-pinctrl-sh-pfc-r8a7795-Add-SDHI0-3-support.patch
new file mode 100644
index 00000000000000..27546bed02eda9
--- /dev/null
+++ b/patches/0188-pinctrl-sh-pfc-r8a7795-Add-SDHI0-3-support.patch
@@ -0,0 +1,329 @@
+From 1fdf80b6555193fb86504b5d2e522b4ab4a7f231 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Tue, 29 Aug 2017 17:51:57 +0200
+Subject: [PATCH 0188/1795] pinctrl: sh-pfc: r8a7795: Add SDHI0-3 support
+
+Add SDHI0-3 support for R-Car H3 ES2.0 based on a patch from the Renesas
+BSP. SDHI pin config is identical to H3 ES1.*.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9ed139586923becc4741c609304eecad6d5ffe53)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 275 +++++++++++++++++++++++++++
+ 1 file changed, 275 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 8b35772cda98..b225bc2f9bea 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2734,6 +2734,213 @@ static const unsigned int scif5_clk_b_mux[] = {
+ 	SCK5_B_MARK,
+ };
+ 
++/* - SDHI0 ------------------------------------------------------------------ */
++static const unsigned int sdhi0_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 2),
++};
++static const unsigned int sdhi0_data1_mux[] = {
++	SD0_DAT0_MARK,
++};
++static const unsigned int sdhi0_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++};
++static const unsigned int sdhi0_data4_mux[] = {
++	SD0_DAT0_MARK, SD0_DAT1_MARK,
++	SD0_DAT2_MARK, SD0_DAT3_MARK,
++};
++static const unsigned int sdhi0_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
++};
++static const unsigned int sdhi0_ctrl_mux[] = {
++	SD0_CLK_MARK, SD0_CMD_MARK,
++};
++static const unsigned int sdhi0_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 12),
++};
++static const unsigned int sdhi0_cd_mux[] = {
++	SD0_CD_MARK,
++};
++static const unsigned int sdhi0_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 13),
++};
++static const unsigned int sdhi0_wp_mux[] = {
++	SD0_WP_MARK,
++};
++/* - SDHI1 ------------------------------------------------------------------ */
++static const unsigned int sdhi1_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int sdhi1_data1_mux[] = {
++	SD1_DAT0_MARK,
++};
++static const unsigned int sdhi1_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int sdhi1_data4_mux[] = {
++	SD1_DAT0_MARK, SD1_DAT1_MARK,
++	SD1_DAT2_MARK, SD1_DAT3_MARK,
++};
++static const unsigned int sdhi1_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int sdhi1_ctrl_mux[] = {
++	SD1_CLK_MARK, SD1_CMD_MARK,
++};
++static const unsigned int sdhi1_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 14),
++};
++static const unsigned int sdhi1_cd_mux[] = {
++	SD1_CD_MARK,
++};
++static const unsigned int sdhi1_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 15),
++};
++static const unsigned int sdhi1_wp_mux[] = {
++	SD1_WP_MARK,
++};
++/* - SDHI2 ------------------------------------------------------------------ */
++static const unsigned int sdhi2_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(4, 2),
++};
++static const unsigned int sdhi2_data1_mux[] = {
++	SD2_DAT0_MARK,
++};
++static const unsigned int sdhi2_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int sdhi2_data4_mux[] = {
++	SD2_DAT0_MARK, SD2_DAT1_MARK,
++	SD2_DAT2_MARK, SD2_DAT3_MARK,
++};
++static const unsigned int sdhi2_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
++	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
++	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int sdhi2_data8_mux[] = {
++	SD2_DAT0_MARK, SD2_DAT1_MARK,
++	SD2_DAT2_MARK, SD2_DAT3_MARK,
++	SD2_DAT4_MARK, SD2_DAT5_MARK,
++	SD2_DAT6_MARK, SD2_DAT7_MARK,
++};
++static const unsigned int sdhi2_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
++};
++static const unsigned int sdhi2_ctrl_mux[] = {
++	SD2_CLK_MARK, SD2_CMD_MARK,
++};
++static const unsigned int sdhi2_cd_a_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(4, 13),
++};
++static const unsigned int sdhi2_cd_a_mux[] = {
++	SD2_CD_A_MARK,
++};
++static const unsigned int sdhi2_cd_b_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(5, 10),
++};
++static const unsigned int sdhi2_cd_b_mux[] = {
++	SD2_CD_B_MARK,
++};
++static const unsigned int sdhi2_wp_a_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(4, 14),
++};
++static const unsigned int sdhi2_wp_a_mux[] = {
++	SD2_WP_A_MARK,
++};
++static const unsigned int sdhi2_wp_b_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(5, 11),
++};
++static const unsigned int sdhi2_wp_b_mux[] = {
++	SD2_WP_B_MARK,
++};
++static const unsigned int sdhi2_ds_pins[] = {
++	/* DS */
++	RCAR_GP_PIN(4, 6),
++};
++static const unsigned int sdhi2_ds_mux[] = {
++	SD2_DS_MARK,
++};
++/* - SDHI3 ------------------------------------------------------------------ */
++static const unsigned int sdhi3_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(4, 9),
++};
++static const unsigned int sdhi3_data1_mux[] = {
++	SD3_DAT0_MARK,
++};
++static const unsigned int sdhi3_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
++	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
++};
++static const unsigned int sdhi3_data4_mux[] = {
++	SD3_DAT0_MARK, SD3_DAT1_MARK,
++	SD3_DAT2_MARK, SD3_DAT3_MARK,
++};
++static const unsigned int sdhi3_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
++	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
++	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
++	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
++};
++static const unsigned int sdhi3_data8_mux[] = {
++	SD3_DAT0_MARK, SD3_DAT1_MARK,
++	SD3_DAT2_MARK, SD3_DAT3_MARK,
++	SD3_DAT4_MARK, SD3_DAT5_MARK,
++	SD3_DAT6_MARK, SD3_DAT7_MARK,
++};
++static const unsigned int sdhi3_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
++};
++static const unsigned int sdhi3_ctrl_mux[] = {
++	SD3_CLK_MARK, SD3_CMD_MARK,
++};
++static const unsigned int sdhi3_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(4, 15),
++};
++static const unsigned int sdhi3_cd_mux[] = {
++	SD3_CD_MARK,
++};
++static const unsigned int sdhi3_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(4, 16),
++};
++static const unsigned int sdhi3_wp_mux[] = {
++	SD3_WP_MARK,
++};
++static const unsigned int sdhi3_ds_pins[] = {
++	/* DS */
++	RCAR_GP_PIN(4, 17),
++};
++static const unsigned int sdhi3_ds_mux[] = {
++	SD3_DS_MARK,
++};
++
+ /* - SCIF Clock ------------------------------------------------------------- */
+ static const unsigned int scif_clk_a_pins[] = {
+ 	/* SCIF_CLK */
+@@ -2943,6 +3150,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif5_clk_b),
+ 	SH_PFC_PIN_GROUP(scif_clk_a),
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(sdhi0_data1),
++	SH_PFC_PIN_GROUP(sdhi0_data4),
++	SH_PFC_PIN_GROUP(sdhi0_ctrl),
++	SH_PFC_PIN_GROUP(sdhi0_cd),
++	SH_PFC_PIN_GROUP(sdhi0_wp),
++	SH_PFC_PIN_GROUP(sdhi1_data1),
++	SH_PFC_PIN_GROUP(sdhi1_data4),
++	SH_PFC_PIN_GROUP(sdhi1_ctrl),
++	SH_PFC_PIN_GROUP(sdhi1_cd),
++	SH_PFC_PIN_GROUP(sdhi1_wp),
++	SH_PFC_PIN_GROUP(sdhi2_data1),
++	SH_PFC_PIN_GROUP(sdhi2_data4),
++	SH_PFC_PIN_GROUP(sdhi2_data8),
++	SH_PFC_PIN_GROUP(sdhi2_ctrl),
++	SH_PFC_PIN_GROUP(sdhi2_cd_a),
++	SH_PFC_PIN_GROUP(sdhi2_wp_a),
++	SH_PFC_PIN_GROUP(sdhi2_cd_b),
++	SH_PFC_PIN_GROUP(sdhi2_wp_b),
++	SH_PFC_PIN_GROUP(sdhi2_ds),
++	SH_PFC_PIN_GROUP(sdhi3_data1),
++	SH_PFC_PIN_GROUP(sdhi3_data4),
++	SH_PFC_PIN_GROUP(sdhi3_data8),
++	SH_PFC_PIN_GROUP(sdhi3_ctrl),
++	SH_PFC_PIN_GROUP(sdhi3_cd),
++	SH_PFC_PIN_GROUP(sdhi3_wp),
++	SH_PFC_PIN_GROUP(sdhi3_ds),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
+@@ -3168,6 +3401,44 @@ static const char * const scif_clk_groups[] = {
+ 	"scif_clk_b",
+ };
+ 
++static const char * const sdhi0_groups[] = {
++	"sdhi0_data1",
++	"sdhi0_data4",
++	"sdhi0_ctrl",
++	"sdhi0_cd",
++	"sdhi0_wp",
++};
++
++static const char * const sdhi1_groups[] = {
++	"sdhi1_data1",
++	"sdhi1_data4",
++	"sdhi1_ctrl",
++	"sdhi1_cd",
++	"sdhi1_wp",
++};
++
++static const char * const sdhi2_groups[] = {
++	"sdhi2_data1",
++	"sdhi2_data4",
++	"sdhi2_data8",
++	"sdhi2_ctrl",
++	"sdhi2_cd_a",
++	"sdhi2_wp_a",
++	"sdhi2_cd_b",
++	"sdhi2_wp_b",
++	"sdhi2_ds",
++};
++
++static const char * const sdhi3_groups[] = {
++	"sdhi3_data1",
++	"sdhi3_data4",
++	"sdhi3_data8",
++	"sdhi3_ctrl",
++	"sdhi3_cd",
++	"sdhi3_wp",
++	"sdhi3_ds",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -3205,6 +3476,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif4),
+ 	SH_PFC_FUNCTION(scif5),
+ 	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(sdhi0),
++	SH_PFC_FUNCTION(sdhi1),
++	SH_PFC_FUNCTION(sdhi2),
++	SH_PFC_FUNCTION(sdhi3),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
+-- 
+2.19.0
+
diff --git a/patches/0189-pinctrl-sh-pfc-r8a7795-Re-add-DRIF-support.patch b/patches/0189-pinctrl-sh-pfc-r8a7795-Re-add-DRIF-support.patch
new file mode 100644
index 00000000000000..572d492c07e5f7
--- /dev/null
+++ b/patches/0189-pinctrl-sh-pfc-r8a7795-Re-add-DRIF-support.patch
@@ -0,0 +1,347 @@
+From faffef37ed192db1d74b641328a420a552ed7e78 Mon Sep 17 00:00:00 2001
+From: Dirk Behme <dirk.behme@de.bosch.com>
+Date: Wed, 30 Aug 2017 10:05:48 +0200
+Subject: [PATCH 0189/1795] pinctrl: sh-pfc: r8a7795: Re-add DRIF support
+
+DRIF support for r8a7795 was initially added with commit 2d775831988
+("pinctrl: sh-pfc: r8a7795: Add DRIF support") and later dropped from
+the new pfc-r8a7795.c while re-naming the initial pfc-r8a7795.c to
+pfc-r8a7795-es1.c in commit b205914c8f8 ("pinctrl: sh-pfc: r8a7795:
+Add support for R-Car H3 ES2.0"). As the DRIF doesn't differ, re-add
+it here.
+
+Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 641b0ab8029119d777cb248ef20f920d288b322a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 291 +++++++++++++++++++++++++++
+ 1 file changed, 291 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index b225bc2f9bea..9e420f7fed72 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1659,6 +1659,221 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
+ 	AVB_AVTP_CAPTURE_B_MARK,
+ };
+ 
++/* - DRIF0 --------------------------------------------------------------- */
++static const unsigned int drif0_ctrl_a_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
++};
++static const unsigned int drif0_ctrl_a_mux[] = {
++	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
++};
++static const unsigned int drif0_data0_a_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 10),
++};
++static const unsigned int drif0_data0_a_mux[] = {
++	RIF0_D0_A_MARK,
++};
++static const unsigned int drif0_data1_a_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 7),
++};
++static const unsigned int drif0_data1_a_mux[] = {
++	RIF0_D1_A_MARK,
++};
++static const unsigned int drif0_ctrl_b_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
++};
++static const unsigned int drif0_ctrl_b_mux[] = {
++	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
++};
++static const unsigned int drif0_data0_b_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(5, 1),
++};
++static const unsigned int drif0_data0_b_mux[] = {
++	RIF0_D0_B_MARK,
++};
++static const unsigned int drif0_data1_b_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(5, 2),
++};
++static const unsigned int drif0_data1_b_mux[] = {
++	RIF0_D1_B_MARK,
++};
++static const unsigned int drif0_ctrl_c_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
++};
++static const unsigned int drif0_ctrl_c_mux[] = {
++	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
++};
++static const unsigned int drif0_data0_c_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(5, 13),
++};
++static const unsigned int drif0_data0_c_mux[] = {
++	RIF0_D0_C_MARK,
++};
++static const unsigned int drif0_data1_c_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(5, 14),
++};
++static const unsigned int drif0_data1_c_mux[] = {
++	RIF0_D1_C_MARK,
++};
++/* - DRIF1 --------------------------------------------------------------- */
++static const unsigned int drif1_ctrl_a_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
++};
++static const unsigned int drif1_ctrl_a_mux[] = {
++	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
++};
++static const unsigned int drif1_data0_a_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int drif1_data0_a_mux[] = {
++	RIF1_D0_A_MARK,
++};
++static const unsigned int drif1_data1_a_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 20),
++};
++static const unsigned int drif1_data1_a_mux[] = {
++	RIF1_D1_A_MARK,
++};
++static const unsigned int drif1_ctrl_b_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
++};
++static const unsigned int drif1_ctrl_b_mux[] = {
++	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
++};
++static const unsigned int drif1_data0_b_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(5, 7),
++};
++static const unsigned int drif1_data0_b_mux[] = {
++	RIF1_D0_B_MARK,
++};
++static const unsigned int drif1_data1_b_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(5, 8),
++};
++static const unsigned int drif1_data1_b_mux[] = {
++	RIF1_D1_B_MARK,
++};
++static const unsigned int drif1_ctrl_c_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
++};
++static const unsigned int drif1_ctrl_c_mux[] = {
++	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
++};
++static const unsigned int drif1_data0_c_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(5, 6),
++};
++static const unsigned int drif1_data0_c_mux[] = {
++	RIF1_D0_C_MARK,
++};
++static const unsigned int drif1_data1_c_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(5, 10),
++};
++static const unsigned int drif1_data1_c_mux[] = {
++	RIF1_D1_C_MARK,
++};
++/* - DRIF2 --------------------------------------------------------------- */
++static const unsigned int drif2_ctrl_a_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
++};
++static const unsigned int drif2_ctrl_a_mux[] = {
++	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
++};
++static const unsigned int drif2_data0_a_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 7),
++};
++static const unsigned int drif2_data0_a_mux[] = {
++	RIF2_D0_A_MARK,
++};
++static const unsigned int drif2_data1_a_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 10),
++};
++static const unsigned int drif2_data1_a_mux[] = {
++	RIF2_D1_A_MARK,
++};
++static const unsigned int drif2_ctrl_b_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
++};
++static const unsigned int drif2_ctrl_b_mux[] = {
++	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
++};
++static const unsigned int drif2_data0_b_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 30),
++};
++static const unsigned int drif2_data0_b_mux[] = {
++	RIF2_D0_B_MARK,
++};
++static const unsigned int drif2_data1_b_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 31),
++};
++static const unsigned int drif2_data1_b_mux[] = {
++	RIF2_D1_B_MARK,
++};
++/* - DRIF3 --------------------------------------------------------------- */
++static const unsigned int drif3_ctrl_a_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
++};
++static const unsigned int drif3_ctrl_a_mux[] = {
++	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
++};
++static const unsigned int drif3_data0_a_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int drif3_data0_a_mux[] = {
++	RIF3_D0_A_MARK,
++};
++static const unsigned int drif3_data1_a_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 20),
++};
++static const unsigned int drif3_data1_a_mux[] = {
++	RIF3_D1_A_MARK,
++};
++static const unsigned int drif3_ctrl_b_pins[] = {
++	/* CLK, SYNC */
++	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
++};
++static const unsigned int drif3_ctrl_b_mux[] = {
++	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
++};
++static const unsigned int drif3_data0_b_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(6, 28),
++};
++static const unsigned int drif3_data0_b_mux[] = {
++	RIF3_D0_B_MARK,
++};
++static const unsigned int drif3_data1_b_pins[] = {
++	/* D1 */
++	RCAR_GP_PIN(6, 29),
++};
++static const unsigned int drif3_data1_b_mux[] = {
++	RIF3_D1_B_MARK,
++};
++
+ /* - DU --------------------------------------------------------------------- */
+ static const unsigned int du_rgb666_pins[] = {
+ 	/* R[7:2], G[7:2], B[7:2] */
+@@ -3001,6 +3216,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
++	SH_PFC_PIN_GROUP(drif0_ctrl_a),
++	SH_PFC_PIN_GROUP(drif0_data0_a),
++	SH_PFC_PIN_GROUP(drif0_data1_a),
++	SH_PFC_PIN_GROUP(drif0_ctrl_b),
++	SH_PFC_PIN_GROUP(drif0_data0_b),
++	SH_PFC_PIN_GROUP(drif0_data1_b),
++	SH_PFC_PIN_GROUP(drif0_ctrl_c),
++	SH_PFC_PIN_GROUP(drif0_data0_c),
++	SH_PFC_PIN_GROUP(drif0_data1_c),
++	SH_PFC_PIN_GROUP(drif1_ctrl_a),
++	SH_PFC_PIN_GROUP(drif1_data0_a),
++	SH_PFC_PIN_GROUP(drif1_data1_a),
++	SH_PFC_PIN_GROUP(drif1_ctrl_b),
++	SH_PFC_PIN_GROUP(drif1_data0_b),
++	SH_PFC_PIN_GROUP(drif1_data1_b),
++	SH_PFC_PIN_GROUP(drif1_ctrl_c),
++	SH_PFC_PIN_GROUP(drif1_data0_c),
++	SH_PFC_PIN_GROUP(drif1_data1_c),
++	SH_PFC_PIN_GROUP(drif2_ctrl_a),
++	SH_PFC_PIN_GROUP(drif2_data0_a),
++	SH_PFC_PIN_GROUP(drif2_data1_a),
++	SH_PFC_PIN_GROUP(drif2_ctrl_b),
++	SH_PFC_PIN_GROUP(drif2_data0_b),
++	SH_PFC_PIN_GROUP(drif2_data1_b),
++	SH_PFC_PIN_GROUP(drif3_ctrl_a),
++	SH_PFC_PIN_GROUP(drif3_data0_a),
++	SH_PFC_PIN_GROUP(drif3_data1_a),
++	SH_PFC_PIN_GROUP(drif3_ctrl_b),
++	SH_PFC_PIN_GROUP(drif3_data0_b),
++	SH_PFC_PIN_GROUP(drif3_data1_b),
+ 	SH_PFC_PIN_GROUP(du_rgb666),
+ 	SH_PFC_PIN_GROUP(du_rgb888),
+ 	SH_PFC_PIN_GROUP(du_clk_out_0),
+@@ -3195,6 +3440,48 @@ static const char * const avb_groups[] = {
+ 	"avb_avtp_capture_b",
+ };
+ 
++static const char * const drif0_groups[] = {
++	"drif0_ctrl_a",
++	"drif0_data0_a",
++	"drif0_data1_a",
++	"drif0_ctrl_b",
++	"drif0_data0_b",
++	"drif0_data1_b",
++	"drif0_ctrl_c",
++	"drif0_data0_c",
++	"drif0_data1_c",
++};
++
++static const char * const drif1_groups[] = {
++	"drif1_ctrl_a",
++	"drif1_data0_a",
++	"drif1_data1_a",
++	"drif1_ctrl_b",
++	"drif1_data0_b",
++	"drif1_data1_b",
++	"drif1_ctrl_c",
++	"drif1_data0_c",
++	"drif1_data1_c",
++};
++
++static const char * const drif2_groups[] = {
++	"drif2_ctrl_a",
++	"drif2_data0_a",
++	"drif2_data1_a",
++	"drif2_ctrl_b",
++	"drif2_data0_b",
++	"drif2_data1_b",
++};
++
++static const char * const drif3_groups[] = {
++	"drif3_ctrl_a",
++	"drif3_data0_a",
++	"drif3_data1_a",
++	"drif3_ctrl_b",
++	"drif3_data0_b",
++	"drif3_data1_b",
++};
++
+ static const char * const du_groups[] = {
+ 	"du_rgb666",
+ 	"du_rgb888",
+@@ -3457,6 +3744,10 @@ static const char * const usb2_ch3_groups[] = {
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(drif0),
++	SH_PFC_FUNCTION(drif1),
++	SH_PFC_FUNCTION(drif2),
++	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+-- 
+2.19.0
+
diff --git a/patches/0190-pinctrl-sh-pfc-r8a77995-Add-EthernetAVB-pins-groups-.patch b/patches/0190-pinctrl-sh-pfc-r8a77995-Add-EthernetAVB-pins-groups-.patch
new file mode 100644
index 00000000000000..0a17e9fbe97322
--- /dev/null
+++ b/patches/0190-pinctrl-sh-pfc-r8a77995-Add-EthernetAVB-pins-groups-.patch
@@ -0,0 +1,169 @@
+From 0eecbed85ed9dea53b414b53d04e37cd94ddeecd Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 14 Sep 2017 08:52:42 +0900
+Subject: [PATCH 0190/1795] pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins,
+ groups and functions
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 66abd968d0ef3eb10dea45b48a31321eb29258f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 119 ++++++++++++++++++++++++++
+ 1 file changed, 119 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 4f5ee1d7317d..9fc4296f9a84 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -936,6 +936,99 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+ };
+ 
++/* - EtherAVB --------------------------------------------------------------- */
++static const unsigned int avb0_link_pins[] = {
++	/* AVB0_LINK */
++	RCAR_GP_PIN(5, 20),
++};
++static const unsigned int avb0_link_mux[] = {
++	AVB0_LINK_MARK,
++};
++static const unsigned int avb0_magic_pins[] = {
++	/* AVB0_MAGIC */
++	RCAR_GP_PIN(5, 18),
++};
++static const unsigned int avb0_magic_mux[] = {
++	AVB0_MAGIC_MARK,
++};
++static const unsigned int avb0_phy_int_pins[] = {
++	/* AVB0_PHY_INT */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int avb0_phy_int_mux[] = {
++	AVB0_PHY_INT_MARK,
++};
++static const unsigned int avb0_mdc_pins[] = {
++	/* AVB0_MDC, AVB0_MDIO */
++	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
++};
++static const unsigned int avb0_mdc_mux[] = {
++	AVB0_MDC_MARK, AVB0_MDIO_MARK,
++};
++static const unsigned int avb0_mii_pins[] = {
++	/*
++	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
++	 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
++	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
++	 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
++	 * AVB0_TXCREFCLK
++	 */
++	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
++	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
++	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
++	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
++	RCAR_GP_PIN(5, 15),
++};
++static const unsigned int avb0_mii_mux[] = {
++	AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
++	AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
++	AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
++	AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
++	AVB0_TXCREFCLK_MARK,
++};
++static const unsigned int avb0_avtp_pps_a_pins[] = {
++	/* AVB0_AVTP_PPS_A */
++	RCAR_GP_PIN(5, 2),
++};
++static const unsigned int avb0_avtp_pps_a_mux[] = {
++	AVB0_AVTP_PPS_A_MARK,
++};
++static const unsigned int avb0_avtp_match_a_pins[] = {
++	/* AVB0_AVTP_MATCH_A */
++	RCAR_GP_PIN(5, 1),
++};
++static const unsigned int avb0_avtp_match_a_mux[] = {
++	AVB0_AVTP_MATCH_A_MARK,
++};
++static const unsigned int avb0_avtp_capture_a_pins[] = {
++	/* AVB0_AVTP_CAPTURE_A */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int avb0_avtp_capture_a_mux[] = {
++	AVB0_AVTP_CAPTURE_A_MARK,
++};
++static const unsigned int avb0_avtp_pps_b_pins[] = {
++	/* AVB0_AVTP_PPS_B */
++	RCAR_GP_PIN(4, 16),
++};
++static const unsigned int avb0_avtp_pps_b_mux[] = {
++	AVB0_AVTP_PPS_B_MARK,
++};
++static const unsigned int avb0_avtp_match_b_pins[] = {
++	/*  AVB0_AVTP_MATCH_B */
++	RCAR_GP_PIN(4, 18),
++};
++static const unsigned int avb0_avtp_match_b_mux[] = {
++	AVB0_AVTP_MATCH_B_MARK,
++};
++static const unsigned int avb0_avtp_capture_b_pins[] = {
++	/* AVB0_AVTP_CAPTURE_B */
++	RCAR_GP_PIN(4, 17),
++};
++static const unsigned int avb0_avtp_capture_b_mux[] = {
++	AVB0_AVTP_CAPTURE_B_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c0_pins[] = {
+ 	/* SCL, SDA */
+@@ -1203,6 +1296,17 @@ static const unsigned int scif_clk_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb0_link),
++	SH_PFC_PIN_GROUP(avb0_magic),
++	SH_PFC_PIN_GROUP(avb0_phy_int),
++	SH_PFC_PIN_GROUP(avb0_mdc),
++	SH_PFC_PIN_GROUP(avb0_mii),
++	SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
++	SH_PFC_PIN_GROUP(avb0_avtp_match_a),
++	SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
++	SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
++	SH_PFC_PIN_GROUP(avb0_avtp_match_b),
++	SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
+ 	SH_PFC_PIN_GROUP(i2c0),
+ 	SH_PFC_PIN_GROUP(i2c1),
+ 	SH_PFC_PIN_GROUP(i2c2_a),
+@@ -1240,6 +1344,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif_clk),
+ };
+ 
++static const char * const avb0_groups[] = {
++	"avb0_link",
++	"avb0_magic",
++	"avb0_phy_int",
++	"avb0_mdc",
++	"avb0_mii",
++	"avb0_avtp_pps_a",
++	"avb0_avtp_match_a",
++	"avb0_avtp_capture_a",
++	"avb0_avtp_pps_b",
++	"avb0_avtp_match_b",
++	"avb0_avtp_capture_b",
++};
++
+ static const char * const i2c0_groups[] = {
+ 	"i2c0",
+ };
+@@ -1311,6 +1429,7 @@ static const char * const scif_clk_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb0),
+ 	SH_PFC_FUNCTION(i2c0),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+-- 
+2.19.0
+
diff --git a/patches/0191-pinctrl-sh-pfc-r8a77995-Add-USB2.0-host-support.patch b/patches/0191-pinctrl-sh-pfc-r8a77995-Add-USB2.0-host-support.patch
new file mode 100644
index 00000000000000..2a85e802b74f24
--- /dev/null
+++ b/patches/0191-pinctrl-sh-pfc-r8a77995-Add-USB2.0-host-support.patch
@@ -0,0 +1,65 @@
+From d283c17cce8762e0c84211116bcd2c71f5644260 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 14 Sep 2017 19:29:21 +0900
+Subject: [PATCH 0191/1795] pinctrl: sh-pfc: r8a77995: Add USB2.0 host support
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f814def530c442bd0765db3fa7fd6f5ba4d466ca)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 9fc4296f9a84..442ff0f23243 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1295,6 +1295,15 @@ static const unsigned int scif_clk_mux[] = {
+ 	SCIF_CLK_MARK,
+ };
+ 
++/* - USB0 ------------------------------------------------------------------- */
++static const unsigned int usb0_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++};
++static const unsigned int usb0_mux[] = {
++	USB0_PWEN_MARK, USB0_OVC_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb0_link),
+ 	SH_PFC_PIN_GROUP(avb0_magic),
+@@ -1342,6 +1351,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif5_data_b),
+ 	SH_PFC_PIN_GROUP(scif5_clk_b),
+ 	SH_PFC_PIN_GROUP(scif_clk),
++	SH_PFC_PIN_GROUP(usb0),
+ };
+ 
+ static const char * const avb0_groups[] = {
+@@ -1428,6 +1438,10 @@ static const char * const scif_clk_groups[] = {
+ 	"scif_clk",
+ };
+ 
++static const char * const usb0_groups[] = {
++	"usb0",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb0),
+ 	SH_PFC_FUNCTION(i2c0),
+@@ -1442,6 +1456,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif4),
+ 	SH_PFC_FUNCTION(scif5),
+ 	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(usb0),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0192-pinctrl-sh-pfc-r8a7795-es1-Add-USB3.0-host-support.patch b/patches/0192-pinctrl-sh-pfc-r8a7795-es1-Add-USB3.0-host-support.patch
new file mode 100644
index 00000000000000..6b219600bef105
--- /dev/null
+++ b/patches/0192-pinctrl-sh-pfc-r8a7795-es1-Add-USB3.0-host-support.patch
@@ -0,0 +1,83 @@
+From 65dec1fa430cdb44d63eaa12740369abc0d8262d Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 2 Oct 2017 18:45:24 +0900
+Subject: [PATCH 0192/1795] pinctrl: sh-pfc: r8a7795-es1: Add USB3.0 host
+ support
+
+This patch adds USB3{0,1} (USB3.0 host) pinmux support to R8A7795 ES1.x
+SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3627126ce39d8c7d35a9251b074fedd2edf9f743)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 29 ++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index ad037534aa13..294f4b44944e 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -3101,6 +3101,23 @@ static const unsigned int pwm6_b_mux[] = {
+ 	PWM6_B_MARK,
+ };
+ 
++/* - USB30 ------------------------------------------------------------------ */
++static const unsigned int usb30_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
++};
++static const unsigned int usb30_mux[] = {
++	USB30_PWEN_MARK, USB30_OVC_MARK,
++};
++/* - USB31 ------------------------------------------------------------------ */
++static const unsigned int usb31_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
++};
++static const unsigned int usb31_mux[] = {
++	USB31_PWEN_MARK, USB31_OVC_MARK,
++};
++
+ /* - QSPI0 ------------------------------------------------------------------ */
+ static const unsigned int qspi0_ctrl_pins[] = {
+ 	/* QSPI0_SPCLK, QSPI0_SSL */
+@@ -4080,6 +4097,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
++	SH_PFC_PIN_GROUP(usb30),
++	SH_PFC_PIN_GROUP(usb31),
+ };
+ 
+ static const char * const audio_clk_groups[] = {
+@@ -4537,6 +4556,14 @@ static const char * const usb2_groups[] = {
+ 	"usb2",
+ };
+ 
++static const char * const usb30_groups[] = {
++	"usb30",
++};
++
++static const char * const usb31_groups[] = {
++	"usb31",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
+@@ -4588,6 +4615,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
++	SH_PFC_FUNCTION(usb30),
++	SH_PFC_FUNCTION(usb31),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0193-pinctrl-sh-pfc-r8a7795-Add-USB3.0-host-support.patch b/patches/0193-pinctrl-sh-pfc-r8a7795-Add-USB3.0-host-support.patch
new file mode 100644
index 00000000000000..42fa77f062a76f
--- /dev/null
+++ b/patches/0193-pinctrl-sh-pfc-r8a7795-Add-USB3.0-host-support.patch
@@ -0,0 +1,67 @@
+From e4acae7e4bc39578d12c117975906e290e9c9eb2 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 2 Oct 2017 18:45:25 +0900
+Subject: [PATCH 0193/1795] pinctrl: sh-pfc: r8a7795: Add USB3.0 host support
+
+This patch adds USB3.0 ch0 pinmux support to R8A7795 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5ec8a41a36715cf543cb7c109097fb3b4cdfb427)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 9e420f7fed72..351855b36f69 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3205,6 +3205,15 @@ static const unsigned int usb2_ch3_mux[] = {
+ 	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
+ };
+ 
++/* - USB30 ------------------------------------------------------------------ */
++static const unsigned int usb30_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
++};
++static const unsigned int usb30_mux[] = {
++	USB30_PWEN_MARK, USB30_OVC_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+@@ -3425,6 +3434,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
+ 	SH_PFC_PIN_GROUP(usb2_ch3),
++	SH_PFC_PIN_GROUP(usb30),
+ };
+ 
+ static const char * const avb_groups[] = {
+@@ -3742,6 +3752,10 @@ static const char * const usb2_ch3_groups[] = {
+ 	"usb2_ch3",
+ };
+ 
++static const char * const usb30_groups[] = {
++	"usb30",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(drif0),
+@@ -3775,6 +3789,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
+ 	SH_PFC_FUNCTION(usb2_ch3),
++	SH_PFC_FUNCTION(usb30),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0194-pinctrl-sh-pfc-r8a7795-Add-Audio-clock-pin-support.patch b/patches/0194-pinctrl-sh-pfc-r8a7795-Add-Audio-clock-pin-support.patch
new file mode 100644
index 00000000000000..dfa297c14653d2
--- /dev/null
+++ b/patches/0194-pinctrl-sh-pfc-r8a7795-Add-Audio-clock-pin-support.patch
@@ -0,0 +1,209 @@
+From 6abda81d300c632161f73f14523952c01c19bad3 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 3 Oct 2017 02:22:51 +0000
+Subject: [PATCH 0194/1795] pinctrl: sh-pfc: r8a7795: Add Audio clock pin
+ support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 55bfea9fdc05e3559164f3d58777d9a28ec42bc5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 159 +++++++++++++++++++++++++++
+ 1 file changed, 159 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 351855b36f69..3363453c4e4e 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1572,6 +1572,127 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+ };
+ 
++/* - AUDIO CLOCK ------------------------------------------------------------ */
++static const unsigned int audio_clk_a_a_pins[] = {
++	/* CLK A */
++	RCAR_GP_PIN(6, 22),
++};
++static const unsigned int audio_clk_a_a_mux[] = {
++	AUDIO_CLKA_A_MARK,
++};
++static const unsigned int audio_clk_a_b_pins[] = {
++	/* CLK A */
++	RCAR_GP_PIN(5, 4),
++};
++static const unsigned int audio_clk_a_b_mux[] = {
++	AUDIO_CLKA_B_MARK,
++};
++static const unsigned int audio_clk_a_c_pins[] = {
++	/* CLK A */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int audio_clk_a_c_mux[] = {
++	AUDIO_CLKA_C_MARK,
++};
++static const unsigned int audio_clk_b_a_pins[] = {
++	/* CLK B */
++	RCAR_GP_PIN(5, 12),
++};
++static const unsigned int audio_clk_b_a_mux[] = {
++	AUDIO_CLKB_A_MARK,
++};
++static const unsigned int audio_clk_b_b_pins[] = {
++	/* CLK B */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int audio_clk_b_b_mux[] = {
++	AUDIO_CLKB_B_MARK,
++};
++static const unsigned int audio_clk_c_a_pins[] = {
++	/* CLK C */
++	RCAR_GP_PIN(5, 21),
++};
++static const unsigned int audio_clk_c_a_mux[] = {
++	AUDIO_CLKC_A_MARK,
++};
++static const unsigned int audio_clk_c_b_pins[] = {
++	/* CLK C */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int audio_clk_c_b_mux[] = {
++	AUDIO_CLKC_B_MARK,
++};
++static const unsigned int audio_clkout_a_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(5, 18),
++};
++static const unsigned int audio_clkout_a_mux[] = {
++	AUDIO_CLKOUT_A_MARK,
++};
++static const unsigned int audio_clkout_b_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(6, 28),
++};
++static const unsigned int audio_clkout_b_mux[] = {
++	AUDIO_CLKOUT_B_MARK,
++};
++static const unsigned int audio_clkout_c_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(5, 3),
++};
++static const unsigned int audio_clkout_c_mux[] = {
++	AUDIO_CLKOUT_C_MARK,
++};
++static const unsigned int audio_clkout_d_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(5, 21),
++};
++static const unsigned int audio_clkout_d_mux[] = {
++	AUDIO_CLKOUT_D_MARK,
++};
++static const unsigned int audio_clkout1_a_pins[] = {
++	/* CLKOUT1 */
++	RCAR_GP_PIN(5, 15),
++};
++static const unsigned int audio_clkout1_a_mux[] = {
++	AUDIO_CLKOUT1_A_MARK,
++};
++static const unsigned int audio_clkout1_b_pins[] = {
++	/* CLKOUT1 */
++	RCAR_GP_PIN(6, 29),
++};
++static const unsigned int audio_clkout1_b_mux[] = {
++	AUDIO_CLKOUT1_B_MARK,
++};
++static const unsigned int audio_clkout2_a_pins[] = {
++	/* CLKOUT2 */
++	RCAR_GP_PIN(5, 16),
++};
++static const unsigned int audio_clkout2_a_mux[] = {
++	AUDIO_CLKOUT2_A_MARK,
++};
++static const unsigned int audio_clkout2_b_pins[] = {
++	/* CLKOUT2 */
++	RCAR_GP_PIN(6, 30),
++};
++static const unsigned int audio_clkout2_b_mux[] = {
++	AUDIO_CLKOUT2_B_MARK,
++};
++static const unsigned int audio_clkout3_a_pins[] = {
++	/* CLKOUT3 */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int audio_clkout3_a_mux[] = {
++	AUDIO_CLKOUT3_A_MARK,
++};
++static const unsigned int audio_clkout3_b_pins[] = {
++	/* CLKOUT3 */
++	RCAR_GP_PIN(6, 31),
++};
++static const unsigned int audio_clkout3_b_mux[] = {
++	AUDIO_CLKOUT3_B_MARK,
++};
++
+ /* - EtherAVB --------------------------------------------------------------- */
+ static const unsigned int avb_link_pins[] = {
+ 	/* AVB_LINK */
+@@ -3215,6 +3336,23 @@ static const unsigned int usb30_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(audio_clk_a_a),
++	SH_PFC_PIN_GROUP(audio_clk_a_b),
++	SH_PFC_PIN_GROUP(audio_clk_a_c),
++	SH_PFC_PIN_GROUP(audio_clk_b_a),
++	SH_PFC_PIN_GROUP(audio_clk_b_b),
++	SH_PFC_PIN_GROUP(audio_clk_c_a),
++	SH_PFC_PIN_GROUP(audio_clk_c_b),
++	SH_PFC_PIN_GROUP(audio_clkout_a),
++	SH_PFC_PIN_GROUP(audio_clkout_b),
++	SH_PFC_PIN_GROUP(audio_clkout_c),
++	SH_PFC_PIN_GROUP(audio_clkout_d),
++	SH_PFC_PIN_GROUP(audio_clkout1_a),
++	SH_PFC_PIN_GROUP(audio_clkout1_b),
++	SH_PFC_PIN_GROUP(audio_clkout2_a),
++	SH_PFC_PIN_GROUP(audio_clkout2_b),
++	SH_PFC_PIN_GROUP(audio_clkout3_a),
++	SH_PFC_PIN_GROUP(audio_clkout3_b),
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+ 	SH_PFC_PIN_GROUP(avb_phy_int),
+@@ -3437,6 +3575,26 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb30),
+ };
+ 
++static const char * const audio_clk_groups[] = {
++	"audio_clk_a_a",
++	"audio_clk_a_b",
++	"audio_clk_a_c",
++	"audio_clk_b_a",
++	"audio_clk_b_b",
++	"audio_clk_c_a",
++	"audio_clk_c_b",
++	"audio_clkout_a",
++	"audio_clkout_b",
++	"audio_clkout_c",
++	"audio_clkout_d",
++	"audio_clkout1_a",
++	"audio_clkout1_b",
++	"audio_clkout2_a",
++	"audio_clkout2_b",
++	"audio_clkout3_a",
++	"audio_clkout3_b",
++};
++
+ static const char * const avb_groups[] = {
+ 	"avb_link",
+ 	"avb_magic",
+@@ -3757,6 +3915,7 @@ static const char * const usb30_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(drif0),
+ 	SH_PFC_FUNCTION(drif1),
+-- 
+2.19.0
+
diff --git a/patches/0195-pinctrl-sh-pfc-r8a7795-Add-Audio-SSI-pin-support.patch b/patches/0195-pinctrl-sh-pfc-r8a7795-Add-Audio-SSI-pin-support.patch
new file mode 100644
index 00000000000000..3d6f0d89598809
--- /dev/null
+++ b/patches/0195-pinctrl-sh-pfc-r8a7795-Add-Audio-SSI-pin-support.patch
@@ -0,0 +1,280 @@
+From ea7d11c0372f0c1dbb73c24f42a11896daa92ccf Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 3 Oct 2017 02:23:11 +0000
+Subject: [PATCH 0195/1795] pinctrl: sh-pfc: r8a7795: Add Audio SSI pin support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0526234d6786c749ca6014edc6dd1242dfe1ddac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 231 +++++++++++++++++++++++++++
+ 1 file changed, 231 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 3363453c4e4e..3712b9187c61 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3277,6 +3277,183 @@ static const unsigned int sdhi3_ds_mux[] = {
+ 	SD3_DS_MARK,
+ };
+ 
++/* - SSI -------------------------------------------------------------------- */
++static const unsigned int ssi0_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 2),
++};
++static const unsigned int ssi0_data_mux[] = {
++	SSI_SDATA0_MARK,
++};
++static const unsigned int ssi01239_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
++};
++static const unsigned int ssi01239_ctrl_mux[] = {
++	SSI_SCK01239_MARK, SSI_WS01239_MARK,
++};
++static const unsigned int ssi1_data_a_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 3),
++};
++static const unsigned int ssi1_data_a_mux[] = {
++	SSI_SDATA1_A_MARK,
++};
++static const unsigned int ssi1_data_b_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(5, 12),
++};
++static const unsigned int ssi1_data_b_mux[] = {
++	SSI_SDATA1_B_MARK,
++};
++static const unsigned int ssi1_ctrl_a_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
++};
++static const unsigned int ssi1_ctrl_a_mux[] = {
++	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
++};
++static const unsigned int ssi1_ctrl_b_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
++};
++static const unsigned int ssi1_ctrl_b_mux[] = {
++	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
++};
++static const unsigned int ssi2_data_a_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 4),
++};
++static const unsigned int ssi2_data_a_mux[] = {
++	SSI_SDATA2_A_MARK,
++};
++static const unsigned int ssi2_data_b_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(5, 13),
++};
++static const unsigned int ssi2_data_b_mux[] = {
++	SSI_SDATA2_B_MARK,
++};
++static const unsigned int ssi2_ctrl_a_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
++};
++static const unsigned int ssi2_ctrl_a_mux[] = {
++	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
++};
++static const unsigned int ssi2_ctrl_b_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
++};
++static const unsigned int ssi2_ctrl_b_mux[] = {
++	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
++};
++static const unsigned int ssi3_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 7),
++};
++static const unsigned int ssi3_data_mux[] = {
++	SSI_SDATA3_MARK,
++};
++static const unsigned int ssi349_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
++};
++static const unsigned int ssi349_ctrl_mux[] = {
++	SSI_SCK349_MARK, SSI_WS349_MARK,
++};
++static const unsigned int ssi4_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 10),
++};
++static const unsigned int ssi4_data_mux[] = {
++	SSI_SDATA4_MARK,
++};
++static const unsigned int ssi4_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
++};
++static const unsigned int ssi4_ctrl_mux[] = {
++	SSI_SCK4_MARK, SSI_WS4_MARK,
++};
++static const unsigned int ssi5_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 13),
++};
++static const unsigned int ssi5_data_mux[] = {
++	SSI_SDATA5_MARK,
++};
++static const unsigned int ssi5_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
++};
++static const unsigned int ssi5_ctrl_mux[] = {
++	SSI_SCK5_MARK, SSI_WS5_MARK,
++};
++static const unsigned int ssi6_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 16),
++};
++static const unsigned int ssi6_data_mux[] = {
++	SSI_SDATA6_MARK,
++};
++static const unsigned int ssi6_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
++};
++static const unsigned int ssi6_ctrl_mux[] = {
++	SSI_SCK6_MARK, SSI_WS6_MARK,
++};
++static const unsigned int ssi7_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int ssi7_data_mux[] = {
++	SSI_SDATA7_MARK,
++};
++static const unsigned int ssi78_ctrl_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
++};
++static const unsigned int ssi78_ctrl_mux[] = {
++	SSI_SCK78_MARK, SSI_WS78_MARK,
++};
++static const unsigned int ssi8_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 20),
++};
++static const unsigned int ssi8_data_mux[] = {
++	SSI_SDATA8_MARK,
++};
++static const unsigned int ssi9_data_a_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int ssi9_data_a_mux[] = {
++	SSI_SDATA9_A_MARK,
++};
++static const unsigned int ssi9_data_b_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(5, 14),
++};
++static const unsigned int ssi9_data_b_mux[] = {
++	SSI_SDATA9_B_MARK,
++};
++static const unsigned int ssi9_ctrl_a_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
++};
++static const unsigned int ssi9_ctrl_a_mux[] = {
++	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
++};
++static const unsigned int ssi9_ctrl_b_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
++};
++static const unsigned int ssi9_ctrl_b_mux[] = {
++	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
++};
++
+ /* - SCIF Clock ------------------------------------------------------------- */
+ static const unsigned int scif_clk_a_pins[] = {
+ 	/* SCIF_CLK */
+@@ -3568,6 +3745,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(sdhi3_cd),
+ 	SH_PFC_PIN_GROUP(sdhi3_wp),
+ 	SH_PFC_PIN_GROUP(sdhi3_ds),
++	SH_PFC_PIN_GROUP(ssi0_data),
++	SH_PFC_PIN_GROUP(ssi01239_ctrl),
++	SH_PFC_PIN_GROUP(ssi1_data_a),
++	SH_PFC_PIN_GROUP(ssi1_data_b),
++	SH_PFC_PIN_GROUP(ssi1_ctrl_a),
++	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
++	SH_PFC_PIN_GROUP(ssi2_data_a),
++	SH_PFC_PIN_GROUP(ssi2_data_b),
++	SH_PFC_PIN_GROUP(ssi2_ctrl_a),
++	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
++	SH_PFC_PIN_GROUP(ssi3_data),
++	SH_PFC_PIN_GROUP(ssi349_ctrl),
++	SH_PFC_PIN_GROUP(ssi4_data),
++	SH_PFC_PIN_GROUP(ssi4_ctrl),
++	SH_PFC_PIN_GROUP(ssi5_data),
++	SH_PFC_PIN_GROUP(ssi5_ctrl),
++	SH_PFC_PIN_GROUP(ssi6_data),
++	SH_PFC_PIN_GROUP(ssi6_ctrl),
++	SH_PFC_PIN_GROUP(ssi7_data),
++	SH_PFC_PIN_GROUP(ssi78_ctrl),
++	SH_PFC_PIN_GROUP(ssi8_data),
++	SH_PFC_PIN_GROUP(ssi9_data_a),
++	SH_PFC_PIN_GROUP(ssi9_data_b),
++	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
++	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
+@@ -3894,6 +4096,34 @@ static const char * const sdhi3_groups[] = {
+ 	"sdhi3_ds",
+ };
+ 
++static const char * const ssi_groups[] = {
++	"ssi0_data",
++	"ssi01239_ctrl",
++	"ssi1_data_a",
++	"ssi1_data_b",
++	"ssi1_ctrl_a",
++	"ssi1_ctrl_b",
++	"ssi2_data_a",
++	"ssi2_data_b",
++	"ssi2_ctrl_a",
++	"ssi2_ctrl_b",
++	"ssi3_data",
++	"ssi349_ctrl",
++	"ssi4_data",
++	"ssi4_ctrl",
++	"ssi5_data",
++	"ssi5_ctrl",
++	"ssi6_data",
++	"ssi6_ctrl",
++	"ssi7_data",
++	"ssi78_ctrl",
++	"ssi8_data",
++	"ssi9_data_a",
++	"ssi9_data_b",
++	"ssi9_ctrl_a",
++	"ssi9_ctrl_b",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -3944,6 +4174,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(sdhi1),
+ 	SH_PFC_FUNCTION(sdhi2),
+ 	SH_PFC_FUNCTION(sdhi3),
++	SH_PFC_FUNCTION(ssi),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
+-- 
+2.19.0
+
diff --git a/patches/0196-pinctrl-sh-pfc-r8a77995-Add-PWM-pins-groups-and-func.patch b/patches/0196-pinctrl-sh-pfc-r8a77995-Add-PWM-pins-groups-and-func.patch
new file mode 100644
index 00000000000000..7ddf7c3647bb2a
--- /dev/null
+++ b/patches/0196-pinctrl-sh-pfc-r8a77995-Add-PWM-pins-groups-and-func.patch
@@ -0,0 +1,205 @@
+From 4174b933d38d248091e3296ab287f2d1b307e512 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Wed, 4 Oct 2017 19:22:39 +0900
+Subject: [PATCH 0196/1795] pinctrl: sh-pfc: r8a77995: Add PWM pins, groups and
+ functions
+
+This patch adds support for PWM on r8a77995.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 47bb129679cc4cf0bdeb145694082fc0b074c947)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 152 ++++++++++++++++++++++++++
+ 1 file changed, 152 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 442ff0f23243..3f67b8d4f050 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1111,6 +1111,118 @@ static const unsigned int mmc_ctrl_mux[] = {
+ 	MMC_CLK_MARK, MMC_CMD_MARK,
+ };
+ 
++/* - PWM0 ------------------------------------------------------------------ */
++static const unsigned int pwm0_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 1),
++};
++
++static const unsigned int pwm0_a_mux[] = {
++	PWM0_A_MARK,
++};
++
++static const unsigned int pwm0_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 18),
++};
++
++static const unsigned int pwm0_b_mux[] = {
++	PWM0_B_MARK,
++};
++
++static const unsigned int pwm0_c_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 29),
++};
++
++static const unsigned int pwm0_c_mux[] = {
++	PWM0_C_MARK,
++};
++
++/* - PWM1 ------------------------------------------------------------------ */
++static const unsigned int pwm1_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 2),
++};
++
++static const unsigned int pwm1_a_mux[] = {
++	PWM1_A_MARK,
++};
++
++static const unsigned int pwm1_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 19),
++};
++
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++
++static const unsigned int pwm1_c_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 30),
++};
++
++static const unsigned int pwm1_c_mux[] = {
++	PWM1_C_MARK,
++};
++
++/* - PWM2 ------------------------------------------------------------------ */
++static const unsigned int pwm2_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 3),
++};
++
++static const unsigned int pwm2_a_mux[] = {
++	PWM2_A_MARK,
++};
++
++static const unsigned int pwm2_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 22),
++};
++
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++
++static const unsigned int pwm2_c_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 31),
++};
++
++static const unsigned int pwm2_c_mux[] = {
++	PWM2_C_MARK,
++};
++
++/* - PWM3 ------------------------------------------------------------------ */
++static const unsigned int pwm3_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 4),
++};
++
++static const unsigned int pwm3_a_mux[] = {
++	PWM3_A_MARK,
++};
++
++static const unsigned int pwm3_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 27),
++};
++
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++
++static const unsigned int pwm3_c_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(4, 0),
++};
++
++static const unsigned int pwm3_c_mux[] = {
++	PWM3_C_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_a_pins[] = {
+ 	/* RX, TX */
+@@ -1326,6 +1438,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(mmc_data4),
+ 	SH_PFC_PIN_GROUP(mmc_data8),
+ 	SH_PFC_PIN_GROUP(mmc_ctrl),
++	SH_PFC_PIN_GROUP(pwm0_a),
++	SH_PFC_PIN_GROUP(pwm0_b),
++	SH_PFC_PIN_GROUP(pwm0_c),
++	SH_PFC_PIN_GROUP(pwm1_a),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm1_c),
++	SH_PFC_PIN_GROUP(pwm2_a),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm2_c),
++	SH_PFC_PIN_GROUP(pwm3_a),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm3_c),
+ 	SH_PFC_PIN_GROUP(scif0_data_a),
+ 	SH_PFC_PIN_GROUP(scif0_clk_a),
+ 	SH_PFC_PIN_GROUP(scif0_data_b),
+@@ -1392,6 +1516,30 @@ static const char * const mmc_groups[] = {
+ 	"mmc_ctrl",
+ };
+ 
++static const char * const pwm0_groups[] = {
++	"pwm0_a",
++	"pwm0_b",
++	"pwm0_c",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1_a",
++	"pwm1_b",
++	"pwm1_c",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2_a",
++	"pwm2_b",
++	"pwm2_c",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3_a",
++	"pwm3_b",
++	"pwm3_c",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data_a",
+ 	"scif0_clk_a",
+@@ -1449,6 +1597,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c3),
+ 	SH_PFC_FUNCTION(mmc),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/0197-pinctrl-sh-pfc-r8a7795-Add-I2C-pin-support.patch b/patches/0197-pinctrl-sh-pfc-r8a7795-Add-I2C-pin-support.patch
new file mode 100644
index 00000000000000..f05d717675e40a
--- /dev/null
+++ b/patches/0197-pinctrl-sh-pfc-r8a7795-Add-I2C-pin-support.patch
@@ -0,0 +1,136 @@
+From 213f4ddc0bdd5ad207bc2e2137918799756d9687 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 4 Oct 2017 17:52:52 +0200
+Subject: [PATCH 0197/1795] pinctrl: sh-pfc: r8a7795: Add I2C pin support
+
+Since pinmuxing for I2C is equal on H3 ES1.0 and later versions, copy
+the I2C settings from ES1.0. Fixes this error in upstream for
+Salvator-XS:
+
+sh-pfc e6060000.pin-controller: function 'i2c2' not supported
+sh-pfc e6060000.pin-controller: invalid function i2c2 in map table
+i2c-rcar: probe of e6510000.i2c failed with error -22
+
+Now, the bus works the same as with other Salvator boards.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f62d4c9efd809b9eff28fb755d7249716d98a7af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 77 ++++++++++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 3712b9187c61..df6a95bce4f8 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2076,6 +2076,57 @@ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
+ 
++/* - I2C -------------------------------------------------------------------- */
++static const unsigned int i2c1_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
++};
++static const unsigned int i2c1_a_mux[] = {
++	SDA1_A_MARK, SCL1_A_MARK,
++};
++static const unsigned int i2c1_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
++};
++static const unsigned int i2c1_b_mux[] = {
++	SDA1_B_MARK, SCL1_B_MARK,
++};
++static const unsigned int i2c2_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
++};
++static const unsigned int i2c2_a_mux[] = {
++	SDA2_A_MARK, SCL2_A_MARK,
++};
++static const unsigned int i2c2_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
++};
++static const unsigned int i2c2_b_mux[] = {
++	SDA2_B_MARK, SCL2_B_MARK,
++};
++static const unsigned int i2c6_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
++};
++static const unsigned int i2c6_a_mux[] = {
++	SDA6_A_MARK, SCL6_A_MARK,
++};
++static const unsigned int i2c6_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
++};
++static const unsigned int i2c6_b_mux[] = {
++	SDA6_B_MARK, SCL6_B_MARK,
++};
++static const unsigned int i2c6_c_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int i2c6_c_mux[] = {
++	SDA6_C_MARK, SCL6_C_MARK,
++};
++
+ /* - MSIOF0 ----------------------------------------------------------------- */
+ static const unsigned int msiof0_clk_pins[] = {
+ 	/* SCK */
+@@ -3578,6 +3629,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(i2c1_a),
++	SH_PFC_PIN_GROUP(i2c1_b),
++	SH_PFC_PIN_GROUP(i2c2_a),
++	SH_PFC_PIN_GROUP(i2c2_b),
++	SH_PFC_PIN_GROUP(i2c6_a),
++	SH_PFC_PIN_GROUP(i2c6_b),
++	SH_PFC_PIN_GROUP(i2c6_c),
+ 	SH_PFC_PIN_GROUP(msiof0_clk),
+ 	SH_PFC_PIN_GROUP(msiof0_sync),
+ 	SH_PFC_PIN_GROUP(msiof0_ss1),
+@@ -3863,6 +3921,22 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const i2c1_groups[] = {
++	"i2c1_a",
++	"i2c1_b",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2_a",
++	"i2c2_b",
++};
++
++static const char * const i2c6_groups[] = {
++	"i2c6_a",
++	"i2c6_b",
++	"i2c6_c",
++};
++
+ static const char * const msiof0_groups[] = {
+ 	"msiof0_clk",
+ 	"msiof0_sync",
+@@ -4152,6 +4226,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(drif2),
+ 	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c6),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+ 	SH_PFC_FUNCTION(msiof2),
+-- 
+2.19.0
+
diff --git a/patches/0198-pinctrl-sh-pfc-r8a7795-es1-Restore-sort-order.patch b/patches/0198-pinctrl-sh-pfc-r8a7795-es1-Restore-sort-order.patch
new file mode 100644
index 00000000000000..e1c923d95a5ad8
--- /dev/null
+++ b/patches/0198-pinctrl-sh-pfc-r8a7795-es1-Restore-sort-order.patch
@@ -0,0 +1,70 @@
+From ad8d9f1bb36ebe45f94985b378412e4592562033 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 5 Oct 2017 12:12:51 +0200
+Subject: [PATCH 0198/1795] pinctrl: sh-pfc: r8a7795-es1: Restore sort order
+
+Move the USB30 pins where they belong.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit abc053c869b6f185d2eece2aa407d82014f22280)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 34 ++++++++++++------------
+ 1 file changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 294f4b44944e..e7fdfa4efeaa 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -3101,23 +3101,6 @@ static const unsigned int pwm6_b_mux[] = {
+ 	PWM6_B_MARK,
+ };
+ 
+-/* - USB30 ------------------------------------------------------------------ */
+-static const unsigned int usb30_pins[] = {
+-	/* PWEN, OVC */
+-	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+-};
+-static const unsigned int usb30_mux[] = {
+-	USB30_PWEN_MARK, USB30_OVC_MARK,
+-};
+-/* - USB31 ------------------------------------------------------------------ */
+-static const unsigned int usb31_pins[] = {
+-	/* PWEN, OVC */
+-	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
+-};
+-static const unsigned int usb31_mux[] = {
+-	USB31_PWEN_MARK, USB31_OVC_MARK,
+-};
+-
+ /* - QSPI0 ------------------------------------------------------------------ */
+ static const unsigned int qspi0_ctrl_pins[] = {
+ 	/* QSPI0_SPCLK, QSPI0_SSL */
+@@ -3791,6 +3774,23 @@ static const unsigned int usb2_mux[] = {
+ 	USB2_PWEN_MARK, USB2_OVC_MARK,
+ };
+ 
++/* - USB30 ------------------------------------------------------------------ */
++static const unsigned int usb30_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
++};
++static const unsigned int usb30_mux[] = {
++	USB30_PWEN_MARK, USB30_OVC_MARK,
++};
++/* - USB31 ------------------------------------------------------------------ */
++static const unsigned int usb31_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
++};
++static const unsigned int usb31_mux[] = {
++	USB31_PWEN_MARK, USB31_OVC_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(audio_clk_a_a),
+ 	SH_PFC_PIN_GROUP(audio_clk_a_b),
+-- 
+2.19.0
+
diff --git a/patches/0199-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch b/patches/0199-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch
new file mode 100644
index 00000000000000..c30ad62e8abed3
--- /dev/null
+++ b/patches/0199-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch
@@ -0,0 +1,68 @@
+From c59efdbac6bb1bdd4b6e9fbf9578cfc300570a02 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 5 Oct 2017 12:14:00 +0200
+Subject: [PATCH 0199/1795] pinctrl: sh-pfc: r8a7795: Restore sort order
+
+Move the SCIF_CLK pins where they belong.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b4062b46daabc6c0e88fa8dde8e2128138713b48)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 32 ++++++++++++++--------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index df6a95bce4f8..9772a6c7b303 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3121,6 +3121,22 @@ static const unsigned int scif5_clk_b_mux[] = {
+ 	SCK5_B_MARK,
+ };
+ 
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(5, 9),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
+ /* - SDHI0 ------------------------------------------------------------------ */
+ static const unsigned int sdhi0_data1_pins[] = {
+ 	/* D0 */
+@@ -3505,22 +3521,6 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
+ 
+-/* - SCIF Clock ------------------------------------------------------------- */
+-static const unsigned int scif_clk_a_pins[] = {
+-	/* SCIF_CLK */
+-	RCAR_GP_PIN(6, 23),
+-};
+-static const unsigned int scif_clk_a_mux[] = {
+-	SCIF_CLK_A_MARK,
+-};
+-static const unsigned int scif_clk_b_pins[] = {
+-	/* SCIF_CLK */
+-	RCAR_GP_PIN(5, 9),
+-};
+-static const unsigned int scif_clk_b_mux[] = {
+-	SCIF_CLK_B_MARK,
+-};
+-
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+-- 
+2.19.0
+
diff --git a/patches/0200-pinctrl-sh-pfc-r8a7795-Add-INTC-EX-pins-groups-and-f.patch b/patches/0200-pinctrl-sh-pfc-r8a7795-Add-INTC-EX-pins-groups-and-f.patch
new file mode 100644
index 00000000000000..638dbdf886a947
--- /dev/null
+++ b/patches/0200-pinctrl-sh-pfc-r8a7795-Add-INTC-EX-pins-groups-and-f.patch
@@ -0,0 +1,114 @@
+From e399da1134e4c85fc880d32e73fc9bfa18ef0ee4 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 13 Mar 2017 11:59:42 +0100
+Subject: [PATCH 0200/1795] pinctrl: sh-pfc: r8a7795: Add INTC-EX pins, groups
+ and function
+
+Add pins, groups, and a function for the INTC-EX interrupt controller on
+R-Car H3 ES2.0.
+
+Extracted from a big patch in the BSP by Takeshi Kihara.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8480e6ca800046d14bfc610a24f2317341250b04)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 60 ++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 9772a6c7b303..22201fc37420 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2127,6 +2127,50 @@ static const unsigned int i2c6_c_mux[] = {
+ 	SDA6_C_MARK, SCL6_C_MARK,
+ };
+ 
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
+ /* - MSIOF0 ----------------------------------------------------------------- */
+ static const unsigned int msiof0_clk_pins[] = {
+ 	/* SCK */
+@@ -3636,6 +3680,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(i2c6_a),
+ 	SH_PFC_PIN_GROUP(i2c6_b),
+ 	SH_PFC_PIN_GROUP(i2c6_c),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
+ 	SH_PFC_PIN_GROUP(msiof0_clk),
+ 	SH_PFC_PIN_GROUP(msiof0_sync),
+ 	SH_PFC_PIN_GROUP(msiof0_ss1),
+@@ -3937,6 +3987,15 @@ static const char * const i2c6_groups[] = {
+ 	"i2c6_c",
+ };
+ 
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
+ static const char * const msiof0_groups[] = {
+ 	"msiof0_clk",
+ 	"msiof0_sync",
+@@ -4229,6 +4288,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c6),
++	SH_PFC_FUNCTION(intc_ex),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+ 	SH_PFC_FUNCTION(msiof2),
+-- 
+2.19.0
+
diff --git a/patches/0201-pinctrl-sh-pfc-r8a7796-Add-support-for-INTC-EX-IRQ-p.patch b/patches/0201-pinctrl-sh-pfc-r8a7796-Add-support-for-INTC-EX-IRQ-p.patch
new file mode 100644
index 00000000000000..b009e553807cbc
--- /dev/null
+++ b/patches/0201-pinctrl-sh-pfc-r8a7796-Add-support-for-INTC-EX-IRQ-p.patch
@@ -0,0 +1,121 @@
+From b078e934e30b1f207352547a30c40e098ca72409 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 24 Oct 2016 20:40:09 +0900
+Subject: [PATCH 0201/1795] pinctrl: sh-pfc: r8a7796: Add support for INTC-EX
+ IRQ pins
+
+Most pins on the r8a7796 SoC can be configured in GPIO mode for
+interrupt and GPIO functionality, while a couple of them can also
+be routed to the INTC-EX hardware block (formerly known as IRQC).
+
+On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
+this patch adds support for them to the PFC driver as "intc_ex_irqN".
+
+[takeshi.kihara.df: Ported from commit bb46f6f3f3bf ("pinctrl: sh-pfc:
+ r8a7795: Add support for INTC-EX IRQ pins")
+ to drivers/pinctrl/sh-pfc/pfc-r8a7796.c]
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit b014912f6c462223229bb9865ceb1a363984c521)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 60 ++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 711333fb2c6e..b5bba8880537 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -2392,6 +2392,50 @@ static const unsigned int i2c6_c_mux[] = {
+ 	SDA6_C_MARK, SCL6_C_MARK,
+ };
+ 
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
+ /* - MSIOF0 ----------------------------------------------------------------- */
+ static const unsigned int msiof0_clk_pins[] = {
+ 	/* SCK */
+@@ -3922,6 +3966,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(i2c6_a),
+ 	SH_PFC_PIN_GROUP(i2c6_b),
+ 	SH_PFC_PIN_GROUP(i2c6_c),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
+ 	SH_PFC_PIN_GROUP(msiof0_clk),
+ 	SH_PFC_PIN_GROUP(msiof0_sync),
+ 	SH_PFC_PIN_GROUP(msiof0_ss1),
+@@ -4286,6 +4336,15 @@ static const char * const i2c6_groups[] = {
+ 	"i2c6_c",
+ };
+ 
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
+ static const char * const msiof0_groups[] = {
+ 	"msiof0_clk",
+ 	"msiof0_sync",
+@@ -4580,6 +4639,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c6),
++	SH_PFC_FUNCTION(intc_ex),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+ 	SH_PFC_FUNCTION(msiof2),
+-- 
+2.19.0
+
diff --git a/patches/0202-pinctrl-sh-pfc-r8a7795-Add-HSCIF-pins-groups-and-fun.patch b/patches/0202-pinctrl-sh-pfc-r8a7795-Add-HSCIF-pins-groups-and-fun.patch
new file mode 100644
index 00000000000000..fa8ed28d198fa4
--- /dev/null
+++ b/patches/0202-pinctrl-sh-pfc-r8a7795-Add-HSCIF-pins-groups-and-fun.patch
@@ -0,0 +1,333 @@
+From f7de0b4f0667ef40404c5151b2bb3c2a429b6eda Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 9 Oct 2017 10:20:53 +0200
+Subject: [PATCH 0202/1795] pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups,
+ and functions
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7a362e3488cbfa921fbca1fa62e1670283c84d19)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 283 +++++++++++++++++++++++++++
+ 1 file changed, 283 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 22201fc37420..1b556a8dcd5e 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2076,6 +2076,213 @@ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
+ 
++/* - HSCIF0 ----------------------------------------------------------------- */
++static const unsigned int hscif0_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
++};
++static const unsigned int hscif0_data_mux[] = {
++	HRX0_MARK, HTX0_MARK,
++};
++static const unsigned int hscif0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 12),
++};
++static const unsigned int hscif0_clk_mux[] = {
++	HSCK0_MARK,
++};
++static const unsigned int hscif0_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
++};
++static const unsigned int hscif0_ctrl_mux[] = {
++	HRTS0_N_MARK, HCTS0_N_MARK,
++};
++/* - HSCIF1 ----------------------------------------------------------------- */
++static const unsigned int hscif1_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
++};
++static const unsigned int hscif1_data_a_mux[] = {
++	HRX1_A_MARK, HTX1_A_MARK,
++};
++static const unsigned int hscif1_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int hscif1_clk_a_mux[] = {
++	HSCK1_A_MARK,
++};
++static const unsigned int hscif1_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
++};
++static const unsigned int hscif1_ctrl_a_mux[] = {
++	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
++};
++
++static const unsigned int hscif1_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
++};
++static const unsigned int hscif1_data_b_mux[] = {
++	HRX1_B_MARK, HTX1_B_MARK,
++};
++static const unsigned int hscif1_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int hscif1_clk_b_mux[] = {
++	HSCK1_B_MARK,
++};
++static const unsigned int hscif1_ctrl_b_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
++};
++static const unsigned int hscif1_ctrl_b_mux[] = {
++	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
++};
++/* - HSCIF2 ----------------------------------------------------------------- */
++static const unsigned int hscif2_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
++};
++static const unsigned int hscif2_data_a_mux[] = {
++	HRX2_A_MARK, HTX2_A_MARK,
++};
++static const unsigned int hscif2_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 10),
++};
++static const unsigned int hscif2_clk_a_mux[] = {
++	HSCK2_A_MARK,
++};
++static const unsigned int hscif2_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
++};
++static const unsigned int hscif2_ctrl_a_mux[] = {
++	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
++};
++
++static const unsigned int hscif2_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
++};
++static const unsigned int hscif2_data_b_mux[] = {
++	HRX2_B_MARK, HTX2_B_MARK,
++};
++static const unsigned int hscif2_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int hscif2_clk_b_mux[] = {
++	HSCK2_B_MARK,
++};
++static const unsigned int hscif2_ctrl_b_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
++};
++static const unsigned int hscif2_ctrl_b_mux[] = {
++	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
++};
++
++static const unsigned int hscif2_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
++};
++static const unsigned int hscif2_data_c_mux[] = {
++	HRX2_C_MARK, HTX2_C_MARK,
++};
++static const unsigned int hscif2_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 24),
++};
++static const unsigned int hscif2_clk_c_mux[] = {
++	HSCK2_C_MARK,
++};
++static const unsigned int hscif2_ctrl_c_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
++};
++static const unsigned int hscif2_ctrl_c_mux[] = {
++	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
++};
++/* - HSCIF3 ----------------------------------------------------------------- */
++static const unsigned int hscif3_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
++};
++static const unsigned int hscif3_data_a_mux[] = {
++	HRX3_A_MARK, HTX3_A_MARK,
++};
++static const unsigned int hscif3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int hscif3_clk_mux[] = {
++	HSCK3_MARK,
++};
++static const unsigned int hscif3_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
++};
++static const unsigned int hscif3_ctrl_mux[] = {
++	HRTS3_N_MARK, HCTS3_N_MARK,
++};
++
++static const unsigned int hscif3_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++};
++static const unsigned int hscif3_data_b_mux[] = {
++	HRX3_B_MARK, HTX3_B_MARK,
++};
++static const unsigned int hscif3_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int hscif3_data_c_mux[] = {
++	HRX3_C_MARK, HTX3_C_MARK,
++};
++static const unsigned int hscif3_data_d_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++};
++static const unsigned int hscif3_data_d_mux[] = {
++	HRX3_D_MARK, HTX3_D_MARK,
++};
++/* - HSCIF4 ----------------------------------------------------------------- */
++static const unsigned int hscif4_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++};
++static const unsigned int hscif4_data_a_mux[] = {
++	HRX4_A_MARK, HTX4_A_MARK,
++};
++static const unsigned int hscif4_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int hscif4_clk_mux[] = {
++	HSCK4_MARK,
++};
++static const unsigned int hscif4_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
++};
++static const unsigned int hscif4_ctrl_mux[] = {
++	HRTS4_N_MARK, HCTS4_N_MARK,
++};
++
++static const unsigned int hscif4_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
++};
++static const unsigned int hscif4_data_b_mux[] = {
++	HRX4_B_MARK, HTX4_B_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c1_a_pins[] = {
+ 	/* SDA, SCL */
+@@ -3673,6 +3880,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hscif0_data),
++	SH_PFC_PIN_GROUP(hscif0_clk),
++	SH_PFC_PIN_GROUP(hscif0_ctrl),
++	SH_PFC_PIN_GROUP(hscif1_data_a),
++	SH_PFC_PIN_GROUP(hscif1_clk_a),
++	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
++	SH_PFC_PIN_GROUP(hscif1_data_b),
++	SH_PFC_PIN_GROUP(hscif1_clk_b),
++	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
++	SH_PFC_PIN_GROUP(hscif2_data_a),
++	SH_PFC_PIN_GROUP(hscif2_clk_a),
++	SH_PFC_PIN_GROUP(hscif2_ctrl_a),
++	SH_PFC_PIN_GROUP(hscif2_data_b),
++	SH_PFC_PIN_GROUP(hscif2_clk_b),
++	SH_PFC_PIN_GROUP(hscif2_ctrl_b),
++	SH_PFC_PIN_GROUP(hscif2_data_c),
++	SH_PFC_PIN_GROUP(hscif2_clk_c),
++	SH_PFC_PIN_GROUP(hscif2_ctrl_c),
++	SH_PFC_PIN_GROUP(hscif3_data_a),
++	SH_PFC_PIN_GROUP(hscif3_clk),
++	SH_PFC_PIN_GROUP(hscif3_ctrl),
++	SH_PFC_PIN_GROUP(hscif3_data_b),
++	SH_PFC_PIN_GROUP(hscif3_data_c),
++	SH_PFC_PIN_GROUP(hscif3_data_d),
++	SH_PFC_PIN_GROUP(hscif4_data_a),
++	SH_PFC_PIN_GROUP(hscif4_clk),
++	SH_PFC_PIN_GROUP(hscif4_ctrl),
++	SH_PFC_PIN_GROUP(hscif4_data_b),
+ 	SH_PFC_PIN_GROUP(i2c1_a),
+ 	SH_PFC_PIN_GROUP(i2c1_b),
+ 	SH_PFC_PIN_GROUP(i2c2_a),
+@@ -3971,6 +4206,49 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const hscif0_groups[] = {
++	"hscif0_data",
++	"hscif0_clk",
++	"hscif0_ctrl",
++};
++
++static const char * const hscif1_groups[] = {
++	"hscif1_data_a",
++	"hscif1_clk_a",
++	"hscif1_ctrl_a",
++	"hscif1_data_b",
++	"hscif1_clk_b",
++	"hscif1_ctrl_b",
++};
++
++static const char * const hscif2_groups[] = {
++	"hscif2_data_a",
++	"hscif2_clk_a",
++	"hscif2_ctrl_a",
++	"hscif2_data_b",
++	"hscif2_clk_b",
++	"hscif2_ctrl_b",
++	"hscif2_data_c",
++	"hscif2_clk_c",
++	"hscif2_ctrl_c",
++};
++
++static const char * const hscif3_groups[] = {
++	"hscif3_data_a",
++	"hscif3_clk",
++	"hscif3_ctrl",
++	"hscif3_data_b",
++	"hscif3_data_c",
++	"hscif3_data_d",
++};
++
++static const char * const hscif4_groups[] = {
++	"hscif4_data_a",
++	"hscif4_clk",
++	"hscif4_ctrl",
++	"hscif4_data_b",
++};
++
+ static const char * const i2c1_groups[] = {
+ 	"i2c1_a",
+ 	"i2c1_b",
+@@ -4285,6 +4563,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(drif2),
+ 	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hscif0),
++	SH_PFC_FUNCTION(hscif1),
++	SH_PFC_FUNCTION(hscif2),
++	SH_PFC_FUNCTION(hscif3),
++	SH_PFC_FUNCTION(hscif4),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c6),
+-- 
+2.19.0
+
diff --git a/patches/0203-pinctrl-sh-pfc-r8a7795-Fix-trivial-typo-in-comment.patch b/patches/0203-pinctrl-sh-pfc-r8a7795-Fix-trivial-typo-in-comment.patch
new file mode 100644
index 00000000000000..ce4738d4146fea
--- /dev/null
+++ b/patches/0203-pinctrl-sh-pfc-r8a7795-Fix-trivial-typo-in-comment.patch
@@ -0,0 +1,31 @@
+From 271db9bcbfdbff88610b298a6a1f7a809f8dd421 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 9 Oct 2017 10:37:24 +0200
+Subject: [PATCH 0203/1795] pinctrl: sh-pfc: r8a7795: Fix trivial typo in
+ comment
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ecd54509a2fb89c533eb8984be4f6d24fb0c2e76)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 1b556a8dcd5e..e9ee6642a53c 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1508,7 +1508,7 @@ static const u16 pinmux_data[] = {
+ };
+ 
+ /*
+- * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
++ * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
+  * Physical layout rows: A - AW, cols: 1 - 39.
+  */
+ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+-- 
+2.19.0
+
diff --git a/patches/0204-pinctrl-sh-pfc-r8a7795-es1-Fix-trivial-typo-in-comme.patch b/patches/0204-pinctrl-sh-pfc-r8a7795-es1-Fix-trivial-typo-in-comme.patch
new file mode 100644
index 00000000000000..c61f4300e188b4
--- /dev/null
+++ b/patches/0204-pinctrl-sh-pfc-r8a7795-es1-Fix-trivial-typo-in-comme.patch
@@ -0,0 +1,31 @@
+From d748539639a409542656b6e22f64752bf2745d18 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 9 Oct 2017 10:37:24 +0200
+Subject: [PATCH 0204/1795] pinctrl: sh-pfc: r8a7795-es1: Fix trivial typo in
+ comment
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit bf3278feae63d3b8aaeaafa6c9e7c8b2fb236aae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index e7fdfa4efeaa..a575681cc98d 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -1443,7 +1443,7 @@ static const u16 pinmux_data[] = {
+ };
+ 
+ /*
+- * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
++ * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
+  * Physical layout rows: A - AW, cols: 1 - 39.
+  */
+ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+-- 
+2.19.0
+
diff --git a/patches/0205-pinctrl-sh-pfc-r8a7796-Fix-trivial-typo-in-comment.patch b/patches/0205-pinctrl-sh-pfc-r8a7796-Fix-trivial-typo-in-comment.patch
new file mode 100644
index 00000000000000..1dd33437954043
--- /dev/null
+++ b/patches/0205-pinctrl-sh-pfc-r8a7796-Fix-trivial-typo-in-comment.patch
@@ -0,0 +1,31 @@
+From 2abc6962ac1f2981d09ae3a3e979218924e83f88 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 9 Oct 2017 10:37:25 +0200
+Subject: [PATCH 0205/1795] pinctrl: sh-pfc: r8a7796: Fix trivial typo in
+ comment
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 94888a4dc39a15ae3a09e1ec4cca0f18cf03a218)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index b5bba8880537..79304027fac7 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -495,7 +495,7 @@ FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
+ #define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
+ #define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
+ 
+-/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
++/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
+ #define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
+ #define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
+ #define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
+-- 
+2.19.0
+
diff --git a/patches/0206-pinctrl-sh-pfc-r8a77995-Add-Audio-clock-pin-support.patch b/patches/0206-pinctrl-sh-pfc-r8a77995-Add-Audio-clock-pin-support.patch
new file mode 100644
index 00000000000000..038153fa80a157
--- /dev/null
+++ b/patches/0206-pinctrl-sh-pfc-r8a77995-Add-Audio-clock-pin-support.patch
@@ -0,0 +1,92 @@
+From ae0d89f075dfa3399a05d2fb2f170784011b84e2 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 10 Oct 2017 07:57:17 +0000
+Subject: [PATCH 0206/1795] pinctrl: sh-pfc: r8a77995: Add Audio clock pin
+ support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6e7b1ee885793ecfa8e1194f92e23856b6c07c41)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 42 +++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 3f67b8d4f050..fa000a91f881 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -936,6 +936,36 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+ };
+ 
++/* - AUDIO CLOCK ------------------------------------------------------------- */
++static const unsigned int audio_clk_a_pins[] = {
++	/* CLK A */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int audio_clk_a_mux[] = {
++	AUDIO_CLKA_MARK,
++};
++static const unsigned int audio_clk_b_pins[] = {
++	/* CLK B */
++	RCAR_GP_PIN(2, 27),
++};
++static const unsigned int audio_clk_b_mux[] = {
++	AUDIO_CLKB_MARK,
++};
++static const unsigned int audio_clkout_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(4, 5),
++};
++static const unsigned int audio_clkout_mux[] = {
++	AUDIO_CLKOUT_MARK,
++};
++static const unsigned int audio_clkout1_pins[] = {
++	/* CLKOUT1 */
++	RCAR_GP_PIN(4, 22),
++};
++static const unsigned int audio_clkout1_mux[] = {
++	AUDIO_CLKOUT1_MARK,
++};
++
+ /* - EtherAVB --------------------------------------------------------------- */
+ static const unsigned int avb0_link_pins[] = {
+ 	/* AVB0_LINK */
+@@ -1417,6 +1447,10 @@ static const unsigned int usb0_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(audio_clk_a),
++	SH_PFC_PIN_GROUP(audio_clk_b),
++	SH_PFC_PIN_GROUP(audio_clkout),
++	SH_PFC_PIN_GROUP(audio_clkout1),
+ 	SH_PFC_PIN_GROUP(avb0_link),
+ 	SH_PFC_PIN_GROUP(avb0_magic),
+ 	SH_PFC_PIN_GROUP(avb0_phy_int),
+@@ -1478,6 +1512,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb0),
+ };
+ 
++static const char * const audio_clk_groups[] = {
++	"audio_clk_a",
++	"audio_clk_b",
++	"audio_clkout",
++	"audio_clkout1",
++};
++
+ static const char * const avb0_groups[] = {
+ 	"avb0_link",
+ 	"avb0_magic",
+@@ -1591,6 +1632,7 @@ static const char * const usb0_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb0),
+ 	SH_PFC_FUNCTION(i2c0),
+ 	SH_PFC_FUNCTION(i2c1),
+-- 
+2.19.0
+
diff --git a/patches/0207-pinctrl-sh-pfc-r8a77995-Add-Audio-SSI-pin-support.patch b/patches/0207-pinctrl-sh-pfc-r8a77995-Add-Audio-SSI-pin-support.patch
new file mode 100644
index 00000000000000..dfbfabb111ee3a
--- /dev/null
+++ b/patches/0207-pinctrl-sh-pfc-r8a77995-Add-Audio-SSI-pin-support.patch
@@ -0,0 +1,110 @@
+From ea18f2b602ec0ffeb05758780d47ae98915ab143 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 10 Oct 2017 07:57:40 +0000
+Subject: [PATCH 0207/1795] pinctrl: sh-pfc: r8a77995: Add Audio SSI pin
+ support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7b9e64a6571ee9132f3515434b7047738cd28075)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 60 +++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index fa000a91f881..1e226c25ce7b 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1437,6 +1437,50 @@ static const unsigned int scif_clk_mux[] = {
+ 	SCIF_CLK_MARK,
+ };
+ 
++/* - SSI ---------------------------------------------------------------*/
++static const unsigned int ssi3_data_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(4, 3),
++};
++static const unsigned int ssi3_data_mux[] = {
++	SSI_SDATA3_MARK,
++};
++static const unsigned int ssi34_ctrl_pins[] = {
++	/* SCK,  WS */
++	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
++};
++static const unsigned int ssi34_ctrl_mux[] = {
++	SSI_SCK34_MARK, SSI_WS34_MARK,
++};
++static const unsigned int ssi4_ctrl_a_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
++};
++static const unsigned int ssi4_ctrl_a_mux[] = {
++	SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
++};
++static const unsigned int ssi4_data_a_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(4, 6),
++};
++static const unsigned int ssi4_data_a_mux[] = {
++	SSI_SDATA4_A_MARK,
++};
++static const unsigned int ssi4_ctrl_b_pins[] = {
++	/* SCK, WS */
++	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
++};
++static const unsigned int ssi4_ctrl_b_mux[] = {
++	SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
++};
++static const unsigned int ssi4_data_b_pins[] = {
++	/* SDATA */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int ssi4_data_b_mux[] = {
++	SSI_SDATA4_B_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+@@ -1509,6 +1553,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif5_data_b),
+ 	SH_PFC_PIN_GROUP(scif5_clk_b),
+ 	SH_PFC_PIN_GROUP(scif_clk),
++	SH_PFC_PIN_GROUP(ssi3_data),
++	SH_PFC_PIN_GROUP(ssi34_ctrl),
++	SH_PFC_PIN_GROUP(ssi4_ctrl_a),
++	SH_PFC_PIN_GROUP(ssi4_data_a),
++	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
++	SH_PFC_PIN_GROUP(ssi4_data_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ };
+ 
+@@ -1627,6 +1677,15 @@ static const char * const scif_clk_groups[] = {
+ 	"scif_clk",
+ };
+ 
++static const char * const ssi_groups[] = {
++	"ssi3_data",
++	"ssi34_ctrl",
++	"ssi4_ctrl_a",
++	"ssi4_data_a",
++	"ssi4_ctrl_b",
++	"ssi4_data_b",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -1650,6 +1709,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif4),
+ 	SH_PFC_FUNCTION(scif5),
+ 	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(ssi),
+ 	SH_PFC_FUNCTION(usb0),
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0208-pinctrl-sh-pfc-r8a77995-Remove-USB0_IDIN-and-USB0_ID.patch b/patches/0208-pinctrl-sh-pfc-r8a77995-Remove-USB0_IDIN-and-USB0_ID.patch
new file mode 100644
index 00000000000000..ef28a8d98fc42c
--- /dev/null
+++ b/patches/0208-pinctrl-sh-pfc-r8a77995-Remove-USB0_IDIN-and-USB0_ID.patch
@@ -0,0 +1,48 @@
+From 9330711de656995c0b9699c065968ccfc64ba1f0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 10 Oct 2017 13:09:37 +0200
+Subject: [PATCH 0208/1795] pinctrl: sh-pfc: r8a77995: Remove USB0_IDIN and
+ USB0_IDPU pins
+
+R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017
+removed the USB0_IDIN and USB0_IDPU pins on R-Car D3.
+
+This change has no functional impact, as these definitions were unused.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit d8ee17f4f2230446309240ed772ece1f8f4ac6fd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 1e226c25ce7b..89b7541ab1ed 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -198,8 +198,8 @@
+ #define GPSR6_0		FM(QSPI0_SPCLK)
+ 
+ /* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */		/* 4 */			/* 5 */		/* 6  - F */
+-#define IP0_3_0		FM(IRQ0_A)		FM(MSIOF2_SYNC_B)	FM(USB0_IDIN)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP0_7_4		FM(MSIOF2_SCK)		F_(0, 0)		FM(USB0_IDPU)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_3_0		FM(IRQ0_A)		FM(MSIOF2_SYNC_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_7_4		FM(MSIOF2_SCK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_11_8	FM(MSIOF2_TXD)		FM(SCL3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_15_12	FM(MSIOF2_RXD)		FM(SDA3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_19_16	FM(MLB_CLK)		FM(MSIOF2_SYNC_A)	FM(SCK5_A)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -522,10 +522,8 @@ static const u16 pinmux_data[] = {
+ 	/* IPSR0 */
+ 	PINMUX_IPSR_MSEL(IP0_3_0,	IRQ0_A, SEL_IRQ_0_0),
+ 	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SYNC_B, SEL_MSIOF2_1),
+-	PINMUX_IPSR_GPSR(IP0_3_0,	USB0_IDIN),
+ 
+ 	PINMUX_IPSR_GPSR(IP0_7_4,	MSIOF2_SCK),
+-	PINMUX_IPSR_GPSR(IP0_7_4,	USB0_IDPU),
+ 
+ 	PINMUX_IPSR_GPSR(IP0_11_8,	MSIOF2_TXD),
+ 	PINMUX_IPSR_MSEL(IP0_11_8,	SCL3_A, SEL_I2C3_0),
+-- 
+2.19.0
+
diff --git a/patches/0209-pinctrl-sh-pfc-r8a7745-Implement-voltage-switching-f.patch b/patches/0209-pinctrl-sh-pfc-r8a7745-Implement-voltage-switching-f.patch
new file mode 100644
index 00000000000000..9f9f9bf4f914c2
--- /dev/null
+++ b/patches/0209-pinctrl-sh-pfc-r8a7745-Implement-voltage-switching-f.patch
@@ -0,0 +1,32 @@
+From c4b5499846f7d31bcf1c8397112de811b4de5563 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 13 Oct 2017 15:49:15 +0100
+Subject: [PATCH 0209/1795] pinctrl: sh-pfc: r8a7745: Implement voltage
+ switching for SDHI
+
+Voltage switching is the same as on the r8a7794.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit df73da6317322e731edc53a95f28af7aab7bee00)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index a0ed220071f5..333a3470e842 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -5097,6 +5097,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
+ #ifdef CONFIG_PINCTRL_PFC_R8A7745
+ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
+ 	.name = "r8a77450_pfc",
++	.ops = &r8a7794_pinmux_ops,
+ 	.unlock_reg = 0xe6060000, /* PMMR */
+ 
+ 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+-- 
+2.19.0
+
diff --git a/patches/0210-pinctrl-sh-pfc-Remove-matching-on-plain-sh-pfc-platf.patch b/patches/0210-pinctrl-sh-pfc-Remove-matching-on-plain-sh-pfc-platf.patch
new file mode 100644
index 00000000000000..07b5a1728ed99a
--- /dev/null
+++ b/patches/0210-pinctrl-sh-pfc-Remove-matching-on-plain-sh-pfc-platf.patch
@@ -0,0 +1,55 @@
+From b4702ca7d1a9d772a2a335892d4bc1d7f4c6c8e6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 10:08:56 +0200
+Subject: [PATCH 0210/1795] pinctrl: sh-pfc: Remove matching on plain sh-pfc
+ platform device
+
+As of commit 8682b3c522c639f3 ("sh-pfc: Remove platform device
+registration"), plain "sh-pfc" platform devices are no longer created.
+Hence remove their match entry, and the now obsolete checks for missing
+device IDs and driver data.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit 35406b1fd68dec6d8b1badd69fcfb65646745dfd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/core.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 0c5e952461fd..9cdbaeab2cf1 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -569,7 +569,6 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 
+ static int sh_pfc_probe(struct platform_device *pdev)
+ {
+-	const struct platform_device_id *platid = platform_get_device_id(pdev);
+ #ifdef CONFIG_OF
+ 	struct device_node *np = pdev->dev.of_node;
+ #endif
+@@ -582,10 +581,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
+ 		info = of_device_get_match_data(&pdev->dev);
+ 	else
+ #endif
+-		info = platid ? (const void *)platid->driver_data : NULL;
+-
+-	if (info == NULL)
+-		return -ENODEV;
++		info = (const void *)platform_get_device_id(pdev)->driver_data;
+ 
+ 	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
+ 	if (pfc == NULL)
+@@ -683,7 +679,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
+ #ifdef CONFIG_PINCTRL_PFC_SHX3
+ 	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
+ #endif
+-	{ "sh-pfc", 0 },
+ 	{ },
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0211-pinctrl-sh-pfc-Drop-width-parameter-of-sh_pfc_-read-.patch b/patches/0211-pinctrl-sh-pfc-Drop-width-parameter-of-sh_pfc_-read-.patch
new file mode 100644
index 00000000000000..e1b07496e281b6
--- /dev/null
+++ b/patches/0211-pinctrl-sh-pfc-Drop-width-parameter-of-sh_pfc_-read-.patch
@@ -0,0 +1,237 @@
+From 56c693ef642533b43526e88787c1ee4a0a6287ba Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 11:03:11 +0200
+Subject: [PATCH 0211/1795] pinctrl: sh-pfc: Drop width parameter of
+ sh_pfc_{read,write}_reg()
+
+On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of
+sh_pfc_{read,write}_reg() already operate on 32-bit registers only.
+Hence make the 32-bit width implicit, and rename the functions to
+sh_pfc_{read,write}() to shorten lines.
+
+All accesses to 8-bit or 16-bit registers are still done using
+sh_pfc_{read,write}_raw_reg().
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit e16a2c7aced8422cda2b7f13ea3f3daccb150db6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/core.c            |  8 ++++----
+ drivers/pinctrl/sh-pfc/core.h            |  5 ++---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 12 ++++++------
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c     | 12 ++++++------
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c     | 12 ++++++------
+ drivers/pinctrl/sh-pfc/pinctrl.c         | 12 ++++++------
+ 6 files changed, 30 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 9cdbaeab2cf1..8b422ac07e57 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -175,19 +175,19 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
+ 	BUG();
+ }
+ 
+-u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
++u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
+ {
+-	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);
++	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
+ }
+ 
+-void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
++void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+ {
+ 	if (pfc->info->unlock_reg)
+ 		sh_pfc_write_raw_reg(
+ 			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
+ 			~data);
+ 
+-	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);
++	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
+ }
+ 
+ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
+diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
+index 6d598dd63720..dd215d36dcc8 100644
+--- a/drivers/pinctrl/sh-pfc/core.h
++++ b/drivers/pinctrl/sh-pfc/core.h
+@@ -26,9 +26,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
+ u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
+ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
+ 			  u32 data);
+-u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
+-void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
+-		      u32 data);
++u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
++void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
+ 
+ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
+ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index a575681cc98d..61bcae5dac52 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -5671,9 +5671,9 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
++	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
++	else if (sh_pfc_read(pfc, PUD + reg) & bit)
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5694,16 +5694,16 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
++	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+ 		enable |= bit;
+ 
+-	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
++	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+ 		updown |= bit;
+ 
+-	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
+-	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
++	sh_pfc_write(pfc, PUD + reg, updown);
++	sh_pfc_write(pfc, PUEN + reg, enable);
+ }
+ 
+ static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index e9ee6642a53c..eea29ef65ec4 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -5660,9 +5660,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
++	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
++	else if (sh_pfc_read(pfc, PUD + reg) & bit)
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5683,16 +5683,16 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
++	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+ 		enable |= bit;
+ 
+-	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
++	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+ 		updown |= bit;
+ 
+-	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
+-	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
++	sh_pfc_write(pfc, PUD + reg, updown);
++	sh_pfc_write(pfc, PUEN + reg, enable);
+ }
+ 
+ static const struct soc_device_attribute r8a7795es1[] = {
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 79304027fac7..970d97b9eb45 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -5724,9 +5724,9 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
++	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
++	else if (sh_pfc_read(pfc, PUD + reg) & bit)
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5747,16 +5747,16 @@ static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 	reg = info->reg;
+ 	bit = BIT(info->bit);
+ 
+-	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
++	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+ 		enable |= bit;
+ 
+-	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
++	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+ 		updown |= bit;
+ 
+-	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
+-	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
++	sh_pfc_write(pfc, PUD + reg, updown);
++	sh_pfc_write(pfc, PUEN + reg, enable);
+ }
+ 
+ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
+diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
+index 5c9d79981e6d..736634aee500 100644
+--- a/drivers/pinctrl/sh-pfc/pinctrl.c
++++ b/drivers/pinctrl/sh-pfc/pinctrl.c
+@@ -513,7 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
+ 		return -EINVAL;
+ 
+ 	spin_lock_irqsave(&pfc->lock, flags);
+-	val = sh_pfc_read_reg(pfc, reg, 32);
++	val = sh_pfc_read(pfc, reg);
+ 	spin_unlock_irqrestore(&pfc->lock, flags);
+ 
+ 	val = (val >> offset) & GENMASK(size - 1, 0);
+@@ -550,11 +550,11 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
+ 
+ 	spin_lock_irqsave(&pfc->lock, flags);
+ 
+-	val = sh_pfc_read_reg(pfc, reg, 32);
++	val = sh_pfc_read(pfc, reg);
+ 	val &= ~GENMASK(offset + size - 1, offset);
+ 	val |= strength << offset;
+ 
+-	sh_pfc_write_reg(pfc, reg, 32, val);
++	sh_pfc_write(pfc, reg, val);
+ 
+ 	spin_unlock_irqrestore(&pfc->lock, flags);
+ 
+@@ -645,7 +645,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
+ 			return bit;
+ 
+ 		spin_lock_irqsave(&pfc->lock, flags);
+-		val = sh_pfc_read_reg(pfc, pocctrl, 32);
++		val = sh_pfc_read(pfc, pocctrl);
+ 		spin_unlock_irqrestore(&pfc->lock, flags);
+ 
+ 		arg = (val & BIT(bit)) ? 3300 : 1800;
+@@ -716,12 +716,12 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
+ 				return -EINVAL;
+ 
+ 			spin_lock_irqsave(&pfc->lock, flags);
+-			val = sh_pfc_read_reg(pfc, pocctrl, 32);
++			val = sh_pfc_read(pfc, pocctrl);
+ 			if (mV == 3300)
+ 				val |= BIT(bit);
+ 			else
+ 				val &= ~BIT(bit);
+-			sh_pfc_write_reg(pfc, pocctrl, 32, val);
++			sh_pfc_write(pfc, pocctrl, val);
+ 			spin_unlock_irqrestore(&pfc->lock, flags);
+ 
+ 			break;
+-- 
+2.19.0
+
diff --git a/patches/0212-pinctrl-sh-pfc-Add-generic-bias-register-description.patch b/patches/0212-pinctrl-sh-pfc-Add-generic-bias-register-description.patch
new file mode 100644
index 00000000000000..3dd81c30a69362
--- /dev/null
+++ b/patches/0212-pinctrl-sh-pfc-Add-generic-bias-register-description.patch
@@ -0,0 +1,54 @@
+From 539ac74ff21330c0941901ad7e20bdd5be8f0923 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:16:14 +0200
+Subject: [PATCH 0212/1795] pinctrl: sh-pfc: Add generic bias register
+ description
+
+Add a generic way to describe bias registers (for pull-up/down control),
+like is already done for config and drive registers.
+
+This makes the sh-pfc core code aware of these registers, which will
+ease introducing suspend/resume support later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit beaa34d9080f20c9f0994071703c5d5c012afb56)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 8688b405e081..1914f4b5fef5 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -148,6 +148,17 @@ struct pinmux_drive_reg {
+ 	.reg = r, \
+ 	.fields =
+ 
++struct pinmux_bias_reg {
++	u32 puen;		/* Pull-enable or pull-up control register */
++	u32 pud;		/* Pull-up/down control register (optional) */
++	const u16 pins[32];
++};
++
++#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
++	.puen = r1,	\
++	.pud = r2,	\
++	.pins =
++
+ struct pinmux_data_reg {
+ 	u32 reg;
+ 	u8 reg_width;
+@@ -245,6 +256,7 @@ struct sh_pfc_soc_info {
+ 
+ 	const struct pinmux_cfg_reg *cfg_regs;
+ 	const struct pinmux_drive_reg *drive_regs;
++	const struct pinmux_bias_reg *bias_regs;
+ 	const struct pinmux_data_reg *data_regs;
+ 
+ 	const u16 *pinmux_data;
+-- 
+2.19.0
+
diff --git a/patches/0213-pinctrl-sh-pfc-Add-sh_pfc_pin_to_bias_reg-helper.patch b/patches/0213-pinctrl-sh-pfc-Add-sh_pfc_pin_to_bias_reg-helper.patch
new file mode 100644
index 00000000000000..003475af70be58
--- /dev/null
+++ b/patches/0213-pinctrl-sh-pfc-Add-sh_pfc_pin_to_bias_reg-helper.patch
@@ -0,0 +1,65 @@
+From 4192a50a337e1192a0d2ecd6edfad01e41019042 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 15:44:38 +0200
+Subject: [PATCH 0213/1795] pinctrl: sh-pfc: Add sh_pfc_pin_to_bias_reg()
+ helper
+
+Add a helper to look up bias registers and bit number for a specific
+pin, using the generic bias register description.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit acdb12453910d86dce3baa95c12178893c0aa32d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/core.c | 20 ++++++++++++++++++++
+ drivers/pinctrl/sh-pfc/core.h |  3 +++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 8b422ac07e57..01c408a3dee4 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -404,6 +404,26 @@ sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
+ 	return NULL;
+ }
+ 
++const struct pinmux_bias_reg *
++sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
++		       unsigned int *bit)
++{
++	unsigned int i, j;
++
++	for (i = 0; pfc->info->bias_regs[i].puen; i++) {
++		for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
++			if (pfc->info->bias_regs[i].pins[j] == pin) {
++				*bit = j;
++				return &pfc->info->bias_regs[i];
++			}
++		}
++	}
++
++	WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
++
++	return NULL;
++}
++
+ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
+ {
+ 	struct sh_pfc_pin_range *range;
+diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
+index dd215d36dcc8..460d996513ac 100644
+--- a/drivers/pinctrl/sh-pfc/core.h
++++ b/drivers/pinctrl/sh-pfc/core.h
+@@ -35,5 +35,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
+ const struct sh_pfc_bias_info *
+ sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
+ 			unsigned int num, unsigned int pin);
++const struct pinmux_bias_reg *
++sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
++		       unsigned int *bit);
+ 
+ #endif /* __SH_PFC_CORE_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0214-pinctrl-sh-pfc-r8a7795-es1-Use-generic-bias-register.patch b/patches/0214-pinctrl-sh-pfc-r8a7795-es1-Use-generic-bias-register.patch
new file mode 100644
index 00000000000000..f02faadb38ad37
--- /dev/null
+++ b/patches/0214-pinctrl-sh-pfc-r8a7795-es1-Use-generic-bias-register.patch
@@ -0,0 +1,572 @@
+From 0b35e6dabb38934976a2bdd994945d098e59db05 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:12:32 +0200
+Subject: [PATCH 0214/1795] pinctrl: sh-pfc: r8a7795-es1: Use generic bias
+ register description
+
+Move R-Car H3 ES1.x bias support over to the generic way to describe
+bias registers, which will be needed for suspend/resume support.
+
+As the new description is more compact, this decreases kernel size by
+ca. 304 bytes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit e1a16b5b426c5c10dbe2653af93d12d939855b65)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 499 ++++++++++++-----------
+ 1 file changed, 258 insertions(+), 241 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 61bcae5dac52..8042c9331a51 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -1449,6 +1449,7 @@ static const u16 pinmux_data[] = {
+ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+ #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
+ #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
++#define PIN_NONE U16_MAX
+ 
+ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+@@ -5438,242 +5439,261 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ 	return bit;
+ }
+ 
+-#define PUEN	0xe6060400
+-#define PUD	0xe6060440
+-
+-#define PU0	0x00
+-#define PU1	0x04
+-#define PU2	0x08
+-#define PU3	0x0c
+-#define PU4	0x10
+-#define PU5	0x14
+-#define PU6	0x18
+-
+-static const struct sh_pfc_bias_info bias_info[] = {
+-	{ RCAR_GP_PIN(2, 11),    PU0, 31 },	/* AVB_PHY_INT */
+-	{ RCAR_GP_PIN(2, 10),    PU0, 30 },	/* AVB_MAGIC */
+-	{ RCAR_GP_PIN(2,  9),    PU0, 29 },	/* AVB_MDC */
+-	{ PIN_NUMBER('A', 9),    PU0, 28 },	/* AVB_MDIO */
+-	{ PIN_NUMBER('A', 12),   PU0, 27 },	/* AVB_TXCREFCLK */
+-	{ PIN_NUMBER('B', 17),   PU0, 26 },	/* AVB_TD3 */
+-	{ PIN_NUMBER('A', 17),   PU0, 25 },	/* AVB_TD2 */
+-	{ PIN_NUMBER('B', 18),   PU0, 24 },	/* AVB_TD1 */
+-	{ PIN_NUMBER('A', 18),   PU0, 23 },	/* AVB_TD0 */
+-	{ PIN_NUMBER('A', 19),   PU0, 22 },	/* AVB_TXC */
+-	{ PIN_NUMBER('A', 8),    PU0, 21 },	/* AVB_TX_CTL */
+-	{ PIN_NUMBER('B', 14),   PU0, 20 },	/* AVB_RD3 */
+-	{ PIN_NUMBER('A', 14),   PU0, 19 },	/* AVB_RD2 */
+-	{ PIN_NUMBER('B', 13),   PU0, 18 },	/* AVB_RD1 */
+-	{ PIN_NUMBER('A', 13),   PU0, 17 },	/* AVB_RD0 */
+-	{ PIN_NUMBER('B', 19),   PU0, 16 },	/* AVB_RXC */
+-	{ PIN_NUMBER('A', 16),   PU0, 15 },	/* AVB_RX_CTL */
+-	{ PIN_NUMBER('V', 7),    PU0, 14 },	/* RPC_RESET# */
+-	{ PIN_NUMBER('V', 6),    PU0, 13 },	/* RPC_WP# */
+-	{ PIN_NUMBER('Y', 7),    PU0, 12 },	/* RPC_INT# */
+-	{ PIN_NUMBER('V', 5),    PU0, 11 },	/* QSPI1_SSL */
+-	{ PIN_A_NUMBER('C', 3),  PU0, 10 },	/* QSPI1_IO3 */
+-	{ PIN_A_NUMBER('E', 4),  PU0,  9 },	/* QSPI1_IO2 */
+-	{ PIN_A_NUMBER('E', 5),  PU0,  8 },	/* QSPI1_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 7),  PU0,  7 },	/* QSPI1_MOSI_IO0 */
+-	{ PIN_NUMBER('V', 3),    PU0,  6 },	/* QSPI1_SPCLK */
+-	{ PIN_NUMBER('Y', 3),    PU0,  5 },	/* QSPI0_SSL */
+-	{ PIN_A_NUMBER('B', 6),  PU0,  4 },	/* QSPI0_IO3 */
+-	{ PIN_NUMBER('Y', 6),    PU0,  3 },	/* QSPI0_IO2 */
+-	{ PIN_A_NUMBER('B', 4),  PU0,  2 },	/* QSPI0_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 5),  PU0,  1 },	/* QSPI0_MOSI_IO0 */
+-	{ PIN_NUMBER('W', 3),    PU0,  0 },	/* QSPI0_SPCLK */
+-
+-	{ RCAR_GP_PIN(1, 19),    PU1, 31 },	/* A19 */
+-	{ RCAR_GP_PIN(1, 18),    PU1, 30 },	/* A18 */
+-	{ RCAR_GP_PIN(1, 17),    PU1, 29 },	/* A17 */
+-	{ RCAR_GP_PIN(1, 16),    PU1, 28 },	/* A16 */
+-	{ RCAR_GP_PIN(1, 15),    PU1, 27 },	/* A15 */
+-	{ RCAR_GP_PIN(1, 14),    PU1, 26 },	/* A14 */
+-	{ RCAR_GP_PIN(1, 13),    PU1, 25 },	/* A13 */
+-	{ RCAR_GP_PIN(1, 12),    PU1, 24 },	/* A12 */
+-	{ RCAR_GP_PIN(1, 11),    PU1, 23 },	/* A11 */
+-	{ RCAR_GP_PIN(1, 10),    PU1, 22 },	/* A10 */
+-	{ RCAR_GP_PIN(1,  9),    PU1, 21 },	/* A9 */
+-	{ RCAR_GP_PIN(1,  8),    PU1, 20 },	/* A8 */
+-	{ RCAR_GP_PIN(1,  7),    PU1, 19 },	/* A7 */
+-	{ RCAR_GP_PIN(1,  6),    PU1, 18 },	/* A6 */
+-	{ RCAR_GP_PIN(1,  5),    PU1, 17 },	/* A5 */
+-	{ RCAR_GP_PIN(1,  4),    PU1, 16 },	/* A4 */
+-	{ RCAR_GP_PIN(1,  3),    PU1, 15 },	/* A3 */
+-	{ RCAR_GP_PIN(1,  2),    PU1, 14 },	/* A2 */
+-	{ RCAR_GP_PIN(1,  1),    PU1, 13 },	/* A1 */
+-	{ RCAR_GP_PIN(1,  0),    PU1, 12 },	/* A0 */
+-	{ RCAR_GP_PIN(2,  8),    PU1, 11 },	/* PWM2_A */
+-	{ RCAR_GP_PIN(2,  7),    PU1, 10 },	/* PWM1_A */
+-	{ RCAR_GP_PIN(2,  6),    PU1,  9 },	/* PWM0 */
+-	{ RCAR_GP_PIN(2,  5),    PU1,  8 },	/* IRQ5 */
+-	{ RCAR_GP_PIN(2,  4),    PU1,  7 },	/* IRQ4 */
+-	{ RCAR_GP_PIN(2,  3),    PU1,  6 },	/* IRQ3 */
+-	{ RCAR_GP_PIN(2,  2),    PU1,  5 },	/* IRQ2 */
+-	{ RCAR_GP_PIN(2,  1),    PU1,  4 },	/* IRQ1 */
+-	{ RCAR_GP_PIN(2,  0),    PU1,  3 },	/* IRQ0 */
+-	{ RCAR_GP_PIN(2, 14),    PU1,  2 },	/* AVB_AVTP_CAPTURE_A */
+-	{ RCAR_GP_PIN(2, 13),    PU1,  1 },	/* AVB_AVTP_MATCH_A */
+-	{ RCAR_GP_PIN(2, 12),    PU1,  0 },	/* AVB_LINK */
+-
+-	{ PIN_A_NUMBER('P', 8),  PU2, 31 },	/* DU_DOTCLKIN1 */
+-	{ PIN_A_NUMBER('P', 7),  PU2, 30 },	/* DU_DOTCLKIN0 */
+-	{ RCAR_GP_PIN(7,  3),    PU2, 29 },	/* HDMI1_CEC */
+-	{ RCAR_GP_PIN(7,  2),    PU2, 28 },	/* HDMI0_CEC */
+-	{ RCAR_GP_PIN(7,  1),    PU2, 27 },	/* AVS2 */
+-	{ RCAR_GP_PIN(7,  0),    PU2, 26 },	/* AVS1 */
+-	{ RCAR_GP_PIN(0, 15),    PU2, 25 },	/* D15 */
+-	{ RCAR_GP_PIN(0, 14),    PU2, 24 },	/* D14 */
+-	{ RCAR_GP_PIN(0, 13),    PU2, 23 },	/* D13 */
+-	{ RCAR_GP_PIN(0, 12),    PU2, 22 },	/* D12 */
+-	{ RCAR_GP_PIN(0, 11),    PU2, 21 },	/* D11 */
+-	{ RCAR_GP_PIN(0, 10),    PU2, 20 },	/* D10 */
+-	{ RCAR_GP_PIN(0,  9),    PU2, 19 },	/* D9 */
+-	{ RCAR_GP_PIN(0,  8),    PU2, 18 },	/* D8 */
+-	{ RCAR_GP_PIN(0,  7),    PU2, 17 },	/* D7 */
+-	{ RCAR_GP_PIN(0,  6),    PU2, 16 },	/* D6 */
+-	{ RCAR_GP_PIN(0,  5),    PU2, 15 },	/* D5 */
+-	{ RCAR_GP_PIN(0,  4),    PU2, 14 },	/* D4 */
+-	{ RCAR_GP_PIN(0,  3),    PU2, 13 },	/* D3 */
+-	{ RCAR_GP_PIN(0,  2),    PU2, 12 },	/* D2 */
+-	{ RCAR_GP_PIN(0,  1),    PU2, 11 },	/* D1 */
+-	{ RCAR_GP_PIN(0,  0),    PU2, 10 },	/* D0 */
+-	{ PIN_NUMBER('C', 1),    PU2,  9 },	/* PRESETOUT# */
+-	{ RCAR_GP_PIN(1, 27),    PU2,  8 },	/* EX_WAIT0_A */
+-	{ RCAR_GP_PIN(1, 26),    PU2,  7 },	/* WE1_N */
+-	{ RCAR_GP_PIN(1, 25),    PU2,  6 },	/* WE0_N */
+-	{ RCAR_GP_PIN(1, 24),    PU2,  5 },	/* RD_WR_N */
+-	{ RCAR_GP_PIN(1, 23),    PU2,  4 },	/* RD_N */
+-	{ RCAR_GP_PIN(1, 22),    PU2,  3 },	/* BS_N */
+-	{ RCAR_GP_PIN(1, 21),    PU2,  2 },	/* CS1_N_A26 */
+-	{ RCAR_GP_PIN(1, 20),    PU2,  1 },	/* CS0_N */
+-	{ PIN_NUMBER('F', 1),    PU2,  0 },	/* CLKOUT */
+-
+-	{ RCAR_GP_PIN(4,  9),    PU3, 31 },	/* SD3_DAT0 */
+-	{ RCAR_GP_PIN(4,  8),    PU3, 30 },	/* SD3_CMD */
+-	{ RCAR_GP_PIN(4,  7),    PU3, 29 },	/* SD3_CLK */
+-	{ RCAR_GP_PIN(4,  6),    PU3, 28 },	/* SD2_DS */
+-	{ RCAR_GP_PIN(4,  5),    PU3, 27 },	/* SD2_DAT3 */
+-	{ RCAR_GP_PIN(4,  4),    PU3, 26 },	/* SD2_DAT2 */
+-	{ RCAR_GP_PIN(4,  3),    PU3, 25 },	/* SD2_DAT1 */
+-	{ RCAR_GP_PIN(4,  2),    PU3, 24 },	/* SD2_DAT0 */
+-	{ RCAR_GP_PIN(4,  1),    PU3, 23 },	/* SD2_CMD */
+-	{ RCAR_GP_PIN(4,  0),    PU3, 22 },	/* SD2_CLK */
+-	{ RCAR_GP_PIN(3, 11),    PU3, 21 },	/* SD1_DAT3 */
+-	{ RCAR_GP_PIN(3, 10),    PU3, 20 },	/* SD1_DAT2 */
+-	{ RCAR_GP_PIN(3,  9),    PU3, 19 },	/* SD1_DAT1 */
+-	{ RCAR_GP_PIN(3,  8),    PU3, 18 },	/* SD1_DAT0 */
+-	{ RCAR_GP_PIN(3,  7),    PU3, 17 },	/* SD1_CMD */
+-	{ RCAR_GP_PIN(3,  6),    PU3, 16 },	/* SD1_CLK */
+-	{ RCAR_GP_PIN(3,  5),    PU3, 15 },	/* SD0_DAT3 */
+-	{ RCAR_GP_PIN(3,  4),    PU3, 14 },	/* SD0_DAT2 */
+-	{ RCAR_GP_PIN(3,  3),    PU3, 13 },	/* SD0_DAT1 */
+-	{ RCAR_GP_PIN(3,  2),    PU3, 12 },	/* SD0_DAT0 */
+-	{ RCAR_GP_PIN(3,  1),    PU3, 11 },	/* SD0_CMD */
+-	{ RCAR_GP_PIN(3,  0),    PU3, 10 },	/* SD0_CLK */
+-	{ PIN_A_NUMBER('T', 30), PU3,  9 },	/* ASEBRK */
+-	/* bit 8 n/a */
+-	{ PIN_A_NUMBER('R', 29), PU3,  7 },	/* TDI */
+-	{ PIN_A_NUMBER('R', 30), PU3,  6 },	/* TMS */
+-	{ PIN_A_NUMBER('T', 27), PU3,  5 },	/* TCK */
+-	{ PIN_A_NUMBER('R', 26), PU3,  4 },	/* TRST# */
+-	{ PIN_A_NUMBER('D', 39), PU3,  3 },	/* EXTALR*/
+-	{ PIN_A_NUMBER('D', 38), PU3,  2 },	/* FSCLKST# */
+-	{ PIN_A_NUMBER('R', 8),  PU3,  1 },	/* DU_DOTCLKIN3 */
+-	{ PIN_A_NUMBER('R', 7),  PU3,  0 },	/* DU_DOTCLKIN2 */
+-
+-	{ RCAR_GP_PIN(5, 19),    PU4, 31 },	/* MSIOF0_SS1 */
+-	{ RCAR_GP_PIN(5, 18),    PU4, 30 },	/* MSIOF0_SYNC */
+-	{ RCAR_GP_PIN(5, 17),    PU4, 29 },	/* MSIOF0_SCK */
+-	{ RCAR_GP_PIN(5, 16),    PU4, 28 },	/* HRTS0_N */
+-	{ RCAR_GP_PIN(5, 15),    PU4, 27 },	/* HCTS0_N */
+-	{ RCAR_GP_PIN(5, 14),    PU4, 26 },	/* HTX0 */
+-	{ RCAR_GP_PIN(5, 13),    PU4, 25 },	/* HRX0 */
+-	{ RCAR_GP_PIN(5, 12),    PU4, 24 },	/* HSCK0 */
+-	{ RCAR_GP_PIN(5, 11),    PU4, 23 },	/* RX2_A */
+-	{ RCAR_GP_PIN(5, 10),    PU4, 22 },	/* TX2_A */
+-	{ RCAR_GP_PIN(5,  9),    PU4, 21 },	/* SCK2 */
+-	{ RCAR_GP_PIN(5,  8),    PU4, 20 },	/* RTS1_N_TANS */
+-	{ RCAR_GP_PIN(5,  7),    PU4, 19 },	/* CTS1_N */
+-	{ RCAR_GP_PIN(5,  6),    PU4, 18 },	/* TX1_A */
+-	{ RCAR_GP_PIN(5,  5),    PU4, 17 },	/* RX1_A */
+-	{ RCAR_GP_PIN(5,  4),    PU4, 16 },	/* RTS0_N_TANS */
+-	{ RCAR_GP_PIN(5,  3),    PU4, 15 },	/* CTS0_N */
+-	{ RCAR_GP_PIN(5,  2),    PU4, 14 },	/* TX0 */
+-	{ RCAR_GP_PIN(5,  1),    PU4, 13 },	/* RX0 */
+-	{ RCAR_GP_PIN(5,  0),    PU4, 12 },	/* SCK0 */
+-	{ RCAR_GP_PIN(3, 15),    PU4, 11 },	/* SD1_WP */
+-	{ RCAR_GP_PIN(3, 14),    PU4, 10 },	/* SD1_CD */
+-	{ RCAR_GP_PIN(3, 13),    PU4,  9 },	/* SD0_WP */
+-	{ RCAR_GP_PIN(3, 12),    PU4,  8 },	/* SD0_CD */
+-	{ RCAR_GP_PIN(4, 17),    PU4,  7 },	/* SD3_DS */
+-	{ RCAR_GP_PIN(4, 16),    PU4,  6 },	/* SD3_DAT7 */
+-	{ RCAR_GP_PIN(4, 15),    PU4,  5 },	/* SD3_DAT6 */
+-	{ RCAR_GP_PIN(4, 14),    PU4,  4 },	/* SD3_DAT5 */
+-	{ RCAR_GP_PIN(4, 13),    PU4,  3 },	/* SD3_DAT4 */
+-	{ RCAR_GP_PIN(4, 12),    PU4,  2 },	/* SD3_DAT3 */
+-	{ RCAR_GP_PIN(4, 11),    PU4,  1 },	/* SD3_DAT2 */
+-	{ RCAR_GP_PIN(4, 10),    PU4,  0 },	/* SD3_DAT1 */
+-
+-	{ RCAR_GP_PIN(6, 24),    PU5, 31 },	/* USB0_PWEN */
+-	{ RCAR_GP_PIN(6, 23),    PU5, 30 },	/* AUDIO_CLKB_B */
+-	{ RCAR_GP_PIN(6, 22),    PU5, 29 },	/* AUDIO_CLKA_A */
+-	{ RCAR_GP_PIN(6, 21),    PU5, 28 },	/* SSI_SDATA9_A */
+-	{ RCAR_GP_PIN(6, 20),    PU5, 27 },	/* SSI_SDATA8 */
+-	{ RCAR_GP_PIN(6, 19),    PU5, 26 },	/* SSI_SDATA7 */
+-	{ RCAR_GP_PIN(6, 18),    PU5, 25 },	/* SSI_WS78 */
+-	{ RCAR_GP_PIN(6, 17),    PU5, 24 },	/* SSI_SCK78 */
+-	{ RCAR_GP_PIN(6, 16),    PU5, 23 },	/* SSI_SDATA6 */
+-	{ RCAR_GP_PIN(6, 15),    PU5, 22 },	/* SSI_WS6 */
+-	{ RCAR_GP_PIN(6, 14),    PU5, 21 },	/* SSI_SCK6 */
+-	{ RCAR_GP_PIN(6, 13),    PU5, 20 },	/* SSI_SDATA5 */
+-	{ RCAR_GP_PIN(6, 12),    PU5, 19 },	/* SSI_WS5 */
+-	{ RCAR_GP_PIN(6, 11),    PU5, 18 },	/* SSI_SCK5 */
+-	{ RCAR_GP_PIN(6, 10),    PU5, 17 },	/* SSI_SDATA4 */
+-	{ RCAR_GP_PIN(6,  9),    PU5, 16 },	/* SSI_WS4 */
+-	{ RCAR_GP_PIN(6,  8),    PU5, 15 },	/* SSI_SCK4 */
+-	{ RCAR_GP_PIN(6,  7),    PU5, 14 },	/* SSI_SDATA3 */
+-	{ RCAR_GP_PIN(6,  6),    PU5, 13 },	/* SSI_WS349 */
+-	{ RCAR_GP_PIN(6,  5),    PU5, 12 },	/* SSI_SCK349 */
+-	{ RCAR_GP_PIN(6,  4),    PU5, 11 },	/* SSI_SDATA2_A */
+-	{ RCAR_GP_PIN(6,  3),    PU5, 10 },	/* SSI_SDATA1_A */
+-	{ RCAR_GP_PIN(6,  2),    PU5,  9 },	/* SSI_SDATA0 */
+-	{ RCAR_GP_PIN(6,  1),    PU5,  8 },	/* SSI_WS01239 */
+-	{ RCAR_GP_PIN(6,  0),    PU5,  7 },	/* SSI_SCK01239 */
+-	{ PIN_NUMBER('H', 37),   PU5,  6 },	/* MLB_REF */
+-	{ RCAR_GP_PIN(5, 25),    PU5,  5 },	/* MLB_DAT */
+-	{ RCAR_GP_PIN(5, 24),    PU5,  4 },	/* MLB_SIG */
+-	{ RCAR_GP_PIN(5, 23),    PU5,  3 },	/* MLB_CLK */
+-	{ RCAR_GP_PIN(5, 22),    PU5,  2 },	/* MSIOF0_RXD */
+-	{ RCAR_GP_PIN(5, 21),    PU5,  1 },	/* MSIOF0_SS2 */
+-	{ RCAR_GP_PIN(5, 20),    PU5,  0 },	/* MSIOF0_TXD */
+-
+-	{ RCAR_GP_PIN(6, 31),    PU6,  6 },	/* USB31_OVC */
+-	{ RCAR_GP_PIN(6, 30),    PU6,  5 },	/* USB31_PWEN */
+-	{ RCAR_GP_PIN(6, 29),    PU6,  4 },	/* USB30_OVC */
+-	{ RCAR_GP_PIN(6, 28),    PU6,  3 },	/* USB30_PWEN */
+-	{ RCAR_GP_PIN(6, 27),    PU6,  2 },	/* USB1_OVC */
+-	{ RCAR_GP_PIN(6, 26),    PU6,  1 },	/* USB1_PWEN */
+-	{ RCAR_GP_PIN(6, 25),    PU6,  0 },	/* USB0_OVC */
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
++		[ 0] = PIN_NUMBER('W', 3),	/* QSPI0_SPCLK */
++		[ 1] = PIN_A_NUMBER('C', 5),	/* QSPI0_MOSI_IO0 */
++		[ 2] = PIN_A_NUMBER('B', 4),	/* QSPI0_MISO_IO1 */
++		[ 3] = PIN_NUMBER('Y', 6),	/* QSPI0_IO2 */
++		[ 4] = PIN_A_NUMBER('B', 6),	/* QSPI0_IO3 */
++		[ 5] = PIN_NUMBER('Y', 3),	/* QSPI0_SSL */
++		[ 6] = PIN_NUMBER('V', 3),	/* QSPI1_SPCLK */
++		[ 7] = PIN_A_NUMBER('C', 7),	/* QSPI1_MOSI_IO0 */
++		[ 8] = PIN_A_NUMBER('E', 5),	/* QSPI1_MISO_IO1 */
++		[ 9] = PIN_A_NUMBER('E', 4),	/* QSPI1_IO2 */
++		[10] = PIN_A_NUMBER('C', 3),	/* QSPI1_IO3 */
++		[11] = PIN_NUMBER('V', 5),	/* QSPI1_SSL */
++		[12] = PIN_NUMBER('Y', 7),	/* RPC_INT# */
++		[13] = PIN_NUMBER('V', 6),	/* RPC_WP# */
++		[14] = PIN_NUMBER('V', 7),	/* RPC_RESET# */
++		[15] = PIN_NUMBER('A', 16),	/* AVB_RX_CTL */
++		[16] = PIN_NUMBER('B', 19),	/* AVB_RXC */
++		[17] = PIN_NUMBER('A', 13),	/* AVB_RD0 */
++		[18] = PIN_NUMBER('B', 13),	/* AVB_RD1 */
++		[19] = PIN_NUMBER('A', 14),	/* AVB_RD2 */
++		[20] = PIN_NUMBER('B', 14),	/* AVB_RD3 */
++		[21] = PIN_NUMBER('A', 8),	/* AVB_TX_CTL */
++		[22] = PIN_NUMBER('A', 19),	/* AVB_TXC */
++		[23] = PIN_NUMBER('A', 18),	/* AVB_TD0 */
++		[24] = PIN_NUMBER('B', 18),	/* AVB_TD1 */
++		[25] = PIN_NUMBER('A', 17),	/* AVB_TD2 */
++		[26] = PIN_NUMBER('B', 17),	/* AVB_TD3 */
++		[27] = PIN_NUMBER('A', 12),	/* AVB_TXCREFCLK */
++		[28] = PIN_NUMBER('A', 9),	/* AVB_MDIO */
++		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
++		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
++		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
++	} },
++	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
++		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
++		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
++		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
++		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
++		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
++		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
++		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
++		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
++		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
++		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
++		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
++		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
++		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
++		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
++		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
++		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
++		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
++		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
++		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
++		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
++		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
++		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
++		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
++		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
++		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
++		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
++		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
++		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
++		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
++		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
++		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
++		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
++		[ 0] = PIN_NUMBER('F', 1),	/* CLKOUT */
++		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
++		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N_A26 */
++		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
++		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
++		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
++		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
++		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
++		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
++		[ 9] = PIN_NUMBER('C', 1),	/* PRESETOUT# */
++		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
++		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
++		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
++		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
++		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
++		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
++		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
++		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
++		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
++		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
++		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
++		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
++		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
++		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
++		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
++		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
++		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
++		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
++		[28] = RCAR_GP_PIN(7,  2),	/* HDMI0_CEC */
++		[29] = RCAR_GP_PIN(7,  3),	/* HDMI1_CEC */
++		[30] = PIN_A_NUMBER('P', 7),	/* DU_DOTCLKIN0 */
++		[31] = PIN_A_NUMBER('P', 8),	/* DU_DOTCLKIN1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
++		[ 0] = PIN_A_NUMBER('R', 7),	/* DU_DOTCLKIN2 */
++		[ 1] = PIN_A_NUMBER('R', 8),	/* DU_DOTCLKIN3 */
++		[ 2] = PIN_A_NUMBER('D', 38),	/* FSCLKST# */
++		[ 3] = PIN_A_NUMBER('D', 39),	/* EXTALR*/
++		[ 4] = PIN_A_NUMBER('R', 26),	/* TRST# */
++		[ 5] = PIN_A_NUMBER('T', 27),	/* TCK */
++		[ 6] = PIN_A_NUMBER('R', 30),	/* TMS */
++		[ 7] = PIN_A_NUMBER('R', 29),	/* TDI */
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_A_NUMBER('T', 30),	/* ASEBRK */
++		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
++		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
++		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
++		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
++		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
++		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
++		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
++		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
++		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
++		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
++		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
++		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
++		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
++		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
++		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
++		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
++		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
++		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
++		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
++		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
++		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
++		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
++		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
++		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
++		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
++		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
++		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
++		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
++		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
++		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
++		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
++		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
++		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
++		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
++		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
++		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
++		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
++		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N_TANS */
++		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
++		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
++		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N_TANS */
++		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
++		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
++		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
++		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
++		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
++		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
++		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
++		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
++		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
++		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
++		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
++		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
++		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
++		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
++		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
++		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
++		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
++		[ 6] = PIN_NUMBER('H', 37),	/* MLB_REF */
++		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
++		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
++		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
++		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
++		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
++		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
++		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
++		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
++		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
++		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
++		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
++		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
++		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
++		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
++		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
++		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
++		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
++		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
++		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
++		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
++		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
++		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
++		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
++		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
++		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
++	} },
++	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
++		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
++		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
++		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
++		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
++		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
++		[ 5] = RCAR_GP_PIN(6, 30),	/* USB31_PWEN */
++		[ 6] = RCAR_GP_PIN(6, 31),	/* USB31_OVC */
++		[ 7] = PIN_NONE,
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ /* sentinel */ },
+ };
+ 
+ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
+ 					       unsigned int pin)
+ {
+-	const struct sh_pfc_bias_info *info;
+-	u32 reg;
+-	u32 bit;
++	const struct pinmux_bias_reg *reg;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return PIN_CONFIG_BIAS_DISABLE;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
++	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read(pfc, PUD + reg) & bit)
++	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5682,28 +5702,24 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
+ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 				       unsigned int bias)
+ {
+-	const struct sh_pfc_bias_info *info;
++	const struct pinmux_bias_reg *reg;
+ 	u32 enable, updown;
+-	u32 reg;
+-	u32 bit;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
++	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+-		enable |= bit;
++		enable |= BIT(bit);
+ 
+-	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
++	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+-		updown |= bit;
++		updown |= BIT(bit);
+ 
+-	sh_pfc_write(pfc, PUD + reg, updown);
+-	sh_pfc_write(pfc, PUEN + reg, enable);
++	sh_pfc_write(pfc, reg->pud, updown);
++	sh_pfc_write(pfc, reg->puen, enable);
+ }
+ 
+ static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
+@@ -5728,6 +5744,7 @@ const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
+ 
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
++	.bias_regs = pinmux_bias_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0215-pinctrl-sh-pfc-r8a7795-Use-generic-bias-register-des.patch b/patches/0215-pinctrl-sh-pfc-r8a7795-Use-generic-bias-register-des.patch
new file mode 100644
index 00000000000000..98e7a4bf6a46d0
--- /dev/null
+++ b/patches/0215-pinctrl-sh-pfc-r8a7795-Use-generic-bias-register-des.patch
@@ -0,0 +1,571 @@
+From 8a4eb0e9cd6bad312e33f4b11e46cea2455dc569 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:13:35 +0200
+Subject: [PATCH 0215/1795] pinctrl: sh-pfc: r8a7795: Use generic bias register
+ description
+
+Move R-Car H3 ES2.0 bias support over to the generic way to describe
+bias registers, which will be needed for suspend/resume support.
+
+As the new description is more compact, this decreases kernel size by
+ca. 308 bytes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6f4b74f37576a6d1356b435c42df07d2b8dc9e13)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 499 ++++++++++++++-------------
+ 1 file changed, 258 insertions(+), 241 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index eea29ef65ec4..0a16dea0dace 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1514,6 +1514,7 @@ static const u16 pinmux_data[] = {
+ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+ #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
+ #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
++#define PIN_NONE U16_MAX
+ 
+ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+@@ -5427,242 +5428,261 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
+ 	return bit;
+ }
+ 
+-#define PUEN	0xe6060400
+-#define PUD	0xe6060440
+-
+-#define PU0	0x00
+-#define PU1	0x04
+-#define PU2	0x08
+-#define PU3	0x0c
+-#define PU4	0x10
+-#define PU5	0x14
+-#define PU6	0x18
+-
+-static const struct sh_pfc_bias_info bias_info[] = {
+-	{ RCAR_GP_PIN(2, 11),    PU0, 31 },	/* AVB_PHY_INT */
+-	{ RCAR_GP_PIN(2, 10),    PU0, 30 },	/* AVB_MAGIC */
+-	{ RCAR_GP_PIN(2,  9),    PU0, 29 },	/* AVB_MDC */
+-	{ PIN_NUMBER('A', 9),    PU0, 28 },	/* AVB_MDIO */
+-	{ PIN_NUMBER('A', 12),   PU0, 27 },	/* AVB_TXCREFCLK */
+-	{ PIN_NUMBER('B', 17),   PU0, 26 },	/* AVB_TD3 */
+-	{ PIN_NUMBER('A', 17),   PU0, 25 },	/* AVB_TD2 */
+-	{ PIN_NUMBER('B', 18),   PU0, 24 },	/* AVB_TD1 */
+-	{ PIN_NUMBER('A', 18),   PU0, 23 },	/* AVB_TD0 */
+-	{ PIN_NUMBER('A', 19),   PU0, 22 },	/* AVB_TXC */
+-	{ PIN_NUMBER('A', 8),    PU0, 21 },	/* AVB_TX_CTL */
+-	{ PIN_NUMBER('B', 14),   PU0, 20 },	/* AVB_RD3 */
+-	{ PIN_NUMBER('A', 14),   PU0, 19 },	/* AVB_RD2 */
+-	{ PIN_NUMBER('B', 13),   PU0, 18 },	/* AVB_RD1 */
+-	{ PIN_NUMBER('A', 13),   PU0, 17 },	/* AVB_RD0 */
+-	{ PIN_NUMBER('B', 19),   PU0, 16 },	/* AVB_RXC */
+-	{ PIN_NUMBER('A', 16),   PU0, 15 },	/* AVB_RX_CTL */
+-	{ PIN_NUMBER('V', 7),    PU0, 14 },	/* RPC_RESET# */
+-	{ PIN_NUMBER('V', 6),    PU0, 13 },	/* RPC_WP# */
+-	{ PIN_NUMBER('Y', 7),    PU0, 12 },	/* RPC_INT# */
+-	{ PIN_NUMBER('V', 5),    PU0, 11 },	/* QSPI1_SSL */
+-	{ PIN_A_NUMBER('C', 3),  PU0, 10 },	/* QSPI1_IO3 */
+-	{ PIN_A_NUMBER('E', 4),  PU0,  9 },	/* QSPI1_IO2 */
+-	{ PIN_A_NUMBER('E', 5),  PU0,  8 },	/* QSPI1_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 7),  PU0,  7 },	/* QSPI1_MOSI_IO0 */
+-	{ PIN_NUMBER('V', 3),    PU0,  6 },	/* QSPI1_SPCLK */
+-	{ PIN_NUMBER('Y', 3),    PU0,  5 },	/* QSPI0_SSL */
+-	{ PIN_A_NUMBER('B', 6),  PU0,  4 },	/* QSPI0_IO3 */
+-	{ PIN_NUMBER('Y', 6),    PU0,  3 },	/* QSPI0_IO2 */
+-	{ PIN_A_NUMBER('B', 4),  PU0,  2 },	/* QSPI0_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 5),  PU0,  1 },	/* QSPI0_MOSI_IO0 */
+-	{ PIN_NUMBER('W', 3),    PU0,  0 },	/* QSPI0_SPCLK */
+-
+-	{ RCAR_GP_PIN(1, 19),    PU1, 31 },	/* A19 */
+-	{ RCAR_GP_PIN(1, 18),    PU1, 30 },	/* A18 */
+-	{ RCAR_GP_PIN(1, 17),    PU1, 29 },	/* A17 */
+-	{ RCAR_GP_PIN(1, 16),    PU1, 28 },	/* A16 */
+-	{ RCAR_GP_PIN(1, 15),    PU1, 27 },	/* A15 */
+-	{ RCAR_GP_PIN(1, 14),    PU1, 26 },	/* A14 */
+-	{ RCAR_GP_PIN(1, 13),    PU1, 25 },	/* A13 */
+-	{ RCAR_GP_PIN(1, 12),    PU1, 24 },	/* A12 */
+-	{ RCAR_GP_PIN(1, 11),    PU1, 23 },	/* A11 */
+-	{ RCAR_GP_PIN(1, 10),    PU1, 22 },	/* A10 */
+-	{ RCAR_GP_PIN(1,  9),    PU1, 21 },	/* A9 */
+-	{ RCAR_GP_PIN(1,  8),    PU1, 20 },	/* A8 */
+-	{ RCAR_GP_PIN(1,  7),    PU1, 19 },	/* A7 */
+-	{ RCAR_GP_PIN(1,  6),    PU1, 18 },	/* A6 */
+-	{ RCAR_GP_PIN(1,  5),    PU1, 17 },	/* A5 */
+-	{ RCAR_GP_PIN(1,  4),    PU1, 16 },	/* A4 */
+-	{ RCAR_GP_PIN(1,  3),    PU1, 15 },	/* A3 */
+-	{ RCAR_GP_PIN(1,  2),    PU1, 14 },	/* A2 */
+-	{ RCAR_GP_PIN(1,  1),    PU1, 13 },	/* A1 */
+-	{ RCAR_GP_PIN(1,  0),    PU1, 12 },	/* A0 */
+-	{ RCAR_GP_PIN(2,  8),    PU1, 11 },	/* PWM2_A */
+-	{ RCAR_GP_PIN(2,  7),    PU1, 10 },	/* PWM1_A */
+-	{ RCAR_GP_PIN(2,  6),    PU1,  9 },	/* PWM0 */
+-	{ RCAR_GP_PIN(2,  5),    PU1,  8 },	/* IRQ5 */
+-	{ RCAR_GP_PIN(2,  4),    PU1,  7 },	/* IRQ4 */
+-	{ RCAR_GP_PIN(2,  3),    PU1,  6 },	/* IRQ3 */
+-	{ RCAR_GP_PIN(2,  2),    PU1,  5 },	/* IRQ2 */
+-	{ RCAR_GP_PIN(2,  1),    PU1,  4 },	/* IRQ1 */
+-	{ RCAR_GP_PIN(2,  0),    PU1,  3 },	/* IRQ0 */
+-	{ RCAR_GP_PIN(2, 14),    PU1,  2 },	/* AVB_AVTP_CAPTURE_A */
+-	{ RCAR_GP_PIN(2, 13),    PU1,  1 },	/* AVB_AVTP_MATCH_A */
+-	{ RCAR_GP_PIN(2, 12),    PU1,  0 },	/* AVB_LINK */
+-
+-	{ PIN_A_NUMBER('P', 8),  PU2, 31 },	/* DU_DOTCLKIN1 */
+-	{ PIN_A_NUMBER('P', 7),  PU2, 30 },	/* DU_DOTCLKIN0 */
+-	{ RCAR_GP_PIN(7,  3),    PU2, 29 },	/* HDMI1_CEC */
+-	{ RCAR_GP_PIN(7,  2),    PU2, 28 },	/* HDMI0_CEC */
+-	{ RCAR_GP_PIN(7,  1),    PU2, 27 },	/* AVS2 */
+-	{ RCAR_GP_PIN(7,  0),    PU2, 26 },	/* AVS1 */
+-	{ RCAR_GP_PIN(0, 15),    PU2, 25 },	/* D15 */
+-	{ RCAR_GP_PIN(0, 14),    PU2, 24 },	/* D14 */
+-	{ RCAR_GP_PIN(0, 13),    PU2, 23 },	/* D13 */
+-	{ RCAR_GP_PIN(0, 12),    PU2, 22 },	/* D12 */
+-	{ RCAR_GP_PIN(0, 11),    PU2, 21 },	/* D11 */
+-	{ RCAR_GP_PIN(0, 10),    PU2, 20 },	/* D10 */
+-	{ RCAR_GP_PIN(0,  9),    PU2, 19 },	/* D9 */
+-	{ RCAR_GP_PIN(0,  8),    PU2, 18 },	/* D8 */
+-	{ RCAR_GP_PIN(0,  7),    PU2, 17 },	/* D7 */
+-	{ RCAR_GP_PIN(0,  6),    PU2, 16 },	/* D6 */
+-	{ RCAR_GP_PIN(0,  5),    PU2, 15 },	/* D5 */
+-	{ RCAR_GP_PIN(0,  4),    PU2, 14 },	/* D4 */
+-	{ RCAR_GP_PIN(0,  3),    PU2, 13 },	/* D3 */
+-	{ RCAR_GP_PIN(0,  2),    PU2, 12 },	/* D2 */
+-	{ RCAR_GP_PIN(0,  1),    PU2, 11 },	/* D1 */
+-	{ RCAR_GP_PIN(0,  0),    PU2, 10 },	/* D0 */
+-	{ PIN_NUMBER('C', 1),    PU2,  9 },	/* PRESETOUT# */
+-	{ RCAR_GP_PIN(1, 27),    PU2,  8 },	/* EX_WAIT0_A */
+-	{ RCAR_GP_PIN(1, 26),    PU2,  7 },	/* WE1_N */
+-	{ RCAR_GP_PIN(1, 25),    PU2,  6 },	/* WE0_N */
+-	{ RCAR_GP_PIN(1, 24),    PU2,  5 },	/* RD_WR_N */
+-	{ RCAR_GP_PIN(1, 23),    PU2,  4 },	/* RD_N */
+-	{ RCAR_GP_PIN(1, 22),    PU2,  3 },	/* BS_N */
+-	{ RCAR_GP_PIN(1, 21),    PU2,  2 },	/* CS1_N */
+-	{ RCAR_GP_PIN(1, 20),    PU2,  1 },	/* CS0_N */
+-	{ PIN_NUMBER('F', 1),    PU2,  0 },	/* CLKOUT */
+-
+-	{ RCAR_GP_PIN(4,  9),    PU3, 31 },	/* SD3_DAT0 */
+-	{ RCAR_GP_PIN(4,  8),    PU3, 30 },	/* SD3_CMD */
+-	{ RCAR_GP_PIN(4,  7),    PU3, 29 },	/* SD3_CLK */
+-	{ RCAR_GP_PIN(4,  6),    PU3, 28 },	/* SD2_DS */
+-	{ RCAR_GP_PIN(4,  5),    PU3, 27 },	/* SD2_DAT3 */
+-	{ RCAR_GP_PIN(4,  4),    PU3, 26 },	/* SD2_DAT2 */
+-	{ RCAR_GP_PIN(4,  3),    PU3, 25 },	/* SD2_DAT1 */
+-	{ RCAR_GP_PIN(4,  2),    PU3, 24 },	/* SD2_DAT0 */
+-	{ RCAR_GP_PIN(4,  1),    PU3, 23 },	/* SD2_CMD */
+-	{ RCAR_GP_PIN(4,  0),    PU3, 22 },	/* SD2_CLK */
+-	{ RCAR_GP_PIN(3, 11),    PU3, 21 },	/* SD1_DAT3 */
+-	{ RCAR_GP_PIN(3, 10),    PU3, 20 },	/* SD1_DAT2 */
+-	{ RCAR_GP_PIN(3,  9),    PU3, 19 },	/* SD1_DAT1 */
+-	{ RCAR_GP_PIN(3,  8),    PU3, 18 },	/* SD1_DAT0 */
+-	{ RCAR_GP_PIN(3,  7),    PU3, 17 },	/* SD1_CMD */
+-	{ RCAR_GP_PIN(3,  6),    PU3, 16 },	/* SD1_CLK */
+-	{ RCAR_GP_PIN(3,  5),    PU3, 15 },	/* SD0_DAT3 */
+-	{ RCAR_GP_PIN(3,  4),    PU3, 14 },	/* SD0_DAT2 */
+-	{ RCAR_GP_PIN(3,  3),    PU3, 13 },	/* SD0_DAT1 */
+-	{ RCAR_GP_PIN(3,  2),    PU3, 12 },	/* SD0_DAT0 */
+-	{ RCAR_GP_PIN(3,  1),    PU3, 11 },	/* SD0_CMD */
+-	{ RCAR_GP_PIN(3,  0),    PU3, 10 },	/* SD0_CLK */
+-	{ PIN_A_NUMBER('T', 30), PU3,  9 },	/* ASEBRK */
+-	/* bit 8 n/a */
+-	{ PIN_A_NUMBER('R', 29), PU3,  7 },	/* TDI */
+-	{ PIN_A_NUMBER('R', 30), PU3,  6 },	/* TMS */
+-	{ PIN_A_NUMBER('T', 27), PU3,  5 },	/* TCK */
+-	{ PIN_A_NUMBER('R', 26), PU3,  4 },	/* TRST# */
+-	{ PIN_A_NUMBER('D', 39), PU3,  3 },	/* EXTALR*/
+-	{ PIN_A_NUMBER('D', 38), PU3,  2 },	/* FSCLKST# */
+-	{ PIN_A_NUMBER('R', 8),  PU3,  1 },	/* DU_DOTCLKIN3 */
+-	{ PIN_A_NUMBER('R', 7),  PU3,  0 },	/* DU_DOTCLKIN2 */
+-
+-	{ RCAR_GP_PIN(5, 19),    PU4, 31 },	/* MSIOF0_SS1 */
+-	{ RCAR_GP_PIN(5, 18),    PU4, 30 },	/* MSIOF0_SYNC */
+-	{ RCAR_GP_PIN(5, 17),    PU4, 29 },	/* MSIOF0_SCK */
+-	{ RCAR_GP_PIN(5, 16),    PU4, 28 },	/* HRTS0_N */
+-	{ RCAR_GP_PIN(5, 15),    PU4, 27 },	/* HCTS0_N */
+-	{ RCAR_GP_PIN(5, 14),    PU4, 26 },	/* HTX0 */
+-	{ RCAR_GP_PIN(5, 13),    PU4, 25 },	/* HRX0 */
+-	{ RCAR_GP_PIN(5, 12),    PU4, 24 },	/* HSCK0 */
+-	{ RCAR_GP_PIN(5, 11),    PU4, 23 },	/* RX2_A */
+-	{ RCAR_GP_PIN(5, 10),    PU4, 22 },	/* TX2_A */
+-	{ RCAR_GP_PIN(5,  9),    PU4, 21 },	/* SCK2 */
+-	{ RCAR_GP_PIN(5,  8),    PU4, 20 },	/* RTS1_N_TANS */
+-	{ RCAR_GP_PIN(5,  7),    PU4, 19 },	/* CTS1_N */
+-	{ RCAR_GP_PIN(5,  6),    PU4, 18 },	/* TX1_A */
+-	{ RCAR_GP_PIN(5,  5),    PU4, 17 },	/* RX1_A */
+-	{ RCAR_GP_PIN(5,  4),    PU4, 16 },	/* RTS0_N_TANS */
+-	{ RCAR_GP_PIN(5,  3),    PU4, 15 },	/* CTS0_N */
+-	{ RCAR_GP_PIN(5,  2),    PU4, 14 },	/* TX0 */
+-	{ RCAR_GP_PIN(5,  1),    PU4, 13 },	/* RX0 */
+-	{ RCAR_GP_PIN(5,  0),    PU4, 12 },	/* SCK0 */
+-	{ RCAR_GP_PIN(3, 15),    PU4, 11 },	/* SD1_WP */
+-	{ RCAR_GP_PIN(3, 14),    PU4, 10 },	/* SD1_CD */
+-	{ RCAR_GP_PIN(3, 13),    PU4,  9 },	/* SD0_WP */
+-	{ RCAR_GP_PIN(3, 12),    PU4,  8 },	/* SD0_CD */
+-	{ RCAR_GP_PIN(4, 17),    PU4,  7 },	/* SD3_DS */
+-	{ RCAR_GP_PIN(4, 16),    PU4,  6 },	/* SD3_DAT7 */
+-	{ RCAR_GP_PIN(4, 15),    PU4,  5 },	/* SD3_DAT6 */
+-	{ RCAR_GP_PIN(4, 14),    PU4,  4 },	/* SD3_DAT5 */
+-	{ RCAR_GP_PIN(4, 13),    PU4,  3 },	/* SD3_DAT4 */
+-	{ RCAR_GP_PIN(4, 12),    PU4,  2 },	/* SD3_DAT3 */
+-	{ RCAR_GP_PIN(4, 11),    PU4,  1 },	/* SD3_DAT2 */
+-	{ RCAR_GP_PIN(4, 10),    PU4,  0 },	/* SD3_DAT1 */
+-
+-	{ RCAR_GP_PIN(6, 24),    PU5, 31 },	/* USB0_PWEN */
+-	{ RCAR_GP_PIN(6, 23),    PU5, 30 },	/* AUDIO_CLKB_B */
+-	{ RCAR_GP_PIN(6, 22),    PU5, 29 },	/* AUDIO_CLKA_A */
+-	{ RCAR_GP_PIN(6, 21),    PU5, 28 },	/* SSI_SDATA9_A */
+-	{ RCAR_GP_PIN(6, 20),    PU5, 27 },	/* SSI_SDATA8 */
+-	{ RCAR_GP_PIN(6, 19),    PU5, 26 },	/* SSI_SDATA7 */
+-	{ RCAR_GP_PIN(6, 18),    PU5, 25 },	/* SSI_WS78 */
+-	{ RCAR_GP_PIN(6, 17),    PU5, 24 },	/* SSI_SCK78 */
+-	{ RCAR_GP_PIN(6, 16),    PU5, 23 },	/* SSI_SDATA6 */
+-	{ RCAR_GP_PIN(6, 15),    PU5, 22 },	/* SSI_WS6 */
+-	{ RCAR_GP_PIN(6, 14),    PU5, 21 },	/* SSI_SCK6 */
+-	{ RCAR_GP_PIN(6, 13),    PU5, 20 },	/* SSI_SDATA5 */
+-	{ RCAR_GP_PIN(6, 12),    PU5, 19 },	/* SSI_WS5 */
+-	{ RCAR_GP_PIN(6, 11),    PU5, 18 },	/* SSI_SCK5 */
+-	{ RCAR_GP_PIN(6, 10),    PU5, 17 },	/* SSI_SDATA4 */
+-	{ RCAR_GP_PIN(6,  9),    PU5, 16 },	/* SSI_WS4 */
+-	{ RCAR_GP_PIN(6,  8),    PU5, 15 },	/* SSI_SCK4 */
+-	{ RCAR_GP_PIN(6,  7),    PU5, 14 },	/* SSI_SDATA3 */
+-	{ RCAR_GP_PIN(6,  6),    PU5, 13 },	/* SSI_WS349 */
+-	{ RCAR_GP_PIN(6,  5),    PU5, 12 },	/* SSI_SCK349 */
+-	{ RCAR_GP_PIN(6,  4),    PU5, 11 },	/* SSI_SDATA2_A */
+-	{ RCAR_GP_PIN(6,  3),    PU5, 10 },	/* SSI_SDATA1_A */
+-	{ RCAR_GP_PIN(6,  2),    PU5,  9 },	/* SSI_SDATA0 */
+-	{ RCAR_GP_PIN(6,  1),    PU5,  8 },	/* SSI_WS01239 */
+-	{ RCAR_GP_PIN(6,  0),    PU5,  7 },	/* SSI_SCK01239 */
+-	{ PIN_NUMBER('H', 37),   PU5,  6 },	/* MLB_REF */
+-	{ RCAR_GP_PIN(5, 25),    PU5,  5 },	/* MLB_DAT */
+-	{ RCAR_GP_PIN(5, 24),    PU5,  4 },	/* MLB_SIG */
+-	{ RCAR_GP_PIN(5, 23),    PU5,  3 },	/* MLB_CLK */
+-	{ RCAR_GP_PIN(5, 22),    PU5,  2 },	/* MSIOF0_RXD */
+-	{ RCAR_GP_PIN(5, 21),    PU5,  1 },	/* MSIOF0_SS2 */
+-	{ RCAR_GP_PIN(5, 20),    PU5,  0 },	/* MSIOF0_TXD */
+-
+-	{ RCAR_GP_PIN(6, 31),    PU6,  6 },	/* USB2_CH3_OVC */
+-	{ RCAR_GP_PIN(6, 30),    PU6,  5 },	/* USB2_CH3_PWEN */
+-	{ RCAR_GP_PIN(6, 29),    PU6,  4 },	/* USB30_OVC */
+-	{ RCAR_GP_PIN(6, 28),    PU6,  3 },	/* USB30_PWEN */
+-	{ RCAR_GP_PIN(6, 27),    PU6,  2 },	/* USB1_OVC */
+-	{ RCAR_GP_PIN(6, 26),    PU6,  1 },	/* USB1_PWEN */
+-	{ RCAR_GP_PIN(6, 25),    PU6,  0 },	/* USB0_OVC */
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
++		[ 0] = PIN_NUMBER('W', 3),	/* QSPI0_SPCLK */
++		[ 1] = PIN_A_NUMBER('C', 5),	/* QSPI0_MOSI_IO0 */
++		[ 2] = PIN_A_NUMBER('B', 4),	/* QSPI0_MISO_IO1 */
++		[ 3] = PIN_NUMBER('Y', 6),	/* QSPI0_IO2 */
++		[ 4] = PIN_A_NUMBER('B', 6),	/* QSPI0_IO3 */
++		[ 5] = PIN_NUMBER('Y', 3),	/* QSPI0_SSL */
++		[ 6] = PIN_NUMBER('V', 3),	/* QSPI1_SPCLK */
++		[ 7] = PIN_A_NUMBER('C', 7),	/* QSPI1_MOSI_IO0 */
++		[ 8] = PIN_A_NUMBER('E', 5),	/* QSPI1_MISO_IO1 */
++		[ 9] = PIN_A_NUMBER('E', 4),	/* QSPI1_IO2 */
++		[10] = PIN_A_NUMBER('C', 3),	/* QSPI1_IO3 */
++		[11] = PIN_NUMBER('V', 5),	/* QSPI1_SSL */
++		[12] = PIN_NUMBER('Y', 7),	/* RPC_INT# */
++		[13] = PIN_NUMBER('V', 6),	/* RPC_WP# */
++		[14] = PIN_NUMBER('V', 7),	/* RPC_RESET# */
++		[15] = PIN_NUMBER('A', 16),	/* AVB_RX_CTL */
++		[16] = PIN_NUMBER('B', 19),	/* AVB_RXC */
++		[17] = PIN_NUMBER('A', 13),	/* AVB_RD0 */
++		[18] = PIN_NUMBER('B', 13),	/* AVB_RD1 */
++		[19] = PIN_NUMBER('A', 14),	/* AVB_RD2 */
++		[20] = PIN_NUMBER('B', 14),	/* AVB_RD3 */
++		[21] = PIN_NUMBER('A', 8),	/* AVB_TX_CTL */
++		[22] = PIN_NUMBER('A', 19),	/* AVB_TXC */
++		[23] = PIN_NUMBER('A', 18),	/* AVB_TD0 */
++		[24] = PIN_NUMBER('B', 18),	/* AVB_TD1 */
++		[25] = PIN_NUMBER('A', 17),	/* AVB_TD2 */
++		[26] = PIN_NUMBER('B', 17),	/* AVB_TD3 */
++		[27] = PIN_NUMBER('A', 12),	/* AVB_TXCREFCLK */
++		[28] = PIN_NUMBER('A', 9),	/* AVB_MDIO */
++		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
++		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
++		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
++	} },
++	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
++		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
++		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
++		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
++		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
++		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
++		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
++		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
++		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
++		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
++		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
++		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
++		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
++		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
++		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
++		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
++		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
++		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
++		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
++		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
++		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
++		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
++		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
++		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
++		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
++		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
++		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
++		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
++		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
++		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
++		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
++		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
++		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
++		[ 0] = PIN_NUMBER('F', 1),	/* CLKOUT */
++		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
++		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
++		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
++		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
++		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
++		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
++		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
++		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
++		[ 9] = PIN_NUMBER('C', 1),	/* PRESETOUT# */
++		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
++		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
++		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
++		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
++		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
++		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
++		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
++		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
++		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
++		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
++		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
++		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
++		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
++		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
++		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
++		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
++		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
++		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
++		[28] = RCAR_GP_PIN(7,  2),	/* HDMI0_CEC */
++		[29] = RCAR_GP_PIN(7,  3),	/* HDMI1_CEC */
++		[30] = PIN_A_NUMBER('P', 7),	/* DU_DOTCLKIN0 */
++		[31] = PIN_A_NUMBER('P', 8),	/* DU_DOTCLKIN1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
++		[ 0] = PIN_A_NUMBER('R', 7),	/* DU_DOTCLKIN2 */
++		[ 1] = PIN_A_NUMBER('R', 8),	/* DU_DOTCLKIN3 */
++		[ 2] = PIN_A_NUMBER('D', 38),	/* FSCLKST# */
++		[ 3] = PIN_A_NUMBER('D', 39),	/* EXTALR*/
++		[ 4] = PIN_A_NUMBER('R', 26),	/* TRST# */
++		[ 5] = PIN_A_NUMBER('T', 27),	/* TCK */
++		[ 6] = PIN_A_NUMBER('R', 30),	/* TMS */
++		[ 7] = PIN_A_NUMBER('R', 29),	/* TDI */
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_A_NUMBER('T', 30),	/* ASEBRK */
++		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
++		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
++		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
++		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
++		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
++		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
++		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
++		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
++		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
++		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
++		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
++		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
++		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
++		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
++		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
++		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
++		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
++		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
++		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
++		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
++		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
++		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
++		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
++		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
++		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
++		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
++		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
++		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
++		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
++		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
++		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
++		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
++		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
++		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
++		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
++		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
++		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
++		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N_TANS */
++		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
++		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
++		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N_TANS */
++		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
++		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
++		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
++		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
++		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
++		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
++		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
++		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
++		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
++		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
++		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
++		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
++		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
++		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
++		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
++		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
++		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
++		[ 6] = PIN_NUMBER('H', 37),	/* MLB_REF */
++		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
++		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
++		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
++		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
++		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
++		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
++		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
++		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
++		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
++		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
++		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
++		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
++		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
++		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
++		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
++		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
++		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
++		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
++		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
++		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
++		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
++		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
++		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
++		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
++		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
++	} },
++	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
++		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
++		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
++		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
++		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
++		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
++		[ 5] = RCAR_GP_PIN(6, 30),	/* USB2_CH3_PWEN */
++		[ 6] = RCAR_GP_PIN(6, 31),	/* USB2_CH3_OVC */
++		[ 7] = PIN_NONE,
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ /* sentinel */ },
+ };
+ 
+ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
+ 					    unsigned int pin)
+ {
+-	const struct sh_pfc_bias_info *info;
+-	u32 reg;
+-	u32 bit;
++	const struct pinmux_bias_reg *reg;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return PIN_CONFIG_BIAS_DISABLE;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
++	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read(pfc, PUD + reg) & bit)
++	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5671,28 +5691,24 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
+ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 				   unsigned int bias)
+ {
+-	const struct sh_pfc_bias_info *info;
++	const struct pinmux_bias_reg *reg;
+ 	u32 enable, updown;
+-	u32 reg;
+-	u32 bit;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
++	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+-		enable |= bit;
++		enable |= BIT(bit);
+ 
+-	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
++	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+-		updown |= bit;
++		updown |= BIT(bit);
+ 
+-	sh_pfc_write(pfc, PUD + reg, updown);
+-	sh_pfc_write(pfc, PUEN + reg, enable);
++	sh_pfc_write(pfc, reg->pud, updown);
++	sh_pfc_write(pfc, reg->puen, enable);
+ }
+ 
+ static const struct soc_device_attribute r8a7795es1[] = {
+@@ -5731,6 +5747,7 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = {
+ 
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
++	.bias_regs = pinmux_bias_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0216-pinctrl-sh-pfc-r8a7796-Use-generic-bias-register-des.patch b/patches/0216-pinctrl-sh-pfc-r8a7796-Use-generic-bias-register-des.patch
new file mode 100644
index 00000000000000..0e269e1ec3bf85
--- /dev/null
+++ b/patches/0216-pinctrl-sh-pfc-r8a7796-Use-generic-bias-register-des.patch
@@ -0,0 +1,571 @@
+From 4d8a0298a38b8b7b1607cf463850d5f51f0bde79 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:14:29 +0200
+Subject: [PATCH 0216/1795] pinctrl: sh-pfc: r8a7796: Use generic bias register
+ description
+
+Move R-Car M3-W bias support over to the generic way to describe bias
+registers, which will be needed for suspend/resume support.
+
+As the new description is more compact, this decreases kernel size by
+ca. 304 bytes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 58668a67afa19a445f6446d7abc1636ad5237c68)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 499 ++++++++++++++-------------
+ 1 file changed, 258 insertions(+), 241 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 970d97b9eb45..ebf38ea8abbe 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -1518,6 +1518,7 @@ static const u16 pinmux_data[] = {
+ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+ #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
+ #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
++#define PIN_NONE U16_MAX
+ 
+ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+@@ -5491,242 +5492,261 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
+ 	return bit;
+ }
+ 
+-#define PUEN	0xe6060400
+-#define PUD	0xe6060440
+-
+-#define PU0	0x00
+-#define PU1	0x04
+-#define PU2	0x08
+-#define PU3	0x0c
+-#define PU4	0x10
+-#define PU5	0x14
+-#define PU6	0x18
+-
+-static const struct sh_pfc_bias_info bias_info[] = {
+-	{ RCAR_GP_PIN(2, 11),    PU0, 31 },	/* AVB_PHY_INT */
+-	{ RCAR_GP_PIN(2, 10),    PU0, 30 },	/* AVB_MAGIC */
+-	{ RCAR_GP_PIN(2,  9),    PU0, 29 },	/* AVB_MDC */
+-	{ PIN_NUMBER('A', 9),    PU0, 28 },	/* AVB_MDIO */
+-	{ PIN_NUMBER('A', 12),   PU0, 27 },	/* AVB_TXCREFCLK */
+-	{ PIN_NUMBER('B', 17),   PU0, 26 },	/* AVB_TD3 */
+-	{ PIN_NUMBER('A', 17),   PU0, 25 },	/* AVB_TD2 */
+-	{ PIN_NUMBER('B', 18),   PU0, 24 },	/* AVB_TD1 */
+-	{ PIN_NUMBER('A', 18),   PU0, 23 },	/* AVB_TD0 */
+-	{ PIN_NUMBER('A', 19),   PU0, 22 },	/* AVB_TXC */
+-	{ PIN_NUMBER('A', 8),    PU0, 21 },	/* AVB_TX_CTL */
+-	{ PIN_NUMBER('B', 14),   PU0, 20 },	/* AVB_RD3 */
+-	{ PIN_NUMBER('A', 14),   PU0, 19 },	/* AVB_RD2 */
+-	{ PIN_NUMBER('B', 13),   PU0, 18 },	/* AVB_RD1 */
+-	{ PIN_NUMBER('A', 13),   PU0, 17 },	/* AVB_RD0 */
+-	{ PIN_NUMBER('B', 19),   PU0, 16 },	/* AVB_RXC */
+-	{ PIN_NUMBER('A', 16),   PU0, 15 },	/* AVB_RX_CTL */
+-	{ PIN_NUMBER('V', 7),    PU0, 14 },	/* RPC_RESET# */
+-	{ PIN_NUMBER('V', 6),    PU0, 13 },	/* RPC_WP# */
+-	{ PIN_NUMBER('Y', 7),    PU0, 12 },	/* RPC_INT# */
+-	{ PIN_NUMBER('V', 5),    PU0, 11 },	/* QSPI1_SSL */
+-	{ PIN_A_NUMBER('C', 3),  PU0, 10 },	/* QSPI1_IO3 */
+-	{ PIN_A_NUMBER('E', 4),  PU0,  9 },	/* QSPI1_IO2 */
+-	{ PIN_A_NUMBER('E', 5),  PU0,  8 },	/* QSPI1_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 7),  PU0,  7 },	/* QSPI1_MOSI_IO0 */
+-	{ PIN_NUMBER('V', 3),    PU0,  6 },	/* QSPI1_SPCLK */
+-	{ PIN_NUMBER('Y', 3),    PU0,  5 },	/* QSPI0_SSL */
+-	{ PIN_A_NUMBER('B', 6),  PU0,  4 },	/* QSPI0_IO3 */
+-	{ PIN_NUMBER('Y', 6),    PU0,  3 },	/* QSPI0_IO2 */
+-	{ PIN_A_NUMBER('B', 4),  PU0,  2 },	/* QSPI0_MISO_IO1 */
+-	{ PIN_A_NUMBER('C', 5),  PU0,  1 },	/* QSPI0_MOSI_IO0 */
+-	{ PIN_NUMBER('W', 3),    PU0,  0 },	/* QSPI0_SPCLK */
+-
+-	{ RCAR_GP_PIN(1, 19),    PU1, 31 },	/* A19 */
+-	{ RCAR_GP_PIN(1, 18),    PU1, 30 },	/* A18 */
+-	{ RCAR_GP_PIN(1, 17),    PU1, 29 },	/* A17 */
+-	{ RCAR_GP_PIN(1, 16),    PU1, 28 },	/* A16 */
+-	{ RCAR_GP_PIN(1, 15),    PU1, 27 },	/* A15 */
+-	{ RCAR_GP_PIN(1, 14),    PU1, 26 },	/* A14 */
+-	{ RCAR_GP_PIN(1, 13),    PU1, 25 },	/* A13 */
+-	{ RCAR_GP_PIN(1, 12),    PU1, 24 },	/* A12 */
+-	{ RCAR_GP_PIN(1, 11),    PU1, 23 },	/* A11 */
+-	{ RCAR_GP_PIN(1, 10),    PU1, 22 },	/* A10 */
+-	{ RCAR_GP_PIN(1,  9),    PU1, 21 },	/* A9 */
+-	{ RCAR_GP_PIN(1,  8),    PU1, 20 },	/* A8 */
+-	{ RCAR_GP_PIN(1,  7),    PU1, 19 },	/* A7 */
+-	{ RCAR_GP_PIN(1,  6),    PU1, 18 },	/* A6 */
+-	{ RCAR_GP_PIN(1,  5),    PU1, 17 },	/* A5 */
+-	{ RCAR_GP_PIN(1,  4),    PU1, 16 },	/* A4 */
+-	{ RCAR_GP_PIN(1,  3),    PU1, 15 },	/* A3 */
+-	{ RCAR_GP_PIN(1,  2),    PU1, 14 },	/* A2 */
+-	{ RCAR_GP_PIN(1,  1),    PU1, 13 },	/* A1 */
+-	{ RCAR_GP_PIN(1,  0),    PU1, 12 },	/* A0 */
+-	{ RCAR_GP_PIN(2,  8),    PU1, 11 },	/* PWM2_A */
+-	{ RCAR_GP_PIN(2,  7),    PU1, 10 },	/* PWM1_A */
+-	{ RCAR_GP_PIN(2,  6),    PU1,  9 },	/* PWM0 */
+-	{ RCAR_GP_PIN(2,  5),    PU1,  8 },	/* IRQ5 */
+-	{ RCAR_GP_PIN(2,  4),    PU1,  7 },	/* IRQ4 */
+-	{ RCAR_GP_PIN(2,  3),    PU1,  6 },	/* IRQ3 */
+-	{ RCAR_GP_PIN(2,  2),    PU1,  5 },	/* IRQ2 */
+-	{ RCAR_GP_PIN(2,  1),    PU1,  4 },	/* IRQ1 */
+-	{ RCAR_GP_PIN(2,  0),    PU1,  3 },	/* IRQ0 */
+-	{ RCAR_GP_PIN(2, 14),    PU1,  2 },	/* AVB_AVTP_CAPTURE_A */
+-	{ RCAR_GP_PIN(2, 13),    PU1,  1 },	/* AVB_AVTP_MATCH_A */
+-	{ RCAR_GP_PIN(2, 12),    PU1,  0 },	/* AVB_LINK */
+-
+-	{ PIN_A_NUMBER('P', 8),  PU2, 31 },	/* DU_DOTCLKIN1 */
+-	{ PIN_A_NUMBER('P', 7),  PU2, 30 },	/* DU_DOTCLKIN0 */
+-	{ RCAR_GP_PIN(7,  3),    PU2, 29 },	/* GP7_03 */
+-	{ RCAR_GP_PIN(7,  2),    PU2, 28 },	/* HDMI0_CEC */
+-	{ RCAR_GP_PIN(7,  1),    PU2, 27 },	/* AVS2 */
+-	{ RCAR_GP_PIN(7,  0),    PU2, 26 },	/* AVS1 */
+-	{ RCAR_GP_PIN(0, 15),    PU2, 25 },	/* D15 */
+-	{ RCAR_GP_PIN(0, 14),    PU2, 24 },	/* D14 */
+-	{ RCAR_GP_PIN(0, 13),    PU2, 23 },	/* D13 */
+-	{ RCAR_GP_PIN(0, 12),    PU2, 22 },	/* D12 */
+-	{ RCAR_GP_PIN(0, 11),    PU2, 21 },	/* D11 */
+-	{ RCAR_GP_PIN(0, 10),    PU2, 20 },	/* D10 */
+-	{ RCAR_GP_PIN(0,  9),    PU2, 19 },	/* D9 */
+-	{ RCAR_GP_PIN(0,  8),    PU2, 18 },	/* D8 */
+-	{ RCAR_GP_PIN(0,  7),    PU2, 17 },	/* D7 */
+-	{ RCAR_GP_PIN(0,  6),    PU2, 16 },	/* D6 */
+-	{ RCAR_GP_PIN(0,  5),    PU2, 15 },	/* D5 */
+-	{ RCAR_GP_PIN(0,  4),    PU2, 14 },	/* D4 */
+-	{ RCAR_GP_PIN(0,  3),    PU2, 13 },	/* D3 */
+-	{ RCAR_GP_PIN(0,  2),    PU2, 12 },	/* D2 */
+-	{ RCAR_GP_PIN(0,  1),    PU2, 11 },	/* D1 */
+-	{ RCAR_GP_PIN(0,  0),    PU2, 10 },	/* D0 */
+-	{ PIN_NUMBER('C', 1),    PU2,  9 },	/* PRESETOUT# */
+-	{ RCAR_GP_PIN(1, 27),    PU2,  8 },	/* EX_WAIT0_A */
+-	{ RCAR_GP_PIN(1, 26),    PU2,  7 },	/* WE1_N */
+-	{ RCAR_GP_PIN(1, 25),    PU2,  6 },	/* WE0_N */
+-	{ RCAR_GP_PIN(1, 24),    PU2,  5 },	/* RD_WR_N */
+-	{ RCAR_GP_PIN(1, 23),    PU2,  4 },	/* RD_N */
+-	{ RCAR_GP_PIN(1, 22),    PU2,  3 },	/* BS_N */
+-	{ RCAR_GP_PIN(1, 21),    PU2,  2 },	/* CS1_N */
+-	{ RCAR_GP_PIN(1, 20),    PU2,  1 },	/* CS0_N */
+-	{ RCAR_GP_PIN(1, 28),    PU2,  0 },	/* CLKOUT */
+-
+-	{ RCAR_GP_PIN(4,  9),    PU3, 31 },	/* SD3_DAT0 */
+-	{ RCAR_GP_PIN(4,  8),    PU3, 30 },	/* SD3_CMD */
+-	{ RCAR_GP_PIN(4,  7),    PU3, 29 },	/* SD3_CLK */
+-	{ RCAR_GP_PIN(4,  6),    PU3, 28 },	/* SD2_DS */
+-	{ RCAR_GP_PIN(4,  5),    PU3, 27 },	/* SD2_DAT3 */
+-	{ RCAR_GP_PIN(4,  4),    PU3, 26 },	/* SD2_DAT2 */
+-	{ RCAR_GP_PIN(4,  3),    PU3, 25 },	/* SD2_DAT1 */
+-	{ RCAR_GP_PIN(4,  2),    PU3, 24 },	/* SD2_DAT0 */
+-	{ RCAR_GP_PIN(4,  1),    PU3, 23 },	/* SD2_CMD */
+-	{ RCAR_GP_PIN(4,  0),    PU3, 22 },	/* SD2_CLK */
+-	{ RCAR_GP_PIN(3, 11),    PU3, 21 },	/* SD1_DAT3 */
+-	{ RCAR_GP_PIN(3, 10),    PU3, 20 },	/* SD1_DAT2 */
+-	{ RCAR_GP_PIN(3,  9),    PU3, 19 },	/* SD1_DAT1 */
+-	{ RCAR_GP_PIN(3,  8),    PU3, 18 },	/* SD1_DAT0 */
+-	{ RCAR_GP_PIN(3,  7),    PU3, 17 },	/* SD1_CMD */
+-	{ RCAR_GP_PIN(3,  6),    PU3, 16 },	/* SD1_CLK */
+-	{ RCAR_GP_PIN(3,  5),    PU3, 15 },	/* SD0_DAT3 */
+-	{ RCAR_GP_PIN(3,  4),    PU3, 14 },	/* SD0_DAT2 */
+-	{ RCAR_GP_PIN(3,  3),    PU3, 13 },	/* SD0_DAT1 */
+-	{ RCAR_GP_PIN(3,  2),    PU3, 12 },	/* SD0_DAT0 */
+-	{ RCAR_GP_PIN(3,  1),    PU3, 11 },	/* SD0_CMD */
+-	{ RCAR_GP_PIN(3,  0),    PU3, 10 },	/* SD0_CLK */
+-	{ PIN_A_NUMBER('T', 30), PU3,  9 },	/* ASEBRK */
+-	/* bit 8 n/a */
+-	{ PIN_A_NUMBER('R', 29), PU3,  7 },	/* TDI */
+-	{ PIN_A_NUMBER('R', 30), PU3,  6 },	/* TMS */
+-	{ PIN_A_NUMBER('T', 27), PU3,  5 },	/* TCK */
+-	{ PIN_A_NUMBER('R', 26), PU3,  4 },	/* TRST# */
+-	{ PIN_A_NUMBER('D', 39), PU3,  3 },	/* EXTALR*/
+-	{ PIN_A_NUMBER('D', 38), PU3,  2 },	/* FSCLKST */
+-	/* bit 1 n/a on M3*/
+-	{ PIN_A_NUMBER('R', 8),  PU3,  0 },	/* DU_DOTCLKIN2 */
+-
+-	{ RCAR_GP_PIN(5, 19),    PU4, 31 },	/* MSIOF0_SS1 */
+-	{ RCAR_GP_PIN(5, 18),    PU4, 30 },	/* MSIOF0_SYNC */
+-	{ RCAR_GP_PIN(5, 17),    PU4, 29 },	/* MSIOF0_SCK */
+-	{ RCAR_GP_PIN(5, 16),    PU4, 28 },	/* HRTS0_N */
+-	{ RCAR_GP_PIN(5, 15),    PU4, 27 },	/* HCTS0_N */
+-	{ RCAR_GP_PIN(5, 14),    PU4, 26 },	/* HTX0 */
+-	{ RCAR_GP_PIN(5, 13),    PU4, 25 },	/* HRX0 */
+-	{ RCAR_GP_PIN(5, 12),    PU4, 24 },	/* HSCK0 */
+-	{ RCAR_GP_PIN(5, 11),    PU4, 23 },	/* RX2_A */
+-	{ RCAR_GP_PIN(5, 10),    PU4, 22 },	/* TX2_A */
+-	{ RCAR_GP_PIN(5,  9),    PU4, 21 },	/* SCK2 */
+-	{ RCAR_GP_PIN(5,  8),    PU4, 20 },	/* RTS1_N_TANS */
+-	{ RCAR_GP_PIN(5,  7),    PU4, 19 },	/* CTS1_N */
+-	{ RCAR_GP_PIN(5,  6),    PU4, 18 },	/* TX1_A */
+-	{ RCAR_GP_PIN(5,  5),    PU4, 17 },	/* RX1_A */
+-	{ RCAR_GP_PIN(5,  4),    PU4, 16 },	/* RTS0_N_TANS */
+-	{ RCAR_GP_PIN(5,  3),    PU4, 15 },	/* CTS0_N */
+-	{ RCAR_GP_PIN(5,  2),    PU4, 14 },	/* TX0 */
+-	{ RCAR_GP_PIN(5,  1),    PU4, 13 },	/* RX0 */
+-	{ RCAR_GP_PIN(5,  0),    PU4, 12 },	/* SCK0 */
+-	{ RCAR_GP_PIN(3, 15),    PU4, 11 },	/* SD1_WP */
+-	{ RCAR_GP_PIN(3, 14),    PU4, 10 },	/* SD1_CD */
+-	{ RCAR_GP_PIN(3, 13),    PU4,  9 },	/* SD0_WP */
+-	{ RCAR_GP_PIN(3, 12),    PU4,  8 },	/* SD0_CD */
+-	{ RCAR_GP_PIN(4, 17),    PU4,  7 },	/* SD3_DS */
+-	{ RCAR_GP_PIN(4, 16),    PU4,  6 },	/* SD3_DAT7 */
+-	{ RCAR_GP_PIN(4, 15),    PU4,  5 },	/* SD3_DAT6 */
+-	{ RCAR_GP_PIN(4, 14),    PU4,  4 },	/* SD3_DAT5 */
+-	{ RCAR_GP_PIN(4, 13),    PU4,  3 },	/* SD3_DAT4 */
+-	{ RCAR_GP_PIN(4, 12),    PU4,  2 },	/* SD3_DAT3 */
+-	{ RCAR_GP_PIN(4, 11),    PU4,  1 },	/* SD3_DAT2 */
+-	{ RCAR_GP_PIN(4, 10),    PU4,  0 },	/* SD3_DAT1 */
+-
+-	{ RCAR_GP_PIN(6, 24),    PU5, 31 },	/* USB0_PWEN */
+-	{ RCAR_GP_PIN(6, 23),    PU5, 30 },	/* AUDIO_CLKB_B */
+-	{ RCAR_GP_PIN(6, 22),    PU5, 29 },	/* AUDIO_CLKA_A */
+-	{ RCAR_GP_PIN(6, 21),    PU5, 28 },	/* SSI_SDATA9_A */
+-	{ RCAR_GP_PIN(6, 20),    PU5, 27 },	/* SSI_SDATA8 */
+-	{ RCAR_GP_PIN(6, 19),    PU5, 26 },	/* SSI_SDATA7 */
+-	{ RCAR_GP_PIN(6, 18),    PU5, 25 },	/* SSI_WS78 */
+-	{ RCAR_GP_PIN(6, 17),    PU5, 24 },	/* SSI_SCK78 */
+-	{ RCAR_GP_PIN(6, 16),    PU5, 23 },	/* SSI_SDATA6 */
+-	{ RCAR_GP_PIN(6, 15),    PU5, 22 },	/* SSI_WS6 */
+-	{ RCAR_GP_PIN(6, 14),    PU5, 21 },	/* SSI_SCK6 */
+-	{ RCAR_GP_PIN(6, 13),    PU5, 20 },	/* SSI_SDATA5 */
+-	{ RCAR_GP_PIN(6, 12),    PU5, 19 },	/* SSI_WS5 */
+-	{ RCAR_GP_PIN(6, 11),    PU5, 18 },	/* SSI_SCK5 */
+-	{ RCAR_GP_PIN(6, 10),    PU5, 17 },	/* SSI_SDATA4 */
+-	{ RCAR_GP_PIN(6,  9),    PU5, 16 },	/* SSI_WS4 */
+-	{ RCAR_GP_PIN(6,  8),    PU5, 15 },	/* SSI_SCK4 */
+-	{ RCAR_GP_PIN(6,  7),    PU5, 14 },	/* SSI_SDATA3 */
+-	{ RCAR_GP_PIN(6,  6),    PU5, 13 },	/* SSI_WS349 */
+-	{ RCAR_GP_PIN(6,  5),    PU5, 12 },	/* SSI_SCK349 */
+-	{ RCAR_GP_PIN(6,  4),    PU5, 11 },	/* SSI_SDATA2_A */
+-	{ RCAR_GP_PIN(6,  3),    PU5, 10 },	/* SSI_SDATA1_A */
+-	{ RCAR_GP_PIN(6,  2),    PU5,  9 },	/* SSI_SDATA0 */
+-	{ RCAR_GP_PIN(6,  1),    PU5,  8 },	/* SSI_WS01239 */
+-	{ RCAR_GP_PIN(6,  0),    PU5,  7 },	/* SSI_SCK01239 */
+-	{ PIN_NUMBER('H', 37),   PU5,  6 },	/* MLB_REF */
+-	{ RCAR_GP_PIN(5, 25),    PU5,  5 },	/* MLB_DAT */
+-	{ RCAR_GP_PIN(5, 24),    PU5,  4 },	/* MLB_SIG */
+-	{ RCAR_GP_PIN(5, 23),    PU5,  3 },	/* MLB_CLK */
+-	{ RCAR_GP_PIN(5, 22),    PU5,  2 },	/* MSIOF0_RXD */
+-	{ RCAR_GP_PIN(5, 21),    PU5,  1 },	/* MSIOF0_SS2 */
+-	{ RCAR_GP_PIN(5, 20),    PU5,  0 },	/* MSIOF0_TXD */
+-
+-	{ RCAR_GP_PIN(6, 31),    PU6,  6 },	/* GP6_31 */
+-	{ RCAR_GP_PIN(6, 30),    PU6,  5 },	/* GP6_30 */
+-	{ RCAR_GP_PIN(6, 29),    PU6,  4 },	/* USB30_OVC */
+-	{ RCAR_GP_PIN(6, 28),    PU6,  3 },	/* USB30_PWEN */
+-	{ RCAR_GP_PIN(6, 27),    PU6,  2 },	/* USB1_OVC */
+-	{ RCAR_GP_PIN(6, 26),    PU6,  1 },	/* USB1_PWEN */
+-	{ RCAR_GP_PIN(6, 25),    PU6,  0 },	/* USB0_OVC */
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
++		[ 0] = PIN_NUMBER('W', 3),	/* QSPI0_SPCLK */
++		[ 1] = PIN_A_NUMBER('C', 5),	/* QSPI0_MOSI_IO0 */
++		[ 2] = PIN_A_NUMBER('B', 4),	/* QSPI0_MISO_IO1 */
++		[ 3] = PIN_NUMBER('Y', 6),	/* QSPI0_IO2 */
++		[ 4] = PIN_A_NUMBER('B', 6),	/* QSPI0_IO3 */
++		[ 5] = PIN_NUMBER('Y', 3),	/* QSPI0_SSL */
++		[ 6] = PIN_NUMBER('V', 3),	/* QSPI1_SPCLK */
++		[ 7] = PIN_A_NUMBER('C', 7),	/* QSPI1_MOSI_IO0 */
++		[ 8] = PIN_A_NUMBER('E', 5),	/* QSPI1_MISO_IO1 */
++		[ 9] = PIN_A_NUMBER('E', 4),	/* QSPI1_IO2 */
++		[10] = PIN_A_NUMBER('C', 3),	/* QSPI1_IO3 */
++		[11] = PIN_NUMBER('V', 5),	/* QSPI1_SSL */
++		[12] = PIN_NUMBER('Y', 7),	/* RPC_INT# */
++		[13] = PIN_NUMBER('V', 6),	/* RPC_WP# */
++		[14] = PIN_NUMBER('V', 7),	/* RPC_RESET# */
++		[15] = PIN_NUMBER('A', 16),	/* AVB_RX_CTL */
++		[16] = PIN_NUMBER('B', 19),	/* AVB_RXC */
++		[17] = PIN_NUMBER('A', 13),	/* AVB_RD0 */
++		[18] = PIN_NUMBER('B', 13),	/* AVB_RD1 */
++		[19] = PIN_NUMBER('A', 14),	/* AVB_RD2 */
++		[20] = PIN_NUMBER('B', 14),	/* AVB_RD3 */
++		[21] = PIN_NUMBER('A', 8),	/* AVB_TX_CTL */
++		[22] = PIN_NUMBER('A', 19),	/* AVB_TXC */
++		[23] = PIN_NUMBER('A', 18),	/* AVB_TD0 */
++		[24] = PIN_NUMBER('B', 18),	/* AVB_TD1 */
++		[25] = PIN_NUMBER('A', 17),	/* AVB_TD2 */
++		[26] = PIN_NUMBER('B', 17),	/* AVB_TD3 */
++		[27] = PIN_NUMBER('A', 12),	/* AVB_TXCREFCLK */
++		[28] = PIN_NUMBER('A', 9),	/* AVB_MDIO */
++		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
++		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
++		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
++	} },
++	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
++		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
++		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
++		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
++		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
++		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
++		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
++		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
++		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
++		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
++		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
++		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
++		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
++		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
++		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
++		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
++		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
++		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
++		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
++		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
++		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
++		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
++		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
++		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
++		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
++		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
++		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
++		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
++		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
++		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
++		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
++		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
++		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
++		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
++		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
++		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
++		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
++		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
++		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
++		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
++		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
++		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
++		[ 9] = PIN_NUMBER('C', 1),	/* PRESETOUT# */
++		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
++		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
++		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
++		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
++		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
++		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
++		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
++		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
++		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
++		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
++		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
++		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
++		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
++		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
++		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
++		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
++		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
++		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
++		[28] = RCAR_GP_PIN(7,  2),	/* HDMI0_CEC */
++		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
++		[30] = PIN_A_NUMBER('P', 7),	/* DU_DOTCLKIN0 */
++		[31] = PIN_A_NUMBER('P', 8),	/* DU_DOTCLKIN1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
++		[ 0] = PIN_A_NUMBER('R', 8),	/* DU_DOTCLKIN2 */
++		[ 1] = PIN_NONE,
++		[ 2] = PIN_A_NUMBER('D', 38),	/* FSCLKST */
++		[ 3] = PIN_A_NUMBER('D', 39),	/* EXTALR*/
++		[ 4] = PIN_A_NUMBER('R', 26),	/* TRST# */
++		[ 5] = PIN_A_NUMBER('T', 27),	/* TCK */
++		[ 6] = PIN_A_NUMBER('R', 30),	/* TMS */
++		[ 7] = PIN_A_NUMBER('R', 29),	/* TDI */
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_A_NUMBER('T', 30),	/* ASEBRK */
++		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
++		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
++		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
++		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
++		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
++		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
++		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
++		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
++		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
++		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
++		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
++		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
++		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
++		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
++		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
++		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
++		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
++		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
++		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
++		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
++		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
++		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
++		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
++		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
++		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
++		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
++		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
++		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
++		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
++		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
++		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
++		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
++		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
++		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
++		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
++		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
++		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
++		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N_TANS */
++		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
++		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
++		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N_TANS */
++		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
++		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
++		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
++		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
++		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
++		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
++		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
++		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
++		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
++		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
++		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
++		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
++		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
++		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
++		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
++		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
++		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
++		[ 6] = PIN_NUMBER('H', 37),	/* MLB_REF */
++		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
++		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
++		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
++		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
++		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
++		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
++		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
++		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
++		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
++		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
++		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
++		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
++		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
++		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
++		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
++		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
++		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
++		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
++		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
++		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
++		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
++		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
++		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
++		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
++		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
++	} },
++	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
++		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
++		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
++		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
++		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
++		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
++		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
++		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
++		[ 7] = PIN_NONE,
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ /* sentinel */ },
+ };
+ 
+ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
+ 					    unsigned int pin)
+ {
+-	const struct sh_pfc_bias_info *info;
+-	u32 reg;
+-	u32 bit;
++	const struct pinmux_bias_reg *reg;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return PIN_CONFIG_BIAS_DISABLE;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))
++	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ 		return PIN_CONFIG_BIAS_DISABLE;
+-	else if (sh_pfc_read(pfc, PUD + reg) & bit)
++	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_PULL_DOWN;
+@@ -5735,28 +5755,24 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
+ static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 				   unsigned int bias)
+ {
+-	const struct sh_pfc_bias_info *info;
++	const struct pinmux_bias_reg *reg;
+ 	u32 enable, updown;
+-	u32 reg;
+-	u32 bit;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return;
+ 
+-	reg = info->reg;
+-	bit = BIT(info->bit);
+-
+-	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;
++	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+ 	if (bias != PIN_CONFIG_BIAS_DISABLE)
+-		enable |= bit;
++		enable |= BIT(bit);
+ 
+-	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;
++	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+-		updown |= bit;
++		updown |= BIT(bit);
+ 
+-	sh_pfc_write(pfc, PUD + reg, updown);
+-	sh_pfc_write(pfc, PUEN + reg, enable);
++	sh_pfc_write(pfc, reg->pud, updown);
++	sh_pfc_write(pfc, reg->puen, enable);
+ }
+ 
+ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
+@@ -5781,6 +5797,7 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = {
+ 
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
++	.bias_regs = pinmux_bias_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0217-pinctrl-sh-pfc-r8a7778-Use-generic-bias-register-des.patch b/patches/0217-pinctrl-sh-pfc-r8a7778-Use-generic-bias-register-des.patch
new file mode 100644
index 00000000000000..dc5f003c0e157e
--- /dev/null
+++ b/patches/0217-pinctrl-sh-pfc-r8a7778-Use-generic-bias-register-des.patch
@@ -0,0 +1,468 @@
+From 6a6c47f957e8720a093aee0305b64c09be899f85 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 16:57:20 +0200
+Subject: [PATCH 0217/1795] pinctrl: sh-pfc: r8a7778: Use generic bias register
+ description
+
+Move R-Car M1A bias support over to the generic way to describe bias
+registers.
+
+As the new description is more compact, this decreases kernel size by
+ca. 148 bytes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3f8833ad66519cf2e4373bf3153f9937ef691717)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 403 +++++++++++++++------------
+ 1 file changed, 222 insertions(+), 181 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+index c3af9ebee4af..00d61d175249 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+@@ -2912,189 +2912,230 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ 	{ },
+ };
+ 
+-#define PUPR0	0x100
+-#define PUPR1	0x104
+-#define PUPR2	0x108
+-#define PUPR3	0x10c
+-#define PUPR4	0x110
+-#define PUPR5	0x114
+-
+-static const struct sh_pfc_bias_info bias_info[] = {
+-	{ RCAR_GP_PIN(0,  6), PUPR0,  0 },	/* A0 */
+-	{ RCAR_GP_PIN(0,  7), PUPR0,  1 },	/* A1 */
+-	{ RCAR_GP_PIN(0,  8), PUPR0,  2 },	/* A2 */
+-	{ RCAR_GP_PIN(0,  9), PUPR0,  3 },	/* A3 */
+-	{ RCAR_GP_PIN(0, 10), PUPR0,  4 },	/* A4 */
+-	{ RCAR_GP_PIN(0, 11), PUPR0,  5 },	/* A5 */
+-	{ RCAR_GP_PIN(0, 12), PUPR0,  6 },	/* A6 */
+-	{ RCAR_GP_PIN(0, 13), PUPR0,  7 },	/* A7 */
+-	{ RCAR_GP_PIN(0, 14), PUPR0,  8 },	/* A8 */
+-	{ RCAR_GP_PIN(0, 15), PUPR0,  9 },	/* A9 */
+-	{ RCAR_GP_PIN(0, 16), PUPR0, 10 },	/* A10 */
+-	{ RCAR_GP_PIN(0, 17), PUPR0, 11 },	/* A11 */
+-	{ RCAR_GP_PIN(0, 18), PUPR0, 12 },	/* A12 */
+-	{ RCAR_GP_PIN(0, 19), PUPR0, 13 },	/* A13 */
+-	{ RCAR_GP_PIN(0, 20), PUPR0, 14 },	/* A14 */
+-	{ RCAR_GP_PIN(0, 21), PUPR0, 15 },	/* A15 */
+-	{ RCAR_GP_PIN(0, 22), PUPR0, 16 },	/* A16 */
+-	{ RCAR_GP_PIN(0, 23), PUPR0, 17 },	/* A17 */
+-	{ RCAR_GP_PIN(0, 24), PUPR0, 18 },	/* A18 */
+-	{ RCAR_GP_PIN(0, 25), PUPR0, 19 },	/* A19 */
+-	{ RCAR_GP_PIN(0, 26), PUPR0, 20 },	/* A20 */
+-	{ RCAR_GP_PIN(0, 27), PUPR0, 21 },	/* A21 */
+-	{ RCAR_GP_PIN(0, 28), PUPR0, 22 },	/* A22 */
+-	{ RCAR_GP_PIN(0, 29), PUPR0, 23 },	/* A23 */
+-	{ RCAR_GP_PIN(0, 30), PUPR0, 24 },	/* A24 */
+-	{ RCAR_GP_PIN(0, 31), PUPR0, 25 },	/* A25 */
+-	{ RCAR_GP_PIN(1,  3), PUPR0, 26 },	/* /EX_CS0 */
+-	{ RCAR_GP_PIN(1,  4), PUPR0, 27 },	/* /EX_CS1 */
+-	{ RCAR_GP_PIN(1,  5), PUPR0, 28 },	/* /EX_CS2 */
+-	{ RCAR_GP_PIN(1,  6), PUPR0, 29 },	/* /EX_CS3 */
+-	{ RCAR_GP_PIN(1,  7), PUPR0, 30 },	/* /EX_CS4 */
+-	{ RCAR_GP_PIN(1,  8), PUPR0, 31 },	/* /EX_CS5 */
+-
+-	{ RCAR_GP_PIN(0,  0), PUPR1,  0 },	/* /PRESETOUT	*/
+-	{ RCAR_GP_PIN(0,  5), PUPR1,  1 },	/* /BS		*/
+-	{ RCAR_GP_PIN(1,  0), PUPR1,  2 },	/* RD//WR	*/
+-	{ RCAR_GP_PIN(1,  1), PUPR1,  3 },	/* /WE0		*/
+-	{ RCAR_GP_PIN(1,  2), PUPR1,  4 },	/* /WE1		*/
+-	{ RCAR_GP_PIN(1, 11), PUPR1,  5 },	/* EX_WAIT0	*/
+-	{ RCAR_GP_PIN(1,  9), PUPR1,  6 },	/* DREQ0	*/
+-	{ RCAR_GP_PIN(1, 10), PUPR1,  7 },	/* DACK0	*/
+-	{ RCAR_GP_PIN(1, 12), PUPR1,  8 },	/* IRQ0		*/
+-	{ RCAR_GP_PIN(1, 13), PUPR1,  9 },	/* IRQ1		*/
+-
+-	{ RCAR_GP_PIN(1, 22), PUPR2,  0 },	/* DU0_DR0	*/
+-	{ RCAR_GP_PIN(1, 23), PUPR2,  1 },	/* DU0_DR1	*/
+-	{ RCAR_GP_PIN(1, 24), PUPR2,  2 },	/* DU0_DR2	*/
+-	{ RCAR_GP_PIN(1, 25), PUPR2,  3 },	/* DU0_DR3	*/
+-	{ RCAR_GP_PIN(1, 26), PUPR2,  4 },	/* DU0_DR4	*/
+-	{ RCAR_GP_PIN(1, 27), PUPR2,  5 },	/* DU0_DR5	*/
+-	{ RCAR_GP_PIN(1, 28), PUPR2,  6 },	/* DU0_DR6	*/
+-	{ RCAR_GP_PIN(1, 29), PUPR2,  7 },	/* DU0_DR7	*/
+-	{ RCAR_GP_PIN(1, 30), PUPR2,  8 },	/* DU0_DG0	*/
+-	{ RCAR_GP_PIN(1, 31), PUPR2,  9 },	/* DU0_DG1	*/
+-	{ RCAR_GP_PIN(2,  0), PUPR2, 10 },	/* DU0_DG2	*/
+-	{ RCAR_GP_PIN(2,  1), PUPR2, 11 },	/* DU0_DG3	*/
+-	{ RCAR_GP_PIN(2,  2), PUPR2, 12 },	/* DU0_DG4	*/
+-	{ RCAR_GP_PIN(2,  3), PUPR2, 13 },	/* DU0_DG5	*/
+-	{ RCAR_GP_PIN(2,  4), PUPR2, 14 },	/* DU0_DG6	*/
+-	{ RCAR_GP_PIN(2,  5), PUPR2, 15 },	/* DU0_DG7	*/
+-	{ RCAR_GP_PIN(2,  6), PUPR2, 16 },	/* DU0_DB0	*/
+-	{ RCAR_GP_PIN(2,  7), PUPR2, 17 },	/* DU0_DB1	*/
+-	{ RCAR_GP_PIN(2,  8), PUPR2, 18 },	/* DU0_DB2	*/
+-	{ RCAR_GP_PIN(2,  9), PUPR2, 19 },	/* DU0_DB3	*/
+-	{ RCAR_GP_PIN(2, 10), PUPR2, 20 },	/* DU0_DB4	*/
+-	{ RCAR_GP_PIN(2, 11), PUPR2, 21 },	/* DU0_DB5	*/
+-	{ RCAR_GP_PIN(2, 12), PUPR2, 22 },	/* DU0_DB6	*/
+-	{ RCAR_GP_PIN(2, 13), PUPR2, 23 },	/* DU0_DB7	*/
+-	{ RCAR_GP_PIN(2, 14), PUPR2, 24 },	/* DU0_DOTCLKIN	*/
+-	{ RCAR_GP_PIN(2, 15), PUPR2, 25 },	/* DU0_DOTCLKOUT0 */
+-	{ RCAR_GP_PIN(2, 17), PUPR2, 26 },	/* DU0_HSYNC	*/
+-	{ RCAR_GP_PIN(2, 18), PUPR2, 27 },	/* DU0_VSYNC	*/
+-	{ RCAR_GP_PIN(2, 19), PUPR2, 28 },	/* DU0_EXODDF	*/
+-	{ RCAR_GP_PIN(2, 20), PUPR2, 29 },	/* DU0_DISP	*/
+-	{ RCAR_GP_PIN(2, 21), PUPR2, 30 },	/* DU0_CDE	*/
+-	{ RCAR_GP_PIN(2, 16), PUPR2, 31 },	/* DU0_DOTCLKOUT1 */
+-
+-	{ RCAR_GP_PIN(3, 24), PUPR3,  0 },	/* VI0_CLK	*/
+-	{ RCAR_GP_PIN(3, 25), PUPR3,  1 },	/* VI0_CLKENB	*/
+-	{ RCAR_GP_PIN(3, 26), PUPR3,  2 },	/* VI0_FIELD	*/
+-	{ RCAR_GP_PIN(3, 27), PUPR3,  3 },	/* /VI0_HSYNC	*/
+-	{ RCAR_GP_PIN(3, 28), PUPR3,  4 },	/* /VI0_VSYNC	*/
+-	{ RCAR_GP_PIN(3, 29), PUPR3,  5 },	/* VI0_DATA0	*/
+-	{ RCAR_GP_PIN(3, 30), PUPR3,  6 },	/* VI0_DATA1	*/
+-	{ RCAR_GP_PIN(3, 31), PUPR3,  7 },	/* VI0_DATA2	*/
+-	{ RCAR_GP_PIN(4,  0), PUPR3,  8 },	/* VI0_DATA3	*/
+-	{ RCAR_GP_PIN(4,  1), PUPR3,  9 },	/* VI0_DATA4	*/
+-	{ RCAR_GP_PIN(4,  2), PUPR3, 10 },	/* VI0_DATA5	*/
+-	{ RCAR_GP_PIN(4,  3), PUPR3, 11 },	/* VI0_DATA6	*/
+-	{ RCAR_GP_PIN(4,  4), PUPR3, 12 },	/* VI0_DATA7	*/
+-	{ RCAR_GP_PIN(4,  5), PUPR3, 13 },	/* VI0_G2	*/
+-	{ RCAR_GP_PIN(4,  6), PUPR3, 14 },	/* VI0_G3	*/
+-	{ RCAR_GP_PIN(4,  7), PUPR3, 15 },	/* VI0_G4	*/
+-	{ RCAR_GP_PIN(4,  8), PUPR3, 16 },	/* VI0_G5	*/
+-	{ RCAR_GP_PIN(4, 21), PUPR3, 17 },	/* VI1_DATA12	*/
+-	{ RCAR_GP_PIN(4, 22), PUPR3, 18 },	/* VI1_DATA13	*/
+-	{ RCAR_GP_PIN(4, 23), PUPR3, 19 },	/* VI1_DATA14	*/
+-	{ RCAR_GP_PIN(4, 24), PUPR3, 20 },	/* VI1_DATA15	*/
+-	{ RCAR_GP_PIN(4,  9), PUPR3, 21 },	/* ETH_REF_CLK	*/
+-	{ RCAR_GP_PIN(4, 10), PUPR3, 22 },	/* ETH_TXD0	*/
+-	{ RCAR_GP_PIN(4, 11), PUPR3, 23 },	/* ETH_TXD1	*/
+-	{ RCAR_GP_PIN(4, 12), PUPR3, 24 },	/* ETH_CRS_DV	*/
+-	{ RCAR_GP_PIN(4, 13), PUPR3, 25 },	/* ETH_TX_EN	*/
+-	{ RCAR_GP_PIN(4, 14), PUPR3, 26 },	/* ETH_RX_ER	*/
+-	{ RCAR_GP_PIN(4, 15), PUPR3, 27 },	/* ETH_RXD0	*/
+-	{ RCAR_GP_PIN(4, 16), PUPR3, 28 },	/* ETH_RXD1	*/
+-	{ RCAR_GP_PIN(4, 17), PUPR3, 29 },	/* ETH_MDC	*/
+-	{ RCAR_GP_PIN(4, 18), PUPR3, 30 },	/* ETH_MDIO	*/
+-	{ RCAR_GP_PIN(4, 19), PUPR3, 31 },	/* ETH_LINK	*/
+-
+-	{ RCAR_GP_PIN(3,  6), PUPR4,  0 },	/* SSI_SCK012	*/
+-	{ RCAR_GP_PIN(3,  7), PUPR4,  1 },	/* SSI_WS012	*/
+-	{ RCAR_GP_PIN(3, 10), PUPR4,  2 },	/* SSI_SDATA0	*/
+-	{ RCAR_GP_PIN(3,  9), PUPR4,  3 },	/* SSI_SDATA1	*/
+-	{ RCAR_GP_PIN(3,  8), PUPR4,  4 },	/* SSI_SDATA2	*/
+-	{ RCAR_GP_PIN(3,  2), PUPR4,  5 },	/* SSI_SCK34	*/
+-	{ RCAR_GP_PIN(3,  3), PUPR4,  6 },	/* SSI_WS34	*/
+-	{ RCAR_GP_PIN(3,  5), PUPR4,  7 },	/* SSI_SDATA3	*/
+-	{ RCAR_GP_PIN(3,  4), PUPR4,  8 },	/* SSI_SDATA4	*/
+-	{ RCAR_GP_PIN(2, 31), PUPR4,  9 },	/* SSI_SCK5	*/
+-	{ RCAR_GP_PIN(3,  0), PUPR4, 10 },	/* SSI_WS5	*/
+-	{ RCAR_GP_PIN(3,  1), PUPR4, 11 },	/* SSI_SDATA5	*/
+-	{ RCAR_GP_PIN(2, 28), PUPR4, 12 },	/* SSI_SCK6	*/
+-	{ RCAR_GP_PIN(2, 29), PUPR4, 13 },	/* SSI_WS6	*/
+-	{ RCAR_GP_PIN(2, 30), PUPR4, 14 },	/* SSI_SDATA6	*/
+-	{ RCAR_GP_PIN(2, 24), PUPR4, 15 },	/* SSI_SCK78	*/
+-	{ RCAR_GP_PIN(2, 25), PUPR4, 16 },	/* SSI_WS78	*/
+-	{ RCAR_GP_PIN(2, 27), PUPR4, 17 },	/* SSI_SDATA7	*/
+-	{ RCAR_GP_PIN(2, 26), PUPR4, 18 },	/* SSI_SDATA8	*/
+-	{ RCAR_GP_PIN(3, 23), PUPR4, 19 },	/* TCLK0	*/
+-	{ RCAR_GP_PIN(3, 11), PUPR4, 20 },	/* SD0_CLK	*/
+-	{ RCAR_GP_PIN(3, 12), PUPR4, 21 },	/* SD0_CMD	*/
+-	{ RCAR_GP_PIN(3, 13), PUPR4, 22 },	/* SD0_DAT0	*/
+-	{ RCAR_GP_PIN(3, 14), PUPR4, 23 },	/* SD0_DAT1	*/
+-	{ RCAR_GP_PIN(3, 15), PUPR4, 24 },	/* SD0_DAT2	*/
+-	{ RCAR_GP_PIN(3, 16), PUPR4, 25 },	/* SD0_DAT3	*/
+-	{ RCAR_GP_PIN(3, 17), PUPR4, 26 },	/* SD0_CD	*/
+-	{ RCAR_GP_PIN(3, 18), PUPR4, 27 },	/* SD0_WP	*/
+-	{ RCAR_GP_PIN(2, 22), PUPR4, 28 },	/* AUDIO_CLKA	*/
+-	{ RCAR_GP_PIN(2, 23), PUPR4, 29 },	/* AUDIO_CLKB	*/
+-	{ RCAR_GP_PIN(1, 14), PUPR4, 30 },	/* IRQ2		*/
+-	{ RCAR_GP_PIN(1, 15), PUPR4, 31 },	/* IRQ3		*/
+-
+-	{ RCAR_GP_PIN(0,  1), PUPR5,  0 },	/* PENC0	*/
+-	{ RCAR_GP_PIN(0,  2), PUPR5,  1 },	/* PENC1	*/
+-	{ RCAR_GP_PIN(0,  3), PUPR5,  2 },	/* USB_OVC0	*/
+-	{ RCAR_GP_PIN(0,  4), PUPR5,  3 },	/* USB_OVC1	*/
+-	{ RCAR_GP_PIN(1, 16), PUPR5,  4 },	/* SCIF_CLK	*/
+-	{ RCAR_GP_PIN(1, 17), PUPR5,  5 },	/* TX0		*/
+-	{ RCAR_GP_PIN(1, 18), PUPR5,  6 },	/* RX0		*/
+-	{ RCAR_GP_PIN(1, 19), PUPR5,  7 },	/* SCK0		*/
+-	{ RCAR_GP_PIN(1, 20), PUPR5,  8 },	/* /CTS0	*/
+-	{ RCAR_GP_PIN(1, 21), PUPR5,  9 },	/* /RTS0	*/
+-	{ RCAR_GP_PIN(3, 19), PUPR5, 10 },	/* HSPI_CLK0	*/
+-	{ RCAR_GP_PIN(3, 20), PUPR5, 11 },	/* /HSPI_CS0	*/
+-	{ RCAR_GP_PIN(3, 21), PUPR5, 12 },	/* HSPI_RX0	*/
+-	{ RCAR_GP_PIN(3, 22), PUPR5, 13 },	/* HSPI_TX0	*/
+-	{ RCAR_GP_PIN(4, 20), PUPR5, 14 },	/* ETH_MAGIC	*/
+-	{ RCAR_GP_PIN(4, 25), PUPR5, 15 },	/* AVS1		*/
+-	{ RCAR_GP_PIN(4, 26), PUPR5, 16 },	/* AVS2		*/
++#define PIN_NONE	U16_MAX
++
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(0,  6),	/* A0 */
++		[ 1] = RCAR_GP_PIN(0,  7),	/* A1 */
++		[ 2] = RCAR_GP_PIN(0,  8),	/* A2 */
++		[ 3] = RCAR_GP_PIN(0,  9),	/* A3 */
++		[ 4] = RCAR_GP_PIN(0, 10),	/* A4 */
++		[ 5] = RCAR_GP_PIN(0, 11),	/* A5 */
++		[ 6] = RCAR_GP_PIN(0, 12),	/* A6 */
++		[ 7] = RCAR_GP_PIN(0, 13),	/* A7 */
++		[ 8] = RCAR_GP_PIN(0, 14),	/* A8 */
++		[ 9] = RCAR_GP_PIN(0, 15),	/* A9 */
++		[10] = RCAR_GP_PIN(0, 16),	/* A10 */
++		[11] = RCAR_GP_PIN(0, 17),	/* A11 */
++		[12] = RCAR_GP_PIN(0, 18),	/* A12 */
++		[13] = RCAR_GP_PIN(0, 19),	/* A13 */
++		[14] = RCAR_GP_PIN(0, 20),	/* A14 */
++		[15] = RCAR_GP_PIN(0, 21),	/* A15 */
++		[16] = RCAR_GP_PIN(0, 22),	/* A16 */
++		[17] = RCAR_GP_PIN(0, 23),	/* A17 */
++		[18] = RCAR_GP_PIN(0, 24),	/* A18 */
++		[19] = RCAR_GP_PIN(0, 25),	/* A19 */
++		[20] = RCAR_GP_PIN(0, 26),	/* A20 */
++		[21] = RCAR_GP_PIN(0, 27),	/* A21 */
++		[22] = RCAR_GP_PIN(0, 28),	/* A22 */
++		[23] = RCAR_GP_PIN(0, 29),	/* A23 */
++		[24] = RCAR_GP_PIN(0, 30),	/* A24 */
++		[25] = RCAR_GP_PIN(0, 31),	/* A25 */
++		[26] = RCAR_GP_PIN(1,  3),	/* /EX_CS0 */
++		[27] = RCAR_GP_PIN(1,  4),	/* /EX_CS1 */
++		[28] = RCAR_GP_PIN(1,  5),	/* /EX_CS2 */
++		[29] = RCAR_GP_PIN(1,  6),	/* /EX_CS3 */
++		[30] = RCAR_GP_PIN(1,  7),	/* /EX_CS4 */
++		[31] = RCAR_GP_PIN(1,  8),	/* /EX_CS5 */
++	} },
++	{ PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(0,  0),	/* /PRESETOUT	*/
++		[ 1] = RCAR_GP_PIN(0,  5),	/* /BS		*/
++		[ 2] = RCAR_GP_PIN(1,  0),	/* RD//WR	*/
++		[ 3] = RCAR_GP_PIN(1,  1),	/* /WE0		*/
++		[ 4] = RCAR_GP_PIN(1,  2),	/* /WE1		*/
++		[ 5] = RCAR_GP_PIN(1, 11),	/* EX_WAIT0	*/
++		[ 6] = RCAR_GP_PIN(1,  9),	/* DREQ0	*/
++		[ 7] = RCAR_GP_PIN(1, 10),	/* DACK0	*/
++		[ 8] = RCAR_GP_PIN(1, 12),	/* IRQ0		*/
++		[ 9] = RCAR_GP_PIN(1, 13),	/* IRQ1		*/
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(1, 22),	/* DU0_DR0	*/
++		[ 1] = RCAR_GP_PIN(1, 23),	/* DU0_DR1	*/
++		[ 2] = RCAR_GP_PIN(1, 24),	/* DU0_DR2	*/
++		[ 3] = RCAR_GP_PIN(1, 25),	/* DU0_DR3	*/
++		[ 4] = RCAR_GP_PIN(1, 26),	/* DU0_DR4	*/
++		[ 5] = RCAR_GP_PIN(1, 27),	/* DU0_DR5	*/
++		[ 6] = RCAR_GP_PIN(1, 28),	/* DU0_DR6	*/
++		[ 7] = RCAR_GP_PIN(1, 29),	/* DU0_DR7	*/
++		[ 8] = RCAR_GP_PIN(1, 30),	/* DU0_DG0	*/
++		[ 9] = RCAR_GP_PIN(1, 31),	/* DU0_DG1	*/
++		[10] = RCAR_GP_PIN(2,  0),	/* DU0_DG2	*/
++		[11] = RCAR_GP_PIN(2,  1),	/* DU0_DG3	*/
++		[12] = RCAR_GP_PIN(2,  2),	/* DU0_DG4	*/
++		[13] = RCAR_GP_PIN(2,  3),	/* DU0_DG5	*/
++		[14] = RCAR_GP_PIN(2,  4),	/* DU0_DG6	*/
++		[15] = RCAR_GP_PIN(2,  5),	/* DU0_DG7	*/
++		[16] = RCAR_GP_PIN(2,  6),	/* DU0_DB0	*/
++		[17] = RCAR_GP_PIN(2,  7),	/* DU0_DB1	*/
++		[18] = RCAR_GP_PIN(2,  8),	/* DU0_DB2	*/
++		[19] = RCAR_GP_PIN(2,  9),	/* DU0_DB3	*/
++		[20] = RCAR_GP_PIN(2, 10),	/* DU0_DB4	*/
++		[21] = RCAR_GP_PIN(2, 11),	/* DU0_DB5	*/
++		[22] = RCAR_GP_PIN(2, 12),	/* DU0_DB6	*/
++		[23] = RCAR_GP_PIN(2, 13),	/* DU0_DB7	*/
++		[24] = RCAR_GP_PIN(2, 14),	/* DU0_DOTCLKIN	*/
++		[25] = RCAR_GP_PIN(2, 15),	/* DU0_DOTCLKOUT0 */
++		[26] = RCAR_GP_PIN(2, 17),	/* DU0_HSYNC	*/
++		[27] = RCAR_GP_PIN(2, 18),	/* DU0_VSYNC	*/
++		[28] = RCAR_GP_PIN(2, 19),	/* DU0_EXODDF	*/
++		[29] = RCAR_GP_PIN(2, 20),	/* DU0_DISP	*/
++		[30] = RCAR_GP_PIN(2, 21),	/* DU0_CDE	*/
++		[31] = RCAR_GP_PIN(2, 16),	/* DU0_DOTCLKOUT1 */
++	} },
++	{ PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(3, 24),	/* VI0_CLK	*/
++		[ 1] = RCAR_GP_PIN(3, 25),	/* VI0_CLKENB	*/
++		[ 2] = RCAR_GP_PIN(3, 26),	/* VI0_FIELD	*/
++		[ 3] = RCAR_GP_PIN(3, 27),	/* /VI0_HSYNC	*/
++		[ 4] = RCAR_GP_PIN(3, 28),	/* /VI0_VSYNC	*/
++		[ 5] = RCAR_GP_PIN(3, 29),	/* VI0_DATA0	*/
++		[ 6] = RCAR_GP_PIN(3, 30),	/* VI0_DATA1	*/
++		[ 7] = RCAR_GP_PIN(3, 31),	/* VI0_DATA2	*/
++		[ 8] = RCAR_GP_PIN(4,  0),	/* VI0_DATA3	*/
++		[ 9] = RCAR_GP_PIN(4,  1),	/* VI0_DATA4	*/
++		[10] = RCAR_GP_PIN(4,  2),	/* VI0_DATA5	*/
++		[11] = RCAR_GP_PIN(4,  3),	/* VI0_DATA6	*/
++		[12] = RCAR_GP_PIN(4,  4),	/* VI0_DATA7	*/
++		[13] = RCAR_GP_PIN(4,  5),	/* VI0_G2	*/
++		[14] = RCAR_GP_PIN(4,  6),	/* VI0_G3	*/
++		[15] = RCAR_GP_PIN(4,  7),	/* VI0_G4	*/
++		[16] = RCAR_GP_PIN(4,  8),	/* VI0_G5	*/
++		[17] = RCAR_GP_PIN(4, 21),	/* VI1_DATA12	*/
++		[18] = RCAR_GP_PIN(4, 22),	/* VI1_DATA13	*/
++		[19] = RCAR_GP_PIN(4, 23),	/* VI1_DATA14	*/
++		[20] = RCAR_GP_PIN(4, 24),	/* VI1_DATA15	*/
++		[21] = RCAR_GP_PIN(4,  9),	/* ETH_REF_CLK	*/
++		[22] = RCAR_GP_PIN(4, 10),	/* ETH_TXD0	*/
++		[23] = RCAR_GP_PIN(4, 11),	/* ETH_TXD1	*/
++		[24] = RCAR_GP_PIN(4, 12),	/* ETH_CRS_DV	*/
++		[25] = RCAR_GP_PIN(4, 13),	/* ETH_TX_EN	*/
++		[26] = RCAR_GP_PIN(4, 14),	/* ETH_RX_ER	*/
++		[27] = RCAR_GP_PIN(4, 15),	/* ETH_RXD0	*/
++		[28] = RCAR_GP_PIN(4, 16),	/* ETH_RXD1	*/
++		[29] = RCAR_GP_PIN(4, 17),	/* ETH_MDC	*/
++		[30] = RCAR_GP_PIN(4, 18),	/* ETH_MDIO	*/
++		[31] = RCAR_GP_PIN(4, 19),	/* ETH_LINK	*/
++	} },
++	{ PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(3,  6),	/* SSI_SCK012	*/
++		[ 1] = RCAR_GP_PIN(3,  7),	/* SSI_WS012	*/
++		[ 2] = RCAR_GP_PIN(3, 10),	/* SSI_SDATA0	*/
++		[ 3] = RCAR_GP_PIN(3,  9),	/* SSI_SDATA1	*/
++		[ 4] = RCAR_GP_PIN(3,  8),	/* SSI_SDATA2	*/
++		[ 5] = RCAR_GP_PIN(3,  2),	/* SSI_SCK34	*/
++		[ 6] = RCAR_GP_PIN(3,  3),	/* SSI_WS34	*/
++		[ 7] = RCAR_GP_PIN(3,  5),	/* SSI_SDATA3	*/
++		[ 8] = RCAR_GP_PIN(3,  4),	/* SSI_SDATA4	*/
++		[ 9] = RCAR_GP_PIN(2, 31),	/* SSI_SCK5	*/
++		[10] = RCAR_GP_PIN(3,  0),	/* SSI_WS5	*/
++		[11] = RCAR_GP_PIN(3,  1),	/* SSI_SDATA5	*/
++		[12] = RCAR_GP_PIN(2, 28),	/* SSI_SCK6	*/
++		[13] = RCAR_GP_PIN(2, 29),	/* SSI_WS6	*/
++		[14] = RCAR_GP_PIN(2, 30),	/* SSI_SDATA6	*/
++		[15] = RCAR_GP_PIN(2, 24),	/* SSI_SCK78	*/
++		[16] = RCAR_GP_PIN(2, 25),	/* SSI_WS78	*/
++		[17] = RCAR_GP_PIN(2, 27),	/* SSI_SDATA7	*/
++		[18] = RCAR_GP_PIN(2, 26),	/* SSI_SDATA8	*/
++		[19] = RCAR_GP_PIN(3, 23),	/* TCLK0	*/
++		[20] = RCAR_GP_PIN(3, 11),	/* SD0_CLK	*/
++		[21] = RCAR_GP_PIN(3, 12),	/* SD0_CMD	*/
++		[22] = RCAR_GP_PIN(3, 13),	/* SD0_DAT0	*/
++		[23] = RCAR_GP_PIN(3, 14),	/* SD0_DAT1	*/
++		[24] = RCAR_GP_PIN(3, 15),	/* SD0_DAT2	*/
++		[25] = RCAR_GP_PIN(3, 16),	/* SD0_DAT3	*/
++		[26] = RCAR_GP_PIN(3, 17),	/* SD0_CD	*/
++		[27] = RCAR_GP_PIN(3, 18),	/* SD0_WP	*/
++		[28] = RCAR_GP_PIN(2, 22),	/* AUDIO_CLKA	*/
++		[29] = RCAR_GP_PIN(2, 23),	/* AUDIO_CLKB	*/
++		[30] = RCAR_GP_PIN(1, 14),	/* IRQ2		*/
++		[31] = RCAR_GP_PIN(1, 15),	/* IRQ3		*/
++	} },
++	{ PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
++		[ 0] = RCAR_GP_PIN(0,  1),	/* PENC0	*/
++		[ 1] = RCAR_GP_PIN(0,  2),	/* PENC1	*/
++		[ 2] = RCAR_GP_PIN(0,  3),	/* USB_OVC0	*/
++		[ 3] = RCAR_GP_PIN(0,  4),	/* USB_OVC1	*/
++		[ 4] = RCAR_GP_PIN(1, 16),	/* SCIF_CLK	*/
++		[ 5] = RCAR_GP_PIN(1, 17),	/* TX0		*/
++		[ 6] = RCAR_GP_PIN(1, 18),	/* RX0		*/
++		[ 7] = RCAR_GP_PIN(1, 19),	/* SCK0		*/
++		[ 8] = RCAR_GP_PIN(1, 20),	/* /CTS0	*/
++		[ 9] = RCAR_GP_PIN(1, 21),	/* /RTS0	*/
++		[10] = RCAR_GP_PIN(3, 19),	/* HSPI_CLK0	*/
++		[11] = RCAR_GP_PIN(3, 20),	/* /HSPI_CS0	*/
++		[12] = RCAR_GP_PIN(3, 21),	/* HSPI_RX0	*/
++		[13] = RCAR_GP_PIN(3, 22),	/* HSPI_TX0	*/
++		[14] = RCAR_GP_PIN(4, 20),	/* ETH_MAGIC	*/
++		[15] = RCAR_GP_PIN(4, 25),	/* AVS1		*/
++		[16] = RCAR_GP_PIN(4, 26),	/* AVS2		*/
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ /* sentinel */ },
+ };
+ 
+ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
+ 					    unsigned int pin)
+ {
+-	const struct sh_pfc_bias_info *info;
++	const struct pinmux_bias_reg *reg;
+ 	void __iomem *addr;
++	unsigned int bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return PIN_CONFIG_BIAS_DISABLE;
+ 
+-	addr = pfc->windows->virt + info->reg;
++	addr = pfc->windows->virt + reg->puen;
+ 
+-	if (ioread32(addr) & BIT(info->bit))
++	if (ioread32(addr) & BIT(bit))
+ 		return PIN_CONFIG_BIAS_PULL_UP;
+ 	else
+ 		return PIN_CONFIG_BIAS_DISABLE;
+@@ -3103,21 +3144,20 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
+ static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ 				   unsigned int bias)
+ {
+-	const struct sh_pfc_bias_info *info;
++	const struct pinmux_bias_reg *reg;
+ 	void __iomem *addr;
++	unsigned int bit;
+ 	u32 value;
+-	u32 bit;
+ 
+-	info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
+-	if (!info)
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
+ 		return;
+ 
+-	addr = pfc->windows->virt + info->reg;
+-	bit = BIT(info->bit);
++	addr = pfc->windows->virt + reg->puen;
+ 
+-	value = ioread32(addr) & ~bit;
++	value = ioread32(addr) & ~BIT(bit);
+ 	if (bias == PIN_CONFIG_BIAS_PULL_UP)
+-		value |= bit;
++		value |= BIT(bit);
+ 	iowrite32(value, addr);
+ }
+ 
+@@ -3144,6 +3184,7 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+ 	.nr_functions = ARRAY_SIZE(pinmux_functions),
+ 
+ 	.cfg_regs = pinmux_config_regs,
++	.bias_regs = pinmux_bias_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0218-pinctrl-sh-pfc-Remove-obsolete-sh_pfc_pin_to_bias_in.patch b/patches/0218-pinctrl-sh-pfc-Remove-obsolete-sh_pfc_pin_to_bias_in.patch
new file mode 100644
index 00000000000000..a087304c0b3622
--- /dev/null
+++ b/patches/0218-pinctrl-sh-pfc-Remove-obsolete-sh_pfc_pin_to_bias_in.patch
@@ -0,0 +1,81 @@
+From a6ad0cae8dff4147623ffea53e769b7de76305e2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 17:12:39 +0200
+Subject: [PATCH 0218/1795] pinctrl: sh-pfc: Remove obsolete
+ sh_pfc_pin_to_bias_info()
+
+All users of sh_pfc_pin_to_bias_info() and the related data structures
+have been converted to sh_pfc_pin_to_bias_reg(), so those can be
+removed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit 1860bb134fc29dee0aeb912ae20799119b920df9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/core.c   | 15 ---------------
+ drivers/pinctrl/sh-pfc/core.h   |  3 ---
+ drivers/pinctrl/sh-pfc/sh_pfc.h |  6 ------
+ 3 files changed, 24 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 01c408a3dee4..2fe5fd6c5d17 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -389,21 +389,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
+ 	return 0;
+ }
+ 
+-const struct sh_pfc_bias_info *
+-sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
+-			unsigned int num, unsigned int pin)
+-{
+-	unsigned int i;
+-
+-	for (i = 0; i < num; i++)
+-		if (info[i].pin == pin)
+-			return &info[i];
+-
+-	WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
+-
+-	return NULL;
+-}
+-
+ const struct pinmux_bias_reg *
+ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
+ 		       unsigned int *bit)
+diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
+index 460d996513ac..5af8ee26c03e 100644
+--- a/drivers/pinctrl/sh-pfc/core.h
++++ b/drivers/pinctrl/sh-pfc/core.h
+@@ -32,9 +32,6 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
+ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
+ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
+ 
+-const struct sh_pfc_bias_info *
+-sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
+-			unsigned int num, unsigned int pin);
+ const struct pinmux_bias_reg *
+ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
+ 		       unsigned int *bit);
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 1914f4b5fef5..18fd87826629 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -200,12 +200,6 @@ struct sh_pfc_window {
+ 	unsigned long size;
+ };
+ 
+-struct sh_pfc_bias_info {
+-	u16 pin;
+-	u16 reg : 11;
+-	u16 bit : 5;
+-};
+-
+ struct sh_pfc_pin_range;
+ 
+ struct sh_pfc {
+-- 
+2.19.0
+
diff --git a/patches/0219-pinctrl-sh-pfc-Add-generic-IOCTRL-register-descripti.patch b/patches/0219-pinctrl-sh-pfc-Add-generic-IOCTRL-register-descripti.patch
new file mode 100644
index 00000000000000..4dbda131c34a3c
--- /dev/null
+++ b/patches/0219-pinctrl-sh-pfc-Add-generic-IOCTRL-register-descripti.patch
@@ -0,0 +1,47 @@
+From 2a2278d75807c8374cb358073e0fc503d2a0d8d9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:16:31 +0200
+Subject: [PATCH 0219/1795] pinctrl: sh-pfc: Add generic IOCTRL register
+ description
+
+Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage
+and time delay control), like is already done for config, drive, and
+bias registers.
+
+This makes the sh-pfc core code aware of these registers, which will
+ease introducing suspend/resume support later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9e9bd06a353786ac3c01e76606e64aa660243aab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 18fd87826629..b9bb56c91b6f 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -159,6 +159,10 @@ struct pinmux_bias_reg {
+ 	.pud = r2,	\
+ 	.pins =
+ 
++struct pinmux_ioctrl_reg {
++	u32 reg;
++};
++
+ struct pinmux_data_reg {
+ 	u32 reg;
+ 	u8 reg_width;
+@@ -251,6 +255,7 @@ struct sh_pfc_soc_info {
+ 	const struct pinmux_cfg_reg *cfg_regs;
+ 	const struct pinmux_drive_reg *drive_regs;
+ 	const struct pinmux_bias_reg *bias_regs;
++	const struct pinmux_ioctrl_reg *ioctrl_regs;
+ 	const struct pinmux_data_reg *data_regs;
+ 
+ 	const u16 *pinmux_data;
+-- 
+2.19.0
+
diff --git a/patches/0220-pinctrl-sh-pfc-r8a7795-es1-Use-generic-IOCTRL-regist.patch b/patches/0220-pinctrl-sh-pfc-r8a7795-es1-Use-generic-IOCTRL-regist.patch
new file mode 100644
index 00000000000000..dd742db04894f4
--- /dev/null
+++ b/patches/0220-pinctrl-sh-pfc-r8a7795-es1-Use-generic-IOCTRL-regist.patch
@@ -0,0 +1,56 @@
+From af0a61ea63d6523aec3578b626d9c83d846761f6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:14:56 +0200
+Subject: [PATCH 0220/1795] pinctrl: sh-pfc: r8a7795-es1: Use generic IOCTRL
+ register description
+
+Move R-Car H3 ES1.x I/O voltage support over to the generic way to
+describe IOCTRL registers, which will be needed for suspend/resume
+support.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5d9d1d1ae512600bd1d050cc0a55235435fc3050)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 8042c9331a51..292e35d4d2f4 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -5423,12 +5423,21 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 	{ },
+ };
+ 
++enum ioctrl_regs {
++	POCCTRL,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[POCCTRL] = { 0xe6060380, },
++	{ /* sentinel */ },
++};
++
+ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ 				     u32 *pocctrl)
+ {
+ 	int bit = -EINVAL;
+ 
+-	*pocctrl = 0xe6060380;
++	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
+ 
+ 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ 		bit = pin & 0x1f;
+@@ -5745,6 +5754,7 @@ const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
+ 	.bias_regs = pinmux_bias_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0221-pinctrl-sh-pfc-r8a7795-Use-generic-IOCTRL-register-d.patch b/patches/0221-pinctrl-sh-pfc-r8a7795-Use-generic-IOCTRL-register-d.patch
new file mode 100644
index 00000000000000..b9282f5854a2cd
--- /dev/null
+++ b/patches/0221-pinctrl-sh-pfc-r8a7795-Use-generic-IOCTRL-register-d.patch
@@ -0,0 +1,55 @@
+From 023f553357c868d539615823f404d21afc97df53 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:15:06 +0200
+Subject: [PATCH 0221/1795] pinctrl: sh-pfc: r8a7795: Use generic IOCTRL
+ register description
+
+Move R-Car H3 ES2.0 I/O voltage support over to the generic way to
+describe IOCTRL registers, which will be needed for suspend/resume
+support.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit e2aad8464c0bf183be64c2120a37e87790dba367)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 0a16dea0dace..d1cec6d12e81 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -5413,11 +5413,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 	{ },
+ };
+ 
++enum ioctrl_regs {
++	POCCTRL,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[POCCTRL] = { 0xe6060380, },
++	{ /* sentinel */ },
++};
++
+ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+ {
+ 	int bit = -EINVAL;
+ 
+-	*pocctrl = 0xe6060380;
++	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
+ 
+ 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ 		bit = pin & 0x1f;
+@@ -5748,6 +5757,7 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = {
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
+ 	.bias_regs = pinmux_bias_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0222-pinctrl-sh-pfc-r8a7796-Use-generic-IOCTRL-register-d.patch b/patches/0222-pinctrl-sh-pfc-r8a7796-Use-generic-IOCTRL-register-d.patch
new file mode 100644
index 00000000000000..8f1b26d53365ee
--- /dev/null
+++ b/patches/0222-pinctrl-sh-pfc-r8a7796-Use-generic-IOCTRL-register-d.patch
@@ -0,0 +1,54 @@
+From 37f4d24cd799739ea0b859214a0a96d3c1b7e69d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:15:17 +0200
+Subject: [PATCH 0222/1795] pinctrl: sh-pfc: r8a7796: Use generic IOCTRL
+ register description
+
+Move R-Car M3-W I/O voltage support over to the generic way to describe
+IOCTRL registers, which will be needed for suspend/resume support.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3870a6f6ac255340767de64e71fbbfc54eb39403)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index ebf38ea8abbe..d8dc984cde6d 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -5477,11 +5477,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 	{ },
+ };
+ 
++enum ioctrl_regs {
++	POCCTRL,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[POCCTRL] = { 0xe6060380, },
++	{ /* sentinel */ },
++};
++
+ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+ {
+ 	int bit = -EINVAL;
+ 
+-	*pocctrl = 0xe6060380;
++	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
+ 
+ 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ 		bit = pin & 0x1f;
+@@ -5798,6 +5807,7 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = {
+ 	.cfg_regs = pinmux_config_regs,
+ 	.drive_regs = pinmux_drive_regs,
+ 	.bias_regs = pinmux_bias_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/0223-pinctrl-sh-pfc-Save-restore-registers-for-PSCI-syste.patch b/patches/0223-pinctrl-sh-pfc-Save-restore-registers-for-PSCI-syste.patch
new file mode 100644
index 00000000000000..f8a23f7508e887
--- /dev/null
+++ b/patches/0223-pinctrl-sh-pfc-Save-restore-registers-for-PSCI-syste.patch
@@ -0,0 +1,174 @@
+From f25ccbb1aaa5adbb6bdc7b60d439b140822134b1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 29 Sep 2017 14:17:18 +0200
+Subject: [PATCH 0223/1795] pinctrl: sh-pfc: Save/restore registers for PSCI
+ system suspend
+
+During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
+pinctrl register state is lost.  Note that as the boot loader skips most
+initialization after system resume, pinctrl register state differs from
+the state encountered during normal system boot, too.
+
+To fix this, save all GPIO and peripheral function select, module
+select, drive strength control, bias, and other I/O control registers
+during system suspend, and restore them during system resume.
+
+Note that to avoid overhead on platforms not needing it, the
+suspend/resume code has a build time dependency on sleep and PSCI
+support, and a runtime dependency on PSCI.
+
+Inspired by a patch in the BSP by Hien Dang.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8843797df383ac7ed7cf4f87cc18a4ec6d929b60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/core.c   | 97 +++++++++++++++++++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h |  1 +
+ 2 files changed, 98 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 2fe5fd6c5d17..cf4ae4bc9115 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -24,6 +24,7 @@
+ #include <linux/of_device.h>
+ #include <linux/pinctrl/machine.h>
+ #include <linux/platform_device.h>
++#include <linux/psci.h>
+ #include <linux/slab.h>
+ 
+ #include "core.h"
+@@ -572,6 +573,97 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ };
+ #endif
+ 
++#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
++static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
++{
++}
++
++static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
++{
++	pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
++}
++
++static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
++{
++	sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
++}
++
++static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
++	void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
++{
++	unsigned int i, n = 0;
++
++	if (pfc->info->cfg_regs)
++		for (i = 0; pfc->info->cfg_regs[i].reg; i++)
++			do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
++
++	if (pfc->info->drive_regs)
++		for (i = 0; pfc->info->drive_regs[i].reg; i++)
++			do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
++
++	if (pfc->info->bias_regs)
++		for (i = 0; pfc->info->bias_regs[i].puen; i++) {
++			do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
++			if (pfc->info->bias_regs[i].pud)
++				do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
++		}
++
++	if (pfc->info->ioctrl_regs)
++		for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
++			do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
++
++	return n;
++}
++
++static int sh_pfc_suspend_init(struct sh_pfc *pfc)
++{
++	unsigned int n;
++
++	/* This is the best we can do to check for the presence of PSCI */
++	if (!psci_ops.cpu_suspend)
++		return 0;
++
++	n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
++	if (!n)
++		return 0;
++
++	pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
++					     sizeof(*pfc->saved_regs),
++					     GFP_KERNEL);
++	if (!pfc->saved_regs)
++		return -ENOMEM;
++
++	dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
++	return 0;
++}
++
++static int sh_pfc_suspend_noirq(struct device *dev)
++{
++	struct sh_pfc *pfc = dev_get_drvdata(dev);
++
++	if (pfc->saved_regs)
++		sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
++	return 0;
++}
++
++static int sh_pfc_resume_noirq(struct device *dev)
++{
++	struct sh_pfc *pfc = dev_get_drvdata(dev);
++
++	if (pfc->saved_regs)
++		sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
++	return 0;
++}
++
++static const struct dev_pm_ops sh_pfc_pm  = {
++	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
++};
++#define DEV_PM_OPS	&sh_pfc_pm
++#else
++static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
++#define DEV_PM_OPS	NULL
++#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
++
+ static int sh_pfc_probe(struct platform_device *pdev)
+ {
+ #ifdef CONFIG_OF
+@@ -610,6 +702,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
+ 		info = pfc->info;
+ 	}
+ 
++	ret = sh_pfc_suspend_init(pfc);
++	if (ret)
++		return ret;
++
+ 	/* Enable dummy states for those platforms without pinctrl support */
+ 	if (!of_have_populated_dt())
+ 		pinctrl_provide_dummies();
+@@ -693,6 +789,7 @@ static struct platform_driver sh_pfc_driver = {
+ 	.driver		= {
+ 		.name	= DRV_NAME,
+ 		.of_match_table = of_match_ptr(sh_pfc_of_table),
++		.pm     = DEV_PM_OPS,
+ 	},
+ };
+ 
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index b9bb56c91b6f..213108a058fe 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -222,6 +222,7 @@ struct sh_pfc {
+ 	unsigned int nr_gpio_pins;
+ 
+ 	struct sh_pfc_chip *gpio;
++	u32 *saved_regs;
+ };
+ 
+ struct sh_pfc_soc_operations {
+-- 
+2.19.0
+
diff --git a/patches/0224-serial-sh-sci-Support-for-variable-HSCIF-hardware-RX.patch b/patches/0224-serial-sh-sci-Support-for-variable-HSCIF-hardware-RX.patch
new file mode 100644
index 00000000000000..61d44362eb3d0a
--- /dev/null
+++ b/patches/0224-serial-sh-sci-Support-for-variable-HSCIF-hardware-RX.patch
@@ -0,0 +1,181 @@
+From 315999a928cd1ceea3148a6e43c04c7c8a5b02ea Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 29 Sep 2017 15:08:53 +0200
+Subject: [PATCH 0224/1795] serial: sh-sci: Support for variable HSCIF hardware
+ RX timeout
+
+HSCIF has facilities that allow changing the timeout after which an RX
+interrupt is triggered even if the FIFO is not filled. This patch allows
+changing the default (15 bits of silence) using the existing sysfs
+attribute "rx_fifo_timeout".
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fa2abb03637a55288b22082d3d679db4fe74112a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 52 ++++++++++++++++++++++++++-----------
+ drivers/tty/serial/sh-sci.h |  3 +++
+ 2 files changed, 40 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 5d33bc1a0e09..6c9f99e67c13 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -149,6 +149,7 @@ struct sci_port {
+ 	int				rx_trigger;
+ 	struct timer_list		rx_fifo_timer;
+ 	int				rx_fifo_timeout;
++	u16				hscif_tot;
+ 
+ 	bool has_rtscts;
+ 	bool autorts;
+@@ -1106,8 +1107,14 @@ static ssize_t rx_fifo_timeout_show(struct device *dev,
+ {
+ 	struct uart_port *port = dev_get_drvdata(dev);
+ 	struct sci_port *sci = to_sci_port(port);
++	int v;
+ 
+-	return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
++	if (port->type == PORT_HSCIF)
++		v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
++	else
++		v = sci->rx_fifo_timeout;
++
++	return sprintf(buf, "%d\n", v);
+ }
+ 
+ static ssize_t rx_fifo_timeout_store(struct device *dev,
+@@ -1123,11 +1130,19 @@ static ssize_t rx_fifo_timeout_store(struct device *dev,
+ 	ret = kstrtol(buf, 0, &r);
+ 	if (ret)
+ 		return ret;
+-	sci->rx_fifo_timeout = r;
+-	scif_set_rtrg(port, 1);
+-	if (r > 0)
+-		setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
+-			    (unsigned long)sci);
++
++	if (port->type == PORT_HSCIF) {
++		if (r < 0 || r > 3)
++			return -EINVAL;
++		sci->hscif_tot = r << HSSCR_TOT_SHIFT;
++	} else {
++		sci->rx_fifo_timeout = r;
++		scif_set_rtrg(port, 1);
++		if (r > 0)
++			setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
++				    (unsigned long)sci);
++	}
++
+ 	return count;
+ }
+ 
+@@ -2044,9 +2059,13 @@ static void sci_shutdown(struct uart_port *port)
+ 	spin_lock_irqsave(&port->lock, flags);
+ 	sci_stop_rx(port);
+ 	sci_stop_tx(port);
+-	/* Stop RX and TX, disable related interrupts, keep clock source */
++	/*
++	 * Stop RX and TX, disable related interrupts, keep clock source
++	 * and HSCIF TOT bits
++	 */
+ 	scr = serial_port_in(port, SCSCR);
+-	serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
++	serial_port_out(port, SCSCR, scr &
++			(SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
+ 	spin_unlock_irqrestore(&port->lock, flags);
+ 
+ #ifdef CONFIG_SERIAL_SH_SCI_DMA
+@@ -2193,7 +2212,7 @@ static void sci_reset(struct uart_port *port)
+ 	unsigned int status;
+ 	struct sci_port *s = to_sci_port(port);
+ 
+-	serial_port_out(port, SCSCR, 0x00);	/* TE=0, RE=0, CKE1=0 */
++	serial_port_out(port, SCSCR, s->hscif_tot);	/* TE=0, RE=0, CKE1=0 */
+ 
+ 	reg = sci_getreg(port, SCFCR);
+ 	if (reg->size)
+@@ -2363,7 +2382,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 		dev_dbg(port->dev,
+ 			 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
+ 			 scr_val, smr_val, brr, sccks, dl, srr);
+-		serial_port_out(port, SCSCR, scr_val);
++		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 		serial_port_out(port, SCSMR, smr_val);
+ 		serial_port_out(port, SCBRR, brr);
+ 		if (sci_getreg(port, HSSRR)->size)
+@@ -2377,7 +2396,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 		smr_val |= serial_port_in(port, SCSMR) &
+ 			   (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
+ 		dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
+-		serial_port_out(port, SCSCR, scr_val);
++		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 		serial_port_out(port, SCSMR, smr_val);
+ 	}
+ 
+@@ -2414,7 +2433,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	scr_val |= SCSCR_RE | SCSCR_TE |
+ 		   (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
+ 	dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
+-	serial_port_out(port, SCSCR, scr_val);
++	serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 	if ((srr + 1 == 5) &&
+ 	    (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
+ 		/*
+@@ -2780,6 +2799,7 @@ static int sci_init_single(struct platform_device *dev,
+ 	}
+ 
+ 	sci_port->rx_fifo_timeout = 0;
++	sci_port->hscif_tot = 0;
+ 
+ 	/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
+ 	 * match the SoC datasheet, this should be investigated. Let platform
+@@ -2866,7 +2886,7 @@ static void serial_console_write(struct console *co, const char *s,
+ 	ctrl_temp = SCSCR_RE | SCSCR_TE |
+ 		    (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
+ 		    (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
+-	serial_port_out(port, SCSCR, ctrl_temp);
++	serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
+ 
+ 	uart_console_write(port, s, count, serial_console_putchar);
+ 
+@@ -2993,7 +3013,8 @@ static int sci_remove(struct platform_device *dev)
+ 		sysfs_remove_file(&dev->dev.kobj,
+ 				  &dev_attr_rx_fifo_trigger.attr);
+ 	}
+-	if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
++	if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
++	    port->port.type == PORT_HSCIF) {
+ 		sysfs_remove_file(&dev->dev.kobj,
+ 				  &dev_attr_rx_fifo_timeout.attr);
+ 	}
+@@ -3182,7 +3203,8 @@ static int sci_probe(struct platform_device *dev)
+ 		if (ret)
+ 			return ret;
+ 	}
+-	if (sp->port.type == PORT_SCIFA || sp->port.type ==  PORT_SCIFB) {
++	if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
++	    sp->port.type == PORT_HSCIF) {
+ 		ret = sysfs_create_file(&dev->dev.kobj,
+ 				&dev_attr_rx_fifo_timeout.attr);
+ 		if (ret) {
+diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
+index 938e23a2d166..a5f792fd48d9 100644
+--- a/drivers/tty/serial/sh-sci.h
++++ b/drivers/tty/serial/sh-sci.h
+@@ -63,6 +63,9 @@ enum {
+ #define SCSCR_TDRQE	BIT(15)	/* Tx Data Transfer Request Enable */
+ #define SCSCR_RDRQE	BIT(14)	/* Rx Data Transfer Request Enable */
+ 
++/* Serial Control Register, HSCIF-only bits */
++#define HSSCR_TOT_SHIFT	14
++
+ /* SCxSR (Serial Status Register) on SCI */
+ #define SCI_TDRE	BIT(7)	/* Transmit Data Register Empty */
+ #define SCI_RDRF	BIT(6)	/* Receive Data Register Full */
+-- 
+2.19.0
+
diff --git a/patches/0225-serial-sh-sci-Use-of_device_get_match_data-helper.patch b/patches/0225-serial-sh-sci-Use-of_device_get_match_data-helper.patch
new file mode 100644
index 00000000000000..201924a7d8777b
--- /dev/null
+++ b/patches/0225-serial-sh-sci-Use-of_device_get_match_data-helper.patch
@@ -0,0 +1,65 @@
+From 91b4056ca5ae05b69c021e40c64c41cf3a085f73 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:21:56 +0200
+Subject: [PATCH 0225/1795] serial: sh-sci: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+Note that when used with DT, there's always a valid match.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 6e605a01501b20ba8ace196536899195c8d296f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 6c9f99e67c13..2ce33146928c 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -37,6 +37,7 @@
+ #include <linux/module.h>
+ #include <linux/mm.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/scatterlist.h>
+@@ -3070,17 +3071,15 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
+ 					  unsigned int *dev_id)
+ {
+ 	struct device_node *np = pdev->dev.of_node;
+-	const struct of_device_id *match;
+ 	struct plat_sci_port *p;
+ 	struct sci_port *sp;
++	const void *data;
+ 	int id;
+ 
+ 	if (!IS_ENABLED(CONFIG_OF) || !np)
+ 		return NULL;
+ 
+-	match = of_match_node(of_sci_match, np);
+-	if (!match)
+-		return NULL;
++	data = of_device_get_match_data(&pdev->dev);
+ 
+ 	p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
+ 	if (!p)
+@@ -3100,8 +3099,8 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
+ 	sp = &sci_ports[id];
+ 	*dev_id = id;
+ 
+-	p->type = SCI_OF_TYPE(match->data);
+-	p->regtype = SCI_OF_REGTYPE(match->data);
++	p->type = SCI_OF_TYPE(data);
++	p->regtype = SCI_OF_REGTYPE(data);
+ 
+ 	sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
+ 
+-- 
+2.19.0
+
diff --git a/patches/0226-serial-sh-sci-Fix-init-data-attribute-for-struct-por.patch b/patches/0226-serial-sh-sci-Fix-init-data-attribute-for-struct-por.patch
new file mode 100644
index 00000000000000..80815e62def7a3
--- /dev/null
+++ b/patches/0226-serial-sh-sci-Fix-init-data-attribute-for-struct-por.patch
@@ -0,0 +1,41 @@
+From d9a67bba32c654ddb30d93a75a7aa0bd932ae5c5 Mon Sep 17 00:00:00 2001
+From: Matthias Kaehlcke <mka@chromium.org>
+Date: Mon, 9 Oct 2017 18:26:22 -0700
+Subject: [PATCH 0226/1795] serial: sh-sci: Fix init data attribute for struct
+ 'port_cfg'
+
+The __init attribute is meant to mark functions, use __initdata instead
+for the data structure.
+
+This fixes the following error when building with clang:
+
+drivers/tty/serial/sh-sci.c:3247:15: error: '__section__' attribute only
+  applies to functions, methods, properties, and global variables
+    static struct __init plat_sci_port port_cfg;
+
+Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
+Reviewed-by: Guenter Roeck <groeck@chromium.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit dd076cffb8cd675a8973fc9b6cea0c04be6f0111)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 2ce33146928c..7a6b896a2324 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -3274,7 +3274,7 @@ early_platform_init_buffer("earlyprintk", &sci_driver,
+ 			   early_serial_buf, ARRAY_SIZE(early_serial_buf));
+ #endif
+ #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
+-static struct __init plat_sci_port port_cfg;
++static struct plat_sci_port port_cfg __initdata;
+ 
+ static int __init early_console_setup(struct earlycon_device *device,
+ 				      int type)
+-- 
+2.19.0
+
diff --git a/patches/0227-serial-sh-sci-Fix-unlocked-access-to-SCSCR-register.patch b/patches/0227-serial-sh-sci-Fix-unlocked-access-to-SCSCR-register.patch
new file mode 100644
index 00000000000000..a5df46bf3c7f51
--- /dev/null
+++ b/patches/0227-serial-sh-sci-Fix-unlocked-access-to-SCSCR-register.patch
@@ -0,0 +1,152 @@
+From a0ec1fcfd1a61b1e07e971941299db39889a7715 Mon Sep 17 00:00:00 2001
+From: Takatoshi Akiyama <takatoshi.akiyama.kj@ps.hitachi-solutions.com>
+Date: Thu, 2 Nov 2017 11:14:55 +0100
+Subject: [PATCH 0227/1795] serial: sh-sci: Fix unlocked access to SCSCR
+ register
+
+The SCSCR register access in sci_break_ctl() is not locked.
+
+sci_start_tx() and sci_set_termios() changes the SCSCR register,
+but does not lock sci_port.
+
+Therefore, this patch adds lock during register access.
+
+Also, remove the log output that leads to a double lock.
+
+Some analysis of where locks are not taken is as follows.
+It appears that the lock is not taken in:
+  - sci_start_tx(), sci_stop_tx()  as this is installed as a callback.
+    And all callers of the callback take the lock.
+  - start_rx as callers take the lock.
+  - stop_rx. this is both installed as a callback and called directly.
+    In both cases the caller takes the lock.
+
+Signed-off-by: Takatoshi Akiyama <takatoshi.akiyama.kj@ps.hitachi-solutions.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1be2266392196de82d1cfcc8a68e770cf8f48c60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 25 ++++++++++++++++---------
+ 1 file changed, 16 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 7a6b896a2324..78f862df4f6e 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -1225,8 +1225,11 @@ static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
+ 	dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
+ 			  sg_dma_address(&s->sg_rx[0]));
+ 	dma_release_channel(chan);
+-	if (enable_pio)
++	if (enable_pio) {
++		spin_lock_irqsave(&port->lock, flags);
+ 		sci_start_rx(port);
++		spin_unlock_irqrestore(&port->lock, flags);
++	}
+ }
+ 
+ static void sci_dma_rx_complete(void *arg)
+@@ -1293,8 +1296,11 @@ static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
+ 	dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
+ 			 DMA_TO_DEVICE);
+ 	dma_release_channel(chan);
+-	if (enable_pio)
++	if (enable_pio) {
++		spin_lock_irqsave(&port->lock, flags);
+ 		sci_start_tx(port);
++		spin_unlock_irqrestore(&port->lock, flags);
++	}
+ }
+ 
+ static void sci_submit_rx(struct sci_port *s)
+@@ -2003,6 +2009,7 @@ static void sci_enable_ms(struct uart_port *port)
+ static void sci_break_ctl(struct uart_port *port, int break_state)
+ {
+ 	unsigned short scscr, scsptr;
++	unsigned long flags;
+ 
+ 	/* check wheter the port has SCSPTR */
+ 	if (!sci_getreg(port, SCSPTR)->size) {
+@@ -2013,6 +2020,7 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
+ 		return;
+ 	}
+ 
++	spin_lock_irqsave(&port->lock, flags);
+ 	scsptr = serial_port_in(port, SCSPTR);
+ 	scscr = serial_port_in(port, SCSCR);
+ 
+@@ -2026,6 +2034,7 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
+ 
+ 	serial_port_out(port, SCSPTR, scsptr);
+ 	serial_port_out(port, SCSCR, scscr);
++	spin_unlock_irqrestore(&port->lock, flags);
+ }
+ 
+ static int sci_startup(struct uart_port *port)
+@@ -2254,6 +2263,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	int min_err = INT_MAX, err;
+ 	unsigned long max_freq = 0;
+ 	int best_clk = -1;
++	unsigned long flags;
+ 
+ 	if ((termios->c_cflag & CSIZE) == CS7)
+ 		smr_val |= SCSMR_CHR;
+@@ -2363,6 +2373,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 		serial_port_out(port, SCCKS, sccks);
+ 	}
+ 
++	spin_lock_irqsave(&port->lock, flags);
++
+ 	sci_reset(port);
+ 
+ 	uart_update_timeout(port, termios->c_cflag, baud);
+@@ -2380,9 +2392,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 			case 27: smr_val |= SCSMR_SRC_27; break;
+ 			}
+ 		smr_val |= cks;
+-		dev_dbg(port->dev,
+-			 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
+-			 scr_val, smr_val, brr, sccks, dl, srr);
+ 		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 		serial_port_out(port, SCSMR, smr_val);
+ 		serial_port_out(port, SCBRR, brr);
+@@ -2396,7 +2405,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 		scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
+ 		smr_val |= serial_port_in(port, SCSMR) &
+ 			   (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
+-		dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
+ 		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 		serial_port_out(port, SCSMR, smr_val);
+ 	}
+@@ -2433,7 +2441,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 
+ 	scr_val |= SCSCR_RE | SCSCR_TE |
+ 		   (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
+-	dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
+ 	serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 	if ((srr + 1 == 5) &&
+ 	    (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
+@@ -2480,8 +2487,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	s->rx_frame = (100 * bits * HZ) / (baud / 10);
+ #ifdef CONFIG_SERIAL_SH_SCI_DMA
+ 	s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
+-	dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
+-		s->rx_timeout * 1000 / HZ, port->timeout);
+ 	if (s->rx_timeout < msecs_to_jiffies(20))
+ 		s->rx_timeout = msecs_to_jiffies(20);
+ #endif
+@@ -2489,6 +2494,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	if ((termios->c_cflag & CREAD) != 0)
+ 		sci_start_rx(port);
+ 
++	spin_unlock_irqrestore(&port->lock, flags);
++
+ 	sci_port_disable(s);
+ 
+ 	if (UART_ENABLE_MS(port, termios->c_cflag))
+-- 
+2.19.0
+
diff --git a/patches/0228-Input-st1232-remove-obsolete-platform-device-support.patch b/patches/0228-Input-st1232-remove-obsolete-platform-device-support.patch
new file mode 100644
index 00000000000000..a495a6bd375ba9
--- /dev/null
+++ b/patches/0228-Input-st1232-remove-obsolete-platform-device-support.patch
@@ -0,0 +1,106 @@
+From abf37b18d56babeae031e39766b7bd7e8119b0be Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 31 Oct 2017 09:47:28 -0700
+Subject: [PATCH 0228/1795] Input: st1232 - remove obsolete platform device
+ support
+
+Commit 1fa59bda21c7fa36 ("ARM: shmobile: Remove legacy board code for
+Armadillo-800 EVA"), removed the last user of st1232_pdata and the
+"st1232-ts" platform device.  All remaining users use DT.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+(cherry picked from commit 4a1a57df97636b9323c4221cc75a35694b6d34c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/input/touchscreen/st1232.c         | 16 +++-------------
+ include/linux/platform_data/st1232_pdata.h | 14 --------------
+ 2 files changed, 3 insertions(+), 27 deletions(-)
+ delete mode 100644 include/linux/platform_data/st1232_pdata.h
+
+diff --git a/drivers/input/touchscreen/st1232.c b/drivers/input/touchscreen/st1232.c
+index be5615c6bf8f..d5dfa4053bbf 100644
+--- a/drivers/input/touchscreen/st1232.c
++++ b/drivers/input/touchscreen/st1232.c
+@@ -29,7 +29,6 @@
+ #include <linux/pm_qos.h>
+ #include <linux/slab.h>
+ #include <linux/types.h>
+-#include <linux/platform_data/st1232_pdata.h>
+ 
+ #define ST1232_TS_NAME	"st1232-ts"
+ 
+@@ -152,10 +151,9 @@ static void st1232_ts_power(struct st1232_ts_data *ts, bool poweron)
+ }
+ 
+ static int st1232_ts_probe(struct i2c_client *client,
+-					const struct i2c_device_id *id)
++			   const struct i2c_device_id *id)
+ {
+ 	struct st1232_ts_data *ts;
+-	struct st1232_pdata *pdata = dev_get_platdata(&client->dev);
+ 	struct input_dev *input_dev;
+ 	int error;
+ 
+@@ -180,13 +178,7 @@ static int st1232_ts_probe(struct i2c_client *client,
+ 	ts->client = client;
+ 	ts->input_dev = input_dev;
+ 
+-	if (pdata)
+-		ts->reset_gpio = pdata->reset_gpio;
+-	else if (client->dev.of_node)
+-		ts->reset_gpio = of_get_gpio(client->dev.of_node, 0);
+-	else
+-		ts->reset_gpio = -ENODEV;
+-
++	ts->reset_gpio = of_get_gpio(client->dev.of_node, 0);
+ 	if (gpio_is_valid(ts->reset_gpio)) {
+ 		error = devm_gpio_request(&client->dev, ts->reset_gpio, NULL);
+ 		if (error) {
+@@ -281,13 +273,11 @@ static const struct i2c_device_id st1232_ts_id[] = {
+ };
+ MODULE_DEVICE_TABLE(i2c, st1232_ts_id);
+ 
+-#ifdef CONFIG_OF
+ static const struct of_device_id st1232_ts_dt_ids[] = {
+ 	{ .compatible = "sitronix,st1232", },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, st1232_ts_dt_ids);
+-#endif
+ 
+ static struct i2c_driver st1232_ts_driver = {
+ 	.probe		= st1232_ts_probe,
+@@ -295,7 +285,7 @@ static struct i2c_driver st1232_ts_driver = {
+ 	.id_table	= st1232_ts_id,
+ 	.driver = {
+ 		.name	= ST1232_TS_NAME,
+-		.of_match_table = of_match_ptr(st1232_ts_dt_ids),
++		.of_match_table = st1232_ts_dt_ids,
+ 		.pm	= &st1232_ts_pm_ops,
+ 	},
+ };
+diff --git a/include/linux/platform_data/st1232_pdata.h b/include/linux/platform_data/st1232_pdata.h
+deleted file mode 100644
+index 1dcd23bee24e..000000000000
+--- a/include/linux/platform_data/st1232_pdata.h
++++ /dev/null
+@@ -1,14 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-#ifndef _LINUX_ST1232_PDATA_H
+-#define _LINUX_ST1232_PDATA_H
+-
+-/*
+- * Optional platform data
+- *
+- * Use this if you want the driver to drive the reset pin.
+- */
+-struct st1232_pdata {
+-	int reset_gpio;
+-};
+-
+-#endif
+-- 
+2.19.0
+
diff --git a/patches/0229-usb-gadget-udc-renesas_usb3-move-pm_runtime_-en-dis-.patch b/patches/0229-usb-gadget-udc-renesas_usb3-move-pm_runtime_-en-dis-.patch
new file mode 100644
index 00000000000000..47752e78e41c71
--- /dev/null
+++ b/patches/0229-usb-gadget-udc-renesas_usb3-move-pm_runtime_-en-dis-.patch
@@ -0,0 +1,61 @@
+From e47755f19d73ee0f9b76b6aab46148b36eaf947e Mon Sep 17 00:00:00 2001
+From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
+Date: Fri, 29 Sep 2017 20:44:59 +0900
+Subject: [PATCH 0229/1795] usb: gadget: udc: renesas_usb3: move
+ pm_runtime_{en,dis}able()
+
+This patch moves pm_runtime_{en,dis}able() call timing to
+renesas_usb3_{probe,remove}() for supporting PM_SLEEP feature in
+the future.
+
+Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
+[shimoda: Revise the commit log]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+
+(cherry picked from commit cf06df3fae286b795c1abf59c4b493ebf30a7a9f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 8de7d72b130b..3f662e524300 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2247,7 +2247,6 @@ static int renesas_usb3_start(struct usb_gadget *gadget,
+ 	/* hook up the driver */
+ 	usb3->driver = driver;
+ 
+-	pm_runtime_enable(usb3_to_dev(usb3));
+ 	pm_runtime_get_sync(usb3_to_dev(usb3));
+ 
+ 	renesas_usb3_init_controller(usb3);
+@@ -2265,7 +2264,6 @@ static int renesas_usb3_stop(struct usb_gadget *gadget)
+ 	renesas_usb3_stop_controller(usb3);
+ 
+ 	pm_runtime_put(usb3_to_dev(usb3));
+-	pm_runtime_disable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+ }
+@@ -2418,6 +2416,7 @@ static int renesas_usb3_remove(struct platform_device *pdev)
+ 	renesas_usb3_dma_free_prd(usb3, &pdev->dev);
+ 
+ 	__renesas_usb3_ep_free_request(usb3->ep0_req);
++	pm_runtime_disable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+ }
+@@ -2653,6 +2652,7 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	renesas_usb3_debugfs_init(usb3, &pdev->dev);
+ 
+ 	dev_info(&pdev->dev, "probed\n");
++	pm_runtime_enable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0230-usb-gadget-udc-renesas_usb3-Add-suspend-resume-funct.patch b/patches/0230-usb-gadget-udc-renesas_usb3-Add-suspend-resume-funct.patch
new file mode 100644
index 00000000000000..58a3f9ecae001c
--- /dev/null
+++ b/patches/0230-usb-gadget-udc-renesas_usb3-Add-suspend-resume-funct.patch
@@ -0,0 +1,73 @@
+From 4a8fe03b5d9996f0223676cb95584dcb72239152 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 29 Sep 2017 20:45:00 +0900
+Subject: [PATCH 0230/1795] usb: gadget: udc: renesas_usb3: Add suspend/resume
+ functions
+
+This patch adds support suspend/resume functions
+
+Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
+[shimoda: add the commit log]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+
+(cherry picked from commit 90d588642a7ff598533f68c2f56ee64657a40186)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 34 +++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 3f662e524300..3368cb1ac51c 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2668,11 +2668,45 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	return ret;
+ }
+ 
++#ifdef CONFIG_PM_SLEEP
++static int renesas_usb3_suspend(struct device *dev)
++{
++	struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
++
++	/* Not started */
++	if (!usb3->driver)
++		return 0;
++
++	renesas_usb3_stop_controller(usb3);
++	pm_runtime_put(dev);
++
++	return 0;
++}
++
++static int renesas_usb3_resume(struct device *dev)
++{
++	struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
++
++	/* Not started */
++	if (!usb3->driver)
++		return 0;
++
++	pm_runtime_get_sync(dev);
++	renesas_usb3_init_controller(usb3);
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(renesas_usb3_pm_ops, renesas_usb3_suspend,
++			renesas_usb3_resume);
++
+ static struct platform_driver renesas_usb3_driver = {
+ 	.probe		= renesas_usb3_probe,
+ 	.remove		= renesas_usb3_remove,
+ 	.driver		= {
+ 		.name =	(char *)udc_name,
++		.pm		= &renesas_usb3_pm_ops,
+ 		.of_match_table = of_match_ptr(usb3_of_match),
+ 	},
+ };
+-- 
+2.19.0
+
diff --git a/patches/0231-usb-gadget-udc-renesas_usb3-add-support-for-generic-.patch b/patches/0231-usb-gadget-udc-renesas_usb3-add-support-for-generic-.patch
new file mode 100644
index 00000000000000..57b060d14df1f2
--- /dev/null
+++ b/patches/0231-usb-gadget-udc-renesas_usb3-add-support-for-generic-.patch
@@ -0,0 +1,139 @@
+From 7fc5a807ad121c4c9eb52c022037f1df5ad8a442 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 29 Sep 2017 20:45:01 +0900
+Subject: [PATCH 0231/1795] usb: gadget: udc: renesas_usb3: add support for
+ generic phy
+
+This patch adds support for generic phy as an optional. If you want
+to use a generic phy (e.g. phy-rcar-gen3-usb3 driver) on this driver,
+you have to do "insmod phy-rcar-gen3-usb3.ko" first for now.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 279d4bc6406022461713cd6a3e5411336d2ff26b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/gadget/udc/renesas_usb3.c
+---
+ .../devicetree/bindings/usb/renesas_usb3.txt  |  4 +++
+ drivers/usb/gadget/udc/renesas_usb3.c         | 26 +++++++++++++++++--
+ 2 files changed, 28 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usb3.txt b/Documentation/devicetree/bindings/usb/renesas_usb3.txt
+index e28025883b79..87a45e2f9b7f 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usb3.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usb3.txt
+@@ -15,6 +15,10 @@ Required properties:
+   - interrupts: Interrupt specifier for the USB3.0 Peripheral
+   - clocks: clock phandle and specifier pair
+ 
++Optional properties:
++  - phys: phandle + phy specifier pair
++  - phy-names: must be "usb"
++
+ Example of R-Car H3 ES1.x:
+ 	usb3_peri0: usb@ee020000 {
+ 		compatible = "renesas,r8a7795-usb3-peri",
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 3368cb1ac51c..ef833f5c2523 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -1,7 +1,7 @@
+ /*
+  * Renesas USB3.0 Peripheral driver (USB gadget)
+  *
+- * Copyright (C) 2015  Renesas Electronics Corporation
++ * Copyright (C) 2015-2017  Renesas Electronics Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -17,6 +17,7 @@
+ #include <linux/io.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
++#include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/sizes.h>
+@@ -334,6 +335,7 @@ struct renesas_usb3 {
+ 	struct usb_gadget_driver *driver;
+ 	struct extcon_dev *extcon;
+ 	struct work_struct extcon_work;
++	struct phy *phy;
+ 	struct dentry *dentry;
+ 
+ 	struct renesas_usb3_ep *usb3_ep;
+@@ -2247,6 +2249,9 @@ static int renesas_usb3_start(struct usb_gadget *gadget,
+ 	/* hook up the driver */
+ 	usb3->driver = driver;
+ 
++	if (usb3->phy)
++		phy_init(usb3->phy);
++
+ 	pm_runtime_get_sync(usb3_to_dev(usb3));
+ 
+ 	renesas_usb3_init_controller(usb3);
+@@ -2263,6 +2268,9 @@ static int renesas_usb3_stop(struct usb_gadget *gadget)
+ 	usb3->driver = NULL;
+ 	renesas_usb3_stop_controller(usb3);
+ 
++	if (usb3->phy)
++		phy_exit(usb3->phy);
++
+ 	pm_runtime_put(usb3_to_dev(usb3));
+ 
+ 	return 0;
+@@ -2416,6 +2424,8 @@ static int renesas_usb3_remove(struct platform_device *pdev)
+ 	renesas_usb3_dma_free_prd(usb3, &pdev->dev);
+ 
+ 	__renesas_usb3_ep_free_request(usb3->ep0_req);
++	if (usb3->phy)
++		phy_put(usb3->phy);
+ 	pm_runtime_disable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+@@ -2647,11 +2657,19 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto err_dev_create;
+ 
++	/*
++	 * This is an optional. So, if this driver cannot get a phy,
++	 * this driver will not handle a phy anymore.
++	 */
++	usb3->phy = devm_phy_get(&pdev->dev, "usb");
++	if (IS_ERR(usb3->phy))
++		usb3->phy = NULL;
++
+ 	usb3->workaround_for_vbus = priv->workaround_for_vbus;
+ 
+ 	renesas_usb3_debugfs_init(usb3, &pdev->dev);
+ 
+-	dev_info(&pdev->dev, "probed\n");
++	dev_info(&pdev->dev, "probed%s\n", usb3->phy ? " with phy" : "");
+ 	pm_runtime_enable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+@@ -2678,6 +2696,8 @@ static int renesas_usb3_suspend(struct device *dev)
+ 		return 0;
+ 
+ 	renesas_usb3_stop_controller(usb3);
++	if (usb3->phy)
++		phy_exit(usb3->phy);
+ 	pm_runtime_put(dev);
+ 
+ 	return 0;
+@@ -2691,6 +2711,8 @@ static int renesas_usb3_resume(struct device *dev)
+ 	if (!usb3->driver)
+ 		return 0;
+ 
++	if (usb3->phy)
++		phy_init(usb3->phy);
+ 	pm_runtime_get_sync(dev);
+ 	renesas_usb3_init_controller(usb3);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0232-usb-gadget-udc-renesas_usb3-Use-of_device_get_match_.patch b/patches/0232-usb-gadget-udc-renesas_usb3-Use-of_device_get_match_.patch
new file mode 100644
index 00000000000000..4e893f8d52b255
--- /dev/null
+++ b/patches/0232-usb-gadget-udc-renesas_usb3-Use-of_device_get_match_.patch
@@ -0,0 +1,51 @@
+From aa05d4b8bc56911dd2ac9793871436e2f6f9792a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:23:31 +0200
+Subject: [PATCH 0232/1795] usb: gadget: udc: renesas_usb3: Use
+ of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding,
+postponing the matching until when it's really needed.
+Note that the renesas_usb3 driver is used with DT only, so there's
+always a valid match.
+
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit ca02a5af650cf3addb004196c2ab713b020445ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index ef833f5c2523..0a74919bd754 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2582,20 +2582,15 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ {
+ 	struct renesas_usb3 *usb3;
+ 	struct resource *res;
+-	const struct of_device_id *match;
+ 	int irq, ret;
+ 	const struct renesas_usb3_priv *priv;
+ 	const struct soc_device_attribute *attr;
+ 
+-	match = of_match_node(usb3_of_match, pdev->dev.of_node);
+-	if (!match)
+-		return -ENODEV;
+-
+ 	attr = soc_device_match(renesas_usb3_quirks_match);
+ 	if (attr)
+ 		priv = attr->data;
+ 	else
+-		priv = match->data;
++		priv = of_device_get_match_data(&pdev->dev);
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0) {
+-- 
+2.19.0
+
diff --git a/patches/0233-usb-gadget-udc-renesas_usb3-make-const-array-max_pac.patch b/patches/0233-usb-gadget-udc-renesas_usb3-make-const-array-max_pac.patch
new file mode 100644
index 00000000000000..0b1f67c5abcc58
--- /dev/null
+++ b/patches/0233-usb-gadget-udc-renesas_usb3-make-const-array-max_pac.patch
@@ -0,0 +1,44 @@
+From 9f7c4bf1285af7b5ed33355cf03b9c58d3404c2e Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 2 Nov 2017 15:53:25 +0000
+Subject: [PATCH 0233/1795] usb: gadget: udc: renesas_usb3: make const array
+ max_packet_array static
+
+Don't populate the const array max_packet_array on the stack, instead make
+it static. Makes the object code smaller by over 90 bytes:
+
+Before:
+   text	   data	    bss	    dec	    hex	filename
+  34337	   5612	    128	  40077	   9c8d	renesas_usb3.o
+
+After:
+   text	   data	    bss	    dec	    hex	filename
+  34149	   5708	    128	  39985	   9c31	renesas_usb3.o
+
+(gcc version 7.2.0 x86_64)
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 8af620f06f015eb9e9062f6398204ee011b5ef22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 0a74919bd754..7e0548f6bd9e 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2066,7 +2066,7 @@ static u32 usb3_calc_rammap_val(struct renesas_usb3_ep *usb3_ep,
+ 				const struct usb_endpoint_descriptor *desc)
+ {
+ 	int i;
+-	const u32 max_packet_array[] = {8, 16, 32, 64, 512};
++	static const u32 max_packet_array[] = {8, 16, 32, 64, 512};
+ 	u32 mpkt = PN_RAMMAP_MPKT(1024);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(max_packet_array); i++) {
+-- 
+2.19.0
+
diff --git a/patches/0234-USB-add-SPDX-identifiers-to-all-remaining-files-in-d.patch b/patches/0234-USB-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
new file mode 100644
index 00000000000000..710c02b2588a05
--- /dev/null
+++ b/patches/0234-USB-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
@@ -0,0 +1,6543 @@
+From e87ed8b2a6064dff3432e141f58bf5259ac7d626 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Fri, 3 Nov 2017 11:28:30 +0100
+Subject: [PATCH 0234/1795] USB: add SPDX identifiers to all remaining files in
+ drivers/usb/
+
+It's good to have SPDX identifiers in all files to make it easier to
+audit the kernel tree for correct licenses.
+
+Update the drivers/usb/ and include/linux/usb* files with the correct
+SPDX license identifier based on the license text in the file itself.
+The SPDX identifier is a legally binding shorthand, which can be used
+instead of the full boiler plate text.
+
+This work is based on a script and data from Thomas Gleixner, Philippe
+Ombredanne, and Kate Stewart.
+
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Kate Stewart <kstewart@linuxfoundation.org>
+Cc: Philippe Ombredanne <pombredanne@nexb.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5fd54ace4721fc5ce2bb5aef6318fcf17f421460)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/atm/cxacru.c                       | 1 +
+ drivers/usb/atm/speedtch.c                     | 1 +
+ drivers/usb/atm/ueagle-atm.c                   | 1 +
+ drivers/usb/atm/usbatm.c                       | 1 +
+ drivers/usb/atm/usbatm.h                       | 1 +
+ drivers/usb/atm/xusbatm.c                      | 1 +
+ drivers/usb/c67x00/c67x00-drv.c                | 1 +
+ drivers/usb/c67x00/c67x00-hcd.c                | 1 +
+ drivers/usb/c67x00/c67x00-hcd.h                | 1 +
+ drivers/usb/c67x00/c67x00-ll-hpi.c             | 1 +
+ drivers/usb/c67x00/c67x00-sched.c              | 1 +
+ drivers/usb/c67x00/c67x00.h                    | 1 +
+ drivers/usb/chipidea/bits.h                    | 1 +
+ drivers/usb/chipidea/ci.h                      | 1 +
+ drivers/usb/chipidea/ci_hdrc_imx.c             | 1 +
+ drivers/usb/chipidea/ci_hdrc_imx.h             | 1 +
+ drivers/usb/chipidea/ci_hdrc_msm.c             | 1 +
+ drivers/usb/chipidea/ci_hdrc_pci.c             | 1 +
+ drivers/usb/chipidea/ci_hdrc_usb2.c            | 1 +
+ drivers/usb/chipidea/ci_hdrc_zevio.c           | 1 +
+ drivers/usb/chipidea/core.c                    | 1 +
+ drivers/usb/chipidea/host.c                    | 1 +
+ drivers/usb/chipidea/otg.c                     | 1 +
+ drivers/usb/chipidea/otg.h                     | 1 +
+ drivers/usb/chipidea/otg_fsm.c                 | 1 +
+ drivers/usb/chipidea/otg_fsm.h                 | 1 +
+ drivers/usb/chipidea/udc.c                     | 1 +
+ drivers/usb/chipidea/udc.h                     | 1 +
+ drivers/usb/chipidea/ulpi.c                    | 1 +
+ drivers/usb/chipidea/usbmisc_imx.c             | 1 +
+ drivers/usb/class/cdc-acm.c                    | 1 +
+ drivers/usb/class/cdc-wdm.c                    | 1 +
+ drivers/usb/class/usblp.c                      | 1 +
+ drivers/usb/class/usbtmc.c                     | 1 +
+ drivers/usb/common/common.c                    | 1 +
+ drivers/usb/common/led.c                       | 1 +
+ drivers/usb/common/ulpi.c                      | 1 +
+ drivers/usb/common/usb-otg-fsm.c               | 1 +
+ drivers/usb/core/devices.c                     | 1 +
+ drivers/usb/core/devio.c                       | 1 +
+ drivers/usb/core/hcd-pci.c                     | 1 +
+ drivers/usb/core/hcd.c                         | 1 +
+ drivers/usb/core/hub.h                         | 1 +
+ drivers/usb/core/ledtrig-usbport.c             | 1 +
+ drivers/usb/core/of.c                          | 1 +
+ drivers/usb/core/otg_whitelist.h               | 1 +
+ drivers/usb/core/port.c                        | 1 +
+ drivers/usb/core/quirks.c                      | 1 +
+ drivers/usb/core/usb-acpi.c                    | 1 +
+ drivers/usb/dwc2/core.c                        | 1 +
+ drivers/usb/dwc2/core.h                        | 1 +
+ drivers/usb/dwc2/core_intr.c                   | 1 +
+ drivers/usb/dwc2/debug.h                       | 1 +
+ drivers/usb/dwc2/debugfs.c                     | 1 +
+ drivers/usb/dwc2/gadget.c                      | 1 +
+ drivers/usb/dwc2/hcd.c                         | 1 +
+ drivers/usb/dwc2/hcd.h                         | 1 +
+ drivers/usb/dwc2/hcd_ddma.c                    | 1 +
+ drivers/usb/dwc2/hcd_intr.c                    | 1 +
+ drivers/usb/dwc2/hcd_queue.c                   | 1 +
+ drivers/usb/dwc2/hw.h                          | 1 +
+ drivers/usb/dwc2/params.c                      | 1 +
+ drivers/usb/dwc2/pci.c                         | 1 +
+ drivers/usb/dwc2/platform.c                    | 1 +
+ drivers/usb/dwc3/core.c                        | 1 +
+ drivers/usb/dwc3/core.h                        | 1 +
+ drivers/usb/dwc3/debug.h                       | 1 +
+ drivers/usb/dwc3/debugfs.c                     | 1 +
+ drivers/usb/dwc3/drd.c                         | 1 +
+ drivers/usb/dwc3/dwc3-exynos.c                 | 1 +
+ drivers/usb/dwc3/dwc3-keystone.c               | 1 +
+ drivers/usb/dwc3/dwc3-of-simple.c              | 1 +
+ drivers/usb/dwc3/dwc3-omap.c                   | 1 +
+ drivers/usb/dwc3/dwc3-pci.c                    | 1 +
+ drivers/usb/dwc3/dwc3-st.c                     | 1 +
+ drivers/usb/dwc3/ep0.c                         | 1 +
+ drivers/usb/dwc3/gadget.c                      | 1 +
+ drivers/usb/dwc3/gadget.h                      | 1 +
+ drivers/usb/dwc3/host.c                        | 1 +
+ drivers/usb/dwc3/io.h                          | 1 +
+ drivers/usb/dwc3/trace.c                       | 1 +
+ drivers/usb/dwc3/trace.h                       | 1 +
+ drivers/usb/dwc3/ulpi.c                        | 1 +
+ drivers/usb/early/ehci-dbgp.c                  | 1 +
+ drivers/usb/early/xhci-dbc.c                   | 1 +
+ drivers/usb/early/xhci-dbc.h                   | 1 +
+ drivers/usb/gadget/composite.c                 | 1 +
+ drivers/usb/gadget/config.c                    | 1 +
+ drivers/usb/gadget/configfs.c                  | 1 +
+ drivers/usb/gadget/epautoconf.c                | 1 +
+ drivers/usb/gadget/function/f_acm.c            | 1 +
+ drivers/usb/gadget/function/f_ecm.c            | 1 +
+ drivers/usb/gadget/function/f_eem.c            | 1 +
+ drivers/usb/gadget/function/f_fs.c             | 1 +
+ drivers/usb/gadget/function/f_hid.c            | 1 +
+ drivers/usb/gadget/function/f_loopback.c       | 1 +
+ drivers/usb/gadget/function/f_mass_storage.c   | 1 +
+ drivers/usb/gadget/function/f_midi.c           | 1 +
+ drivers/usb/gadget/function/f_ncm.c            | 1 +
+ drivers/usb/gadget/function/f_obex.c           | 1 +
+ drivers/usb/gadget/function/f_phonet.c         | 1 +
+ drivers/usb/gadget/function/f_printer.c        | 1 +
+ drivers/usb/gadget/function/f_rndis.c          | 1 +
+ drivers/usb/gadget/function/f_serial.c         | 1 +
+ drivers/usb/gadget/function/f_sourcesink.c     | 1 +
+ drivers/usb/gadget/function/f_subset.c         | 1 +
+ drivers/usb/gadget/function/f_tcm.c            | 1 +
+ drivers/usb/gadget/function/f_uac1.c           | 1 +
+ drivers/usb/gadget/function/f_uac1_legacy.c    | 1 +
+ drivers/usb/gadget/function/f_uac2.c           | 1 +
+ drivers/usb/gadget/function/f_uvc.c            | 1 +
+ drivers/usb/gadget/function/f_uvc.h            | 1 +
+ drivers/usb/gadget/function/rndis.c            | 1 +
+ drivers/usb/gadget/function/rndis.h            | 1 +
+ drivers/usb/gadget/function/storage_common.c   | 1 +
+ drivers/usb/gadget/function/u_audio.c          | 1 +
+ drivers/usb/gadget/function/u_audio.h          | 1 +
+ drivers/usb/gadget/function/u_ecm.h            | 1 +
+ drivers/usb/gadget/function/u_eem.h            | 1 +
+ drivers/usb/gadget/function/u_ether.c          | 1 +
+ drivers/usb/gadget/function/u_ether.h          | 1 +
+ drivers/usb/gadget/function/u_ether_configfs.h | 1 +
+ drivers/usb/gadget/function/u_fs.h             | 1 +
+ drivers/usb/gadget/function/u_gether.h         | 1 +
+ drivers/usb/gadget/function/u_hid.h            | 1 +
+ drivers/usb/gadget/function/u_midi.h           | 1 +
+ drivers/usb/gadget/function/u_ncm.h            | 1 +
+ drivers/usb/gadget/function/u_phonet.h         | 1 +
+ drivers/usb/gadget/function/u_printer.h        | 1 +
+ drivers/usb/gadget/function/u_rndis.h          | 1 +
+ drivers/usb/gadget/function/u_serial.c         | 1 +
+ drivers/usb/gadget/function/u_serial.h         | 1 +
+ drivers/usb/gadget/function/u_tcm.h            | 1 +
+ drivers/usb/gadget/function/u_uac1.h           | 1 +
+ drivers/usb/gadget/function/u_uac1_legacy.c    | 1 +
+ drivers/usb/gadget/function/u_uac1_legacy.h    | 1 +
+ drivers/usb/gadget/function/u_uac2.h           | 1 +
+ drivers/usb/gadget/function/u_uvc.h            | 1 +
+ drivers/usb/gadget/function/uvc.h              | 1 +
+ drivers/usb/gadget/function/uvc_configfs.c     | 1 +
+ drivers/usb/gadget/function/uvc_configfs.h     | 1 +
+ drivers/usb/gadget/function/uvc_queue.c        | 1 +
+ drivers/usb/gadget/function/uvc_v4l2.c         | 1 +
+ drivers/usb/gadget/function/uvc_v4l2.h         | 1 +
+ drivers/usb/gadget/function/uvc_video.c        | 1 +
+ drivers/usb/gadget/function/uvc_video.h        | 1 +
+ drivers/usb/gadget/functions.c                 | 1 +
+ drivers/usb/gadget/legacy/acm_ms.c             | 1 +
+ drivers/usb/gadget/legacy/audio.c              | 1 +
+ drivers/usb/gadget/legacy/cdc2.c               | 1 +
+ drivers/usb/gadget/legacy/dbgp.c               | 1 +
+ drivers/usb/gadget/legacy/ether.c              | 1 +
+ drivers/usb/gadget/legacy/g_ffs.c              | 1 +
+ drivers/usb/gadget/legacy/gmidi.c              | 1 +
+ drivers/usb/gadget/legacy/hid.c                | 1 +
+ drivers/usb/gadget/legacy/inode.c              | 1 +
+ drivers/usb/gadget/legacy/mass_storage.c       | 1 +
+ drivers/usb/gadget/legacy/multi.c              | 1 +
+ drivers/usb/gadget/legacy/ncm.c                | 1 +
+ drivers/usb/gadget/legacy/nokia.c              | 1 +
+ drivers/usb/gadget/legacy/printer.c            | 1 +
+ drivers/usb/gadget/legacy/serial.c             | 1 +
+ drivers/usb/gadget/legacy/tcm_usb_gadget.c     | 1 +
+ drivers/usb/gadget/legacy/webcam.c             | 1 +
+ drivers/usb/gadget/legacy/zero.c               | 1 +
+ drivers/usb/gadget/u_f.c                       | 1 +
+ drivers/usb/gadget/u_f.h                       | 1 +
+ drivers/usb/gadget/u_os_desc.h                 | 1 +
+ drivers/usb/gadget/udc/amd5536udc.h            | 1 +
+ drivers/usb/gadget/udc/amd5536udc_pci.c        | 1 +
+ drivers/usb/gadget/udc/at91_udc.c              | 1 +
+ drivers/usb/gadget/udc/at91_udc.h              | 1 +
+ drivers/usb/gadget/udc/atmel_usba_udc.c        | 1 +
+ drivers/usb/gadget/udc/atmel_usba_udc.h        | 1 +
+ drivers/usb/gadget/udc/bcm63xx_udc.c           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc.h               | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_cmd.c           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_cmd.h           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_core.c          | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_dbg.c           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_dbg.h           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_ep.c            | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_ep.h            | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_pci.c           | 1 +
+ drivers/usb/gadget/udc/bdc/bdc_udc.c           | 1 +
+ drivers/usb/gadget/udc/core.c                  | 1 +
+ drivers/usb/gadget/udc/dummy_hcd.c             | 1 +
+ drivers/usb/gadget/udc/fotg210-udc.c           | 1 +
+ drivers/usb/gadget/udc/fotg210.h               | 1 +
+ drivers/usb/gadget/udc/fsl_mxc_udc.c           | 1 +
+ drivers/usb/gadget/udc/fsl_qe_udc.c            | 1 +
+ drivers/usb/gadget/udc/fsl_qe_udc.h            | 1 +
+ drivers/usb/gadget/udc/fsl_udc_core.c          | 1 +
+ drivers/usb/gadget/udc/fsl_usb2_udc.h          | 1 +
+ drivers/usb/gadget/udc/fusb300_udc.c           | 1 +
+ drivers/usb/gadget/udc/fusb300_udc.h           | 1 +
+ drivers/usb/gadget/udc/goku_udc.c              | 1 +
+ drivers/usb/gadget/udc/goku_udc.h              | 1 +
+ drivers/usb/gadget/udc/gr_udc.c                | 1 +
+ drivers/usb/gadget/udc/gr_udc.h                | 1 +
+ drivers/usb/gadget/udc/lpc32xx_udc.c           | 1 +
+ drivers/usb/gadget/udc/m66592-udc.c            | 1 +
+ drivers/usb/gadget/udc/m66592-udc.h            | 1 +
+ drivers/usb/gadget/udc/mv_u3d.h                | 1 +
+ drivers/usb/gadget/udc/mv_u3d_core.c           | 1 +
+ drivers/usb/gadget/udc/mv_udc.h                | 1 +
+ drivers/usb/gadget/udc/mv_udc_core.c           | 1 +
+ drivers/usb/gadget/udc/net2272.c               | 1 +
+ drivers/usb/gadget/udc/net2272.h               | 1 +
+ drivers/usb/gadget/udc/net2280.c               | 1 +
+ drivers/usb/gadget/udc/net2280.h               | 1 +
+ drivers/usb/gadget/udc/omap_udc.c              | 1 +
+ drivers/usb/gadget/udc/pch_udc.c               | 1 +
+ drivers/usb/gadget/udc/pxa25x_udc.c            | 1 +
+ drivers/usb/gadget/udc/pxa25x_udc.h            | 1 +
+ drivers/usb/gadget/udc/pxa27x_udc.c            | 1 +
+ drivers/usb/gadget/udc/pxa27x_udc.h            | 1 +
+ drivers/usb/gadget/udc/r8a66597-udc.c          | 1 +
+ drivers/usb/gadget/udc/r8a66597-udc.h          | 1 +
+ drivers/usb/gadget/udc/renesas_usb3.c          | 1 +
+ drivers/usb/gadget/udc/s3c-hsudc.c             | 1 +
+ drivers/usb/gadget/udc/s3c2410_udc.c           | 1 +
+ drivers/usb/gadget/udc/s3c2410_udc.h           | 1 +
+ drivers/usb/gadget/udc/snps_udc_core.c         | 1 +
+ drivers/usb/gadget/udc/snps_udc_plat.c         | 1 +
+ drivers/usb/gadget/udc/trace.c                 | 1 +
+ drivers/usb/gadget/udc/trace.h                 | 1 +
+ drivers/usb/gadget/udc/udc-xilinx.c            | 1 +
+ drivers/usb/gadget/usbstring.c                 | 1 +
+ drivers/usb/host/bcma-hcd.c                    | 1 +
+ drivers/usb/host/ehci-atmel.c                  | 1 +
+ drivers/usb/host/ehci-dbg.c                    | 1 +
+ drivers/usb/host/ehci-exynos.c                 | 1 +
+ drivers/usb/host/ehci-fsl.c                    | 1 +
+ drivers/usb/host/ehci-fsl.h                    | 1 +
+ drivers/usb/host/ehci-grlib.c                  | 1 +
+ drivers/usb/host/ehci-hcd.c                    | 1 +
+ drivers/usb/host/ehci-hub.c                    | 1 +
+ drivers/usb/host/ehci-mem.c                    | 1 +
+ drivers/usb/host/ehci-mv.c                     | 1 +
+ drivers/usb/host/ehci-mxc.c                    | 1 +
+ drivers/usb/host/ehci-omap.c                   | 1 +
+ drivers/usb/host/ehci-orion.c                  | 1 +
+ drivers/usb/host/ehci-pci.c                    | 1 +
+ drivers/usb/host/ehci-platform.c               | 1 +
+ drivers/usb/host/ehci-pmcmsp.c                 | 1 +
+ drivers/usb/host/ehci-ppc-of.c                 | 1 +
+ drivers/usb/host/ehci-ps3.c                    | 1 +
+ drivers/usb/host/ehci-q.c                      | 1 +
+ drivers/usb/host/ehci-sched.c                  | 1 +
+ drivers/usb/host/ehci-sh.c                     | 1 +
+ drivers/usb/host/ehci-spear.c                  | 1 +
+ drivers/usb/host/ehci-st.c                     | 1 +
+ drivers/usb/host/ehci-sysfs.c                  | 1 +
+ drivers/usb/host/ehci-tegra.c                  | 1 +
+ drivers/usb/host/ehci-tilegx.c                 | 1 +
+ drivers/usb/host/ehci-timer.c                  | 1 +
+ drivers/usb/host/ehci-w90x900.c                | 1 +
+ drivers/usb/host/ehci-xilinx-of.c              | 1 +
+ drivers/usb/host/ehci.h                        | 1 +
+ drivers/usb/host/fhci-dbg.c                    | 1 +
+ drivers/usb/host/fhci-hcd.c                    | 1 +
+ drivers/usb/host/fhci-hub.c                    | 1 +
+ drivers/usb/host/fhci-mem.c                    | 1 +
+ drivers/usb/host/fhci-q.c                      | 1 +
+ drivers/usb/host/fhci-sched.c                  | 1 +
+ drivers/usb/host/fhci-tds.c                    | 1 +
+ drivers/usb/host/fhci.h                        | 1 +
+ drivers/usb/host/fotg210-hcd.c                 | 1 +
+ drivers/usb/host/fsl-mph-dr-of.c               | 1 +
+ drivers/usb/host/hwa-hc.c                      | 1 +
+ drivers/usb/host/imx21-dbg.c                   | 1 +
+ drivers/usb/host/imx21-hcd.c                   | 1 +
+ drivers/usb/host/imx21-hcd.h                   | 1 +
+ drivers/usb/host/isp116x-hcd.c                 | 1 +
+ drivers/usb/host/isp1362-hcd.c                 | 1 +
+ drivers/usb/host/max3421-hcd.c                 | 1 +
+ drivers/usb/host/ohci-at91.c                   | 1 +
+ drivers/usb/host/ohci-da8xx.c                  | 1 +
+ drivers/usb/host/ohci-dbg.c                    | 1 +
+ drivers/usb/host/ohci-exynos.c                 | 1 +
+ drivers/usb/host/ohci-hcd.c                    | 1 +
+ drivers/usb/host/ohci-hub.c                    | 1 +
+ drivers/usb/host/ohci-mem.c                    | 1 +
+ drivers/usb/host/ohci-nxp.c                    | 1 +
+ drivers/usb/host/ohci-omap.c                   | 1 +
+ drivers/usb/host/ohci-pci.c                    | 1 +
+ drivers/usb/host/ohci-platform.c               | 1 +
+ drivers/usb/host/ohci-ppc-of.c                 | 1 +
+ drivers/usb/host/ohci-ps3.c                    | 1 +
+ drivers/usb/host/ohci-pxa27x.c                 | 1 +
+ drivers/usb/host/ohci-q.c                      | 1 +
+ drivers/usb/host/ohci-s3c2410.c                | 1 +
+ drivers/usb/host/ohci-sa1111.c                 | 1 +
+ drivers/usb/host/ohci-sm501.c                  | 1 +
+ drivers/usb/host/ohci-spear.c                  | 1 +
+ drivers/usb/host/ohci-st.c                     | 1 +
+ drivers/usb/host/ohci-tilegx.c                 | 1 +
+ drivers/usb/host/ohci-tmio.c                   | 1 +
+ drivers/usb/host/ohci.h                        | 1 +
+ drivers/usb/host/oxu210hp-hcd.c                | 1 +
+ drivers/usb/host/pci-quirks.c                  | 1 +
+ drivers/usb/host/r8a66597-hcd.c                | 1 +
+ drivers/usb/host/r8a66597.h                    | 1 +
+ drivers/usb/host/sl811-hcd.c                   | 1 +
+ drivers/usb/host/sl811_cs.c                    | 1 +
+ drivers/usb/host/ssb-hcd.c                     | 1 +
+ drivers/usb/host/u132-hcd.c                    | 1 +
+ drivers/usb/host/uhci-hcd.c                    | 1 +
+ drivers/usb/host/whci/asl.c                    | 1 +
+ drivers/usb/host/whci/debug.c                  | 1 +
+ drivers/usb/host/whci/hcd.c                    | 1 +
+ drivers/usb/host/whci/hw.c                     | 1 +
+ drivers/usb/host/whci/init.c                   | 1 +
+ drivers/usb/host/whci/int.c                    | 1 +
+ drivers/usb/host/whci/pzl.c                    | 1 +
+ drivers/usb/host/whci/qset.c                   | 1 +
+ drivers/usb/host/whci/whcd.h                   | 1 +
+ drivers/usb/host/whci/whci-hc.h                | 1 +
+ drivers/usb/host/whci/wusb.c                   | 1 +
+ drivers/usb/host/xhci-dbg.c                    | 1 +
+ drivers/usb/host/xhci-ext-caps.h               | 1 +
+ drivers/usb/host/xhci-hub.c                    | 1 +
+ drivers/usb/host/xhci-mem.c                    | 1 +
+ drivers/usb/host/xhci-mtk-sch.c                | 1 +
+ drivers/usb/host/xhci-mtk.c                    | 1 +
+ drivers/usb/host/xhci-mtk.h                    | 1 +
+ drivers/usb/host/xhci-mvebu.c                  | 1 +
+ drivers/usb/host/xhci-mvebu.h                  | 1 +
+ drivers/usb/host/xhci-pci.c                    | 1 +
+ drivers/usb/host/xhci-plat.c                   | 1 +
+ drivers/usb/host/xhci-plat.h                   | 1 +
+ drivers/usb/host/xhci-rcar.c                   | 1 +
+ drivers/usb/host/xhci-rcar.h                   | 1 +
+ drivers/usb/host/xhci-ring.c                   | 1 +
+ drivers/usb/host/xhci-tegra.c                  | 1 +
+ drivers/usb/host/xhci-trace.c                  | 1 +
+ drivers/usb/host/xhci-trace.h                  | 1 +
+ drivers/usb/host/xhci.c                        | 1 +
+ drivers/usb/host/xhci.h                        | 1 +
+ drivers/usb/image/mdc800.c                     | 1 +
+ drivers/usb/image/microtek.c                   | 1 +
+ drivers/usb/isp1760/isp1760-core.c             | 1 +
+ drivers/usb/isp1760/isp1760-core.h             | 1 +
+ drivers/usb/isp1760/isp1760-regs.h             | 1 +
+ drivers/usb/isp1760/isp1760-udc.c              | 1 +
+ drivers/usb/isp1760/isp1760-udc.h              | 1 +
+ drivers/usb/misc/adutux.c                      | 1 +
+ drivers/usb/misc/appledisplay.c                | 1 +
+ drivers/usb/misc/chaoskey.c                    | 1 +
+ drivers/usb/misc/cypress_cy7c63.c              | 1 +
+ drivers/usb/misc/cytherm.c                     | 1 +
+ drivers/usb/misc/ehset.c                       | 1 +
+ drivers/usb/misc/emi26.c                       | 1 +
+ drivers/usb/misc/emi62.c                       | 1 +
+ drivers/usb/misc/ezusb.c                       | 1 +
+ drivers/usb/misc/ftdi-elan.c                   | 1 +
+ drivers/usb/misc/idmouse.c                     | 1 +
+ drivers/usb/misc/iowarrior.c                   | 1 +
+ drivers/usb/misc/isight_firmware.c             | 1 +
+ drivers/usb/misc/ldusb.c                       | 1 +
+ drivers/usb/misc/legousbtower.c                | 1 +
+ drivers/usb/misc/lvstest.c                     | 1 +
+ drivers/usb/misc/rio500.c                      | 1 +
+ drivers/usb/misc/rio500_usb.h                  | 1 +
+ drivers/usb/misc/sisusbvga/sisusb.c            | 1 +
+ drivers/usb/misc/sisusbvga/sisusb.h            | 1 +
+ drivers/usb/misc/sisusbvga/sisusb_con.c        | 1 +
+ drivers/usb/misc/sisusbvga/sisusb_init.c       | 1 +
+ drivers/usb/misc/sisusbvga/sisusb_init.h       | 1 +
+ drivers/usb/misc/sisusbvga/sisusb_struct.h     | 1 +
+ drivers/usb/misc/trancevibrator.c              | 1 +
+ drivers/usb/misc/usb251xb.c                    | 1 +
+ drivers/usb/misc/usb3503.c                     | 1 +
+ drivers/usb/misc/usb4604.c                     | 1 +
+ drivers/usb/misc/usb_u132.h                    | 1 +
+ drivers/usb/misc/usblcd.c                      | 1 +
+ drivers/usb/misc/usbsevseg.c                   | 1 +
+ drivers/usb/misc/usbtest.c                     | 1 +
+ drivers/usb/misc/uss720.c                      | 1 +
+ drivers/usb/misc/yurex.c                       | 1 +
+ drivers/usb/mon/mon_main.c                     | 1 +
+ drivers/usb/mtu3/mtu3.h                        | 1 +
+ drivers/usb/mtu3/mtu3_core.c                   | 1 +
+ drivers/usb/mtu3/mtu3_dr.c                     | 1 +
+ drivers/usb/mtu3/mtu3_dr.h                     | 1 +
+ drivers/usb/mtu3/mtu3_gadget.c                 | 1 +
+ drivers/usb/mtu3/mtu3_gadget_ep0.c             | 1 +
+ drivers/usb/mtu3/mtu3_host.c                   | 1 +
+ drivers/usb/mtu3/mtu3_hw_regs.h                | 1 +
+ drivers/usb/mtu3/mtu3_plat.c                   | 1 +
+ drivers/usb/mtu3/mtu3_qmu.c                    | 1 +
+ drivers/usb/mtu3/mtu3_qmu.h                    | 1 +
+ drivers/usb/musb/am35x.c                       | 1 +
+ drivers/usb/musb/blackfin.c                    | 1 +
+ drivers/usb/musb/blackfin.h                    | 1 +
+ drivers/usb/musb/cppi_dma.c                    | 1 +
+ drivers/usb/musb/da8xx.c                       | 1 +
+ drivers/usb/musb/davinci.c                     | 1 +
+ drivers/usb/musb/davinci.h                     | 1 +
+ drivers/usb/musb/jz4740.c                      | 1 +
+ drivers/usb/musb/musb_am335x.c                 | 1 +
+ drivers/usb/musb/musb_core.c                   | 1 +
+ drivers/usb/musb/musb_core.h                   | 1 +
+ drivers/usb/musb/musb_cppi41.c                 | 1 +
+ drivers/usb/musb/musb_debug.h                  | 1 +
+ drivers/usb/musb/musb_debugfs.c                | 1 +
+ drivers/usb/musb/musb_dma.h                    | 1 +
+ drivers/usb/musb/musb_dsps.c                   | 1 +
+ drivers/usb/musb/musb_gadget.c                 | 1 +
+ drivers/usb/musb/musb_gadget.h                 | 1 +
+ drivers/usb/musb/musb_gadget_ep0.c             | 1 +
+ drivers/usb/musb/musb_host.c                   | 1 +
+ drivers/usb/musb/musb_host.h                   | 1 +
+ drivers/usb/musb/musb_io.h                     | 1 +
+ drivers/usb/musb/musb_regs.h                   | 1 +
+ drivers/usb/musb/musb_trace.c                  | 1 +
+ drivers/usb/musb/musb_trace.h                  | 1 +
+ drivers/usb/musb/musb_virthub.c                | 1 +
+ drivers/usb/musb/musbhsdma.c                   | 1 +
+ drivers/usb/musb/musbhsdma.h                   | 1 +
+ drivers/usb/musb/omap2430.c                    | 1 +
+ drivers/usb/musb/omap2430.h                    | 1 +
+ drivers/usb/musb/sunxi.c                       | 1 +
+ drivers/usb/musb/tusb6010.c                    | 1 +
+ drivers/usb/musb/tusb6010.h                    | 1 +
+ drivers/usb/musb/tusb6010_omap.c               | 1 +
+ drivers/usb/musb/ux500.c                       | 1 +
+ drivers/usb/musb/ux500_dma.c                   | 1 +
+ drivers/usb/phy/of.c                           | 1 +
+ drivers/usb/phy/phy-ab8500-usb.c               | 1 +
+ drivers/usb/phy/phy-am335x-control.c           | 1 +
+ drivers/usb/phy/phy-am335x.c                   | 1 +
+ drivers/usb/phy/phy-fsl-usb.c                  | 1 +
+ drivers/usb/phy/phy-fsl-usb.h                  | 1 +
+ drivers/usb/phy/phy-generic.c                  | 1 +
+ drivers/usb/phy/phy-gpio-vbus-usb.c            | 1 +
+ drivers/usb/phy/phy-isp1301-omap.c             | 1 +
+ drivers/usb/phy/phy-isp1301.c                  | 1 +
+ drivers/usb/phy/phy-keystone.c                 | 1 +
+ drivers/usb/phy/phy-mv-usb.c                   | 1 +
+ drivers/usb/phy/phy-mv-usb.h                   | 1 +
+ drivers/usb/phy/phy-mxs-usb.c                  | 1 +
+ drivers/usb/phy/phy-omap-otg.c                 | 1 +
+ drivers/usb/phy/phy-tahvo.c                    | 1 +
+ drivers/usb/phy/phy-tegra-usb.c                | 1 +
+ drivers/usb/phy/phy-twl6030-usb.c              | 1 +
+ drivers/usb/phy/phy-ulpi-viewport.c            | 1 +
+ drivers/usb/phy/phy-ulpi.c                     | 1 +
+ drivers/usb/phy/phy.c                          | 1 +
+ drivers/usb/renesas_usbhs/common.c             | 1 +
+ drivers/usb/renesas_usbhs/common.h             | 1 +
+ drivers/usb/renesas_usbhs/fifo.c               | 1 +
+ drivers/usb/renesas_usbhs/fifo.h               | 1 +
+ drivers/usb/renesas_usbhs/mod.c                | 1 +
+ drivers/usb/renesas_usbhs/mod.h                | 1 +
+ drivers/usb/renesas_usbhs/mod_gadget.c         | 1 +
+ drivers/usb/renesas_usbhs/mod_host.c           | 1 +
+ drivers/usb/renesas_usbhs/pipe.c               | 1 +
+ drivers/usb/renesas_usbhs/pipe.h               | 1 +
+ drivers/usb/renesas_usbhs/rcar2.c              | 1 +
+ drivers/usb/renesas_usbhs/rcar3.c              | 1 +
+ drivers/usb/serial/aircable.c                  | 1 +
+ drivers/usb/serial/ark3116.c                   | 1 +
+ drivers/usb/serial/belkin_sa.c                 | 1 +
+ drivers/usb/serial/belkin_sa.h                 | 1 +
+ drivers/usb/serial/bus.c                       | 1 +
+ drivers/usb/serial/ch341.c                     | 1 +
+ drivers/usb/serial/console.c                   | 1 +
+ drivers/usb/serial/cp210x.c                    | 1 +
+ drivers/usb/serial/cyberjack.c                 | 1 +
+ drivers/usb/serial/cypress_m8.c                | 1 +
+ drivers/usb/serial/digi_acceleport.c           | 1 +
+ drivers/usb/serial/empeg.c                     | 1 +
+ drivers/usb/serial/f81232.c                    | 1 +
+ drivers/usb/serial/f81534.c                    | 1 +
+ drivers/usb/serial/ftdi_sio.c                  | 1 +
+ drivers/usb/serial/garmin_gps.c                | 1 +
+ drivers/usb/serial/generic.c                   | 1 +
+ drivers/usb/serial/io_16654.h                  | 1 +
+ drivers/usb/serial/io_edgeport.c               | 1 +
+ drivers/usb/serial/io_edgeport.h               | 1 +
+ drivers/usb/serial/io_ionsp.h                  | 1 +
+ drivers/usb/serial/io_ti.c                     | 1 +
+ drivers/usb/serial/io_ti.h                     | 1 +
+ drivers/usb/serial/io_usbvend.h                | 1 +
+ drivers/usb/serial/ipaq.c                      | 1 +
+ drivers/usb/serial/ipw.c                       | 1 +
+ drivers/usb/serial/ir-usb.c                    | 1 +
+ drivers/usb/serial/iuu_phoenix.c               | 1 +
+ drivers/usb/serial/iuu_phoenix.h               | 1 +
+ drivers/usb/serial/keyspan.c                   | 1 +
+ drivers/usb/serial/keyspan_pda.c               | 1 +
+ drivers/usb/serial/kl5kusb105.c                | 1 +
+ drivers/usb/serial/kobil_sct.c                 | 1 +
+ drivers/usb/serial/mct_u232.c                  | 1 +
+ drivers/usb/serial/mct_u232.h                  | 1 +
+ drivers/usb/serial/metro-usb.c                 | 1 +
+ drivers/usb/serial/mos7720.c                   | 1 +
+ drivers/usb/serial/mos7840.c                   | 1 +
+ drivers/usb/serial/mxuport.c                   | 1 +
+ drivers/usb/serial/navman.c                    | 1 +
+ drivers/usb/serial/omninet.c                   | 1 +
+ drivers/usb/serial/opticon.c                   | 1 +
+ drivers/usb/serial/option.c                    | 1 +
+ drivers/usb/serial/oti6858.c                   | 1 +
+ drivers/usb/serial/oti6858.h                   | 1 +
+ drivers/usb/serial/pl2303.c                    | 1 +
+ drivers/usb/serial/pl2303.h                    | 1 +
+ drivers/usb/serial/qcaux.c                     | 1 +
+ drivers/usb/serial/qcserial.c                  | 1 +
+ drivers/usb/serial/quatech2.c                  | 1 +
+ drivers/usb/serial/safe_serial.c               | 1 +
+ drivers/usb/serial/sierra.c                    | 1 +
+ drivers/usb/serial/spcp8x5.c                   | 1 +
+ drivers/usb/serial/ssu100.c                    | 1 +
+ drivers/usb/serial/symbolserial.c              | 1 +
+ drivers/usb/serial/ti_usb_3410_5052.c          | 1 +
+ drivers/usb/serial/upd78f0730.c                | 1 +
+ drivers/usb/serial/usb-serial-simple.c         | 1 +
+ drivers/usb/serial/usb-serial.c                | 1 +
+ drivers/usb/serial/usb_debug.c                 | 1 +
+ drivers/usb/serial/usb_wwan.c                  | 1 +
+ drivers/usb/serial/visor.c                     | 1 +
+ drivers/usb/serial/visor.h                     | 1 +
+ drivers/usb/serial/whiteheat.c                 | 1 +
+ drivers/usb/serial/whiteheat.h                 | 1 +
+ drivers/usb/serial/wishbone-serial.c           | 1 +
+ drivers/usb/serial/xsens_mt.c                  | 1 +
+ drivers/usb/storage/alauda.c                   | 1 +
+ drivers/usb/storage/cypress_atacb.c            | 1 +
+ drivers/usb/storage/datafab.c                  | 1 +
+ drivers/usb/storage/debug.c                    | 1 +
+ drivers/usb/storage/debug.h                    | 1 +
+ drivers/usb/storage/ene_ub6250.c               | 1 +
+ drivers/usb/storage/freecom.c                  | 1 +
+ drivers/usb/storage/initializers.c             | 1 +
+ drivers/usb/storage/initializers.h             | 1 +
+ drivers/usb/storage/isd200.c                   | 1 +
+ drivers/usb/storage/jumpshot.c                 | 1 +
+ drivers/usb/storage/karma.c                    | 1 +
+ drivers/usb/storage/onetouch.c                 | 1 +
+ drivers/usb/storage/option_ms.c                | 1 +
+ drivers/usb/storage/protocol.c                 | 1 +
+ drivers/usb/storage/protocol.h                 | 1 +
+ drivers/usb/storage/realtek_cr.c               | 1 +
+ drivers/usb/storage/scsiglue.c                 | 1 +
+ drivers/usb/storage/scsiglue.h                 | 1 +
+ drivers/usb/storage/sddr09.c                   | 1 +
+ drivers/usb/storage/sddr55.c                   | 1 +
+ drivers/usb/storage/shuttle_usbat.c            | 1 +
+ drivers/usb/storage/transport.c                | 1 +
+ drivers/usb/storage/transport.h                | 1 +
+ drivers/usb/storage/uas.c                      | 1 +
+ drivers/usb/storage/unusual_alauda.h           | 1 +
+ drivers/usb/storage/unusual_cypress.h          | 1 +
+ drivers/usb/storage/unusual_datafab.h          | 1 +
+ drivers/usb/storage/unusual_devs.h             | 1 +
+ drivers/usb/storage/unusual_ene_ub6250.h       | 1 +
+ drivers/usb/storage/unusual_freecom.h          | 1 +
+ drivers/usb/storage/unusual_isd200.h           | 1 +
+ drivers/usb/storage/unusual_jumpshot.h         | 1 +
+ drivers/usb/storage/unusual_karma.h            | 1 +
+ drivers/usb/storage/unusual_onetouch.h         | 1 +
+ drivers/usb/storage/unusual_realtek.h          | 1 +
+ drivers/usb/storage/unusual_sddr09.h           | 1 +
+ drivers/usb/storage/unusual_sddr55.h           | 1 +
+ drivers/usb/storage/unusual_uas.h              | 1 +
+ drivers/usb/storage/unusual_usbat.h            | 1 +
+ drivers/usb/storage/usb.c                      | 1 +
+ drivers/usb/storage/usb.h                      | 1 +
+ drivers/usb/storage/usual-tables.c             | 1 +
+ drivers/usb/typec/typec.c                      | 1 +
+ drivers/usb/typec/typec_wcove.c                | 1 +
+ drivers/usb/typec/ucsi/ucsi.c                  | 1 +
+ drivers/usb/typec/ucsi/ucsi_acpi.c             | 1 +
+ drivers/usb/usb-skeleton.c                     | 1 +
+ drivers/usb/usbip/stub.h                       | 1 +
+ drivers/usb/usbip/stub_dev.c                   | 1 +
+ drivers/usb/usbip/stub_main.c                  | 1 +
+ drivers/usb/usbip/stub_rx.c                    | 1 +
+ drivers/usb/usbip/stub_tx.c                    | 1 +
+ drivers/usb/usbip/usbip_common.c               | 1 +
+ drivers/usb/usbip/usbip_common.h               | 1 +
+ drivers/usb/usbip/usbip_event.c                | 1 +
+ drivers/usb/usbip/vhci.h                       | 1 +
+ drivers/usb/usbip/vhci_hcd.c                   | 1 +
+ drivers/usb/usbip/vhci_rx.c                    | 1 +
+ drivers/usb/usbip/vhci_sysfs.c                 | 1 +
+ drivers/usb/usbip/vhci_tx.c                    | 1 +
+ drivers/usb/usbip/vudc.h                       | 1 +
+ drivers/usb/usbip/vudc_dev.c                   | 1 +
+ drivers/usb/usbip/vudc_main.c                  | 1 +
+ drivers/usb/usbip/vudc_rx.c                    | 1 +
+ drivers/usb/usbip/vudc_sysfs.c                 | 1 +
+ drivers/usb/usbip/vudc_transfer.c              | 1 +
+ drivers/usb/usbip/vudc_tx.c                    | 1 +
+ drivers/usb/wusbcore/cbaf.c                    | 1 +
+ drivers/usb/wusbcore/crypto.c                  | 1 +
+ drivers/usb/wusbcore/dev-sysfs.c               | 1 +
+ drivers/usb/wusbcore/devconnect.c              | 1 +
+ drivers/usb/wusbcore/mmc.c                     | 1 +
+ drivers/usb/wusbcore/pal.c                     | 1 +
+ drivers/usb/wusbcore/reservation.c             | 1 +
+ drivers/usb/wusbcore/rh.c                      | 1 +
+ drivers/usb/wusbcore/security.c                | 1 +
+ drivers/usb/wusbcore/wa-hc.c                   | 1 +
+ drivers/usb/wusbcore/wa-hc.h                   | 1 +
+ drivers/usb/wusbcore/wa-nep.c                  | 1 +
+ drivers/usb/wusbcore/wa-rpipe.c                | 1 +
+ drivers/usb/wusbcore/wa-xfer.c                 | 1 +
+ drivers/usb/wusbcore/wusbhc.c                  | 1 +
+ drivers/usb/wusbcore/wusbhc.h                  | 1 +
+ include/linux/usb/association.h                | 1 +
+ include/linux/usb/audio-v2.h                   | 1 +
+ include/linux/usb/audio.h                      | 1 +
+ include/linux/usb/c67x00.h                     | 1 +
+ include/linux/usb/cdc-wdm.h                    | 1 +
+ include/linux/usb/cdc.h                        | 1 +
+ include/linux/usb/cdc_ncm.h                    | 1 +
+ include/linux/usb/composite.h                  | 1 +
+ include/linux/usb/ehci_def.h                   | 1 +
+ include/linux/usb/ehci_pdriver.h               | 1 +
+ include/linux/usb/g_hid.h                      | 1 +
+ include/linux/usb/gadget.h                     | 1 +
+ include/linux/usb/gpio_vbus.h                  | 1 +
+ include/linux/usb/hcd.h                        | 1 +
+ include/linux/usb/input.h                      | 1 +
+ include/linux/usb/isp1301.h                    | 1 +
+ include/linux/usb/m66592.h                     | 1 +
+ include/linux/usb/musb-ux500.h                 | 1 +
+ include/linux/usb/net2280.h                    | 1 +
+ include/linux/usb/of.h                         | 1 +
+ include/linux/usb/ohci_pdriver.h               | 1 +
+ include/linux/usb/otg-fsm.h                    | 1 +
+ include/linux/usb/phy_companion.h              | 1 +
+ include/linux/usb/r8a66597.h                   | 1 +
+ include/linux/usb/renesas_usbhs.h              | 1 +
+ include/linux/usb/rndis_host.h                 | 1 +
+ include/linux/usb/samsung_usb_phy.h            | 1 +
+ include/linux/usb/serial.h                     | 1 +
+ include/linux/usb/storage.h                    | 1 +
+ include/linux/usb/tegra_usb_phy.h              | 1 +
+ include/linux/usb/tilegx.h                     | 1 +
+ include/linux/usb/ulpi.h                       | 1 +
+ include/linux/usb/usb338x.h                    | 1 +
+ include/linux/usb/usbnet.h                     | 1 +
+ include/linux/usb/wusb-wa.h                    | 1 +
+ include/linux/usb/wusb.h                       | 1 +
+ include/linux/usb/xhci-dbgp.h                  | 1 +
+ include/linux/usbdevice_fs.h                   | 1 +
+ 651 files changed, 651 insertions(+)
+
+diff --git a/drivers/usb/atm/cxacru.c b/drivers/usb/atm/cxacru.c
+index 5160a4a966b3..d72ff2ee4a6f 100644
+--- a/drivers/usb/atm/cxacru.c
++++ b/drivers/usb/atm/cxacru.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /******************************************************************************
+  *  cxacru.c  -  driver for USB ADSL modems based on
+  *               Conexant AccessRunner chipset
+diff --git a/drivers/usb/atm/speedtch.c b/drivers/usb/atm/speedtch.c
+index 3676adb40d89..811ec79bf756 100644
+--- a/drivers/usb/atm/speedtch.c
++++ b/drivers/usb/atm/speedtch.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /******************************************************************************
+  *  speedtch.c  -  Alcatel SpeedTouch USB xDSL modem driver
+  *
+diff --git a/drivers/usb/atm/ueagle-atm.c b/drivers/usb/atm/ueagle-atm.c
+index ba7616395db2..ab75690044bb 100644
+--- a/drivers/usb/atm/ueagle-atm.c
++++ b/drivers/usb/atm/ueagle-atm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*-
+  * Copyright (c) 2003, 2004
+  *	Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
+diff --git a/drivers/usb/atm/usbatm.c b/drivers/usb/atm/usbatm.c
+index 8607af758bbd..ce1c57cb413f 100644
+--- a/drivers/usb/atm/usbatm.c
++++ b/drivers/usb/atm/usbatm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /******************************************************************************
+  *  usbatm.c - Generic USB xDSL driver core
+  *
+diff --git a/drivers/usb/atm/usbatm.h b/drivers/usb/atm/usbatm.h
+index f3eecd967a8a..72f9d3b8adb6 100644
+--- a/drivers/usb/atm/usbatm.h
++++ b/drivers/usb/atm/usbatm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /******************************************************************************
+  *  usbatm.h - Generic USB xDSL driver core
+  *
+diff --git a/drivers/usb/atm/xusbatm.c b/drivers/usb/atm/xusbatm.c
+index c73c1ec3005e..7c55032a2c2c 100644
+--- a/drivers/usb/atm/xusbatm.c
++++ b/drivers/usb/atm/xusbatm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /******************************************************************************
+  *  xusbatm.c -	dumb usbatm-based driver for modems initialized in userspace
+  *
+diff --git a/drivers/usb/c67x00/c67x00-drv.c b/drivers/usb/c67x00/c67x00-drv.c
+index 5796c8820514..3e4b46f8aa67 100644
+--- a/drivers/usb/c67x00/c67x00-drv.c
++++ b/drivers/usb/c67x00/c67x00-drv.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00-drv.c: Cypress C67X00 USB Common infrastructure
+  *
+diff --git a/drivers/usb/c67x00/c67x00-hcd.c b/drivers/usb/c67x00/c67x00-hcd.c
+index 30d3f346686e..705c40a0097d 100644
+--- a/drivers/usb/c67x00/c67x00-hcd.c
++++ b/drivers/usb/c67x00/c67x00-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00-hcd.c: Cypress C67X00 USB Host Controller Driver
+  *
+diff --git a/drivers/usb/c67x00/c67x00-hcd.h b/drivers/usb/c67x00/c67x00-hcd.h
+index cf8a455a6403..05ab1ba3b327 100644
+--- a/drivers/usb/c67x00/c67x00-hcd.h
++++ b/drivers/usb/c67x00/c67x00-hcd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00-hcd.h: Cypress C67X00 USB HCD
+  *
+diff --git a/drivers/usb/c67x00/c67x00-ll-hpi.c b/drivers/usb/c67x00/c67x00-ll-hpi.c
+index b58151841e10..285f40aa16bf 100644
+--- a/drivers/usb/c67x00/c67x00-ll-hpi.c
++++ b/drivers/usb/c67x00/c67x00-ll-hpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00-ll-hpi.c: Cypress C67X00 USB Low level interface using HPI
+  *
+diff --git a/drivers/usb/c67x00/c67x00-sched.c b/drivers/usb/c67x00/c67x00-sched.c
+index 7311ed61e99a..d2a96eb457f7 100644
+--- a/drivers/usb/c67x00/c67x00-sched.c
++++ b/drivers/usb/c67x00/c67x00-sched.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00-sched.c: Cypress C67X00 USB Host Controller Driver - TD scheduling
+  *
+diff --git a/drivers/usb/c67x00/c67x00.h b/drivers/usb/c67x00/c67x00.h
+index a26e9ded0f32..31339d7f7a4b 100644
+--- a/drivers/usb/c67x00/c67x00.h
++++ b/drivers/usb/c67x00/c67x00.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * c67x00.h: Cypress C67X00 USB register and field definitions
+  *
+diff --git a/drivers/usb/chipidea/bits.h b/drivers/usb/chipidea/bits.h
+index e462f55c8b99..018a28e2e7d8 100644
+--- a/drivers/usb/chipidea/bits.h
++++ b/drivers/usb/chipidea/bits.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * bits.h - register bits of the ChipIdea USB IP core
+  *
+diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
+index 6743f85b1b7a..fa6dd9d9f5c6 100644
+--- a/drivers/usb/chipidea/ci.h
++++ b/drivers/usb/chipidea/ci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ci.h - common structures, functions, and macros of the ChipIdea driver
+  *
+diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
+index 5f4a8157fad8..9a2f7416ff9e 100644
+--- a/drivers/usb/chipidea/ci_hdrc_imx.c
++++ b/drivers/usb/chipidea/ci_hdrc_imx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2012 Freescale Semiconductor, Inc.
+  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+diff --git a/drivers/usb/chipidea/ci_hdrc_imx.h b/drivers/usb/chipidea/ci_hdrc_imx.h
+index d666c9f036ba..98a8b8c817ff 100644
+--- a/drivers/usb/chipidea/ci_hdrc_imx.h
++++ b/drivers/usb/chipidea/ci_hdrc_imx.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2012 Freescale Semiconductor, Inc.
+  *
+diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c
+index 53f3bf459dd1..eefa9eb6478d 100644
+--- a/drivers/usb/chipidea/ci_hdrc_msm.c
++++ b/drivers/usb/chipidea/ci_hdrc_msm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+  *
+  * This program is free software; you can redistribute it and/or modify
+diff --git a/drivers/usb/chipidea/ci_hdrc_pci.c b/drivers/usb/chipidea/ci_hdrc_pci.c
+index 39414e4b2d81..a9dd661026bf 100644
+--- a/drivers/usb/chipidea/ci_hdrc_pci.c
++++ b/drivers/usb/chipidea/ci_hdrc_pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ci_hdrc_pci.c - MIPS USB IP core family device controller
+  *
+diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c b/drivers/usb/chipidea/ci_hdrc_usb2.c
+index 99425db9ba62..41c5f8b9c0b9 100644
+--- a/drivers/usb/chipidea/ci_hdrc_usb2.c
++++ b/drivers/usb/chipidea/ci_hdrc_usb2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Marvell Technology Group Ltd.
+  *
+diff --git a/drivers/usb/chipidea/ci_hdrc_zevio.c b/drivers/usb/chipidea/ci_hdrc_zevio.c
+index 1264de505527..b8c75304d805 100644
+--- a/drivers/usb/chipidea/ci_hdrc_zevio.c
++++ b/drivers/usb/chipidea/ci_hdrc_zevio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *	Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+  *
+diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
+index 43ea5fb87b9a..708c2eaba81c 100644
+--- a/drivers/usb/chipidea/core.c
++++ b/drivers/usb/chipidea/core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * core.c - ChipIdea USB IP core family device controller
+  *
+diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
+index 18cb8e46262d..a49e8567ac7d 100644
+--- a/drivers/usb/chipidea/host.c
++++ b/drivers/usb/chipidea/host.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * host.c - ChipIdea USB host controller driver
+  *
+diff --git a/drivers/usb/chipidea/otg.c b/drivers/usb/chipidea/otg.c
+index 10236fe71522..ef22fcc63f33 100644
+--- a/drivers/usb/chipidea/otg.c
++++ b/drivers/usb/chipidea/otg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * otg.c - ChipIdea USB IP core OTG driver
+  *
+diff --git a/drivers/usb/chipidea/otg.h b/drivers/usb/chipidea/otg.h
+index 9ecb598e48f0..b8e2415bfa7c 100644
+--- a/drivers/usb/chipidea/otg.h
++++ b/drivers/usb/chipidea/otg.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
+  *
+diff --git a/drivers/usb/chipidea/otg_fsm.c b/drivers/usb/chipidea/otg_fsm.c
+index 5ea0246f650d..485aaa1747e8 100644
+--- a/drivers/usb/chipidea/otg_fsm.c
++++ b/drivers/usb/chipidea/otg_fsm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
+  *
+diff --git a/drivers/usb/chipidea/otg_fsm.h b/drivers/usb/chipidea/otg_fsm.h
+index 6366fe398ba6..08e74aeea21d 100644
+--- a/drivers/usb/chipidea/otg_fsm.h
++++ b/drivers/usb/chipidea/otg_fsm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Freescale Semiconductor, Inc.
+  *
+diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
+index fe8a90543ea3..b575bf171866 100644
+--- a/drivers/usb/chipidea/udc.c
++++ b/drivers/usb/chipidea/udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * udc.c - ChipIdea UDC driver
+  *
+diff --git a/drivers/usb/chipidea/udc.h b/drivers/usb/chipidea/udc.h
+index 2ecd1174d66c..840275342873 100644
+--- a/drivers/usb/chipidea/udc.h
++++ b/drivers/usb/chipidea/udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * udc.h - ChipIdea UDC structures
+  *
+diff --git a/drivers/usb/chipidea/ulpi.c b/drivers/usb/chipidea/ulpi.c
+index 1219583dc1b2..c4e1900b9777 100644
+--- a/drivers/usb/chipidea/ulpi.c
++++ b/drivers/usb/chipidea/ulpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2016 Linaro Ltd.
+  *
+diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
+index 9f4a0185dd60..e3842238adeb 100644
+--- a/drivers/usb/chipidea/usbmisc_imx.c
++++ b/drivers/usb/chipidea/usbmisc_imx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2012 Freescale Semiconductor, Inc.
+  *
+diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
+index f2f31fc16f29..df5affe54b11 100644
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * cdc-acm.c
+  *
+diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c
+index 3e865dbf878c..80529ac4b083 100644
+--- a/drivers/usb/class/cdc-wdm.c
++++ b/drivers/usb/class/cdc-wdm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * cdc-wdm.c
+  *
+diff --git a/drivers/usb/class/usblp.c b/drivers/usb/class/usblp.c
+index fb87c17ed6fa..af771fa25800 100644
+--- a/drivers/usb/class/usblp.c
++++ b/drivers/usb/class/usblp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * usblp.c
+  *
+diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c
+index 6ebfabfa0dc7..c2f1e3f9946d 100644
+--- a/drivers/usb/class/usbtmc.c
++++ b/drivers/usb/class/usbtmc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /**
+  * drivers/usb/class/usbtmc.c - USB Test & Measurement class driver
+  *
+diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
+index 552ff7ac5a6b..2b45b0517b3d 100644
+--- a/drivers/usb/common/common.c
++++ b/drivers/usb/common/common.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Provides code common for host and device side USB.
+  *
+diff --git a/drivers/usb/common/led.c b/drivers/usb/common/led.c
+index df23da00a901..fd5538c8e067 100644
+--- a/drivers/usb/common/led.c
++++ b/drivers/usb/common/led.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * LED Triggers for USB Activity
+  *
+diff --git a/drivers/usb/common/ulpi.c b/drivers/usb/common/ulpi.c
+index e02acfb1ca95..315724ee9f07 100644
+--- a/drivers/usb/common/ulpi.c
++++ b/drivers/usb/common/ulpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * ulpi.c - USB ULPI PHY bus
+  *
+diff --git a/drivers/usb/common/usb-otg-fsm.c b/drivers/usb/common/usb-otg-fsm.c
+index b8fe31e409a5..f960d5374ee0 100644
+--- a/drivers/usb/common/usb-otg-fsm.c
++++ b/drivers/usb/common/usb-otg-fsm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * OTG Finite State Machine from OTG spec
+  *
+diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c
+index 55dea2e7828f..1c8b6faa7e66 100644
+--- a/drivers/usb/core/devices.c
++++ b/drivers/usb/core/devices.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * devices.c
+  * (C) Copyright 1999 Randy Dunlap.
+diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
+index ab245352f102..85e1d230499f 100644
+--- a/drivers/usb/core/devio.c
++++ b/drivers/usb/core/devio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*****************************************************************************/
+ 
+ /*
+diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
+index ea829ad798c0..07d5919ccae1 100644
+--- a/drivers/usb/core/hcd-pci.c
++++ b/drivers/usb/core/hcd-pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * (C) Copyright David Brownell 2000-2002
+  *
+diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
+index d0b2e0ed9bab..9fa30a6ada6e 100644
+--- a/drivers/usb/core/hcd.c
++++ b/drivers/usb/core/hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * (C) Copyright Linus Torvalds 1999
+  * (C) Copyright Johannes Erdfelt 1999-2001
+diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
+index 34c1a7e22aae..7d29bf3f095b 100644
+--- a/drivers/usb/core/hub.h
++++ b/drivers/usb/core/hub.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * usb hub driver head file
+  *
+diff --git a/drivers/usb/core/ledtrig-usbport.c b/drivers/usb/core/ledtrig-usbport.c
+index 2de0444c95a8..68cebddde0b8 100644
+--- a/drivers/usb/core/ledtrig-usbport.c
++++ b/drivers/usb/core/ledtrig-usbport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB port LED trigger
+  *
+diff --git a/drivers/usb/core/of.c b/drivers/usb/core/of.c
+index 3863bb1ce8c5..a95416d28aa6 100644
+--- a/drivers/usb/core/of.c
++++ b/drivers/usb/core/of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * of.c		The helpers for hcd device tree support
+  *
+diff --git a/drivers/usb/core/otg_whitelist.h b/drivers/usb/core/otg_whitelist.h
+index 085049d37d7a..4629f6e93954 100644
+--- a/drivers/usb/core/otg_whitelist.h
++++ b/drivers/usb/core/otg_whitelist.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * drivers/usb/core/otg_whitelist.h
+  *
+diff --git a/drivers/usb/core/port.c b/drivers/usb/core/port.c
+index 460c855be0d0..bd757a951a18 100644
+--- a/drivers/usb/core/port.c
++++ b/drivers/usb/core/port.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * usb port device code
+  *
+diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
+index 99f67764765f..bfd913ab5d7d 100644
+--- a/drivers/usb/core/quirks.c
++++ b/drivers/usb/core/quirks.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB device quirk handling logic and table
+  *
+diff --git a/drivers/usb/core/usb-acpi.c b/drivers/usb/core/usb-acpi.c
+index ef9cf4a21afe..90afee5079dc 100644
+--- a/drivers/usb/core/usb-acpi.c
++++ b/drivers/usb/core/usb-acpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB-ACPI glue code
+  *
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index 1b6612c2cdda..82a7d98c3436 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * core.c - DesignWare HS OTG Controller common routines
+  *
+diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
+index 3c0d386dc62f..70cea7441650 100644
+--- a/drivers/usb/dwc2/core.h
++++ b/drivers/usb/dwc2/core.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * core.h - DesignWare HS OTG Controller common declarations
+  *
+diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
+index b8bcb007c92a..ab3fa1630853 100644
+--- a/drivers/usb/dwc2/core_intr.c
++++ b/drivers/usb/dwc2/core_intr.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * core_intr.c - DesignWare HS OTG Controller common interrupt handling
+  *
+diff --git a/drivers/usb/dwc2/debug.h b/drivers/usb/dwc2/debug.h
+index 8222783e6822..7e2442bcbb2e 100644
+--- a/drivers/usb/dwc2/debug.h
++++ b/drivers/usb/dwc2/debug.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * debug.h - Designware USB2 DRD controller debug header
+  *
+diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
+index 794b959a7c8c..c6492cca872f 100644
+--- a/drivers/usb/dwc2/debugfs.c
++++ b/drivers/usb/dwc2/debugfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * debugfs.c - Designware USB2 DRD controller debugfs
+  *
+diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
+index e164439b2154..83c413511b17 100644
+--- a/drivers/usb/dwc2/gadget.c
++++ b/drivers/usb/dwc2/gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+  *		http://www.samsung.com
+diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
+index fa20ec43a187..32ccdb9c7f78 100644
+--- a/drivers/usb/dwc2/hcd.c
++++ b/drivers/usb/dwc2/hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hcd.c - DesignWare HS OTG Controller host-mode routines
+  *
+diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
+index 461bdc67df6f..72e9bb4981f5 100644
+--- a/drivers/usb/dwc2/hcd.h
++++ b/drivers/usb/dwc2/hcd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hcd.h - DesignWare HS OTG Controller host-mode declarations
+  *
+diff --git a/drivers/usb/dwc2/hcd_ddma.c b/drivers/usb/dwc2/hcd_ddma.c
+index b8bdf545c3a7..28c8898b3b66 100644
+--- a/drivers/usb/dwc2/hcd_ddma.c
++++ b/drivers/usb/dwc2/hcd_ddma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hcd_ddma.c - DesignWare HS OTG Controller descriptor DMA routines
+  *
+diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
+index 17905ba1139c..4e462a30fbc9 100644
+--- a/drivers/usb/dwc2/hcd_intr.c
++++ b/drivers/usb/dwc2/hcd_intr.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
+  *
+diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
+index 56e61220efc6..2a915c5adfdb 100644
+--- a/drivers/usb/dwc2/hcd_queue.c
++++ b/drivers/usb/dwc2/hcd_queue.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
+  *
+diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
+index 4592012c4743..2c906d8ee465 100644
+--- a/drivers/usb/dwc2/hw.h
++++ b/drivers/usb/dwc2/hw.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * hw.h - DesignWare HS OTG Controller hardware definitions
+  *
+diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
+index a3ffe97170ff..a0aa0c7cf645 100644
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright (C) 2004-2016 Synopsys, Inc.
+  *
+diff --git a/drivers/usb/dwc2/pci.c b/drivers/usb/dwc2/pci.c
+index fdeb8c7bf30a..3ecc951a1aea 100644
+--- a/drivers/usb/dwc2/pci.c
++++ b/drivers/usb/dwc2/pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * pci.c - DesignWare HS OTG Controller PCI driver
+  *
+diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
+index daf0d37acb37..3e26550d13dd 100644
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * platform.c - DesignWare HS OTG Controller platform driver
+  *
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 8b323a360e03..0855c26d2649 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * core.c - DesignWare USB3 DRD Controller Core file
+  *
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+index abd1142c9e4d..371dc5140bae 100644
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * core.h - DesignWare USB3 DRD Core Header
+  *
+diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
+index 5e9c070ec874..2778d2d1e9b6 100644
+--- a/drivers/usb/dwc3/debug.h
++++ b/drivers/usb/dwc3/debug.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * debug.h - DesignWare USB3 DRD Controller Debug Header
+  *
+diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
+index 4e09be80e59f..b104a8786896 100644
+--- a/drivers/usb/dwc3/debugfs.c
++++ b/drivers/usb/dwc3/debugfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * debugfs.c - DesignWare USB3 DRD Controller DebugFS file
+  *
+diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
+index 2765c51c7ef5..a7e6803ba2e1 100644
+--- a/drivers/usb/dwc3/drd.c
++++ b/drivers/usb/dwc3/drd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * drd.c - DesignWare USB3 DRD Controller Dual-role support
+  *
+diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
+index e089df72f766..24294c3e3c9b 100644
+--- a/drivers/usb/dwc3/dwc3-exynos.c
++++ b/drivers/usb/dwc3/dwc3-exynos.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * dwc3-exynos.c - Samsung EXYNOS DWC3 Specific Glue layer
+  *
+diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c
+index d2ed9523e77c..7310646aec33 100644
+--- a/drivers/usb/dwc3/dwc3-keystone.c
++++ b/drivers/usb/dwc3/dwc3-keystone.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * dwc3-keystone.c - Keystone Specific Glue layer
+  *
+diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
+index acf41ba3638d..5257d8b60bfa 100644
+--- a/drivers/usb/dwc3/dwc3-of-simple.c
++++ b/drivers/usb/dwc3/dwc3-of-simple.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * dwc3-of-simple.c - OF glue layer for simple integrations
+  *
+diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
+index fdd0d5aa1f5e..4eb197f90b3a 100644
+--- a/drivers/usb/dwc3/dwc3-omap.c
++++ b/drivers/usb/dwc3/dwc3-omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * dwc3-omap.c - OMAP Specific Glue layer
+  *
+diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
+index 09c0454833ad..b0a1463c659a 100644
+--- a/drivers/usb/dwc3/dwc3-pci.c
++++ b/drivers/usb/dwc3/dwc3-pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * dwc3-pci.c - PCI Specific glue layer
+  *
+diff --git a/drivers/usb/dwc3/dwc3-st.c b/drivers/usb/dwc3/dwc3-st.c
+index 505676fd3ba4..3d635df22568 100644
+--- a/drivers/usb/dwc3/dwc3-st.c
++++ b/drivers/usb/dwc3/dwc3-st.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /**
+  * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
+  *
+diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
+index 89fe53c846ef..09973b017e01 100644
+--- a/drivers/usb/dwc3/ep0.c
++++ b/drivers/usb/dwc3/ep0.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
+  *
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index d7fae66a0681..021ec29890b8 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
+  *
+diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
+index 4a3227543255..fe502e542c39 100644
+--- a/drivers/usb/dwc3/gadget.h
++++ b/drivers/usb/dwc3/gadget.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * gadget.h - DesignWare USB3 DRD Gadget Header
+  *
+diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
+index 76f0b0df37c1..8eddbe17e99e 100644
+--- a/drivers/usb/dwc3/host.c
++++ b/drivers/usb/dwc3/host.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * host.c - DesignWare USB3 DRD Controller Host Glue
+  *
+diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
+index c69b06696824..085db0412ce0 100644
+--- a/drivers/usb/dwc3/io.h
++++ b/drivers/usb/dwc3/io.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * io.h - DesignWare USB3 DRD IO Header
+  *
+diff --git a/drivers/usb/dwc3/trace.c b/drivers/usb/dwc3/trace.c
+index 6cd166412ad0..31acdc3ce436 100644
+--- a/drivers/usb/dwc3/trace.c
++++ b/drivers/usb/dwc3/trace.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * trace.c - DesignWare USB3 DRD Controller Trace Support
+  *
+diff --git a/drivers/usb/dwc3/trace.h b/drivers/usb/dwc3/trace.h
+index 6504b116da04..9e6e10b2ea5c 100644
+--- a/drivers/usb/dwc3/trace.h
++++ b/drivers/usb/dwc3/trace.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * trace.h - DesignWare USB3 DRD Controller Trace Support
+  *
+diff --git a/drivers/usb/dwc3/ulpi.c b/drivers/usb/dwc3/ulpi.c
+index e87ce8e9edee..5a6edbfc9e88 100644
+--- a/drivers/usb/dwc3/ulpi.c
++++ b/drivers/usb/dwc3/ulpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
+  *
+diff --git a/drivers/usb/early/ehci-dbgp.c b/drivers/usb/early/ehci-dbgp.c
+index e2654443e8eb..d633c2abe5a4 100644
+--- a/drivers/usb/early/ehci-dbgp.c
++++ b/drivers/usb/early/ehci-dbgp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Standalone EHCI usb debug driver
+  *
+diff --git a/drivers/usb/early/xhci-dbc.c b/drivers/usb/early/xhci-dbc.c
+index 12fe70beae69..6901a08a6866 100644
+--- a/drivers/usb/early/xhci-dbc.c
++++ b/drivers/usb/early/xhci-dbc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * xhci-dbc.c - xHCI debug capability early driver
+  *
+diff --git a/drivers/usb/early/xhci-dbc.h b/drivers/usb/early/xhci-dbc.h
+index a516cab0bf4a..1107ef5f2ebd 100644
+--- a/drivers/usb/early/xhci-dbc.h
++++ b/drivers/usb/early/xhci-dbc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xhci-dbc.h - xHCI debug capability early driver
+  *
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index b805962f5154..cde9f6c6ba45 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * composite.c - infrastructure for Composite USB Gadgets
+  *
+diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c
+index 17a6077b89a4..80a75c038696 100644
+--- a/drivers/usb/gadget/config.c
++++ b/drivers/usb/gadget/config.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * usb/gadget/config.c -- simplify building config descriptors
+  *
+diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
+index aeb9f3c40521..4ddf063b9f47 100644
+--- a/drivers/usb/gadget/configfs.c
++++ b/drivers/usb/gadget/configfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/configfs.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
+diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
+index 30fdab0ae383..3a3b3027f234 100644
+--- a/drivers/usb/gadget/epautoconf.c
++++ b/drivers/usb/gadget/epautoconf.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * epautoconf.c -- endpoint autoconfiguration for usb gadget drivers
+  *
+diff --git a/drivers/usb/gadget/function/f_acm.c b/drivers/usb/gadget/function/f_acm.c
+index 5e3828d9dac7..5a2229784bd6 100644
+--- a/drivers/usb/gadget/function/f_acm.c
++++ b/drivers/usb/gadget/function/f_acm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_acm.c -- USB CDC serial (ACM) function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index 4c488d15b6f6..d2a83dd78cb9 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_ecm.c -- USB CDC Ethernet (ECM) link function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_eem.c b/drivers/usb/gadget/function/f_eem.c
+index 007ec6e4a5d4..bfb4cacc8b8e 100644
+--- a/drivers/usb/gadget/function/f_eem.c
++++ b/drivers/usb/gadget/function/f_eem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_eem.c -- USB CDC Ethernet (EEM) link function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c
+index 17467545391b..3910c1cda7a5 100644
+--- a/drivers/usb/gadget/function/f_fs.c
++++ b/drivers/usb/gadget/function/f_fs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_fs.c -- user mode file system API for USB composite function controllers
+  *
+diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c
+index d8e359ef6eb1..fc1d9282c1d9 100644
+--- a/drivers/usb/gadget/function/f_hid.c
++++ b/drivers/usb/gadget/function/f_hid.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_hid.c -- USB HID function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_loopback.c b/drivers/usb/gadget/function/f_loopback.c
+index e70093835e14..2dea6e63ef4d 100644
+--- a/drivers/usb/gadget/function/f_loopback.c
++++ b/drivers/usb/gadget/function/f_loopback.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_loopback.c - USB peripheral loopback configuration driver
+  *
+diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c
+index 5153e29870c3..697224237976 100644
+--- a/drivers/usb/gadget/function/f_mass_storage.c
++++ b/drivers/usb/gadget/function/f_mass_storage.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * f_mass_storage.c -- Mass Storage USB Composite Function
+  *
+diff --git a/drivers/usb/gadget/function/f_midi.c b/drivers/usb/gadget/function/f_midi.c
+index 71cf552b8828..8e43a6459c73 100644
+--- a/drivers/usb/gadget/function/f_midi.c
++++ b/drivers/usb/gadget/function/f_midi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_midi.c -- USB MIDI class function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 45b334ceaf2e..a45e6174a387 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_ncm.c -- USB CDC Network (NCM) link function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_obex.c b/drivers/usb/gadget/function/f_obex.c
+index d43e86cea74f..34e81d888b24 100644
+--- a/drivers/usb/gadget/function/f_obex.c
++++ b/drivers/usb/gadget/function/f_obex.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_obex.c -- USB CDC OBEX function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_phonet.c b/drivers/usb/gadget/function/f_phonet.c
+index 9c4c58e4a1a2..1dc3aa62223d 100644
+--- a/drivers/usb/gadget/function/f_phonet.c
++++ b/drivers/usb/gadget/function/f_phonet.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * f_phonet.c -- USB CDC Phonet function
+  *
+diff --git a/drivers/usb/gadget/function/f_printer.c b/drivers/usb/gadget/function/f_printer.c
+index e6d4fa5eeff1..7e8da6af745e 100644
+--- a/drivers/usb/gadget/function/f_printer.c
++++ b/drivers/usb/gadget/function/f_printer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_printer.c - USB printer function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c
+index c7c5b3ce1d98..355e2308bd7a 100644
+--- a/drivers/usb/gadget/function/f_rndis.c
++++ b/drivers/usb/gadget/function/f_rndis.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_rndis.c -- RNDIS link function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_serial.c b/drivers/usb/gadget/function/f_serial.c
+index cb00ada21d9c..9dae136d81e4 100644
+--- a/drivers/usb/gadget/function/f_serial.c
++++ b/drivers/usb/gadget/function/f_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_serial.c - generic USB serial function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_sourcesink.c b/drivers/usb/gadget/function/f_sourcesink.c
+index 8784fa12ea2c..4581b172ced7 100644
+--- a/drivers/usb/gadget/function/f_sourcesink.c
++++ b/drivers/usb/gadget/function/f_sourcesink.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_sourcesink.c - USB peripheral source/sink configuration driver
+  *
+diff --git a/drivers/usb/gadget/function/f_subset.c b/drivers/usb/gadget/function/f_subset.c
+index 434b983f3b4c..8e13415cf91e 100644
+--- a/drivers/usb/gadget/function/f_subset.c
++++ b/drivers/usb/gadget/function/f_subset.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_subset.c -- "CDC Subset" Ethernet link function driver
+  *
+diff --git a/drivers/usb/gadget/function/f_tcm.c b/drivers/usb/gadget/function/f_tcm.c
+index a82e2bd5ea34..5f2890902270 100644
+--- a/drivers/usb/gadget/function/f_tcm.c
++++ b/drivers/usb/gadget/function/f_tcm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* Target based USB-Gadget
+  *
+  * UAS protocol handling, target callbacks, configfs handling,
+diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c
+index 29efbedc91f9..9dc33cbcc06c 100644
+--- a/drivers/usb/gadget/function/f_uac1.c
++++ b/drivers/usb/gadget/function/f_uac1.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_uac1.c -- USB Audio Class 1.0 Function (using u_audio API)
+  *
+diff --git a/drivers/usb/gadget/function/f_uac1_legacy.c b/drivers/usb/gadget/function/f_uac1_legacy.c
+index 5d229e72912e..83d33ee3c40a 100644
+--- a/drivers/usb/gadget/function/f_uac1_legacy.c
++++ b/drivers/usb/gadget/function/f_uac1_legacy.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_audio.c -- USB Audio class function driver
+   *
+diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c
+index d063f0401f84..c64662849e79 100644
+--- a/drivers/usb/gadget/function/f_uac2.c
++++ b/drivers/usb/gadget/function/f_uac2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * f_uac2.c -- USB Audio Class 2.0 Function
+  *
+diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c
+index f8a1881609a2..67af76361e7f 100644
+--- a/drivers/usb/gadget/function/f_uvc.c
++++ b/drivers/usb/gadget/function/f_uvc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	uvc_gadget.c  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/f_uvc.h b/drivers/usb/gadget/function/f_uvc.h
+index d0a73bdcbba1..b78d1af0aa9c 100644
+--- a/drivers/usb/gadget/function/f_uvc.h
++++ b/drivers/usb/gadget/function/f_uvc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	f_uvc.h  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/rndis.c b/drivers/usb/gadget/function/rndis.c
+index d6341045c631..ac8a5476d968 100644
+--- a/drivers/usb/gadget/function/rndis.c
++++ b/drivers/usb/gadget/function/rndis.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * RNDIS MSG parser
+  *
+diff --git a/drivers/usb/gadget/function/rndis.h b/drivers/usb/gadget/function/rndis.h
+index 21e0430ffb98..f3bbd224cc16 100644
+--- a/drivers/usb/gadget/function/rndis.h
++++ b/drivers/usb/gadget/function/rndis.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * RNDIS	Definitions for Remote NDIS
+  *
+diff --git a/drivers/usb/gadget/function/storage_common.c b/drivers/usb/gadget/function/storage_common.c
+index 8fbf6861690d..1beb7ce507ce 100644
+--- a/drivers/usb/gadget/function/storage_common.c
++++ b/drivers/usb/gadget/function/storage_common.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * storage_common.c -- Common definitions for mass storage functionality
+  *
+diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c
+index d3a639297e06..f21bede8cf90 100644
+--- a/drivers/usb/gadget/function/u_audio.c
++++ b/drivers/usb/gadget/function/u_audio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_audio.c -- interface to USB gadget "ALSA sound card" utilities
+  *
+diff --git a/drivers/usb/gadget/function/u_audio.h b/drivers/usb/gadget/function/u_audio.h
+index 07e13784cbb8..fae06fa2ef5d 100644
+--- a/drivers/usb/gadget/function/u_audio.h
++++ b/drivers/usb/gadget/function/u_audio.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_audio.h -- interface to USB gadget "ALSA sound card" utilities
+  *
+diff --git a/drivers/usb/gadget/function/u_ecm.h b/drivers/usb/gadget/function/u_ecm.h
+index 262cc03cc2c0..320cd890bb0e 100644
+--- a/drivers/usb/gadget/function/u_ecm.h
++++ b/drivers/usb/gadget/function/u_ecm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_ecm.h
+  *
+diff --git a/drivers/usb/gadget/function/u_eem.h b/drivers/usb/gadget/function/u_eem.h
+index e3ae97874c4f..b756664f9c5e 100644
+--- a/drivers/usb/gadget/function/u_eem.h
++++ b/drivers/usb/gadget/function/u_eem.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_eem.h
+  *
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index bdbc3fdc7c4f..247eb69cb99b 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_ether.c -- Ethernet-over-USB link layer utilities for Gadget stack
+  *
+diff --git a/drivers/usb/gadget/function/u_ether.h b/drivers/usb/gadget/function/u_ether.h
+index c77145bd6b5b..015084eda722 100644
+--- a/drivers/usb/gadget/function/u_ether.h
++++ b/drivers/usb/gadget/function/u_ether.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_ether.h -- interface to USB gadget "ethernet link" utilities
+  *
+diff --git a/drivers/usb/gadget/function/u_ether_configfs.h b/drivers/usb/gadget/function/u_ether_configfs.h
+index e4c3f84af4c3..0f303fc288fa 100644
+--- a/drivers/usb/gadget/function/u_ether_configfs.h
++++ b/drivers/usb/gadget/function/u_ether_configfs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_ether_configfs.h
+  *
+diff --git a/drivers/usb/gadget/function/u_fs.h b/drivers/usb/gadget/function/u_fs.h
+index 79f70ebf85dc..79a585ce51c1 100644
+--- a/drivers/usb/gadget/function/u_fs.h
++++ b/drivers/usb/gadget/function/u_fs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_fs.h
+  *
+diff --git a/drivers/usb/gadget/function/u_gether.h b/drivers/usb/gadget/function/u_gether.h
+index d4078426ba5d..b9643d83b5cc 100644
+--- a/drivers/usb/gadget/function/u_gether.h
++++ b/drivers/usb/gadget/function/u_gether.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_gether.h
+  *
+diff --git a/drivers/usb/gadget/function/u_hid.h b/drivers/usb/gadget/function/u_hid.h
+index aaa0e368a159..5c9cae57b41a 100644
+--- a/drivers/usb/gadget/function/u_hid.h
++++ b/drivers/usb/gadget/function/u_hid.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_hid.h
+  *
+diff --git a/drivers/usb/gadget/function/u_midi.h b/drivers/usb/gadget/function/u_midi.h
+index 22510189758e..0b3e14bb9021 100644
+--- a/drivers/usb/gadget/function/u_midi.h
++++ b/drivers/usb/gadget/function/u_midi.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_midi.h
+  *
+diff --git a/drivers/usb/gadget/function/u_ncm.h b/drivers/usb/gadget/function/u_ncm.h
+index ce0f3a78ca13..e90054039f40 100644
+--- a/drivers/usb/gadget/function/u_ncm.h
++++ b/drivers/usb/gadget/function/u_ncm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_ncm.h
+  *
+diff --git a/drivers/usb/gadget/function/u_phonet.h b/drivers/usb/gadget/function/u_phonet.h
+index 98ced18779ea..5387ed46f415 100644
+--- a/drivers/usb/gadget/function/u_phonet.h
++++ b/drivers/usb/gadget/function/u_phonet.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_phonet.h - interface to Phonet
+  *
+diff --git a/drivers/usb/gadget/function/u_printer.h b/drivers/usb/gadget/function/u_printer.h
+index 8d30b7577f87..65737e58259a 100644
+--- a/drivers/usb/gadget/function/u_printer.h
++++ b/drivers/usb/gadget/function/u_printer.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_printer.h
+  *
+diff --git a/drivers/usb/gadget/function/u_rndis.h b/drivers/usb/gadget/function/u_rndis.h
+index efdb7ac381d9..87d365d9cf5d 100644
+--- a/drivers/usb/gadget/function/u_rndis.h
++++ b/drivers/usb/gadget/function/u_rndis.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_rndis.h
+  *
+diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
+index 4176216d54be..b0ab05716f2b 100644
+--- a/drivers/usb/gadget/function/u_serial.c
++++ b/drivers/usb/gadget/function/u_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_serial.c - utilities for USB gadget "serial port"/TTY support
+  *
+diff --git a/drivers/usb/gadget/function/u_serial.h b/drivers/usb/gadget/function/u_serial.h
+index c20210c0babd..44617b205bc7 100644
+--- a/drivers/usb/gadget/function/u_serial.h
++++ b/drivers/usb/gadget/function/u_serial.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_serial.h - interface to USB gadget "serial port"/TTY utilities
+  *
+diff --git a/drivers/usb/gadget/function/u_tcm.h b/drivers/usb/gadget/function/u_tcm.h
+index 0bd751e0483f..1ec6f702d400 100644
+--- a/drivers/usb/gadget/function/u_tcm.h
++++ b/drivers/usb/gadget/function/u_tcm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_tcm.h
+  *
+diff --git a/drivers/usb/gadget/function/u_uac1.h b/drivers/usb/gadget/function/u_uac1.h
+index 6f188fd8633f..84e05cc42659 100644
+--- a/drivers/usb/gadget/function/u_uac1.h
++++ b/drivers/usb/gadget/function/u_uac1.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_uac1.h - Utility definitions for UAC1 function
+  *
+diff --git a/drivers/usb/gadget/function/u_uac1_legacy.c b/drivers/usb/gadget/function/u_uac1_legacy.c
+index fa4684a1c54c..0f66c4b4f772 100644
+--- a/drivers/usb/gadget/function/u_uac1_legacy.c
++++ b/drivers/usb/gadget/function/u_uac1_legacy.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_uac1.c -- ALSA audio utilities for Gadget stack
+  *
+diff --git a/drivers/usb/gadget/function/u_uac1_legacy.h b/drivers/usb/gadget/function/u_uac1_legacy.h
+index d715b1af56a4..ad77043567cd 100644
+--- a/drivers/usb/gadget/function/u_uac1_legacy.h
++++ b/drivers/usb/gadget/function/u_uac1_legacy.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * u_uac1.h -- interface to USB gadget "ALSA AUDIO" utilities
+  *
+diff --git a/drivers/usb/gadget/function/u_uac2.h b/drivers/usb/gadget/function/u_uac2.h
+index 19eeb83538a5..6ad31b29df8a 100644
+--- a/drivers/usb/gadget/function/u_uac2.h
++++ b/drivers/usb/gadget/function/u_uac2.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_uac2.h
+  *
+diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h
+index 4676b60a5063..ec5b5e6839b3 100644
+--- a/drivers/usb/gadget/function/u_uvc.h
++++ b/drivers/usb/gadget/function/u_uvc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_uvc.h
+  *
+diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h
+index 11d70dead32b..f6388ddad19f 100644
+--- a/drivers/usb/gadget/function/uvc.h
++++ b/drivers/usb/gadget/function/uvc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	uvc_gadget.h  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c
+index 844cb738bafd..66f1312d50e7 100644
+--- a/drivers/usb/gadget/function/uvc_configfs.c
++++ b/drivers/usb/gadget/function/uvc_configfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * uvc_configfs.c
+  *
+diff --git a/drivers/usb/gadget/function/uvc_configfs.h b/drivers/usb/gadget/function/uvc_configfs.h
+index 085e67be7c71..f604bcb241ea 100644
+--- a/drivers/usb/gadget/function/uvc_configfs.h
++++ b/drivers/usb/gadget/function/uvc_configfs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * uvc_configfs.h
+  *
+diff --git a/drivers/usb/gadget/function/uvc_queue.c b/drivers/usb/gadget/function/uvc_queue.c
+index 6377e9fee6e5..6c819d9fa7af 100644
+--- a/drivers/usb/gadget/function/uvc_queue.c
++++ b/drivers/usb/gadget/function/uvc_queue.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	uvc_queue.c  --  USB Video Class driver - Buffers management
+  *
+diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c
+index 3e22b45687d3..207df9e51d34 100644
+--- a/drivers/usb/gadget/function/uvc_v4l2.c
++++ b/drivers/usb/gadget/function/uvc_v4l2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	uvc_v4l2.c  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/uvc_v4l2.h b/drivers/usb/gadget/function/uvc_v4l2.h
+index 2683b92fda65..0b3a2a88799d 100644
+--- a/drivers/usb/gadget/function/uvc_v4l2.h
++++ b/drivers/usb/gadget/function/uvc_v4l2.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *	uvc_v4l2.h  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c
+index 0f01c04d7cbd..29d81ac02391 100644
+--- a/drivers/usb/gadget/function/uvc_video.c
++++ b/drivers/usb/gadget/function/uvc_video.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	uvc_video.c  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/function/uvc_video.h b/drivers/usb/gadget/function/uvc_video.h
+index ef00f06fa00b..1c48a8bdca02 100644
+--- a/drivers/usb/gadget/function/uvc_video.h
++++ b/drivers/usb/gadget/function/uvc_video.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *	uvc_video.h  --  USB Video Class Gadget driver
+  *
+diff --git a/drivers/usb/gadget/functions.c b/drivers/usb/gadget/functions.c
+index b13f839e7368..203361a64212 100644
+--- a/drivers/usb/gadget/functions.c
++++ b/drivers/usb/gadget/functions.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/kernel.h>
+ #include <linux/slab.h>
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/legacy/acm_ms.c b/drivers/usb/gadget/legacy/acm_ms.c
+index c39de65a448b..eed2cb6483b6 100644
+--- a/drivers/usb/gadget/legacy/acm_ms.c
++++ b/drivers/usb/gadget/legacy/acm_ms.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * acm_ms.c -- Composite driver, with ACM and mass storage support
+  *
+diff --git a/drivers/usb/gadget/legacy/audio.c b/drivers/usb/gadget/legacy/audio.c
+index 1f5cdbe162df..d0bffaa0bc09 100644
+--- a/drivers/usb/gadget/legacy/audio.c
++++ b/drivers/usb/gadget/legacy/audio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * audio.c -- Audio gadget driver
+  *
+diff --git a/drivers/usb/gadget/legacy/cdc2.c b/drivers/usb/gadget/legacy/cdc2.c
+index 51c08682de84..074c0d4efcf9 100644
+--- a/drivers/usb/gadget/legacy/cdc2.c
++++ b/drivers/usb/gadget/legacy/cdc2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * cdc2.c -- CDC Composite driver, with ECM and ACM support
+  *
+diff --git a/drivers/usb/gadget/legacy/dbgp.c b/drivers/usb/gadget/legacy/dbgp.c
+index 99ca3dabc4f3..e1d566c9918a 100644
+--- a/drivers/usb/gadget/legacy/dbgp.c
++++ b/drivers/usb/gadget/legacy/dbgp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * dbgp.c -- EHCI Debug Port device gadget
+  *
+diff --git a/drivers/usb/gadget/legacy/ether.c b/drivers/usb/gadget/legacy/ether.c
+index 25a2c2e48592..8eb0043f6697 100644
+--- a/drivers/usb/gadget/legacy/ether.c
++++ b/drivers/usb/gadget/legacy/ether.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * ether.c -- Ethernet gadget driver, with CDC and non-CDC options
+  *
+diff --git a/drivers/usb/gadget/legacy/g_ffs.c b/drivers/usb/gadget/legacy/g_ffs.c
+index 6da7316f8e87..95db302cec7d 100644
+--- a/drivers/usb/gadget/legacy/g_ffs.c
++++ b/drivers/usb/gadget/legacy/g_ffs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * g_ffs.c -- user mode file system API for USB composite function controllers
+  *
+diff --git a/drivers/usb/gadget/legacy/gmidi.c b/drivers/usb/gadget/legacy/gmidi.c
+index 0bf39c3ccdb1..c03674b02718 100644
+--- a/drivers/usb/gadget/legacy/gmidi.c
++++ b/drivers/usb/gadget/legacy/gmidi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * gmidi.c -- USB MIDI Gadget Driver
+  *
+diff --git a/drivers/usb/gadget/legacy/hid.c b/drivers/usb/gadget/legacy/hid.c
+index a71a884f79fc..c9fb9a3c034f 100644
+--- a/drivers/usb/gadget/legacy/hid.c
++++ b/drivers/usb/gadget/legacy/hid.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * hid.c -- HID Composite driver
+  *
+diff --git a/drivers/usb/gadget/legacy/inode.c b/drivers/usb/gadget/legacy/inode.c
+index 5c28bee327e1..ae4fe683f7e0 100644
+--- a/drivers/usb/gadget/legacy/inode.c
++++ b/drivers/usb/gadget/legacy/inode.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * inode.c -- user mode filesystem api for usb gadget controllers
+  *
+diff --git a/drivers/usb/gadget/legacy/mass_storage.c b/drivers/usb/gadget/legacy/mass_storage.c
+index fcba59782f26..3700cd272d75 100644
+--- a/drivers/usb/gadget/legacy/mass_storage.c
++++ b/drivers/usb/gadget/legacy/mass_storage.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * mass_storage.c -- Mass Storage USB Gadget
+  *
+diff --git a/drivers/usb/gadget/legacy/multi.c b/drivers/usb/gadget/legacy/multi.c
+index a70a406580ea..7dc276c68b54 100644
+--- a/drivers/usb/gadget/legacy/multi.c
++++ b/drivers/usb/gadget/legacy/multi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * multi.c -- Multifunction Composite driver
+  *
+diff --git a/drivers/usb/gadget/legacy/ncm.c b/drivers/usb/gadget/legacy/ncm.c
+index 0aba68253e3d..7bfd306ea1ee 100644
+--- a/drivers/usb/gadget/legacy/ncm.c
++++ b/drivers/usb/gadget/legacy/ncm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * ncm.c -- NCM gadget driver
+  *
+diff --git a/drivers/usb/gadget/legacy/nokia.c b/drivers/usb/gadget/legacy/nokia.c
+index b1e535f4022e..f10dd6e19cc9 100644
+--- a/drivers/usb/gadget/legacy/nokia.c
++++ b/drivers/usb/gadget/legacy/nokia.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * nokia.c -- Nokia Composite Gadget Driver
+  *
+diff --git a/drivers/usb/gadget/legacy/printer.c b/drivers/usb/gadget/legacy/printer.c
+index 4c9cfff34a03..6e1eef41ad86 100644
+--- a/drivers/usb/gadget/legacy/printer.c
++++ b/drivers/usb/gadget/legacy/printer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * printer.c -- Printer gadget driver
+  *
+diff --git a/drivers/usb/gadget/legacy/serial.c b/drivers/usb/gadget/legacy/serial.c
+index 9d89adce756d..e84cb9f97b5d 100644
+--- a/drivers/usb/gadget/legacy/serial.c
++++ b/drivers/usb/gadget/legacy/serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * serial.c -- USB gadget serial driver
+  *
+diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
+index 0b0bb98319cd..1089cb118b66 100644
+--- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c
++++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* Target based USB-Gadget
+  *
+  * UAS protocol handling, target callbacks, configfs handling,
+diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c
+index 82c13fce9232..a3929a38ede9 100644
+--- a/drivers/usb/gadget/legacy/webcam.c
++++ b/drivers/usb/gadget/legacy/webcam.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	webcam.c -- USB webcam gadget driver
+  *
+diff --git a/drivers/usb/gadget/legacy/zero.c b/drivers/usb/gadget/legacy/zero.c
+index d02e2ce73ea5..521f4484ad4d 100644
+--- a/drivers/usb/gadget/legacy/zero.c
++++ b/drivers/usb/gadget/legacy/zero.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * zero.c -- Gadget Zero, for USB development
+  *
+diff --git a/drivers/usb/gadget/u_f.c b/drivers/usb/gadget/u_f.c
+index 18839732c840..f52fb321d266 100644
+--- a/drivers/usb/gadget/u_f.c
++++ b/drivers/usb/gadget/u_f.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_f.c -- USB function utilities for Gadget stack
+  *
+diff --git a/drivers/usb/gadget/u_f.h b/drivers/usb/gadget/u_f.h
+index 2f03334c6874..0fb702c8a250 100644
+--- a/drivers/usb/gadget/u_f.h
++++ b/drivers/usb/gadget/u_f.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_f.h
+  *
+diff --git a/drivers/usb/gadget/u_os_desc.h b/drivers/usb/gadget/u_os_desc.h
+index 947b7ddff691..cfa53a204de1 100644
+--- a/drivers/usb/gadget/u_os_desc.h
++++ b/drivers/usb/gadget/u_os_desc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * u_os_desc.h
+  *
+diff --git a/drivers/usb/gadget/udc/amd5536udc.h b/drivers/usb/gadget/udc/amd5536udc.h
+index 4fe22d432af2..5a92388ef8bb 100644
+--- a/drivers/usb/gadget/udc/amd5536udc.h
++++ b/drivers/usb/gadget/udc/amd5536udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/amd5536udc_pci.c b/drivers/usb/gadget/udc/amd5536udc_pci.c
+index 57a13f080a79..cf9117e84534 100644
+--- a/drivers/usb/gadget/udc/amd5536udc_pci.c
++++ b/drivers/usb/gadget/udc/amd5536udc_pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * amd5536udc_pci.c -- AMD 5536 UDC high/full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/at91_udc.c b/drivers/usb/gadget/udc/at91_udc.c
+index 8bc78418d40e..972f78409df7 100644
+--- a/drivers/usb/gadget/udc/at91_udc.c
++++ b/drivers/usb/gadget/udc/at91_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * at91_udc -- driver for at91-series USB peripheral controller
+  *
+diff --git a/drivers/usb/gadget/udc/at91_udc.h b/drivers/usb/gadget/udc/at91_udc.h
+index 9bbe72764f31..9581a868032e 100644
+--- a/drivers/usb/gadget/udc/at91_udc.h
++++ b/drivers/usb/gadget/udc/at91_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2004 by Thomas Rathbone, HP Labs
+  * Copyright (C) 2005 by Ivan Kokshaysky
+diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
+index a884c022df7a..12543decf9ab 100644
+--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
++++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the Atmel USBA high speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.h b/drivers/usb/gadget/udc/atmel_usba_udc.h
+index f8ebe0389bd4..10df5e4aaeb2 100644
+--- a/drivers/usb/gadget/udc/atmel_usba_udc.h
++++ b/drivers/usb/gadget/udc/atmel_usba_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the Atmel USBA high speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/bcm63xx_udc.c b/drivers/usb/gadget/udc/bcm63xx_udc.c
+index f78503203f42..403cb339fd7b 100644
+--- a/drivers/usb/gadget/udc/bcm63xx_udc.c
++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bcm63xx_udc.c -- BCM63xx UDC high/full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc.h b/drivers/usb/gadget/udc/bdc/bdc.h
+index 6df0352cdc50..960620bccc25 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc.h
++++ b/drivers/usb/gadget/udc/bdc/bdc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc.h - header for the BRCM BDC USB3.0 device controller
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_cmd.c b/drivers/usb/gadget/udc/bdc/bdc_cmd.c
+index 6e920f1dce02..ad3240375f87 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_cmd.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_cmd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_cmd.c - BRCM BDC USB3.0 device controller
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_cmd.h b/drivers/usb/gadget/udc/bdc/bdc_cmd.h
+index 61d0e3bf9853..64648fbef233 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_cmd.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_cmd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_cmd.h - header for the BDC debug functions
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_core.c b/drivers/usb/gadget/udc/bdc/bdc_core.c
+index 7a8af4b916cf..2ab6a6b45f9e 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_core.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_core.c - BRCM BDC USB3.0 device controller core operations
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_dbg.c b/drivers/usb/gadget/udc/bdc/bdc_dbg.c
+index ac98f6f681b7..11216cd6cb94 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_dbg.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_dbg.c - BRCM BDC USB3.0 device controller debug functions
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_dbg.h b/drivers/usb/gadget/udc/bdc/bdc_dbg.h
+index 338a6c701315..f62d59b30a3e 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_dbg.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_dbg.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_dbg.h - header for the BDC debug functions
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.c b/drivers/usb/gadget/udc/bdc/bdc_ep.c
+index bfd8f7ade935..e9fda8e6e87d 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_ep.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_ep.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_ep.c - BRCM BDC USB3.0 device controller endpoint related functions
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.h b/drivers/usb/gadget/udc/bdc/bdc_ep.h
+index 8a6b36cbf2ea..db52fc78c8bf 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_ep.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_ep.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_ep.h - header for the BDC debug functions
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_pci.c b/drivers/usb/gadget/udc/bdc/bdc_pci.c
+index 708e36f530d8..1fec9c4fdadd 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_pci.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_pci.c - BRCM BDC USB3.0 device controller PCI interface file.
+  *
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_udc.c b/drivers/usb/gadget/udc/bdc/bdc_udc.c
+index c84346146456..492b8b872d2c 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_udc.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * bdc_udc.c - BRCM BDC USB3.0 device controller gagdet ops
+  *
+diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
+index ad315c4c6f35..9f928875d411 100644
+--- a/drivers/usb/gadget/udc/core.c
++++ b/drivers/usb/gadget/udc/core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * udc.c - Core UDC Framework
+  *
+diff --git a/drivers/usb/gadget/udc/dummy_hcd.c b/drivers/usb/gadget/udc/dummy_hcd.c
+index f04e91ef9e7c..af3dc1d33683 100644
+--- a/drivers/usb/gadget/udc/dummy_hcd.c
++++ b/drivers/usb/gadget/udc/dummy_hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * dummy_hcd.c -- Dummy/Loopback USB host and device emulator driver.
+  *
+diff --git a/drivers/usb/gadget/udc/fotg210-udc.c b/drivers/usb/gadget/udc/fotg210-udc.c
+index 78d0204e3e20..6a7e0e26a1d1 100644
+--- a/drivers/usb/gadget/udc/fotg210-udc.c
++++ b/drivers/usb/gadget/udc/fotg210-udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FOTG210 UDC Driver supports Bulk transfer so far
+  *
+diff --git a/drivers/usb/gadget/udc/fotg210.h b/drivers/usb/gadget/udc/fotg210.h
+index bbf991bcbe7c..2c825a884ebc 100644
+--- a/drivers/usb/gadget/udc/fotg210.h
++++ b/drivers/usb/gadget/udc/fotg210.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Faraday FOTG210 USB OTG controller
+  *
+diff --git a/drivers/usb/gadget/udc/fsl_mxc_udc.c b/drivers/usb/gadget/udc/fsl_mxc_udc.c
+index f16e149c5b3e..089fbfc44da7 100644
+--- a/drivers/usb/gadget/udc/fsl_mxc_udc.c
++++ b/drivers/usb/gadget/udc/fsl_mxc_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2009
+  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c b/drivers/usb/gadget/udc/fsl_qe_udc.c
+index a3e72d690eef..228577c6c180 100644
+--- a/drivers/usb/gadget/udc/fsl_qe_udc.c
++++ b/drivers/usb/gadget/udc/fsl_qe_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * driver/usb/gadget/fsl_qe_udc.c
+  *
+diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.h b/drivers/usb/gadget/udc/fsl_qe_udc.h
+index 7026919fc901..2b1aec81c397 100644
+--- a/drivers/usb/gadget/udc/fsl_qe_udc.h
++++ b/drivers/usb/gadget/udc/fsl_qe_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * drivers/usb/gadget/qe_udc.h
+  *
+diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
+index 7874c112f3fd..e728a7f481d9 100644
+--- a/drivers/usb/gadget/udc/fsl_udc_core.c
++++ b/drivers/usb/gadget/udc/fsl_udc_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
+  * All rights reserved.
+diff --git a/drivers/usb/gadget/udc/fsl_usb2_udc.h b/drivers/usb/gadget/udc/fsl_usb2_udc.h
+index e92b8408b6f6..e5a25ef5803b 100644
+--- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
++++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2004,2012 Freescale Semiconductor, Inc
+  * All rights reserved.
+diff --git a/drivers/usb/gadget/udc/fusb300_udc.c b/drivers/usb/gadget/udc/fusb300_udc.c
+index e0c1b0099265..e05946c421ed 100644
+--- a/drivers/usb/gadget/udc/fusb300_udc.c
++++ b/drivers/usb/gadget/udc/fusb300_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Fusb300 UDC (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/fusb300_udc.h b/drivers/usb/gadget/udc/fusb300_udc.h
+index ad39f892d200..4b055ef31cc1 100644
+--- a/drivers/usb/gadget/udc/fusb300_udc.h
++++ b/drivers/usb/gadget/udc/fusb300_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Fusb300 UDC (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/goku_udc.c b/drivers/usb/gadget/udc/goku_udc.c
+index 8433c22900dc..f90a82a739c4 100644
+--- a/drivers/usb/gadget/udc/goku_udc.c
++++ b/drivers/usb/gadget/udc/goku_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Toshiba TC86C001 ("Goku-S") USB Device Controller driver
+  *
+diff --git a/drivers/usb/gadget/udc/goku_udc.h b/drivers/usb/gadget/udc/goku_udc.h
+index 64eb0f2b5ea0..99a01453df06 100644
+--- a/drivers/usb/gadget/udc/goku_udc.h
++++ b/drivers/usb/gadget/udc/goku_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Toshiba TC86C001 ("Goku-S") USB Device Controller driver
+  *
+diff --git a/drivers/usb/gadget/udc/gr_udc.c b/drivers/usb/gadget/udc/gr_udc.c
+index 1f9941145746..675aa1043be4 100644
+--- a/drivers/usb/gadget/udc/gr_udc.c
++++ b/drivers/usb/gadget/udc/gr_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC.
+  *
+diff --git a/drivers/usb/gadget/udc/gr_udc.h b/drivers/usb/gadget/udc/gr_udc.h
+index 4297c4e8021f..6c08ddf03521 100644
+--- a/drivers/usb/gadget/udc/gr_udc.h
++++ b/drivers/usb/gadget/udc/gr_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC.
+  *
+diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c
+index 8f32b5ee7734..7dcd0904bf25 100644
+--- a/drivers/usb/gadget/udc/lpc32xx_udc.c
++++ b/drivers/usb/gadget/udc/lpc32xx_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Gadget driver for LPC32xx
+  *
+diff --git a/drivers/usb/gadget/udc/m66592-udc.c b/drivers/usb/gadget/udc/m66592-udc.c
+index 46ce7bc15f2b..39076551e325 100644
+--- a/drivers/usb/gadget/udc/m66592-udc.c
++++ b/drivers/usb/gadget/udc/m66592-udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * M66592 UDC (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/m66592-udc.h b/drivers/usb/gadget/udc/m66592-udc.h
+index 96d49d7bfb6b..4a62b4fda942 100644
+--- a/drivers/usb/gadget/udc/m66592-udc.h
++++ b/drivers/usb/gadget/udc/m66592-udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * M66592 UDC (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/mv_u3d.h b/drivers/usb/gadget/udc/mv_u3d.h
+index e32a787ac373..4c7812429920 100644
+--- a/drivers/usb/gadget/udc/mv_u3d.h
++++ b/drivers/usb/gadget/udc/mv_u3d.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  *
+diff --git a/drivers/usb/gadget/udc/mv_u3d_core.c b/drivers/usb/gadget/udc/mv_u3d_core.c
+index 772049afe166..6f336fe8bbef 100644
+--- a/drivers/usb/gadget/udc/mv_u3d_core.c
++++ b/drivers/usb/gadget/udc/mv_u3d_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  *
+diff --git a/drivers/usb/gadget/udc/mv_udc.h b/drivers/usb/gadget/udc/mv_udc.h
+index be77f207dbaf..4acf7edf4d86 100644
+--- a/drivers/usb/gadget/udc/mv_udc.h
++++ b/drivers/usb/gadget/udc/mv_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  *
+diff --git a/drivers/usb/gadget/udc/mv_udc_core.c b/drivers/usb/gadget/udc/mv_udc_core.c
+index 4103bf7cf52a..df4065cf5fcd 100644
+--- a/drivers/usb/gadget/udc/mv_udc_core.c
++++ b/drivers/usb/gadget/udc/mv_udc_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  * Author: Chao Xie <chao.xie@marvell.com>
+diff --git a/drivers/usb/gadget/udc/net2272.c b/drivers/usb/gadget/udc/net2272.c
+index 8f85a51bd2b3..a3018f93df58 100644
+--- a/drivers/usb/gadget/udc/net2272.c
++++ b/drivers/usb/gadget/udc/net2272.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for PLX NET2272 USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/net2272.h b/drivers/usb/gadget/udc/net2272.h
+index 69bc9c3c6ce4..f0212cf042a2 100644
+--- a/drivers/usb/gadget/udc/net2272.h
++++ b/drivers/usb/gadget/udc/net2272.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * PLX NET2272 high/full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/net2280.c b/drivers/usb/gadget/udc/net2280.c
+index f608c1f85e61..a0b2ab0c04f7 100644
+--- a/drivers/usb/gadget/udc/net2280.c
++++ b/drivers/usb/gadget/udc/net2280.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for the PLX NET2280 USB device controller.
+  * Specs and errata are available from <http://www.plxtech.com>.
+diff --git a/drivers/usb/gadget/udc/net2280.h b/drivers/usb/gadget/udc/net2280.h
+index 1088c3745999..18a881e7f93f 100644
+--- a/drivers/usb/gadget/udc/net2280.h
++++ b/drivers/usb/gadget/udc/net2280.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * NetChip 2280 high/full speed USB device controller.
+  * Unlike many such controllers, this one talks PCI.
+diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c
+index f05ba6825bfe..5531ea492ed2 100644
+--- a/drivers/usb/gadget/udc/omap_udc.c
++++ b/drivers/usb/gadget/udc/omap_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
+  *
+diff --git a/drivers/usb/gadget/udc/pch_udc.c b/drivers/usb/gadget/udc/pch_udc.c
+index 84dcbcd756f0..cc24334504b8 100644
+--- a/drivers/usb/gadget/udc/pch_udc.c
++++ b/drivers/usb/gadget/udc/pch_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+  *
+diff --git a/drivers/usb/gadget/udc/pxa25x_udc.c b/drivers/usb/gadget/udc/pxa25x_udc.c
+index a238da906115..ffbd4dd84c15 100644
+--- a/drivers/usb/gadget/udc/pxa25x_udc.c
++++ b/drivers/usb/gadget/udc/pxa25x_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
+  *
+diff --git a/drivers/usb/gadget/udc/pxa25x_udc.h b/drivers/usb/gadget/udc/pxa25x_udc.h
+index a458bec2536d..1532e7e71f99 100644
+--- a/drivers/usb/gadget/udc/pxa25x_udc.h
++++ b/drivers/usb/gadget/udc/pxa25x_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Intel PXA25x on-chip full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/pxa27x_udc.c b/drivers/usb/gadget/udc/pxa27x_udc.c
+index d48e239660c3..14606f340325 100644
+--- a/drivers/usb/gadget/udc/pxa27x_udc.c
++++ b/drivers/usb/gadget/udc/pxa27x_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Handles the Intel 27x USB Device Controller (UDC)
+  *
+diff --git a/drivers/usb/gadget/udc/pxa27x_udc.h b/drivers/usb/gadget/udc/pxa27x_udc.h
+index cea2cb79b30c..cfdece686abe 100644
+--- a/drivers/usb/gadget/udc/pxa27x_udc.h
++++ b/drivers/usb/gadget/udc/pxa27x_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * linux/drivers/usb/gadget/pxa27x_udc.h
+  * Intel PXA27x on-chip full speed USB device controller
+diff --git a/drivers/usb/gadget/udc/r8a66597-udc.c b/drivers/usb/gadget/udc/r8a66597-udc.c
+index 84b227ede082..8d876d90b7ff 100644
+--- a/drivers/usb/gadget/udc/r8a66597-udc.c
++++ b/drivers/usb/gadget/udc/r8a66597-udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A66597 UDC (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/r8a66597-udc.h b/drivers/usb/gadget/udc/r8a66597-udc.h
+index 45c4b2df1785..0f6d41e61841 100644
+--- a/drivers/usb/gadget/udc/r8a66597-udc.h
++++ b/drivers/usb/gadget/udc/r8a66597-udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A66597 UDC
+  *
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 7e0548f6bd9e..9f68b46d5d1a 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Renesas USB3.0 Peripheral driver (USB gadget)
+  *
+diff --git a/drivers/usb/gadget/udc/s3c-hsudc.c b/drivers/usb/gadget/udc/s3c-hsudc.c
+index 42587b738a1f..9707b945eef2 100644
+--- a/drivers/usb/gadget/udc/s3c-hsudc.c
++++ b/drivers/usb/gadget/udc/s3c-hsudc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* linux/drivers/usb/gadget/s3c-hsudc.c
+  *
+  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+diff --git a/drivers/usb/gadget/udc/s3c2410_udc.c b/drivers/usb/gadget/udc/s3c2410_udc.c
+index 394abd5d65c0..ed874cabd339 100644
+--- a/drivers/usb/gadget/udc/s3c2410_udc.c
++++ b/drivers/usb/gadget/udc/s3c2410_udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * linux/drivers/usb/gadget/s3c2410_udc.c
+  *
+diff --git a/drivers/usb/gadget/udc/s3c2410_udc.h b/drivers/usb/gadget/udc/s3c2410_udc.h
+index 93bf225f1969..cfabc83c2244 100644
+--- a/drivers/usb/gadget/udc/s3c2410_udc.h
++++ b/drivers/usb/gadget/udc/s3c2410_udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * linux/drivers/usb/gadget/s3c2410_udc.h
+  * Samsung on-chip full speed USB device controllers
+diff --git a/drivers/usb/gadget/udc/snps_udc_core.c b/drivers/usb/gadget/udc/snps_udc_core.c
+index 38a165dbf924..dba9359ece0d 100644
+--- a/drivers/usb/gadget/udc/snps_udc_core.c
++++ b/drivers/usb/gadget/udc/snps_udc_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
+  *
+diff --git a/drivers/usb/gadget/udc/snps_udc_plat.c b/drivers/usb/gadget/udc/snps_udc_plat.c
+index e8a5fdaee37d..800a35b48ab1 100644
+--- a/drivers/usb/gadget/udc/snps_udc_plat.c
++++ b/drivers/usb/gadget/udc/snps_udc_plat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * snps_udc_plat.c - Synopsys UDC Platform Driver
+  *
+diff --git a/drivers/usb/gadget/udc/trace.c b/drivers/usb/gadget/udc/trace.c
+index 8c551ab91ad8..fbc139292245 100644
+--- a/drivers/usb/gadget/udc/trace.c
++++ b/drivers/usb/gadget/udc/trace.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * trace.c - USB Gadget Framework Trace Support
+  *
+diff --git a/drivers/usb/gadget/udc/trace.h b/drivers/usb/gadget/udc/trace.h
+index da29874b5366..06b162bcdb54 100644
+--- a/drivers/usb/gadget/udc/trace.h
++++ b/drivers/usb/gadget/udc/trace.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * udc.c - Core UDC Framework
+  *
+diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c
+index de207a90571e..374a75d68365 100644
+--- a/drivers/usb/gadget/udc/udc-xilinx.c
++++ b/drivers/usb/gadget/udc/udc-xilinx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Xilinx USB peripheral controller driver
+  *
+diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
+index 73a4dfba0edb..6c7a4e0c45c8 100644
+--- a/drivers/usb/gadget/usbstring.c
++++ b/drivers/usb/gadget/usbstring.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: LGPL-2.1+
+ /*
+  * Copyright (C) 2003 David Brownell
+  *
+diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c
+index 5f425c89faf1..0f595c630600 100644
+--- a/drivers/usb/host/bcma-hcd.c
++++ b/drivers/usb/host/bcma-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Broadcom specific Advanced Microcontroller Bus
+  * Broadcom USB-core driver (BCMA bus glue)
+diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
+index 7440722bfbf0..a058c0310a5a 100644
+--- a/drivers/usb/host/ehci-atmel.c
++++ b/drivers/usb/host/ehci-atmel.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for EHCI UHP on Atmel chips
+  *
+diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c
+index 8c5a6fee4dfd..3bd0b2273171 100644
+--- a/drivers/usb/host/ehci-dbg.c
++++ b/drivers/usb/host/ehci-dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001-2002 by David Brownell
+  *
+diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
+index 26b641100639..0a131659fc33 100644
+--- a/drivers/usb/host/ehci-exynos.c
++++ b/drivers/usb/host/ehci-exynos.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * SAMSUNG EXYNOS USB HOST EHCI Controller
+  *
+diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
+index d025cc06dda7..7c4bb32230d2 100644
+--- a/drivers/usb/host/ehci-fsl.c
++++ b/drivers/usb/host/ehci-fsl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2005-2009 MontaVista Software, Inc.
+  * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
+diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
+index 1a8a60a57cf2..21a6f10b5e3a 100644
+--- a/drivers/usb/host/ehci-fsl.h
++++ b/drivers/usb/host/ehci-fsl.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
+  * Copyright (c) 2005 MontaVista Software
+  *
+diff --git a/drivers/usb/host/ehci-grlib.c b/drivers/usb/host/ehci-grlib.c
+index 21650044b09e..a8cffcf13451 100644
+--- a/drivers/usb/host/ehci-grlib.c
++++ b/drivers/usb/host/ehci-grlib.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Aeroflex Gaisler GRLIB GRUSBHC EHCI host controller
+  *
+diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
+index 6e834b83a104..f3e18dbf821c 100644
+--- a/drivers/usb/host/ehci-hcd.c
++++ b/drivers/usb/host/ehci-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Enhanced Host Controller Interface (EHCI) driver for USB.
+  *
+diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
+index 37ef2ac9cdae..fcf339aef017 100644
+--- a/drivers/usb/host/ehci-hub.c
++++ b/drivers/usb/host/ehci-hub.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2001-2004 by David Brownell
+  *
+diff --git a/drivers/usb/host/ehci-mem.c b/drivers/usb/host/ehci-mem.c
+index 9b7e63977215..212d2042fb9f 100644
+--- a/drivers/usb/host/ehci-mem.c
++++ b/drivers/usb/host/ehci-mem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001 by David Brownell
+  *
+diff --git a/drivers/usb/host/ehci-mv.c b/drivers/usb/host/ehci-mv.c
+index 849806a75f1c..c9e15225a30f 100644
+--- a/drivers/usb/host/ehci-mv.c
++++ b/drivers/usb/host/ehci-mv.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  * Author: Chao Xie <chao.xie@marvell.com>
+diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
+index c7a9b31eeaef..67adea97c26c 100644
+--- a/drivers/usb/host/ehci-mxc.c
++++ b/drivers/usb/host/ehci-mxc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 4d308533bc83..dd319d3219b6 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * ehci-omap.c - driver for USBHOST on OMAP3/4 processors
+  *
+diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
+index 1aec87ec68df..199a6d2778dd 100644
+--- a/drivers/usb/host/ehci-orion.c
++++ b/drivers/usb/host/ehci-orion.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * drivers/usb/host/ehci-orion.c
+  *
+diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
+index 93326974ff4b..f6015f6ca488 100644
+--- a/drivers/usb/host/ehci-pci.c
++++ b/drivers/usb/host/ehci-pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
+  *
+diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
+index f1908ea9fbd8..cb77af3a71c1 100644
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Generic platform ehci driver
+  *
+diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c
+index 342816a7f8b1..9a05bff230bb 100644
+--- a/drivers/usb/host/ehci-pmcmsp.c
++++ b/drivers/usb/host/ehci-pmcmsp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * PMC MSP EHCI (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
+index 1a10c8d542ca..576f7d79ad4e 100644
+--- a/drivers/usb/host/ehci-ppc-of.c
++++ b/drivers/usb/host/ehci-ppc-of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * EHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
+index 7934ff9b35e1..c74066790e69 100644
+--- a/drivers/usb/host/ehci-ps3.c
++++ b/drivers/usb/host/ehci-ps3.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  PS3 EHCI Host Controller driver
+  *
+diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
+index 8f3f055c05fa..c0074f212a09 100644
+--- a/drivers/usb/host/ehci-q.c
++++ b/drivers/usb/host/ehci-q.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2001-2004 by David Brownell
+  *
+diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
+index 6bc6304672bc..ebbc2c60de89 100644
+--- a/drivers/usb/host/ehci-sched.c
++++ b/drivers/usb/host/ehci-sched.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001-2004 by David Brownell
+  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
+diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c
+index 5caf88d679e4..d565f24ca7f5 100644
+--- a/drivers/usb/host/ehci-sh.c
++++ b/drivers/usb/host/ehci-sh.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * SuperH EHCI host controller driver
+  *
+diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
+index 1f25c7985f5b..d12259d06f53 100644
+--- a/drivers/usb/host/ehci-spear.c
++++ b/drivers/usb/host/ehci-spear.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Driver for EHCI HCD on SPEAr SOC
+ *
+diff --git a/drivers/usb/host/ehci-st.c b/drivers/usb/host/ehci-st.c
+index be4a2788fc58..336e9fa5274f 100644
+--- a/drivers/usb/host/ehci-st.c
++++ b/drivers/usb/host/ehci-st.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ST EHCI driver
+  *
+diff --git a/drivers/usb/host/ehci-sysfs.c b/drivers/usb/host/ehci-sysfs.c
+index 5216f2b09d63..16669619cfc5 100644
+--- a/drivers/usb/host/ehci-sysfs.c
++++ b/drivers/usb/host/ehci-sysfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2007 by Alan Stern
+  *
+diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
+index 9a3d7db5be57..fe8423e17877 100644
+--- a/drivers/usb/host/ehci-tegra.c
++++ b/drivers/usb/host/ehci-tegra.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
+  *
+diff --git a/drivers/usb/host/ehci-tilegx.c b/drivers/usb/host/ehci-tilegx.c
+index bdb93b6a356f..d41b3d217253 100644
+--- a/drivers/usb/host/ehci-tilegx.c
++++ b/drivers/usb/host/ehci-tilegx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2012 Tilera Corporation. All Rights Reserved.
+  *
+diff --git a/drivers/usb/host/ehci-timer.c b/drivers/usb/host/ehci-timer.c
+index 0b6cdb723192..047a5b131717 100644
+--- a/drivers/usb/host/ehci-timer.c
++++ b/drivers/usb/host/ehci-timer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2012 by Alan Stern
+  *
+diff --git a/drivers/usb/host/ehci-w90x900.c b/drivers/usb/host/ehci-w90x900.c
+index 63b9d0c67963..da2c99d3ba6b 100644
+--- a/drivers/usb/host/ehci-w90x900.c
++++ b/drivers/usb/host/ehci-w90x900.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * linux/driver/usb/host/ehci-w90x900.c
+  *
+diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c
+index f54480850bb8..886b05678de9 100644
+--- a/drivers/usb/host/ehci-xilinx-of.c
++++ b/drivers/usb/host/ehci-xilinx-of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * EHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
+index a8e36170d8b8..1794d6254cfc 100644
+--- a/drivers/usb/host/ehci.h
++++ b/drivers/usb/host/ehci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001-2002 by David Brownell
+  *
+diff --git a/drivers/usb/host/fhci-dbg.c b/drivers/usb/host/fhci-dbg.c
+index b58e7a60913a..9935f10ad407 100644
+--- a/drivers/usb/host/fhci-dbg.c
++++ b/drivers/usb/host/fhci-dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c
+index 55a0ae6f2d74..763131134ab1 100644
+--- a/drivers/usb/host/fhci-hcd.c
++++ b/drivers/usb/host/fhci-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-hub.c b/drivers/usb/host/fhci-hub.c
+index 60d55eb3de0d..d50a9ca15830 100644
+--- a/drivers/usb/host/fhci-hub.c
++++ b/drivers/usb/host/fhci-hub.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-mem.c b/drivers/usb/host/fhci-mem.c
+index b0b88f57a5ac..532a5960ff48 100644
+--- a/drivers/usb/host/fhci-mem.c
++++ b/drivers/usb/host/fhci-mem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-q.c b/drivers/usb/host/fhci-q.c
+index 03be7494a476..664e1f98d68f 100644
+--- a/drivers/usb/host/fhci-q.c
++++ b/drivers/usb/host/fhci-q.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-sched.c b/drivers/usb/host/fhci-sched.c
+index 2f162faabbca..c8f3de90f464 100644
+--- a/drivers/usb/host/fhci-sched.c
++++ b/drivers/usb/host/fhci-sched.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci-tds.c b/drivers/usb/host/fhci-tds.c
+index f82ad5df1b0d..fa54315064da 100644
+--- a/drivers/usb/host/fhci-tds.c
++++ b/drivers/usb/host/fhci-tds.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fhci.h b/drivers/usb/host/fhci.h
+index 3fc82c1c3c73..257c04c8af0c 100644
+--- a/drivers/usb/host/fhci.h
++++ b/drivers/usb/host/fhci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Freescale QUICC Engine USB Host Controller Driver
+  *
+diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c
+index 457cc6525abd..26f1c5d533f2 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* Faraday FOTG210 EHCI-like driver
+  *
+  * Copyright (c) 2013 Faraday Technology Corporation
+diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
+index ba557cdba8ef..c749cbd8dd3c 100644
+--- a/drivers/usb/host/fsl-mph-dr-of.c
++++ b/drivers/usb/host/fsl-mph-dr-of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Setup platform devices needed by the Freescale multi-port host
+  * and/or dual-role USB controller modules based on the description
+diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c
+index da3b18038d23..e5fda058b5d6 100644
+--- a/drivers/usb/host/hwa-hc.c
++++ b/drivers/usb/host/hwa-hc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Host Wire Adapter:
+  * Driver glue, HWA-specific functions, bridges to WAHC and WUSBHC
+diff --git a/drivers/usb/host/imx21-dbg.c b/drivers/usb/host/imx21-dbg.c
+index 4f320d050da7..d6a72acceacf 100644
+--- a/drivers/usb/host/imx21-dbg.c
++++ b/drivers/usb/host/imx21-dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2009 by Martin Fuzzey
+  *
+diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
+index 39ae7fb64b6f..4dbf28bc2652 100644
+--- a/drivers/usb/host/imx21-hcd.c
++++ b/drivers/usb/host/imx21-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Host Controller Driver for IMX21
+  *
+diff --git a/drivers/usb/host/imx21-hcd.h b/drivers/usb/host/imx21-hcd.h
+index 05122f8a6983..768e714bcb30 100644
+--- a/drivers/usb/host/imx21-hcd.h
++++ b/drivers/usb/host/imx21-hcd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Macros and prototypes for i.MX21
+  *
+diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
+index 73fec38754f9..2488cc80ae20 100644
+--- a/drivers/usb/host/isp116x-hcd.c
++++ b/drivers/usb/host/isp116x-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ISP116x HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/isp1362-hcd.c b/drivers/usb/host/isp1362-hcd.c
+index 9b7e307e2d54..079bc8e5e241 100644
+--- a/drivers/usb/host/isp1362-hcd.c
++++ b/drivers/usb/host/isp1362-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ISP1362 HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/max3421-hcd.c b/drivers/usb/host/max3421-hcd.c
+index 0ece9a9341e5..6a007f91a863 100644
+--- a/drivers/usb/host/max3421-hcd.c
++++ b/drivers/usb/host/max3421-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MAX3421 Host Controller driver for USB.
+  *
+diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
+index 5302f988e7e6..5ad9e9bdc8ee 100644
+--- a/drivers/usb/host/ohci-at91.c
++++ b/drivers/usb/host/ohci-at91.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
+index 05da2cb59612..2056573c2b12 100644
+--- a/drivers/usb/host/ohci-da8xx.c
++++ b/drivers/usb/host/ohci-da8xx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-dbg.c b/drivers/usb/host/ohci-dbg.c
+index c3eded317495..ac7d4ac34b02 100644
+--- a/drivers/usb/host/ohci-dbg.c
++++ b/drivers/usb/host/ohci-dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
+index 6865b919403f..a12cbb295425 100644
+--- a/drivers/usb/host/ohci-exynos.c
++++ b/drivers/usb/host/ohci-exynos.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * SAMSUNG EXYNOS USB HOST OHCI Controller
+  *
+diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
+index b4599aa428f3..41fd0b8937d7 100644
+--- a/drivers/usb/host/ohci-hcd.c
++++ b/drivers/usb/host/ohci-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Open Host Controller Interface (OHCI) driver for USB.
+  *
+diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
+index aca57bcb9afe..634f3c7bf774 100644
+--- a/drivers/usb/host/ohci-hub.c
++++ b/drivers/usb/host/ohci-hub.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-mem.c b/drivers/usb/host/ohci-mem.c
+index ed8a762b8670..b3da3f12e5b1 100644
+--- a/drivers/usb/host/ohci-mem.c
++++ b/drivers/usb/host/ohci-mem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
+index 6df8e2ed40fd..5509b50bc417 100644
+--- a/drivers/usb/host/ohci-nxp.c
++++ b/drivers/usb/host/ohci-nxp.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * driver for NXP USB Host devices
+  *
+diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
+index 91393ec7d850..0201c49bc4fc 100644
+--- a/drivers/usb/host/ohci-omap.c
++++ b/drivers/usb/host/ohci-omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
+index a84aebe9b0a9..fbcd34911025 100644
+--- a/drivers/usb/host/ohci-pci.c
++++ b/drivers/usb/host/ohci-pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
+index 61fe2b985070..908ebcfbc350 100644
+--- a/drivers/usb/host/ohci-platform.c
++++ b/drivers/usb/host/ohci-platform.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Generic platform ohci driver
+  *
+diff --git a/drivers/usb/host/ohci-ppc-of.c b/drivers/usb/host/ohci-ppc-of.c
+index 4f87a5c61b08..76a9b40b08f1 100644
+--- a/drivers/usb/host/ohci-ppc-of.c
++++ b/drivers/usb/host/ohci-ppc-of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-ps3.c b/drivers/usb/host/ohci-ps3.c
+index 71d8bc4c27f6..bb0375d9eef0 100644
+--- a/drivers/usb/host/ohci-ps3.c
++++ b/drivers/usb/host/ohci-ps3.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  PS3 OHCI Host Controller driver
+  *
+diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
+index 21c010ffb03c..3e2474959735 100644
+--- a/drivers/usb/host/ohci-pxa27x.c
++++ b/drivers/usb/host/ohci-pxa27x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
+index 24edb7674710..4ccb85a67bb3 100644
+--- a/drivers/usb/host/ohci-q.c
++++ b/drivers/usb/host/ohci-q.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
+index b006b93126f7..4511e27e9da8 100644
+--- a/drivers/usb/host/ohci-s3c2410.c
++++ b/drivers/usb/host/ohci-s3c2410.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-sa1111.c b/drivers/usb/host/ohci-sa1111.c
+index 3a9ea32508df..a022db46e999 100644
+--- a/drivers/usb/host/ohci-sa1111.c
++++ b/drivers/usb/host/ohci-sa1111.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-sm501.c b/drivers/usb/host/ohci-sm501.c
+index d4e0f7cd96fa..c9233cddf9a2 100644
+--- a/drivers/usb/host/ohci-sm501.c
++++ b/drivers/usb/host/ohci-sm501.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci-spear.c b/drivers/usb/host/ohci-spear.c
+index 56478ed2f932..b3554f70bd27 100644
+--- a/drivers/usb/host/ohci-spear.c
++++ b/drivers/usb/host/ohci-spear.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+diff --git a/drivers/usb/host/ohci-st.c b/drivers/usb/host/ohci-st.c
+index 02816a1515a1..697e6d95bb7e 100644
+--- a/drivers/usb/host/ohci-st.c
++++ b/drivers/usb/host/ohci-st.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ST OHCI driver
+  *
+diff --git a/drivers/usb/host/ohci-tilegx.c b/drivers/usb/host/ohci-tilegx.c
+index e1b208da460a..e5a9f68cd648 100644
+--- a/drivers/usb/host/ohci-tilegx.c
++++ b/drivers/usb/host/ohci-tilegx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2012 Tilera Corporation. All Rights Reserved.
+  *
+diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c
+index 16d081a093bb..5702964408db 100644
+--- a/drivers/usb/host/ohci-tmio.c
++++ b/drivers/usb/host/ohci-tmio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * OHCI HCD(Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
+index 12742d002d2d..508a803139dd 100644
+--- a/drivers/usb/host/ohci.h
++++ b/drivers/usb/host/ohci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * OHCI HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
+index ed20fb34c897..b0cb356f9d72 100644
+--- a/drivers/usb/host/oxu210hp-hcd.c
++++ b/drivers/usb/host/oxu210hp-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
+  * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
+diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
+index e1faee1f8602..db85ac6f89fc 100644
+--- a/drivers/usb/host/pci-quirks.c
++++ b/drivers/usb/host/pci-quirks.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * This file contains code to reset and initialize USB host controllers.
+  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
+diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
+index 5e5fc9d7d533..e4e0d2ac24ce 100644
+--- a/drivers/usb/host/r8a66597-hcd.c
++++ b/drivers/usb/host/r8a66597-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A66597 HCD (Host Controller Driver)
+  *
+diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
+index 672cea307abb..0e1a0c3a805a 100644
+--- a/drivers/usb/host/r8a66597.h
++++ b/drivers/usb/host/r8a66597.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A66597 HCD (Host Controller Driver)
+  *
+diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
+index 24ad1d6cec25..601fb00603cc 100644
+--- a/drivers/usb/host/sl811-hcd.c
++++ b/drivers/usb/host/sl811-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * SL811HS HCD (Host Controller Driver) for USB.
+  *
+diff --git a/drivers/usb/host/sl811_cs.c b/drivers/usb/host/sl811_cs.c
+index 88a9bffe93df..72136373ffab 100644
+--- a/drivers/usb/host/sl811_cs.c
++++ b/drivers/usb/host/sl811_cs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * PCMCIA driver for SL811HS (as found in REX-CFU1U)
+  * Filename: sl811_cs.c
+diff --git a/drivers/usb/host/ssb-hcd.c b/drivers/usb/host/ssb-hcd.c
+index 62b6b7804c66..2f9087dc4cab 100644
+--- a/drivers/usb/host/ssb-hcd.c
++++ b/drivers/usb/host/ssb-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Sonics Silicon Backplane
+  * Broadcom USB-core driver  (SSB bus glue)
+diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
+index c38855aed62c..228d22bfb36e 100644
+--- a/drivers/usb/host/u132-hcd.c
++++ b/drivers/usb/host/u132-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Host Controller Driver for the Elan Digital Systems U132 adapter
+ *
+diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
+index c3267a78c94e..babeefd84ffd 100644
+--- a/drivers/usb/host/uhci-hcd.c
++++ b/drivers/usb/host/uhci-hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Universal Host Controller Interface driver for USB.
+  *
+diff --git a/drivers/usb/host/whci/asl.c b/drivers/usb/host/whci/asl.c
+index 773249306031..81a6286f50cf 100644
+--- a/drivers/usb/host/whci/asl.c
++++ b/drivers/usb/host/whci/asl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) asynchronous schedule management.
+  *
+diff --git a/drivers/usb/host/whci/debug.c b/drivers/usb/host/whci/debug.c
+index 774b89d28fae..3cbd84893b6f 100644
+--- a/drivers/usb/host/whci/debug.c
++++ b/drivers/usb/host/whci/debug.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) debug.
+  *
+diff --git a/drivers/usb/host/whci/hcd.c b/drivers/usb/host/whci/hcd.c
+index cf84269c3e6d..eb30567fa6d1 100644
+--- a/drivers/usb/host/whci/hcd.c
++++ b/drivers/usb/host/whci/hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) driver.
+  *
+diff --git a/drivers/usb/host/whci/hw.c b/drivers/usb/host/whci/hw.c
+index 6afa2e379160..2a89686d6971 100644
+--- a/drivers/usb/host/whci/hw.c
++++ b/drivers/usb/host/whci/hw.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) hardware access helpers.
+  *
+diff --git a/drivers/usb/host/whci/init.c b/drivers/usb/host/whci/init.c
+index ad8eb575c30a..48a6f50df24a 100644
+--- a/drivers/usb/host/whci/init.c
++++ b/drivers/usb/host/whci/init.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) initialization.
+  *
+diff --git a/drivers/usb/host/whci/int.c b/drivers/usb/host/whci/int.c
+index 0c086b2790d1..15a2df0b29ab 100644
+--- a/drivers/usb/host/whci/int.c
++++ b/drivers/usb/host/whci/int.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) interrupt handling.
+  *
+diff --git a/drivers/usb/host/whci/pzl.c b/drivers/usb/host/whci/pzl.c
+index 33c5580b4d25..bafac6a88551 100644
+--- a/drivers/usb/host/whci/pzl.c
++++ b/drivers/usb/host/whci/pzl.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) periodic schedule management.
+  *
+diff --git a/drivers/usb/host/whci/qset.c b/drivers/usb/host/whci/qset.c
+index c0e6812426b3..1a92d0e492a0 100644
+--- a/drivers/usb/host/whci/qset.c
++++ b/drivers/usb/host/whci/qset.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) qset management.
+  *
+diff --git a/drivers/usb/host/whci/whcd.h b/drivers/usb/host/whci/whcd.h
+index c80c7d93bc4a..4712972682fe 100644
+--- a/drivers/usb/host/whci/whcd.h
++++ b/drivers/usb/host/whci/whcd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) private header.
+  *
+diff --git a/drivers/usb/host/whci/whci-hc.h b/drivers/usb/host/whci/whci-hc.h
+index 4d4cbc0730bf..5dfbc9837b00 100644
+--- a/drivers/usb/host/whci/whci-hc.h
++++ b/drivers/usb/host/whci/whci-hc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) data structures.
+  *
+diff --git a/drivers/usb/host/whci/wusb.c b/drivers/usb/host/whci/wusb.c
+index 8d2762682869..8c8d8bc8eac4 100644
+--- a/drivers/usb/host/whci/wusb.c
++++ b/drivers/usb/host/whci/wusb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless Host Controller (WHC) WUSB operations.
+  *
+diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
+index 2c83b37ae8f2..83904170be5c 100644
+--- a/drivers/usb/host/xhci-dbg.c
++++ b/drivers/usb/host/xhci-dbg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
+index 28deea584884..259963bbe3aa 100644
+--- a/drivers/usb/host/xhci-ext-caps.h
++++ b/drivers/usb/host/xhci-ext-caps.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index c01d1f3a1c7d..fff62fe0a097 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index b7b55eb82714..17dcc8ae6859 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+index 6e7ddf6cafae..42e4701ee944 100644
+--- a/drivers/usb/host/xhci-mtk-sch.c
++++ b/drivers/usb/host/xhci-mtk-sch.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2015 MediaTek Inc.
+  * Author:
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 8fb60657ed4f..4e2fb05282a6 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MediaTek xHCI Host Controller Driver
+  *
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 3aa5e1d25064..047d1a60341b 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2015 MediaTek Inc.
+  * Author:
+diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
+index 85908a3ecb8f..fe7a2f84faeb 100644
+--- a/drivers/usb/host/xhci-mvebu.c
++++ b/drivers/usb/host/xhci-mvebu.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Marvell
+  * Author: Gregory CLEMENT <gregory.clement@free-electrons.com>
+diff --git a/drivers/usb/host/xhci-mvebu.h b/drivers/usb/host/xhci-mvebu.h
+index 301fc984cae6..619792ae75b8 100644
+--- a/drivers/usb/host/xhci-mvebu.h
++++ b/drivers/usb/host/xhci-mvebu.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Marvell
+  *
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index 838d37e79fa2..dd4b5e2615cf 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver PCI Bus Glue.
+  *
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 830dd0dbbce0..a15f1f295afc 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xhci-plat.c - xHCI host controller driver platform Bus Glue.
+  *
+diff --git a/drivers/usb/host/xhci-plat.h b/drivers/usb/host/xhci-plat.h
+index 29b227895b07..ac8f8eb0bf49 100644
+--- a/drivers/usb/host/xhci-plat.h
++++ b/drivers/usb/host/xhci-plat.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xhci-plat.h - xHCI host controller driver platform Bus Glue.
+  *
+diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
+index 97f23cc31f4c..407fa95f7122 100644
+--- a/drivers/usb/host/xhci-rcar.c
++++ b/drivers/usb/host/xhci-rcar.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver for R-Car SoCs
+  *
+diff --git a/drivers/usb/host/xhci-rcar.h b/drivers/usb/host/xhci-rcar.h
+index d247951147a1..162706528c4c 100644
+--- a/drivers/usb/host/xhci-rcar.h
++++ b/drivers/usb/host/xhci-rcar.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * drivers/usb/host/xhci-rcar.h
+  *
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 6996235e34a9..3a50897ed766 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
+index 32ddafe7af87..6197fce3dce2 100644
+--- a/drivers/usb/host/xhci-tegra.c
++++ b/drivers/usb/host/xhci-tegra.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * NVIDIA Tegra xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-trace.c b/drivers/usb/host/xhci-trace.c
+index 367b630bdb3c..0be3e83025ae 100644
+--- a/drivers/usb/host/xhci-trace.c
++++ b/drivers/usb/host/xhci-trace.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index 02a1164ca599..447edc6343d2 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 6b11fd9d8efe..55bb05893c55 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * xHCI host controller driver
+  *
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 11232e62b898..6b4c7ae70ab1 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ 
+ /*
+  * xHCI host controller driver
+diff --git a/drivers/usb/image/mdc800.c b/drivers/usb/image/mdc800.c
+index e92540a21b6b..ef10a0ecae1b 100644
+--- a/drivers/usb/image/mdc800.c
++++ b/drivers/usb/image/mdc800.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * copyright (C) 1999/2000 by Henning Zabel <henning@uni-paderborn.de>
+  *
+diff --git a/drivers/usb/image/microtek.c b/drivers/usb/image/microtek.c
+index 0b21ba757bba..9f2f563c82ed 100644
+--- a/drivers/usb/image/microtek.c
++++ b/drivers/usb/image/microtek.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* Driver for Microtek Scanmaker X6 USB scanner, and possibly others.
+  *
+  * (C) Copyright 2000 John Fremlin <vii@penguinpowered.com>
+diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c
+index bfa402cf3a27..8157d18135b8 100644
+--- a/drivers/usb/isp1760/isp1760-core.c
++++ b/drivers/usb/isp1760/isp1760-core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the NXP ISP1760 chip
+  *
+diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h
+index c70f8368a794..47985161ee77 100644
+--- a/drivers/usb/isp1760/isp1760-core.h
++++ b/drivers/usb/isp1760/isp1760-core.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the NXP ISP1760 chip
+  *
+diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h
+index b67095c9a9d4..eecdb76c132c 100644
+--- a/drivers/usb/isp1760/isp1760-regs.h
++++ b/drivers/usb/isp1760/isp1760-regs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the NXP ISP1760 chip
+  *
+diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c
+index 69400f3da886..1300154252dc 100644
+--- a/drivers/usb/isp1760/isp1760-udc.c
++++ b/drivers/usb/isp1760/isp1760-udc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the NXP ISP1761 device controller
+  *
+diff --git a/drivers/usb/isp1760/isp1760-udc.h b/drivers/usb/isp1760/isp1760-udc.h
+index 26899ed81145..ea1598df1f11 100644
+--- a/drivers/usb/isp1760/isp1760-udc.h
++++ b/drivers/usb/isp1760/isp1760-udc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for the NXP ISP1761 device controller
+  *
+diff --git a/drivers/usb/misc/adutux.c b/drivers/usb/misc/adutux.c
+index 1c0ada75c35d..092db5ae5fa1 100644
+--- a/drivers/usb/misc/adutux.c
++++ b/drivers/usb/misc/adutux.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * adutux - driver for ADU devices from Ontrak Control Systems
+  * This is an experimental driver. Use at your own risk.
+diff --git a/drivers/usb/misc/appledisplay.c b/drivers/usb/misc/appledisplay.c
+index 8efdc500e790..b75defc52c24 100644
+--- a/drivers/usb/misc/appledisplay.c
++++ b/drivers/usb/misc/appledisplay.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Apple Cinema Display driver
+  *
+diff --git a/drivers/usb/misc/chaoskey.c b/drivers/usb/misc/chaoskey.c
+index abec6e604a62..8a22b4997c5f 100644
+--- a/drivers/usb/misc/chaoskey.c
++++ b/drivers/usb/misc/chaoskey.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * chaoskey - driver for ChaosKey device from Altus Metrum.
+  *
+diff --git a/drivers/usb/misc/cypress_cy7c63.c b/drivers/usb/misc/cypress_cy7c63.c
+index 5c93a888c40e..819ad8dc2376 100644
+--- a/drivers/usb/misc/cypress_cy7c63.c
++++ b/drivers/usb/misc/cypress_cy7c63.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+ * cypress_cy7c63.c
+ *
+diff --git a/drivers/usb/misc/cytherm.c b/drivers/usb/misc/cytherm.c
+index 63207c42acf6..a65f8817ecf8 100644
+--- a/drivers/usb/misc/cytherm.c
++++ b/drivers/usb/misc/cytherm.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* -*- linux-c -*-
+  * Cypress USB Thermometer driver 
+  * 
+diff --git a/drivers/usb/misc/ehset.c b/drivers/usb/misc/ehset.c
+index c31b4a33e6bb..8b8e25424aa1 100644
+--- a/drivers/usb/misc/ehset.c
++++ b/drivers/usb/misc/ehset.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+  *
+diff --git a/drivers/usb/misc/emi26.c b/drivers/usb/misc/emi26.c
+index 8950fa5e973d..81836e9d787f 100644
+--- a/drivers/usb/misc/emi26.c
++++ b/drivers/usb/misc/emi26.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* 
+  * Emagic EMI 2|6 usb audio interface firmware loader.
+  * Copyright (C) 2002
+diff --git a/drivers/usb/misc/emi62.c b/drivers/usb/misc/emi62.c
+index 1d9be4431b72..fad894a63c52 100644
+--- a/drivers/usb/misc/emi62.c
++++ b/drivers/usb/misc/emi62.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /* 
+  * Emagic EMI 2|6 usb audio interface firmware loader.
+  * Copyright (C) 2002
+diff --git a/drivers/usb/misc/ezusb.c b/drivers/usb/misc/ezusb.c
+index 837208f14f86..c9be0d484e5c 100644
+--- a/drivers/usb/misc/ezusb.c
++++ b/drivers/usb/misc/ezusb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * EZ-USB specific functions used by some of the USB to Serial drivers.
+  *
+diff --git a/drivers/usb/misc/ftdi-elan.c b/drivers/usb/misc/ftdi-elan.c
+index 424ff12f3b51..c1fbc2a32eb2 100644
+--- a/drivers/usb/misc/ftdi-elan.c
++++ b/drivers/usb/misc/ftdi-elan.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB FTDI client driver for Elan Digital Systems's Uxxx adapters
+  *
+diff --git a/drivers/usb/misc/idmouse.c b/drivers/usb/misc/idmouse.c
+index 39d8fedfaf3b..8d144903f05e 100644
+--- a/drivers/usb/misc/idmouse.c
++++ b/drivers/usb/misc/idmouse.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* Siemens ID Mouse driver v0.6
+ 
+   This program is free software; you can redistribute it and/or
+diff --git a/drivers/usb/misc/iowarrior.c b/drivers/usb/misc/iowarrior.c
+index be5881303681..ad3109490c0f 100644
+--- a/drivers/usb/misc/iowarrior.c
++++ b/drivers/usb/misc/iowarrior.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  *  Native support for the I/O-Warrior USB devices
+  *
+diff --git a/drivers/usb/misc/isight_firmware.c b/drivers/usb/misc/isight_firmware.c
+index 1c61830e96f9..91c028f16d31 100644
+--- a/drivers/usb/misc/isight_firmware.c
++++ b/drivers/usb/misc/isight_firmware.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for loading USB isight firmware
+  *
+diff --git a/drivers/usb/misc/ldusb.c b/drivers/usb/misc/ldusb.c
+index 6635a3c990f6..ff69a1284886 100644
+--- a/drivers/usb/misc/ldusb.c
++++ b/drivers/usb/misc/ldusb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /**
+  * Generic USB driver for report based interrupt in/out devices
+  * like LD Didactic's USB devices. LD Didactic's USB devices are
+diff --git a/drivers/usb/misc/legousbtower.c b/drivers/usb/misc/legousbtower.c
+index 5628f678ab59..cd4d49d8aea5 100644
+--- a/drivers/usb/misc/legousbtower.c
++++ b/drivers/usb/misc/legousbtower.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * LEGO USB Tower driver
+  *
+diff --git a/drivers/usb/misc/lvstest.c b/drivers/usb/misc/lvstest.c
+index ddddd6387f66..5e5d128e16c0 100644
+--- a/drivers/usb/misc/lvstest.c
++++ b/drivers/usb/misc/lvstest.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * drivers/usb/misc/lvstest.c
+  *
+diff --git a/drivers/usb/misc/rio500.c b/drivers/usb/misc/rio500.c
+index ddfebb144aaa..84bd682e9e61 100644
+--- a/drivers/usb/misc/rio500.c
++++ b/drivers/usb/misc/rio500.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* -*- linux-c -*- */
+ 
+ /* 
+diff --git a/drivers/usb/misc/rio500_usb.h b/drivers/usb/misc/rio500_usb.h
+index 359abc98e706..ce2ac1099d86 100644
+--- a/drivers/usb/misc/rio500_usb.h
++++ b/drivers/usb/misc/rio500_usb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*  ----------------------------------------------------------------------
+ 
+     Copyright (C) 2000  Cesar Miquel  (miquel@df.uba.ar)
+diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c
+index 30774e0aeadd..3e65bdc2615c 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb.c
++++ b/drivers/usb/misc/sisusbvga/sisusb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+ /*
+  * sisusb - usb kernel driver for SiS315(E) based USB2VGA dongles
+  *
+diff --git a/drivers/usb/misc/sisusbvga/sisusb.h b/drivers/usb/misc/sisusbvga/sisusb.h
+index 55492a5930bd..20f03ad0ea16 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb.h
++++ b/drivers/usb/misc/sisusbvga/sisusb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+ /*
+  * sisusb - usb kernel driver for Net2280/SiS315 based USB2VGA dongles
+  *
+diff --git a/drivers/usb/misc/sisusbvga/sisusb_con.c b/drivers/usb/misc/sisusbvga/sisusb_con.c
+index f019d80ca9e4..73f7bde78e11 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb_con.c
++++ b/drivers/usb/misc/sisusbvga/sisusb_con.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+ /*
+  * sisusb - usb kernel driver for SiS315(E) based USB2VGA dongles
+  *
+diff --git a/drivers/usb/misc/sisusbvga/sisusb_init.c b/drivers/usb/misc/sisusbvga/sisusb_init.c
+index bf0032ca35ed..6a30e8bd9221 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb_init.c
++++ b/drivers/usb/misc/sisusbvga/sisusb_init.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+ /*
+  * sisusb - usb kernel driver for SiS315(E) based USB2VGA dongles
+  *
+diff --git a/drivers/usb/misc/sisusbvga/sisusb_init.h b/drivers/usb/misc/sisusbvga/sisusb_init.h
+index e79a616f0d26..1782c759c4ad 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb_init.h
++++ b/drivers/usb/misc/sisusbvga/sisusb_init.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /* $XFree86$ */
+ /* $XdotOrg$ */
+ /*
+diff --git a/drivers/usb/misc/sisusbvga/sisusb_struct.h b/drivers/usb/misc/sisusbvga/sisusb_struct.h
+index 1c4240e802c1..706d77090e00 100644
+--- a/drivers/usb/misc/sisusbvga/sisusb_struct.h
++++ b/drivers/usb/misc/sisusbvga/sisusb_struct.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * General structure definitions for universal mode switching modules
+  *
+diff --git a/drivers/usb/misc/trancevibrator.c b/drivers/usb/misc/trancevibrator.c
+index 1862ed15ce28..405726b8ebe6 100644
+--- a/drivers/usb/misc/trancevibrator.c
++++ b/drivers/usb/misc/trancevibrator.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * PlayStation 2 Trance Vibrator driver
+  *
+diff --git a/drivers/usb/misc/usb251xb.c b/drivers/usb/misc/usb251xb.c
+index 135c91c434bf..e1153c4fe97f 100644
+--- a/drivers/usb/misc/usb251xb.c
++++ b/drivers/usb/misc/usb251xb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Microchip USB251xB USB 2.0 Hi-Speed Hub Controller
+  * Configuration via SMBus.
+diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
+index 03be5d574f23..e9ed1623d6f1 100644
+--- a/drivers/usb/misc/usb3503.c
++++ b/drivers/usb/misc/usb3503.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for SMSC USB3503 USB 2.0 hub controller driver
+  *
+diff --git a/drivers/usb/misc/usb4604.c b/drivers/usb/misc/usb4604.c
+index e9f37fb746ac..40fa85807aae 100644
+--- a/drivers/usb/misc/usb4604.c
++++ b/drivers/usb/misc/usb4604.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for SMSC USB4604 USB HSIC 4-port 2.0 hub controller driver
+  * Based on usb3503 driver
+diff --git a/drivers/usb/misc/usb_u132.h b/drivers/usb/misc/usb_u132.h
+index dc2e5a31caec..4dbfea3237f7 100644
+--- a/drivers/usb/misc/usb_u132.h
++++ b/drivers/usb/misc/usb_u132.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Common Header File for the Elan Digital Systems U132 adapter
+ * this file should be included by both the "ftdi-u132" and
+diff --git a/drivers/usb/misc/usblcd.c b/drivers/usb/misc/usblcd.c
+index 0f5ad896c7e3..9ba4a4e68d91 100644
+--- a/drivers/usb/misc/usblcd.c
++++ b/drivers/usb/misc/usblcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*****************************************************************************
+  *                          USBLCD Kernel Driver                             *
+  *                            Version 1.05                                   *
+diff --git a/drivers/usb/misc/usbsevseg.c b/drivers/usb/misc/usbsevseg.c
+index 3f6a28045b53..4990d5757019 100644
+--- a/drivers/usb/misc/usbsevseg.c
++++ b/drivers/usb/misc/usbsevseg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB 7 Segment Driver
+  *
+diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c
+index b3fc602b2e24..ae6c20ce998c 100644
+--- a/drivers/usb/misc/usbtest.c
++++ b/drivers/usb/misc/usbtest.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/kernel.h>
+ #include <linux/errno.h>
+ #include <linux/init.h>
+diff --git a/drivers/usb/misc/uss720.c b/drivers/usb/misc/uss720.c
+index 8a13b2fcf3e1..876a7a32defc 100644
+--- a/drivers/usb/misc/uss720.c
++++ b/drivers/usb/misc/uss720.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*****************************************************************************/
+ 
+ /*
+diff --git a/drivers/usb/misc/yurex.c b/drivers/usb/misc/yurex.c
+index 47763311a42e..ceb35dbcd4d0 100644
+--- a/drivers/usb/misc/yurex.c
++++ b/drivers/usb/misc/yurex.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for Meywa-Denki & KAYAC YUREX
+  *
+diff --git a/drivers/usb/mon/mon_main.c b/drivers/usb/mon/mon_main.c
+index 46847340b819..9812d102a005 100644
+--- a/drivers/usb/mon/mon_main.c
++++ b/drivers/usb/mon/mon_main.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * The USB Monitor, inspired by Dave Harding's USBMon.
+  *
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index b26fffc58446..375958b516e3 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3.h - MediaTek USB3 DRD header
+  *
+diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
+index 947579842ad7..415579fc6d9f 100644
+--- a/drivers/usb/mtu3/mtu3_core.c
++++ b/drivers/usb/mtu3/mtu3_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_core.c - hardware access layer and gadget init/exit of
+  *                     MediaTek usb3 Dual-Role Controller Driver
+diff --git a/drivers/usb/mtu3/mtu3_dr.c b/drivers/usb/mtu3/mtu3_dr.c
+index 560256115b23..fe8ff399777d 100644
+--- a/drivers/usb/mtu3/mtu3_dr.c
++++ b/drivers/usb/mtu3/mtu3_dr.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_dr.c - dual role switch and host glue layer
+  *
+diff --git a/drivers/usb/mtu3/mtu3_dr.h b/drivers/usb/mtu3/mtu3_dr.h
+index 9b228b5811b0..d4d07ac115fd 100644
+--- a/drivers/usb/mtu3/mtu3_dr.h
++++ b/drivers/usb/mtu3/mtu3_dr.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_dr.h - dual role switch and host glue layer header
+  *
+diff --git a/drivers/usb/mtu3/mtu3_gadget.c b/drivers/usb/mtu3/mtu3_gadget.c
+index 434fca58143c..e7eefc516432 100644
+--- a/drivers/usb/mtu3/mtu3_gadget.c
++++ b/drivers/usb/mtu3/mtu3_gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_gadget.c - MediaTek usb3 DRD peripheral support
+  *
+diff --git a/drivers/usb/mtu3/mtu3_gadget_ep0.c b/drivers/usb/mtu3/mtu3_gadget_ep0.c
+index 958d74dd2b78..228444361a24 100644
+--- a/drivers/usb/mtu3/mtu3_gadget_ep0.c
++++ b/drivers/usb/mtu3/mtu3_gadget_ep0.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_gadget_ep0.c - MediaTek USB3 DRD peripheral driver ep0 handling
+  *
+diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
+index e42d308b8dc2..36d6660d09bd 100644
+--- a/drivers/usb/mtu3/mtu3_host.c
++++ b/drivers/usb/mtu3/mtu3_host.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_dr.c - dual role switch and host glue layer
+  *
+diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
+index 06b29664470f..3d9127917981 100644
+--- a/drivers/usb/mtu3/mtu3_hw_regs.h
++++ b/drivers/usb/mtu3/mtu3_hw_regs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
+  *
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index 088e3e685c4f..742b269b6e02 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2016 MediaTek Inc.
+  *
+diff --git a/drivers/usb/mtu3/mtu3_qmu.c b/drivers/usb/mtu3/mtu3_qmu.c
+index 7d9ba8a52368..78328677681e 100644
+--- a/drivers/usb/mtu3/mtu3_qmu.c
++++ b/drivers/usb/mtu3/mtu3_qmu.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_qmu.c - Queue Management Unit driver for device controller
+  *
+diff --git a/drivers/usb/mtu3/mtu3_qmu.h b/drivers/usb/mtu3/mtu3_qmu.h
+index 4dafa16bf120..05cfdfe8be4c 100644
+--- a/drivers/usb/mtu3/mtu3_qmu.h
++++ b/drivers/usb/mtu3/mtu3_qmu.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mtu3_qmu.h - Queue Management Unit driver header
+  *
+diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
+index 02fbb4fe3745..cfaf98251735 100644
+--- a/drivers/usb/musb/am35x.c
++++ b/drivers/usb/musb/am35x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ 
+ /*
+  * Texas Instruments AM35x "glue layer"
+diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
+index 4418574a36a1..b0b2a8ef48ab 100644
+--- a/drivers/usb/musb/blackfin.c
++++ b/drivers/usb/musb/blackfin.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * MUSB OTG controller driver for Blackfin Processors
+  *
+diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h
+index c84dae546dc6..f3cedcf693b2 100644
+--- a/drivers/usb/musb/blackfin.h
++++ b/drivers/usb/musb/blackfin.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2007 by Analog Devices, Inc.
+  *
+diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
+index a13bd3625043..b4d6d9bb3239 100644
+--- a/drivers/usb/musb/cppi_dma.c
++++ b/drivers/usb/musb/cppi_dma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005-2006 by Texas Instruments
+  *
+diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
+index 972bf4210189..685e11868d35 100644
+--- a/drivers/usb/musb/da8xx.c
++++ b/drivers/usb/musb/da8xx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Texas Instruments DA8xx/OMAP-L1x "glue layer"
+  *
+diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
+index 52b491d3d5d8..321199f35881 100644
+--- a/drivers/usb/musb/davinci.c
++++ b/drivers/usb/musb/davinci.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005-2006 by Texas Instruments
+  *
+diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
+index 371baa0ee509..2e507cedf2f4 100644
+--- a/drivers/usb/musb/davinci.h
++++ b/drivers/usb/musb/davinci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005-2006 by Texas Instruments
+  *
+diff --git a/drivers/usb/musb/jz4740.c b/drivers/usb/musb/jz4740.c
+index 40c68c23d553..354d143ad740 100644
+--- a/drivers/usb/musb/jz4740.c
++++ b/drivers/usb/musb/jz4740.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Ingenic JZ4740 "glue layer"
+  *
+diff --git a/drivers/usb/musb/musb_am335x.c b/drivers/usb/musb/musb_am335x.c
+index 1e58ed2361cc..5f04f8e3a640 100644
+--- a/drivers/usb/musb/musb_am335x.c
++++ b/drivers/usb/musb/musb_am335x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/module.h>
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index ff17e94ef465..43af5ee3784b 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver core code
+  *
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index 20f4614178d9..ea4a67486009 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver defines
+  *
+diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c
+index 1ec0a4947b6b..d0dd4f470bbe 100644
+--- a/drivers/usb/musb/musb_cppi41.c
++++ b/drivers/usb/musb/musb_cppi41.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/dmaengine.h>
+diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
+index 9a78877a8afe..345a359de57a 100644
+--- a/drivers/usb/musb/musb_debug.h
++++ b/drivers/usb/musb/musb_debug.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver debug defines
+  *
+diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
+index 952733ceaac8..b91d4b60b8c7 100644
+--- a/drivers/usb/musb/musb_debugfs.c
++++ b/drivers/usb/musb/musb_debugfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver debugfs support
+  *
+diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
+index 04c3bd86bd62..7fea3455cd3b 100644
+--- a/drivers/usb/musb/musb_dma.h
++++ b/drivers/usb/musb/musb_dma.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver DMA controller abstraction
+  *
+diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
+index f6b526606ad1..ba8ea45e58b5 100644
+--- a/drivers/usb/musb/musb_dsps.c
++++ b/drivers/usb/musb/musb_dsps.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Texas Instruments DSPS platforms "glue layer"
+  *
+diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
+index 87f932d4b72c..738c5c39031e 100644
+--- a/drivers/usb/musb/musb_gadget.c
++++ b/drivers/usb/musb/musb_gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver peripheral support
+  *
+diff --git a/drivers/usb/musb/musb_gadget.h b/drivers/usb/musb/musb_gadget.h
+index 0314dfc770c7..c8c9d5565848 100644
+--- a/drivers/usb/musb/musb_gadget.h
++++ b/drivers/usb/musb/musb_gadget.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver peripheral defines
+  *
+diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
+index e85b9c2a4910..fd79b55b96a5 100644
+--- a/drivers/usb/musb/musb_gadget_ep0.c
++++ b/drivers/usb/musb/musb_gadget_ep0.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG peripheral driver ep0 handling
+  *
+diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
+index 802388bb42ba..28e9e6198d9c 100644
+--- a/drivers/usb/musb/musb_host.c
++++ b/drivers/usb/musb/musb_host.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver host support
+  *
+diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
+index 54d02ed032df..686f3dba5e46 100644
+--- a/drivers/usb/musb/musb_host.h
++++ b/drivers/usb/musb/musb_host.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver host defines
+  *
+diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
+index 17a80ae20674..2ebf033ced87 100644
+--- a/drivers/usb/musb/musb_io.h
++++ b/drivers/usb/musb/musb_io.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver register I/O
+  *
+diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
+index cff5bcf0d00f..31f92798b408 100644
+--- a/drivers/usb/musb/musb_regs.h
++++ b/drivers/usb/musb/musb_regs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver register defines
+  *
+diff --git a/drivers/usb/musb/musb_trace.c b/drivers/usb/musb/musb_trace.c
+index 70973d901a21..037509918844 100644
+--- a/drivers/usb/musb/musb_trace.c
++++ b/drivers/usb/musb/musb_trace.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * musb_trace.c - MUSB Controller Trace Support
+  *
+diff --git a/drivers/usb/musb/musb_trace.h b/drivers/usb/musb/musb_trace.h
+index f031c9e74322..669cd1df5bf8 100644
+--- a/drivers/usb/musb/musb_trace.h
++++ b/drivers/usb/musb/musb_trace.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * musb_trace.h - MUSB Controller Trace Support
+  *
+diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
+index 5eca5d2d5e00..76fd93a65e7b 100644
+--- a/drivers/usb/musb/musb_virthub.c
++++ b/drivers/usb/musb/musb_virthub.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver virtual root hub support
+  *
+diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
+index 3620073da58c..d1bb309070a4 100644
+--- a/drivers/usb/musb/musbhsdma.c
++++ b/drivers/usb/musb/musbhsdma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver - support for Mentor's DMA controller
+  *
+diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
+index a3dcbd55e436..51289c0b277e 100644
+--- a/drivers/usb/musb/musbhsdma.h
++++ b/drivers/usb/musb/musbhsdma.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * MUSB OTG driver - support for Mentor's DMA controller
+  *
+diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
+index 456f3e6ecf03..f68053165b05 100644
+--- a/drivers/usb/musb/omap2430.c
++++ b/drivers/usb/musb/omap2430.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005-2007 by Texas Instruments
+  * Some code has been taken from tusb6010.c
+diff --git a/drivers/usb/musb/omap2430.h b/drivers/usb/musb/omap2430.h
+index 1b5e83a9840e..f484ba592d40 100644
+--- a/drivers/usb/musb/omap2430.h
++++ b/drivers/usb/musb/omap2430.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005-2006 by Texas Instruments
+  *
+diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
+index dc353e24d53c..ecc9e1a60f46 100644
+--- a/drivers/usb/musb/sunxi.c
++++ b/drivers/usb/musb/sunxi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Allwinner sun4i MUSB Glue Layer
+  *
+diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
+index 4eb640c54f2c..9ec06c573e96 100644
+--- a/drivers/usb/musb/tusb6010.c
++++ b/drivers/usb/musb/tusb6010.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * TUSB6010 USB 2.0 OTG Dual Role controller
+  *
+diff --git a/drivers/usb/musb/tusb6010.h b/drivers/usb/musb/tusb6010.h
+index 72cdad23ced9..fc8c01d994c6 100644
+--- a/drivers/usb/musb/tusb6010.h
++++ b/drivers/usb/musb/tusb6010.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
+  *
+diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
+index e8060e49b0f4..9db5eb9ba215 100644
+--- a/drivers/usb/musb/tusb6010_omap.c
++++ b/drivers/usb/musb/tusb6010_omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
+  *
+diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
+index 5a572500c418..b29930253acb 100644
+--- a/drivers/usb/musb/ux500.c
++++ b/drivers/usb/musb/ux500.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2010 ST-Ericsson AB
+  * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
+index c92a295049ad..1a14b0e15ba3 100644
+--- a/drivers/usb/musb/ux500_dma.c
++++ b/drivers/usb/musb/ux500_dma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * drivers/usb/musb/ux500_dma.c
+  *
+diff --git a/drivers/usb/phy/of.c b/drivers/usb/phy/of.c
+index 66ffa82457a8..3b0ebdb63488 100644
+--- a/drivers/usb/phy/of.c
++++ b/drivers/usb/phy/of.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB of helper code
+  *
+diff --git a/drivers/usb/phy/phy-ab8500-usb.c b/drivers/usb/phy/phy-ab8500-usb.c
+index 61bf2285d5b1..c1394c524c6b 100644
+--- a/drivers/usb/phy/phy-ab8500-usb.c
++++ b/drivers/usb/phy/phy-ab8500-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB transceiver driver for AB8500 family chips
+  *
+diff --git a/drivers/usb/phy/phy-am335x-control.c b/drivers/usb/phy/phy-am335x-control.c
+index 5f5f19813fde..a3cb25cb74f8 100644
+--- a/drivers/usb/phy/phy-am335x-control.c
++++ b/drivers/usb/phy/phy-am335x-control.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/err.h>
+diff --git a/drivers/usb/phy/phy-am335x.c b/drivers/usb/phy/phy-am335x.c
+index 7e5aece769da..b36fa8b953d0 100644
+--- a/drivers/usb/phy/phy-am335x.c
++++ b/drivers/usb/phy/phy-am335x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/dma-mapping.h>
+diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
+index 9b4354a00ca7..b55d4b800647 100644
+--- a/drivers/usb/phy/phy-fsl-usb.c
++++ b/drivers/usb/phy/phy-fsl-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
+  *
+diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
+index 23149954a09c..5db4668661cd 100644
+--- a/drivers/usb/phy/phy-fsl-usb.h
++++ b/drivers/usb/phy/phy-fsl-usb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+  *
+  * This program is free software; you can redistribute  it and/or modify it
+diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c
+index 89d6e7a5fdb7..055ecf416aae 100644
+--- a/drivers/usb/phy/phy-generic.c
++++ b/drivers/usb/phy/phy-generic.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * NOP USB transceiver for all USB transceiver which are either built-in
+  * into USB IP or which are mostly autonomous.
+diff --git a/drivers/usb/phy/phy-gpio-vbus-usb.c b/drivers/usb/phy/phy-gpio-vbus-usb.c
+index f66120db8a41..d7a3aeaa5ae6 100644
+--- a/drivers/usb/phy/phy-gpio-vbus-usb.c
++++ b/drivers/usb/phy/phy-gpio-vbus-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
+  *
+diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c
+index c6052c814bcc..453dfeab0b58 100644
+--- a/drivers/usb/phy/phy-isp1301-omap.c
++++ b/drivers/usb/phy/phy-isp1301-omap.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * isp1301_omap - ISP 1301 USB transceiver, talking to OMAP OTG controller
+  *
+diff --git a/drivers/usb/phy/phy-isp1301.c b/drivers/usb/phy/phy-isp1301.c
+index f333024660b4..22499abc8272 100644
+--- a/drivers/usb/phy/phy-isp1301.c
++++ b/drivers/usb/phy/phy-isp1301.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * NXP ISP1301 USB transceiver driver
+  *
+diff --git a/drivers/usb/phy/phy-keystone.c b/drivers/usb/phy/phy-keystone.c
+index 01d4e4cdbc79..0670414ccc38 100644
+--- a/drivers/usb/phy/phy-keystone.c
++++ b/drivers/usb/phy/phy-keystone.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * phy-keystone - USB PHY, talking to dwc3 controller in Keystone.
+  *
+diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c
+index 0e315694adc9..8c21b7efb2d8 100644
+--- a/drivers/usb/phy/phy-mv-usb.c
++++ b/drivers/usb/phy/phy-mv-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  * Author: Chao Xie <chao.xie@marvell.com>
+diff --git a/drivers/usb/phy/phy-mv-usb.h b/drivers/usb/phy/phy-mv-usb.h
+index 551da6eb0ba8..6150f6bba30b 100644
+--- a/drivers/usb/phy/phy-mv-usb.h
++++ b/drivers/usb/phy/phy-mv-usb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  *
+diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
+index 0e2f1a36d315..7ffc367a1581 100644
+--- a/drivers/usb/phy/phy-mxs-usb.c
++++ b/drivers/usb/phy/phy-mxs-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2012-2014 Freescale Semiconductor, Inc.
+  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+diff --git a/drivers/usb/phy/phy-omap-otg.c b/drivers/usb/phy/phy-omap-otg.c
+index 800d1d90753d..1ce4a846d9b0 100644
+--- a/drivers/usb/phy/phy-omap-otg.c
++++ b/drivers/usb/phy/phy-omap-otg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * OMAP OTG controller driver
+  *
+diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c
+index bf2c364867a0..3a437bf5e004 100644
+--- a/drivers/usb/phy/phy-tahvo.c
++++ b/drivers/usb/phy/phy-tahvo.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Tahvo USB transceiver driver
+  *
+diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
+index ccc2bf5274b4..1ebfbdef4529 100644
+--- a/drivers/usb/phy/phy-tegra-usb.c
++++ b/drivers/usb/phy/phy-tegra-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2010 Google, Inc.
+  * Copyright (C) 2013 NVIDIA Corporation
+diff --git a/drivers/usb/phy/phy-twl6030-usb.c b/drivers/usb/phy/phy-twl6030-usb.c
+index b5dc077ed7d3..ddcb0dff4d5e 100644
+--- a/drivers/usb/phy/phy-twl6030-usb.c
++++ b/drivers/usb/phy/phy-twl6030-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * twl6030_usb - TWL6030 USB transceiver, talking to OMAP OTG driver.
+  *
+diff --git a/drivers/usb/phy/phy-ulpi-viewport.c b/drivers/usb/phy/phy-ulpi-viewport.c
+index 18bb8264b5a0..394778a5219c 100644
+--- a/drivers/usb/phy/phy-ulpi-viewport.c
++++ b/drivers/usb/phy/phy-ulpi-viewport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 Google, Inc.
+  *
+diff --git a/drivers/usb/phy/phy-ulpi.c b/drivers/usb/phy/phy-ulpi.c
+index f48a7a21e3c2..1a594b356ad8 100644
+--- a/drivers/usb/phy/phy-ulpi.c
++++ b/drivers/usb/phy/phy-ulpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Generic ULPI USB transceiver support
+  *
+diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
+index 89f4ac4cd93e..3405e8e30a01 100644
+--- a/drivers/usb/phy/phy.c
++++ b/drivers/usb/phy/phy.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * phy.c -- USB phy handling
+  *
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index f0ce304c5aaf..f5968a0d392a 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
+index 8c5fc12ad778..416331c6990a 100644
+--- a/drivers/usb/renesas_usbhs/common.h
++++ b/drivers/usb/renesas_usbhs/common.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
+index 5d369b38868a..e3be608993af 100644
+--- a/drivers/usb/renesas_usbhs/fifo.c
++++ b/drivers/usb/renesas_usbhs/fifo.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/fifo.h b/drivers/usb/renesas_usbhs/fifo.h
+index 8b98507d7abc..7a741234c24b 100644
+--- a/drivers/usb/renesas_usbhs/fifo.h
++++ b/drivers/usb/renesas_usbhs/fifo.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/mod.c b/drivers/usb/renesas_usbhs/mod.c
+index 28965ef4f824..c0a0789d8b1e 100644
+--- a/drivers/usb/renesas_usbhs/mod.c
++++ b/drivers/usb/renesas_usbhs/mod.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/mod.h b/drivers/usb/renesas_usbhs/mod.h
+index 1ef5bf604070..5355a13045d9 100644
+--- a/drivers/usb/renesas_usbhs/mod.h
++++ b/drivers/usb/renesas_usbhs/mod.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c
+index c068b673420b..019bbc8bf9b2 100644
+--- a/drivers/usb/renesas_usbhs/mod_gadget.c
++++ b/drivers/usb/renesas_usbhs/mod_gadget.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/mod_host.c b/drivers/usb/renesas_usbhs/mod_host.c
+index e256351cb72d..1ab0ac83b00c 100644
+--- a/drivers/usb/renesas_usbhs/mod_host.c
++++ b/drivers/usb/renesas_usbhs/mod_host.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/pipe.c b/drivers/usb/renesas_usbhs/pipe.c
+index d811f0550c04..3c500aaadf35 100644
+--- a/drivers/usb/renesas_usbhs/pipe.c
++++ b/drivers/usb/renesas_usbhs/pipe.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/pipe.h b/drivers/usb/renesas_usbhs/pipe.h
+index 95185fdb29b1..ed32cb11fe09 100644
+--- a/drivers/usb/renesas_usbhs/pipe.h
++++ b/drivers/usb/renesas_usbhs/pipe.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver
+  *
+diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c
+index 277160bc6f25..b03b3cb36b49 100644
+--- a/drivers/usb/renesas_usbhs/rcar2.c
++++ b/drivers/usb/renesas_usbhs/rcar2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB driver R-Car Gen. 2 initialization and power control
+  *
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index 02b67abfc2a1..0857d0d0abcd 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Renesas USB driver R-Car Gen. 3 initialization and power control
+  *
+diff --git a/drivers/usb/serial/aircable.c b/drivers/usb/serial/aircable.c
+index 569c2200ba42..2ea3fc79acd6 100644
+--- a/drivers/usb/serial/aircable.c
++++ b/drivers/usb/serial/aircable.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * AIRcable USB Bluetooth Dongle Driver.
+  *
+diff --git a/drivers/usb/serial/ark3116.c b/drivers/usb/serial/ark3116.c
+index 0adbd38b4eea..a0cc93b0c64d 100644
+--- a/drivers/usb/serial/ark3116.c
++++ b/drivers/usb/serial/ark3116.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2009 by Bart Hartgers (bart.hartgers+ark3116@gmail.com)
+  * Original version:
+diff --git a/drivers/usb/serial/belkin_sa.c b/drivers/usb/serial/belkin_sa.c
+index 15bc71853db5..6e0c98bde745 100644
+--- a/drivers/usb/serial/belkin_sa.c
++++ b/drivers/usb/serial/belkin_sa.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Belkin USB Serial Adapter Driver
+  *
+diff --git a/drivers/usb/serial/belkin_sa.h b/drivers/usb/serial/belkin_sa.h
+index c74b58ab56f9..345c57f63831 100644
+--- a/drivers/usb/serial/belkin_sa.h
++++ b/drivers/usb/serial/belkin_sa.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Definitions for Belkin USB Serial Adapter Driver
+  *
+diff --git a/drivers/usb/serial/bus.c b/drivers/usb/serial/bus.c
+index 8936a83c96cd..db49e2a4346b 100644
+--- a/drivers/usb/serial/bus.c
++++ b/drivers/usb/serial/bus.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial Converter Bus specific functions
+  *
+diff --git a/drivers/usb/serial/ch341.c b/drivers/usb/serial/ch341.c
+index 578596d301b8..ce021982aad8 100644
+--- a/drivers/usb/serial/ch341.c
++++ b/drivers/usb/serial/ch341.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2007, Frank A Kingswood <frank@kingswood-consulting.co.uk>
+  * Copyright 2007, Werner Cornelius <werner@cornelius-consult.de>
+diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c
+index 43a862a90a77..4f80a422d4e5 100644
+--- a/drivers/usb/serial/console.c
++++ b/drivers/usb/serial/console.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial Console driver
+  *
+diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
+index c931ae689a91..1f7c7949e134 100644
+--- a/drivers/usb/serial/cp210x.c
++++ b/drivers/usb/serial/cp210x.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Silicon Laboratories CP210x USB to RS232 serial adaptor driver
+  *
+diff --git a/drivers/usb/serial/cyberjack.c b/drivers/usb/serial/cyberjack.c
+index 47fbd9f0c0c7..830e793dfe44 100644
+--- a/drivers/usb/serial/cyberjack.c
++++ b/drivers/usb/serial/cyberjack.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  REINER SCT cyberJack pinpad/e-com USB Chipcard Reader Driver
+  *
+diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
+index 90110de715e0..a43ee56d3032 100644
+--- a/drivers/usb/serial/cypress_m8.c
++++ b/drivers/usb/serial/cypress_m8.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Cypress M8 driver
+  *
+diff --git a/drivers/usb/serial/digi_acceleport.c b/drivers/usb/serial/digi_acceleport.c
+index 2ce39af32cfa..fc30c1d04d6e 100644
+--- a/drivers/usb/serial/digi_acceleport.c
++++ b/drivers/usb/serial/digi_acceleport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+ *  Digi AccelePort USB-4 and USB-2 Serial Converters
+ *
+diff --git a/drivers/usb/serial/empeg.c b/drivers/usb/serial/empeg.c
+index 90e603d5f660..b270ff3a721a 100644
+--- a/drivers/usb/serial/empeg.c
++++ b/drivers/usb/serial/empeg.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Empeg empeg-car player driver
+  *
+diff --git a/drivers/usb/serial/f81232.c b/drivers/usb/serial/f81232.c
+index 972f5a5fe577..869bfd05e02e 100644
+--- a/drivers/usb/serial/f81232.c
++++ b/drivers/usb/serial/f81232.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Fintek F81232 USB to serial adaptor driver
+  *
+diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c
+index 3d616a2a9f96..c1cc5ef18bf6 100644
+--- a/drivers/usb/serial/f81534.c
++++ b/drivers/usb/serial/f81534.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * F81532/F81534 USB to Serial Ports Bridge
+  *
+diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
+index 385f2ae3be24..1b037348d3fc 100644
+--- a/drivers/usb/serial/ftdi_sio.c
++++ b/drivers/usb/serial/ftdi_sio.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB FTDI SIO driver
+  *
+diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
+index 91e7e3a166a5..3f9340669e01 100644
+--- a/drivers/usb/serial/garmin_gps.c
++++ b/drivers/usb/serial/garmin_gps.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Garmin GPS driver
+  *
+diff --git a/drivers/usb/serial/generic.c b/drivers/usb/serial/generic.c
+index 35cb8c0e584f..6d64595df6fd 100644
+--- a/drivers/usb/serial/generic.c
++++ b/drivers/usb/serial/generic.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial Converter Generic functions
+  *
+diff --git a/drivers/usb/serial/io_16654.h b/drivers/usb/serial/io_16654.h
+index a53abc9530ff..9a594aa65cd8 100644
+--- a/drivers/usb/serial/io_16654.h
++++ b/drivers/usb/serial/io_16654.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  *
+  *	16654.H		Definitions for 16C654 UART used on EdgePorts
+diff --git a/drivers/usb/serial/io_edgeport.c b/drivers/usb/serial/io_edgeport.c
+index 01f3ac7769f3..3b16370697f4 100644
+--- a/drivers/usb/serial/io_edgeport.c
++++ b/drivers/usb/serial/io_edgeport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Edgeport USB Serial Converter driver
+  *
+diff --git a/drivers/usb/serial/io_edgeport.h b/drivers/usb/serial/io_edgeport.h
+index ad9c1d47a619..657158133a88 100644
+--- a/drivers/usb/serial/io_edgeport.h
++++ b/drivers/usb/serial/io_edgeport.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  *
+  *	io_edgeport.h	Edgeport Linux Interface definitions
+diff --git a/drivers/usb/serial/io_ionsp.h b/drivers/usb/serial/io_ionsp.h
+index 5cc591bae54d..e9d5cde2e4a6 100644
+--- a/drivers/usb/serial/io_ionsp.h
++++ b/drivers/usb/serial/io_ionsp.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  *
+  *	IONSP.H		Definitions for I/O Networks Serial Protocol
+diff --git a/drivers/usb/serial/io_ti.c b/drivers/usb/serial/io_ti.c
+index 6cefb9cb133d..c6fc62447b25 100644
+--- a/drivers/usb/serial/io_ti.c
++++ b/drivers/usb/serial/io_ti.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Edgeport USB Serial Converter driver
+  *
+diff --git a/drivers/usb/serial/io_ti.h b/drivers/usb/serial/io_ti.h
+index 1bd67b24f916..42eb4afc4550 100644
+--- a/drivers/usb/serial/io_ti.h
++++ b/drivers/usb/serial/io_ti.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*****************************************************************************
+  *
+  *	Copyright (C) 1997-2002 Inside Out Networks, Inc.
+diff --git a/drivers/usb/serial/io_usbvend.h b/drivers/usb/serial/io_usbvend.h
+index 6f6a856bc37c..fec5a0aec075 100644
+--- a/drivers/usb/serial/io_usbvend.h
++++ b/drivers/usb/serial/io_usbvend.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /************************************************************************
+  *
+  *	USBVEND.H		Vendor-specific USB definitions
+diff --git a/drivers/usb/serial/ipaq.c b/drivers/usb/serial/ipaq.c
+index cde0dcdce9c4..52da1a82d7f0 100644
+--- a/drivers/usb/serial/ipaq.c
++++ b/drivers/usb/serial/ipaq.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Compaq iPAQ driver
+  *
+diff --git a/drivers/usb/serial/ipw.c b/drivers/usb/serial/ipw.c
+index 8b1cf18a668b..4a534e8037d5 100644
+--- a/drivers/usb/serial/ipw.c
++++ b/drivers/usb/serial/ipw.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * IPWireless 3G UMTS TDD Modem driver (USB connected)
+  *
+diff --git a/drivers/usb/serial/ir-usb.c b/drivers/usb/serial/ir-usb.c
+index f9734a96d516..8109bcfed9f4 100644
+--- a/drivers/usb/serial/ir-usb.c
++++ b/drivers/usb/serial/ir-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB IR Dongle driver
+  *
+diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
+index 18fc992a245f..c0565a352674 100644
+--- a/drivers/usb/serial/iuu_phoenix.c
++++ b/drivers/usb/serial/iuu_phoenix.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Infinity Unlimited USB Phoenix driver
+  *
+diff --git a/drivers/usb/serial/iuu_phoenix.h b/drivers/usb/serial/iuu_phoenix.h
+index b82630a3b8fd..d473cde2aae7 100644
+--- a/drivers/usb/serial/iuu_phoenix.h
++++ b/drivers/usb/serial/iuu_phoenix.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Infinity Unlimited USB Phoenix driver
+  *
+diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c
+index 5662d324edd2..c5e34999bea4 100644
+--- a/drivers/usb/serial/keyspan.c
++++ b/drivers/usb/serial/keyspan.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+   Keyspan USB to Serial Converter driver
+ 
+diff --git a/drivers/usb/serial/keyspan_pda.c b/drivers/usb/serial/keyspan_pda.c
+index f8e8285663a6..40b87c48e585 100644
+--- a/drivers/usb/serial/keyspan_pda.c
++++ b/drivers/usb/serial/keyspan_pda.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Keyspan PDA / Xircom / Entrega Converter driver
+  *
+diff --git a/drivers/usb/serial/kl5kusb105.c b/drivers/usb/serial/kl5kusb105.c
+index 595415e59d5d..e71978840780 100644
+--- a/drivers/usb/serial/kl5kusb105.c
++++ b/drivers/usb/serial/kl5kusb105.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * KLSI KL5KUSB105 chip RS232 converter driver
+  *
+diff --git a/drivers/usb/serial/kobil_sct.c b/drivers/usb/serial/kobil_sct.c
+index 3024b9b25360..32e5b6b3a85a 100644
+--- a/drivers/usb/serial/kobil_sct.c
++++ b/drivers/usb/serial/kobil_sct.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *  KOBIL USB Smart Card Terminal Driver
+  *
+diff --git a/drivers/usb/serial/mct_u232.c b/drivers/usb/serial/mct_u232.c
+index 70f346f1aa86..ef4f9067499a 100644
+--- a/drivers/usb/serial/mct_u232.c
++++ b/drivers/usb/serial/mct_u232.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * MCT (Magic Control Technology Corp.) USB RS232 Converter Driver
+  *
+diff --git a/drivers/usb/serial/mct_u232.h b/drivers/usb/serial/mct_u232.h
+index d325bb8cb583..bd3f40770adb 100644
+--- a/drivers/usb/serial/mct_u232.h
++++ b/drivers/usb/serial/mct_u232.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
+  *
+diff --git a/drivers/usb/serial/metro-usb.c b/drivers/usb/serial/metro-usb.c
+index 3950d44b80f1..3b78b446aadc 100644
+--- a/drivers/usb/serial/metro-usb.c
++++ b/drivers/usb/serial/metro-usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+   Some of this code is credited to Linux USB open source files that are
+   distributed with Linux.
+diff --git a/drivers/usb/serial/mos7720.c b/drivers/usb/serial/mos7720.c
+index a453965f9e9a..b7075252e9ca 100644
+--- a/drivers/usb/serial/mos7720.c
++++ b/drivers/usb/serial/mos7720.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * mos7720.c
+  *   Controls the Moschip 7720 usb to dual port serial converter
+diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
+index 5e490177cf75..a6d39a0a3c46 100644
+--- a/drivers/usb/serial/mos7840.c
++++ b/drivers/usb/serial/mos7840.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+diff --git a/drivers/usb/serial/mxuport.c b/drivers/usb/serial/mxuport.c
+index 3aef091fe88b..1e9430b077f2 100644
+--- a/drivers/usb/serial/mxuport.c
++++ b/drivers/usb/serial/mxuport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *	mxuport.c - MOXA UPort series driver
+  *
+diff --git a/drivers/usb/serial/navman.c b/drivers/usb/serial/navman.c
+index 2a97cdc078d5..ab387a58992b 100644
+--- a/drivers/usb/serial/navman.c
++++ b/drivers/usb/serial/navman.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Navman Serial USB driver
+  *
+diff --git a/drivers/usb/serial/omninet.c b/drivers/usb/serial/omninet.c
+index efcd7feed6f4..8e1406aecafb 100644
+--- a/drivers/usb/serial/omninet.c
++++ b/drivers/usb/serial/omninet.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB ZyXEL omni.net LCD PLUS driver
+  *
+diff --git a/drivers/usb/serial/opticon.c b/drivers/usb/serial/opticon.c
+index 58657d64678b..66e6f77d27c2 100644
+--- a/drivers/usb/serial/opticon.c
++++ b/drivers/usb/serial/opticon.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Opticon USB barcode to serial driver
+  *
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index 0600dadd6a0c..9a777a6d1ad6 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+   USB Driver for GSM modems
+ 
+diff --git a/drivers/usb/serial/oti6858.c b/drivers/usb/serial/oti6858.c
+index b11eead469ee..c6adf41b62da 100644
+--- a/drivers/usb/serial/oti6858.c
++++ b/drivers/usb/serial/oti6858.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Ours Technology Inc. OTi-6858 USB to serial adapter driver.
+  *
+diff --git a/drivers/usb/serial/oti6858.h b/drivers/usb/serial/oti6858.h
+index 704ac3a532b3..9fb62f03005d 100644
+--- a/drivers/usb/serial/oti6858.h
++++ b/drivers/usb/serial/oti6858.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Ours Technology Inc. OTi-6858 USB to serial adapter driver.
+  *
+diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
+index 2153e67eeeee..9dad6fdf5e08 100644
+--- a/drivers/usb/serial/pl2303.c
++++ b/drivers/usb/serial/pl2303.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Prolific PL2303 USB to serial adaptor driver
+  *
+diff --git a/drivers/usb/serial/pl2303.h b/drivers/usb/serial/pl2303.h
+index cec7141245ef..1f17e074a1b8 100644
+--- a/drivers/usb/serial/pl2303.h
++++ b/drivers/usb/serial/pl2303.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Prolific PL2303 USB to serial adaptor driver header file
+  *
+diff --git a/drivers/usb/serial/qcaux.c b/drivers/usb/serial/qcaux.c
+index 6e9f8af96959..f4a5921cc500 100644
+--- a/drivers/usb/serial/qcaux.c
++++ b/drivers/usb/serial/qcaux.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Qualcomm USB Auxiliary Serial Port driver
+  *
+diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c
+index 55a8fb25ce2b..246213c03920 100644
+--- a/drivers/usb/serial/qcserial.c
++++ b/drivers/usb/serial/qcserial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Qualcomm Serial USB driver
+  *
+diff --git a/drivers/usb/serial/quatech2.c b/drivers/usb/serial/quatech2.c
+index 60e17d1444c3..58fe44db82e8 100644
+--- a/drivers/usb/serial/quatech2.c
++++ b/drivers/usb/serial/quatech2.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * usb-serial driver for Quatech USB 2 devices
+  *
+diff --git a/drivers/usb/serial/safe_serial.c b/drivers/usb/serial/safe_serial.c
+index 27d7a7016298..3dd85f025cbe 100644
+--- a/drivers/usb/serial/safe_serial.c
++++ b/drivers/usb/serial/safe_serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Safe Encapsulated USB Serial Driver
+  *
+diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c
+index a9c5564b6b65..75adcf1607a0 100644
+--- a/drivers/usb/serial/sierra.c
++++ b/drivers/usb/serial/sierra.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+   USB Driver for Sierra Wireless
+ 
+diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
+index 5167b6564c8b..48d330ff03fa 100644
+--- a/drivers/usb/serial/spcp8x5.c
++++ b/drivers/usb/serial/spcp8x5.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * spcp8x5 USB to serial adaptor driver
+  *
+diff --git a/drivers/usb/serial/ssu100.c b/drivers/usb/serial/ssu100.c
+index 5aa7bbbeba3d..a7db9aff97a1 100644
+--- a/drivers/usb/serial/ssu100.c
++++ b/drivers/usb/serial/ssu100.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * usb-serial driver for Quatech SSU-100
+  *
+diff --git a/drivers/usb/serial/symbolserial.c b/drivers/usb/serial/symbolserial.c
+index 0d1727232d0c..25d966165211 100644
+--- a/drivers/usb/serial/symbolserial.c
++++ b/drivers/usb/serial/symbolserial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Symbol USB barcode to serial driver
+  *
+diff --git a/drivers/usb/serial/ti_usb_3410_5052.c b/drivers/usb/serial/ti_usb_3410_5052.c
+index 8fc3854e5e69..eb184a78db94 100644
+--- a/drivers/usb/serial/ti_usb_3410_5052.c
++++ b/drivers/usb/serial/ti_usb_3410_5052.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * TI 3410/5052 USB Serial Driver
+  *
+diff --git a/drivers/usb/serial/upd78f0730.c b/drivers/usb/serial/upd78f0730.c
+index 6819a3486e5d..facad97ff487 100644
+--- a/drivers/usb/serial/upd78f0730.c
++++ b/drivers/usb/serial/upd78f0730.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Renesas Electronics uPD78F0730 USB to serial converter driver
+  *
+diff --git a/drivers/usb/serial/usb-serial-simple.c b/drivers/usb/serial/usb-serial-simple.c
+index 2674da40d9cd..1e8c1ae1209c 100644
+--- a/drivers/usb/serial/usb-serial-simple.c
++++ b/drivers/usb/serial/usb-serial-simple.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial "Simple" driver
+  *
+diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
+index bb34f9f7eaf4..1030949a9647 100644
+--- a/drivers/usb/serial/usb-serial.c
++++ b/drivers/usb/serial/usb-serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial Converter driver
+  *
+diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c
+index c593ca8800e5..97e03e538009 100644
+--- a/drivers/usb/serial/usb_debug.c
++++ b/drivers/usb/serial/usb_debug.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Debug cable driver
+  *
+diff --git a/drivers/usb/serial/usb_wwan.c b/drivers/usb/serial/usb_wwan.c
+index 59bfcb3da116..9e48be615b2f 100644
+--- a/drivers/usb/serial/usb_wwan.c
++++ b/drivers/usb/serial/usb_wwan.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+   USB Driver layer for GSM modems
+ 
+diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
+index 879840ec0658..3ad6fb4523b1 100644
+--- a/drivers/usb/serial/visor.c
++++ b/drivers/usb/serial/visor.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB HandSpring Visor, Palm m50x, and Sony Clie driver
+  * (supports all of the Palm OS USB devices)
+diff --git a/drivers/usb/serial/visor.h b/drivers/usb/serial/visor.h
+index 4c456dd69ce5..e87de8c0c239 100644
+--- a/drivers/usb/serial/visor.h
++++ b/drivers/usb/serial/visor.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB HandSpring Visor driver
+  *
+diff --git a/drivers/usb/serial/whiteheat.c b/drivers/usb/serial/whiteheat.c
+index 55cebc1e6fec..1873f1046c58 100644
+--- a/drivers/usb/serial/whiteheat.c
++++ b/drivers/usb/serial/whiteheat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB ConnectTech WhiteHEAT driver
+  *
+diff --git a/drivers/usb/serial/whiteheat.h b/drivers/usb/serial/whiteheat.h
+index 38065df4d2d8..024cc9266ecb 100644
+--- a/drivers/usb/serial/whiteheat.h
++++ b/drivers/usb/serial/whiteheat.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB ConnectTech WhiteHEAT driver
+  *
+diff --git a/drivers/usb/serial/wishbone-serial.c b/drivers/usb/serial/wishbone-serial.c
+index 4fed4a0bd702..8f227c485bfd 100644
+--- a/drivers/usb/serial/wishbone-serial.c
++++ b/drivers/usb/serial/wishbone-serial.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Wishbone-Serial adapter driver
+  *
+diff --git a/drivers/usb/serial/xsens_mt.c b/drivers/usb/serial/xsens_mt.c
+index 3837d5113bb2..ef5f3f655a42 100644
+--- a/drivers/usb/serial/xsens_mt.c
++++ b/drivers/usb/serial/xsens_mt.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Xsens MT USB driver
+  *
+diff --git a/drivers/usb/storage/alauda.c b/drivers/usb/storage/alauda.c
+index 878b4b8761f5..ad71ff132080 100644
+--- a/drivers/usb/storage/alauda.c
++++ b/drivers/usb/storage/alauda.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Alauda-based card readers
+  *
+diff --git a/drivers/usb/storage/cypress_atacb.c b/drivers/usb/storage/cypress_atacb.c
+index 5e4af44d7d9f..a326ad73de16 100644
+--- a/drivers/usb/storage/cypress_atacb.c
++++ b/drivers/usb/storage/cypress_atacb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Support for emulating SAT (ata pass through) on devices based
+  *       on the Cypress USB/ATA bridge supporting ATACB.
+diff --git a/drivers/usb/storage/datafab.c b/drivers/usb/storage/datafab.c
+index 723197af6ec5..f408d26700ce 100644
+--- a/drivers/usb/storage/datafab.c
++++ b/drivers/usb/storage/datafab.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Datafab USB Compact Flash reader
+  *
+diff --git a/drivers/usb/storage/debug.c b/drivers/usb/storage/debug.c
+index 8d20804a59e6..182d2f8e9b2b 100644
+--- a/drivers/usb/storage/debug.c
++++ b/drivers/usb/storage/debug.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Debugging Functions Source Code File
+diff --git a/drivers/usb/storage/debug.h b/drivers/usb/storage/debug.h
+index 8ab73299b650..69dd4c480fb2 100644
+--- a/drivers/usb/storage/debug.h
++++ b/drivers/usb/storage/debug.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Debugging Functions Header File
+diff --git a/drivers/usb/storage/ene_ub6250.c b/drivers/usb/storage/ene_ub6250.c
+index 28100374f7bd..fc733fa14415 100644
+--- a/drivers/usb/storage/ene_ub6250.c
++++ b/drivers/usb/storage/ene_ub6250.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *
+  * This program is free software; you can redistribute it and/or modify it
+diff --git a/drivers/usb/storage/freecom.c b/drivers/usb/storage/freecom.c
+index c0a5d954414b..3b1ffadd07bf 100644
+--- a/drivers/usb/storage/freecom.c
++++ b/drivers/usb/storage/freecom.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Freecom USB/IDE adaptor
+  *
+diff --git a/drivers/usb/storage/initializers.c b/drivers/usb/storage/initializers.c
+index d9d8c17e05d1..9b574caa80ac 100644
+--- a/drivers/usb/storage/initializers.c
++++ b/drivers/usb/storage/initializers.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Special Initializers for certain USB Mass Storage devices
+  *
+diff --git a/drivers/usb/storage/initializers.h b/drivers/usb/storage/initializers.h
+index 039abf4d1cb7..9e6f6efb57f4 100644
+--- a/drivers/usb/storage/initializers.h
++++ b/drivers/usb/storage/initializers.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Header file for Special Initializers for certain USB Mass Storage devices
+  *
+diff --git a/drivers/usb/storage/isd200.c b/drivers/usb/storage/isd200.c
+index 6a7720e66595..0f8603cf2755 100644
+--- a/drivers/usb/storage/isd200.c
++++ b/drivers/usb/storage/isd200.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Transport & Protocol Driver for In-System Design, Inc. ISD200 ASIC
+  *
+diff --git a/drivers/usb/storage/jumpshot.c b/drivers/usb/storage/jumpshot.c
+index 011e5270690a..a1ead5b9d559 100644
+--- a/drivers/usb/storage/jumpshot.c
++++ b/drivers/usb/storage/jumpshot.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Lexar "Jumpshot" Compact Flash reader
+  *
+diff --git a/drivers/usb/storage/karma.c b/drivers/usb/storage/karma.c
+index b05ba4929f00..7ecf2f83f8c9 100644
+--- a/drivers/usb/storage/karma.c
++++ b/drivers/usb/storage/karma.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Rio Karma
+  *
+diff --git a/drivers/usb/storage/onetouch.c b/drivers/usb/storage/onetouch.c
+index acc3d03d8c1e..27873d0ad130 100644
+--- a/drivers/usb/storage/onetouch.c
++++ b/drivers/usb/storage/onetouch.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Support for the Maxtor OneTouch USB hard drive's button
+  *
+diff --git a/drivers/usb/storage/option_ms.c b/drivers/usb/storage/option_ms.c
+index 57282f12317b..7146c83bf82b 100644
+--- a/drivers/usb/storage/option_ms.c
++++ b/drivers/usb/storage/option_ms.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Option High Speed Mobile Devices.
+  *
+diff --git a/drivers/usb/storage/protocol.c b/drivers/usb/storage/protocol.c
+index 74c38870a17e..b8b8e7066a04 100644
+--- a/drivers/usb/storage/protocol.c
++++ b/drivers/usb/storage/protocol.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  *
+diff --git a/drivers/usb/storage/protocol.h b/drivers/usb/storage/protocol.h
+index a55666880b7b..abedf13a8cf1 100644
+--- a/drivers/usb/storage/protocol.h
++++ b/drivers/usb/storage/protocol.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Protocol Functions Header File
+diff --git a/drivers/usb/storage/realtek_cr.c b/drivers/usb/storage/realtek_cr.c
+index ec83b3b5efa9..7d02a7c5cdd6 100644
+--- a/drivers/usb/storage/realtek_cr.c
++++ b/drivers/usb/storage/realtek_cr.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Realtek RTS51xx USB card reader
+  *
+diff --git a/drivers/usb/storage/scsiglue.c b/drivers/usb/storage/scsiglue.c
+index 8cd2926fb1fe..878922fb54b8 100644
+--- a/drivers/usb/storage/scsiglue.c
++++ b/drivers/usb/storage/scsiglue.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * SCSI layer glue code
+diff --git a/drivers/usb/storage/scsiglue.h b/drivers/usb/storage/scsiglue.h
+index d0a331dd9bc5..add14c47ce1d 100644
+--- a/drivers/usb/storage/scsiglue.h
++++ b/drivers/usb/storage/scsiglue.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * SCSI Connecting Glue Header File
+diff --git a/drivers/usb/storage/sddr09.c b/drivers/usb/storage/sddr09.c
+index 44f8ffccd031..b37cb07dfc80 100644
+--- a/drivers/usb/storage/sddr09.c
++++ b/drivers/usb/storage/sddr09.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for SanDisk SDDR-09 SmartMedia reader
+  *
+diff --git a/drivers/usb/storage/sddr55.c b/drivers/usb/storage/sddr55.c
+index 147c50b3e00f..2e76b8e8c6ca 100644
+--- a/drivers/usb/storage/sddr55.c
++++ b/drivers/usb/storage/sddr55.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for SanDisk SDDR-55 SmartMedia reader
+  *
+diff --git a/drivers/usb/storage/shuttle_usbat.c b/drivers/usb/storage/shuttle_usbat.c
+index 3b0294e4df93..3e9da1d257b6 100644
+--- a/drivers/usb/storage/shuttle_usbat.c
++++ b/drivers/usb/storage/shuttle_usbat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for SCM Microsystems (a.k.a. Shuttle) USB-ATAPI cable
+  *
+diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c
+index a3ccb899df60..b31568e8f6c3 100644
+--- a/drivers/usb/storage/transport.c
++++ b/drivers/usb/storage/transport.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  *
+diff --git a/drivers/usb/storage/transport.h b/drivers/usb/storage/transport.h
+index dae3ecd2e6cf..98591db5fb6a 100644
+--- a/drivers/usb/storage/transport.h
++++ b/drivers/usb/storage/transport.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Transport Functions Header File
+diff --git a/drivers/usb/storage/uas.c b/drivers/usb/storage/uas.c
+index 33a6d624c843..4aadb1ccbf1f 100644
+--- a/drivers/usb/storage/uas.c
++++ b/drivers/usb/storage/uas.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Attached SCSI
+  * Note that this is not the same as the USB Mass Storage driver
+diff --git a/drivers/usb/storage/unusual_alauda.h b/drivers/usb/storage/unusual_alauda.h
+index 763bc03032a1..311c5a21ac13 100644
+--- a/drivers/usb/storage/unusual_alauda.h
++++ b/drivers/usb/storage/unusual_alauda.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Alauda-based card readers
+  *
+diff --git a/drivers/usb/storage/unusual_cypress.h b/drivers/usb/storage/unusual_cypress.h
+index e9a2eb88869a..285370f13ee4 100644
+--- a/drivers/usb/storage/unusual_cypress.h
++++ b/drivers/usb/storage/unusual_cypress.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for devices based on the Cypress USB/ATA bridge
+  *	with support for ATACB
+diff --git a/drivers/usb/storage/unusual_datafab.h b/drivers/usb/storage/unusual_datafab.h
+index 5049b6bbe5d5..03c0e72d7b9d 100644
+--- a/drivers/usb/storage/unusual_datafab.h
++++ b/drivers/usb/storage/unusual_datafab.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Datafab USB Compact Flash reader
+  *
+diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
+index d100290628bd..389cb4a1f9ba 100644
+--- a/drivers/usb/storage/unusual_devs.h
++++ b/drivers/usb/storage/unusual_devs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Unusual Devices File
+diff --git a/drivers/usb/storage/unusual_ene_ub6250.h b/drivers/usb/storage/unusual_ene_ub6250.h
+index 5667f5d365c6..c9d9e52d884d 100644
+--- a/drivers/usb/storage/unusual_ene_ub6250.h
++++ b/drivers/usb/storage/unusual_ene_ub6250.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  *
+  * This program is free software; you can redistribute it and/or modify it
+diff --git a/drivers/usb/storage/unusual_freecom.h b/drivers/usb/storage/unusual_freecom.h
+index 1f5aab42ece2..06088feb8f96 100644
+--- a/drivers/usb/storage/unusual_freecom.h
++++ b/drivers/usb/storage/unusual_freecom.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Freecom USB/IDE adaptor
+  *
+diff --git a/drivers/usb/storage/unusual_isd200.h b/drivers/usb/storage/unusual_isd200.h
+index 9b6862ec3d4f..b924e3d75960 100644
+--- a/drivers/usb/storage/unusual_isd200.h
++++ b/drivers/usb/storage/unusual_isd200.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for In-System Design, Inc. ISD200 ASIC
+  *
+diff --git a/drivers/usb/storage/unusual_jumpshot.h b/drivers/usb/storage/unusual_jumpshot.h
+index 413e64fa6b95..1ca977374ba4 100644
+--- a/drivers/usb/storage/unusual_jumpshot.h
++++ b/drivers/usb/storage/unusual_jumpshot.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Lexar "Jumpshot" Compact Flash reader
+  *
+diff --git a/drivers/usb/storage/unusual_karma.h b/drivers/usb/storage/unusual_karma.h
+index e6fad3aeae20..84910d13c80a 100644
+--- a/drivers/usb/storage/unusual_karma.h
++++ b/drivers/usb/storage/unusual_karma.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Rio Karma
+  *
+diff --git a/drivers/usb/storage/unusual_onetouch.h b/drivers/usb/storage/unusual_onetouch.h
+index 425dc22f345a..28d39c4e20e2 100644
+--- a/drivers/usb/storage/unusual_onetouch.h
++++ b/drivers/usb/storage/unusual_onetouch.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for the Maxtor OneTouch USB hard drive's button
+  *
+diff --git a/drivers/usb/storage/unusual_realtek.h b/drivers/usb/storage/unusual_realtek.h
+index 8fe624ad302a..736e4f7ebe10 100644
+--- a/drivers/usb/storage/unusual_realtek.h
++++ b/drivers/usb/storage/unusual_realtek.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for Realtek RTS51xx USB card reader
+  *
+diff --git a/drivers/usb/storage/unusual_sddr09.h b/drivers/usb/storage/unusual_sddr09.h
+index d9d38ac4abf9..1098646d4b75 100644
+--- a/drivers/usb/storage/unusual_sddr09.h
++++ b/drivers/usb/storage/unusual_sddr09.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for SanDisk SDDR-09 SmartMedia reader
+  *
+diff --git a/drivers/usb/storage/unusual_sddr55.h b/drivers/usb/storage/unusual_sddr55.h
+index ebb1d1c6c467..b98c778051b8 100644
+--- a/drivers/usb/storage/unusual_sddr55.h
++++ b/drivers/usb/storage/unusual_sddr55.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for SanDisk SDDR-55 SmartMedia reader
+  *
+diff --git a/drivers/usb/storage/unusual_uas.h b/drivers/usb/storage/unusual_uas.h
+index f15aa47c54a9..3abe950e24e1 100644
+--- a/drivers/usb/storage/unusual_uas.h
++++ b/drivers/usb/storage/unusual_uas.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Attached SCSI devices - Unusual Devices File
+  *
+diff --git a/drivers/usb/storage/unusual_usbat.h b/drivers/usb/storage/unusual_usbat.h
+index 2044ad5ef5e4..ac6bae08ac79 100644
+--- a/drivers/usb/storage/unusual_usbat.h
++++ b/drivers/usb/storage/unusual_usbat.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Unusual Devices File for SCM Microsystems (a.k.a. Shuttle) USB-ATAPI cable
+  *
+diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
+index 0dceb9fa3a06..84b8553944da 100644
+--- a/drivers/usb/storage/usb.c
++++ b/drivers/usb/storage/usb.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  *
+diff --git a/drivers/usb/storage/usb.h b/drivers/usb/storage/usb.h
+index 8fae28b40bb4..aa3da222f6b1 100644
+--- a/drivers/usb/storage/usb.h
++++ b/drivers/usb/storage/usb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage compliant devices
+  * Main Header File
+diff --git a/drivers/usb/storage/usual-tables.c b/drivers/usb/storage/usual-tables.c
+index 499669bcf700..90ac516c1f12 100644
+--- a/drivers/usb/storage/usual-tables.c
++++ b/drivers/usb/storage/usual-tables.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Driver for USB Mass Storage devices
+  * Usual Tables File for usb-storage and libusual
+diff --git a/drivers/usb/typec/typec.c b/drivers/usb/typec/typec.c
+index 24e355ba109d..51fbd9a3ef9f 100644
+--- a/drivers/usb/typec/typec.c
++++ b/drivers/usb/typec/typec.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Type-C Connector Class
+  *
+diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c
+index e9c4e784a9cb..d51535a6b31a 100644
+--- a/drivers/usb/typec/typec_wcove.c
++++ b/drivers/usb/typec/typec_wcove.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /**
+  * typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
+  *
+diff --git a/drivers/usb/typec/ucsi/ucsi.c b/drivers/usb/typec/ucsi/ucsi.c
+index 251f5d66651e..d6e299ff28cf 100644
+--- a/drivers/usb/typec/ucsi/ucsi.c
++++ b/drivers/usb/typec/ucsi/ucsi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Type-C Connector System Software Interface driver
+  *
+diff --git a/drivers/usb/typec/ucsi/ucsi_acpi.c b/drivers/usb/typec/ucsi/ucsi_acpi.c
+index 494d2a49203a..1972507bfe23 100644
+--- a/drivers/usb/typec/ucsi/ucsi_acpi.c
++++ b/drivers/usb/typec/ucsi/ucsi_acpi.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * UCSI ACPI driver
+  *
+diff --git a/drivers/usb/usb-skeleton.c b/drivers/usb/usb-skeleton.c
+index bb0bd732e29a..cc31a1b6c7bd 100644
+--- a/drivers/usb/usb-skeleton.c
++++ b/drivers/usb/usb-skeleton.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Skeleton driver - 2.2
+  *
+diff --git a/drivers/usb/usbip/stub.h b/drivers/usb/usbip/stub.h
+index 84c0599b45b7..fb03061a979e 100644
+--- a/drivers/usb/usbip/stub.h
++++ b/drivers/usb/usbip/stub.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/stub_dev.c b/drivers/usb/usbip/stub_dev.c
+index cc847f2edf38..fa4d107053f0 100644
+--- a/drivers/usb/usbip/stub_dev.c
++++ b/drivers/usb/usbip/stub_dev.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/stub_main.c b/drivers/usb/usbip/stub_main.c
+index 108dd65fbfbc..f595d9d62d94 100644
+--- a/drivers/usb/usbip/stub_main.c
++++ b/drivers/usb/usbip/stub_main.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/stub_rx.c b/drivers/usb/usbip/stub_rx.c
+index 5b807185f79e..874f1d21ba5d 100644
+--- a/drivers/usb/usbip/stub_rx.c
++++ b/drivers/usb/usbip/stub_rx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/stub_tx.c b/drivers/usb/usbip/stub_tx.c
+index 96aa375b80d9..24e6a71f6c91 100644
+--- a/drivers/usb/usbip/stub_tx.c
++++ b/drivers/usb/usbip/stub_tx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/usbip_common.c b/drivers/usb/usbip/usbip_common.c
+index 7f0d22131121..31d9019ea177 100644
+--- a/drivers/usb/usbip/usbip_common.c
++++ b/drivers/usb/usbip/usbip_common.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/usbip_common.h b/drivers/usb/usbip/usbip_common.h
+index c81c44c13a56..0598bb144cc6 100644
+--- a/drivers/usb/usbip/usbip_common.h
++++ b/drivers/usb/usbip/usbip_common.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/usbip_event.c b/drivers/usb/usbip/usbip_event.c
+index f8f7f3803a99..734d44d186e9 100644
+--- a/drivers/usb/usbip/usbip_event.c
++++ b/drivers/usb/usbip/usbip_event.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015 Nobuo Iwata
+diff --git a/drivers/usb/usbip/vhci.h b/drivers/usb/usbip/vhci.h
+index 5cfb59e98e44..04240e450e3f 100644
+--- a/drivers/usb/usbip/vhci.h
++++ b/drivers/usb/usbip/vhci.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015 Nobuo Iwata
+diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c
+index 05aa1ba351b6..d95801e42fe7 100644
+--- a/drivers/usb/usbip/vhci_hcd.c
++++ b/drivers/usb/usbip/vhci_hcd.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015-2016 Nobuo Iwata
+diff --git a/drivers/usb/usbip/vhci_rx.c b/drivers/usb/usbip/vhci_rx.c
+index 1343037d00f9..c7bef8d1db7f 100644
+--- a/drivers/usb/usbip/vhci_rx.c
++++ b/drivers/usb/usbip/vhci_rx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/vhci_sysfs.c b/drivers/usb/usbip/vhci_sysfs.c
+index 4a22a9f06d96..6e6dbc3d184a 100644
+--- a/drivers/usb/usbip/vhci_sysfs.c
++++ b/drivers/usb/usbip/vhci_sysfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  * Copyright (C) 2015-2016 Nobuo Iwata
+diff --git a/drivers/usb/usbip/vhci_tx.c b/drivers/usb/usbip/vhci_tx.c
+index a9a663a578b6..3669fd53c354 100644
+--- a/drivers/usb/usbip/vhci_tx.c
++++ b/drivers/usb/usbip/vhci_tx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2003-2008 Takahiro Hirofuchi
+  *
+diff --git a/drivers/usb/usbip/vudc.h b/drivers/usb/usbip/vudc.h
+index 25e01b09c4c3..44fb24193acd 100644
+--- a/drivers/usb/usbip/vudc.h
++++ b/drivers/usb/usbip/vudc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_dev.c b/drivers/usb/usbip/vudc_dev.c
+index 968471b62cbc..0c07348820ea 100644
+--- a/drivers/usb/usbip/vudc_dev.c
++++ b/drivers/usb/usbip/vudc_dev.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_main.c b/drivers/usb/usbip/vudc_main.c
+index 9e655714e389..63aee6bb0dd9 100644
+--- a/drivers/usb/usbip/vudc_main.c
++++ b/drivers/usb/usbip/vudc_main.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_rx.c b/drivers/usb/usbip/vudc_rx.c
+index d020e72b3122..be847fdd7df9 100644
+--- a/drivers/usb/usbip/vudc_rx.c
++++ b/drivers/usb/usbip/vudc_rx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_sysfs.c b/drivers/usb/usbip/vudc_sysfs.c
+index 7efa374a4970..8fca14efc827 100644
+--- a/drivers/usb/usbip/vudc_sysfs.c
++++ b/drivers/usb/usbip/vudc_sysfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_transfer.c b/drivers/usb/usbip/vudc_transfer.c
+index 4cfd475ee865..11604fa586b4 100644
+--- a/drivers/usb/usbip/vudc_transfer.c
++++ b/drivers/usb/usbip/vudc_transfer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/usbip/vudc_tx.c b/drivers/usb/usbip/vudc_tx.c
+index 3ab4c86486a7..2b954cea8336 100644
+--- a/drivers/usb/usbip/vudc_tx.c
++++ b/drivers/usb/usbip/vudc_tx.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2015 Karol Kosik <karo9@interia.eu>
+  * Copyright (C) 2015-2016 Samsung Electronics
+diff --git a/drivers/usb/wusbcore/cbaf.c b/drivers/usb/wusbcore/cbaf.c
+index aa4e440e9975..5a3ee0d6cf31 100644
+--- a/drivers/usb/wusbcore/cbaf.c
++++ b/drivers/usb/wusbcore/cbaf.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB - Cable Based Association
+  *
+diff --git a/drivers/usb/wusbcore/crypto.c b/drivers/usb/wusbcore/crypto.c
+index 062c205f0046..011ce6a35137 100644
+--- a/drivers/usb/wusbcore/crypto.c
++++ b/drivers/usb/wusbcore/crypto.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Ultra Wide Band
+  * AES-128 CCM Encryption
+diff --git a/drivers/usb/wusbcore/dev-sysfs.c b/drivers/usb/wusbcore/dev-sysfs.c
+index 78212f8180ce..02457f7e2ee3 100644
+--- a/drivers/usb/wusbcore/dev-sysfs.c
++++ b/drivers/usb/wusbcore/dev-sysfs.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB devices
+  * sysfs bindings
+diff --git a/drivers/usb/wusbcore/devconnect.c b/drivers/usb/wusbcore/devconnect.c
+index bf9551735938..18826c98b7d6 100644
+--- a/drivers/usb/wusbcore/devconnect.c
++++ b/drivers/usb/wusbcore/devconnect.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB Wire Adapter: Control/Data Streaming Interface (WUSB[8])
+  * Device Connect handling
+diff --git a/drivers/usb/wusbcore/mmc.c b/drivers/usb/wusbcore/mmc.c
+index 3f485df96226..235099df783e 100644
+--- a/drivers/usb/wusbcore/mmc.c
++++ b/drivers/usb/wusbcore/mmc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB Wire Adapter: Control/Data Streaming Interface (WUSB[8])
+  * MMC (Microscheduled Management Command) handling
+diff --git a/drivers/usb/wusbcore/pal.c b/drivers/usb/wusbcore/pal.c
+index 090f27371a8f..6e47b055ad47 100644
+--- a/drivers/usb/wusbcore/pal.c
++++ b/drivers/usb/wusbcore/pal.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Host Controller
+  * UWB Protocol Adaptation Layer (PAL) glue.
+diff --git a/drivers/usb/wusbcore/reservation.c b/drivers/usb/wusbcore/reservation.c
+index 7b1b2e2fb673..9463afe44c09 100644
+--- a/drivers/usb/wusbcore/reservation.c
++++ b/drivers/usb/wusbcore/reservation.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB cluster reservation management
+  *
+diff --git a/drivers/usb/wusbcore/rh.c b/drivers/usb/wusbcore/rh.c
+index a082fe62b1f0..0fb11cde5ff8 100644
+--- a/drivers/usb/wusbcore/rh.c
++++ b/drivers/usb/wusbcore/rh.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Host Controller
+  * Root Hub operations
+diff --git a/drivers/usb/wusbcore/security.c b/drivers/usb/wusbcore/security.c
+index 170f2c38de9b..1f84d4aea125 100644
+--- a/drivers/usb/wusbcore/security.c
++++ b/drivers/usb/wusbcore/security.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Host Controller
+  * Security support: encryption enablement, etc
+diff --git a/drivers/usb/wusbcore/wa-hc.c b/drivers/usb/wusbcore/wa-hc.c
+index d01496fd27fe..80e539931e34 100644
+--- a/drivers/usb/wusbcore/wa-hc.c
++++ b/drivers/usb/wusbcore/wa-hc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wire Adapter Host Controller Driver
+  * Common items to HWA and DWA based HCDs
+diff --git a/drivers/usb/wusbcore/wa-hc.h b/drivers/usb/wusbcore/wa-hc.h
+index edc7267157f3..ab5fc274a73f 100644
+--- a/drivers/usb/wusbcore/wa-hc.h
++++ b/drivers/usb/wusbcore/wa-hc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * HWA Host Controller Driver
+  * Wire Adapter Control/Data Streaming Iface (WUSB1.0[8])
+diff --git a/drivers/usb/wusbcore/wa-nep.c b/drivers/usb/wusbcore/wa-nep.c
+index e3819fc182b0..4cfc5ba70e62 100644
+--- a/drivers/usb/wusbcore/wa-nep.c
++++ b/drivers/usb/wusbcore/wa-nep.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB Wire Adapter: Control/Data Streaming Interface (WUSB[8])
+  * Notification EndPoint support
+diff --git a/drivers/usb/wusbcore/wa-rpipe.c b/drivers/usb/wusbcore/wa-rpipe.c
+index c7ecdbe19a32..aff01f19f09e 100644
+--- a/drivers/usb/wusbcore/wa-rpipe.c
++++ b/drivers/usb/wusbcore/wa-rpipe.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB Wire Adapter
+  * rpipe management
+diff --git a/drivers/usb/wusbcore/wa-xfer.c b/drivers/usb/wusbcore/wa-xfer.c
+index e70322b1dd02..e9c09155432d 100644
+--- a/drivers/usb/wusbcore/wa-xfer.c
++++ b/drivers/usb/wusbcore/wa-xfer.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * WUSB Wire Adapter
+  * Data transfer and URB enqueing
+diff --git a/drivers/usb/wusbcore/wusbhc.c b/drivers/usb/wusbcore/wusbhc.c
+index 5338e42533c8..ebd07e906906 100644
+--- a/drivers/usb/wusbcore/wusbhc.c
++++ b/drivers/usb/wusbcore/wusbhc.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Host Controller
+  * sysfs glue, wusbcore module support and life cycle management
+diff --git a/drivers/usb/wusbcore/wusbhc.h b/drivers/usb/wusbcore/wusbhc.h
+index 8c5bd000739b..6ccef2d0c7b3 100644
+--- a/drivers/usb/wusbcore/wusbhc.h
++++ b/drivers/usb/wusbcore/wusbhc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Host Controller
+  * Common infrastructure for WHCI and HWA WUSB-HC drivers
+diff --git a/include/linux/usb/association.h b/include/linux/usb/association.h
+index 0a4a18b3c1bb..d7f3cb9b9db5 100644
+--- a/include/linux/usb/association.h
++++ b/include/linux/usb/association.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB - Cable Based Association
+  *
+diff --git a/include/linux/usb/audio-v2.h b/include/linux/usb/audio-v2.h
+index fd73bc0e9027..3119d0ace7aa 100644
+--- a/include/linux/usb/audio-v2.h
++++ b/include/linux/usb/audio-v2.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (c) 2010 Daniel Mack <daniel@caiaq.de>
+  *
+diff --git a/include/linux/usb/audio.h b/include/linux/usb/audio.h
+index 3d84619110a4..170acd500ea1 100644
+--- a/include/linux/usb/audio.h
++++ b/include/linux/usb/audio.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * <linux/usb/audio.h> -- USB Audio definitions.
+  *
+diff --git a/include/linux/usb/c67x00.h b/include/linux/usb/c67x00.h
+index 83c6b45470ca..2fc39e3b7281 100644
+--- a/include/linux/usb/c67x00.h
++++ b/include/linux/usb/c67x00.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * usb_c67x00.h: platform definitions for the Cypress C67X00 USB chip
+  *
+diff --git a/include/linux/usb/cdc-wdm.h b/include/linux/usb/cdc-wdm.h
+index 0b3f4295c025..9b895f93d8de 100644
+--- a/include/linux/usb/cdc-wdm.h
++++ b/include/linux/usb/cdc-wdm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB CDC Device Management subdriver
+  *
+diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h
+index b5706f94ee9e..35d784cf32a4 100644
+--- a/include/linux/usb/cdc.h
++++ b/include/linux/usb/cdc.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB CDC common helpers
+  *
+diff --git a/include/linux/usb/cdc_ncm.h b/include/linux/usb/cdc_ncm.h
+index 1a59699cf82a..1646c06989df 100644
+--- a/include/linux/usb/cdc_ncm.h
++++ b/include/linux/usb/cdc_ncm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+ /*
+  * Copyright (C) ST-Ericsson 2010-2012
+  * Contact: Alexey Orishko <alexey.orishko@stericsson.com>
+diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
+index 590d313b5f39..4b6b9283fa7b 100644
+--- a/include/linux/usb/composite.h
++++ b/include/linux/usb/composite.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * composite.h -- framework for usb gadgets which are composite devices
+  *
+diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
+index e479033bd782..a15ce99dfc2d 100644
+--- a/include/linux/usb/ehci_def.h
++++ b/include/linux/usb/ehci_def.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001-2002 by David Brownell
+  *
+diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h
+index db0431b39a63..dd742afdc03f 100644
+--- a/include/linux/usb/ehci_pdriver.h
++++ b/include/linux/usb/ehci_pdriver.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
+  *
+diff --git a/include/linux/usb/g_hid.h b/include/linux/usb/g_hid.h
+index 50f5745df28c..7581e488c237 100644
+--- a/include/linux/usb/g_hid.h
++++ b/include/linux/usb/g_hid.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * g_hid.h -- Header file for USB HID gadget driver
+  *
+diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
+index 21468a722c4a..d3badbbbda97 100644
+--- a/include/linux/usb/gadget.h
++++ b/include/linux/usb/gadget.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * <linux/usb/gadget.h>
+  *
+diff --git a/include/linux/usb/gpio_vbus.h b/include/linux/usb/gpio_vbus.h
+index 837bba604a0b..804fb06cf6d6 100644
+--- a/include/linux/usb/gpio_vbus.h
++++ b/include/linux/usb/gpio_vbus.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * A simple GPIO VBUS sensing driver for B peripheral only devices
+  * with internal transceivers.
+diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
+index a1f03ebfde47..176900528822 100644
+--- a/include/linux/usb/hcd.h
++++ b/include/linux/usb/hcd.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (c) 2001-2002 by David Brownell
+  *
+diff --git a/include/linux/usb/input.h b/include/linux/usb/input.h
+index 0e010b220e85..974befa72ac0 100644
+--- a/include/linux/usb/input.h
++++ b/include/linux/usb/input.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2005 Dmitry Torokhov
+  *
+diff --git a/include/linux/usb/isp1301.h b/include/linux/usb/isp1301.h
+index d3a851c28b6a..dedb3b2473e8 100644
+--- a/include/linux/usb/isp1301.h
++++ b/include/linux/usb/isp1301.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * NXP ISP1301 USB transceiver driver
+  *
+diff --git a/include/linux/usb/m66592.h b/include/linux/usb/m66592.h
+index a4ba31ab2fed..2dfe68183495 100644
+--- a/include/linux/usb/m66592.h
++++ b/include/linux/usb/m66592.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * M66592 driver platform data
+  *
+diff --git a/include/linux/usb/musb-ux500.h b/include/linux/usb/musb-ux500.h
+index 1e2c7130f6e1..c4b7ad9850ca 100644
+--- a/include/linux/usb/musb-ux500.h
++++ b/include/linux/usb/musb-ux500.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2013 ST-Ericsson AB
+  *
+diff --git a/include/linux/usb/net2280.h b/include/linux/usb/net2280.h
+index 725120224472..08b85caecfaf 100644
+--- a/include/linux/usb/net2280.h
++++ b/include/linux/usb/net2280.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * NetChip 2280 high/full speed USB device controller.
+  * Unlike many such controllers, this one talks PCI.
+diff --git a/include/linux/usb/of.h b/include/linux/usb/of.h
+index 4031f47629ec..6cbe7a5c2b57 100644
+--- a/include/linux/usb/of.h
++++ b/include/linux/usb/of.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * OF helpers for usb devices.
+  *
+diff --git a/include/linux/usb/ohci_pdriver.h b/include/linux/usb/ohci_pdriver.h
+index 012f2b7eb2b6..7eb16cf587ee 100644
+--- a/include/linux/usb/ohci_pdriver.h
++++ b/include/linux/usb/ohci_pdriver.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
+  *
+diff --git a/include/linux/usb/otg-fsm.h b/include/linux/usb/otg-fsm.h
+index a0a8f878503c..e78eb577d0fa 100644
+--- a/include/linux/usb/otg-fsm.h
++++ b/include/linux/usb/otg-fsm.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+  *
+  * This program is free software; you can redistribute  it and/or modify it
+diff --git a/include/linux/usb/phy_companion.h b/include/linux/usb/phy_companion.h
+index edd2ec23d282..407f530061cd 100644
+--- a/include/linux/usb/phy_companion.h
++++ b/include/linux/usb/phy_companion.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * phy-companion.h -- phy companion to indicate the comparator part of PHY
+  *
+diff --git a/include/linux/usb/r8a66597.h b/include/linux/usb/r8a66597.h
+index 55805f9dcf21..c0753d026bbf 100644
+--- a/include/linux/usb/r8a66597.h
++++ b/include/linux/usb/r8a66597.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A66597 driver platform data
+  *
+diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h
+index 00a47d058d83..88b002252551 100644
+--- a/include/linux/usb/renesas_usbhs.h
++++ b/include/linux/usb/renesas_usbhs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-1.0+
+ /*
+  * Renesas USB
+  *
+diff --git a/include/linux/usb/rndis_host.h b/include/linux/usb/rndis_host.h
+index d44ef85db177..809bccd08455 100644
+--- a/include/linux/usb/rndis_host.h
++++ b/include/linux/usb/rndis_host.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Host Side support for RNDIS Networking Links
+  * Copyright (C) 2005 by David Brownell
+diff --git a/include/linux/usb/samsung_usb_phy.h b/include/linux/usb/samsung_usb_phy.h
+index 916782699f1c..dc0071741695 100644
+--- a/include/linux/usb/samsung_usb_phy.h
++++ b/include/linux/usb/samsung_usb_phy.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2012 Samsung Electronics Co.Ltd
+  *		http://www.samsung.com/
+diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
+index e2f0ab07eea5..106551a5616e 100644
+--- a/include/linux/usb/serial.h
++++ b/include/linux/usb/serial.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * USB Serial Converter stuff
+  *
+diff --git a/include/linux/usb/storage.h b/include/linux/usb/storage.h
+index 305ee8db7faf..e0240f864548 100644
+--- a/include/linux/usb/storage.h
++++ b/include/linux/usb/storage.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #ifndef __LINUX_USB_STORAGE_H
+ #define __LINUX_USB_STORAGE_H
+ 
+diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h
+index 1de16c324ec8..d641ea1660b7 100644
+--- a/include/linux/usb/tegra_usb_phy.h
++++ b/include/linux/usb/tegra_usb_phy.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2010 Google, Inc.
+  *
+diff --git a/include/linux/usb/tilegx.h b/include/linux/usb/tilegx.h
+index 2d65e3435680..817908573fe8 100644
+--- a/include/linux/usb/tilegx.h
++++ b/include/linux/usb/tilegx.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright 2012 Tilera Corporation. All Rights Reserved.
+  *
+diff --git a/include/linux/usb/ulpi.h b/include/linux/usb/ulpi.h
+index 5f07407a367a..c515765adab7 100644
+--- a/include/linux/usb/ulpi.h
++++ b/include/linux/usb/ulpi.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * ulpi.h -- ULPI defines and function prorotypes
+  *
+diff --git a/include/linux/usb/usb338x.h b/include/linux/usb/usb338x.h
+index 11525d8d89a7..7189e3387bf9 100644
+--- a/include/linux/usb/usb338x.h
++++ b/include/linux/usb/usb338x.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB 338x super/high/full speed USB device controller.
+  * Unlike many such controllers, this one talks PCI.
+diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h
+index e87a805cbfef..e2ec3582e549 100644
+--- a/include/linux/usb/usbnet.h
++++ b/include/linux/usb/usbnet.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * USB Networking Link Interface
+  *
+diff --git a/include/linux/usb/wusb-wa.h b/include/linux/usb/wusb-wa.h
+index c1257130769b..64a840b5106e 100644
+--- a/include/linux/usb/wusb-wa.h
++++ b/include/linux/usb/wusb-wa.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Wire Adapter constants and structures.
+  *
+diff --git a/include/linux/usb/wusb.h b/include/linux/usb/wusb.h
+index eeb28329fa3c..9e4a3213f2c2 100644
+--- a/include/linux/usb/wusb.h
++++ b/include/linux/usb/wusb.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Wireless USB Standard Definitions
+  * Event Size Tables
+diff --git a/include/linux/usb/xhci-dbgp.h b/include/linux/usb/xhci-dbgp.h
+index 80c1cca1f529..0a37f1283bf0 100644
+--- a/include/linux/usb/xhci-dbgp.h
++++ b/include/linux/usb/xhci-dbgp.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Standalone xHCI debug capability driver
+  *
+diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h
+index 04a26285416c..79aab0065ec8 100644
+--- a/include/linux/usbdevice_fs.h
++++ b/include/linux/usbdevice_fs.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*****************************************************************************/
+ 
+ /*
+-- 
+2.19.0
+
diff --git a/patches/0235-USB-gadget-udc-Remove-redundant-license-text.patch b/patches/0235-USB-gadget-udc-Remove-redundant-license-text.patch
new file mode 100644
index 00000000000000..3bd38afb0f19f7
--- /dev/null
+++ b/patches/0235-USB-gadget-udc-Remove-redundant-license-text.patch
@@ -0,0 +1,1121 @@
+From b84a248245993bdfe08bc9aa11218b11daa2e634 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 15:37:31 +0100
+Subject: [PATCH 0235/1795] USB: gadget: udc: Remove redundant license text
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Now that the SPDX tag is in all USB files, that identifies the license
+in a specific and legally-defined manner.  So the extra GPL text wording
+can be removed as it is no longer needed at all.
+
+This is done on a quest to remove the 700+ different ways that files in
+the kernel describe the GPL license text.  And there's unneeded stuff
+like the address (sometimes incorrect) for the FSF which is never
+needed.
+
+No copyright headers or other non-license-description text was removed.
+
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Vladimir Zapolskiy <vz@mleia.com>
+Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
+Cc: Daniel Mack <daniel@zonque.org>
+Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
+Cc: Michal Simek <michal.simek@xilinx.com>
+Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
+Cc: Raviteja Garimella <raviteja.garimella@broadcom.com>
+Cc: Romain Perier <romain.perier@collabora.com>
+Cc: Johan Hovold <johan@kernel.org>
+Cc: Al Cooper <alcooperx@gmail.com>
+Cc: Srinath Mannam <srinath.mannam@broadcom.com>
+Cc: Roger Quadros <rogerq@ti.com>
+Cc: Krzysztof Opasiak <k.opasiak@samsung.com>
+Cc: Stefan Agner <stefan@agner.ch>
+Cc: Alan Stern <stern@rowland.harvard.edu>
+Cc: "Felix Hädicke" <felixhaedicke@web.de>
+Cc: Peter Chen <peter.chen@nxp.com>
+Cc: Allen Pais <allen.lkml@gmail.com>
+Cc: Yuyang Du <yuyang.du@intel.com>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
+Acked-by: Li Yang <leoyang.li@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 229e3682393c31349539c79131996feeee6d5387)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/amd5536udc.h     |  5 -----
+ drivers/usb/gadget/udc/amd5536udc_pci.c |  5 -----
+ drivers/usb/gadget/udc/at91_udc.c       |  5 -----
+ drivers/usb/gadget/udc/at91_udc.h       |  5 -----
+ drivers/usb/gadget/udc/atmel_usba_udc.c |  4 ----
+ drivers/usb/gadget/udc/atmel_usba_udc.h |  4 ----
+ drivers/usb/gadget/udc/bcm63xx_udc.c    |  5 -----
+ drivers/usb/gadget/udc/bdc/bdc.h        |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_cmd.c    |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_cmd.h    |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_core.c   |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_dbg.c    |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_dbg.h    |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_ep.c     |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_ep.h     |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_pci.c    |  6 ------
+ drivers/usb/gadget/udc/bdc/bdc_udc.c    |  6 ------
+ drivers/usb/gadget/udc/core.c           | 12 ------------
+ drivers/usb/gadget/udc/dummy_hcd.c      |  5 -----
+ drivers/usb/gadget/udc/fotg210-udc.c    |  4 ----
+ drivers/usb/gadget/udc/fotg210.h        |  5 -----
+ drivers/usb/gadget/udc/fsl_mxc_udc.c    |  5 -----
+ drivers/usb/gadget/udc/fsl_qe_udc.c     |  5 -----
+ drivers/usb/gadget/udc/fsl_qe_udc.h     |  5 -----
+ drivers/usb/gadget/udc/fsl_udc_core.c   |  5 -----
+ drivers/usb/gadget/udc/fsl_usb2_udc.h   |  5 -----
+ drivers/usb/gadget/udc/fusb300_udc.c    |  4 ----
+ drivers/usb/gadget/udc/fusb300_udc.h    |  4 ----
+ drivers/usb/gadget/udc/goku_udc.c       |  4 ----
+ drivers/usb/gadget/udc/goku_udc.h       |  4 ----
+ drivers/usb/gadget/udc/gr_udc.c         |  5 -----
+ drivers/usb/gadget/udc/gr_udc.h         |  5 -----
+ drivers/usb/gadget/udc/lpc32xx_udc.c    | 14 --------------
+ drivers/usb/gadget/udc/m66592-udc.c     |  4 ----
+ drivers/usb/gadget/udc/m66592-udc.h     |  4 ----
+ drivers/usb/gadget/udc/mv_u3d.h         |  4 ----
+ drivers/usb/gadget/udc/mv_u3d_core.c    |  4 ----
+ drivers/usb/gadget/udc/mv_udc.h         |  5 -----
+ drivers/usb/gadget/udc/mv_udc_core.c    |  5 -----
+ drivers/usb/gadget/udc/net2272.c        | 14 --------------
+ drivers/usb/gadget/udc/net2272.h        | 14 --------------
+ drivers/usb/gadget/udc/net2280.c        |  5 -----
+ drivers/usb/gadget/udc/net2280.h        |  5 -----
+ drivers/usb/gadget/udc/omap_udc.c       |  5 -----
+ drivers/usb/gadget/udc/pch_udc.c        |  4 ----
+ drivers/usb/gadget/udc/pxa25x_udc.c     |  5 -----
+ drivers/usb/gadget/udc/pxa25x_udc.h     |  6 ------
+ drivers/usb/gadget/udc/pxa27x_udc.c     |  5 -----
+ drivers/usb/gadget/udc/pxa27x_udc.h     |  5 -----
+ drivers/usb/gadget/udc/r8a66597-udc.c   |  4 ----
+ drivers/usb/gadget/udc/r8a66597-udc.h   |  4 ----
+ drivers/usb/gadget/udc/renesas_usb3.c   |  4 ----
+ drivers/usb/gadget/udc/s3c-hsudc.c      |  6 +-----
+ drivers/usb/gadget/udc/s3c2410_udc.c    |  5 -----
+ drivers/usb/gadget/udc/s3c2410_udc.h    |  5 -----
+ drivers/usb/gadget/udc/snps_udc_core.c  |  5 -----
+ drivers/usb/gadget/udc/snps_udc_plat.c  |  9 ---------
+ drivers/usb/gadget/udc/trace.c          |  9 ---------
+ drivers/usb/gadget/udc/trace.h          | 12 ------------
+ drivers/usb/gadget/udc/udc-xilinx.c     |  6 ------
+ 60 files changed, 1 insertion(+), 346 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/amd5536udc.h b/drivers/usb/gadget/udc/amd5536udc.h
+index 5a92388ef8bb..dfdef6a28904 100644
+--- a/drivers/usb/gadget/udc/amd5536udc.h
++++ b/drivers/usb/gadget/udc/amd5536udc.h
+@@ -4,11 +4,6 @@
+  *
+  * Copyright (C) 2007 AMD (http://www.amd.com)
+  * Author: Thomas Dahlmann
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef AMD5536UDC_H
+diff --git a/drivers/usb/gadget/udc/amd5536udc_pci.c b/drivers/usb/gadget/udc/amd5536udc_pci.c
+index cf9117e84534..57b6f66331cf 100644
+--- a/drivers/usb/gadget/udc/amd5536udc_pci.c
++++ b/drivers/usb/gadget/udc/amd5536udc_pci.c
+@@ -4,11 +4,6 @@
+  *
+  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
+  * Author: Thomas Dahlmann
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ /*
+diff --git a/drivers/usb/gadget/udc/at91_udc.c b/drivers/usb/gadget/udc/at91_udc.c
+index 972f78409df7..bfe278294e88 100644
+--- a/drivers/usb/gadget/udc/at91_udc.c
++++ b/drivers/usb/gadget/udc/at91_udc.c
+@@ -5,11 +5,6 @@
+  * Copyright (C) 2004 by Thomas Rathbone
+  * Copyright (C) 2005 by HP Labs
+  * Copyright (C) 2005 by David Brownell
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #undef	VERBOSE_DEBUG
+diff --git a/drivers/usb/gadget/udc/at91_udc.h b/drivers/usb/gadget/udc/at91_udc.h
+index 9581a868032e..fd58c5b81826 100644
+--- a/drivers/usb/gadget/udc/at91_udc.h
++++ b/drivers/usb/gadget/udc/at91_udc.h
+@@ -3,11 +3,6 @@
+  * Copyright (C) 2004 by Thomas Rathbone, HP Labs
+  * Copyright (C) 2005 by Ivan Kokshaysky
+  * Copyright (C) 2006 by SAN People
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef AT91_UDC_H
+diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
+index 12543decf9ab..075eaaa8a408 100644
+--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
++++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
+@@ -3,10 +3,6 @@
+  * Driver for the Atmel USBA high speed USB device controller
+  *
+  * Copyright (C) 2005-2007 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #include <linux/clk.h>
+ #include <linux/clk/at91_pmc.h>
+diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.h b/drivers/usb/gadget/udc/atmel_usba_udc.h
+index 10df5e4aaeb2..860a00a6fdd0 100644
+--- a/drivers/usb/gadget/udc/atmel_usba_udc.h
++++ b/drivers/usb/gadget/udc/atmel_usba_udc.h
+@@ -3,10 +3,6 @@
+  * Driver for the Atmel USBA high speed USB device controller
+  *
+  * Copyright (C) 2005-2007 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ #ifndef __LINUX_USB_GADGET_USBA_UDC_H__
+ #define __LINUX_USB_GADGET_USBA_UDC_H__
+diff --git a/drivers/usb/gadget/udc/bcm63xx_udc.c b/drivers/usb/gadget/udc/bcm63xx_udc.c
+index 403cb339fd7b..29f254793592 100644
+--- a/drivers/usb/gadget/udc/bcm63xx_udc.c
++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c
+@@ -4,11 +4,6 @@
+  *
+  * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
+  * Copyright (C) 2012 Broadcom Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/bitops.h>
+diff --git a/drivers/usb/gadget/udc/bdc/bdc.h b/drivers/usb/gadget/udc/bdc/bdc.h
+index 960620bccc25..6e1e881dc51e 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc.h
++++ b/drivers/usb/gadget/udc/bdc/bdc.h
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ 
+ #ifndef	__LINUX_BDC_H__
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_cmd.c b/drivers/usb/gadget/udc/bdc/bdc_cmd.c
+index ad3240375f87..6305bf2c8b59 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_cmd.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_cmd.c
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #include <linux/scatterlist.h>
+ #include <linux/slab.h>
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_cmd.h b/drivers/usb/gadget/udc/bdc/bdc_cmd.h
+index 64648fbef233..29cc988a671a 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_cmd.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_cmd.h
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #ifndef __LINUX_BDC_CMD_H__
+ #define __LINUX_BDC_CMD_H__
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_core.c b/drivers/usb/gadget/udc/bdc/bdc_core.c
+index 2ab6a6b45f9e..d39f070acbd7 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_core.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_core.c
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_dbg.c b/drivers/usb/gadget/udc/bdc/bdc_dbg.c
+index 11216cd6cb94..7ba7448ad743 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_dbg.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_dbg.c
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ 
+ #include "bdc.h"
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_dbg.h b/drivers/usb/gadget/udc/bdc/bdc_dbg.h
+index f62d59b30a3e..373d5abffbb8 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_dbg.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_dbg.h
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #ifndef __LINUX_BDC_DBG_H__
+ #define __LINUX_BDC_DBG_H__
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.c b/drivers/usb/gadget/udc/bdc/bdc_ep.c
+index e9fda8e6e87d..f40d4c13cfa4 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_ep.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_ep.c
+@@ -7,12 +7,6 @@
+  * Author: Ashwini Pahuja
+  *
+  * Based on drivers under drivers/usb/
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #include <linux/module.h>
+ #include <linux/pci.h>
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.h b/drivers/usb/gadget/udc/bdc/bdc_ep.h
+index db52fc78c8bf..a37ff8033b4f 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_ep.h
++++ b/drivers/usb/gadget/udc/bdc/bdc_ep.h
+@@ -5,12 +5,6 @@
+  * Copyright (C) 2014 Broadcom Corporation
+  *
+  * Author: Ashwini Pahuja
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #ifndef __LINUX_BDC_EP_H__
+ #define __LINUX_BDC_EP_H__
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_pci.c b/drivers/usb/gadget/udc/bdc/bdc_pci.c
+index 1fec9c4fdadd..6dbc489513cd 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_pci.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_pci.c
+@@ -7,12 +7,6 @@
+  * Author: Ashwini Pahuja
+  *
+  * Based on drivers under drivers/usb/
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_udc.c b/drivers/usb/gadget/udc/bdc/bdc_udc.c
+index 492b8b872d2c..7bfd58c846f7 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_udc.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_udc.c
+@@ -7,12 +7,6 @@
+  * Author: Ashwini Pahuja
+  *
+  * Based on drivers under drivers/usb/gadget/udc/
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  */
+ #include <linux/module.h>
+ #include <linux/pci.h>
+diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
+index 9f928875d411..2908c1a0eb6d 100644
+--- a/drivers/usb/gadget/udc/core.c
++++ b/drivers/usb/gadget/udc/core.c
+@@ -4,18 +4,6 @@
+  *
+  * Copyright (C) 2010 Texas Instruments
+  * Author: Felipe Balbi <balbi@ti.com>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2  of
+- * the License as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/dummy_hcd.c b/drivers/usb/gadget/udc/dummy_hcd.c
+index af3dc1d33683..2edca6213a8b 100644
+--- a/drivers/usb/gadget/udc/dummy_hcd.c
++++ b/drivers/usb/gadget/udc/dummy_hcd.c
+@@ -6,11 +6,6 @@
+  *
+  * Copyright (C) 2003 David Brownell
+  * Copyright (C) 2003-2005 Alan Stern
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ 
+diff --git a/drivers/usb/gadget/udc/fotg210-udc.c b/drivers/usb/gadget/udc/fotg210-udc.c
+index 6a7e0e26a1d1..53a48f561458 100644
+--- a/drivers/usb/gadget/udc/fotg210-udc.c
++++ b/drivers/usb/gadget/udc/fotg210-udc.c
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2013 Faraday Technology Corporation
+  *
+  * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #include <linux/dma-mapping.h>
+diff --git a/drivers/usb/gadget/udc/fotg210.h b/drivers/usb/gadget/udc/fotg210.h
+index 2c825a884ebc..08c32957503b 100644
+--- a/drivers/usb/gadget/udc/fotg210.h
++++ b/drivers/usb/gadget/udc/fotg210.h
+@@ -4,11 +4,6 @@
+  *
+  * Copyright (C) 2013 Faraday Technology Corporation
+  * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/fsl_mxc_udc.c b/drivers/usb/gadget/udc/fsl_mxc_udc.c
+index 089fbfc44da7..f29cf5c6160c 100644
+--- a/drivers/usb/gadget/udc/fsl_mxc_udc.c
++++ b/drivers/usb/gadget/udc/fsl_mxc_udc.c
+@@ -6,11 +6,6 @@
+  * Description:
+  * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
+  * driver to function correctly on these systems.
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+  */
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c b/drivers/usb/gadget/udc/fsl_qe_udc.c
+index 228577c6c180..2707be628298 100644
+--- a/drivers/usb/gadget/udc/fsl_qe_udc.c
++++ b/drivers/usb/gadget/udc/fsl_qe_udc.c
+@@ -12,11 +12,6 @@
+  * Freescle QE/CPM USB Pheripheral Controller Driver
+  * The controller can be found on MPC8360, MPC8272, and etc.
+  * MPC8360 Rev 1.1 may need QE mircocode update
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation;  either version 2 of the License, or (at your
+- * option) any later version.
+  */
+ 
+ #undef USB_TRACE
+diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.h b/drivers/usb/gadget/udc/fsl_qe_udc.h
+index 2b1aec81c397..2c537a904ee7 100644
+--- a/drivers/usb/gadget/udc/fsl_qe_udc.h
++++ b/drivers/usb/gadget/udc/fsl_qe_udc.h
+@@ -9,11 +9,6 @@
+  *
+  * Description:
+  * Freescale USB device/endpoint management registers
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or (at
+- * your option) any later version.
+  */
+ 
+ #ifndef __FSL_QE_UDC_H
+diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
+index e728a7f481d9..f210cfdb9d44 100644
+--- a/drivers/usb/gadget/udc/fsl_udc_core.c
++++ b/drivers/usb/gadget/udc/fsl_udc_core.c
+@@ -11,11 +11,6 @@
+  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
+  * The driver is previously named as mpc_udc.  Based on bare board
+  * code from Dave Liu and Shlomi Gridish.
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+  */
+ 
+ #undef VERBOSE
+diff --git a/drivers/usb/gadget/udc/fsl_usb2_udc.h b/drivers/usb/gadget/udc/fsl_usb2_udc.h
+index e5a25ef5803b..4ba651ae9048 100644
+--- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
++++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
+@@ -3,11 +3,6 @@
+  * Copyright (C) 2004,2012 Freescale Semiconductor, Inc
+  * All rights reserved.
+  *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+  * Freescale USB device/endpoint management registers
+  */
+ #ifndef __FSL_USB2_UDC_H
+diff --git a/drivers/usb/gadget/udc/fusb300_udc.c b/drivers/usb/gadget/udc/fusb300_udc.c
+index e05946c421ed..263804d154a7 100644
+--- a/drivers/usb/gadget/udc/fusb300_udc.c
++++ b/drivers/usb/gadget/udc/fusb300_udc.c
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2010 Faraday Technology Corp.
+  *
+  * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ #include <linux/dma-mapping.h>
+ #include <linux/err.h>
+diff --git a/drivers/usb/gadget/udc/fusb300_udc.h b/drivers/usb/gadget/udc/fusb300_udc.h
+index 4b055ef31cc1..eb3d6d379ba7 100644
+--- a/drivers/usb/gadget/udc/fusb300_udc.h
++++ b/drivers/usb/gadget/udc/fusb300_udc.h
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2010 Faraday Technology Corp.
+  *
+  * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ 
+diff --git a/drivers/usb/gadget/udc/goku_udc.c b/drivers/usb/gadget/udc/goku_udc.c
+index f90a82a739c4..41590ac57d7d 100644
+--- a/drivers/usb/gadget/udc/goku_udc.c
++++ b/drivers/usb/gadget/udc/goku_udc.c
+@@ -6,10 +6,6 @@
+  *      by Stuart Lynne, Tom Rushworth, and Bruce Balden
+  * Copyright (C) 2002 Toshiba Corporation
+  * Copyright (C) 2003 MontaVista Software (source@mvista.com)
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2.  This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ /*
+diff --git a/drivers/usb/gadget/udc/goku_udc.h b/drivers/usb/gadget/udc/goku_udc.h
+index 99a01453df06..70023d401079 100644
+--- a/drivers/usb/gadget/udc/goku_udc.h
++++ b/drivers/usb/gadget/udc/goku_udc.h
+@@ -6,10 +6,6 @@
+  *      by Stuart Lynne, Tom Rushworth, and Bruce Balden
+  * Copyright (C) 2002 Toshiba Corporation
+  * Copyright (C) 2003 MontaVista Software (source@mvista.com)
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2.  This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ /*
+diff --git a/drivers/usb/gadget/udc/gr_udc.c b/drivers/usb/gadget/udc/gr_udc.c
+index 675aa1043be4..936ec65c09b3 100644
+--- a/drivers/usb/gadget/udc/gr_udc.c
++++ b/drivers/usb/gadget/udc/gr_udc.c
+@@ -10,11 +10,6 @@
+  * Full documentation of the GRUSBDC core can be found here:
+  * http://www.gaisler.com/products/grlib/grip.pdf
+  *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  * Contributors:
+  * - Andreas Larsson <andreas@gaisler.com>
+  * - Marko Isomaki
+diff --git a/drivers/usb/gadget/udc/gr_udc.h b/drivers/usb/gadget/udc/gr_udc.h
+index 6c08ddf03521..3e913268c8c5 100644
+--- a/drivers/usb/gadget/udc/gr_udc.h
++++ b/drivers/usb/gadget/udc/gr_udc.h
+@@ -10,11 +10,6 @@
+  * Full documentation of the GRUSBDC core can be found here:
+  * http://www.gaisler.com/products/grlib/grip.pdf
+  *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+  * Contributors:
+  * - Andreas Larsson <andreas@gaisler.com>
+  * - Marko Isomaki
+diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c
+index 7dcd0904bf25..b0781771704e 100644
+--- a/drivers/usb/gadget/udc/lpc32xx_udc.c
++++ b/drivers/usb/gadget/udc/lpc32xx_udc.c
+@@ -13,20 +13,6 @@
+  *
+  * Note: This driver is based on original work done by Mike James for
+  *       the LPC3180.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/usb/gadget/udc/m66592-udc.c b/drivers/usb/gadget/udc/m66592-udc.c
+index 39076551e325..1b43a6e95d70 100644
+--- a/drivers/usb/gadget/udc/m66592-udc.c
++++ b/drivers/usb/gadget/udc/m66592-udc.c
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2006-2007 Renesas Solutions Corp.
+  *
+  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/m66592-udc.h b/drivers/usb/gadget/udc/m66592-udc.h
+index 4a62b4fda942..01a64685b8a3 100644
+--- a/drivers/usb/gadget/udc/m66592-udc.h
++++ b/drivers/usb/gadget/udc/m66592-udc.h
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2006-2007 Renesas Solutions Corp.
+  *
+  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #ifndef __M66592_UDC_H__
+diff --git a/drivers/usb/gadget/udc/mv_u3d.h b/drivers/usb/gadget/udc/mv_u3d.h
+index 4c7812429920..982625b7197a 100644
+--- a/drivers/usb/gadget/udc/mv_u3d.h
++++ b/drivers/usb/gadget/udc/mv_u3d.h
+@@ -1,10 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+  */
+ 
+ #ifndef __MV_U3D_H
+diff --git a/drivers/usb/gadget/udc/mv_u3d_core.c b/drivers/usb/gadget/udc/mv_u3d_core.c
+index 6f336fe8bbef..35e02a8d0091 100644
+--- a/drivers/usb/gadget/udc/mv_u3d_core.c
++++ b/drivers/usb/gadget/udc/mv_u3d_core.c
+@@ -1,10 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/mv_udc.h b/drivers/usb/gadget/udc/mv_udc.h
+index 4acf7edf4d86..b3f759c0962c 100644
+--- a/drivers/usb/gadget/udc/mv_udc.h
++++ b/drivers/usb/gadget/udc/mv_udc.h
+@@ -1,11 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+  */
+ 
+ #ifndef __MV_UDC_H
+diff --git a/drivers/usb/gadget/udc/mv_udc_core.c b/drivers/usb/gadget/udc/mv_udc_core.c
+index df4065cf5fcd..95f52232493b 100644
+--- a/drivers/usb/gadget/udc/mv_udc_core.c
++++ b/drivers/usb/gadget/udc/mv_udc_core.c
+@@ -3,11 +3,6 @@
+  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+  * Author: Chao Xie <chao.xie@marvell.com>
+  *	   Neil Zhang <zhangwm@marvell.com>
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/net2272.c b/drivers/usb/gadget/udc/net2272.c
+index a3018f93df58..660878a19505 100644
+--- a/drivers/usb/gadget/udc/net2272.c
++++ b/drivers/usb/gadget/udc/net2272.c
+@@ -4,20 +4,6 @@
+  *
+  * Copyright (C) 2005-2006 PLX Technology, Inc.
+  * Copyright (C) 2006-2011 Analog Devices, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #include <linux/delay.h>
+diff --git a/drivers/usb/gadget/udc/net2272.h b/drivers/usb/gadget/udc/net2272.h
+index f0212cf042a2..8e644627992d 100644
+--- a/drivers/usb/gadget/udc/net2272.h
++++ b/drivers/usb/gadget/udc/net2272.h
+@@ -4,20 +4,6 @@
+  *
+  * Copyright (C) 2005-2006 PLX Technology, Inc.
+  * Copyright (C) 2006-2011 Analog Devices, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+ #ifndef __NET2272_H__
+diff --git a/drivers/usb/gadget/udc/net2280.c b/drivers/usb/gadget/udc/net2280.c
+index a0b2ab0c04f7..318246d8b2e2 100644
+--- a/drivers/usb/gadget/udc/net2280.c
++++ b/drivers/usb/gadget/udc/net2280.c
+@@ -32,11 +32,6 @@
+  *
+  * Modified Ricardo Ribalda Qtechnology AS  to provide compatibility
+  *	with usb 338x chip. Based on PLX driver
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/net2280.h b/drivers/usb/gadget/udc/net2280.h
+index 18a881e7f93f..b65a797544d7 100644
+--- a/drivers/usb/gadget/udc/net2280.h
++++ b/drivers/usb/gadget/udc/net2280.h
+@@ -8,11 +8,6 @@
+  * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
+  * Copyright (C) 2003 David Brownell
+  * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/usb/net2280.h>
+diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c
+index 5531ea492ed2..fc7f810baef7 100644
+--- a/drivers/usb/gadget/udc/omap_udc.c
++++ b/drivers/usb/gadget/udc/omap_udc.c
+@@ -6,11 +6,6 @@
+  * Copyright (C) 2004-2005 David Brownell
+  *
+  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #undef	DEBUG
+diff --git a/drivers/usb/gadget/udc/pch_udc.c b/drivers/usb/gadget/udc/pch_udc.c
+index cc24334504b8..afaea11ec771 100644
+--- a/drivers/usb/gadget/udc/pch_udc.c
++++ b/drivers/usb/gadget/udc/pch_udc.c
+@@ -1,10 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/pxa25x_udc.c b/drivers/usb/gadget/udc/pxa25x_udc.c
+index ffbd4dd84c15..da0daa1432de 100644
+--- a/drivers/usb/gadget/udc/pxa25x_udc.c
++++ b/drivers/usb/gadget/udc/pxa25x_udc.c
+@@ -7,11 +7,6 @@
+  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
+  * Copyright (C) 2003 David Brownell
+  * Copyright (C) 2003 Joshua Wise
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ /* #define VERBOSE_DEBUG */
+diff --git a/drivers/usb/gadget/udc/pxa25x_udc.h b/drivers/usb/gadget/udc/pxa25x_udc.h
+index 1532e7e71f99..ccc6b921f067 100644
+--- a/drivers/usb/gadget/udc/pxa25x_udc.h
++++ b/drivers/usb/gadget/udc/pxa25x_udc.h
+@@ -4,12 +4,6 @@
+  *
+  * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+  * Copyright (C) 2003 David Brownell
+- *
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef __LINUX_USB_GADGET_PXA25X_H
+diff --git a/drivers/usb/gadget/udc/pxa27x_udc.c b/drivers/usb/gadget/udc/pxa27x_udc.c
+index 14606f340325..be2761f1b3f5 100644
+--- a/drivers/usb/gadget/udc/pxa27x_udc.c
++++ b/drivers/usb/gadget/udc/pxa27x_udc.c
+@@ -4,11 +4,6 @@
+  *
+  * Inspired by original driver by Frank Becker, David Brownell, and others.
+  * Copyright (C) 2008 Robert Jarzmik
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/gadget/udc/pxa27x_udc.h b/drivers/usb/gadget/udc/pxa27x_udc.h
+index cfdece686abe..1128d39a4255 100644
+--- a/drivers/usb/gadget/udc/pxa27x_udc.h
++++ b/drivers/usb/gadget/udc/pxa27x_udc.h
+@@ -5,11 +5,6 @@
+  *
+  * Inspired by original driver by Frank Becker, David Brownell, and others.
+  * Copyright (C) 2008 Robert Jarzmik
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef __LINUX_USB_GADGET_PXA27X_H
+diff --git a/drivers/usb/gadget/udc/r8a66597-udc.c b/drivers/usb/gadget/udc/r8a66597-udc.c
+index 8d876d90b7ff..5f0618716ca7 100644
+--- a/drivers/usb/gadget/udc/r8a66597-udc.c
++++ b/drivers/usb/gadget/udc/r8a66597-udc.c
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2006-2009 Renesas Solutions Corp.
+  *
+  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/r8a66597-udc.h b/drivers/usb/gadget/udc/r8a66597-udc.h
+index 0f6d41e61841..9a115caba661 100644
+--- a/drivers/usb/gadget/udc/r8a66597-udc.h
++++ b/drivers/usb/gadget/udc/r8a66597-udc.h
+@@ -5,10 +5,6 @@
+  * Copyright (C) 2007-2009 Renesas Solutions Corp.
+  *
+  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #ifndef __R8A66597_H__
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 9f68b46d5d1a..7e04b5c0fd32 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -3,10 +3,6 @@
+  * Renesas USB3.0 Peripheral driver (USB gadget)
+  *
+  * Copyright (C) 2015-2017  Renesas Electronics Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+  */
+ 
+ #include <linux/debugfs.h>
+diff --git a/drivers/usb/gadget/udc/s3c-hsudc.c b/drivers/usb/gadget/udc/s3c-hsudc.c
+index 9707b945eef2..31c7c5587cf9 100644
+--- a/drivers/usb/gadget/udc/s3c-hsudc.c
++++ b/drivers/usb/gadget/udc/s3c-hsudc.c
+@@ -9,11 +9,7 @@
+  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
+  * Each endpoint can be configured as either in or out endpoint. Endpoints
+  * can be configured for Bulk or Interrupt transfer mode.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+-*/
++ */
+ 
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+diff --git a/drivers/usb/gadget/udc/s3c2410_udc.c b/drivers/usb/gadget/udc/s3c2410_udc.c
+index ed874cabd339..f154f49e98c8 100644
+--- a/drivers/usb/gadget/udc/s3c2410_udc.c
++++ b/drivers/usb/gadget/udc/s3c2410_udc.c
+@@ -6,11 +6,6 @@
+  *
+  * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
+  *	Additional cleanups by Ben Dooks <ben-linux@fluff.org>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #define pr_fmt(fmt) "s3c2410_udc: " fmt
+diff --git a/drivers/usb/gadget/udc/s3c2410_udc.h b/drivers/usb/gadget/udc/s3c2410_udc.h
+index cfabc83c2244..bdcaa8dd300f 100644
+--- a/drivers/usb/gadget/udc/s3c2410_udc.h
++++ b/drivers/usb/gadget/udc/s3c2410_udc.h
+@@ -5,11 +5,6 @@
+  *
+  * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
+  *	Additional cleanups by Ben Dooks <ben-linux@fluff.org>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #ifndef _S3C2410_UDC_H
+diff --git a/drivers/usb/gadget/udc/snps_udc_core.c b/drivers/usb/gadget/udc/snps_udc_core.c
+index dba9359ece0d..4f2233b91d38 100644
+--- a/drivers/usb/gadget/udc/snps_udc_core.c
++++ b/drivers/usb/gadget/udc/snps_udc_core.c
+@@ -4,11 +4,6 @@
+  *
+  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
+  * Author: Thomas Dahlmann
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ /*
+diff --git a/drivers/usb/gadget/udc/snps_udc_plat.c b/drivers/usb/gadget/udc/snps_udc_plat.c
+index 800a35b48ab1..32f1d3e90c26 100644
+--- a/drivers/usb/gadget/udc/snps_udc_plat.c
++++ b/drivers/usb/gadget/udc/snps_udc_plat.c
+@@ -3,15 +3,6 @@
+  * snps_udc_plat.c - Synopsys UDC Platform Driver
+  *
+  * Copyright (C) 2016 Broadcom
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation version 2.
+- *
+- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+- * kind, whether express or implied; without even the implied warranty
+- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #include <linux/extcon.h>
+diff --git a/drivers/usb/gadget/udc/trace.c b/drivers/usb/gadget/udc/trace.c
+index fbc139292245..7430624c0bd7 100644
+--- a/drivers/usb/gadget/udc/trace.c
++++ b/drivers/usb/gadget/udc/trace.c
+@@ -4,15 +4,6 @@
+  *
+  * Copyright (C) 2016 Intel Corporation
+  * Author: Felipe Balbi <felipe.balbi@linux.intel.com>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2  of
+- * the License as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #define CREATE_TRACE_POINTS
+diff --git a/drivers/usb/gadget/udc/trace.h b/drivers/usb/gadget/udc/trace.h
+index 06b162bcdb54..f07ddb3f4bb9 100644
+--- a/drivers/usb/gadget/udc/trace.h
++++ b/drivers/usb/gadget/udc/trace.h
+@@ -4,18 +4,6 @@
+  *
+  * Copyright (C) 2016 Intel Corporation
+  * Author: Felipe Balbi <felipe.balbi@linux.intel.com>
+- *
+- * This program is free software: you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2  of
+- * the License as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ #undef TRACE_SYSTEM
+diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c
+index 374a75d68365..7da2b9ce8cb3 100644
+--- a/drivers/usb/gadget/udc/udc-xilinx.c
++++ b/drivers/usb/gadget/udc/udc-xilinx.c
+@@ -9,12 +9,6 @@
+  *
+  * Some parts of this driver code is based on the driver for at91-series
+  * USB peripheral controller (at91_udc.c).
+- *
+- * This program is free software; you can redistribute it
+- * and/or modify it under the terms of the GNU General Public
+- * License as published by the Free Software Foundation;
+- * either version 2 of the License, or (at your option) any
+- * later version.
+  */
+ 
+ #include <linux/delay.h>
+-- 
+2.19.0
+
diff --git a/patches/0236-usb-renesas_usbhs-unify-Gen2-3-pipe_config-setting.patch b/patches/0236-usb-renesas_usbhs-unify-Gen2-3-pipe_config-setting.patch
new file mode 100644
index 00000000000000..f231384454acea
--- /dev/null
+++ b/patches/0236-usb-renesas_usbhs-unify-Gen2-3-pipe_config-setting.patch
@@ -0,0 +1,56 @@
+From 0277eb130c00c4dbcba8a152569403bc58378423 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 20:09:13 +0900
+Subject: [PATCH 0236/1795] usb: renesas_usbhs: unify Gen2/3 pipe_config
+ setting
+
+This patch unifies the Gen2 and Gen3 pipe_config setting on
+usbhs_parse_dt().
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit a877b8e553fd2808e8693c75e0d945f413ccf5b6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.c | 13 ++++---------
+ 1 file changed, 4 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index f5968a0d392a..8392de20cac1 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -520,8 +520,11 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ 		dparam->enable_gpio = gpio;
+ 
+ 	if (dparam->type == USBHS_TYPE_RCAR_GEN2 ||
+-	    dparam->type == USBHS_TYPE_RCAR_GEN3)
++	    dparam->type == USBHS_TYPE_RCAR_GEN3) {
+ 		dparam->has_usb_dmac = 1;
++		dparam->pipe_configs = usbhsc_new_pipe;
++		dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
++	}
+ 
+ 	return info;
+ }
+@@ -578,17 +581,9 @@ static int usbhs_probe(struct platform_device *pdev)
+ 	switch (priv->dparam.type) {
+ 	case USBHS_TYPE_RCAR_GEN2:
+ 		priv->pfunc = usbhs_rcar2_ops;
+-		if (!priv->dparam.pipe_configs) {
+-			priv->dparam.pipe_configs = usbhsc_new_pipe;
+-			priv->dparam.pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+-		}
+ 		break;
+ 	case USBHS_TYPE_RCAR_GEN3:
+ 		priv->pfunc = usbhs_rcar3_ops;
+-		if (!priv->dparam.pipe_configs) {
+-			priv->dparam.pipe_configs = usbhsc_new_pipe;
+-			priv->dparam.pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+-		}
+ 		break;
+ 	default:
+ 		if (!info->platform_callback.get_id) {
+-- 
+2.19.0
+
diff --git a/patches/0237-usb-renesas_usbhs-add-support-for-R-Car-D3.patch b/patches/0237-usb-renesas_usbhs-add-support-for-R-Car-D3.patch
new file mode 100644
index 00000000000000..6071fdbe57836f
--- /dev/null
+++ b/patches/0237-usb-renesas_usbhs-add-support-for-R-Car-D3.patch
@@ -0,0 +1,187 @@
+From 2c5234135015cd090d5a440bf9fca2c7142c2b6c Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 3 Oct 2017 20:09:14 +0900
+Subject: [PATCH 0237/1795] usb: renesas_usbhs: add support for R-Car D3
+
+This patch adds support for R-Car D3. This SoC needs to release
+the PLL reset by the UGCTRL register. So, since this is not the same
+as other R-Car Gen3 SoCs, this patch adds a new type as
+"USBHS_TYPE_RCAR_GEN3_WITH_PLL".
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 0f38672c629b79fa2b929d2c391bc063a08279eb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/usb/renesas_usbhs.txt |  1 +
+ drivers/usb/renesas_usbhs/common.c            | 10 +++-
+ drivers/usb/renesas_usbhs/rcar3.c             | 48 +++++++++++++++++++
+ drivers/usb/renesas_usbhs/rcar3.h             |  1 +
+ include/linux/usb/renesas_usbhs.h             |  5 +-
+ 5 files changed, 62 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+index 9e18e000339e..e79f6e43061a 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+@@ -10,6 +10,7 @@ Required properties:
+ 	- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
+ 	- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
+ 	- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
++	- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
+ 	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device
+ 	- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+ 
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index 8392de20cac1..c0dcb1b1a37d 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -486,6 +486,10 @@ static const struct of_device_id usbhs_of_match[] = {
+ 		.compatible = "renesas,usbhs-r8a7796",
+ 		.data = (void *)USBHS_TYPE_RCAR_GEN3,
+ 	},
++	{
++		.compatible = "renesas,usbhs-r8a77995",
++		.data = (void *)USBHS_TYPE_RCAR_GEN3_WITH_PLL,
++	},
+ 	{
+ 		.compatible = "renesas,rcar-gen2-usbhs",
+ 		.data = (void *)USBHS_TYPE_RCAR_GEN2,
+@@ -520,7 +524,8 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ 		dparam->enable_gpio = gpio;
+ 
+ 	if (dparam->type == USBHS_TYPE_RCAR_GEN2 ||
+-	    dparam->type == USBHS_TYPE_RCAR_GEN3) {
++	    dparam->type == USBHS_TYPE_RCAR_GEN3 ||
++	    dparam->type == USBHS_TYPE_RCAR_GEN3_WITH_PLL) {
+ 		dparam->has_usb_dmac = 1;
+ 		dparam->pipe_configs = usbhsc_new_pipe;
+ 		dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+@@ -585,6 +590,9 @@ static int usbhs_probe(struct platform_device *pdev)
+ 	case USBHS_TYPE_RCAR_GEN3:
+ 		priv->pfunc = usbhs_rcar3_ops;
+ 		break;
++	case USBHS_TYPE_RCAR_GEN3_WITH_PLL:
++		priv->pfunc = usbhs_rcar3_with_pll_ops;
++		break;
+ 	default:
+ 		if (!info->platform_callback.get_id) {
+ 			dev_err(&pdev->dev, "no platform callbacks");
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index 0857d0d0abcd..11a13887a71d 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -16,24 +16,39 @@
+ #include "rcar3.h"
+ 
+ #define LPSTS		0x102
++#define UGCTRL		0x180	/* 32-bit register */
+ #define UGCTRL2		0x184	/* 32-bit register */
++#define UGSTS		0x188	/* 32-bit register */
+ 
+ /* Low Power Status register (LPSTS) */
+ #define LPSTS_SUSPM	0x4000
+ 
++/* R-Car D3 only: USB General control register (UGCTRL) */
++#define UGCTRL_PLLRESET		0x00000001
++#define UGCTRL_CONNECT		0x00000004
++
+ /*
+  * USB General control register 2 (UGCTRL2)
+  * Remarks: bit[31:11] and bit[9:6] should be 0
+  */
+ #define UGCTRL2_RESERVED_3	0x00000001	/* bit[3:0] should be B'0001 */
++#define UGCTRL2_USB0SEL_HSUSB	0x00000020
+ #define UGCTRL2_USB0SEL_OTG	0x00000030
+ #define UGCTRL2_VBUSSEL		0x00000400
+ 
++/* R-Car D3 only: USB General status register (UGSTS) */
++#define UGSTS_LOCK		0x00000100
++
+ static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
+ {
+ 	iowrite32(data, priv->base + reg);
+ }
+ 
++static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
++{
++	return ioread32(priv->base + reg);
++}
++
+ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
+ 				void __iomem *base, int enable)
+ {
+@@ -53,6 +68,34 @@ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
+ 	return 0;
+ }
+ 
++/* R-Car D3 needs to release UGCTRL.PLLRESET */
++static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
++					  void __iomem *base, int enable)
++{
++	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
++	u32 val;
++	int timeout = 1000;
++
++	if (enable) {
++		usbhs_write32(priv, UGCTRL, 0);	/* release PLLRESET */
++		usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 |
++			      UGCTRL2_USB0SEL_HSUSB);
++
++		usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
++		do {
++			val = usbhs_read32(priv, UGSTS);
++			udelay(1);
++		} while (!(val & UGSTS_LOCK) && timeout--);
++		usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
++	} else {
++		usbhs_write32(priv, UGCTRL, 0);
++		usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
++		usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
++	}
++
++	return 0;
++}
++
+ static int usbhs_rcar3_get_id(struct platform_device *pdev)
+ {
+ 	return USBHS_GADGET;
+@@ -62,3 +105,8 @@ const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
+ 	.power_ctrl = usbhs_rcar3_power_ctrl,
+ 	.get_id = usbhs_rcar3_get_id,
+ };
++
++const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = {
++	.power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
++	.get_id = usbhs_rcar3_get_id,
++};
+diff --git a/drivers/usb/renesas_usbhs/rcar3.h b/drivers/usb/renesas_usbhs/rcar3.h
+index 5f850b23ff18..7fe98175f94f 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.h
++++ b/drivers/usb/renesas_usbhs/rcar3.h
+@@ -1,3 +1,4 @@
+ #include "common.h"
+ 
+ extern const struct renesas_usbhs_platform_callback usbhs_rcar3_ops;
++extern const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops;
+diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h
+index 88b002252551..67102f3d59d4 100644
+--- a/include/linux/usb/renesas_usbhs.h
++++ b/include/linux/usb/renesas_usbhs.h
+@@ -184,8 +184,9 @@ struct renesas_usbhs_driver_param {
+ #define USBHS_USB_DMAC_XFER_SIZE	32	/* hardcode the xfer size */
+ };
+ 
+-#define USBHS_TYPE_RCAR_GEN2	1
+-#define USBHS_TYPE_RCAR_GEN3	2
++#define USBHS_TYPE_RCAR_GEN2		1
++#define USBHS_TYPE_RCAR_GEN3		2
++#define USBHS_TYPE_RCAR_GEN3_WITH_PLL	3
+ 
+ /*
+  * option:
+-- 
+2.19.0
+
diff --git a/patches/0238-usb-renesas_usbhs-Use-of_device_get_match_data-helpe.patch b/patches/0238-usb-renesas_usbhs-Use-of_device_get_match_data-helpe.patch
new file mode 100644
index 00000000000000..f67e68e9fb48f2
--- /dev/null
+++ b/patches/0238-usb-renesas_usbhs-Use-of_device_get_match_data-helpe.patch
@@ -0,0 +1,43 @@
+From 3d9b462a291f5179d72164a0566f33d2b1b49716 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:26:48 +0200
+Subject: [PATCH 0238/1795] usb: renesas_usbhs: Use of_device_get_match_data()
+ helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit b61e47b44882f6e578ef7c14197ea90a2703b5a0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index c0dcb1b1a37d..e1bc8a84c118 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -506,7 +506,6 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ {
+ 	struct renesas_usbhs_platform_info *info;
+ 	struct renesas_usbhs_driver_param *dparam;
+-	const struct of_device_id *of_id = of_match_device(usbhs_of_match, dev);
+ 	u32 tmp;
+ 	int gpio;
+ 
+@@ -515,7 +514,7 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ 		return NULL;
+ 
+ 	dparam = &info->driver_param;
+-	dparam->type = of_id ? (uintptr_t)of_id->data : 0;
++	dparam->type = (uintptr_t)of_device_get_match_data(dev);
+ 	if (!of_property_read_u32(dev->of_node, "renesas,buswait", &tmp))
+ 		dparam->buswait_bwait = tmp;
+ 	gpio = of_get_named_gpio_flags(dev->of_node, "renesas,enable-gpio", 0,
+-- 
+2.19.0
+
diff --git a/patches/0239-usb-renesas_usbhs-Add-compatible-string-for-r8a7743-.patch b/patches/0239-usb-renesas_usbhs-Add-compatible-string-for-r8a7743-.patch
new file mode 100644
index 00000000000000..2fefd520052760
--- /dev/null
+++ b/patches/0239-usb-renesas_usbhs-Add-compatible-string-for-r8a7743-.patch
@@ -0,0 +1,54 @@
+From a70b330da673d8cc50fd1b905d811fc3a2d328ed Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 6 Oct 2017 17:49:34 +0100
+Subject: [PATCH 0239/1795] usb: renesas_usbhs: Add compatible string for
+ r8a7743/5
+
+This patch adds support for r8a7743/5 SoCs. The Renesas RZ/G1[ME]
+(R8A7743/5) usbhs is identical to the R-Car Gen2 family.
+
+No driver change is needed due to the fallback compatible value
+"renesas,rcar-gen2-usbhs".
+Adding the SoC-specific compatible values here has two purposes:
+  1. Document which SoCs have this hardware module,
+  2. Allow checkpatch to validate compatible values.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit e0d63c4083852e07655dfcda1320504c304218be)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+index e79f6e43061a..47394ab788e3 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+@@ -3,6 +3,8 @@ Renesas Electronics USBHS driver
+ Required properties:
+   - compatible: Must contain one or more of the following:
+ 
++	- "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device
++	- "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
+ 	- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
+ 	- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
+ 	- "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device
+@@ -11,7 +13,7 @@ Required properties:
+ 	- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
+ 	- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
+ 	- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
+-	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device
++	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
+ 	- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+ 
+ 	When compatible with the generic version, nodes must list the
+-- 
+2.19.0
+
diff --git a/patches/0240-renesas_usbhs-use-renesas_usbhs_get_info.patch b/patches/0240-renesas_usbhs-use-renesas_usbhs_get_info.patch
new file mode 100644
index 00000000000000..0932e0892d00ae
--- /dev/null
+++ b/patches/0240-renesas_usbhs-use-renesas_usbhs_get_info.patch
@@ -0,0 +1,43 @@
+From b3df3cadbc6c6abadab3c7236bc7824f91f901b5 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 7 Nov 2017 08:26:07 +0000
+Subject: [PATCH 0240/1795] renesas_usbhs: use renesas_usbhs_get_info()
+
+We already have renesas_usbhs_get_info() macro.
+Let's use it.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit f0f14a7a815de478669bd2906e35eef6da730d83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index e1bc8a84c118..26685beffc9a 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -535,7 +535,7 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ 
+ static int usbhs_probe(struct platform_device *pdev)
+ {
+-	struct renesas_usbhs_platform_info *info = dev_get_platdata(&pdev->dev);
++	struct renesas_usbhs_platform_info *info = renesas_usbhs_get_info(pdev);
+ 	struct renesas_usbhs_driver_callback *dfunc;
+ 	struct usbhs_priv *priv;
+ 	struct resource *res, *irq_res;
+@@ -713,7 +713,7 @@ static int usbhs_probe(struct platform_device *pdev)
+ static int usbhs_remove(struct platform_device *pdev)
+ {
+ 	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+-	struct renesas_usbhs_platform_info *info = dev_get_platdata(&pdev->dev);
++	struct renesas_usbhs_platform_info *info = renesas_usbhs_get_info(pdev);
+ 	struct renesas_usbhs_driver_callback *dfunc = &info->driver_callback;
+ 
+ 	dev_dbg(&pdev->dev, "usb remove\n");
+-- 
+2.19.0
+
diff --git a/patches/0241-USB-renesas_usbhs-Remove-redundant-license-text.patch b/patches/0241-USB-renesas_usbhs-Remove-redundant-license-text.patch
new file mode 100644
index 00000000000000..6fcfab5c9dfecc
--- /dev/null
+++ b/patches/0241-USB-renesas_usbhs-Remove-redundant-license-text.patch
@@ -0,0 +1,290 @@
+From c260e626de8725235537f3ba06f10d61276dff92 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 15:37:12 +0100
+Subject: [PATCH 0241/1795] USB: renesas_usbhs: Remove redundant license text
+
+Now that the SPDX tag is in all USB files, that identifies the license
+in a specific and legally-defined manner.  So the extra GPL text wording
+can be removed as it is no longer needed at all.
+
+This is done on a quest to remove the 700+ different ways that files in
+the kernel describe the GPL license text.  And there's unneeded stuff
+like the address (sometimes incorrect) for the FSF which is never
+needed.
+
+No copyright headers or other non-license-description text was removed.
+
+Cc: Rob Herring <robh@kernel.org>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Chanwoo Choi <cw00.choi@samsung.com>
+Cc: Johan Hovold <johan@kernel.org>
+Cc: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
+Cc: Bhumika Goyal <bhumirks@gmail.com>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1250413a81612f49a0ae9f89342108c625779280)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.c     | 10 ----------
+ drivers/usb/renesas_usbhs/common.h     | 10 ----------
+ drivers/usb/renesas_usbhs/fifo.c       | 10 ----------
+ drivers/usb/renesas_usbhs/fifo.h       | 10 ----------
+ drivers/usb/renesas_usbhs/mod.c        | 10 ----------
+ drivers/usb/renesas_usbhs/mod.h        | 10 ----------
+ drivers/usb/renesas_usbhs/mod_gadget.c | 10 ----------
+ drivers/usb/renesas_usbhs/mod_host.c   | 10 ----------
+ drivers/usb/renesas_usbhs/pipe.c       | 10 ----------
+ drivers/usb/renesas_usbhs/pipe.h       | 10 ----------
+ drivers/usb/renesas_usbhs/rcar2.c      |  6 ------
+ drivers/usb/renesas_usbhs/rcar3.c      |  5 -----
+ 12 files changed, 111 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index 26685beffc9a..56079bb6759a 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/err.h>
+ #include <linux/gpio.h>
+diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
+index 416331c6990a..64797784a6df 100644
+--- a/drivers/usb/renesas_usbhs/common.h
++++ b/drivers/usb/renesas_usbhs/common.h
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #ifndef RENESAS_USB_DRIVER_H
+ #define RENESAS_USB_DRIVER_H
+diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
+index e3be608993af..b295e204a575 100644
+--- a/drivers/usb/renesas_usbhs/fifo.c
++++ b/drivers/usb/renesas_usbhs/fifo.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/delay.h>
+ #include <linux/io.h>
+diff --git a/drivers/usb/renesas_usbhs/fifo.h b/drivers/usb/renesas_usbhs/fifo.h
+index 7a741234c24b..88d1816bcda2 100644
+--- a/drivers/usb/renesas_usbhs/fifo.h
++++ b/drivers/usb/renesas_usbhs/fifo.h
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #ifndef RENESAS_USB_FIFO_H
+ #define RENESAS_USB_FIFO_H
+diff --git a/drivers/usb/renesas_usbhs/mod.c b/drivers/usb/renesas_usbhs/mod.c
+index c0a0789d8b1e..7475c4f64724 100644
+--- a/drivers/usb/renesas_usbhs/mod.c
++++ b/drivers/usb/renesas_usbhs/mod.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/interrupt.h>
+ 
+diff --git a/drivers/usb/renesas_usbhs/mod.h b/drivers/usb/renesas_usbhs/mod.h
+index 5355a13045d9..a4a61d6b82a1 100644
+--- a/drivers/usb/renesas_usbhs/mod.h
++++ b/drivers/usb/renesas_usbhs/mod.h
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #ifndef RENESAS_USB_MOD_H
+ #define RENESAS_USB_MOD_H
+diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c
+index 019bbc8bf9b2..34ee9ebe12a3 100644
+--- a/drivers/usb/renesas_usbhs/mod_gadget.c
++++ b/drivers/usb/renesas_usbhs/mod_gadget.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/delay.h>
+ #include <linux/dma-mapping.h>
+diff --git a/drivers/usb/renesas_usbhs/mod_host.c b/drivers/usb/renesas_usbhs/mod_host.c
+index 1ab0ac83b00c..4e59c649db81 100644
+--- a/drivers/usb/renesas_usbhs/mod_host.c
++++ b/drivers/usb/renesas_usbhs/mod_host.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/io.h>
+ #include <linux/list.h>
+diff --git a/drivers/usb/renesas_usbhs/pipe.c b/drivers/usb/renesas_usbhs/pipe.c
+index 3c500aaadf35..093cd8e87335 100644
+--- a/drivers/usb/renesas_usbhs/pipe.c
++++ b/drivers/usb/renesas_usbhs/pipe.c
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+diff --git a/drivers/usb/renesas_usbhs/pipe.h b/drivers/usb/renesas_usbhs/pipe.h
+index ed32cb11fe09..d3d002244891 100644
+--- a/drivers/usb/renesas_usbhs/pipe.h
++++ b/drivers/usb/renesas_usbhs/pipe.h
+@@ -4,16 +4,6 @@
+  *
+  * Copyright (C) 2011 Renesas Solutions Corp.
+  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+- *
+  */
+ #ifndef RENESAS_USB_PIPE_H
+ #define RENESAS_USB_PIPE_H
+diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c
+index b03b3cb36b49..85a0e0933917 100644
+--- a/drivers/usb/renesas_usbhs/rcar2.c
++++ b/drivers/usb/renesas_usbhs/rcar2.c
+@@ -3,12 +3,6 @@
+  * Renesas USB driver R-Car Gen. 2 initialization and power control
+  *
+  * Copyright (C) 2014 Ulrich Hecht
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #include <linux/gpio.h>
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index 11a13887a71d..c929d296c77b 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -3,11 +3,6 @@
+  * Renesas USB driver R-Car Gen. 3 initialization and power control
+  *
+  * Copyright (C) 2016 Renesas Electronics Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+  */
+ 
+ #include <linux/delay.h>
+-- 
+2.19.0
+
diff --git a/patches/0242-USB-renesas_usbhs-rcar-.h-add-SPDX-tags.patch b/patches/0242-USB-renesas_usbhs-rcar-.h-add-SPDX-tags.patch
new file mode 100644
index 00000000000000..bd6a2cc155d6c2
--- /dev/null
+++ b/patches/0242-USB-renesas_usbhs-rcar-.h-add-SPDX-tags.patch
@@ -0,0 +1,48 @@
+From 164ed12b0d524f87fcec3bfc45426524dbd502b2 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 16:34:10 +0100
+Subject: [PATCH 0242/1795] USB: renesas_usbhs: rcar?.h: add SPDX tags
+
+These files somehow never got an SPDX tag added to them, maybe due to
+the small size.  So provide the default identifier of the whole project:
+	SPDX-License-Identifier: GPL-2.0
+
+The SPDX identifier is a legally binding shorthand, which can be used
+instead of the full boiler plate text.
+
+Cc: Rob Herring <robh@kernel.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Kate Stewart <kstewart@linuxfoundation.org>
+Cc: Philippe Ombredanne <pombredanne@nexb.com>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fc9904d3c46e92c103414606fc407c7aa24d443b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/rcar2.h | 1 +
+ drivers/usb/renesas_usbhs/rcar3.h | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/usb/renesas_usbhs/rcar2.h b/drivers/usb/renesas_usbhs/rcar2.h
+index f07f10d9b3b2..45e3526cedeb 100644
+--- a/drivers/usb/renesas_usbhs/rcar2.h
++++ b/drivers/usb/renesas_usbhs/rcar2.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include "common.h"
+ 
+ extern const struct renesas_usbhs_platform_callback
+diff --git a/drivers/usb/renesas_usbhs/rcar3.h b/drivers/usb/renesas_usbhs/rcar3.h
+index 7fe98175f94f..49e535a31771 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.h
++++ b/drivers/usb/renesas_usbhs/rcar3.h
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ #include "common.h"
+ 
+ extern const struct renesas_usbhs_platform_callback usbhs_rcar3_ops;
+-- 
+2.19.0
+
diff --git a/patches/0243-mmc-usdhi6rol0-catch-all-errors-when-getting-regulat.patch b/patches/0243-mmc-usdhi6rol0-catch-all-errors-when-getting-regulat.patch
new file mode 100644
index 00000000000000..302e94cbc62493
--- /dev/null
+++ b/patches/0243-mmc-usdhi6rol0-catch-all-errors-when-getting-regulat.patch
@@ -0,0 +1,39 @@
+From e79c556ce0654bea231f81bac611ba2ae06fa158 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 14 Oct 2017 21:17:19 +0200
+Subject: [PATCH 0243/1795] mmc: usdhi6rol0: catch all errors when getting
+ regulators
+
+Bail out everytime when mmc_regulator_get_supply() returns an errno, not
+only when probing gets deferred. This is currently a no-op, because this
+function only returns -EPROBE_DEFER or 0 right now. But if it will throw
+another error somewhen, it will be for a reason. (This still doesn't change
+that getting regulators is optional, so 0 can still mean no regulators
+found). So, let us a) be future proof and b) have driver code which is
+easier to understand.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 2d87ddd7b63e276a2e0a11788fce9e91c4d23a86)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/usdhi6rol0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/usdhi6rol0.c b/drivers/mmc/host/usdhi6rol0.c
+index 64da6a88cfb9..cdfeb15b6f05 100644
+--- a/drivers/mmc/host/usdhi6rol0.c
++++ b/drivers/mmc/host/usdhi6rol0.c
+@@ -1757,7 +1757,7 @@ static int usdhi6_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 
+ 	ret = mmc_regulator_get_supply(mmc);
+-	if (ret == -EPROBE_DEFER)
++	if (ret)
+ 		goto e_free_mmc;
+ 
+ 	ret = mmc_of_parse(mmc);
+-- 
+2.19.0
+
diff --git a/patches/0244-v4l-vsp1-Use-generic-node-name.patch b/patches/0244-v4l-vsp1-Use-generic-node-name.patch
new file mode 100644
index 00000000000000..0c98ccd96f3c7c
--- /dev/null
+++ b/patches/0244-v4l-vsp1-Use-generic-node-name.patch
@@ -0,0 +1,32 @@
+From 2892128629195637e74b01f114db9cedf859862e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 30 Aug 2017 11:57:31 +0200
+Subject: [PATCH 0244/1795] v4l: vsp1: Use generic node name
+
+Use the preferred generic node name in the example.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 0e1bfb72b076b07dc844bf33c19d62a3075f540f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/media/renesas,vsp1.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.txt b/Documentation/devicetree/bindings/media/renesas,vsp1.txt
+index 9b695bcbf219..16427017cb45 100644
+--- a/Documentation/devicetree/bindings/media/renesas,vsp1.txt
++++ b/Documentation/devicetree/bindings/media/renesas,vsp1.txt
+@@ -22,7 +22,7 @@ Optional properties:
+ 
+ Example: R8A7790 (R-Car H2) VSP1-S node
+ 
+-	vsp1@fe928000 {
++	vsp@fe928000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0245-media-vsp1-add-a-missing-kernel-doc-parameter.patch b/patches/0245-media-vsp1-add-a-missing-kernel-doc-parameter.patch
new file mode 100644
index 00000000000000..051cab9403ec4a
--- /dev/null
+++ b/patches/0245-media-vsp1-add-a-missing-kernel-doc-parameter.patch
@@ -0,0 +1,31 @@
+From 6fe502a359e88834c2533d184c004d6869693897 Mon Sep 17 00:00:00 2001
+From: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+Date: Wed, 29 Nov 2017 10:11:04 -0500
+Subject: [PATCH 0245/1795] media: vsp1: add a missing kernel-doc parameter
+
+Fix this warning:
+	drivers/media/platform/vsp1/vsp1_dl.c:87: warning: No description found for parameter 'has_chain'
+
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 2afe216d3d88b729c40d83abce5b2d4b72d289c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index e5d8d99e124c..0b86ed01e85d 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -70,6 +70,7 @@ struct vsp1_dl_body {
+  * @dma: DMA address for the header
+  * @body0: first display list body
+  * @fragments: list of extra display list bodies
++ * @has_chain: if true, indicates that there's a partition chain
+  * @chain: entry in the display list partition chain
+  */
+ struct vsp1_dl_list {
+-- 
+2.19.0
+
diff --git a/patches/0246-usb-host-xhci-support-option-to-disable-the-xHCI-USB.patch b/patches/0246-usb-host-xhci-support-option-to-disable-the-xHCI-USB.patch
new file mode 100644
index 00000000000000..3882dc116594f5
--- /dev/null
+++ b/patches/0246-usb-host-xhci-support-option-to-disable-the-xHCI-USB.patch
@@ -0,0 +1,84 @@
+From 2acd90ace90f3051f7bd6ac7c54ceb38f29cd039 Mon Sep 17 00:00:00 2001
+From: "Thang Q. Nguyen" <tqnguyen@apm.com>
+Date: Thu, 5 Oct 2017 11:21:37 +0300
+Subject: [PATCH 0246/1795] usb: host: xhci support option to disable the xHCI
+ USB2 HW LPM
+
+XHCI specification 1.1 does not require xHCI-compliant controllers
+to always enable hardware USB2 LPM. However, the current xHCI
+driver always enable it when seeing HLC=1.
+This patch supports an option for users to control disabling
+USB2 Hardware LPM via DT/ACPI attribute.
+This option is needed in case user would like to disable this
+feature. For example, their xHCI controller has its USB2 HW LPM
+broken.
+
+Signed-off-by: Tung Nguyen <tunguyen@apm.com>
+Signed-off-by: Thang Q. Nguyen <tqnguyen@apm.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 4750bc78efdb126ddc40f1b34dbae7ce319344cb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
+ drivers/usb/host/xhci-plat.c                       | 3 +++
+ drivers/usb/host/xhci.c                            | 2 +-
+ drivers/usb/host/xhci.h                            | 1 +
+ 4 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+index 7a69b8b47b97..4143ef222540 100644
+--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+@@ -27,6 +27,7 @@ Required properties:
+ 
+ Optional properties:
+   - clocks: reference to a clock
++  - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
+   - usb3-lpm-capable: determines if platform is USB3 LPM capable
+   - quirk-broken-port-ped: set if the controller has broken port disable mechanism
+ 
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index a15f1f295afc..5340e4ad8d13 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -264,6 +264,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 		goto disable_clk;
+ 	}
+ 
++	if (device_property_read_bool(sysdev, "usb2-lpm-disable"))
++		xhci->quirks |= XHCI_HW_LPM_DISABLE;
++
+ 	if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
+ 		xhci->quirks |= XHCI_LPM_SUPPORT;
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 55bb05893c55..ae7acaa420c6 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -4115,7 +4115,7 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
+ 	xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
+ 			enable ? "enable" : "disable", port_num + 1);
+ 
+-	if (enable) {
++	if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
+ 		/* Host supports BESL timeout instead of HIRD */
+ 		if (udev->usb2_hw_lpm_besl_capable) {
+ 			/* if device doesn't have a preferred BESL value use a
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 6b4c7ae70ab1..c9fc67a30e4c 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1836,6 +1836,7 @@ struct xhci_hcd {
+ #define XHCI_LIMIT_ENDPOINT_INTERVAL_7	(1 << 26)
+ #define XHCI_U2_DISABLE_WAKE	(1 << 27)
+ #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL	(1 << 28)
++#define XHCI_HW_LPM_DISABLE	(1 << 29)
+ #define XHCI_SUSPEND_DELAY	(1 << 30)
+ 
+ 	unsigned int		num_active_eps;
+-- 
+2.19.0
+
diff --git a/patches/0247-xhci-add-port-speed-ID-to-portsc-tracing.patch b/patches/0247-xhci-add-port-speed-ID-to-portsc-tracing.patch
new file mode 100644
index 00000000000000..6c8c9888efa16f
--- /dev/null
+++ b/patches/0247-xhci-add-port-speed-ID-to-portsc-tracing.patch
@@ -0,0 +1,45 @@
+From 6d943fe49482e42c3b76ea16a97a9ecf1042941e Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:38 +0300
+Subject: [PATCH 0247/1795] xhci: add port speed ID to portsc tracing
+
+Shows the port speed protocol speed ID (PSID) in use.
+speed ID may map to custom speeds, but in most cases it uses default
+
+1 = Full-Speed        12 MB/s
+2 = Low-Speed         1.5 Mb/s
+3 = High-speed        480 Mb/s
+4 = SuperSpeed        5 Gb/s
+5 = SuperSpeedPlus    10 Gb/s
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 8f11487719401e20ecc58c114d9fc3177535c40a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.h | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index c9fc67a30e4c..b1ef8fe056eb 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2449,11 +2449,12 @@ static inline const char *xhci_decode_portsc(u32 portsc)
+ 	static char str[256];
+ 	int ret;
+ 
+-	ret = sprintf(str, "%s %s %s Link:%s ",
++	ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
+ 		      portsc & PORT_POWER	? "Powered" : "Powered-off",
+ 		      portsc & PORT_CONNECT	? "Connected" : "Not-connected",
+ 		      portsc & PORT_PE		? "Enabled" : "Disabled",
+-		      xhci_portsc_link_state_string(portsc));
++		      xhci_portsc_link_state_string(portsc),
++		      DEV_PORT_SPEED(portsc));
+ 
+ 	if (portsc & PORT_OC)
+ 		ret += sprintf(str + ret, "OverCurrent ");
+-- 
+2.19.0
+
diff --git a/patches/0248-usb-xhci-Add-debugfs-interface-for-xHCI-driver.patch b/patches/0248-usb-xhci-Add-debugfs-interface-for-xHCI-driver.patch
new file mode 100644
index 00000000000000..f535d581087018
--- /dev/null
+++ b/patches/0248-usb-xhci-Add-debugfs-interface-for-xHCI-driver.patch
@@ -0,0 +1,936 @@
+From c748c216d7c504d47ef948a8e0be40a64cb4a60a Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:39 +0300
+Subject: [PATCH 0248/1795] usb: xhci: Add debugfs interface for xHCI driver
+
+This adds debugfs consumer for xHCI driver. The debugfs entries
+read all host registers, device/endpoint contexts, command ring,
+event ring and various endpoint rings. With these entries, users
+can check the registers and memory spaces used by a host during
+run time, or save all the information with a simple 'cp -r' for
+post-mortem programs.
+
+The file hierarchy looks like this.
+
+[root of debugfs]
+|__usb
+|____[e,u,o]hci                 <---------[root for other HCIs]
+|____xhci                       <---------------[root for xHCI]
+|______0000:00:14.0             <--------------[xHCI host name]
+|________reg-cap                <--------[capability registers]
+|________reg-op                 <-------[operational registers]
+|________reg-runtime            <-----------[runtime registers]
+|________reg-ext-#cap_name      <----[extended capability regs]
+|________command-ring           <-------[root for command ring]
+|__________cycle                <------------------[ring cycle]
+|__________dequeue              <--------[ring dequeue pointer]
+|__________enqueue              <--------[ring enqueue pointer]
+|__________trbs                 <-------------------[ring trbs]
+|________event-ring             <---------[root for event ring]
+|__________cycle                <------------------[ring cycle]
+|__________dequeue              <--------[ring dequeue pointer]
+|__________enqueue              <--------[ring enqueue pointer]
+|__________trbs                 <-------------------[ring trbs]
+|________devices                <------------[root for devices]
+|__________#slot_id             <-----------[root for a device]
+|____________name               <-----------------[device name]
+|____________slot-context       <----------------[slot context]
+|____________ep-context         <-----------[endpoint contexts]
+|____________ep#ep_index        <--------[root for an endpoint]
+|______________cycle            <------------------[ring cycle]
+|______________dequeue          <--------[ring dequeue pointer]
+|______________enqueue          <--------[ring enqueue pointer]
+|______________trbs             <-------------------[ring trbs]
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 02b6fdc2a153e61b957937772a562fb6357dc861)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/Makefile       |   4 +
+ drivers/usb/host/xhci-debugfs.c | 526 ++++++++++++++++++++++++++++++++
+ drivers/usb/host/xhci-debugfs.h | 137 +++++++++
+ drivers/usb/host/xhci-mem.c     |   5 +-
+ drivers/usb/host/xhci.c         |  23 +-
+ drivers/usb/host/xhci.h         |   9 +
+ 6 files changed, 700 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/usb/host/xhci-debugfs.c
+ create mode 100644 drivers/usb/host/xhci-debugfs.h
+
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index 4ab2689c8952..81bfd7c70bd2 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -26,6 +26,10 @@ ifneq ($(CONFIG_USB_XHCI_RCAR), )
+ 	xhci-plat-hcd-y		+= xhci-rcar.o
+ endif
+ 
++ifneq ($(CONFIG_DEBUG_FS),)
++	xhci-hcd-y		+= xhci-debugfs.o
++endif
++
+ obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
+ 
+ obj-$(CONFIG_USB_PCI)	+= pci-quirks.o
+diff --git a/drivers/usb/host/xhci-debugfs.c b/drivers/usb/host/xhci-debugfs.c
+new file mode 100644
+index 000000000000..6772ee90944b
+--- /dev/null
++++ b/drivers/usb/host/xhci-debugfs.c
+@@ -0,0 +1,526 @@
++/*
++ * xhci-debugfs.c - xHCI debugfs interface
++ *
++ * Copyright (C) 2017 Intel Corporation
++ *
++ * Author: Lu Baolu <baolu.lu@linux.intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/slab.h>
++
++#include "xhci.h"
++#include "xhci-debugfs.h"
++
++static const struct debugfs_reg32 xhci_cap_regs[] = {
++	dump_register(CAPLENGTH),
++	dump_register(HCSPARAMS1),
++	dump_register(HCSPARAMS2),
++	dump_register(HCSPARAMS3),
++	dump_register(HCCPARAMS1),
++	dump_register(DOORBELLOFF),
++	dump_register(RUNTIMEOFF),
++	dump_register(HCCPARAMS2),
++};
++
++static const struct debugfs_reg32 xhci_op_regs[] = {
++	dump_register(USBCMD),
++	dump_register(USBSTS),
++	dump_register(PAGESIZE),
++	dump_register(DNCTRL),
++	dump_register(CRCR),
++	dump_register(DCBAAP_LOW),
++	dump_register(DCBAAP_HIGH),
++	dump_register(CONFIG),
++};
++
++static const struct debugfs_reg32 xhci_runtime_regs[] = {
++	dump_register(MFINDEX),
++	dump_register(IR0_IMAN),
++	dump_register(IR0_IMOD),
++	dump_register(IR0_ERSTSZ),
++	dump_register(IR0_ERSTBA_LOW),
++	dump_register(IR0_ERSTBA_HIGH),
++	dump_register(IR0_ERDP_LOW),
++	dump_register(IR0_ERDP_HIGH),
++};
++
++static const struct debugfs_reg32 xhci_extcap_legsup[] = {
++	dump_register(EXTCAP_USBLEGSUP),
++	dump_register(EXTCAP_USBLEGCTLSTS),
++};
++
++static const struct debugfs_reg32 xhci_extcap_protocol[] = {
++	dump_register(EXTCAP_REVISION),
++	dump_register(EXTCAP_NAME),
++	dump_register(EXTCAP_PORTINFO),
++	dump_register(EXTCAP_PORTTYPE),
++	dump_register(EXTCAP_MANTISSA1),
++	dump_register(EXTCAP_MANTISSA2),
++	dump_register(EXTCAP_MANTISSA3),
++	dump_register(EXTCAP_MANTISSA4),
++	dump_register(EXTCAP_MANTISSA5),
++	dump_register(EXTCAP_MANTISSA6),
++};
++
++static const struct debugfs_reg32 xhci_extcap_dbc[] = {
++	dump_register(EXTCAP_DBC_CAPABILITY),
++	dump_register(EXTCAP_DBC_DOORBELL),
++	dump_register(EXTCAP_DBC_ERSTSIZE),
++	dump_register(EXTCAP_DBC_ERST_LOW),
++	dump_register(EXTCAP_DBC_ERST_HIGH),
++	dump_register(EXTCAP_DBC_ERDP_LOW),
++	dump_register(EXTCAP_DBC_ERDP_HIGH),
++	dump_register(EXTCAP_DBC_CONTROL),
++	dump_register(EXTCAP_DBC_STATUS),
++	dump_register(EXTCAP_DBC_PORTSC),
++	dump_register(EXTCAP_DBC_CONT_LOW),
++	dump_register(EXTCAP_DBC_CONT_HIGH),
++	dump_register(EXTCAP_DBC_DEVINFO1),
++	dump_register(EXTCAP_DBC_DEVINFO2),
++};
++
++static struct dentry *xhci_debugfs_root;
++
++static struct xhci_regset *xhci_debugfs_alloc_regset(struct xhci_hcd *xhci)
++{
++	struct xhci_regset	*regset;
++
++	regset = kzalloc(sizeof(*regset), GFP_KERNEL);
++	if (!regset)
++		return NULL;
++
++	/*
++	 * The allocation and free of regset are executed in order.
++	 * We needn't a lock here.
++	 */
++	INIT_LIST_HEAD(&regset->list);
++	list_add_tail(&regset->list, &xhci->regset_list);
++
++	return regset;
++}
++
++static void xhci_debugfs_free_regset(struct xhci_regset *regset)
++{
++	if (!regset)
++		return;
++
++	list_del(&regset->list);
++	kfree(regset);
++}
++
++static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base,
++				const struct debugfs_reg32 *regs,
++				size_t nregs, struct dentry *parent,
++				const char *fmt, ...)
++{
++	struct xhci_regset	*rgs;
++	va_list			args;
++	struct debugfs_regset32	*regset;
++	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
++
++	rgs = xhci_debugfs_alloc_regset(xhci);
++	if (!rgs)
++		return;
++
++	va_start(args, fmt);
++	vsnprintf(rgs->name, sizeof(rgs->name), fmt, args);
++	va_end(args);
++
++	regset = &rgs->regset;
++	regset->regs = regs;
++	regset->nregs = nregs;
++	regset->base = hcd->regs + base;
++
++	debugfs_create_regset32((const char *)rgs->name, 0444, parent, regset);
++}
++
++static void xhci_debugfs_extcap_regset(struct xhci_hcd *xhci, int cap_id,
++				       const struct debugfs_reg32 *regs,
++				       size_t n, const char *cap_name)
++{
++	u32			offset;
++	int			index = 0;
++	size_t			psic, nregs = n;
++	void __iomem		*base = &xhci->cap_regs->hc_capbase;
++
++	offset = xhci_find_next_ext_cap(base, 0, cap_id);
++	while (offset) {
++		if (cap_id == XHCI_EXT_CAPS_PROTOCOL) {
++			psic = XHCI_EXT_PORT_PSIC(readl(base + offset + 8));
++			nregs = min(4 + psic, n);
++		}
++
++		xhci_debugfs_regset(xhci, offset, regs, nregs,
++				    xhci->debugfs_root, "%s:%02d",
++				    cap_name, index);
++		offset = xhci_find_next_ext_cap(base, offset, cap_id);
++		index++;
++	}
++}
++
++static int xhci_ring_enqueue_show(struct seq_file *s, void *unused)
++{
++	dma_addr_t		dma;
++	struct xhci_ring	*ring = s->private;
++
++	dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
++	seq_printf(s, "%pad\n", &dma);
++
++	return 0;
++}
++
++static int xhci_ring_dequeue_show(struct seq_file *s, void *unused)
++{
++	dma_addr_t		dma;
++	struct xhci_ring	*ring = s->private;
++
++	dma = xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
++	seq_printf(s, "%pad\n", &dma);
++
++	return 0;
++}
++
++static int xhci_ring_cycle_show(struct seq_file *s, void *unused)
++{
++	struct xhci_ring	*ring = s->private;
++
++	seq_printf(s, "%d\n", ring->cycle_state);
++
++	return 0;
++}
++
++static void xhci_ring_dump_segment(struct seq_file *s,
++				   struct xhci_segment *seg)
++{
++	int			i;
++	dma_addr_t		dma;
++	union xhci_trb		*trb;
++
++	for (i = 0; i < TRBS_PER_SEGMENT; i++) {
++		trb = &seg->trbs[i];
++		dma = seg->dma + i * sizeof(*trb);
++		seq_printf(s, "%pad: %s\n", &dma,
++			   xhci_decode_trb(trb->generic.field[0],
++					   trb->generic.field[1],
++					   trb->generic.field[2],
++					   trb->generic.field[3]));
++	}
++}
++
++static int xhci_ring_trb_show(struct seq_file *s, void *unused)
++{
++	int			i;
++	struct xhci_ring	*ring = s->private;
++	struct xhci_segment	*seg = ring->first_seg;
++
++	for (i = 0; i < ring->num_segs; i++) {
++		xhci_ring_dump_segment(s, seg);
++		seg = seg->next;
++	}
++
++	return 0;
++}
++
++static struct xhci_file_map ring_files[] = {
++	{"enqueue",		xhci_ring_enqueue_show, },
++	{"dequeue",		xhci_ring_dequeue_show, },
++	{"cycle",		xhci_ring_cycle_show, },
++	{"trbs",		xhci_ring_trb_show, },
++};
++
++static int xhci_ring_open(struct inode *inode, struct file *file)
++{
++	int			i;
++	struct xhci_file_map	*f_map;
++	const char		*file_name = file_dentry(file)->d_iname;
++
++	for (i = 0; i < ARRAY_SIZE(ring_files); i++) {
++		f_map = &ring_files[i];
++
++		if (strcmp(f_map->name, file_name) == 0)
++			break;
++	}
++
++	return single_open(file, f_map->show, inode->i_private);
++}
++
++static const struct file_operations xhci_ring_fops = {
++	.open			= xhci_ring_open,
++	.read			= seq_read,
++	.llseek			= seq_lseek,
++	.release		= single_release,
++};
++
++static int xhci_slot_context_show(struct seq_file *s, void *unused)
++{
++	struct xhci_hcd		*xhci;
++	struct xhci_slot_ctx	*slot_ctx;
++	struct xhci_slot_priv	*priv = s->private;
++	struct xhci_virt_device	*dev = priv->dev;
++
++	xhci = hcd_to_xhci(bus_to_hcd(dev->udev->bus));
++	slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
++	seq_printf(s, "%pad: %s\n", &dev->out_ctx->dma,
++		   xhci_decode_slot_context(slot_ctx->dev_info,
++					    slot_ctx->dev_info2,
++					    slot_ctx->tt_info,
++					    slot_ctx->dev_state));
++
++	return 0;
++}
++
++static int xhci_endpoint_context_show(struct seq_file *s, void *unused)
++{
++	int			dci;
++	dma_addr_t		dma;
++	struct xhci_hcd		*xhci;
++	struct xhci_ep_ctx	*ep_ctx;
++	struct xhci_slot_priv	*priv = s->private;
++	struct xhci_virt_device	*dev = priv->dev;
++
++	xhci = hcd_to_xhci(bus_to_hcd(dev->udev->bus));
++
++	for (dci = 1; dci < 32; dci++) {
++		ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, dci);
++		dma = dev->out_ctx->dma + dci * CTX_SIZE(xhci->hcc_params);
++		seq_printf(s, "%pad: %s\n", &dma,
++			   xhci_decode_ep_context(ep_ctx->ep_info,
++						  ep_ctx->ep_info2,
++						  ep_ctx->deq,
++						  ep_ctx->tx_info));
++	}
++
++	return 0;
++}
++
++static int xhci_device_name_show(struct seq_file *s, void *unused)
++{
++	struct xhci_slot_priv	*priv = s->private;
++	struct xhci_virt_device	*dev = priv->dev;
++
++	seq_printf(s, "%s\n", dev_name(&dev->udev->dev));
++
++	return 0;
++}
++
++static struct xhci_file_map context_files[] = {
++	{"name",		xhci_device_name_show, },
++	{"slot-context",	xhci_slot_context_show, },
++	{"ep-context",		xhci_endpoint_context_show, },
++};
++
++static int xhci_context_open(struct inode *inode, struct file *file)
++{
++	int			i;
++	struct xhci_file_map	*f_map;
++	const char		*file_name = file_dentry(file)->d_iname;
++
++	for (i = 0; i < ARRAY_SIZE(context_files); i++) {
++		f_map = &context_files[i];
++
++		if (strcmp(f_map->name, file_name) == 0)
++			break;
++	}
++
++	return single_open(file, f_map->show, inode->i_private);
++}
++
++static const struct file_operations xhci_context_fops = {
++	.open			= xhci_context_open,
++	.read			= seq_read,
++	.llseek			= seq_lseek,
++	.release		= single_release,
++};
++
++static void xhci_debugfs_create_files(struct xhci_hcd *xhci,
++				      struct xhci_file_map *files,
++				      size_t nentries, void *data,
++				      struct dentry *parent,
++				      const struct file_operations *fops)
++{
++	int			i;
++
++	for (i = 0; i < nentries; i++)
++		debugfs_create_file(files[i].name, 0444, parent, data, fops);
++}
++
++static struct dentry *xhci_debugfs_create_ring_dir(struct xhci_hcd *xhci,
++						   struct xhci_ring *ring,
++						   const char *name,
++						   struct dentry *parent)
++{
++	struct dentry		*dir;
++
++	dir = debugfs_create_dir(name, parent);
++	xhci_debugfs_create_files(xhci, ring_files, ARRAY_SIZE(ring_files),
++				  ring, dir, &xhci_ring_fops);
++
++	return dir;
++}
++
++static void xhci_debugfs_create_context_files(struct xhci_hcd *xhci,
++					      struct dentry *parent,
++					      int slot_id)
++{
++	struct xhci_virt_device	*dev = xhci->devs[slot_id];
++
++	xhci_debugfs_create_files(xhci, context_files,
++				  ARRAY_SIZE(context_files),
++				  dev->debugfs_private,
++				  parent, &xhci_context_fops);
++}
++
++void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
++				  struct xhci_virt_device *dev,
++				  int ep_index)
++{
++	struct xhci_ep_priv	*epriv;
++	struct xhci_slot_priv	*spriv = dev->debugfs_private;
++
++	if (spriv->eps[ep_index])
++		return;
++
++	epriv = kzalloc(sizeof(*epriv), GFP_KERNEL);
++	if (!epriv)
++		return;
++
++	snprintf(epriv->name, sizeof(epriv->name), "ep%02d", ep_index);
++	epriv->root = xhci_debugfs_create_ring_dir(xhci,
++						   dev->eps[ep_index].new_ring,
++						   epriv->name,
++						   spriv->root);
++	spriv->eps[ep_index] = epriv;
++}
++
++void xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci,
++				  struct xhci_virt_device *dev,
++				  int ep_index)
++{
++	struct xhci_ep_priv	*epriv;
++	struct xhci_slot_priv	*spriv = dev->debugfs_private;
++
++	if (!spriv || !spriv->eps[ep_index])
++		return;
++
++	epriv = spriv->eps[ep_index];
++	debugfs_remove_recursive(epriv->root);
++	spriv->eps[ep_index] = NULL;
++	kfree(epriv);
++}
++
++void xhci_debugfs_create_slot(struct xhci_hcd *xhci, int slot_id)
++{
++	struct xhci_slot_priv	*priv;
++	struct xhci_virt_device	*dev = xhci->devs[slot_id];
++
++	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return;
++
++	snprintf(priv->name, sizeof(priv->name), "%02d", slot_id);
++	priv->root = debugfs_create_dir(priv->name, xhci->debugfs_slots);
++	priv->dev = dev;
++	dev->debugfs_private = priv;
++
++	xhci_debugfs_create_ring_dir(xhci, dev->eps[0].ring,
++				     "ep00", priv->root);
++
++	xhci_debugfs_create_context_files(xhci, priv->root, slot_id);
++}
++
++void xhci_debugfs_remove_slot(struct xhci_hcd *xhci, int slot_id)
++{
++	int			i;
++	struct xhci_slot_priv	*priv;
++	struct xhci_virt_device	*dev = xhci->devs[slot_id];
++
++	if (!dev || !dev->debugfs_private)
++		return;
++
++	priv = dev->debugfs_private;
++
++	debugfs_remove_recursive(priv->root);
++
++	for (i = 0; i < 31; i++)
++		kfree(priv->eps[i]);
++
++	kfree(priv);
++	dev->debugfs_private = NULL;
++}
++
++void xhci_debugfs_init(struct xhci_hcd *xhci)
++{
++	struct device		*dev = xhci_to_hcd(xhci)->self.controller;
++
++	xhci->debugfs_root = debugfs_create_dir(dev_name(dev),
++						xhci_debugfs_root);
++
++	INIT_LIST_HEAD(&xhci->regset_list);
++
++	xhci_debugfs_regset(xhci,
++			    0,
++			    xhci_cap_regs, ARRAY_SIZE(xhci_cap_regs),
++			    xhci->debugfs_root, "reg-cap");
++
++	xhci_debugfs_regset(xhci,
++			    HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)),
++			    xhci_op_regs, ARRAY_SIZE(xhci_op_regs),
++			    xhci->debugfs_root, "reg-op");
++
++	xhci_debugfs_regset(xhci,
++			    readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK,
++			    xhci_runtime_regs, ARRAY_SIZE(xhci_runtime_regs),
++			    xhci->debugfs_root, "reg-runtime");
++
++	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_LEGACY,
++				   xhci_extcap_legsup,
++				   ARRAY_SIZE(xhci_extcap_legsup),
++				   "reg-ext-legsup");
++
++	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_PROTOCOL,
++				   xhci_extcap_protocol,
++				   ARRAY_SIZE(xhci_extcap_protocol),
++				   "reg-ext-protocol");
++
++	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_DEBUG,
++				   xhci_extcap_dbc,
++				   ARRAY_SIZE(xhci_extcap_dbc),
++				   "reg-ext-dbc");
++
++	xhci_debugfs_create_ring_dir(xhci, xhci->cmd_ring,
++				     "command-ring",
++				     xhci->debugfs_root);
++
++	xhci_debugfs_create_ring_dir(xhci, xhci->event_ring,
++				     "event-ring",
++				     xhci->debugfs_root);
++
++	xhci->debugfs_slots = debugfs_create_dir("devices", xhci->debugfs_root);
++}
++
++void xhci_debugfs_exit(struct xhci_hcd *xhci)
++{
++	struct xhci_regset	*rgs, *tmp;
++
++	debugfs_remove_recursive(xhci->debugfs_root);
++	xhci->debugfs_root = NULL;
++	xhci->debugfs_slots = NULL;
++
++	list_for_each_entry_safe(rgs, tmp, &xhci->regset_list, list)
++		xhci_debugfs_free_regset(rgs);
++}
++
++void __init xhci_debugfs_create_root(void)
++{
++	xhci_debugfs_root = debugfs_create_dir("xhci", usb_debug_root);
++}
++
++void __exit xhci_debugfs_remove_root(void)
++{
++	debugfs_remove_recursive(xhci_debugfs_root);
++	xhci_debugfs_root = NULL;
++}
+diff --git a/drivers/usb/host/xhci-debugfs.h b/drivers/usb/host/xhci-debugfs.h
+new file mode 100644
+index 000000000000..3adc9976f180
+--- /dev/null
++++ b/drivers/usb/host/xhci-debugfs.h
+@@ -0,0 +1,137 @@
++/*
++ * xhci-debugfs.h - xHCI debugfs interface
++ *
++ * Copyright (C) 2017 Intel Corporation
++ *
++ * Author: Lu Baolu <baolu.lu@linux.intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __LINUX_XHCI_DEBUGFS_H
++#define __LINUX_XHCI_DEBUGFS_H
++
++#include <linux/debugfs.h>
++
++#define DEBUGFS_NAMELEN 32
++
++#define REG_CAPLENGTH					0x00
++#define REG_HCSPARAMS1					0x04
++#define REG_HCSPARAMS2					0x08
++#define REG_HCSPARAMS3					0x0c
++#define REG_HCCPARAMS1					0x10
++#define REG_DOORBELLOFF					0x14
++#define REG_RUNTIMEOFF					0x18
++#define REG_HCCPARAMS2					0x1c
++
++#define	REG_USBCMD					0x00
++#define REG_USBSTS					0x04
++#define REG_PAGESIZE					0x08
++#define REG_DNCTRL					0x14
++#define REG_CRCR					0x18
++#define REG_DCBAAP_LOW					0x30
++#define REG_DCBAAP_HIGH					0x34
++#define REG_CONFIG					0x38
++
++#define REG_MFINDEX					0x00
++#define REG_IR0_IMAN					0x20
++#define REG_IR0_IMOD					0x24
++#define REG_IR0_ERSTSZ					0x28
++#define REG_IR0_ERSTBA_LOW				0x30
++#define REG_IR0_ERSTBA_HIGH				0x34
++#define REG_IR0_ERDP_LOW				0x38
++#define REG_IR0_ERDP_HIGH				0x3c
++
++#define REG_EXTCAP_USBLEGSUP				0x00
++#define REG_EXTCAP_USBLEGCTLSTS				0x04
++
++#define REG_EXTCAP_REVISION				0x00
++#define REG_EXTCAP_NAME					0x04
++#define REG_EXTCAP_PORTINFO				0x08
++#define REG_EXTCAP_PORTTYPE				0x0c
++#define REG_EXTCAP_MANTISSA1				0x10
++#define REG_EXTCAP_MANTISSA2				0x14
++#define REG_EXTCAP_MANTISSA3				0x18
++#define REG_EXTCAP_MANTISSA4				0x1c
++#define REG_EXTCAP_MANTISSA5				0x20
++#define REG_EXTCAP_MANTISSA6				0x24
++
++#define REG_EXTCAP_DBC_CAPABILITY			0x00
++#define REG_EXTCAP_DBC_DOORBELL				0x04
++#define REG_EXTCAP_DBC_ERSTSIZE				0x08
++#define REG_EXTCAP_DBC_ERST_LOW				0x10
++#define REG_EXTCAP_DBC_ERST_HIGH			0x14
++#define REG_EXTCAP_DBC_ERDP_LOW				0x18
++#define REG_EXTCAP_DBC_ERDP_HIGH			0x1c
++#define REG_EXTCAP_DBC_CONTROL				0x20
++#define REG_EXTCAP_DBC_STATUS				0x24
++#define REG_EXTCAP_DBC_PORTSC				0x28
++#define REG_EXTCAP_DBC_CONT_LOW				0x30
++#define REG_EXTCAP_DBC_CONT_HIGH			0x34
++#define REG_EXTCAP_DBC_DEVINFO1				0x38
++#define REG_EXTCAP_DBC_DEVINFO2				0x3c
++
++#define dump_register(nm)				\
++{							\
++	.name	= __stringify(nm),			\
++	.offset	= REG_ ##nm,				\
++}
++
++struct xhci_regset {
++	char			name[DEBUGFS_NAMELEN];
++	struct debugfs_regset32	regset;
++	size_t			nregs;
++	struct dentry		*parent;
++	struct list_head	list;
++};
++
++struct xhci_file_map {
++	const char		*name;
++	int			(*show)(struct seq_file *s, void *unused);
++};
++
++struct xhci_ep_priv {
++	char			name[DEBUGFS_NAMELEN];
++	struct dentry		*root;
++};
++
++struct xhci_slot_priv {
++	char			name[DEBUGFS_NAMELEN];
++	struct dentry		*root;
++	struct xhci_ep_priv	*eps[31];
++	struct xhci_virt_device	*dev;
++};
++
++#ifdef CONFIG_DEBUG_FS
++void xhci_debugfs_init(struct xhci_hcd *xhci);
++void xhci_debugfs_exit(struct xhci_hcd *xhci);
++void __init xhci_debugfs_create_root(void);
++void __exit xhci_debugfs_remove_root(void);
++void xhci_debugfs_create_slot(struct xhci_hcd *xhci, int slot_id);
++void xhci_debugfs_remove_slot(struct xhci_hcd *xhci, int slot_id);
++void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
++				  struct xhci_virt_device *virt_dev,
++				  int ep_index);
++void xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci,
++				  struct xhci_virt_device *virt_dev,
++				  int ep_index);
++#else
++static inline void xhci_debugfs_init(struct xhci_hcd *xhci) { }
++static inline void xhci_debugfs_exit(struct xhci_hcd *xhci) { }
++static inline void __init xhci_debugfs_create_root(void) { }
++static inline void __exit xhci_debugfs_remove_root(void) { }
++static inline void xhci_debugfs_create_slot(struct xhci_hcd *x, int s) { }
++static inline void xhci_debugfs_remove_slot(struct xhci_hcd *x, int s) { }
++static inline void
++xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
++			     struct xhci_virt_device *virt_dev,
++			     int ep_index) { }
++static inline void
++xhci_debugfs_remove_endpoint(struct xhci_hcd *xhci,
++			     struct xhci_virt_device *virt_dev,
++			     int ep_index) { }
++#endif /* CONFIG_DEBUG_FS */
++
++#endif /* __LINUX_XHCI_DEBUGFS_H */
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 17dcc8ae6859..477868b5b307 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -29,6 +29,7 @@
+ 
+ #include "xhci.h"
+ #include "xhci-trace.h"
++#include "xhci-debugfs.h"
+ 
+ /*
+  * Allocates a generic ring segment from the ring pool, sets the dma address,
+@@ -466,8 +467,6 @@ int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
+ 	return 0;
+ }
+ 
+-#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
+-
+ static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
+ 						    int type, gfp_t flags)
+ {
+@@ -971,6 +970,7 @@ void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
+ 	}
+ out:
+ 	/* we are now at a leaf device */
++	xhci_debugfs_remove_slot(xhci, slot_id);
+ 	xhci_free_virt_device(xhci, slot_id);
+ }
+ 
+@@ -1513,7 +1513,6 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
+ 	ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
+ 				      EP_AVG_TRB_LENGTH(avg_trb_len));
+ 
+-	/* FIXME Debug endpoint context */
+ 	return 0;
+ }
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index ae7acaa420c6..920bfb8162f7 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -33,6 +33,7 @@
+ #include "xhci.h"
+ #include "xhci-trace.h"
+ #include "xhci-mtk.h"
++#include "xhci-debugfs.h"
+ 
+ #define DRIVER_AUTHOR "Sarah Sharp"
+ #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
+@@ -633,6 +634,9 @@ int xhci_run(struct usb_hcd *hcd)
+ 	}
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"Finished xhci_run for USB2 roothub");
++
++	xhci_debugfs_init(xhci);
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(xhci_run);
+@@ -661,6 +665,8 @@ static void xhci_stop(struct usb_hcd *hcd)
+ 		return;
+ 	}
+ 
++	xhci_debugfs_exit(xhci);
++
+ 	spin_lock_irq(&xhci->lock);
+ 	xhci->xhc_state |= XHCI_STATE_HALTED;
+ 	xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
+@@ -1643,6 +1649,8 @@ static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+ 	ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
+ 	new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
+ 
++	xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
++
+ 	xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
+ 
+ 	if (xhci->quirks & XHCI_MTK_HOST)
+@@ -1766,6 +1774,8 @@ static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+ 	/* Store the usb_device pointer for later use */
+ 	ep->hcpriv = udev;
+ 
++	xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
++
+ 	xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
+ 			(unsigned int) ep->desc.bEndpointAddress,
+ 			udev->slot_id,
+@@ -2816,6 +2826,7 @@ static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+ 	/* Free any rings allocated for added endpoints */
+ 	for (i = 0; i < 31; i++) {
+ 		if (virt_dev->eps[i].new_ring) {
++			xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
+ 			xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
+ 			virt_dev->eps[i].new_ring = NULL;
+ 		}
+@@ -3531,6 +3542,7 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
+ 		}
+ 
+ 		if (ep->ring) {
++			xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
+ 			xhci_free_endpoint_ring(xhci, virt_dev, i);
+ 			last_freed_endpoint = i;
+ 		}
+@@ -3564,6 +3576,8 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	struct xhci_slot_ctx *slot_ctx;
+ 	int i, ret;
+ 
++	xhci_debugfs_remove_slot(xhci, udev->slot_id);
++
+ #ifndef CONFIG_USB_DEFAULT_PERSIST
+ 	/*
+ 	 * We called pm_runtime_get_noresume when the device was attached.
+@@ -3727,6 +3741,8 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 
+ 	udev->slot_id = slot_id;
+ 
++	xhci_debugfs_create_slot(xhci, slot_id);
++
+ #ifndef CONFIG_USB_DEFAULT_PERSIST
+ 	/*
+ 	 * If resetting upon resume, we can't put the controller into runtime
+@@ -5040,6 +5056,8 @@ static int __init xhci_hcd_init(void)
+ 	if (usb_disabled())
+ 		return -ENODEV;
+ 
++	xhci_debugfs_create_root();
++
+ 	return 0;
+ }
+ 
+@@ -5047,7 +5065,10 @@ static int __init xhci_hcd_init(void)
+  * If an init function is provided, an exit function must also be provided
+  * to allow module unload.
+  */
+-static void __exit xhci_hcd_fini(void) { }
++static void __exit xhci_hcd_fini(void)
++{
++	xhci_debugfs_remove_root();
++}
+ 
+ module_init(xhci_hcd_init);
+ module_exit(xhci_hcd_fini);
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index b1ef8fe056eb..3ece11154a31 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -132,6 +132,8 @@ struct xhci_cap_regs {
+ /* Extended Capabilities pointer from PCI base - section 5.3.6 */
+ #define HCC_EXT_CAPS(p)		XHCI_HCC_EXT_CAPS(p)
+ 
++#define CTX_SIZE(_hcc)		(HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
++
+ /* db_off bitmask - bits 0:1 reserved */
+ #define	DBOFF_MASK	(~0x3)
+ 
+@@ -1013,6 +1015,8 @@ struct xhci_virt_device {
+ 	struct xhci_tt_bw_info		*tt_info;
+ 	/* The current max exit latency for the enabled USB3 link states. */
+ 	u16				current_mel;
++	/* Used for the debugfs interfaces. */
++	void				*debugfs_private;
+ };
+ 
+ /*
+@@ -1867,6 +1871,10 @@ struct xhci_hcd {
+ /* Compliance Mode Timer Triggered every 2 seconds */
+ #define COMP_MODE_RCVRY_MSECS 2000
+ 
++	struct dentry		*debugfs_root;
++	struct dentry		*debugfs_slots;
++	struct list_head	regset_list;
++
+ 	/* platform-specific data -- must come last */
+ 	unsigned long		priv[0] __aligned(sizeof(s64));
+ };
+@@ -2114,6 +2122,7 @@ struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container
+ struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
+ 		unsigned int slot_id, unsigned int ep_index,
+ 		unsigned int stream_id);
++
+ static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
+ 								struct urb *urb)
+ {
+-- 
+2.19.0
+
diff --git a/patches/0249-usb-xhci-Fix-memory-leak-when-xhci_disable_slot-retu.patch b/patches/0249-usb-xhci-Fix-memory-leak-when-xhci_disable_slot-retu.patch
new file mode 100644
index 00000000000000..02d55b5c7e7663
--- /dev/null
+++ b/patches/0249-usb-xhci-Fix-memory-leak-when-xhci_disable_slot-retu.patch
@@ -0,0 +1,62 @@
+From f209a74adc0dd4319e563dfd7e4a6cd3cae8b161 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:42 +0300
+Subject: [PATCH 0249/1795] usb: xhci: Fix memory leak when xhci_disable_slot()
+ returns error
+
+If xhci_disable_slot() returns success, a disable slot command
+trb was queued in the command ring. The command completion
+handler will free the virtual device data structure associated
+with the slot. On the other hand, when xhci_disable_slot()
+returns error, the invokers should take the responsibilities to
+free the slot related data structure. Otherwise, memory leakage
+happens.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 11ec7588a10d4bc2e1e385ac565d2166d375fba1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/host/xhci.c
+---
+ drivers/usb/host/xhci.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 920bfb8162f7..6dc536fa2e3b 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3606,11 +3606,9 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	}
+ 
+ 	virt_dev->udev = NULL;
+-	xhci_disable_slot(xhci, udev->slot_id);
+-	/*
+-	 * Event command completion handler will free any data structures
+-	 * associated with the slot.  XXX Can free sleep?
+-	 */
++	ret = xhci_disable_slot(xhci, udev->slot_id);
++	if (ret)
++		xhci_free_virt_device(xhci, udev->slot_id);
+ }
+ 
+ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
+@@ -3757,7 +3755,11 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	return 1;
+ 
+ disable_slot:
+-	return xhci_disable_slot(xhci, udev->slot_id);
++	ret = xhci_disable_slot(xhci, udev->slot_id);
++	if (ret)
++		xhci_free_virt_device(xhci, udev->slot_id);
++
++	return 0;
+ }
+ 
+ /*
+-- 
+2.19.0
+
diff --git a/patches/0250-usb-xhci-Remove-xhci-mutex-from-xhci_alloc_dev.patch b/patches/0250-usb-xhci-Remove-xhci-mutex-from-xhci_alloc_dev.patch
new file mode 100644
index 00000000000000..054d572e8e0ab8
--- /dev/null
+++ b/patches/0250-usb-xhci-Remove-xhci-mutex-from-xhci_alloc_dev.patch
@@ -0,0 +1,57 @@
+From 0c8a4aadaeef8a7285610ea591b52bdfe4cc7d85 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:44 +0300
+Subject: [PATCH 0250/1795] usb: xhci: Remove xhci->mutex from xhci_alloc_dev()
+
+xhci->mutex was added in xhci_alloc_dev()  to protect two race sources
+(xhci->slot_id and xhci->addr_dev) by commit a00918d0521d ("usb: host:
+xhci: add mutex for non-thread-safe data").
+
+While xhci->slot_id has been discarded in commit c2d3d49bba08 ("usb:
+xhci: move slot_id from xhci_hcd to xhci_command structure"), and
+xhci->addr_dev has been removed in commit 87e44f2aac8d ("usb: xhci:
+remove the use of xhci->addr_dev"), it's now safe to remove the use of
+xhci->mutex in xhci_alloc_dev().
+
+Link: https://marc.info/?l=linux-usb&m=150306294725821&w=2
+
+Suggested-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 089ed4904e948f93a82ebf62b068ae55aec852ab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 6dc536fa2e3b..2ac8f8622f8c 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3684,13 +3684,10 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	if (!command)
+ 		return 0;
+ 
+-	/* xhci->slot_id and xhci->addr_dev are not thread-safe */
+-	mutex_lock(&xhci->mutex);
+ 	spin_lock_irqsave(&xhci->lock, flags);
+ 	ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
+ 	if (ret) {
+ 		spin_unlock_irqrestore(&xhci->lock, flags);
+-		mutex_unlock(&xhci->mutex);
+ 		xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
+ 		xhci_free_command(xhci, command);
+ 		return 0;
+@@ -3700,7 +3697,6 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 
+ 	wait_for_completion(command->completion);
+ 	slot_id = command->slot_id;
+-	mutex_unlock(&xhci->mutex);
+ 
+ 	if (!slot_id || command->status != COMP_SUCCESS) {
+ 		xhci_err(xhci, "Error while assigning device slot ID\n");
+-- 
+2.19.0
+
diff --git a/patches/0251-usb-xhci-Handle-USB-transaction-error-on-address-com.patch b/patches/0251-usb-xhci-Handle-USB-transaction-error-on-address-com.patch
new file mode 100644
index 00000000000000..ce703ff76c283a
--- /dev/null
+++ b/patches/0251-usb-xhci-Handle-USB-transaction-error-on-address-com.patch
@@ -0,0 +1,58 @@
+From 6eb3a1a5206dfa2fc00402d2915ad0a4ed6973ac Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:45 +0300
+Subject: [PATCH 0251/1795] usb: xhci: Handle USB transaction error on address
+ command
+
+Xhci driver handles USB transaction errors on transfer events,
+but transaction errors are possible on address device command
+completion events as well.
+
+The xHCI specification (section 4.6.5) says: A USB Transaction
+Error Completion Code for an Address Device Command may be due
+to a Stall response from a device. Software should issue a Disable
+Slot Command for the Device Slot then an Enable Slot Command to
+recover from this error.
+
+This patch handles USB transaction errors on address command
+completion events. The related discussion threads can be found
+through below links.
+
+http://marc.info/?l=linux-usb&m=149362010728921&w=2
+http://marc.info/?l=linux-usb&m=149252752825755&w=2
+
+Suggested-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 651aaf36a7d7b36a58980e70133f9437d4f6d312)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 2ac8f8622f8c..e13f9bb99baf 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3879,8 +3879,14 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
+ 		break;
+ 	case COMP_USB_TRANSACTION_ERROR:
+ 		dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
+-		ret = -EPROTO;
+-		break;
++
++		mutex_unlock(&xhci->mutex);
++		ret = xhci_disable_slot(xhci, udev->slot_id);
++		if (!ret)
++			xhci_alloc_dev(hcd, udev);
++		kfree(command->completion);
++		kfree(command);
++		return -EPROTO;
+ 	case COMP_INCOMPATIBLE_DEVICE_ERROR:
+ 		dev_warn(&udev->dev,
+ 			 "ERROR: Incompatible device for setup %s command\n", act);
+-- 
+2.19.0
+
diff --git a/patches/0252-usb-xhci-reduce-device-initiated-resume-time-varianc.patch b/patches/0252-usb-xhci-reduce-device-initiated-resume-time-varianc.patch
new file mode 100644
index 00000000000000..9b77089b625035
--- /dev/null
+++ b/patches/0252-usb-xhci-reduce-device-initiated-resume-time-varianc.patch
@@ -0,0 +1,90 @@
+From bb3bc9048a1b8947369989c20df077e22adcd0db Mon Sep 17 00:00:00 2001
+From: Anshuman Gupta <anshuman.gupta@intel.com>
+Date: Thu, 5 Oct 2017 11:21:46 +0300
+Subject: [PATCH 0252/1795] usb: xhci: reduce device initiated resume time
+ variance.
+
+This patch will improve the variable auto-resume latency of an usb-port.
+
+The attempt to sync the start of root hub polling with resume time
+signaling finish was ruined by a later request to start immediate
+root hub polling.
+
+When xhci gets a port status change event interrupt due to PORT_PLC
+(port link state transition), linux Host controller driver drives the
+resume signalling on the bus for the amount of time defined by
+USB_REUME_TIMEOUT(40ms) macro.
+
+This 40ms delay for resume signalling is in acceptable limit, but
+it get worse when xhci goes for polling mode in order to detect other
+events on its ports and modify rh_timer timer with a variable time out of
+1ms to (HZ/4)ms.
+
+drivers/usb/core/hcd.c line 799
+mod_timer (&hcd->rh_timer, (jiffies/(HZ/4) + 1) * (HZ/4)).
+
+Due to above variable timeout usb auto-resume latency varies from
+40ms to ~300ms.
+
+Log Snippet:
+~128ms latency
+[   53.112049] hub 1-0:1.0: state 7 ports 12 chg 0000 evt 0000
+[   53.229200] hub 1-0:1.0: state 7 ports 12 chg 0000 evt 0004
+[   53.240177] usb 1-2: usb wakeup-resume
+[   53.240195] usb 1-2: finish resume
+[   53.240357] usb usb1-port2: resume, status 0
+-----------------------------------------------------------------
+~300ms latency
+[   59.946620] hub 1-0:1.0: state 7 ports 12 chg 0000 evt 0000
+[   59.979341] hub 1-0:1.0: state 7 ports 12 chg 0000 evt 0000
+[   60.229342] hub 1-0:1.0: state 7 ports 12 chg 0000 evt 0004
+[   60.251321] usb 1-2: usb wakeup-resume
+[   60.251335] usb 1-2: finish resume
+[   60.251539] usb usb1-port2: resume, status 0
+
+This variable resume latency can be optimized, as in case of PORT_PLC
+change event rh_timer has already been modified with USB_RESUME_TIMEOUT
+(40ms) delay,leaving the rest to GetPortStatus and started polling for
+root hub status (invoking usb_hcd_poll_rh_status).
+We can avoid polling as we have already modified rh_timer with
+delay of 40ms.
+
+This patch set the HCD_FLAG_POLL_RH to hcd->flags after modification of
+rh_timer, and avoids polling of root hub status. so rh_timer can fire
+after 40ms and usb device auto-resuem latency will be around 40ms.
+
+[topic and first two senctences of commit message changed -Mathias]
+Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 0914ea66d24c045cdc4f424342057980e86629cf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 3a50897ed766..91cab441b82f 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1681,9 +1681,14 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 			bus_state->resume_done[faked_port_index] = jiffies +
+ 				msecs_to_jiffies(USB_RESUME_TIMEOUT);
+ 			set_bit(faked_port_index, &bus_state->resuming_ports);
++			/* Do the rest in GetPortStatus after resume time delay.
++			 * Avoid polling roothub status before that so that a
++			 * usb device auto-resume latency around ~40ms.
++			 */
++			set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+ 			mod_timer(&hcd->rh_timer,
+ 				  bus_state->resume_done[faked_port_index]);
+-			/* Do the rest in GetPortStatus */
++			bogus_port_status = true;
+ 		}
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0253-xhci-allow-TRACE-to-work-with-EVENT-ring-dequeue.patch b/patches/0253-xhci-allow-TRACE-to-work-with-EVENT-ring-dequeue.patch
new file mode 100644
index 00000000000000..df7d43c9c4dc28
--- /dev/null
+++ b/patches/0253-xhci-allow-TRACE-to-work-with-EVENT-ring-dequeue.patch
@@ -0,0 +1,56 @@
+From a8c2b0929f10346e095fdc1fb0964a01e3db18fc Mon Sep 17 00:00:00 2001
+From: Adam Wallis <awallis@codeaurora.org>
+Date: Thu, 5 Oct 2017 11:21:47 +0300
+Subject: [PATCH 0253/1795] xhci: allow TRACE to work with EVENT ring dequeue
+
+inc_deq() currently bails earlier for EVENT rings than the common return
+point of the function, due to the fact that EVENT rings do not have
+link TRBs. The unfortunate side effect of this is that the very useful
+trace_xhci_inc_deq() function is not called/usable for EVENT ring
+debug.
+
+This patch provides a refactor by removing the multiple return exit
+points into a single return which additionally allows for all rings to
+use the trace function.
+
+Signed-off-by: Adam Wallis <awallis@codeaurora.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 49d5b05e191d4486c125ff00a01fc5e9e7ba452c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 91cab441b82f..d5f44776b360 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -172,13 +172,13 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
+ 	if (ring->type == TYPE_EVENT) {
+ 		if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
+ 			ring->dequeue++;
+-			return;
++			goto out;
+ 		}
+ 		if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
+ 			ring->cycle_state ^= 1;
+ 		ring->deq_seg = ring->deq_seg->next;
+ 		ring->dequeue = ring->deq_seg->trbs;
+-		return;
++		goto out;
+ 	}
+ 
+ 	/* All other rings have link trbs */
+@@ -191,6 +191,7 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
+ 		ring->dequeue = ring->deq_seg->trbs;
+ 	}
+ 
++out:
+ 	trace_xhci_inc_deq(ring);
+ 
+ 	return;
+-- 
+2.19.0
+
diff --git a/patches/0254-xhci-trace-slot-context-when-calling-xhci_configure_.patch b/patches/0254-xhci-trace-slot-context-when-calling-xhci_configure_.patch
new file mode 100644
index 00000000000000..acb79d682b6e2f
--- /dev/null
+++ b/patches/0254-xhci-trace-slot-context-when-calling-xhci_configure_.patch
@@ -0,0 +1,60 @@
+From 48d08f105349df89d0e30287bb4a7d330f705736 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Thu, 5 Oct 2017 11:21:48 +0300
+Subject: [PATCH 0254/1795] xhci: trace slot context when calling
+ xhci_configure_endpoint()
+
+Add trace showing content of input slot context for
+configure endpoint and evaluate context commands
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit e3a78ff022c64b518d3efd9ea0f26a784dc0b629)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-trace.h | 5 +++++
+ drivers/usb/host/xhci.c       | 4 ++++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index 447edc6343d2..183ed1cf2138 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -415,6 +415,11 @@ DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_set_deq,
+ 	TP_ARGS(ctx)
+ );
+ 
++DEFINE_EVENT(xhci_log_slot_ctx, xhci_configure_endpoint,
++	TP_PROTO(struct xhci_slot_ctx *ctx),
++	TP_ARGS(ctx)
++);
++
+ DECLARE_EVENT_CLASS(xhci_log_ring,
+ 	TP_PROTO(struct xhci_ring *ring),
+ 	TP_ARGS(ring),
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index e13f9bb99baf..1af90f1c59e8 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -2608,6 +2608,7 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci,
+ 	unsigned long flags;
+ 	struct xhci_input_control_ctx *ctrl_ctx;
+ 	struct xhci_virt_device *virt_dev;
++	struct xhci_slot_ctx *slot_ctx;
+ 
+ 	if (!command)
+ 		return -EINVAL;
+@@ -2646,6 +2647,9 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci,
+ 		return -ENOMEM;
+ 	}
+ 
++	slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
++	trace_xhci_configure_endpoint(slot_ctx);
++
+ 	if (!ctx_change)
+ 		ret = xhci_queue_configure_endpoint(xhci, command,
+ 				command->in_ctx->dma,
+-- 
+2.19.0
+
diff --git a/patches/0255-usb-host-xhci-plat-Use-of_device_get_match_data-help.patch b/patches/0255-usb-host-xhci-plat-Use-of_device_get_match_data-help.patch
new file mode 100644
index 00000000000000..48eb9a164b55a8
--- /dev/null
+++ b/patches/0255-usb-host-xhci-plat-Use-of_device_get_match_data-help.patch
@@ -0,0 +1,54 @@
+From 0619363d176d80ae9655a48ac605354787b15c5a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 5 Oct 2017 11:21:49 +0300
+Subject: [PATCH 0255/1795] usb: host: xhci-plat: Use
+ of_device_get_match_data() helper
+
+Use the of_device_get_match_data() helper instead of open coding.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 2847d242a1e48ca734cee742efa0f70abf545d1e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-plat.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 5340e4ad8d13..c79d8914f67a 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -17,6 +17,7 @@
+ #include <linux/module.h>
+ #include <linux/pci.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/usb/phy.h>
+ #include <linux/slab.h>
+@@ -153,7 +154,7 @@ MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
+ 
+ static int xhci_plat_probe(struct platform_device *pdev)
+ {
+-	const struct of_device_id *match;
++	const struct xhci_plat_priv *priv_match;
+ 	const struct hc_driver	*driver;
+ 	struct device		*sysdev;
+ 	struct xhci_hcd		*xhci;
+@@ -243,9 +244,8 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	xhci = hcd_to_xhci(hcd);
+-	match = of_match_node(usb_xhci_of_match, pdev->dev.of_node);
+-	if (match) {
+-		const struct xhci_plat_priv *priv_match = match->data;
++	priv_match = of_device_get_match_data(&pdev->dev);
++	if (priv_match) {
+ 		struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
+ 
+ 		/* Just copy data for now */
+-- 
+2.19.0
+
diff --git a/patches/0256-xhci-Convert-timers-to-use-timer_setup.patch b/patches/0256-xhci-Convert-timers-to-use-timer_setup.patch
new file mode 100644
index 00000000000000..749532caf09d4a
--- /dev/null
+++ b/patches/0256-xhci-Convert-timers-to-use-timer_setup.patch
@@ -0,0 +1,77 @@
+From 657d0af147d88ecdf0ed98d7758fd5e00457053f Mon Sep 17 00:00:00 2001
+From: Kees Cook <keescook@chromium.org>
+Date: Mon, 16 Oct 2017 16:16:58 -0700
+Subject: [PATCH 0256/1795] xhci: Convert timers to use timer_setup()
+
+In preparation for unconditionally passing the struct timer_list pointer to
+all timer callbacks, switch to using the new timer_setup() and from_timer()
+to pass the timer pointer explicitly.
+
+Cc: Mathias Nyman <mathias.nyman@intel.com>
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: linux-usb@vger.kernel.org
+Signed-off-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 66a4550308b8391fecd46c7e733cbccb3e01ee96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-mem.c  | 4 ++--
+ drivers/usb/host/xhci-ring.c | 9 +++------
+ drivers/usb/host/xhci.h      | 2 +-
+ 3 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 477868b5b307..d10129e664fd 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -801,8 +801,8 @@ void xhci_free_stream_info(struct xhci_hcd *xhci,
+ static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
+ 		struct xhci_virt_ep *ep)
+ {
+-	setup_timer(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
+-		    (unsigned long)ep);
++	timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
++		    0);
+ 	ep->xhci = xhci;
+ }
+ 
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index d5f44776b360..54231beef4f5 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -948,15 +948,12 @@ void xhci_hc_died(struct xhci_hcd *xhci)
+  * Instead we use a combination of that flag and checking if a new timer is
+  * pending.
+  */
+-void xhci_stop_endpoint_command_watchdog(unsigned long arg)
++void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
+ {
+-	struct xhci_hcd *xhci;
+-	struct xhci_virt_ep *ep;
++	struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
++	struct xhci_hcd *xhci = ep->xhci;
+ 	unsigned long flags;
+ 
+-	ep = (struct xhci_virt_ep *) arg;
+-	xhci = ep->xhci;
+-
+ 	spin_lock_irqsave(&xhci->lock, flags);
+ 
+ 	/* bail out if cmd completed but raced with stop ep watchdog timer.*/
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 3ece11154a31..fd13ae14c28b 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2083,7 +2083,7 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
+ 		struct xhci_dequeue_state *deq_state);
+ void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
+ 		unsigned int stream_id, struct xhci_td *td);
+-void xhci_stop_endpoint_command_watchdog(unsigned long arg);
++void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
+ void xhci_handle_command_timeout(struct work_struct *work);
+ 
+ void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
+-- 
+2.19.0
+
diff --git a/patches/0257-usb-host-xhci-mark-expected-switch-fall-through.patch b/patches/0257-usb-host-xhci-mark-expected-switch-fall-through.patch
new file mode 100644
index 00000000000000..52299d09b4fb52
--- /dev/null
+++ b/patches/0257-usb-host-xhci-mark-expected-switch-fall-through.patch
@@ -0,0 +1,32 @@
+From 1b4c6eb98b397c9261b6f2096332d416c0216df5 Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
+Date: Wed, 25 Oct 2017 13:49:01 -0500
+Subject: [PATCH 0257/1795] usb: host: xhci: mark expected switch fall-through
+
+In preparation to enabling -Wimplicit-fallthrough, mark switch cases
+where we are expecting to fall through.
+
+Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 7d864999814e777fe083c2fd156112ccf9058882)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 1af90f1c59e8..19bd1c1df9cc 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -4338,6 +4338,7 @@ static unsigned long long xhci_calculate_intel_u1_timeout(
+ 			break;
+ 		}
+ 		/* Otherwise the calculation is the same as isoc eps */
++		/* fall through */
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 		timeout_ns = xhci_service_interval_to_ns(desc);
+ 		timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
+-- 
+2.19.0
+
diff --git a/patches/0258-usb-host-xhci-mem-mark-expected-switch-fall-through.patch b/patches/0258-usb-host-xhci-mem-mark-expected-switch-fall-through.patch
new file mode 100644
index 00000000000000..478a470c29f445
--- /dev/null
+++ b/patches/0258-usb-host-xhci-mem-mark-expected-switch-fall-through.patch
@@ -0,0 +1,33 @@
+From dab4d700bd90cffdd04e75c7b8df74438907ea4d Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
+Date: Wed, 25 Oct 2017 13:49:10 -0500
+Subject: [PATCH 0258/1795] usb: host: xhci-mem: mark expected switch
+ fall-through
+
+In preparation to enabling -Wimplicit-fallthrough, mark switch cases
+where we are expecting to fall through.
+
+Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1356cedd99aab15a60c4c4ade79e52c4b5200fdf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-mem.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index d10129e664fd..804aef5d4e47 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -1328,6 +1328,7 @@ static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
+ 		 * since it uses the same rules as low speed interrupt
+ 		 * endpoints.
+ 		 */
++		/* fall through */
+ 
+ 	case USB_SPEED_LOW:
+ 		if (usb_endpoint_xfer_int(&ep->desc) ||
+-- 
+2.19.0
+
diff --git a/patches/0259-usb-host-xhci-hub-mark-expected-switch-fall-through.patch b/patches/0259-usb-host-xhci-hub-mark-expected-switch-fall-through.patch
new file mode 100644
index 00000000000000..bea3de470282a0
--- /dev/null
+++ b/patches/0259-usb-host-xhci-hub-mark-expected-switch-fall-through.patch
@@ -0,0 +1,33 @@
+From ceec8275dc8d6704c0d041f86e80a666593d9dbf Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
+Date: Wed, 25 Oct 2017 13:49:38 -0500
+Subject: [PATCH 0259/1795] usb: host: xhci-hub: mark expected switch
+ fall-through
+
+In preparation to enabling -Wimplicit-fallthrough, mark switch cases
+where we are expecting to fall through.
+
+Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ff504f572cf8667414a44e88c06ea0d421b42566)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index fff62fe0a097..8e4345cb89e9 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -1378,6 +1378,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			break;
+ 		case USB_PORT_FEAT_C_SUSPEND:
+ 			bus_state->port_c_suspend &= ~(1 << wIndex);
++			/* fall through */
+ 		case USB_PORT_FEAT_C_RESET:
+ 		case USB_PORT_FEAT_C_BH_PORT_RESET:
+ 		case USB_PORT_FEAT_C_CONNECTION:
+-- 
+2.19.0
+
diff --git a/patches/0260-USB-host-xhci-Remove-redundant-license-text.patch b/patches/0260-USB-host-xhci-Remove-redundant-license-text.patch
new file mode 100644
index 00000000000000..88df1a97aace57
--- /dev/null
+++ b/patches/0260-USB-host-xhci-Remove-redundant-license-text.patch
@@ -0,0 +1,472 @@
+From 79d6077c4e3b925b73104bb9b1ed6169f01fdd1e Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Mon, 6 Nov 2017 15:37:23 +0100
+Subject: [PATCH 0260/1795] USB: host: xhci: Remove redundant license text
+
+Now that the SPDX tag is in all USB files, that identifies the license
+in a specific and legally-defined manner.  So the extra GPL text wording
+can be removed as it is no longer needed at all.
+
+This is done on a quest to remove the 700+ different ways that files in
+the kernel describe the GPL license text.  And there's unneeded stuff
+like the address (sometimes incorrect) for the FSF which is never
+needed.
+
+No copyright headers or other non-license-description text was removed.
+
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: Thierry Reding <thierry.reding@gmail.com>
+Cc: Jonathan Hunter <jonathanh@nvidia.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 9ed64195e35efa8901d20a0cd8ff3668ae68e7d6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-dbg.c      | 13 -------------
+ drivers/usb/host/xhci-debugfs.c  |  4 ----
+ drivers/usb/host/xhci-debugfs.h  |  4 ----
+ drivers/usb/host/xhci-ext-caps.h | 13 -------------
+ drivers/usb/host/xhci-hub.c      | 13 -------------
+ drivers/usb/host/xhci-mem.c      | 13 -------------
+ drivers/usb/host/xhci-mtk-sch.c  | 10 ----------
+ drivers/usb/host/xhci-mtk.c      | 10 ----------
+ drivers/usb/host/xhci-mtk.h      | 10 ----------
+ drivers/usb/host/xhci-mvebu.c    |  4 ----
+ drivers/usb/host/xhci-mvebu.h    |  4 ----
+ drivers/usb/host/xhci-pci.c      | 13 -------------
+ drivers/usb/host/xhci-plat.c     |  4 ----
+ drivers/usb/host/xhci-plat.h     |  4 ----
+ drivers/usb/host/xhci-rcar.c     |  4 ----
+ drivers/usb/host/xhci-rcar.h     |  4 ----
+ drivers/usb/host/xhci-ring.c     | 13 -------------
+ drivers/usb/host/xhci-tegra.c    |  4 ----
+ drivers/usb/host/xhci-trace.c    |  4 ----
+ drivers/usb/host/xhci-trace.h    |  4 ----
+ drivers/usb/host/xhci.c          | 13 -------------
+ drivers/usb/host/xhci.h          | 13 -------------
+ 22 files changed, 178 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
+index 83904170be5c..584d7b9a3683 100644
+--- a/drivers/usb/host/xhci-dbg.c
++++ b/drivers/usb/host/xhci-dbg.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #include "xhci.h"
+diff --git a/drivers/usb/host/xhci-debugfs.c b/drivers/usb/host/xhci-debugfs.c
+index 6772ee90944b..b799ed83cc7a 100644
+--- a/drivers/usb/host/xhci-debugfs.c
++++ b/drivers/usb/host/xhci-debugfs.c
+@@ -4,10 +4,6 @@
+  * Copyright (C) 2017 Intel Corporation
+  *
+  * Author: Lu Baolu <baolu.lu@linux.intel.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #include <linux/slab.h>
+diff --git a/drivers/usb/host/xhci-debugfs.h b/drivers/usb/host/xhci-debugfs.h
+index 3adc9976f180..09cfd3998125 100644
+--- a/drivers/usb/host/xhci-debugfs.h
++++ b/drivers/usb/host/xhci-debugfs.h
+@@ -4,10 +4,6 @@
+  * Copyright (C) 2017 Intel Corporation
+  *
+  * Author: Lu Baolu <baolu.lu@linux.intel.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #ifndef __LINUX_XHCI_DEBUGFS_H
+diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
+index 259963bbe3aa..bf7316e130d3 100644
+--- a/drivers/usb/host/xhci-ext-caps.h
++++ b/drivers/usb/host/xhci-ext-caps.h
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ /* Up to 16 ms to halt an HC */
+ #define XHCI_MAX_HALT_USEC	(16*1000)
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 8e4345cb89e9..0fb3fec94e04 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ 
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 804aef5d4e47..c44f09f17f5e 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #include <linux/usb.h>
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+index 42e4701ee944..449c143c0574 100644
+--- a/drivers/usb/host/xhci-mtk-sch.c
++++ b/drivers/usb/host/xhci-mtk-sch.c
+@@ -4,16 +4,6 @@
+  * Author:
+  *  Zhigang.Wei <zhigang.wei@mediatek.com>
+  *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #include <linux/kernel.h>
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 4e2fb05282a6..95f583f41bfd 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -5,16 +5,6 @@
+  * Copyright (c) 2015 MediaTek Inc.
+  * Author:
+  *  Chunfeng Yun <chunfeng.yun@mediatek.com>
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 047d1a60341b..1aec83460574 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -4,16 +4,6 @@
+  * Author:
+  *  Zhigang.Wei <zhigang.wei@mediatek.com>
+  *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
+- *
+- * This software is licensed under the terms of the GNU General Public
+- * License version 2, as published by the Free Software Foundation, and
+- * may be copied, distributed, and modified under those terms.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+  */
+ 
+ #ifndef _XHCI_MTK_H_
+diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
+index fe7a2f84faeb..32e158568788 100644
+--- a/drivers/usb/host/xhci-mvebu.c
++++ b/drivers/usb/host/xhci-mvebu.c
+@@ -2,10 +2,6 @@
+ /*
+  * Copyright (C) 2014 Marvell
+  * Author: Gregory CLEMENT <gregory.clement@free-electrons.com>
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+  */
+ 
+ #include <linux/io.h>
+diff --git a/drivers/usb/host/xhci-mvebu.h b/drivers/usb/host/xhci-mvebu.h
+index 619792ae75b8..09791df2cec0 100644
+--- a/drivers/usb/host/xhci-mvebu.h
++++ b/drivers/usb/host/xhci-mvebu.h
+@@ -3,10 +3,6 @@
+  * Copyright (C) 2014 Marvell
+  *
+  * Gregory Clement <gregory.clement@free-electrons.com>
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2.  This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #ifndef __LINUX_XHCI_MVEBU_H
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index dd4b5e2615cf..c3ae5784649a 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #include <linux/pci.h>
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index c79d8914f67a..833ca511fd35 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -6,10 +6,6 @@
+  * Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+  *
+  * A lot of code borrowed from the Linux xHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/usb/host/xhci-plat.h b/drivers/usb/host/xhci-plat.h
+index ac8f8eb0bf49..ae29f22ff5bd 100644
+--- a/drivers/usb/host/xhci-plat.h
++++ b/drivers/usb/host/xhci-plat.h
+@@ -3,10 +3,6 @@
+  * xhci-plat.h - xHCI host controller driver platform Bus Glue.
+  *
+  * Copyright (C) 2015 Renesas Electronics Corporation
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+  */
+ 
+ #ifndef _XHCI_PLAT_H
+diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
+index 407fa95f7122..f33ffc2bc4ed 100644
+--- a/drivers/usb/host/xhci-rcar.c
++++ b/drivers/usb/host/xhci-rcar.c
+@@ -3,10 +3,6 @@
+  * xHCI host controller driver for R-Car SoCs
+  *
+  * Copyright (C) 2014 Renesas Electronics Corporation
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+  */
+ 
+ #include <linux/firmware.h>
+diff --git a/drivers/usb/host/xhci-rcar.h b/drivers/usb/host/xhci-rcar.h
+index 162706528c4c..804b6ab4246f 100644
+--- a/drivers/usb/host/xhci-rcar.h
++++ b/drivers/usb/host/xhci-rcar.h
+@@ -3,10 +3,6 @@
+  * drivers/usb/host/xhci-rcar.h
+  *
+  * Copyright (C) 2014 Renesas Electronics Corporation
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+  */
+ 
+ #ifndef _XHCI_RCAR_H
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 54231beef4f5..c5cbc685c691 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ /*
+diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
+index 6197fce3dce2..da808645f4b7 100644
+--- a/drivers/usb/host/xhci-tegra.c
++++ b/drivers/usb/host/xhci-tegra.c
+@@ -4,10 +4,6 @@
+  *
+  * Copyright (C) 2014 NVIDIA Corporation
+  * Copyright (C) 2014 Google, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/usb/host/xhci-trace.c b/drivers/usb/host/xhci-trace.c
+index 0be3e83025ae..d0070814d1ea 100644
+--- a/drivers/usb/host/xhci-trace.c
++++ b/drivers/usb/host/xhci-trace.c
+@@ -6,10 +6,6 @@
+  *
+  * Author: Xenia Ragiadakou
+  * Email : burzalodowa@gmail.com
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #define CREATE_TRACE_POINTS
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index 183ed1cf2138..f6cbf6190c60 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -6,10 +6,6 @@
+  *
+  * Author: Xenia Ragiadakou
+  * Email : burzalodowa@gmail.com
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+  */
+ 
+ #undef TRACE_SYSTEM
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 19bd1c1df9cc..4bceebb965ca 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -6,19 +6,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #include <linux/pci.h>
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index fd13ae14c28b..5f1fe671b694 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -7,19 +7,6 @@
+  *
+  * Author: Sarah Sharp
+  * Some code borrowed from the Linux EHCI driver.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+- * for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software Foundation,
+- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+ 
+ #ifndef __LINUX_XHCI_HCD_H
+-- 
+2.19.0
+
diff --git a/patches/0261-xhci-Fix-xhci-debugfs-NULL-pointer-dereference-in-re.patch b/patches/0261-xhci-Fix-xhci-debugfs-NULL-pointer-dereference-in-re.patch
new file mode 100644
index 00000000000000..885082b4d75912
--- /dev/null
+++ b/patches/0261-xhci-Fix-xhci-debugfs-NULL-pointer-dereference-in-re.patch
@@ -0,0 +1,55 @@
+From 244b4f620363b798348f0302d62c8b36db28e2d5 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Thu, 21 Dec 2017 15:06:13 +0200
+Subject: [PATCH 0261/1795] xhci: Fix xhci debugfs NULL pointer dereference in
+ resume from hibernate
+
+Free the virt_device and its debugfs_private member together.
+
+When resuming from hibernate the .free_dev callback unconditionally
+freed the debugfs_private member, but could leave virt_device intact.
+
+This triggered a NULL pointer dereference after resume when usbmuxd
+sent a USBDEVFS_SETCONFIGURATION ioctl to a device, trying to add a
+endpoint debugfs entry to a already freed debugfs_private pointer.
+
+Fixes: 02b6fdc2a153 ("usb: xhci: Add debugfs interface for xHCI driver")
+Reported-by: Alexander Kappner <agk@godking.net>
+Tested-by: Alexander Kappner <agk@godking.net>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 052f71e25a7ecd80a9567b291df8ea333d9a8565)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 4bceebb965ca..05d45079a259 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3567,8 +3567,6 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	struct xhci_slot_ctx *slot_ctx;
+ 	int i, ret;
+ 
+-	xhci_debugfs_remove_slot(xhci, udev->slot_id);
+-
+ #ifndef CONFIG_USB_DEFAULT_PERSIST
+ 	/*
+ 	 * We called pm_runtime_get_noresume when the device was attached.
+@@ -3598,8 +3596,10 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 
+ 	virt_dev->udev = NULL;
+ 	ret = xhci_disable_slot(xhci, udev->slot_id);
+-	if (ret)
++	if (ret) {
++		xhci_debugfs_remove_slot(xhci, udev->slot_id);
+ 		xhci_free_virt_device(xhci, udev->slot_id);
++	}
+ }
+ 
+ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
+-- 
+2.19.0
+
diff --git a/patches/0262-media-v4l-fwnode-Support-generic-parsing-of-graph-en.patch b/patches/0262-media-v4l-fwnode-Support-generic-parsing-of-graph-en.patch
new file mode 100644
index 00000000000000..6feeb47aa55d87
--- /dev/null
+++ b/patches/0262-media-v4l-fwnode-Support-generic-parsing-of-graph-en.patch
@@ -0,0 +1,508 @@
+From 69c822e4c2c5c2a3909c2727fa20d5456533333d Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Thu, 17 Aug 2017 11:28:21 -0400
+Subject: [PATCH 0262/1795] media: v4l: fwnode: Support generic parsing of
+ graph endpoints in a device
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add two functions for parsing devices graph endpoints:
+v4l2_async_notifier_parse_fwnode_endpoints and
+v4l2_async_notifier_parse_fwnode_endpoints_by_port. The former iterates
+over all endpoints whereas the latter only iterates over the endpoints in
+a given port.
+
+The former is mostly useful for existing drivers that currently implement
+the iteration over all the endpoints themselves whereas the latter is
+especially intended for devices with both sinks and sources: async
+sub-devices for external devices connected to the device's sources will
+have already been set up, or the external sub-devices are part of the
+master device.
+
+Depends-on: ("device property: preserve usecount for node passed to of_fwnode_graph_get_port_parent()")
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 9ca4653121329595443df4e7a458154e8f745edf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c  |  31 ++++
+ drivers/media/v4l2-core/v4l2-fwnode.c | 196 ++++++++++++++++++++++++++
+ include/media/v4l2-async.h            |  24 +++-
+ include/media/v4l2-fwnode.h           | 118 ++++++++++++++++
+ 4 files changed, 367 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index d741a8e0fdac..e67aeecd674d 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -22,6 +22,7 @@
+ 
+ #include <media/v4l2-async.h>
+ #include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
+ #include <media/v4l2-subdev.h>
+ 
+ static bool match_i2c(struct v4l2_subdev *sd, struct v4l2_async_subdev *asd)
+@@ -273,6 +274,36 @@ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ }
+ EXPORT_SYMBOL(v4l2_async_notifier_unregister);
+ 
++void v4l2_async_notifier_cleanup(struct v4l2_async_notifier *notifier)
++{
++	unsigned int i;
++
++	if (!notifier->max_subdevs)
++		return;
++
++	for (i = 0; i < notifier->num_subdevs; i++) {
++		struct v4l2_async_subdev *asd = notifier->subdevs[i];
++
++		switch (asd->match_type) {
++		case V4L2_ASYNC_MATCH_FWNODE:
++			fwnode_handle_put(asd->match.fwnode.fwnode);
++			break;
++		default:
++			WARN_ON_ONCE(true);
++			break;
++		}
++
++		kfree(asd);
++	}
++
++	notifier->max_subdevs = 0;
++	notifier->num_subdevs = 0;
++
++	kvfree(notifier->subdevs);
++	notifier->subdevs = NULL;
++}
++EXPORT_SYMBOL_GPL(v4l2_async_notifier_cleanup);
++
+ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ {
+ 	struct v4l2_async_notifier *notifier;
+diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
+index 40b2fbfe8865..df0695b7bbcc 100644
+--- a/drivers/media/v4l2-core/v4l2-fwnode.c
++++ b/drivers/media/v4l2-core/v4l2-fwnode.c
+@@ -19,6 +19,7 @@
+  */
+ #include <linux/acpi.h>
+ #include <linux/kernel.h>
++#include <linux/mm.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/property.h>
+@@ -26,6 +27,7 @@
+ #include <linux/string.h>
+ #include <linux/types.h>
+ 
++#include <media/v4l2-async.h>
+ #include <media/v4l2-fwnode.h>
+ 
+ enum v4l2_fwnode_bus_type {
+@@ -388,6 +390,200 @@ void v4l2_fwnode_put_link(struct v4l2_fwnode_link *link)
+ }
+ EXPORT_SYMBOL_GPL(v4l2_fwnode_put_link);
+ 
++static int v4l2_async_notifier_realloc(struct v4l2_async_notifier *notifier,
++				       unsigned int max_subdevs)
++{
++	struct v4l2_async_subdev **subdevs;
++
++	if (max_subdevs <= notifier->max_subdevs)
++		return 0;
++
++	subdevs = kvmalloc_array(
++		max_subdevs, sizeof(*notifier->subdevs),
++		GFP_KERNEL | __GFP_ZERO);
++	if (!subdevs)
++		return -ENOMEM;
++
++	if (notifier->subdevs) {
++		memcpy(subdevs, notifier->subdevs,
++		       sizeof(*subdevs) * notifier->num_subdevs);
++
++		kvfree(notifier->subdevs);
++	}
++
++	notifier->subdevs = subdevs;
++	notifier->max_subdevs = max_subdevs;
++
++	return 0;
++}
++
++static int v4l2_async_notifier_fwnode_parse_endpoint(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	struct fwnode_handle *endpoint, unsigned int asd_struct_size,
++	int (*parse_endpoint)(struct device *dev,
++			    struct v4l2_fwnode_endpoint *vep,
++			    struct v4l2_async_subdev *asd))
++{
++	struct v4l2_async_subdev *asd;
++	struct v4l2_fwnode_endpoint *vep;
++	int ret = 0;
++
++	asd = kzalloc(asd_struct_size, GFP_KERNEL);
++	if (!asd)
++		return -ENOMEM;
++
++	asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
++	asd->match.fwnode.fwnode =
++		fwnode_graph_get_remote_port_parent(endpoint);
++	if (!asd->match.fwnode.fwnode) {
++		dev_warn(dev, "bad remote port parent\n");
++		ret = -EINVAL;
++		goto out_err;
++	}
++
++	vep = v4l2_fwnode_endpoint_alloc_parse(endpoint);
++	if (IS_ERR(vep)) {
++		ret = PTR_ERR(vep);
++		dev_warn(dev, "unable to parse V4L2 fwnode endpoint (%d)\n",
++			 ret);
++		goto out_err;
++	}
++
++	ret = parse_endpoint ? parse_endpoint(dev, vep, asd) : 0;
++	if (ret == -ENOTCONN)
++		dev_dbg(dev, "ignoring port@%u/endpoint@%u\n", vep->base.port,
++			vep->base.id);
++	else if (ret < 0)
++		dev_warn(dev,
++			 "driver could not parse port@%u/endpoint@%u (%d)\n",
++			 vep->base.port, vep->base.id, ret);
++	v4l2_fwnode_endpoint_free(vep);
++	if (ret < 0)
++		goto out_err;
++
++	notifier->subdevs[notifier->num_subdevs] = asd;
++	notifier->num_subdevs++;
++
++	return 0;
++
++out_err:
++	fwnode_handle_put(asd->match.fwnode.fwnode);
++	kfree(asd);
++
++	return ret == -ENOTCONN ? 0 : ret;
++}
++
++static int __v4l2_async_notifier_parse_fwnode_endpoints(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	size_t asd_struct_size, unsigned int port, bool has_port,
++	int (*parse_endpoint)(struct device *dev,
++			    struct v4l2_fwnode_endpoint *vep,
++			    struct v4l2_async_subdev *asd))
++{
++	struct fwnode_handle *fwnode;
++	unsigned int max_subdevs = notifier->max_subdevs;
++	int ret;
++
++	if (WARN_ON(asd_struct_size < sizeof(struct v4l2_async_subdev)))
++		return -EINVAL;
++
++	for (fwnode = NULL; (fwnode = fwnode_graph_get_next_endpoint(
++				     dev_fwnode(dev), fwnode)); ) {
++		struct fwnode_handle *dev_fwnode;
++		bool is_available;
++
++		dev_fwnode = fwnode_graph_get_port_parent(fwnode);
++		is_available = fwnode_device_is_available(dev_fwnode);
++		fwnode_handle_put(dev_fwnode);
++		if (!is_available)
++			continue;
++
++		if (has_port) {
++			struct fwnode_endpoint ep;
++
++			ret = fwnode_graph_parse_endpoint(fwnode, &ep);
++			if (ret) {
++				fwnode_handle_put(fwnode);
++				return ret;
++			}
++
++			if (ep.port != port)
++				continue;
++		}
++		max_subdevs++;
++	}
++
++	/* No subdevs to add? Return here. */
++	if (max_subdevs == notifier->max_subdevs)
++		return 0;
++
++	ret = v4l2_async_notifier_realloc(notifier, max_subdevs);
++	if (ret)
++		return ret;
++
++	for (fwnode = NULL; (fwnode = fwnode_graph_get_next_endpoint(
++				     dev_fwnode(dev), fwnode)); ) {
++		struct fwnode_handle *dev_fwnode;
++		bool is_available;
++
++		dev_fwnode = fwnode_graph_get_port_parent(fwnode);
++		is_available = fwnode_device_is_available(dev_fwnode);
++		fwnode_handle_put(dev_fwnode);
++
++		if (!fwnode_device_is_available(dev_fwnode))
++			continue;
++
++		if (WARN_ON(notifier->num_subdevs >= notifier->max_subdevs)) {
++			ret = -EINVAL;
++			break;
++		}
++
++		if (has_port) {
++			struct fwnode_endpoint ep;
++
++			ret = fwnode_graph_parse_endpoint(fwnode, &ep);
++			if (ret)
++				break;
++
++			if (ep.port != port)
++				continue;
++		}
++
++		ret = v4l2_async_notifier_fwnode_parse_endpoint(
++			dev, notifier, fwnode, asd_struct_size, parse_endpoint);
++		if (ret < 0)
++			break;
++	}
++
++	fwnode_handle_put(fwnode);
++
++	return ret;
++}
++
++int v4l2_async_notifier_parse_fwnode_endpoints(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	size_t asd_struct_size,
++	int (*parse_endpoint)(struct device *dev,
++			    struct v4l2_fwnode_endpoint *vep,
++			    struct v4l2_async_subdev *asd))
++{
++	return __v4l2_async_notifier_parse_fwnode_endpoints(
++		dev, notifier, asd_struct_size, 0, false, parse_endpoint);
++}
++EXPORT_SYMBOL_GPL(v4l2_async_notifier_parse_fwnode_endpoints);
++
++int v4l2_async_notifier_parse_fwnode_endpoints_by_port(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	size_t asd_struct_size, unsigned int port,
++	int (*parse_endpoint)(struct device *dev,
++			    struct v4l2_fwnode_endpoint *vep,
++			    struct v4l2_async_subdev *asd))
++{
++	return __v4l2_async_notifier_parse_fwnode_endpoints(
++		dev, notifier, asd_struct_size, port, true, parse_endpoint);
++}
++EXPORT_SYMBOL_GPL(v4l2_async_notifier_parse_fwnode_endpoints_by_port);
++
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
+ MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
+diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h
+index c69d8c8a66d0..329aeebd1a80 100644
+--- a/include/media/v4l2-async.h
++++ b/include/media/v4l2-async.h
+@@ -18,7 +18,6 @@ struct device;
+ struct device_node;
+ struct v4l2_device;
+ struct v4l2_subdev;
+-struct v4l2_async_notifier;
+ 
+ /* A random max subdevice number, used to allocate an array on stack */
+ #define V4L2_MAX_SUBDEVS 128U
+@@ -50,6 +49,10 @@ enum v4l2_async_match_type {
+  * @match:	union of per-bus type matching data sets
+  * @list:	used to link struct v4l2_async_subdev objects, waiting to be
+  *		probed, to a notifier->waiting list
++ *
++ * When this struct is used as a member in a driver specific struct,
++ * the driver specific struct shall contain the &struct
++ * v4l2_async_subdev as its first member.
+  */
+ struct v4l2_async_subdev {
+ 	enum v4l2_async_match_type match_type;
+@@ -78,7 +81,8 @@ struct v4l2_async_subdev {
+ /**
+  * struct v4l2_async_notifier - v4l2_device notifier data
+  *
+- * @num_subdevs: number of subdevices
++ * @num_subdevs: number of subdevices used in the subdevs array
++ * @max_subdevs: number of subdevices allocated in the subdevs array
+  * @subdevs:	array of pointers to subdevice descriptors
+  * @v4l2_dev:	pointer to struct v4l2_device
+  * @waiting:	list of struct v4l2_async_subdev, waiting for their drivers
+@@ -90,6 +94,7 @@ struct v4l2_async_subdev {
+  */
+ struct v4l2_async_notifier {
+ 	unsigned int num_subdevs;
++	unsigned int max_subdevs;
+ 	struct v4l2_async_subdev **subdevs;
+ 	struct v4l2_device *v4l2_dev;
+ 	struct list_head waiting;
+@@ -120,6 +125,21 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+  */
+ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier);
+ 
++/**
++ * v4l2_async_notifier_cleanup - clean up notifier resources
++ * @notifier: the notifier the resources of which are to be cleaned up
++ *
++ * Release memory resources related to a notifier, including the async
++ * sub-devices allocated for the purposes of the notifier but not the notifier
++ * itself. The user is responsible for calling this function to clean up the
++ * notifier after calling @v4l2_async_notifier_parse_fwnode_endpoints.
++ *
++ * There is no harm from calling v4l2_async_notifier_cleanup in other
++ * cases as long as its memory has been zeroed after it has been
++ * allocated.
++ */
++void v4l2_async_notifier_cleanup(struct v4l2_async_notifier *notifier);
++
+ /**
+  * v4l2_async_register_subdev - registers a sub-device to the asynchronous
+  * 	subdevice framework
+diff --git a/include/media/v4l2-fwnode.h b/include/media/v4l2-fwnode.h
+index 7adec9851d9e..ac605af9b877 100644
+--- a/include/media/v4l2-fwnode.h
++++ b/include/media/v4l2-fwnode.h
+@@ -25,6 +25,8 @@
+ #include <media/v4l2-mediabus.h>
+ 
+ struct fwnode_handle;
++struct v4l2_async_notifier;
++struct v4l2_async_subdev;
+ 
+ #define V4L2_FWNODE_CSI2_MAX_DATA_LANES	4
+ 
+@@ -122,4 +124,120 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *fwnode,
+ 			   struct v4l2_fwnode_link *link);
+ void v4l2_fwnode_put_link(struct v4l2_fwnode_link *link);
+ 
++/**
++ * v4l2_async_notifier_parse_fwnode_endpoints - Parse V4L2 fwnode endpoints in a
++ *						device node
++ * @dev: the device the endpoints of which are to be parsed
++ * @notifier: notifier for @dev
++ * @asd_struct_size: size of the driver's async sub-device struct, including
++ *		     sizeof(struct v4l2_async_subdev). The &struct
++ *		     v4l2_async_subdev shall be the first member of
++ *		     the driver's async sub-device struct, i.e. both
++ *		     begin at the same memory address.
++ * @parse_endpoint: Driver's callback function called on each V4L2 fwnode
++ *		    endpoint. Optional.
++ *		    Return: %0 on success
++ *			    %-ENOTCONN if the endpoint is to be skipped but this
++ *				       should not be considered as an error
++ *			    %-EINVAL if the endpoint configuration is invalid
++ *
++ * Parse the fwnode endpoints of the @dev device and populate the async sub-
++ * devices array of the notifier. The @parse_endpoint callback function is
++ * called for each endpoint with the corresponding async sub-device pointer to
++ * let the caller initialize the driver-specific part of the async sub-device
++ * structure.
++ *
++ * The notifier memory shall be zeroed before this function is called on the
++ * notifier.
++ *
++ * This function may not be called on a registered notifier and may be called on
++ * a notifier only once.
++ *
++ * Do not change the notifier's subdevs array, take references to the subdevs
++ * array itself or change the notifier's num_subdevs field. This is because this
++ * function allocates and reallocates the subdevs array based on parsing
++ * endpoints.
++ *
++ * The &struct v4l2_fwnode_endpoint passed to the callback function
++ * @parse_endpoint is released once the function is finished. If there is a need
++ * to retain that configuration, the user needs to allocate memory for it.
++ *
++ * Any notifier populated using this function must be released with a call to
++ * v4l2_async_notifier_cleanup() after it has been unregistered and the async
++ * sub-devices are no longer in use, even if the function returned an error.
++ *
++ * Return: %0 on success, including when no async sub-devices are found
++ *	   %-ENOMEM if memory allocation failed
++ *	   %-EINVAL if graph or endpoint parsing failed
++ *	   Other error codes as returned by @parse_endpoint
++ */
++int v4l2_async_notifier_parse_fwnode_endpoints(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	size_t asd_struct_size,
++	int (*parse_endpoint)(struct device *dev,
++			      struct v4l2_fwnode_endpoint *vep,
++			      struct v4l2_async_subdev *asd));
++
++/**
++ * v4l2_async_notifier_parse_fwnode_endpoints_by_port - Parse V4L2 fwnode
++ *							endpoints of a port in a
++ *							device node
++ * @dev: the device the endpoints of which are to be parsed
++ * @notifier: notifier for @dev
++ * @asd_struct_size: size of the driver's async sub-device struct, including
++ *		     sizeof(struct v4l2_async_subdev). The &struct
++ *		     v4l2_async_subdev shall be the first member of
++ *		     the driver's async sub-device struct, i.e. both
++ *		     begin at the same memory address.
++ * @port: port number where endpoints are to be parsed
++ * @parse_endpoint: Driver's callback function called on each V4L2 fwnode
++ *		    endpoint. Optional.
++ *		    Return: %0 on success
++ *			    %-ENOTCONN if the endpoint is to be skipped but this
++ *				       should not be considered as an error
++ *			    %-EINVAL if the endpoint configuration is invalid
++ *
++ * This function is just like v4l2_async_notifier_parse_fwnode_endpoints() with
++ * the exception that it only parses endpoints in a given port. This is useful
++ * on devices that have both sinks and sources: the async sub-devices connected
++ * to sources have already been configured by another driver (on capture
++ * devices). In this case the driver must know which ports to parse.
++ *
++ * Parse the fwnode endpoints of the @dev device on a given @port and populate
++ * the async sub-devices array of the notifier. The @parse_endpoint callback
++ * function is called for each endpoint with the corresponding async sub-device
++ * pointer to let the caller initialize the driver-specific part of the async
++ * sub-device structure.
++ *
++ * The notifier memory shall be zeroed before this function is called on the
++ * notifier the first time.
++ *
++ * This function may not be called on a registered notifier and may be called on
++ * a notifier only once per port.
++ *
++ * Do not change the notifier's subdevs array, take references to the subdevs
++ * array itself or change the notifier's num_subdevs field. This is because this
++ * function allocates and reallocates the subdevs array based on parsing
++ * endpoints.
++ *
++ * The &struct v4l2_fwnode_endpoint passed to the callback function
++ * @parse_endpoint is released once the function is finished. If there is a need
++ * to retain that configuration, the user needs to allocate memory for it.
++ *
++ * Any notifier populated using this function must be released with a call to
++ * v4l2_async_notifier_cleanup() after it has been unregistered and the async
++ * sub-devices are no longer in use, even if the function returned an error.
++ *
++ * Return: %0 on success, including when no async sub-devices are found
++ *	   %-ENOMEM if memory allocation failed
++ *	   %-EINVAL if graph or endpoint parsing failed
++ *	   Other error codes as returned by @parse_endpoint
++ */
++int v4l2_async_notifier_parse_fwnode_endpoints_by_port(
++	struct device *dev, struct v4l2_async_notifier *notifier,
++	size_t asd_struct_size, unsigned int port,
++	int (*parse_endpoint)(struct device *dev,
++			      struct v4l2_fwnode_endpoint *vep,
++			      struct v4l2_async_subdev *asd));
++
+ #endif /* _V4L2_FWNODE_H */
+-- 
+2.19.0
+
diff --git a/patches/0263-media-rcar-vin-Use-generic-parser-for-parsing-fwnode.patch b/patches/0263-media-rcar-vin-Use-generic-parser-for-parsing-fwnode.patch
new file mode 100644
index 00000000000000..3560efa6ec1be3
--- /dev/null
+++ b/patches/0263-media-rcar-vin-Use-generic-parser-for-parsing-fwnode.patch
@@ -0,0 +1,372 @@
+From 3122a6041558b46d6fe73d1a71372ea01c03cc92 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Fri, 1 Sep 2017 18:41:19 -0400
+Subject: [PATCH 0263/1795] media: rcar-vin: Use generic parser for parsing
+ fwnode endpoints
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Instead of using a custom driver implementation, use
+v4l2_async_notifier_parse_fwnode_endpoints() to parse the fwnode endpoints
+of the device.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 85999e8ec0ee7cf1039152b34a3fc3d91e7e27c3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 107 ++++++--------------
+ drivers/media/platform/rcar-vin/rcar-dma.c  |  10 +-
+ drivers/media/platform/rcar-vin/rcar-v4l2.c |  14 +--
+ drivers/media/platform/rcar-vin/rcar-vin.h  |   4 +-
+ 4 files changed, 46 insertions(+), 89 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 142de447aaaa..380288658601 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -21,6 +21,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ 
++#include <media/v4l2-async.h>
+ #include <media/v4l2-fwnode.h>
+ 
+ #include "rcar-vin.h"
+@@ -77,14 +78,14 @@ static int rvin_digital_notify_complete(struct v4l2_async_notifier *notifier)
+ 	int ret;
+ 
+ 	/* Verify subdevices mbus format */
+-	if (!rvin_mbus_supported(&vin->digital)) {
++	if (!rvin_mbus_supported(vin->digital)) {
+ 		vin_err(vin, "Unsupported media bus format for %s\n",
+-			vin->digital.subdev->name);
++			vin->digital->subdev->name);
+ 		return -EINVAL;
+ 	}
+ 
+ 	vin_dbg(vin, "Found media bus format for %s: %d\n",
+-		vin->digital.subdev->name, vin->digital.code);
++		vin->digital->subdev->name, vin->digital->code);
+ 
+ 	ret = v4l2_device_register_subdev_nodes(&vin->v4l2_dev);
+ 	if (ret < 0) {
+@@ -103,7 +104,7 @@ static void rvin_digital_notify_unbind(struct v4l2_async_notifier *notifier,
+ 
+ 	vin_dbg(vin, "unbind digital subdev %s\n", subdev->name);
+ 	rvin_v4l2_remove(vin);
+-	vin->digital.subdev = NULL;
++	vin->digital->subdev = NULL;
+ }
+ 
+ static int rvin_digital_notify_bound(struct v4l2_async_notifier *notifier,
+@@ -120,117 +121,71 @@ static int rvin_digital_notify_bound(struct v4l2_async_notifier *notifier,
+ 	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
+ 	if (ret < 0)
+ 		return ret;
+-	vin->digital.source_pad = ret;
++	vin->digital->source_pad = ret;
+ 
+ 	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SINK);
+-	vin->digital.sink_pad = ret < 0 ? 0 : ret;
++	vin->digital->sink_pad = ret < 0 ? 0 : ret;
+ 
+-	vin->digital.subdev = subdev;
++	vin->digital->subdev = subdev;
+ 
+ 	vin_dbg(vin, "bound subdev %s source pad: %u sink pad: %u\n",
+-		subdev->name, vin->digital.source_pad,
+-		vin->digital.sink_pad);
++		subdev->name, vin->digital->source_pad,
++		vin->digital->sink_pad);
+ 
+ 	return 0;
+ }
+ 
+-static int rvin_digitial_parse_v4l2(struct rvin_dev *vin,
+-				    struct device_node *ep,
+-				    struct v4l2_mbus_config *mbus_cfg)
++static int rvin_digital_parse_v4l2(struct device *dev,
++				   struct v4l2_fwnode_endpoint *vep,
++				   struct v4l2_async_subdev *asd)
+ {
+-	struct v4l2_fwnode_endpoint v4l2_ep;
+-	int ret;
++	struct rvin_dev *vin = dev_get_drvdata(dev);
++	struct rvin_graph_entity *rvge =
++		container_of(asd, struct rvin_graph_entity, asd);
+ 
+-	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
+-	if (ret) {
+-		vin_err(vin, "Could not parse v4l2 endpoint\n");
+-		return -EINVAL;
+-	}
++	if (vep->base.port || vep->base.id)
++		return -ENOTCONN;
+ 
+-	mbus_cfg->type = v4l2_ep.bus_type;
++	rvge->mbus_cfg.type = vep->bus_type;
+ 
+-	switch (mbus_cfg->type) {
++	switch (rvge->mbus_cfg.type) {
+ 	case V4L2_MBUS_PARALLEL:
+ 		vin_dbg(vin, "Found PARALLEL media bus\n");
+-		mbus_cfg->flags = v4l2_ep.bus.parallel.flags;
++		rvge->mbus_cfg.flags = vep->bus.parallel.flags;
+ 		break;
+ 	case V4L2_MBUS_BT656:
+ 		vin_dbg(vin, "Found BT656 media bus\n");
+-		mbus_cfg->flags = 0;
++		rvge->mbus_cfg.flags = 0;
+ 		break;
+ 	default:
+ 		vin_err(vin, "Unknown media bus type\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	return 0;
+-}
+-
+-static int rvin_digital_graph_parse(struct rvin_dev *vin)
+-{
+-	struct device_node *ep, *np;
+-	int ret;
+-
+-	vin->digital.asd.match.fwnode.fwnode = NULL;
+-	vin->digital.subdev = NULL;
+-
+-	/*
+-	 * Port 0 id 0 is local digital input, try to get it.
+-	 * Not all instances can or will have this, that is OK
+-	 */
+-	ep = of_graph_get_endpoint_by_regs(vin->dev->of_node, 0, 0);
+-	if (!ep)
+-		return 0;
+-
+-	np = of_graph_get_remote_port_parent(ep);
+-	if (!np) {
+-		vin_err(vin, "No remote parent for digital input\n");
+-		of_node_put(ep);
+-		return -EINVAL;
+-	}
+-	of_node_put(np);
+-
+-	ret = rvin_digitial_parse_v4l2(vin, ep, &vin->digital.mbus_cfg);
+-	of_node_put(ep);
+-	if (ret)
+-		return ret;
+-
+-	vin->digital.asd.match.fwnode.fwnode = of_fwnode_handle(np);
+-	vin->digital.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
++	vin->digital = rvge;
+ 
+ 	return 0;
+ }
+ 
+ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ {
+-	struct v4l2_async_subdev **subdevs = NULL;
+ 	int ret;
+ 
+-	ret = rvin_digital_graph_parse(vin);
++	ret = v4l2_async_notifier_parse_fwnode_endpoints(
++		vin->dev, &vin->notifier,
++		sizeof(struct rvin_graph_entity), rvin_digital_parse_v4l2);
+ 	if (ret)
+ 		return ret;
+ 
+-	if (!vin->digital.asd.match.fwnode.fwnode) {
+-		vin_dbg(vin, "No digital subdevice found\n");
++	if (!vin->digital)
+ 		return -ENODEV;
+-	}
+-
+-	/* Register the subdevices notifier. */
+-	subdevs = devm_kzalloc(vin->dev, sizeof(*subdevs), GFP_KERNEL);
+-	if (subdevs == NULL)
+-		return -ENOMEM;
+-
+-	subdevs[0] = &vin->digital.asd;
+ 
+ 	vin_dbg(vin, "Found digital subdevice %pOF\n",
+-		to_of_node(subdevs[0]->match.fwnode.fwnode));
++		to_of_node(vin->digital->asd.match.fwnode.fwnode));
+ 
+-	vin->notifier.num_subdevs = 1;
+-	vin->notifier.subdevs = subdevs;
+ 	vin->notifier.bound = rvin_digital_notify_bound;
+ 	vin->notifier.unbind = rvin_digital_notify_unbind;
+ 	vin->notifier.complete = rvin_digital_notify_complete;
+-
+ 	ret = v4l2_async_notifier_register(&vin->v4l2_dev, &vin->notifier);
+ 	if (ret < 0) {
+ 		vin_err(vin, "Notifier registration failed\n");
+@@ -290,6 +245,8 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
++	platform_set_drvdata(pdev, vin);
++
+ 	ret = rvin_digital_graph_init(vin);
+ 	if (ret < 0)
+ 		goto error;
+@@ -297,11 +254,10 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	pm_suspend_ignore_children(&pdev->dev, true);
+ 	pm_runtime_enable(&pdev->dev);
+ 
+-	platform_set_drvdata(pdev, vin);
+-
+ 	return 0;
+ error:
+ 	rvin_dma_remove(vin);
++	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+ 	return ret;
+ }
+@@ -313,6 +269,7 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	pm_runtime_disable(&pdev->dev);
+ 
+ 	v4l2_async_notifier_unregister(&vin->notifier);
++	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+ 	rvin_dma_remove(vin);
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index b136844499f6..23fdff7a7370 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -183,7 +183,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	/*
+ 	 * Input interface
+ 	 */
+-	switch (vin->digital.code) {
++	switch (vin->digital->code) {
+ 	case MEDIA_BUS_FMT_YUYV8_1X16:
+ 		/* BT.601/BT.1358 16bit YCbCr422 */
+ 		vnmc |= VNMC_INF_YUV16;
+@@ -191,7 +191,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
+-		vnmc |= vin->digital.mbus_cfg.type == V4L2_MBUS_BT656 ?
++		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
+ 			VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601;
+ 		input_is_yuv = true;
+ 		break;
+@@ -200,7 +200,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	case MEDIA_BUS_FMT_UYVY10_2X10:
+ 		/* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
+-		vnmc |= vin->digital.mbus_cfg.type == V4L2_MBUS_BT656 ?
++		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
+ 			VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601;
+ 		input_is_yuv = true;
+ 		break;
+@@ -212,11 +212,11 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
+ 
+ 	/* Hsync Signal Polarity Select */
+-	if (!(vin->digital.mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
++	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+ 		dmr2 |= VNDMR2_HPS;
+ 
+ 	/* Vsync Signal Polarity Select */
+-	if (!(vin->digital.mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
++	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
+ 		dmr2 |= VNDMR2_VPS;
+ 
+ 	/*
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index dd37ea811680..b479b882da12 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -111,7 +111,7 @@ static int rvin_reset_format(struct rvin_dev *vin)
+ 	struct v4l2_mbus_framefmt *mf = &fmt.format;
+ 	int ret;
+ 
+-	fmt.pad = vin->digital.source_pad;
++	fmt.pad = vin->digital->source_pad;
+ 
+ 	ret = v4l2_subdev_call(vin_to_source(vin), pad, get_fmt, NULL, &fmt);
+ 	if (ret)
+@@ -172,13 +172,13 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 
+ 	sd = vin_to_source(vin);
+ 
+-	v4l2_fill_mbus_format(&format.format, pix, vin->digital.code);
++	v4l2_fill_mbus_format(&format.format, pix, vin->digital->code);
+ 
+ 	pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ 	if (pad_cfg == NULL)
+ 		return -ENOMEM;
+ 
+-	format.pad = vin->digital.source_pad;
++	format.pad = vin->digital->source_pad;
+ 
+ 	field = pix->field;
+ 
+@@ -555,7 +555,7 @@ static int rvin_enum_dv_timings(struct file *file, void *priv_fh,
+ 	if (timings->pad)
+ 		return -EINVAL;
+ 
+-	timings->pad = vin->digital.sink_pad;
++	timings->pad = vin->digital->sink_pad;
+ 
+ 	ret = v4l2_subdev_call(sd, pad, enum_dv_timings, timings);
+ 
+@@ -607,7 +607,7 @@ static int rvin_dv_timings_cap(struct file *file, void *priv_fh,
+ 	if (cap->pad)
+ 		return -EINVAL;
+ 
+-	cap->pad = vin->digital.sink_pad;
++	cap->pad = vin->digital->sink_pad;
+ 
+ 	ret = v4l2_subdev_call(sd, pad, dv_timings_cap, cap);
+ 
+@@ -625,7 +625,7 @@ static int rvin_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
+ 	if (edid->pad)
+ 		return -EINVAL;
+ 
+-	edid->pad = vin->digital.sink_pad;
++	edid->pad = vin->digital->sink_pad;
+ 
+ 	ret = v4l2_subdev_call(sd, pad, get_edid, edid);
+ 
+@@ -643,7 +643,7 @@ static int rvin_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
+ 	if (edid->pad)
+ 		return -EINVAL;
+ 
+-	edid->pad = vin->digital.sink_pad;
++	edid->pad = vin->digital->sink_pad;
+ 
+ 	ret = v4l2_subdev_call(sd, pad, set_edid, edid);
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 9bfb5a7c4dc4..5382078143fb 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -126,7 +126,7 @@ struct rvin_dev {
+ 	struct v4l2_device v4l2_dev;
+ 	struct v4l2_ctrl_handler ctrl_handler;
+ 	struct v4l2_async_notifier notifier;
+-	struct rvin_graph_entity digital;
++	struct rvin_graph_entity *digital;
+ 
+ 	struct mutex lock;
+ 	struct vb2_queue queue;
+@@ -145,7 +145,7 @@ struct rvin_dev {
+ 	struct v4l2_rect compose;
+ };
+ 
+-#define vin_to_source(vin)		vin->digital.subdev
++#define vin_to_source(vin)		((vin)->digital->subdev)
+ 
+ /* Debug */
+ #define vin_dbg(d, fmt, arg...)		dev_dbg(d->dev, fmt, ##arg)
+-- 
+2.19.0
+
diff --git a/patches/0264-of-pci-Add-of_pci_dma_range_parser_init-for-dma-rang.patch b/patches/0264-of-pci-Add-of_pci_dma_range_parser_init-for-dma-rang.patch
new file mode 100644
index 00000000000000..b8561990ed6e75
--- /dev/null
+++ b/patches/0264-of-pci-Add-of_pci_dma_range_parser_init-for-dma-rang.patch
@@ -0,0 +1,100 @@
+From d55ac622b9edc3f20ab6addaaafc8b86a6cd73b3 Mon Sep 17 00:00:00 2001
+From: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
+Date: Tue, 26 Sep 2017 12:22:54 +0200
+Subject: [PATCH 0264/1795] of/pci: Add of_pci_dma_range_parser_init() for
+ dma-ranges parsing support
+
+Several host bridge drivers duplicate of_pci_range_parser_init() in order
+to parse their dma-ranges property.
+
+Provide of_pci_dma_range_parser_init() for that use case.
+
+Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit a060c2104ef83e62346b7e893947a940471c0d7c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/address.c       | 19 ++++++++++++++++---
+ include/linux/of_address.h | 10 +++++++++-
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/of/address.c b/drivers/of/address.c
+index 792722e7d458..fa6cabfc3cb9 100644
+--- a/drivers/of/address.c
++++ b/drivers/of/address.c
+@@ -232,8 +232,8 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
+ }
+ EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+ 
+-int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+-				struct device_node *node)
++static int parser_init(struct of_pci_range_parser *parser,
++			struct device_node *node, const char *name)
+ {
+ 	const int na = 3, ns = 2;
+ 	int rlen;
+@@ -242,7 +242,7 @@ int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+ 	parser->pna = of_n_addr_cells(node);
+ 	parser->np = parser->pna + na + ns;
+ 
+-	parser->range = of_get_property(node, "ranges", &rlen);
++	parser->range = of_get_property(node, name, &rlen);
+ 	if (parser->range == NULL)
+ 		return -ENOENT;
+ 
+@@ -250,8 +250,21 @@ int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+ 
+ 	return 0;
+ }
++
++int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++				struct device_node *node)
++{
++	return parser_init(parser, node, "ranges");
++}
+ EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+ 
++int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser,
++				struct device_node *node)
++{
++	return parser_init(parser, node, "dma-ranges");
++}
++EXPORT_SYMBOL_GPL(of_pci_dma_range_parser_init);
++
+ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+ 						struct of_pci_range *range)
+ {
+diff --git a/include/linux/of_address.h b/include/linux/of_address.h
+index b8ac44c9748e..30e40fb6936b 100644
+--- a/include/linux/of_address.h
++++ b/include/linux/of_address.h
+@@ -50,6 +50,8 @@ extern const __be32 *of_get_address(struct device_node *dev, int index,
+ 
+ extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+ 			struct device_node *node);
++extern int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser,
++			struct device_node *node);
+ extern struct of_pci_range *of_pci_range_parser_one(
+ 					struct of_pci_range_parser *parser,
+ 					struct of_pci_range *range);
+@@ -86,7 +88,13 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
+ static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+ 			struct device_node *node)
+ {
+-	return -1;
++	return -ENOSYS;
++}
++
++static inline int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser,
++			struct device_node *node)
++{
++	return -ENOSYS;
+ }
+ 
+ static inline struct of_pci_range *of_pci_range_parser_one(
+-- 
+2.19.0
+
diff --git a/patches/0265-PCI-Use-of_pci_dma_range_parser_init-to-reduce-dupli.patch b/patches/0265-PCI-Use-of_pci_dma_range_parser_init-to-reduce-dupli.patch
new file mode 100644
index 00000000000000..d726f5a1a40f60
--- /dev/null
+++ b/patches/0265-PCI-Use-of_pci_dma_range_parser_init-to-reduce-dupli.patch
@@ -0,0 +1,215 @@
+From 6b78052b0e747d5eb1d769f5e8d91bb32a9a9477 Mon Sep 17 00:00:00 2001
+From: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
+Date: Tue, 26 Sep 2017 12:26:55 +0200
+Subject: [PATCH 0265/1795] PCI: Use of_pci_dma_range_parser_init() to reduce
+ duplication
+
+Use the new of_pci_dma_range_parser_init() to reduce code duplication.
+
+Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 1e61a57cac560844580ab532a4e2f5061ef77039)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pci-ftpci100.c  | 20 +-------------------
+ drivers/pci/host/pci-rcar-gen2.c | 20 +-------------------
+ drivers/pci/host/pci-xgene.c     | 20 +-------------------
+ drivers/pci/host/pcie-iproc.c    | 20 +-------------------
+ drivers/pci/host/pcie-rcar.c     | 20 +-------------------
+ 5 files changed, 5 insertions(+), 95 deletions(-)
+
+diff --git a/drivers/pci/host/pci-ftpci100.c b/drivers/pci/host/pci-ftpci100.c
+index 4e6b21931514..a3d60860c088 100644
+--- a/drivers/pci/host/pci-ftpci100.c
++++ b/drivers/pci/host/pci-ftpci100.c
+@@ -373,24 +373,6 @@ static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
+ 	return 0;
+ }
+ 
+-static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+-				     struct device_node *node)
+-{
+-	const int na = 3, ns = 2;
+-	int rlen;
+-
+-	parser->node = node;
+-	parser->pna = of_n_addr_cells(node);
+-	parser->np = parser->pna + na + ns;
+-
+-	parser->range = of_get_property(node, "dma-ranges", &rlen);
+-	if (!parser->range)
+-		return -ENOENT;
+-	parser->end = parser->range + rlen / sizeof(__be32);
+-
+-	return 0;
+-}
+-
+ static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
+ 					    struct device_node *np)
+ {
+@@ -405,7 +387,7 @@ static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
+ 	int i = 0;
+ 	u32 val;
+ 
+-	if (pci_dma_range_parser_init(&parser, np)) {
++	if (of_pci_dma_range_parser_init(&parser, np)) {
+ 		dev_err(dev, "missing dma-ranges property\n");
+ 		return -EINVAL;
+ 	}
+diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
+index 6f879685fedd..e46de69f0380 100644
+--- a/drivers/pci/host/pci-rcar-gen2.c
++++ b/drivers/pci/host/pci-rcar-gen2.c
+@@ -293,24 +293,6 @@ static struct pci_ops rcar_pci_ops = {
+ 	.write	= pci_generic_config_write,
+ };
+ 
+-static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+-				     struct device_node *node)
+-{
+-	const int na = 3, ns = 2;
+-	int rlen;
+-
+-	parser->node = node;
+-	parser->pna = of_n_addr_cells(node);
+-	parser->np = parser->pna + na + ns;
+-
+-	parser->range = of_get_property(node, "dma-ranges", &rlen);
+-	if (!parser->range)
+-		return -ENOENT;
+-
+-	parser->end = parser->range + rlen / sizeof(__be32);
+-	return 0;
+-}
+-
+ static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
+ 					 struct device_node *np)
+ {
+@@ -320,7 +302,7 @@ static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
+ 	int index = 0;
+ 
+ 	/* Failure to parse is ok as we fall back to defaults */
+-	if (pci_dma_range_parser_init(&parser, np))
++	if (of_pci_dma_range_parser_init(&parser, np))
+ 		return 0;
+ 
+ 	/* Get the dma-ranges from DT */
+diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
+index c78fd9c2cf8c..0860f30674a8 100644
+--- a/drivers/pci/host/pci-xgene.c
++++ b/drivers/pci/host/pci-xgene.c
+@@ -542,24 +542,6 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
+ 	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
+ }
+ 
+-static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+-				     struct device_node *node)
+-{
+-	const int na = 3, ns = 2;
+-	int rlen;
+-
+-	parser->node = node;
+-	parser->pna = of_n_addr_cells(node);
+-	parser->np = parser->pna + na + ns;
+-
+-	parser->range = of_get_property(node, "dma-ranges", &rlen);
+-	if (!parser->range)
+-		return -ENOENT;
+-	parser->end = parser->range + rlen / sizeof(__be32);
+-
+-	return 0;
+-}
+-
+ static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
+ {
+ 	struct device_node *np = port->node;
+@@ -568,7 +550,7 @@ static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
+ 	struct device *dev = port->dev;
+ 	u8 ib_reg_mask = 0;
+ 
+-	if (pci_dma_range_parser_init(&parser, np)) {
++	if (of_pci_dma_range_parser_init(&parser, np)) {
+ 		dev_err(dev, "missing dma-ranges property\n");
+ 		return -EINVAL;
+ 	}
+diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
+index c0ecc9f35667..75836067f538 100644
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -1097,24 +1097,6 @@ static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
+ 	return ret;
+ }
+ 
+-static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+-				     struct device_node *node)
+-{
+-	const int na = 3, ns = 2;
+-	int rlen;
+-
+-	parser->node = node;
+-	parser->pna = of_n_addr_cells(node);
+-	parser->np = parser->pna + na + ns;
+-
+-	parser->range = of_get_property(node, "dma-ranges", &rlen);
+-	if (!parser->range)
+-		return -ENOENT;
+-
+-	parser->end = parser->range + rlen / sizeof(__be32);
+-	return 0;
+-}
+-
+ static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
+ {
+ 	struct of_pci_range range;
+@@ -1122,7 +1104,7 @@ static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
+ 	int ret;
+ 
+ 	/* Get the dma-ranges from DT */
+-	ret = pci_dma_range_parser_init(&parser, pcie->dev->of_node);
++	ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 41edce16a07c..bab9f24ae70b 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -1027,24 +1027,6 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
+ 	return 0;
+ }
+ 
+-static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+-				     struct device_node *node)
+-{
+-	const int na = 3, ns = 2;
+-	int rlen;
+-
+-	parser->node = node;
+-	parser->pna = of_n_addr_cells(node);
+-	parser->np = parser->pna + na + ns;
+-
+-	parser->range = of_get_property(node, "dma-ranges", &rlen);
+-	if (!parser->range)
+-		return -ENOENT;
+-
+-	parser->end = parser->range + rlen / sizeof(__be32);
+-	return 0;
+-}
+-
+ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
+ 					  struct device_node *np)
+ {
+@@ -1053,7 +1035,7 @@ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
+ 	int index = 0;
+ 	int err;
+ 
+-	if (pci_dma_range_parser_init(&parser, np))
++	if (of_pci_dma_range_parser_init(&parser, np))
+ 		return -EINVAL;
+ 
+ 	/* Get the dma-ranges from DT */
+-- 
+2.19.0
+
diff --git a/patches/0266-dt-bindings-PCI-rcar-Correct-example-to-match-realit.patch b/patches/0266-dt-bindings-PCI-rcar-Correct-example-to-match-realit.patch
new file mode 100644
index 00000000000000..e7dff3c8f91d05
--- /dev/null
+++ b/patches/0266-dt-bindings-PCI-rcar-Correct-example-to-match-realit.patch
@@ -0,0 +1,55 @@
+From 5a05f3348a284fa95ac9c2dc1e4d423ebd9297d8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 11 Oct 2017 15:50:13 +0200
+Subject: [PATCH 0266/1795] dt-bindings: PCI: rcar: Correct example to match
+ reality
+
+Correct the USB subnodes in the example, as in f7d569c1e6a6 ("ARM: dts:
+r8a779x: Fix PCI bus dtc warnings").
+  1. Drop the bogus 'device_type = "pci"' properties,
+  2. Correct the unit addresses.
+
+Update other bits in the example to match real use:
+  1. Rename the USB subnodes from "pci" to "usb",
+  2. Update the "phys" property.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit f6755643d62e14c55c2f864a7995fd8001ae3f51)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pci/pci-rcar-gen2.txt          | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+index 3d038638612b..9fe7e12a7bf3 100644
+--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
++++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+@@ -60,17 +60,15 @@ Example SoC configuration:
+ 				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+ 				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+ 
+-		pci@0,1 {
++		usb@1,0 {
+ 			reg = <0x800 0 0 0 0>;
+-			device_type = "pci";
+-			phys = <&usbphy 0 0>;
++			phys = <&usb0 0>;
+ 			phy-names = "usb";
+ 		};
+ 
+-		pci@0,2 {
++		usb@2,0 {
+ 			reg = <0x1000 0 0 0 0>;
+-			device_type = "pci";
+-			phys = <&usbphy 0 0>;
++			phys = <&usb0 0>;
+ 			phy-names = "usb";
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0267-dt-bindings-clock-Add-R8A77970-CPG-core-clock-defini.patch b/patches/0267-dt-bindings-clock-Add-R8A77970-CPG-core-clock-defini.patch
new file mode 100644
index 00000000000000..09d3ca92a3369b
--- /dev/null
+++ b/patches/0267-dt-bindings-clock-Add-R8A77970-CPG-core-clock-defini.patch
@@ -0,0 +1,81 @@
+From fae1c8b8d88c761f2a7111b6f68a721d3414e4ee Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 9 Sep 2017 00:34:19 +0300
+Subject: [PATCH 0267/1795] dt-bindings: clock: Add R8A77970 CPG core clock
+ definitions
+
+Add macros usable by the device tree sources to reference the R8A77970
+CPG core clocks by index. The data come from the table 8.2c of R-Car
+Series, 3rd Generation User's Manual: Hardware (Rev. 0.55, Jun. 30, 2017).
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ecadea00f588d7047572a878072c766c75725d1f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/clock/r8a77970-cpg-mssr.h | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+ create mode 100644 include/dt-bindings/clock/r8a77970-cpg-mssr.h
+
+diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+new file mode 100644
+index 000000000000..4146395595b1
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (C) 2016 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a77970 CPG Core Clocks */
++#define R8A77970_CLK_Z2			0
++#define R8A77970_CLK_ZR			1
++#define R8A77970_CLK_ZTR		2
++#define R8A77970_CLK_ZTRD2		3
++#define R8A77970_CLK_ZT			4
++#define R8A77970_CLK_ZX			5
++#define R8A77970_CLK_S1D1		6
++#define R8A77970_CLK_S1D2		7
++#define R8A77970_CLK_S1D4		8
++#define R8A77970_CLK_S2D1		9
++#define R8A77970_CLK_S2D2		10
++#define R8A77970_CLK_S2D4		11
++#define R8A77970_CLK_LB			12
++#define R8A77970_CLK_CL			13
++#define R8A77970_CLK_ZB3		14
++#define R8A77970_CLK_ZB3D2		15
++#define R8A77970_CLK_DDR		16
++#define R8A77970_CLK_CR			17
++#define R8A77970_CLK_CRD2		18
++#define R8A77970_CLK_SD0H		19
++#define R8A77970_CLK_SD0		20
++#define R8A77970_CLK_RPC		21
++#define R8A77970_CLK_RPCD2		22
++#define R8A77970_CLK_MSO		23
++#define R8A77970_CLK_CANFD		24
++#define R8A77970_CLK_CSI0		25
++#define R8A77970_CLK_FRAY		26
++#define R8A77970_CLK_CP			27
++#define R8A77970_CLK_CPEX		28
++#define R8A77970_CLK_R			29
++#define R8A77970_CLK_OSC		30
++
++#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0268-clk-renesas-cpg-mssr-Add-R8A77970-support.patch b/patches/0268-clk-renesas-cpg-mssr-Add-R8A77970-support.patch
new file mode 100644
index 00000000000000..b69f68251d4bfb
--- /dev/null
+++ b/patches/0268-clk-renesas-cpg-mssr-Add-R8A77970-support.patch
@@ -0,0 +1,323 @@
+From b0872681f0f04ffc998ca964bcf93123fbd8c866 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 9 Sep 2017 00:34:20 +0300
+Subject: [PATCH 0268/1795] clk: renesas: cpg-mssr: Add R8A77970 support
+
+Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and
+Software Reset support, using the CPG/MSSR driver core and the common
+R-Car Gen3 code.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8d46e28fb5081b49c5b24c814ad464fb99359d58)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/renesas,cpg-mssr.txt       |   5 +-
+ drivers/clk/renesas/Kconfig                   |   5 +
+ drivers/clk/renesas/Makefile                  |   1 +
+ drivers/clk/renesas/r8a77970-cpg-mssr.c       | 199 ++++++++++++++++++
+ drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
+ 6 files changed, 215 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/renesas/r8a77970-cpg-mssr.c
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+index 316e13686568..f1890d0777a6 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+@@ -22,6 +22,7 @@ Required Properties:
+       - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
+       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
+       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
++      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+       - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
+ 
+   - reg: Base address and length of the memory resource used by the CPG/MSSR
+@@ -31,8 +32,8 @@ Required Properties:
+     clock-names
+   - clock-names: List of external parent clock names. Valid names are:
+       - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+-		 r8a7795, r8a7796, r8a77995)
+-      - "extalr" (r8a7795, r8a7796)
++		 r8a7795, r8a7796, r8a77970, r8a77995)
++      - "extalr" (r8a7795, r8a7796, r8a77970)
+       - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+ 
+   - #clock-cells: Must be 2
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index acbb38151ba1..43b5a89c4b28 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -15,6 +15,7 @@ config CLK_RENESAS
+ 	select CLK_R8A7794 if ARCH_R8A7794
+ 	select CLK_R8A7795 if ARCH_R8A7795
+ 	select CLK_R8A7796 if ARCH_R8A7796
++	select CLK_R8A77970 if ARCH_R8A77970
+ 	select CLK_R8A77995 if ARCH_R8A77995
+ 	select CLK_SH73A0 if ARCH_SH73A0
+ 
+@@ -95,6 +96,10 @@ config CLK_R8A7796
+ 	bool "R-Car M3-W clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+ 
++config CLK_R8A77970
++	bool "R-Car V3M clock support" if COMPILE_TEST
++	select CLK_RCAR_GEN3_CPG
++
+ config CLK_R8A77995
+ 	bool "R-Car D3 clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index cbbb081e2145..34c4e0b37afa 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792)		+= r8a7792-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7794)		+= r8a7794-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7795)		+= r8a7795-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o
++obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
+ obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
+ 
+diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
+new file mode 100644
+index 000000000000..72f98527473a
+--- /dev/null
++++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
+@@ -0,0 +1,199 @@
++/*
++ * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2017 Cogent Embedded Inc.
++ *
++ * Based on r8a7795-cpg-mssr.c
++ *
++ * Copyright (C) 2015 Glider bvba
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++
++#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen3-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++	CLK_EXTALR,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL0,
++	CLK_PLL1,
++	CLK_PLL3,
++	CLK_PLL1_DIV2,
++	CLK_PLL1_DIV4,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",	CLK_EXTAL),
++	DEF_INPUT("extalr",	CLK_EXTALR),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
++	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
++	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
++	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
++
++	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
++	DEF_FIXED(".pll1_div4",	CLK_PLL1_DIV4,	CLK_PLL1_DIV2,	2, 1),
++
++	/* Core Clock Outputs */
++	DEF_FIXED("ztr",	R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED("ztrd2",	R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
++	DEF_FIXED("zt",		R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED("zx",		R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
++	DEF_FIXED("s1d1",	R8A77970_CLK_S1D1,  CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED("s1d2",	R8A77970_CLK_S1D2,  CLK_PLL1_DIV2,  8, 1),
++	DEF_FIXED("s1d4",	R8A77970_CLK_S1D4,  CLK_PLL1_DIV2, 16, 1),
++	DEF_FIXED("s2d1",	R8A77970_CLK_S2D1,  CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED("s2d2",	R8A77970_CLK_S2D2,  CLK_PLL1_DIV2, 12, 1),
++	DEF_FIXED("s2d4",	R8A77970_CLK_S2D4,  CLK_PLL1_DIV2, 24, 1),
++
++	DEF_FIXED("cl",		R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
++	DEF_FIXED("cp",		R8A77970_CLK_CP,    CLK_EXTAL,	    2, 1),
++
++	DEF_DIV6P1("canfd",	R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
++	DEF_DIV6P1("mso",	R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
++	DEF_DIV6P1("csi0",	R8A77970_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
++
++	DEF_FIXED("osc",	R8A77970_CLK_OSC,   CLK_PLL1_DIV2, 12*1024, 1),
++	DEF_FIXED("r",		R8A77970_CLK_R,	    CLK_EXTALR,	   1, 1),
++};
++
++static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
++	DEF_MOD("ivcp1e",		 127,	R8A77970_CLK_S2D1),
++	DEF_MOD("scif4",		 203,	R8A77970_CLK_S2D4),
++	DEF_MOD("scif3",		 204,	R8A77970_CLK_S2D4),
++	DEF_MOD("scif1",		 206,	R8A77970_CLK_S2D4),
++	DEF_MOD("scif0",		 207,	R8A77970_CLK_S2D4),
++	DEF_MOD("msiof3",		 208,	R8A77970_CLK_MSO),
++	DEF_MOD("msiof2",		 209,	R8A77970_CLK_MSO),
++	DEF_MOD("msiof1",		 210,	R8A77970_CLK_MSO),
++	DEF_MOD("msiof0",		 211,	R8A77970_CLK_MSO),
++	DEF_MOD("mfis",			 213,	R8A77970_CLK_S2D2),
++	DEF_MOD("sys-dmac2",		 217,	R8A77970_CLK_S2D1),
++	DEF_MOD("sys-dmac1",		 218,	R8A77970_CLK_S2D1),
++	DEF_MOD("rwdt",			 402,	R8A77970_CLK_R),
++	DEF_MOD("intc-ex",		 407,	R8A77970_CLK_CP),
++	DEF_MOD("intc-ap",		 408,	R8A77970_CLK_S2D1),
++	DEF_MOD("hscif3",		 517,	R8A77970_CLK_S2D1),
++	DEF_MOD("hscif2",		 518,	R8A77970_CLK_S2D1),
++	DEF_MOD("hscif1",		 519,	R8A77970_CLK_S2D1),
++	DEF_MOD("hscif0",		 520,	R8A77970_CLK_S2D1),
++	DEF_MOD("thermal",		 522,	R8A77970_CLK_CP),
++	DEF_MOD("pwm",			 523,	R8A77970_CLK_S2D4),
++	DEF_MOD("fcpvd0",		 603,	R8A77970_CLK_S2D1),
++	DEF_MOD("vspd0",		 623,	R8A77970_CLK_S2D1),
++	DEF_MOD("csi40",		 716,	R8A77970_CLK_CSI0),
++	DEF_MOD("du0",			 724,	R8A77970_CLK_S2D1),
++	DEF_MOD("vin3",			 808,	R8A77970_CLK_S2D1),
++	DEF_MOD("vin2",			 809,	R8A77970_CLK_S2D1),
++	DEF_MOD("vin1",			 810,	R8A77970_CLK_S2D1),
++	DEF_MOD("vin0",			 811,	R8A77970_CLK_S2D1),
++	DEF_MOD("etheravb",		 812,	R8A77970_CLK_S2D2),
++	DEF_MOD("gpio5",		 907,	R8A77970_CLK_CP),
++	DEF_MOD("gpio4",		 908,	R8A77970_CLK_CP),
++	DEF_MOD("gpio3",		 909,	R8A77970_CLK_CP),
++	DEF_MOD("gpio2",		 910,	R8A77970_CLK_CP),
++	DEF_MOD("gpio1",		 911,	R8A77970_CLK_CP),
++	DEF_MOD("gpio0",		 912,	R8A77970_CLK_CP),
++	DEF_MOD("can-fd",		 914,	R8A77970_CLK_S2D2),
++	DEF_MOD("i2c4",			 927,	R8A77970_CLK_S2D2),
++	DEF_MOD("i2c3",			 928,	R8A77970_CLK_S2D2),
++	DEF_MOD("i2c2",			 929,	R8A77970_CLK_S2D2),
++	DEF_MOD("i2c1",			 930,	R8A77970_CLK_S2D2),
++	DEF_MOD("i2c0",			 931,	R8A77970_CLK_S2D2),
++};
++
++static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
++};
++
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ *   MD		EXTAL		PLL0	PLL1	PLL3
++ * 14 13 19	(MHz)
++ *-------------------------------------------------
++ * 0  0  0	16.66 x 1	x192	x192	x96
++ * 0  0  1	16.66 x 1	x192	x192	x80
++ * 0  1  0	20    x 1	x160	x160	x80
++ * 0  1  1	20    x 1	x160	x160	x66
++ * 1  0  0	27    / 2	x236	x236	x118
++ * 1  0  1	27    / 2	x236	x236	x98
++ * 1  1  0	33.33 / 2	x192	x192	x96
++ * 1  1  1	33.33 / 2	x192	x192	x80
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
++					 (((md) & BIT(13)) >> 12) | \
++					 (((md) & BIT(19)) >> 19))
++
++static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
++	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
++	{ 1,		192,	1,	96,	1,	},
++	{ 1,		192,	1,	80,	1,	},
++	{ 1,		160,	1,	80,	1,	},
++	{ 1,		160,	1,	66,	1,	},
++	{ 2,		236,	1,	118,	1,	},
++	{ 2,		236,	1,	98,	1,	},
++	{ 2,		192,	1,	96,	1,	},
++	{ 2,		192,	1,	80,	1,	},
++};
++
++static int __init r8a77970_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++
++	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
++}
++
++const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks = r8a77970_core_clks,
++	.num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
++	.last_dt_core_clk = LAST_DT_CORE_CLK,
++	.num_total_core_clks = MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks = r8a77970_mod_clks,
++	.num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
++	.num_hw_mod_clks = 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks = r8a77970_crit_mod_clks,
++	.num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
++
++	/* Callbacks */
++	.init = r8a77970_cpg_mssr_init,
++	.cpg_clk_register = rcar_gen3_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 30c23b882675..4b05c159993f 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -681,6 +681,12 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a7796_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_CLK_R8A77970
++	{
++		.compatible = "renesas,r8a77970-cpg-mssr",
++		.data = &r8a77970_cpg_mssr_info,
++	},
++#endif
+ #ifdef CONFIG_CLK_R8A77995
+ 	{
+ 		.compatible = "renesas,r8a77995-cpg-mssr",
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index 94b9071d1061..66528ce3eb37 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -138,6 +138,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/0269-clk-renesas-mstp-Delete-error-messages-for-failed-me.patch b/patches/0269-clk-renesas-mstp-Delete-error-messages-for-failed-me.patch
new file mode 100644
index 00000000000000..87c6a39059dd10
--- /dev/null
+++ b/patches/0269-clk-renesas-mstp-Delete-error-messages-for-failed-me.patch
@@ -0,0 +1,48 @@
+From b0abe3ce5ff251955511fc6ad116553ea82269c7 Mon Sep 17 00:00:00 2001
+From: Markus Elfring <elfring@users.sourceforge.net>
+Date: Mon, 25 Sep 2017 10:10:51 +0200
+Subject: [PATCH 0269/1795] clk: renesas: mstp: Delete error messages for
+ failed memory allocations
+
+The script "checkpatch.pl" pointed information out like the following.
+
+WARNING: Possible unnecessary 'out of memory' message
+
+Thus fix affected source code places.
+
+Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 168bcbcb1c72a4753fc64ef384b46e330bfccd08)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-mstp.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
+index 500a9e4e03c4..c944cc421e30 100644
+--- a/drivers/clk/renesas/clk-mstp.c
++++ b/drivers/clk/renesas/clk-mstp.c
+@@ -156,10 +156,8 @@ static struct clk * __init cpg_mstp_clock_register(const char *name,
+ 	struct clk *clk;
+ 
+ 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
+-	if (!clock) {
+-		pr_err("%s: failed to allocate MSTP clock.\n", __func__);
++	if (!clock)
+ 		return ERR_PTR(-ENOMEM);
+-	}
+ 
+ 	init.name = name;
+ 	init.ops = &cpg_mstp_clock_ops;
+@@ -196,7 +194,6 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
+ 	if (group == NULL || clks == NULL) {
+ 		kfree(group);
+ 		kfree(clks);
+-		pr_err("%s: failed to allocate group\n", __func__);
+ 		return;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0270-clk-renesas-rcar-gen2-Delete-error-message-for-faile.patch b/patches/0270-clk-renesas-rcar-gen2-Delete-error-message-for-faile.patch
new file mode 100644
index 00000000000000..5c96841e04c698
--- /dev/null
+++ b/patches/0270-clk-renesas-rcar-gen2-Delete-error-message-for-faile.patch
@@ -0,0 +1,36 @@
+From b9a3a26bc2f5047917b2741cc51c5f407725059d Mon Sep 17 00:00:00 2001
+From: Markus Elfring <elfring@users.sourceforge.net>
+Date: Mon, 25 Sep 2017 10:10:51 +0200
+Subject: [PATCH 0270/1795] clk: renesas: rcar-gen2: Delete error message for
+ failed memory allocation
+
+The script "checkpatch.pl" pointed information out like the following.
+
+WARNING: Possible unnecessary 'out of memory' message
+
+Thus fix affected source code places.
+
+Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b4021bbe10017d994e5a96ebfd2677bbaf2b37e0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-rcar-gen2.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
+index 0b2e56d0d94b..d14cbe1ca29a 100644
+--- a/drivers/clk/renesas/clk-rcar-gen2.c
++++ b/drivers/clk/renesas/clk-rcar-gen2.c
+@@ -423,7 +423,6 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
+ 		/* We're leaking memory on purpose, there's no point in cleaning
+ 		 * up as the system won't boot anyway.
+ 		 */
+-		pr_err("%s: failed to allocate cpg\n", __func__);
+ 		return;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0271-clk-renesas-r8a7795-Correct-parent-clock-of-INTC-AP.patch b/patches/0271-clk-renesas-r8a7795-Correct-parent-clock-of-INTC-AP.patch
new file mode 100644
index 00000000000000..ebeac9a62c1624
--- /dev/null
+++ b/patches/0271-clk-renesas-r8a7795-Correct-parent-clock-of-INTC-AP.patch
@@ -0,0 +1,44 @@
+From 9cfc39f6f58659edd94a78b36d2342397c0c5fcf Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 10 Oct 2017 13:04:28 +0200
+Subject: [PATCH 0271/1795] clk: renesas: r8a7795: Correct parent clock of
+ INTC-AP
+
+According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
+September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
+H3 ES2.0 is S0D3.
+
+This change has no functional impact.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 21bffe57f85c24fbb8d54aea4e46d2eac77242f6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7795-cpg-mssr.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+index 762b2f8824f1..b1d9f48eae9e 100644
+--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+@@ -149,7 +149,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
+ 	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),
+ 	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),
+ 	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),
+-	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),
++	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),
+ 	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),
+ 	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),
+ 	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),
+@@ -348,6 +348,7 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
+ 	{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 },	/* SYS-DMAC2 */
+ 	{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 },	/* SYS-DMAC1 */
+ 	{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 },	/* SYS-DMAC0 */
++	{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 },	/* INTC-AP */
+ 	{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 },	/* AUDMAC1 */
+ 	{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 },	/* AUDMAC0 */
+ 	{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 },	/* PWM */
+-- 
+2.19.0
+
diff --git a/patches/0272-clk-renesas-r8a7796-Correct-parent-clock-of-INTC-AP.patch b/patches/0272-clk-renesas-r8a7796-Correct-parent-clock-of-INTC-AP.patch
new file mode 100644
index 00000000000000..82020b2935eab0
--- /dev/null
+++ b/patches/0272-clk-renesas-r8a7796-Correct-parent-clock-of-INTC-AP.patch
@@ -0,0 +1,36 @@
+From c6a279f99b38a474a441023908e4b7d6f78106a2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 10 Oct 2017 13:07:45 +0200
+Subject: [PATCH 0272/1795] clk: renesas: r8a7796: Correct parent clock of
+ INTC-AP
+
+According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
+September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
+M3-W is S0D3.
+
+This change has no functional impact.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6e7ddf89d67c2b0cdd7a392bece9411789dda49b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+index e5e7fb212288..b3767472088a 100644
+--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+@@ -143,7 +143,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
+ 	DEF_MOD("usb-dmac1",		 331,	R8A7796_CLK_S3D1),
+ 	DEF_MOD("rwdt",			 402,	R8A7796_CLK_R),
+ 	DEF_MOD("intc-ex",		 407,	R8A7796_CLK_CP),
+-	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),
++	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S0D3),
+ 	DEF_MOD("audmac1",		 501,	R8A7796_CLK_S0D3),
+ 	DEF_MOD("audmac0",		 502,	R8A7796_CLK_S0D3),
+ 	DEF_MOD("drif7",		 508,	R8A7796_CLK_S3D2),
+-- 
+2.19.0
+
diff --git a/patches/0273-clk-renesas-r8a77995-Correct-parent-clock-of-INTC-AP.patch b/patches/0273-clk-renesas-r8a77995-Correct-parent-clock-of-INTC-AP.patch
new file mode 100644
index 00000000000000..123be805aac759
--- /dev/null
+++ b/patches/0273-clk-renesas-r8a77995-Correct-parent-clock-of-INTC-AP.patch
@@ -0,0 +1,36 @@
+From 475dce5c147717255ae2bcbd4f4133157846d9ad Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 10 Oct 2017 13:08:11 +0200
+Subject: [PATCH 0273/1795] clk: renesas: r8a77995: Correct parent clock of
+ INTC-AP
+
+According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
+September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
+D3 is S1D2.
+
+This change has no functional impact.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0022e4a2ef8f20257b21b8fa27c0cb683485270b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
+index e594cf8ee63b..ea4cafbe6e85 100644
+--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
+@@ -127,7 +127,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
+ 	DEF_MOD("usb-dmac1",		 331,	R8A77995_CLK_S3D1),
+ 	DEF_MOD("rwdt",			 402,	R8A77995_CLK_R),
+ 	DEF_MOD("intc-ex",		 407,	R8A77995_CLK_CP),
+-	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S3D1),
++	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S1D2),
+ 	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S3D1),
+ 	DEF_MOD("hscif3",		 517,	R8A77995_CLK_S3D1C),
+ 	DEF_MOD("hscif0",		 520,	R8A77995_CLK_S3D1C),
+-- 
+2.19.0
+
diff --git a/patches/0274-dt-bindings-clk-r7s72100-Add-missing-I-and-G-clocks.patch b/patches/0274-dt-bindings-clk-r7s72100-Add-missing-I-and-G-clocks.patch
new file mode 100644
index 00000000000000..1c47ba1615b140
--- /dev/null
+++ b/patches/0274-dt-bindings-clk-r7s72100-Add-missing-I-and-G-clocks.patch
@@ -0,0 +1,38 @@
+From 04db571fcda05d741275fd0b725888b9b55483fb Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:04 +0200
+Subject: [PATCH 0274/1795] dt-bindings: clk: r7s72100: Add missing I and G
+ clocks
+
+Add the missing definitions for the I (CPU) and G (Image Processing)
+clocks, so these clocks can be referred to from device nodes in DT.
+
+Note that these clocks are already fully supported otherwise (DT
+bindings, Linux driver, r7s72100.dtsi), they were just omitted from the
+header file.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 44842cc8a89aa7742bc47737aa75da5910aa5f33)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/clock/r7s72100-clock.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
+index 7dd8bc0c3cd0..0dcb3e87d44c 100644
+--- a/include/dt-bindings/clock/r7s72100-clock.h
++++ b/include/dt-bindings/clock/r7s72100-clock.h
+@@ -11,6 +11,8 @@
+ #define __DT_BINDINGS_CLOCK_R7S72100_H__
+ 
+ #define R7S72100_CLK_PLL	0
++#define R7S72100_CLK_I		1
++#define R7S72100_CLK_G		2
+ 
+ /* MSTP2 */
+ #define R7S72100_CLK_CORESIGHT	0
+-- 
+2.19.0
+
diff --git a/patches/0275-clk-renesas-rz-clk-rz-is-meant-for-RZ-A1.patch b/patches/0275-clk-renesas-rz-clk-rz-is-meant-for-RZ-A1.patch
new file mode 100644
index 00000000000000..9ad943cc2ece41
--- /dev/null
+++ b/patches/0275-clk-renesas-rz-clk-rz-is-meant-for-RZ-A1.patch
@@ -0,0 +1,47 @@
+From 03d64d8af06c8c14f445b81607cdb48bbc3cf577 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 10:54:22 +0200
+Subject: [PATCH 0275/1795] clk: renesas: rz: clk-rz is meant for RZ/A1
+
+The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
+RZ/G, RZ/N, and RZ/T).  Clarify that the renesas,rz-cpg-clocks DT
+bindings and clk-rz driver apply to RZ/A1 only.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit d454cecc637b90996ab15b2e61a6cc51b7e1463c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/clock/renesas,rz-cpg-clocks.txt       | 4 ++--
+ drivers/clk/renesas/clk-rz.c                                  | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+index bb5d942075fb..8ff3e2774ed8 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+@@ -1,6 +1,6 @@
+-* Renesas RZ Clock Pulse Generator (CPG)
++* Renesas RZ/A1 Clock Pulse Generator (CPG)
+ 
+-The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
++The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
+ CPU and GPU clocks, and several fixed ratio dividers.
+ The CPG also provides a Clock Domain for SoC devices, in combination with the
+ CPG Module Stop (MSTP) Clocks.
+diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
+index 5adb934326d1..127c58135c8f 100644
+--- a/drivers/clk/renesas/clk-rz.c
++++ b/drivers/clk/renesas/clk-rz.c
+@@ -1,5 +1,5 @@
+ /*
+- * rz Core CPG Clocks
++ * RZ/A1 Core CPG Clocks
+  *
+  * Copyright (C) 2013 Ideas On Board SPRL
+  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+-- 
+2.19.0
+
diff --git a/patches/0276-clk-renesas-cpg-mssr-Add-du1-clock-to-R8A7745.patch b/patches/0276-clk-renesas-cpg-mssr-Add-du1-clock-to-R8A7745.patch
new file mode 100644
index 00000000000000..394e41dc979514
--- /dev/null
+++ b/patches/0276-clk-renesas-cpg-mssr-Add-du1-clock-to-R8A7745.patch
@@ -0,0 +1,30 @@
+From 21b3f97340469262eee16a38dca60d5c26360f66 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 13 Oct 2017 16:22:21 +0100
+Subject: [PATCH 0276/1795] clk: renesas: cpg-mssr: Add du1 clock to R8A7745
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9dc0ddee8d6dcc201b7f9ebc1c0834b0fa306096)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7745-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+index 9e2360a8e14b..2859504cc866 100644
+--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
+ 	DEF_MOD("scif2",		 719,	R8A7745_CLK_P),
+ 	DEF_MOD("scif1",		 720,	R8A7745_CLK_P),
+ 	DEF_MOD("scif0",		 721,	R8A7745_CLK_P),
++	DEF_MOD("du1",			 723,	R8A7745_CLK_ZX),
+ 	DEF_MOD("du0",			 724,	R8A7745_CLK_ZX),
+ 	DEF_MOD("ipmmu-sgx",		 800,	R8A7745_CLK_ZX),
+ 	DEF_MOD("vin1",			 810,	R8A7745_CLK_ZG),
+-- 
+2.19.0
+
diff --git a/patches/0277-clk-renesas-cpg-mssr-Restore-module-clocks-during-re.patch b/patches/0277-clk-renesas-cpg-mssr-Restore-module-clocks-during-re.patch
new file mode 100644
index 00000000000000..fb7001853173d6
--- /dev/null
+++ b/patches/0277-clk-renesas-cpg-mssr-Restore-module-clocks-during-re.patch
@@ -0,0 +1,186 @@
+From 04609a5a9b37f365963103b69cd42ffbac9f9545 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 7 Jun 2017 13:20:06 +0200
+Subject: [PATCH 0277/1795] clk: renesas: cpg-mssr: Restore module clocks
+ during resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
+clock register state is lost.  Note that as the boot loader skips most
+initialization after system resume, clock register state differs from
+the state encountered during normal system boot, too.
+
+Hence after s2ram, some operations may fail because module clocks are
+disabled, while drivers expect them to be still enabled.  E.g. EtherAVB
+fails when Wake-on-LAN has been enabled using "ethtool -s eth0 wol g":
+
+    ravb e6800000.ethernet eth0: failed to switch device to config mode
+    ravb e6800000.ethernet eth0: device will be stopped after h/w processes are done.
+    ravb e6800000.ethernet eth0: failed to switch device to config
+    PM: Device e6800000.ethernet failed to resume: error -110
+
+In addition, some module clocks that were disabled by
+clk_disable_unused() may have been re-enabled, wasting power.
+
+To fix this, restore all bits of the SMSTPCR registers that represent
+clocks under control of Linux.
+
+Notes:
+  - While this fixes EtherAVB operation after resume from s2ram,
+    EtherAVB cannot be used as an actual wake-up source from s2ram, only
+    from s2idle, due to PSCI limitations,
+  - To avoid overhead on platforms not needing it, the suspend/resume
+    code has a build time dependency on sleep and PSCI support, and a
+    runtime dependency on PSCI.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 560869100b99a3daea329efce738a3b7ae357be8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/renesas-cpg-mssr.c | 84 ++++++++++++++++++++++++++
+ 1 file changed, 84 insertions(+)
+
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 4b05c159993f..3af0b5328fb0 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -26,6 +26,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_clock.h>
+ #include <linux/pm_domain.h>
++#include <linux/psci.h>
+ #include <linux/reset-controller.h>
+ #include <linux/slab.h>
+ 
+@@ -106,6 +107,8 @@ static const u16 srcr[] = {
+  * @num_core_clks: Number of Core Clocks in clks[]
+  * @num_mod_clks: Number of Module Clocks in clks[]
+  * @last_dt_core_clk: ID of the last Core Clock exported to DT
++ * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
++ * @smstpcr_saved[].val: Saved values of SMSTPCR[]
+  */
+ struct cpg_mssr_priv {
+ #ifdef CONFIG_RESET_CONTROLLER
+@@ -119,6 +122,11 @@ struct cpg_mssr_priv {
+ 	unsigned int num_core_clks;
+ 	unsigned int num_mod_clks;
+ 	unsigned int last_dt_core_clk;
++
++	struct {
++		u32 mask;
++		u32 val;
++	} smstpcr_saved[ARRAY_SIZE(smstpcr)];
+ };
+ 
+ 
+@@ -383,6 +391,7 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
+ 
+ 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
+ 	priv->clks[id] = clk;
++	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
+ 	return;
+ 
+ fail:
+@@ -701,6 +710,79 @@ static void cpg_mssr_del_clk_provider(void *data)
+ 	of_clk_del_provider(data);
+ }
+ 
++#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
++static int cpg_mssr_suspend_noirq(struct device *dev)
++{
++	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
++	unsigned int reg;
++
++	/* This is the best we can do to check for the presence of PSCI */
++	if (!psci_ops.cpu_suspend)
++		return 0;
++
++	/* Save module registers with bits under our control */
++	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
++		if (priv->smstpcr_saved[reg].mask)
++			priv->smstpcr_saved[reg].val =
++				readl(priv->base + SMSTPCR(reg));
++	}
++
++	return 0;
++}
++
++static int cpg_mssr_resume_noirq(struct device *dev)
++{
++	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
++	unsigned int reg, i;
++	u32 mask, oldval, newval;
++
++	/* This is the best we can do to check for the presence of PSCI */
++	if (!psci_ops.cpu_suspend)
++		return 0;
++
++	/* Restore module clocks */
++	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
++		mask = priv->smstpcr_saved[reg].mask;
++		if (!mask)
++			continue;
++
++		oldval = readl(priv->base + SMSTPCR(reg));
++		newval = oldval & ~mask;
++		newval |= priv->smstpcr_saved[reg].val & mask;
++		if (newval == oldval)
++			continue;
++
++		writel(newval, priv->base + SMSTPCR(reg));
++
++		/* Wait until enabled clocks are really enabled */
++		mask &= ~priv->smstpcr_saved[reg].val;
++		if (!mask)
++			continue;
++
++		for (i = 1000; i > 0; --i) {
++			oldval = readl(priv->base + MSTPSR(reg));
++			if (!(oldval & mask))
++				break;
++			cpu_relax();
++		}
++
++		if (!i)
++			dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
++				 priv->base + SMSTPCR(reg), oldval & mask);
++	}
++
++	return 0;
++}
++
++static const struct dev_pm_ops cpg_mssr_pm = {
++	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
++				      cpg_mssr_resume_noirq)
++};
++#define DEV_PM_OPS	&cpg_mssr_pm
++#else
++#define DEV_PM_OPS	NULL
++#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
++
+ static int __init cpg_mssr_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -736,6 +818,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
+ 	if (!clks)
+ 		return -ENOMEM;
+ 
++	dev_set_drvdata(dev, priv);
+ 	priv->clks = clks;
+ 	priv->num_core_clks = info->num_total_core_clks;
+ 	priv->num_mod_clks = info->num_hw_mod_clks;
+@@ -776,6 +859,7 @@ static struct platform_driver cpg_mssr_driver = {
+ 	.driver		= {
+ 		.name	= "renesas-cpg-mssr",
+ 		.of_match_table = cpg_mssr_match,
++		.pm = DEV_PM_OPS,
+ 	},
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0278-clk-renesas-cpg-mssr-Add-support-to-restore-core-clo.patch b/patches/0278-clk-renesas-cpg-mssr-Add-support-to-restore-core-clo.patch
new file mode 100644
index 00000000000000..af22fab4561c1d
--- /dev/null
+++ b/patches/0278-clk-renesas-cpg-mssr-Add-support-to-restore-core-clo.patch
@@ -0,0 +1,169 @@
+From bee7831ae25e2d51fde4a930ac04f43fa730f7c0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 21 Jun 2017 22:24:15 +0200
+Subject: [PATCH 0278/1795] clk: renesas: cpg-mssr: Add support to restore core
+ clocks during resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
+losing clock configuration.  Hence add a notifier chain that can be used
+by core clocks to save/restore clock state during system suspend/resume.
+
+The implementation of the actual clock state save/restore operations is
+clock-specific, and to be registered with the notifier chain in the SoC
+or family-specific cpg_mssr_info.cpg_clk_register() callback.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 1f4023cdd1bdbe6cb01d0b2cbd1f46207189e3cf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen2-cpg.c    |  7 +++----
+ drivers/clk/renesas/rcar-gen2-cpg.h    |  6 +++---
+ drivers/clk/renesas/rcar-gen3-cpg.c    |  3 ++-
+ drivers/clk/renesas/rcar-gen3-cpg.h    |  3 ++-
+ drivers/clk/renesas/renesas-cpg-mssr.c | 12 +++++++++++-
+ drivers/clk/renesas/renesas-cpg-mssr.h |  3 ++-
+ 6 files changed, 23 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
+index 123b1e622179..feb14579a71b 100644
+--- a/drivers/clk/renesas/rcar-gen2-cpg.c
++++ b/drivers/clk/renesas/rcar-gen2-cpg.c
+@@ -262,10 +262,9 @@ static unsigned int cpg_pll0_div __initdata;
+ static u32 cpg_mode __initdata;
+ 
+ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+-					       const struct cpg_core_clk *core,
+-					       const struct cpg_mssr_info *info,
+-					       struct clk **clks,
+-					       void __iomem *base)
++	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
++	struct clk **clks, void __iomem *base,
++	struct raw_notifier_head *notifiers)
+ {
+ 	const struct clk_div_table *table = NULL;
+ 	const struct clk *parent;
+diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h
+index 9eba07ff8b11..020a3baad015 100644
+--- a/drivers/clk/renesas/rcar-gen2-cpg.h
++++ b/drivers/clk/renesas/rcar-gen2-cpg.h
+@@ -34,9 +34,9 @@ struct rcar_gen2_cpg_pll_config {
+ };
+ 
+ struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
+-				       const struct cpg_core_clk *core,
+-				       const struct cpg_mssr_info *info,
+-				       struct clk **clks, void __iomem *base);
++	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
++	struct clk **clks, void __iomem *base,
++	struct raw_notifier_head *notifiers);
+ int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
+ 		       unsigned int pll0_div, u32 mode);
+ 
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index 951105816547..139985257003 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -265,7 +265,8 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
+ 
+ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+-	struct clk **clks, void __iomem *base)
++	struct clk **clks, void __iomem *base,
++	struct raw_notifier_head *notifiers)
+ {
+ 	const struct clk *parent;
+ 	unsigned int mult = 1;
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
+index d756ef8b78eb..2e4284399f53 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.h
++++ b/drivers/clk/renesas/rcar-gen3-cpg.h
+@@ -44,7 +44,8 @@ struct rcar_gen3_cpg_pll_config {
+ 
+ struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
+ 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+-	struct clk **clks, void __iomem *base);
++	struct clk **clks, void __iomem *base,
++	struct raw_notifier_head *notifiers);
+ int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
+ 		       unsigned int clk_extalr, u32 mode);
+ 
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 3af0b5328fb0..080ddfc695d6 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -107,6 +107,7 @@ static const u16 srcr[] = {
+  * @num_core_clks: Number of Core Clocks in clks[]
+  * @num_mod_clks: Number of Module Clocks in clks[]
+  * @last_dt_core_clk: ID of the last Core Clock exported to DT
++ * @notifiers: Notifier chain to save/restore clock state for system resume
+  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
+  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
+  */
+@@ -123,6 +124,7 @@ struct cpg_mssr_priv {
+ 	unsigned int num_mod_clks;
+ 	unsigned int last_dt_core_clk;
+ 
++	struct raw_notifier_head notifiers;
+ 	struct {
+ 		u32 mask;
+ 		u32 val;
+@@ -313,7 +315,8 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
+ 	default:
+ 		if (info->cpg_clk_register)
+ 			clk = info->cpg_clk_register(dev, core, info,
+-						     priv->clks, priv->base);
++						     priv->clks, priv->base,
++						     &priv->notifiers);
+ 		else
+ 			dev_err(dev, "%s has unsupported core clock type %u\n",
+ 				core->name, core->type);
+@@ -727,6 +730,9 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
+ 				readl(priv->base + SMSTPCR(reg));
+ 	}
+ 
++	/* Save core clocks */
++	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
++
+ 	return 0;
+ }
+ 
+@@ -740,6 +746,9 @@ static int cpg_mssr_resume_noirq(struct device *dev)
+ 	if (!psci_ops.cpu_suspend)
+ 		return 0;
+ 
++	/* Restore core clocks */
++	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
++
+ 	/* Restore module clocks */
+ 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
+ 		mask = priv->smstpcr_saved[reg].mask;
+@@ -823,6 +832,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
+ 	priv->num_core_clks = info->num_total_core_clks;
+ 	priv->num_mod_clks = info->num_hw_mod_clks;
+ 	priv->last_dt_core_clk = info->last_dt_core_clk;
++	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
+ 
+ 	for (i = 0; i < nclks; i++)
+ 		clks[i] = ERR_PTR(-ENOENT);
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index 66528ce3eb37..0745b0930308 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -127,7 +127,8 @@ struct cpg_mssr_info {
+ 	struct clk *(*cpg_clk_register)(struct device *dev,
+ 					const struct cpg_core_clk *core,
+ 					const struct cpg_mssr_info *info,
+-					struct clk **clks, void __iomem *base);
++					struct clk **clks, void __iomem *base,
++					struct raw_notifier_head *notifiers);
+ };
+ 
+ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
+-- 
+2.19.0
+
diff --git a/patches/0279-clk-renesas-div6-Restore-clock-state-during-resume.patch b/patches/0279-clk-renesas-div6-Restore-clock-state-during-resume.patch
new file mode 100644
index 00000000000000..d236fd082b5755
--- /dev/null
+++ b/patches/0279-clk-renesas-div6-Restore-clock-state-during-resume.patch
@@ -0,0 +1,158 @@
+From 40bb75f4cf2b7017af8c0783ca720713c8934d34 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 21 Jun 2017 22:34:33 +0200
+Subject: [PATCH 0279/1795] clk: renesas: div6: Restore clock state during
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
+clock configuration.  Register an (optional) notifier to restore the
+DIV6 clock state during system resume.
+
+As DIV6 clocks can be picky w.r.t. modifying multiple register fields at
+once, restore is not implemented by blindly restoring the register
+value, but by using the existing cpg_div6_clock_{en,dis}able() helpers.
+
+Note that this does not yet support DIV6 clocks with multiple parents,
+which do not exist on R-Car Gen3 SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 9f8c71e5134982cdf8ee35acb204715a2a47ba2e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-div6.c         | 38 ++++++++++++++++++++++++--
+ drivers/clk/renesas/clk-div6.h         |  3 +-
+ drivers/clk/renesas/renesas-cpg-mssr.c |  3 +-
+ 3 files changed, 40 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
+index 3e0040c0ac87..151336d2ba59 100644
+--- a/drivers/clk/renesas/clk-div6.c
++++ b/drivers/clk/renesas/clk-div6.c
+@@ -14,8 +14,10 @@
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
++#include <linux/notifier.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
++#include <linux/pm.h>
+ #include <linux/slab.h>
+ 
+ #include "clk-div6.h"
+@@ -32,6 +34,7 @@
+  * @src_shift: Shift to access the register bits to select the parent clock
+  * @src_width: Number of register bits to select the parent clock (may be 0)
+  * @parents: Array to map from valid parent clocks indices to hardware indices
++ * @nb: Notifier block to save/restore clock state for system resume
+  */
+ struct div6_clock {
+ 	struct clk_hw hw;
+@@ -40,6 +43,7 @@ struct div6_clock {
+ 	u32 src_shift;
+ 	u32 src_width;
+ 	u8 *parents;
++	struct notifier_block nb;
+ };
+ 
+ #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
+@@ -176,6 +180,29 @@ static const struct clk_ops cpg_div6_clock_ops = {
+ 	.set_rate = cpg_div6_clock_set_rate,
+ };
+ 
++static int cpg_div6_clock_notifier_call(struct notifier_block *nb,
++					unsigned long action, void *data)
++{
++	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
++
++	switch (action) {
++	case PM_EVENT_RESUME:
++		/*
++		 * TODO: This does not yet support DIV6 clocks with multiple
++		 * parents, as the parent selection bits are not restored.
++		 * Fortunately so far such DIV6 clocks are found only on
++		 * R/SH-Mobile SoCs, while the resume functionality is only
++		 * needed on R-Car Gen3.
++		 */
++		if (__clk_get_enable_count(clock->hw.clk))
++			cpg_div6_clock_enable(&clock->hw);
++		else
++			cpg_div6_clock_disable(&clock->hw);
++		return NOTIFY_OK;
++	}
++
++	return NOTIFY_DONE;
++}
+ 
+ /**
+  * cpg_div6_register - Register a DIV6 clock
+@@ -183,11 +210,13 @@ static const struct clk_ops cpg_div6_clock_ops = {
+  * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
+  * @parent_names: Array containing the names of the parent clocks
+  * @reg: Mapped register used to control the DIV6 clock
++ * @notifiers: Optional notifier chain to save/restore state for system resume
+  */
+ struct clk * __init cpg_div6_register(const char *name,
+ 				      unsigned int num_parents,
+ 				      const char **parent_names,
+-				      void __iomem *reg)
++				      void __iomem *reg,
++				      struct raw_notifier_head *notifiers)
+ {
+ 	unsigned int valid_parents;
+ 	struct clk_init_data init;
+@@ -258,6 +287,11 @@ struct clk * __init cpg_div6_register(const char *name,
+ 	if (IS_ERR(clk))
+ 		goto free_parents;
+ 
++	if (notifiers) {
++		clock->nb.notifier_call = cpg_div6_clock_notifier_call;
++		raw_notifier_chain_register(notifiers, &clock->nb);
++	}
++
+ 	return clk;
+ 
+ free_parents:
+@@ -301,7 +335,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
+ 	for (i = 0; i < num_parents; i++)
+ 		parent_names[i] = of_clk_get_parent_name(np, i);
+ 
+-	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
++	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
+ 	if (IS_ERR(clk)) {
+ 		pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
+ 		       __func__, np->name, PTR_ERR(clk));
+diff --git a/drivers/clk/renesas/clk-div6.h b/drivers/clk/renesas/clk-div6.h
+index 065dfb49adf6..3af640a0b08d 100644
+--- a/drivers/clk/renesas/clk-div6.h
++++ b/drivers/clk/renesas/clk-div6.h
+@@ -3,6 +3,7 @@
+ #define __RENESAS_CLK_DIV6_H__
+ 
+ struct clk *cpg_div6_register(const char *name, unsigned int num_parents,
+-			      const char **parent_names, void __iomem *reg);
++			      const char **parent_names, void __iomem *reg,
++			      struct raw_notifier_head *notifiers);
+ 
+ #endif
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 080ddfc695d6..998a2f4b5db5 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -304,7 +304,8 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
+ 
+ 		if (core->type == CLK_TYPE_DIV6P1) {
+ 			clk = cpg_div6_register(core->name, 1, &parent_name,
+-						priv->base + core->offset);
++						priv->base + core->offset,
++						&priv->notifiers);
+ 		} else {
+ 			clk = clk_register_fixed_factor(NULL, core->name,
+ 							parent_name, 0,
+-- 
+2.19.0
+
diff --git a/patches/0280-clk-renesas-rcar-gen3-Restore-SDHI-clocks-during-res.patch b/patches/0280-clk-renesas-rcar-gen3-Restore-SDHI-clocks-during-res.patch
new file mode 100644
index 00000000000000..2fe3060831457e
--- /dev/null
+++ b/patches/0280-clk-renesas-rcar-gen3-Restore-SDHI-clocks-during-res.patch
@@ -0,0 +1,184 @@
+From ca28660adc03f2c0fd9f6f202338a1b61f4b73b6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 21 Jun 2017 22:51:21 +0200
+Subject: [PATCH 0280/1795] clk: renesas: rcar-gen3: Restore SDHI clocks during
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
+clock configuration.  Register a notifier to save/restore SDHI clock
+registers during system suspend/resume.
+
+This is implemented using the cpg_simple_notifier abstraction, which can
+be reused for others clocks that just need to save/restore a single
+register.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 9f55b17ff6387ab9c4caa9280e2e194bb03ad532)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen3-cpg.c | 63 +++++++++++++++++++++++------
+ 1 file changed, 50 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index 139985257003..267b5629e3bd 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -19,6 +19,7 @@
+ #include <linux/err.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
++#include <linux/pm.h>
+ #include <linux/slab.h>
+ #include <linux/sys_soc.h>
+ 
+@@ -29,6 +30,36 @@
+ #define CPG_PLL2CR		0x002c
+ #define CPG_PLL4CR		0x01f4
+ 
++struct cpg_simple_notifier {
++	struct notifier_block nb;
++	void __iomem *reg;
++	u32 saved;
++};
++
++static int cpg_simple_notifier_call(struct notifier_block *nb,
++				    unsigned long action, void *data)
++{
++	struct cpg_simple_notifier *csn =
++		container_of(nb, struct cpg_simple_notifier, nb);
++
++	switch (action) {
++	case PM_EVENT_SUSPEND:
++		csn->saved = readl(csn->reg);
++		return NOTIFY_OK;
++
++	case PM_EVENT_RESUME:
++		writel(csn->saved, csn->reg);
++		return NOTIFY_OK;
++	}
++	return NOTIFY_DONE;
++}
++
++static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
++					 struct cpg_simple_notifier *csn)
++{
++	csn->nb.notifier_call = cpg_simple_notifier_call;
++	raw_notifier_chain_register(notifiers, &csn->nb);
++}
+ 
+ /*
+  * SDn Clock
+@@ -55,8 +86,8 @@ struct sd_div_table {
+ 
+ struct sd_clock {
+ 	struct clk_hw hw;
+-	void __iomem *reg;
+ 	const struct sd_div_table *div_table;
++	struct cpg_simple_notifier csn;
+ 	unsigned int div_num;
+ 	unsigned int div_min;
+ 	unsigned int div_max;
+@@ -97,12 +128,12 @@ static const struct sd_div_table cpg_sd_div_table[] = {
+ static int cpg_sd_clock_enable(struct clk_hw *hw)
+ {
+ 	struct sd_clock *clock = to_sd_clock(hw);
+-	u32 val = readl(clock->reg);
++	u32 val = readl(clock->csn.reg);
+ 
+ 	val &= ~(CPG_SD_STP_MASK);
+ 	val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
+ 
+-	writel(val, clock->reg);
++	writel(val, clock->csn.reg);
+ 
+ 	return 0;
+ }
+@@ -111,14 +142,14 @@ static void cpg_sd_clock_disable(struct clk_hw *hw)
+ {
+ 	struct sd_clock *clock = to_sd_clock(hw);
+ 
+-	writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
++	writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
+ }
+ 
+ static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
+ {
+ 	struct sd_clock *clock = to_sd_clock(hw);
+ 
+-	return !(readl(clock->reg) & CPG_SD_STP_MASK);
++	return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
+ }
+ 
+ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
+@@ -170,10 +201,10 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
+ 
+ 	clock->cur_div_idx = i;
+ 
+-	val = readl(clock->reg);
++	val = readl(clock->csn.reg);
+ 	val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
+ 	val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
+-	writel(val, clock->reg);
++	writel(val, clock->csn.reg);
+ 
+ 	return 0;
+ }
+@@ -188,8 +219,8 @@ static const struct clk_ops cpg_sd_clock_ops = {
+ };
+ 
+ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
+-					       void __iomem *base,
+-					       const char *parent_name)
++	void __iomem *base, const char *parent_name,
++	struct raw_notifier_head *notifiers)
+ {
+ 	struct clk_init_data init;
+ 	struct sd_clock *clock;
+@@ -207,12 +238,12 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
+ 	init.parent_names = &parent_name;
+ 	init.num_parents = 1;
+ 
+-	clock->reg = base + core->offset;
++	clock->csn.reg = base + core->offset;
+ 	clock->hw.init = &init;
+ 	clock->div_table = cpg_sd_div_table;
+ 	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
+ 
+-	sd_fc = readl(clock->reg) & CPG_SD_FC_MASK;
++	sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
+ 	for (i = 0; i < clock->div_num; i++)
+ 		if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
+ 			break;
+@@ -233,8 +264,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
+ 
+ 	clk = clk_register(NULL, &clock->hw);
+ 	if (IS_ERR(clk))
+-		kfree(clock);
++		goto free_clock;
++
++	cpg_simple_notifier_register(notifiers, &clock->csn);
++	return clk;
+ 
++free_clock:
++	kfree(clock);
+ 	return clk;
+ }
+ 
+@@ -332,7 +368,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 		break;
+ 
+ 	case CLK_TYPE_GEN3_SD:
+-		return cpg_sd_clk_register(core, base, __clk_get_name(parent));
++		return cpg_sd_clk_register(core, base, __clk_get_name(parent),
++					   notifiers);
+ 
+ 	case CLK_TYPE_GEN3_R:
+ 		if (cpg_quirks & RCKCR_CKSEL) {
+-- 
+2.19.0
+
diff --git a/patches/0281-clk-renesas-rcar-gen3-Restore-R-clock-during-resume.patch b/patches/0281-clk-renesas-rcar-gen3-Restore-R-clock-during-resume.patch
new file mode 100644
index 00000000000000..eb95fddc2d7576
--- /dev/null
+++ b/patches/0281-clk-renesas-rcar-gen3-Restore-R-clock-during-resume.patch
@@ -0,0 +1,59 @@
+From 9ac4df59f7a13f5e0b994f120703d4040b986a75 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 28 Jun 2017 21:15:49 +0200
+Subject: [PATCH 0281/1795] clk: renesas: rcar-gen3: Restore R clock during
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
+clock configuration.  Register a notifier to save/restore the RCKCR
+register during system suspend/resume.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 3f7a4d084159c52513d1ff77f3b3b880bcf517d9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen3-cpg.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index 267b5629e3bd..0904886f5501 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -373,18 +373,27 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 
+ 	case CLK_TYPE_GEN3_R:
+ 		if (cpg_quirks & RCKCR_CKSEL) {
++			struct cpg_simple_notifier *csn;
++
++			csn = kzalloc(sizeof(*csn), GFP_KERNEL);
++			if (!csn)
++				return ERR_PTR(-ENOMEM);
++
++			csn->reg = base + CPG_RCKCR;
++
+ 			/*
+ 			 * RINT is default.
+ 			 * Only if EXTALR is populated, we switch to it.
+ 			 */
+-			value = readl(base + CPG_RCKCR) & 0x3f;
++			value = readl(csn->reg) & 0x3f;
+ 
+ 			if (clk_get_rate(clks[cpg_clk_extalr])) {
+ 				parent = clks[cpg_clk_extalr];
+ 				value |= BIT(15);
+ 			}
+ 
+-			writel(value, base + CPG_RCKCR);
++			writel(value, csn->reg);
++			cpg_simple_notifier_register(notifiers, csn);
+ 			break;
+ 		}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0282-dt-bindings-power-add-R8A77970-SYSC-power-domain-def.patch b/patches/0282-dt-bindings-power-add-R8A77970-SYSC-power-domain-def.patch
new file mode 100644
index 00000000000000..005ef9603a50e6
--- /dev/null
+++ b/patches/0282-dt-bindings-power-add-R8A77970-SYSC-power-domain-def.patch
@@ -0,0 +1,65 @@
+From 47f2a0db6c2a3e874d5a19ba5a5f8e0f8026394c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:37:19 +0300
+Subject: [PATCH 0282/1795] dt-bindings: power: add R8A77970 SYSC power domain
+ definitions
+
+Add macros usable by the device tree sources to reference R8A77970 SYSC
+power domains by index.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 833bdb47c826a1a64daac194c98887d1d68f2ce8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/power/r8a77970-sysc.h | 32 +++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 include/dt-bindings/power/r8a77970-sysc.h
+
+diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
+new file mode 100644
+index 000000000000..bf54779d1625
+--- /dev/null
++++ b/include/dt-bindings/power/r8a77970-sysc.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright (C) 2017 Cogent Embedded Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A77970_PD_CA53_CPU0		 5
++#define R8A77970_PD_CA53_CPU1		 6
++#define R8A77970_PD_CR7			13
++#define R8A77970_PD_CA53_SCU		21
++#define R8A77970_PD_A2IR0		23
++#define R8A77970_PD_A3IR			24
++#define R8A77970_PD_A2IR1		27
++#define R8A77970_PD_A2IR2		28
++#define R8A77970_PD_A2IR3		29
++#define R8A77970_PD_A2SC0		30
++#define R8A77970_PD_A2SC1		31
++
++/* Always-on power area */
++#define R8A77970_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0283-soc-renesas-rcar-sysc-add-R8A77970-support.patch b/patches/0283-soc-renesas-rcar-sysc-add-R8A77970-support.patch
new file mode 100644
index 00000000000000..6416926cedb737
--- /dev/null
+++ b/patches/0283-soc-renesas-rcar-sysc-add-R8A77970-support.patch
@@ -0,0 +1,149 @@
+From f8ec6a0a42bce4d4d067225f38c11a00b82398c3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 12 Sep 2017 23:37:20 +0300
+Subject: [PATCH 0283/1795] soc: renesas: rcar-sysc: add R8A77970 support
+
+Add support for R-Car V3M (R8A77970) SoC power areas to the R-Car SYSC
+driver.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bab9b2a74fe9da96e895e0919f625679a0a8c964)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/power/renesas,rcar-sysc.txt      |  1 +
+ drivers/soc/renesas/Kconfig                   |  5 +++
+ drivers/soc/renesas/Makefile                  |  1 +
+ drivers/soc/renesas/r8a77970-sysc.c           | 39 +++++++++++++++++++
+ drivers/soc/renesas/rcar-sysc.c               |  3 ++
+ drivers/soc/renesas/rcar-sysc.h               |  1 +
+ 6 files changed, 50 insertions(+)
+ create mode 100644 drivers/soc/renesas/r8a77970-sysc.c
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+index 98cc8c09d02d..8690f10426a3 100644
+--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
++++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+@@ -17,6 +17,7 @@ Required properties:
+       - "renesas,r8a7794-sysc" (R-Car E2)
+       - "renesas,r8a7795-sysc" (R-Car H3)
+       - "renesas,r8a7796-sysc" (R-Car M3-W)
++      - "renesas,r8a77970-sysc" (R-Car V3M)
+       - "renesas,r8a77995-sysc" (R-Car D3)
+   - reg: Address start and address range for the device.
+   - #power-domain-cells: Must be 1.
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index f0d562a7c4d3..09550b1da56d 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -14,6 +14,7 @@ config SOC_RENESAS
+ 	select SYSC_R8A7794 if ARCH_R8A7794
+ 	select SYSC_R8A7795 if ARCH_R8A7795
+ 	select SYSC_R8A7796 if ARCH_R8A7796
++	select SYSC_R8A77970 if ARCH_R8A77970
+ 	select SYSC_R8A77995 if ARCH_R8A77995
+ 
+ if SOC_RENESAS
+@@ -55,6 +56,10 @@ config SYSC_R8A7796
+ 	bool "R-Car M3-W System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+ 
++config SYSC_R8A77970
++	bool "R-Car V3M System Controller support" if COMPILE_TEST
++	select SYSC_RCAR
++
+ config SYSC_R8A77995
+ 	bool "R-Car D3 System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index 763c03d80436..845d62a08ce1 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSC_R8A7792)	+= r8a7792-sysc.o
+ obj-$(CONFIG_SYSC_R8A7794)	+= r8a7794-sysc.o
+ obj-$(CONFIG_SYSC_R8A7795)	+= r8a7795-sysc.o
+ obj-$(CONFIG_SYSC_R8A7796)	+= r8a7796-sysc.o
++obj-$(CONFIG_SYSC_R8A77970)	+= r8a77970-sysc.o
+ obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
+ 
+ # Family
+diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c
+new file mode 100644
+index 000000000000..8c614164718e
+--- /dev/null
++++ b/drivers/soc/renesas/r8a77970-sysc.c
+@@ -0,0 +1,39 @@
++/*
++ * Renesas R-Car V3M System Controller
++ *
++ * Copyright (C) 2017 Cogent Embedded Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a77970-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
++	{ "ca53-scu",	0x140, 0, R8A77970_PD_CA53_SCU,	R8A77970_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca53-cpu0",	0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu1",	0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "cr7",	0x240, 0, R8A77970_PD_CR7,	R8A77970_PD_ALWAYS_ON },
++	{ "a3ir",	0x180, 0, R8A77970_PD_A3IR,	R8A77970_PD_ALWAYS_ON },
++	{ "a2ir0",	0x400, 0, R8A77970_PD_A2IR0,	R8A77970_PD_ALWAYS_ON },
++	{ "a2ir1",	0x400, 1, R8A77970_PD_A2IR1,	R8A77970_PD_A2IR0 },
++	{ "a2ir2",	0x400, 2, R8A77970_PD_A2IR2,	R8A77970_PD_A2IR0 },
++	{ "a2ir3",	0x400, 3, R8A77970_PD_A2IR3,	R8A77970_PD_A2IR0 },
++	{ "a2sc0",	0x400, 4, R8A77970_PD_A2SC0,	R8A77970_PD_ALWAYS_ON },
++	{ "a2sc1",	0x400, 5, R8A77970_PD_A2SC1,	R8A77970_PD_A2SC0 },
++};
++
++const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
++	.areas = r8a77970_areas,
++	.num_areas = ARRAY_SIZE(r8a77970_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index c8406e81640f..55a47e509e49 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] = {
+ #ifdef CONFIG_SYSC_R8A7796
+ 	{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
+ #endif
++#ifdef CONFIG_SYSC_R8A77970
++	{ .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
++#endif
+ #ifdef CONFIG_SYSC_R8A77995
+ 	{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
+ #endif
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index 2f524922c4d2..9d9daf9eb91b 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info;
+ extern const struct rcar_sysc_info r8a7794_sysc_info;
+ extern const struct rcar_sysc_info r8a7795_sysc_info;
+ extern const struct rcar_sysc_info r8a7796_sysc_info;
++extern const struct rcar_sysc_info r8a77970_sysc_info;
+ extern const struct rcar_sysc_info r8a77995_sysc_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/0284-arm64-renesas-Add-Renesas-R8A77970-Kconfig-support.patch b/patches/0284-arm64-renesas-Add-Renesas-R8A77970-Kconfig-support.patch
new file mode 100644
index 00000000000000..d0c28641ffb57b
--- /dev/null
+++ b/patches/0284-arm64-renesas-Add-Renesas-R8A77970-Kconfig-support.patch
@@ -0,0 +1,37 @@
+From c78a1c56f0f58fa7962972ee9c8f958c8077fb90 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 25 Aug 2017 14:56:50 +0200
+Subject: [PATCH 0284/1795] arm64: renesas: Add Renesas R8A77970 Kconfig
+ support
+
+Add a configuration option for the R-Car V3M SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a6d21c0940490a343c6894bd78601be9e0e36f45)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/Kconfig.platforms | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index 456d21542250..b4da79327fe0 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -185,6 +185,12 @@ config ARCH_R8A7796
+ 	help
+ 	  This enables support for the Renesas R-Car M3-W SoC.
+ 
++config ARCH_R8A77970
++	bool "Renesas R-Car V3M SoC Platform"
++	depends on ARCH_RENESAS
++	help
++	  This enables support for the Renesas R-Car V3M SoC.
++
+ config ARCH_R8A77995
+ 	bool "Renesas R-Car D3 SoC Platform"
+ 	depends on ARCH_RENESAS
+-- 
+2.19.0
+
diff --git a/patches/0285-media-v4l-async-Remove-re-probing-support.patch b/patches/0285-media-v4l-async-Remove-re-probing-support.patch
new file mode 100644
index 00000000000000..19fb4c240b240f
--- /dev/null
+++ b/patches/0285-media-v4l-async-Remove-re-probing-support.patch
@@ -0,0 +1,124 @@
+From 45d68b403db35ae5889cf74783cecbb507847630 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Tue, 5 Sep 2017 08:11:59 -0400
+Subject: [PATCH 0285/1795] media: v4l: async: Remove re-probing support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove V4L2 async re-probing support. The re-probing support has been
+there to support cases where the sub-devices require resources provided by
+the main driver's hardware to function, such as clocks.
+
+Reprobing has allowed unbinding and again binding the main driver without
+explicitly unbinding the sub-device drivers. This is certainly not a
+common need, and the responsibility will be the user's going forward.
+
+An alternative could have been to introduce notifier specific locks.
+Considering the complexity of the re-probing and that it isn't really a
+solution to a problem but a workaround, remove re-probing instead.
+
+If there is a need to support the clock provider unregister/register cycle
+while keeping the clock references in the consumers in the future, this
+should be implemented in the clock framework instead, not in V4L2.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit de8dd7b2afc3108a0dddd70f0fd897ab89e141ed)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 54 +---------------------------
+ 1 file changed, 1 insertion(+), 53 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index e67aeecd674d..ca77728077db 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -199,78 +199,26 @@ EXPORT_SYMBOL(v4l2_async_notifier_register);
+ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ {
+ 	struct v4l2_subdev *sd, *tmp;
+-	unsigned int notif_n_subdev = notifier->num_subdevs;
+-	unsigned int n_subdev = min(notif_n_subdev, V4L2_MAX_SUBDEVS);
+-	struct device **dev;
+-	int i = 0;
+ 
+ 	if (!notifier->v4l2_dev)
+ 		return;
+ 
+-	dev = kvmalloc_array(n_subdev, sizeof(*dev), GFP_KERNEL);
+-	if (!dev) {
+-		dev_err(notifier->v4l2_dev->dev,
+-			"Failed to allocate device cache!\n");
+-	}
+-
+ 	mutex_lock(&list_lock);
+ 
+ 	list_del(&notifier->list);
+ 
+ 	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
+-		struct device *d;
+-
+-		d = get_device(sd->dev);
+-
+ 		v4l2_async_cleanup(sd);
+ 
+-		/* If we handled USB devices, we'd have to lock the parent too */
+-		device_release_driver(d);
+-
+ 		if (notifier->unbind)
+ 			notifier->unbind(notifier, sd, sd->asd);
+ 
+-		/*
+-		 * Store device at the device cache, in order to call
+-		 * put_device() on the final step
+-		 */
+-		if (dev)
+-			dev[i++] = d;
+-		else
+-			put_device(d);
++		list_move(&sd->async_list, &subdev_list);
+ 	}
+ 
+ 	mutex_unlock(&list_lock);
+ 
+-	/*
+-	 * Call device_attach() to reprobe devices
+-	 *
+-	 * NOTE: If dev allocation fails, i is 0, and the whole loop won't be
+-	 * executed.
+-	 */
+-	while (i--) {
+-		struct device *d = dev[i];
+-
+-		if (d && device_attach(d) < 0) {
+-			const char *name = "(none)";
+-			int lock = device_trylock(d);
+-
+-			if (lock && d->driver)
+-				name = d->driver->name;
+-			dev_err(d, "Failed to re-probe to %s\n", name);
+-			if (lock)
+-				device_unlock(d);
+-		}
+-		put_device(d);
+-	}
+-	kvfree(dev);
+-
+ 	notifier->v4l2_dev = NULL;
+-
+-	/*
+-	 * Don't care about the waiting list, it is initialised and populated
+-	 * upon notifier registration.
+-	 */
+ }
+ EXPORT_SYMBOL(v4l2_async_notifier_unregister);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0286-media-v4l-async-Don-t-set-sd-dev-NULL-in-v4l2_async_.patch b/patches/0286-media-v4l-async-Don-t-set-sd-dev-NULL-in-v4l2_async_.patch
new file mode 100644
index 00000000000000..b054d3c12d0c18
--- /dev/null
+++ b/patches/0286-media-v4l-async-Don-t-set-sd-dev-NULL-in-v4l2_async_.patch
@@ -0,0 +1,40 @@
+From 7bec44f514a003810212fdf6e101ee50ee42a8db Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Tue, 3 Oct 2017 07:10:41 -0400
+Subject: [PATCH 0286/1795] media: v4l: async: Don't set sd->dev NULL in
+ v4l2_async_cleanup
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v4l2_async_cleanup() is called when the async sub-device is unbound from
+the media device. As the pointer is set by the driver registering the
+async sub-device, leave the pointer as set by the driver.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 99b7a995a4a02522292ea6313bd626a33fb0e037)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index ca77728077db..590fbc9e63a9 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -135,7 +135,6 @@ static void v4l2_async_cleanup(struct v4l2_subdev *sd)
+ 	/* Subdevice driver will reprobe and put the subdev back onto the list */
+ 	list_del_init(&sd->async_list);
+ 	sd->asd = NULL;
+-	sd->dev = NULL;
+ }
+ 
+ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+-- 
+2.19.0
+
diff --git a/patches/0287-media-v4l-async-fix-unbind-error-in-v4l2_async_notif.patch b/patches/0287-media-v4l-async-fix-unbind-error-in-v4l2_async_notif.patch
new file mode 100644
index 00000000000000..7f9c7cc2a3dc24
--- /dev/null
+++ b/patches/0287-media-v4l-async-fix-unbind-error-in-v4l2_async_notif.patch
@@ -0,0 +1,61 @@
+From 56b4b2d2a05140a3f3d68ec0573cb29e2177a364 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Mon, 2 Oct 2017 16:16:52 -0400
+Subject: [PATCH 0287/1795] media: v4l: async: fix unbind error in
+ v4l2_async_notifier_unregister()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The call to v4l2_async_cleanup() will set sd->asd to NULL so passing it to
+notifier->unbind() has no effect and leaves the notifier confused. Call
+the unbind() callback prior to cleaning up the subdevice to avoid this.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 633d185b7239a4b342bab4cc15a414f7d74635ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 590fbc9e63a9..325ec4062b4f 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -207,11 +207,11 @@ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ 	list_del(&notifier->list);
+ 
+ 	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
+-		v4l2_async_cleanup(sd);
+-
+ 		if (notifier->unbind)
+ 			notifier->unbind(notifier, sd, sd->asd);
+ 
++		v4l2_async_cleanup(sd);
++
+ 		list_move(&sd->async_list, &subdev_list);
+ 	}
+ 
+@@ -299,11 +299,11 @@ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd)
+ 
+ 	list_add(&sd->asd->list, &notifier->waiting);
+ 
+-	v4l2_async_cleanup(sd);
+-
+ 	if (notifier->unbind)
+ 		notifier->unbind(notifier, sd, sd->asd);
+ 
++	v4l2_async_cleanup(sd);
++
+ 	mutex_unlock(&list_lock);
+ }
+ EXPORT_SYMBOL(v4l2_async_unregister_subdev);
+-- 
+2.19.0
+
diff --git a/patches/0288-media-v4l-async-Fix-notifier-complete-callback-error.patch b/patches/0288-media-v4l-async-Fix-notifier-complete-callback-error.patch
new file mode 100644
index 00000000000000..821eac6d315d60
--- /dev/null
+++ b/patches/0288-media-v4l-async-Fix-notifier-complete-callback-error.patch
@@ -0,0 +1,179 @@
+From f0d3311fc01ce963aed5c4e6ca4136b05bbd8860 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Mon, 2 Oct 2017 06:24:54 -0400
+Subject: [PATCH 0288/1795] media: v4l: async: Fix notifier complete callback
+ error handling
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The notifier complete callback may return an error. This error code was
+simply returned to the caller but never handled properly.
+
+Move calling the complete callback function to the caller from
+v4l2_async_test_notify and undo the work that was done either in async
+sub-device or async notifier registration.
+
+Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit fb45f436b8186cafc95939087ce1dc565be26c3d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 78 +++++++++++++++++++++-------
+ 1 file changed, 60 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 325ec4062b4f..e36d6274a692 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -123,9 +123,6 @@ static int v4l2_async_test_notify(struct v4l2_async_notifier *notifier,
+ 	/* Move from the global subdevice list to notifier's done */
+ 	list_move(&sd->async_list, &notifier->done);
+ 
+-	if (list_empty(&notifier->waiting) && notifier->complete)
+-		return notifier->complete(notifier);
+-
+ 	return 0;
+ }
+ 
+@@ -137,11 +134,27 @@ static void v4l2_async_cleanup(struct v4l2_subdev *sd)
+ 	sd->asd = NULL;
+ }
+ 
++static void v4l2_async_notifier_unbind_all_subdevs(
++	struct v4l2_async_notifier *notifier)
++{
++	struct v4l2_subdev *sd, *tmp;
++
++	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
++		if (notifier->unbind)
++			notifier->unbind(notifier, sd, sd->asd);
++
++		v4l2_async_cleanup(sd);
++
++		list_move(&sd->async_list, &subdev_list);
++	}
++}
++
+ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 				 struct v4l2_async_notifier *notifier)
+ {
+ 	struct v4l2_subdev *sd, *tmp;
+ 	struct v4l2_async_subdev *asd;
++	int ret;
+ 	int i;
+ 
+ 	if (!v4l2_dev || !notifier->num_subdevs ||
+@@ -186,19 +199,30 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 		}
+ 	}
+ 
++	if (list_empty(&notifier->waiting) && notifier->complete) {
++		ret = notifier->complete(notifier);
++		if (ret)
++			goto err_complete;
++	}
++
+ 	/* Keep also completed notifiers on the list */
+ 	list_add(&notifier->list, &notifier_list);
+ 
+ 	mutex_unlock(&list_lock);
+ 
+ 	return 0;
++
++err_complete:
++	v4l2_async_notifier_unbind_all_subdevs(notifier);
++
++	mutex_unlock(&list_lock);
++
++	return ret;
+ }
+ EXPORT_SYMBOL(v4l2_async_notifier_register);
+ 
+ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ {
+-	struct v4l2_subdev *sd, *tmp;
+-
+ 	if (!notifier->v4l2_dev)
+ 		return;
+ 
+@@ -206,14 +230,7 @@ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ 
+ 	list_del(&notifier->list);
+ 
+-	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
+-		if (notifier->unbind)
+-			notifier->unbind(notifier, sd, sd->asd);
+-
+-		v4l2_async_cleanup(sd);
+-
+-		list_move(&sd->async_list, &subdev_list);
+-	}
++	v4l2_async_notifier_unbind_all_subdevs(notifier);
+ 
+ 	mutex_unlock(&list_lock);
+ 
+@@ -254,6 +271,7 @@ EXPORT_SYMBOL_GPL(v4l2_async_notifier_cleanup);
+ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ {
+ 	struct v4l2_async_notifier *notifier;
++	int ret;
+ 
+ 	/*
+ 	 * No reference taken. The reference is held by the device
+@@ -269,19 +287,43 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 
+ 	list_for_each_entry(notifier, &notifier_list, list) {
+ 		struct v4l2_async_subdev *asd = v4l2_async_belongs(notifier, sd);
+-		if (asd) {
+-			int ret = v4l2_async_test_notify(notifier, sd, asd);
+-			mutex_unlock(&list_lock);
+-			return ret;
+-		}
++		int ret;
++
++		if (!asd)
++			continue;
++
++		ret = v4l2_async_test_notify(notifier, sd, asd);
++		if (ret)
++			goto err_unlock;
++
++		if (!list_empty(&notifier->waiting) || !notifier->complete)
++			goto out_unlock;
++
++		ret = notifier->complete(notifier);
++		if (ret)
++			goto err_cleanup;
++
++		goto out_unlock;
+ 	}
+ 
+ 	/* None matched, wait for hot-plugging */
+ 	list_add(&sd->async_list, &subdev_list);
+ 
++out_unlock:
+ 	mutex_unlock(&list_lock);
+ 
+ 	return 0;
++
++err_cleanup:
++	if (notifier->unbind)
++		notifier->unbind(notifier, sd, sd->asd);
++
++	v4l2_async_cleanup(sd);
++
++err_unlock:
++	mutex_unlock(&list_lock);
++
++	return ret;
+ }
+ EXPORT_SYMBOL(v4l2_async_register_subdev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0289-media-v4l-async-Correctly-serialise-async-sub-device.patch b/patches/0289-media-v4l-async-Correctly-serialise-async-sub-device.patch
new file mode 100644
index 00000000000000..015d0276a95979
--- /dev/null
+++ b/patches/0289-media-v4l-async-Correctly-serialise-async-sub-device.patch
@@ -0,0 +1,63 @@
+From 5b1369c3e7b25db8d31afb042ab8b30810a20dfa Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Tue, 3 Oct 2017 02:26:32 -0400
+Subject: [PATCH 0289/1795] media: v4l: async: Correctly serialise async
+ sub-device unregistration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The check whether an async sub-device is bound to a notifier was performed
+without list_lock held, making it possible for another process to
+unbind the async sub-device before the sub-device unregistration function
+proceeds to take the lock.
+
+Fix this by first acquiring the lock and then proceeding with the check.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 7fc4fdb9e1bd821c0bd39543d233ac5246aef2de)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 18 +++++++-----------
+ 1 file changed, 7 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index e36d6274a692..cd0a716a3a45 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -329,20 +329,16 @@ EXPORT_SYMBOL(v4l2_async_register_subdev);
+ 
+ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd)
+ {
+-	struct v4l2_async_notifier *notifier = sd->notifier;
+-
+-	if (!sd->asd) {
+-		if (!list_empty(&sd->async_list))
+-			v4l2_async_cleanup(sd);
+-		return;
+-	}
+-
+ 	mutex_lock(&list_lock);
+ 
+-	list_add(&sd->asd->list, &notifier->waiting);
++	if (sd->asd) {
++		struct v4l2_async_notifier *notifier = sd->notifier;
+ 
+-	if (notifier->unbind)
+-		notifier->unbind(notifier, sd, sd->asd);
++		list_add(&sd->asd->list, &notifier->waiting);
++
++		if (notifier->unbind)
++			notifier->unbind(notifier, sd, sd->asd);
++	}
+ 
+ 	v4l2_async_cleanup(sd);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0290-media-v4l-async-Use-more-intuitive-names-for-interna.patch b/patches/0290-media-v4l-async-Use-more-intuitive-names-for-interna.patch
new file mode 100644
index 00000000000000..e50623cc4325d9
--- /dev/null
+++ b/patches/0290-media-v4l-async-Use-more-intuitive-names-for-interna.patch
@@ -0,0 +1,92 @@
+From 9d6b90cedd232febcabb6ec121f5869192ec4183 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Mon, 4 Sep 2017 12:44:39 -0400
+Subject: [PATCH 0290/1795] media: v4l: async: Use more intuitive names for
+ internal functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Rename internal functions to make the names of the functions better
+describe what they do.
+
+	Old name			New name
+	v4l2_async_test_notify	v4l2_async_match_notify
+	v4l2_async_belongs	v4l2_async_find_match
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Pavel Machek <pavel@ucw.cz>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit c8114d90707d04922a8f23345a88eb6baa19424f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index cd0a716a3a45..46aebfc75e43 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -61,8 +61,8 @@ static LIST_HEAD(subdev_list);
+ static LIST_HEAD(notifier_list);
+ static DEFINE_MUTEX(list_lock);
+ 
+-static struct v4l2_async_subdev *v4l2_async_belongs(struct v4l2_async_notifier *notifier,
+-						    struct v4l2_subdev *sd)
++static struct v4l2_async_subdev *v4l2_async_find_match(
++	struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd)
+ {
+ 	bool (*match)(struct v4l2_subdev *, struct v4l2_async_subdev *);
+ 	struct v4l2_async_subdev *asd;
+@@ -96,9 +96,9 @@ static struct v4l2_async_subdev *v4l2_async_belongs(struct v4l2_async_notifier *
+ 	return NULL;
+ }
+ 
+-static int v4l2_async_test_notify(struct v4l2_async_notifier *notifier,
+-				  struct v4l2_subdev *sd,
+-				  struct v4l2_async_subdev *asd)
++static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
++				   struct v4l2_subdev *sd,
++				   struct v4l2_async_subdev *asd)
+ {
+ 	int ret;
+ 
+@@ -188,11 +188,11 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 	list_for_each_entry_safe(sd, tmp, &subdev_list, async_list) {
+ 		int ret;
+ 
+-		asd = v4l2_async_belongs(notifier, sd);
++		asd = v4l2_async_find_match(notifier, sd);
+ 		if (!asd)
+ 			continue;
+ 
+-		ret = v4l2_async_test_notify(notifier, sd, asd);
++		ret = v4l2_async_match_notify(notifier, sd, asd);
+ 		if (ret < 0) {
+ 			mutex_unlock(&list_lock);
+ 			return ret;
+@@ -286,13 +286,14 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 	INIT_LIST_HEAD(&sd->async_list);
+ 
+ 	list_for_each_entry(notifier, &notifier_list, list) {
+-		struct v4l2_async_subdev *asd = v4l2_async_belongs(notifier, sd);
++		struct v4l2_async_subdev *asd = v4l2_async_find_match(notifier,
++								      sd);
+ 		int ret;
+ 
+ 		if (!asd)
+ 			continue;
+ 
+-		ret = v4l2_async_test_notify(notifier, sd, asd);
++		ret = v4l2_async_match_notify(notifier, sd, asd);
+ 		if (ret)
+ 			goto err_unlock;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0291-media-v4l-async-Move-async-subdev-notifier-operation.patch b/patches/0291-media-v4l-async-Move-async-subdev-notifier-operation.patch
new file mode 100644
index 00000000000000..68ee87d1012702
--- /dev/null
+++ b/patches/0291-media-v4l-async-Move-async-subdev-notifier-operation.patch
@@ -0,0 +1,637 @@
+From 157fa333ce17664fadc4a0dfa2435ac90b2efb5e Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Wed, 30 Aug 2017 13:18:04 -0400
+Subject: [PATCH 0291/1795] media: v4l: async: Move async subdev notifier
+ operations to a separate structure
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The async subdev notifier .bound(), .unbind() and .complete() operations
+are function pointers stored directly in the v4l2_async_subdev
+structure. As the structure isn't immutable, this creates a potential
+security risk as the function pointers are mutable.
+
+To fix this, move the function pointers to a new
+v4l2_async_subdev_operations structure that can be made const in
+drivers.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit b6ee3f0dcf43dc3e8dbbe9be9c4e728c8d52f1ba)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/am437x/am437x-vpfe.c   |  8 +++--
+ drivers/media/platform/atmel/atmel-isc.c      | 10 +++++--
+ drivers/media/platform/atmel/atmel-isi.c      | 10 +++++--
+ drivers/media/platform/davinci/vpif_capture.c |  8 +++--
+ drivers/media/platform/davinci/vpif_display.c |  8 +++--
+ drivers/media/platform/exynos4-is/media-dev.c |  8 +++--
+ drivers/media/platform/omap3isp/isp.c         |  6 +++-
+ drivers/media/platform/pxa_camera.c           |  8 +++--
+ .../media/platform/qcom/camss-8x16/camss.c    |  8 +++--
+ drivers/media/platform/rcar-vin/rcar-core.c   | 10 +++++--
+ drivers/media/platform/rcar_drif.c            | 10 +++++--
+ .../media/platform/soc_camera/soc_camera.c    | 14 +++++----
+ drivers/media/platform/stm32/stm32-dcmi.c     | 10 +++++--
+ drivers/media/platform/ti-vpe/cal.c           |  8 +++--
+ drivers/media/platform/xilinx/xilinx-vipp.c   |  8 +++--
+ drivers/media/v4l2-core/v4l2-async.c          | 30 +++++++++----------
+ drivers/staging/media/imx/imx-media-dev.c     |  8 +++--
+ include/media/v4l2-async.h                    | 29 +++++++++++-------
+ 18 files changed, 135 insertions(+), 66 deletions(-)
+
+diff --git a/drivers/media/platform/am437x/am437x-vpfe.c b/drivers/media/platform/am437x/am437x-vpfe.c
+index dfcc484cab89..0997c640191d 100644
+--- a/drivers/media/platform/am437x/am437x-vpfe.c
++++ b/drivers/media/platform/am437x/am437x-vpfe.c
+@@ -2417,6 +2417,11 @@ static int vpfe_async_complete(struct v4l2_async_notifier *notifier)
+ 	return vpfe_probe_complete(vpfe);
+ }
+ 
++static const struct v4l2_async_notifier_operations vpfe_async_ops = {
++	.bound = vpfe_async_bound,
++	.complete = vpfe_async_complete,
++};
++
+ static struct vpfe_config *
+ vpfe_get_pdata(struct platform_device *pdev)
+ {
+@@ -2590,8 +2595,7 @@ static int vpfe_probe(struct platform_device *pdev)
+ 
+ 	vpfe->notifier.subdevs = vpfe->cfg->asd;
+ 	vpfe->notifier.num_subdevs = ARRAY_SIZE(vpfe->cfg->asd);
+-	vpfe->notifier.bound = vpfe_async_bound;
+-	vpfe->notifier.complete = vpfe_async_complete;
++	vpfe->notifier.ops = &vpfe_async_ops;
+ 	ret = v4l2_async_notifier_register(&vpfe->v4l2_dev,
+ 						&vpfe->notifier);
+ 	if (ret) {
+diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c
+index d7103c5f92c3..48544c4137cb 100644
+--- a/drivers/media/platform/atmel/atmel-isc.c
++++ b/drivers/media/platform/atmel/atmel-isc.c
+@@ -1639,6 +1639,12 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier)
+ 	return 0;
+ }
+ 
++static const struct v4l2_async_notifier_operations isc_async_ops = {
++	.bound = isc_async_bound,
++	.unbind = isc_async_unbind,
++	.complete = isc_async_complete,
++};
++
+ static void isc_subdev_cleanup(struct isc_device *isc)
+ {
+ 	struct isc_subdev_entity *subdev_entity;
+@@ -1851,9 +1857,7 @@ static int atmel_isc_probe(struct platform_device *pdev)
+ 	list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
+ 		subdev_entity->notifier.subdevs = &subdev_entity->asd;
+ 		subdev_entity->notifier.num_subdevs = 1;
+-		subdev_entity->notifier.bound = isc_async_bound;
+-		subdev_entity->notifier.unbind = isc_async_unbind;
+-		subdev_entity->notifier.complete = isc_async_complete;
++		subdev_entity->notifier.ops = &isc_async_ops;
+ 
+ 		ret = v4l2_async_notifier_register(&isc->v4l2_dev,
+ 						   &subdev_entity->notifier);
+diff --git a/drivers/media/platform/atmel/atmel-isi.c b/drivers/media/platform/atmel/atmel-isi.c
+index 891fa2505efa..eadbf9def358 100644
+--- a/drivers/media/platform/atmel/atmel-isi.c
++++ b/drivers/media/platform/atmel/atmel-isi.c
+@@ -1105,6 +1105,12 @@ static int isi_graph_notify_bound(struct v4l2_async_notifier *notifier,
+ 	return 0;
+ }
+ 
++static const struct v4l2_async_notifier_operations isi_graph_notify_ops = {
++	.bound = isi_graph_notify_bound,
++	.unbind = isi_graph_notify_unbind,
++	.complete = isi_graph_notify_complete,
++};
++
+ static int isi_graph_parse(struct atmel_isi *isi, struct device_node *node)
+ {
+ 	struct device_node *ep = NULL;
+@@ -1152,9 +1158,7 @@ static int isi_graph_init(struct atmel_isi *isi)
+ 
+ 	isi->notifier.subdevs = subdevs;
+ 	isi->notifier.num_subdevs = 1;
+-	isi->notifier.bound = isi_graph_notify_bound;
+-	isi->notifier.unbind = isi_graph_notify_unbind;
+-	isi->notifier.complete = isi_graph_notify_complete;
++	isi->notifier.ops = &isi_graph_notify_ops;
+ 
+ 	ret = v4l2_async_notifier_register(&isi->v4l2_dev, &isi->notifier);
+ 	if (ret < 0) {
+diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c
+index dc8fc2120b63..4d60176caf6d 100644
+--- a/drivers/media/platform/davinci/vpif_capture.c
++++ b/drivers/media/platform/davinci/vpif_capture.c
+@@ -1500,6 +1500,11 @@ static int vpif_async_complete(struct v4l2_async_notifier *notifier)
+ 	return vpif_probe_complete();
+ }
+ 
++static const struct v4l2_async_notifier_operations vpif_async_ops = {
++	.bound = vpif_async_bound,
++	.complete = vpif_async_complete,
++};
++
+ static struct vpif_capture_config *
+ vpif_capture_get_pdata(struct platform_device *pdev)
+ {
+@@ -1693,8 +1698,7 @@ static __init int vpif_probe(struct platform_device *pdev)
+ 	} else {
+ 		vpif_obj.notifier.subdevs = vpif_obj.config->asd;
+ 		vpif_obj.notifier.num_subdevs = vpif_obj.config->asd_sizes[0];
+-		vpif_obj.notifier.bound = vpif_async_bound;
+-		vpif_obj.notifier.complete = vpif_async_complete;
++		vpif_obj.notifier.ops = &vpif_async_ops;
+ 		err = v4l2_async_notifier_register(&vpif_obj.v4l2_dev,
+ 						   &vpif_obj.notifier);
+ 		if (err) {
+diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c
+index 56fe4e5b396e..ff2f75a328c9 100644
+--- a/drivers/media/platform/davinci/vpif_display.c
++++ b/drivers/media/platform/davinci/vpif_display.c
+@@ -1232,6 +1232,11 @@ static int vpif_async_complete(struct v4l2_async_notifier *notifier)
+ 	return vpif_probe_complete();
+ }
+ 
++static const struct v4l2_async_notifier_operations vpif_async_ops = {
++	.bound = vpif_async_bound,
++	.complete = vpif_async_complete,
++};
++
+ /*
+  * vpif_probe: This function creates device entries by register itself to the
+  * V4L2 driver and initializes fields of each channel objects
+@@ -1313,8 +1318,7 @@ static __init int vpif_probe(struct platform_device *pdev)
+ 	} else {
+ 		vpif_obj.notifier.subdevs = vpif_obj.config->asd;
+ 		vpif_obj.notifier.num_subdevs = vpif_obj.config->asd_sizes[0];
+-		vpif_obj.notifier.bound = vpif_async_bound;
+-		vpif_obj.notifier.complete = vpif_async_complete;
++		vpif_obj.notifier.ops = &vpif_async_ops;
+ 		err = v4l2_async_notifier_register(&vpif_obj.v4l2_dev,
+ 						   &vpif_obj.notifier);
+ 		if (err) {
+diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c
+index d4656d5175d7..c15596b56dc9 100644
+--- a/drivers/media/platform/exynos4-is/media-dev.c
++++ b/drivers/media/platform/exynos4-is/media-dev.c
+@@ -1405,6 +1405,11 @@ static int subdev_notifier_complete(struct v4l2_async_notifier *notifier)
+ 	return media_device_register(&fmd->media_dev);
+ }
+ 
++static const struct v4l2_async_notifier_operations subdev_notifier_ops = {
++	.bound = subdev_notifier_bound,
++	.complete = subdev_notifier_complete,
++};
++
+ static int fimc_md_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -1479,8 +1484,7 @@ static int fimc_md_probe(struct platform_device *pdev)
+ 	if (fmd->num_sensors > 0) {
+ 		fmd->subdev_notifier.subdevs = fmd->async_subdevs;
+ 		fmd->subdev_notifier.num_subdevs = fmd->num_sensors;
+-		fmd->subdev_notifier.bound = subdev_notifier_bound;
+-		fmd->subdev_notifier.complete = subdev_notifier_complete;
++		fmd->subdev_notifier.ops = &subdev_notifier_ops;
+ 		fmd->num_sensors = 0;
+ 
+ 		ret = v4l2_async_notifier_register(&fmd->v4l2_dev,
+diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c
+index 9f023bc6e1b7..8c76aa08b056 100644
+--- a/drivers/media/platform/omap3isp/isp.c
++++ b/drivers/media/platform/omap3isp/isp.c
+@@ -2218,6 +2218,10 @@ static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
+ 	return media_device_register(&isp->media_dev);
+ }
+ 
++static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
++	.complete = isp_subdev_notifier_complete,
++};
++
+ /*
+  * isp_probe - Probe ISP platform device
+  * @pdev: Pointer to ISP platform device
+@@ -2386,7 +2390,7 @@ static int isp_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto error_register_entities;
+ 
+-	isp->notifier.complete = isp_subdev_notifier_complete;
++	isp->notifier.ops = &isp_subdev_notifier_ops;
+ 
+ 	ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
+ 	if (ret)
+diff --git a/drivers/media/platform/pxa_camera.c b/drivers/media/platform/pxa_camera.c
+index edca993c2b1f..9d3f0cb1d95a 100644
+--- a/drivers/media/platform/pxa_camera.c
++++ b/drivers/media/platform/pxa_camera.c
+@@ -2221,6 +2221,11 @@ static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
+ 	mutex_unlock(&pcdev->mlock);
+ }
+ 
++static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
++	.bound = pxa_camera_sensor_bound,
++	.unbind = pxa_camera_sensor_unbind,
++};
++
+ /*
+  * Driver probe, remove, suspend and resume operations
+  */
+@@ -2489,8 +2494,7 @@ static int pxa_camera_probe(struct platform_device *pdev)
+ 	pcdev->asds[0] = &pcdev->asd;
+ 	pcdev->notifier.subdevs = pcdev->asds;
+ 	pcdev->notifier.num_subdevs = 1;
+-	pcdev->notifier.bound = pxa_camera_sensor_bound;
+-	pcdev->notifier.unbind = pxa_camera_sensor_unbind;
++	pcdev->notifier.ops = &pxa_camera_sensor_ops;
+ 
+ 	if (!of_have_populated_dt())
+ 		pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
+diff --git a/drivers/media/platform/qcom/camss-8x16/camss.c b/drivers/media/platform/qcom/camss-8x16/camss.c
+index a3760b5dd1d1..390a42c17b66 100644
+--- a/drivers/media/platform/qcom/camss-8x16/camss.c
++++ b/drivers/media/platform/qcom/camss-8x16/camss.c
+@@ -601,6 +601,11 @@ static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
+ 	return media_device_register(&camss->media_dev);
+ }
+ 
++static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
++	.bound = camss_subdev_notifier_bound,
++	.complete = camss_subdev_notifier_complete,
++};
++
+ static const struct media_device_ops camss_media_ops = {
+ 	.link_notify = v4l2_pipeline_link_notify,
+ };
+@@ -655,8 +660,7 @@ static int camss_probe(struct platform_device *pdev)
+ 		goto err_register_entities;
+ 
+ 	if (camss->notifier.num_subdevs) {
+-		camss->notifier.bound = camss_subdev_notifier_bound;
+-		camss->notifier.complete = camss_subdev_notifier_complete;
++		camss->notifier.ops = &camss_subdev_notifier_ops;
+ 
+ 		ret = v4l2_async_notifier_register(&camss->v4l2_dev,
+ 						   &camss->notifier);
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 380288658601..108d776f3265 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -134,6 +134,12 @@ static int rvin_digital_notify_bound(struct v4l2_async_notifier *notifier,
+ 
+ 	return 0;
+ }
++static const struct v4l2_async_notifier_operations rvin_digital_notify_ops = {
++	.bound = rvin_digital_notify_bound,
++	.unbind = rvin_digital_notify_unbind,
++	.complete = rvin_digital_notify_complete,
++};
++
+ 
+ static int rvin_digital_parse_v4l2(struct device *dev,
+ 				   struct v4l2_fwnode_endpoint *vep,
+@@ -183,9 +189,7 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 	vin_dbg(vin, "Found digital subdevice %pOF\n",
+ 		to_of_node(vin->digital->asd.match.fwnode.fwnode));
+ 
+-	vin->notifier.bound = rvin_digital_notify_bound;
+-	vin->notifier.unbind = rvin_digital_notify_unbind;
+-	vin->notifier.complete = rvin_digital_notify_complete;
++	vin->notifier.ops = &rvin_digital_notify_ops;
+ 	ret = v4l2_async_notifier_register(&vin->v4l2_dev, &vin->notifier);
+ 	if (ret < 0) {
+ 		vin_err(vin, "Notifier registration failed\n");
+diff --git a/drivers/media/platform/rcar_drif.c b/drivers/media/platform/rcar_drif.c
+index 522364ff0d5d..0b2214d6d621 100644
+--- a/drivers/media/platform/rcar_drif.c
++++ b/drivers/media/platform/rcar_drif.c
+@@ -1185,6 +1185,12 @@ static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
+ 	return ret;
+ }
+ 
++static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = {
++	.bound = rcar_drif_notify_bound,
++	.unbind = rcar_drif_notify_unbind,
++	.complete = rcar_drif_notify_complete,
++};
++
+ /* Read endpoint properties */
+ static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
+ 					struct fwnode_handle *fwnode)
+@@ -1347,9 +1353,7 @@ static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
+ 	if (ret)
+ 		goto error;
+ 
+-	sdr->notifier.bound = rcar_drif_notify_bound;
+-	sdr->notifier.unbind = rcar_drif_notify_unbind;
+-	sdr->notifier.complete = rcar_drif_notify_complete;
++	sdr->notifier.ops = &rcar_drif_notify_ops;
+ 
+ 	/* Register notifier */
+ 	ret = v4l2_async_notifier_register(&sdr->v4l2_dev, &sdr->notifier);
+diff --git a/drivers/media/platform/soc_camera/soc_camera.c b/drivers/media/platform/soc_camera/soc_camera.c
+index 1f3c450c7a69..916ff68b73d4 100644
+--- a/drivers/media/platform/soc_camera/soc_camera.c
++++ b/drivers/media/platform/soc_camera/soc_camera.c
+@@ -1391,6 +1391,12 @@ static int soc_camera_async_complete(struct v4l2_async_notifier *notifier)
+ 	return 0;
+ }
+ 
++static const struct v4l2_async_notifier_operations soc_camera_async_ops = {
++	.bound = soc_camera_async_bound,
++	.unbind = soc_camera_async_unbind,
++	.complete = soc_camera_async_complete,
++};
++
+ static int scan_async_group(struct soc_camera_host *ici,
+ 			    struct v4l2_async_subdev **asd, unsigned int size)
+ {
+@@ -1437,9 +1443,7 @@ static int scan_async_group(struct soc_camera_host *ici,
+ 
+ 	sasc->notifier.subdevs = asd;
+ 	sasc->notifier.num_subdevs = size;
+-	sasc->notifier.bound = soc_camera_async_bound;
+-	sasc->notifier.unbind = soc_camera_async_unbind;
+-	sasc->notifier.complete = soc_camera_async_complete;
++	sasc->notifier.ops = &soc_camera_async_ops;
+ 
+ 	icd->sasc = sasc;
+ 	icd->parent = ici->v4l2_dev.dev;
+@@ -1537,9 +1541,7 @@ static int soc_of_bind(struct soc_camera_host *ici,
+ 
+ 	sasc->notifier.subdevs = &info->subdev;
+ 	sasc->notifier.num_subdevs = 1;
+-	sasc->notifier.bound = soc_camera_async_bound;
+-	sasc->notifier.unbind = soc_camera_async_unbind;
+-	sasc->notifier.complete = soc_camera_async_complete;
++	sasc->notifier.ops = &soc_camera_async_ops;
+ 
+ 	icd->sasc = sasc;
+ 	icd->parent = ici->v4l2_dev.dev;
+diff --git a/drivers/media/platform/stm32/stm32-dcmi.c b/drivers/media/platform/stm32/stm32-dcmi.c
+index 35ba6f211b79..ac4c450a6c7d 100644
+--- a/drivers/media/platform/stm32/stm32-dcmi.c
++++ b/drivers/media/platform/stm32/stm32-dcmi.c
+@@ -1495,6 +1495,12 @@ static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier,
+ 	return 0;
+ }
+ 
++static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = {
++	.bound = dcmi_graph_notify_bound,
++	.unbind = dcmi_graph_notify_unbind,
++	.complete = dcmi_graph_notify_complete,
++};
++
+ static int dcmi_graph_parse(struct stm32_dcmi *dcmi, struct device_node *node)
+ {
+ 	struct device_node *ep = NULL;
+@@ -1542,9 +1548,7 @@ static int dcmi_graph_init(struct stm32_dcmi *dcmi)
+ 
+ 	dcmi->notifier.subdevs = subdevs;
+ 	dcmi->notifier.num_subdevs = 1;
+-	dcmi->notifier.bound = dcmi_graph_notify_bound;
+-	dcmi->notifier.unbind = dcmi_graph_notify_unbind;
+-	dcmi->notifier.complete = dcmi_graph_notify_complete;
++	dcmi->notifier.ops = &dcmi_graph_notify_ops;
+ 
+ 	ret = v4l2_async_notifier_register(&dcmi->v4l2_dev, &dcmi->notifier);
+ 	if (ret < 0) {
+diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
+index 42e383a48ffe..8b586c864524 100644
+--- a/drivers/media/platform/ti-vpe/cal.c
++++ b/drivers/media/platform/ti-vpe/cal.c
+@@ -1522,6 +1522,11 @@ static int cal_async_complete(struct v4l2_async_notifier *notifier)
+ 	return 0;
+ }
+ 
++static const struct v4l2_async_notifier_operations cal_async_ops = {
++	.bound = cal_async_bound,
++	.complete = cal_async_complete,
++};
++
+ static int cal_complete_ctx(struct cal_ctx *ctx)
+ {
+ 	struct video_device *vfd;
+@@ -1736,8 +1741,7 @@ static int of_cal_create_instance(struct cal_ctx *ctx, int inst)
+ 	ctx->asd_list[0] = asd;
+ 	ctx->notifier.subdevs = ctx->asd_list;
+ 	ctx->notifier.num_subdevs = 1;
+-	ctx->notifier.bound = cal_async_bound;
+-	ctx->notifier.complete = cal_async_complete;
++	ctx->notifier.ops = &cal_async_ops;
+ 	ret = v4l2_async_notifier_register(&ctx->v4l2_dev,
+ 					   &ctx->notifier);
+ 	if (ret) {
+diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c b/drivers/media/platform/xilinx/xilinx-vipp.c
+index ebfdf334d99c..d881cf09876d 100644
+--- a/drivers/media/platform/xilinx/xilinx-vipp.c
++++ b/drivers/media/platform/xilinx/xilinx-vipp.c
+@@ -351,6 +351,11 @@ static int xvip_graph_notify_bound(struct v4l2_async_notifier *notifier,
+ 	return -EINVAL;
+ }
+ 
++static const struct v4l2_async_notifier_operations xvip_graph_notify_ops = {
++	.bound = xvip_graph_notify_bound,
++	.complete = xvip_graph_notify_complete,
++};
++
+ static int xvip_graph_parse_one(struct xvip_composite_device *xdev,
+ 				struct device_node *node)
+ {
+@@ -548,8 +553,7 @@ static int xvip_graph_init(struct xvip_composite_device *xdev)
+ 
+ 	xdev->notifier.subdevs = subdevs;
+ 	xdev->notifier.num_subdevs = num_subdevs;
+-	xdev->notifier.bound = xvip_graph_notify_bound;
+-	xdev->notifier.complete = xvip_graph_notify_complete;
++	xdev->notifier.ops = &xvip_graph_notify_ops;
+ 
+ 	ret = v4l2_async_notifier_register(&xdev->v4l2_dev, &xdev->notifier);
+ 	if (ret < 0) {
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 46aebfc75e43..9d6fc5f25619 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -102,16 +102,16 @@ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ {
+ 	int ret;
+ 
+-	if (notifier->bound) {
+-		ret = notifier->bound(notifier, sd, asd);
++	if (notifier->ops->bound) {
++		ret = notifier->ops->bound(notifier, sd, asd);
+ 		if (ret < 0)
+ 			return ret;
+ 	}
+ 
+ 	ret = v4l2_device_register_subdev(notifier->v4l2_dev, sd);
+ 	if (ret < 0) {
+-		if (notifier->unbind)
+-			notifier->unbind(notifier, sd, asd);
++		if (notifier->ops->unbind)
++			notifier->ops->unbind(notifier, sd, asd);
+ 		return ret;
+ 	}
+ 
+@@ -140,9 +140,8 @@ static void v4l2_async_notifier_unbind_all_subdevs(
+ 	struct v4l2_subdev *sd, *tmp;
+ 
+ 	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
+-		if (notifier->unbind)
+-			notifier->unbind(notifier, sd, sd->asd);
+-
++		if (notifier->ops->unbind)
++			notifier->ops->unbind(notifier, sd, sd->asd);
+ 		v4l2_async_cleanup(sd);
+ 
+ 		list_move(&sd->async_list, &subdev_list);
+@@ -199,8 +198,8 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 		}
+ 	}
+ 
+-	if (list_empty(&notifier->waiting) && notifier->complete) {
+-		ret = notifier->complete(notifier);
++	if (list_empty(&notifier->waiting) && notifier->ops->complete) {
++		ret = notifier->ops->complete(notifier);
+ 		if (ret)
+ 			goto err_complete;
+ 	}
+@@ -297,10 +296,10 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 		if (ret)
+ 			goto err_unlock;
+ 
+-		if (!list_empty(&notifier->waiting) || !notifier->complete)
++		if (!list_empty(&notifier->waiting) || !notifier->ops->complete)
+ 			goto out_unlock;
+ 
+-		ret = notifier->complete(notifier);
++		ret = notifier->ops->complete(notifier);
+ 		if (ret)
+ 			goto err_cleanup;
+ 
+@@ -316,9 +315,8 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 	return 0;
+ 
+ err_cleanup:
+-	if (notifier->unbind)
+-		notifier->unbind(notifier, sd, sd->asd);
+-
++	if (notifier->ops->unbind)
++		notifier->ops->unbind(notifier, sd, sd->asd);
+ 	v4l2_async_cleanup(sd);
+ 
+ err_unlock:
+@@ -337,8 +335,8 @@ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd)
+ 
+ 		list_add(&sd->asd->list, &notifier->waiting);
+ 
+-		if (notifier->unbind)
+-			notifier->unbind(notifier, sd, sd->asd);
++		if (notifier->ops->unbind)
++			notifier->ops->unbind(notifier, sd, sd->asd);
+ 	}
+ 
+ 	v4l2_async_cleanup(sd);
+diff --git a/drivers/staging/media/imx/imx-media-dev.c b/drivers/staging/media/imx/imx-media-dev.c
+index b55e5ebba8b4..47c4c954fed5 100644
+--- a/drivers/staging/media/imx/imx-media-dev.c
++++ b/drivers/staging/media/imx/imx-media-dev.c
+@@ -440,6 +440,11 @@ static int imx_media_probe_complete(struct v4l2_async_notifier *notifier)
+ 	return media_device_register(&imxmd->md);
+ }
+ 
++static const struct v4l2_async_notifier_operations imx_media_subdev_ops = {
++	.bound = imx_media_subdev_bound,
++	.complete = imx_media_probe_complete,
++};
++
+ /*
+  * adds controls to a video device from an entity subdevice.
+  * Continues upstream from the entity's sink pads.
+@@ -608,8 +613,7 @@ static int imx_media_probe(struct platform_device *pdev)
+ 
+ 	/* prepare the async subdev notifier and register it */
+ 	imxmd->subdev_notifier.subdevs = imxmd->async_ptrs;
+-	imxmd->subdev_notifier.bound = imx_media_subdev_bound;
+-	imxmd->subdev_notifier.complete = imx_media_probe_complete;
++	imxmd->subdev_notifier.ops = &imx_media_subdev_ops;
+ 	ret = v4l2_async_notifier_register(&imxmd->v4l2_dev,
+ 					   &imxmd->subdev_notifier);
+ 	if (ret) {
+diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h
+index 329aeebd1a80..68606afb5ef9 100644
+--- a/include/media/v4l2-async.h
++++ b/include/media/v4l2-async.h
+@@ -18,6 +18,7 @@ struct device;
+ struct device_node;
+ struct v4l2_device;
+ struct v4l2_subdev;
++struct v4l2_async_notifier;
+ 
+ /* A random max subdevice number, used to allocate an array on stack */
+ #define V4L2_MAX_SUBDEVS 128U
+@@ -78,9 +79,26 @@ struct v4l2_async_subdev {
+ 	struct list_head list;
+ };
+ 
++/**
++ * struct v4l2_async_notifier_operations - Asynchronous V4L2 notifier operations
++ * @bound:	a subdevice driver has successfully probed one of the subdevices
++ * @complete:	all subdevices have been probed successfully
++ * @unbind:	a subdevice is leaving
++ */
++struct v4l2_async_notifier_operations {
++	int (*bound)(struct v4l2_async_notifier *notifier,
++		     struct v4l2_subdev *subdev,
++		     struct v4l2_async_subdev *asd);
++	int (*complete)(struct v4l2_async_notifier *notifier);
++	void (*unbind)(struct v4l2_async_notifier *notifier,
++		       struct v4l2_subdev *subdev,
++		       struct v4l2_async_subdev *asd);
++};
++
+ /**
+  * struct v4l2_async_notifier - v4l2_device notifier data
+  *
++ * @ops:	notifier operations
+  * @num_subdevs: number of subdevices used in the subdevs array
+  * @max_subdevs: number of subdevices allocated in the subdevs array
+  * @subdevs:	array of pointers to subdevice descriptors
+@@ -88,11 +106,9 @@ struct v4l2_async_subdev {
+  * @waiting:	list of struct v4l2_async_subdev, waiting for their drivers
+  * @done:	list of struct v4l2_subdev, already probed
+  * @list:	member in a global list of notifiers
+- * @bound:	a subdevice driver has successfully probed one of subdevices
+- * @complete:	all subdevices have been probed successfully
+- * @unbind:	a subdevice is leaving
+  */
+ struct v4l2_async_notifier {
++	const struct v4l2_async_notifier_operations *ops;
+ 	unsigned int num_subdevs;
+ 	unsigned int max_subdevs;
+ 	struct v4l2_async_subdev **subdevs;
+@@ -100,13 +116,6 @@ struct v4l2_async_notifier {
+ 	struct list_head waiting;
+ 	struct list_head done;
+ 	struct list_head list;
+-	int (*bound)(struct v4l2_async_notifier *notifier,
+-		     struct v4l2_subdev *subdev,
+-		     struct v4l2_async_subdev *asd);
+-	int (*complete)(struct v4l2_async_notifier *notifier);
+-	void (*unbind)(struct v4l2_async_notifier *notifier,
+-		       struct v4l2_subdev *subdev,
+-		       struct v4l2_async_subdev *asd);
+ };
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/0292-media-v4l-async-Introduce-helpers-for-calling-async-.patch b/patches/0292-media-v4l-async-Introduce-helpers-for-calling-async-.patch
new file mode 100644
index 00000000000000..547578fc7c3826
--- /dev/null
+++ b/patches/0292-media-v4l-async-Introduce-helpers-for-calling-async-.patch
@@ -0,0 +1,143 @@
+From d9756f22830290044e522ddeff4d5ad9f92b7d50 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Fri, 1 Sep 2017 08:27:32 -0400
+Subject: [PATCH 0292/1795] media: v4l: async: Introduce helpers for calling
+ async ops callbacks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add three helper functions to call async operations callbacks. Besides
+simplifying callbacks, this allows async notifiers to have no ops set,
+i.e. it can be left NULL.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Pavel Machek <pavel@ucw.cz>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit ddddc18b219ada692704c5467d16fff8c79cf287)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 56 +++++++++++++++++++---------
+ 1 file changed, 39 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 9d6fc5f25619..e170682dae78 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -25,6 +25,34 @@
+ #include <media/v4l2-fwnode.h>
+ #include <media/v4l2-subdev.h>
+ 
++static int v4l2_async_notifier_call_bound(struct v4l2_async_notifier *n,
++					  struct v4l2_subdev *subdev,
++					  struct v4l2_async_subdev *asd)
++{
++	if (!n->ops || !n->ops->bound)
++		return 0;
++
++	return n->ops->bound(n, subdev, asd);
++}
++
++static void v4l2_async_notifier_call_unbind(struct v4l2_async_notifier *n,
++					    struct v4l2_subdev *subdev,
++					    struct v4l2_async_subdev *asd)
++{
++	if (!n->ops || !n->ops->unbind)
++		return;
++
++	n->ops->unbind(n, subdev, asd);
++}
++
++static int v4l2_async_notifier_call_complete(struct v4l2_async_notifier *n)
++{
++	if (!n->ops || !n->ops->complete)
++		return 0;
++
++	return n->ops->complete(n);
++}
++
+ static bool match_i2c(struct v4l2_subdev *sd, struct v4l2_async_subdev *asd)
+ {
+ #if IS_ENABLED(CONFIG_I2C)
+@@ -102,16 +130,13 @@ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ {
+ 	int ret;
+ 
+-	if (notifier->ops->bound) {
+-		ret = notifier->ops->bound(notifier, sd, asd);
+-		if (ret < 0)
+-			return ret;
+-	}
++	ret = v4l2_async_notifier_call_bound(notifier, sd, asd);
++	if (ret < 0)
++		return ret;
+ 
+ 	ret = v4l2_device_register_subdev(notifier->v4l2_dev, sd);
+ 	if (ret < 0) {
+-		if (notifier->ops->unbind)
+-			notifier->ops->unbind(notifier, sd, asd);
++		v4l2_async_notifier_call_unbind(notifier, sd, asd);
+ 		return ret;
+ 	}
+ 
+@@ -140,8 +165,7 @@ static void v4l2_async_notifier_unbind_all_subdevs(
+ 	struct v4l2_subdev *sd, *tmp;
+ 
+ 	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
+-		if (notifier->ops->unbind)
+-			notifier->ops->unbind(notifier, sd, sd->asd);
++		v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
+ 		v4l2_async_cleanup(sd);
+ 
+ 		list_move(&sd->async_list, &subdev_list);
+@@ -198,8 +222,8 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 		}
+ 	}
+ 
+-	if (list_empty(&notifier->waiting) && notifier->ops->complete) {
+-		ret = notifier->ops->complete(notifier);
++	if (list_empty(&notifier->waiting)) {
++		ret = v4l2_async_notifier_call_complete(notifier);
+ 		if (ret)
+ 			goto err_complete;
+ 	}
+@@ -296,10 +320,10 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 		if (ret)
+ 			goto err_unlock;
+ 
+-		if (!list_empty(&notifier->waiting) || !notifier->ops->complete)
++		if (!list_empty(&notifier->waiting))
+ 			goto out_unlock;
+ 
+-		ret = notifier->ops->complete(notifier);
++		ret = v4l2_async_notifier_call_complete(notifier);
+ 		if (ret)
+ 			goto err_cleanup;
+ 
+@@ -315,8 +339,7 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 	return 0;
+ 
+ err_cleanup:
+-	if (notifier->ops->unbind)
+-		notifier->ops->unbind(notifier, sd, sd->asd);
++	v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
+ 	v4l2_async_cleanup(sd);
+ 
+ err_unlock:
+@@ -335,8 +358,7 @@ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd)
+ 
+ 		list_add(&sd->asd->list, &notifier->waiting);
+ 
+-		if (notifier->ops->unbind)
+-			notifier->ops->unbind(notifier, sd, sd->asd);
++		v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
+ 	}
+ 
+ 	v4l2_async_cleanup(sd);
+-- 
+2.19.0
+
diff --git a/patches/0293-media-v4l-async-Register-sub-devices-before-calling-.patch b/patches/0293-media-v4l-async-Register-sub-devices-before-calling-.patch
new file mode 100644
index 00000000000000..b3dfd55f0e9d4f
--- /dev/null
+++ b/patches/0293-media-v4l-async-Register-sub-devices-before-calling-.patch
@@ -0,0 +1,51 @@
+From 2cc4c9fbfa694282fdc7ad1d3f3b80ebdf0fc9b8 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Mon, 17 Jul 2017 10:04:20 -0400
+Subject: [PATCH 0293/1795] media: v4l: async: Register sub-devices before
+ calling bound callback
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Register the sub-device before calling the notifier's bound callback.
+Doing this the other way around is problematic as the struct v4l2_device
+has not assigned for the sub-device yet and may be required by the bound
+callback.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Pavel Machek <pavel@ucw.cz>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 24def9b586349ec1ecea7989fc219e688d1d1e74)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index e170682dae78..46db85685894 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -130,13 +130,13 @@ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ {
+ 	int ret;
+ 
+-	ret = v4l2_async_notifier_call_bound(notifier, sd, asd);
++	ret = v4l2_device_register_subdev(notifier->v4l2_dev, sd);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ret = v4l2_device_register_subdev(notifier->v4l2_dev, sd);
++	ret = v4l2_async_notifier_call_bound(notifier, sd, asd);
+ 	if (ret < 0) {
+-		v4l2_async_notifier_call_unbind(notifier, sd, asd);
++		v4l2_device_unregister_subdev(sd);
+ 		return ret;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0294-media-v4l-async-Allow-async-notifier-register-call-s.patch b/patches/0294-media-v4l-async-Allow-async-notifier-register-call-s.patch
new file mode 100644
index 00000000000000..6ac71c2a4044ef
--- /dev/null
+++ b/patches/0294-media-v4l-async-Allow-async-notifier-register-call-s.patch
@@ -0,0 +1,66 @@
+From ed4ee829e5416cb26456b7ff6730da2a9a4bb8b2 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Wed, 6 Sep 2017 10:48:33 -0400
+Subject: [PATCH 0294/1795] media: v4l: async: Allow async notifier register
+ call succeed with no subdevs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The information on how many async sub-devices would be bindable to a
+notifier is typically dependent on information from platform firmware and
+it's not driver's business to be aware of that.
+
+Many V4L2 main drivers are perfectly usable (and useful) without async
+sub-devices and so if there aren't any around, just proceed call the
+notifier's complete callback immediately without registering the notifier
+itself.
+
+If a driver needs to check whether there are async sub-devices available,
+it can be done by inspecting the notifier's num_subdevs field which tells
+the number of async sub-devices.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 479bc5a8c662e9d9de47e95ee26ebaf15f36a771)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 46db85685894..1b536d68cedf 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -180,14 +180,22 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 	int ret;
+ 	int i;
+ 
+-	if (!v4l2_dev || !notifier->num_subdevs ||
+-	    notifier->num_subdevs > V4L2_MAX_SUBDEVS)
++	if (!v4l2_dev || notifier->num_subdevs > V4L2_MAX_SUBDEVS)
+ 		return -EINVAL;
+ 
+ 	notifier->v4l2_dev = v4l2_dev;
+ 	INIT_LIST_HEAD(&notifier->waiting);
+ 	INIT_LIST_HEAD(&notifier->done);
+ 
++	if (!notifier->num_subdevs) {
++		int ret;
++
++		ret = v4l2_async_notifier_call_complete(notifier);
++		notifier->v4l2_dev = NULL;
++
++		return ret;
++	}
++
+ 	for (i = 0; i < notifier->num_subdevs; i++) {
+ 		asd = notifier->subdevs[i];
+ 
+-- 
+2.19.0
+
diff --git a/patches/0295-media-v4l-async-Prepare-for-async-sub-device-notifie.patch b/patches/0295-media-v4l-async-Prepare-for-async-sub-device-notifie.patch
new file mode 100644
index 00000000000000..36de84bfe69dad
--- /dev/null
+++ b/patches/0295-media-v4l-async-Prepare-for-async-sub-device-notifie.patch
@@ -0,0 +1,156 @@
+From b3f644d737be449ef694f03816217b72787a08e2 Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Sun, 24 Sep 2017 20:48:08 -0400
+Subject: [PATCH 0295/1795] media: v4l: async: Prepare for async sub-device
+ notifiers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Refactor the V4L2 async framework a little in preparation for async
+sub-device notifiers. This avoids making some structural changes in the
+patch actually implementing sub-device notifiers, making that patch easier
+to review.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a3620cb48d303f07160694c00d9c1c8f0ea96690)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 69 ++++++++++++++++++++--------
+ 1 file changed, 50 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 1b536d68cedf..6265717769d2 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -125,12 +125,13 @@ static struct v4l2_async_subdev *v4l2_async_find_match(
+ }
+ 
+ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
++				   struct v4l2_device *v4l2_dev,
+ 				   struct v4l2_subdev *sd,
+ 				   struct v4l2_async_subdev *asd)
+ {
+ 	int ret;
+ 
+-	ret = v4l2_device_register_subdev(notifier->v4l2_dev, sd);
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -151,6 +152,29 @@ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ 	return 0;
+ }
+ 
++/* Test all async sub-devices in a notifier for a match. */
++static int v4l2_async_notifier_try_all_subdevs(
++	struct v4l2_async_notifier *notifier)
++{
++	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
++	struct v4l2_subdev *sd, *tmp;
++
++	list_for_each_entry_safe(sd, tmp, &subdev_list, async_list) {
++		struct v4l2_async_subdev *asd;
++		int ret;
++
++		asd = v4l2_async_find_match(notifier, sd);
++		if (!asd)
++			continue;
++
++		ret = v4l2_async_match_notify(notifier, v4l2_dev, sd, asd);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
+ static void v4l2_async_cleanup(struct v4l2_subdev *sd)
+ {
+ 	v4l2_device_unregister_subdev(sd);
+@@ -172,18 +196,15 @@ static void v4l2_async_notifier_unbind_all_subdevs(
+ 	}
+ }
+ 
+-int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+-				 struct v4l2_async_notifier *notifier)
++static int __v4l2_async_notifier_register(struct v4l2_async_notifier *notifier)
+ {
+-	struct v4l2_subdev *sd, *tmp;
+ 	struct v4l2_async_subdev *asd;
+ 	int ret;
+ 	int i;
+ 
+-	if (!v4l2_dev || notifier->num_subdevs > V4L2_MAX_SUBDEVS)
++	if (notifier->num_subdevs > V4L2_MAX_SUBDEVS)
+ 		return -EINVAL;
+ 
+-	notifier->v4l2_dev = v4l2_dev;
+ 	INIT_LIST_HEAD(&notifier->waiting);
+ 	INIT_LIST_HEAD(&notifier->done);
+ 
+@@ -216,18 +237,10 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 
+ 	mutex_lock(&list_lock);
+ 
+-	list_for_each_entry_safe(sd, tmp, &subdev_list, async_list) {
+-		int ret;
+-
+-		asd = v4l2_async_find_match(notifier, sd);
+-		if (!asd)
+-			continue;
+-
+-		ret = v4l2_async_match_notify(notifier, sd, asd);
+-		if (ret < 0) {
+-			mutex_unlock(&list_lock);
+-			return ret;
+-		}
++	ret = v4l2_async_notifier_try_all_subdevs(notifier);
++	if (ret) {
++		mutex_unlock(&list_lock);
++		return ret;
+ 	}
+ 
+ 	if (list_empty(&notifier->waiting)) {
+@@ -250,6 +263,23 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 
+ 	return ret;
+ }
++
++int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
++				 struct v4l2_async_notifier *notifier)
++{
++	int ret;
++
++	if (WARN_ON(!v4l2_dev))
++		return -EINVAL;
++
++	notifier->v4l2_dev = v4l2_dev;
++
++	ret = __v4l2_async_notifier_register(notifier);
++	if (ret)
++		notifier->v4l2_dev = NULL;
++
++	return ret;
++}
+ EXPORT_SYMBOL(v4l2_async_notifier_register);
+ 
+ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+@@ -324,7 +354,8 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 		if (!asd)
+ 			continue;
+ 
+-		ret = v4l2_async_match_notify(notifier, sd, asd);
++		ret = v4l2_async_match_notify(notifier, notifier->v4l2_dev, sd,
++					      asd);
+ 		if (ret)
+ 			goto err_unlock;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0296-media-v4l-async-Allow-binding-notifiers-to-sub-devic.patch b/patches/0296-media-v4l-async-Allow-binding-notifiers-to-sub-devic.patch
new file mode 100644
index 00000000000000..3a7806ce5bdb91
--- /dev/null
+++ b/patches/0296-media-v4l-async-Allow-binding-notifiers-to-sub-devic.patch
@@ -0,0 +1,439 @@
+From 25d47861b6734a88db8b319306abc3c44b776b5b Mon Sep 17 00:00:00 2001
+From: Sakari Ailus <sakari.ailus@linux.intel.com>
+Date: Sun, 24 Sep 2017 20:54:31 -0400
+Subject: [PATCH 0296/1795] media: v4l: async: Allow binding notifiers to
+ sub-devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Registering a notifier has required the knowledge of struct v4l2_device
+for the reason that sub-devices generally are registered to the
+v4l2_device (as well as the media device, also available through
+v4l2_device).
+
+This information is not available for sub-device drivers at probe time.
+
+What this patch does is that it allows registering notifiers without
+having v4l2_device around. Instead the sub-device pointer is stored in the
+notifier. Once the sub-device of the driver that registered the notifier
+is registered, the notifier will gain the knowledge of the v4l2_device,
+and the binding of async sub-devices from the sub-device driver's notifier
+may proceed.
+
+The complete callback of the root notifier will be called only when the
+v4l2_device is available and no notifier has pending sub-devices to bind.
+No complete callbacks are supported for sub-device notifiers.
+
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 2cab00bb076b9f0e8442e3d72425843d2b441143)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-async.c | 212 ++++++++++++++++++++++-----
+ include/media/v4l2-async.h           |  19 ++-
+ 2 files changed, 189 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c
+index 6265717769d2..ed539c4fd5dc 100644
+--- a/drivers/media/v4l2-core/v4l2-async.c
++++ b/drivers/media/v4l2-core/v4l2-async.c
+@@ -124,11 +124,87 @@ static struct v4l2_async_subdev *v4l2_async_find_match(
+ 	return NULL;
+ }
+ 
++/* Find the sub-device notifier registered by a sub-device driver. */
++static struct v4l2_async_notifier *v4l2_async_find_subdev_notifier(
++	struct v4l2_subdev *sd)
++{
++	struct v4l2_async_notifier *n;
++
++	list_for_each_entry(n, &notifier_list, list)
++		if (n->sd == sd)
++			return n;
++
++	return NULL;
++}
++
++/* Get v4l2_device related to the notifier if one can be found. */
++static struct v4l2_device *v4l2_async_notifier_find_v4l2_dev(
++	struct v4l2_async_notifier *notifier)
++{
++	while (notifier->parent)
++		notifier = notifier->parent;
++
++	return notifier->v4l2_dev;
++}
++
++/*
++ * Return true if all child sub-device notifiers are complete, false otherwise.
++ */
++static bool v4l2_async_notifier_can_complete(
++	struct v4l2_async_notifier *notifier)
++{
++	struct v4l2_subdev *sd;
++
++	if (!list_empty(&notifier->waiting))
++		return false;
++
++	list_for_each_entry(sd, &notifier->done, async_list) {
++		struct v4l2_async_notifier *subdev_notifier =
++			v4l2_async_find_subdev_notifier(sd);
++
++		if (subdev_notifier &&
++		    !v4l2_async_notifier_can_complete(subdev_notifier))
++			return false;
++	}
++
++	return true;
++}
++
++/*
++ * Complete the master notifier if possible. This is done when all async
++ * sub-devices have been bound; v4l2_device is also available then.
++ */
++static int v4l2_async_notifier_try_complete(
++	struct v4l2_async_notifier *notifier)
++{
++	/* Quick check whether there are still more sub-devices here. */
++	if (!list_empty(&notifier->waiting))
++		return 0;
++
++	/* Check the entire notifier tree; find the root notifier first. */
++	while (notifier->parent)
++		notifier = notifier->parent;
++
++	/* This is root if it has v4l2_dev. */
++	if (!notifier->v4l2_dev)
++		return 0;
++
++	/* Is everything ready? */
++	if (!v4l2_async_notifier_can_complete(notifier))
++		return 0;
++
++	return v4l2_async_notifier_call_complete(notifier);
++}
++
++static int v4l2_async_notifier_try_all_subdevs(
++	struct v4l2_async_notifier *notifier);
++
+ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ 				   struct v4l2_device *v4l2_dev,
+ 				   struct v4l2_subdev *sd,
+ 				   struct v4l2_async_subdev *asd)
+ {
++	struct v4l2_async_notifier *subdev_notifier;
+ 	int ret;
+ 
+ 	ret = v4l2_device_register_subdev(v4l2_dev, sd);
+@@ -149,17 +225,36 @@ static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier,
+ 	/* Move from the global subdevice list to notifier's done */
+ 	list_move(&sd->async_list, &notifier->done);
+ 
+-	return 0;
++	/*
++	 * See if the sub-device has a notifier. If not, return here.
++	 */
++	subdev_notifier = v4l2_async_find_subdev_notifier(sd);
++	if (!subdev_notifier || subdev_notifier->parent)
++		return 0;
++
++	/*
++	 * Proceed with checking for the sub-device notifier's async
++	 * sub-devices, and return the result. The error will be handled by the
++	 * caller.
++	 */
++	subdev_notifier->parent = notifier;
++
++	return v4l2_async_notifier_try_all_subdevs(subdev_notifier);
+ }
+ 
+ /* Test all async sub-devices in a notifier for a match. */
+ static int v4l2_async_notifier_try_all_subdevs(
+ 	struct v4l2_async_notifier *notifier)
+ {
+-	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
+-	struct v4l2_subdev *sd, *tmp;
++	struct v4l2_device *v4l2_dev =
++		v4l2_async_notifier_find_v4l2_dev(notifier);
++	struct v4l2_subdev *sd;
++
++	if (!v4l2_dev)
++		return 0;
+ 
+-	list_for_each_entry_safe(sd, tmp, &subdev_list, async_list) {
++again:
++	list_for_each_entry(sd, &subdev_list, async_list) {
+ 		struct v4l2_async_subdev *asd;
+ 		int ret;
+ 
+@@ -170,6 +265,14 @@ static int v4l2_async_notifier_try_all_subdevs(
+ 		ret = v4l2_async_match_notify(notifier, v4l2_dev, sd, asd);
+ 		if (ret < 0)
+ 			return ret;
++
++		/*
++		 * v4l2_async_match_notify() may lead to registering a
++		 * new notifier and thus changing the async subdevs
++		 * list. In order to proceed safely from here, restart
++		 * parsing the list from the beginning.
++		 */
++		goto again;
+ 	}
+ 
+ 	return 0;
+@@ -183,17 +286,26 @@ static void v4l2_async_cleanup(struct v4l2_subdev *sd)
+ 	sd->asd = NULL;
+ }
+ 
++/* Unbind all sub-devices in the notifier tree. */
+ static void v4l2_async_notifier_unbind_all_subdevs(
+ 	struct v4l2_async_notifier *notifier)
+ {
+ 	struct v4l2_subdev *sd, *tmp;
+ 
+ 	list_for_each_entry_safe(sd, tmp, &notifier->done, async_list) {
++		struct v4l2_async_notifier *subdev_notifier =
++			v4l2_async_find_subdev_notifier(sd);
++
++		if (subdev_notifier)
++			v4l2_async_notifier_unbind_all_subdevs(subdev_notifier);
++
+ 		v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
+ 		v4l2_async_cleanup(sd);
+ 
+ 		list_move(&sd->async_list, &subdev_list);
+ 	}
++
++	notifier->parent = NULL;
+ }
+ 
+ static int __v4l2_async_notifier_register(struct v4l2_async_notifier *notifier)
+@@ -208,15 +320,6 @@ static int __v4l2_async_notifier_register(struct v4l2_async_notifier *notifier)
+ 	INIT_LIST_HEAD(&notifier->waiting);
+ 	INIT_LIST_HEAD(&notifier->done);
+ 
+-	if (!notifier->num_subdevs) {
+-		int ret;
+-
+-		ret = v4l2_async_notifier_call_complete(notifier);
+-		notifier->v4l2_dev = NULL;
+-
+-		return ret;
+-	}
+-
+ 	for (i = 0; i < notifier->num_subdevs; i++) {
+ 		asd = notifier->subdevs[i];
+ 
+@@ -238,16 +341,12 @@ static int __v4l2_async_notifier_register(struct v4l2_async_notifier *notifier)
+ 	mutex_lock(&list_lock);
+ 
+ 	ret = v4l2_async_notifier_try_all_subdevs(notifier);
+-	if (ret) {
+-		mutex_unlock(&list_lock);
+-		return ret;
+-	}
++	if (ret)
++		goto err_unbind;
+ 
+-	if (list_empty(&notifier->waiting)) {
+-		ret = v4l2_async_notifier_call_complete(notifier);
+-		if (ret)
+-			goto err_complete;
+-	}
++	ret = v4l2_async_notifier_try_complete(notifier);
++	if (ret)
++		goto err_unbind;
+ 
+ 	/* Keep also completed notifiers on the list */
+ 	list_add(&notifier->list, &notifier_list);
+@@ -256,7 +355,10 @@ static int __v4l2_async_notifier_register(struct v4l2_async_notifier *notifier)
+ 
+ 	return 0;
+ 
+-err_complete:
++err_unbind:
++	/*
++	 * On failure, unbind all sub-devices registered through this notifier.
++	 */
+ 	v4l2_async_notifier_unbind_all_subdevs(notifier);
+ 
+ 	mutex_unlock(&list_lock);
+@@ -269,7 +371,7 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ {
+ 	int ret;
+ 
+-	if (WARN_ON(!v4l2_dev))
++	if (WARN_ON(!v4l2_dev || notifier->sd))
+ 		return -EINVAL;
+ 
+ 	notifier->v4l2_dev = v4l2_dev;
+@@ -282,20 +384,39 @@ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ }
+ EXPORT_SYMBOL(v4l2_async_notifier_register);
+ 
++int v4l2_async_subdev_notifier_register(struct v4l2_subdev *sd,
++					struct v4l2_async_notifier *notifier)
++{
++	int ret;
++
++	if (WARN_ON(!sd || notifier->v4l2_dev))
++		return -EINVAL;
++
++	notifier->sd = sd;
++
++	ret = __v4l2_async_notifier_register(notifier);
++	if (ret)
++		notifier->sd = NULL;
++
++	return ret;
++}
++EXPORT_SYMBOL(v4l2_async_subdev_notifier_register);
++
+ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier)
+ {
+-	if (!notifier->v4l2_dev)
++	if (!notifier->v4l2_dev && !notifier->sd)
+ 		return;
+ 
+ 	mutex_lock(&list_lock);
+ 
+-	list_del(&notifier->list);
+-
+ 	v4l2_async_notifier_unbind_all_subdevs(notifier);
+ 
+-	mutex_unlock(&list_lock);
+-
++	notifier->sd = NULL;
+ 	notifier->v4l2_dev = NULL;
++
++	list_del(&notifier->list);
++
++	mutex_unlock(&list_lock);
+ }
+ EXPORT_SYMBOL(v4l2_async_notifier_unregister);
+ 
+@@ -331,6 +452,7 @@ EXPORT_SYMBOL_GPL(v4l2_async_notifier_cleanup);
+ 
+ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ {
++	struct v4l2_async_notifier *subdev_notifier;
+ 	struct v4l2_async_notifier *notifier;
+ 	int ret;
+ 
+@@ -347,24 +469,26 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 	INIT_LIST_HEAD(&sd->async_list);
+ 
+ 	list_for_each_entry(notifier, &notifier_list, list) {
+-		struct v4l2_async_subdev *asd = v4l2_async_find_match(notifier,
+-								      sd);
++		struct v4l2_device *v4l2_dev =
++			v4l2_async_notifier_find_v4l2_dev(notifier);
++		struct v4l2_async_subdev *asd;
+ 		int ret;
+ 
++		if (!v4l2_dev)
++			continue;
++
++		asd = v4l2_async_find_match(notifier, sd);
+ 		if (!asd)
+ 			continue;
+ 
+ 		ret = v4l2_async_match_notify(notifier, notifier->v4l2_dev, sd,
+ 					      asd);
+ 		if (ret)
+-			goto err_unlock;
+-
+-		if (!list_empty(&notifier->waiting))
+-			goto out_unlock;
++			goto err_unbind;
+ 
+-		ret = v4l2_async_notifier_call_complete(notifier);
++		ret = v4l2_async_notifier_try_complete(notifier);
+ 		if (ret)
+-			goto err_cleanup;
++			goto err_unbind;
+ 
+ 		goto out_unlock;
+ 	}
+@@ -377,11 +501,19 @@ int v4l2_async_register_subdev(struct v4l2_subdev *sd)
+ 
+ 	return 0;
+ 
+-err_cleanup:
+-	v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
++err_unbind:
++	/*
++	 * Complete failed. Unbind the sub-devices bound through registering
++	 * this async sub-device.
++	 */
++	subdev_notifier = v4l2_async_find_subdev_notifier(sd);
++	if (subdev_notifier)
++		v4l2_async_notifier_unbind_all_subdevs(subdev_notifier);
++
++	if (sd->asd)
++		v4l2_async_notifier_call_unbind(notifier, sd, sd->asd);
+ 	v4l2_async_cleanup(sd);
+ 
+-err_unlock:
+ 	mutex_unlock(&list_lock);
+ 
+ 	return ret;
+diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h
+index 68606afb5ef9..17c4ac7c73e8 100644
+--- a/include/media/v4l2-async.h
++++ b/include/media/v4l2-async.h
+@@ -82,7 +82,8 @@ struct v4l2_async_subdev {
+ /**
+  * struct v4l2_async_notifier_operations - Asynchronous V4L2 notifier operations
+  * @bound:	a subdevice driver has successfully probed one of the subdevices
+- * @complete:	all subdevices have been probed successfully
++ * @complete:	All subdevices have been probed successfully. The complete
++ *		callback is only executed for the root notifier.
+  * @unbind:	a subdevice is leaving
+  */
+ struct v4l2_async_notifier_operations {
+@@ -102,7 +103,9 @@ struct v4l2_async_notifier_operations {
+  * @num_subdevs: number of subdevices used in the subdevs array
+  * @max_subdevs: number of subdevices allocated in the subdevs array
+  * @subdevs:	array of pointers to subdevice descriptors
+- * @v4l2_dev:	pointer to struct v4l2_device
++ * @v4l2_dev:	v4l2_device of the root notifier, NULL otherwise
++ * @sd:		sub-device that registered the notifier, NULL otherwise
++ * @parent:	parent notifier
+  * @waiting:	list of struct v4l2_async_subdev, waiting for their drivers
+  * @done:	list of struct v4l2_subdev, already probed
+  * @list:	member in a global list of notifiers
+@@ -113,6 +116,8 @@ struct v4l2_async_notifier {
+ 	unsigned int max_subdevs;
+ 	struct v4l2_async_subdev **subdevs;
+ 	struct v4l2_device *v4l2_dev;
++	struct v4l2_subdev *sd;
++	struct v4l2_async_notifier *parent;
+ 	struct list_head waiting;
+ 	struct list_head done;
+ 	struct list_head list;
+@@ -127,6 +132,16 @@ struct v4l2_async_notifier {
+ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev,
+ 				 struct v4l2_async_notifier *notifier);
+ 
++/**
++ * v4l2_async_subdev_notifier_register - registers a subdevice asynchronous
++ *					 notifier for a sub-device
++ *
++ * @sd: pointer to &struct v4l2_subdev
++ * @notifier: pointer to &struct v4l2_async_notifier
++ */
++int v4l2_async_subdev_notifier_register(struct v4l2_subdev *sd,
++					struct v4l2_async_notifier *notifier);
++
+ /**
+  * v4l2_async_notifier_unregister - unregisters a subdevice asynchronous notifier
+  *
+-- 
+2.19.0
+
diff --git a/patches/0297-PM-Domains-Allow-genpd-users-to-specify-default-acti.patch b/patches/0297-PM-Domains-Allow-genpd-users-to-specify-default-acti.patch
new file mode 100644
index 00000000000000..c195ebb059e84d
--- /dev/null
+++ b/patches/0297-PM-Domains-Allow-genpd-users-to-specify-default-acti.patch
@@ -0,0 +1,72 @@
+From 66bc21cc6151a59df5b3b60592f34750ab4322b0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 7 Nov 2017 13:48:11 +0100
+Subject: [PATCH 0297/1795] PM / Domains: Allow genpd users to specify default
+ active wakeup behavior
+
+It is quite common for PM Domains to require slave devices to be kept
+active during system suspend if they are to be used as wakeup sources.
+To enable this, currently each PM Domain or driver has to provide its
+own gpd_dev_ops.active_wakeup() callback.
+
+Introduce a new flag GENPD_FLAG_ACTIVE_WAKEUP to consolidate this.
+If specified, all slave devices configured as wakeup sources will be
+kept active during system suspend.
+
+PM Domains that need more fine-grained controls, based on the slave
+device, can still provide their own callbacks, as before.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Kevin Hilman <khilman@baylibre.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit 95a20ef6f7e54c6a982715a7d0da2fd81790db28)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/base/power/domain.c | 3 +++
+ include/linux/pm_domain.h   | 7 ++++---
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
+index c276ba1c0a19..5d63c34e0420 100644
+--- a/drivers/base/power/domain.c
++++ b/drivers/base/power/domain.c
+@@ -124,6 +124,7 @@ static const struct genpd_lock_ops genpd_spin_ops = {
+ #define genpd_status_on(genpd)		(genpd->status == GPD_STATE_ACTIVE)
+ #define genpd_is_irq_safe(genpd)	(genpd->flags & GENPD_FLAG_IRQ_SAFE)
+ #define genpd_is_always_on(genpd)	(genpd->flags & GENPD_FLAG_ALWAYS_ON)
++#define genpd_is_active_wakeup(genpd)	(genpd->flags & GENPD_FLAG_ACTIVE_WAKEUP)
+ 
+ static inline bool irq_safe_dev_in_no_sleep_domain(struct device *dev,
+ 		const struct generic_pm_domain *genpd)
+@@ -774,6 +775,8 @@ static bool pm_genpd_present(const struct generic_pm_domain *genpd)
+ static bool genpd_dev_active_wakeup(const struct generic_pm_domain *genpd,
+ 				    struct device *dev)
+ {
++	if (genpd_is_active_wakeup(genpd))
++		return true;
+ 	return GENPD_DEV_CALLBACK(genpd, bool, active_wakeup, dev);
+ }
+ 
+diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
+index 84f423d5633e..a6688efb29ee 100644
+--- a/include/linux/pm_domain.h
++++ b/include/linux/pm_domain.h
+@@ -18,9 +18,10 @@
+ #include <linux/spinlock.h>
+ 
+ /* Defines used for the flags field in the struct generic_pm_domain */
+-#define GENPD_FLAG_PM_CLK	(1U << 0) /* PM domain uses PM clk */
+-#define GENPD_FLAG_IRQ_SAFE	(1U << 1) /* PM domain operates in atomic */
+-#define GENPD_FLAG_ALWAYS_ON	(1U << 2) /* PM domain is always powered on */
++#define GENPD_FLAG_PM_CLK	 (1U << 0) /* PM domain uses PM clk */
++#define GENPD_FLAG_IRQ_SAFE	 (1U << 1) /* PM domain operates in atomic */
++#define GENPD_FLAG_ALWAYS_ON	 (1U << 2) /* PM domain is always powered on */
++#define GENPD_FLAG_ACTIVE_WAKEUP (1U << 3) /* Keep devices active if wakeup */
+ 
+ enum gpd_status {
+ 	GPD_STATE_ACTIVE = 0,	/* PM domain is active */
+-- 
+2.19.0
+
diff --git a/patches/0298-dt-bindings-apmu-Document-r8a7745-support.patch b/patches/0298-dt-bindings-apmu-Document-r8a7745-support.patch
new file mode 100644
index 00000000000000..8c8f21fb2fd49e
--- /dev/null
+++ b/patches/0298-dt-bindings-apmu-Document-r8a7745-support.patch
@@ -0,0 +1,32 @@
+From 3f1118a9e691c6bdf8eb7ed21396261d8bbf35d2 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 22 Aug 2017 14:52:19 +0100
+Subject: [PATCH 0298/1795] dt-bindings: apmu: Document r8a7745 support
+
+Document APMU and SMP enable method for RZ/G1E (also known as
+r8a7745) SoC.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 055fb568157c3a6754228138b3ca51247cb4f466)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/power/renesas,apmu.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
+index af21502e939c..f747f95eee58 100644
+--- a/Documentation/devicetree/bindings/power/renesas,apmu.txt
++++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
+@@ -8,6 +8,7 @@ Required properties:
+ - compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
+ 	      Examples with soctypes are:
+ 		- "renesas,r8a7743-apmu" (RZ/G1M)
++		- "renesas,r8a7745-apmu" (RZ/G1E)
+ 		- "renesas,r8a7790-apmu" (R-Car H2)
+ 		- "renesas,r8a7791-apmu" (R-Car M2-W)
+ 		- "renesas,r8a7792-apmu" (R-Car V2H)
+-- 
+2.19.0
+
diff --git a/patches/0299-ARM-dts-r8a7790-Convert-to-new-CPG-MSSR-bindings.patch b/patches/0299-ARM-dts-r8a7790-Convert-to-new-CPG-MSSR-bindings.patch
new file mode 100644
index 00000000000000..dc85a246dad86d
--- /dev/null
+++ b/patches/0299-ARM-dts-r8a7790-Convert-to-new-CPG-MSSR-bindings.patch
@@ -0,0 +1,1126 @@
+From 1c60909eb8eaadd3ff9a0684a0364f807f1b6aa0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:11:34 +0200
+Subject: [PATCH 0299/1795] ARM: dts: r8a7790: Convert to new CPG/MSSR bindings
+
+Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
+Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
+(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
+Generator / Module Standby and Software Reset" DT bindings.
+
+This simplifies the DTS files, and allows to add support for reset
+control later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5802c420636559ffd37095d2886f6964d9b55b11)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts |   7 +-
+ arch/arm/boot/dts/r8a7790.dtsi      | 557 +++++-----------------------
+ 2 files changed, 99 insertions(+), 465 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index ba100a6f67ca..e3d27783b6b5 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -316,11 +316,8 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+-		 <&mstp7_clks R8A7790_CLK_DU1>,
+-		 <&mstp7_clks R8A7790_CLK_DU2>,
+-		 <&mstp7_clks R8A7790_CLK_LVDS0>,
+-		 <&mstp7_clks R8A7790_CLK_LVDS1>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+ 		 <&x13_clk>, <&x2_clk>;
+ 	clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+ 		      "dclkin.0", "dclkin.1";
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 16358bf8d1db..5a31dfc0c316 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -10,7 +10,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/r8a7790-clock.h>
++#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+@@ -52,7 +52,7 @@
+ 			reg = <0>;
+ 			clock-frequency = <1300000000>;
+ 			voltage-tolerance = <1>; /* 1% */
+-			clocks = <&cpg_clocks R8A7790_CLK_Z>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ 			clock-latency = <300000>; /* 300 us */
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+ 			next-level-cache = <&L2_CA15>;
+@@ -185,7 +185,7 @@
+ 			<0 0xf1004000 0 0x2000>,
+ 			<0 0xf1006000 0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
++		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+@@ -199,7 +199,7 @@
+ 		gpio-ranges = <&pfc 0 0 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
++		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -212,7 +212,7 @@
+ 		gpio-ranges = <&pfc 0 32 30>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
++		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -225,7 +225,7 @@
+ 		gpio-ranges = <&pfc 0 64 30>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
++		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -238,7 +238,7 @@
+ 		gpio-ranges = <&pfc 0 96 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
++		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -251,7 +251,7 @@
+ 		gpio-ranges = <&pfc 0 128 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
++		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -264,7 +264,7 @@
+ 		gpio-ranges = <&pfc 0 160 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
++		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -274,7 +274,7 @@
+ 				"renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
++		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+@@ -292,7 +292,7 @@
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
++		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 
+@@ -312,7 +312,7 @@
+ 			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
++		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 
+@@ -330,7 +330,7 @@
+ 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
++		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -358,7 +358,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
++		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -389,7 +389,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
++		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -418,7 +418,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
++		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -447,7 +447,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
++		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -460,7 +460,7 @@
+ 		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ 			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "ch0", "ch1";
+-		clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
++		clocks = <&cpg CPG_MOD 330>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+@@ -472,7 +472,7 @@
+ 		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ 			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "ch0", "ch1";
+-		clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
++		clocks = <&cpg CPG_MOD 331>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+@@ -484,7 +484,7 @@
+ 		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6508000 0 0x40>;
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
++		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+@@ -496,7 +496,7 @@
+ 		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6518000 0 0x40>;
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
++		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -508,7 +508,7 @@
+ 		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6530000 0 0x40>;
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
++		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -520,7 +520,7 @@
+ 		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6540000 0 0x40>;
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
++		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+@@ -533,7 +533,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6500000 0 0x425>;
+ 		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
++		clocks = <&cpg CPG_MOD 318>;
+ 		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -548,7 +548,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6510000 0 0x425>;
+ 		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
++		clocks = <&cpg CPG_MOD 323>;
+ 		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -563,7 +563,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6520000 0 0x425>;
+ 		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
++		clocks = <&cpg CPG_MOD 300>;
+ 		dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+ 		       <&dmac1 0x69>, <&dmac1 0x6a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -578,7 +578,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe60b0000 0 0x425>;
+ 		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
++		clocks = <&cpg CPG_MOD 926>;
+ 		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -590,7 +590,7 @@
+ 		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+ 		reg = <0 0xee200000 0 0x80>;
+ 		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
++		clocks = <&cpg CPG_MOD 315>;
+ 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -604,7 +604,7 @@
+ 		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+ 		reg = <0 0xee220000 0 0x80>;
+ 		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
++		clocks = <&cpg CPG_MOD 305>;
+ 		dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+ 		       <&dmac1 0xe1>, <&dmac1 0xe2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -623,7 +623,7 @@
+ 		compatible = "renesas,sdhi-r8a7790";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
++		clocks = <&cpg CPG_MOD 314>;
+ 		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ 		       <&dmac1 0xcd>, <&dmac1 0xce>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -636,7 +636,7 @@
+ 		compatible = "renesas,sdhi-r8a7790";
+ 		reg = <0 0xee120000 0 0x328>;
+ 		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
++		clocks = <&cpg CPG_MOD 313>;
+ 		dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ 		       <&dmac1 0xc9>, <&dmac1 0xca>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -649,7 +649,7 @@
+ 		compatible = "renesas,sdhi-r8a7790";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
++		clocks = <&cpg CPG_MOD 312>;
+ 		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ 		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -662,7 +662,7 @@
+ 		compatible = "renesas,sdhi-r8a7790";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
++		clocks = <&cpg CPG_MOD 311>;
+ 		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ 		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -676,7 +676,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c40000 0 64>;
+ 		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
++		clocks = <&cpg CPG_MOD 204>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+@@ -690,7 +690,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c50000 0 64>;
+ 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
++		clocks = <&cpg CPG_MOD 203>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+@@ -704,7 +704,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c60000 0 64>;
+ 		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
++		clocks = <&cpg CPG_MOD 202>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+@@ -718,7 +718,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c20000 0 0x100>;
+ 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
++		clocks = <&cpg CPG_MOD 206>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+@@ -732,7 +732,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c30000 0 0x100>;
+ 		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
++		clocks = <&cpg CPG_MOD 207>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+@@ -746,7 +746,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6ce0000 0 0x100>;
+ 		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
++		clocks = <&cpg CPG_MOD 216>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+@@ -760,7 +760,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e60000 0 64>;
+ 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+@@ -775,7 +775,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e68000 0 64>;
+ 		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+@@ -790,7 +790,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e56000 0 64>;
+ 		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+@@ -805,7 +805,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c0000 0 96>;
+ 		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+@@ -820,7 +820,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c8000 0 96>;
+ 		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+@@ -852,7 +852,7 @@
+ 		compatible = "renesas,ether-r8a7790";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
++		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+@@ -865,7 +865,7 @@
+ 			     "renesas,etheravb-rcar-gen2";
+ 		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
++		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -876,7 +876,7 @@
+ 		compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+ 		reg = <0 0xee300000 0 0x2000>;
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
++		clocks = <&cpg CPG_MOD 815>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -885,7 +885,7 @@
+ 		compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+ 		reg = <0 0xee500000 0 0x2000>;
+ 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
++		clocks = <&cpg CPG_MOD 814>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -894,7 +894,7 @@
+ 		compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
+ 		reg = <0 0xe6590000 0 0x100>;
+ 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+ 		dma-names = "ch0", "ch1", "ch2", "ch3";
+@@ -911,7 +911,7 @@
+ 		reg = <0 0xe6590100 0 0x100>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -930,7 +930,7 @@
+ 		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef0000 0 0x1000>;
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
++		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -939,7 +939,7 @@
+ 		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef1000 0 0x1000>;
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
++		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -948,7 +948,7 @@
+ 		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef2000 0 0x1000>;
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
++		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -957,7 +957,7 @@
+ 		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef3000 0 0x1000>;
+ 		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
++		clocks = <&cpg CPG_MOD 808>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -966,7 +966,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe920000 0 0x8000>;
+ 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
++		clocks = <&cpg CPG_MOD 130>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -974,7 +974,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
++		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -982,7 +982,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
++		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -990,7 +990,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe938000 0 0x8000>;
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
++		clocks = <&cpg CPG_MOD 127>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1003,11 +1003,9 @@
+ 		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+-			 <&mstp7_clks R8A7790_CLK_DU1>,
+-			 <&mstp7_clks R8A7790_CLK_DU2>,
+-			 <&mstp7_clks R8A7790_CLK_LVDS0>,
+-			 <&mstp7_clks R8A7790_CLK_LVDS1>;
++		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
++			 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
++			 <&cpg CPG_MOD 725>;
+ 		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ 		status = "disabled";
+ 
+@@ -1037,8 +1035,8 @@
+ 		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e80000 0 0x1000>;
+ 		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
+-			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1048,8 +1046,8 @@
+ 		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e88000 0 0x1000>;
+ 		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
+-			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1059,7 +1057,7 @@
+ 		compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
+ 		reg = <0 0xfe980000 0 0x10300>;
+ 		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7790_CLK_JPU>;
++		clocks = <&cpg CPG_MOD 106>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1126,376 +1124,14 @@
+ 			clock-frequency = <0>;
+ 		};
+ 
+-		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@e6150000 {
+-			compatible = "renesas,r8a7790-cpg-clocks",
+-				     "renesas,rcar-gen2-cpg-clocks";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7790-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk &usb_extal_clk>;
+-			#clock-cells = <1>;
+-			clock-output-names = "main", "pll0", "pll1", "pll3",
+-					     "lb", "qspi", "sdh", "sd0", "sd1",
+-					     "z", "rcan", "adsp";
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
+ 		};
+-
+-		/* Variable factor clocks */
+-		sd2_clk: sd2@e6150078 {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150078 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		sd3_clk: sd3@e615026c {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe615026c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		mmc0_clk: mmc0@e6150240 {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150240 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		mmc1_clk: mmc1@e6150244 {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150244 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		ssp_clk: ssp@e6150248 {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150248 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		ssprs_clk: ssprs@e615024c {
+-			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe615024c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-
+-		/* Fixed factor clocks */
+-		pll1_div2_clk: pll1_div2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		z2_clk: z2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		zg_clk: zg {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zx_clk: zx {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zs_clk: zs {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		hp_clk: hp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		i_clk: i {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		b_clk: b {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		p_clk: p {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <24>;
+-			clock-mult = <1>;
+-		};
+-		cl_clk: cl {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <48>;
+-			clock-mult = <1>;
+-		};
+-		m2_clk: m2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		imp_clk: imp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <4>;
+-			clock-mult = <1>;
+-		};
+-		rclk_clk: rclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(48 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		oscclk_clk: oscclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(12 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		zb3_clk: zb3 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <4>;
+-			clock-mult = <1>;
+-		};
+-		zb3d2_clk: zb3d2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		ddr_clk: ddr {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		mp_clk: mp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <15>;
+-			clock-mult = <1>;
+-		};
+-		cp_clk: cp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&extal_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-
+-		/* Gate clocks */
+-		mstp0_clks: mstp0_clks@e6150130 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+-			clocks = <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7790_CLK_MSIOF0>;
+-			clock-output-names = "msiof0";
+-		};
+-		mstp1_clks: mstp1_clks@e6150134 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+-			clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
+-				 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
+-				 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+-				 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
+-				R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
+-				R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
+-				R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
+-				R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
+-				R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
+-				R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
+-			>;
+-			clock-output-names =
+-				"vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
+-				"tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
+-				"fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
+-				"vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
+-		};
+-		mstp2_clks: mstp2_clks@e6150138 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
+-				 <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
+-				R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
+-				R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+-				R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
+-			>;
+-			clock-output-names =
+-				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+-				"scifb1", "msiof1", "msiof3", "scifb2",
+-				"sys-dmac1", "sys-dmac0";
+-		};
+-		mstp3_clks: mstp3_clks@e615013c {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+-			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
+-				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
+-				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
+-				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
+-				R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
+-				R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
+-			>;
+-			clock-output-names =
+-				"iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
+-				"sdhi2", "sdhi1", "sdhi0", "mmcif0",
+-				"iic0", "pciec", "iic1", "ssusb", "cmt1",
+-				"usbdmac0", "usbdmac1";
+-		};
+-		mstp4_clks: mstp4_clks@e6150140 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+-			clocks = <&cp_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;
+-			clock-output-names = "irqc", "intc-sys";
+-		};
+-		mstp5_clks: mstp5_clks@e6150144 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+-			clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
+-				 <&extal_clk>, <&p_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
+-				R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
+-				R8A7790_CLK_PWM
+-			>;
+-			clock-output-names = "audmac0", "audmac1", "adsp_mod",
+-					     "thermal", "pwm";
+-		};
+-		mstp7_clks: mstp7_clks@e615014c {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+-			clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+-				 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
+-				 <&zx_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
+-				R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
+-				R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
+-				R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
+-			>;
+-			clock-output-names =
+-				"ehci", "hsusb", "hscif1", "hscif0", "scif1",
+-				"scif0", "du2", "du1", "du0", "lvds1", "lvds0";
+-		};
+-		mstp8_clks: mstp8_clks@e6150990 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+-			clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+-			         <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
+-				 <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
+-				R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
+-				R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
+-				R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
+-			>;
+-			clock-output-names =
+-				"mlb", "vin3", "vin2", "vin1", "vin0",
+-				"etheravb", "ether", "sata1", "sata0";
+-		};
+-		mstp9_clks: mstp9_clks@e6150994 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+-			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
+-				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
+-				R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
+-				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
+-				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
+-			>;
+-			clock-output-names =
+-				"gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
+-				"rcan1", "rcan0", "qspi_mod", "iic3",
+-				"i2c3", "i2c2", "i2c1", "i2c0";
+-		};
+-		mstp10_clks: mstp10_clks@e6150998 {
+-			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+-			clocks = <&p_clk>,
+-				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-				<&p_clk>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
+-
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7790_CLK_SSI_ALL
+-				R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
+-				R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
+-				R8A7790_CLK_SCU_ALL
+-				R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
+-				R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
+-				R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
+-				R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
+-			>;
+-			clock-output-names =
+-				"ssi-all",
+-				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+-				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+-				"scu-all",
+-				"scu-dvc1", "scu-dvc0",
+-				"scu-ctu1-mix1", "scu-ctu0-mix0",
+-				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+-				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+-		};
+ 	};
+ 
+ 	prr: chipid@ff000044 {
+@@ -1518,7 +1154,7 @@
+ 		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+ 		reg = <0 0xe6b10000 0 0x2c>;
+ 		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
++		clocks = <&cpg CPG_MOD 917>;
+ 		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1534,7 +1170,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e20000 0 0x0064>;
+ 		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
++		clocks = <&cpg CPG_MOD 0>;
+ 		dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ 		       <&dmac1 0x51>, <&dmac1 0x52>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1549,7 +1185,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e10000 0 0x0064>;
+ 		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
++		clocks = <&cpg CPG_MOD 208>;
+ 		dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ 		       <&dmac1 0x55>, <&dmac1 0x56>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1564,7 +1200,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e00000 0 0x0064>;
+ 		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
++		clocks = <&cpg CPG_MOD 205>;
+ 		dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ 		       <&dmac1 0x41>, <&dmac1 0x42>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1579,7 +1215,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6c90000 0 0x0064>;
+ 		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
++		clocks = <&cpg CPG_MOD 215>;
+ 		dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+ 		       <&dmac1 0x45>, <&dmac1 0x46>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1593,7 +1229,7 @@
+ 		compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
+ 		reg = <0 0xee000000 0 0xc00>;
+ 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
++		clocks = <&cpg CPG_MOD 328>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		phys = <&usb2 1>;
+ 		phy-names = "usb";
+@@ -1606,7 +1242,7 @@
+ 		reg = <0 0xee090000 0 0xc00>,
+ 		      <0 0xee080000 0 0x1100>;
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -1639,7 +1275,7 @@
+ 		reg = <0 0xee0b0000 0 0xc00>,
+ 		      <0 0xee0a0000 0 0x1100>;
+ 		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -1657,7 +1293,7 @@
+ 	pci2: pci@ee0d0000 {
+ 		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+ 		device_type = "pci";
+-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		reg = <0 0xee0d0000 0 0xc00>,
+ 		      <0 0xee0c0000 0 0x1100>;
+@@ -1707,7 +1343,7 @@
+ 		#interrupt-cells = <1>;
+ 		interrupt-map-mask = <0 0 0 0>;
+ 		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
++		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ 		clock-names = "pcie", "pcie_bus";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1728,21 +1364,22 @@
+ 			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+-		clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+-			<&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
+-			<&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
+-			<&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
+-			<&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
+-			<&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
+-			<&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
+-			<&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
+-			<&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
+-			<&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
+-			<&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
+-			<&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
+-			<&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
+-			<&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
+-			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
++		clocks = <&cpg CPG_MOD 1005>,
++			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++			 <&cpg CPG_CORE R8A7790_CLK_M2>;
+ 		clock-names = "ssi-all",
+ 				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ 				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-- 
+2.19.0
+
diff --git a/patches/0300-ARM-dts-r8a7792-Convert-to-new-CPG-MSSR-bindings.patch b/patches/0300-ARM-dts-r8a7792-Convert-to-new-CPG-MSSR-bindings.patch
new file mode 100644
index 00000000000000..24299cd33699c4
--- /dev/null
+++ b/patches/0300-ARM-dts-r8a7792-Convert-to-new-CPG-MSSR-bindings.patch
@@ -0,0 +1,735 @@
+From 39a958a38410e62533019207ab3dee62733a290f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:11:36 +0200
+Subject: [PATCH 0300/1795] ARM: dts: r8a7792: Convert to new CPG/MSSR bindings
+
+Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse
+Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings
+to the new unified "Renesas Clock Pulse Generator / Module Standby and
+Software Reset" DT bindings.
+
+This simplifies the DTS files, and allows to add support for reset
+control later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 762dbc444ca240580f7eda5b9152d147cca608b3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792-blanche.dts |   3 +-
+ arch/arm/boot/dts/r8a7792-wheat.dts   |   3 +-
+ arch/arm/boot/dts/r8a7792.dtsi        | 333 +++++---------------------
+ 3 files changed, 63 insertions(+), 276 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
+index f3ea43b7b724..9b67dca6c9ef 100644
+--- a/arch/arm/boot/dts/r8a7792-blanche.dts
++++ b/arch/arm/boot/dts/r8a7792-blanche.dts
+@@ -310,8 +310,7 @@
+ 	pinctrl-0 = <&du0_pins &du1_pins>;
+ 	pinctrl-names = "default";
+ 
+-	clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
+-		 <&x1_clk>, <&x2_clk>;
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
+ 	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 	status = "okay";
+ 
+diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
+index c24f26fdab1f..b9471b67b728 100644
+--- a/arch/arm/boot/dts/r8a7792-wheat.dts
++++ b/arch/arm/boot/dts/r8a7792-wheat.dts
+@@ -305,8 +305,7 @@
+ 	pinctrl-0 = <&du0_pins &du1_pins>;
+ 	pinctrl-names = "default";
+ 
+-	clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
+-		 <&osc2_clk>;
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>;
+ 	clock-names = "du.0", "du.1", "dclkin.0";
+ 	status = "okay";
+ 
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 2623f39bed2b..a209787d899a 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -8,7 +8,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/r8a7792-clock.h>
++#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7792-sysc.h>
+@@ -46,7 +46,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <0>;
+ 			clock-frequency = <1000000000>;
+-			clocks = <&z_clk>;
++			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
+ 			power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+ 			next-level-cache = <&L2_CA15>;
+ 		};
+@@ -92,7 +92,7 @@
+ 			      <0 0xf1006000 0 0x2000>;
+ 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ 				      IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>;
++			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+@@ -106,7 +106,7 @@
+ 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
++			clocks = <&cpg CPG_MOD 407>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -153,7 +153,7 @@
+ 			gpio-ranges = <&pfc 0 0 29>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
++			clocks = <&cpg CPG_MOD 912>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -167,7 +167,7 @@
+ 			gpio-ranges = <&pfc 0 32 23>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
++			clocks = <&cpg CPG_MOD 911>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -181,7 +181,7 @@
+ 			gpio-ranges = <&pfc 0 64 32>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
++			clocks = <&cpg CPG_MOD 910>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -195,7 +195,7 @@
+ 			gpio-ranges = <&pfc 0 96 28>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
++			clocks = <&cpg CPG_MOD 909>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -209,7 +209,7 @@
+ 			gpio-ranges = <&pfc 0 128 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
++			clocks = <&cpg CPG_MOD 908>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -223,7 +223,7 @@
+ 			gpio-ranges = <&pfc 0 160 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
++			clocks = <&cpg CPG_MOD 907>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -237,7 +237,7 @@
+ 			gpio-ranges = <&pfc 0 192 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
++			clocks = <&cpg CPG_MOD 905>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -251,7 +251,7 @@
+ 			gpio-ranges = <&pfc 0 224 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
++			clocks = <&cpg CPG_MOD 904>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -265,7 +265,7 @@
+ 			gpio-ranges = <&pfc 0 256 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
++			clocks = <&cpg CPG_MOD 921>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -279,7 +279,7 @@
+ 			gpio-ranges = <&pfc 0 288 17>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
++			clocks = <&cpg CPG_MOD 919>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -293,7 +293,7 @@
+ 			gpio-ranges = <&pfc 0 320 32>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
++			clocks = <&cpg CPG_MOD 914>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -307,7 +307,7 @@
+ 			gpio-ranges = <&pfc 0 352 30>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+-			clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
++			clocks = <&cpg CPG_MOD 913>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -336,7 +336,7 @@
+ 					  "ch4", "ch5", "ch6", "ch7",
+ 					  "ch8", "ch9", "ch10", "ch11",
+ 					  "ch12", "ch13", "ch14";
+-			clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
++			clocks = <&cpg CPG_MOD 219>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			#dma-cells = <1>;
+@@ -368,7 +368,7 @@
+ 					  "ch4", "ch5", "ch6", "ch7",
+ 					  "ch8", "ch9", "ch10", "ch11",
+ 					  "ch12", "ch13", "ch14";
+-			clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
++			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			#dma-cells = <1>;
+@@ -380,8 +380,8 @@
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+ 			reg = <0 0xe6e60000 0 64>;
+ 			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 721>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ 			       <&dmac1 0x29>, <&dmac1 0x2a>;
+@@ -395,8 +395,8 @@
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+ 			reg = <0 0xe6e68000 0 64>;
+ 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 720>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ 			       <&dmac1 0x2d>, <&dmac1 0x2e>;
+@@ -410,8 +410,8 @@
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+ 			reg = <0 0xe6e58000 0 64>;
+ 			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 719>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ 			       <&dmac1 0x2b>, <&dmac1 0x2c>;
+@@ -425,8 +425,8 @@
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+ 			reg = <0 0xe6ea8000 0 64>;
+ 			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 718>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ 			       <&dmac1 0x2f>, <&dmac1 0x30>;
+@@ -440,8 +440,8 @@
+ 				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 			reg = <0 0xe62c0000 0 96>;
+ 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 717>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ 			       <&dmac1 0x39>, <&dmac1 0x3a>;
+@@ -455,8 +455,8 @@
+ 				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 			reg = <0 0xe62c8000 0 96>;
+ 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+-				 <&scif_clk>;
++			clocks = <&cpg CPG_MOD 716>,
++				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ 			       <&dmac1 0x4d>, <&dmac1 0x4e>;
+@@ -490,7 +490,7 @@
+ 			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ 			       <&dmac1 0xcd>, <&dmac1 0xce>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
++			clocks = <&cpg CPG_MOD 314>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -500,7 +500,7 @@
+ 				     "renesas,rcar-gen2-jpu";
+ 			reg = <0 0xfe980000 0 0x10300>;
+ 			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp1_clks R8A7792_CLK_JPU>;
++			clocks = <&cpg CPG_MOD 106>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -509,7 +509,7 @@
+ 				     "renesas,etheravb-rcar-gen2";
+ 			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ 			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -522,7 +522,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6508000 0 0x40>;
+ 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
++			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+@@ -535,7 +535,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6518000 0 0x40>;
+ 			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
++			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+@@ -548,7 +548,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6530000 0 0x40>;
+ 			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
++			clocks = <&cpg CPG_MOD 929>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+@@ -561,7 +561,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6540000 0 0x40>;
+ 			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
++			clocks = <&cpg CPG_MOD 928>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+@@ -574,7 +574,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6520000 0 0x40>;
+ 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
++			clocks = <&cpg CPG_MOD 927>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+@@ -587,7 +587,7 @@
+ 				     "renesas,rcar-gen2-i2c";
+ 			reg = <0 0xe6528000 0 0x40>;
+ 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
++			clocks = <&cpg CPG_MOD 925>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			i2c-scl-internal-delay-ns = <110>;
+ 			#address-cells = <1>;
+@@ -599,7 +599,7 @@
+ 			compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+ 			reg = <0 0xe6b10000 0 0x2c>;
+ 			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
++			clocks = <&cpg CPG_MOD 917>;
+ 			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ 			       <&dmac1 0x17>, <&dmac1 0x18>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+@@ -615,7 +615,7 @@
+ 				     "renesas,rcar-gen2-msiof";
+ 			reg = <0 0xe6e20000 0 0x0064>;
+ 			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
++			clocks = <&cpg CPG_MOD 000>;
+ 			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ 			       <&dmac1 0x51>, <&dmac1 0x52>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+@@ -630,7 +630,7 @@
+ 				     "renesas,rcar-gen2-msiof";
+ 			reg = <0 0xe6e10000 0 0x0064>;
+ 			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
++			clocks = <&cpg CPG_MOD 208>;
+ 			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ 			       <&dmac1 0x55>, <&dmac1 0x56>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+@@ -646,8 +646,8 @@
+ 			reg-names = "du";
+ 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R8A7792_CLK_DU0>,
+-				 <&mstp7_clks R8A7792_CLK_DU1>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>;
+ 			clock-names = "du.0", "du.1";
+ 			status = "disabled";
+ 
+@@ -673,8 +673,8 @@
+ 				     "renesas,rcar-gen2-can";
+ 			reg = <0 0xe6e80000 0 0x1000>;
+ 			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
+-				 <&rcan_clk>, <&can_clk>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ 			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+@@ -685,8 +685,8 @@
+ 				     "renesas,rcar-gen2-can";
+ 			reg = <0 0xe6e88000 0 0x1000>;
+ 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
+-				 <&rcan_clk>, <&can_clk>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ 			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+@@ -697,7 +697,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef0000 0 0x1000>;
+ 			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
++			clocks = <&cpg CPG_MOD 811>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -707,7 +707,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef1000 0 0x1000>;
+ 			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
++			clocks = <&cpg CPG_MOD 810>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -717,7 +717,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef2000 0 0x1000>;
+ 			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
++			clocks = <&cpg CPG_MOD 809>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -727,7 +727,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef3000 0 0x1000>;
+ 			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
++			clocks = <&cpg CPG_MOD 808>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -737,7 +737,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef4000 0 0x1000>;
+ 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
++			clocks = <&cpg CPG_MOD 805>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -747,7 +747,7 @@
+ 				     "renesas,rcar-gen2-vin";
+ 			reg = <0 0xe6ef5000 0 0x1000>;
+ 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
++			clocks = <&cpg CPG_MOD 804>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+@@ -756,7 +756,7 @@
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe928000 0 0x8000>;
+ 			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
++			clocks = <&cpg CPG_MOD 131>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -764,7 +764,7 @@
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe930000 0 0x8000>;
+ 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
++			clocks = <&cpg CPG_MOD 128>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+@@ -772,229 +772,18 @@
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe938000 0 0x8000>;
+ 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
++			clocks = <&cpg CPG_MOD 127>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ 		};
+ 
+-		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@e6150000 {
+-			compatible = "renesas,r8a7792-cpg-clocks",
+-				     "renesas,rcar-gen2-cpg-clocks";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7792-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+ 			clocks = <&extal_clk>;
+-			#clock-cells = <1>;
+-			clock-output-names = "main", "pll0", "pll1", "pll3",
+-					     "lb", "qspi";
++			clock-names = "extal";
++			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
+ 		};
+-
+-		/* Fixed factor clocks */
+-		pll1_div2_clk: pll1_div2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		z_clk: z {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
+-			#clock-cells = <0>;
+-			clock-div = <1>;
+-			clock-mult = <1>;
+-		};
+-		zx_clk: zx {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zs_clk: zs {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		hp_clk: hp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		p_clk: p {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <24>;
+-			clock-mult = <1>;
+-		};
+-		cp_clk: cp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <48>;
+-			clock-mult = <1>;
+-		};
+-		mp_clk: mp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <15>;
+-			clock-mult = <1>;
+-		};
+-		m2_clk: m2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		sd_clk: sd {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		rcan_clk: rcan {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <49>;
+-			clock-mult = <1>;
+-		};
+-		zg_clk: zg {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <5>;
+-			clock-mult = <1>;
+-		};
+-
+-		/* Gate clocks */
+-		mstp0_clks: mstp0_clks@e6150130 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+-			clocks = <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7792_CLK_MSIOF0>;
+-			clock-output-names = "msiof0";
+-		};
+-		mstp1_clks: mstp1_clks@e6150134 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+-			clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_JPU
+-				R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
+-				R8A7792_CLK_VSP1_SY
+-			>;
+-			clock-output-names = "jpu", "vsp1du1", "vsp1du0",
+-					     "vsp1-sy";
+-		};
+-		mstp2_clks: mstp2_clks@e6150138 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+-			clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_MSIOF1
+-				R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
+-			>;
+-			clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
+-		};
+-		mstp3_clks: mstp3_clks@e615013c {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+-			clocks = <&sd_clk>;
+-			#clock-cells = <1>;
+-			renesas,clock-indices = <R8A7792_CLK_SDHI0>;
+-			clock-output-names = "sdhi0";
+-		};
+-		mstp4_clks: mstp4_clks@e6150140 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+-			clocks = <&cp_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS
+-			>;
+-			clock-output-names = "irqc", "intc-sys";
+-		};
+-		mstp7_clks: mstp7_clks@e615014c {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+-			clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+-				 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
+-				R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
+-				R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
+-				R8A7792_CLK_DU1 R8A7792_CLK_DU0
+-			>;
+-			clock-output-names = "hscif1", "hscif0", "scif3",
+-					     "scif2", "scif1", "scif0",
+-					     "du1", "du0";
+-		};
+-		mstp8_clks: mstp8_clks@e6150990 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+-			clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+-			         <&zg_clk>, <&zg_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
+-				R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
+-				R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
+-				R8A7792_CLK_ETHERAVB
+-			>;
+-			clock-output-names = "vin5", "vin4", "vin3", "vin2",
+-					     "vin1", "vin0", "etheravb";
+-		};
+-		mstp9_clks: mstp9_clks@e6150994 {
+-			compatible = "renesas,r8a7792-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+-			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
+-				 <&cpg_clocks R8A7792_CLK_QSPI>,
+-				 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
+-				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
+-				R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
+-				R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
+-				R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
+-				R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
+-				R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
+-				R8A7792_CLK_QSPI_MOD
+-				R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
+-				R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
+-				R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
+-				R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
+-			>;
+-			clock-output-names =
+-				"gpio7", "gpio6", "gpio5", "gpio4",
+-				"gpio3", "gpio2", "gpio1", "gpio0",
+-				"gpio11", "gpio10", "can1", "can0",
+-				"qspi_mod", "gpio9", "gpio8",
+-				"i2c5", "i2c4", "i2c3", "i2c2",
+-				"i2c1", "i2c0";
+-		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0301-ARM-dts-r8a7793-Convert-to-new-CPG-MSSR-bindings.patch b/patches/0301-ARM-dts-r8a7793-Convert-to-new-CPG-MSSR-bindings.patch
new file mode 100644
index 00000000000000..6773fd7d6f9405
--- /dev/null
+++ b/patches/0301-ARM-dts-r8a7793-Convert-to-new-CPG-MSSR-bindings.patch
@@ -0,0 +1,927 @@
+From e979202e66bcf05fe306ac86726b0faa08823419 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:11:37 +0200
+Subject: [PATCH 0301/1795] ARM: dts: r8a7793: Convert to new CPG/MSSR bindings
+
+Convert the R-Car M2-N SoC from the old "Renesas R-Car Gen2 Clock Pulse
+Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
+(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
+Generator / Module Standby and Software Reset" DT bindings.
+
+This simplifies the DTS files, and allows to add support for reset
+control later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d77fe953768850557a1851d2c933b76b2083e4d5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts |   4 +-
+ arch/arm/boot/dts/r8a7793.dtsi     | 459 +++++------------------------
+ 2 files changed, 82 insertions(+), 381 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 76e3aca2029e..51b3ffac8efa 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -303,9 +303,7 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7793_CLK_DU0>,
+-		 <&mstp7_clks R8A7793_CLK_DU1>,
+-		 <&mstp7_clks R8A7793_CLK_LVDS0>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ 		 <&x13_clk>, <&x2_clk>;
+ 	clock-names = "du.0", "du.1", "lvds.0",
+ 		      "dclkin.0", "dclkin.1";
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 497716b6fbe2..ef8009c01e66 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -8,7 +8,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/r8a7793-clock.h>
++#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7793-sysc.h>
+@@ -43,7 +43,7 @@
+ 			reg = <0>;
+ 			clock-frequency = <1500000000>;
+ 			voltage-tolerance = <1>; /* 1% */
+-			clocks = <&cpg_clocks R8A7793_CLK_Z>;
++			clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
+ 			clock-latency = <300000>; /* 300 us */
+ 			power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+ 
+@@ -108,7 +108,7 @@
+ 			<0 0xf1004000 0 0x2000>,
+ 			<0 0xf1006000 0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>;
++		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+@@ -122,7 +122,7 @@
+ 		gpio-ranges = <&pfc 0 0 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
++		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -135,7 +135,7 @@
+ 		gpio-ranges = <&pfc 0 32 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
++		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -148,7 +148,7 @@
+ 		gpio-ranges = <&pfc 0 64 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
++		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -161,7 +161,7 @@
+ 		gpio-ranges = <&pfc 0 96 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
++		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -174,7 +174,7 @@
+ 		gpio-ranges = <&pfc 0 128 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
++		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -187,7 +187,7 @@
+ 		gpio-ranges = <&pfc 0 160 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
++		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -200,7 +200,7 @@
+ 		gpio-ranges = <&pfc 0 192 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
++		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -213,7 +213,7 @@
+ 		gpio-ranges = <&pfc 0 224 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
++		clocks = <&cpg CPG_MOD 904>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -223,7 +223,7 @@
+ 				"renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
++		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+@@ -241,7 +241,7 @@
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
++		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 
+@@ -261,7 +261,7 @@
+ 			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
++		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 
+@@ -285,7 +285,7 @@
+ 			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
++		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -313,7 +313,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
++		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -344,7 +344,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
++		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -373,7 +373,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
++		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -402,7 +402,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
++		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -416,7 +416,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6508000 0 0x40>;
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
++		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -428,7 +428,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6518000 0 0x40>;
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
++		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -440,7 +440,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6530000 0 0x40>;
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
++		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -452,7 +452,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6540000 0 0x40>;
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
++		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -464,7 +464,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6520000 0 0x40>;
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
++		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -477,7 +477,7 @@
+ 		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6528000 0 0x40>;
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
++		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+@@ -491,7 +491,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe60b0000 0 0x425>;
+ 		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
++		clocks = <&cpg CPG_MOD 926>;
+ 		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -506,7 +506,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6500000 0 0x425>;
+ 		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
++		clocks = <&cpg CPG_MOD 318>;
+ 		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -521,7 +521,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6510000 0 0x425>;
+ 		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
++		clocks = <&cpg CPG_MOD 323>;
+ 		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -538,7 +538,7 @@
+ 		compatible = "renesas,sdhi-r8a7793";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
++		clocks = <&cpg CPG_MOD 314>;
+ 		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ 		       <&dmac1 0xcd>, <&dmac1 0xce>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -551,7 +551,7 @@
+ 		compatible = "renesas,sdhi-r8a7793";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
++		clocks = <&cpg CPG_MOD 312>;
+ 		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ 		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -564,7 +564,7 @@
+ 		compatible = "renesas,sdhi-r8a7793";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
++		clocks = <&cpg CPG_MOD 311>;
+ 		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ 		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -577,7 +577,7 @@
+ 		compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+ 		reg = <0 0xee200000 0 0x80>;
+ 		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
++		clocks = <&cpg CPG_MOD 315>;
+ 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -592,7 +592,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c40000 0 64>;
+ 		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
++		clocks = <&cpg CPG_MOD 204>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+@@ -606,7 +606,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c50000 0 64>;
+ 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
++		clocks = <&cpg CPG_MOD 203>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+@@ -620,7 +620,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c60000 0 64>;
+ 		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
++		clocks = <&cpg CPG_MOD 202>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+@@ -634,7 +634,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c70000 0 64>;
+ 		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
++		clocks = <&cpg CPG_MOD 1106>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+@@ -648,7 +648,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c78000 0 64>;
+ 		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
++		clocks = <&cpg CPG_MOD 1107>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+@@ -662,7 +662,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c80000 0 64>;
+ 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
++		clocks = <&cpg CPG_MOD 1108>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+@@ -676,7 +676,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c20000 0 0x100>;
+ 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
++		clocks = <&cpg CPG_MOD 206>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+@@ -690,7 +690,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c30000 0 0x100>;
+ 		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
++		clocks = <&cpg CPG_MOD 207>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+@@ -704,7 +704,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6ce0000 0 0x100>;
+ 		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
++		clocks = <&cpg CPG_MOD 216>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+@@ -718,7 +718,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e60000 0 64>;
+ 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+@@ -733,7 +733,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e68000 0 64>;
+ 		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+@@ -748,7 +748,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e58000 0 64>;
+ 		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+@@ -763,7 +763,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ea8000 0 64>;
+ 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+@@ -778,7 +778,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee0000 0 64>;
+ 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+@@ -793,7 +793,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee8000 0 64>;
+ 		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+@@ -808,7 +808,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c0000 0 96>;
+ 		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+@@ -823,7 +823,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c8000 0 96>;
+ 		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+@@ -838,7 +838,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62d0000 0 96>;
+ 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+@@ -870,7 +870,7 @@
+ 		compatible = "renesas,ether-r8a7793";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
++		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+@@ -882,7 +882,7 @@
+ 		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef0000 0 0x1000>;
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7793_CLK_VIN0>;
++		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -891,7 +891,7 @@
+ 		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef1000 0 0x1000>;
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7793_CLK_VIN1>;
++		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -900,7 +900,7 @@
+ 		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef2000 0 0x1000>;
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7793_CLK_VIN2>;
++		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -909,7 +909,7 @@
+ 		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+ 		reg = <0 0xe6b10000 0 0x2c>;
+ 		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
++		clocks = <&cpg CPG_MOD 917>;
+ 		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -927,9 +927,9 @@
+ 		reg-names = "du", "lvds.0";
+ 		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7793_CLK_DU0>,
+-			 <&mstp7_clks R8A7793_CLK_DU1>,
+-			 <&mstp7_clks R8A7793_CLK_LVDS0>;
++		clocks = <&cpg CPG_MOD 724>,
++			 <&cpg CPG_MOD 723>,
++			 <&cpg CPG_MOD 726>;
+ 		clock-names = "du.0", "du.1", "lvds.0";
+ 		status = "disabled";
+ 
+@@ -954,8 +954,8 @@
+ 		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e80000 0 0x1000>;
+ 		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
+-			 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -965,8 +965,8 @@
+ 		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e88000 0 0x1000>;
+ 		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
+-			 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1029,312 +1029,14 @@
+ 		};
+ 
+ 		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@e6150000 {
+-			compatible = "renesas,r8a7793-cpg-clocks",
+-				     "renesas,rcar-gen2-cpg-clocks";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7793-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk &usb_extal_clk>;
+-			#clock-cells = <1>;
+-			clock-output-names = "main", "pll0", "pll1", "pll3",
+-					     "lb", "qspi", "sdh", "sd0", "z",
+-					     "rcan", "adsp";
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
+ 		};
+-
+-		/* Variable factor clocks */
+-		sd2_clk: sd2@e6150078 {
+-			compatible = "renesas,r8a7793-div6-clock",
+-				     "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150078 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		sd3_clk: sd3@e615026c {
+-			compatible = "renesas,r8a7793-div6-clock",
+-				     "renesas,cpg-div6-clock";
+-			reg = <0 0xe615026c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		mmc0_clk: mmc0@e6150240 {
+-			compatible = "renesas,r8a7793-div6-clock",
+-				     "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150240 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-
+-		/* Fixed factor clocks */
+-		pll1_div2_clk: pll1_div2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		zg_clk: zg {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <5>;
+-			clock-mult = <1>;
+-		};
+-		zx_clk: zx {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zs_clk: zs {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		hp_clk: hp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		p_clk: p {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <24>;
+-			clock-mult = <1>;
+-		};
+-		m2_clk: m2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		rclk_clk: rclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(48 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		mp_clk: mp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <15>;
+-			clock-mult = <1>;
+-		};
+-		cp_clk: cp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&extal_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-
+-		/* Gate clocks */
+-		mstp1_clks: mstp1_clks@e6150134 {
+-			compatible = "renesas,r8a7793-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+-			clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+-				 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+-				 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+-				 <&zs_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
+-				R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
+-				R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
+-				R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
+-				R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
+-				R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
+-				R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
+-				R8A7793_CLK_VSP1_S
+-			>;
+-			clock-output-names =
+-				"vcp0", "vpc0", "ssp_dev", "tmu1",
+-				"pvrsrvkm", "tddmac", "fdp1", "fdp0",
+-				"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+-				"vsp1-du0", "vsps";
+-		};
+-		mstp2_clks: mstp2_clks@e6150138 {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
+-				R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
+-				R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
+-			>;
+-			clock-output-names =
+-				"scifa2", "scifa1", "scifa0", "scifb0",
+-				"scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
+-		};
+-		mstp3_clks: mstp3_clks@e615013c {
+-			compatible = "renesas,r8a7793-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+-			clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
+-				 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
+-				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
+-				 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
+-				R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
+-				R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
+-				R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
+-				R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
+-				R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
+-			>;
+-			clock-output-names =
+-				"tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
+-				"i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+-				"usbdmac0", "usbdmac1";
+-		};
+-		mstp4_clks: mstp4_clks@e6150140 {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+-			clocks = <&cp_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS
+-			>;
+-			clock-output-names = "irqc", "intc-sys";
+-		};
+-		mstp5_clks: mstp5_clks@e6150144 {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+-			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
+-					 R8A7793_CLK_THERMAL>;
+-			clock-output-names = "audmac0", "audmac1", "thermal";
+-		};
+-		mstp7_clks: mstp7_clks@e615014c {
+-			compatible = "renesas,r8a7793-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+-			clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
+-				 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+-				 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
+-				 <&zx_clk>, <&zx_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
+-				R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
+-				R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
+-				R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
+-				R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
+-				R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
+-				R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
+-			>;
+-			clock-output-names =
+-				"ehci", "hsusb", "hscif2", "scif5", "scif4",
+-				"hscif1", "hscif0", "scif3", "scif2",
+-				"scif1", "scif0", "du1", "du0", "lvds0";
+-		};
+-		mstp8_clks: mstp8_clks@e6150990 {
+-			compatible = "renesas,r8a7793-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+-			clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+-				 <&p_clk>, <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
+-				R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
+-				R8A7793_CLK_ETHER R8A7793_CLK_SATA1
+-				R8A7793_CLK_SATA0
+-			>;
+-			clock-output-names =
+-				"ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
+-				"sata1", "sata0";
+-		};
+-		mstp9_clks: mstp9_clks@e6150994 {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+-			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&p_clk>, <&p_clk>,
+-				 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
+-				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
+-				R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
+-				R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
+-				R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
+-				R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
+-				R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
+-				R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
+-				R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
+-				R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
+-			>;
+-			clock-output-names =
+-				"gpio7", "gpio6", "gpio5", "gpio4",
+-				"gpio3", "gpio2", "gpio1", "gpio0",
+-				"rcan1", "rcan0", "qspi_mod", "i2c5",
+-				"i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
+-				"i2c0";
+-		};
+-		mstp10_clks: mstp10_clks@e6150998 {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+-			clocks = <&p_clk>,
+-				<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-				<&p_clk>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
+-
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_SSI_ALL
+-				R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
+-				R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
+-				R8A7793_CLK_SCU_ALL
+-				R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
+-				R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
+-				R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
+-				R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
+-			>;
+-			clock-output-names =
+-				"ssi-all",
+-				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+-				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+-				"scu-all",
+-				"scu-dvc1", "scu-dvc0",
+-				"scu-ctu1-mix1", "scu-ctu0-mix0",
+-				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+-				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+-		};
+-		mstp11_clks: mstp11_clks@e615099c {
+-			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
+-			>;
+-			clock-output-names = "scifa3", "scifa4", "scifa5";
+-		};
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+@@ -1428,19 +1130,20 @@
+ 			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+-		clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+-			<&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
+-			<&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
+-			<&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
+-			<&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
+-			<&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
+-			<&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
+-			<&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
+-			<&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
+-			<&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
+-			<&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
+-			<&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
+-			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
++		clocks = <&cpg CPG_MOD 1005>,
++			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++			 <&cpg CPG_CORE R8A7793_CLK_M2>;
+ 		clock-names = "ssi-all",
+ 				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ 				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-- 
+2.19.0
+
diff --git a/patches/0302-ARM-dts-r8a7794-Convert-to-new-CPG-MSSR-bindings.patch b/patches/0302-ARM-dts-r8a7794-Convert-to-new-CPG-MSSR-bindings.patch
new file mode 100644
index 00000000000000..faf6a413cec25d
--- /dev/null
+++ b/patches/0302-ARM-dts-r8a7794-Convert-to-new-CPG-MSSR-bindings.patch
@@ -0,0 +1,1025 @@
+From 4425847ea908956226189e89938679e8fe7f82f2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:11:38 +0200
+Subject: [PATCH 0302/1795] ARM: dts: r8a7794: Convert to new CPG/MSSR bindings
+
+Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
+Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
+(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
+Generator / Module Standby and Software Reset" DT bindings.
+
+This simplifies the DTS files, and allows to add support for reset
+control later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 58d6c357b1f7851d632bb70de3a9ada219f201c2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts  |   3 +-
+ arch/arm/boot/dts/r8a7794-silk.dts |   3 +-
+ arch/arm/boot/dts/r8a7794.dtsi     | 528 +++++------------------------
+ 3 files changed, 82 insertions(+), 452 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index f1eea13cdf44..e45f92b5eb11 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -167,8 +167,7 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
+-		 <&mstp7_clks R8A7794_CLK_DU1>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ 		 <&x13_clk>, <&x2_clk>;
+ 	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index 4cb5278d104d..edfad0e5ac53 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -423,8 +423,7 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
+-		 <&mstp7_clks R8A7794_CLK_DU1>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ 		 <&x2_clk>, <&x3_clk>;
+ 	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 26535414203a..ebd44d9982be 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -9,7 +9,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/r8a7794-clock.h>
++#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7794-sysc.h>
+@@ -43,7 +43,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <0>;
+ 			clock-frequency = <1000000000>;
+-			clocks = <&z2_clk>;
++			clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+ 			power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+ 			next-level-cache = <&L2_CA7>;
+ 		};
+@@ -75,7 +75,7 @@
+ 			<0 0xf1004000 0 0x2000>,
+ 			<0 0xf1006000 0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
++		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+@@ -89,7 +89,7 @@
+ 		gpio-ranges = <&pfc 0 0 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
++		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -102,7 +102,7 @@
+ 		gpio-ranges = <&pfc 0 32 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
++		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -115,7 +115,7 @@
+ 		gpio-ranges = <&pfc 0 64 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
++		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -128,7 +128,7 @@
+ 		gpio-ranges = <&pfc 0 96 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
++		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -141,7 +141,7 @@
+ 		gpio-ranges = <&pfc 0 128 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
++		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -154,7 +154,7 @@
+ 		gpio-ranges = <&pfc 0 160 28>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
++		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -167,7 +167,7 @@
+ 		gpio-ranges = <&pfc 0 192 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
++		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -176,7 +176,7 @@
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
++		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 
+@@ -196,7 +196,7 @@
+ 			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
++		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 
+@@ -228,7 +228,7 @@
+ 			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
++		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -261,7 +261,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
++		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -292,7 +292,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
++		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -320,7 +320,7 @@
+ 				  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+ 				  "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+ 				  "ch12";
+-		clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
++		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -332,7 +332,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c40000 0 64>;
+ 		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
++		clocks = <&cpg CPG_MOD 204>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+@@ -346,7 +346,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c50000 0 64>;
+ 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
++		clocks = <&cpg CPG_MOD 203>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+@@ -360,7 +360,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c60000 0 64>;
+ 		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
++		clocks = <&cpg CPG_MOD 202>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+@@ -374,7 +374,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c70000 0 64>;
+ 		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
++		clocks = <&cpg CPG_MOD 1106>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+@@ -388,7 +388,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c78000 0 64>;
+ 		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
++		clocks = <&cpg CPG_MOD 1107>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+@@ -402,7 +402,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c80000 0 64>;
+ 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
++		clocks = <&cpg CPG_MOD 1108>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+@@ -416,7 +416,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c20000 0 0x100>;
+ 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
++		clocks = <&cpg CPG_MOD 206>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+@@ -430,7 +430,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c30000 0 0x100>;
+ 		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
++		clocks = <&cpg CPG_MOD 207>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+@@ -444,7 +444,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6ce0000 0 0x100>;
+ 		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
++		clocks = <&cpg CPG_MOD 216>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+@@ -458,7 +458,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e60000 0 64>;
+ 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+@@ -473,7 +473,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e68000 0 64>;
+ 		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+@@ -488,7 +488,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e58000 0 64>;
+ 		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+@@ -503,7 +503,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ea8000 0 64>;
+ 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+@@ -518,7 +518,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee0000 0 64>;
+ 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+@@ -533,7 +533,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee8000 0 64>;
+ 		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+@@ -548,7 +548,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c0000 0 96>;
+ 		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+@@ -563,7 +563,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c8000 0 96>;
+ 		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+@@ -578,7 +578,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62d0000 0 96>;
+ 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+@@ -610,7 +610,7 @@
+ 		compatible = "renesas,ether-r8a7794";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
++		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+@@ -623,7 +623,7 @@
+ 			     "renesas,etheravb-rcar-gen2";
+ 		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
++		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -635,7 +635,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6508000 0 0x40>;
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
++		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -647,7 +647,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6518000 0 0x40>;
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
++		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -659,7 +659,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6530000 0 0x40>;
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
++		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -671,7 +671,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6540000 0 0x40>;
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
++		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -683,7 +683,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6520000 0 0x40>;
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
++		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -695,7 +695,7 @@
+ 		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6528000 0 0x40>;
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
++		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -708,7 +708,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6500000 0 0x425>;
+ 		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
++		clocks = <&cpg CPG_MOD 318>;
+ 		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -723,7 +723,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6510000 0 0x425>;
+ 		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
++		clocks = <&cpg CPG_MOD 323>;
+ 		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -737,7 +737,7 @@
+ 		compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
+ 		reg = <0 0xee200000 0 0x80>;
+ 		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
++		clocks = <&cpg CPG_MOD 315>;
+ 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -750,7 +750,7 @@
+ 		compatible = "renesas,sdhi-r8a7794";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
++		clocks = <&cpg CPG_MOD 314>;
+ 		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ 		       <&dmac1 0xcd>, <&dmac1 0xce>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -763,7 +763,7 @@
+ 		compatible = "renesas,sdhi-r8a7794";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
++		clocks = <&cpg CPG_MOD 312>;
+ 		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ 		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -776,7 +776,7 @@
+ 		compatible = "renesas,sdhi-r8a7794";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
++		clocks = <&cpg CPG_MOD 311>;
+ 		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ 		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -789,7 +789,7 @@
+ 		compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+ 		reg = <0 0xe6b10000 0 0x2c>;
+ 		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
++		clocks = <&cpg CPG_MOD 917>;
+ 		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -804,7 +804,7 @@
+ 		compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef0000 0 0x1000>;
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
++		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -813,7 +813,7 @@
+ 		compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef1000 0 0x1000>;
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
++		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -824,7 +824,7 @@
+ 		reg = <0 0xee090000 0 0xc00>,
+ 		      <0 0xee080000 0 0x1100>;
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -857,7 +857,7 @@
+ 		reg = <0 0xee0d0000 0 0xc00>,
+ 		      <0 0xee0c0000 0 0x1100>;
+ 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -888,7 +888,7 @@
+ 		compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
+ 		reg = <0 0xe6590000 0 0x100>;
+ 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		renesas,buswait = <4>;
+ 		phys = <&usb0 1>;
+@@ -902,7 +902,7 @@
+ 		reg = <0 0xe6590100 0 0x100>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-		clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -921,7 +921,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
++		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -929,7 +929,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
++		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -939,8 +939,7 @@
+ 		reg-names = "du";
+ 		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7794_CLK_DU0>,
+-			 <&mstp7_clks R8A7794_CLK_DU1>;
++		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+ 		clock-names = "du.0", "du.1";
+ 		status = "disabled";
+ 
+@@ -965,8 +964,8 @@
+ 		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e80000 0 0x1000>;
+ 		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
+-			 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -976,8 +975,8 @@
+ 		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e88000 0 0x1000>;
+ 		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
+-			 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1040,370 +1039,14 @@
+ 			clock-frequency = <0>;
+ 		};
+ 
+-		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@e6150000 {
+-			compatible = "renesas,r8a7794-cpg-clocks",
+-				     "renesas,rcar-gen2-cpg-clocks";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7794-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk &usb_extal_clk>;
+-			#clock-cells = <1>;
+-			clock-output-names = "main", "pll0", "pll1", "pll3",
+-					     "lb", "qspi", "sdh", "sd0", "rcan";
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
+ 		};
+-		/* Variable factor clocks */
+-		sd2_clk: sd2@e6150078 {
+-			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150078 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		sd3_clk: sd3@e615026c {
+-			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe615026c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		mmc0_clk: mmc0@e6150240 {
+-			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150240 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-
+-		/* Fixed factor clocks */
+-		pll1_div2_clk: pll1_div2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		z2_clk: z2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
+-			#clock-cells = <0>;
+-			clock-div = <1>;
+-			clock-mult = <1>;
+-		};
+-		zg_clk: zg {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		zx_clk: zx {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zs_clk: zs {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		hp_clk: hp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		i_clk: i {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		b_clk: b {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		p_clk: p {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <24>;
+-			clock-mult = <1>;
+-		};
+-		cl_clk: cl {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <48>;
+-			clock-mult = <1>;
+-		};
+-		m2_clk: m2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		rclk_clk: rclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(48 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		oscclk_clk: oscclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(12 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		zb3_clk: zb3 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <4>;
+-			clock-mult = <1>;
+-		};
+-		zb3d2_clk: zb3d2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		ddr_clk: ddr {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		mp_clk: mp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <15>;
+-			clock-mult = <1>;
+-		};
+-		cp_clk: cp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <48>;
+-			clock-mult = <1>;
+-		};
+-
+-		acp_clk: acp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&extal_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-
+-		/* Gate clocks */
+-		mstp0_clks: mstp0_clks@e6150130 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+-			clocks = <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7794_CLK_MSIOF0>;
+-			clock-output-names = "msiof0";
+-		};
+-		mstp1_clks: mstp1_clks@e6150134 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+-			clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
+-				 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+-				 <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
+-				R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
+-				R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
+-				R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
+-			>;
+-			clock-output-names =
+-				"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
+-				"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
+-		};
+-		mstp2_clks: mstp2_clks@e6150138 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
+-				R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
+-				R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
+-				R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
+-			>;
+-			clock-output-names =
+-				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+-				"scifb1", "msiof1", "scifb2",
+-				"sys-dmac1", "sys-dmac0";
+-		};
+-		mstp3_clks: mstp3_clks@e615013c {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+-			clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
+-				 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-			        R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
+-				R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
+-				R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
+-				R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
+-			>;
+-			clock-output-names =
+-			        "sdhi2", "sdhi1", "sdhi0",
+-				"mmcif0", "i2c6", "i2c7",
+-				"cmt1", "usbdmac0", "usbdmac1";
+-		};
+-		mstp4_clks: mstp4_clks@e6150140 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+-			clocks = <&cp_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>;
+-			clock-output-names = "irqc", "intc-sys";
+-		};
+-		mstp5_clks: mstp5_clks@e6150144 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+-			clocks = <&hp_clk>, <&p_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7794_CLK_AUDIO_DMAC0
+-					 R8A7794_CLK_PWM>;
+-			clock-output-names = "audmac0", "pwm";
+-		};
+-		mstp7_clks: mstp7_clks@e615014c {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+-			clocks = <&mp_clk>, <&hp_clk>,
+-				 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+-				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+-				 <&zx_clk>, <&zx_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
+-				R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
+-				R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
+-				R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
+-				R8A7794_CLK_SCIF0
+-				R8A7794_CLK_DU1 R8A7794_CLK_DU0
+-			>;
+-			clock-output-names =
+-				"ehci", "hsusb",
+-				"hscif2", "scif5", "scif4", "hscif1", "hscif0",
+-				"scif3", "scif2", "scif1", "scif0",
+-				"du1", "du0";
+-		};
+-		mstp8_clks: mstp8_clks@e6150990 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+-			clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
+-				R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
+-			>;
+-			clock-output-names =
+-				"vin1", "vin0", "etheravb", "ether";
+-		};
+-		mstp9_clks: mstp9_clks@e6150994 {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+-			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
+-				 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
+-				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
+-					 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
+-					 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
+-					 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
+-					 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
+-					 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
+-					 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
+-					 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
+-			clock-output-names =
+-				"gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
+-				"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
+-				"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
+-		};
+-		mstp10_clks: mstp10_clks@e6150998 {
+-			compatible = "renesas,r8a7794-mstp-clocks",
+-				     "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+-			clocks = <&p_clk>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-				 <&p_clk>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+-				 <&mstp10_clks R8A7794_CLK_SCU_ALL>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7794_CLK_SSI_ALL
+-					 R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
+-					 R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
+-					 R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
+-					 R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
+-					 R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
+-					 R8A7794_CLK_SCU_ALL
+-					 R8A7794_CLK_SCU_DVC1
+-					 R8A7794_CLK_SCU_DVC0
+-					 R8A7794_CLK_SCU_CTU1_MIX1
+-					 R8A7794_CLK_SCU_CTU0_MIX0
+-					 R8A7794_CLK_SCU_SRC6
+-					 R8A7794_CLK_SCU_SRC5
+-					 R8A7794_CLK_SCU_SRC4
+-					 R8A7794_CLK_SCU_SRC3
+-					 R8A7794_CLK_SCU_SRC2
+-					 R8A7794_CLK_SCU_SRC1>;
+-			clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
+-					     "ssi6", "ssi5", "ssi4", "ssi3",
+-					     "ssi2", "ssi1", "ssi0",
+-					     "scu-all", "scu-dvc1", "scu-dvc0",
+-					     "scu-ctu1-mix1", "scu-ctu0-mix0",
+-					     "scu-src6", "scu-src5", "scu-src4",
+-					     "scu-src3", "scu-src2", "scu-src1";
+-		};
+-		mstp11_clks: mstp11_clks@e615099c {
+-			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
+-			>;
+-			clock-output-names = "scifa3", "scifa4", "scifa5";
+-		};
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+@@ -1490,31 +1133,20 @@
+ 			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+-		clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
+-			 <&mstp10_clks R8A7794_CLK_SSI9>,
+-			 <&mstp10_clks R8A7794_CLK_SSI8>,
+-			 <&mstp10_clks R8A7794_CLK_SSI7>,
+-			 <&mstp10_clks R8A7794_CLK_SSI6>,
+-			 <&mstp10_clks R8A7794_CLK_SSI5>,
+-			 <&mstp10_clks R8A7794_CLK_SSI4>,
+-			 <&mstp10_clks R8A7794_CLK_SSI3>,
+-			 <&mstp10_clks R8A7794_CLK_SSI2>,
+-			 <&mstp10_clks R8A7794_CLK_SSI1>,
+-			 <&mstp10_clks R8A7794_CLK_SSI0>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
+-			 <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
++		clocks = <&cpg CPG_MOD 1005>,
++			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++			 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
++			 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
++			 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ 			 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+-			 <&m2_clk>;
++			 <&cpg CPG_CORE R8A7794_CLK_M2>;
+ 		clock-names = "ssi-all",
+ 			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ 			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-- 
+2.19.0
+
diff --git a/patches/0303-ARM-dts-r8a7790-Stop-grouping-clocks-under-a-clocks-.patch b/patches/0303-ARM-dts-r8a7790-Stop-grouping-clocks-under-a-clocks-.patch
new file mode 100644
index 00000000000000..f1929a68e8a444
--- /dev/null
+++ b/patches/0303-ARM-dts-r8a7790-Stop-grouping-clocks-under-a-clocks-.patch
@@ -0,0 +1,169 @@
+From 1e6046d7c0b7f4390d98674a9d591a5966207104 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:16:54 +0200
+Subject: [PATCH 0303/1795] ARM: dts: r8a7790: Stop grouping clocks under a
+ "clocks" subnode
+
+The current practice is to not group clocks under a "clocks" subnode,
+but just put them together with the other on-SoC devices.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 80e1a5f318850f2bbb5fa4a49fbfa9a8f3afd5f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 137 ++++++++++++++++-----------------
+ 1 file changed, 66 insertions(+), 71 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 5a31dfc0c316..70040c6c4cea 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1061,77 +1061,72 @@
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 	};
+ 
+-	clocks {
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-
+-		/* External root clock */
+-		extal_clk: extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overriden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External PCIe clock - can be overridden by the board */
+-		pcie_bus_clk: pcie_bus {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		/*
+-		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
+-		 * default. Boards that provide audio clocks should override them.
+-		 */
+-		audio_clk_a: audio_clk_a {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_b: audio_clk_b {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_c: audio_clk_c {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External SCIF clock */
+-		scif_clk: scif {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External USB clock - can be overridden by the board */
+-		usb_extal_clk: usb_extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <48000000>;
+-		};
+-
+-		/* External CAN clock */
+-		can_clk: can {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7790-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-		};
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External USB clock - can be overridden by the board */
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <48000000>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	cpg: clock-controller@e6150000 {
++		compatible = "renesas,r8a7790-cpg-mssr";
++		reg = <0 0xe6150000 0 0x1000>;
++		clocks = <&extal_clk>, <&usb_extal_clk>;
++		clock-names = "extal", "usb_extal";
++		#clock-cells = <2>;
++		#power-domain-cells = <0>;
+ 	};
+ 
+ 	prr: chipid@ff000044 {
+-- 
+2.19.0
+
diff --git a/patches/0304-ARM-dts-r8a7793-Stop-grouping-clocks-under-a-clocks-.patch b/patches/0304-ARM-dts-r8a7793-Stop-grouping-clocks-under-a-clocks-.patch
new file mode 100644
index 00000000000000..a0b01a30d58291
--- /dev/null
+++ b/patches/0304-ARM-dts-r8a7793-Stop-grouping-clocks-under-a-clocks-.patch
@@ -0,0 +1,157 @@
+From 33ad27d7d8b0b7937d1a9d36e0c6c5862771aadf Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:16:56 +0200
+Subject: [PATCH 0304/1795] ARM: dts: r8a7793: Stop grouping clocks under a
+ "clocks" subnode
+
+The current practice is to not group clocks under a "clocks" subnode,
+but just put them together with the other on-SoC devices.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c67e243ccf06aec0fece59b8a1f3eb719e07b0e3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 125 ++++++++++++++++-----------------
+ 1 file changed, 60 insertions(+), 65 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index ef8009c01e66..d48b97c853cd 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -972,71 +972,66 @@
+ 		status = "disabled";
+ 	};
+ 
+-	clocks {
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-
+-		/* External root clock */
+-		extal_clk: extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/*
+-		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
+-		 * default. Boards that provide audio clocks should override them.
+-		 */
+-		audio_clk_a: audio_clk_a {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_b: audio_clk_b {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_c: audio_clk_c {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External USB clock - can be overridden by the board */
+-		usb_extal_clk: usb_extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <48000000>;
+-		};
+-
+-		/* External CAN clock */
+-		can_clk: can {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External SCIF clock */
+-		scif_clk: scif {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* Special CPG clocks */
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7793-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-		};
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External USB clock - can be overridden by the board */
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <48000000>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* Special CPG clocks */
++	cpg: clock-controller@e6150000 {
++		compatible = "renesas,r8a7793-cpg-mssr";
++		reg = <0 0xe6150000 0 0x1000>;
++		clocks = <&extal_clk>, <&usb_extal_clk>;
++		clock-names = "extal", "usb_extal";
++		#clock-cells = <2>;
++		#power-domain-cells = <0>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+-- 
+2.19.0
+
diff --git a/patches/0305-ARM-dts-r8a7794-Stop-grouping-clocks-under-a-clocks-.patch b/patches/0305-ARM-dts-r8a7794-Stop-grouping-clocks-under-a-clocks-.patch
new file mode 100644
index 00000000000000..d5589c3c6a50f7
--- /dev/null
+++ b/patches/0305-ARM-dts-r8a7794-Stop-grouping-clocks-under-a-clocks-.patch
@@ -0,0 +1,156 @@
+From 8c44d94c9599cb1c2ddefc5224b168eb4b07686a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 Aug 2017 11:16:57 +0200
+Subject: [PATCH 0305/1795] ARM: dts: r8a7794: Stop grouping clocks under a
+ "clocks" subnode
+
+The current practice is to not group clocks under a "clocks" subnode,
+but just put them together with the other on-SoC devices.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9fb1c8ff4ca36a13fdeb7e4161687eaf4685dc7a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 124 ++++++++++++++++-----------------
+ 1 file changed, 59 insertions(+), 65 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index ebd44d9982be..a4c35d29f77c 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -982,71 +982,65 @@
+ 		status = "disabled";
+ 	};
+ 
+-	clocks {
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-
+-		/* External root clock */
+-		extal_clk: extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overriden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External USB clock - can be overridden by the board */
+-		usb_extal_clk: usb_extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <48000000>;
+-		};
+-
+-		/* External CAN clock */
+-		can_clk: can {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External SCIF clock */
+-		scif_clk: scif {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/*
+-		 * The external audio clocks are configured  as 0 Hz fixed
+-		 * frequency clocks by default.  Boards that provide audio
+-		 * clocks should override them.
+-		 */
+-		audio_clka: audio_clka {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clkb: audio_clkb {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clkc: audio_clkc {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7794-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-		};
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External USB clock - can be overridden by the board */
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <48000000>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/*
++	 * The external audio clocks are configured  as 0 Hz fixed
++	 * frequency clocks by default.  Boards that provide audio
++	 * clocks should override them.
++	 */
++	audio_clka: audio_clka {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkb: audio_clkb {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkc: audio_clkc {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	cpg: clock-controller@e6150000 {
++		compatible = "renesas,r8a7794-cpg-mssr";
++		reg = <0 0xe6150000 0 0x1000>;
++		clocks = <&extal_clk>, <&usb_extal_clk>;
++		clock-names = "extal", "usb_extal";
++		#clock-cells = <2>;
++		#power-domain-cells = <0>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+-- 
+2.19.0
+
diff --git a/patches/0306-ARM-dts-r8a7743-Add-SDHI-controllers.patch b/patches/0306-ARM-dts-r8a7743-Add-SDHI-controllers.patch
new file mode 100644
index 00000000000000..8409edbdbb5be2
--- /dev/null
+++ b/patches/0306-ARM-dts-r8a7743-Add-SDHI-controllers.patch
@@ -0,0 +1,72 @@
+From 3bd4a3000be77a1f40473b278ba04aa67c72e819 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 14 Aug 2017 12:49:47 +0100
+Subject: [PATCH 0306/1795] ARM: dts: r8a7743: Add SDHI controllers
+
+Add the SDHI controllers to the r8a7743 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 63ce8a617b5129f7cb20ed0d6d822a31ecca4696)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 42 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 14222c72f0e0..6dd9b0b3d818 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -779,6 +779,48 @@
+ 			max-frequency = <97500000>;
+ 			status = "disabled";
+ 		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7743";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7743";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7743";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0307-ARM-dts-iwg20m-Enable-SDHI0-controller.patch b/patches/0307-ARM-dts-iwg20m-Enable-SDHI0-controller.patch
new file mode 100644
index 00000000000000..a5a6579e67a2de
--- /dev/null
+++ b/patches/0307-ARM-dts-iwg20m-Enable-SDHI0-controller.patch
@@ -0,0 +1,59 @@
+From c14967645b8e04d829852b843e520c93d6d50325 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 14 Aug 2017 12:49:48 +0100
+Subject: [PATCH 0307/1795] ARM: dts: iwg20m: Enable SDHI0 controller
+
+Enable the SDHI0 controller on iWave RZG1M Qseven SOM.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e75e71e7bcee2e04be8bbca6fb67af1a45fa128b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+index ff7993818637..4119737cb883 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
++++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+@@ -9,6 +9,7 @@
+  */
+ 
+ #include "r8a7743.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	compatible = "iwave,g20m", "renesas,r8a7743";
+@@ -42,6 +43,12 @@
+ 		groups = "mmc_data8_b", "mmc_ctrl";
+ 		function = "mmc";
+ 	};
++
++	sdhi0_pins: sd0 {
++		groups = "sdhi0_data4", "sdhi0_ctrl";
++		function = "sdhi0";
++		power-source = <3300>;
++	};
+ };
+ 
+ &mmcif0 {
+@@ -53,3 +60,13 @@
+ 	non-removable;
+ 	status = "okay";
+ };
++
++&sdhi0 {
++	pinctrl-0 = <&sdhi0_pins>;
++	pinctrl-names = "default";
++
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
++	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0308-ARM-Add-definition-for-monitor-mode.patch b/patches/0308-ARM-Add-definition-for-monitor-mode.patch
new file mode 100644
index 00000000000000..f39d94ba154896
--- /dev/null
+++ b/patches/0308-ARM-Add-definition-for-monitor-mode.patch
@@ -0,0 +1,36 @@
+From 71ff1cae2dbd2d97a919ff99d5ab03d5cd784e4e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 1 Sep 2017 10:37:44 +0200
+Subject: [PATCH 0308/1795] ARM: Add definition for monitor mode
+
+<asm/ptrace.h> provides *_MODE definitions for the various processor
+modes, but monitor mode was missing.
+
+Add MON_MODE to avoid code using the hardcoded value.
+
+Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c5d43be52e0c7380f985585ef72dac1a6a89b59d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/include/uapi/asm/ptrace.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
+index b67cda536c25..a9aa6acbf1bf 100644
+--- a/arch/arm/include/uapi/asm/ptrace.h
++++ b/arch/arm/include/uapi/asm/ptrace.h
+@@ -54,6 +54,7 @@
+ #endif
+ #define FIQ_MODE	0x00000011
+ #define IRQ_MODE	0x00000012
++#define MON_MODE	0x00000016
+ #define ABT_MODE	0x00000017
+ #define HYP_MODE	0x0000001a
+ #define UND_MODE	0x0000001b
+-- 
+2.19.0
+
diff --git a/patches/0309-ARM-shmobile-rcar-gen2-Make-sure-CNTVOFF-is-initiali.patch b/patches/0309-ARM-shmobile-rcar-gen2-Make-sure-CNTVOFF-is-initiali.patch
new file mode 100644
index 00000000000000..8dfa2e59daf82d
--- /dev/null
+++ b/patches/0309-ARM-shmobile-rcar-gen2-Make-sure-CNTVOFF-is-initiali.patch
@@ -0,0 +1,176 @@
+From 4f747caaec0cf4659c925252288b55d9b995b1e9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 1 Sep 2017 10:37:45 +0200
+Subject: [PATCH 0309/1795] ARM: shmobile: rcar-gen2: Make sure CNTVOFF is
+ initialized on CA7/15
+
+On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
+Ideally it should be initialized by the boot loader, but it isn't.
+
+For the boot CPU, CNTVOFF is initialized by Linux since commit
+9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
+initialization for r8a7794").
+For secondary CPU cores, no such initialization is done.
+
+Hence when enabling SMP on r8a7794, the kernel log is spammed with:
+
+    WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
+	     Please report this, consider using a different clocksource, if possible.
+	     Your kernel is probably still fine.
+
+As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
+respect to CNTVOFF, we have been very lucky this just worked on R-Car
+Gen2 SoCs with Cortex-A15 cores.
+
+To fix this:
+  - Move the existing inline asm code to initialize CNTVOFF to an
+    assembler source file (adding comments and replacing hardcoded
+    constants by definitions in the process), so it can be reused,
+  - Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
+    Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
+  - Wrap the standard secondary_startup() routine inside a routine which
+    initializes CNTVOFF.
+
+Based on patches by Hisashi Nakamura in the BSP.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3fd45a136ff61bb54deab70fb2d534a85e40481f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/Makefile          |  1 +
+ arch/arm/mach-shmobile/common.h          |  2 ++
+ arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++
+ arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
+ arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++-----------
+ 5 files changed, 43 insertions(+), 19 deletions(-)
+ create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
+
+diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
+index e16b81ec4b07..1939f521579c 100644
+--- a/arch/arm/mach-shmobile/Makefile
++++ b/arch/arm/mach-shmobile/Makefile
+@@ -23,6 +23,7 @@ cpu-y				:= platsmp.o headsmp.o
+ # Shared SoC family objects
+ obj-$(CONFIG_ARCH_RCAR_GEN2)	+= setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
+ CFLAGS_setup-rcar-gen2.o	+= -march=armv7-a
++obj-$(CONFIG_ARCH_RCAR_GEN2)	+= headsmp-apmu.o
+ obj-$(CONFIG_ARCH_R8A7790)	+= regulator-quirk-rcar-gen2.o
+ obj-$(CONFIG_ARCH_R8A7791)	+= regulator-quirk-rcar-gen2.o
+ obj-$(CONFIG_ARCH_R8A7793)	+= regulator-quirk-rcar-gen2.o
+diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
+index f8fcd799d677..a8fa4f7e1f60 100644
+--- a/arch/arm/mach-shmobile/common.h
++++ b/arch/arm/mach-shmobile/common.h
+@@ -2,6 +2,7 @@
+ #ifndef __ARCH_MACH_COMMON_H
+ #define __ARCH_MACH_COMMON_H
+ 
++extern void shmobile_init_cntvoff(void);
+ extern void shmobile_init_delay(void);
+ extern void shmobile_boot_vector(void);
+ extern unsigned long shmobile_boot_fn;
+@@ -12,6 +13,7 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
+ 			      unsigned long arg);
+ extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
+ extern bool shmobile_smp_init_fallback_ops(void);
++extern void shmobile_boot_apmu(void);
+ extern void shmobile_boot_scu(void);
+ extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
+ 					  unsigned int max_cpus);
+diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
+new file mode 100644
+index 000000000000..db4743d2bf91
+--- /dev/null
++++ b/arch/arm/mach-shmobile/headsmp-apmu.S
+@@ -0,0 +1,37 @@
++/*
++ * SMP support for APMU based systems with Cortex A7/A15
++ *
++ * Copyright (C) 2014  Renesas Electronics Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++
++ENTRY(shmobile_init_cntvoff)
++	/*
++	 * CNTVOFF has to be initialized either from non-secure Hypervisor
++	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
++	 * then it should be handled by the secure code
++	 */
++	cps	#MON_MODE
++	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
++	orr	r0, r1, #1
++	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
++	instr_sync
++	mov	r0, #0
++	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
++	instr_sync
++	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
++	instr_sync
++	cps	#SVC_MODE
++	ret	lr
++ENDPROC(shmobile_init_cntvoff)
++
++ENTRY(shmobile_boot_apmu)
++	bl	shmobile_init_cntvoff
++	b	secondary_startup
++ENDPROC(shmobile_boot_apmu)
+diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
+index 3ca2c13346f0..4422b615a6ee 100644
+--- a/arch/arm/mach-shmobile/platsmp-apmu.c
++++ b/arch/arm/mach-shmobile/platsmp-apmu.c
+@@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+ int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
+ {
+ 	/* For this particular CPU register boot vector */
+-	shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
++	shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
+ 
+ 	return apmu_wrap(cpu, apmu_power_on);
+ }
+diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+index 7ab1690fab82..5561dbed7a33 100644
+--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+@@ -70,28 +70,12 @@ void __init rcar_gen2_timer_init(void)
+ 	void __iomem *base;
+ 	u32 freq;
+ 
++	shmobile_init_cntvoff();
++
+ 	if (of_machine_is_compatible("renesas,r8a7745") ||
+ 	    of_machine_is_compatible("renesas,r8a7792") ||
+ 	    of_machine_is_compatible("renesas,r8a7794")) {
+ 		freq = 260000000 / 8;	/* ZS / 8 */
+-		/* CNTVOFF has to be initialized either from non-secure
+-		 * Hypervisor mode or secure Monitor mode with SCR.NS==1.
+-		 * If TrustZone is enabled then it should be handled by the
+-		 * secure code.
+-		 */
+-		asm volatile(
+-		"	cps	0x16\n"
+-		"	mrc	p15, 0, r1, c1, c1, 0\n"
+-		"	orr	r0, r1, #1\n"
+-		"	mcr	p15, 0, r0, c1, c1, 0\n"
+-		"	isb\n"
+-		"	mov	r0, #0\n"
+-		"	mcrr	p15, 4, r0, r0, c14\n"
+-		"	isb\n"
+-		"	mcr	p15, 0, r1, c1, c1, 0\n"
+-		"	isb\n"
+-		"	cps	0x13\n"
+-			: : : "r0", "r1");
+ 	} else {
+ 		/* At Linux boot time the r8a7790 arch timer comes up
+ 		 * with the counter disabled. Moreover, it may also report
+-- 
+2.19.0
+
diff --git a/patches/0310-ARM-dts-iwg20d-q7-Add-SDHI1-support.patch b/patches/0310-ARM-dts-iwg20d-q7-Add-SDHI1-support.patch
new file mode 100644
index 00000000000000..91979987b7b34b
--- /dev/null
+++ b/patches/0310-ARM-dts-iwg20d-q7-Add-SDHI1-support.patch
@@ -0,0 +1,91 @@
+From f479f8119f907eb1330b3ac96aeb84807c37ff84 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 14 Aug 2017 12:49:49 +0100
+Subject: [PATCH 0310/1795] ARM: dts: iwg20d-q7: Add SDHI1 support
+
+Define the iWave RainboW-G20D-Qseven board dependent part of the
+SDHI1 device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 029efb3a03c5039902a6f1cfe266ed664cb97f20)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index 081af0192851..4ff27d23ecf0 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -19,6 +19,29 @@
+ 		serial0 = &scif0;
+ 		ethernet0 = &avb;
+ 	};
++
++	vcc_sdhi1: regulator-vcc-sdhi1 {
++		compatible = "regulator-fixed";
++
++		regulator-name = "SDHI1 Vcc";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
++	};
++
++	vccq_sdhi1: regulator-vccq-sdhi1 {
++		compatible = "regulator-gpio";
++
++		regulator-name = "SDHI1 VccQ";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
++		gpios-states = <1>;
++		states = <3300000 1
++			  1800000 0>;
++	};
+ };
+ 
+ &pfc {
+@@ -31,6 +54,18 @@
+ 		groups = "avb_mdio", "avb_gmii";
+ 		function = "avb";
+ 	};
++
++	sdhi1_pins: sd1 {
++		groups = "sdhi1_data4", "sdhi1_ctrl";
++		function = "sdhi1";
++		power-source = <3300>;
++	};
++
++	sdhi1_pins_uhs: sd1_uhs {
++		groups = "sdhi1_data4", "sdhi1_ctrl";
++		function = "sdhi1";
++		power-source = <1800>;
++	};
+ };
+ 
+ &scif0 {
+@@ -54,3 +89,16 @@
+ 		micrel,led-mode = <1>;
+ 	};
+ };
++
++&sdhi1 {
++	pinctrl-0 = <&sdhi1_pins>;
++	pinctrl-1 = <&sdhi1_pins_uhs>;
++	pinctrl-names = "default", "state_uhs";
++
++	vmmc-supply = <&vcc_sdhi1>;
++	vqmmc-supply = <&vccq_sdhi1>;
++	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
++	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
++	sd-uhs-sdr50;
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0311-ARM-dts-r8a7745-Add-GPIO-support.patch b/patches/0311-ARM-dts-r8a7745-Add-GPIO-support.patch
new file mode 100644
index 00000000000000..42d05022981795
--- /dev/null
+++ b/patches/0311-ARM-dts-r8a7745-Add-GPIO-support.patch
@@ -0,0 +1,135 @@
+From 576ce10d5a13723cd99456066585e26805e118d7 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 18 Aug 2017 15:56:01 +0100
+Subject: [PATCH 0311/1795] ARM: dts: r8a7745: Add GPIO support
+
+Describe GPIO blocks in the R8A7745 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3163c03ec37aef502474122b857452fb948c7596)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 105 +++++++++++++++++++++++++++++++++
+ 1 file changed, 105 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index aff90dfb8b32..18ca7ae8dd3f 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -65,6 +65,111 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
++
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
++
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
++
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
++
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
++
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 28>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
++
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a7745",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 905>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 905>;
++		};
++
+ 		irqc: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0312-ARM-dts-iwg22m-Add-iWave-RZG1E-SODIMM-SOM.patch b/patches/0312-ARM-dts-iwg22m-Add-iWave-RZG1E-SODIMM-SOM.patch
new file mode 100644
index 00000000000000..0dc81afdf5ed8e
--- /dev/null
+++ b/patches/0312-ARM-dts-iwg22m-Add-iWave-RZG1E-SODIMM-SOM.patch
@@ -0,0 +1,51 @@
+From c24a340b9b80b70771f31a9c383789df541a23c9 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 15 Aug 2017 11:54:19 +0100
+Subject: [PATCH 0312/1795] ARM: dts: iwg22m: Add iWave RZG1E SODIMM SOM
+
+Add support for iWave RZG1E SODIMM System On Module.
+http://www.iwavesystems.com/rz-g1e-sodimm-module.html
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c9a41f515d1e5955c44cb04926f5f5f4be4a0cd0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+new file mode 100644
+index 000000000000..9dbd854aacf8
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -0,0 +1,24 @@
++/*
++ * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7745.dtsi"
++
++/ {
++	compatible = "iwave,g22m", "renesas,r8a7745";
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0 0x40000000 0 0x20000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <20000000>;
++};
+-- 
+2.19.0
+
diff --git a/patches/0313-ARM-dts-iwg22d-sodimm-Add-support-for-iWave-G22D-SOD.patch b/patches/0313-ARM-dts-iwg22d-sodimm-Add-support-for-iWave-G22D-SOD.patch
new file mode 100644
index 00000000000000..d21ae705b570fe
--- /dev/null
+++ b/patches/0313-ARM-dts-iwg22d-sodimm-Add-support-for-iWave-G22D-SOD.patch
@@ -0,0 +1,69 @@
+From d2f84c54f891ecf34b39b16f18fb99ad0d71967b Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 15 Aug 2017 11:54:20 +0100
+Subject: [PATCH 0313/1795] ARM: dts: iwg22d-sodimm: Add support for iWave
+ G22D-SODIMM board
+
+Add support for iWave RainboW-G22D-SODIMM board based on RZ/G1E.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a59eb272a4eae10eb4f7a3e7b15aa47d57b32699)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/Makefile                  |  1 +
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++
+ 2 files changed, 30 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 300f441698fb..2fca3799bef6 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -726,6 +726,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
+ 	r8a7740-armadillo800eva.dtb \
+ 	r8a7743-iwg20d-q7.dtb \
+ 	r8a7743-sk-rzg1m.dtb \
++	r8a7745-iwg22d-sodimm.dtb \
+ 	r8a7745-sk-rzg1e.dtb \
+ 	r8a7778-bockw.dtb \
+ 	r8a7779-marzen.dtb \
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+new file mode 100644
+index 000000000000..cbc19feb1565
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -0,0 +1,29 @@
++/*
++ * Device Tree Source for the iWave-RZG1E SODIMM carrier board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a7745-iwg22m.dtsi"
++
++/ {
++	model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
++	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
++
++	aliases {
++		serial0 = &scif4;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
++
++&scif4 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0314-ARM-dts-r8a7745-Add-I2C-DT-support.patch b/patches/0314-ARM-dts-r8a7745-Add-I2C-DT-support.patch
new file mode 100644
index 00000000000000..f19a11a863d4db
--- /dev/null
+++ b/patches/0314-ARM-dts-r8a7745-Add-I2C-DT-support.patch
@@ -0,0 +1,130 @@
+From 6378b07982ccf1cbc2c8de7362f6fb09d1837e16 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 22 Aug 2017 16:27:02 +0100
+Subject: [PATCH 0314/1795] ARM: dts: r8a7745: Add I2C DT support
+
+Add I2C[0-5] devices to the r8a7745 device tree.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 282fbf4066e58b4c60683ab5cba30c5c998c7250)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 93 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 18ca7ae8dd3f..2fa989f631a9 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -18,6 +18,15 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		i2c5 = &i2c5;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -613,6 +622,90 @@
+ 			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
++
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c4: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c5: i2c@e6528000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0315-ARM-dts-r8a7745-Add-MMC-interface-support.patch b/patches/0315-ARM-dts-r8a7745-Add-MMC-interface-support.patch
new file mode 100644
index 00000000000000..55008979774b28
--- /dev/null
+++ b/patches/0315-ARM-dts-r8a7745-Add-MMC-interface-support.patch
@@ -0,0 +1,46 @@
+From 47981b7b3054ad0f1e3689368412c0980c34629d Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 17 Aug 2017 18:31:42 +0100
+Subject: [PATCH 0315/1795] ARM: dts: r8a7745: Add MMC interface support
+
+Add MMC interface support for r8a7745 SoC.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 933b16efb7be16e98a6bcd04ed59c5e91371afef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 2fa989f631a9..7fd2967b1f42 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -706,6 +706,22 @@
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7745",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			max-frequency = <97500000>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0316-ARM-dts-iwg22m-Add-eMMC-support.patch b/patches/0316-ARM-dts-iwg22m-Add-eMMC-support.patch
new file mode 100644
index 00000000000000..3a7af69827c687
--- /dev/null
+++ b/patches/0316-ARM-dts-iwg22m-Add-eMMC-support.patch
@@ -0,0 +1,58 @@
+From 5ace30c5e4e493be141e14ea7ce06689568a9731 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 17 Aug 2017 18:31:43 +0100
+Subject: [PATCH 0316/1795] ARM: dts: iwg22m: Add eMMC support
+
+Add eMMC support for iW-RainboW-G22M-SM.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3350ed907182049b806992f228021e7997183dda)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index 9dbd854aacf8..afb1148baa2f 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -17,8 +17,34 @@
+ 		device_type = "memory";
+ 		reg = <0 0x40000000 0 0x20000000>;
+ 	};
++
++	reg_3p3v: 3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "3P3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
+ };
+ 
+ &extal_clk {
+ 	clock-frequency = <20000000>;
+ };
++
++&pfc {
++	mmcif0_pins: mmc {
++		groups = "mmc_data8", "mmc_ctrl";
++		function = "mmc";
++	};
++};
++
++&mmcif0 {
++	pinctrl-0 = <&mmcif0_pins>;
++	pinctrl-names = "default";
++
++	vmmc-supply = <&reg_3p3v>;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0317-ARM-dts-iwg22m-Add-RTC-support.patch b/patches/0317-ARM-dts-iwg22m-Add-RTC-support.patch
new file mode 100644
index 00000000000000..64133f53720fbb
--- /dev/null
+++ b/patches/0317-ARM-dts-iwg22m-Add-RTC-support.patch
@@ -0,0 +1,52 @@
+From 4e37e633d67abb5e400255802f7caa72da39ed4c Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 22 Aug 2017 19:22:46 +0100
+Subject: [PATCH 0317/1795] ARM: dts: iwg22m: Add RTC support
+
+Add support for the bq32000 RTC to the iwg22m device tree.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a7b8f48d2fa14330a1886f7fd640187c8b4470c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index afb1148baa2f..e306e7c5b644 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -37,6 +37,11 @@
+ 		groups = "mmc_data8", "mmc_ctrl";
+ 		function = "mmc";
+ 	};
++
++	i2c3_pins: i2c3 {
++		groups = "i2c3_b";
++		function = "i2c3";
++	};
+ };
+ 
+ &mmcif0 {
+@@ -48,3 +53,16 @@
+ 	non-removable;
+ 	status = "okay";
+ };
++
++&i2c3 {
++	pinctrl-0 = <&i2c3_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	rtc@68 {
++		compatible = "ti,bq32000";
++		reg = <0x68>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0318-ARM-dts-r8a7791-Convert-to-new-CPG-MSSR-bindings.patch b/patches/0318-ARM-dts-r8a7791-Convert-to-new-CPG-MSSR-bindings.patch
new file mode 100644
index 00000000000000..bea66ed14a55fe
--- /dev/null
+++ b/patches/0318-ARM-dts-r8a7791-Convert-to-new-CPG-MSSR-bindings.patch
@@ -0,0 +1,1174 @@
+From 553c0b129c47bd15e679113af208e03a799f27d1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 23 Aug 2017 13:59:25 +0200
+Subject: [PATCH 0318/1795] ARM: dts: r8a7791: Convert to new CPG/MSSR bindings
+
+Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse
+Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
+(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
+Generator / Module Standby and Software Reset" DT bindings.
+
+This simplifies the DTS files, and allows to add support for reset
+control later.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 362b334b17943d84d2878d2733f0ce695d45a2b6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts |   4 +-
+ arch/arm/boot/dts/r8a7791-porter.dts  |   4 +-
+ arch/arm/boot/dts/r8a7791.dtsi        | 557 +++++---------------------
+ 3 files changed, 104 insertions(+), 461 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index 25c3a10d669c..4126de417922 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -336,9 +336,7 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+-		 <&mstp7_clks R8A7791_CLK_DU1>,
+-		 <&mstp7_clks R8A7791_CLK_LVDS0>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ 		 <&x13_clk>, <&x2_clk>;
+ 	clock-names = "du.0", "du.1", "lvds.0",
+ 		      "dclkin.0", "dclkin.1";
+diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
+index b6ebe79261c6..9a02d03b23c2 100644
+--- a/arch/arm/boot/dts/r8a7791-porter.dts
++++ b/arch/arm/boot/dts/r8a7791-porter.dts
+@@ -419,9 +419,7 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+-		 <&mstp7_clks R8A7791_CLK_DU1>,
+-		 <&mstp7_clks R8A7791_CLK_LVDS0>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
+ 		 <&x3_clk>, <&x16_clk>;
+ 	clock-names = "du.0", "du.1", "lvds.0",
+ 		      "dclkin.0", "dclkin.1";
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index f1d1a9772153..5fca397b722b 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -10,7 +10,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/r8a7791-clock.h>
++#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+@@ -51,7 +51,7 @@
+ 			reg = <0>;
+ 			clock-frequency = <1500000000>;
+ 			voltage-tolerance = <1>; /* 1% */
+-			clocks = <&cpg_clocks R8A7791_CLK_Z>;
++			clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
+ 			clock-latency = <300000>; /* 300 us */
+ 			power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+ 			next-level-cache = <&L2_CA15>;
+@@ -117,7 +117,7 @@
+ 			<0 0xf1004000 0 0x2000>,
+ 			<0 0xf1006000 0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
++		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+@@ -131,7 +131,7 @@
+ 		gpio-ranges = <&pfc 0 0 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
++		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -144,7 +144,7 @@
+ 		gpio-ranges = <&pfc 0 32 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
++		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -157,7 +157,7 @@
+ 		gpio-ranges = <&pfc 0 64 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
++		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -170,7 +170,7 @@
+ 		gpio-ranges = <&pfc 0 96 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
++		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -183,7 +183,7 @@
+ 		gpio-ranges = <&pfc 0 128 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
++		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -196,7 +196,7 @@
+ 		gpio-ranges = <&pfc 0 160 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
++		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -209,7 +209,7 @@
+ 		gpio-ranges = <&pfc 0 192 32>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
++		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -222,7 +222,7 @@
+ 		gpio-ranges = <&pfc 0 224 26>;
+ 		#interrupt-cells = <2>;
+ 		interrupt-controller;
+-		clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
++		clocks = <&cpg CPG_MOD 904>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -232,7 +232,7 @@
+ 				"renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
++		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+@@ -250,7 +250,7 @@
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
++		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 
+@@ -270,7 +270,7 @@
+ 			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
++		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 
+@@ -294,7 +294,7 @@
+ 			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
++		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -322,7 +322,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
++		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -353,7 +353,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12", "ch13", "ch14";
+-		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
++		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -382,7 +382,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
++		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -411,7 +411,7 @@
+ 				"ch4", "ch5", "ch6", "ch7",
+ 				"ch8", "ch9", "ch10", "ch11",
+ 				"ch12";
+-		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
++		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+@@ -424,7 +424,7 @@
+ 		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ 			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "ch0", "ch1";
+-		clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
++		clocks = <&cpg CPG_MOD 330>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+@@ -436,7 +436,7 @@
+ 		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ 			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "ch0", "ch1";
+-		clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
++		clocks = <&cpg CPG_MOD 331>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+@@ -449,7 +449,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6508000 0 0x40>;
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
++		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -461,7 +461,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6518000 0 0x40>;
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
++		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -473,7 +473,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6530000 0 0x40>;
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
++		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -485,7 +485,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6540000 0 0x40>;
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
++		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -497,7 +497,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6520000 0 0x40>;
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
++		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+@@ -510,7 +510,7 @@
+ 		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ 		reg = <0 0xe6528000 0 0x40>;
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
++		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+@@ -524,7 +524,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe60b0000 0 0x425>;
+ 		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
++		clocks = <&cpg CPG_MOD 926>;
+ 		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -539,7 +539,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6500000 0 0x425>;
+ 		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
++		clocks = <&cpg CPG_MOD 318>;
+ 		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -554,7 +554,7 @@
+ 			     "renesas,rmobile-iic";
+ 		reg = <0 0xe6510000 0 0x425>;
+ 		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
++		clocks = <&cpg CPG_MOD 323>;
+ 		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -571,7 +571,7 @@
+ 		compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
+ 		reg = <0 0xee200000 0 0x80>;
+ 		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
++		clocks = <&cpg CPG_MOD 315>;
+ 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -585,7 +585,7 @@
+ 		compatible = "renesas,sdhi-r8a7791";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
++		clocks = <&cpg CPG_MOD 314>;
+ 		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ 		       <&dmac1 0xcd>, <&dmac1 0xce>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -598,7 +598,7 @@
+ 		compatible = "renesas,sdhi-r8a7791";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
++		clocks = <&cpg CPG_MOD 312>;
+ 		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ 		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -611,7 +611,7 @@
+ 		compatible = "renesas,sdhi-r8a7791";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
++		clocks = <&cpg CPG_MOD 311>;
+ 		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ 		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -625,7 +625,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c40000 0 64>;
+ 		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
++		clocks = <&cpg CPG_MOD 204>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+@@ -639,7 +639,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c50000 0 64>;
+ 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
++		clocks = <&cpg CPG_MOD 203>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+@@ -653,7 +653,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c60000 0 64>;
+ 		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
++		clocks = <&cpg CPG_MOD 202>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+@@ -667,7 +667,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c70000 0 64>;
+ 		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
++		clocks = <&cpg CPG_MOD 1106>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+@@ -681,7 +681,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c78000 0 64>;
+ 		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
++		clocks = <&cpg CPG_MOD 1107>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+@@ -695,7 +695,7 @@
+ 			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+ 		reg = <0 0xe6c80000 0 64>;
+ 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
++		clocks = <&cpg CPG_MOD 1108>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+@@ -709,7 +709,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c20000 0 0x100>;
+ 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
++		clocks = <&cpg CPG_MOD 206>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+@@ -723,7 +723,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6c30000 0 0x100>;
+ 		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
++		clocks = <&cpg CPG_MOD 207>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+@@ -737,7 +737,7 @@
+ 			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+ 		reg = <0 0xe6ce0000 0 0x100>;
+ 		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
++		clocks = <&cpg CPG_MOD 216>;
+ 		clock-names = "fck";
+ 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+@@ -751,7 +751,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e60000 0 64>;
+ 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+@@ -766,7 +766,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e68000 0 64>;
+ 		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+@@ -779,7 +779,7 @@
+ 	adc: adc@e6e54000 {
+ 		compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ 		reg = <0 0xe6e54000 0 64>;
+-		clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
++		clocks = <&cpg CPG_MOD 901>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -790,7 +790,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6e58000 0 64>;
+ 		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+@@ -805,7 +805,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ea8000 0 64>;
+ 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+@@ -820,7 +820,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee0000 0 64>;
+ 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+@@ -835,7 +835,7 @@
+ 			     "renesas,scif";
+ 		reg = <0 0xe6ee8000 0 64>;
+ 		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+@@ -850,7 +850,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c0000 0 96>;
+ 		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+@@ -865,7 +865,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62c8000 0 96>;
+ 		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+@@ -880,7 +880,7 @@
+ 			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+ 		reg = <0 0xe62d0000 0 96>;
+ 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
++		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ 			 <&scif_clk>;
+ 		clock-names = "fck", "brg_int", "scif_clk";
+ 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+@@ -912,7 +912,7 @@
+ 		compatible = "renesas,ether-r8a7791";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
++		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+@@ -925,7 +925,7 @@
+ 			     "renesas,etheravb-rcar-gen2";
+ 		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
++		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -936,7 +936,7 @@
+ 		compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ 		reg = <0 0xee300000 0 0x2000>;
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
++		clocks = <&cpg CPG_MOD 815>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -945,7 +945,7 @@
+ 		compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ 		reg = <0 0xee500000 0 0x2000>;
+ 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
++		clocks = <&cpg CPG_MOD 814>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -954,7 +954,7 @@
+ 		compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
+ 		reg = <0 0xe6590000 0 0x100>;
+ 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+ 		dma-names = "ch0", "ch1", "ch2", "ch3";
+@@ -971,7 +971,7 @@
+ 		reg = <0 0xe6590100 0 0x100>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
++		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -990,7 +990,7 @@
+ 		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef0000 0 0x1000>;
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
++		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -999,7 +999,7 @@
+ 		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef1000 0 0x1000>;
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
++		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -1008,7 +1008,7 @@
+ 		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+ 		reg = <0 0xe6ef2000 0 0x1000>;
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
++		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 	};
+@@ -1017,7 +1017,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
++		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1025,7 +1025,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
++		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1033,7 +1033,7 @@
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe938000 0 0x8000>;
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
++		clocks = <&cpg CPG_MOD 127>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1044,9 +1044,9 @@
+ 		reg-names = "du", "lvds.0";
+ 		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+-			 <&mstp7_clks R8A7791_CLK_DU1>,
+-			 <&mstp7_clks R8A7791_CLK_LVDS0>;
++		clocks = <&cpg CPG_MOD 724>,
++			 <&cpg CPG_MOD 723>,
++			 <&cpg CPG_MOD 726>;
+ 		clock-names = "du.0", "du.1", "lvds.0";
+ 		status = "disabled";
+ 
+@@ -1071,8 +1071,8 @@
+ 		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e80000 0 0x1000>;
+ 		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
+-			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1082,8 +1082,8 @@
+ 		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+ 		reg = <0 0xe6e88000 0 0x1000>;
+ 		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
+-			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
++		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
++			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1093,7 +1093,7 @@
+ 		compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
+ 		reg = <0 0xfe980000 0 0x10300>;
+ 		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp1_clks R8A7791_CLK_JPU>;
++		clocks = <&cpg CPG_MOD 106>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+@@ -1160,368 +1160,14 @@
+ 			clock-frequency = <0>;
+ 		};
+ 
+-		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@e6150000 {
+-			compatible = "renesas,r8a7791-cpg-clocks",
+-				     "renesas,rcar-gen2-cpg-clocks";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7791-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk &usb_extal_clk>;
+-			#clock-cells = <1>;
+-			clock-output-names = "main", "pll0", "pll1", "pll3",
+-					     "lb", "qspi", "sdh", "sd0", "z",
+-					     "rcan", "adsp";
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
+ 		};
+-
+-		/* Variable factor clocks */
+-		sd2_clk: sd2@e6150078 {
+-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150078 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		sd3_clk: sd3@e615026c {
+-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe615026c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		mmc0_clk: mmc0@e6150240 {
+-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150240 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		ssp_clk: ssp@e6150248 {
+-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe6150248 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-		ssprs_clk: ssprs@e615024c {
+-			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+-			reg = <0 0xe615024c 0 4>;
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-		};
+-
+-		/* Fixed factor clocks */
+-		pll1_div2_clk: pll1_div2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		zg_clk: zg {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zx_clk: zx {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <3>;
+-			clock-mult = <1>;
+-		};
+-		zs_clk: zs {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <6>;
+-			clock-mult = <1>;
+-		};
+-		hp_clk: hp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		i_clk: i {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-		b_clk: b {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <12>;
+-			clock-mult = <1>;
+-		};
+-		p_clk: p {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <24>;
+-			clock-mult = <1>;
+-		};
+-		cl_clk: cl {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <48>;
+-			clock-mult = <1>;
+-		};
+-		m2_clk: m2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		rclk_clk: rclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(48 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		oscclk_clk: oscclk {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+-			#clock-cells = <0>;
+-			clock-div = <(12 * 1024)>;
+-			clock-mult = <1>;
+-		};
+-		zb3_clk: zb3 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <4>;
+-			clock-mult = <1>;
+-		};
+-		zb3d2_clk: zb3d2 {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		ddr_clk: ddr {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+-			#clock-cells = <0>;
+-			clock-div = <8>;
+-			clock-mult = <1>;
+-		};
+-		mp_clk: mp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&pll1_div2_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <15>;
+-			clock-mult = <1>;
+-		};
+-		cp_clk: cp {
+-			compatible = "fixed-factor-clock";
+-			clocks = <&extal_clk>;
+-			#clock-cells = <0>;
+-			clock-div = <2>;
+-			clock-mult = <1>;
+-		};
+-
+-		/* Gate clocks */
+-		mstp0_clks: mstp0_clks@e6150130 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+-			clocks = <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7791_CLK_MSIOF0>;
+-			clock-output-names = "msiof0";
+-		};
+-		mstp1_clks: mstp1_clks@e6150134 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+-			clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
+-				 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+-				 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
+-				 <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
+-				R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
+-				R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
+-				R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
+-				R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
+-				R8A7791_CLK_VSP1_S
+-			>;
+-			clock-output-names =
+-				"vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
+-				"2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
+-				"tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
+-		};
+-		mstp2_clks: mstp2_clks@e6150138 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&mp_clk>, <&mp_clk>, <&mp_clk>,
+-				 <&zs_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
+-				R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
+-				R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
+-				R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
+-			>;
+-			clock-output-names =
+-				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+-				"scifb1", "msiof1", "scifb2",
+-				"sys-dmac1", "sys-dmac0";
+-		};
+-		mstp3_clks: mstp3_clks@e615013c {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+-			clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
+-				 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
+-				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
+-				R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
+-				R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
+-			>;
+-			clock-output-names =
+-				"tpu0", "sdhi2", "sdhi1", "sdhi0",
+-				"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+-				"usbdmac0", "usbdmac1";
+-		};
+-		mstp4_clks: mstp4_clks@e6150140 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+-			clocks = <&cp_clk>, <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>;
+-			clock-output-names = "irqc", "intc-sys";
+-		};
+-		mstp5_clks: mstp5_clks@e6150144 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+-			clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
+-				 <&extal_clk>, <&p_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
+-				R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
+-				R8A7791_CLK_PWM
+-			>;
+-			clock-output-names = "audmac0", "audmac1", "adsp_mod",
+-					     "thermal", "pwm";
+-		};
+-		mstp7_clks: mstp7_clks@e615014c {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+-			clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+-				 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+-				 <&zx_clk>, <&zx_clk>, <&zx_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+-				R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
+-				R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
+-				R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
+-				R8A7791_CLK_LVDS0
+-			>;
+-			clock-output-names =
+-				"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+-				"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
+-		};
+-		mstp8_clks: mstp8_clks@e6150990 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+-			clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
+-			         <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
+-				 <&zs_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
+-				R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
+-				R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
+-				R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
+-			>;
+-			clock-output-names =
+-				"ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
+-				"etheravb", "ether", "sata1", "sata0";
+-		};
+-		mstp9_clks: mstp9_clks@e6150994 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+-			clocks = <&p_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+-				 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
+-				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+-				 <&hp_clk>, <&hp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_GYROADC
+-				R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
+-				R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
+-				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
+-				R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
+-				R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
+-			>;
+-			clock-output-names =
+-				"gyroadc",
+-				"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
+-				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
+-				"i2c1", "i2c0";
+-		};
+-		mstp10_clks: mstp10_clks@e6150998 {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+-			clocks = <&p_clk>,
+-				<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-				<&p_clk>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
+-				<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
+-
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_SSI_ALL
+-				R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
+-				R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
+-				R8A7791_CLK_SCU_ALL
+-				R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
+-				R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
+-				R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
+-				R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
+-			>;
+-			clock-output-names =
+-				"ssi-all",
+-				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+-				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+-				"scu-all",
+-				"scu-dvc1", "scu-dvc0",
+-				"scu-ctu1-mix1", "scu-ctu0-mix0",
+-				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+-				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
+-		};
+-		mstp11_clks: mstp11_clks@e615099c {
+-			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+-			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+-			#clock-cells = <1>;
+-			clock-indices = <
+-				R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
+-			>;
+-			clock-output-names = "scifa3", "scifa4", "scifa5";
+-		};
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+@@ -1544,7 +1190,7 @@
+ 		compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+ 		reg = <0 0xe6b10000 0 0x2c>;
+ 		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
++		clocks = <&cpg CPG_MOD 917>;
+ 		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1560,7 +1206,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e20000 0 0x0064>;
+ 		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
++		clocks = <&cpg CPG_MOD 000>;
+ 		dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ 		       <&dmac1 0x51>, <&dmac1 0x52>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1575,7 +1221,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e10000 0 0x0064>;
+ 		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
++		clocks = <&cpg CPG_MOD 208>;
+ 		dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ 		       <&dmac1 0x55>, <&dmac1 0x56>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1590,7 +1236,7 @@
+ 			     "renesas,rcar-gen2-msiof";
+ 		reg = <0 0xe6e00000 0 0x0064>;
+ 		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
++		clocks = <&cpg CPG_MOD 205>;
+ 		dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ 		       <&dmac1 0x41>, <&dmac1 0x42>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+@@ -1604,7 +1250,7 @@
+ 		compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
+ 		reg = <0 0xee000000 0 0xc00>;
+ 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
++		clocks = <&cpg CPG_MOD 328>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		phys = <&usb2 1>;
+ 		phy-names = "usb";
+@@ -1617,7 +1263,7 @@
+ 		reg = <0 0xee090000 0 0xc00>,
+ 		      <0 0xee080000 0 0x1100>;
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -1650,7 +1296,7 @@
+ 		reg = <0 0xee0d0000 0 0xc00>,
+ 		      <0 0xee0c0000 0 0x1100>;
+ 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
++		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+ 
+@@ -1697,7 +1343,7 @@
+ 		#interrupt-cells = <1>;
+ 		interrupt-map-mask = <0 0 0 0>;
+ 		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
++		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ 		clock-names = "pcie", "pcie_bus";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		status = "disabled";
+@@ -1778,21 +1424,22 @@
+ 			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+-		clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+-			<&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
+-			<&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
+-			<&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
+-			<&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
+-			<&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
+-			<&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
+-			<&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
+-			<&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
+-			<&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
+-			<&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
+-			<&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
+-			<&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
+-			<&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
+-			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
++		clocks = <&cpg CPG_MOD 1005>,
++			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++			 <&cpg CPG_CORE R8A7791_CLK_M2>;
+ 		clock-names = "ssi-all",
+ 				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ 				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-- 
+2.19.0
+
diff --git a/patches/0319-ARM-dts-r8a7791-Stop-grouping-clocks-under-a-clocks-.patch b/patches/0319-ARM-dts-r8a7791-Stop-grouping-clocks-under-a-clocks-.patch
new file mode 100644
index 00000000000000..a59f6c8d0eebcf
--- /dev/null
+++ b/patches/0319-ARM-dts-r8a7791-Stop-grouping-clocks-under-a-clocks-.patch
@@ -0,0 +1,169 @@
+From 139ab80b673b34a956a4488712951c2465e23451 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 23 Aug 2017 13:59:26 +0200
+Subject: [PATCH 0319/1795] ARM: dts: r8a7791: Stop grouping clocks under a
+ "clocks" subnode
+
+The current practice is to not group clocks under a "clocks" subnode,
+but just put them together with the other on-SoC devices.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 580aa7cb473880213a55afdb5c34ae844fda07fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 137 ++++++++++++++++-----------------
+ 1 file changed, 66 insertions(+), 71 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 5fca397b722b..e984b106dd1a 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -1097,77 +1097,72 @@
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 	};
+ 
+-	clocks {
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-
+-		/* External root clock */
+-		extal_clk: extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overriden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/*
+-		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
+-		 * default. Boards that provide audio clocks should override them.
+-		 */
+-		audio_clk_a: audio_clk_a {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_b: audio_clk_b {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-		audio_clk_c: audio_clk_c {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External PCIe clock - can be overridden by the board */
+-		pcie_bus_clk: pcie_bus {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External SCIF clock */
+-		scif_clk: scif {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* External USB clock - can be overridden by the board */
+-		usb_extal_clk: usb_extal {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <48000000>;
+-		};
+-
+-		/* External CAN clock */
+-		can_clk: can {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			/* This value must be overridden by the board. */
+-			clock-frequency = <0>;
+-		};
+-
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7791-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-		};
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External USB clock - can be overridden by the board */
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <48000000>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	cpg: clock-controller@e6150000 {
++		compatible = "renesas,r8a7791-cpg-mssr";
++		reg = <0 0xe6150000 0 0x1000>;
++		clocks = <&extal_clk>, <&usb_extal_clk>;
++		clock-names = "extal", "usb_extal";
++		#clock-cells = <2>;
++		#power-domain-cells = <0>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+-- 
+2.19.0
+
diff --git a/patches/0320-ARM-dts-gr-peach-Remove-empty-line.patch b/patches/0320-ARM-dts-gr-peach-Remove-empty-line.patch
new file mode 100644
index 00000000000000..6c78b40bbaa746
--- /dev/null
+++ b/patches/0320-ARM-dts-gr-peach-Remove-empty-line.patch
@@ -0,0 +1,32 @@
+From 4149d7af7e971e6b7c17bdcab274dff08fef8387 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 24 Aug 2017 10:48:40 +0200
+Subject: [PATCH 0320/1795] ARM: dts: gr-peach: Remove empty line
+
+Remove an empty line in gr-peach device tree source file.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f7c68cdfebf6ad6b3c4d6b6c8966414219d035e3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index a1b2aef984f6..1c40a1afbd8e 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -28,7 +28,6 @@
+ 	memory@20000000 {
+ 		device_type = "memory";
+ 		reg = <0x20000000 0x00a00000>;
+-
+ 	};
+ 
+ 	lbsc {
+-- 
+2.19.0
+
diff --git a/patches/0321-ARM-dts-gr-peach-Add-SCIF2-pin-group.patch b/patches/0321-ARM-dts-gr-peach-Add-SCIF2-pin-group.patch
new file mode 100644
index 00000000000000..c171e0ed515d62
--- /dev/null
+++ b/patches/0321-ARM-dts-gr-peach-Add-SCIF2-pin-group.patch
@@ -0,0 +1,55 @@
+From dc4cc15dd69043c6531ea3c405dd336161d72b60 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 24 Aug 2017 10:48:41 +0200
+Subject: [PATCH 0321/1795] ARM: dts: gr-peach: Add SCIF2 pin group
+
+Add pin configuration subnode for SCIF2 serial debug interface.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2f8be2d1dadb2b73a1c1ce244c88c509791f5cf2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index 1c40a1afbd8e..bcfa6445bbaa 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -11,6 +11,7 @@
+ 
+ /dts-v1/;
+ #include "r7s72100.dtsi"
++#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
+ 
+ / {
+ 	model = "GR-Peach";
+@@ -52,6 +53,13 @@
+ 	};
+ };
+ 
++&pinctrl {
++	scif2_pins: serial2 {
++		/* P6_2 as RxD2; P6_3 as TxD2 */
++		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <13333000>;
+ };
+@@ -61,5 +69,8 @@
+ };
+ 
+ &scif2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&scif2_pins>;
++
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0322-ARM-dts-gr-peach-Add-user-led-device-nodes.patch b/patches/0322-ARM-dts-gr-peach-Add-user-led-device-nodes.patch
new file mode 100644
index 00000000000000..8cfccb4b20b205
--- /dev/null
+++ b/patches/0322-ARM-dts-gr-peach-Add-user-led-device-nodes.patch
@@ -0,0 +1,48 @@
+From a5c53a2a23dab16bab4e6618c346bb4635d671f1 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 24 Aug 2017 10:48:43 +0200
+Subject: [PATCH 0322/1795] ARM: dts: gr-peach: Add user led device nodes
+
+Add device nodes for user leds on gr-peach board.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cfce5ac1aaf08fc0920d6572779360f80e8f3489)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index bcfa6445bbaa..13d745bb56a5 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -11,6 +11,7 @@
+ 
+ /dts-v1/;
+ #include "r7s72100.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
+ 
+ / {
+@@ -51,6 +52,15 @@
+ 			reg = <0x00600000 0x00200000>;
+ 		};
+ 	};
++
++leds {
++		status = "okay";
++		compatible = "gpio-leds";
++
++		led1 {
++			gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
++		};
++	};
+ };
+ 
+ &pinctrl {
+-- 
+2.19.0
+
diff --git a/patches/0323-ARM-dts-r8a7745-Add-Ethernet-AVB-support.patch b/patches/0323-ARM-dts-r8a7745-Add-Ethernet-AVB-support.patch
new file mode 100644
index 00000000000000..f1e7d9c34bcd7b
--- /dev/null
+++ b/patches/0323-ARM-dts-r8a7745-Add-Ethernet-AVB-support.patch
@@ -0,0 +1,43 @@
+From ccfeafb1a22c1b8151bfb2170bb5cc30b89a7879 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 25 Aug 2017 09:31:53 +0100
+Subject: [PATCH 0323/1795] ARM: dts: r8a7745: Add Ethernet AVB support
+
+Add Ethernet AVB support for r8a7745 SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 372b01369fed699c417789ad94344847e09b7a43)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 7fd2967b1f42..6e82991b7997 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -623,6 +623,19 @@
+ 			status = "disabled";
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7745",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		i2c0: i2c@e6508000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/0324-ARM-dts-iwg20d-q7-Add-chosen-node.patch b/patches/0324-ARM-dts-iwg20d-q7-Add-chosen-node.patch
new file mode 100644
index 00000000000000..12146e9c83f69a
--- /dev/null
+++ b/patches/0324-ARM-dts-iwg20d-q7-Add-chosen-node.patch
@@ -0,0 +1,33 @@
+From 59455def98217aab1abe4a5b354b2b0b1c764aa8 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 29 Aug 2017 10:56:22 +0100
+Subject: [PATCH 0324/1795] ARM: dts: iwg20d-q7: Add chosen node
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f9c1e87e77ca1ef1c4de2d419b0dcb42e4a47043)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index 4ff27d23ecf0..e30c58625e65 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -20,6 +20,11 @@
+ 		ethernet0 = &avb;
+ 	};
+ 
++	chosen {
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
++		stdout-path = "serial0:115200n8";
++	};
++
+ 	vcc_sdhi1: regulator-vcc-sdhi1 {
+ 		compatible = "regulator-fixed";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0325-ARM-dts-iwg20d-q7-Add-RTC-support.patch b/patches/0325-ARM-dts-iwg20d-q7-Add-RTC-support.patch
new file mode 100644
index 00000000000000..5553a3092843da
--- /dev/null
+++ b/patches/0325-ARM-dts-iwg20d-q7-Add-RTC-support.patch
@@ -0,0 +1,54 @@
+From 3b824ad388e614c4ee6852c7cd92a827304dbb50 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 29 Aug 2017 10:56:23 +0100
+Subject: [PATCH 0325/1795] ARM: dts: iwg20d-q7: Add RTC support
+
+Define the iWave RainboW-G20D-Qseven board dependent part of the
+RTC device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e0e63658c2f291e0672fdf96df1f9f2963a6a9f6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index e30c58625e65..2b58b53aa171 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -50,6 +50,11 @@
+ };
+ 
+ &pfc {
++	i2c2_pins: i2c2 {
++		groups = "i2c2";
++		function = "i2c2";
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data_d";
+ 		function = "scif0";
+@@ -107,3 +112,16 @@
+ 	sd-uhs-sdr50;
+ 	status = "okay";
+ };
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	rtc@68 {
++		compatible = "ti,bq32000";
++		reg = <0x68>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0326-ARM-dts-iwg22d-sodimm-Add-pinctl-support-for-scif4.patch b/patches/0326-ARM-dts-iwg22d-sodimm-Add-pinctl-support-for-scif4.patch
new file mode 100644
index 00000000000000..2fd4cc17623542
--- /dev/null
+++ b/patches/0326-ARM-dts-iwg22d-sodimm-Add-pinctl-support-for-scif4.patch
@@ -0,0 +1,41 @@
+From 0ac8320ef2b5606dca1af2593a07585f7ad71dbf Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Thu, 17 Aug 2017 16:09:09 +0100
+Subject: [PATCH 0326/1795] ARM: dts: iwg22d-sodimm: Add pinctl support for
+ scif4
+
+Adding pinctrl support for scif4 interface.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 67dbb081815e013e1e7911305b43b44537a78ed2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index cbc19feb1565..442a5cbb0838 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -24,6 +24,16 @@
+ 	};
+ };
+ 
++&pfc {
++	scif4_pins: scif4 {
++		groups = "scif4_data_b";
++		function = "scif4";
++	};
++};
++
+ &scif4 {
++	pinctrl-0 = <&scif4_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0327-ARM-dts-iwg22d-sodimm-Add-Ethernet-AVB-support.patch b/patches/0327-ARM-dts-iwg22d-sodimm-Add-Ethernet-AVB-support.patch
new file mode 100644
index 00000000000000..05298a50865897
--- /dev/null
+++ b/patches/0327-ARM-dts-iwg22d-sodimm-Add-Ethernet-AVB-support.patch
@@ -0,0 +1,76 @@
+From 22c15495dd18dddaa0f62204f9e86b8978608b90 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 16:17:14 +0100
+Subject: [PATCH 0327/1795] ARM: dts: iwg22d-sodimm: Add Ethernet AVB support
+
+Define the iWave RainboW-G22D board dependent part of the Ethernet
+AVB device node.
+
+On some older versions of the platform (before R4.0) the phy address
+may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which
+will be the first mainstream release), hence using 3 in the dts.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d6ee805325b1d082fa33be3024163e5f7931ed54)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 +++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 442a5cbb0838..aac84c67a31d 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -17,9 +17,11 @@
+ 
+ 	aliases {
+ 		serial0 = &scif4;
++		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ };
+@@ -29,6 +31,11 @@
+ 		groups = "scif4_data_b";
+ 		function = "scif4";
+ 	};
++
++	avb_pins: avb {
++		groups = "avb_mdio", "avb_gmii";
++		function = "avb";
++	};
+ };
+ 
+ &scif4 {
+@@ -37,3 +44,22 @@
+ 
+ 	status = "okay";
+ };
++
++&avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
++	phy-handle = <&phy3>;
++	phy-mode = "gmii";
++	renesas,no-ether-link;
++	status = "okay";
++
++	phy3: ethernet-phy@3 {
++	/*
++	 * On some older versions of the platform (before R4.0) the phy address
++	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
++	 */
++		reg = <3>;
++		micrel,led-mode = <1>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0328-ARM-dts-r8a7743-Add-internal-PCI-bridge-nodes.patch b/patches/0328-ARM-dts-r8a7743-Add-internal-PCI-bridge-nodes.patch
new file mode 100644
index 00000000000000..4c40fa1155da0b
--- /dev/null
+++ b/patches/0328-ARM-dts-r8a7743-Add-internal-PCI-bridge-nodes.patch
@@ -0,0 +1,76 @@
+From e9dc72e3f9d279568911b7cb5aff4a9a34ccac51 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 14:41:09 +0100
+Subject: [PATCH 0328/1795] ARM: dts: r8a7743: Add internal PCI bridge nodes
+
+Add device nodes for the r8a7743 internal PCI bridge devices.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 46d9cf5202fd8cd266748779c1a941aaeff0dcad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 46 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 6dd9b0b3d818..3f1faad7c24f 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -821,6 +821,52 @@
+ 			resets = <&cpg 311>;
+ 			status = "disabled";
+ 		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7743",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7743",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0329-ARM-dts-r8a7743-Add-USB-PHY-DT-support.patch b/patches/0329-ARM-dts-r8a7743-Add-USB-PHY-DT-support.patch
new file mode 100644
index 00000000000000..b4cdd403a10a68
--- /dev/null
+++ b/patches/0329-ARM-dts-r8a7743-Add-USB-PHY-DT-support.patch
@@ -0,0 +1,52 @@
+From 85f4fbdcfcd70b8b5d9090e12c07aa0d09e1e848 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 14:41:10 +0100
+Subject: [PATCH 0329/1795] ARM: dts: r8a7743: Add USB PHY DT support
+
+Define the r8a7743 generic part of the USB PHY device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9412c391af67fc8aa4e2d8975ba6143cd5289296)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 3f1faad7c24f..a81d70e713ea 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -822,6 +822,28 @@
+ 			status = "disabled";
+ 		};
+ 
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7743",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
++		};
++
+ 		pci0: pci@ee090000 {
+ 			compatible = "renesas,pci-r8a7743",
+ 				     "renesas,pci-rcar-gen2";
+-- 
+2.19.0
+
diff --git a/patches/0330-ARM-dts-r8a7743-Link-PCI-USB-devices-to-USB-PHY.patch b/patches/0330-ARM-dts-r8a7743-Link-PCI-USB-devices-to-USB-PHY.patch
new file mode 100644
index 00000000000000..6dbea13df61721
--- /dev/null
+++ b/patches/0330-ARM-dts-r8a7743-Link-PCI-USB-devices-to-USB-PHY.patch
@@ -0,0 +1,62 @@
+From 8b68cd39a7aef64e7bc58dad5a207f2e1f226a87 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 14:41:11 +0100
+Subject: [PATCH 0330/1795] ARM: dts: r8a7743: Link PCI USB devices to USB PHY
+
+Describe the PCI USB devices that are behind the PCI bridges, adding
+necessary links to the USB PHY device.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 96963454655c10663f1bc2eea57ac734cab171a7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index a81d70e713ea..665a5152951f 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -865,6 +865,18 @@
+ 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
+ 		};
+ 
+ 		pci1: pci@ee0d0000 {
+@@ -888,6 +900,18 @@
+ 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0331-ARM-dts-iwg20d-q7-Enable-internal-PCI.patch b/patches/0331-ARM-dts-iwg20d-q7-Enable-internal-PCI.patch
new file mode 100644
index 00000000000000..66d5706e9d38dd
--- /dev/null
+++ b/patches/0331-ARM-dts-iwg20d-q7-Enable-internal-PCI.patch
@@ -0,0 +1,57 @@
+From d5ad76c95319d1951c1dca5ff88e0bcf7a1e62c3 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 14:41:12 +0100
+Subject: [PATCH 0331/1795] ARM: dts: iwg20d-q7: Enable internal PCI
+
+Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers
+attached to them.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 35a8eeeac89c56435277fa76f8d557bf00530320)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index 2b58b53aa171..63166f9bdb65 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -76,6 +76,16 @@
+ 		function = "sdhi1";
+ 		power-source = <1800>;
+ 	};
++
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
++
++	usb1_pins: usb1 {
++		groups = "usb1";
++		function = "usb1";
++	};
+ };
+ 
+ &scif0 {
+@@ -125,3 +135,15 @@
+ 		reg = <0x68>;
+ 	};
+ };
++
++&pci0 {
++	status = "okay";
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++};
++
++&pci1 {
++	status = "okay";
++	pinctrl-0 = <&usb1_pins>;
++	pinctrl-names = "default";
++};
+-- 
+2.19.0
+
diff --git a/patches/0332-ARM-dts-iwg20d-q7-Enable-USB-PHY.patch b/patches/0332-ARM-dts-iwg20d-q7-Enable-USB-PHY.patch
new file mode 100644
index 00000000000000..13d1347072cd4a
--- /dev/null
+++ b/patches/0332-ARM-dts-iwg20d-q7-Enable-USB-PHY.patch
@@ -0,0 +1,29 @@
+From 922080e3220cd9c10aefc53ec5d78cc3a35e3770 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 30 Aug 2017 14:41:13 +0100
+Subject: [PATCH 0332/1795] ARM: dts: iwg20d-q7: Enable USB PHY
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 51be0086e6d2ebb3f0ddbeedab8d7c4232c1c5f6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index 63166f9bdb65..0136864bc595 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -147,3 +147,7 @@
+ 	pinctrl-0 = <&usb1_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0333-ARM-dts-alt-use-correct-logic-for-SD-WP-pins.patch b/patches/0333-ARM-dts-alt-use-correct-logic-for-SD-WP-pins.patch
new file mode 100644
index 00000000000000..b5896260662fc1
--- /dev/null
+++ b/patches/0333-ARM-dts-alt-use-correct-logic-for-SD-WP-pins.patch
@@ -0,0 +1,42 @@
+From 40eeebc982025a35bdcbe92969a2199c7b260259 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 5 Sep 2017 19:26:31 +0200
+Subject: [PATCH 0333/1795] ARM: dts: alt: use correct logic for SD WP pins
+
+The WP pins are ACTIVE_HIGH, fix it in the DTS.
+
+Fixes: 2b41091b896b ("ARM: dts: alt: add SDHI0 and 1 support")
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a2f74d0e655eac78dbbd4ade88ee08b1f8ec7ec1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index e45f92b5eb11..bd98790d964e 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -304,7 +304,7 @@
+ 	vmmc-supply = <&vcc_sdhi0>;
+ 	vqmmc-supply = <&vccq_sdhi0>;
+ 	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+-	wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
++	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ 	sd-uhs-sdr50;
+ 	sd-uhs-sdr104;
+ 	status = "okay";
+@@ -318,7 +318,7 @@
+ 	vmmc-supply = <&vcc_sdhi1>;
+ 	vqmmc-supply = <&vccq_sdhi1>;
+ 	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+-	wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
++	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ 	sd-uhs-sdr50;
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0334-ARM-dts-r8a7743-Add-IIC-cores-to-dtsi.patch b/patches/0334-ARM-dts-r8a7743-Add-IIC-cores-to-dtsi.patch
new file mode 100644
index 00000000000000..52982ab747c98d
--- /dev/null
+++ b/patches/0334-ARM-dts-r8a7743-Add-IIC-cores-to-dtsi.patch
@@ -0,0 +1,91 @@
+From cfba28871dbb8060b20eacde7c0aee4383ca08da Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 6 Sep 2017 14:52:06 +0100
+Subject: [PATCH 0334/1795] ARM: dts: r8a7743: Add IIC cores to dtsi
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f523405f2a22cc0c30701ea0cb3671dc0abbcda1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 55 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 665a5152951f..266c5eca9f74 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -25,6 +25,9 @@
+ 		i2c3 = &i2c3;
+ 		i2c4 = &i2c4;
+ 		i2c5 = &i2c5;
++		i2c6 = &iic0;
++		i2c7 = &iic1;
++		i2c8 = &iic3;
+ 	};
+ 
+ 	cpus {
+@@ -436,6 +439,58 @@
+ 			status = "disabled";
+ 		};
+ 
++		iic0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
++
++		iic1: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
++
++		iic3: i2c@e60b0000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
++			       <&dmac1 0x77>, <&dmac1 0x78>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 926>;
++			status = "disabled";
++		};
++
+ 		scifa0: serial@e6c40000 {
+ 			compatible = "renesas,scifa-r8a7743",
+ 				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-- 
+2.19.0
+
diff --git a/patches/0335-ARM-dts-r8a7790-Add-reset-control-properties.patch b/patches/0335-ARM-dts-r8a7790-Add-reset-control-properties.patch
new file mode 100644
index 00000000000000..950ef62c6d8c76
--- /dev/null
+++ b/patches/0335-ARM-dts-r8a7790-Add-reset-control-properties.patch
@@ -0,0 +1,599 @@
+From 5e3cd4bd7cb68f2326c1537811b14131fd705b11 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Sep 2017 15:09:55 +0200
+Subject: [PATCH 0335/1795] ARM: dts: r8a7790: Add reset control properties
+
+Add properties to describe the reset topology for on-SoC devices:
+  - Add the "#reset-cells" property to the CPG/MSSR device node,
+  - Add resets and reset-names properties to the various device nodes.
+
+This allows to reset SoC devices using the Reset Controller API.
+
+Note that resets usually match the corresponding module clocks.
+Exceptions are:
+  - The audio module has resets for the Serial Sound Interfaces only,
+  - The display module has only a single reset for all DU channels, but
+    adding reset properties for the display is postponed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 34fbd2b12761d11166414ca766637c7e6bbb39d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 76 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 76 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 70040c6c4cea..081cf5cdb13b 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -188,6 +188,7 @@
+ 		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 408>;
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+@@ -201,6 +202,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 912>;
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+@@ -214,6 +216,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 911>;
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+@@ -227,6 +230,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 910>;
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+@@ -240,6 +244,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 909>;
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+@@ -253,6 +258,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 908>;
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+@@ -266,6 +272,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 907>;
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+@@ -276,6 +283,7 @@
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 522>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+ 
+@@ -295,6 +303,7 @@
+ 		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 124>;
+ 
+ 		renesas,channels-mask = <0x60>;
+ 
+@@ -315,6 +324,7 @@
+ 		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 329>;
+ 
+ 		renesas,channels-mask = <0xff>;
+ 
+@@ -332,6 +342,7 @@
+ 			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 407>;
+ 	};
+ 
+ 	dmac0: dma-controller@e6700000 {
+@@ -361,6 +372,7 @@
+ 		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 219>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -392,6 +404,7 @@
+ 		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 218>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -421,6 +434,7 @@
+ 		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 502>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -450,6 +464,7 @@
+ 		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 501>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -462,6 +477,7 @@
+ 		interrupt-names = "ch0", "ch1";
+ 		clocks = <&cpg CPG_MOD 330>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 330>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+ 	};
+@@ -474,6 +490,7 @@
+ 		interrupt-names = "ch0", "ch1";
+ 		clocks = <&cpg CPG_MOD 331>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 331>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+ 	};
+@@ -486,6 +503,7 @@
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 931>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+ 	};
+@@ -498,6 +516,7 @@
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 930>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -510,6 +529,7 @@
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 929>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -522,6 +542,7 @@
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 928>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+ 	};
+@@ -538,6 +559,7 @@
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 318>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -553,6 +575,7 @@
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 323>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -568,6 +591,7 @@
+ 		       <&dmac1 0x69>, <&dmac1 0x6a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 300>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -583,6 +607,7 @@
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 926>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -595,6 +620,7 @@
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 315>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+ 		max-frequency = <97500000>;
+@@ -609,6 +635,7 @@
+ 		       <&dmac1 0xe1>, <&dmac1 0xe2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 305>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+ 		max-frequency = <97500000>;
+@@ -629,6 +656,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 314>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -642,6 +670,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 313>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -655,6 +684,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 312>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -668,6 +698,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 311>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -682,6 +713,7 @@
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 204>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -696,6 +728,7 @@
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 203>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -710,6 +743,7 @@
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 202>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -724,6 +758,7 @@
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 206>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -738,6 +773,7 @@
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 207>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -752,6 +788,7 @@
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 216>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -767,6 +804,7 @@
+ 		       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 721>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -782,6 +820,7 @@
+ 		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 720>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -797,6 +836,7 @@
+ 		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 310>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -812,6 +852,7 @@
+ 		       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 717>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -827,6 +868,7 @@
+ 		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 716>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -854,6 +896,7 @@
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 813>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -867,6 +910,7 @@
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 812>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -878,6 +922,7 @@
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 815>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 815>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -887,6 +932,7 @@
+ 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 814>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 814>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -899,6 +945,7 @@
+ 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+ 		dma-names = "ch0", "ch1", "ch2", "ch3";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		renesas,buswait = <4>;
+ 		phys = <&usb0 1>;
+ 		phy-names = "usb";
+@@ -914,6 +961,7 @@
+ 		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		status = "disabled";
+ 
+ 		usb0: usb-channel@0 {
+@@ -932,6 +980,7 @@
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 811>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -941,6 +990,7 @@
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 810>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -950,6 +1000,7 @@
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 809>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -959,6 +1010,7 @@
+ 		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 808>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 808>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -968,6 +1020,7 @@
+ 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 130>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 130>;
+ 	};
+ 
+ 	vsp1@fe928000 {
+@@ -976,6 +1029,7 @@
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 131>;
+ 	};
+ 
+ 	vsp1@fe930000 {
+@@ -984,6 +1038,7 @@
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 128>;
+ 	};
+ 
+ 	vsp1@fe938000 {
+@@ -992,6 +1047,7 @@
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 127>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 127>;
+ 	};
+ 
+ 	du: display@feb00000 {
+@@ -1039,6 +1095,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 916>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1050,6 +1107,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 915>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1059,6 +1117,7 @@
+ 		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 106>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 106>;
+ 	};
+ 
+ 	/* External root clock */
+@@ -1154,6 +1213,7 @@
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 917>;
+ 		num-cs = <1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -1170,6 +1230,7 @@
+ 		       <&dmac1 0x51>, <&dmac1 0x52>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 0>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1185,6 +1246,7 @@
+ 		       <&dmac1 0x55>, <&dmac1 0x56>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 208>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1200,6 +1262,7 @@
+ 		       <&dmac1 0x41>, <&dmac1 0x42>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 205>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1215,6 +1278,7 @@
+ 		       <&dmac1 0x45>, <&dmac1 0x46>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 215>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1226,6 +1290,7 @@
+ 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 328>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 328>;
+ 		phys = <&usb2 1>;
+ 		phy-names = "usb";
+ 		status = "disabled";
+@@ -1239,6 +1304,7 @@
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <0 0>;
+@@ -1272,6 +1338,7 @@
+ 		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <1 1>;
+@@ -1290,6 +1357,7 @@
+ 		device_type = "pci";
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		reg = <0 0xee0d0000 0 0xc00>,
+ 		      <0 0xee0c0000 0 0x1100>;
+ 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1341,6 +1409,7 @@
+ 		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ 		clock-names = "pcie", "pcie_bus";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 319>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1385,6 +1454,13 @@
+ 				"dvc.0", "dvc.1",
+ 				"clk_a", "clk_b", "clk_c", "clk_i";
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++		resets = <&cpg 1005>,
++			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
++			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
++			 <&cpg 1014>, <&cpg 1015>;
++		reset-names = "ssi-all",
++			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+ 
+ 		status = "disabled";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0336-ARM-dts-r8a7791-Add-reset-control-properties.patch b/patches/0336-ARM-dts-r8a7791-Add-reset-control-properties.patch
new file mode 100644
index 00000000000000..af213ad1d975be
--- /dev/null
+++ b/patches/0336-ARM-dts-r8a7791-Add-reset-control-properties.patch
@@ -0,0 +1,647 @@
+From 84c3c44910e17217284753e74ab8621686a7c947 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Sep 2017 15:09:56 +0200
+Subject: [PATCH 0336/1795] ARM: dts: r8a7791: Add reset control properties
+
+Add properties to describe the reset topology for on-SoC devices:
+  - Add the "#reset-cells" property to the CPG/MSSR device node,
+  - Add resets and reset-names properties to the various device nodes.
+
+This allows to reset SoC devices using the Reset Controller API.
+
+Note that resets usually match the corresponding module clocks.
+Exceptions are:
+  - The audio module has resets for the Serial Sound Interfaces only,
+  - The display module has only a single reset for all DU channels, but
+    adding reset properties for the display is postponed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit be5ae56e5f2d1f4eff1c2eca3d8e7d801085a6e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 82 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 82 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index e984b106dd1a..5a8a15847076 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -120,6 +120,7 @@
+ 		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 408>;
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+@@ -133,6 +134,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 912>;
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+@@ -146,6 +148,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 911>;
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+@@ -159,6 +162,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 910>;
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+@@ -172,6 +176,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 909>;
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+@@ -185,6 +190,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 908>;
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+@@ -198,6 +204,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 907>;
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+@@ -211,6 +218,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 905>;
+ 	};
+ 
+ 	gpio7: gpio@e6055800 {
+@@ -224,6 +232,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 904>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 904>;
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+@@ -234,6 +243,7 @@
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 522>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+ 
+@@ -253,6 +263,7 @@
+ 		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 124>;
+ 
+ 		renesas,channels-mask = <0x60>;
+ 
+@@ -273,6 +284,7 @@
+ 		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 329>;
+ 
+ 		renesas,channels-mask = <0xff>;
+ 
+@@ -296,6 +308,7 @@
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 407>;
+ 	};
+ 
+ 	dmac0: dma-controller@e6700000 {
+@@ -325,6 +338,7 @@
+ 		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 219>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -356,6 +370,7 @@
+ 		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 218>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -385,6 +400,7 @@
+ 		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 502>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -414,6 +430,7 @@
+ 		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 501>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -426,6 +443,7 @@
+ 		interrupt-names = "ch0", "ch1";
+ 		clocks = <&cpg CPG_MOD 330>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 330>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+ 	};
+@@ -438,6 +456,7 @@
+ 		interrupt-names = "ch0", "ch1";
+ 		clocks = <&cpg CPG_MOD 331>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 331>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <2>;
+ 	};
+@@ -451,6 +470,7 @@
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 931>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -463,6 +483,7 @@
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 930>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -475,6 +496,7 @@
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 929>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -487,6 +509,7 @@
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 928>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -499,6 +522,7 @@
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 927>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -512,6 +536,7 @@
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 925>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+ 	};
+@@ -529,6 +554,7 @@
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 926>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -544,6 +570,7 @@
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 318>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -559,6 +586,7 @@
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 323>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -576,6 +604,7 @@
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 315>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+ 		max-frequency = <97500000>;
+@@ -591,6 +620,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 314>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -604,6 +634,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 312>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -617,6 +648,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 311>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -631,6 +663,7 @@
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 204>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -645,6 +678,7 @@
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 203>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -659,6 +693,7 @@
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 202>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -673,6 +708,7 @@
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 1106>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -687,6 +723,7 @@
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 1107>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -701,6 +738,7 @@
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 1108>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -715,6 +753,7 @@
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 206>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -729,6 +768,7 @@
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 207>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -743,6 +783,7 @@
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 216>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -758,6 +799,7 @@
+ 		       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 721>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -773,6 +815,7 @@
+ 		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 720>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -782,6 +825,7 @@
+ 		clocks = <&cpg CPG_MOD 901>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 901>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -797,6 +841,7 @@
+ 		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 719>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -812,6 +857,7 @@
+ 		       <&dmac1 0x2f>, <&dmac1 0x30>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 718>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -827,6 +873,7 @@
+ 		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 715>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -842,6 +889,7 @@
+ 		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 714>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -857,6 +905,7 @@
+ 		       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 717>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -872,6 +921,7 @@
+ 		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 716>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -887,6 +937,7 @@
+ 		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 713>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -914,6 +965,7 @@
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 813>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -927,6 +979,7 @@
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 812>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -938,6 +991,7 @@
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 815>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 815>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -947,6 +1001,7 @@
+ 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 814>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 814>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -959,6 +1014,7 @@
+ 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+ 		dma-names = "ch0", "ch1", "ch2", "ch3";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		renesas,buswait = <4>;
+ 		phys = <&usb0 1>;
+ 		phy-names = "usb";
+@@ -974,6 +1030,7 @@
+ 		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		status = "disabled";
+ 
+ 		usb0: usb-channel@0 {
+@@ -992,6 +1049,7 @@
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 811>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1001,6 +1059,7 @@
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 810>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1010,6 +1069,7 @@
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 809>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1019,6 +1079,7 @@
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 131>;
+ 	};
+ 
+ 	vsp1@fe930000 {
+@@ -1027,6 +1088,7 @@
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 128>;
+ 	};
+ 
+ 	vsp1@fe938000 {
+@@ -1035,6 +1097,7 @@
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 127>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 127>;
+ 	};
+ 
+ 	du: display@feb00000 {
+@@ -1075,6 +1138,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 916>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1086,6 +1150,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 915>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1095,6 +1160,7 @@
+ 		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 106>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 106>;
+ 	};
+ 
+ 	/* External root clock */
+@@ -1163,6 +1229,7 @@
+ 		clock-names = "extal", "usb_extal";
+ 		#clock-cells = <2>;
+ 		#power-domain-cells = <0>;
++		#reset-cells = <1>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+@@ -1190,6 +1257,7 @@
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 917>;
+ 		num-cs = <1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -1206,6 +1274,7 @@
+ 		       <&dmac1 0x51>, <&dmac1 0x52>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 0>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1221,6 +1290,7 @@
+ 		       <&dmac1 0x55>, <&dmac1 0x56>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 208>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1236,6 +1306,7 @@
+ 		       <&dmac1 0x41>, <&dmac1 0x42>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 205>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -1247,6 +1318,7 @@
+ 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 328>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 328>;
+ 		phys = <&usb2 1>;
+ 		phy-names = "usb";
+ 		status = "disabled";
+@@ -1260,6 +1332,7 @@
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <0 0>;
+@@ -1293,6 +1366,7 @@
+ 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <1 1>;
+@@ -1341,6 +1415,7 @@
+ 		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ 		clock-names = "pcie", "pcie_bus";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 319>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1445,6 +1520,13 @@
+ 				"dvc.0", "dvc.1",
+ 				"clk_a", "clk_b", "clk_c", "clk_i";
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++		resets = <&cpg 1005>,
++			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
++			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
++			 <&cpg 1014>, <&cpg 1015>;
++		reset-names = "ssi-all",
++			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+ 
+ 		status = "disabled";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0337-ARM-dts-r8a7792-Add-reset-control-properties.patch b/patches/0337-ARM-dts-r8a7792-Add-reset-control-properties.patch
new file mode 100644
index 00000000000000..14427555b66f37
--- /dev/null
+++ b/patches/0337-ARM-dts-r8a7792-Add-reset-control-properties.patch
@@ -0,0 +1,394 @@
+From e62f4f75f422e7f3f05cb52b0894e6ab3a051aa9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Sep 2017 15:09:57 +0200
+Subject: [PATCH 0337/1795] ARM: dts: r8a7792: Add reset control properties
+
+Add properties to describe the reset topology for on-SoC devices:
+  - Add the "#reset-cells" property to the CPG/MSSR device node,
+  - Add resets and reset-names properties to the various device nodes.
+
+This allows to reset SoC devices using the Reset Controller API.
+
+Note that resets usually match the corresponding module clocks.
+Exceptions are:
+  - The audio module has resets for the Serial Sound Interfaces only,
+    but audio is not yet enabled in r8a7792.dtsi,
+  - The display module has only a single reset for all DU channels, but
+    adding reset properties for the display is postponed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6e11a322f1d7505d3a1db4ae26c6c0e46082f4ae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 45 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index a209787d899a..c332f77ebb6b 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -95,6 +95,7 @@
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
+ 		};
+ 
+ 		irqc: interrupt-controller@e61c0000 {
+@@ -108,6 +109,7 @@
+ 				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 407>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
+ 		};
+ 
+ 		timer {
+@@ -155,6 +157,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 912>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
+ 		};
+ 
+ 		gpio1: gpio@e6051000 {
+@@ -169,6 +172,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 911>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
+ 		};
+ 
+ 		gpio2: gpio@e6052000 {
+@@ -183,6 +187,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 910>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
+ 		};
+ 
+ 		gpio3: gpio@e6053000 {
+@@ -197,6 +202,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 909>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
+ 		};
+ 
+ 		gpio4: gpio@e6054000 {
+@@ -211,6 +217,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 908>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
+ 		};
+ 
+ 		gpio5: gpio@e6055000 {
+@@ -225,6 +232,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 907>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
+ 		};
+ 
+ 		gpio6: gpio@e6055100 {
+@@ -239,6 +247,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 905>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 905>;
+ 		};
+ 
+ 		gpio7: gpio@e6055200 {
+@@ -253,6 +262,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 904>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 904>;
+ 		};
+ 
+ 		gpio8: gpio@e6055300 {
+@@ -267,6 +277,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 921>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 921>;
+ 		};
+ 
+ 		gpio9: gpio@e6055400 {
+@@ -281,6 +292,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 919>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 919>;
+ 		};
+ 
+ 		gpio10: gpio@e6055500 {
+@@ -295,6 +307,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 914>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
+ 		};
+ 
+ 		gpio11: gpio@e6055600 {
+@@ -309,6 +322,7 @@
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 913>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 913>;
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+@@ -339,6 +353,7 @@
+ 			clocks = <&cpg CPG_MOD 219>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <15>;
+ 		};
+@@ -371,6 +386,7 @@
+ 			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <15>;
+ 		};
+@@ -387,6 +403,7 @@
+ 			       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 721>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -402,6 +419,7 @@
+ 			       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 720>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -417,6 +435,7 @@
+ 			       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 719>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -432,6 +451,7 @@
+ 			       <&dmac1 0x2f>, <&dmac1 0x30>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 718>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -447,6 +467,7 @@
+ 			       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 717>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -462,6 +483,7 @@
+ 			       <&dmac1 0x4d>, <&dmac1 0x4e>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -492,6 +514,7 @@
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			clocks = <&cpg CPG_MOD 314>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -502,6 +525,7 @@
+ 			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 106>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 106>;
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+@@ -511,6 +535,7 @@
+ 			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+@@ -524,6 +549,7 @@
+ 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -537,6 +563,7 @@
+ 			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -550,6 +577,7 @@
+ 			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 929>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -563,6 +591,7 @@
+ 			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 928>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -576,6 +605,7 @@
+ 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 927>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -589,6 +619,7 @@
+ 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 925>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
+ 			i2c-scl-internal-delay-ns = <110>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -604,6 +635,7 @@
+ 			       <&dmac1 0x17>, <&dmac1 0x18>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
+ 			num-cs = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -620,6 +652,7 @@
+ 			       <&dmac1 0x51>, <&dmac1 0x52>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 000>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+@@ -635,6 +668,7 @@
+ 			       <&dmac1 0x55>, <&dmac1 0x56>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 208>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+@@ -677,6 +711,7 @@
+ 				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ 			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -689,6 +724,7 @@
+ 				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
+ 			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -699,6 +735,7 @@
+ 			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 811>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -709,6 +746,7 @@
+ 			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 810>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -719,6 +757,7 @@
+ 			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 809>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -729,6 +768,7 @@
+ 			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 808>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -739,6 +779,7 @@
+ 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 805>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 805>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -749,6 +790,7 @@
+ 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 804>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 804>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -758,6 +800,7 @@
+ 			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 131>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
+ 		};
+ 
+ 		vsp1@fe930000 {
+@@ -766,6 +809,7 @@
+ 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 128>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
+ 		};
+ 
+ 		vsp1@fe938000 {
+@@ -774,6 +818,7 @@
+ 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 127>;
+ 			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
+ 		};
+ 
+ 		cpg: clock-controller@e6150000 {
+-- 
+2.19.0
+
diff --git a/patches/0338-ARM-dts-r8a7793-Add-reset-control-properties.patch b/patches/0338-ARM-dts-r8a7793-Add-reset-control-properties.patch
new file mode 100644
index 00000000000000..6c3e5b8d7fa979
--- /dev/null
+++ b/patches/0338-ARM-dts-r8a7793-Add-reset-control-properties.patch
@@ -0,0 +1,487 @@
+From d6753ef94cf17003c47bff19a7a867632d4ad40d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Sep 2017 15:09:58 +0200
+Subject: [PATCH 0338/1795] ARM: dts: r8a7793: Add reset control properties
+
+Add properties to describe the reset topology for on-SoC devices:
+  - Add the "#reset-cells" property to the CPG/MSSR device node,
+  - Add resets and reset-names properties to the various device nodes.
+
+This allows to reset SoC devices using the Reset Controller API.
+
+Note that resets usually match the corresponding module clocks.
+Exceptions are:
+  - The audio module has resets for the Serial Sound Interfaces only,
+  - The display module has only a single reset for all DU channels, but
+    adding reset properties for the display is postponed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 84fb19e1d201ba862cf25995cdb7c061c9d938ea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 62 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index d48b97c853cd..aa19b93494bf 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -111,6 +111,7 @@
+ 		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 408>;
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+@@ -124,6 +125,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 912>;
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+@@ -137,6 +139,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 911>;
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+@@ -150,6 +153,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 910>;
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+@@ -163,6 +167,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 909>;
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+@@ -176,6 +181,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 908>;
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+@@ -189,6 +195,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 907>;
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+@@ -202,6 +209,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 905>;
+ 	};
+ 
+ 	gpio7: gpio@e6055800 {
+@@ -215,6 +223,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 904>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 904>;
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+@@ -225,6 +234,7 @@
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 522>;
+ 		#thermal-sensor-cells = <0>;
+ 	};
+ 
+@@ -244,6 +254,7 @@
+ 		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 124>;
+ 
+ 		renesas,channels-mask = <0x60>;
+ 
+@@ -264,6 +275,7 @@
+ 		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 329>;
+ 
+ 		renesas,channels-mask = <0xff>;
+ 
+@@ -287,6 +299,7 @@
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 407>;
+ 	};
+ 
+ 	dmac0: dma-controller@e6700000 {
+@@ -316,6 +329,7 @@
+ 		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 219>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -347,6 +361,7 @@
+ 		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 218>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -376,6 +391,7 @@
+ 		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 502>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -405,6 +421,7 @@
+ 		clocks = <&cpg CPG_MOD 501>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 501>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -418,6 +435,7 @@
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 931>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -430,6 +448,7 @@
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 930>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -442,6 +461,7 @@
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 929>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -454,6 +474,7 @@
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 928>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -466,6 +487,7 @@
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 927>;
+ 		i2c-scl-internal-delay-ns = <6>;
+ 		status = "disabled";
+ 	};
+@@ -479,6 +501,7 @@
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 925>;
+ 		i2c-scl-internal-delay-ns = <110>;
+ 		status = "disabled";
+ 	};
+@@ -496,6 +519,7 @@
+ 		       <&dmac1 0x77>, <&dmac1 0x78>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 926>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -511,6 +535,7 @@
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 318>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -526,6 +551,7 @@
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 323>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -544,6 +570,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 314>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -557,6 +584,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 312>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -570,6 +598,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 311>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -582,6 +611,7 @@
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 315>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+ 		max-frequency = <97500000>;
+@@ -598,6 +628,7 @@
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 204>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -612,6 +643,7 @@
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 203>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -626,6 +658,7 @@
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 202>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -640,6 +673,7 @@
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 1106>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -654,6 +688,7 @@
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 1107>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -668,6 +703,7 @@
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 1108>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -682,6 +718,7 @@
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 206>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -696,6 +733,7 @@
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 207>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -710,6 +748,7 @@
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 216>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -725,6 +764,7 @@
+ 		       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 721>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -740,6 +780,7 @@
+ 		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 720>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -755,6 +796,7 @@
+ 		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 719>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -770,6 +812,7 @@
+ 		       <&dmac1 0x2f>, <&dmac1 0x30>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 718>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -785,6 +828,7 @@
+ 		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 715>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -800,6 +844,7 @@
+ 		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 714>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -815,6 +860,7 @@
+ 		       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 717>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -830,6 +876,7 @@
+ 		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 716>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -845,6 +892,7 @@
+ 		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 713>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -872,6 +920,7 @@
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 813>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -884,6 +933,7 @@
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 811>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -893,6 +943,7 @@
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 810>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -902,6 +953,7 @@
+ 		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 809>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 809>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -914,6 +966,7 @@
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 917>;
+ 		num-cs = <1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -958,6 +1011,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 916>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -969,6 +1023,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 915>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1147,6 +1202,13 @@
+ 				"dvc.0", "dvc.1",
+ 				"clk_a", "clk_b", "clk_c", "clk_i";
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++		resets = <&cpg 1005>,
++			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
++			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
++			 <&cpg 1014>, <&cpg 1015>;
++		reset-names = "ssi-all",
++			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+ 
+ 		status = "disabled";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0339-ARM-dts-r8a7794-Add-reset-control-properties.patch b/patches/0339-ARM-dts-r8a7794-Add-reset-control-properties.patch
new file mode 100644
index 00000000000000..e1491a3ca4db93
--- /dev/null
+++ b/patches/0339-ARM-dts-r8a7794-Add-reset-control-properties.patch
@@ -0,0 +1,503 @@
+From 2ae20c8f260aff5923d844be0e0bd70b030b34f2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 11 Sep 2017 15:09:59 +0200
+Subject: [PATCH 0339/1795] ARM: dts: r8a7794: Add reset control properties
+
+Add properties to describe the reset topology for on-SoC devices:
+  - Add the "#reset-cells" property to the CPG/MSSR device node,
+  - Add resets and reset-names properties to the various device nodes.
+
+This allows to reset SoC devices using the Reset Controller API.
+
+Note that resets usually match the corresponding module clocks.
+Exceptions are:
+  - The audio module has resets for the Serial Sound Interfaces only,
+  - The display module has only a single reset for all DU channels, but
+    adding reset properties for the display is postponed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 615beb759ca494a4b1a202f571af41549064dc2f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 64 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index a4c35d29f77c..035c33715b65 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -78,6 +78,7 @@
+ 		clocks = <&cpg CPG_MOD 408>;
+ 		clock-names = "clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 408>;
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+@@ -91,6 +92,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 912>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 912>;
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+@@ -104,6 +106,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 911>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 911>;
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+@@ -117,6 +120,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 910>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 910>;
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+@@ -130,6 +134,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 909>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 909>;
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+@@ -143,6 +148,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 908>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 908>;
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+@@ -156,6 +162,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 907>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 907>;
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+@@ -169,6 +176,7 @@
+ 		interrupt-controller;
+ 		clocks = <&cpg CPG_MOD 905>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 905>;
+ 	};
+ 
+ 	cmt0: timer@ffca0000 {
+@@ -179,6 +187,7 @@
+ 		clocks = <&cpg CPG_MOD 124>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 124>;
+ 
+ 		renesas,channels-mask = <0x60>;
+ 
+@@ -199,6 +208,7 @@
+ 		clocks = <&cpg CPG_MOD 329>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 329>;
+ 
+ 		renesas,channels-mask = <0xff>;
+ 
+@@ -230,6 +240,7 @@
+ 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 407>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 407>;
+ 	};
+ 
+ 	pfc: pin-controller@e6060000 {
+@@ -264,6 +275,7 @@
+ 		clocks = <&cpg CPG_MOD 219>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 219>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -295,6 +307,7 @@
+ 		clocks = <&cpg CPG_MOD 218>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 218>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <15>;
+ 	};
+@@ -323,6 +336,7 @@
+ 		clocks = <&cpg CPG_MOD 502>;
+ 		clock-names = "fck";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 502>;
+ 		#dma-cells = <1>;
+ 		dma-channels = <13>;
+ 	};
+@@ -338,6 +352,7 @@
+ 		       <&dmac1 0x21>, <&dmac1 0x22>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 204>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -352,6 +367,7 @@
+ 		       <&dmac1 0x25>, <&dmac1 0x26>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 203>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -366,6 +382,7 @@
+ 		       <&dmac1 0x27>, <&dmac1 0x28>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 202>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -380,6 +397,7 @@
+ 		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 1106>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -394,6 +412,7 @@
+ 		       <&dmac1 0x1f>, <&dmac1 0x20>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 1107>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -408,6 +427,7 @@
+ 		       <&dmac1 0x23>, <&dmac1 0x24>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 1108>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -422,6 +442,7 @@
+ 		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 206>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -436,6 +457,7 @@
+ 		       <&dmac1 0x19>, <&dmac1 0x1a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 207>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -450,6 +472,7 @@
+ 		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 216>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -465,6 +488,7 @@
+ 		       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 721>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -480,6 +504,7 @@
+ 		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 720>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -495,6 +520,7 @@
+ 		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 719>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -510,6 +536,7 @@
+ 		       <&dmac1 0x2f>, <&dmac1 0x30>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 718>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -525,6 +552,7 @@
+ 		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 715>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -540,6 +568,7 @@
+ 		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 714>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -555,6 +584,7 @@
+ 		       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 717>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -570,6 +600,7 @@
+ 		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 716>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -585,6 +616,7 @@
+ 		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 713>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -612,6 +644,7 @@
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 813>;
+ 		phy-mode = "rmii";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -625,6 +658,7 @@
+ 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 812>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 812>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -637,6 +671,7 @@
+ 		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 931>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 931>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -649,6 +684,7 @@
+ 		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 930>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 930>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -661,6 +697,7 @@
+ 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 929>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 929>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -673,6 +710,7 @@
+ 		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 928>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 928>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -685,6 +723,7 @@
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 927>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 927>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -697,6 +736,7 @@
+ 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 925>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 925>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		i2c-scl-internal-delay-ns = <6>;
+@@ -713,6 +753,7 @@
+ 		       <&dmac1 0x61>, <&dmac1 0x62>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 318>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -728,6 +769,7 @@
+ 		       <&dmac1 0x65>, <&dmac1 0x66>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 323>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		status = "disabled";
+@@ -742,6 +784,7 @@
+ 		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 315>;
+ 		reg-io-width = <4>;
+ 		status = "disabled";
+ 	};
+@@ -756,6 +799,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 314>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -769,6 +813,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 312>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -782,6 +827,7 @@
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 311>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -794,6 +840,7 @@
+ 		       <&dmac1 0x17>, <&dmac1 0x18>;
+ 		dma-names = "tx", "rx", "tx", "rx";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 917>;
+ 		num-cs = <1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -806,6 +853,7 @@
+ 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 811>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 811>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -815,6 +863,7 @@
+ 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 810>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 810>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -826,6 +875,7 @@
+ 		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <0 0>;
+@@ -859,6 +909,7 @@
+ 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 703>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 703>;
+ 		status = "disabled";
+ 
+ 		bus-range = <1 1>;
+@@ -890,6 +941,7 @@
+ 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 704>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		renesas,buswait = <4>;
+ 		phys = <&usb0 1>;
+ 		phy-names = "usb";
+@@ -905,6 +957,7 @@
+ 		clocks = <&cpg CPG_MOD 704>;
+ 		clock-names = "usbhs";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 704>;
+ 		status = "disabled";
+ 
+ 		usb0: usb-channel@0 {
+@@ -923,6 +976,7 @@
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 131>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 131>;
+ 	};
+ 
+ 	vsp1@fe930000 {
+@@ -931,6 +985,7 @@
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 128>;
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 128>;
+ 	};
+ 
+ 	du: display@feb00000 {
+@@ -968,6 +1023,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 916>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -979,6 +1035,7 @@
+ 			 <&can_clk>;
+ 		clock-names = "clkp1", "clkp2", "can_clk";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 915>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -1151,6 +1208,13 @@
+ 			      "dvc.0", "dvc.1",
+ 			      "clk_a", "clk_b", "clk_c", "clk_i";
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++		resets = <&cpg 1005>,
++			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
++			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
++			 <&cpg 1014>, <&cpg 1015>;
++		reset-names = "ssi-all",
++			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+ 
+ 		status = "disabled";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0340-ARM-dts-r8a7745-Add-SDHI-controllers.patch b/patches/0340-ARM-dts-r8a7745-Add-SDHI-controllers.patch
new file mode 100644
index 00000000000000..bc20b1d8f8de01
--- /dev/null
+++ b/patches/0340-ARM-dts-r8a7745-Add-SDHI-controllers.patch
@@ -0,0 +1,73 @@
+From 62e948ac92001e98bbb8154e4fa9ce212daf3f3f Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:35 +0100
+Subject: [PATCH 0340/1795] ARM: dts: r8a7745: Add SDHI controllers
+
+Add the SDHI controllers to the r8a7745 device tree.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7079131ef9b934df48602b22e30282d25a6a4827)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 42 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 6e82991b7997..adf30890cb07 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -735,6 +735,48 @@
+ 			max-frequency = <97500000>;
+ 			status = "disabled";
+ 		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7745";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7745";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7745";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0341-ARM-dts-iwg22m-Enable-SDHI1-controller.patch b/patches/0341-ARM-dts-iwg22m-Enable-SDHI1-controller.patch
new file mode 100644
index 00000000000000..d00d56c4d94647
--- /dev/null
+++ b/patches/0341-ARM-dts-iwg22m-Enable-SDHI1-controller.patch
@@ -0,0 +1,63 @@
+From 18f77d5f34bed83b8fa3622428b6c439e2bc6b71 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:36 +0100
+Subject: [PATCH 0341/1795] ARM: dts: iwg22m: Enable SDHI1 controller
+
+Enable the SDHI1 controller on iWave RZ/G1E SoM.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 599114ee21057040c058043fdc1367878350d5e4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index e306e7c5b644..f7f9ceff35a6 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -9,6 +9,7 @@
+  */
+ 
+ #include "r8a7745.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	compatible = "iwave,g22m", "renesas,r8a7745";
+@@ -38,6 +39,12 @@
+ 		function = "mmc";
+ 	};
+ 
++	sdhi1_pins: sd1 {
++		groups = "sdhi1_data4", "sdhi1_ctrl";
++		function = "sdhi1";
++		power-source = <3300>;
++	};
++
+ 	i2c3_pins: i2c3 {
+ 		groups = "i2c3_b";
+ 		function = "i2c3";
+@@ -54,6 +61,16 @@
+ 	status = "okay";
+ };
+ 
++&sdhi1 {
++	pinctrl-0 = <&sdhi1_pins>;
++	pinctrl-names = "default";
++
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
++	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
++
+ &i2c3 {
+ 	pinctrl-0 = <&i2c3_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0342-ARM-dts-r8a7743-Add-QSPI-support.patch b/patches/0342-ARM-dts-r8a7743-Add-QSPI-support.patch
new file mode 100644
index 00000000000000..5c6f85e80f82e6
--- /dev/null
+++ b/patches/0342-ARM-dts-r8a7743-Add-QSPI-support.patch
@@ -0,0 +1,56 @@
+From b1748ab5423d0c637aef61b5a64729435eb131df Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:38 +0100
+Subject: [PATCH 0342/1795] ARM: dts: r8a7743: Add QSPI support
+
+Add the DT node for the QSPI interface to the SoC dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 450c03718e971880ae067dc5f94a86f961acd6c3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 266c5eca9f74..454f98060d6f 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -28,6 +28,7 @@
+ 		i2c6 = &iic0;
+ 		i2c7 = &iic1;
+ 		i2c8 = &iic3;
++		spi0 = &qspi;
+ 	};
+ 
+ 	cpus {
+@@ -835,6 +836,22 @@
+ 			status = "disabled";
+ 		};
+ 
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7743", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 917>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7743";
+ 			reg = <0 0xee100000 0 0x328>;
+-- 
+2.19.0
+
diff --git a/patches/0343-ARM-dts-iwg20m-Add-SPI-NOR-support.patch b/patches/0343-ARM-dts-iwg20m-Add-SPI-NOR-support.patch
new file mode 100644
index 00000000000000..ec1a6003b9ef73
--- /dev/null
+++ b/patches/0343-ARM-dts-iwg20m-Add-SPI-NOR-support.patch
@@ -0,0 +1,66 @@
+From 54b96d62b5347afc9a76c0f3bfa1652c84d7cbe2 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:39 +0100
+Subject: [PATCH 0343/1795] ARM: dts: iwg20m: Add SPI NOR support
+
+Add support for the SPI NOR device used to boot up the system
+to the System on Module DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 781e923a5fe4751d3aaa740ca3de0f9d179c34ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+index 4119737cb883..75a8ca571846 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
++++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+@@ -44,6 +44,11 @@
+ 		function = "mmc";
+ 	};
+ 
++	qspi_pins: qspi {
++		groups = "qspi_ctrl", "qspi_data2";
++		function = "qspi";
++	};
++
+ 	sdhi0_pins: sd0 {
+ 		groups = "sdhi0_data4", "sdhi0_ctrl";
+ 		function = "sdhi0";
+@@ -61,6 +66,27 @@
+ 	status = "okay";
+ };
+ 
++&qspi {
++	pinctrl-0 = <&qspi_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++
++	/* WARNING - This device contains the bootloader. Handle with care. */
++	flash: flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "sst,sst25vf016b", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <1>;
++		spi-rx-bus-width = <1>;
++		m25p,fast-read;
++		spi-cpol;
++		spi-cpha;
++	};
++};
++
+ &sdhi0 {
+ 	pinctrl-0 = <&sdhi0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0344-ARM-dts-r8a7745-Add-QSPI-support.patch b/patches/0344-ARM-dts-r8a7745-Add-QSPI-support.patch
new file mode 100644
index 00000000000000..46d9e7a03e7f08
--- /dev/null
+++ b/patches/0344-ARM-dts-r8a7745-Add-QSPI-support.patch
@@ -0,0 +1,56 @@
+From aff1f39acaf43c4d7b58995b86eadde0c14b6a31 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:40 +0100
+Subject: [PATCH 0344/1795] ARM: dts: r8a7745: Add QSPI support
+
+Add the DT node for the QSPI interface to the SoC dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2391d0269a85c3a7942cb7e2bbac5751a7191e10)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index adf30890cb07..5cc4009c4265 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -25,6 +25,7 @@
+ 		i2c3 = &i2c3;
+ 		i2c4 = &i2c4;
+ 		i2c5 = &i2c5;
++		spi0 = &qspi;
+ 	};
+ 
+ 	cpus {
+@@ -736,6 +737,22 @@
+ 			status = "disabled";
+ 		};
+ 
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7745", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 917>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7745";
+ 			reg = <0 0xee100000 0 0x328>;
+-- 
+2.19.0
+
diff --git a/patches/0345-ARM-dts-iwg22m-Add-SPI-NOR-support.patch b/patches/0345-ARM-dts-iwg22m-Add-SPI-NOR-support.patch
new file mode 100644
index 00000000000000..38330f7bcb9e8f
--- /dev/null
+++ b/patches/0345-ARM-dts-iwg22m-Add-SPI-NOR-support.patch
@@ -0,0 +1,66 @@
+From a3c122f22f9b1255d4e3dbc98949909bc278ad88 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 13 Sep 2017 18:05:41 +0100
+Subject: [PATCH 0345/1795] ARM: dts: iwg22m: Add SPI NOR support
+
+Add support for the SPI NOR device used to boot up the system
+to the System on Module DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cf1cc6f1da41ceb60f6389b6b46f4f6dc06a2b63)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index f7f9ceff35a6..ed9a8cf3fe36 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -39,6 +39,11 @@
+ 		function = "mmc";
+ 	};
+ 
++	qspi_pins: qspi {
++		groups = "qspi_ctrl", "qspi_data2";
++		function = "qspi";
++	};
++
+ 	sdhi1_pins: sd1 {
+ 		groups = "sdhi1_data4", "sdhi1_ctrl";
+ 		function = "sdhi1";
+@@ -61,6 +66,27 @@
+ 	status = "okay";
+ };
+ 
++&qspi {
++	pinctrl-0 = <&qspi_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++
++	/* WARNING - This device contains the bootloader. Handle with care. */
++	flash: flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "sst,sst25vf016b", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <1>;
++		spi-rx-bus-width = <1>;
++		m25p,fast-read;
++		spi-cpol;
++		spi-cpha;
++	};
++};
++
+ &sdhi1 {
+ 	pinctrl-0 = <&sdhi1_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0346-ARM-dts-iwg22d-Enable-SDHI0-controller.patch b/patches/0346-ARM-dts-iwg22d-Enable-SDHI0-controller.patch
new file mode 100644
index 00000000000000..a8890194c5166c
--- /dev/null
+++ b/patches/0346-ARM-dts-iwg22d-Enable-SDHI0-controller.patch
@@ -0,0 +1,72 @@
+From f96a74f32a325e943ef4eda618536a4bb18495e9 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 22 Sep 2017 14:01:02 +0100
+Subject: [PATCH 0346/1795] ARM: dts: iwg22d: Enable SDHI0 controller
+
+Enable the SDHI0 controller on iWave RZ/G1E carrier board.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ec301d261d5a5a71f2ba1baf7a852b220fe69f3c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index aac84c67a31d..8772c561e3a8 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -24,6 +24,19 @@
+ 		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ 		stdout-path = "serial0:115200n8";
+ 	};
++
++	vccq_sdhi0: regulator-vccq-sdhi0 {
++		compatible = "regulator-gpio";
++
++		regulator-name = "SDHI0 VccQ";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
++		gpios-states = <1>;
++		states = <3300000 1
++			  1800000 0>;
++	};
+ };
+ 
+ &pfc {
+@@ -36,6 +49,12 @@
+ 		groups = "avb_mdio", "avb_gmii";
+ 		function = "avb";
+ 	};
++
++	sdhi0_pins: sd0 {
++		groups = "sdhi0_data4", "sdhi0_ctrl";
++		function = "sdhi0";
++		power-source = <3300>;
++	};
+ };
+ 
+ &scif4 {
+@@ -63,3 +82,13 @@
+ 		micrel,led-mode = <1>;
+ 	};
+ };
++
++&sdhi0 {
++	pinctrl-0 = <&sdhi0_pins>;
++	pinctrl-names = "default";
++
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&vccq_sdhi0>;
++	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0347-ARM-dts-r8a7745-Add-MSIOF-012-support.patch b/patches/0347-ARM-dts-r8a7745-Add-MSIOF-012-support.patch
new file mode 100644
index 00000000000000..2bb0c59f9d709a
--- /dev/null
+++ b/patches/0347-ARM-dts-r8a7745-Add-MSIOF-012-support.patch
@@ -0,0 +1,91 @@
+From 129f4bb964a8dadfb65f6d08d5d7d6f7eb1054fe Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 27 Sep 2017 10:57:05 +0100
+Subject: [PATCH 0347/1795] ARM: dts: r8a7745: Add MSIOF[012] support
+
+Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
+Also, define aliases for spi[123].
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e527649c320062f53d8437d1a49b3ed4fccf7750)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 51 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 5cc4009c4265..6ba3b8b04edb 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -26,6 +26,9 @@
+ 		i2c4 = &i2c4;
+ 		i2c5 = &i2c5;
+ 		spi0 = &qspi;
++		spi1 = &msiof0;
++		spi2 = &msiof1;
++		spi3 = &msiof2;
+ 	};
+ 
+ 	cpus {
+@@ -753,6 +756,54 @@
+ 			status = "disabled";
+ 		};
+ 
++		msiof0: spi@e6e20000 {
++			compatible = "renesas,msiof-r8a7745",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e20000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 000>;
++			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
++			       <&dmac1 0x51>, <&dmac1 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 000>;
++			status = "disabled";
++		};
++
++		msiof1: spi@e6e10000 {
++			compatible = "renesas,msiof-r8a7745",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e10000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
++			       <&dmac1 0x55>, <&dmac1 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 208>;
++			status = "disabled";
++		};
++
++		msiof2: spi@e6e00000 {
++			compatible = "renesas,msiof-r8a7745",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 205>;
++			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
++			       <&dmac1 0x41>, <&dmac1 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 205>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7745";
+ 			reg = <0 0xee100000 0 0x328>;
+-- 
+2.19.0
+
diff --git a/patches/0348-ARM-dts-r8a7743-Add-MSIOF-012-support.patch b/patches/0348-ARM-dts-r8a7743-Add-MSIOF-012-support.patch
new file mode 100644
index 00000000000000..1516c7aeed318d
--- /dev/null
+++ b/patches/0348-ARM-dts-r8a7743-Add-MSIOF-012-support.patch
@@ -0,0 +1,91 @@
+From 39ef217c9d3c09d6ec57e1a498a25529ebff823e Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 27 Sep 2017 10:57:04 +0100
+Subject: [PATCH 0348/1795] ARM: dts: r8a7743: Add MSIOF[012] support
+
+Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
+Also, define aliases for spi[123].
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7031a219f649d12acda8a70a4b6b816ee123c8e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 51 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 454f98060d6f..d541fd9ffafb 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -29,6 +29,9 @@
+ 		i2c7 = &iic1;
+ 		i2c8 = &iic3;
+ 		spi0 = &qspi;
++		spi1 = &msiof0;
++		spi2 = &msiof1;
++		spi3 = &msiof2;
+ 	};
+ 
+ 	cpus {
+@@ -852,6 +855,54 @@
+ 			status = "disabled";
+ 		};
+ 
++		msiof0: spi@e6e20000 {
++			compatible = "renesas,msiof-r8a7743",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e20000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 000>;
++			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
++			       <&dmac1 0x51>, <&dmac1 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 000>;
++			status = "disabled";
++		};
++
++		msiof1: spi@e6e10000 {
++			compatible = "renesas,msiof-r8a7743",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e10000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
++			       <&dmac1 0x55>, <&dmac1 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 208>;
++			status = "disabled";
++		};
++
++		msiof2: spi@e6e00000 {
++			compatible = "renesas,msiof-r8a7743",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 205>;
++			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
++			       <&dmac1 0x41>, <&dmac1 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 205>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7743";
+ 			reg = <0 0xee100000 0 0x328>;
+-- 
+2.19.0
+
diff --git a/patches/0349-ARM-dts-gr-peach-Fix-leds-node-name-indent.patch b/patches/0349-ARM-dts-gr-peach-Fix-leds-node-name-indent.patch
new file mode 100644
index 00000000000000..4a022847b5de2b
--- /dev/null
+++ b/patches/0349-ARM-dts-gr-peach-Fix-leds-node-name-indent.patch
@@ -0,0 +1,32 @@
+From 197c7a96da0defc856f838edc5cb4db140911609 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 5 Oct 2017 10:58:18 +0200
+Subject: [PATCH 0349/1795] ARM: dts: gr-peach: Fix 'leds' node name indent
+
+Fix 'leds' node name indent as it was wrongly aligned.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4f049e09d833dd9b8c2b0cf7a609d9fc5f9d6348)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index 13d745bb56a5..a1c5e8823d2b 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -53,7 +53,7 @@
+ 		};
+ 	};
+ 
+-leds {
++	leds {
+ 		status = "okay";
+ 		compatible = "gpio-leds";
+ 
+-- 
+2.19.0
+
diff --git a/patches/0350-ARM-dts-gr-peach-Enable-MTU2-timer-pulse-unit.patch b/patches/0350-ARM-dts-gr-peach-Enable-MTU2-timer-pulse-unit.patch
new file mode 100644
index 00000000000000..31305c35f271f0
--- /dev/null
+++ b/patches/0350-ARM-dts-gr-peach-Enable-MTU2-timer-pulse-unit.patch
@@ -0,0 +1,38 @@
+From 8021ff1808756504b68aab234ba864e6a43218bd Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 5 Oct 2017 10:58:19 +0200
+Subject: [PATCH 0350/1795] ARM: dts: gr-peach: Enable MTU2 timer pulse unit
+
+MTU2 multi-function/multi-channel timer/counter is not enabled for
+GR-Peach board. The timer is used as clock event source to schedule
+wake-ups, and without this enabled all sleeps not performed through busy
+waiting hang the board.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 62cea6d2c6758d6a9513ecf3c70498623d5bf1d2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index a1c5e8823d2b..9661d43f5236 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -78,6 +78,10 @@
+ 	clock-frequency = <48000000>;
+ };
+ 
++&mtu2 {
++	status = "okay";
++};
++
+ &scif2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&scif2_pins>;
+-- 
+2.19.0
+
diff --git a/patches/0351-ARM-dts-r8a7790-Use-generic-node-name-for-VSP1-nodes.patch b/patches/0351-ARM-dts-r8a7790-Use-generic-node-name-for-VSP1-nodes.patch
new file mode 100644
index 00000000000000..dbffab4d1dbf6b
--- /dev/null
+++ b/patches/0351-ARM-dts-r8a7790-Use-generic-node-name-for-VSP1-nodes.patch
@@ -0,0 +1,60 @@
+From 5fe460c89a0e94f10c8f2c9c2a63459c80008082 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:36:46 +0200
+Subject: [PATCH 0351/1795] ARM: dts: r8a7790: Use generic node name for VSP1
+ nodes
+
+Use the preferred generic node name instead of the specific name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9f77b4801944b6c74b871f9252e09177e273212c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 081cf5cdb13b..17a48199b7a9 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1014,7 +1014,7 @@
+ 		status = "disabled";
+ 	};
+ 
+-	vsp1@fe920000 {
++	vsp@fe920000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe920000 0 0x8000>;
+ 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1023,7 +1023,7 @@
+ 		resets = <&cpg 130>;
+ 	};
+ 
+-	vsp1@fe928000 {
++	vsp@fe928000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1032,7 +1032,7 @@
+ 		resets = <&cpg 131>;
+ 	};
+ 
+-	vsp1@fe930000 {
++	vsp@fe930000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1041,7 +1041,7 @@
+ 		resets = <&cpg 128>;
+ 	};
+ 
+-	vsp1@fe938000 {
++	vsp@fe938000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe938000 0 0x8000>;
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0352-ARM-dts-r8a7791-Use-generic-node-name-for-VSP1-nodes.patch b/patches/0352-ARM-dts-r8a7791-Use-generic-node-name-for-VSP1-nodes.patch
new file mode 100644
index 00000000000000..4be00dc9aa80ed
--- /dev/null
+++ b/patches/0352-ARM-dts-r8a7791-Use-generic-node-name-for-VSP1-nodes.patch
@@ -0,0 +1,51 @@
+From df30c9a8d7830eeb517dd6a036f0d66dee9de3da Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:36:47 +0200
+Subject: [PATCH 0352/1795] ARM: dts: r8a7791: Use generic node name for VSP1
+ nodes
+
+Use the preferred generic node name instead of the specific name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 18e5500c1510c844d5c3071f06089b638326bc52)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 5a8a15847076..97bed8253bc3 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -1073,7 +1073,7 @@
+ 		status = "disabled";
+ 	};
+ 
+-	vsp1@fe928000 {
++	vsp@fe928000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1082,7 +1082,7 @@
+ 		resets = <&cpg 131>;
+ 	};
+ 
+-	vsp1@fe930000 {
++	vsp@fe930000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1091,7 +1091,7 @@
+ 		resets = <&cpg 128>;
+ 	};
+ 
+-	vsp1@fe938000 {
++	vsp@fe938000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe938000 0 0x8000>;
+ 		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0353-ARM-dts-r8a7792-Use-generic-node-name-for-VSP1-nodes.patch b/patches/0353-ARM-dts-r8a7792-Use-generic-node-name-for-VSP1-nodes.patch
new file mode 100644
index 00000000000000..a3e84f8004f88b
--- /dev/null
+++ b/patches/0353-ARM-dts-r8a7792-Use-generic-node-name-for-VSP1-nodes.patch
@@ -0,0 +1,51 @@
+From f0c581605ab095ba6b5e08cd8958b78242ee7b01 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:36:48 +0200
+Subject: [PATCH 0353/1795] ARM: dts: r8a7792: Use generic node name for VSP1
+ nodes
+
+Use the preferred generic node name instead of the specific name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2ea2e06cdac491cf254ce6221371a6993e7a46fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index c332f77ebb6b..549eafe8ff12 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -794,7 +794,7 @@
+ 			status = "disabled";
+ 		};
+ 
+-		vsp1@fe928000 {
++		vsp@fe928000 {
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe928000 0 0x8000>;
+ 			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+@@ -803,7 +803,7 @@
+ 			resets = <&cpg 131>;
+ 		};
+ 
+-		vsp1@fe930000 {
++		vsp@fe930000 {
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe930000 0 0x8000>;
+ 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+@@ -812,7 +812,7 @@
+ 			resets = <&cpg 128>;
+ 		};
+ 
+-		vsp1@fe938000 {
++		vsp@fe938000 {
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe938000 0 0x8000>;
+ 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0354-ARM-dts-r8a7794-Use-generic-node-name-for-VSP1-nodes.patch b/patches/0354-ARM-dts-r8a7794-Use-generic-node-name-for-VSP1-nodes.patch
new file mode 100644
index 00000000000000..2f543d65fa54b1
--- /dev/null
+++ b/patches/0354-ARM-dts-r8a7794-Use-generic-node-name-for-VSP1-nodes.patch
@@ -0,0 +1,42 @@
+From 2bc2d1aba4fbf74f4d0b5d0c11952c0c84838395 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 4 Oct 2017 14:36:49 +0200
+Subject: [PATCH 0354/1795] ARM: dts: r8a7794: Use generic node name for VSP1
+ nodes
+
+Use the preferred generic node name instead of the specific name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8b40ea19233cc53f9d5d33a44d6fc833a765bab2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 035c33715b65..19cff0dd90cf 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -970,7 +970,7 @@
+ 		};
+ 	};
+ 
+-	vsp1@fe928000 {
++	vsp@fe928000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe928000 0 0x8000>;
+ 		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+@@ -979,7 +979,7 @@
+ 		resets = <&cpg 131>;
+ 	};
+ 
+-	vsp1@fe930000 {
++	vsp@fe930000 {
+ 		compatible = "renesas,vsp1";
+ 		reg = <0 0xfe930000 0 0x8000>;
+ 		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0355-ARM-dts-iwg20d-q7-Rework-DT-architecture.patch b/patches/0355-ARM-dts-iwg20d-q7-Rework-DT-architecture.patch
new file mode 100644
index 00000000000000..608c17b457871e
--- /dev/null
+++ b/patches/0355-ARM-dts-iwg20d-q7-Rework-DT-architecture.patch
@@ -0,0 +1,354 @@
+From 16762b33fc60038d19a2bd2bc712ecb003b0e609 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 6 Oct 2017 18:59:52 +0100
+Subject: [PATCH 0355/1795] ARM: dts: iwg20d-q7: Rework DT architecture
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since the same carrier board may host RZ/G1M and RZ/G1N based
+Systems on Module, the DT architecture for iwg20d-q7 needs
+better decoupling. This patch provides:
+* iwg20d-q7-common.dtsi - its purpose is to define the carrier
+  board definitions, and its content is basically the same
+  as the previous version of r8a7743-iwg20d-q7.dts, only it
+  has no reference to the SoM .dtsi, and that's why the
+  filename doesn't mention the SoC name any more.
+* r8a7743-iwg20d-q7.dts - its new purpose is to put together
+  the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
+  .dtsi defined by this very patch, along with "model" and
+  "compatible" properties.
+The final DT architecture to describe the board is now:
+r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
+├── r8a7743-iwg20m.dtsi         # SoM
+│   └── r8a7743.dtsi            # SoC
+└── iwg20d-q7-common.dtsi       # Carrier Board
+and maximizes the reuse of the definitions for the carrier board
+and for the SoM.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 147 ++++++++++++++++++++++++
+ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 139 +---------------------
+ 2 files changed, 149 insertions(+), 137 deletions(-)
+ create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+new file mode 100644
+index 000000000000..1c072c0a4888
+--- /dev/null
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -0,0 +1,147 @@
++/*
++ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/ {
++	aliases {
++		serial0 = &scif0;
++		ethernet0 = &avb;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
++		stdout-path = "serial0:115200n8";
++	};
++
++	vcc_sdhi1: regulator-vcc-sdhi1 {
++		compatible = "regulator-fixed";
++
++		regulator-name = "SDHI1 Vcc";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
++	};
++
++	vccq_sdhi1: regulator-vccq-sdhi1 {
++		compatible = "regulator-gpio";
++
++		regulator-name = "SDHI1 VccQ";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
++		gpios-states = <1>;
++		states = <3300000 1
++			  1800000 0>;
++	};
++};
++
++&avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
++	phy-handle = <&phy3>;
++	phy-mode = "gmii";
++	renesas,no-ether-link;
++	status = "okay";
++
++	phy3: ethernet-phy@3 {
++		reg = <3>;
++		micrel,led-mode = <1>;
++	};
++};
++
++&i2c2 {
++	pinctrl-0 = <&i2c2_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	rtc@68 {
++		compatible = "ti,bq32000";
++		reg = <0x68>;
++	};
++};
++
++&pci0 {
++	status = "okay";
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++};
++
++&pci1 {
++	status = "okay";
++	pinctrl-0 = <&usb1_pins>;
++	pinctrl-names = "default";
++};
++
++&pfc {
++	avb_pins: avb {
++		groups = "avb_mdio", "avb_gmii";
++		function = "avb";
++	};
++
++	i2c2_pins: i2c2 {
++		groups = "i2c2";
++		function = "i2c2";
++	};
++
++	scif0_pins: scif0 {
++		groups = "scif0_data_d";
++		function = "scif0";
++	};
++
++	sdhi1_pins: sd1 {
++		groups = "sdhi1_data4", "sdhi1_ctrl";
++		function = "sdhi1";
++		power-source = <3300>;
++	};
++
++	sdhi1_pins_uhs: sd1_uhs {
++		groups = "sdhi1_data4", "sdhi1_ctrl";
++		function = "sdhi1";
++		power-source = <1800>;
++	};
++
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
++
++	usb1_pins: usb1 {
++		groups = "usb1";
++		function = "usb1";
++	};
++};
++
++&scif0 {
++	pinctrl-0 = <&scif0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&sdhi1 {
++	pinctrl-0 = <&sdhi1_pins>;
++	pinctrl-1 = <&sdhi1_pins_uhs>;
++	pinctrl-names = "default", "state_uhs";
++
++	vmmc-supply = <&vcc_sdhi1>;
++	vqmmc-supply = <&vccq_sdhi1>;
++	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
++	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
++	sd-uhs-sdr50;
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+index 0136864bc595..6aa6b7467704 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Device Tree Source for the iWave-RZG1M Qseven carrier board
++ * Device Tree Source for the iWave-RZ/G1M Qseven board
+  *
+  * Copyright (C) 2017 Renesas Electronics Corp.
+  *
+@@ -10,144 +10,9 @@
+ 
+ /dts-v1/;
+ #include "r8a7743-iwg20m.dtsi"
++#include "iwg20d-q7-common.dtsi"
+ 
+ / {
+ 	model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
+ 	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
+-
+-	aliases {
+-		serial0 = &scif0;
+-		ethernet0 = &avb;
+-	};
+-
+-	chosen {
+-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+-		stdout-path = "serial0:115200n8";
+-	};
+-
+-	vcc_sdhi1: regulator-vcc-sdhi1 {
+-		compatible = "regulator-fixed";
+-
+-		regulator-name = "SDHI1 Vcc";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-
+-		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+-	};
+-
+-	vccq_sdhi1: regulator-vccq-sdhi1 {
+-		compatible = "regulator-gpio";
+-
+-		regulator-name = "SDHI1 VccQ";
+-		regulator-min-microvolt = <1800000>;
+-		regulator-max-microvolt = <3300000>;
+-
+-		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+-		gpios-states = <1>;
+-		states = <3300000 1
+-			  1800000 0>;
+-	};
+-};
+-
+-&pfc {
+-	i2c2_pins: i2c2 {
+-		groups = "i2c2";
+-		function = "i2c2";
+-	};
+-
+-	scif0_pins: scif0 {
+-		groups = "scif0_data_d";
+-		function = "scif0";
+-	};
+-
+-	avb_pins: avb {
+-		groups = "avb_mdio", "avb_gmii";
+-		function = "avb";
+-	};
+-
+-	sdhi1_pins: sd1 {
+-		groups = "sdhi1_data4", "sdhi1_ctrl";
+-		function = "sdhi1";
+-		power-source = <3300>;
+-	};
+-
+-	sdhi1_pins_uhs: sd1_uhs {
+-		groups = "sdhi1_data4", "sdhi1_ctrl";
+-		function = "sdhi1";
+-		power-source = <1800>;
+-	};
+-
+-	usb0_pins: usb0 {
+-		groups = "usb0";
+-		function = "usb0";
+-	};
+-
+-	usb1_pins: usb1 {
+-		groups = "usb1";
+-		function = "usb1";
+-	};
+-};
+-
+-&scif0 {
+-	pinctrl-0 = <&scif0_pins>;
+-	pinctrl-names = "default";
+-
+-	status = "okay";
+-};
+-
+-&avb {
+-	pinctrl-0 = <&avb_pins>;
+-	pinctrl-names = "default";
+-
+-	phy-handle = <&phy3>;
+-	phy-mode = "gmii";
+-	renesas,no-ether-link;
+-	status = "okay";
+-
+-	phy3: ethernet-phy@3 {
+-		reg = <3>;
+-		micrel,led-mode = <1>;
+-	};
+-};
+-
+-&sdhi1 {
+-	pinctrl-0 = <&sdhi1_pins>;
+-	pinctrl-1 = <&sdhi1_pins_uhs>;
+-	pinctrl-names = "default", "state_uhs";
+-
+-	vmmc-supply = <&vcc_sdhi1>;
+-	vqmmc-supply = <&vccq_sdhi1>;
+-	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+-	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+-	sd-uhs-sdr50;
+-	status = "okay";
+-};
+-
+-&i2c2 {
+-	pinctrl-0 = <&i2c2_pins>;
+-	pinctrl-names = "default";
+-
+-	status = "okay";
+-	clock-frequency = <400000>;
+-
+-	rtc@68 {
+-		compatible = "ti,bq32000";
+-		reg = <0x68>;
+-	};
+-};
+-
+-&pci0 {
+-	status = "okay";
+-	pinctrl-0 = <&usb0_pins>;
+-	pinctrl-names = "default";
+-};
+-
+-&pci1 {
+-	status = "okay";
+-	pinctrl-0 = <&usb1_pins>;
+-	pinctrl-names = "default";
+-};
+-
+-&usbphy {
+-	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0356-ARM-dts-iwg20d-q7-dbcm-ca-Add-device-trees-for-camer.patch b/patches/0356-ARM-dts-iwg20d-q7-dbcm-ca-Add-device-trees-for-camer.patch
new file mode 100644
index 00000000000000..c37b030effbd90
--- /dev/null
+++ b/patches/0356-ARM-dts-iwg20d-q7-dbcm-ca-Add-device-trees-for-camer.patch
@@ -0,0 +1,115 @@
+From a8cc1d99bb84c57292f92a6c12369b618f0ef635 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 6 Oct 2017 18:59:53 +0100
+Subject: [PATCH 0356/1795] ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for
+ camera DB
+
+This patch adds a .dtsi that describes the camera daughter board
+and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's
+RZ/G1M/G1N Qseven carrier board, and the camera daughter board.
+The camera daughter board .dtsi adds support for ttySC[14].
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2ee18841ff649e973d62afc6096b892396a676ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/Makefile                    |  1 +
+ arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi      | 43 +++++++++++++++++++
+ .../boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts    | 19 ++++++++
+ 3 files changed, 63 insertions(+)
+ create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
+ create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 2fca3799bef6..b6c97b70e85f 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -725,6 +725,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
+ 	r8a73a4-ape6evm.dtb \
+ 	r8a7740-armadillo800eva.dtb \
+ 	r8a7743-iwg20d-q7.dtb \
++	r8a7743-iwg20d-q7-dbcm-ca.dtb \
+ 	r8a7743-sk-rzg1m.dtb \
+ 	r8a7745-iwg22d-sodimm.dtb \
+ 	r8a7745-sk-rzg1e.dtb \
+diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
+new file mode 100644
+index 000000000000..31fab5f183a9
+--- /dev/null
++++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
+@@ -0,0 +1,43 @@
++/*
++ * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/ {
++	aliases {
++		serial1 = &scif1;
++		serial4 = &hscif1;
++	};
++};
++
++&hscif1 {
++	pinctrl-0 = <&hscif1_pins>;
++	pinctrl-names = "default";
++
++	uart-has-rtscts;
++	status = "okay";
++};
++
++&pfc {
++	hscif1_pins: hscif1 {
++		groups = "hscif1_data_c", "hscif1_ctrl_c";
++		function = "hscif1";
++	};
++
++	scif1_pins: scif1 {
++		groups = "scif1_data_d";
++		function = "scif1";
++	};
++};
++
++&scif1 {
++	pinctrl-0 = <&scif1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+new file mode 100644
+index 000000000000..d90eb8464222
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+@@ -0,0 +1,19 @@
++/*
++ * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a7743-iwg20m.dtsi"
++#include "iwg20d-q7-common.dtsi"
++#include "iwg20d-q7-dbcm-ca.dtsi"
++
++/ {
++	model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
++	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
++};
+-- 
+2.19.0
+
diff --git a/patches/0357-ARM-shmobile-rcar-gen2-fix-non-SMP-build.patch b/patches/0357-ARM-shmobile-rcar-gen2-fix-non-SMP-build.patch
new file mode 100644
index 00000000000000..07d0be3a160026
--- /dev/null
+++ b/patches/0357-ARM-shmobile-rcar-gen2-fix-non-SMP-build.patch
@@ -0,0 +1,43 @@
+From 0fd0162006ab86bf8ea25ae63abdb03c3e932b13 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 5 Oct 2017 14:09:04 +0200
+Subject: [PATCH 0357/1795] ARM: shmobile: rcar-gen2: fix non-SMP build
+
+A bugfix for the SMP case broke the build for the UP case:
+
+arch/arm/mach-shmobile/headsmp-apmu.o: In function `shmobile_boot_apmu':
+(.text+0x34): undefined reference to `secondary_startup'
+
+The assembler file mixes code that is used for SMP with code
+that we also need on a single-CPU build, so I'm leaving it
+always enabled in the Makefile, but enclose the SMP code
+in an #ifdef.
+
+Fixes: fd45a136ff6 ("ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 703ef76b8fd5169d5cff30de5b958d6728b9a147)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/headsmp-apmu.S | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
+index db4743d2bf91..5672b5849401 100644
+--- a/arch/arm/mach-shmobile/headsmp-apmu.S
++++ b/arch/arm/mach-shmobile/headsmp-apmu.S
+@@ -31,7 +31,9 @@ ENTRY(shmobile_init_cntvoff)
+ 	ret	lr
+ ENDPROC(shmobile_init_cntvoff)
+ 
++#ifdef CONFIG_SMP
+ ENTRY(shmobile_boot_apmu)
+ 	bl	shmobile_init_cntvoff
+ 	b	secondary_startup
+ ENDPROC(shmobile_boot_apmu)
++#endif
+-- 
+2.19.0
+
diff --git a/patches/0358-ARM-dts-r8a7790-add-cpu-capacity-dmips-mhz-informati.patch b/patches/0358-ARM-dts-r8a7790-add-cpu-capacity-dmips-mhz-informati.patch
new file mode 100644
index 00000000000000..d9da7c786493b1
--- /dev/null
+++ b/patches/0358-ARM-dts-r8a7790-add-cpu-capacity-dmips-mhz-informati.patch
@@ -0,0 +1,110 @@
+From 411620ade654d757bc374b32abc778a68b1b62d7 Mon Sep 17 00:00:00 2001
+From: Dietmar Eggemann <dietmar.eggemann@arm.com>
+Date: Wed, 30 Aug 2017 15:41:20 +0100
+Subject: [PATCH 0358/1795] ARM: dts: r8a7790: add cpu capacity-dmips-mhz
+ information
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The following 'capacity-dmips-mhz' dt property values are used:
+
+Cortex-A15: 1024, Cortex-A7: 539
+
+They have been derived form the cpu_efficiency values:
+
+Cortex-A15: 3891, Cortex-A7: 2048
+
+by scaling them so that the Cortex-A15s (big cores) use 1024.
+
+The cpu_efficiency values were originally derived from the "Big.LITTLE
+Processing with ARM Cortex™-A15 & Cortex-A7" white paper
+(http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x
+(3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the
+Dhrystone benchmark.
+
+The following platform is affected once cpu-invariant accounting
+support is re-connected to the task scheduler:
+
+r8a7790-lager
+
+Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5bdc81259bb0efd5bd71820ef15757b70beae751)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 17a48199b7a9..92b7f3bd8b69 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -56,6 +56,7 @@
+ 			clock-latency = <300000>; /* 300 us */
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+ 			next-level-cache = <&L2_CA15>;
++			capacity-dmips-mhz = <1024>;
+ 
+ 			/* kHz - uV - OPPs unknown yet */
+ 			operating-points = <1400000 1000000>,
+@@ -73,6 +74,7 @@
+ 			clock-frequency = <1300000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+ 			next-level-cache = <&L2_CA15>;
++			capacity-dmips-mhz = <1024>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -82,6 +84,7 @@
+ 			clock-frequency = <1300000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+ 			next-level-cache = <&L2_CA15>;
++			capacity-dmips-mhz = <1024>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -91,6 +94,7 @@
+ 			clock-frequency = <1300000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+ 			next-level-cache = <&L2_CA15>;
++			capacity-dmips-mhz = <1024>;
+ 		};
+ 
+ 		cpu4: cpu@100 {
+@@ -100,6 +104,7 @@
+ 			clock-frequency = <780000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+ 			next-level-cache = <&L2_CA7>;
++			capacity-dmips-mhz = <539>;
+ 		};
+ 
+ 		cpu5: cpu@101 {
+@@ -109,6 +114,7 @@
+ 			clock-frequency = <780000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+ 			next-level-cache = <&L2_CA7>;
++			capacity-dmips-mhz = <539>;
+ 		};
+ 
+ 		cpu6: cpu@102 {
+@@ -118,6 +124,7 @@
+ 			clock-frequency = <780000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+ 			next-level-cache = <&L2_CA7>;
++			capacity-dmips-mhz = <539>;
+ 		};
+ 
+ 		cpu7: cpu@103 {
+@@ -127,6 +134,7 @@
+ 			clock-frequency = <780000000>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+ 			next-level-cache = <&L2_CA7>;
++			capacity-dmips-mhz = <539>;
+ 		};
+ 
+ 		L2_CA15: cache-controller-0 {
+-- 
+2.19.0
+
diff --git a/patches/0359-ARM-dts-r8a7745-Add-internal-PCI-bridge-nodes.patch b/patches/0359-ARM-dts-r8a7745-Add-internal-PCI-bridge-nodes.patch
new file mode 100644
index 00000000000000..aa568d0e55ee55
--- /dev/null
+++ b/patches/0359-ARM-dts-r8a7745-Add-internal-PCI-bridge-nodes.patch
@@ -0,0 +1,78 @@
+From 9354b4e81df0df6e48729786dfbf27ceed3043f2 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:58:57 +0100
+Subject: [PATCH 0359/1795] ARM: dts: r8a7745: Add internal PCI bridge nodes
+
+Add device nodes for the r8a7745 internal PCI bridge devices.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ab290a32925e6f7db9e71546098077b3e72cc617)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 46 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 6ba3b8b04edb..b4e9536a84d6 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -845,6 +845,52 @@
+ 			resets = <&cpg 311>;
+ 			status = "disabled";
+ 		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7745",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7745",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0360-ARM-dts-r8a7745-Add-USB-PHY-DT-support.patch b/patches/0360-ARM-dts-r8a7745-Add-USB-PHY-DT-support.patch
new file mode 100644
index 00000000000000..c12e1258f6f6b1
--- /dev/null
+++ b/patches/0360-ARM-dts-r8a7745-Add-USB-PHY-DT-support.patch
@@ -0,0 +1,54 @@
+From 12e38865e6bbce1fa5869a7fb42b222a8c143997 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:58:58 +0100
+Subject: [PATCH 0360/1795] ARM: dts: r8a7745: Add USB PHY DT support
+
+Define the r8a7745 generic part of the USB PHY device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 237173a4bbf4c0710dbb7c35a4e2763671d293df)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index b4e9536a84d6..17cfa53f3c76 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -891,6 +891,28 @@
+ 					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
++
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7745",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0361-ARM-dts-r8a7745-Link-PCI-USB-devices-to-USB-PHY.patch b/patches/0361-ARM-dts-r8a7745-Link-PCI-USB-devices-to-USB-PHY.patch
new file mode 100644
index 00000000000000..9f2bc5b98bfefa
--- /dev/null
+++ b/patches/0361-ARM-dts-r8a7745-Link-PCI-USB-devices-to-USB-PHY.patch
@@ -0,0 +1,64 @@
+From 070402edc4ea80d4ab9b25fe31c9aa1f4926ec2a Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:58:59 +0100
+Subject: [PATCH 0361/1795] ARM: dts: r8a7745: Link PCI USB devices to USB PHY
+
+Describe the PCI USB devices that are behind the PCI bridges, adding
+necessary links to the USB PHY device.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c3e35873e37b77581be942b7284e705e997014fc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 17cfa53f3c76..3a50f703601c 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -867,6 +867,18 @@
+ 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
+ 		};
+ 
+ 		pci1: pci@ee0d0000 {
+@@ -890,6 +902,18 @@
+ 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
+ 		};
+ 
+ 		usbphy: usb-phy@e6590100 {
+-- 
+2.19.0
+
diff --git a/patches/0362-ARM-dts-iwg22d-sodimm-Enable-internal-PCI.patch b/patches/0362-ARM-dts-iwg22d-sodimm-Enable-internal-PCI.patch
new file mode 100644
index 00000000000000..7ef3b85e6f55fc
--- /dev/null
+++ b/patches/0362-ARM-dts-iwg22d-sodimm-Enable-internal-PCI.patch
@@ -0,0 +1,48 @@
+From bb213fd07ad2ee702b1e8bb0faa602a4b6b0e481 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:59:00 +0100
+Subject: [PATCH 0362/1795] ARM: dts: iwg22d-sodimm: Enable internal PCI
+
+Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers
+attached to them.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bc058f6f03e47610c994a97ecf3bf8a3ea44efee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 8772c561e3a8..e378e5ecfcac 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -55,6 +55,11 @@
+ 		function = "sdhi0";
+ 		power-source = <3300>;
+ 	};
++
++	usb1_pins: usb1 {
++		groups = "usb1";
++		function = "usb1";
++	};
+ };
+ 
+ &scif4 {
+@@ -92,3 +97,9 @@
+ 	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ 	status = "okay";
+ };
++
++&pci1 {
++	status = "okay";
++	pinctrl-0 = <&usb1_pins>;
++	pinctrl-names = "default";
++};
+-- 
+2.19.0
+
diff --git a/patches/0363-ARM-dts-iwg22d-sodimm-Enable-USB-PHY.patch b/patches/0363-ARM-dts-iwg22d-sodimm-Enable-USB-PHY.patch
new file mode 100644
index 00000000000000..3db61e01cb0321
--- /dev/null
+++ b/patches/0363-ARM-dts-iwg22d-sodimm-Enable-USB-PHY.patch
@@ -0,0 +1,31 @@
+From 1e3fa967de72779d6549221efd1c643dd8ce8329 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:59:01 +0100
+Subject: [PATCH 0363/1795] ARM: dts: iwg22d-sodimm: Enable USB PHY
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aea3c9d9726148331d874c2b91aeb663430099d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index e378e5ecfcac..52153ec3638c 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -103,3 +103,7 @@
+ 	pinctrl-0 = <&usb1_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0364-ARM-dts-r8a7743-Add-HS-USB-device-node.patch b/patches/0364-ARM-dts-r8a7743-Add-HS-USB-device-node.patch
new file mode 100644
index 00000000000000..d7af4cf7dad82c
--- /dev/null
+++ b/patches/0364-ARM-dts-r8a7743-Add-HS-USB-device-node.patch
@@ -0,0 +1,47 @@
+From 947d458159c41ad526d67da3b3fb1f789ca20d73 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:21:18 +0100
+Subject: [PATCH 0364/1795] ARM: dts: r8a7743: Add HS-USB device node
+
+Define the R8A7743 generic part of the HS-USB device node. It is up to the
+board file to enable the device.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4b4a3b1c33b7a389d90624683d8f1a8d1dc2affa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index d541fd9ffafb..080eff9bb3c3 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -945,6 +945,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7743",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
+ 		usbphy: usb-phy@e6590100 {
+ 			compatible = "renesas,usb-phy-r8a7743",
+ 				     "renesas,rcar-gen2-usb-phy";
+-- 
+2.19.0
+
diff --git a/patches/0365-ARM-dts-iwg20d-q7-Enable-HS-USB.patch b/patches/0365-ARM-dts-iwg20d-q7-Enable-HS-USB.patch
new file mode 100644
index 00000000000000..04ac2188de01e8
--- /dev/null
+++ b/patches/0365-ARM-dts-iwg20d-q7-Enable-HS-USB.patch
@@ -0,0 +1,49 @@
+From 95234bd9270f928699852899f0fb70cf0c6ac134 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 11 Oct 2017 10:04:33 +0100
+Subject: [PATCH 0365/1795] ARM: dts: iwg20d-q7: Enable HS-USB
+
+Enable HS-USB device for the iWave G20D-Q7 carrier board based on
+RZ/G1M.
+Also disable the host mode support on usb otg port by default to avoid
+pin conflicts.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 405b580227ff1ae8fde82a666a2a5c0391a7e64a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 1c072c0a4888..efd8af9242d1 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -58,6 +58,12 @@
+ 	};
+ };
+ 
++&hsusb {
++	status = "okay";
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++};
++
+ &i2c2 {
+ 	pinctrl-0 = <&i2c2_pins>;
+ 	pinctrl-names = "default";
+@@ -72,7 +78,6 @@
+ };
+ 
+ &pci0 {
+-	status = "okay";
+ 	pinctrl-0 = <&usb0_pins>;
+ 	pinctrl-names = "default";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0366-ARM-dts-r8a7743-Add-USB-DMAC-device-nodes.patch b/patches/0366-ARM-dts-r8a7743-Add-USB-DMAC-device-nodes.patch
new file mode 100644
index 00000000000000..a08561355c5f80
--- /dev/null
+++ b/patches/0366-ARM-dts-r8a7743-Add-USB-DMAC-device-nodes.patch
@@ -0,0 +1,58 @@
+From c48fda1c61636880c65acc88c30b360b47100bc8 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:21:20 +0100
+Subject: [PATCH 0366/1795] ARM: dts: r8a7743: Add USB-DMAC device nodes
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 310861003a0d59cb410538bcdf73a218157a111d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 080eff9bb3c3..de89295ce63a 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -355,6 +355,34 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7743-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7743-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
+ 		/* The memory map in the User's Manual maps the cores to bus
+ 		 *  numbers
+ 		 */
+-- 
+2.19.0
+
diff --git a/patches/0367-ARM-dts-r8a7743-Enable-DMA-for-HSUSB.patch b/patches/0367-ARM-dts-r8a7743-Enable-DMA-for-HSUSB.patch
new file mode 100644
index 00000000000000..9a7be8d22535b6
--- /dev/null
+++ b/patches/0367-ARM-dts-r8a7743-Enable-DMA-for-HSUSB.patch
@@ -0,0 +1,35 @@
+From 759882d9670e03790c7bf95b673c56b7f276ecfb Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Oct 2017 14:21:21 +0100
+Subject: [PATCH 0367/1795] ARM: dts: r8a7743: Enable DMA for HSUSB
+
+This patch adds DMA properties to the HSUSB node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e0a10e7b070624965f20205c59fb2a0c0b465782)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index de89295ce63a..699c04003eac 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -979,6 +979,9 @@
+ 			reg = <0 0xe6590000 0 0x100>;
+ 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ 			resets = <&cpg 704>;
+ 			renesas,buswait = <4>;
+-- 
+2.19.0
+
diff --git a/patches/0368-ARM-dts-gr-peach-Add-ETHER-pin-group.patch b/patches/0368-ARM-dts-gr-peach-Add-ETHER-pin-group.patch
new file mode 100644
index 00000000000000..d0bfd172ebc288
--- /dev/null
+++ b/patches/0368-ARM-dts-gr-peach-Add-ETHER-pin-group.patch
@@ -0,0 +1,74 @@
+From 30bc7176644a8c333af54344268411e3a4aa318c Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Mon, 9 Oct 2017 10:48:34 +0200
+Subject: [PATCH 0368/1795] ARM: dts: gr-peach: Add ETHER pin group
+
+Add pin configuration subnode for ETHER pin group.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 349adfbf27269bad4fa6915e77c97a06487266a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 39 +++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index 9661d43f5236..eca14e3801ec 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -68,6 +68,28 @@
+ 		/* P6_2 as RxD2; P6_3 as TxD2 */
+ 		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
+ 	};
++
++	ether_pins: ether {
++		/* Ethernet on Ports 1,3,5,10 */
++		pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
++			 <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
++			 <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
++			 <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
++			 <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
++			 <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
++			 <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
++			 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
++			 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
++			 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
++			 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
++			 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
++			 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
++			 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
++			 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
++			 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
++			 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
++			 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
++	};
+ };
+ 
+ &extal_clk {
+@@ -88,3 +110,20 @@
+ 
+ 	status = "okay";
+ };
++
++&ether {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ether_pins>;
++
++	status = "okay";
++
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++
++	phy0: ethernet-phy@0 {
++		reg = <0>;
++
++		reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
++		reset-delay-us = <5>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0369-ARM-dts-gr-peach-Enable-ostm0-and-ostm1-timers.patch b/patches/0369-ARM-dts-gr-peach-Enable-ostm0-and-ostm1-timers.patch
new file mode 100644
index 00000000000000..104bb9fe8e26ee
--- /dev/null
+++ b/patches/0369-ARM-dts-gr-peach-Enable-ostm0-and-ostm1-timers.patch
@@ -0,0 +1,49 @@
+From 220560cedb30236cef3392b5c91a34c0dc5d7dfc Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Mon, 9 Oct 2017 10:48:35 +0200
+Subject: [PATCH 0369/1795] ARM: dts: gr-peach: Enable ostm0 and ostm1 timers
+
+Enable ostm0 and ostm1 timers to be used as clock source and clockevent
+source. The timers provides greater accuracy than the already enabled
+mtu2 one.
+
+With these enabled:
+
+clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns
+sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns
+ostm: used for clocksource
+ostm: used for clock events
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Suggested-by: Chris Brandt <chris.brandt@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1126e108a3ad8ae92a0532259e3da4b14072355f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-gr-peach.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+index eca14e3801ec..779f724b4531 100644
+--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
++++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
+@@ -104,6 +104,14 @@
+ 	status = "okay";
+ };
+ 
++&ostm0 {
++	status = "okay";
++};
++
++&ostm1 {
++	status = "okay";
++};
++
+ &scif2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&scif2_pins>;
+-- 
+2.19.0
+
diff --git a/patches/0370-ARM-dts-r8a7778-Use-R-Car-GPIO-Gen1-fallback-compat-.patch b/patches/0370-ARM-dts-r8a7778-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
new file mode 100644
index 00000000000000..2e02542cc9bc10
--- /dev/null
+++ b/patches/0370-ARM-dts-r8a7778-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
@@ -0,0 +1,85 @@
+From 265433338c117cfe3b48d1ab9639316b82e1759e Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:02 +0200
+Subject: [PATCH 0370/1795] ARM: dts: r8a7778: Use R-Car GPIO Gen1 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen1 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in DT of r8a7778 SoC.
+
+As the driver does not match on "renesas,gpio-r8a7778" there
+are some run-time considerations for this patch:
+
+* When a resulting DTB is used with kernels newer than v4.14 this should
+  not have any run-time effect as renesas,rcar-gen1-gpio is matched by the
+  driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback
+  compatibility strings")
+
+* However, when used with older kernels GPIO will be disabled as
+  no compat string match will be made by the driver.
+
+The regression documented above for the new DTB with old kernel case
+is acceptable in my opinion.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9b43ba66f145127025cf82a35f47f228ea936935)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7778.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
+index 8f3156c0e575..a31817b2dda7 100644
+--- a/arch/arm/boot/dts/r8a7778.dtsi
++++ b/arch/arm/boot/dts/r8a7778.dtsi
+@@ -88,7 +88,7 @@
+ 	};
+ 
+ 	gpio0: gpio@ffc40000 {
+-		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc40000 0x2c>;
+ 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -99,7 +99,7 @@
+ 	};
+ 
+ 	gpio1: gpio@ffc41000 {
+-		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc41000 0x2c>;
+ 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -110,7 +110,7 @@
+ 	};
+ 
+ 	gpio2: gpio@ffc42000 {
+-		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc42000 0x2c>;
+ 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -121,7 +121,7 @@
+ 	};
+ 
+ 	gpio3: gpio@ffc43000 {
+-		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc43000 0x2c>;
+ 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -132,7 +132,7 @@
+ 	};
+ 
+ 	gpio4: gpio@ffc44000 {
+-		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc44000 0x2c>;
+ 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0371-ARM-dts-r8a7779-Use-R-Car-GPIO-Gen1-fallback-compat-.patch b/patches/0371-ARM-dts-r8a7779-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
new file mode 100644
index 00000000000000..e95f2364f9371b
--- /dev/null
+++ b/patches/0371-ARM-dts-r8a7779-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
@@ -0,0 +1,103 @@
+From d48e4046d1f3d07f05062fb82c279d0eb4c83681 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:03 +0200
+Subject: [PATCH 0371/1795] ARM: dts: r8a7779: Use R-Car GPIO Gen1 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen1 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in DT of r8a7779 SoC.
+
+As the driver does not match on "renesas,gpio-r8a7779" there
+are some run-time considerations for this patch:
+
+* When a resulting DTB is used with kernels newer than v4.14 this should
+  not have any run-time effect as renesas,rcar-gen1-gpio is matched by the
+  driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback
+  compatibility strings")
+
+* However, when used with older kernels GPIO will be disabled as
+  no compat string match will be made by the driver.
+
+The regression documented above for the new DTB with old kernel case
+is acceptable in my opinion.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 88cb141b84ca665110ef36db76294453b83486df)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7779.dtsi | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
+index 8ee0b2ca5d39..ccef2cfab6e0 100644
+--- a/arch/arm/boot/dts/r8a7779.dtsi
++++ b/arch/arm/boot/dts/r8a7779.dtsi
+@@ -76,7 +76,7 @@
+ 	};
+ 
+ 	gpio0: gpio@ffc40000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc40000 0x2c>;
+ 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -87,7 +87,7 @@
+ 	};
+ 
+ 	gpio1: gpio@ffc41000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc41000 0x2c>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -98,7 +98,7 @@
+ 	};
+ 
+ 	gpio2: gpio@ffc42000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc42000 0x2c>;
+ 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -109,7 +109,7 @@
+ 	};
+ 
+ 	gpio3: gpio@ffc43000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc43000 0x2c>;
+ 		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -120,7 +120,7 @@
+ 	};
+ 
+ 	gpio4: gpio@ffc44000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc44000 0x2c>;
+ 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -131,7 +131,7 @@
+ 	};
+ 
+ 	gpio5: gpio@ffc45000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc45000 0x2c>;
+ 		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -142,7 +142,7 @@
+ 	};
+ 
+ 	gpio6: gpio@ffc46000 {
+-		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
+ 		reg = <0xffc46000 0x2c>;
+ 		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0372-ARM-dts-r8a7743-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0372-ARM-dts-r8a7743-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..994438f38e8cd9
--- /dev/null
+++ b/patches/0372-ARM-dts-r8a7743-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,101 @@
+From fddd8b8f28b27ff7d05543e93ae27aa51c9dc37d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:04 +0200
+Subject: [PATCH 0372/1795] ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7743 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 936e7d7472547294fa305f60546afad232896fdc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 699c04003eac..f29f15d4d659 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -108,7 +108,7 @@
+ 
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6050000 0 0x50>;
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -123,7 +123,7 @@
+ 
+ 		gpio1: gpio@e6051000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6051000 0 0x50>;
+ 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -138,7 +138,7 @@
+ 
+ 		gpio2: gpio@e6052000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6052000 0 0x50>;
+ 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -153,7 +153,7 @@
+ 
+ 		gpio3: gpio@e6053000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6053000 0 0x50>;
+ 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -168,7 +168,7 @@
+ 
+ 		gpio4: gpio@e6054000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6054000 0 0x50>;
+ 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -183,7 +183,7 @@
+ 
+ 		gpio5: gpio@e6055000 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055000 0 0x50>;
+ 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -198,7 +198,7 @@
+ 
+ 		gpio6: gpio@e6055400 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055400 0 0x50>;
+ 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -213,7 +213,7 @@
+ 
+ 		gpio7: gpio@e6055800 {
+ 			compatible = "renesas,gpio-r8a7743",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055800 0 0x50>;
+ 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0373-ARM-dts-r8a7790-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0373-ARM-dts-r8a7790-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..952924663933b9
--- /dev/null
+++ b/patches/0373-ARM-dts-r8a7790-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,83 @@
+From 7e83b4c2ad382fde41d8dbec7507c2f4360ec6a2 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:05 +0200
+Subject: [PATCH 0373/1795] ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7790 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 26742a192c82cc28723c80dbecc5976db0508461)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 92b7f3bd8b69..f247beb3863f 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -200,7 +200,7 @@
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6050000 0 0x50>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -214,7 +214,7 @@
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6051000 0 0x50>;
+ 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -228,7 +228,7 @@
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6052000 0 0x50>;
+ 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -242,7 +242,7 @@
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6053000 0 0x50>;
+ 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -256,7 +256,7 @@
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6054000 0 0x50>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -270,7 +270,7 @@
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055000 0 0x50>;
+ 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0374-ARM-dts-r8a7791-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0374-ARM-dts-r8a7791-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..946a19efe37dd6
--- /dev/null
+++ b/patches/0374-ARM-dts-r8a7791-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,101 @@
+From a0fed110964f7f05148f04c0af71efb0c54fc1de Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:06 +0200
+Subject: [PATCH 0374/1795] ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7791 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7140383d59fc590b9f52e4133e8454603c76bb78)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 97bed8253bc3..3c7b919efa48 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -124,7 +124,7 @@
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6050000 0 0x50>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -138,7 +138,7 @@
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6051000 0 0x50>;
+ 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -152,7 +152,7 @@
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6052000 0 0x50>;
+ 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -166,7 +166,7 @@
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6053000 0 0x50>;
+ 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -180,7 +180,7 @@
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6054000 0 0x50>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -194,7 +194,7 @@
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055000 0 0x50>;
+ 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -208,7 +208,7 @@
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055400 0 0x50>;
+ 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -222,7 +222,7 @@
+ 	};
+ 
+ 	gpio7: gpio@e6055800 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055800 0 0x50>;
+ 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0375-ARM-dts-r8a7792-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0375-ARM-dts-r8a7792-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..0c8a613f78e11a
--- /dev/null
+++ b/patches/0375-ARM-dts-r8a7792-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,137 @@
+From 9df8c510114f951a67872bed0e8c46b2d4da465f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:07 +0200
+Subject: [PATCH 0375/1795] ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7792 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7f4a16c4143a99ca4520c565abb07a4fffbae0ff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 549eafe8ff12..56570d1ce5f6 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -147,7 +147,7 @@
+ 
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6050000 0 0x50>;
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -162,7 +162,7 @@
+ 
+ 		gpio1: gpio@e6051000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6051000 0 0x50>;
+ 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -177,7 +177,7 @@
+ 
+ 		gpio2: gpio@e6052000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6052000 0 0x50>;
+ 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -192,7 +192,7 @@
+ 
+ 		gpio3: gpio@e6053000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6053000 0 0x50>;
+ 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -207,7 +207,7 @@
+ 
+ 		gpio4: gpio@e6054000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6054000 0 0x50>;
+ 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -222,7 +222,7 @@
+ 
+ 		gpio5: gpio@e6055000 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055000 0 0x50>;
+ 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -237,7 +237,7 @@
+ 
+ 		gpio6: gpio@e6055100 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055100 0 0x50>;
+ 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -252,7 +252,7 @@
+ 
+ 		gpio7: gpio@e6055200 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055200 0 0x50>;
+ 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -267,7 +267,7 @@
+ 
+ 		gpio8: gpio@e6055300 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055300 0 0x50>;
+ 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -282,7 +282,7 @@
+ 
+ 		gpio9: gpio@e6055400 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055400 0 0x50>;
+ 			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -297,7 +297,7 @@
+ 
+ 		gpio10: gpio@e6055500 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055500 0 0x50>;
+ 			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+@@ -312,7 +312,7 @@
+ 
+ 		gpio11: gpio@e6055600 {
+ 			compatible = "renesas,gpio-r8a7792",
+-				     "renesas,gpio-rcar";
++				     "renesas,rcar-gen2-gpio";
+ 			reg = <0 0xe6055600 0 0x50>;
+ 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0376-ARM-dts-r8a7793-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0376-ARM-dts-r8a7793-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..cfa668821ace63
--- /dev/null
+++ b/patches/0376-ARM-dts-r8a7793-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,101 @@
+From fab2272b7cde0df3c5a40d58b6441067d08609a9 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:08 +0200
+Subject: [PATCH 0376/1795] ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7793 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c37417dca041d76a66a78012f93e9a3c879706c4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index aa19b93494bf..76418c375a10 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -115,7 +115,7 @@
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6050000 0 0x50>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -129,7 +129,7 @@
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6051000 0 0x50>;
+ 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -143,7 +143,7 @@
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6052000 0 0x50>;
+ 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -157,7 +157,7 @@
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6053000 0 0x50>;
+ 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -171,7 +171,7 @@
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6054000 0 0x50>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -185,7 +185,7 @@
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055000 0 0x50>;
+ 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -199,7 +199,7 @@
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055400 0 0x50>;
+ 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -213,7 +213,7 @@
+ 	};
+ 
+ 	gpio7: gpio@e6055800 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055800 0 0x50>;
+ 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0377-ARM-dts-r8a7794-Use-R-Car-GPIO-Gen2-fallback-compat-.patch b/patches/0377-ARM-dts-r8a7794-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..2cde4e441ed196
--- /dev/null
+++ b/patches/0377-ARM-dts-r8a7794-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
@@ -0,0 +1,92 @@
+From 69f4f9a7fb4c8167e026ef0f20ae2794a5fd9a0d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 13 Oct 2017 14:33:09 +0200
+Subject: [PATCH 0377/1795] ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback
+ compat string
+
+Use newly added R-Car GPIO Gen2 fallback compat string
+in place of now deprecated non-generation specific
+R-Car GPIO fallback compat string in the DT of the r8a7794 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7ee06c8a0b3a1fad3d9660da00e895aaf784fdee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 19cff0dd90cf..7720a6ca8702 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -82,7 +82,7 @@
+ 	};
+ 
+ 	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6050000 0 0x50>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -96,7 +96,7 @@
+ 	};
+ 
+ 	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6051000 0 0x50>;
+ 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -110,7 +110,7 @@
+ 	};
+ 
+ 	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6052000 0 0x50>;
+ 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -124,7 +124,7 @@
+ 	};
+ 
+ 	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6053000 0 0x50>;
+ 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -138,7 +138,7 @@
+ 	};
+ 
+ 	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6054000 0 0x50>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -152,7 +152,7 @@
+ 	};
+ 
+ 	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055000 0 0x50>;
+ 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+@@ -166,7 +166,7 @@
+ 	};
+ 
+ 	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
++		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+ 		reg = <0 0xe6055400 0 0x50>;
+ 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 		#gpio-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0378-ARM-dts-r8a73a4-Add-clock-for-CA15-CPU0-core.patch b/patches/0378-ARM-dts-r8a73a4-Add-clock-for-CA15-CPU0-core.patch
new file mode 100644
index 00000000000000..6e00d0a2053c38
--- /dev/null
+++ b/patches/0378-ARM-dts-r8a73a4-Add-clock-for-CA15-CPU0-core.patch
@@ -0,0 +1,33 @@
+From c3bcbf251d600d2aa5c561a8ba939b454baa5d3e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:06 +0200
+Subject: [PATCH 0378/1795] ARM: dts: r8a73a4: Add clock for CA15 CPU0 core
+
+Improve hardware description by adding a clocks property to the device
+node corresponding to the primary CA15 CPU core, which is for now the
+only one described.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a7869a5bc82682ac31452e178b4b3e9f8b48e7df)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a73a4.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
+index 310222634570..dd4d09712a2a 100644
+--- a/arch/arm/boot/dts/r8a73a4.dtsi
++++ b/arch/arm/boot/dts/r8a73a4.dtsi
+@@ -27,6 +27,7 @@
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a15";
+ 			reg = <0>;
++			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+ 			clock-frequency = <1500000000>;
+ 			power-domains = <&pd_a2sl>;
+ 			next-level-cache = <&L2_CA15>;
+-- 
+2.19.0
+
diff --git a/patches/0379-ARM-dts-r8a7743-Add-missing-clock-for-secondary-CA15.patch b/patches/0379-ARM-dts-r8a7743-Add-missing-clock-for-secondary-CA15.patch
new file mode 100644
index 00000000000000..52a3ae508ed062
--- /dev/null
+++ b/patches/0379-ARM-dts-r8a7743-Add-missing-clock-for-secondary-CA15.patch
@@ -0,0 +1,35 @@
+From 5cd5a2d51ab0b63cf42907e2240e537575793874 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:07 +0200
+Subject: [PATCH 0379/1795] ARM: dts: r8a7743: Add missing clock for secondary
+ CA15 CPU core
+
+Currently only the primary CPU in the CA15 cluster has a clocks
+property, while the secondary CPU core is driven by the same clock.
+Add the missing clocks property to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a60ddf507dda0ede43b72d348283d8725a5a83c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index f29f15d4d659..4db4f61be25a 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -63,6 +63,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <1>;
+ 			clock-frequency = <1500000000>;
++			clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+ 			power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+ 			next-level-cache = <&L2_CA15>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0380-ARM-dts-r8a7778-Add-clock-for-CA9-CPU-core.patch b/patches/0380-ARM-dts-r8a7778-Add-clock-for-CA9-CPU-core.patch
new file mode 100644
index 00000000000000..f6f502b02f62d1
--- /dev/null
+++ b/patches/0380-ARM-dts-r8a7778-Add-clock-for-CA9-CPU-core.patch
@@ -0,0 +1,32 @@
+From 959a804bf0129e6aa6f36446563555f93ad82040 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:08 +0200
+Subject: [PATCH 0380/1795] ARM: dts: r8a7778: Add clock for CA9 CPU core
+
+Improve hardware description by adding a clock property to the device
+node corresponding to the CA9 CPU core.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d3e865a35a4f8cee0d0b86d7cd6d05908f01a874)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7778.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
+index a31817b2dda7..a39472aab867 100644
+--- a/arch/arm/boot/dts/r8a7778.dtsi
++++ b/arch/arm/boot/dts/r8a7778.dtsi
+@@ -33,6 +33,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <0>;
+ 			clock-frequency = <800000000>;
++			clocks = <&z_clk>;
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0381-ARM-dts-r8a7779-Add-clocks-for-CA9-CPU-cores.patch b/patches/0381-ARM-dts-r8a7779-Add-clocks-for-CA9-CPU-cores.patch
new file mode 100644
index 00000000000000..fa15ef35cc8880
--- /dev/null
+++ b/patches/0381-ARM-dts-r8a7779-Add-clocks-for-CA9-CPU-cores.patch
@@ -0,0 +1,55 @@
+From 3833771167d6331d84b32c43c0cc78a80514d7c5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:09 +0200
+Subject: [PATCH 0381/1795] ARM: dts: r8a7779: Add clocks for CA9 CPU cores
+
+Improve hardware description by adding clocks properties to the device
+nodes corresponding to the CA9 CPU cores.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fa9f95a3d1bf827e7b83310e5e5c83f36382e25f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7779.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
+index ccef2cfab6e0..e8eb94748b27 100644
+--- a/arch/arm/boot/dts/r8a7779.dtsi
++++ b/arch/arm/boot/dts/r8a7779.dtsi
+@@ -29,12 +29,14 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <0>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg_clocks R8A7779_CLK_Z>;
+ 		};
+ 		cpu@1 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a9";
+ 			reg = <1>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg_clocks R8A7779_CLK_Z>;
+ 			power-domains = <&sysc R8A7779_PD_ARM1>;
+ 		};
+ 		cpu@2 {
+@@ -42,6 +44,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <2>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg_clocks R8A7779_CLK_Z>;
+ 			power-domains = <&sysc R8A7779_PD_ARM2>;
+ 		};
+ 		cpu@3 {
+@@ -49,6 +52,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <3>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg_clocks R8A7779_CLK_Z>;
+ 			power-domains = <&sysc R8A7779_PD_ARM3>;
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0382-ARM-dts-r8a7790-Add-missing-clocks-for-secondary-CA1.patch b/patches/0382-ARM-dts-r8a7790-Add-missing-clocks-for-secondary-CA1.patch
new file mode 100644
index 00000000000000..060afd386e53bc
--- /dev/null
+++ b/patches/0382-ARM-dts-r8a7790-Add-missing-clocks-for-secondary-CA1.patch
@@ -0,0 +1,51 @@
+From 72ee2e263237758876cb92c39c7d5ff162f85176 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:10 +0200
+Subject: [PATCH 0382/1795] ARM: dts: r8a7790: Add missing clocks for secondary
+ CA15 CPU cores
+
+Currently only the primary CPU in the CA15 cluster has a clocks
+property, while the secondary CPU cores are driven by the same clock.
+Add the missing clocks properties to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aa4c2fdf495f000fa9ae57c073c0c4575c21983e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index f247beb3863f..e85eb42f97e8 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -72,6 +72,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <1>;
+ 			clock-frequency = <1300000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+ 			next-level-cache = <&L2_CA15>;
+ 			capacity-dmips-mhz = <1024>;
+@@ -82,6 +83,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <2>;
+ 			clock-frequency = <1300000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+ 			next-level-cache = <&L2_CA15>;
+ 			capacity-dmips-mhz = <1024>;
+@@ -92,6 +94,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <3>;
+ 			clock-frequency = <1300000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+ 			power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+ 			next-level-cache = <&L2_CA15>;
+ 			capacity-dmips-mhz = <1024>;
+-- 
+2.19.0
+
diff --git a/patches/0383-ARM-dts-r8a7790-Add-clocks-for-CA7-CPU-cores.patch b/patches/0383-ARM-dts-r8a7790-Add-clocks-for-CA7-CPU-cores.patch
new file mode 100644
index 00000000000000..326fe21adc3dcb
--- /dev/null
+++ b/patches/0383-ARM-dts-r8a7790-Add-clocks-for-CA7-CPU-cores.patch
@@ -0,0 +1,58 @@
+From 7ef8ec38176b6ac2b13053b9fdc62339baca234b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:11 +0200
+Subject: [PATCH 0383/1795] ARM: dts: r8a7790: Add clocks for CA7 CPU cores
+
+Currently only the CPU cores in the CA15 cluster have clocks properties.
+Add the missing clocks properties for the CPU cores in the CA7 cluster
+to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aea0089ae8058a9bf4c9766f3208809fc28c99f0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index e85eb42f97e8..2f017fee4009 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -105,6 +105,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <0x100>;
+ 			clock-frequency = <780000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+ 			next-level-cache = <&L2_CA7>;
+ 			capacity-dmips-mhz = <539>;
+@@ -115,6 +116,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <0x101>;
+ 			clock-frequency = <780000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+ 			next-level-cache = <&L2_CA7>;
+ 			capacity-dmips-mhz = <539>;
+@@ -125,6 +127,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <0x102>;
+ 			clock-frequency = <780000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+ 			next-level-cache = <&L2_CA7>;
+ 			capacity-dmips-mhz = <539>;
+@@ -135,6 +138,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <0x103>;
+ 			clock-frequency = <780000000>;
++			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+ 			power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+ 			next-level-cache = <&L2_CA7>;
+ 			capacity-dmips-mhz = <539>;
+-- 
+2.19.0
+
diff --git a/patches/0384-ARM-dts-r8a7791-Add-missing-clock-for-secondary-CA15.patch b/patches/0384-ARM-dts-r8a7791-Add-missing-clock-for-secondary-CA15.patch
new file mode 100644
index 00000000000000..60ec42ebb2dad2
--- /dev/null
+++ b/patches/0384-ARM-dts-r8a7791-Add-missing-clock-for-secondary-CA15.patch
@@ -0,0 +1,34 @@
+From e3bcee14abab1ed64763806f05be4c5d4a38d396 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:12 +0200
+Subject: [PATCH 0384/1795] ARM: dts: r8a7791: Add missing clock for secondary
+ CA15 CPU core
+
+Currently only the primary CPU in the CA15 cluster has a clocks
+property, while the secondary CPU core is driven by the same clock.
+Add the missing clocks property to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 60b672fe7e28358c1cffdab4724b203f6cf2901b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 3c7b919efa48..67831d0405f3 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -70,6 +70,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <1>;
+ 			clock-frequency = <1500000000>;
++			clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
+ 			power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+ 			next-level-cache = <&L2_CA15>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0385-ARM-dts-r8a7792-Add-missing-clock-for-secondary-CA15.patch b/patches/0385-ARM-dts-r8a7792-Add-missing-clock-for-secondary-CA15.patch
new file mode 100644
index 00000000000000..3b69b48db5c777
--- /dev/null
+++ b/patches/0385-ARM-dts-r8a7792-Add-missing-clock-for-secondary-CA15.patch
@@ -0,0 +1,34 @@
+From 0724ed943b0fb5e49864b39a3435e6ea6bc7a7cf Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:13 +0200
+Subject: [PATCH 0385/1795] ARM: dts: r8a7792: Add missing clock for secondary
+ CA15 CPU core
+
+Currently only the primary CPU in the CA15 cluster has a clocks
+property, while the secondary CPU core is driven by the same clock.
+Add the missing clocks property to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8684a24caa3d59d9ba03f1e6f9653b49ac78ec04)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 56570d1ce5f6..131f65b0426e 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -56,6 +56,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <1>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
+ 			power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+ 			next-level-cache = <&L2_CA15>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0386-ARM-dts-r8a7793-Add-missing-clock-for-secondary-CA15.patch b/patches/0386-ARM-dts-r8a7793-Add-missing-clock-for-secondary-CA15.patch
new file mode 100644
index 00000000000000..1964eefa49a090
--- /dev/null
+++ b/patches/0386-ARM-dts-r8a7793-Add-missing-clock-for-secondary-CA15.patch
@@ -0,0 +1,34 @@
+From 34eca55947a67ffae3e8e0a5a58d819dc1e8ad8b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:14 +0200
+Subject: [PATCH 0386/1795] ARM: dts: r8a7793: Add missing clock for secondary
+ CA15 CPU core
+
+Currently only the primary CPU in the CA15 cluster has a clocks
+property, while the secondary CPU core is driven by the same clock.
+Add the missing clocks property to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f359fd3bba71176a122939fe3db9c7f20000d3f0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 76418c375a10..58eae569b4e0 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -62,6 +62,7 @@
+ 			compatible = "arm,cortex-a15";
+ 			reg = <1>;
+ 			clock-frequency = <1500000000>;
++			clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
+ 			power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0387-ARM-dts-r8a7794-Add-missing-clock-for-secondary-CA7-.patch b/patches/0387-ARM-dts-r8a7794-Add-missing-clock-for-secondary-CA7-.patch
new file mode 100644
index 00000000000000..d01cf22c5ccb15
--- /dev/null
+++ b/patches/0387-ARM-dts-r8a7794-Add-missing-clock-for-secondary-CA7-.patch
@@ -0,0 +1,34 @@
+From 6a57903ef929d211486385240e3dbd8169541d37 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:15 +0200
+Subject: [PATCH 0387/1795] ARM: dts: r8a7794: Add missing clock for secondary
+ CA7 CPU core
+
+Currently only the primary CPU in the CA7 cluster has a clocks property,
+while the secondary CPU core is driven by the same clock.
+Add the missing clocks property to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5614e69269232da1f378e5be92714b96cdb090ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 7720a6ca8702..905e50c9b524 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -53,6 +53,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <1>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+ 			power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+ 			next-level-cache = <&L2_CA7>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0388-ARM-dts-sh73a0-Add-clocks-for-CA9-CPU-cores.patch b/patches/0388-ARM-dts-sh73a0-Add-clocks-for-CA9-CPU-cores.patch
new file mode 100644
index 00000000000000..ba15a4a32aa2d5
--- /dev/null
+++ b/patches/0388-ARM-dts-sh73a0-Add-clocks-for-CA9-CPU-cores.patch
@@ -0,0 +1,40 @@
+From b8c2322b1e1bc578b6d4ef3926c23ced487ddaf5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:16 +0200
+Subject: [PATCH 0388/1795] ARM: dts: sh73a0: Add clocks for CA9 CPU cores
+
+Improve hardware description by adding clocks properties to the device
+nodes corresponding to the CA9 CPU cores.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e5042d0b97be6a831f9f204f3574d73b3f947fa5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/sh73a0.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
+index 5fc24d4c2d5d..52e63075fdb4 100644
+--- a/arch/arm/boot/dts/sh73a0.dtsi
++++ b/arch/arm/boot/dts/sh73a0.dtsi
+@@ -27,6 +27,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <0>;
+ 			clock-frequency = <1196000000>;
++			clocks = <&cpg_clocks SH73A0_CLK_Z>;
+ 			power-domains = <&pd_a2sl>;
+ 			next-level-cache = <&L2>;
+ 		};
+@@ -35,6 +36,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <1>;
+ 			clock-frequency = <1196000000>;
++			clocks = <&cpg_clocks SH73A0_CLK_Z>;
+ 			power-domains = <&pd_a2sl>;
+ 			next-level-cache = <&L2>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0389-ARM-dts-r7s72100-Add-clock-for-CA9-CPU-core.patch b/patches/0389-ARM-dts-r7s72100-Add-clock-for-CA9-CPU-core.patch
new file mode 100644
index 00000000000000..5a590ba14456c0
--- /dev/null
+++ b/patches/0389-ARM-dts-r7s72100-Add-clock-for-CA9-CPU-core.patch
@@ -0,0 +1,32 @@
+From 76f08dc4d7b846f57e585be8591a7b8aebb3c4a7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 12 Oct 2017 11:35:05 +0200
+Subject: [PATCH 0389/1795] ARM: dts: r7s72100: Add clock for CA9 CPU core
+
+Improve hardware description by adding a clock property to the device
+node corresponding to the CA9 CPU core.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f20d89ac0fefad2465e6ce6d64e9ff82e33889dd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index 4ed12a4d9d51..ab9645a42eca 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -203,6 +203,7 @@
+ 			compatible = "arm,cortex-a9";
+ 			reg = <0>;
+ 			clock-frequency = <400000000>;
++			clocks = <&cpg_clocks R7S72100_CLK_I>;
+ 			next-level-cache = <&L2>;
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0390-ARM-dts-r8a7743-Add-xhci-support-to-SoC-dtsi.patch b/patches/0390-ARM-dts-r8a7743-Add-xhci-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..c0ae6416b9e0d0
--- /dev/null
+++ b/patches/0390-ARM-dts-r8a7743-Add-xhci-support-to-SoC-dtsi.patch
@@ -0,0 +1,51 @@
+From 60fe245dd40e51d86fece5c0f2d307e64f1044f7 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 16 Oct 2017 11:12:49 +0100
+Subject: [PATCH 0390/1795] ARM: dts: r8a7743: Add xhci support to SoC dtsi
+
+Add node for xhci. Boards DT files will enable it if needed.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b6d3b649441936621c87b79bff8dd436e2397e3c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 4db4f61be25a..7bbba4a36f31 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -932,6 +932,26 @@
+ 			status = "disabled";
+ 		};
+ 
++		/*
++		 * pci1 and xhci share the same phy, therefore only one of them
++		 * can be active at any one time. If both of them are enabled,
++		 * a race condition will determine who'll control the phy.
++		 * A firmware file is needed by the xhci driver in order for
++		 * USB 3.0 to work properly.
++		 */
++		xhci: usb@ee000000 {
++			compatible = "renesas,xhci-r8a7743",
++				     "renesas,rcar-gen2-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			phys = <&usb2 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7743";
+ 			reg = <0 0xee100000 0 0x328>;
+-- 
+2.19.0
+
diff --git a/patches/0391-ARM-shmobile-pm-rmobile-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch b/patches/0391-ARM-shmobile-pm-rmobile-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
new file mode 100644
index 00000000000000..47382f8ddaceb4
--- /dev/null
+++ b/patches/0391-ARM-shmobile-pm-rmobile-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
@@ -0,0 +1,47 @@
+From 65f83a72556e167909fe7e962b369d93b466ef61 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 7 Nov 2017 13:48:12 +0100
+Subject: [PATCH 0391/1795] ARM: shmobile: pm-rmobile: Use
+ GENPD_FLAG_ACTIVE_WAKEUP
+
+Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to
+remove the driver's own "always true" callback.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit eb0ddf9dd22be098301ab8a09e9be5a13ae8c804)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/pm-rmobile.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
+index 3a4ed4c33a68..e348bcfe389d 100644
+--- a/arch/arm/mach-shmobile/pm-rmobile.c
++++ b/arch/arm/mach-shmobile/pm-rmobile.c
+@@ -120,18 +120,12 @@ static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
+ 	return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
+ }
+ 
+-static bool rmobile_pd_active_wakeup(struct device *dev)
+-{
+-	return true;
+-}
+-
+ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
+ {
+ 	struct generic_pm_domain *genpd = &rmobile_pd->genpd;
+ 	struct dev_power_governor *gov = rmobile_pd->gov;
+ 
+-	genpd->flags |= GENPD_FLAG_PM_CLK;
+-	genpd->dev_ops.active_wakeup	= rmobile_pd_active_wakeup;
++	genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ 	genpd->power_off		= rmobile_pd_power_down;
+ 	genpd->power_on			= rmobile_pd_power_up;
+ 	genpd->attach_dev		= cpg_mstp_attach_dev;
+-- 
+2.19.0
+
diff --git a/patches/0392-ARM-dts-r8a779x-Add-reset-cells-in-cpg-mssr.patch b/patches/0392-ARM-dts-r8a779x-Add-reset-cells-in-cpg-mssr.patch
new file mode 100644
index 00000000000000..0f13a0ee2eed9d
--- /dev/null
+++ b/patches/0392-ARM-dts-r8a779x-Add-reset-cells-in-cpg-mssr.patch
@@ -0,0 +1,88 @@
+From ad495deef5a3262d7e1f50edd2e74787fdeb326f Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 16 Nov 2017 14:35:57 +0100
+Subject: [PATCH 0392/1795] ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssr
+
+With the latest dtc, we get many warnings about the missing
+'#reset-cells' property in these controllers, e.g.:
+
+arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0])
+arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0])
+arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0])
+arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0])
+arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0])
+arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0])
+
+This adds it for the three r8a779x chips that were lacking it. The
+binding mandates this as <1>, so this is the value I use.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+[geert: Add fix for r8a7793.dtsi]
+Fixes: 34fbd2b12761d111 ("ARM: dts: r8a7790: Add reset control properties")
+Fixes: 6e11a322f1d7505d ("ARM: dts: r8a7792: Add reset control properties")
+Fixes: 84fb19e1d201ba86 ("ARM: dts: r8a7793: Add reset control properties")
+Fixes: 615beb759ca494a4 ("ARM: dts: r8a7794: Add reset control properties")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 098f53050154498876ef3febde706ff5c8b25cf4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 1 +
+ arch/arm/boot/dts/r8a7792.dtsi | 1 +
+ arch/arm/boot/dts/r8a7793.dtsi | 1 +
+ arch/arm/boot/dts/r8a7794.dtsi | 1 +
+ 4 files changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 2f017fee4009..62baabd757b6 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1201,6 +1201,7 @@
+ 		clock-names = "extal", "usb_extal";
+ 		#clock-cells = <2>;
+ 		#power-domain-cells = <0>;
++		#reset-cells = <1>;
+ 	};
+ 
+ 	prr: chipid@ff000044 {
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 131f65b0426e..3d080e07374c 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -829,6 +829,7 @@
+ 			clock-names = "extal";
+ 			#clock-cells = <2>;
+ 			#power-domain-cells = <0>;
++			#reset-cells = <1>;
+ 		};
+ 	};
+ 
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 58eae569b4e0..0cd1035de1a4 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -1088,6 +1088,7 @@
+ 		clock-names = "extal", "usb_extal";
+ 		#clock-cells = <2>;
+ 		#power-domain-cells = <0>;
++		#reset-cells = <1>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 905e50c9b524..5643976c1356 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -1099,6 +1099,7 @@
+ 		clock-names = "extal", "usb_extal";
+ 		#clock-cells = <2>;
+ 		#power-domain-cells = <0>;
++		#reset-cells = <1>;
+ 	};
+ 
+ 	rst: reset-controller@e6160000 {
+-- 
+2.19.0
+
diff --git a/patches/0393-i2c-gpio-Convert-to-use-descriptors.patch b/patches/0393-i2c-gpio-Convert-to-use-descriptors.patch
new file mode 100644
index 00000000000000..f14ed6db1ccfeb
--- /dev/null
+++ b/patches/0393-i2c-gpio-Convert-to-use-descriptors.patch
@@ -0,0 +1,1548 @@
+From cb5c2d12d354f389b27d466c2e3df1b61385651d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 01:30:46 +0200
+Subject: [PATCH 0393/1795] i2c: gpio: Convert to use descriptors
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This converts the GPIO-based I2C-driver to using GPIO
+descriptors instead of the old global numberspace-based
+GPIO interface. We:
+
+- Convert the driver to unconditionally grab two GPIOs
+  from the device by index 0 (SDA) and 1 (SCL) which
+  will work fine with device tree and descriptor tables.
+  The existing device trees will continue to work just
+  like before, but without any roundtrip through the
+  global numberspace.
+
+- Brutally convert all boardfiles still passing global
+  GPIOs by registering descriptor tables associated with
+  the devices instead so this driver does not need to keep
+  supporting passing any GPIO numbers as platform data.
+
+There is no stepwise approach as elegant as this, I
+strongly prefer this big hammer over any antsteps for this
+conversion. This way the old GPIO numbers go away and
+NEVER COME BACK.
+
+Special conversion for the different boards utilizing
+I2C-GPIO:
+
+- EP93xx (arch/arm/mach-ep93xx): pretty straight forward as
+  all boards were using the same two GPIO lines, just define
+  these two in a lookup table for "i2c-gpio" and register
+  these along with the device. None of them define any
+  other platform data so just pass NULL as platform data.
+  This platform selects GPIOLIB so all should be smooth.
+  The pins appear on a gpiochip for bank "G" as pins 1 (SDA)
+  and 0 (SCL).
+
+- IXP4 (arch/arm/mach-ixp4): descriptor tables have to
+  be registered for each board separately. They all use
+  "IXP4XX_GPIO_CHIP" so it is pretty straight forward.
+  Most board define no other platform data than SCL/SDA
+  so they can drop the #include of <linux/i2c-gpio.h> and
+  assign NULL to platform data.
+
+  The "goramo_mlr" (Goramo Multilink Router) board is a bit
+  worrisome: it implements its own I2C bit-banging in the
+  board file, and optionally registers an I2C serial port,
+  but claims the same GPIO lines for itself in the board file.
+  This is not going to work: there will be competition for the
+  GPIO lines, so delete the optional extra I2C bus instead, no
+  I2C devices are registered on it anyway, there are just hints
+  that it may contain an EEPROM that may be accessed from
+  userspace. This needs to be fixed up properly by the serial
+  clock using I2C emulation so drop a note in the code.
+
+- KS8695 board acs5k (arch/arm/mach-ks8695/board-acs5.c)
+  has some platform data in addition to the pins so it needs to
+  be kept around sans GPIO lines. Its GPIO chip is named
+  "KS8695" and the arch selects GPIOLIB.
+
+- PXA boards (arch/arm/mach-pxa/*) use some of the platform
+  data so it needs to be preserved here. The viper board even
+  registers two GPIO I2Cs. The gpiochip is named "gpio-pxa" and
+  the arch selects GPIOLIB.
+
+- SA1100 Simpad (arch/arm/mach-sa1100/simpad.c) defines a GPIO
+  I2C bus, and the arch selects GPIOLIB.
+
+- Blackfin boards (arch/blackfin/bf533 etc) for these I assume
+  their I2C GPIOs refer to the local gpiochip defined in
+  arch/blackfin/kernel/bfin_gpio.c names "BFIN-GPIO".
+  The arch selects GPIOLIB. The boards get spiked with
+  IF_ENABLED(I2C_GPIO) but that is a side effect of it
+  being like that already (I would just have Kconfig select
+  I2C_GPIO and get rid of them all.) I also delete any
+  platform data set to 0 as it will get that value anyway
+  from static declartions of platform data.
+
+- The MIPS selects GPIOLIB and the Alchemy machine is using
+  two local GPIO chips, one of them has a GPIO I2C. We need
+  to adjust the local offset from the global number space here.
+  The ATH79 has a proper GPIO driver in drivers/gpio/gpio-ath79.c
+  and AFAICT the chip is named "ath79-gpio" and the PB44
+  PCF857x expander spawns from this on GPIO 1 and 0. The latter
+  board only use the platform data to specify pins so it can be
+  cut altogether after this.
+
+- The MFD Silicon Motion SM501 is a special case. It dynamically
+  spawns an I2C bus off the MFD using sm501_create_subdev().
+  We use an approach to dynamically create a machine descriptor
+  table and attach this to the "SM501-LOW" or "SM501-HIGH"
+  gpiochip. We use chip-local offsets to grab the right lines.
+  We can get rid of two local static inline helpers as part
+  of this refactoring.
+
+Cc: Steven Miao <realmz6@gmail.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Magnus Damm <magnus.damm@gmail.com>
+Cc: Ben Dooks <ben.dooks@codethink.co.uk>
+Cc: Heiko Schocher <hs@denx.de>
+Acked-by: Wu, Aaron <Aaron.Wu@analog.com>
+Acked-by: Olof Johansson <olof@lixom.net>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Acked-by: Ralf Baechle <ralf@linux-mips.org>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit b2e63555592f81331c8da3afaa607d8cf83e8138)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-ep93xx/core.c                  |  39 +++---
+ arch/arm/mach-ep93xx/edb93xx.c               |  15 +--
+ arch/arm/mach-ep93xx/include/mach/platform.h |   4 +-
+ arch/arm/mach-ep93xx/simone.c                |  12 +-
+ arch/arm/mach-ep93xx/snappercl15.c           |  12 +-
+ arch/arm/mach-ep93xx/vision_ep9307.c         |   7 +-
+ arch/arm/mach-ixp4xx/avila-setup.c           |  17 ++-
+ arch/arm/mach-ixp4xx/dsmg600-setup.c         |  16 ++-
+ arch/arm/mach-ixp4xx/fsg-setup.c             |  16 ++-
+ arch/arm/mach-ixp4xx/goramo_mlr.c            |  24 +---
+ arch/arm/mach-ixp4xx/ixdp425-setup.c         |  16 ++-
+ arch/arm/mach-ixp4xx/nas100d-setup.c         |  16 ++-
+ arch/arm/mach-ixp4xx/nslu2-setup.c           |  16 ++-
+ arch/arm/mach-ks8695/board-acs5k.c           |  13 +-
+ arch/arm/mach-pxa/palmz72.c                  |  12 +-
+ arch/arm/mach-pxa/viper.c                    |  27 +++-
+ arch/arm/mach-sa1100/simpad.c                |  12 +-
+ arch/blackfin/mach-bf533/boards/blackstamp.c |  19 ++-
+ arch/blackfin/mach-bf533/boards/ezkit.c      |  18 ++-
+ arch/blackfin/mach-bf533/boards/stamp.c      |  18 ++-
+ arch/blackfin/mach-bf561/boards/ezkit.c      |  18 ++-
+ arch/mips/alchemy/board-gpr.c                |  19 ++-
+ arch/mips/ath79/mach-pb44.c                  |  16 ++-
+ drivers/i2c/busses/i2c-gpio.c                | 134 +++++++++----------
+ drivers/mfd/sm501.c                          |  49 ++++---
+ include/linux/i2c-gpio.h                     |   4 -
+ 26 files changed, 327 insertions(+), 242 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index f53c61813998..7e99fe829ad1 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -31,7 +31,7 @@
+ #include <linux/amba/serial.h>
+ #include <linux/mtd/physmap.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/spi/spi.h>
+ #include <linux/export.h>
+ #include <linux/irqchip/arm-vic.h>
+@@ -320,42 +320,45 @@ void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
+ /*************************************************************************
+  * EP93xx i2c peripheral handling
+  *************************************************************************/
+-static struct i2c_gpio_platform_data ep93xx_i2c_data;
++
++/* All EP93xx devices use the same two GPIO pins for I2C bit-banging */
++static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		/* Use local offsets on gpiochip/port "G" */
++		GPIO_LOOKUP_IDX("G", 1, NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("G", 0, NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
+ 
+ static struct platform_device ep93xx_i2c_device = {
+ 	.name		= "i2c-gpio",
+ 	.id		= 0,
+ 	.dev		= {
+-		.platform_data	= &ep93xx_i2c_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+ /**
+  * ep93xx_register_i2c - Register the i2c platform device.
+- * @data:	platform specific i2c-gpio configuration (__initdata)
+  * @devices:	platform specific i2c bus device information (__initdata)
+  * @num:	the number of devices on the i2c bus
+  */
+-void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
+-				struct i2c_board_info *devices, int num)
++void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
+ {
+ 	/*
+-	 * Set the EEPROM interface pin drive type control.
+-	 * Defines the driver type for the EECLK and EEDAT pins as either
+-	 * open drain, which will require an external pull-up, or a normal
+-	 * CMOS driver.
++	 * FIXME: this just sets the two pins as non-opendrain, as no
++	 * platforms tries to do that anyway. Flag the applicable lines
++	 * as open drain in the GPIO_LOOKUP above and the driver or
++	 * gpiolib will handle open drain/open drain emulation as need
++	 * be. Right now i2c-gpio emulates open drain which is not
++	 * optimal.
+ 	 */
+-	if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
+-		pr_warning("sda != EEDAT, open drain has no effect\n");
+-	if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
+-		pr_warning("scl != EECLK, open drain has no effect\n");
+-
+-	__raw_writel((data->sda_is_open_drain << 1) |
+-		     (data->scl_is_open_drain << 0),
++	__raw_writel((0 << 1) | (0 << 0),
+ 		     EP93XX_GPIO_EEDRIVE);
+ 
+-	ep93xx_i2c_data = *data;
+ 	i2c_register_board_info(0, devices, num);
++	gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table);
+ 	platform_device_register(&ep93xx_i2c_device);
+ }
+ 
+diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
+index 7a7f280b07d7..8e89ec8b6f0f 100644
+--- a/arch/arm/mach-ep93xx/edb93xx.c
++++ b/arch/arm/mach-ep93xx/edb93xx.c
+@@ -28,7 +28,6 @@
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
+ #include <linux/spi/spi.h>
+ 
+ #include <sound/cs4271.h>
+@@ -61,14 +60,6 @@ static struct ep93xx_eth_data __initdata edb93xx_eth_data = {
+ /*************************************************************************
+  * EDB93xx i2c peripheral handling
+  *************************************************************************/
+-static struct i2c_gpio_platform_data __initdata edb93xx_i2c_gpio_data = {
+-	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
+-	.sda_is_open_drain	= 0,
+-	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
+-	.scl_is_open_drain	= 0,
+-	.udelay			= 0,	/* default to 100 kHz */
+-	.timeout		= 0,	/* default to 100 ms */
+-};
+ 
+ static struct i2c_board_info __initdata edb93xxa_i2c_board_info[] = {
+ 	{
+@@ -86,13 +77,11 @@ static void __init edb93xx_register_i2c(void)
+ {
+ 	if (machine_is_edb9302a() || machine_is_edb9307a() ||
+ 	    machine_is_edb9315a()) {
+-		ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
+-				    edb93xxa_i2c_board_info,
++		ep93xx_register_i2c(edb93xxa_i2c_board_info,
+ 				    ARRAY_SIZE(edb93xxa_i2c_board_info));
+ 	} else if (machine_is_edb9302() || machine_is_edb9307()
+ 		|| machine_is_edb9312() || machine_is_edb9315()) {
+-		ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
+-				    edb93xx_i2c_board_info,
++		ep93xx_register_i2c(edb93xx_i2c_board_info,
+ 				    ARRAY_SIZE(edb93xx_i2c_board_info));
+ 	}
+ }
+diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
+index 3bbe1591013e..6c41c794bed5 100644
+--- a/arch/arm/mach-ep93xx/include/mach/platform.h
++++ b/arch/arm/mach-ep93xx/include/mach/platform.h
+@@ -8,7 +8,6 @@
+ #include <linux/reboot.h>
+ 
+ struct device;
+-struct i2c_gpio_platform_data;
+ struct i2c_board_info;
+ struct spi_board_info;
+ struct platform_device;
+@@ -37,8 +36,7 @@ void ep93xx_register_flash(unsigned int width,
+ 			   resource_size_t start, resource_size_t size);
+ 
+ void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
+-void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
+-			 struct i2c_board_info *devices, int num);
++void ep93xx_register_i2c(struct i2c_board_info *devices, int num);
+ void ep93xx_register_spi(struct ep93xx_spi_info *info,
+ 			 struct spi_board_info *devices, int num);
+ void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
+diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
+index c7a40f245892..e61f3dee24c2 100644
+--- a/arch/arm/mach-ep93xx/simone.c
++++ b/arch/arm/mach-ep93xx/simone.c
+@@ -19,7 +19,6 @@
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
+ #include <linux/mmc/host.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/mmc_spi.h>
+@@ -129,15 +128,6 @@ static struct ep93xx_spi_info simone_spi_info __initdata = {
+ 	.use_dma = 1,
+ };
+ 
+-static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = {
+-	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
+-	.sda_is_open_drain	= 0,
+-	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
+-	.scl_is_open_drain	= 0,
+-	.udelay			= 0,
+-	.timeout		= 0,
+-};
+-
+ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
+ 	{
+ 		I2C_BOARD_INFO("ds1337", 0x68),
+@@ -161,7 +151,7 @@ static void __init simone_init_machine(void)
+ 	ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
+ 	ep93xx_register_eth(&simone_eth_data, 1);
+ 	ep93xx_register_fb(&simone_fb_info);
+-	ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
++	ep93xx_register_i2c(simone_i2c_board_info,
+ 			    ARRAY_SIZE(simone_i2c_board_info));
+ 	ep93xx_register_spi(&simone_spi_info, simone_spi_devices,
+ 			    ARRAY_SIZE(simone_spi_devices));
+diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
+index 8b29398f4dc7..45940c1d7787 100644
+--- a/arch/arm/mach-ep93xx/snappercl15.c
++++ b/arch/arm/mach-ep93xx/snappercl15.c
+@@ -21,7 +21,6 @@
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
+ #include <linux/fb.h>
+ 
+ #include <linux/mtd/partitions.h>
+@@ -127,15 +126,6 @@ static struct ep93xx_eth_data __initdata snappercl15_eth_data = {
+ 	.phy_id			= 1,
+ };
+ 
+-static struct i2c_gpio_platform_data __initdata snappercl15_i2c_gpio_data = {
+-	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
+-	.sda_is_open_drain	= 0,
+-	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
+-	.scl_is_open_drain	= 0,
+-	.udelay			= 0,
+-	.timeout		= 0,
+-};
+-
+ static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
+ 	{
+ 		/* Audio codec */
+@@ -161,7 +151,7 @@ static void __init snappercl15_init_machine(void)
+ {
+ 	ep93xx_init_devices();
+ 	ep93xx_register_eth(&snappercl15_eth_data, 1);
+-	ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
++	ep93xx_register_i2c(snappercl15_i2c_data,
+ 			    ARRAY_SIZE(snappercl15_i2c_data));
+ 	ep93xx_register_fb(&snappercl15_fb_info);
+ 	snappercl15_register_audio();
+diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
+index 1daf9441058c..5a0b6187990a 100644
+--- a/arch/arm/mach-ep93xx/vision_ep9307.c
++++ b/arch/arm/mach-ep93xx/vision_ep9307.c
+@@ -22,7 +22,6 @@
+ #include <linux/io.h>
+ #include <linux/mtd/partitions.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
+ #include <linux/platform_data/pca953x.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/flash.h>
+@@ -144,10 +143,6 @@ static struct pca953x_platform_data pca953x_77_gpio_data = {
+ /*************************************************************************
+  * I2C Bus
+  *************************************************************************/
+-static struct i2c_gpio_platform_data vision_i2c_gpio_data __initdata = {
+-	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
+-	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
+-};
+ 
+ static struct i2c_board_info vision_i2c_info[] __initdata = {
+ 	{
+@@ -289,7 +284,7 @@ static void __init vision_init_machine(void)
+ 
+ 	vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
+ 
+-	ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
++	ep93xx_register_i2c(vision_i2c_info,
+ 				ARRAY_SIZE(vision_i2c_info));
+ 	ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
+ 				ARRAY_SIZE(vision_spi_board_info));
+diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
+index 186df64ceae7..c80f02ecfe6d 100644
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -18,7 +18,7 @@
+ #include <linux/serial.h>
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <asm/types.h>
+ #include <asm/setup.h>
+ #include <asm/memory.h>
+@@ -50,16 +50,21 @@ static struct platform_device avila_flash = {
+ 	.resource	= &avila_flash_resource,
+ };
+ 
+-static struct i2c_gpio_platform_data avila_i2c_gpio_data = {
+-	.sda_pin	= AVILA_SDA_PIN,
+-	.scl_pin	= AVILA_SCL_PIN,
++static struct gpiod_lookup_table avila_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device avila_i2c_gpio = {
+ 	.name		= "i2c-gpio",
+ 	.id		= 0,
+ 	.dev	 = {
+-		.platform_data	= &avila_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -148,6 +153,8 @@ static void __init avila_init(void)
+ 	avila_flash_resource.end =
+ 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+ 
++	gpiod_add_lookup_table(&avila_i2c_gpiod_table);
++
+ 	platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices));
+ 
+ 	avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1);
+diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+index db488ecc98b5..270b09d0d205 100644
+--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
++++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+@@ -26,7 +26,7 @@
+ #include <linux/leds.h>
+ #include <linux/reboot.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ 
+ #include <mach/hardware.h>
+ 
+@@ -69,16 +69,21 @@ static struct platform_device dsmg600_flash = {
+ 	.resource		= &dsmg600_flash_resource,
+ };
+ 
+-static struct i2c_gpio_platform_data dsmg600_i2c_gpio_data = {
+-	.sda_pin		= DSMG600_SDA_PIN,
+-	.scl_pin		= DSMG600_SCL_PIN,
++static struct gpiod_lookup_table dsmg600_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device dsmg600_i2c_gpio = {
+ 	.name			= "i2c-gpio",
+ 	.id			= 0,
+ 	.dev	 = {
+-		.platform_data	= &dsmg600_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -270,6 +275,7 @@ static void __init dsmg600_init(void)
+ 	dsmg600_flash_resource.end =
+ 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+ 
++	gpiod_add_lookup_table(&dsmg600_i2c_gpiod_table);
+ 	i2c_register_board_info(0, dsmg600_i2c_board_info,
+ 				ARRAY_SIZE(dsmg600_i2c_board_info));
+ 
+diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
+index 6e32cbc4f590..73c72eaeb034 100644
+--- a/arch/arm/mach-ixp4xx/fsg-setup.c
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -23,7 +23,7 @@
+ #include <linux/leds.h>
+ #include <linux/reboot.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/io.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -55,16 +55,21 @@ static struct platform_device fsg_flash = {
+ 	.resource		= &fsg_flash_resource,
+ };
+ 
+-static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
+-	.sda_pin		= FSG_SDA_PIN,
+-	.scl_pin		= FSG_SCL_PIN,
++static struct gpiod_lookup_table fsg_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device fsg_i2c_gpio = {
+ 	.name			= "i2c-gpio",
+ 	.id			= 0,
+ 	.dev = {
+-		.platform_data	= &fsg_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -197,6 +202,7 @@ static void __init fsg_init(void)
+ 	/* Configure CS2 for operation, 8bit and writable */
+ 	*IXP4XX_EXP_CS2 = 0xbfff0002;
+ 
++	gpiod_add_lookup_table(&fsg_i2c_gpiod_table);
+ 	i2c_register_board_info(0, fsg_i2c_board_info,
+ 				ARRAY_SIZE(fsg_i2c_board_info));
+ 
+diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
+index 145ec5c1b0eb..4d805080020e 100644
+--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
++++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
+@@ -7,7 +7,6 @@
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
+ #include <linux/hdlc.h>
+-#include <linux/i2c-gpio.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/kernel.h>
+@@ -79,6 +78,12 @@
+ static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
+ static u8 control_value;
+ 
++/*
++ * FIXME: this is reimplementing I2C bit-bangining. Move this
++ * over to using driver/i2c/busses/i2c-gpio.c like all other boards
++ * and register proper I2C device(s) on the bus for this. (See
++ * other IXP4xx boards for examples.)
++ */
+ static void set_scl(u8 value)
+ {
+ 	gpio_set_value(GPIO_SCL, !!value);
+@@ -217,20 +222,6 @@ static struct platform_device device_flash = {
+ 	.resource	= &flash_resource,
+ };
+ 
+-
+-/* I^2C interface */
+-static struct i2c_gpio_platform_data i2c_data = {
+-	.sda_pin	= GPIO_SDA,
+-	.scl_pin	= GPIO_SCL,
+-};
+-
+-static struct platform_device device_i2c = {
+-	.name		= "i2c-gpio",
+-	.id		= 0,
+-	.dev		= { .platform_data = &i2c_data },
+-};
+-
+-
+ /* IXP425 2 UART ports */
+ static struct resource uart_resources[] = {
+ 	{
+@@ -412,9 +403,6 @@ static void __init gmlr_init(void)
+ 	if (hw_bits & CFG_HW_HAS_HSS1)
+ 		device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
+ 
+-	if (hw_bits & CFG_HW_HAS_EEPROM)
+-		device_tab[devices++] = &device_i2c; /* max index 6 */
+-
+ 	gpio_request(GPIO_SCL, "SCL/clock");
+ 	gpio_request(GPIO_SDA, "SDA/data");
+ 	gpio_request(GPIO_STR, "strobe");
+diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+index 8f5e01527b1b..917af44c5780 100644
+--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+@@ -15,7 +15,7 @@
+ #include <linux/serial.h>
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/io.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/rawnand.h>
+@@ -123,16 +123,21 @@ static struct platform_device ixdp425_flash_nand = {
+ };
+ #endif	/* CONFIG_MTD_NAND_PLATFORM */
+ 
+-static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
+-	.sda_pin	= IXDP425_SDA_PIN,
+-	.scl_pin	= IXDP425_SCL_PIN,
++static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device ixdp425_i2c_gpio = {
+ 	.name		= "i2c-gpio",
+ 	.id		= 0,
+ 	.dev	 = {
+-		.platform_data	= &ixdp425_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -246,6 +251,7 @@ static void __init ixdp425_init(void)
+ 		ixdp425_uart_data[1].flags = 0;
+ 	}
+ 
++	gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
+ 	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
+ }
+ 
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index 1b8170d65c74..6c57b74cd703 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -28,7 +28,7 @@
+ #include <linux/leds.h>
+ #include <linux/reboot.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/io.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -101,16 +101,21 @@ static struct platform_device nas100d_leds = {
+ 	.dev.platform_data	= &nas100d_led_data,
+ };
+ 
+-static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = {
+-	.sda_pin		= NAS100D_SDA_PIN,
+-	.scl_pin		= NAS100D_SCL_PIN,
++static struct gpiod_lookup_table nas100d_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device nas100d_i2c_gpio = {
+ 	.name			= "i2c-gpio",
+ 	.id			= 0,
+ 	.dev	 = {
+-		.platform_data	= &nas100d_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -281,6 +286,7 @@ static void __init nas100d_init(void)
+ 	nas100d_flash_resource.end =
+ 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+ 
++	gpiod_add_lookup_table(&nas100d_i2c_gpiod_table);
+ 	i2c_register_board_info(0, nas100d_i2c_board_info,
+ 				ARRAY_SIZE(nas100d_i2c_board_info));
+ 
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index bd8dc65b4ffc..3bc4c69b8479 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -25,7 +25,7 @@
+ #include <linux/leds.h>
+ #include <linux/reboot.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/io.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -69,9 +69,14 @@ static struct platform_device nslu2_flash = {
+ 	.resource		= &nslu2_flash_resource,
+ };
+ 
+-static struct i2c_gpio_platform_data nslu2_i2c_gpio_data = {
+-	.sda_pin		= NSLU2_SDA_PIN,
+-	.scl_pin		= NSLU2_SCL_PIN,
++static struct gpiod_lookup_table nslu2_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SDA_PIN,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SCL_PIN,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct i2c_board_info __initdata nslu2_i2c_board_info [] = {
+@@ -116,7 +121,7 @@ static struct platform_device nslu2_i2c_gpio = {
+ 	.name			= "i2c-gpio",
+ 	.id			= 0,
+ 	.dev	 = {
+-		.platform_data	= &nslu2_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	},
+ };
+ 
+@@ -251,6 +256,7 @@ static void __init nslu2_init(void)
+ 	nslu2_flash_resource.end =
+ 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+ 
++	gpiod_add_lookup_table(&nslu2_i2c_gpiod_table);
+ 	i2c_register_board_info(0, nslu2_i2c_board_info,
+ 				ARRAY_SIZE(nslu2_i2c_board_info));
+ 
+diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
+index e4d709c8ed32..f034724e01e1 100644
+--- a/arch/arm/mach-ks8695/board-acs5k.c
++++ b/arch/arm/mach-ks8695/board-acs5k.c
+@@ -16,7 +16,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+-
++#include <linux/gpio/machine.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-algo-bit.h>
+ #include <linux/i2c-gpio.h>
+@@ -38,9 +38,15 @@
+ 
+ #include "generic.h"
+ 
++static struct gpiod_lookup_table acs5k_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("KS8695", 4, NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("KS8695", 5, NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data acs5k_i2c_device_platdata = {
+-	.sda_pin	= 4,
+-	.scl_pin	= 5,
+ 	.udelay		= 10,
+ };
+ 
+@@ -95,6 +101,7 @@ static struct i2c_board_info acs5k_i2c_devs[] __initdata = {
+ static void acs5k_i2c_init(void)
+ {
+ 	/* The gpio interface */
++	gpiod_add_lookup_table(&acs5k_i2c_gpiod_table);
+ 	platform_device_register(&acs5k_i2c_device);
+ 	/* I2C devices */
+ 	i2c_register_board_info(0, acs5k_i2c_devs,
+diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
+index 29630061e700..94f75632c007 100644
+--- a/arch/arm/mach-pxa/palmz72.c
++++ b/arch/arm/mach-pxa/palmz72.c
+@@ -31,6 +31,7 @@
+ #include <linux/power_supply.h>
+ #include <linux/usb/gpio_vbus.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ 
+ #include <asm/mach-types.h>
+ #include <asm/suspend.h>
+@@ -320,9 +321,15 @@ static struct soc_camera_link palmz72_iclink = {
+ 	.flags		= SOCAM_DATAWIDTH_8,
+ };
+ 
++static struct gpiod_lookup_table palmz72_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("gpio-pxa", 118, NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio-pxa", 117, NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data palmz72_i2c_bus_data = {
+-	.sda_pin	= 118,
+-	.scl_pin	= 117,
+ 	.udelay		= 10,
+ 	.timeout	= 100,
+ };
+@@ -369,6 +376,7 @@ static void __init palmz72_camera_init(void)
+ {
+ 	palmz72_cam_gpio_init();
+ 	pxa_set_camera_info(&palmz72_pxacamera_platform_data);
++	gpiod_add_lookup_table(&palmz72_i2c_gpiod_table);
+ 	platform_device_register(&palmz72_i2c_bus_device);
+ 	platform_device_register(&palmz72_camera);
+ }
+diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
+index 8e89d91b206b..a680742bee2b 100644
+--- a/arch/arm/mach-pxa/viper.c
++++ b/arch/arm/mach-pxa/viper.c
+@@ -36,6 +36,7 @@
+ #include <linux/gpio.h>
+ #include <linux/jiffies.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/i2c/pxa-i2c.h>
+ #include <linux/serial_8250.h>
+ #include <linux/smc91x.h>
+@@ -458,9 +459,17 @@ static struct platform_device smc91x_device = {
+ };
+ 
+ /* i2c */
++static struct gpiod_lookup_table viper_i2c_gpiod_table = {
++	.dev_id		= "i2c-gpio",
++	.table		= {
++		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SDA_GPIO,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SCL_GPIO,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data i2c_bus_data = {
+-	.sda_pin = VIPER_RTC_I2C_SDA_GPIO,
+-	.scl_pin = VIPER_RTC_I2C_SCL_GPIO,
+ 	.udelay  = 10,
+ 	.timeout = HZ,
+ };
+@@ -779,12 +788,20 @@ static int __init viper_tpm_setup(char *str)
+ 
+ __setup("tpm=", viper_tpm_setup);
+ 
++struct gpiod_lookup_table viper_tpm_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SDA_GPIO,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SCL_GPIO,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static void __init viper_tpm_init(void)
+ {
+ 	struct platform_device *tpm_device;
+ 	struct i2c_gpio_platform_data i2c_tpm_data = {
+-		.sda_pin = VIPER_TPM_I2C_SDA_GPIO,
+-		.scl_pin = VIPER_TPM_I2C_SCL_GPIO,
+ 		.udelay  = 10,
+ 		.timeout = HZ,
+ 	};
+@@ -794,6 +811,7 @@ static void __init viper_tpm_init(void)
+ 	if (!viper_tpm)
+ 		return;
+ 
++	gpiod_add_lookup_table(&viper_tpm_i2c_gpiod_table);
+ 	tpm_device = platform_device_alloc("i2c-gpio", 2);
+ 	if (tpm_device) {
+ 		if (!platform_device_add_data(tpm_device,
+@@ -943,6 +961,7 @@ static void __init viper_init(void)
+ 		smc91x_device.num_resources--;
+ 
+ 	pxa_set_i2c_info(NULL);
++	gpiod_add_lookup_table(&viper_i2c_gpiod_table);
+ 	pwm_add_table(viper_pwm_lookup, ARRAY_SIZE(viper_pwm_lookup));
+ 	platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
+ 
+diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
+index e8d25a7bbcb8..10c7ea426e5b 100644
+--- a/arch/arm/mach-sa1100/simpad.c
++++ b/arch/arm/mach-sa1100/simpad.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/io.h>
+ #include <linux/gpio/driver.h>
++#include <linux/gpio/machine.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/setup.h>
+@@ -324,9 +325,15 @@ static struct platform_device simpad_gpio_leds = {
+ /*
+  * i2c
+  */
++static struct gpiod_lookup_table simpad_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO21, NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO25, NULL, 1, GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data simpad_i2c_data = {
+-	.sda_pin = GPIO_GPIO21,
+-	.scl_pin = GPIO_GPIO25,
+ 	.udelay = 10,
+ 	.timeout = HZ,
+ };
+@@ -381,6 +388,7 @@ static int __init simpad_init(void)
+ 			      ARRAY_SIZE(simpad_flash_resources));
+ 	sa11x0_register_mcp(&simpad_mcp_data);
+ 
++	gpiod_add_lookup_table(&simpad_i2c_gpiod_table);
+ 	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+ 	if(ret)
+ 		printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
+diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
+index 0ccf0cf4daaf..d801ca5ca6c4 100644
+--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
++++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
+@@ -22,6 +22,7 @@
+ #include <linux/irq.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c.h>
++#include <linux/gpio/machine.h>
+ #include <asm/dma.h>
+ #include <asm/bfin5xx_spi.h>
+ #include <asm/portmux.h>
+@@ -362,11 +363,17 @@ static struct platform_device bfin_device_gpiokeys = {
+ #if IS_ENABLED(CONFIG_I2C_GPIO)
+ #include <linux/i2c-gpio.h>
+ 
++static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
++				GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
++				GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data i2c_gpio_data = {
+-	.sda_pin		= GPIO_PF8,
+-	.scl_pin		= GPIO_PF9,
+-	.sda_is_open_drain	= 0,
+-	.scl_is_open_drain	= 0,
+ 	.udelay			= 40,
+ }; /* This hasn't actually been used these pins
+     * are (currently) free pins on the expansion connector */
+@@ -462,7 +469,9 @@ static int __init blackstamp_init(void)
+ 	int ret;
+ 
+ 	printk(KERN_INFO "%s(): registering device resources\n", __func__);
+-
++#if IS_ENABLED(CONFIG_I2C_GPIO)
++	gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
++#endif
+ 	i2c_register_board_info(0, bfin_i2c_board_info,
+ 				ARRAY_SIZE(bfin_i2c_board_info));
+ 
+diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
+index 3625e9eaa8a8..463a72358b0e 100644
+--- a/arch/blackfin/mach-bf533/boards/ezkit.c
++++ b/arch/blackfin/mach-bf533/boards/ezkit.c
+@@ -19,6 +19,7 @@
+ #endif
+ #include <linux/irq.h>
+ #include <linux/i2c.h>
++#include <linux/gpio/machine.h>
+ #include <asm/dma.h>
+ #include <asm/bfin5xx_spi.h>
+ #include <asm/portmux.h>
+@@ -390,11 +391,17 @@ static struct platform_device bfin_device_gpiokeys = {
+ #if IS_ENABLED(CONFIG_I2C_GPIO)
+ #include <linux/i2c-gpio.h>
+ 
++static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
++				GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
++				GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data i2c_gpio_data = {
+-	.sda_pin		= GPIO_PF1,
+-	.scl_pin		= GPIO_PF0,
+-	.sda_is_open_drain	= 0,
+-	.scl_is_open_drain	= 0,
+ 	.udelay			= 40,
+ };
+ 
+@@ -516,6 +523,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
+ static int __init ezkit_init(void)
+ {
+ 	printk(KERN_INFO "%s(): registering device resources\n", __func__);
++#if IS_ENABLED(CONFIG_I2C_GPIO)
++	gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
++#endif
+ 	platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+ 	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+ 	i2c_register_board_info(0, bfin_i2c_board_info,
+diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
+index 23eada79439c..d2479359adb7 100644
+--- a/arch/blackfin/mach-bf533/boards/stamp.c
++++ b/arch/blackfin/mach-bf533/boards/stamp.c
+@@ -21,6 +21,7 @@
+ #include <linux/gpio.h>
+ #include <linux/irq.h>
+ #include <linux/i2c.h>
++#include <linux/gpio/machine.h>
+ #include <asm/dma.h>
+ #include <asm/bfin5xx_spi.h>
+ #include <asm/reboot.h>
+@@ -512,11 +513,17 @@ static struct platform_device bfin_device_gpiokeys = {
+ #if IS_ENABLED(CONFIG_I2C_GPIO)
+ #include <linux/i2c-gpio.h>
+ 
++static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
++				GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
++				GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data i2c_gpio_data = {
+-	.sda_pin		= GPIO_PF2,
+-	.scl_pin		= GPIO_PF3,
+-	.sda_is_open_drain	= 0,
+-	.scl_is_open_drain	= 0,
+ 	.udelay			= 10,
+ };
+ 
+@@ -848,6 +855,9 @@ static int __init stamp_init(void)
+ 
+ 	printk(KERN_INFO "%s(): registering device resources\n", __func__);
+ 
++#if IS_ENABLED(CONFIG_I2C_GPIO)
++	gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
++#endif
+ 	i2c_register_board_info(0, bfin_i2c_board_info,
+ 				ARRAY_SIZE(bfin_i2c_board_info));
+ 
+diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
+index 57d1c43726d9..72f757ebaa84 100644
+--- a/arch/blackfin/mach-bf561/boards/ezkit.c
++++ b/arch/blackfin/mach-bf561/boards/ezkit.c
+@@ -16,6 +16,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/gpio.h>
+ #include <linux/delay.h>
++#include <linux/gpio/machine.h>
+ #include <asm/dma.h>
+ #include <asm/bfin5xx_spi.h>
+ #include <asm/portmux.h>
+@@ -379,11 +380,17 @@ static struct platform_device bfin_device_gpiokeys = {
+ #if IS_ENABLED(CONFIG_I2C_GPIO)
+ #include <linux/i2c-gpio.h>
+ 
++static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
++				GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
++				GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data i2c_gpio_data = {
+-	.sda_pin		= GPIO_PF1,
+-	.scl_pin		= GPIO_PF0,
+-	.sda_is_open_drain	= 0,
+-	.scl_is_open_drain	= 0,
+ 	.udelay			= 10,
+ };
+ 
+@@ -633,6 +640,9 @@ static int __init ezkit_init(void)
+ 
+ 	printk(KERN_INFO "%s(): registering device resources\n", __func__);
+ 
++#if IS_ENABLED(CONFIG_I2C_GPIO)
++	gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
++#endif
+ 	ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+ 	if (ret < 0)
+ 		return ret;
+diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
+index 6fb6b3faa158..daebc36e5ecb 100644
+--- a/arch/mips/alchemy/board-gpr.c
++++ b/arch/mips/alchemy/board-gpr.c
+@@ -30,6 +30,7 @@
+ #include <linux/gpio.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+ #include <asm/reboot.h>
+@@ -218,10 +219,23 @@ static struct platform_device gpr_led_devices = {
+ /*
+  * I2C
+  */
++static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		/*
++		 * This should be on "GPIO2" which has base at 200 so
++		 * the global numbers 209 and 210 should correspond to
++		 * local offsets 9 and 10.
++		 */
++		GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
++				GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
++				GPIO_ACTIVE_HIGH),
++	},
++};
++
+ static struct i2c_gpio_platform_data gpr_i2c_data = {
+-	.sda_pin		= 209,
+ 	.sda_is_open_drain	= 1,
+-	.scl_pin		= 210,
+ 	.scl_is_open_drain	= 1,
+ 	.udelay			= 2,		/* ~100 kHz */
+ 	.timeout		= HZ,
+@@ -295,6 +309,7 @@ arch_initcall(gpr_pci_init);
+ 
+ static int __init gpr_dev_init(void)
+ {
++	gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
+ 	i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
+ 
+ 	return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
+diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
+index be78298dffb4..a95409063847 100644
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -11,7 +11,7 @@
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/platform_data/pcf857x.h>
+ 
+ #include "machtypes.h"
+@@ -33,16 +33,21 @@
+ #define PB44_KEYS_POLL_INTERVAL		20	/* msecs */
+ #define PB44_KEYS_DEBOUNCE_INTERVAL	(3 * PB44_KEYS_POLL_INTERVAL)
+ 
+-static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {
+-	.sda_pin	= PB44_GPIO_I2C_SDA,
+-	.scl_pin	= PB44_GPIO_I2C_SCL,
++static struct gpiod_lookup_table pb44_i2c_gpiod_table = {
++	.dev_id = "i2c-gpio",
++	.table = {
++		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SDA,
++				NULL, 0, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SCL,
++				NULL, 1, GPIO_ACTIVE_HIGH),
++	},
+ };
+ 
+ static struct platform_device pb44_i2c_gpio_device = {
+ 	.name		= "i2c-gpio",
+ 	.id		= 0,
+ 	.dev = {
+-		.platform_data	= &pb44_i2c_gpio_data,
++		.platform_data	= NULL,
+ 	}
+ };
+ 
+@@ -103,6 +108,7 @@ static struct ath79_spi_platform_data pb44_spi_data = {
+ 
+ static void __init pb44_init(void)
+ {
++	gpiod_add_lookup_table(&pb44_i2c_gpiod_table);
+ 	i2c_register_board_info(0, pb44_i2c_board_info,
+ 				ARRAY_SIZE(pb44_i2c_board_info));
+ 	platform_device_register(&pb44_i2c_gpio_device);
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index 0ef8fcc6ac3a..b4664037eded 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -14,11 +14,12 @@
+ #include <linux/module.h>
+ #include <linux/slab.h>
+ #include <linux/platform_device.h>
+-#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/of.h>
+-#include <linux/of_gpio.h>
+ 
+ struct i2c_gpio_private_data {
++	struct gpio_desc *sda;
++	struct gpio_desc *scl;
+ 	struct i2c_adapter adap;
+ 	struct i2c_algo_bit_data bit_data;
+ 	struct i2c_gpio_platform_data pdata;
+@@ -27,12 +28,18 @@ struct i2c_gpio_private_data {
+ /* Toggle SDA by changing the direction of the pin */
+ static void i2c_gpio_setsda_dir(void *data, int state)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
+-
++	struct i2c_gpio_private_data *priv = data;
++
++	/*
++	 * This is a way of saying "do not drive
++	 * me actively high" which means emulating open drain.
++	 * The right way to do this is for gpiolib to
++	 * handle this, by the function below.
++	 */
+ 	if (state)
+-		gpio_direction_input(pdata->sda_pin);
++		gpiod_direction_input(priv->sda);
+ 	else
+-		gpio_direction_output(pdata->sda_pin, 0);
++		gpiod_direction_output(priv->sda, 0);
+ }
+ 
+ /*
+@@ -42,20 +49,20 @@ static void i2c_gpio_setsda_dir(void *data, int state)
+  */
+ static void i2c_gpio_setsda_val(void *data, int state)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
++	struct i2c_gpio_private_data *priv = data;
+ 
+-	gpio_set_value(pdata->sda_pin, state);
++	gpiod_set_value(priv->sda, state);
+ }
+ 
+ /* Toggle SCL by changing the direction of the pin. */
+ static void i2c_gpio_setscl_dir(void *data, int state)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
++	struct i2c_gpio_private_data *priv = data;
+ 
+ 	if (state)
+-		gpio_direction_input(pdata->scl_pin);
++		gpiod_direction_input(priv->scl);
+ 	else
+-		gpio_direction_output(pdata->scl_pin, 0);
++		gpiod_direction_output(priv->scl, 0);
+ }
+ 
+ /*
+@@ -66,44 +73,23 @@ static void i2c_gpio_setscl_dir(void *data, int state)
+  */
+ static void i2c_gpio_setscl_val(void *data, int state)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
++	struct i2c_gpio_private_data *priv = data;
+ 
+-	gpio_set_value(pdata->scl_pin, state);
++	gpiod_set_value(priv->scl, state);
+ }
+ 
+ static int i2c_gpio_getsda(void *data)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
++	struct i2c_gpio_private_data *priv = data;
+ 
+-	return gpio_get_value(pdata->sda_pin);
++	return gpiod_get_value(priv->sda);
+ }
+ 
+ static int i2c_gpio_getscl(void *data)
+ {
+-	struct i2c_gpio_platform_data *pdata = data;
++	struct i2c_gpio_private_data *priv = data;
+ 
+-	return gpio_get_value(pdata->scl_pin);
+-}
+-
+-static int of_i2c_gpio_get_pins(struct device_node *np,
+-				unsigned int *sda_pin, unsigned int *scl_pin)
+-{
+-	if (of_gpio_count(np) < 2)
+-		return -ENODEV;
+-
+-	*sda_pin = of_get_gpio(np, 0);
+-	*scl_pin = of_get_gpio(np, 1);
+-
+-	if (*sda_pin == -EPROBE_DEFER || *scl_pin == -EPROBE_DEFER)
+-		return -EPROBE_DEFER;
+-
+-	if (!gpio_is_valid(*sda_pin) || !gpio_is_valid(*scl_pin)) {
+-		pr_err("%pOF: invalid GPIO pins, sda=%d/scl=%d\n",
+-		       np, *sda_pin, *scl_pin);
+-		return -ENODEV;
+-	}
+-
+-	return 0;
++	return gpiod_get_value(priv->scl);
+ }
+ 
+ static void of_i2c_gpio_get_props(struct device_node *np,
+@@ -130,64 +116,65 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	struct i2c_gpio_platform_data *pdata;
+ 	struct i2c_algo_bit_data *bit_data;
+ 	struct i2c_adapter *adap;
+-	unsigned int sda_pin, scl_pin;
+ 	int ret;
+ 
+-	/* First get the GPIO pins; if it fails, we'll defer the probe. */
+-	if (pdev->dev.of_node) {
+-		ret = of_i2c_gpio_get_pins(pdev->dev.of_node,
+-					   &sda_pin, &scl_pin);
+-		if (ret)
+-			return ret;
+-	} else {
+-		if (!dev_get_platdata(&pdev->dev))
+-			return -ENXIO;
+-		pdata = dev_get_platdata(&pdev->dev);
+-		sda_pin = pdata->sda_pin;
+-		scl_pin = pdata->scl_pin;
+-	}
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
+ 
+-	ret = devm_gpio_request(&pdev->dev, sda_pin, "sda");
+-	if (ret) {
++	/* First get the GPIO pins; if it fails, we'll defer the probe. */
++	priv->sda = devm_gpiod_get_index(&pdev->dev, NULL, 0, GPIOD_OUT_HIGH);
++	if (IS_ERR(priv->sda)) {
++		ret = PTR_ERR(priv->sda);
++		/* FIXME: hack in the old code, is this really necessary? */
+ 		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;	/* Try again later */
++			ret = -EPROBE_DEFER;
+ 		return ret;
+ 	}
+-	ret = devm_gpio_request(&pdev->dev, scl_pin, "scl");
+-	if (ret) {
++	priv->scl = devm_gpiod_get_index(&pdev->dev, NULL, 1, GPIOD_OUT_LOW);
++	if (IS_ERR(priv->scl)) {
++		ret = PTR_ERR(priv->scl);
++		/* FIXME: hack in the old code, is this really necessary? */
+ 		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;	/* Try again later */
++			ret = -EPROBE_DEFER;
+ 		return ret;
+ 	}
+ 
+-	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+ 	adap = &priv->adap;
+ 	bit_data = &priv->bit_data;
+ 	pdata = &priv->pdata;
+ 
+ 	if (pdev->dev.of_node) {
+-		pdata->sda_pin = sda_pin;
+-		pdata->scl_pin = scl_pin;
+ 		of_i2c_gpio_get_props(pdev->dev.of_node, pdata);
+ 	} else {
+-		memcpy(pdata, dev_get_platdata(&pdev->dev), sizeof(*pdata));
++		/*
++		 * If all platform data settings are zero it is OK
++		 * to not provide any platform data from the board.
++		 */
++		if (dev_get_platdata(&pdev->dev))
++			memcpy(pdata, dev_get_platdata(&pdev->dev),
++			       sizeof(*pdata));
+ 	}
+ 
++	/*
++	 * FIXME: this is a hack emulating the open drain emulation
++	 * that gpiolib can already do for us. Make all clients properly
++	 * flag their lines as open drain and get rid of this property
++	 * and the special callback.
++	 */
+ 	if (pdata->sda_is_open_drain) {
+-		gpio_direction_output(pdata->sda_pin, 1);
++		gpiod_direction_output(priv->sda, 1);
+ 		bit_data->setsda = i2c_gpio_setsda_val;
+ 	} else {
+-		gpio_direction_input(pdata->sda_pin);
++		gpiod_direction_input(priv->sda);
+ 		bit_data->setsda = i2c_gpio_setsda_dir;
+ 	}
+ 
+ 	if (pdata->scl_is_open_drain || pdata->scl_is_output_only) {
+-		gpio_direction_output(pdata->scl_pin, 1);
++		gpiod_direction_output(priv->scl, 1);
+ 		bit_data->setscl = i2c_gpio_setscl_val;
+ 	} else {
+-		gpio_direction_input(pdata->scl_pin);
++		gpiod_direction_input(priv->scl);
+ 		bit_data->setscl = i2c_gpio_setscl_dir;
+ 	}
+ 
+@@ -207,7 +194,7 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	else
+ 		bit_data->timeout = HZ / 10;		/* 100 ms */
+ 
+-	bit_data->data = pdata;
++	bit_data->data = priv;
+ 
+ 	adap->owner = THIS_MODULE;
+ 	if (pdev->dev.of_node)
+@@ -227,8 +214,13 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, priv);
+ 
+-	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
+-		 pdata->sda_pin, pdata->scl_pin,
++	/*
++	 * FIXME: using global GPIO numbers is not helpful. If/when we
++	 * get accessors to get the actual name of the GPIO line,
++	 * from the descriptor, then provide that instead.
++	 */
++	dev_info(&pdev->dev, "using lines %u (SDA) and %u (SCL%s)\n",
++		 desc_to_gpio(priv->sda), desc_to_gpio(priv->scl),
+ 		 pdata->scl_is_output_only
+ 		 ? ", no clock stretching" : "");
+ 
+diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
+index 3270b8dbc949..d67bbb153af4 100644
+--- a/drivers/mfd/sm501.c
++++ b/drivers/mfd/sm501.c
+@@ -20,6 +20,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pci.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/gpio/machine.h>
+ #include <linux/slab.h>
+ 
+ #include <linux/sm501.h>
+@@ -1108,14 +1109,6 @@ static void sm501_gpio_remove(struct sm501_devdata *sm)
+ 	kfree(gpio->regs_res);
+ }
+ 
+-static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
+-{
+-	struct sm501_gpio *gpio = &sm->gpio;
+-	int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
+-
+-	return (pin % 32) + base;
+-}
+-
+ static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+ {
+ 	return sm->gpio.registered;
+@@ -1130,11 +1123,6 @@ static inline void sm501_gpio_remove(struct sm501_devdata *sm)
+ {
+ }
+ 
+-static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
+-{
+-	return -1;
+-}
+-
+ static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
+ {
+ 	return 0;
+@@ -1146,20 +1134,37 @@ static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
+ {
+ 	struct i2c_gpio_platform_data *icd;
+ 	struct platform_device *pdev;
++	struct gpiod_lookup_table *lookup;
+ 
+ 	pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
+ 				   sizeof(struct i2c_gpio_platform_data));
+ 	if (!pdev)
+ 		return -ENOMEM;
+ 
+-	icd = dev_get_platdata(&pdev->dev);
+-
+-	/* We keep the pin_sda and pin_scl fields relative in case the
+-	 * same platform data is passed to >1 SM501.
+-	 */
++	/* Create a gpiod lookup using gpiochip-local offsets */
++	lookup = devm_kzalloc(&pdev->dev,
++			      sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
++			      GFP_KERNEL);
++	lookup->dev_id = "i2c-gpio";
++	if (iic->pin_sda < 32)
++		lookup->table[0].chip_label = "SM501-LOW";
++	else
++		lookup->table[0].chip_label = "SM501-HIGH";
++	lookup->table[0].chip_hwnum = iic->pin_sda % 32;
++	lookup->table[0].con_id = NULL;
++	lookup->table[0].idx = 0;
++	lookup->table[0].flags = GPIO_ACTIVE_HIGH;
++	if (iic->pin_scl < 32)
++		lookup->table[1].chip_label = "SM501-LOW";
++	else
++		lookup->table[1].chip_label = "SM501-HIGH";
++	lookup->table[1].chip_hwnum = iic->pin_scl % 32;
++	lookup->table[1].con_id = NULL;
++	lookup->table[1].idx = 1;
++	lookup->table[1].flags = GPIO_ACTIVE_HIGH;
++	gpiod_add_lookup_table(lookup);
+ 
+-	icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
+-	icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
++	icd = dev_get_platdata(&pdev->dev);
+ 	icd->timeout = iic->timeout;
+ 	icd->udelay = iic->udelay;
+ 
+@@ -1171,9 +1176,9 @@ static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
+ 
+ 	pdev->id = iic->bus_num;
+ 
+-	dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
++	dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
+ 		 iic->bus_num,
+-		 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
++		 iic->pin_sda, iic->pin_scl);
+ 
+ 	return sm501_register_device(sm, pdev);
+ }
+diff --git a/include/linux/i2c-gpio.h b/include/linux/i2c-gpio.h
+index c1bcb1f1d73b..352c1426fd4d 100644
+--- a/include/linux/i2c-gpio.h
++++ b/include/linux/i2c-gpio.h
+@@ -12,8 +12,6 @@
+ 
+ /**
+  * struct i2c_gpio_platform_data - Platform-dependent data for i2c-gpio
+- * @sda_pin: GPIO pin ID to use for SDA
+- * @scl_pin: GPIO pin ID to use for SCL
+  * @udelay: signal toggle delay. SCL frequency is (500 / udelay) kHz
+  * @timeout: clock stretching timeout in jiffies. If the slave keeps
+  *	SCL low for longer than this, the transfer will time out.
+@@ -26,8 +24,6 @@
+  * @scl_is_output_only: SCL output drivers cannot be turned off.
+  */
+ struct i2c_gpio_platform_data {
+-	unsigned int	sda_pin;
+-	unsigned int	scl_pin;
+ 	int		udelay;
+ 	int		timeout;
+ 	unsigned int	sda_is_open_drain:1;
+-- 
+2.19.0
+
diff --git a/patches/0394-gpio-Make-it-possible-for-consumers-to-enforce-open-.patch b/patches/0394-gpio-Make-it-possible-for-consumers-to-enforce-open-.patch
new file mode 100644
index 00000000000000..891fdbd96dffdc
--- /dev/null
+++ b/patches/0394-gpio-Make-it-possible-for-consumers-to-enforce-open-.patch
@@ -0,0 +1,97 @@
+From dfdd0a7f23007b03125d56dd275f67b557b8bdf1 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 19:26:22 +0200
+Subject: [PATCH 0394/1795] gpio: Make it possible for consumers to enforce
+ open drain
+
+Some busses, like I2C, strictly need to have the line handled
+as open drain, i.e. not actively driven high. For this reason
+the i2c-gpio.c bit-banged I2C driver is reimplementing open
+drain handling outside of gpiolib.
+
+This is not very optimal. Instead make it possible for a
+consumer to explcitly express that the line must be handled
+as open drain instead of allowing local hacks papering over
+this issue.
+
+The descriptor tables, whether DT, ACPI or board files, should
+of course have flagged these lines as open drain. E.g.:
+enum gpio_lookup_flags GPIO_OPEN_DRAIN for a board file, or
+gpios = <&foo 42 GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN>; in a
+device tree using <dt-bindings/gpio/gpio.h>
+
+But more often than not, these descriptors are wrong. So
+we need to make it possible for consumers to enforce this
+open drain behaviour.
+
+We now have two new enumerated GPIO descriptor config flags:
+GPIOD_OUT_LOW_OPEN_DRAIN and GPIOD_OUT_HIGH_OPEN_DRAIN
+that will set up the lined enforced as open drain as output
+low or high, using open drain (if the driver supports it)
+or using open drain emulation (setting the line as input
+to drive it high) from the gpiolib core.
+
+Cc: linux-gpio@vger.kernel.org
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit f926dfc112bc6cf41d7068ee5e3f261e13a5bec8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpiolib.c        | 13 +++++++++++++
+ include/linux/gpio/consumer.h |  6 ++++++
+ 2 files changed, 19 insertions(+)
+
+diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
+index 99d0b3510b54..e7660b708635 100644
+--- a/drivers/gpio/gpiolib.c
++++ b/drivers/gpio/gpiolib.c
+@@ -3268,8 +3268,21 @@ int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
+ 
+ 	if (lflags & GPIO_ACTIVE_LOW)
+ 		set_bit(FLAG_ACTIVE_LOW, &desc->flags);
++
+ 	if (lflags & GPIO_OPEN_DRAIN)
+ 		set_bit(FLAG_OPEN_DRAIN, &desc->flags);
++	else if (dflags & GPIOD_FLAGS_BIT_OPEN_DRAIN) {
++		/*
++		 * This enforces open drain mode from the consumer side.
++		 * This is necessary for some busses like I2C, but the lookup
++		 * should *REALLY* have specified them as open drain in the
++		 * first place, so print a little warning here.
++		 */
++		set_bit(FLAG_OPEN_DRAIN, &desc->flags);
++		gpiod_warn(desc,
++			   "enforced open drain please flag it properly in DT/ACPI DSDT/board file\n");
++	}
++
+ 	if (lflags & GPIO_OPEN_SOURCE)
+ 		set_bit(FLAG_OPEN_SOURCE, &desc->flags);
+ 	if (lflags & GPIO_SLEEP_MAY_LOOSE_VALUE)
+diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h
+index c4a350d83578..11fb79f3dd24 100644
+--- a/include/linux/gpio/consumer.h
++++ b/include/linux/gpio/consumer.h
+@@ -29,6 +29,7 @@ struct gpio_descs {
+ #define GPIOD_FLAGS_BIT_DIR_SET		BIT(0)
+ #define GPIOD_FLAGS_BIT_DIR_OUT		BIT(1)
+ #define GPIOD_FLAGS_BIT_DIR_VAL		BIT(2)
++#define GPIOD_FLAGS_BIT_OPEN_DRAIN	BIT(3)
+ 
+ /**
+  * Optional flags that can be passed to one of gpiod_* to configure direction
+@@ -40,6 +41,11 @@ enum gpiod_flags {
+ 	GPIOD_OUT_LOW	= GPIOD_FLAGS_BIT_DIR_SET | GPIOD_FLAGS_BIT_DIR_OUT,
+ 	GPIOD_OUT_HIGH	= GPIOD_FLAGS_BIT_DIR_SET | GPIOD_FLAGS_BIT_DIR_OUT |
+ 			  GPIOD_FLAGS_BIT_DIR_VAL,
++	GPIOD_OUT_LOW_OPEN_DRAIN = GPIOD_FLAGS_BIT_DIR_SET |
++			  GPIOD_FLAGS_BIT_DIR_OUT | GPIOD_FLAGS_BIT_OPEN_DRAIN,
++	GPIOD_OUT_HIGH_OPEN_DRAIN = GPIOD_FLAGS_BIT_DIR_SET |
++			  GPIOD_FLAGS_BIT_DIR_OUT | GPIOD_FLAGS_BIT_DIR_VAL |
++			  GPIOD_FLAGS_BIT_OPEN_DRAIN,
+ };
+ 
+ #ifdef CONFIG_GPIOLIB
+-- 
+2.19.0
+
diff --git a/patches/0395-i2c-gpio-Enforce-open-drain-through-gpiolib.patch b/patches/0395-i2c-gpio-Enforce-open-drain-through-gpiolib.patch
new file mode 100644
index 00000000000000..c25c17b0bdccfa
--- /dev/null
+++ b/patches/0395-i2c-gpio-Enforce-open-drain-through-gpiolib.patch
@@ -0,0 +1,195 @@
+From 91fa59090303fbd277bbcde4b459949431802788 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 19:54:21 +0200
+Subject: [PATCH 0395/1795] i2c: gpio: Enforce open drain through gpiolib
+
+The I2C GPIO bitbang driver currently emulates open drain
+behaviour by implementing what the gpiolib already does:
+not actively driving the line high, instead setting it to
+input.
+
+This makes no sense. Use the new facility in gpiolib to
+request the lines enforced into open drain mode, and let
+the open drain emulation already present in the gpiolib
+kick in and handle this.
+
+As a bonus: if the GPIO driver in the back-end actually
+supports open drain in hardware using the .set_config()
+callback, it will be utilized. That's correct: we never
+used that hardware feature before, instead relying on
+emulating open drain even if the GPIO controller could
+actually handle this for us.
+
+Users will sometimes get messages like this:
+gpio-485 (?): enforced open drain please flag it properly
+  in DT/ACPI DSDT/board file
+gpio-486 (?): enforced open drain please flag it properly
+  in DT/ACPI DSDT/board file
+i2c-gpio gpio-i2c: using lines 485 (SDA) and 486 (SCL)
+
+Which is completely proper: since the line is used as
+open drain, it should actually be flagged properly with
+e.g.
+
+gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>,
+        <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+Or similar facilities in board file descriptor tables
+or ACPI DSDT.
+
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 7bb75029ef34838604357350b4f24d6535e9d01f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-gpio.c | 102 +++++++++++++---------------------
+ 1 file changed, 39 insertions(+), 63 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index b4664037eded..97b9c29e9429 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -25,23 +25,6 @@ struct i2c_gpio_private_data {
+ 	struct i2c_gpio_platform_data pdata;
+ };
+ 
+-/* Toggle SDA by changing the direction of the pin */
+-static void i2c_gpio_setsda_dir(void *data, int state)
+-{
+-	struct i2c_gpio_private_data *priv = data;
+-
+-	/*
+-	 * This is a way of saying "do not drive
+-	 * me actively high" which means emulating open drain.
+-	 * The right way to do this is for gpiolib to
+-	 * handle this, by the function below.
+-	 */
+-	if (state)
+-		gpiod_direction_input(priv->sda);
+-	else
+-		gpiod_direction_output(priv->sda, 0);
+-}
+-
+ /*
+  * Toggle SDA by changing the output value of the pin. This is only
+  * valid for pins configured as open drain (i.e. setting the value
+@@ -54,17 +37,6 @@ static void i2c_gpio_setsda_val(void *data, int state)
+ 	gpiod_set_value(priv->sda, state);
+ }
+ 
+-/* Toggle SCL by changing the direction of the pin. */
+-static void i2c_gpio_setscl_dir(void *data, int state)
+-{
+-	struct i2c_gpio_private_data *priv = data;
+-
+-	if (state)
+-		gpiod_direction_input(priv->scl);
+-	else
+-		gpiod_direction_output(priv->scl, 0);
+-}
+-
+ /*
+  * Toggle SCL by changing the output value of the pin. This is used
+  * for pins that are configured as open drain and for output-only
+@@ -116,30 +88,13 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	struct i2c_gpio_platform_data *pdata;
+ 	struct i2c_algo_bit_data *bit_data;
+ 	struct i2c_adapter *adap;
++	enum gpiod_flags gflags;
+ 	int ret;
+ 
+ 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	/* First get the GPIO pins; if it fails, we'll defer the probe. */
+-	priv->sda = devm_gpiod_get_index(&pdev->dev, NULL, 0, GPIOD_OUT_HIGH);
+-	if (IS_ERR(priv->sda)) {
+-		ret = PTR_ERR(priv->sda);
+-		/* FIXME: hack in the old code, is this really necessary? */
+-		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;
+-		return ret;
+-	}
+-	priv->scl = devm_gpiod_get_index(&pdev->dev, NULL, 1, GPIOD_OUT_LOW);
+-	if (IS_ERR(priv->scl)) {
+-		ret = PTR_ERR(priv->scl);
+-		/* FIXME: hack in the old code, is this really necessary? */
+-		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;
+-		return ret;
+-	}
+-
+ 	adap = &priv->adap;
+ 	bit_data = &priv->bit_data;
+ 	pdata = &priv->pdata;
+@@ -157,27 +112,48 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/*
+-	 * FIXME: this is a hack emulating the open drain emulation
+-	 * that gpiolib can already do for us. Make all clients properly
+-	 * flag their lines as open drain and get rid of this property
+-	 * and the special callback.
++	 * First get the GPIO pins; if it fails, we'll defer the probe.
++	 * If the SDA line is marked from platform data or device tree as
++	 * "open drain" it means something outside of our control is making
++	 * this line being handled as open drain, and we should just handle
++	 * it as any other output. Else we enforce open drain as this is
++	 * required for an I2C bus.
+ 	 */
+-	if (pdata->sda_is_open_drain) {
+-		gpiod_direction_output(priv->sda, 1);
+-		bit_data->setsda = i2c_gpio_setsda_val;
+-	} else {
+-		gpiod_direction_input(priv->sda);
+-		bit_data->setsda = i2c_gpio_setsda_dir;
++	if (pdata->sda_is_open_drain)
++		gflags = GPIOD_OUT_HIGH;
++	else
++		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
++	priv->sda = devm_gpiod_get_index(&pdev->dev, NULL, 0, gflags);
++	if (IS_ERR(priv->sda)) {
++		ret = PTR_ERR(priv->sda);
++		/* FIXME: hack in the old code, is this really necessary? */
++		if (ret == -EINVAL)
++			ret = -EPROBE_DEFER;
++		return ret;
+ 	}
+-
+-	if (pdata->scl_is_open_drain || pdata->scl_is_output_only) {
+-		gpiod_direction_output(priv->scl, 1);
+-		bit_data->setscl = i2c_gpio_setscl_val;
+-	} else {
+-		gpiod_direction_input(priv->scl);
+-		bit_data->setscl = i2c_gpio_setscl_dir;
++	/*
++	 * If the SCL line is marked from platform data or device tree as
++	 * "open drain" it means something outside of our control is making
++	 * this line being handled as open drain, and we should just handle
++	 * it as any other output. Else we enforce open drain as this is
++	 * required for an I2C bus.
++	 */
++	if (pdata->scl_is_open_drain)
++		gflags = GPIOD_OUT_LOW;
++	else
++		gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
++	priv->scl = devm_gpiod_get_index(&pdev->dev, NULL, 1, gflags);
++	if (IS_ERR(priv->scl)) {
++		ret = PTR_ERR(priv->scl);
++		/* FIXME: hack in the old code, is this really necessary? */
++		if (ret == -EINVAL)
++			ret = -EPROBE_DEFER;
++		return ret;
+ 	}
+ 
++	bit_data->setsda = i2c_gpio_setsda_val;
++	bit_data->setscl = i2c_gpio_setscl_val;
++
+ 	if (!pdata->scl_is_output_only)
+ 		bit_data->getscl = i2c_gpio_getscl;
+ 	bit_data->getsda = i2c_gpio_getsda;
+-- 
+2.19.0
+
diff --git a/patches/0396-i2c-gpio-Augment-all-boardfiles-to-use-open-drain.patch b/patches/0396-i2c-gpio-Augment-all-boardfiles-to-use-open-drain.patch
new file mode 100644
index 00000000000000..8428c0c251bba4
--- /dev/null
+++ b/patches/0396-i2c-gpio-Augment-all-boardfiles-to-use-open-drain.patch
@@ -0,0 +1,360 @@
+From 68aba523a18ba1aa4cb155f3f6f92733002cbafe Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 23:03:32 +0200
+Subject: [PATCH 0396/1795] i2c: gpio: Augment all boardfiles to use open drain
+
+We now handle the open drain mode internally in the I2C GPIO
+driver, but we will get warnings from the gpiolib that we
+override the default mode of the line so it becomes open
+drain.
+
+We can fix all in-kernel users by simply passing the right
+flag along in the descriptor table, and we already touched
+all of these files in the series so let's just tidy it up.
+
+Cc: Steven Miao <realmz6@gmail.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Acked-by: Olof Johansson <olof@lixom.net>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
+Acked-by: Ralf Baechle <ralf@linux-mips.org>
+Acked-by: Wu, Aaron <Aaron.Wu@analog.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 4d0ce62c0a02e41a65cfdcfe277f5be430edc371)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-ep93xx/core.c                  | 6 ++++--
+ arch/arm/mach-ixp4xx/avila-setup.c           | 4 ++--
+ arch/arm/mach-ixp4xx/dsmg600-setup.c         | 4 ++--
+ arch/arm/mach-ixp4xx/fsg-setup.c             | 4 ++--
+ arch/arm/mach-ixp4xx/ixdp425-setup.c         | 4 ++--
+ arch/arm/mach-ixp4xx/nas100d-setup.c         | 4 ++--
+ arch/arm/mach-ixp4xx/nslu2-setup.c           | 4 ++--
+ arch/arm/mach-ks8695/board-acs5k.c           | 6 ++++--
+ arch/arm/mach-pxa/palmz72.c                  | 6 ++++--
+ arch/arm/mach-pxa/viper.c                    | 8 ++++----
+ arch/arm/mach-sa1100/simpad.c                | 6 ++++--
+ arch/blackfin/mach-bf533/boards/blackstamp.c | 4 ++--
+ arch/blackfin/mach-bf533/boards/ezkit.c      | 4 ++--
+ arch/blackfin/mach-bf533/boards/stamp.c      | 4 ++--
+ arch/blackfin/mach-bf561/boards/ezkit.c      | 4 ++--
+ arch/mips/alchemy/board-gpr.c                | 4 ++++
+ arch/mips/ath79/mach-pb44.c                  | 4 ++--
+ drivers/mfd/sm501.c                          | 4 ++--
+ 18 files changed, 48 insertions(+), 36 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index 7e99fe829ad1..e70feec6fad5 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -326,8 +326,10 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		/* Use local offsets on gpiochip/port "G" */
+-		GPIO_LOOKUP_IDX("G", 1, NULL, 0, GPIO_ACTIVE_HIGH),
+-		GPIO_LOOKUP_IDX("G", 0, NULL, 1, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("G", 1, NULL, 0,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
++		GPIO_LOOKUP_IDX("G", 0, NULL, 1,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
+index c80f02ecfe6d..77def6169f50 100644
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -54,9 +54,9 @@ static struct gpiod_lookup_table avila_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+index 270b09d0d205..8751cc273ce0 100644
+--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
++++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+@@ -73,9 +73,9 @@ static struct gpiod_lookup_table dsmg600_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
+index 73c72eaeb034..033f79b35d51 100644
+--- a/arch/arm/mach-ixp4xx/fsg-setup.c
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -59,9 +59,9 @@ static struct gpiod_lookup_table fsg_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+index 917af44c5780..b168e2fbdbeb 100644
+--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+@@ -127,9 +127,9 @@ static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index 6c57b74cd703..216a11b0e9b2 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -105,9 +105,9 @@ static struct gpiod_lookup_table nas100d_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index 3bc4c69b8479..91da63a7d7b5 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -73,9 +73,9 @@ static struct gpiod_lookup_table nslu2_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SDA_PIN,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SCL_PIN,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
+index f034724e01e1..937eb1d47e7b 100644
+--- a/arch/arm/mach-ks8695/board-acs5k.c
++++ b/arch/arm/mach-ks8695/board-acs5k.c
+@@ -41,8 +41,10 @@
+ static struct gpiod_lookup_table acs5k_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+-		GPIO_LOOKUP_IDX("KS8695", 4, NULL, 0, GPIO_ACTIVE_HIGH),
+-		GPIO_LOOKUP_IDX("KS8695", 5, NULL, 1, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("KS8695", 4, NULL, 0,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
++		GPIO_LOOKUP_IDX("KS8695", 5, NULL, 1,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
+index 94f75632c007..5877e547cecd 100644
+--- a/arch/arm/mach-pxa/palmz72.c
++++ b/arch/arm/mach-pxa/palmz72.c
+@@ -324,8 +324,10 @@ static struct soc_camera_link palmz72_iclink = {
+ static struct gpiod_lookup_table palmz72_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+-		GPIO_LOOKUP_IDX("gpio-pxa", 118, NULL, 0, GPIO_ACTIVE_HIGH),
+-		GPIO_LOOKUP_IDX("gpio-pxa", 117, NULL, 1, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio-pxa", 118, NULL, 0,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
++		GPIO_LOOKUP_IDX("gpio-pxa", 117, NULL, 1,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
+index a680742bee2b..4185e7ff073f 100644
+--- a/arch/arm/mach-pxa/viper.c
++++ b/arch/arm/mach-pxa/viper.c
+@@ -463,9 +463,9 @@ static struct gpiod_lookup_table viper_i2c_gpiod_table = {
+ 	.dev_id		= "i2c-gpio",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SDA_GPIO,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SCL_GPIO,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+@@ -792,9 +792,9 @@ struct gpiod_lookup_table viper_tpm_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SDA_GPIO,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SCL_GPIO,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
+index 10c7ea426e5b..9db483a42826 100644
+--- a/arch/arm/mach-sa1100/simpad.c
++++ b/arch/arm/mach-sa1100/simpad.c
+@@ -328,8 +328,10 @@ static struct platform_device simpad_gpio_leds = {
+ static struct gpiod_lookup_table simpad_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+-		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO21, NULL, 0, GPIO_ACTIVE_HIGH),
+-		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO25, NULL, 1, GPIO_ACTIVE_HIGH),
++		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO21, NULL, 0,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
++		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO25, NULL, 1,
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
+index d801ca5ca6c4..fab69c736515 100644
+--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
++++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
+@@ -367,9 +367,9 @@ static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
+index 463a72358b0e..d64d270e9e62 100644
+--- a/arch/blackfin/mach-bf533/boards/ezkit.c
++++ b/arch/blackfin/mach-bf533/boards/ezkit.c
+@@ -395,9 +395,9 @@ static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
+index d2479359adb7..27cbf2fa2c62 100644
+--- a/arch/blackfin/mach-bf533/boards/stamp.c
++++ b/arch/blackfin/mach-bf533/boards/stamp.c
+@@ -517,9 +517,9 @@ static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
+index 72f757ebaa84..acc5363f60c6 100644
+--- a/arch/blackfin/mach-bf561/boards/ezkit.c
++++ b/arch/blackfin/mach-bf561/boards/ezkit.c
+@@ -384,9 +384,9 @@ static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
+-				GPIO_ACTIVE_HIGH),
++				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
+index daebc36e5ecb..328d697e72b4 100644
+--- a/arch/mips/alchemy/board-gpr.c
++++ b/arch/mips/alchemy/board-gpr.c
+@@ -235,6 +235,10 @@ static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
+ };
+ 
+ static struct i2c_gpio_platform_data gpr_i2c_data = {
++	/*
++	 * The open drain mode is hardwired somewhere or an electrical
++	 * property of the alchemy GPIO controller.
++	 */
+ 	.sda_is_open_drain	= 1,
+ 	.scl_is_open_drain	= 1,
+ 	.udelay			= 2,		/* ~100 kHz */
+diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
+index a95409063847..6b2c6f3baefa 100644
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -37,9 +37,9 @@ static struct gpiod_lookup_table pb44_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SDA,
+-				NULL, 0, GPIO_ACTIVE_HIGH),
++				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SCL,
+-				NULL, 1, GPIO_ACTIVE_HIGH),
++				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+ 
+diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
+index d67bbb153af4..b4063b145d29 100644
+--- a/drivers/mfd/sm501.c
++++ b/drivers/mfd/sm501.c
+@@ -1153,7 +1153,7 @@ static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
+ 	lookup->table[0].chip_hwnum = iic->pin_sda % 32;
+ 	lookup->table[0].con_id = NULL;
+ 	lookup->table[0].idx = 0;
+-	lookup->table[0].flags = GPIO_ACTIVE_HIGH;
++	lookup->table[0].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
+ 	if (iic->pin_scl < 32)
+ 		lookup->table[1].chip_label = "SM501-LOW";
+ 	else
+@@ -1161,7 +1161,7 @@ static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
+ 	lookup->table[1].chip_hwnum = iic->pin_scl % 32;
+ 	lookup->table[1].con_id = NULL;
+ 	lookup->table[1].idx = 1;
+-	lookup->table[1].flags = GPIO_ACTIVE_HIGH;
++	lookup->table[1].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
+ 	gpiod_add_lookup_table(lookup);
+ 
+ 	icd = dev_get_platdata(&pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0397-i2c-gpio-Local-vars-in-probe.patch b/patches/0397-i2c-gpio-Local-vars-in-probe.patch
new file mode 100644
index 00000000000000..72095e5e9f23b3
--- /dev/null
+++ b/patches/0397-i2c-gpio-Local-vars-in-probe.patch
@@ -0,0 +1,106 @@
+From 3eee2e832d3ec882cfcf5f06b161a462c1b9d8e3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 23:15:35 +0200
+Subject: [PATCH 0397/1795] i2c: gpio: Local vars in probe
+
+By creating local variables for *dev and *np, the code become
+much easier to read, in my opinion.
+
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit b9ab0517efc0111b516878ab872e2b3dd7bb40a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-gpio.c | 27 ++++++++++++++-------------
+ 1 file changed, 14 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index 97b9c29e9429..a702e493275c 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -88,10 +88,12 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	struct i2c_gpio_platform_data *pdata;
+ 	struct i2c_algo_bit_data *bit_data;
+ 	struct i2c_adapter *adap;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
+ 	enum gpiod_flags gflags;
+ 	int ret;
+ 
+-	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+@@ -99,16 +101,15 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	bit_data = &priv->bit_data;
+ 	pdata = &priv->pdata;
+ 
+-	if (pdev->dev.of_node) {
+-		of_i2c_gpio_get_props(pdev->dev.of_node, pdata);
++	if (np) {
++		of_i2c_gpio_get_props(np, pdata);
+ 	} else {
+ 		/*
+ 		 * If all platform data settings are zero it is OK
+ 		 * to not provide any platform data from the board.
+ 		 */
+-		if (dev_get_platdata(&pdev->dev))
+-			memcpy(pdata, dev_get_platdata(&pdev->dev),
+-			       sizeof(*pdata));
++		if (dev_get_platdata(dev))
++			memcpy(pdata, dev_get_platdata(dev), sizeof(*pdata));
+ 	}
+ 
+ 	/*
+@@ -123,7 +124,7 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 		gflags = GPIOD_OUT_HIGH;
+ 	else
+ 		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
+-	priv->sda = devm_gpiod_get_index(&pdev->dev, NULL, 0, gflags);
++	priv->sda = devm_gpiod_get_index(dev, NULL, 0, gflags);
+ 	if (IS_ERR(priv->sda)) {
+ 		ret = PTR_ERR(priv->sda);
+ 		/* FIXME: hack in the old code, is this really necessary? */
+@@ -142,7 +143,7 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 		gflags = GPIOD_OUT_LOW;
+ 	else
+ 		gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
+-	priv->scl = devm_gpiod_get_index(&pdev->dev, NULL, 1, gflags);
++	priv->scl = devm_gpiod_get_index(dev, NULL, 1, gflags);
+ 	if (IS_ERR(priv->scl)) {
+ 		ret = PTR_ERR(priv->scl);
+ 		/* FIXME: hack in the old code, is this really necessary? */
+@@ -173,15 +174,15 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	bit_data->data = priv;
+ 
+ 	adap->owner = THIS_MODULE;
+-	if (pdev->dev.of_node)
+-		strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
++	if (np)
++		strlcpy(adap->name, dev_name(dev), sizeof(adap->name));
+ 	else
+ 		snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id);
+ 
+ 	adap->algo_data = bit_data;
+ 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+-	adap->dev.parent = &pdev->dev;
+-	adap->dev.of_node = pdev->dev.of_node;
++	adap->dev.parent = dev;
++	adap->dev.of_node = np;
+ 
+ 	adap->nr = pdev->id;
+ 	ret = i2c_bit_add_numbered_bus(adap);
+@@ -195,7 +196,7 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	 * get accessors to get the actual name of the GPIO line,
+ 	 * from the descriptor, then provide that instead.
+ 	 */
+-	dev_info(&pdev->dev, "using lines %u (SDA) and %u (SCL%s)\n",
++	dev_info(dev, "using lines %u (SDA) and %u (SCL%s)\n",
+ 		 desc_to_gpio(priv->sda), desc_to_gpio(priv->scl),
+ 		 pdata->scl_is_output_only
+ 		 ? ", no clock stretching" : "");
+-- 
+2.19.0
+
diff --git a/patches/0398-dt-bindings-i2c-i2c-gpio-Add-support-for-named-gpios.patch b/patches/0398-dt-bindings-i2c-i2c-gpio-Add-support-for-named-gpios.patch
new file mode 100644
index 00000000000000..b5471a63b46280
--- /dev/null
+++ b/patches/0398-dt-bindings-i2c-i2c-gpio-Add-support-for-named-gpios.patch
@@ -0,0 +1,89 @@
+From b606d8c3f34946f044c550d0e179577c2a4c98d8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 24 Aug 2017 09:21:12 +0200
+Subject: [PATCH 0398/1795] dt-bindings: i2c: i2c-gpio: Add support for named
+ gpios
+
+The current i2c-gpio DT bindings use a single unnamed "gpios" property
+to refer to the SDA and SCL signal lines by index.  This is error-prone
+for the casual DT writer and reviewer, as one has to look up the order
+in the DT bindings.
+
+Fix this by amending the DT bindings to use two separate named gpios
+properties, and deprecate the old unnamed variant.
+
+Take this opportunity to clearly deprecate the "i2c-gpio,sda-open-drain"
+and "i2c-gpio,scl-open-drain" flags as well. The commit describes
+in detail what these flags actually mean, and why they should not be
+used in new device trees.
+
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[Augmented to what I and Rob would like]
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+
+(cherry picked from commit 7d29f509d2cfd807b2fccc643ac1f7066b9b1949)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/i2c/i2c-gpio.txt      | 32 +++++++++++++------
+ 1 file changed, 23 insertions(+), 9 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
+index 4f8ec947c6bd..38a05562d1d2 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
+@@ -2,25 +2,39 @@ Device-Tree bindings for i2c gpio driver
+ 
+ Required properties:
+ 	- compatible = "i2c-gpio";
+-	- gpios: sda and scl gpio
+-
++	- sda-gpios: gpio used for the sda signal, this should be flagged as
++	  active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)
++	  from <dt-bindings/gpio/gpio.h> since the signal is by definition
++	  open drain.
++	- scl-gpios: gpio used for the scl signal, this should be flagged as
++	  active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)
++	  from <dt-bindings/gpio/gpio.h> since the signal is by definition
++	  open drain.
+ 
+ Optional properties:
+-	- i2c-gpio,sda-open-drain: sda as open drain
+-	- i2c-gpio,scl-open-drain: scl as open drain
+ 	- i2c-gpio,scl-output-only: scl as output only
+ 	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
+ 	- i2c-gpio,timeout-ms: timeout to get data
+ 
++Deprecated properties, do not use in new device tree sources:
++	- gpios: sda and scl gpio, alternative for {sda,scl}-gpios
++	- i2c-gpio,sda-open-drain: this means that something outside of our
++	  control has put the GPIO line used for SDA into open drain mode, and
++	  that something is not the GPIO chip. It is essentially an
++	  inconsistency flag.
++	- i2c-gpio,scl-open-drain: this means that something outside of our
++	  control has put the GPIO line used for SCL into open drain mode, and
++	  that something is not the GPIO chip. It is essentially an
++	  inconsistency flag.
++
+ Example nodes:
+ 
++#include <dt-bindings/gpio/gpio.h>
++
+ i2c@0 {
+ 	compatible = "i2c-gpio";
+-	gpios = <&pioA 23 0 /* sda */
+-		 &pioA 24 0 /* scl */
+-		>;
+-	i2c-gpio,sda-open-drain;
+-	i2c-gpio,scl-open-drain;
++	sda-gpios = <&pioA 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++	scl-gpios = <&pioA 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ 	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/0399-i2c-gpio-Add-support-for-named-gpios-in-DT.patch b/patches/0399-i2c-gpio-Add-support-for-named-gpios-in-DT.patch
new file mode 100644
index 00000000000000..f6cf5eacda6e55
--- /dev/null
+++ b/patches/0399-i2c-gpio-Add-support-for-named-gpios-in-DT.patch
@@ -0,0 +1,114 @@
+From 1c0061a023205bf2ced3d02a846afa153594ad1e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 16 Sep 2017 23:56:49 +0200
+Subject: [PATCH 0399/1795] i2c: gpio: Add support for named gpios in DT
+
+This adds support for using the "sda" and "scl" GPIOs in
+device tree instead of anonymously using index 0 and 1 of
+the "gpios" property.
+
+We add a helper function to retrieve the GPIO descriptors
+and some explicit error handling since the probe may have
+to be deferred. At least this happened to me when moving
+to using named "sda" and "scl" lines (all of a sudden this
+started to probe before the GPIO driver) so we need to
+gracefully defer probe when we ge -ENOENT in the error
+pointer.
+
+Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 05c74778858d7d9907d607172fcc9646b70b6364)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-gpio.c | 59 +++++++++++++++++++++++++----------
+ 1 file changed, 43 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index a702e493275c..d80ea6ce91bb 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -82,6 +82,42 @@ static void of_i2c_gpio_get_props(struct device_node *np,
+ 		of_property_read_bool(np, "i2c-gpio,scl-output-only");
+ }
+ 
++static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
++					   const char *con_id,
++					   unsigned int index,
++					   enum gpiod_flags gflags)
++{
++	struct gpio_desc *retdesc;
++	int ret;
++
++	retdesc = devm_gpiod_get(dev, con_id, gflags);
++	if (!IS_ERR(retdesc)) {
++		dev_dbg(dev, "got GPIO from name %s\n", con_id);
++		return retdesc;
++	}
++
++	retdesc = devm_gpiod_get_index(dev, NULL, index, gflags);
++	if (!IS_ERR(retdesc)) {
++		dev_dbg(dev, "got GPIO from index %u\n", index);
++		return retdesc;
++	}
++
++	ret = PTR_ERR(retdesc);
++
++	/* FIXME: hack in the old code, is this really necessary? */
++	if (ret == -EINVAL)
++		retdesc = ERR_PTR(-EPROBE_DEFER);
++
++	/* This happens if the GPIO driver is not yet probed, let's defer */
++	if (ret == -ENOENT)
++		retdesc = ERR_PTR(-EPROBE_DEFER);
++
++	if (ret != -EPROBE_DEFER)
++		dev_err(dev, "error trying to get descriptor: %d\n", ret);
++
++	return retdesc;
++}
++
+ static int i2c_gpio_probe(struct platform_device *pdev)
+ {
+ 	struct i2c_gpio_private_data *priv;
+@@ -124,14 +160,10 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 		gflags = GPIOD_OUT_HIGH;
+ 	else
+ 		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
+-	priv->sda = devm_gpiod_get_index(dev, NULL, 0, gflags);
+-	if (IS_ERR(priv->sda)) {
+-		ret = PTR_ERR(priv->sda);
+-		/* FIXME: hack in the old code, is this really necessary? */
+-		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;
+-		return ret;
+-	}
++	priv->sda = i2c_gpio_get_desc(dev, "sda", 0, gflags);
++	if (IS_ERR(priv->sda))
++		return PTR_ERR(priv->sda);
++
+ 	/*
+ 	 * If the SCL line is marked from platform data or device tree as
+ 	 * "open drain" it means something outside of our control is making
+@@ -143,14 +175,9 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 		gflags = GPIOD_OUT_LOW;
+ 	else
+ 		gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
+-	priv->scl = devm_gpiod_get_index(dev, NULL, 1, gflags);
+-	if (IS_ERR(priv->scl)) {
+-		ret = PTR_ERR(priv->scl);
+-		/* FIXME: hack in the old code, is this really necessary? */
+-		if (ret == -EINVAL)
+-			ret = -EPROBE_DEFER;
+-		return ret;
+-	}
++	priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags);
++	if (IS_ERR(priv->scl))
++		return PTR_ERR(priv->scl);
+ 
+ 	bit_data->setsda = i2c_gpio_setsda_val;
+ 	bit_data->setscl = i2c_gpio_setscl_val;
+-- 
+2.19.0
+
diff --git a/patches/0400-ARM-sa1100-simpad-Correct-I2C-GPIO-offsets.patch b/patches/0400-ARM-sa1100-simpad-Correct-I2C-GPIO-offsets.patch
new file mode 100644
index 00000000000000..7a9ee0e84469cd
--- /dev/null
+++ b/patches/0400-ARM-sa1100-simpad-Correct-I2C-GPIO-offsets.patch
@@ -0,0 +1,108 @@
+From 3d747c153d9a53da489ee304a7226323870f2a0e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Tue, 7 Nov 2017 21:18:57 +0100
+Subject: [PATCH 0400/1795] ARM: sa1100: simpad: Correct I2C GPIO offsets
+
+Arnd reported the following build bug bug:
+
+In file included from arch/arm/mach-sa1100/simpad.c:20:0:
+arch/arm/mach-sa1100/include/mach/SA-1100.h:1118:18: error: large
+integer implicitly truncated to unsigned type [-Werror=overflow]
+                      (0x00000001 << (Nb))
+                      ^
+include/linux/gpio/machine.h:56:16: note: in definition of macro
+'GPIO_LOOKUP_IDX'
+.chip_hwnum = _chip_hwnum,
+              ^~~~~~~~~~~
+arch/arm/mach-sa1100/include/mach/SA-1100.h:1140:21: note: in
+expansion of macro 'GPIO_GPIO'
+                    ^~~~~~~~~
+arch/arm/mach-sa1100/simpad.c:331:27: note: in expansion of
+macro 'GPIO_GPIO21'
+  GPIO_LOOKUP_IDX("gpio", GPIO_GPIO21, NULL, 0,
+
+This is what happened:
+
+commit b2e63555592f81331c8da3afaa607d8cf83e8138
+"i2c: gpio: Convert to use descriptors"
+commit 4d0ce62c0a02e41a65cfdcfe277f5be430edc371
+"i2c: gpio: Augment all boardfiles to use open drain"
+together uncovered an old bug in the Simpad board
+file: as theGPIO_LOOKUP_IDX() encodes GPIO offsets
+on gpiochips in an u16 (see <linux/gpio/machine.h>)
+these GPIO "numbers" does not fit, since in
+arch/arm/mach-sa1100/include/mach/SA-1100.h it is
+defined as:
+
+  #define GPIO_GPIO(Nb) (0x00000001 << (Nb))
+  (...)
+  #define GPIO_GPIO21 GPIO_GPIO(21) /* GPIO [21] */
+
+This is however provably wrong, since the i2c-gpio
+driver uses proper GPIO numbers, albeit earlier from
+the global number space, whereas this GPIO_GPIO21
+is the local line offset in the GPIO register, which
+is used in other code but certainly not in the
+gpiolib GPIO driver in drivers/gpio/gpio-sa1100.c, which
+has code like this:
+
+static void sa1100_gpio_set(struct gpio_chip *chip,
+                            unsigned offset, int value)
+{
+    int reg = value ? R_GPSR : R_GPCR;
+
+    writel_relaxed(BIT(offset),
+        sa1100_gpio_chip(chip)->membase + reg);
+}
+
+So far everything however compiled fine as an unsigned
+int was used to pass the GPIO numbers in
+struct i2c_gpio_platform_data. We can trace the actual error
+back to
+
+commit dbd406f9d0a1d33a1303eb75cbe3f9435513d339
+"ARM: 7025/1: simpad: add GPIO based device definitions."
+This added the i2c_gpio with the wrong offsets.
+
+This commit was before the SA1100 was converted to use
+the gpiolib, but as can be seen from the contemporary
+gpio.c in mach-sa1100, it was already using:
+
+static int sa1100_gpio_get(struct gpio_chip *chip,
+                           unsigned offset)
+{
+        return GPLR & GPIO_GPIO(offset);
+}
+
+And GPIO_GPIO() is essentially the BIT() macro.
+
+Reported-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit d82e99a6f9b38cb1a044b4cd979bd49fd3f67cd2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-sa1100/simpad.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
+index 9db483a42826..7d4feb8a49ac 100644
+--- a/arch/arm/mach-sa1100/simpad.c
++++ b/arch/arm/mach-sa1100/simpad.c
+@@ -328,9 +328,9 @@ static struct platform_device simpad_gpio_leds = {
+ static struct gpiod_lookup_table simpad_i2c_gpiod_table = {
+ 	.dev_id = "i2c-gpio",
+ 	.table = {
+-		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO21, NULL, 0,
++		GPIO_LOOKUP_IDX("gpio", 21, NULL, 0,
+ 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+-		GPIO_LOOKUP_IDX("gpio", GPIO_GPIO25, NULL, 1,
++		GPIO_LOOKUP_IDX("gpio", 25, NULL, 1,
+ 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+ 	},
+ };
+-- 
+2.19.0
+
diff --git a/patches/0401-lib-dma-debug.c-fix-incorrect-pfn-calculation.patch b/patches/0401-lib-dma-debug.c-fix-incorrect-pfn-calculation.patch
new file mode 100644
index 00000000000000..0a5eb97275e9a8
--- /dev/null
+++ b/patches/0401-lib-dma-debug.c-fix-incorrect-pfn-calculation.patch
@@ -0,0 +1,101 @@
+From cc6073c3c612928080b9d2a8cf9cac97d42d2136 Mon Sep 17 00:00:00 2001
+From: Miles Chen <miles.chen@mediatek.com>
+Date: Fri, 17 Nov 2017 15:26:19 -0800
+Subject: [PATCH 0401/1795] lib/dma-debug.c: fix incorrect pfn calculation
+
+dma-debug reports the following warning:
+
+  WARNING: CPU: 3 PID: 298 at kernel-4.4/lib/dma-debug.c:604
+  debug _dma_assert_idle+0x1a8/0x230()
+  DMA-API: cpu touching an active dma mapped cacheline [cln=0x00000882300]
+  CPU: 3 PID: 298 Comm: vold Tainted: G        W  O    4.4.22+ #1
+  Hardware name: MT6739 (DT)
+  Call trace:
+    debug_dma_assert_idle+0x1a8/0x230
+    wp_page_copy.isra.96+0x118/0x520
+    do_wp_page+0x4fc/0x534
+    handle_mm_fault+0xd4c/0x1310
+    do_page_fault+0x1c8/0x394
+    do_mem_abort+0x50/0xec
+
+I found that debug_dma_alloc_coherent() and debug_dma_free_coherent()
+assume that dma_alloc_coherent() always returns a linear address.
+
+However it's possible that dma_alloc_coherent() returns a non-linear
+address.  In this case, page_to_pfn(virt_to_page(virt)) will return an
+incorrect pfn.  If the pfn is valid and mapped as a COW page, we will
+hit the warning when doing wp_page_copy().
+
+Fix this by calculating pfn for linear and non-linear addresses.
+
+[miles.chen@mediatek.com: v4]
+  Link: http://lkml.kernel.org/r/1510872972-23919-1-git-send-email-miles.chen@mediatek.com
+Link: http://lkml.kernel.org/r/1506484087-1177-1-git-send-email-miles.chen@mediatek.com
+Signed-off-by: Miles Chen <miles.chen@mediatek.com>
+Reviewed-by: Robin Murphy <robin.murphy@arm.com>
+Cc: Christoph Hellwig <hch@lst.de>
+Cc: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+
+(cherry picked from commit 3aaabbf1c39effa2ac0c11103ed07ef03b0a0d89)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ lib/dma-debug.c | 20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/lib/dma-debug.c b/lib/dma-debug.c
+index ea4cc3dde4f1..1b34d210452c 100644
+--- a/lib/dma-debug.c
++++ b/lib/dma-debug.c
+@@ -1495,14 +1495,22 @@ void debug_dma_alloc_coherent(struct device *dev, size_t size,
+ 	if (!entry)
+ 		return;
+ 
++	/* handle vmalloc and linear addresses */
++	if (!is_vmalloc_addr(virt) && !virt_to_page(virt))
++		return;
++
+ 	entry->type      = dma_debug_coherent;
+ 	entry->dev       = dev;
+-	entry->pfn	 = page_to_pfn(virt_to_page(virt));
+ 	entry->offset	 = offset_in_page(virt);
+ 	entry->size      = size;
+ 	entry->dev_addr  = dma_addr;
+ 	entry->direction = DMA_BIDIRECTIONAL;
+ 
++	if (is_vmalloc_addr(virt))
++		entry->pfn = vmalloc_to_pfn(virt);
++	else
++		entry->pfn = page_to_pfn(virt_to_page(virt));
++
+ 	add_dma_entry(entry);
+ }
+ EXPORT_SYMBOL(debug_dma_alloc_coherent);
+@@ -1513,13 +1521,21 @@ void debug_dma_free_coherent(struct device *dev, size_t size,
+ 	struct dma_debug_entry ref = {
+ 		.type           = dma_debug_coherent,
+ 		.dev            = dev,
+-		.pfn		= page_to_pfn(virt_to_page(virt)),
+ 		.offset		= offset_in_page(virt),
+ 		.dev_addr       = addr,
+ 		.size           = size,
+ 		.direction      = DMA_BIDIRECTIONAL,
+ 	};
+ 
++	/* handle vmalloc and linear addresses */
++	if (!is_vmalloc_addr(virt) && !virt_to_page(virt))
++		return;
++
++	if (is_vmalloc_addr(virt))
++		ref.pfn = vmalloc_to_pfn(virt);
++	else
++		ref.pfn = page_to_pfn(virt_to_page(virt));
++
+ 	if (unlikely(dma_debug_disabled()))
+ 		return;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0402-include-linux-slab.h-add-kmalloc_array_node-and-kcal.patch b/patches/0402-include-linux-slab.h-add-kmalloc_array_node-and-kcal.patch
new file mode 100644
index 00000000000000..64e368ba7d47e6
--- /dev/null
+++ b/patches/0402-include-linux-slab.h-add-kmalloc_array_node-and-kcal.patch
@@ -0,0 +1,82 @@
+From cd32c0ac9de45f5317ca81b77aed8021f85b8dd7 Mon Sep 17 00:00:00 2001
+From: Johannes Thumshirn <jthumshirn@suse.de>
+Date: Wed, 15 Nov 2017 17:32:29 -0800
+Subject: [PATCH 0402/1795] include/linux/slab.h: add kmalloc_array_node() and
+ kcalloc_node()
+
+Patch series "Add kmalloc_array_node() and kcalloc_node()".
+
+Our current memeory allocation routines suffer form an API imbalance,
+for one we have kmalloc_array() and kcalloc() which check for overflows
+in size multiplication and we have kmalloc_node() and kzalloc_node()
+which allow for memory allocation on a certain NUMA node but don't check
+for eventual overflows.
+
+This patch (of 6):
+
+We have kmalloc_array() and kcalloc() wrappers on top of kmalloc() which
+ensure us overflow free multiplication for the size of a memory
+allocation but these implementations are not NUMA-aware.
+
+Likewise we have kmalloc_node() which is a NUMA-aware version of
+kmalloc() but the implementation is not aware of any possible overflows
+in eventual size calculations.
+
+Introduce a combination of the two above cases to have a NUMA-node aware
+version of kmalloc_array() and kcalloc().
+
+Link: http://lkml.kernel.org/r/20170927082038.3782-2-jthumshirn@suse.de
+Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de>
+Acked-by: Vlastimil Babka <vbabka@suse.cz>
+Cc: Christoph Hellwig <hch@lst.de>
+Cc: Christoph Lameter <cl@linux.com>
+Cc: Damien Le Moal <damien.lemoal@wdc.com>
+Cc: David Rientjes <rientjes@google.com>
+Cc: "David S. Miller" <davem@davemloft.net>
+Cc: Doug Ledford <dledford@redhat.com>
+Cc: Hal Rosenstock <hal.rosenstock@gmail.com>
+Cc: Jens Axboe <axboe@kernel.dk>
+Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com>
+Cc: Mike Marciniszyn <infinipath@intel.com>
+Cc: Pekka Enberg <penberg@kernel.org>
+Cc: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+Cc: Sean Hefty <sean.hefty@intel.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+(cherry picked from commit 5799b255c491d853b73fb9e0e1760210315d06cd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/slab.h | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/include/linux/slab.h b/include/linux/slab.h
+index ae5ed6492d54..28687c296ece 100644
+--- a/include/linux/slab.h
++++ b/include/linux/slab.h
+@@ -630,6 +630,22 @@ extern void *__kmalloc_track_caller(size_t, gfp_t, unsigned long);
+ #define kmalloc_track_caller(size, flags) \
+ 	__kmalloc_track_caller(size, flags, _RET_IP_)
+ 
++static inline void *kmalloc_array_node(size_t n, size_t size, gfp_t flags,
++				       int node)
++{
++	if (size != 0 && n > SIZE_MAX / size)
++		return NULL;
++	if (__builtin_constant_p(n) && __builtin_constant_p(size))
++		return kmalloc_node(n * size, flags, node);
++	return __kmalloc_node(n * size, flags, node);
++}
++
++static inline void *kcalloc_node(size_t n, size_t size, gfp_t flags, int node)
++{
++	return kmalloc_array_node(n, size, flags | __GFP_ZERO, node);
++}
++
++
+ #ifdef CONFIG_NUMA
+ extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, unsigned long);
+ #define kmalloc_node_track_caller(size, flags, node) \
+-- 
+2.19.0
+
diff --git a/patches/0403-gpio-pca953x-fix-vendor-prefix-for-PCA9654.patch b/patches/0403-gpio-pca953x-fix-vendor-prefix-for-PCA9654.patch
new file mode 100644
index 00000000000000..40c6e9b7c8fda0
--- /dev/null
+++ b/patches/0403-gpio-pca953x-fix-vendor-prefix-for-PCA9654.patch
@@ -0,0 +1,53 @@
+From 3318d957d96d8b67fbcdda6b09353394a0f9e8c9 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 16 Nov 2017 23:18:32 +0300
+Subject: [PATCH 0403/1795] gpio: pca953x: fix vendor prefix for PCA9654
+
+Despite commit 55020c8056a8 ("of: Add vendor prefix for ON Semiconductor
+Corp.") was made long ago, the latter commit 9f49f6dd0473 ("gpio: pca953x:
+add onsemi,pca9654 id") made use of another, undocumented vendor prefix.
+Since such prefix doesn't seem to be used in any device trees, I think we
+can just fix the "compatible" string in the driver and the bindings and be
+done with that...
+
+Fixes: 9f49f6dd0473 ("gpio: pca953x: add onsemi,pca9654 id")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 8a64e557f399090f5d1917b2f32a065da2b12be1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 2 +-
+ drivers/gpio/gpio-pca953x.c                             | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+index 7f57271df2bc..0d0158728f89 100644
+--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+@@ -27,7 +27,7 @@ Required properties:
+ 	ti,tca6424
+ 	ti,tca9539
+ 	ti,tca9554
+-	onsemi,pca9654
++	onnn,pca9654
+ 	exar,xra1202
+ 
+ Optional properties:
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index 1b9dbf691ae7..c4795167119b 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -947,7 +947,7 @@ static const struct of_device_id pca953x_dt_ids[] = {
+ 	{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
+ 	{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+ 
+-	{ .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
++	{ .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
+ 
+ 	{ .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
+ 	{ }
+-- 
+2.19.0
+
diff --git a/patches/0404-i2c-generic-recovery-check-SCL-before-SDA.patch b/patches/0404-i2c-generic-recovery-check-SCL-before-SDA.patch
new file mode 100644
index 00000000000000..a1f7964631478c
--- /dev/null
+++ b/patches/0404-i2c-generic-recovery-check-SCL-before-SDA.patch
@@ -0,0 +1,60 @@
+From 6d547f3d524fda1f98d3805045bce8825217a2cb Mon Sep 17 00:00:00 2001
+From: Claudio Foellmi <claudio.foellmi@ergon.ch>
+Date: Thu, 5 Oct 2017 14:44:14 +0200
+Subject: [PATCH 0404/1795] i2c: generic recovery: check SCL before SDA
+
+Move the check for a stuck SCL before the check for a high SDA.
+This prevent false positives in the specific case that SDA is fine
+and SCL is stuck, which previously returned 0.
+
+Also check SDA again after the loop, if we can.
+Together, these changes should lead to a lot more failed
+recoveries being caught and returning error codes.
+
+Signed-off-by: Claudio Foellmi <claudio.foellmi@ergon.ch>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 1f35b8653687b9c08c8d58489c1b5cb9cf961c17)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 7b961c9c62ef..6334f8837371 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -205,9 +205,6 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 	 */
+ 	while (i++ < RECOVERY_CLK_CNT * 2) {
+ 		if (val) {
+-			/* Break if SDA is high */
+-			if (bri->get_sda && bri->get_sda(adap))
+-					break;
+ 			/* SCL shouldn't be low here */
+ 			if (!bri->get_scl(adap)) {
+ 				dev_err(&adap->dev,
+@@ -215,6 +212,9 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 				ret = -EBUSY;
+ 				break;
+ 			}
++			/* Break if SDA is high */
++			if (bri->get_sda && bri->get_sda(adap))
++				break;
+ 		}
+ 
+ 		val = !val;
+@@ -222,6 +222,10 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 		ndelay(RECOVERY_NDELAY);
+ 	}
+ 
++	/* check if recovery actually succeeded */
++	if (bri->get_sda && !bri->get_sda(adap))
++		ret = -EBUSY;
++
+ 	if (bri->unprepare_recovery)
+ 		bri->unprepare_recovery(adap);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0405-soc-mediatek-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch b/patches/0405-soc-mediatek-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
new file mode 100644
index 00000000000000..5c950daba61edc
--- /dev/null
+++ b/patches/0405-soc-mediatek-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
@@ -0,0 +1,54 @@
+From 5990b15a0ea2af0b547f888eb5bc020e251a86d3 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 7 Nov 2017 13:48:13 +0100
+Subject: [PATCH 0405/1795] soc: mediatek: Use GENPD_FLAG_ACTIVE_WAKEUP
+
+Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to
+remove the driver's own flag-based callback.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit 7534d181a8e60dff0c2a8e12aa6515a87a25b47d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/mediatek/mtk-scpsys.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
+index fb2a8b1e7979..102f1c6277a9 100644
+--- a/drivers/soc/mediatek/mtk-scpsys.c
++++ b/drivers/soc/mediatek/mtk-scpsys.c
+@@ -361,17 +361,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
+ 	return ret;
+ }
+ 
+-static bool scpsys_active_wakeup(struct device *dev)
+-{
+-	struct generic_pm_domain *genpd;
+-	struct scp_domain *scpd;
+-
+-	genpd = pd_to_genpd(dev->pm_domain);
+-	scpd = container_of(genpd, struct scp_domain, genpd);
+-
+-	return scpd->data->active_wakeup;
+-}
+-
+ static void init_clks(struct platform_device *pdev, struct clk **clk)
+ {
+ 	int i;
+@@ -466,7 +455,8 @@ static struct scp *init_scp(struct platform_device *pdev,
+ 		genpd->name = data->name;
+ 		genpd->power_off = scpsys_power_off;
+ 		genpd->power_on = scpsys_power_on;
+-		genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
++		if (scpd->data->active_wakeup)
++			genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+ 	}
+ 
+ 	return scp;
+-- 
+2.19.0
+
diff --git a/patches/0406-soc-rockchip-power-domain-Use-GENPD_FLAG_ACTIVE_WAKE.patch b/patches/0406-soc-rockchip-power-domain-Use-GENPD_FLAG_ACTIVE_WAKE.patch
new file mode 100644
index 00000000000000..f50128fdd9fe94
--- /dev/null
+++ b/patches/0406-soc-rockchip-power-domain-Use-GENPD_FLAG_ACTIVE_WAKE.patch
@@ -0,0 +1,56 @@
+From 31c03bb4aba613e1f55e2a979e13f4c6afcfe368 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 7 Nov 2017 13:48:14 +0100
+Subject: [PATCH 0406/1795] soc: rockchip: power-domain: Use
+ GENPD_FLAG_ACTIVE_WAKEUP
+
+Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to
+remove the driver's own flag-based callback.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit 89c7aea915c0c9820191a533e1f304e234074b2d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/rockchip/pm_domains.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index ba009bb9d82b..e89188da1a9d 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -358,17 +358,6 @@ static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
+ 	pm_clk_destroy(dev);
+ }
+ 
+-static bool rockchip_active_wakeup(struct device *dev)
+-{
+-	struct generic_pm_domain *genpd;
+-	struct rockchip_pm_domain *pd;
+-
+-	genpd = pd_to_genpd(dev->pm_domain);
+-	pd = container_of(genpd, struct rockchip_pm_domain, genpd);
+-
+-	return pd->info->active_wakeup;
+-}
+-
+ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ 				      struct device_node *node)
+ {
+@@ -489,8 +478,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ 	pd->genpd.power_on = rockchip_pd_power_on;
+ 	pd->genpd.attach_dev = rockchip_pd_attach_dev;
+ 	pd->genpd.detach_dev = rockchip_pd_detach_dev;
+-	pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
+ 	pd->genpd.flags = GENPD_FLAG_PM_CLK;
++	if (pd_info->active_wakeup)
++		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+ 	pm_genpd_init(&pd->genpd, NULL, false);
+ 
+ 	pmu->genpd_data.domains[id] = &pd->genpd;
+-- 
+2.19.0
+
diff --git a/patches/0407-PM-Domains-Remove-gpd_dev_ops.active_wakeup-callback.patch b/patches/0407-PM-Domains-Remove-gpd_dev_ops.active_wakeup-callback.patch
new file mode 100644
index 00000000000000..d600ee7fbb1949
--- /dev/null
+++ b/patches/0407-PM-Domains-Remove-gpd_dev_ops.active_wakeup-callback.patch
@@ -0,0 +1,83 @@
+From de1b4d5b82804ef1f8f2eb74e25bc8004a6a7c67 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 7 Nov 2017 13:48:15 +0100
+Subject: [PATCH 0407/1795] PM / Domains: Remove gpd_dev_ops.active_wakeup()
+ callback
+
+There are no more users left of the gpd_dev_ops.active_wakeup()
+callback.  All have been converted to GENPD_FLAG_ACTIVE_WAKEUP.
+Hence remove the callback.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Kevin Hilman <khilman@baylibre.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit d0af45f1f6528949e05385976eb61c5ebd31854e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/base/power/domain.c | 14 +++-----------
+ include/linux/pm_domain.h   |  1 -
+ 2 files changed, 3 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
+index 5d63c34e0420..104f3d928b13 100644
+--- a/drivers/base/power/domain.c
++++ b/drivers/base/power/domain.c
+@@ -772,14 +772,6 @@ static bool pm_genpd_present(const struct generic_pm_domain *genpd)
+ 
+ #ifdef CONFIG_PM_SLEEP
+ 
+-static bool genpd_dev_active_wakeup(const struct generic_pm_domain *genpd,
+-				    struct device *dev)
+-{
+-	if (genpd_is_active_wakeup(genpd))
+-		return true;
+-	return GENPD_DEV_CALLBACK(genpd, bool, active_wakeup, dev);
+-}
+-
+ /**
+  * genpd_sync_power_off - Synchronously power off a PM domain and its masters.
+  * @genpd: PM domain to power off, if possible.
+@@ -884,7 +876,7 @@ static bool resume_needed(struct device *dev,
+ 	if (!device_can_wakeup(dev))
+ 		return false;
+ 
+-	active_wakeup = genpd_dev_active_wakeup(genpd, dev);
++	active_wakeup = genpd_is_active_wakeup(genpd);
+ 	return device_may_wakeup(dev) ? active_wakeup : !active_wakeup;
+ }
+ 
+@@ -954,7 +946,7 @@ static int genpd_finish_suspend(struct device *dev, bool poweroff)
+ 	if (IS_ERR(genpd))
+ 		return -EINVAL;
+ 
+-	if (dev->power.wakeup_path && genpd_dev_active_wakeup(genpd, dev))
++	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
+ 		return 0;
+ 
+ 	if (poweroff)
+@@ -1009,7 +1001,7 @@ static int pm_genpd_resume_noirq(struct device *dev)
+ 	if (IS_ERR(genpd))
+ 		return -EINVAL;
+ 
+-	if (dev->power.wakeup_path && genpd_dev_active_wakeup(genpd, dev))
++	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
+ 		return 0;
+ 
+ 	genpd_lock(genpd);
+diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
+index a6688efb29ee..fe23bf0bd985 100644
+--- a/include/linux/pm_domain.h
++++ b/include/linux/pm_domain.h
+@@ -36,7 +36,6 @@ struct dev_power_governor {
+ struct gpd_dev_ops {
+ 	int (*start)(struct device *dev);
+ 	int (*stop)(struct device *dev);
+-	bool (*active_wakeup)(struct device *dev);
+ };
+ 
+ struct genpd_power_state {
+-- 
+2.19.0
+
diff --git a/patches/0408-PM-runtime-Drop-children-check-from-__pm_runtime_set.patch b/patches/0408-PM-runtime-Drop-children-check-from-__pm_runtime_set.patch
new file mode 100644
index 00000000000000..f636e576eb9d03
--- /dev/null
+++ b/patches/0408-PM-runtime-Drop-children-check-from-__pm_runtime_set.patch
@@ -0,0 +1,100 @@
+From ebb50b76c08f058dfa56ba5a7bb314474a0a7754 Mon Sep 17 00:00:00 2001
+From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
+Date: Thu, 16 Nov 2017 22:51:22 +0100
+Subject: [PATCH 0408/1795] PM / runtime: Drop children check from
+ __pm_runtime_set_status()
+
+The check for "active" children in __pm_runtime_set_status(), when
+trying to set the parent device status to "suspended", doesn't
+really make sense, because in fact it is not invalid to set the
+status of a device with runtime PM disabled to "suspended" in any
+case.  It is invalid to enable runtime PM for a device with its
+status set to "suspended" while its child_count reference counter
+is nonzero, but the check in __pm_runtime_set_status() doesn't
+really cover that situation.
+
+For this reason, drop the children check from __pm_runtime_set_status()
+and add a check against child_count reference counters of "suspended"
+devices to pm_runtime_enable().
+
+Fixes: a8636c89648a (PM / Runtime: Don't allow to suspend a device with an active child)
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Johan Hovold <johan@kernel.org>
+(cherry picked from commit f8817f61e8215b0ff1b73a0d33fa04ef9e6bce8b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/power/runtime_pm.txt |  3 +--
+ drivers/base/power/runtime.c       | 31 +++++++++++-------------------
+ 2 files changed, 12 insertions(+), 22 deletions(-)
+
+diff --git a/Documentation/power/runtime_pm.txt b/Documentation/power/runtime_pm.txt
+index 625549d4c74a..0fde3dcf077a 100644
+--- a/Documentation/power/runtime_pm.txt
++++ b/Documentation/power/runtime_pm.txt
+@@ -435,8 +435,7 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
+       PM status to 'suspended' and update its parent's counter of 'active'
+       children as appropriate (it is only valid to use this function if
+       'power.runtime_error' is set or 'power.disable_depth' is greater than
+-      zero); it will fail and return an error code if the device has a child
+-      which is active and the 'power.ignore_children' flag is unset
++      zero)
+ 
+   bool pm_runtime_active(struct device *dev);
+     - return true if the device's runtime PM status is 'active' or its
+diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
+index b2b1eece0db1..3da090e7ed05 100644
+--- a/drivers/base/power/runtime.c
++++ b/drivers/base/power/runtime.c
+@@ -1102,29 +1102,13 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
+ 		goto out;
+ 	}
+ 
+-	if (dev->power.runtime_status == status)
++	if (dev->power.runtime_status == status || !parent)
+ 		goto out_set;
+ 
+ 	if (status == RPM_SUSPENDED) {
+-		/*
+-		 * It is invalid to suspend a device with an active child,
+-		 * unless it has been set to ignore its children.
+-		 */
+-		if (!dev->power.ignore_children &&
+-			atomic_read(&dev->power.child_count)) {
+-			dev_err(dev, "runtime PM trying to suspend device but active child\n");
+-			error = -EBUSY;
+-			goto out;
+-		}
+-
+-		if (parent) {
+-			atomic_add_unless(&parent->power.child_count, -1, 0);
+-			notify_parent = !parent->power.ignore_children;
+-		}
+-		goto out_set;
+-	}
+-
+-	if (parent) {
++		atomic_add_unless(&parent->power.child_count, -1, 0);
++		notify_parent = !parent->power.ignore_children;
++	} else {
+ 		spin_lock_nested(&parent->power.lock, SINGLE_DEPTH_NESTING);
+ 
+ 		/*
+@@ -1308,6 +1292,13 @@ void pm_runtime_enable(struct device *dev)
+ 	else
+ 		dev_warn(dev, "Unbalanced %s!\n", __func__);
+ 
++	WARN(!dev->power.disable_depth &&
++	     dev->power.runtime_status == RPM_SUSPENDED &&
++	     !dev->power.ignore_children &&
++	     atomic_read(&dev->power.child_count) > 0,
++	     "Enabling runtime PM for inactive device (%s) with active children\n",
++	     dev_name(dev));
++
+ 	spin_unlock_irqrestore(&dev->power.lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(pm_runtime_enable);
+-- 
+2.19.0
+
diff --git a/patches/0409-dt-bindings-add-eeprom-size-property.patch b/patches/0409-dt-bindings-add-eeprom-size-property.patch
new file mode 100644
index 00000000000000..2a69bf21cefdce
--- /dev/null
+++ b/patches/0409-dt-bindings-add-eeprom-size-property.patch
@@ -0,0 +1,36 @@
+From 4fc67a9516c3251ba882f86d7257a987b95cccb0 Mon Sep 17 00:00:00 2001
+From: Divagar Mohandass <divagar.mohandass@intel.com>
+Date: Tue, 10 Oct 2017 11:30:35 +0530
+Subject: [PATCH 0409/1795] dt-bindings: add eeprom "size" property
+
+This adds eeprom "size" as optional property for i2c eeproms.
+The "size" property allows explicitly specifying the size of the
+EEPROM chip in bytes.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit f2f5afd3845c88e96e863ae31f6a7587906af0e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/eeprom.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/eeprom.txt
+index afc04589eadf..27f2bc15298a 100644
+--- a/Documentation/devicetree/bindings/eeprom/eeprom.txt
++++ b/Documentation/devicetree/bindings/eeprom/eeprom.txt
+@@ -36,6 +36,8 @@ Optional properties:
+ 
+   - read-only: this parameterless property disables writes to the eeprom
+ 
++  - size: total eeprom size in bytes
++
+ Example:
+ 
+ eeprom@52 {
+-- 
+2.19.0
+
diff --git a/patches/0410-dt-bindings-eeprom-rename-to-at24.txt.patch b/patches/0410-dt-bindings-eeprom-rename-to-at24.txt.patch
new file mode 100644
index 00000000000000..2a988b410eaf21
--- /dev/null
+++ b/patches/0410-dt-bindings-eeprom-rename-to-at24.txt.patch
@@ -0,0 +1,28 @@
+From b60564d4bda2aad5a67eb759eff5476824163483 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa@the-dreams.de>
+Date: Thu, 7 Dec 2017 11:38:28 +0100
+Subject: [PATCH 0410/1795] dt-bindings: eeprom: rename to at24.txt
+
+This binding documentation is for the at24 driver, so the filename
+should reflect it. This avoids confusion because we also have an
+"eeprom" driver in Linux but it doesn't support DT even.
+
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit fe06a3fa28917defb70483b2da710d5c54156e52)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/{eeprom.txt => at24.txt} | 0
+ 1 file changed, 0 insertions(+), 0 deletions(-)
+ rename Documentation/devicetree/bindings/eeprom/{eeprom.txt => at24.txt} (100%)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+similarity index 100%
+rename from Documentation/devicetree/bindings/eeprom/eeprom.txt
+rename to Documentation/devicetree/bindings/eeprom/at24.txt
+-- 
+2.19.0
+
diff --git a/patches/0411-dt-bindings-add-eeprom-no-read-rollover-property.patch b/patches/0411-dt-bindings-add-eeprom-no-read-rollover-property.patch
new file mode 100644
index 00000000000000..251eccd16f6268
--- /dev/null
+++ b/patches/0411-dt-bindings-add-eeprom-no-read-rollover-property.patch
@@ -0,0 +1,38 @@
+From d2f69f52ffba37a7e4c5fb6b5f68a38ec59d04bf Mon Sep 17 00:00:00 2001
+From: Sven Van Asbroeck <svendev@arcx.com>
+Date: Fri, 8 Dec 2017 11:28:31 -0500
+Subject: [PATCH 0411/1795] dt-bindings: add eeprom "no-read-rollover" property
+
+Adds an optional property for at24 eeproms. This parameterless
+property indicates that the multi-address eeprom does not
+automatically roll over reads to the next slave address.
+
+Signed-off-by: Sven Van Asbroeck <svendev@arcx.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit 355dd4ca10b49183272ec54ed9853bb4b95d2391)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index 27f2bc15298a..a0415b8471bb 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -38,6 +38,11 @@ Optional properties:
+ 
+   - size: total eeprom size in bytes
+ 
++  - no-read-rollover:
++			This parameterless property indicates that the multi-address
++			eeprom does not automatically roll over reads to the next
++			slave address. Please consult the manual of your device.
++
+ Example:
+ 
+ eeprom@52 {
+-- 
+2.19.0
+
diff --git a/patches/0412-dt-bindings-at24-new-optional-property-wp-gpios.patch b/patches/0412-dt-bindings-at24-new-optional-property-wp-gpios.patch
new file mode 100644
index 00000000000000..933a76847aab42
--- /dev/null
+++ b/patches/0412-dt-bindings-at24-new-optional-property-wp-gpios.patch
@@ -0,0 +1,51 @@
+From cd352f491c0979826b29b1a6d3220d5c6cf8b304 Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <brgl@bgdev.pl>
+Date: Tue, 19 Dec 2017 12:09:23 +0100
+Subject: [PATCH 0412/1795] dt-bindings: at24: new optional property - wp-gpios
+
+AT24 EEPROMs have a write-protect pin, which - when pulled high -
+inhibits writes to the upper quadrant of memory (although it has been
+observed that on some chips it disables writing to the entire memory
+range).
+
+On some boards, this pin is connected to a GPIO and pulled high by
+default, which forces the user to manually change its state before
+writing. On linux this means that we either need to hog the line all
+the time, or set the GPIO value before writing from outside of the
+at24 driver.
+
+Add a new optional property to the device tree binding document, which
+allows to specify the GPIO line to which the write-protect pin is
+connected.
+
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 3f3d8ef7f4eff5909b0cc996718de81de99af1e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index a0415b8471bb..cbc80e194ac6 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -43,10 +43,13 @@ Optional properties:
+ 			eeprom does not automatically roll over reads to the next
+ 			slave address. Please consult the manual of your device.
+ 
++  - wp-gpios: GPIO to which the write-protect pin of the chip is connected.
++
+ Example:
+ 
+ eeprom@52 {
+ 	compatible = "atmel,24c32";
+ 	reg = <0x52>;
+ 	pagesize = <32>;
++	wp-gpios = <&gpio1 3 0>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/0413-dt-bindings-at24-consistently-document-the-compatibl.patch b/patches/0413-dt-bindings-at24-consistently-document-the-compatibl.patch
new file mode 100644
index 00000000000000..c8ff212e878ae6
--- /dev/null
+++ b/patches/0413-dt-bindings-at24-consistently-document-the-compatibl.patch
@@ -0,0 +1,92 @@
+From 1120188e35e783fab93874b8631720f9dfbe1804 Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <brgl@bgdev.pl>
+Date: Thu, 28 Dec 2017 11:49:10 +0100
+Subject: [PATCH 0413/1795] dt-bindings: at24: consistently document the
+ compatible property
+
+Current description of the compatible property for at24 is quite vague.
+
+State explicitly that any "<manufacturer>,<model>" pair is accepted as
+long as a correct fallback is used for non-atmel chips.
+
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 6da28acf745fe2537d77b9044f78a2a4e100c773)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/eeprom/at24.txt       | 58 ++++++++++++-------
+ 1 file changed, 36 insertions(+), 22 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index cbc80e194ac6..5ac18ce2e8cd 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -2,28 +2,42 @@ EEPROMs (I2C)
+ 
+ Required properties:
+ 
+-  - compatible : should be "<manufacturer>,<type>", like these:
+-
+-	"atmel,24c00", "atmel,24c01", "atmel,24c02", "atmel,24c04",
+-	"atmel,24c08", "atmel,24c16", "atmel,24c32", "atmel,24c64",
+-	"atmel,24c128", "atmel,24c256", "atmel,24c512", "atmel,24c1024"
+-
+-	"catalyst,24c32"
+-
+-	"microchip,24c128"
+-
+-	"ramtron,24c64"
+-
+-	"renesas,r1ex24002"
+-
+-	The following manufacturers values have been deprecated:
+-	"at", "at24"
+-
+-	 If there is no specific driver for <manufacturer>, a generic
+-	 device with <type> and manufacturer "atmel" should be used.
+-	 Possible types are:
+-	 "24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",
+-	 "24c128", "24c256", "24c512", "24c1024", "spd"
++  - compatible: Must be a "<manufacturer>,<model>" pair. The following <model>
++                values are supported (assuming "atmel" as manufacturer):
++
++                "atmel,24c00",
++                "atmel,24c01",
++                "atmel,24c02",
++                "atmel,spd",
++                "atmel,24c04",
++                "atmel,24c08",
++                "atmel,24c16",
++                "atmel,24c32",
++                "atmel,24c64",
++                "atmel,24c128",
++                "atmel,24c256",
++                "atmel,24c512",
++                "atmel,24c1024",
++
++                If <manufacturer> is not "atmel", then a fallback must be used
++                with the same <model> and "atmel" as manufacturer.
++
++                Example:
++                        compatible = "microchip,24c128", "atmel,24c128";
++
++                Supported manufacturers are:
++
++                "catalyst",
++                "microchip",
++                "ramtron",
++                "renesas",
++                "nxp",
++                "st",
++
++                Some vendors use different model names for chips which are just
++                variants of the above. Known such exceptions are listed below:
++
++                "renesas,r1ex24002" - the fallback is "atmel,24c02"
+ 
+   - reg : the I2C address of the EEPROM
+ 
+-- 
+2.19.0
+
diff --git a/patches/0414-dt-bindings-at24-fix-formatting-and-style.patch b/patches/0414-dt-bindings-at24-fix-formatting-and-style.patch
new file mode 100644
index 00000000000000..8c62d411da4d8e
--- /dev/null
+++ b/patches/0414-dt-bindings-at24-fix-formatting-and-style.patch
@@ -0,0 +1,61 @@
+From 74e8f1062e610e343783db228bb96a9d71a8038f Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <brgl@bgdev.pl>
+Date: Thu, 28 Dec 2017 11:49:11 +0100
+Subject: [PATCH 0414/1795] dt-bindings: at24: fix formatting and style
+
+Make formatting and style consistent for the entire document.
+
+This patch doesn't change the content of the binding.
+
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit e32a1f30b67521335aa1869263bf9220b5df2b83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/eeprom/at24.txt       | 22 +++++++++----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index 5ac18ce2e8cd..07a289ba831d 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -39,23 +39,23 @@ Required properties:
+ 
+                 "renesas,r1ex24002" - the fallback is "atmel,24c02"
+ 
+-  - reg : the I2C address of the EEPROM
++  - reg: The I2C address of the EEPROM.
+ 
+ Optional properties:
+ 
+-  - pagesize : the length of the pagesize for writing. Please consult the
+-               manual of your device, that value varies a lot. A wrong value
+-	       may result in data loss! If not specified, a safety value of
+-	       '1' is used which will be very slow.
++  - pagesize: The length of the pagesize for writing. Please consult the
++              manual of your device, that value varies a lot. A wrong value
++              may result in data loss! If not specified, a safety value of
++              '1' is used which will be very slow.
+ 
+-  - read-only: this parameterless property disables writes to the eeprom
++  - read-only: This parameterless property disables writes to the eeprom.
+ 
+-  - size: total eeprom size in bytes
++  - size: Total eeprom size in bytes.
+ 
+-  - no-read-rollover:
+-			This parameterless property indicates that the multi-address
+-			eeprom does not automatically roll over reads to the next
+-			slave address. Please consult the manual of your device.
++  - no-read-rollover: This parameterless property indicates that the
++                      multi-address eeprom does not automatically roll over
++                      reads to the next slave address. Please consult the
++                      manual of your device.
+ 
+   - wp-gpios: GPIO to which the write-protect pin of the chip is connected.
+ 
+-- 
+2.19.0
+
diff --git a/patches/0415-dt-bindings-at24-extend-the-list-of-supported-chips.patch b/patches/0415-dt-bindings-at24-extend-the-list-of-supported-chips.patch
new file mode 100644
index 00000000000000..2a4f913b9e82ec
--- /dev/null
+++ b/patches/0415-dt-bindings-at24-extend-the-list-of-supported-chips.patch
@@ -0,0 +1,49 @@
+From 66f39698215144daa6601104317feb5d488a66de Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <brgl@bgdev.pl>
+Date: Thu, 28 Dec 2017 11:49:12 +0100
+Subject: [PATCH 0415/1795] dt-bindings: at24: extend the list of supported
+ chips
+
+Add other variants of at24 EEPROMs we support in the driver to the
+list of allowed compatible fallbacks.
+
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit e36820425f699e4a4ebefb583df6308d6749eef3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index 07a289ba831d..1812c848e369 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -7,13 +7,22 @@ Required properties:
+ 
+                 "atmel,24c00",
+                 "atmel,24c01",
++                "atmel,24cs01",
+                 "atmel,24c02",
++                "atmel,24cs02",
++                "atmel,24mac402",
++                "atmel,24mac602",
+                 "atmel,spd",
+                 "atmel,24c04",
++                "atmel,24cs04",
+                 "atmel,24c08",
++                "atmel,24cs08",
+                 "atmel,24c16",
++                "atmel,24cs16",
+                 "atmel,24c32",
++                "atmel,24cs32",
+                 "atmel,24c64",
++                "atmel,24cs64",
+                 "atmel,24c128",
+                 "atmel,24c256",
+                 "atmel,24c512",
+-- 
+2.19.0
+
diff --git a/patches/0416-dt-bindings-at24-sort-manufacturers-alphabetically.patch b/patches/0416-dt-bindings-at24-sort-manufacturers-alphabetically.patch
new file mode 100644
index 00000000000000..12468b811d6e03
--- /dev/null
+++ b/patches/0416-dt-bindings-at24-sort-manufacturers-alphabetically.patch
@@ -0,0 +1,36 @@
+From 0b6a3d9b45ec93af1837b10992a6d389bf6ac55f Mon Sep 17 00:00:00 2001
+From: Peter Rosin <peda@axentia.se>
+Date: Tue, 16 Jan 2018 17:06:15 +0100
+Subject: [PATCH 0416/1795] dt-bindings: at24: sort manufacturers
+ alphabetically
+
+Makes them easier to find.
+
+Signed-off-by: Peter Rosin <peda@axentia.se>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit 377999caf72233af4abebb511359647f312c4e6e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index 1812c848e369..abfae1beca2b 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -38,9 +38,9 @@ Required properties:
+ 
+                 "catalyst",
+                 "microchip",
++                "nxp",
+                 "ramtron",
+                 "renesas",
+-                "nxp",
+                 "st",
+ 
+                 Some vendors use different model names for chips which are just
+-- 
+2.19.0
+
diff --git a/patches/0417-drm-drivers-drop-redundant-drm_edid_to_eld-calls.patch b/patches/0417-drm-drivers-drop-redundant-drm_edid_to_eld-calls.patch
new file mode 100644
index 00000000000000..71971ac45abfad
--- /dev/null
+++ b/patches/0417-drm-drivers-drop-redundant-drm_edid_to_eld-calls.patch
@@ -0,0 +1,244 @@
+From 24ab204442b03b1b39857a26f4e0e879a9f77fd9 Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Wed, 1 Nov 2017 16:21:02 +0200
+Subject: [PATCH 0417/1795] drm/drivers: drop redundant drm_edid_to_eld() calls
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+drm_add_edid_modes() now fills in the ELD automatically, so the calls to
+drm_edid_to_eld() are redundant. Remove them.
+
+All the other places are obvious, but nv50 has detached
+drm_edid_to_eld() from the drm_add_edid_modes() call.
+
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: Christian König <christian.koenig@amd.com>
+Cc: Archit Taneja <architt@codeaurora.org>
+Cc: Andrzej Hajda <a.hajda@samsung.com>
+Cc: Russell King <linux@armlinux.org.uk>
+Cc: CK Hu <ck.hu@mediatek.com>
+Cc: Philipp Zabel <p.zabel@pengutronix.de>
+Cc: Ben Skeggs <bskeggs@redhat.com>
+Cc: Mark Yao <mark.yao@rock-chips.com>
+Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
+Cc: Vincent Abriou <vincent.abriou@st.com>
+Cc: Thierry Reding <thierry.reding@gmail.com>
+Cc: Eric Anholt <eric@anholt.net>
+Acked-by: Eric Anholt <eric@anholt.net>
+Acked-by: Archit Taneja <architt@codeaurora.org>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/0959ca02b983afc9e74dd9acd190ba6e25f21678.1509545641.git.jani.nikula@intel.com
+(cherry picked from commit d471ed04b487c6e66a406bf3763efbfed56baa5b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 1 -
+ drivers/gpu/drm/bridge/analogix-anx78xx.c      | 2 --
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c      | 2 --
+ drivers/gpu/drm/i2c/tda998x_drv.c              | 1 -
+ drivers/gpu/drm/i915/intel_dp.c                | 1 -
+ drivers/gpu/drm/i915/intel_modes.c             | 1 -
+ drivers/gpu/drm/mediatek/mtk_hdmi.c            | 1 -
+ drivers/gpu/drm/nouveau/nv50_display.c         | 5 +----
+ drivers/gpu/drm/radeon/radeon_connectors.c     | 1 -
+ drivers/gpu/drm/radeon/radeon_dp_mst.c         | 1 -
+ drivers/gpu/drm/rockchip/cdn-dp-core.c         | 4 +---
+ drivers/gpu/drm/sti/sti_hdmi.c                 | 1 -
+ drivers/gpu/drm/tegra/output.c                 | 1 -
+ drivers/gpu/drm/vc4/vc4_hdmi.c                 | 1 -
+ 14 files changed, 2 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+index 1eff36a87595..5647af335334 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -353,7 +353,6 @@ static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
+ 	if (amdgpu_connector->edid) {
+ 		drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
+ 		ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
+-		drm_edid_to_eld(connector, amdgpu_connector->edid);
+ 		return ret;
+ 	}
+ 	drm_mode_connector_update_edid_property(connector, NULL);
+diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c
+index 9385eb0b1ee4..ed12a7ddd64a 100644
+--- a/drivers/gpu/drm/bridge/analogix-anx78xx.c
++++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
+@@ -977,8 +977,6 @@ static int anx78xx_get_modes(struct drm_connector *connector)
+ 	}
+ 
+ 	num_modes = drm_add_edid_modes(connector, anx78xx->edid);
+-	/* Store the ELD */
+-	drm_edid_to_eld(connector, anx78xx->edid);
+ 
+ unlock:
+ 	mutex_unlock(&anx78xx->lock);
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 994f16727458..bc848885735a 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1914,8 +1914,6 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
+ 		drm_mode_connector_update_edid_property(connector, edid);
+ 		cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
+ 		ret = drm_add_edid_modes(connector, edid);
+-		/* Store the ELD */
+-		drm_edid_to_eld(connector, edid);
+ 		kfree(edid);
+ 	} else {
+ 		dev_dbg(hdmi->dev, "failed to get edid\n");
+diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
+index 54e3255dde13..8c8953e069cd 100644
+--- a/drivers/gpu/drm/i2c/tda998x_drv.c
++++ b/drivers/gpu/drm/i2c/tda998x_drv.c
+@@ -1100,7 +1100,6 @@ static int tda998x_connector_get_modes(struct drm_connector *connector)
+ 
+ 	drm_mode_connector_update_edid_property(connector, edid);
+ 	n = drm_add_edid_modes(connector, edid);
+-	drm_edid_to_eld(connector, edid);
+ 
+ 	kfree(edid);
+ 
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 76cf68745870..87d04212f0e5 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -5878,7 +5878,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
+ 		if (drm_add_edid_modes(connector, edid)) {
+ 			drm_mode_connector_update_edid_property(connector,
+ 								edid);
+-			drm_edid_to_eld(connector, edid);
+ 		} else {
+ 			kfree(edid);
+ 			edid = ERR_PTR(-EINVAL);
+diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
+index 28a778b785ac..4e43f873c889 100644
+--- a/drivers/gpu/drm/i915/intel_modes.c
++++ b/drivers/gpu/drm/i915/intel_modes.c
+@@ -57,7 +57,6 @@ int intel_connector_update_modes(struct drm_connector *connector,
+ 
+ 	drm_mode_connector_update_edid_property(connector, edid);
+ 	ret = drm_add_edid_modes(connector, edid);
+-	drm_edid_to_eld(connector, edid);
+ 
+ 	intel_connector_update_eld_conn_type(connector);
+ 
+diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
+index 690c67507cbc..34f84fe3f05e 100644
+--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
++++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
+@@ -1222,7 +1222,6 @@ static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
+ 	drm_mode_connector_update_edid_property(conn, edid);
+ 
+ 	ret = drm_add_edid_modes(conn, edid);
+-	drm_edid_to_eld(conn, edid);
+ 	kfree(edid);
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
+index 926ec51ba5be..e558fa480682 100644
+--- a/drivers/gpu/drm/nouveau/nv50_display.c
++++ b/drivers/gpu/drm/nouveau/nv50_display.c
+@@ -2688,7 +2688,6 @@ nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
+ 	if (!drm_detect_monitor_audio(nv_connector->edid))
+ 		return;
+ 
+-	drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
+ 	memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
+ 
+ 	nvif_mthd(disp->disp, 0, &args,
+@@ -3064,10 +3063,8 @@ nv50_mstc_get_modes(struct drm_connector *connector)
+ 
+ 	mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
+ 	drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
+-	if (mstc->edid) {
++	if (mstc->edid)
+ 		ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
+-		drm_edid_to_eld(&mstc->connector, mstc->edid);
+-	}
+ 
+ 	if (!mstc->connector.display_info.bpc)
+ 		mstc->connector.display_info.bpc = 8;
+diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
+index 337d3a1c2a40..ff2b4827d743 100644
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -385,7 +385,6 @@ static int radeon_ddc_get_modes(struct drm_connector *connector)
+ 	if (radeon_connector->edid) {
+ 		drm_mode_connector_update_edid_property(connector, radeon_connector->edid);
+ 		ret = drm_add_edid_modes(connector, radeon_connector->edid);
+-		drm_edid_to_eld(connector, radeon_connector->edid);
+ 		return ret;
+ 	}
+ 	drm_mode_connector_update_edid_property(connector, NULL);
+diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
+index 2917ea1b667e..183b4b482138 100644
+--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
++++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
+@@ -197,7 +197,6 @@ static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
+ 	if (radeon_connector->edid) {
+ 		drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
+ 		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
+-		drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
+ 		return ret;
+ 	}
+ 	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
+diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
+index a57da051f516..9841986d0313 100644
+--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
+@@ -276,11 +276,9 @@ static int cdn_dp_connector_get_modes(struct drm_connector *connector)
+ 
+ 		dp->sink_has_audio = drm_detect_monitor_audio(edid);
+ 		ret = drm_add_edid_modes(connector, edid);
+-		if (ret) {
++		if (ret)
+ 			drm_mode_connector_update_edid_property(connector,
+ 								edid);
+-			drm_edid_to_eld(connector, edid);
+-		}
+ 	}
+ 	mutex_unlock(&dp->lock);
+ 
+diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
+index 30f02d2fdd03..d1902750a85d 100644
+--- a/drivers/gpu/drm/sti/sti_hdmi.c
++++ b/drivers/gpu/drm/sti/sti_hdmi.c
+@@ -976,7 +976,6 @@ static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
+ 
+ 	count = drm_add_edid_modes(connector, edid);
+ 	drm_mode_connector_update_edid_property(connector, edid);
+-	drm_edid_to_eld(connector, edid);
+ 
+ 	kfree(edid);
+ 	return count;
+diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
+index 595d1ec3e02e..1480f6aaffe4 100644
+--- a/drivers/gpu/drm/tegra/output.c
++++ b/drivers/gpu/drm/tegra/output.c
+@@ -36,7 +36,6 @@ int tegra_output_connector_get_modes(struct drm_connector *connector)
+ 
+ 	if (edid) {
+ 		err = drm_add_edid_modes(connector, edid);
+-		drm_edid_to_eld(connector, edid);
+ 		kfree(edid);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
+index 8f71157a2b06..111c5b6c3a4a 100644
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -287,7 +287,6 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
+ 
+ 	drm_mode_connector_update_edid_property(connector, edid);
+ 	ret = drm_add_edid_modes(connector, edid);
+-	drm_edid_to_eld(connector, edid);
+ 	kfree(edid);
+ 
+ 	return ret;
+-- 
+2.19.0
+
diff --git a/patches/0418-i2c-sh_mobile-remove-redundant-initialization.patch b/patches/0418-i2c-sh_mobile-remove-redundant-initialization.patch
new file mode 100644
index 00000000000000..a8b71b66119f2a
--- /dev/null
+++ b/patches/0418-i2c-sh_mobile-remove-redundant-initialization.patch
@@ -0,0 +1,41 @@
+From 168dcb66fc443df0eff60b8842cc4447e35a9ff8 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 2 Nov 2017 13:47:27 +0100
+Subject: [PATCH 0418/1795] i2c: sh_mobile: remove redundant initialization
+
+Following the documentation, we initialize the HW before each START in
+start_ch(). No need to do the same in activate_ch().
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit f289800af1fd4379403f2630e7e9420401a4cd8e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index c03acdf71397..0ac152586e74 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -303,16 +303,6 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
+ 	/* Wake up device and enable clock */
+ 	pm_runtime_get_sync(pd->dev);
+ 	clk_prepare_enable(pd->clk);
+-
+-	/* Enable channel and configure rx ack */
+-	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
+-
+-	/* Mask all interrupts */
+-	iic_wr(pd, ICIC, 0);
+-
+-	/* Set the clock */
+-	iic_wr(pd, ICCL, pd->iccl & 0xff);
+-	iic_wr(pd, ICCH, pd->icch & 0xff);
+ }
+ 
+ static void deactivate_ch(struct sh_mobile_i2c_data *pd)
+-- 
+2.19.0
+
diff --git a/patches/0419-i2c-sh_mobile-remove-redundant-deinitialization.patch b/patches/0419-i2c-sh_mobile-remove-redundant-deinitialization.patch
new file mode 100644
index 00000000000000..bfe35f44ea99fd
--- /dev/null
+++ b/patches/0419-i2c-sh_mobile-remove-redundant-deinitialization.patch
@@ -0,0 +1,36 @@
+From f6d43419546bc9db4680769b307295bd3cf27903 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 2 Nov 2017 13:47:28 +0100
+Subject: [PATCH 0419/1795] i2c: sh_mobile: remove redundant deinitialization
+
+No need to clear the interrupt registers because right after that we
+disable the IP core which will reload registers with their initial
+values anyhow.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 3f3a513985ce55d69922cc9b5a0e095432cdfbc4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 0ac152586e74..cbaed24fb18f 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -307,10 +307,6 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
+ 
+ static void deactivate_ch(struct sh_mobile_i2c_data *pd)
+ {
+-	/* Clear/disable interrupts */
+-	iic_wr(pd, ICSR, 0);
+-	iic_wr(pd, ICIC, 0);
+-
+ 	/* Disable channel */
+ 	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0420-i2c-sh_mobile-manually-inline-two-short-functions.patch b/patches/0420-i2c-sh_mobile-manually-inline-two-short-functions.patch
new file mode 100644
index 00000000000000..ff2f5ebc249f11
--- /dev/null
+++ b/patches/0420-i2c-sh_mobile-manually-inline-two-short-functions.patch
@@ -0,0 +1,75 @@
+From 98c11ae95939a8529f7b76eda7ed1cd40e8d20da Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 2 Nov 2017 13:47:29 +0100
+Subject: [PATCH 0420/1795] i2c: sh_mobile: manually "inline" two short
+ functions
+
+Those two functions are very short and only called once. The code
+becomes easier to understand if the code is directly put into the main
+xfer function.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 91a5e63e3f9879e5030064a3c0d23c3777c4f4d0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 28 +++++++++-------------------
+ 1 file changed, 9 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index cbaed24fb18f..02c2912bebb4 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -298,23 +298,6 @@ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
+ 	return 0;
+ }
+ 
+-static void activate_ch(struct sh_mobile_i2c_data *pd)
+-{
+-	/* Wake up device and enable clock */
+-	pm_runtime_get_sync(pd->dev);
+-	clk_prepare_enable(pd->clk);
+-}
+-
+-static void deactivate_ch(struct sh_mobile_i2c_data *pd)
+-{
+-	/* Disable channel */
+-	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
+-
+-	/* Disable clock and mark device as idle */
+-	clk_disable_unprepare(pd->clk);
+-	pm_runtime_put_sync(pd->dev);
+-}
+-
+ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
+ 			    enum sh_mobile_i2c_op op, unsigned char data)
+ {
+@@ -717,7 +700,9 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 	int i;
+ 	long timeout;
+ 
+-	activate_ch(pd);
++	/* Wake up device and enable clock */
++	pm_runtime_get_sync(pd->dev);
++	clk_prepare_enable(pd->clk);
+ 
+ 	/* Process all messages */
+ 	for (i = 0; i < num; i++) {
+@@ -754,7 +739,12 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 			break;
+ 	}
+ 
+-	deactivate_ch(pd);
++	/* Disable channel */
++	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
++
++	/* Disable clock and mark device as idle */
++	clk_disable_unprepare(pd->clk);
++	pm_runtime_put_sync(pd->dev);
+ 
+ 	if (!err)
+ 		err = num;
+-- 
+2.19.0
+
diff --git a/patches/0421-i2c-sh_mobile-use-direct-writes-when-accessing-ICE-b.patch b/patches/0421-i2c-sh_mobile-use-direct-writes-when-accessing-ICE-b.patch
new file mode 100644
index 00000000000000..32a28be564c3d2
--- /dev/null
+++ b/patches/0421-i2c-sh_mobile-use-direct-writes-when-accessing-ICE-b.patch
@@ -0,0 +1,47 @@
+From ae60ed6fbf22f4225061357da8664924668d7769 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 2 Nov 2017 13:47:30 +0100
+Subject: [PATCH 0421/1795] i2c: sh_mobile: use direct writes when accessing
+ ICE bit
+
+ICE bit is for resetting the module. Other bits don't matter then, so we
+don't need to use the iic_set_clr() function but can use iic_wr().
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 832a522a3ef5e96b517163ee7d4c249545d88626)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 02c2912bebb4..72c9483db769 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -620,10 +620,10 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
+ 
+ 	if (do_init) {
+ 		/* Initialize channel registers */
+-		iic_set_clr(pd, ICCR, 0, ICCR_ICE);
++		iic_wr(pd, ICCR, 0);
+ 
+ 		/* Enable channel and configure rx ack */
+-		iic_set_clr(pd, ICCR, ICCR_ICE, 0);
++		iic_wr(pd, ICCR, ICCR_ICE);
+ 
+ 		/* Set the clock */
+ 		iic_wr(pd, ICCL, pd->iccl & 0xff);
+@@ -740,7 +740,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 	}
+ 
+ 	/* Disable channel */
+-	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
++	iic_wr(pd, ICCR, 0);
+ 
+ 	/* Disable clock and mark device as idle */
+ 	clk_disable_unprepare(pd->clk);
+-- 
+2.19.0
+
diff --git a/patches/0422-i2c-sh_mobile-shorten-exit-of-xfer-routine.patch b/patches/0422-i2c-sh_mobile-shorten-exit-of-xfer-routine.patch
new file mode 100644
index 00000000000000..f6f67c9152a3b2
--- /dev/null
+++ b/patches/0422-i2c-sh_mobile-shorten-exit-of-xfer-routine.patch
@@ -0,0 +1,34 @@
+From e099190654238c33c7657f858a5ca8dd3daa6398 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 2 Nov 2017 13:47:31 +0100
+Subject: [PATCH 0422/1795] i2c: sh_mobile: shorten exit of xfer routine
+
+We can use the ternary operator for easier reading.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit a4d16493be406273320f152814c33ccdb17dcf91)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 72c9483db769..ebd146ccb244 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -746,9 +746,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 	clk_disable_unprepare(pd->clk);
+ 	pm_runtime_put_sync(pd->dev);
+ 
+-	if (!err)
+-		err = num;
+-	return err;
++	return err ?: num;
+ }
+ 
+ static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
+-- 
+2.19.0
+
diff --git a/patches/0423-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch b/patches/0423-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
new file mode 100644
index 00000000000000..ad1146d6f9e443
--- /dev/null
+++ b/patches/0423-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
@@ -0,0 +1,41 @@
+From 7778c156f79a2ce12c021ff8e449b5fda6efa42f Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 8 Nov 2017 09:50:37 +0100
+Subject: [PATCH 0423/1795] i2c: sh_mobile: let RuntimePM do the clock handling
+
+No need to do it manually.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 91701ae85dff9703335b5912673df75f4b6f4c53)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index ebd146ccb244..80561ffbcf7b 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -702,7 +702,6 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 
+ 	/* Wake up device and enable clock */
+ 	pm_runtime_get_sync(pd->dev);
+-	clk_prepare_enable(pd->clk);
+ 
+ 	/* Process all messages */
+ 	for (i = 0; i < num; i++) {
+@@ -743,7 +742,6 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 	iic_wr(pd, ICCR, 0);
+ 
+ 	/* Disable clock and mark device as idle */
+-	clk_disable_unprepare(pd->clk);
+ 	pm_runtime_put_sync(pd->dev);
+ 
+ 	return err ?: num;
+-- 
+2.19.0
+
diff --git a/patches/0424-i2c-sh_mobile-avoid-unnecessary-register-read.patch b/patches/0424-i2c-sh_mobile-avoid-unnecessary-register-read.patch
new file mode 100644
index 00000000000000..866b3209ce4608
--- /dev/null
+++ b/patches/0424-i2c-sh_mobile-avoid-unnecessary-register-read.patch
@@ -0,0 +1,36 @@
+From afa2b3d18bedd1ceb702cfffd5ab9d8a91bf1210 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 9 Nov 2017 23:20:53 +0100
+Subject: [PATCH 0424/1795] i2c: sh_mobile: avoid unnecessary register read
+
+There is no data when the first WAIT interrupt arrives. No need to read
+something then.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 2967f9ca8b0dc8d924e0f14c55d1e73d9c6c4975)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 80561ffbcf7b..40a66d466c3c 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -433,8 +433,9 @@ static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
+ 				break;
+ 			}
+ 			data = i2c_op(pd, OP_RX_STOP_DATA, 0);
+-		} else
++		} else if (real_pos >= 0) {
+ 			data = i2c_op(pd, OP_RX, 0);
++		}
+ 
+ 		if (real_pos >= 0)
+ 			pd->msg->buf[real_pos] = data;
+-- 
+2.19.0
+
diff --git a/patches/0425-i2c-sh_mobile-send-STOP-according-to-datasheet.patch b/patches/0425-i2c-sh_mobile-send-STOP-according-to-datasheet.patch
new file mode 100644
index 00000000000000..b10e7aeaf8a10e
--- /dev/null
+++ b/patches/0425-i2c-sh_mobile-send-STOP-according-to-datasheet.patch
@@ -0,0 +1,111 @@
+From ecde2ad896297eed23d9c78b740ce2b0906e76b9 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Fri, 10 Nov 2017 12:52:10 +0100
+Subject: [PATCH 0425/1795] i2c: sh_mobile: send STOP according to datasheet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We initiate STOP (or REP_START) on the second last WAIT interrupt
+currently. This works fine but is not according to the datasheet which
+says to do it on the last WAIT interrupt. This also simplifies the code
+quite a lot, so let's do it.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit a4fde7e5c9d6432ba863ee53debf27f10b370678)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 29 ++++++-----------------------
+ 1 file changed, 6 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 40a66d466c3c..c904be631db3 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -40,21 +40,21 @@
+ /* BUS:     S     A8     ACK   P(*)                                         */
+ /* IRQ:       DTE   WAIT                                                    */
+ /* ICIC:                                                                    */
+-/* ICCR: 0x94 0x90                                                          */
++/* ICCR: 0x94       0x90                                                    */
+ /* ICDR:      A8                                                            */
+ /*                                                                          */
+ /* 1 byte transmit                                                          */
+ /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
+ /* IRQ:       DTE   WAIT         WAIT                                       */
+ /* ICIC:      -DTE                                                          */
+-/* ICCR: 0x94       0x90                                                    */
++/* ICCR: 0x94                    0x90                                       */
+ /* ICDR:      A8    D8(1)                                                   */
+ /*                                                                          */
+ /* 2 byte transmit                                                          */
+ /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
+ /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
+ /* ICIC:      -DTE                                                          */
+-/* ICCR: 0x94                    0x90                                       */
++/* ICCR: 0x94                                  0x90                         */
+ /* ICDR:      A8    D8(1)        D8(2)                                      */
+ /*                                                                          */
+ /* 3 bytes or more, +---------+ gets repeated                               */
+@@ -113,7 +113,6 @@ enum sh_mobile_i2c_op {
+ 	OP_TX_FIRST,
+ 	OP_TX,
+ 	OP_TX_STOP,
+-	OP_TX_STOP_DATA,
+ 	OP_TX_TO_RX,
+ 	OP_RX,
+ 	OP_RX_STOP,
+@@ -319,10 +318,7 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
+ 	case OP_TX: /* write data */
+ 		iic_wr(pd, ICDR, data);
+ 		break;
+-	case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
+-		iic_wr(pd, ICDR, data);
+-		/* fallthrough */
+-	case OP_TX_STOP: /* issue a stop */
++	case OP_TX_STOP: /* issue a stop (or rep_start) */
+ 		iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
+ 					       : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
+ 		break;
+@@ -356,11 +352,6 @@ static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
+ 	return pd->pos == -1;
+ }
+ 
+-static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
+-{
+-	return pd->pos == pd->msg->len - 1;
+-}
+-
+ static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
+ 				   unsigned char *buf)
+ {
+@@ -378,20 +369,12 @@ static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
+ 	unsigned char data;
+ 
+ 	if (pd->pos == pd->msg->len) {
+-		/* Send stop if we haven't yet (DMA case) */
+-		if (pd->send_stop && pd->stop_after_dma)
+-			i2c_op(pd, OP_TX_STOP, 0);
++		i2c_op(pd, OP_TX_STOP, 0);
+ 		return 1;
+ 	}
+ 
+ 	sh_mobile_i2c_get_data(pd, &data);
+-
+-	if (sh_mobile_i2c_is_last_byte(pd))
+-		i2c_op(pd, OP_TX_STOP_DATA, data);
+-	else if (sh_mobile_i2c_is_first_byte(pd))
+-		i2c_op(pd, OP_TX_FIRST, data);
+-	else
+-		i2c_op(pd, OP_TX, data);
++	i2c_op(pd, sh_mobile_i2c_is_first_byte(pd) ? OP_TX_FIRST : OP_TX, data);
+ 
+ 	pd->pos++;
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0426-i2c-sh_mobile-make-sure-to-not-accidently-trigger-ST.patch b/patches/0426-i2c-sh_mobile-make-sure-to-not-accidently-trigger-ST.patch
new file mode 100644
index 00000000000000..d9b005f194e7e0
--- /dev/null
+++ b/patches/0426-i2c-sh_mobile-make-sure-to-not-accidently-trigger-ST.patch
@@ -0,0 +1,50 @@
+From c26b8bd9db771ff232f11b9f16f01d79f2c678d5 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 15 Nov 2017 15:32:21 +0100
+Subject: [PATCH 0426/1795] i2c: sh_mobile: make sure to not accidently trigger
+ STOP
+
+The datasheet was a bit vague, but after consultation with HW designers,
+we came to the conclusion that we should set the SCP bit always when
+dealing only with the ICE bit. A set SCP bit is ignored, and thus fine,
+a cleared one may trigger STOP on the bus.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 4ed152c4daf32d2cd4a5285f3aaca3a4c89a31fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index c904be631db3..bc1605a31534 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -604,10 +604,10 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
+ 
+ 	if (do_init) {
+ 		/* Initialize channel registers */
+-		iic_wr(pd, ICCR, 0);
++		iic_wr(pd, ICCR, ICCR_SCP);
+ 
+ 		/* Enable channel and configure rx ack */
+-		iic_wr(pd, ICCR, ICCR_ICE);
++		iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
+ 
+ 		/* Set the clock */
+ 		iic_wr(pd, ICCL, pd->iccl & 0xff);
+@@ -723,7 +723,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ 	}
+ 
+ 	/* Disable channel */
+-	iic_wr(pd, ICCR, 0);
++	iic_wr(pd, ICCR, ICCR_SCP);
+ 
+ 	/* Disable clock and mark device as idle */
+ 	pm_runtime_put_sync(pd->dev);
+-- 
+2.19.0
+
diff --git a/patches/0427-iommu-ipmmu-vmsa-Add-r8a7796-DT-binding.patch b/patches/0427-iommu-ipmmu-vmsa-Add-r8a7796-DT-binding.patch
new file mode 100644
index 00000000000000..bdbd9d85383eff
--- /dev/null
+++ b/patches/0427-iommu-ipmmu-vmsa-Add-r8a7796-DT-binding.patch
@@ -0,0 +1,36 @@
+From 01b27d89150a0e53c8ec2bb1255e1a53d4b2eb1d Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Wed, 20 Dec 2017 09:48:00 -0700
+Subject: [PATCH 0427/1795] iommu/ipmmu-vmsa: Add r8a7796 DT binding
+
+Update the IPMMU DT binding documentation to include the r8a7796 compat
+string for R-Car M3-W.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit ca84eaeb3e0520555ee031b5ed26ce1b4b1bbd84)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+index 857df929a654..43cff3e449d0 100644
+--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
++++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+@@ -16,6 +16,7 @@ Required Properties:
+     - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
+     - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
+     - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
++    - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
+     - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
+ 
+   - reg: Base address and size of the IPMMU registers.
+-- 
+2.19.0
+
diff --git a/patches/0428-iommu-ipmmu-vmsa-Add-r8a779-70-95-DT-bindings.patch b/patches/0428-iommu-ipmmu-vmsa-Add-r8a779-70-95-DT-bindings.patch
new file mode 100644
index 00000000000000..81b0ad172f98e1
--- /dev/null
+++ b/patches/0428-iommu-ipmmu-vmsa-Add-r8a779-70-95-DT-bindings.patch
@@ -0,0 +1,36 @@
+From 546a4e95f3ba2beb2c034247173d8156452f30dc Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 09:48:01 -0700
+Subject: [PATCH 0428/1795] iommu/ipmmu-vmsa: Add r8a779(70|95) DT bindings
+
+Update the IPMMU DT binding documentation to include the
+r8a77970 (R-Car V3M) and r8a77995 (R-Car D3) compat strings.
+
+Based on work for r8a7796 by Magnus Damm.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+(cherry picked from commit 9327b810bb7e1f3322fe8ed862a62fe0f2c9f14b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+index 43cff3e449d0..1fd5d69647ca 100644
+--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
++++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+@@ -17,6 +17,8 @@ Required Properties:
+     - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
+     - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
+     - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
++    - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
++    - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
+     - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
+ 
+   - reg: Base address and size of the IPMMU registers.
+-- 
+2.19.0
+
diff --git a/patches/0429-iommu-ipmmu-vmsa-Remove-redundant-of_iommu_init_fn-h.patch b/patches/0429-iommu-ipmmu-vmsa-Remove-redundant-of_iommu_init_fn-h.patch
new file mode 100644
index 00000000000000..31f1d754df7602
--- /dev/null
+++ b/patches/0429-iommu-ipmmu-vmsa-Remove-redundant-of_iommu_init_fn-h.patch
@@ -0,0 +1,48 @@
+From 8bfebd2651ccc99bc7db7a01bcea3371e1b36076 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Tue, 9 Jan 2018 16:17:26 +0000
+Subject: [PATCH 0429/1795] iommu/ipmmu-vmsa: Remove redundant of_iommu_init_fn
+ hook
+
+Having of_iommu_init() call ipmmu_init() via ipmmu_vmsa_iommu_of_setup()
+does nothing that the subsys_initcall wouldn't do slightly later anyway,
+since probe-deferral of masters means it is no longer critical to
+register the driver super-early. Clean it up.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+(cherry picked from commit e7747d88e05eabed6fd921c3636a9d1f5b4f754f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/iommu/ipmmu-vmsa.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 8dce3a9de9d8..331dad909301 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -1108,18 +1108,8 @@ static void __exit ipmmu_exit(void)
+ subsys_initcall(ipmmu_init);
+ module_exit(ipmmu_exit);
+ 
+-#ifdef CONFIG_IOMMU_DMA
+-static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np)
+-{
+-	ipmmu_init();
+-	return 0;
+-}
+-
+-IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa",
+-		 ipmmu_vmsa_iommu_of_setup);
+-IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795",
+-		 ipmmu_vmsa_iommu_of_setup);
+-#endif
++IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa", NULL);
++IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795", NULL);
+ 
+ MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
+ MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
+-- 
+2.19.0
+
diff --git a/patches/0430-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-N.patch b/patches/0430-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-N.patch
new file mode 100644
index 00000000000000..4203db5f416179
--- /dev/null
+++ b/patches/0430-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-N.patch
@@ -0,0 +1,44 @@
+From 74ee9b182420b8b95dcdb1ad61da5d13ff62bb44 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 16:25:12 +0100
+Subject: [PATCH 0430/1795] dt-bindings/irqchip/renesas-irqc: Document R-Car
+ M3-N support
+
+Document support for the Interrupt Controller for Externel Devices
+(INTC-EX) in the Renesas M3-N (r8a77965) SoC.
+
+No driver update is needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: devicetree@vger.kernel.org
+Cc: Jason Cooper <jason@lakedaemon.net>
+Cc: Marc Zyngier <marc.zyngier@arm.com>
+Cc: linux-renesas-soc@vger.kernel.org
+Cc: Rob Herring <robh+dt@kernel.org>
+Link: https://lkml.kernel.org/r/1519658712-22910-1-git-send-email-geert%2Brenesas@glider.be
+
+(cherry picked from commit 7998a4ecc61fbef5547afd379b8953b526709dd2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/interrupt-controller/renesas,irqc.txt    | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+index 33c9a10fdc91..20f121daa910 100644
+--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
++++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+@@ -14,6 +14,7 @@ Required properties:
+     - "renesas,irqc-r8a7794" (R-Car E2)
+     - "renesas,intc-ex-r8a7795" (R-Car H3)
+     - "renesas,intc-ex-r8a7796" (R-Car M3-W)
++    - "renesas,intc-ex-r8a77965" (R-Car M3-N)
+     - "renesas,intc-ex-r8a77970" (R-Car V3M)
+     - "renesas,intc-ex-r8a77995" (R-Car D3)
+ - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+-- 
+2.19.0
+
diff --git a/patches/0431-PCI-Remove-PCI_REASSIGN_ALL_RSRC-use-on-arm-and-arm6.patch b/patches/0431-PCI-Remove-PCI_REASSIGN_ALL_RSRC-use-on-arm-and-arm6.patch
new file mode 100644
index 00000000000000..726e28f6441144
--- /dev/null
+++ b/patches/0431-PCI-Remove-PCI_REASSIGN_ALL_RSRC-use-on-arm-and-arm6.patch
@@ -0,0 +1,121 @@
+From 1ca9a01f5b8e699ee2569755e3f7ef17ba3c31cb Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Thu, 30 Nov 2017 11:21:57 -0600
+Subject: [PATCH 0431/1795] PCI: Remove PCI_REASSIGN_ALL_RSRC use on arm and
+ arm64
+
+On arm, PCI_REASSIGN_ALL_RSRC is used only in pcibios_assign_all_busses(),
+which helps decide whether to reconfigure bridge bus numbers.  It has
+nothing to do with BAR assignments.  On arm64 and powerpc,
+pcibios_assign_all_busses() tests PCI_REASSIGN_ALL_BUS, which makes more
+sense.
+
+Align arm with arm64 and powerpc, so they all use PCI_REASSIGN_ALL_BUS for
+pcibios_assign_all_busses().
+
+Remove PCI_REASSIGN_ALL_RSRC from the generic, Tegra, Versatile, and
+R-Car drivers.  These drivers are used only on arm or arm64, where
+PCI_REASSIGN_ALL_RSRC is not used after this change, so removing it
+should have no effect.
+
+No functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
+Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+(cherry picked from commit 7153884c088a9500f9379aeec877f3d4d4ec4fba)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/include/asm/pci.h         | 5 +----
+ arch/arm/kernel/bios32.c           | 2 +-
+ drivers/pci/host/pci-host-common.c | 2 +-
+ drivers/pci/host/pci-tegra.c       | 2 +-
+ drivers/pci/host/pci-versatile.c   | 2 +-
+ drivers/pci/host/pcie-rcar.c       | 2 +-
+ 6 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
+index 960d9dc4f380..1f0de808d111 100644
+--- a/arch/arm/include/asm/pci.h
++++ b/arch/arm/include/asm/pci.h
+@@ -10,10 +10,7 @@ extern unsigned long pcibios_min_io;
+ extern unsigned long pcibios_min_mem;
+ #define PCIBIOS_MIN_MEM pcibios_min_mem
+ 
+-static inline int pcibios_assign_all_busses(void)
+-{
+-	return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
+-}
++#define pcibios_assign_all_busses()	pci_has_flag(PCI_REASSIGN_ALL_BUS)
+ 
+ #ifdef CONFIG_PCI_DOMAINS
+ static inline int pci_proc_domain(struct pci_bus *bus)
+diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
+index 0cd0aefb3a8f..ed46ca69813d 100644
+--- a/arch/arm/kernel/bios32.c
++++ b/arch/arm/kernel/bios32.c
+@@ -527,7 +527,7 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
+ 	struct pci_sys_data *sys;
+ 	LIST_HEAD(head);
+ 
+-	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
++	pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ 	if (hw->preinit)
+ 		hw->preinit();
+ 	pcibios_init_hw(parent, hw, &head);
+diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/host/pci-host-common.c
+index 148896f73c06..eabaaa325bd2 100644
+--- a/drivers/pci/host/pci-host-common.c
++++ b/drivers/pci/host/pci-host-common.c
+@@ -142,7 +142,7 @@ int pci_host_common_probe(struct platform_device *pdev,
+ 
+ 	/* Do not reassign resources if probe only */
+ 	if (!pci_has_flag(PCI_PROBE_ONLY))
+-		pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
++		pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ 
+ 	list_splice_init(&resources, &bridge->windows);
+ 	bridge->dev.parent = dev;
+diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
+index 1987fec1f126..5c85bb3e39c4 100644
+--- a/drivers/pci/host/pci-tegra.c
++++ b/drivers/pci/host/pci-tegra.c
+@@ -2278,7 +2278,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
+ 
+ 	tegra_pcie_enable_ports(pcie);
+ 
+-	pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
++	pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ 	host->busnr = pcie->busn.start;
+ 	host->dev.parent = &pdev->dev;
+ 	host->ops = &tegra_pcie_ops;
+diff --git a/drivers/pci/host/pci-versatile.c b/drivers/pci/host/pci-versatile.c
+index aff4cfb555fb..286a79567207 100644
+--- a/drivers/pci/host/pci-versatile.c
++++ b/drivers/pci/host/pci-versatile.c
+@@ -202,7 +202,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
+ 	writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
+ 
+ 	pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
+-	pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
++	pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ 
+ 	list_splice_init(&pci_res, &bridge->windows);
+ 	bridge->dev.parent = dev;
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index bab9f24ae70b..0c8b19e6a4c8 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -459,7 +459,7 @@ static int rcar_pcie_enable(struct rcar_pcie *pcie)
+ 
+ 	rcar_pcie_setup(&bridge->windows, pcie);
+ 
+-	pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
++	pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ 
+ 	bridge->dev.parent = dev;
+ 	bridge->sysdata = pcie;
+-- 
+2.19.0
+
diff --git a/patches/0432-net-phy-micrel-Use-strlcpy-for-ethtool-get_strings.patch b/patches/0432-net-phy-micrel-Use-strlcpy-for-ethtool-get_strings.patch
new file mode 100644
index 00000000000000..29d6aa1ceced20
--- /dev/null
+++ b/patches/0432-net-phy-micrel-Use-strlcpy-for-ethtool-get_strings.patch
@@ -0,0 +1,40 @@
+From 9bf4836d8bfe1e2787f9ce8df62b9ddaf8a32556 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 2 Mar 2018 15:08:38 -0800
+Subject: [PATCH 0432/1795] net: phy: micrel: Use strlcpy() for
+ ethtool::get_strings
+
+Our statistics strings are allocated at initialization without being
+bound to a specific size, yet, we would copy ETH_GSTRING_LEN bytes using
+memcpy() which would create out of bounds accesses, this was flagged by
+KASAN. Replace this with strlcpy() to make sure we are bound the source
+buffer size and we also always NUL-terminate strings.
+
+Fixes: 2b2427d06426 ("phy: micrel: Add ethtool statistics counters")
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 55f53567afe5f0cd2fd9e006b174c08c31c466f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/micrel.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index 422ff6333c52..0bcb51cd95ca 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -664,8 +664,8 @@ static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
+ 	int i;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
+-		memcpy(data + i * ETH_GSTRING_LEN,
+-		       kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
++		strlcpy(data + i * ETH_GSTRING_LEN,
++			kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
+ 	}
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0433-ravb-kill-redundant-check-in-the-probe-method.patch b/patches/0433-ravb-kill-redundant-check-in-the-probe-method.patch
new file mode 100644
index 00000000000000..451e8cf08762b7
--- /dev/null
+++ b/patches/0433-ravb-kill-redundant-check-in-the-probe-method.patch
@@ -0,0 +1,37 @@
+From 4394fc44808a446efafe1ce41f8257114c0cedf7 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 31 Dec 2017 21:41:35 +0300
+Subject: [PATCH 0433/1795] ravb: kill redundant check in the probe() method
+
+Browsing thru the driver disassembly, I noticed that gcc was  able to
+figure  out  that the 'ndev' pointer is always non-NULL when calling
+free_netdev()  on the probe() method's  error path and  thus skip that
+redundant NULL check... gcc is smart, be like gcc! :-)
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 5d0c100c228b51ce2c14bdbc845ca446e0494689)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 98e82669d41d..1cc2c266fe9f 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -2181,8 +2181,7 @@ static int ravb_probe(struct platform_device *pdev)
+ 	if (chip_id != RCAR_GEN2)
+ 		ravb_ptp_stop(ndev);
+ out_release:
+-	if (ndev)
+-		free_netdev(ndev);
++	free_netdev(ndev);
+ 
+ 	pm_runtime_put(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0434-ravb-Remove-obsolete-explicit-clock-handling-for-WoL.patch b/patches/0434-ravb-Remove-obsolete-explicit-clock-handling-for-WoL.patch
new file mode 100644
index 00000000000000..fc84f5530c50c9
--- /dev/null
+++ b/patches/0434-ravb-Remove-obsolete-explicit-clock-handling-for-WoL.patch
@@ -0,0 +1,56 @@
+From bb222cc5d313a69bb037b8a0368f738e60fe4a0c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Feb 2018 14:40:00 +0100
+Subject: [PATCH 0434/1795] ravb: Remove obsolete explicit clock handling for
+ WoL
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, if Wake-on-LAN is enabled, the EtherAVB device's module clock
+is manually kept running during system suspend, to make sure the device
+stays active.
+
+Since commit 91c719f5ec6671f7 ("soc: renesas: rcar-sysc: Keep wakeup
+sources active during system suspend") , this workaround is no longer
+needed.  Hence remove all explicit clock handling to keep the device
+active.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit dd62c236c0fe1166d037485494ec5ff6545480eb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 1cc2c266fe9f..e38d25d981e3 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -2231,9 +2231,6 @@ static int ravb_wol_setup(struct net_device *ndev)
+ 	/* Enable MagicPacket */
+ 	ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
+ 
+-	/* Increased clock usage so device won't be suspended */
+-	clk_enable(priv->clk);
+-
+ 	return enable_irq_wake(priv->emac_irq);
+ }
+ 
+@@ -2252,9 +2249,6 @@ static int ravb_wol_restore(struct net_device *ndev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	/* Restore clock usage count */
+-	clk_disable(priv->clk);
+-
+ 	return disable_irq_wake(priv->emac_irq);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0435-DT-net-renesas-ravb-document-R8A77980-bindings.patch b/patches/0435-DT-net-renesas-ravb-document-R8A77980-bindings.patch
new file mode 100644
index 00000000000000..56111b3b76d80e
--- /dev/null
+++ b/patches/0435-DT-net-renesas-ravb-document-R8A77980-bindings.patch
@@ -0,0 +1,35 @@
+From e4a886d786ce255abbc3221fc66a2505bfbcc147 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 1 Feb 2018 23:13:45 +0300
+Subject: [PATCH 0435/1795] DT: net: renesas,ravb: document R8A77980 bindings
+
+Renesas R-Car V3H (R8A77980) SoC has the R-Car gen3 compatible EtherAVB
+device, so document the SoC specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 3a291aa11898bc9577c16339f108aac02ba0d109)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index c902261893b9..92fd4b2f17b2 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -18,6 +18,7 @@ Required properties:
+       - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+       - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+       - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
++      - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+       - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
+       - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ 		R-Car Gen3 devices.
+-- 
+2.19.0
+
diff --git a/patches/0436-dt-bindings-net-renesas-ravb-Make-stream-buffer-opti.patch b/patches/0436-dt-bindings-net-renesas-ravb-Make-stream-buffer-opti.patch
new file mode 100644
index 00000000000000..f4179fd9111bf7
--- /dev/null
+++ b/patches/0436-dt-bindings-net-renesas-ravb-Make-stream-buffer-opti.patch
@@ -0,0 +1,46 @@
+From 911eda488b798963cf87c26368eeb497862b9991 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 16:01:48 +0100
+Subject: [PATCH 0436/1795] dt-bindings: net: renesas-ravb: Make stream buffer
+ optional
+
+The Stream Buffer for EtherAVB-IF (STBE) is an optional component, and
+is not present on all SoCs.
+
+Document this in the DT bindings, including a list of SoCs that do have
+it.
+
+Fixes: 785ec87483d1e24a ("ravb: document R8A77970 bindings")
+Fixes: f231c4178a655b09 ("dt-bindings: net: renesas-ravb: Add support for R8A77995 RAVB")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 25b5cdfcce1b57971840505dfc78556bd12dea6d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index 92fd4b2f17b2..b4dc455eb155 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -27,7 +27,11 @@ Required properties:
+ 	SoC-specific version corresponding to the platform first followed by
+ 	the generic version.
+ 
+-- reg: offset and length of (1) the register block and (2) the stream buffer.
++- reg: Offset and length of (1) the register block and (2) the stream buffer.
++       The region for the register block is mandatory.
++       The region for the stream buffer is optional, as it is only present on
++       R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
++       and M3-N (R8A77965).
+ - interrupts: A list of interrupt-specifiers, one for each entry in
+ 	      interrupt-names.
+ 	      If interrupt-names is not present, an interrupt specifier
+-- 
+2.19.0
+
diff --git a/patches/0437-dt-bindings-can-rcar_can-document-r8a774-35-can-supp.patch b/patches/0437-dt-bindings-can-rcar_can-document-r8a774-35-can-supp.patch
new file mode 100644
index 00000000000000..e3a0172dc47111
--- /dev/null
+++ b/patches/0437-dt-bindings-can-rcar_can-document-r8a774-35-can-supp.patch
@@ -0,0 +1,48 @@
+From cff3f5acf09430590792756ba59706de212d90ff Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:42 +0000
+Subject: [PATCH 0437/1795] dt-bindings: can: rcar_can: document r8a774[35] can
+ support
+
+Document "renesas,can-r8a7743" and "renesas,can-r8a7745" compatible
+strings. Since the fallback compatible string ("renesas,rcar-gen2-can")
+activates the right code in the driver, no driver change is needed.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+(cherry picked from commit 216bf2f490c214b8a0702b52cc957138ba24bc3f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/can/rcar_can.txt | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
+index 06bb7cc334c8..94a7f33ac5e9 100644
+--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
++++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
+@@ -2,7 +2,9 @@ Renesas R-Car CAN controller Device Tree Bindings
+ -------------------------------------------------
+ 
+ Required properties:
+-- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
++- compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
++	      "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
++	      "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
+ 	      "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
+ 	      "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
+ 	      "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
+@@ -12,7 +14,8 @@ Required properties:
+ 	      "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
+ 	      "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
+ 	      "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
+-	      "renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device.
++	      "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1
++	      compatible device.
+ 	      "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
+ 	      When compatible with the generic version, nodes must list the
+ 	      SoC-specific version corresponding to the platform first
+-- 
+2.19.0
+
diff --git a/patches/0438-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch b/patches/0438-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch
new file mode 100644
index 00000000000000..6c50f6d8308159
--- /dev/null
+++ b/patches/0438-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch
@@ -0,0 +1,90 @@
+From a6e1e1c623a59c9b6f01a919ef8d103a08c128c1 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 17 Nov 2017 11:00:28 +0900
+Subject: [PATCH 0438/1795] dmaengine: rcar-dmac: ensure CHCR DE bit is
+ actually 0 after clearing
+
+DMAC reads data from source device, and buffered it until transferable
+size for sink device. Because of this behavior, DMAC is including
+buffered data .
+
+Now, CHCR DE bit is controlling DMA transfer enable/disable.
+
+If DE bit was cleared during data transferring, or during buffering,
+it will flush buffered data if source device was peripheral device
+(The buffered data will be removed if source device was memory).
+Because of this behavior, driver should ensure that DE bit is actually
+0 after clearing.
+
+This patch adds new rcar_dmac_chcr_de_barrier() and call it after CHCR
+register access.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+(cherry picked from commit a8d46a7f5d17ca9cbe9e9c7d1d23dc6ea437e141)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 9d6ce5051d8f..01818dc00d46 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -10,6 +10,7 @@
+  * published by the Free Software Foundation.
+  */
+ 
++#include <linux/delay.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/dmaengine.h>
+ #include <linux/interrupt.h>
+@@ -741,6 +742,24 @@ static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
+ /* -----------------------------------------------------------------------------
+  * Stop and reset
+  */
++static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
++{
++	u32 chcr;
++	unsigned int i;
++
++	/*
++	 * Ensure that the setting of the DE bit is actually 0 after
++	 * clearing it.
++	 */
++	for (i = 0; i < 1024; i++) {
++		chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
++		if (!(chcr & RCAR_DMACHCR_DE))
++			return;
++		udelay(1);
++	}
++
++	dev_err(chan->chan.device->dev, "CHCR DE check error\n");
++}
+ 
+ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+ {
+@@ -749,6 +768,7 @@ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+ 	chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
+ 		  RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
+ 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
++	rcar_dmac_chcr_de_barrier(chan);
+ }
+ 
+ static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
+@@ -1490,6 +1510,8 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
+ 	if (chcr & RCAR_DMACHCR_TE)
+ 		mask |= RCAR_DMACHCR_DE;
+ 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
++	if (mask & RCAR_DMACHCR_DE)
++		rcar_dmac_chcr_de_barrier(chan);
+ 
+ 	if (chcr & RCAR_DMACHCR_DSE)
+ 		ret |= rcar_dmac_isr_desc_stage_end(chan);
+-- 
+2.19.0
+
diff --git a/patches/0439-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch b/patches/0439-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch
new file mode 100644
index 00000000000000..f5aa8e9672c4b4
--- /dev/null
+++ b/patches/0439-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch
@@ -0,0 +1,112 @@
+From bcae7f43ca3f23210a7aba08fdc5112b74da1255 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 17 Nov 2017 02:09:32 +0000
+Subject: [PATCH 0439/1795] dmaengine: rcar-dmac: use TCRB instead of TCR for
+ residue
+
+SYS/RT/Audio DMAC includes independent data buffers for reading
+and writing. Therefore, the read transfer counter and write transfer
+counter have different values.
+TCR indicates read counter, and TCRB indicates write counter.
+The relationship is like below.
+
+	        TCR       TCRB
+	[SOURCE] -> [DMAC] -> [SINK]
+
+In the MEM_TO_DEV direction, what really matters is how much data has
+been written to the device. If the DMA is interrupted between read and
+write, then, the data doesn't end up in the destination, so shouldn't
+be counted. TCRB is thus the register we should use in this cases.
+
+In the DEV_TO_MEM direction, the situation is more complex. Both the
+read and write side are important. What matters from a data consumer
+point of view is how much data has been written to memory.
+On the other hand, if the transfer is interrupted between read and
+write, we'll end up losing data. It can also be important to report.
+
+In the MEM_TO_MEM direction, what matters is of course how much data
+has been written to memory from data consumer point of view.
+Here, because read and write have independent data buffers, it will
+take a while for TCR and TCRB to become equal. Thus we should check
+TCRB in this case, too.
+
+Thus, all cases we should check TCRB instead of TCR.
+
+Without this patch, Sound Capture has noise after PulseAudio support
+(= 07b7acb51d2 ("ASoC: rsnd: update pointer more accurate")), because
+the recorder will use wrong residue counter which indicates transferred
+from sound device, but in reality the data was not yet put to memory
+and recorder will record it.
+
+However, because DMAC is buffering data until it can be transferable
+size, TCRB might not be updated.
+For example, if consumer doesn't know how much data can be received,
+it requests enough size to DMAC. But in reality, it might receive very
+few data. In such case, DMAC just buffered it until transferable size,
+and no TCRB updated.
+
+In such case, this buffered data will be transferred if CHCR::DE bit was
+cleared, and this is happen if rcar_dmac_chan_halt(). In other word, it
+happen when consumer called dmaengine_terminate_all().
+
+Because of this behavior, it need to flush buffered data when it returns
+"residue" (= dmaengine_tx_status()).
+Otherwise, consumer might calculate wrong things if it called
+dmaengine_tx_status() and dmaengine_terminate_all() consecutively.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+(cherry picked from commit 73a47bd0da668c99f04e9076f2b02101a5b2749b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 22 +++++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 01818dc00d46..dfcf8a49c508 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -761,6 +761,23 @@ static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
+ 	dev_err(chan->chan.device->dev, "CHCR DE check error\n");
+ }
+ 
++static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
++{
++	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
++
++	if (!(chcr & RCAR_DMACHCR_DE))
++		return;
++
++	/* set DE=0 and flush remaining data */
++	rcar_dmac_chan_write(chan, RCAR_DMACHCR, (chcr & ~RCAR_DMACHCR_DE));
++
++	/* make sure all remaining data was flushed */
++	rcar_dmac_chcr_de_barrier(chan);
++
++	/* back DE */
++	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
++}
++
+ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+ {
+ 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+@@ -1338,8 +1355,11 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
+ 		residue += chunk->size;
+ 	}
+ 
++	if (desc->direction == DMA_DEV_TO_MEM)
++		rcar_dmac_sync_tcr(chan);
++
+ 	/* Add the residue for the current chunk. */
+-	residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift;
++	residue += rcar_dmac_chan_read(chan, RCAR_DMATCRB) << desc->xfer_shift;
+ 
+ 	return residue;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0440-dmaengine-rcar-dmac-Make-DMAC-reinit-during-system-r.patch b/patches/0440-dmaengine-rcar-dmac-Make-DMAC-reinit-during-system-r.patch
new file mode 100644
index 00000000000000..ded68d53938f33
--- /dev/null
+++ b/patches/0440-dmaengine-rcar-dmac-Make-DMAC-reinit-during-system-r.patch
@@ -0,0 +1,73 @@
+From 8a0ee2f2d70c52429cec06b81ce4ae04f45f4f88 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 17 Jan 2018 10:38:28 +0100
+Subject: [PATCH 0440/1795] dmaengine: rcar-dmac: Make DMAC reinit during
+ system resume explicit
+
+The current (empty) system sleep callbacks rely on the PM core to force
+a runtime resume to reinitialize the DMAC registers during system
+resume.  Without a reinitialization, e.g. SCIF DMA will hang silently
+after a system resume on R-Car Gen3.
+
+Make this explicit by using pm_runtime_force_{suspend,resume}() as the
+system sleep callbacks instead.  Use SET_LATE_SYSTEM_SLEEP_PM_OPS() as
+DMA engines must be initialized before all DMA slave devices.
+
+Fixes: 17218e0092f8 "PM / genpd: Stop/start devices without pm_runtime_force_suspend/resume()"
+Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit 1131b0a4af911de50b22239cabdf6dcd3f15df15)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 24 +++++++-----------------
+ 1 file changed, 7 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index dfcf8a49c508..ed8d934d5f48 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -1666,22 +1666,6 @@ static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec,
+  * Power management
+  */
+ 
+-#ifdef CONFIG_PM_SLEEP
+-static int rcar_dmac_sleep_suspend(struct device *dev)
+-{
+-	/*
+-	 * TODO: Wait for the current transfer to complete and stop the device.
+-	 */
+-	return 0;
+-}
+-
+-static int rcar_dmac_sleep_resume(struct device *dev)
+-{
+-	/* TODO: Resume transfers, if any. */
+-	return 0;
+-}
+-#endif
+-
+ #ifdef CONFIG_PM
+ static int rcar_dmac_runtime_suspend(struct device *dev)
+ {
+@@ -1697,7 +1681,13 @@ static int rcar_dmac_runtime_resume(struct device *dev)
+ #endif
+ 
+ static const struct dev_pm_ops rcar_dmac_pm = {
+-	SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume)
++	/*
++	 * TODO for system sleep/resume:
++	 *   - Wait for the current transfer to complete and stop the device,
++	 *   - Resume transfers, if any.
++	 */
++	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				     pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
+ 			   NULL)
+ };
+-- 
+2.19.0
+
diff --git a/patches/0441-dt-bindings-display-rcar-du-Document-R8A774-35-DU.patch b/patches/0441-dt-bindings-display-rcar-du-Document-R8A774-35-DU.patch
new file mode 100644
index 00000000000000..bca402a1ece843
--- /dev/null
+++ b/patches/0441-dt-bindings-display-rcar-du-Document-R8A774-35-DU.patch
@@ -0,0 +1,83 @@
+From 4859c7bc62c1fc26bbf71e7545cec30ffbca28fc Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 13 Oct 2017 16:22:19 +0100
+Subject: [PATCH 0441/1795] dt-bindings: display: rcar-du: Document R8A774[35]
+ DU
+
+Add device tree bindings for r8a7743 and r8a7745 DUs.
+r8a7743 DU is similar to the one from r8a7791, r8a7745 DU is similar
+to the one from r8a7794.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+[Don't reference R8A779[0123456] and R8A774[35] explicitly]
+[Number all DPAD, HDMI and LVDS ports]
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+(cherry picked from commit faf4a3ff36137aaa8de1a8da99a92f6e712903f1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/display/renesas,du.txt           | 30 +++++++++++--------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index 4bbd1e9bf3be..cd48aba3bc8c 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -3,6 +3,8 @@
+ Required Properties:
+ 
+   - compatible: must be one of the following.
++    - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
++    - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
+     - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
+     - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
+     - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
+@@ -27,10 +29,10 @@ Required Properties:
+   - clock-names: Name of the clocks. This property is model-dependent.
+     - R8A7779 uses a single functional clock. The clock doesn't need to be
+       named.
+-    - R8A779[0123456] use one functional clock per channel and one clock per
+-      LVDS encoder (if available). The functional clocks must be named "du.x"
+-      with "x" being the channel numerical index. The LVDS clocks must be
+-      named "lvds.x" with "x" being the LVDS encoder numerical index.
++    - All other DU instances use one functional clock per channel and one
++      clock per LVDS encoder (if available). The functional clocks must be
++      named "du.x" with "x" being the channel numerical index. The LVDS clocks
++      must be named "lvds.x" with "x" being the LVDS encoder numerical index.
+     - In addition to the functional and encoder clocks, all DU versions also
+       support externally supplied pixel clocks. Those clocks are optional.
+       When supplied they must be named "dclkin.x" with "x" being the input
+@@ -49,16 +51,18 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
+ The following table lists for each supported model the port number
+ corresponding to each DU output.
+ 
+-		Port 0		Port1		Port2		Port3
++                      Port0          Port1          Port2          Port3
+ -----------------------------------------------------------------------------
+- R8A7779 (H1)	DPAD 0		DPAD 1		-		-
+- R8A7790 (H2)	DPAD		LVDS 0		LVDS 1		-
+- R8A7791 (M2-W)	DPAD		LVDS 0		-		-
+- R8A7792 (V2H)	DPAD 0		DPAD 1		-		-
+- R8A7793 (M2-N)	DPAD		LVDS 0		-		-
+- R8A7794 (E2)	DPAD 0		DPAD 1		-		-
+- R8A7795 (H3)	DPAD		HDMI 0		HDMI 1		LVDS
+- R8A7796 (M3-W)	DPAD		HDMI		LVDS		-
++ R8A7743 (RZ/G1M)     DPAD 0         LVDS 0         -              -
++ R8A7745 (RZ/G1E)     DPAD 0         DPAD 1         -              -
++ R8A7779 (R-Car H1)   DPAD 0         DPAD 1         -              -
++ R8A7790 (R-Car H2)   DPAD 0         LVDS 0         LVDS 1         -
++ R8A7791 (R-Car M2-W) DPAD 0         LVDS 0         -              -
++ R8A7792 (R-Car V2H)  DPAD 0         DPAD 1         -              -
++ R8A7793 (R-Car M2-N) DPAD 0         LVDS 0         -              -
++ R8A7794 (R-Car E2)   DPAD 0         DPAD 1         -              -
++ R8A7795 (R-Car H3)   DPAD 0         HDMI 0         HDMI 1         LVDS 0
++ R8A7796 (R-Car M3-W) DPAD 0         HDMI 0         LVDS 0         -
+ 
+ 
+ Example: R8A7795 (R-Car H3) ES2.0 DU
+-- 
+2.19.0
+
diff --git a/patches/0442-drm-rcar-du-Add-R8A7743-support.patch b/patches/0442-drm-rcar-du-Add-R8A7743-support.patch
new file mode 100644
index 00000000000000..edf80627518a8d
--- /dev/null
+++ b/patches/0442-drm-rcar-du-Add-R8A7743-support.patch
@@ -0,0 +1,61 @@
+From 07084ee18d47e03cb5e7fb976cd1be040eccaffb Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 13 Oct 2017 16:22:20 +0100
+Subject: [PATCH 0442/1795] drm: rcar-du: Add R8A7743 support
+
+Add support for the R8A7743 DU (which is very similar to the R8A7791 DU);
+it has 1 DPAD (RGB) output and 1 LVDS output.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit 36a46da90212ddeeb78c2f902caaca264d8496a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index d2f29e6b1112..3db5e8df4ce6 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -34,6 +34,27 @@
+  * Device Information
+  */
+ 
++static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
++	.gen = 2,
++	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
++		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
++	.num_crtcs = 2,
++	.routes = {
++		/*
++		 * R8A7743 has one RGB output and one LVDS output
++		 */
++		[RCAR_DU_OUTPUT_DPAD0] = {
++			.possible_crtcs = BIT(1) | BIT(0),
++			.port = 0,
++		},
++		[RCAR_DU_OUTPUT_LVDS0] = {
++			.possible_crtcs = BIT(0),
++			.port = 1,
++		},
++	},
++	.num_lvds = 1,
++};
++
+ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
+ 	.gen = 2,
+ 	.features = 0,
+@@ -207,6 +228,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+ };
+ 
+ static const struct of_device_id rcar_du_of_table[] = {
++	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
+ 	{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
+ 	{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
+ 	{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
+-- 
+2.19.0
+
diff --git a/patches/0443-drm-rcar-du-Add-R8A7745-support.patch b/patches/0443-drm-rcar-du-Add-R8A7745-support.patch
new file mode 100644
index 00000000000000..e0f46f0342a45f
--- /dev/null
+++ b/patches/0443-drm-rcar-du-Add-R8A7745-support.patch
@@ -0,0 +1,61 @@
+From 04678e8faacd542164393a6ed01a998778240013 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 13 Oct 2017 16:22:22 +0100
+Subject: [PATCH 0443/1795] drm: rcar-du: Add R8A7745 support
+
+Add support for the R8A7745 DU (which is very similar to the R8A7794 DU);
+it has 2 RGB outputs.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit cdd90700157293dc7cb67d932b4f2fc44bd2a623)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index 3db5e8df4ce6..faa5b328986a 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -55,6 +55,27 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
+ 	.num_lvds = 1,
+ };
+ 
++static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
++	.gen = 2,
++	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
++		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
++	.num_crtcs = 2,
++	.routes = {
++		/*
++		 * R8A7745 has two RGB outputs
++		 */
++		[RCAR_DU_OUTPUT_DPAD0] = {
++			.possible_crtcs = BIT(0),
++			.port = 0,
++		},
++		[RCAR_DU_OUTPUT_DPAD1] = {
++			.possible_crtcs = BIT(1),
++			.port = 1,
++		},
++	},
++	.num_lvds = 0,
++};
++
+ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
+ 	.gen = 2,
+ 	.features = 0,
+@@ -229,6 +250,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+ 
+ static const struct of_device_id rcar_du_of_table[] = {
+ 	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
++	{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
+ 	{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
+ 	{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
+ 	{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
+-- 
+2.19.0
+
diff --git a/patches/0444-drm-rcar-du-Don-t-set-connector-DPMS-property.patch b/patches/0444-drm-rcar-du-Don-t-set-connector-DPMS-property.patch
new file mode 100644
index 00000000000000..ec10d7ad71ee68
--- /dev/null
+++ b/patches/0444-drm-rcar-du-Don-t-set-connector-DPMS-property.patch
@@ -0,0 +1,46 @@
+From 848186f058e2e86385e8a2508464df6b14806bfb Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 Aug 2017 15:36:19 +0300
+Subject: [PATCH 0444/1795] drm: rcar-du: Don't set connector DPMS property
+
+Since commit 4a97a3da420b ("drm: Don't update property values for atomic
+drivers") atomic drivers must not update property values as properties
+are read from the state instead. To catch remaining users, the
+drm_object_property_set_value() function now throws a warning when
+called by atomic drivers on non-immutable properties, and we hit that
+warning when creating connectors.
+
+The easy fix is to just remove the drm_object_property_set_value() as it
+is used here to set the initial value of the connector's DPMS property
+to OFF. The DPMS property applies on top of the connector's state crtc
+pointer (initialized to NULL) that is the main connector on/off control,
+and should thus default to ON.
+
+Fixes: 4a97a3da420b ("drm: Don't update property values for atomic drivers")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit e2f930aaa3519865bbdfa1a37d4974a717c1fa09)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+index b373ad48ef5f..e96f2df0c305 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+@@ -79,10 +79,6 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
+ 
+ 	drm_connector_helper_add(connector, &connector_helper_funcs);
+ 
+-	connector->dpms = DRM_MODE_DPMS_OFF;
+-	drm_object_property_set_value(&connector->base,
+-		rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF);
+-
+ 	ret = drm_mode_connector_attach_encoder(connector, encoder);
+ 	if (ret < 0)
+ 		return ret;
+-- 
+2.19.0
+
diff --git a/patches/0445-drm-rcar-du-Implement-system-suspend-resume-support.patch b/patches/0445-drm-rcar-du-Implement-system-suspend-resume-support.patch
new file mode 100644
index 00000000000000..c59edfaa03b680
--- /dev/null
+++ b/patches/0445-drm-rcar-du-Implement-system-suspend-resume-support.patch
@@ -0,0 +1,83 @@
+From 0de8e6c848876ba932158c6e4123460a4bb9b467 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 15 Sep 2017 17:42:06 +0100
+Subject: [PATCH 0445/1795] drm: rcar-du: Implement system suspend/resume
+ support
+
+To support system suspend operations we must ensure the hardware is
+stopped, and resumed explicitly from the suspend and resume handlers.
+
+Implement suspend and resume functions using the DRM atomic helper
+functions.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 7912dee7775e4c7590c227b4163bdb635bc50dd6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 18 +++++++++++++++---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.h |  1 +
+ 2 files changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index faa5b328986a..6e02c762a557 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -22,6 +22,7 @@
+ #include <linux/wait.h>
+ 
+ #include <drm/drmP.h>
++#include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
+@@ -309,9 +310,19 @@ static struct drm_driver rcar_du_driver = {
+ static int rcar_du_pm_suspend(struct device *dev)
+ {
+ 	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
++	struct drm_atomic_state *state;
+ 
+ 	drm_kms_helper_poll_disable(rcdu->ddev);
+-	/* TODO Suspend the CRTC */
++	drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true);
++
++	state = drm_atomic_helper_suspend(rcdu->ddev);
++	if (IS_ERR(state)) {
++		drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
++		drm_kms_helper_poll_enable(rcdu->ddev);
++		return PTR_ERR(state);
++	}
++
++	rcdu->suspend_state = state;
+ 
+ 	return 0;
+ }
+@@ -320,9 +331,10 @@ static int rcar_du_pm_resume(struct device *dev)
+ {
+ 	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
+ 
+-	/* TODO Resume the CRTC */
+-
++	drm_atomic_helper_resume(rcdu->ddev, rcdu->suspend_state);
++	drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
+ 	drm_kms_helper_poll_enable(rcdu->ddev);
++
+ 	return 0;
+ }
+ #endif
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+index f8cd79488ece..f400fde65a0c 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+@@ -81,6 +81,7 @@ struct rcar_du_device {
+ 
+ 	struct drm_device *ddev;
+ 	struct drm_fbdev_cma *fbdev;
++	struct drm_atomic_state *suspend_state;
+ 
+ 	struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS];
+ 	unsigned int num_crtcs;
+-- 
+2.19.0
+
diff --git a/patches/0446-drm-rcar-du-Remove-unused-CRTC-suspend-resume-functi.patch b/patches/0446-drm-rcar-du-Remove-unused-CRTC-suspend-resume-functi.patch
new file mode 100644
index 00000000000000..29b23d639157fc
--- /dev/null
+++ b/patches/0446-drm-rcar-du-Remove-unused-CRTC-suspend-resume-functi.patch
@@ -0,0 +1,70 @@
+From 33974b9dc235304e04e9858c4ae1965d37a54888 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 15 Sep 2017 17:42:07 +0100
+Subject: [PATCH 0446/1795] drm: rcar-du: Remove unused CRTC suspend/resume
+ functions
+
+An early implementation of suspend-resume helpers are available in the
+CRTC module, however they are unused and no longer needed.
+
+With suspend and resume handled by the core DRM atomic helpers, we can
+remove the unused functions.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit cf05f74ef40ed608e554f635799e831995213215)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 35 --------------------------
+ 1 file changed, 35 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index 301ea1a8018e..b492063a6e1f 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -557,41 +557,6 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
+ 	rcar_du_group_start_stop(rcrtc->group, false);
+ }
+ 
+-void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
+-{
+-	if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
+-		rcar_du_vsp_disable(rcrtc);
+-
+-	rcar_du_crtc_stop(rcrtc);
+-	rcar_du_crtc_put(rcrtc);
+-}
+-
+-void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
+-{
+-	unsigned int i;
+-
+-	if (!rcrtc->crtc.state->active)
+-		return;
+-
+-	rcar_du_crtc_get(rcrtc);
+-	rcar_du_crtc_setup(rcrtc);
+-
+-	/* Commit the planes state. */
+-	if (!rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) {
+-		for (i = 0; i < rcrtc->group->num_planes; ++i) {
+-			struct rcar_du_plane *plane = &rcrtc->group->planes[i];
+-
+-			if (plane->plane.state->crtc != &rcrtc->crtc)
+-				continue;
+-
+-			rcar_du_plane_setup(plane);
+-		}
+-	}
+-
+-	rcar_du_crtc_update_planes(rcrtc);
+-	rcar_du_crtc_start(rcrtc);
+-}
+-
+ /* -----------------------------------------------------------------------------
+  * CRTC Functions
+  */
+-- 
+2.19.0
+
diff --git a/patches/0447-drm-rcar-du-Share-plane-atomic-check-code-between-Ge.patch b/patches/0447-drm-rcar-du-Share-plane-atomic-check-code-between-Ge.patch
new file mode 100644
index 00000000000000..719f4a9fffc3ed
--- /dev/null
+++ b/patches/0447-drm-rcar-du-Share-plane-atomic-check-code-between-Ge.patch
@@ -0,0 +1,131 @@
+From 30c337e0d6f24d60ee3abfcd894e9a71d40c4304 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 Aug 2017 18:45:21 +0300
+Subject: [PATCH 0447/1795] drm: rcar-du: Share plane atomic check code between
+ Gen2 and Gen3
+
+The plane atomic check implementation is identical on Gen2 (DU planes)
+and Gen3 (VSP planes), but two separate functions exist as they operate
+on different data structures. Refactor the code to share the
+implementation.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+(cherry picked from commit 9c893a61b79d38b8997cc417a6b359222cf92414)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_plane.c | 27 ++++++++++++++++---------
+ drivers/gpu/drm/rcar-du/rcar_du_plane.h |  4 ++++
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c   | 22 +-------------------
+ 3 files changed, 22 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+index 61833cc1c699..4f076c364f25 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+@@ -565,27 +565,26 @@ void __rcar_du_plane_setup(struct rcar_du_group *rgrp,
+ 	}
+ }
+ 
+-static int rcar_du_plane_atomic_check(struct drm_plane *plane,
+-				      struct drm_plane_state *state)
++int __rcar_du_plane_atomic_check(struct drm_plane *plane,
++				 struct drm_plane_state *state,
++				 const struct rcar_du_format_info **format)
+ {
+-	struct rcar_du_plane_state *rstate = to_rcar_plane_state(state);
+-	struct rcar_du_plane *rplane = to_rcar_plane(plane);
+-	struct rcar_du_device *rcdu = rplane->group->dev;
++	struct drm_device *dev = plane->dev;
+ 
+ 	if (!state->fb || !state->crtc) {
+-		rstate->format = NULL;
++		*format = NULL;
+ 		return 0;
+ 	}
+ 
+ 	if (state->src_w >> 16 != state->crtc_w ||
+ 	    state->src_h >> 16 != state->crtc_h) {
+-		dev_dbg(rcdu->dev, "%s: scaling not supported\n", __func__);
++		dev_dbg(dev->dev, "%s: scaling not supported\n", __func__);
+ 		return -EINVAL;
+ 	}
+ 
+-	rstate->format = rcar_du_format_info(state->fb->format->format);
+-	if (rstate->format == NULL) {
+-		dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__,
++	*format = rcar_du_format_info(state->fb->format->format);
++	if (*format == NULL) {
++		dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
+ 			state->fb->format->format);
+ 		return -EINVAL;
+ 	}
+@@ -593,6 +592,14 @@ static int rcar_du_plane_atomic_check(struct drm_plane *plane,
+ 	return 0;
+ }
+ 
++static int rcar_du_plane_atomic_check(struct drm_plane *plane,
++				      struct drm_plane_state *state)
++{
++	struct rcar_du_plane_state *rstate = to_rcar_plane_state(state);
++
++	return __rcar_du_plane_atomic_check(plane, state, &rstate->format);
++}
++
+ static void rcar_du_plane_atomic_update(struct drm_plane *plane,
+ 					struct drm_plane_state *old_state)
+ {
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+index f62e09f195de..890321b4665d 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+@@ -73,6 +73,10 @@ to_rcar_plane_state(struct drm_plane_state *state)
+ int rcar_du_atomic_check_planes(struct drm_device *dev,
+ 				struct drm_atomic_state *state);
+ 
++int __rcar_du_plane_atomic_check(struct drm_plane *plane,
++				 struct drm_plane_state *state,
++				 const struct rcar_du_format_info **format);
++
+ int rcar_du_planes_init(struct rcar_du_group *rgrp);
+ 
+ void __rcar_du_plane_setup(struct rcar_du_group *rgrp,
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index 2c96147bc444..dd66dcb8da23 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -268,28 +268,8 @@ static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
+ 					  struct drm_plane_state *state)
+ {
+ 	struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
+-	struct rcar_du_vsp_plane *rplane = to_rcar_vsp_plane(plane);
+-	struct rcar_du_device *rcdu = rplane->vsp->dev;
+-
+-	if (!state->fb || !state->crtc) {
+-		rstate->format = NULL;
+-		return 0;
+-	}
+ 
+-	if (state->src_w >> 16 != state->crtc_w ||
+-	    state->src_h >> 16 != state->crtc_h) {
+-		dev_dbg(rcdu->dev, "%s: scaling not supported\n", __func__);
+-		return -EINVAL;
+-	}
+-
+-	rstate->format = rcar_du_format_info(state->fb->format->format);
+-	if (rstate->format == NULL) {
+-		dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__,
+-			state->fb->format->format);
+-		return -EINVAL;
+-	}
+-
+-	return 0;
++	return __rcar_du_plane_atomic_check(plane, state, &rstate->format);
+ }
+ 
+ static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
+-- 
+2.19.0
+
diff --git a/patches/0448-dt-bindings-thermal-rcar-Add-device-tree-support-for.patch b/patches/0448-dt-bindings-thermal-rcar-Add-device-tree-support-for.patch
new file mode 100644
index 00000000000000..f05102ad850ef2
--- /dev/null
+++ b/patches/0448-dt-bindings-thermal-rcar-Add-device-tree-support-for.patch
@@ -0,0 +1,40 @@
+From 8975d887aab330282d0396b02298f415f7ab73a1 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:17:28 +0000
+Subject: [PATCH 0448/1795] dt-bindings: thermal: rcar: Add device tree support
+ for r8a7743
+
+Add thermal sensor support for r8a7743 SoC. The Renesas RZ/G1M
+(r8a7743) thermal sensor module is identical to the R-Car Gen2 family.
+
+No driver change is needed due to the fallback compatible value
+"renesas,rcar-gen2-thermal".
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <simon.horman@netronome.com>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 2d14a0ee5e73d5224873777892fd86d3a283b059)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+index a8e52c8ccfcc..349e635f2d87 100644
+--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
++++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+@@ -6,6 +6,7 @@ Required properties:
+ 			   "renesas,rcar-thermal" (without thermal-zone) as fallback.
+ 			  Examples with soctypes are:
+ 			    - "renesas,thermal-r8a73a4" (R-Mobile APE6)
++			    - "renesas,thermal-r8a7743" (RZ/G1M)
+ 			    - "renesas,thermal-r8a7779" (R-Car H1)
+ 			    - "renesas,thermal-r8a7790" (R-Car H2)
+ 			    - "renesas,thermal-r8a7791" (R-Car M2-W)
+-- 
+2.19.0
+
diff --git a/patches/0449-mmc-tmio-use-usleep_range-consistently.patch b/patches/0449-mmc-tmio-use-usleep_range-consistently.patch
new file mode 100644
index 00000000000000..c0ee5a1d1c2d04
--- /dev/null
+++ b/patches/0449-mmc-tmio-use-usleep_range-consistently.patch
@@ -0,0 +1,60 @@
+From 8ac35c08e71ead0d78a77f77c2fbe5292081cd41 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 14 Nov 2017 23:51:04 +0100
+Subject: [PATCH 0449/1795] mmc: tmio: use usleep_range consistently
+
+There are a few udelay() left which are in a range that they should be
+usleep_range() these days.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 754febcc6b749bb05ebb06b0b9cfdda6157e8cfd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 62217afb51d6..36301e385006 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -806,7 +806,7 @@ static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
+ 		if (ret == 0)
+ 			set_bit(i, host->taps);
+ 
+-		mdelay(1);
++		usleep_range(1000, 1200);
+ 	}
+ 
+ 	ret = host->select_tuning(host);
+@@ -958,7 +958,7 @@ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
+ 		 * 100us were not enough. Is this the same 140us delay, as in
+ 		 * tmio_mmc_set_ios()?
+ 		 */
+-		udelay(200);
++		usleep_range(200, 300);
+ 	}
+ 	/*
+ 	 * It seems, VccQ should be switched on after Vcc, this is also what the
+@@ -966,7 +966,7 @@ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
+ 	 */
+ 	if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
+ 		ret = regulator_enable(mmc->supply.vqmmc);
+-		udelay(200);
++		usleep_range(200, 300);
+ 	}
+ 
+ 	if (ret < 0)
+@@ -1059,7 +1059,7 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ 	}
+ 
+ 	/* Let things settle. delay taken from winCE driver */
+-	udelay(140);
++	usleep_range(140, 200);
+ 	if (PTR_ERR(host->mrq) == -EINTR)
+ 		dev_dbg(&host->pdev->dev,
+ 			"%s.%d: IOS interrupted: clk %u, mode %u",
+-- 
+2.19.0
+
diff --git a/patches/0450-dt-bindings-mmc-renesas_sdhi-Add-r8a77995-support.patch b/patches/0450-dt-bindings-mmc-renesas_sdhi-Add-r8a77995-support.patch
new file mode 100644
index 00000000000000..4021d2f8bd3f63
--- /dev/null
+++ b/patches/0450-dt-bindings-mmc-renesas_sdhi-Add-r8a77995-support.patch
@@ -0,0 +1,34 @@
+From 982e0dcfbb153784cd0a7bdba083b0ec669b0e0d Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 15 Nov 2017 16:25:49 +0100
+Subject: [PATCH 0450/1795] dt-bindings: mmc: renesas_sdhi: Add r8a77995
+ support
+
+Adds bindings for the R-Car D3 SoC's SDHI IP.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 448f2f8775d1e8a62a14506b6da38bcedce5eb22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index 3c6762430fd9..d8685cb83325 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -26,6 +26,7 @@ Required properties:
+ 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
+ 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
+ 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
++		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
+ 		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
+ 		"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
+ 		"renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 or RZ/G1
+-- 
+2.19.0
+
diff --git a/patches/0451-mmc-renesas_sdhi-enable-R-Car-D3-r8a77995-support.patch b/patches/0451-mmc-renesas_sdhi-enable-R-Car-D3-r8a77995-support.patch
new file mode 100644
index 00000000000000..eb8169b9738f1f
--- /dev/null
+++ b/patches/0451-mmc-renesas_sdhi-enable-R-Car-D3-r8a77995-support.patch
@@ -0,0 +1,34 @@
+From 08930bda94c5c672bde8a903a82bd3abfa7a16ed Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 29 Nov 2017 17:06:45 +0100
+Subject: [PATCH 0451/1795] mmc: renesas_sdhi: enable R-Car D3 (r8a77995)
+ support
+
+Whitelists for internal DMAC implementation.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit c14e60963ec1e0595250955271abfe4d5e96b3cb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 4c20d368f515..227d613aa250 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -255,6 +255,7 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
+         { .soc_id = "r8a7795", .revision = "ES1.*" },
+         { .soc_id = "r8a7795", .revision = "ES2.0" },
+         { .soc_id = "r8a7796", .revision = "ES1.0" },
++        { .soc_id = "r8a77995", .revision = "ES1.0" },
+         { /* sentinel */ }
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0452-mmc-tmio-use-ioread-for-repeated-access-to-a-registe.patch b/patches/0452-mmc-tmio-use-ioread-for-repeated-access-to-a-registe.patch
new file mode 100644
index 00000000000000..4c68ebdd1ce651
--- /dev/null
+++ b/patches/0452-mmc-tmio-use-ioread-for-repeated-access-to-a-registe.patch
@@ -0,0 +1,62 @@
+From f3463f9dd8b78f57519a989a954a2b8513be5875 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 01:00:21 +0100
+Subject: [PATCH 0452/1795] mmc: tmio: use ioread* for repeated access to a
+ register
+
+Not all archs define reads* and writes*. Switch to ioread*_rep and
+friends which is defined everywhere, so we can enable COMPILE_TEST after
+that.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 0c36fc0dfb4c0fa068d077b9e2806ef87d0221a7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc.h | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index 3e6ff8921440..cd3d7c8d24bf 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -246,7 +246,7 @@ static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
+ static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
+ 				      u16 *buf, int count)
+ {
+-	readsw(host->ctl + (addr << host->bus_shift), buf, count);
++	ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
+ }
+ 
+ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
+@@ -259,7 +259,7 @@ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
+ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
+ 				      u32 *buf, int count)
+ {
+-	readsl(host->ctl + (addr << host->bus_shift), buf, count);
++	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
+ }
+ 
+ static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
+@@ -276,7 +276,7 @@ static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
+ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
+ 				       u16 *buf, int count)
+ {
+-	writesw(host->ctl + (addr << host->bus_shift), buf, count);
++	iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
+ }
+ 
+ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
+@@ -289,7 +289,7 @@ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
+ static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
+ 				       const u32 *buf, int count)
+ {
+-	writesl(host->ctl + (addr << host->bus_shift), buf, count);
++	iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
+ }
+ 
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0453-mmc-renesas_sdhi-remove-eprobe-jump-label.patch b/patches/0453-mmc-renesas_sdhi-remove-eprobe-jump-label.patch
new file mode 100644
index 00000000000000..bd44c2967328bb
--- /dev/null
+++ b/patches/0453-mmc-renesas_sdhi-remove-eprobe-jump-label.patch
@@ -0,0 +1,55 @@
+From 63aae89b0c34a32139dc4428fba416839196b34b Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:38 +0900
+Subject: [PATCH 0453/1795] mmc: renesas_sdhi: remove eprobe jump label
+
+"goto eprobe" does nothing.  Return directly.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 4ce6281791676c134d3ae919edaf76da3cef1d76)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 157e1d9e7725..2daca2b1066f 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -498,7 +498,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	if (IS_ERR(priv->clk)) {
+ 		ret = PTR_ERR(priv->clk);
+ 		dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
+-		goto eprobe;
++		return ret;
+ 	}
+ 
+ 	/*
+@@ -525,10 +525,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	}
+ 
+ 	host = tmio_mmc_host_alloc(pdev);
+-	if (!host) {
+-		ret = -ENOMEM;
+-		goto eprobe;
+-	}
++	if (!host)
++		return -ENOMEM;
+ 
+ 	if (of_data) {
+ 		mmc_data->flags |= of_data->tmio_flags;
+@@ -653,7 +651,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	tmio_mmc_host_remove(host);
+ efree:
+ 	tmio_mmc_host_free(host);
+-eprobe:
++
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
+-- 
+2.19.0
+
diff --git a/patches/0454-mmc-tmio-set-tmio_mmc_host-to-driver-data.patch b/patches/0454-mmc-tmio-set-tmio_mmc_host-to-driver-data.patch
new file mode 100644
index 00000000000000..a91dd7434569d5
--- /dev/null
+++ b/patches/0454-mmc-tmio-set-tmio_mmc_host-to-driver-data.patch
@@ -0,0 +1,95 @@
+From ae430a31f1934f47156894891e8e05d521d03ffb Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:39 +0900
+Subject: [PATCH 0454/1795] mmc: tmio: set tmio_mmc_host to driver data
+
+The remove, suspend, resume hooks need to get tmio_mmc_host.  It is
+tedious to call mmc_priv() to convert mmc_host to tmio_mmc_host.
+We can directly set tmio_mmc_host to driver data.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit a3b05373e0e06dcb04adf2c50b58cd3feb5f8294)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c |  3 +--
+ drivers/mmc/host/tmio_mmc.c          | 12 ++++--------
+ drivers/mmc/host/tmio_mmc_core.c     |  8 +++-----
+ 3 files changed, 8 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 2daca2b1066f..15845893500b 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -658,8 +658,7 @@ EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
+ 
+ int renesas_sdhi_remove(struct platform_device *pdev)
+ {
+-	struct mmc_host *mmc = platform_get_drvdata(pdev);
+-	struct tmio_mmc_host *host = mmc_priv(mmc);
++	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
+ 
+ 	tmio_mmc_host_remove(host);
+ 
+diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
+index 64b7e9f18361..ccfbc154ee5b 100644
+--- a/drivers/mmc/host/tmio_mmc.c
++++ b/drivers/mmc/host/tmio_mmc.c
+@@ -128,15 +128,11 @@ static int tmio_mmc_probe(struct platform_device *pdev)
+ static int tmio_mmc_remove(struct platform_device *pdev)
+ {
+ 	const struct mfd_cell *cell = mfd_get_cell(pdev);
+-	struct mmc_host *mmc = platform_get_drvdata(pdev);
++	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
+ 
+-	if (mmc) {
+-		struct tmio_mmc_host *host = mmc_priv(mmc);
+-
+-		tmio_mmc_host_remove(host);
+-		if (cell->disable)
+-			cell->disable(pdev);
+-	}
++	tmio_mmc_host_remove(host);
++	if (cell->disable)
++		cell->disable(pdev);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 36301e385006..58947a73c65f 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1193,7 +1193,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 		return ret;
+ 
+ 	_host->pdata = pdata;
+-	platform_set_drvdata(pdev, mmc);
++	platform_set_drvdata(pdev, _host);
+ 
+ 	_host->set_pwr = pdata->set_pwr;
+ 	_host->set_clk_div = pdata->set_clk_div;
+@@ -1351,8 +1351,7 @@ EXPORT_SYMBOL_GPL(tmio_mmc_host_remove);
+ #ifdef CONFIG_PM
+ int tmio_mmc_host_runtime_suspend(struct device *dev)
+ {
+-	struct mmc_host *mmc = dev_get_drvdata(dev);
+-	struct tmio_mmc_host *host = mmc_priv(mmc);
++	struct tmio_mmc_host *host = dev_get_drvdata(dev);
+ 
+ 	tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
+ 
+@@ -1372,8 +1371,7 @@ static bool tmio_mmc_can_retune(struct tmio_mmc_host *host)
+ 
+ int tmio_mmc_host_runtime_resume(struct device *dev)
+ {
+-	struct mmc_host *mmc = dev_get_drvdata(dev);
+-	struct tmio_mmc_host *host = mmc_priv(mmc);
++	struct tmio_mmc_host *host = dev_get_drvdata(dev);
+ 
+ 	tmio_mmc_reset(host);
+ 	tmio_mmc_clk_enable(host);
+-- 
+2.19.0
+
diff --git a/patches/0455-mmc-tmio-use-devm_ioremap_resource-instead-of-devm_i.patch b/patches/0455-mmc-tmio-use-devm_ioremap_resource-instead-of-devm_i.patch
new file mode 100644
index 00000000000000..c36bf236590c2e
--- /dev/null
+++ b/patches/0455-mmc-tmio-use-devm_ioremap_resource-instead-of-devm_i.patch
@@ -0,0 +1,51 @@
+From c8e129b03794916337b98962613dc6c9cfb7c784 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:40 +0900
+Subject: [PATCH 0455/1795] mmc: tmio: use devm_ioremap_resource() instead of
+ devm_ioremap()
+
+The TMIO core misses to call request_mem_region().
+devm_ioremap_resource() takes care of it and makes the code cleaner.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 4139696b7978d57ec840b6c9293d4709a46af3bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 58947a73c65f..f6f47e1ce6dd 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1185,8 +1185,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 		_host->write16_hook = NULL;
+ 
+ 	res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	if (!res_ctl)
+-		return -EINVAL;
++	_host->ctl = devm_ioremap_resource(&pdev->dev, res_ctl);
++	if (IS_ERR(_host->ctl))
++		return PTR_ERR(_host->ctl);
+ 
+ 	ret = mmc_of_parse(mmc);
+ 	if (ret < 0)
+@@ -1202,11 +1203,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	_host->ctl = devm_ioremap(&pdev->dev,
+-				  res_ctl->start, resource_size(res_ctl));
+-	if (!_host->ctl)
+-		return -ENOMEM;
+-
+ 	tmio_mmc_ops.card_busy = _host->card_busy;
+ 	tmio_mmc_ops.start_signal_voltage_switch =
+ 		_host->start_signal_voltage_switch;
+-- 
+2.19.0
+
diff --git a/patches/0456-mmc-tmio-move-mmc_host_ops-to-struct-tmio_mmc_host-f.patch b/patches/0456-mmc-tmio-move-mmc_host_ops-to-struct-tmio_mmc_host-f.patch
new file mode 100644
index 00000000000000..1fa94d4cee1937
--- /dev/null
+++ b/patches/0456-mmc-tmio-move-mmc_host_ops-to-struct-tmio_mmc_host-f.patch
@@ -0,0 +1,78 @@
+From a371362459262d700c37096c53907f39f41302d3 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:41 +0900
+Subject: [PATCH 0456/1795] mmc: tmio: move mmc_host_ops to struct
+ tmio_mmc_host from static data
+
+Currently, tmio_mmc_ops is static data and tmio_mmc_host_probe()
+updates some hooks in the static data.  This is a problem when
+two or more instances call tmio_mmc_host_probe() and each of them
+requests to use its own card_busy/start_signal_voltage_switch.
+
+We can borrow a solution from sdhci_alloc_host().  Copy the whole
+ops structure to host->mmc_host_ops, then override the hooks in
+malloc'ed data.  Constify tmio_mmc_ops since it is now a template
+ops used by default.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit c055fc75c1757b220108489038cfe60496b13865)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc.h      | 1 +
+ drivers/mmc/host/tmio_mmc_core.c | 9 +++++----
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index cd3d7c8d24bf..405547f88421 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -134,6 +134,7 @@ struct tmio_mmc_host {
+ 	struct mmc_request      *mrq;
+ 	struct mmc_data         *data;
+ 	struct mmc_host         *mmc;
++	struct mmc_host_ops     ops;
+ 
+ 	/* Callbacks for clock / power control */
+ 	void (*set_pwr)(struct platform_device *host, int state);
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index f6f47e1ce6dd..5d80055b4bb3 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1098,7 +1098,7 @@ static int tmio_multi_io_quirk(struct mmc_card *card,
+ 	return blk_size;
+ }
+ 
+-static struct mmc_host_ops tmio_mmc_ops = {
++static const struct mmc_host_ops tmio_mmc_ops = {
+ 	.request	= tmio_mmc_request,
+ 	.set_ios	= tmio_mmc_set_ios,
+ 	.get_ro         = tmio_mmc_get_ro,
+@@ -1158,6 +1158,8 @@ tmio_mmc_host_alloc(struct platform_device *pdev)
+ 	host = mmc_priv(mmc);
+ 	host->mmc = mmc;
+ 	host->pdev = pdev;
++	host->ops = tmio_mmc_ops;
++	mmc->ops = &host->ops;
+ 
+ 	return host;
+ }
+@@ -1203,10 +1205,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	tmio_mmc_ops.card_busy = _host->card_busy;
+-	tmio_mmc_ops.start_signal_voltage_switch =
++	_host->ops.card_busy = _host->card_busy;
++	_host->ops.start_signal_voltage_switch =
+ 		_host->start_signal_voltage_switch;
+-	mmc->ops = &tmio_mmc_ops;
+ 
+ 	mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
+ 	mmc->caps2 |= pdata->capabilities2;
+-- 
+2.19.0
+
diff --git a/patches/0457-mmc-tmio-renesas_sdhi-set-mmc_host_ops-hooks-directl.patch b/patches/0457-mmc-tmio-renesas_sdhi-set-mmc_host_ops-hooks-directl.patch
new file mode 100644
index 00000000000000..af983e8e51f119
--- /dev/null
+++ b/patches/0457-mmc-tmio-renesas_sdhi-set-mmc_host_ops-hooks-directl.patch
@@ -0,0 +1,69 @@
+From cf5e43a6fe85dc7d230dae0f2edc5ce16ca45335 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:42 +0900
+Subject: [PATCH 0457/1795] mmc: tmio, renesas_sdhi: set mmc_host_ops hooks
+ directly
+
+Drivers can set any mmc_host_ops hooks between tmio_mmc_host_alloc()
+and tmio_mmc_host_probe().  Remove duplicated hooks in tmio_mmc_host.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 2aaa3c5193db9cdfe62201aa4eb4e1007a43fdc8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c | 4 ++--
+ drivers/mmc/host/tmio_mmc.h          | 3 ---
+ drivers/mmc/host/tmio_mmc_core.c     | 4 ----
+ 3 files changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 15845893500b..ae8099690b1a 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -550,8 +550,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	/* SDR speeds are only available on Gen2+ */
+ 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
+ 		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
+-		host->card_busy	= renesas_sdhi_card_busy;
+-		host->start_signal_voltage_switch =
++		host->ops.card_busy = renesas_sdhi_card_busy;
++		host->ops.start_signal_voltage_switch =
+ 			renesas_sdhi_start_signal_voltage_switch;
+ 	}
+ 
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index 405547f88421..dd40b9631b3a 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -186,9 +186,6 @@ struct tmio_mmc_host {
+ 	void (*clk_disable)(struct tmio_mmc_host *host);
+ 	int (*multi_io_quirk)(struct mmc_card *card,
+ 			      unsigned int direction, int blk_size);
+-	int (*card_busy)(struct mmc_host *mmc);
+-	int (*start_signal_voltage_switch)(struct mmc_host *mmc,
+-					   struct mmc_ios *ios);
+ 	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
+ 	void (*hw_reset)(struct tmio_mmc_host *host);
+ 	void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 5d80055b4bb3..8101ca2ca5a9 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1205,10 +1205,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	_host->ops.card_busy = _host->card_busy;
+-	_host->ops.start_signal_voltage_switch =
+-		_host->start_signal_voltage_switch;
+-
+ 	mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
+ 	mmc->caps2 |= pdata->capabilities2;
+ 	mmc->max_segs = pdata->max_segs ? : 32;
+-- 
+2.19.0
+
diff --git a/patches/0458-mmc-tmio-move-mmc_gpio_request_cd-before-mmc_add_hos.patch b/patches/0458-mmc-tmio-move-mmc_gpio_request_cd-before-mmc_add_hos.patch
new file mode 100644
index 00000000000000..fcfce2a818a709
--- /dev/null
+++ b/patches/0458-mmc-tmio-move-mmc_gpio_request_cd-before-mmc_add_hos.patch
@@ -0,0 +1,55 @@
+From 7973e911d4d74aada0a908f39f0d88631baf592d Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:43 +0900
+Subject: [PATCH 0458/1795] mmc: tmio: move mmc_gpio_request_cd() before
+ mmc_add_host()
+
+Drivers do not need to call mmc_gpiod_request_cd_irq() explicitly
+because mmc_start_host() calls it.  To make it work, cd_gpio must
+be set before mmc_add_host().
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit cd82cd213bfa532ca368e4333ba6a0f14185ef9c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 14 ++++++--------
+ 1 file changed, 6 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 8101ca2ca5a9..61eac261d3de 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1205,6 +1205,12 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (ret < 0)
+ 		return ret;
+ 
++	if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
++		ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
++		if (ret)
++			return ret;
++	}
++
+ 	mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
+ 	mmc->caps2 |= pdata->capabilities2;
+ 	mmc->max_segs = pdata->max_segs ? : 32;
+@@ -1300,14 +1306,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 
+ 	dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
+ 
+-	if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
+-		ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
+-		if (ret)
+-			goto remove_host;
+-
+-		mmc_gpiod_request_cd_irq(mmc);
+-	}
+-
+ 	return 0;
+ 
+ remove_host:
+-- 
+2.19.0
+
diff --git a/patches/0459-mmc-renesas_sdhi-remove-always-false-condition.patch b/patches/0459-mmc-renesas_sdhi-remove-always-false-condition.patch
new file mode 100644
index 00000000000000..c04e5ca3a5e9d6
--- /dev/null
+++ b/patches/0459-mmc-renesas_sdhi-remove-always-false-condition.patch
@@ -0,0 +1,39 @@
+From dcec28bb471dc3e99bae538472f439623d070607 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:46 +0900
+Subject: [PATCH 0459/1795] mmc: renesas_sdhi: remove always false condition
+
+renesas_sdhi_probe() always sets host->dma as follows:
+
+        host->dma               = dma_priv;
+
+!host->dma is always false.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 2487e7efc9e13bd11fdc86f1ac12a5a45c4af778)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index 9ab10436e4b8..e210644f1116 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -360,8 +360,8 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 					      struct tmio_mmc_data *pdata)
+ {
+ 	/* We can only either use DMA for both Tx and Rx or not use it at all */
+-	if (!host->dma || (!host->pdev->dev.of_node &&
+-			   (!pdata->chan_priv_tx || !pdata->chan_priv_rx)))
++	if (!host->pdev->dev.of_node &&
++	    (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
+ 		return;
+ 
+ 	if (!host->chan_tx && !host->chan_rx) {
+-- 
+2.19.0
+
diff --git a/patches/0460-mmc-tmio-renesas_sdhi-move-struct-tmio_mmc_dma-to-re.patch b/patches/0460-mmc-tmio-renesas_sdhi-move-struct-tmio_mmc_dma-to-re.patch
new file mode 100644
index 00000000000000..30890ccaa1d52a
--- /dev/null
+++ b/patches/0460-mmc-tmio-renesas_sdhi-move-struct-tmio_mmc_dma-to-re.patch
@@ -0,0 +1,207 @@
+From 5863d8232a4cdaa798360e011da0fa2b8a9c21da Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:47 +0900
+Subject: [PATCH 0460/1795] mmc: tmio, renesas_sdhi: move struct tmio_mmc_dma
+ to renesas_sdhi.h
+
+struct tmio_mmc_dma looks like TMIO core data, but in fact, Renesas
+private data.  Move it to renesas_sdhi.h (probably, it is better to
+rename it to renesas_sdhi_dma, or squash it into struct renesas_sdhi).
+
+I also moved struct renesas_sdhi and host_to_priv() to that header
+because they are necessary to convert the tmio_mmc_host pointer into
+the renesas_sdhi pointer.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 058db2868cd88b5474f26974253407fcbe932c22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi.h               | 19 +++++++++++++++++++
+ drivers/mmc/host/renesas_sdhi_core.c          | 14 --------------
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c |  6 ++++--
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 16 ++++++++++------
+ drivers/mmc/host/tmio_mmc.h                   |  7 -------
+ 5 files changed, 33 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
+index b9dfea5d8193..9a507b3a9838 100644
+--- a/drivers/mmc/host/renesas_sdhi.h
++++ b/drivers/mmc/host/renesas_sdhi.h
+@@ -35,6 +35,25 @@ struct renesas_sdhi_of_data {
+ 	unsigned short max_segs;
+ };
+ 
++struct tmio_mmc_dma {
++	enum dma_slave_buswidth dma_buswidth;
++	bool (*filter)(struct dma_chan *chan, void *arg);
++	void (*enable)(struct tmio_mmc_host *host, bool enable);
++};
++
++struct renesas_sdhi {
++	struct clk *clk;
++	struct clk *clk_cd;
++	struct tmio_mmc_data mmc_data;
++	struct tmio_mmc_dma dma_priv;
++	struct pinctrl *pinctrl;
++	struct pinctrl_state *pins_default, *pins_uhs;
++	void __iomem *scc_ctl;
++};
++
++#define host_to_priv(host) \
++	container_of((host)->pdata, struct renesas_sdhi, mmc_data)
++
+ int renesas_sdhi_probe(struct platform_device *pdev,
+ 		       const struct tmio_mmc_dma_ops *dma_ops);
+ int renesas_sdhi_remove(struct platform_device *pdev);
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index ae8099690b1a..0eb62353630f 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -47,19 +47,6 @@
+ #define SDHI_VER_GEN3_SD	0xcc10
+ #define SDHI_VER_GEN3_SDMMC	0xcd10
+ 
+-#define host_to_priv(host) \
+-	container_of((host)->pdata, struct renesas_sdhi, mmc_data)
+-
+-struct renesas_sdhi {
+-	struct clk *clk;
+-	struct clk *clk_cd;
+-	struct tmio_mmc_data mmc_data;
+-	struct tmio_mmc_dma dma_priv;
+-	struct pinctrl *pinctrl;
+-	struct pinctrl_state *pins_default, *pins_uhs;
+-	void __iomem *scc_ctl;
+-};
+-
+ static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
+ {
+ 	u32 val;
+@@ -540,7 +527,6 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 		host->bus_shift = of_data->bus_shift;
+ 	}
+ 
+-	host->dma		= dma_priv;
+ 	host->write16_hook	= renesas_sdhi_write16_hook;
+ 	host->clk_enable	= renesas_sdhi_clk_enable;
+ 	host->clk_update	= renesas_sdhi_clk_update;
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 227d613aa250..0afc07ea609b 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -103,6 +103,8 @@ renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
+ static void
+ renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
++
+ 	if (!host->chan_tx || !host->chan_rx)
+ 		return;
+ 
+@@ -110,8 +112,8 @@ renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
+ 		renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
+ 						    INFO1_CLEAR);
+ 
+-	if (host->dma->enable)
+-		host->dma->enable(host, enable);
++	if (priv->dma_priv.enable)
++		priv->dma_priv.enable(host, enable);
+ }
+ 
+ static void
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index e210644f1116..aeb3838c05e3 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -117,11 +117,13 @@ MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
+ static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
+ 					     bool enable)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
++
+ 	if (!host->chan_tx || !host->chan_rx)
+ 		return;
+ 
+-	if (host->dma->enable)
+-		host->dma->enable(host, enable);
++	if (priv->dma_priv.enable)
++		priv->dma_priv.enable(host, enable);
+ }
+ 
+ static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
+@@ -359,6 +361,8 @@ static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
+ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 					      struct tmio_mmc_data *pdata)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
++
+ 	/* We can only either use DMA for both Tx and Rx or not use it at all */
+ 	if (!host->pdev->dev.of_node &&
+ 	    (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
+@@ -378,7 +382,7 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 		dma_cap_set(DMA_SLAVE, mask);
+ 
+ 		host->chan_tx = dma_request_slave_channel_compat(mask,
+-					host->dma->filter, pdata->chan_priv_tx,
++					priv->dma_priv.filter, pdata->chan_priv_tx,
+ 					&host->pdev->dev, "tx");
+ 		dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
+ 			host->chan_tx);
+@@ -389,7 +393,7 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 		cfg.direction = DMA_MEM_TO_DEV;
+ 		cfg.dst_addr = res->start +
+ 			(CTL_SD_DATA_PORT << host->bus_shift);
+-		cfg.dst_addr_width = host->dma->dma_buswidth;
++		cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
+ 		if (!cfg.dst_addr_width)
+ 			cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ 		cfg.src_addr = 0;
+@@ -398,7 +402,7 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 			goto ecfgtx;
+ 
+ 		host->chan_rx = dma_request_slave_channel_compat(mask,
+-					host->dma->filter, pdata->chan_priv_rx,
++					priv->dma_priv.filter, pdata->chan_priv_rx,
+ 					&host->pdev->dev, "rx");
+ 		dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
+ 			host->chan_rx);
+@@ -408,7 +412,7 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 
+ 		cfg.direction = DMA_DEV_TO_MEM;
+ 		cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
+-		cfg.src_addr_width = host->dma->dma_buswidth;
++		cfg.src_addr_width = priv->dma_priv.dma_buswidth;
+ 		if (!cfg.src_addr_width)
+ 			cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ 		cfg.dst_addr = 0;
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index dd40b9631b3a..ed375a9056de 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -112,12 +112,6 @@
+ struct tmio_mmc_data;
+ struct tmio_mmc_host;
+ 
+-struct tmio_mmc_dma {
+-	enum dma_slave_buswidth dma_buswidth;
+-	bool (*filter)(struct dma_chan *chan, void *arg);
+-	void (*enable)(struct tmio_mmc_host *host, bool enable);
+-};
+-
+ struct tmio_mmc_dma_ops {
+ 	void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
+ 	void (*enable)(struct tmio_mmc_host *host, bool enable);
+@@ -149,7 +143,6 @@ struct tmio_mmc_host {
+ 
+ 	struct platform_device *pdev;
+ 	struct tmio_mmc_data *pdata;
+-	struct tmio_mmc_dma	*dma;
+ 
+ 	/* DMA support */
+ 	bool			force_pio;
+-- 
+2.19.0
+
diff --git a/patches/0461-mmc-tmio-renesas_sdhi-move-Renesas-specific-DMA-data.patch b/patches/0461-mmc-tmio-renesas_sdhi-move-Renesas-specific-DMA-data.patch
new file mode 100644
index 00000000000000..3c403f2dd92bc8
--- /dev/null
+++ b/patches/0461-mmc-tmio-renesas_sdhi-move-Renesas-specific-DMA-data.patch
@@ -0,0 +1,153 @@
+From ece6be389148e8619253c09edb78f0a99078cb49 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:48 +0900
+Subject: [PATCH 0461/1795] mmc: tmio, renesas_sdhi: move Renesas-specific DMA
+ data to renesas_sdhi.h
+
+struct tmio_mmc_host has "dma_dataend" and "dma_complete", but in fact,
+they are Renesas private data.  Move them to renesas_sdhi.h
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 90d9510645765401c56d75f6003d6cb6c1f7ca2a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi.h               |  2 ++
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c |  8 ++++++--
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 15 ++++++++++-----
+ drivers/mmc/host/tmio_mmc.h                   |  2 --
+ 4 files changed, 18 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
+index 9a507b3a9838..3250dbed402f 100644
+--- a/drivers/mmc/host/renesas_sdhi.h
++++ b/drivers/mmc/host/renesas_sdhi.h
+@@ -39,6 +39,8 @@ struct tmio_mmc_dma {
+ 	enum dma_slave_buswidth dma_buswidth;
+ 	bool (*filter)(struct dma_chan *chan, void *arg);
+ 	void (*enable)(struct tmio_mmc_host *host, bool enable);
++	struct completion	dma_dataend;
++	struct tasklet_struct	dma_complete;
+ };
+ 
+ struct renesas_sdhi {
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 0afc07ea609b..d679f1a28f29 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -132,7 +132,9 @@ renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+ 
+ static void
+ renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
+-	tasklet_schedule(&host->dma_complete);
++	struct renesas_sdhi *priv = host_to_priv(host);
++
++	tasklet_schedule(&priv->dma_priv.dma_complete);
+ }
+ 
+ static void
+@@ -222,10 +224,12 @@ static void
+ renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
+ 				       struct tmio_mmc_data *pdata)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
++
+ 	/* Each value is set to non-zero to assume "enabling" each DMA */
+ 	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
+ 
+-	tasklet_init(&host->dma_complete,
++	tasklet_init(&priv->dma_priv.dma_complete,
+ 		     renesas_sdhi_internal_dmac_complete_tasklet_fn,
+ 		     (unsigned long)host);
+ 	tasklet_init(&host->dma_issue,
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index aeb3838c05e3..c8a74b2dee00 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -140,12 +140,15 @@ static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
+ 
+ static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
+ {
+-	complete(&host->dma_dataend);
++	struct renesas_sdhi *priv = host_to_priv(host);
++
++	complete(&priv->dma_priv.dma_dataend);
+ }
+ 
+ static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
+ {
+ 	struct tmio_mmc_host *host = arg;
++	struct renesas_sdhi *priv = host_to_priv(host);
+ 
+ 	spin_lock_irq(&host->lock);
+ 
+@@ -163,7 +166,7 @@ static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
+ 
+ 	spin_unlock_irq(&host->lock);
+ 
+-	wait_for_completion(&host->dma_dataend);
++	wait_for_completion(&priv->dma_priv.dma_dataend);
+ 
+ 	spin_lock_irq(&host->lock);
+ 	tmio_mmc_do_data_irq(host);
+@@ -173,6 +176,7 @@ static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
+ 
+ static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
+ 	struct scatterlist *sg = host->sg_ptr, *sg_tmp;
+ 	struct dma_async_tx_descriptor *desc = NULL;
+ 	struct dma_chan *chan = host->chan_rx;
+@@ -216,7 +220,7 @@ static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
+ 					       DMA_CTRL_ACK);
+ 
+ 	if (desc) {
+-		reinit_completion(&host->dma_dataend);
++		reinit_completion(&priv->dma_priv.dma_dataend);
+ 		desc->callback = renesas_sdhi_sys_dmac_dma_callback;
+ 		desc->callback_param = host;
+ 
+@@ -247,6 +251,7 @@ static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
+ 
+ static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
+ {
++	struct renesas_sdhi *priv = host_to_priv(host);
+ 	struct scatterlist *sg = host->sg_ptr, *sg_tmp;
+ 	struct dma_async_tx_descriptor *desc = NULL;
+ 	struct dma_chan *chan = host->chan_tx;
+@@ -295,7 +300,7 @@ static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
+ 					       DMA_CTRL_ACK);
+ 
+ 	if (desc) {
+-		reinit_completion(&host->dma_dataend);
++		reinit_completion(&priv->dma_priv.dma_dataend);
+ 		desc->callback = renesas_sdhi_sys_dmac_dma_callback;
+ 		desc->callback_param = host;
+ 
+@@ -424,7 +429,7 @@ static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
+ 		if (!host->bounce_buf)
+ 			goto ebouncebuf;
+ 
+-		init_completion(&host->dma_dataend);
++		init_completion(&priv->dma_priv.dma_dataend);
+ 		tasklet_init(&host->dma_issue,
+ 			     renesas_sdhi_sys_dmac_issue_tasklet_fn,
+ 			     (unsigned long)host);
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index ed375a9056de..5972438105a3 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -148,8 +148,6 @@ struct tmio_mmc_host {
+ 	bool			force_pio;
+ 	struct dma_chan		*chan_rx;
+ 	struct dma_chan		*chan_tx;
+-	struct completion	dma_dataend;
+-	struct tasklet_struct	dma_complete;
+ 	struct tasklet_struct	dma_issue;
+ 	struct scatterlist	bounce_sg;
+ 	u8			*bounce_buf;
+-- 
+2.19.0
+
diff --git a/patches/0462-mmc-tmio-renesas_sdhi-move-ssc_tappos-to-renesas_sdh.patch b/patches/0462-mmc-tmio-renesas_sdhi-move-ssc_tappos-to-renesas_sdh.patch
new file mode 100644
index 00000000000000..3f36c768938f35
--- /dev/null
+++ b/patches/0462-mmc-tmio-renesas_sdhi-move-ssc_tappos-to-renesas_sdh.patch
@@ -0,0 +1,70 @@
+From ad5d7c74ff1601023b5dc2ea1cc9c8294faa8189 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:49 +0900
+Subject: [PATCH 0462/1795] mmc: tmio,renesas_sdhi: move ssc_tappos to
+ renesas_sdhi.h
+
+struct tmio_mmc_host has "scc_tappos", but in fact, it is Renesas
+private data.  Move it to renesas_sdhi.h
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 852d258f8465aa65adcce99f28552dd9b66a14a7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi.h      | 1 +
+ drivers/mmc/host/renesas_sdhi_core.c | 4 ++--
+ drivers/mmc/host/tmio_mmc.h          | 1 -
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
+index 3250dbed402f..f13f798d8506 100644
+--- a/drivers/mmc/host/renesas_sdhi.h
++++ b/drivers/mmc/host/renesas_sdhi.h
+@@ -51,6 +51,7 @@ struct renesas_sdhi {
+ 	struct pinctrl *pinctrl;
+ 	struct pinctrl_state *pins_default, *pins_uhs;
+ 	void __iomem *scc_ctl;
++	u32 scc_tappos;
+ };
+ 
+ #define host_to_priv(host) \
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 0eb62353630f..6a2988bd51a2 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -268,7 +268,7 @@ static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
+ 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
+ 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
+ 
+-	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
++	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
+ 
+ 	/* Read TAPNUM */
+ 	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
+@@ -591,7 +591,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 		for (i = 0; i < of_data->taps_num; i++) {
+ 			if (taps[i].clk_rate == 0 ||
+ 			    taps[i].clk_rate == host->mmc->f_max) {
+-				host->scc_tappos = taps->tap;
++				priv->scc_tappos = taps->tap;
+ 				hit = true;
+ 				break;
+ 			}
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index 5972438105a3..a099fde27026 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -166,7 +166,6 @@ struct tmio_mmc_host {
+ 	struct mutex		ios_lock;	/* protect set_ios() context */
+ 	bool			native_hotplug;
+ 	bool			sdio_irq_enabled;
+-	u32			scc_tappos;
+ 
+ 	/* Mandatory callback */
+ 	int (*clk_enable)(struct tmio_mmc_host *host);
+-- 
+2.19.0
+
diff --git a/patches/0463-mmc-tmio-change-bus_shift-to-unsigned-int.patch b/patches/0463-mmc-tmio-change-bus_shift-to-unsigned-int.patch
new file mode 100644
index 00000000000000..155f46f1e58b97
--- /dev/null
+++ b/patches/0463-mmc-tmio-change-bus_shift-to-unsigned-int.patch
@@ -0,0 +1,38 @@
+From b47fbdaf55d53cd75c10cb7588e0dc4d16dc2b7b Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:50 +0900
+Subject: [PATCH 0463/1795] mmc: tmio: change bus_shift to unsigned int
+
+Sane values for bus_shift are:
+   0 - for 16 bit bus
+   1 - for 32 bit bus
+   2 - for 64 bit bus
+
+"unsigned long" is too much.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit c4ba0e4abda39fb1ca81683be068b4556b2680d4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index a099fde27026..15537c85c51a 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -139,7 +139,7 @@ struct tmio_mmc_host {
+ 	struct scatterlist      *sg_orig;
+ 	unsigned int            sg_len;
+ 	unsigned int            sg_off;
+-	unsigned long		bus_shift;
++	unsigned int		bus_shift;
+ 
+ 	struct platform_device *pdev;
+ 	struct tmio_mmc_data *pdata;
+-- 
+2.19.0
+
diff --git a/patches/0464-mmc-tmio-use-io-accessors-consistently.patch b/patches/0464-mmc-tmio-use-io-accessors-consistently.patch
new file mode 100644
index 00000000000000..b40f290cd45d6a
--- /dev/null
+++ b/patches/0464-mmc-tmio-use-io-accessors-consistently.patch
@@ -0,0 +1,65 @@
+From d41919cd34219e9c7cb1fe82b9167f032cab8423 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 19 Dec 2017 14:34:03 +0100
+Subject: [PATCH 0464/1795] mmc: tmio: use io* accessors consistently
+
+Because we started using io*_rep accessors previously because they are
+more widely defined across architectures, let's be consistent and use
+this family for all accessor wrappers.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit d63da8c64bbf800a12fe0a4a2804e5953b8cf35e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index 15537c85c51a..52198f2929a5 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -228,7 +228,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev);
+ 
+ static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
+ {
+-	return readw(host->ctl + (addr << host->bus_shift));
++	return ioread16(host->ctl + (addr << host->bus_shift));
+ }
+ 
+ static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
+@@ -240,8 +240,8 @@ static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
+ static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
+ 					      int addr)
+ {
+-	return readw(host->ctl + (addr << host->bus_shift)) |
+-	       readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
++	return ioread16(host->ctl + (addr << host->bus_shift)) |
++	       ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
+ }
+ 
+ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
+@@ -258,7 +258,7 @@ static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
+ 	 */
+ 	if (host->write16_hook && host->write16_hook(host, addr))
+ 		return;
+-	writew(val, host->ctl + (addr << host->bus_shift));
++	iowrite16(val, host->ctl + (addr << host->bus_shift));
+ }
+ 
+ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
+@@ -270,8 +270,8 @@ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
+ static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
+ 						int addr, u32 val)
+ {
+-	writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
+-	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
++	iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
++	iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
+ }
+ 
+ static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
+-- 
+2.19.0
+
diff --git a/patches/0465-mfd-tmio-Move-register-macros-to-tmio_core.c.patch b/patches/0465-mfd-tmio-Move-register-macros-to-tmio_core.c.patch
new file mode 100644
index 00000000000000..196bfdf3a45c06
--- /dev/null
+++ b/patches/0465-mfd-tmio-Move-register-macros-to-tmio_core.c.patch
@@ -0,0 +1,83 @@
+From aeb9d3e5e8c2a20bd5f8618a61620d9640579406 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Tue, 7 Nov 2017 17:14:12 +0900
+Subject: [PATCH 0465/1795] mfd: tmio: Move register macros to tmio_core.c
+
+These registers are only used in drivers/mfd/tmio_core.c
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+(cherry picked from commit 299fad6b9b6e4b50929861c701af64a36cde0f31)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mfd/tmio_core.c  | 20 ++++++++++++++++++++
+ include/linux/mfd/tmio.h | 20 --------------------
+ 2 files changed, 20 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/mfd/tmio_core.c b/drivers/mfd/tmio_core.c
+index 83af78c1b0eb..ebf54cc28f7a 100644
+--- a/drivers/mfd/tmio_core.c
++++ b/drivers/mfd/tmio_core.c
+@@ -9,6 +9,26 @@
+ #include <linux/export.h>
+ #include <linux/mfd/tmio.h>
+ 
++#define CNF_CMD     0x04
++#define CNF_CTL_BASE   0x10
++#define CNF_INT_PIN  0x3d
++#define CNF_STOP_CLK_CTL 0x40
++#define CNF_GCLK_CTL 0x41
++#define CNF_SD_CLK_MODE 0x42
++#define CNF_PIN_STATUS 0x44
++#define CNF_PWR_CTL_1 0x48
++#define CNF_PWR_CTL_2 0x49
++#define CNF_PWR_CTL_3 0x4a
++#define CNF_CARD_DETECT_MODE 0x4c
++#define CNF_SD_SLOT 0x50
++#define CNF_EXT_GCLK_CTL_1 0xf0
++#define CNF_EXT_GCLK_CTL_2 0xf1
++#define CNF_EXT_GCLK_CTL_3 0xf9
++#define CNF_SD_LED_EN_1 0xfa
++#define CNF_SD_LED_EN_2 0xfe
++
++#define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
++
+ int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base)
+ {
+ 	/* Enable the MMC/SD Control registers */
+diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
+index e1cfe9194129..396a103c8bc6 100644
+--- a/include/linux/mfd/tmio.h
++++ b/include/linux/mfd/tmio.h
+@@ -25,26 +25,6 @@
+ 		writew((val) >> 16, (addr) + 2); \
+ 	} while (0)
+ 
+-#define CNF_CMD     0x04
+-#define CNF_CTL_BASE   0x10
+-#define CNF_INT_PIN  0x3d
+-#define CNF_STOP_CLK_CTL 0x40
+-#define CNF_GCLK_CTL 0x41
+-#define CNF_SD_CLK_MODE 0x42
+-#define CNF_PIN_STATUS 0x44
+-#define CNF_PWR_CTL_1 0x48
+-#define CNF_PWR_CTL_2 0x49
+-#define CNF_PWR_CTL_3 0x4a
+-#define CNF_CARD_DETECT_MODE 0x4c
+-#define CNF_SD_SLOT 0x50
+-#define CNF_EXT_GCLK_CTL_1 0xf0
+-#define CNF_EXT_GCLK_CTL_2 0xf1
+-#define CNF_EXT_GCLK_CTL_3 0xf9
+-#define CNF_SD_LED_EN_1 0xfa
+-#define CNF_SD_LED_EN_2 0xfe
+-
+-#define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
+-
+ #define sd_config_write8(base, shift, reg, val) \
+ 	tmio_iowrite8((val), (base) + ((reg) << (shift)))
+ #define sd_config_write16(base, shift, reg, val) \
+-- 
+2.19.0
+
diff --git a/patches/0466-mmc-tmio-renesas_sdhi-Remove-unneeded-NULL-check.patch b/patches/0466-mmc-tmio-renesas_sdhi-Remove-unneeded-NULL-check.patch
new file mode 100644
index 00000000000000..a58c3af7644941
--- /dev/null
+++ b/patches/0466-mmc-tmio-renesas_sdhi-Remove-unneeded-NULL-check.patch
@@ -0,0 +1,39 @@
+From c5d2b7e202ffd497dbc27e250cd7b109ea049a26 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 9 Jan 2018 12:39:10 +0300
+Subject: [PATCH 0466/1795] mmc: tmio, renesas_sdhi: Remove unneeded NULL check
+
+The inconsistent NULL checking in this function causes static checker
+warnings.
+
+    drivers/mmc/host/renesas_sdhi_sys_dmac.c:360 renesas_sdhi_sys_dmac_issue_tasklet_fn()
+    error: we previously assumed 'host' could be null (see line 351)
+
+On reviewing this code, "host" can't ever be NULL so we can just remove
+the check.
+
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit b8155d3ff3ebbdfa10c6ec6c5f04b263670727e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index c8a74b2dee00..82d757c480b2 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -348,7 +348,7 @@ static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
+ 
+ 	spin_lock_irq(&host->lock);
+ 
+-	if (host && host->data) {
++	if (host->data) {
+ 		if (host->data->flags & MMC_DATA_READ)
+ 			chan = host->chan_rx;
+ 		else
+-- 
+2.19.0
+
diff --git a/patches/0467-mmc-tmio-use-mmc_can_gpio_cd-instead-of-checking-TMI.patch b/patches/0467-mmc-tmio-use-mmc_can_gpio_cd-instead-of-checking-TMI.patch
new file mode 100644
index 00000000000000..d9e7350d51b509
--- /dev/null
+++ b/patches/0467-mmc-tmio-use-mmc_can_gpio_cd-instead-of-checking-TMI.patch
@@ -0,0 +1,43 @@
+From 12bc63872ef77bdcee59c259e199c43f977cddd0 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Sat, 25 Nov 2017 01:24:44 +0900
+Subject: [PATCH 0467/1795] mmc: tmio: use mmc_can_gpio_cd() instead of
+ checking TMIO_MMC_USE_GPIO_CD
+
+To use a GPIO line for card detection, TMIO_MMC_USE_GPIO_CD is set
+by a legacy board (arch/sh/boards/mach-ecovec24).
+
+For DT platforms, the "cd-gpios" property is a legitimate way for that
+in case the IP-builtin card detection can not be used for some reason.
+mmc_of_parse() calls mmc_gpiod_request_cd() to set up ctx->cd_gpio if
+the "cd-gpios" property is specified.
+
+To cater to both cases, mmc_can_gpio_cd() is a correct way to check
+which card detection logic is used.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit de21dc1d9a2a9fc5023c1fe3a24ba21e68c34928)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 61eac261d3de..ef70322d76be 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1232,7 +1232,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	}
+ 	mmc->max_seg_size = mmc->max_req_size;
+ 
+-	_host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
++	_host->native_hotplug = !(mmc_can_gpio_cd(mmc) ||
+ 				  mmc->caps & MMC_CAP_NEEDS_POLL ||
+ 				  !mmc_card_is_removable(mmc));
+ 
+-- 
+2.19.0
+
diff --git a/patches/0468-mmc-tmio-ioremap-memory-resource-in-tmio_mmc_host_al.patch b/patches/0468-mmc-tmio-ioremap-memory-resource-in-tmio_mmc_host_al.patch
new file mode 100644
index 00000000000000..196bf959a5bf6f
--- /dev/null
+++ b/patches/0468-mmc-tmio-ioremap-memory-resource-in-tmio_mmc_host_al.patch
@@ -0,0 +1,112 @@
+From 7d4dcf125b09a939d67a326d956ac8d533bfa266 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:01 +0900
+Subject: [PATCH 0468/1795] mmc: tmio: ioremap memory resource in
+ tmio_mmc_host_alloc()
+
+The register region is ioremap'ed in the tmio_mmc_host_probe(), i.e.
+drivers cannot get access to the hardware before mmc_add_host().
+
+Actually, renesas_sdhi_core.c reads out the CTL_VERSION register to
+complete the platform-specific settings.  However, at this point,
+the MMC host is already running.
+
+Move the register ioremap to tmio_mmc_host_alloc() so that drivers
+can perform platform-specific settings between tmio_mmc_host_alloc()
+and tmio_mmc_host_probe().
+
+I changed tmio_mmc_host_alloc() to return an error pointer to
+propagate the return code from devm_ioremap_resource().
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 8d09a13386ccdee8fb6d66aa2cfedbbc9255f892)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c |  4 ++--
+ drivers/mmc/host/tmio_mmc.c          |  4 +++-
+ drivers/mmc/host/tmio_mmc_core.c     | 16 +++++++++-------
+ 3 files changed, 14 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 6a2988bd51a2..ccdde2735f68 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -512,8 +512,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	}
+ 
+ 	host = tmio_mmc_host_alloc(pdev);
+-	if (!host)
+-		return -ENOMEM;
++	if (IS_ERR(host))
++		return PTR_ERR(host);
+ 
+ 	if (of_data) {
+ 		mmc_data->flags |= of_data->tmio_flags;
+diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
+index ccfbc154ee5b..d660816bdf89 100644
+--- a/drivers/mmc/host/tmio_mmc.c
++++ b/drivers/mmc/host/tmio_mmc.c
+@@ -93,8 +93,10 @@ static int tmio_mmc_probe(struct platform_device *pdev)
+ 	pdata->flags |= TMIO_MMC_HAVE_HIGH_REG;
+ 
+ 	host = tmio_mmc_host_alloc(pdev);
+-	if (!host)
++	if (IS_ERR(host)) {
++		ret = PTR_ERR(host);
+ 		goto cell_disable;
++	}
+ 
+ 	/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
+ 	host->bus_shift = resource_size(res) >> 10;
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index ef70322d76be..4582c9a3bfb6 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1150,12 +1150,20 @@ tmio_mmc_host_alloc(struct platform_device *pdev)
+ {
+ 	struct tmio_mmc_host *host;
+ 	struct mmc_host *mmc;
++	struct resource *res;
++	void __iomem *ctl;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	ctl = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(ctl))
++		return ERR_CAST(ctl);
+ 
+ 	mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
+ 	if (!mmc)
+-		return NULL;
++		return ERR_PTR(-ENOMEM);
+ 
+ 	host = mmc_priv(mmc);
++	host->ctl = ctl;
+ 	host->mmc = mmc;
+ 	host->pdev = pdev;
+ 	host->ops = tmio_mmc_ops;
+@@ -1177,7 +1185,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ {
+ 	struct platform_device *pdev = _host->pdev;
+ 	struct mmc_host *mmc = _host->mmc;
+-	struct resource *res_ctl;
+ 	int ret;
+ 	u32 irq_mask = TMIO_MASK_CMD;
+ 
+@@ -1186,11 +1193,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
+ 		_host->write16_hook = NULL;
+ 
+-	res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	_host->ctl = devm_ioremap_resource(&pdev->dev, res_ctl);
+-	if (IS_ERR(_host->ctl))
+-		return PTR_ERR(_host->ctl);
+-
+ 	ret = mmc_of_parse(mmc);
+ 	if (ret < 0)
+ 		return ret;
+-- 
+2.19.0
+
diff --git a/patches/0469-mmc-tmio-move-clk_enable-disable-out-of-tmio_mmc_hos.patch b/patches/0469-mmc-tmio-move-clk_enable-disable-out-of-tmio_mmc_hos.patch
new file mode 100644
index 00000000000000..4aecdb4d229bdb
--- /dev/null
+++ b/patches/0469-mmc-tmio-move-clk_enable-disable-out-of-tmio_mmc_hos.patch
@@ -0,0 +1,208 @@
+From 23c06b239ca2faeabdd41628b6f357aec453ce3e Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:02 +0900
+Subject: [PATCH 0469/1795] mmc: tmio: move clk_enable/disable out of
+ tmio_mmc_host_probe()
+
+The clock is enabled in the tmio_mmc_host_probe().  It also prevents
+drivers from performing platform-specific settings before mmc_add_host()
+because the register access generally requires a clock.
+
+Enable/disable the clock in drivers' probe/remove.  Also, I passed
+tmio_mmc_data to tmio_mmc_host_alloc() because renesas_sdhi_clk_enable()
+needs it to get the private data from tmio_mmc_host.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit b21fc294387e4cf7916c132f7d6aaeebd4483a16)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c | 13 ++++++++---
+ drivers/mmc/host/tmio_mmc.c          |  7 ++++--
+ drivers/mmc/host/tmio_mmc.h          |  4 ++--
+ drivers/mmc/host/tmio_mmc_core.c     | 33 +++++++++++-----------------
+ 4 files changed, 30 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index ccdde2735f68..e18a1c553df6 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -511,7 +511,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 						"state_uhs");
+ 	}
+ 
+-	host = tmio_mmc_host_alloc(pdev);
++	host = tmio_mmc_host_alloc(pdev, mmc_data);
+ 	if (IS_ERR(host))
+ 		return PTR_ERR(host);
+ 
+@@ -571,10 +571,14 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	/* All SDHI have SDIO status bits which must be 1 */
+ 	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
+ 
+-	ret = tmio_mmc_host_probe(host, mmc_data, dma_ops);
+-	if (ret < 0)
++	ret = renesas_sdhi_clk_enable(host);
++	if (ret)
+ 		goto efree;
+ 
++	ret = tmio_mmc_host_probe(host, dma_ops);
++	if (ret < 0)
++		goto edisclk;
++
+ 	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
+ 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
+ 		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
+@@ -635,6 +639,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 
+ eirq:
+ 	tmio_mmc_host_remove(host);
++edisclk:
++	renesas_sdhi_clk_disable(host);
+ efree:
+ 	tmio_mmc_host_free(host);
+ 
+@@ -647,6 +653,7 @@ int renesas_sdhi_remove(struct platform_device *pdev)
+ 	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
+ 
+ 	tmio_mmc_host_remove(host);
++	renesas_sdhi_clk_disable(host);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
+index d660816bdf89..11b87ce54764 100644
+--- a/drivers/mmc/host/tmio_mmc.c
++++ b/drivers/mmc/host/tmio_mmc.c
+@@ -92,7 +92,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
+ 
+ 	pdata->flags |= TMIO_MMC_HAVE_HIGH_REG;
+ 
+-	host = tmio_mmc_host_alloc(pdev);
++	host = tmio_mmc_host_alloc(pdev, pdata);
+ 	if (IS_ERR(host)) {
+ 		ret = PTR_ERR(host);
+ 		goto cell_disable;
+@@ -101,7 +101,10 @@ static int tmio_mmc_probe(struct platform_device *pdev)
+ 	/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
+ 	host->bus_shift = resource_size(res) >> 10;
+ 
+-	ret = tmio_mmc_host_probe(host, pdata, NULL);
++	host->mmc->f_max = pdata->hclk;
++	host->mmc->f_min = pdata->hclk / 512;
++
++	ret = tmio_mmc_host_probe(host, NULL);
+ 	if (ret)
+ 		goto host_free;
+ 
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index 52198f2929a5..b52d7368818d 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -195,10 +195,10 @@ struct tmio_mmc_host {
+ 	const struct tmio_mmc_dma_ops *dma_ops;
+ };
+ 
+-struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev);
++struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
++					  struct tmio_mmc_data *pdata);
+ void tmio_mmc_host_free(struct tmio_mmc_host *host);
+ int tmio_mmc_host_probe(struct tmio_mmc_host *host,
+-			struct tmio_mmc_data *pdata,
+ 			const struct tmio_mmc_dma_ops *dma_ops);
+ void tmio_mmc_host_remove(struct tmio_mmc_host *host);
+ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 4582c9a3bfb6..411c6111e267 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1145,8 +1145,8 @@ static void tmio_mmc_of_parse(struct platform_device *pdev,
+ 		pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
+ }
+ 
+-struct tmio_mmc_host*
+-tmio_mmc_host_alloc(struct platform_device *pdev)
++struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
++					  struct tmio_mmc_data *pdata)
+ {
+ 	struct tmio_mmc_host *host;
+ 	struct mmc_host *mmc;
+@@ -1166,9 +1166,12 @@ tmio_mmc_host_alloc(struct platform_device *pdev)
+ 	host->ctl = ctl;
+ 	host->mmc = mmc;
+ 	host->pdev = pdev;
++	host->pdata = pdata;
+ 	host->ops = tmio_mmc_ops;
+ 	mmc->ops = &host->ops;
+ 
++	platform_set_drvdata(pdev, host);
++
+ 	return host;
+ }
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_alloc);
+@@ -1180,14 +1183,21 @@ void tmio_mmc_host_free(struct tmio_mmc_host *host)
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_free);
+ 
+ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+-			struct tmio_mmc_data *pdata,
+ 			const struct tmio_mmc_dma_ops *dma_ops)
+ {
+ 	struct platform_device *pdev = _host->pdev;
++	struct tmio_mmc_data *pdata = _host->pdata;
+ 	struct mmc_host *mmc = _host->mmc;
+ 	int ret;
+ 	u32 irq_mask = TMIO_MASK_CMD;
+ 
++	/*
++	 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
++	 * looping forever...
++	 */
++	if (mmc->f_min == 0)
++		return -EINVAL;
++
+ 	tmio_mmc_of_parse(pdev, pdata);
+ 
+ 	if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
+@@ -1197,9 +1207,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	_host->pdata = pdata;
+-	platform_set_drvdata(pdev, _host);
+-
+ 	_host->set_pwr = pdata->set_pwr;
+ 	_host->set_clk_div = pdata->set_clk_div;
+ 
+@@ -1247,18 +1254,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (pdata->flags & TMIO_MMC_MIN_RCAR2)
+ 		_host->native_hotplug = true;
+ 
+-	if (tmio_mmc_clk_enable(_host) < 0) {
+-		mmc->f_max = pdata->hclk;
+-		mmc->f_min = mmc->f_max / 512;
+-	}
+-
+-	/*
+-	 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
+-	 * looping forever...
+-	 */
+-	if (mmc->f_min == 0)
+-		return -EINVAL;
+-
+ 	/*
+ 	 * While using internal tmio hardware logic for card detection, we need
+ 	 * to ensure it stays powered for it to work.
+@@ -1336,8 +1331,6 @@ void tmio_mmc_host_remove(struct tmio_mmc_host *host)
+ 
+ 	pm_runtime_put_sync(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+-
+-	tmio_mmc_clk_disable(host);
+ }
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_remove);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0470-mmc-tmio-move-tmio_-mmc_of_parse-to-tmio_mmc_host_al.patch b/patches/0470-mmc-tmio-move-tmio_-mmc_of_parse-to-tmio_mmc_host_al.patch
new file mode 100644
index 00000000000000..c52ff5a168cdd4
--- /dev/null
+++ b/patches/0470-mmc-tmio-move-tmio_-mmc_of_parse-to-tmio_mmc_host_al.patch
@@ -0,0 +1,77 @@
+From 0b0a368ec3f116562422f43a5d991ab9e606b29f Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:03 +0900
+Subject: [PATCH 0470/1795] mmc: tmio: move {tmio_}mmc_of_parse() to
+ tmio_mmc_host_alloc()
+
+mmc_of_parse() parses various DT properties and sets capability flags
+accordingly.  However, drivers have no chance to run platform init
+code depending on such flags because mmc_of_parse() is called from
+tmio_mmc_host_probe().
+
+Move mmc_of_parse() to tmio_mmc_host_alloc() so that drivers can
+handle capabilities before mmc_add_host().  Move tmio_mmc_of_parse()
+likewise.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 6fb294f791af8f491812d4eef6b13a57c9c1de34)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 411c6111e267..679bd96f4c14 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1152,6 +1152,7 @@ struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
+ 	struct mmc_host *mmc;
+ 	struct resource *res;
+ 	void __iomem *ctl;
++	int ret;
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	ctl = devm_ioremap_resource(&pdev->dev, res);
+@@ -1170,8 +1171,20 @@ struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
+ 	host->ops = tmio_mmc_ops;
+ 	mmc->ops = &host->ops;
+ 
++	ret = mmc_of_parse(host->mmc);
++	if (ret) {
++		host = ERR_PTR(ret);
++		goto free;
++	}
++
++	tmio_mmc_of_parse(pdev, pdata);
++
+ 	platform_set_drvdata(pdev, host);
+ 
++	return host;
++free:
++	mmc_free_host(mmc);
++
+ 	return host;
+ }
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_alloc);
+@@ -1198,15 +1211,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	if (mmc->f_min == 0)
+ 		return -EINVAL;
+ 
+-	tmio_mmc_of_parse(pdev, pdata);
+-
+ 	if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
+ 		_host->write16_hook = NULL;
+ 
+-	ret = mmc_of_parse(mmc);
+-	if (ret < 0)
+-		return ret;
+-
+ 	_host->set_pwr = pdata->set_pwr;
+ 	_host->set_clk_div = pdata->set_clk_div;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0471-mmc-tmio-remove-dma_ops-from-tmio_mmc_host_probe-arg.patch b/patches/0471-mmc-tmio-remove-dma_ops-from-tmio_mmc_host_probe-arg.patch
new file mode 100644
index 00000000000000..dd6976dbcb9b89
--- /dev/null
+++ b/patches/0471-mmc-tmio-remove-dma_ops-from-tmio_mmc_host_probe-arg.patch
@@ -0,0 +1,96 @@
+From 614593ab2ae7da722c9da5b08ca0c6c452912fcd Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:04 +0900
+Subject: [PATCH 0471/1795] mmc: tmio: remove dma_ops from
+ tmio_mmc_host_probe() argument
+
+Drivers need to set up various struct members for tmio_mmc_host before
+calling tmio_mmc_host_probe().  Do likewise for host->dma_ops instead
+of passing it as a function argument.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit bc45719c1b1a56047246d44c7e4ed88a8ae702c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c | 3 ++-
+ drivers/mmc/host/tmio_mmc.c          | 2 +-
+ drivers/mmc/host/tmio_mmc.h          | 3 +--
+ drivers/mmc/host/tmio_mmc_core.c     | 4 +---
+ 4 files changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index e18a1c553df6..80943fa07db6 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -532,6 +532,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	host->clk_update	= renesas_sdhi_clk_update;
+ 	host->clk_disable	= renesas_sdhi_clk_disable;
+ 	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
++	host->dma_ops		= dma_ops;
+ 
+ 	/* SDR speeds are only available on Gen2+ */
+ 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
+@@ -575,7 +576,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	if (ret)
+ 		goto efree;
+ 
+-	ret = tmio_mmc_host_probe(host, dma_ops);
++	ret = tmio_mmc_host_probe(host);
+ 	if (ret < 0)
+ 		goto edisclk;
+ 
+diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
+index 11b87ce54764..43a2ea5cff24 100644
+--- a/drivers/mmc/host/tmio_mmc.c
++++ b/drivers/mmc/host/tmio_mmc.c
+@@ -104,7 +104,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
+ 	host->mmc->f_max = pdata->hclk;
+ 	host->mmc->f_min = pdata->hclk / 512;
+ 
+-	ret = tmio_mmc_host_probe(host, NULL);
++	ret = tmio_mmc_host_probe(host);
+ 	if (ret)
+ 		goto host_free;
+ 
+diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
+index b52d7368818d..e7d651352dc9 100644
+--- a/drivers/mmc/host/tmio_mmc.h
++++ b/drivers/mmc/host/tmio_mmc.h
+@@ -198,8 +198,7 @@ struct tmio_mmc_host {
+ struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
+ 					  struct tmio_mmc_data *pdata);
+ void tmio_mmc_host_free(struct tmio_mmc_host *host);
+-int tmio_mmc_host_probe(struct tmio_mmc_host *host,
+-			const struct tmio_mmc_dma_ops *dma_ops);
++int tmio_mmc_host_probe(struct tmio_mmc_host *host);
+ void tmio_mmc_host_remove(struct tmio_mmc_host *host);
+ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
+ 
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 679bd96f4c14..1417574a47e7 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1195,8 +1195,7 @@ void tmio_mmc_host_free(struct tmio_mmc_host *host)
+ }
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_free);
+ 
+-int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+-			const struct tmio_mmc_dma_ops *dma_ops)
++int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ {
+ 	struct platform_device *pdev = _host->pdev;
+ 	struct tmio_mmc_data *pdata = _host->pdata;
+@@ -1296,7 +1295,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
+ 	INIT_WORK(&_host->done, tmio_mmc_done_work);
+ 
+ 	/* See if we also get DMA */
+-	_host->dma_ops = dma_ops;
+ 	tmio_mmc_request_dma(_host, pdata);
+ 
+ 	pm_runtime_set_active(&pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0472-soc-renesas-Identify-R-Car-M3-W-ES1.1.patch b/patches/0472-soc-renesas-Identify-R-Car-M3-W-ES1.1.patch
new file mode 100644
index 00000000000000..acb41d4c6ceba3
--- /dev/null
+++ b/patches/0472-soc-renesas-Identify-R-Car-M3-W-ES1.1.patch
@@ -0,0 +1,34 @@
+From b95d3374f2030ac0667bf8a32cad3926fa8fec7c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 18:29:58 +0100
+Subject: [PATCH 0472/1795] soc: renesas: Identify R-Car M3-W ES1.1
+
+The Product Register of R-Car M3-W ES1.1 incorrectly identifies the SoC
+revision as ES2.0.  Add a workaround to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 90f0d2b344313a8a4c366ef60d0df33008d2be84)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 9f4ee2567c72..926b7fd6db2d 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -250,6 +250,9 @@ static int __init renesas_soc_init(void)
+ 	if (chipid) {
+ 		product = readl(chipid);
+ 		iounmap(chipid);
++		/* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */
++		if ((product & 0x7fff) == 0x5210)
++			product ^= 0x11;
+ 		if (soc->id && ((product >> 8) & 0xff) != soc->id) {
+ 			pr_warn("SoC mismatch (product = 0x%x)\n", product);
+ 			return -ENODEV;
+-- 
+2.19.0
+
diff --git a/patches/0473-sata_rcar-Reset-SATA-PHY-when-Salvator-X-board-resum.patch b/patches/0473-sata_rcar-Reset-SATA-PHY-when-Salvator-X-board-resum.patch
new file mode 100644
index 00000000000000..57fbabd0cfeaff
--- /dev/null
+++ b/patches/0473-sata_rcar-Reset-SATA-PHY-when-Salvator-X-board-resum.patch
@@ -0,0 +1,145 @@
+From 135b65f7e72d46116a5afb9325f320e1fca07b11 Mon Sep 17 00:00:00 2001
+From: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
+Date: Mon, 5 Feb 2018 04:18:51 +0900
+Subject: [PATCH 0473/1795] sata_rcar: Reset SATA PHY when Salvator-X board
+ resumes
+
+Because power of Salvator-X board is cut off in suspend,
+it needs to reset SATA PHY state in resume.
+Otherwise, SATA partition could not be accessed anymore.
+
+Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
+Signed-off-by: Hien Dang <hien.dang.eb@rvc.renesas.com>
+[reinit phy in sata_rcar_resume() function on R-Car Gen3 only]
+[factor out SATA module init sequence]
+[fixed the prefix for the subject]
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+
+(cherry picked from commit da77d76b95a0e8940793f4f7fe12a4a2d2048e39)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/ata/sata_rcar.c | 63 ++++++++++++++++++++++++++---------------
+ 1 file changed, 40 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
+index 80ee2f2a50d0..6f47ca34767d 100644
+--- a/drivers/ata/sata_rcar.c
++++ b/drivers/ata/sata_rcar.c
+@@ -146,6 +146,7 @@
+ enum sata_rcar_type {
+ 	RCAR_GEN1_SATA,
+ 	RCAR_GEN2_SATA,
++	RCAR_GEN3_SATA,
+ 	RCAR_R8A7790_ES1_SATA,
+ };
+ 
+@@ -784,26 +785,11 @@ static void sata_rcar_setup_port(struct ata_host *host)
+ 	ioaddr->command_addr	= ioaddr->cmd_addr + (ATA_REG_CMD << 2);
+ }
+ 
+-static void sata_rcar_init_controller(struct ata_host *host)
++static void sata_rcar_init_module(struct sata_rcar_priv *priv)
+ {
+-	struct sata_rcar_priv *priv = host->private_data;
+ 	void __iomem *base = priv->base;
+ 	u32 val;
+ 
+-	/* reset and setup phy */
+-	switch (priv->type) {
+-	case RCAR_GEN1_SATA:
+-		sata_rcar_gen1_phy_init(priv);
+-		break;
+-	case RCAR_GEN2_SATA:
+-	case RCAR_R8A7790_ES1_SATA:
+-		sata_rcar_gen2_phy_init(priv);
+-		break;
+-	default:
+-		dev_warn(host->dev, "SATA phy is not initialized\n");
+-		break;
+-	}
+-
+ 	/* SATA-IP reset state */
+ 	val = ioread32(base + ATAPI_CONTROL1_REG);
+ 	val |= ATAPI_CONTROL1_RESET;
+@@ -824,10 +810,34 @@ static void sata_rcar_init_controller(struct ata_host *host)
+ 	/* ack and mask */
+ 	iowrite32(0, base + SATAINTSTAT_REG);
+ 	iowrite32(0x7ff, base + SATAINTMASK_REG);
++
+ 	/* enable interrupts */
+ 	iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
+ }
+ 
++static void sata_rcar_init_controller(struct ata_host *host)
++{
++	struct sata_rcar_priv *priv = host->private_data;
++	void __iomem *base = priv->base;
++
++	/* reset and setup phy */
++	switch (priv->type) {
++	case RCAR_GEN1_SATA:
++		sata_rcar_gen1_phy_init(priv);
++		break;
++	case RCAR_GEN2_SATA:
++	case RCAR_GEN3_SATA:
++	case RCAR_R8A7790_ES1_SATA:
++		sata_rcar_gen2_phy_init(priv);
++		break;
++	default:
++		dev_warn(host->dev, "SATA phy is not initialized\n");
++		break;
++	}
++
++	sata_rcar_init_module(priv);
++}
++
+ static const struct of_device_id sata_rcar_match[] = {
+ 	{
+ 		/* Deprecated by "renesas,sata-r8a7779" */
+@@ -856,7 +866,7 @@ static const struct of_device_id sata_rcar_match[] = {
+ 	},
+ 	{
+ 		.compatible = "renesas,sata-r8a7795",
+-		.data = (void *)RCAR_GEN2_SATA
++		.data = (void *)RCAR_GEN3_SATA
+ 	},
+ 	{
+ 		.compatible = "renesas,rcar-gen2-sata",
+@@ -864,7 +874,7 @@ static const struct of_device_id sata_rcar_match[] = {
+ 	},
+ 	{
+ 		.compatible = "renesas,rcar-gen3-sata",
+-		.data = (void *)RCAR_GEN2_SATA
++		.data = (void *)RCAR_GEN3_SATA
+ 	},
+ 	{ },
+ };
+@@ -982,11 +992,18 @@ static int sata_rcar_resume(struct device *dev)
+ 	if (ret)
+ 		return ret;
+ 
+-	/* ack and mask */
+-	iowrite32(0, base + SATAINTSTAT_REG);
+-	iowrite32(0x7ff, base + SATAINTMASK_REG);
+-	/* enable interrupts */
+-	iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
++	if (priv->type == RCAR_GEN3_SATA) {
++		sata_rcar_gen2_phy_init(priv);
++		sata_rcar_init_module(priv);
++	} else {
++		/* ack and mask */
++		iowrite32(0, base + SATAINTSTAT_REG);
++		iowrite32(0x7ff, base + SATAINTMASK_REG);
++
++		/* enable interrupts */
++		iowrite32(ATAPI_INT_ENABLE_SATAINT,
++			  base + ATAPI_INT_ENABLE_REG);
++	}
+ 
+ 	ata_host_resume(host);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0474-ata-sata_rcar-Remove-unused-variable-in-sata_rcar_in.patch b/patches/0474-ata-sata_rcar-Remove-unused-variable-in-sata_rcar_in.patch
new file mode 100644
index 00000000000000..d08d6c16f7a524
--- /dev/null
+++ b/patches/0474-ata-sata_rcar-Remove-unused-variable-in-sata_rcar_in.patch
@@ -0,0 +1,34 @@
+From dd1ad9c7e92fe96c501dac157575166493874d13 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 13 Feb 2018 13:43:23 +0100
+Subject: [PATCH 0474/1795] ata: sata_rcar: Remove unused variable in
+ sata_rcar_init_controller()
+
+drivers/ata/sata_rcar.c: In function 'sata_rcar_init_controller':
+drivers/ata/sata_rcar.c:821:8: warning: unused variable 'base' [-Wunused-variable]
+
+Fixes: da77d76b95a0e894 ("sata_rcar: Reset SATA PHY when Salvator-X board resumes")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Tejun Heo <tj@kernel.org>
+(cherry picked from commit 8f8ca51dbb4da0457f57f83d94aea81931b0707a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/ata/sata_rcar.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
+index 6f47ca34767d..6456e07db72a 100644
+--- a/drivers/ata/sata_rcar.c
++++ b/drivers/ata/sata_rcar.c
+@@ -818,7 +818,6 @@ static void sata_rcar_init_module(struct sata_rcar_priv *priv)
+ static void sata_rcar_init_controller(struct ata_host *host)
+ {
+ 	struct sata_rcar_priv *priv = host->private_data;
+-	void __iomem *base = priv->base;
+ 
+ 	/* reset and setup phy */
+ 	switch (priv->type) {
+-- 
+2.19.0
+
diff --git a/patches/0475-cpufreq-Add-and-use-cpufreq_for_each_-valid_-entry_i.patch b/patches/0475-cpufreq-Add-and-use-cpufreq_for_each_-valid_-entry_i.patch
new file mode 100644
index 00000000000000..359c6755c76617
--- /dev/null
+++ b/patches/0475-cpufreq-Add-and-use-cpufreq_for_each_-valid_-entry_i.patch
@@ -0,0 +1,454 @@
+From 60d839c1679a9ea08ff5825785cea57569e32126 Mon Sep 17 00:00:00 2001
+From: Dominik Brodowski <linux@dominikbrodowski.net>
+Date: Tue, 30 Jan 2018 06:42:37 +0100
+Subject: [PATCH 0475/1795] cpufreq: Add and use
+ cpufreq_for_each_{valid_,}entry_idx()
+
+Pointer subtraction is slow and tedious. Therefore, replace all instances
+where cpufreq_for_each_{valid_,}entry loops contained such substractions
+with an iteration macro providing an index to the frequency_table entry.
+
+Suggested-by: Al Viro <viro@ZenIV.linux.org.uk>
+Link: http://lkml.kernel.org/r/20180120020237.GM13338@ZenIV.linux.org.uk
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit ffd81dcfef85a33729f90e4acd2f61a68e56b993)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/cpu-freq/cpu-drivers.txt |   4 +
+ drivers/cpufreq/exynos5440-cpufreq.c   |   7 +-
+ drivers/cpufreq/freq_table.c           |   8 +-
+ drivers/cpufreq/longhaul.c             |   4 +-
+ drivers/cpufreq/pasemi-cpufreq.c       |   6 +-
+ drivers/sh/clk/core.c                  |   5 +-
+ drivers/staging/irda/drivers/sh_sir.c  |   4 +-
+ include/linux/cpufreq.h                | 125 ++++++++++++++++---------
+ 8 files changed, 100 insertions(+), 63 deletions(-)
+
+diff --git a/Documentation/cpu-freq/cpu-drivers.txt b/Documentation/cpu-freq/cpu-drivers.txt
+index 434c49cc7330..61546ac578d6 100644
+--- a/Documentation/cpu-freq/cpu-drivers.txt
++++ b/Documentation/cpu-freq/cpu-drivers.txt
+@@ -291,3 +291,7 @@ For example:
+ 		/* Do something with pos */
+ 		pos->frequency = ...
+ 	}
++
++If you need to work with the position of pos within driver_freq_table,
++do not subtract the pointers, as it is quite costly. Instead, use the
++macros cpufreq_for_each_entry_idx() and cpufreq_for_each_valid_entry_idx().
+diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
+index b6b369c22272..932caa386ece 100644
+--- a/drivers/cpufreq/exynos5440-cpufreq.c
++++ b/drivers/cpufreq/exynos5440-cpufreq.c
+@@ -115,10 +115,10 @@ static struct cpufreq_freqs freqs;
+ static int init_div_table(void)
+ {
+ 	struct cpufreq_frequency_table *pos, *freq_tbl = dvfs_info->freq_table;
+-	unsigned int tmp, clk_div, ema_div, freq, volt_id;
++	unsigned int tmp, clk_div, ema_div, freq, volt_id, idx;
+ 	struct dev_pm_opp *opp;
+ 
+-	cpufreq_for_each_entry(pos, freq_tbl) {
++	cpufreq_for_each_entry_idx(pos, freq_tbl, idx) {
+ 		opp = dev_pm_opp_find_freq_exact(dvfs_info->dev,
+ 					pos->frequency * 1000, true);
+ 		if (IS_ERR(opp)) {
+@@ -154,8 +154,7 @@ static int init_div_table(void)
+ 		tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
+ 			| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
+ 
+-		__raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 *
+-						(pos - freq_tbl));
++		__raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * idx);
+ 		dev_pm_opp_put(opp);
+ 	}
+ 
+diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c
+index 3bbbf9e6960c..6d007f824ca7 100644
+--- a/drivers/cpufreq/freq_table.c
++++ b/drivers/cpufreq/freq_table.c
+@@ -143,10 +143,9 @@ int cpufreq_table_index_unsorted(struct cpufreq_policy *policy,
+ 		break;
+ 	}
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, i) {
+ 		freq = pos->frequency;
+ 
+-		i = pos - table;
+ 		if ((freq < policy->min) || (freq > policy->max))
+ 			continue;
+ 		if (freq == target_freq) {
+@@ -211,15 +210,16 @@ int cpufreq_frequency_table_get_index(struct cpufreq_policy *policy,
+ 		unsigned int freq)
+ {
+ 	struct cpufreq_frequency_table *pos, *table = policy->freq_table;
++	int idx;
+ 
+ 	if (unlikely(!table)) {
+ 		pr_debug("%s: Unable to find frequency table\n", __func__);
+ 		return -ENOENT;
+ 	}
+ 
+-	cpufreq_for_each_valid_entry(pos, table)
++	cpufreq_for_each_valid_entry_idx(pos, table, idx)
+ 		if (pos->frequency == freq)
+-			return pos - table;
++			return idx;
+ 
+ 	return -EINVAL;
+ }
+diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
+index 859a62ea6120..f730b6528c18 100644
+--- a/drivers/cpufreq/longhaul.c
++++ b/drivers/cpufreq/longhaul.c
+@@ -600,7 +600,7 @@ static void longhaul_setup_voltagescaling(void)
+ 	/* Calculate kHz for one voltage step */
+ 	kHz_step = (highest_speed - min_vid_speed) / numvscales;
+ 
+-	cpufreq_for_each_entry(freq_pos, longhaul_table) {
++	cpufreq_for_each_entry_idx(freq_pos, longhaul_table, j) {
+ 		speed = freq_pos->frequency;
+ 		if (speed > min_vid_speed)
+ 			pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
+@@ -609,7 +609,7 @@ static void longhaul_setup_voltagescaling(void)
+ 		freq_pos->driver_data |= mV_vrm_table[pos] << 8;
+ 		vid = vrm_mV_table[mV_vrm_table[pos]];
+ 		pr_info("f: %d kHz, index: %d, vid: %d mV\n",
+-			speed, (int)(freq_pos - longhaul_table), vid.mV);
++			speed, j, vid.mV);
+ 	}
+ 
+ 	can_scale_voltage = 1;
+diff --git a/drivers/cpufreq/pasemi-cpufreq.c b/drivers/cpufreq/pasemi-cpufreq.c
+index b257fc7d5204..75dfbd2a58ea 100644
+--- a/drivers/cpufreq/pasemi-cpufreq.c
++++ b/drivers/cpufreq/pasemi-cpufreq.c
+@@ -139,7 +139,7 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
+ 	struct cpufreq_frequency_table *pos;
+ 	const u32 *max_freqp;
+ 	u32 max_freq;
+-	int cur_astate;
++	int cur_astate, idx;
+ 	struct resource res;
+ 	struct device_node *cpu, *dn;
+ 	int err = -ENODEV;
+@@ -198,9 +198,9 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
+ 	pr_debug("initializing frequency table\n");
+ 
+ 	/* initialize frequency table */
+-	cpufreq_for_each_entry(pos, pas_freqs) {
++	cpufreq_for_each_entry_idx(pos, pas_freqs, idx) {
+ 		pos->frequency = get_astate_freq(pos->driver_data) * 100000;
+-		pr_debug("%d: %d\n", (int)(pos - pas_freqs), pos->frequency);
++		pr_debug("%d: %d\n", idx, pos->frequency);
+ 	}
+ 
+ 	cur_astate = get_cur_astate(policy->cpu);
+diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c
+index 92863e3818e5..9475353f49d6 100644
+--- a/drivers/sh/clk/core.c
++++ b/drivers/sh/clk/core.c
+@@ -197,10 +197,11 @@ int clk_rate_table_find(struct clk *clk,
+ 			unsigned long rate)
+ {
+ 	struct cpufreq_frequency_table *pos;
++	int idx;
+ 
+-	cpufreq_for_each_valid_entry(pos, freq_table)
++	cpufreq_for_each_valid_entry_idx(pos, freq_table, idx)
+ 		if (pos->frequency == rate)
+-			return pos - freq_table;
++			return idx;
+ 
+ 	return -ENOENT;
+ }
+diff --git a/drivers/staging/irda/drivers/sh_sir.c b/drivers/staging/irda/drivers/sh_sir.c
+index fede6864c737..0d0687cc454a 100644
+--- a/drivers/staging/irda/drivers/sh_sir.c
++++ b/drivers/staging/irda/drivers/sh_sir.c
+@@ -226,7 +226,7 @@ static u32 sh_sir_find_sclk(struct clk *irda_clk)
+ 	clk_put(pclk);
+ 
+ 	/* IrDA can not set over peripheral_clk */
+-	cpufreq_for_each_valid_entry(pos, freq_table) {
++	cpufreq_for_each_valid_entry_idx(pos, freq_table, index) {
+ 		u32 freq = pos->frequency;
+ 
+ 		/* IrDA should not over peripheral_clk */
+@@ -236,7 +236,7 @@ static u32 sh_sir_find_sclk(struct clk *irda_clk)
+ 		tmp = freq % SCLK_BASE;
+ 		if (tmp < min) {
+ 			min = tmp;
+-			index = pos - freq_table;
++			break;
+ 		}
+ 	}
+ 
+diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
+index cbf85c4c745f..919295a0b859 100644
+--- a/include/linux/cpufreq.h
++++ b/include/linux/cpufreq.h
+@@ -628,6 +628,18 @@ static inline void dev_pm_opp_free_cpufreq_table(struct device *dev,
+ #define cpufreq_for_each_entry(pos, table)	\
+ 	for (pos = table; pos->frequency != CPUFREQ_TABLE_END; pos++)
+ 
++/*
++ * cpufreq_for_each_entry_idx -	iterate over a cpufreq_frequency_table
++ *	with index
++ * @pos:	the cpufreq_frequency_table * to use as a loop cursor.
++ * @table:	the cpufreq_frequency_table * to iterate over.
++ * @idx:	the table entry currently being processed
++ */
++
++#define cpufreq_for_each_entry_idx(pos, table, idx)	\
++	for (pos = table, idx = 0; pos->frequency != CPUFREQ_TABLE_END; \
++		pos++, idx++)
++
+ /*
+  * cpufreq_for_each_valid_entry -     iterate over a cpufreq_frequency_table
+  *	excluding CPUFREQ_ENTRY_INVALID frequencies.
+@@ -641,6 +653,21 @@ static inline void dev_pm_opp_free_cpufreq_table(struct device *dev,
+ 			continue;					\
+ 		else
+ 
++/*
++ * cpufreq_for_each_valid_entry_idx -     iterate with index over a cpufreq
++ *	frequency_table excluding CPUFREQ_ENTRY_INVALID frequencies.
++ * @pos:	the cpufreq_frequency_table * to use as a loop cursor.
++ * @table:	the cpufreq_frequency_table * to iterate over.
++ * @idx:	the table entry currently being processed
++ */
++
++#define cpufreq_for_each_valid_entry_idx(pos, table, idx)		\
++	cpufreq_for_each_entry_idx(pos, table, idx)			\
++		if (pos->frequency == CPUFREQ_ENTRY_INVALID)		\
++			continue;					\
++		else
++
++
+ int cpufreq_frequency_table_cpuinfo(struct cpufreq_policy *policy,
+ 				    struct cpufreq_frequency_table *table);
+ 
+@@ -667,19 +694,20 @@ static inline int cpufreq_table_find_index_al(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq >= target_freq)
+-			return pos - table;
++			return idx;
+ 
+-		best = pos;
++		best = idx;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Find lowest freq at or above target in a table in descending order */
+@@ -687,28 +715,29 @@ static inline int cpufreq_table_find_index_dl(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq == target_freq)
+-			return pos - table;
++			return idx;
+ 
+ 		if (freq > target_freq) {
+-			best = pos;
++			best = idx;
+ 			continue;
+ 		}
+ 
+ 		/* No freq found above target_freq */
+-		if (best == table - 1)
+-			return pos - table;
++		if (best == -1)
++			return idx;
+ 
+-		return best - table;
++		return best;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Works only on sorted freq-tables */
+@@ -728,28 +757,29 @@ static inline int cpufreq_table_find_index_ah(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq == target_freq)
+-			return pos - table;
++			return idx;
+ 
+ 		if (freq < target_freq) {
+-			best = pos;
++			best = idx;
+ 			continue;
+ 		}
+ 
+ 		/* No freq found below target_freq */
+-		if (best == table - 1)
+-			return pos - table;
++		if (best == -1)
++			return idx;
+ 
+-		return best - table;
++		return best;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Find highest freq at or below target in a table in descending order */
+@@ -757,19 +787,20 @@ static inline int cpufreq_table_find_index_dh(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq <= target_freq)
+-			return pos - table;
++			return idx;
+ 
+-		best = pos;
++		best = idx;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Works only on sorted freq-tables */
+@@ -789,32 +820,33 @@ static inline int cpufreq_table_find_index_ac(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq == target_freq)
+-			return pos - table;
++			return idx;
+ 
+ 		if (freq < target_freq) {
+-			best = pos;
++			best = idx;
+ 			continue;
+ 		}
+ 
+ 		/* No freq found below target_freq */
+-		if (best == table - 1)
+-			return pos - table;
++		if (best == -1)
++			return idx;
+ 
+ 		/* Choose the closest freq */
+-		if (target_freq - best->frequency > freq - target_freq)
+-			return pos - table;
++		if (target_freq - table[best].frequency > freq - target_freq)
++			return idx;
+ 
+-		return best - table;
++		return best;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Find closest freq to target in a table in descending order */
+@@ -822,32 +854,33 @@ static inline int cpufreq_table_find_index_dc(struct cpufreq_policy *policy,
+ 					      unsigned int target_freq)
+ {
+ 	struct cpufreq_frequency_table *table = policy->freq_table;
+-	struct cpufreq_frequency_table *pos, *best = table - 1;
++	struct cpufreq_frequency_table *pos;
+ 	unsigned int freq;
++	int idx, best = -1;
+ 
+-	cpufreq_for_each_valid_entry(pos, table) {
++	cpufreq_for_each_valid_entry_idx(pos, table, idx) {
+ 		freq = pos->frequency;
+ 
+ 		if (freq == target_freq)
+-			return pos - table;
++			return idx;
+ 
+ 		if (freq > target_freq) {
+-			best = pos;
++			best = idx;
+ 			continue;
+ 		}
+ 
+ 		/* No freq found above target_freq */
+-		if (best == table - 1)
+-			return pos - table;
++		if (best == -1)
++			return idx;
+ 
+ 		/* Choose the closest freq */
+-		if (best->frequency - target_freq > target_freq - freq)
+-			return pos - table;
++		if (table[best].frequency - target_freq > target_freq - freq)
++			return idx;
+ 
+-		return best - table;
++		return best;
+ 	}
+ 
+-	return best - table;
++	return best;
+ }
+ 
+ /* Works only on sorted freq-tables */
+-- 
+2.19.0
+
diff --git a/patches/0476-sh_eth-kill-redundant-check-in-the-probe-method.patch b/patches/0476-sh_eth-kill-redundant-check-in-the-probe-method.patch
new file mode 100644
index 00000000000000..6e1310a05bb165
--- /dev/null
+++ b/patches/0476-sh_eth-kill-redundant-check-in-the-probe-method.patch
@@ -0,0 +1,37 @@
+From 9ef47f4fa90319e6b33d0ead11ec4e7da4ad8998 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 31 Dec 2017 21:41:36 +0300
+Subject: [PATCH 0476/1795] sh_eth: kill redundant check in the probe() method
+
+Browsing thru the driver disassembly, I noticed that gcc was  able to
+figure  out  that the 'ndev' pointer is always non-NULL when calling
+free_netdev()  on the probe() method's  error path and  thus skip that
+redundant NULL check... gcc is smart, be like gcc! :-)
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4282fc47c01262fdda55a9d63a4e25173fd9afb4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 007f54b5766b..d7216bcace03 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -3278,8 +3278,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 
+ out_release:
+ 	/* net_dev free */
+-	if (ndev)
+-		free_netdev(ndev);
++	free_netdev(ndev);
+ 
+ 	pm_runtime_put(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0477-sh_eth-remove-sh_eth_plat_data-edmac_endian.patch b/patches/0477-sh_eth-remove-sh_eth_plat_data-edmac_endian.patch
new file mode 100644
index 00000000000000..e6721636fba733
--- /dev/null
+++ b/patches/0477-sh_eth-remove-sh_eth_plat_data-edmac_endian.patch
@@ -0,0 +1,143 @@
+From db1ab7fcf45142b8ee7f464f5cf5f1adeb22cffa Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 5 Jan 2018 00:26:46 +0300
+Subject: [PATCH 0477/1795] sh_eth: remove sh_eth_plat_data::edmac_endian
+
+Since the commit 888cc8c20cf ("sh_eth: remove EDMAC_BIG_ENDIAN") (geez,
+I didn't realize that was 2 years ago!) the initializers in the SuperH
+platform code for the 'sh_eth_plat_data::edmac_endian' stopped to matter,
+so we can remove that field for good (not sure if  it  was ever useful --
+SH7786 Ether has been reported  to have the same EDMAC descriptor/register
+endiannes as configured for the SuperH CPU)...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit e3e49ca9b033adbc99aca25db4b46b0eadd7cfb9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/sh/boards/board-espt.c           | 1 -
+ arch/sh/boards/board-sh7757lcr.c      | 4 ----
+ arch/sh/boards/mach-ecovec24/setup.c  | 1 -
+ arch/sh/boards/mach-se/7724/setup.c   | 1 -
+ arch/sh/boards/mach-sh7763rdp/setup.c | 1 -
+ arch/sh/kernel/cpu/sh2/setup-sh7619.c | 1 -
+ include/linux/sh_eth.h                | 3 ---
+ 7 files changed, 12 deletions(-)
+
+diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c
+index 7291e2f11a47..4d6be53058d6 100644
+--- a/arch/sh/boards/board-espt.c
++++ b/arch/sh/boards/board-espt.c
+@@ -79,7 +79,6 @@ static struct resource sh_eth_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7763_eth_pdata = {
+ 	.phy = 0,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.phy_interface = PHY_INTERFACE_MODE_MII,
+ };
+ 
+diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
+index 0104c8199c48..1bde08dc067d 100644
+--- a/arch/sh/boards/board-sh7757lcr.c
++++ b/arch/sh/boards/board-sh7757lcr.c
+@@ -76,7 +76,6 @@ static struct resource sh_eth0_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7757_eth0_pdata = {
+ 	.phy = 1,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.set_mdio_gate = sh7757_eth_set_mdio_gate,
+ };
+ 
+@@ -104,7 +103,6 @@ static struct resource sh_eth1_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7757_eth1_pdata = {
+ 	.phy = 1,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.set_mdio_gate = sh7757_eth_set_mdio_gate,
+ };
+ 
+@@ -148,7 +146,6 @@ static struct resource sh_eth_giga0_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
+ 	.phy = 18,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
+ 	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
+ };
+@@ -182,7 +179,6 @@ static struct resource sh_eth_giga1_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
+ 	.phy = 19,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
+ 	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
+ };
+diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
+index 1faf6cb93dcb..6f929abe0b50 100644
+--- a/arch/sh/boards/mach-ecovec24/setup.c
++++ b/arch/sh/boards/mach-ecovec24/setup.c
+@@ -159,7 +159,6 @@ static struct resource sh_eth_resources[] = {
+ 
+ static struct sh_eth_plat_data sh_eth_plat = {
+ 	.phy = 0x1f, /* SMSC LAN8700 */
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.phy_interface = PHY_INTERFACE_MODE_MII,
+ 	.ether_link_active_low = 1
+ };
+diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
+index f1fecd395679..255952555656 100644
+--- a/arch/sh/boards/mach-se/7724/setup.c
++++ b/arch/sh/boards/mach-se/7724/setup.c
+@@ -374,7 +374,6 @@ static struct resource sh_eth_resources[] = {
+ 
+ static struct sh_eth_plat_data sh_eth_plat = {
+ 	.phy = 0x1f, /* SMSC LAN8187 */
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.phy_interface = PHY_INTERFACE_MODE_MII,
+ };
+ 
+diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
+index 2c8fb04685d4..6e62686b81b1 100644
+--- a/arch/sh/boards/mach-sh7763rdp/setup.c
++++ b/arch/sh/boards/mach-sh7763rdp/setup.c
+@@ -87,7 +87,6 @@ static struct resource sh_eth_resources[] = {
+ 
+ static struct sh_eth_plat_data sh7763_eth_pdata = {
+ 	.phy = 1,
+-	.edmac_endian = EDMAC_LITTLE_ENDIAN,
+ 	.phy_interface = PHY_INTERFACE_MODE_MII,
+ };
+ 
+diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+index 95796ad00fbe..d08db08dec38 100644
+--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
++++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+@@ -122,7 +122,6 @@ static struct platform_device scif2_device = {
+ 
+ static struct sh_eth_plat_data eth_platform_data = {
+ 	.phy		= 1,
+-	.edmac_endian	= EDMAC_LITTLE_ENDIAN,
+ 	.phy_interface	= PHY_INTERFACE_MODE_MII,
+ };
+ 
+diff --git a/include/linux/sh_eth.h b/include/linux/sh_eth.h
+index 94081e9a5010..6dfda97a6c1a 100644
+--- a/include/linux/sh_eth.h
++++ b/include/linux/sh_eth.h
+@@ -5,12 +5,9 @@
+ #include <linux/phy.h>
+ #include <linux/if_ether.h>
+ 
+-enum {EDMAC_LITTLE_ENDIAN};
+-
+ struct sh_eth_plat_data {
+ 	int phy;
+ 	int phy_irq;
+-	int edmac_endian;
+ 	phy_interface_t phy_interface;
+ 	void (*set_mdio_gate)(void *addr);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0478-sh_eth-gather-all-TSU-init-code-in-one-place.patch b/patches/0478-sh_eth-gather-all-TSU-init-code-in-one-place.patch
new file mode 100644
index 00000000000000..26abe9e2dfd086
--- /dev/null
+++ b/patches/0478-sh_eth-gather-all-TSU-init-code-in-one-place.patch
@@ -0,0 +1,62 @@
+From f311c039bd50c16666bc7a558602d1f83b04bf71 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 14 Jan 2018 20:47:43 +0300
+Subject: [PATCH 0478/1795] sh_eth: gather all TSU init code in one place
+
+The  sh_eth_cpu_data::chip_reset() method  always resets using ARSTR and
+this register is always located at the start of the  TSU register region.
+Therefore, we can  only call  this method if we know TSU is there and thus
+simplify  the probing code a  bit...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 3e14c969a4ecdb4b4a05fb5c806d4f525fe56cff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 12 +++++-------
+ 1 file changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index d7216bcace03..7a56c59476d6 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -3199,7 +3199,6 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 		eth_hw_addr_random(ndev);
+ 	}
+ 
+-	/* ioremap the TSU registers */
+ 	if (mdp->cd->tsu) {
+ 		struct resource *rtsu;
+ 
+@@ -3220,6 +3219,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 			ret = -EBUSY;
+ 			goto out_release;
+ 		}
++		/* ioremap the TSU registers */
+ 		mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
+ 					     resource_size(rtsu));
+ 		if (!mdp->tsu_addr) {
+@@ -3229,14 +3229,12 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 		}
+ 		mdp->port = devno % 2;
+ 		ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
+-	}
+ 
+-	/* Need to init only the first port of the two sharing a TSU */
+-	if (devno % 2 == 0) {
+-		if (mdp->cd->chip_reset)
+-			mdp->cd->chip_reset(ndev);
++		/* Need to init only the first port of the two sharing a TSU */
++		if (devno % 2 == 0) {
++			if (mdp->cd->chip_reset)
++				mdp->cd->chip_reset(ndev);
+ 
+-		if (mdp->cd->tsu) {
+ 			/* TSU init (Init only)*/
+ 			sh_eth_tsu_init(mdp);
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/0479-sh_eth-get-Ether-port-only-when-needed.patch b/patches/0479-sh_eth-get-Ether-port-only-when-needed.patch
new file mode 100644
index 00000000000000..2a41aec90a057d
--- /dev/null
+++ b/patches/0479-sh_eth-get-Ether-port-only-when-needed.patch
@@ -0,0 +1,78 @@
+From b9465449b4bf3becd1713292c7908a9e642377e7 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 14 Jan 2018 20:47:44 +0300
+Subject: [PATCH 0479/1795] sh_eth: get Ether port # only when needed
+
+The dual-port Ether configurations always have a shared TSU to e.g. pass
+the packets between those  ports.  With the  TSU init. code gathered under
+the single *if*, we now can only get the port # from 'platform_device::id'
+only when we actually  need it  (and not recalculate it each time)...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 9662ec19229c89825acac1d62a9d78fb89f8dda5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 13 +++++--------
+ 1 file changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 7a56c59476d6..f17cb74c03e9 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -3102,7 +3102,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 	const struct platform_device_id *id = platform_get_device_id(pdev);
+ 	struct sh_eth_private *mdp;
+ 	struct net_device *ndev;
+-	int ret, devno;
++	int ret;
+ 
+ 	/* get base addr */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -3114,10 +3114,6 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 	pm_runtime_enable(&pdev->dev);
+ 	pm_runtime_get_sync(&pdev->dev);
+ 
+-	devno = pdev->id;
+-	if (devno < 0)
+-		devno = 0;
+-
+ 	ret = platform_get_irq(pdev, 0);
+ 	if (ret < 0)
+ 		goto out_release;
+@@ -3200,6 +3196,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (mdp->cd->tsu) {
++		int port = pdev->id < 0 ? 0 : pdev->id % 2;
+ 		struct resource *rtsu;
+ 
+ 		rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+@@ -3211,7 +3208,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 		/* We can only request the  TSU region  for the first port
+ 		 * of the two  sharing this TSU for the probe to succeed...
+ 		 */
+-		if (devno % 2 == 0 &&
++		if (port == 0 &&
+ 		    !devm_request_mem_region(&pdev->dev, rtsu->start,
+ 					     resource_size(rtsu),
+ 					     dev_name(&pdev->dev))) {
+@@ -3227,11 +3224,11 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 			ret = -ENOMEM;
+ 			goto out_release;
+ 		}
+-		mdp->port = devno % 2;
++		mdp->port = port;
+ 		ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
+ 
+ 		/* Need to init only the first port of the two sharing a TSU */
+-		if (devno % 2 == 0) {
++		if (port == 0) {
+ 			if (mdp->cd->chip_reset)
+ 				mdp->cd->chip_reset(ndev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0480-sh_eth-Remove-obsolete-explicit-clock-handling-for-W.patch b/patches/0480-sh_eth-Remove-obsolete-explicit-clock-handling-for-W.patch
new file mode 100644
index 00000000000000..bd7b5431c6d7a7
--- /dev/null
+++ b/patches/0480-sh_eth-Remove-obsolete-explicit-clock-handling-for-W.patch
@@ -0,0 +1,104 @@
+From 90c9f12af837b6abfe59a523af195c77f699bcd7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Feb 2018 14:42:36 +0100
+Subject: [PATCH 0480/1795] sh_eth: Remove obsolete explicit clock handling for
+ WoL
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, if Wake-on-LAN is enabled, the SH-ETH device's module clock
+is manually kept running during system suspend, to make sure the device
+stays active.
+
+Since commits 91c719f5ec6671f7 ("soc: renesas: rcar-sysc: Keep wakeup
+sources active during system suspend") and 744dddcae84441b1 ("clk:
+renesas: mstp: Keep wakeup sources active during system suspend"), this
+workaround is no longer needed.  Hence remove all explicit clock
+handling to keep the device active.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit b4580c952e89a332f077038ef19a7582950c082d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 18 +++---------------
+ 1 file changed, 3 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index f17cb74c03e9..cffd58af7c45 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -40,7 +40,6 @@
+ #include <linux/slab.h>
+ #include <linux/ethtool.h>
+ #include <linux/if_vlan.h>
+-#include <linux/clk.h>
+ #include <linux/sh_eth.h>
+ #include <linux/of_mdio.h>
+ 
+@@ -2281,7 +2280,7 @@ static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ 	wol->supported = 0;
+ 	wol->wolopts = 0;
+ 
+-	if (mdp->cd->magic && mdp->clk) {
++	if (mdp->cd->magic) {
+ 		wol->supported = WAKE_MAGIC;
+ 		wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
+ 	}
+@@ -2291,7 +2290,7 @@ static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+ 
+-	if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
++	if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
+ 		return -EOPNOTSUPP;
+ 
+ 	mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
+@@ -3130,11 +3129,6 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 		goto out_release;
+ 	}
+ 
+-	/* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
+-	mdp->clk = devm_clk_get(&pdev->dev, NULL);
+-	if (IS_ERR(mdp->clk))
+-		mdp->clk = NULL;
+-
+ 	ndev->base_addr = res->start;
+ 
+ 	spin_lock_init(&mdp->lock);
+@@ -3255,7 +3249,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		goto out_napi_del;
+ 
+-	if (mdp->cd->magic && mdp->clk)
++	if (mdp->cd->magic)
+ 		device_set_wakeup_capable(&pdev->dev, 1);
+ 
+ 	/* print device information */
+@@ -3308,9 +3302,6 @@ static int sh_eth_wol_setup(struct net_device *ndev)
+ 	/* Enable MagicPacket */
+ 	sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
+ 
+-	/* Increased clock usage so device won't be suspended */
+-	clk_enable(mdp->clk);
+-
+ 	return enable_irq_wake(ndev->irq);
+ }
+ 
+@@ -3336,9 +3327,6 @@ static int sh_eth_wol_restore(struct net_device *ndev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	/* Restore clock usage count */
+-	clk_disable(mdp->clk);
+-
+ 	return disable_irq_wake(ndev->irq);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0481-sh_eth-uninline-TSU-register-accessors.patch b/patches/0481-sh_eth-uninline-TSU-register-accessors.patch
new file mode 100644
index 00000000000000..9739e98109742b
--- /dev/null
+++ b/patches/0481-sh_eth-uninline-TSU-register-accessors.patch
@@ -0,0 +1,66 @@
+From af86024a481a94c4a02452ab29dfe47e0a31835d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 27 Feb 2018 14:58:16 +0300
+Subject: [PATCH 0481/1795] sh_eth: uninline TSU register accessors
+
+We have uninlined the sh_eth_{read|write}() functions introduced in the
+commit 4a55530f38e ("net: sh_eth: modify the definitions of register").
+Now remove *inline* from sh_eth_tsu_{read|write}() as  well and move
+these functions from the header to the driver itself. This saves 684
+more bytes of object code (ARM gcc 4.8.5)...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 55ea874306ea28e6be9e07b7e89bbb9fb674e8eb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 11 +++++++++++
+ drivers/net/ethernet/renesas/sh_eth.h | 11 -----------
+ 2 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index cffd58af7c45..4e2f46fa8353 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -439,6 +439,17 @@ static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
+ 		     enum_index);
+ }
+ 
++static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
++			     int enum_index)
++{
++	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
++}
++
++static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
++{
++	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
++}
++
+ static bool sh_eth_is_gether(struct sh_eth_private *mdp)
+ {
+ 	return mdp->reg_offset == sh_eth_offset_gigabit;
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 6ab3d46d4f28..fdd6d71c03d1 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -568,15 +568,4 @@ static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
+ 	return mdp->tsu_addr + mdp->reg_offset[enum_index];
+ }
+ 
+-static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
+-				    int enum_index)
+-{
+-	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
+-}
+-
+-static inline u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
+-{
+-	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
+-}
+-
+ #endif	/* #ifndef __SH_ETH_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0482-mmc-sh_mmcif-remove-redundant-initialization-of-opc.patch b/patches/0482-mmc-sh_mmcif-remove-redundant-initialization-of-opc.patch
new file mode 100644
index 00000000000000..43957410fe209f
--- /dev/null
+++ b/patches/0482-mmc-sh_mmcif-remove-redundant-initialization-of-opc.patch
@@ -0,0 +1,39 @@
+From 0014ec0a6b614c9bb2cd2e4ba1701a989bf1e9f7 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Wed, 17 Jan 2018 13:41:57 +0000
+Subject: [PATCH 0482/1795] mmc: sh_mmcif: remove redundant initialization of
+ 'opc'
+
+Variable opc is initialized with a value that is never read, opc
+is later re-assigned a newer value, hence the initialization can
+be removed.
+
+Cleans up clang warning:
+drivers/mmc/host/sh_mmcif.c:919:6: warning: Value stored to 'opc'
+during its initialization is never read
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 659032dcb9f11c3bd2a3a23db76e6a70b3ddec79)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/sh_mmcif.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
+index 53fb18bb7bee..7bb00c68a756 100644
+--- a/drivers/mmc/host/sh_mmcif.c
++++ b/drivers/mmc/host/sh_mmcif.c
+@@ -916,7 +916,7 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
+ 			       struct mmc_request *mrq)
+ {
+ 	struct mmc_command *cmd = mrq->cmd;
+-	u32 opc = cmd->opcode;
++	u32 opc;
+ 	u32 mask = 0;
+ 	unsigned long flags;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0483-media-v4l-sh_mobile_ceu-Return-buffers-on-streamoff.patch b/patches/0483-media-v4l-sh_mobile_ceu-Return-buffers-on-streamoff.patch
new file mode 100644
index 00000000000000..c8b8baadf9b1b4
--- /dev/null
+++ b/patches/0483-media-v4l-sh_mobile_ceu-Return-buffers-on-streamoff.patch
@@ -0,0 +1,51 @@
+From 1a0db1b0acff0861fec8c2b242d5231f81a285bd Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Wed, 15 Nov 2017 12:59:12 -0500
+Subject: [PATCH 0483/1795] media: v4l: sh_mobile_ceu: Return buffers on
+ streamoff()
+
+videobuf2 core reports an error when not all buffers have been returned
+to the framework:
+
+drivers/media/v4l2-core/videobuf2-core.c:1651
+WARN_ON(atomic_read(&q->owned_by_drv_count))
+
+Fix this returning all buffers currently in capture queue.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 866a6eccdd998418065ff28fd280252bfa63e43c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
+index 36762ec954e7..9180a1d96acb 100644
+--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
+@@ -451,13 +451,18 @@ static void sh_mobile_ceu_stop_streaming(struct vb2_queue *q)
+ 	struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
+ 	struct sh_mobile_ceu_dev *pcdev = ici->priv;
+ 	struct list_head *buf_head, *tmp;
++	struct vb2_v4l2_buffer *vbuf;
+ 
+ 	spin_lock_irq(&pcdev->lock);
+ 
+ 	pcdev->active = NULL;
+ 
+-	list_for_each_safe(buf_head, tmp, &pcdev->capture)
++	list_for_each_safe(buf_head, tmp, &pcdev->capture) {
++		vbuf = &list_entry(buf_head, struct sh_mobile_ceu_buffer,
++				   queue)->vb;
++		vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
+ 		list_del_init(buf_head);
++	}
+ 
+ 	spin_unlock_irq(&pcdev->lock);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0484-pinctrl-sh-pfc-r8a7745-Add-CAN-01-support.patch b/patches/0484-pinctrl-sh-pfc-r8a7745-Add-CAN-01-support.patch
new file mode 100644
index 00000000000000..1483cb81cd8485
--- /dev/null
+++ b/patches/0484-pinctrl-sh-pfc-r8a7745-Add-CAN-01-support.patch
@@ -0,0 +1,199 @@
+From a456a4346b326c870d6b14ff12af2b2d29028f1d Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:43 +0000
+Subject: [PATCH 0484/1795] pinctrl: sh-pfc: r8a7745: Add CAN[01] support
+
+This patch adds PFC CAN0 and CAN1 pin groups and functions, enabling CAN
+bus on the RZ/G1E.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3f35221842305e82494e10fcfc1f5750c8bc682a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 146 +++++++++++++++++++++++++++
+ 1 file changed, 146 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index 333a3470e842..e5b3d5fa4aa0 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -1608,6 +1608,116 @@ static const unsigned int avb_gmii_mux[] = {
+ 	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ 	AVB_COL_MARK,
+ };
++
++/* - CAN -------------------------------------------------------------------- */
++static const unsigned int can0_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
++};
++
++static const unsigned int can0_data_mux[] = {
++	CAN0_TX_MARK, CAN0_RX_MARK,
++};
++
++static const unsigned int can0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
++};
++
++static const unsigned int can0_data_b_mux[] = {
++	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
++};
++
++static const unsigned int can0_data_c_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
++};
++
++static const unsigned int can0_data_c_mux[] = {
++	CAN0_TX_C_MARK, CAN0_RX_C_MARK,
++};
++
++static const unsigned int can0_data_d_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
++};
++
++static const unsigned int can0_data_d_mux[] = {
++	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
++};
++
++static const unsigned int can1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
++};
++
++static const unsigned int can1_data_mux[] = {
++	CAN1_TX_MARK, CAN1_RX_MARK,
++};
++
++static const unsigned int can1_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
++};
++
++static const unsigned int can1_data_b_mux[] = {
++	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
++};
++
++static const unsigned int can1_data_c_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
++};
++
++static const unsigned int can1_data_c_mux[] = {
++	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
++};
++
++static const unsigned int can1_data_d_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
++};
++
++static const unsigned int can1_data_d_mux[] = {
++	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
++};
++
++static const unsigned int can_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(3, 31),
++};
++
++static const unsigned int can_clk_mux[] = {
++	CAN_CLK_MARK,
++};
++
++static const unsigned int can_clk_b_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 23),
++};
++
++static const unsigned int can_clk_b_mux[] = {
++	CAN_CLK_B_MARK,
++};
++
++static const unsigned int can_clk_c_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 0),
++};
++
++static const unsigned int can_clk_c_mux[] = {
++	CAN_CLK_C_MARK,
++};
++
++static const unsigned int can_clk_d_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(5, 0),
++};
++
++static const unsigned int can_clk_d_mux[] = {
++	CAN_CLK_D_MARK,
++};
++
+ /* - DU --------------------------------------------------------------------- */
+ static const unsigned int du0_rgb666_pins[] = {
+ 	/* R[7:2], G[7:2], B[7:2] */
+@@ -3459,6 +3569,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_mdio),
+ 	SH_PFC_PIN_GROUP(avb_mii),
+ 	SH_PFC_PIN_GROUP(avb_gmii),
++	SH_PFC_PIN_GROUP(can0_data),
++	SH_PFC_PIN_GROUP(can0_data_b),
++	SH_PFC_PIN_GROUP(can0_data_c),
++	SH_PFC_PIN_GROUP(can0_data_d),
++	SH_PFC_PIN_GROUP(can1_data),
++	SH_PFC_PIN_GROUP(can1_data_b),
++	SH_PFC_PIN_GROUP(can1_data_c),
++	SH_PFC_PIN_GROUP(can1_data_d),
++	SH_PFC_PIN_GROUP(can_clk),
++	SH_PFC_PIN_GROUP(can_clk_b),
++	SH_PFC_PIN_GROUP(can_clk_c),
++	SH_PFC_PIN_GROUP(can_clk_d),
+ 	SH_PFC_PIN_GROUP(du0_rgb666),
+ 	SH_PFC_PIN_GROUP(du0_rgb888),
+ 	SH_PFC_PIN_GROUP(du0_clk0_out),
+@@ -3731,6 +3853,28 @@ static const char * const avb_groups[] = {
+ 	"avb_gmii",
+ };
+ 
++static const char * const can0_groups[] = {
++	"can0_data",
++	"can0_data_b",
++	"can0_data_c",
++	"can0_data_d",
++	"can_clk",
++	"can_clk_b",
++	"can_clk_c",
++	"can_clk_d",
++};
++
++static const char * const can1_groups[] = {
++	"can1_data",
++	"can1_data_b",
++	"can1_data_c",
++	"can1_data_d",
++	"can_clk",
++	"can_clk_b",
++	"can_clk_c",
++	"can_clk_d",
++};
++
+ static const char * const du0_groups[] = {
+ 	"du0_rgb666",
+ 	"du0_rgb888",
+@@ -4102,6 +4246,8 @@ static const char * const vin1_groups[] = {
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(can0),
++	SH_PFC_FUNCTION(can1),
+ 	SH_PFC_FUNCTION(du0),
+ 	SH_PFC_FUNCTION(du1),
+ 	SH_PFC_FUNCTION(eth),
+-- 
+2.19.0
+
diff --git a/patches/0485-pinctrl-sh-pfc-r8a7795-Add-CAN-support.patch b/patches/0485-pinctrl-sh-pfc-r8a7795-Add-CAN-support.patch
new file mode 100644
index 00000000000000..116169e4c7b89b
--- /dev/null
+++ b/patches/0485-pinctrl-sh-pfc-r8a7795-Add-CAN-support.patch
@@ -0,0 +1,105 @@
+From fac8feab0c97ae451fa002343583bff4725d3f9d Mon Sep 17 00:00:00 2001
+From: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Date: Fri, 10 Nov 2017 13:58:49 +0000
+Subject: [PATCH 0485/1795] pinctrl: sh-pfc: r8a7795: Add CAN support
+
+This patch adds CAN[0-1] pinmux support for R-Car H3 ES2.0. The pin
+config is identical to H3 ES1.*.
+
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a678abfee7ab5d2dcfc2079158ec799c7f4cf204)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 52 ++++++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index d1cec6d12e81..59249a990cef 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1781,6 +1781,38 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
+ 	AVB_AVTP_CAPTURE_B_MARK,
+ };
+ 
++/* - CAN ------------------------------------------------------------------ */
++static const unsigned int can0_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int can0_data_a_mux[] = {
++	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
++};
++static const unsigned int can0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int can0_data_b_mux[] = {
++	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
++};
++static const unsigned int can1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
++};
++static const unsigned int can1_data_mux[] = {
++	CAN1_TX_MARK,		CAN1_RX_MARK,
++};
++
++/* - CAN Clock -------------------------------------------------------------- */
++static const unsigned int can_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int can_clk_mux[] = {
++	CAN_CLK_MARK,
++};
++
+ /* - DRIF0 --------------------------------------------------------------- */
+ static const unsigned int drif0_ctrl_a_pins[] = {
+ 	/* CLK, SYNC */
+@@ -3843,6 +3875,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
++	SH_PFC_PIN_GROUP(can0_data_a),
++	SH_PFC_PIN_GROUP(can0_data_b),
++	SH_PFC_PIN_GROUP(can1_data),
++	SH_PFC_PIN_GROUP(can_clk),
+ 	SH_PFC_PIN_GROUP(drif0_ctrl_a),
+ 	SH_PFC_PIN_GROUP(drif0_data0_a),
+ 	SH_PFC_PIN_GROUP(drif0_data1_a),
+@@ -4154,6 +4190,19 @@ static const char * const avb_groups[] = {
+ 	"avb_avtp_capture_b",
+ };
+ 
++static const char * const can0_groups[] = {
++	"can0_data_a",
++	"can0_data_b",
++};
++
++static const char * const can1_groups[] = {
++	"can1_data",
++};
++
++static const char * const can_clk_groups[] = {
++	"can_clk",
++};
++
+ static const char * const drif0_groups[] = {
+ 	"drif0_ctrl_a",
+ 	"drif0_data0_a",
+@@ -4559,6 +4608,9 @@ static const char * const usb30_groups[] = {
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(can0),
++	SH_PFC_FUNCTION(can1),
++	SH_PFC_FUNCTION(can_clk),
+ 	SH_PFC_FUNCTION(drif0),
+ 	SH_PFC_FUNCTION(drif1),
+ 	SH_PFC_FUNCTION(drif2),
+-- 
+2.19.0
+
diff --git a/patches/0486-pinctrl-sh-pfc-r8a7795-Add-CAN-FD-support.patch b/patches/0486-pinctrl-sh-pfc-r8a7795-Add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..0426ea885ba91b
--- /dev/null
+++ b/patches/0486-pinctrl-sh-pfc-r8a7795-Add-CAN-FD-support.patch
@@ -0,0 +1,90 @@
+From a1fe3648730f5085c2f66d8951f4a672dac7a601 Mon Sep 17 00:00:00 2001
+From: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Date: Fri, 10 Nov 2017 13:58:50 +0000
+Subject: [PATCH 0486/1795] pinctrl: sh-pfc: r8a7795: Add CAN FD support
+
+This patch adds CAN FD[0-1] pinmux support for R-Car H3 ES2.0. The pin
+config is identical to H3 ES1.*.
+
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0e1c7a94c6def25fa2458ad4577b0b9b40443c3b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 37 ++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 59249a990cef..34a2dc471e5a 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1813,6 +1813,29 @@ static const unsigned int can_clk_mux[] = {
+ 	CAN_CLK_MARK,
+ };
+ 
++/* - CAN FD --------------------------------------------------------------- */
++static const unsigned int canfd0_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
++};
++static const unsigned int canfd0_data_a_mux[] = {
++	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
++};
++static const unsigned int canfd0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
++};
++static const unsigned int canfd0_data_b_mux[] = {
++	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
++};
++static const unsigned int canfd1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
++};
++static const unsigned int canfd1_data_mux[] = {
++	CANFD1_TX_MARK,         CANFD1_RX_MARK,
++};
++
+ /* - DRIF0 --------------------------------------------------------------- */
+ static const unsigned int drif0_ctrl_a_pins[] = {
+ 	/* CLK, SYNC */
+@@ -3879,6 +3902,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(can0_data_b),
+ 	SH_PFC_PIN_GROUP(can1_data),
+ 	SH_PFC_PIN_GROUP(can_clk),
++	SH_PFC_PIN_GROUP(canfd0_data_a),
++	SH_PFC_PIN_GROUP(canfd0_data_b),
++	SH_PFC_PIN_GROUP(canfd1_data),
+ 	SH_PFC_PIN_GROUP(drif0_ctrl_a),
+ 	SH_PFC_PIN_GROUP(drif0_data0_a),
+ 	SH_PFC_PIN_GROUP(drif0_data1_a),
+@@ -4203,6 +4229,15 @@ static const char * const can_clk_groups[] = {
+ 	"can_clk",
+ };
+ 
++static const char * const canfd0_groups[] = {
++	"canfd0_data_a",
++	"canfd0_data_b",
++};
++
++static const char * const canfd1_groups[] = {
++	"canfd1_data",
++};
++
+ static const char * const drif0_groups[] = {
+ 	"drif0_ctrl_a",
+ 	"drif0_data0_a",
+@@ -4611,6 +4646,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(can0),
+ 	SH_PFC_FUNCTION(can1),
+ 	SH_PFC_FUNCTION(can_clk),
++	SH_PFC_FUNCTION(canfd0),
++	SH_PFC_FUNCTION(canfd1),
+ 	SH_PFC_FUNCTION(drif0),
+ 	SH_PFC_FUNCTION(drif1),
+ 	SH_PFC_FUNCTION(drif2),
+-- 
+2.19.0
+
diff --git a/patches/0487-pinctrl-sh-pfc-Add-PORT_GP_CFG_-6-22-helper-macros.patch b/patches/0487-pinctrl-sh-pfc-Add-PORT_GP_CFG_-6-22-helper-macros.patch
new file mode 100644
index 00000000000000..f97cdf83ee5641
--- /dev/null
+++ b/patches/0487-pinctrl-sh-pfc-Add-PORT_GP_CFG_-6-22-helper-macros.patch
@@ -0,0 +1,62 @@
+From ea706063ca81a887b331105bbdf5142288077c7a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 10 Nov 2017 20:59:00 +0300
+Subject: [PATCH 0487/1795] pinctrl: sh-pfc: Add PORT_GP_CFG_{6|22}() helper
+ macros
+
+They follow the style of the existing PORT_GP_CFG_<n>() macros and
+will be used by a follow-up  patch for the R8A77970 SoC.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5a0e698876479b71de885fdc181c00ecee5a61a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 213108a058fe..efe07bcca8d0 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -389,10 +389,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
+ 	PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
+ #define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)
+ 
+-#define PORT_GP_CFG_8(bank, fn, sfx, cfg)				\
++#define PORT_GP_CFG_6(bank, fn, sfx, cfg)				\
+ 	PORT_GP_CFG_4(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),				\
+-	PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),				\
++	PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
++#define PORT_GP_6(bank, fn, sfx)	PORT_GP_CFG_6(bank, fn, sfx, 0)
++
++#define PORT_GP_CFG_8(bank, fn, sfx, cfg)				\
++	PORT_GP_CFG_6(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
+ #define PORT_GP_8(bank, fn, sfx)	PORT_GP_CFG_8(bank, fn, sfx, 0)
+@@ -450,9 +454,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
+ 	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
+ #define PORT_GP_21(bank, fn, sfx)	PORT_GP_CFG_21(bank, fn, sfx, 0)
+ 
+-#define PORT_GP_CFG_23(bank, fn, sfx, cfg)				\
++#define PORT_GP_CFG_22(bank, fn, sfx, cfg)				\
+ 	PORT_GP_CFG_21(bank, fn, sfx, cfg),				\
+-	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),				\
++	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
++#define PORT_GP_22(bank, fn, sfx)	PORT_GP_CFG_22(bank, fn, sfx, 0)
++
++#define PORT_GP_CFG_23(bank, fn, sfx, cfg)				\
++	PORT_GP_CFG_22(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
+ #define PORT_GP_23(bank, fn, sfx)	PORT_GP_CFG_23(bank, fn, sfx, 0)
+ 
+-- 
+2.19.0
+
diff --git a/patches/0488-pinctrl-sh-pfc-Add-R8A77970-PFC-support.patch b/patches/0488-pinctrl-sh-pfc-Add-R8A77970-PFC-support.patch
new file mode 100644
index 00000000000000..c430a579102dd1
--- /dev/null
+++ b/patches/0488-pinctrl-sh-pfc-Add-R8A77970-PFC-support.patch
@@ -0,0 +1,2438 @@
+From 290e5355e1d7496c295761d2bb8a6b0683cd8a0a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 10 Nov 2017 20:59:01 +0300
+Subject: [PATCH 0488/1795] pinctrl: sh-pfc: Add R8A77970 PFC support
+
+Add the PFC support for the R8A77970 SoC including pin groups for some
+on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM,
+VIN...
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+[geert: Drop EtherAVB for now]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit b92ac66a1819602b1427ac72d4a70c10ba7640ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/pinctrl/renesas,pfc-pinctrl.txt  |    1 +
+ drivers/pinctrl/sh-pfc/Kconfig                |    5 +
+ drivers/pinctrl/sh-pfc/Makefile               |    1 +
+ drivers/pinctrl/sh-pfc/core.c                 |    6 +
+ drivers/pinctrl/sh-pfc/pfc-r8a77970.c         | 2329 +++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h               |    1 +
+ 6 files changed, 2343 insertions(+)
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index 9b4f8041c36a..bb1790e0b176 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -24,6 +24,7 @@ Required Properties:
+     - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
+     - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
+     - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
++    - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
+     - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
+     - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+ 
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index 5d5312eb7102..4ed3761418f9 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
+         depends on ARCH_R8A7796
+         select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A77970
++	def_bool y
++	depends on ARCH_R8A77970
++	select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_R8A77995
+         def_bool y
+         depends on ARCH_R8A77995
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index a7903904b64e..22e758ce1fc2 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794)	+= pfc-r8a7794.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795-es1.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
++obj-$(CONFIG_PINCTRL_PFC_R8A77970)	+= pfc-r8a77970.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index cf4ae4bc9115..e9eb7a7c6fac 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 		.data = &r8a7796_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A77970
++	{
++		.compatible = "renesas,pfc-r8a77970",
++		.data = &r8a77970_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_R8A77995
+ 	{
+ 		.compatible = "renesas,pfc-r8a77995",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+new file mode 100644
+index 000000000000..794f12d74449
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+@@ -0,0 +1,2329 @@
++/*
++ * R8A77970 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2016 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
++ *
++ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++ *
++ * R-Car Gen3 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2015  Renesas Electronics Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++
++#include "core.h"
++#include "sh_pfc.h"
++
++#define CPU_ALL_PORT(fn, sfx)						\
++	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
++/*
++ * F_() : just information
++ * FM() : macro for FN_xxx / xxx_MARK
++ */
++
++/* GPSR0 */
++#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
++#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
++#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
++#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
++#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
++#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
++#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
++#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
++#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
++#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
++#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
++#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
++#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
++#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
++#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
++#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
++#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
++#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
++#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
++#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
++#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
++#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
++
++/* GPSR1 */
++#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_27_24)
++#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_23_20)
++#define GPSR1_25	F_(CANFD_CLK_A,		IP8_19_16)
++#define GPSR1_24	F_(CANFD1_RX,		IP8_15_12)
++#define GPSR1_23	F_(CANFD1_TX,		IP8_11_8)
++#define GPSR1_22	F_(CANFD0_RX_A,		IP8_7_4)
++#define GPSR1_21	F_(CANFD0_TX_A,		IP8_3_0)
++#define GPSR1_20	F_(AVB0_AVTP_CAPTURE,	IP7_31_28)
++#define GPSR1_19	FM(AVB0_AVTP_MATCH)
++#define GPSR1_18	FM(AVB0_LINK)
++#define GPSR1_17	FM(AVB0_PHY_INT)
++#define GPSR1_16	FM(AVB0_MAGIC)
++#define GPSR1_15	FM(AVB0_MDC)
++#define GPSR1_14	FM(AVB0_MDIO)
++#define GPSR1_13	FM(AVB0_TXCREFCLK)
++#define GPSR1_12	FM(AVB0_TD3)
++#define GPSR1_11	FM(AVB0_TD2)
++#define GPSR1_10	FM(AVB0_TD1)
++#define GPSR1_9		FM(AVB0_TD0)
++#define GPSR1_8		FM(AVB0_TXC)
++#define GPSR1_7		FM(AVB0_TX_CTL)
++#define GPSR1_6		FM(AVB0_RD3)
++#define GPSR1_5		FM(AVB0_RD2)
++#define GPSR1_4		FM(AVB0_RD1)
++#define GPSR1_3		FM(AVB0_RD0)
++#define GPSR1_2		FM(AVB0_RXC)
++#define GPSR1_1		FM(AVB0_RX_CTL)
++#define GPSR1_0		F_(IRQ0,		IP2_27_24)
++
++/* GPSR2 */
++#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
++#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
++#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
++#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
++#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
++#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
++#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
++#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
++#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
++#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
++#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
++#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
++#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
++#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
++#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
++#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
++#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
++
++/* GPSR3 */
++#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
++#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
++#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
++#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
++#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
++#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
++#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
++#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
++#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
++#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
++#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
++#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
++#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
++#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
++#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
++#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
++#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
++
++/* GPSR4 */
++#define GPSR4_5		F_(SDA2,		IP7_27_24)
++#define GPSR4_4		F_(SCL2,		IP7_23_20)
++#define GPSR4_3		F_(SDA1,		IP7_19_16)
++#define GPSR4_2		F_(SCL1,		IP7_15_12)
++#define GPSR4_1		F_(SDA0,		IP7_11_8)
++#define GPSR4_0		F_(SCL0,		IP7_7_4)
++
++/* GPSR5 */
++#define GPSR5_14	FM(RPC_INT_N)
++#define GPSR5_13	FM(RPC_WP_N)
++#define GPSR5_12	FM(RPC_RESET_N)
++#define GPSR5_11	FM(QSPI1_SSL)
++#define GPSR5_10	FM(QSPI1_IO3)
++#define GPSR5_9		FM(QSPI1_IO2)
++#define GPSR5_8		FM(QSPI1_MISO_IO1)
++#define GPSR5_7		FM(QSPI1_MOSI_IO0)
++#define GPSR5_6		FM(QSPI1_SPCLK)
++#define GPSR5_5		FM(QSPI0_SSL)
++#define GPSR5_4		FM(QSPI0_IO3)
++#define GPSR5_3		FM(QSPI0_IO2)
++#define GPSR5_2		FM(QSPI0_MISO_IO1)
++#define GPSR5_1		FM(QSPI0_MOSI_IO0)
++#define GPSR5_0		FM(QSPI0_SPCLK)
++
++
++/* IPSRx */		/* 0 */				/* 1 */			/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
++#define IP0_3_0		FM(DU_DR2)			FM(HSCK0)		F_(0, 0)	FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_7_4		FM(DU_DR3)			FM(HRTS0_N)		F_(0, 0)	FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_11_8	FM(DU_DR4)			FM(HCTS0_N)		F_(0, 0)	FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0)
++#define IP0_15_12	FM(DU_DR5)			FM(HTX0)		F_(0, 0)	FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_19_16	FM(DU_DR6)			FM(MSIOF3_RXD)		F_(0, 0)	FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(DU_DR7)			FM(MSIOF3_TXD)		F_(0, 0)	FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_27_24	FM(DU_DG2)			FM(MSIOF3_SS1)		F_(0, 0)	FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_31_28	FM(DU_DG3)			FM(MSIOF3_SS2)		F_(0, 0)	FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_3_0		FM(DU_DG4)			F_(0, 0)		F_(0, 0)	FM(A8)		FM(FSO_CFE_0_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(DU_DG5)			F_(0, 0)		F_(0, 0)	FM(A9)		FM(FSO_CFE_1_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(DU_DG6)			F_(0, 0)		F_(0, 0)	FM(A10)		FM(FSO_TOE_N_A) 	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(DU_DG7)			F_(0, 0)		F_(0, 0)	FM(A11)		FM(IRQ1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(DU_DB2)			F_(0, 0)		F_(0, 0)	FM(A12)		FM(IRQ2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(DU_DB3)			F_(0, 0)		F_(0, 0)	FM(A13)		FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(DU_DB4)			F_(0, 0)		F_(0, 0)	FM(A14)		FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_31_28	FM(DU_DB5)			F_(0, 0)		F_(0, 0)	FM(A15)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_3_0		FM(DU_DB6)			F_(0, 0)		F_(0, 0)	FM(A16)		FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_7_4		FM(DU_DB7)			F_(0, 0)		F_(0, 0)	FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(SCIF_CLK_A)		F_(0, 0)	FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(HRX0)		F_(0, 0)	FM(A19)		FM(IRQ3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_27_24	FM(IRQ0)			FM(CC5_OSCOUT)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)		FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)		F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)	F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N_TANS)	F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)	F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_23_20	FM(VI0_DATA2)			FM(AVB0_AVTP_PPS)	FM(SDA3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		FM(SCL3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N_TANS)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		FM(PWM0_A)	FM(A22)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)	FM(A23)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)	FM(A24)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)	FM(A25)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)	FM(CS1_N)	FM(FSCLKST2_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)	FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)	FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)	FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)	FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)	FM(D3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)	FM(D4)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)	FM(D5)		FM(MMC_D0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)	FM(D6)		FM(MMC_D1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)	FM(D7)		FM(MMC_D2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_7_4		FM(VI1_DATA5)			F_(0,0)			FM(SCK4)	FM(D8)		FM(MMC_D3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_11_8	FM(VI1_DATA6)			F_(0,0)			FM(RX4)		FM(D9)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_15_12	FM(VI1_DATA7)			F_(0,0)			FM(TX4)		FM(D10)		FM(MMC_D4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_19_16	FM(VI1_DATA8)			F_(0,0)			FM(CTS4_N)	FM(D11)		FM(MMC_D5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_23_20	FM(VI1_DATA9)			F_(0,0)			FM(RTS4_N_TANS)	FM(D12)		FM(MMC_D6)		FM(SCL3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(VI1_DATA10)			F_(0,0)			F_(0, 0)	FM(D13)		FM(MMC_D7)		FM(SDA3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		FM(IRQ4)	FM(D14)		FM(MMC_WP)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		FM(IRQ5)	FM(D15)		FM(MMC_CD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_7_4		FM(SCL0)			FM(DU_DR0)		FM(TPU0TO0)	FM(CLKOUT)	F_(0, 0)		FM(MSIOF0_RXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_11_8	FM(SDA0)			FM(DU_DR1)		FM(TPU0TO1)	FM(BS_N)	FM(SCK0)		FM(MSIOF0_TXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_15_12	FM(SCL1)			FM(DU_DG0)		FM(TPU0TO2)	FM(RD_N)	FM(CTS0_N)		FM(MSIOF0_SCK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_19_16	FM(SDA1)			FM(DU_DG1)		FM(TPU0TO3)	FM(WE0_N)	FM(RTS0_N_TANS)		FM(MSIOF0_SYNC)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_23_20	FM(SCL2)			FM(DU_DB0)		FM(TCLK1_A)	FM(WE1_N)	FM(RX0)			FM(MSIOF0_SS1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_27_24	FM(SDA2)			FM(DU_DB1)		FM(TCLK2_A)	FM(EX_WAIT0)	FM(TX0)			FM(MSIOF0_SS2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_31_28	FM(AVB0_AVTP_CAPTURE)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(FSCLKST2_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_3_0		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)	FM(DU_DISP)	FM(FSCLKST2_N_C)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_7_4		FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)	FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_11_8	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)	FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_15_12	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)	FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0)
++
++#define PINMUX_GPSR	\
++\
++		GPSR1_27 \
++		GPSR1_26 \
++		GPSR1_25 \
++		GPSR1_24 \
++		GPSR1_23 \
++		GPSR1_22 \
++GPSR0_21	GPSR1_21 \
++GPSR0_20	GPSR1_20 \
++GPSR0_19	GPSR1_19 \
++GPSR0_18	GPSR1_18 \
++GPSR0_17	GPSR1_17 \
++GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16 \
++GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15 \
++GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14 \
++GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13 \
++GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12 \
++GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11 \
++GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10			GPSR5_10 \
++GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9				GPSR5_9 \
++GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8				GPSR5_8 \
++GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7				GPSR5_7 \
++GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6				GPSR5_6 \
++GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
++GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
++GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
++GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
++GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
++GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
++
++#define PINMUX_IPSR	\
++\
++FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
++FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
++FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
++FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
++FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
++FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
++FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
++FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
++\
++FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
++FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
++FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
++FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
++FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
++FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
++FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
++FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
++\
++FM(IP8_3_0)	IP8_3_0 \
++FM(IP8_7_4)	IP8_7_4 \
++FM(IP8_11_8)	IP8_11_8 \
++FM(IP8_15_12)	IP8_15_12 \
++FM(IP8_19_16)	IP8_19_16 \
++FM(IP8_23_20)	IP8_23_20 \
++FM(IP8_27_24)	IP8_27_24 \
++FM(IP8_31_28)	IP8_31_28
++
++/* MOD_SEL0 */		/* 0 */			/* 1 */
++#define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
++#define MOD_SEL0_10	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
++#define MOD_SEL0_9	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
++#define MOD_SEL0_8	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
++#define MOD_SEL0_7	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
++#define MOD_SEL0_6	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
++#define MOD_SEL0_5	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
++#define MOD_SEL0_4	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
++#define MOD_SEL0_3	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
++#define MOD_SEL0_2	FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
++#define MOD_SEL0_1	FM(SEL_RSP_0)		FM(SEL_RSP_1)
++#define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
++
++#define PINMUX_MOD_SELS \
++\
++MOD_SEL0_11 \
++MOD_SEL0_10 \
++MOD_SEL0_9 \
++MOD_SEL0_8 \
++MOD_SEL0_7 \
++MOD_SEL0_6 \
++MOD_SEL0_5 \
++MOD_SEL0_4 \
++MOD_SEL0_3 \
++MOD_SEL0_2 \
++MOD_SEL0_1 \
++MOD_SEL0_0
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++#define F_(x, y)
++#define FM(x)   FN_##x,
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_FUNCTION_END,
++#undef F_
++#undef FM
++
++#define F_(x, y)
++#define FM(x)	x##_MARK,
++	PINMUX_MARK_BEGIN,
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_MARK_END,
++#undef F_
++#undef FM
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(),
++
++	PINMUX_SINGLE(AVB0_RX_CTL),
++	PINMUX_SINGLE(AVB0_RXC),
++	PINMUX_SINGLE(AVB0_RD0),
++	PINMUX_SINGLE(AVB0_RD1),
++	PINMUX_SINGLE(AVB0_RD2),
++	PINMUX_SINGLE(AVB0_RD3),
++	PINMUX_SINGLE(AVB0_TX_CTL),
++	PINMUX_SINGLE(AVB0_TXC),
++	PINMUX_SINGLE(AVB0_TD0),
++	PINMUX_SINGLE(AVB0_TD1),
++	PINMUX_SINGLE(AVB0_TD2),
++	PINMUX_SINGLE(AVB0_TD3),
++	PINMUX_SINGLE(AVB0_TXCREFCLK),
++	PINMUX_SINGLE(AVB0_MDIO),
++	PINMUX_SINGLE(AVB0_MDC),
++	PINMUX_SINGLE(AVB0_MAGIC),
++	PINMUX_SINGLE(AVB0_PHY_INT),
++	PINMUX_SINGLE(AVB0_LINK),
++	PINMUX_SINGLE(AVB0_AVTP_MATCH),
++
++	PINMUX_SINGLE(QSPI0_SPCLK),
++	PINMUX_SINGLE(QSPI0_MOSI_IO0),
++	PINMUX_SINGLE(QSPI0_MISO_IO1),
++	PINMUX_SINGLE(QSPI0_IO2),
++	PINMUX_SINGLE(QSPI0_IO3),
++	PINMUX_SINGLE(QSPI0_SSL),
++	PINMUX_SINGLE(QSPI1_SPCLK),
++	PINMUX_SINGLE(QSPI1_MOSI_IO0),
++	PINMUX_SINGLE(QSPI1_MISO_IO1),
++	PINMUX_SINGLE(QSPI1_IO2),
++	PINMUX_SINGLE(QSPI1_IO3),
++	PINMUX_SINGLE(QSPI1_SSL),
++	PINMUX_SINGLE(RPC_RESET_N),
++	PINMUX_SINGLE(RPC_WP_N),
++	PINMUX_SINGLE(RPC_INT_N),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
++	PINMUX_IPSR_GPSR(IP0_3_0,	HSCK0),
++	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
++
++	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
++	PINMUX_IPSR_GPSR(IP0_7_4,	HRTS0_N),
++	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
++
++	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
++	PINMUX_IPSR_GPSR(IP0_11_8,	HCTS0_N),
++	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
++
++	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
++	PINMUX_IPSR_GPSR(IP0_15_12,	HTX0),
++	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
++
++	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
++	PINMUX_IPSR_GPSR(IP0_19_16,	MSIOF3_RXD),
++	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
++
++	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
++	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF3_TXD),
++	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
++
++	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
++	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF3_SS1),
++	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
++
++	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
++	PINMUX_IPSR_GPSR(IP0_31_28,	MSIOF3_SS2),
++	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
++	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
++	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
++	PINMUX_IPSR_MSEL(IP1_3_0,	FSO_CFE_0_N_A,	SEL_RFSO_0),
++
++	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
++	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
++	PINMUX_IPSR_MSEL(IP1_7_4,	FSO_CFE_1_N_A,	SEL_RFSO_0),
++
++	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
++	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
++	PINMUX_IPSR_MSEL(IP1_11_8,	FSO_TOE_N_A,	SEL_RFSO_0),
++
++	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
++	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
++	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ1),
++
++	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
++	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
++	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ2),
++
++	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
++	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
++	PINMUX_IPSR_GPSR(IP1_23_20,	FXR_CLKOUT1),
++
++	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
++	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
++	PINMUX_IPSR_GPSR(IP1_27_24,	FXR_CLKOUT2),
++
++	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
++	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
++	PINMUX_IPSR_GPSR(IP1_31_28,	FXR_TXENA_N),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
++	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
++	PINMUX_IPSR_GPSR(IP2_3_0,	FXR_TXENB_N),
++
++	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
++	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
++
++	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
++	PINMUX_IPSR_MSEL(IP2_11_8,	SCIF_CLK_A,	SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
++
++	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
++	PINMUX_IPSR_GPSR(IP2_15_12,	HRX0),
++	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
++	PINMUX_IPSR_GPSR(IP2_15_12,	IRQ3),
++
++	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
++	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
++
++	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
++
++	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
++	PINMUX_IPSR_GPSR(IP2_27_24,	CC5_OSCOUT),
++
++	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
++	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
++	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
++	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
++	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
++	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
++	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
++
++	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
++	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
++	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N_TANS),
++	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
++
++	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
++	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
++	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
++	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A,	SEL_RSP_0),
++
++	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
++	PINMUX_IPSR_GPSR(IP3_23_20,	AVB0_AVTP_PPS),
++	PINMUX_IPSR_MSEL(IP3_23_20,	SDA3_A,		SEL_I2C3_0),
++
++	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
++	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
++	PINMUX_IPSR_MSEL(IP3_27_24,	SCL3_A,		SEL_I2C3_0),
++
++	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
++	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
++	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A,	SEL_SCIF1_0),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
++	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
++	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A,	SEL_SCIF1_0),
++
++	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
++	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
++	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
++
++	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
++	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
++	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N_TANS),
++
++	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
++	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
++	PINMUX_IPSR_MSEL(IP4_15_12,	PWM0_A,	SEL_PWM0_0),
++
++	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
++	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
++	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A,	SEL_PWM1_0),
++	PINMUX_IPSR_MSEL(IP4_19_16,	FSO_CFE_0_N_B,	SEL_RFSO_1),
++
++	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
++	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
++	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A,	SEL_PWM2_0),
++	PINMUX_IPSR_MSEL(IP4_23_20,	FSO_CFE_1_N_B,	SEL_RFSO_1),
++
++	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
++	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
++	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A,	SEL_PWM3_0),
++	PINMUX_IPSR_MSEL(IP4_27_24,	FSO_TOE_N_B,	SEL_RFSO_1),
++
++	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
++	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
++	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A,	SEL_PWM4_0),
++	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
++	PINMUX_IPSR_GPSR(IP4_31_28,	FSCLKST2_N_A),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
++	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
++	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
++
++	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
++	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
++	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
++
++	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
++	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
++
++	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
++	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
++
++	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
++	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
++	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
++
++	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
++	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CMD),
++
++	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
++	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B,	SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
++	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_D0),
++
++	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
++	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B,	SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
++	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_D1),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
++	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B,	SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
++	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D2),
++
++	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
++	PINMUX_IPSR_GPSR(IP6_7_4,	SCK4),
++	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
++	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D3),
++
++	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
++	PINMUX_IPSR_GPSR(IP6_11_8,	RX4),
++	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
++	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_CLK),
++
++	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
++	PINMUX_IPSR_GPSR(IP6_15_12,	TX4),
++	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
++	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D4),
++
++	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
++	PINMUX_IPSR_GPSR(IP6_19_16,	CTS4_N),
++	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
++	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_D5),
++
++	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
++	PINMUX_IPSR_GPSR(IP6_23_20,	RTS4_N_TANS),
++	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
++	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D6),
++	PINMUX_IPSR_MSEL(IP6_23_20,	SCL3_B,	SEL_I2C3_1),
++
++	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
++	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
++	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D7),
++	PINMUX_IPSR_MSEL(IP6_27_24,	SDA3_B,	SEL_I2C3_1),
++
++	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
++	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
++	PINMUX_IPSR_GPSR(IP6_31_28,	IRQ4),
++	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
++	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_WP),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
++	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
++	PINMUX_IPSR_GPSR(IP7_3_0,	IRQ5),
++	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
++	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_CD),
++
++	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	TPU0TO0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
++	PINMUX_IPSR_GPSR(IP7_7_4,	MSIOF0_RXD),
++
++	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
++	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR1),
++	PINMUX_IPSR_GPSR(IP7_11_8,	TPU0TO1),
++	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
++	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
++	PINMUX_IPSR_GPSR(IP7_11_8,	MSIOF0_TXD),
++
++	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
++	PINMUX_IPSR_GPSR(IP7_15_12,	DU_DG0),
++	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
++	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	MSIOF0_SCK),
++
++	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
++	PINMUX_IPSR_GPSR(IP7_19_16,	DU_DG1),
++	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
++	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
++	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N_TANS),
++	PINMUX_IPSR_GPSR(IP7_19_16,	MSIOF0_SYNC),
++
++	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
++	PINMUX_IPSR_GPSR(IP7_23_20,	DU_DB0),
++	PINMUX_IPSR_MSEL(IP7_23_20,	TCLK1_A,	SEL_TMU_0),
++	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
++	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
++	PINMUX_IPSR_GPSR(IP7_23_20,	MSIOF0_SS1),
++
++	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
++	PINMUX_IPSR_GPSR(IP7_27_24,	DU_DB1),
++	PINMUX_IPSR_MSEL(IP7_27_24,	TCLK2_A,	SEL_TMU_0),
++	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
++	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
++	PINMUX_IPSR_GPSR(IP7_27_24,	MSIOF0_SS2),
++
++	PINMUX_IPSR_GPSR(IP7_31_28,	AVB0_AVTP_CAPTURE),
++	PINMUX_IPSR_GPSR(IP7_31_28,	FSCLKST2_N_B),
++
++	/* IPSR8 */
++	PINMUX_IPSR_MSEL(IP8_3_0,	CANFD0_TX_A,	SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_3_0,	FXR_TXDA),
++	PINMUX_IPSR_MSEL(IP8_3_0,	PWM0_B,		SEL_PWM0_1),
++	PINMUX_IPSR_GPSR(IP8_3_0,	DU_DISP),
++	PINMUX_IPSR_GPSR(IP8_3_0,	FSCLKST2_N_C),
++
++	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_RX_A,	SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_7_4,	RXDA_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_7_4,	PWM1_B,		SEL_PWM1_1),
++	PINMUX_IPSR_GPSR(IP8_7_4,	DU_CDE),
++
++	PINMUX_IPSR_GPSR(IP8_11_8,	CANFD1_TX),
++	PINMUX_IPSR_GPSR(IP8_11_8,	FXR_TXDB),
++	PINMUX_IPSR_MSEL(IP8_11_8,	PWM2_B,		SEL_PWM2_1),
++	PINMUX_IPSR_MSEL(IP8_11_8,	TCLK1_B,	SEL_TMU_1),
++	PINMUX_IPSR_MSEL(IP8_11_8,	TX1_B,		SEL_SCIF1_1),
++
++	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_RX),
++	PINMUX_IPSR_GPSR(IP8_15_12,	RXDB_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_15_12,	PWM3_B,		SEL_PWM3_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK2_B,	SEL_TMU_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	RX1_B,		SEL_SCIF1_1),
++
++	PINMUX_IPSR_MSEL(IP8_19_16,	CANFD_CLK_A,	SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_19_16,	CLK_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_19_16,	PWM4_B,		SEL_PWM4_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	SPEEDIN_B,	SEL_RSP_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	SCIF_CLK_B,	SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKIN),
++	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKEN_IN),
++
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKOUT),
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_OUT),
++};
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++};
++
++/* - CANFD Clock ------------------------------------------------------------ */
++static const unsigned int canfd_clk_a_pins[] = {
++	/* CANFD_CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int canfd_clk_a_mux[] = {
++	CANFD_CLK_A_MARK,
++};
++static const unsigned int canfd_clk_b_pins[] = {
++	/* CANFD_CLK */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int canfd_clk_b_mux[] = {
++	CANFD_CLK_B_MARK,
++};
++
++/* - CANFD0 ----------------------------------------------------------------- */
++static const unsigned int canfd0_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
++};
++static const unsigned int canfd0_data_a_mux[] = {
++	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
++};
++static const unsigned int canfd0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int canfd0_data_b_mux[] = {
++	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
++};
++
++/* - CANFD1 ----------------------------------------------------------------- */
++static const unsigned int canfd1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
++};
++static const unsigned int canfd1_data_mux[] = {
++	CANFD1_TX_MARK, CANFD1_RX_MARK,
++};
++
++/* - DU --------------------------------------------------------------------- */
++static const unsigned int du_rgb666_pins[] = {
++	/* R[7:2], G[7:2], B[7:2] */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
++};
++static const unsigned int du_rgb666_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
++	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
++	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
++	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
++};
++static const unsigned int du_clk_out_pins[] = {
++	/* DOTCLKOUT */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int du_clk_out_mux[] = {
++	DU_DOTCLKOUT_MARK,
++};
++static const unsigned int du_sync_pins[] = {
++	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
++	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
++};
++static const unsigned int du_sync_mux[] = {
++	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
++};
++static const unsigned int du_oddf_pins[] = {
++	/* EXODDF/ODDF/DISP/CDE */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int du_oddf_mux[] = {
++	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
++};
++static const unsigned int du_cde_pins[] = {
++	/* CDE */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int du_cde_mux[] = {
++	DU_CDE_MARK,
++};
++static const unsigned int du_disp_pins[] = {
++	/* DISP */
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int du_disp_mux[] = {
++	DU_DISP_MARK,
++};
++
++/* - HSCIF0 ----------------------------------------------------------------- */
++static const unsigned int hscif0_data_pins[] = {
++	/* HRX, HTX */
++	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int hscif0_data_mux[] = {
++	HRX0_MARK, HTX0_MARK,
++};
++static const unsigned int hscif0_clk_pins[] = {
++	/* HSCK */
++	RCAR_GP_PIN(0, 0),
++};
++static const unsigned int hscif0_clk_mux[] = {
++	HSCK0_MARK,
++};
++static const unsigned int hscif0_ctrl_pins[] = {
++	/* HRTS#, HCTS# */
++	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
++};
++static const unsigned int hscif0_ctrl_mux[] = {
++	HRTS0_N_MARK, HCTS0_N_MARK,
++};
++
++/* - HSCIF1 ----------------------------------------------------------------- */
++static const unsigned int hscif1_data_pins[] = {
++	/* HRX, HTX */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int hscif1_data_mux[] = {
++	HRX1_MARK, HTX1_MARK,
++};
++static const unsigned int hscif1_clk_pins[] = {
++	/* HSCK */
++	RCAR_GP_PIN(2, 7),
++};
++static const unsigned int hscif1_clk_mux[] = {
++	HSCK1_MARK,
++};
++static const unsigned int hscif1_ctrl_pins[] = {
++	/* HRTS#, HCTS# */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int hscif1_ctrl_mux[] = {
++	HRTS1_N_MARK, HCTS1_N_MARK,
++};
++
++/* - HSCIF2 ----------------------------------------------------------------- */
++static const unsigned int hscif2_data_pins[] = {
++	/* HRX, HTX */
++	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
++};
++static const unsigned int hscif2_data_mux[] = {
++	HRX2_MARK, HTX2_MARK,
++};
++static const unsigned int hscif2_clk_pins[] = {
++	/* HSCK */
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int hscif2_clk_mux[] = {
++	HSCK2_MARK,
++};
++static const unsigned int hscif2_ctrl_pins[] = {
++	/* HRTS#, HCTS# */
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int hscif2_ctrl_mux[] = {
++	HRTS2_N_MARK, HCTS2_N_MARK,
++};
++
++/* - HSCIF3 ----------------------------------------------------------------- */
++static const unsigned int hscif3_data_pins[] = {
++	/* HRX, HTX */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int hscif3_data_mux[] = {
++	HRX3_MARK, HTX3_MARK,
++};
++static const unsigned int hscif3_clk_pins[] = {
++	/* HSCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int hscif3_clk_mux[] = {
++	HSCK3_MARK,
++};
++static const unsigned int hscif3_ctrl_pins[] = {
++	/* HRTS#, HCTS# */
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
++};
++static const unsigned int hscif3_ctrl_mux[] = {
++	HRTS3_N_MARK, HCTS3_N_MARK,
++};
++
++/* - I2C0 ------------------------------------------------------------------- */
++static const unsigned int i2c0_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
++};
++static const unsigned int i2c0_mux[] = {
++	SDA0_MARK, SCL0_MARK,
++};
++
++/* - I2C1 ------------------------------------------------------------------- */
++static const unsigned int i2c1_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int i2c1_mux[] = {
++	SDA1_MARK, SCL1_MARK,
++};
++
++/* - I2C2 ------------------------------------------------------------------- */
++static const unsigned int i2c2_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
++};
++static const unsigned int i2c2_mux[] = {
++	SDA2_MARK, SCL2_MARK,
++};
++
++/* - I2C3 ------------------------------------------------------------------- */
++static const unsigned int i2c3_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++};
++static const unsigned int i2c3_a_mux[] = {
++	SDA3_A_MARK, SCL3_A_MARK,
++};
++static const unsigned int i2c3_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
++};
++static const unsigned int i2c3_b_mux[] = {
++	SDA3_B_MARK, SCL3_B_MARK,
++};
++
++/* - I2C4 ------------------------------------------------------------------- */
++static const unsigned int i2c4_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int i2c4_mux[] = {
++	SDA4_MARK, SCL4_MARK,
++};
++
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(0, 11),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(0, 19),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(3, 15),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(3, 16),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
++/* - MMC -------------------------------------------------------------------- */
++static const unsigned int mmc_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 6),
++};
++static const unsigned int mmc_data1_mux[] = {
++	MMC_D0_MARK,
++};
++static const unsigned int mmc_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++};
++static const unsigned int mmc_data4_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++};
++static const unsigned int mmc_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
++};
++static const unsigned int mmc_data8_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++	MMC_D4_MARK, MMC_D5_MARK,
++	MMC_D6_MARK, MMC_D7_MARK,
++};
++static const unsigned int mmc_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
++};
++static const unsigned int mmc_ctrl_mux[] = {
++	MMC_CLK_MARK, MMC_CMD_MARK,
++};
++static const unsigned int mmc_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 16),
++};
++static const unsigned int mmc_cd_mux[] = {
++	MMC_CD_MARK,
++};
++static const unsigned int mmc_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 15),
++};
++static const unsigned int mmc_wp_mux[] = {
++	MMC_WP_MARK,
++};
++
++/* - MSIOF0 ----------------------------------------------------------------- */
++static const unsigned int msiof0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 2),
++};
++static const unsigned int msiof0_clk_mux[] = {
++	MSIOF0_SCK_MARK,
++};
++static const unsigned int msiof0_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(4, 3),
++};
++static const unsigned int msiof0_sync_mux[] = {
++	MSIOF0_SYNC_MARK,
++};
++static const unsigned int msiof0_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(4, 4),
++};
++static const unsigned int msiof0_ss1_mux[] = {
++	MSIOF0_SS1_MARK,
++};
++static const unsigned int msiof0_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(4, 5),
++};
++static const unsigned int msiof0_ss2_mux[] = {
++	MSIOF0_SS2_MARK,
++};
++static const unsigned int msiof0_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int msiof0_txd_mux[] = {
++	MSIOF0_TXD_MARK,
++};
++static const unsigned int msiof0_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(4, 0),
++};
++static const unsigned int msiof0_rxd_mux[] = {
++	MSIOF0_RXD_MARK,
++};
++
++/* - MSIOF1 ----------------------------------------------------------------- */
++static const unsigned int msiof1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(3, 2),
++};
++static const unsigned int msiof1_clk_mux[] = {
++	MSIOF1_SCK_MARK,
++};
++static const unsigned int msiof1_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(3, 3),
++};
++static const unsigned int msiof1_sync_mux[] = {
++	MSIOF1_SYNC_MARK,
++};
++static const unsigned int msiof1_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int msiof1_ss1_mux[] = {
++	MSIOF1_SS1_MARK,
++};
++static const unsigned int msiof1_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int msiof1_ss2_mux[] = {
++	MSIOF1_SS2_MARK,
++};
++static const unsigned int msiof1_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int msiof1_txd_mux[] = {
++	MSIOF1_TXD_MARK,
++};
++static const unsigned int msiof1_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int msiof1_rxd_mux[] = {
++	MSIOF1_RXD_MARK,
++};
++
++/* - MSIOF2 ----------------------------------------------------------------- */
++static const unsigned int msiof2_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int msiof2_clk_mux[] = {
++	MSIOF2_SCK_MARK,
++};
++static const unsigned int msiof2_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int msiof2_sync_mux[] = {
++	MSIOF2_SYNC_MARK,
++};
++static const unsigned int msiof2_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int msiof2_ss1_mux[] = {
++	MSIOF2_SS1_MARK,
++};
++static const unsigned int msiof2_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int msiof2_ss2_mux[] = {
++	MSIOF2_SS2_MARK,
++};
++static const unsigned int msiof2_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int msiof2_txd_mux[] = {
++	MSIOF2_TXD_MARK,
++};
++static const unsigned int msiof2_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int msiof2_rxd_mux[] = {
++	MSIOF2_RXD_MARK,
++};
++
++/* - MSIOF3 ----------------------------------------------------------------- */
++static const unsigned int msiof3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 20),
++};
++static const unsigned int msiof3_clk_mux[] = {
++	MSIOF3_SCK_MARK,
++};
++static const unsigned int msiof3_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int msiof3_sync_mux[] = {
++	MSIOF3_SYNC_MARK,
++};
++static const unsigned int msiof3_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(0, 6),
++};
++static const unsigned int msiof3_ss1_mux[] = {
++	MSIOF3_SS1_MARK,
++};
++static const unsigned int msiof3_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(0, 7),
++};
++static const unsigned int msiof3_ss2_mux[] = {
++	MSIOF3_SS2_MARK,
++};
++static const unsigned int msiof3_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(0, 5),
++};
++static const unsigned int msiof3_txd_mux[] = {
++	MSIOF3_TXD_MARK,
++};
++static const unsigned int msiof3_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(0, 4),
++};
++static const unsigned int msiof3_rxd_mux[] = {
++	MSIOF3_RXD_MARK,
++};
++
++/* - PWM0 ------------------------------------------------------------------- */
++static const unsigned int pwm0_a_pins[] = {
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int pwm0_a_mux[] = {
++	PWM0_A_MARK,
++};
++static const unsigned int pwm0_b_pins[] = {
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int pwm0_b_mux[] = {
++	PWM0_B_MARK,
++};
++
++/* - PWM1 ------------------------------------------------------------------- */
++static const unsigned int pwm1_a_pins[] = {
++	RCAR_GP_PIN(2, 13),
++};
++static const unsigned int pwm1_a_mux[] = {
++	PWM1_A_MARK,
++};
++static const unsigned int pwm1_b_pins[] = {
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++
++/* - PWM2 ------------------------------------------------------------------- */
++static const unsigned int pwm2_a_pins[] = {
++	RCAR_GP_PIN(2, 14),
++};
++static const unsigned int pwm2_a_mux[] = {
++	PWM2_A_MARK,
++};
++static const unsigned int pwm2_b_pins[] = {
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++
++/* - PWM3 ------------------------------------------------------------------- */
++static const unsigned int pwm3_a_pins[] = {
++	RCAR_GP_PIN(2, 15),
++};
++static const unsigned int pwm3_a_mux[] = {
++	PWM3_A_MARK,
++};
++static const unsigned int pwm3_b_pins[] = {
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++
++/* - PWM4 ------------------------------------------------------------------- */
++static const unsigned int pwm4_a_pins[] = {
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int pwm4_a_mux[] = {
++	PWM4_A_MARK,
++};
++static const unsigned int pwm4_b_pins[] = {
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int pwm4_b_mux[] = {
++	PWM4_B_MARK,
++};
++
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int scif0_data_mux[] = {
++	RX0_MARK, TX0_MARK,
++};
++static const unsigned int scif0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int scif0_clk_mux[] = {
++	SCK0_MARK,
++};
++static const unsigned int scif0_ctrl_pins[] = {
++	/* RTS#, CTS# */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int scif0_ctrl_mux[] = {
++	RTS0_N_TANS_MARK, CTS0_N_MARK,
++};
++
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int scif1_data_a_mux[] = {
++	RX1_A_MARK, TX1_A_MARK,
++};
++static const unsigned int scif1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int scif1_clk_mux[] = {
++	SCK1_MARK,
++};
++static const unsigned int scif1_ctrl_pins[] = {
++	/* RTS#, CTS# */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int scif1_ctrl_mux[] = {
++	RTS1_N_TANS_MARK, CTS1_N_MARK,
++};
++static const unsigned int scif1_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
++};
++static const unsigned int scif1_data_b_mux[] = {
++	RX1_B_MARK, TX1_B_MARK,
++};
++
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++};
++static const unsigned int scif3_data_mux[] = {
++	RX3_MARK, TX3_MARK,
++};
++static const unsigned int scif3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int scif3_clk_mux[] = {
++	SCK3_MARK,
++};
++static const unsigned int scif3_ctrl_pins[] = {
++	/* RTS#, CTS# */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int scif3_ctrl_mux[] = {
++	RTS3_N_TANS_MARK, CTS3_N_MARK,
++};
++
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int scif4_data_mux[] = {
++	RX4_MARK, TX4_MARK,
++};
++static const unsigned int scif4_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(3, 9),
++};
++static const unsigned int scif4_clk_mux[] = {
++	SCK4_MARK,
++};
++static const unsigned int scif4_ctrl_pins[] = {
++	/* RTS#, CTS# */
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
++};
++static const unsigned int scif4_ctrl_mux[] = {
++	RTS4_N_TANS_MARK, CTS4_N_MARK,
++};
++
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(4, 4),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(4, 5),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
++/* - VIN0 ------------------------------------------------------------------- */
++static const unsigned int vin0_data8_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++};
++static const unsigned int vin0_data8_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++};
++static const unsigned int vin0_data10_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int vin0_data10_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++};
++static const unsigned int vin0_data12_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++};
++static const unsigned int vin0_data12_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++};
++static const unsigned int vin0_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int vin0_sync_mux[] = {
++	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
++};
++static const unsigned int vin0_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int vin0_field_mux[] = {
++	VI0_FIELD_MARK,
++};
++static const unsigned int vin0_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int vin0_clkenb_mux[] = {
++	VI0_CLKENB_MARK,
++};
++static const unsigned int vin0_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int vin0_clk_mux[] = {
++	VI0_CLK_MARK,
++};
++
++/* - VIN1 ------------------------------------------------------------------- */
++static const unsigned int vin1_data8_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int vin1_data8_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++};
++static const unsigned int vin1_data10_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++};
++static const unsigned int vin1_data10_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK,  VI1_DATA9_MARK,
++};
++static const unsigned int vin1_data12_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int vin1_data12_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK,  VI1_DATA9_MARK,
++	VI1_DATA10_MARK, VI1_DATA11_MARK,
++};
++static const unsigned int vin1_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
++};
++static const unsigned int vin1_sync_mux[] = {
++	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
++};
++static const unsigned int vin1_field_pins[] = {
++	RCAR_GP_PIN(3, 16),
++};
++static const unsigned int vin1_field_mux[] = {
++	/* FIELD */
++	VI1_FIELD_MARK,
++};
++static const unsigned int vin1_clkenb_pins[] = {
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int vin1_clkenb_mux[] = {
++	/* CLKENB */
++	VI1_CLKENB_MARK,
++};
++static const unsigned int vin1_clk_pins[] = {
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int vin1_clk_mux[] = {
++	/* CLK */
++	VI1_CLK_MARK,
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(canfd_clk_a),
++	SH_PFC_PIN_GROUP(canfd_clk_b),
++	SH_PFC_PIN_GROUP(canfd0_data_a),
++	SH_PFC_PIN_GROUP(canfd0_data_b),
++	SH_PFC_PIN_GROUP(canfd1_data),
++	SH_PFC_PIN_GROUP(du_rgb666),
++	SH_PFC_PIN_GROUP(du_clk_out),
++	SH_PFC_PIN_GROUP(du_sync),
++	SH_PFC_PIN_GROUP(du_oddf),
++	SH_PFC_PIN_GROUP(du_cde),
++	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hscif0_data),
++	SH_PFC_PIN_GROUP(hscif0_clk),
++	SH_PFC_PIN_GROUP(hscif0_ctrl),
++	SH_PFC_PIN_GROUP(hscif1_data),
++	SH_PFC_PIN_GROUP(hscif1_clk),
++	SH_PFC_PIN_GROUP(hscif1_ctrl),
++	SH_PFC_PIN_GROUP(hscif2_data),
++	SH_PFC_PIN_GROUP(hscif2_clk),
++	SH_PFC_PIN_GROUP(hscif2_ctrl),
++	SH_PFC_PIN_GROUP(hscif3_data),
++	SH_PFC_PIN_GROUP(hscif3_clk),
++	SH_PFC_PIN_GROUP(hscif3_ctrl),
++	SH_PFC_PIN_GROUP(i2c0),
++	SH_PFC_PIN_GROUP(i2c1),
++	SH_PFC_PIN_GROUP(i2c2),
++	SH_PFC_PIN_GROUP(i2c3_a),
++	SH_PFC_PIN_GROUP(i2c3_b),
++	SH_PFC_PIN_GROUP(i2c4),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
++	SH_PFC_PIN_GROUP(mmc_data1),
++	SH_PFC_PIN_GROUP(mmc_data4),
++	SH_PFC_PIN_GROUP(mmc_data8),
++	SH_PFC_PIN_GROUP(mmc_ctrl),
++	SH_PFC_PIN_GROUP(mmc_cd),
++	SH_PFC_PIN_GROUP(mmc_wp),
++	SH_PFC_PIN_GROUP(msiof0_clk),
++	SH_PFC_PIN_GROUP(msiof0_sync),
++	SH_PFC_PIN_GROUP(msiof0_ss1),
++	SH_PFC_PIN_GROUP(msiof0_ss2),
++	SH_PFC_PIN_GROUP(msiof0_txd),
++	SH_PFC_PIN_GROUP(msiof0_rxd),
++	SH_PFC_PIN_GROUP(msiof1_clk),
++	SH_PFC_PIN_GROUP(msiof1_sync),
++	SH_PFC_PIN_GROUP(msiof1_ss1),
++	SH_PFC_PIN_GROUP(msiof1_ss2),
++	SH_PFC_PIN_GROUP(msiof1_txd),
++	SH_PFC_PIN_GROUP(msiof1_rxd),
++	SH_PFC_PIN_GROUP(msiof2_clk),
++	SH_PFC_PIN_GROUP(msiof2_sync),
++	SH_PFC_PIN_GROUP(msiof2_ss1),
++	SH_PFC_PIN_GROUP(msiof2_ss2),
++	SH_PFC_PIN_GROUP(msiof2_txd),
++	SH_PFC_PIN_GROUP(msiof2_rxd),
++	SH_PFC_PIN_GROUP(msiof3_clk),
++	SH_PFC_PIN_GROUP(msiof3_sync),
++	SH_PFC_PIN_GROUP(msiof3_ss1),
++	SH_PFC_PIN_GROUP(msiof3_ss2),
++	SH_PFC_PIN_GROUP(msiof3_txd),
++	SH_PFC_PIN_GROUP(msiof3_rxd),
++	SH_PFC_PIN_GROUP(pwm0_a),
++	SH_PFC_PIN_GROUP(pwm0_b),
++	SH_PFC_PIN_GROUP(pwm1_a),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm2_a),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm3_a),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm4_a),
++	SH_PFC_PIN_GROUP(pwm4_b),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(scif0_data),
++	SH_PFC_PIN_GROUP(scif0_clk),
++	SH_PFC_PIN_GROUP(scif0_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_a),
++	SH_PFC_PIN_GROUP(scif1_clk),
++	SH_PFC_PIN_GROUP(scif1_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_b),
++	SH_PFC_PIN_GROUP(scif3_data),
++	SH_PFC_PIN_GROUP(scif3_clk),
++	SH_PFC_PIN_GROUP(scif3_ctrl),
++	SH_PFC_PIN_GROUP(scif4_data),
++	SH_PFC_PIN_GROUP(scif4_clk),
++	SH_PFC_PIN_GROUP(scif4_ctrl),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
++	SH_PFC_PIN_GROUP(vin0_data8),
++	SH_PFC_PIN_GROUP(vin0_data10),
++	SH_PFC_PIN_GROUP(vin0_data12),
++	SH_PFC_PIN_GROUP(vin0_sync),
++	SH_PFC_PIN_GROUP(vin0_field),
++	SH_PFC_PIN_GROUP(vin0_clkenb),
++	SH_PFC_PIN_GROUP(vin0_clk),
++	SH_PFC_PIN_GROUP(vin1_data8),
++	SH_PFC_PIN_GROUP(vin1_data10),
++	SH_PFC_PIN_GROUP(vin1_data12),
++	SH_PFC_PIN_GROUP(vin1_sync),
++	SH_PFC_PIN_GROUP(vin1_field),
++	SH_PFC_PIN_GROUP(vin1_clkenb),
++	SH_PFC_PIN_GROUP(vin1_clk),
++};
++
++static const char * const canfd_clk_groups[] = {
++	"canfd_clk_a",
++	"canfd_clk_b",
++};
++
++static const char * const canfd0_groups[] = {
++	"canfd0_data_a",
++	"canfd0_data_b",
++};
++
++static const char * const canfd1_groups[] = {
++	"canfd1_data",
++};
++
++static const char * const du_groups[] = {
++	"du_rgb666",
++	"du_clk_out",
++	"du_sync",
++	"du_oddf",
++	"du_cde",
++	"du_disp",
++};
++
++static const char * const hscif0_groups[] = {
++	"hscif0_data",
++	"hscif0_clk",
++	"hscif0_ctrl",
++};
++
++static const char * const hscif1_groups[] = {
++	"hscif1_data",
++	"hscif1_clk",
++	"hscif1_ctrl",
++};
++
++static const char * const hscif2_groups[] = {
++	"hscif2_data",
++	"hscif2_clk",
++	"hscif2_ctrl",
++};
++
++static const char * const hscif3_groups[] = {
++	"hscif3_data",
++	"hscif3_clk",
++	"hscif3_ctrl",
++};
++
++static const char * const i2c0_groups[] = {
++	"i2c0",
++};
++
++static const char * const i2c1_groups[] = {
++	"i2c1",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2",
++};
++
++static const char * const i2c3_groups[] = {
++	"i2c3_a",
++	"i2c3_b",
++};
++
++static const char * const i2c4_groups[] = {
++	"i2c4",
++};
++
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
++static const char * const mmc_groups[] = {
++	"mmc_data1",
++	"mmc_data4",
++	"mmc_data8",
++	"mmc_ctrl",
++	"mmc_cd",
++	"mmc_wp",
++};
++
++static const char * const msiof0_groups[] = {
++	"msiof0_clk",
++	"msiof0_sync",
++	"msiof0_ss1",
++	"msiof0_ss2",
++	"msiof0_txd",
++	"msiof0_rxd",
++};
++
++static const char * const msiof1_groups[] = {
++	"msiof1_clk",
++	"msiof1_sync",
++	"msiof1_ss1",
++	"msiof1_ss2",
++	"msiof1_txd",
++	"msiof1_rxd",
++};
++
++static const char * const msiof2_groups[] = {
++	"msiof2_clk",
++	"msiof2_sync",
++	"msiof2_ss1",
++	"msiof2_ss2",
++	"msiof2_txd",
++	"msiof2_rxd",
++};
++
++static const char * const msiof3_groups[] = {
++	"msiof3_clk",
++	"msiof3_sync",
++	"msiof3_ss1",
++	"msiof3_ss2",
++	"msiof3_txd",
++	"msiof3_rxd",
++};
++
++static const char * const pwm0_groups[] = {
++	"pwm0_a",
++	"pwm0_b",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1_a",
++	"pwm1_b",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2_a",
++	"pwm2_b",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3_a",
++	"pwm3_b",
++};
++
++static const char * const pwm4_groups[] = {
++	"pwm4_a",
++	"pwm4_b",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data",
++	"scif0_clk",
++	"scif0_ctrl",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data_a",
++	"scif1_clk",
++	"scif1_ctrl",
++	"scif1_data_b",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data",
++	"scif3_clk",
++	"scif3_ctrl",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data",
++	"scif4_clk",
++	"scif4_ctrl",
++};
++
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
++static const char * const vin0_groups[] = {
++	"vin0_data8",
++	"vin0_data10",
++	"vin0_data12",
++	"vin0_sync",
++	"vin0_field",
++	"vin0_clkenb",
++	"vin0_clk",
++};
++
++static const char * const vin1_groups[] = {
++	"vin1_data8",
++	"vin1_data10",
++	"vin1_data12",
++	"vin1_sync",
++	"vin1_field",
++	"vin1_clkenb",
++	"vin1_clk",
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(canfd_clk),
++	SH_PFC_FUNCTION(canfd0),
++	SH_PFC_FUNCTION(canfd1),
++	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hscif0),
++	SH_PFC_FUNCTION(hscif1),
++	SH_PFC_FUNCTION(hscif2),
++	SH_PFC_FUNCTION(hscif3),
++	SH_PFC_FUNCTION(i2c0),
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c3),
++	SH_PFC_FUNCTION(i2c4),
++	SH_PFC_FUNCTION(intc_ex),
++	SH_PFC_FUNCTION(mmc),
++	SH_PFC_FUNCTION(msiof0),
++	SH_PFC_FUNCTION(msiof1),
++	SH_PFC_FUNCTION(msiof2),
++	SH_PFC_FUNCTION(msiof3),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
++	SH_PFC_FUNCTION(pwm4),
++	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(tmu),
++	SH_PFC_FUNCTION(vin0),
++	SH_PFC_FUNCTION(vin1),
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++#define F_(x, y)	FN_##y
++#define FM(x)		FN_##x
++	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_21_FN,	GPSR0_21,
++		GP_0_20_FN,	GPSR0_20,
++		GP_0_19_FN,	GPSR0_19,
++		GP_0_18_FN,	GPSR0_18,
++		GP_0_17_FN,	GPSR0_17,
++		GP_0_16_FN,	GPSR0_16,
++		GP_0_15_FN,	GPSR0_15,
++		GP_0_14_FN,	GPSR0_14,
++		GP_0_13_FN,	GPSR0_13,
++		GP_0_12_FN,	GPSR0_12,
++		GP_0_11_FN,	GPSR0_11,
++		GP_0_10_FN,	GPSR0_10,
++		GP_0_9_FN,	GPSR0_9,
++		GP_0_8_FN,	GPSR0_8,
++		GP_0_7_FN,	GPSR0_7,
++		GP_0_6_FN,	GPSR0_6,
++		GP_0_5_FN,	GPSR0_5,
++		GP_0_4_FN,	GPSR0_4,
++		GP_0_3_FN,	GPSR0_3,
++		GP_0_2_FN,	GPSR0_2,
++		GP_0_1_FN,	GPSR0_1,
++		GP_0_0_FN,	GPSR0_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_27_FN,	GPSR1_27,
++		GP_1_26_FN,	GPSR1_26,
++		GP_1_25_FN,	GPSR1_25,
++		GP_1_24_FN,	GPSR1_24,
++		GP_1_23_FN,	GPSR1_23,
++		GP_1_22_FN,	GPSR1_22,
++		GP_1_21_FN,	GPSR1_21,
++		GP_1_20_FN,	GPSR1_20,
++		GP_1_19_FN,	GPSR1_19,
++		GP_1_18_FN,	GPSR1_18,
++		GP_1_17_FN,	GPSR1_17,
++		GP_1_16_FN,	GPSR1_16,
++		GP_1_15_FN,	GPSR1_15,
++		GP_1_14_FN,	GPSR1_14,
++		GP_1_13_FN,	GPSR1_13,
++		GP_1_12_FN,	GPSR1_12,
++		GP_1_11_FN,	GPSR1_11,
++		GP_1_10_FN,	GPSR1_10,
++		GP_1_9_FN,	GPSR1_9,
++		GP_1_8_FN,	GPSR1_8,
++		GP_1_7_FN,	GPSR1_7,
++		GP_1_6_FN,	GPSR1_6,
++		GP_1_5_FN,	GPSR1_5,
++		GP_1_4_FN,	GPSR1_4,
++		GP_1_3_FN,	GPSR1_3,
++		GP_1_2_FN,	GPSR1_2,
++		GP_1_1_FN,	GPSR1_1,
++		GP_1_0_FN,	GPSR1_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_2_16_FN,	GPSR2_16,
++		GP_2_15_FN,	GPSR2_15,
++		GP_2_14_FN,	GPSR2_14,
++		GP_2_13_FN,	GPSR2_13,
++		GP_2_12_FN,	GPSR2_12,
++		GP_2_11_FN,	GPSR2_11,
++		GP_2_10_FN,	GPSR2_10,
++		GP_2_9_FN,	GPSR2_9,
++		GP_2_8_FN,	GPSR2_8,
++		GP_2_7_FN,	GPSR2_7,
++		GP_2_6_FN,	GPSR2_6,
++		GP_2_5_FN,	GPSR2_5,
++		GP_2_4_FN,	GPSR2_4,
++		GP_2_3_FN,	GPSR2_3,
++		GP_2_2_FN,	GPSR2_2,
++		GP_2_1_FN,	GPSR2_1,
++		GP_2_0_FN,	GPSR2_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_FN,	GPSR3_16,
++		GP_3_15_FN,	GPSR3_15,
++		GP_3_14_FN,	GPSR3_14,
++		GP_3_13_FN,	GPSR3_13,
++		GP_3_12_FN,	GPSR3_12,
++		GP_3_11_FN,	GPSR3_11,
++		GP_3_10_FN,	GPSR3_10,
++		GP_3_9_FN,	GPSR3_9,
++		GP_3_8_FN,	GPSR3_8,
++		GP_3_7_FN,	GPSR3_7,
++		GP_3_6_FN,	GPSR3_6,
++		GP_3_5_FN,	GPSR3_5,
++		GP_3_4_FN,	GPSR3_4,
++		GP_3_3_FN,	GPSR3_3,
++		GP_3_2_FN,	GPSR3_2,
++		GP_3_1_FN,	GPSR3_1,
++		GP_3_0_FN,	GPSR3_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_5_FN,	GPSR4_5,
++		GP_4_4_FN,	GPSR4_4,
++		GP_4_3_FN,	GPSR4_3,
++		GP_4_2_FN,	GPSR4_2,
++		GP_4_1_FN,	GPSR4_1,
++		GP_4_0_FN,	GPSR4_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_14_FN,	GPSR5_14,
++		GP_5_13_FN,	GPSR5_13,
++		GP_5_12_FN,	GPSR5_12,
++		GP_5_11_FN,	GPSR5_11,
++		GP_5_10_FN,	GPSR5_10,
++		GP_5_9_FN,	GPSR5_9,
++		GP_5_8_FN,	GPSR5_8,
++		GP_5_7_FN,	GPSR5_7,
++		GP_5_6_FN,	GPSR5_6,
++		GP_5_5_FN,	GPSR5_5,
++		GP_5_4_FN,	GPSR5_4,
++		GP_5_3_FN,	GPSR5_3,
++		GP_5_2_FN,	GPSR5_2,
++		GP_5_1_FN,	GPSR5_1,
++		GP_5_0_FN,	GPSR5_0, }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
++		IP0_31_28
++		IP0_27_24
++		IP0_23_20
++		IP0_19_16
++		IP0_15_12
++		IP0_11_8
++		IP0_7_4
++		IP0_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
++		IP1_31_28
++		IP1_27_24
++		IP1_23_20
++		IP1_19_16
++		IP1_15_12
++		IP1_11_8
++		IP1_7_4
++		IP1_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
++		IP2_31_28
++		IP2_27_24
++		IP2_23_20
++		IP2_19_16
++		IP2_15_12
++		IP2_11_8
++		IP2_7_4
++		IP2_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
++		IP3_31_28
++		IP3_27_24
++		IP3_23_20
++		IP3_19_16
++		IP3_15_12
++		IP3_11_8
++		IP3_7_4
++		IP3_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
++		IP4_31_28
++		IP4_27_24
++		IP4_23_20
++		IP4_19_16
++		IP4_15_12
++		IP4_11_8
++		IP4_7_4
++		IP4_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
++		IP5_31_28
++		IP5_27_24
++		IP5_23_20
++		IP5_19_16
++		IP5_15_12
++		IP5_11_8
++		IP5_7_4
++		IP5_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
++		IP6_31_28
++		IP6_27_24
++		IP6_23_20
++		IP6_19_16
++		IP6_15_12
++		IP6_11_8
++		IP6_7_4
++		IP6_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
++		IP7_31_28
++		IP7_27_24
++		IP7_23_20
++		IP7_19_16
++		IP7_15_12
++		IP7_11_8
++		IP7_7_4
++		IP7_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
++			     4, 4, 4, 4,
++			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
++		/* RESERVED 31, 30, 29, 28 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 27, 26, 25, 24 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 23, 22, 21, 20 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 19, 18, 17, 16 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 15, 14, 13, 12 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		MOD_SEL0_11
++		MOD_SEL0_10
++		MOD_SEL0_9
++		MOD_SEL0_8
++		MOD_SEL0_7
++		MOD_SEL0_6
++		MOD_SEL0_5
++		MOD_SEL0_4
++		MOD_SEL0_3
++		MOD_SEL0_2
++		MOD_SEL0_1
++		MOD_SEL0_0 }
++	},
++	{ },
++};
++
++static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
++				   u32 *pocctrl)
++{
++	int bit = pin & 0x1f;
++
++	*pocctrl = 0xe6060380;
++	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
++		return bit;
++	if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
++		return bit + 22;
++
++	*pocctrl += 4;
++	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
++		return bit - 10;
++	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
++		return bit + 7;
++
++	return -EINVAL;
++}
++
++static const struct sh_pfc_soc_operations pinmux_ops = {
++	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
++};
++
++const struct sh_pfc_soc_info r8a77970_pinmux_info = {
++	.name = "r8a77970_pfc",
++	.ops = &pinmux_ops,
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index efe07bcca8d0..5747ab0472df 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
++extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+-- 
+2.19.0
+
diff --git a/patches/0489-pinctrl-sh-pfc-r8a7794-Add-can_clk-function.patch b/patches/0489-pinctrl-sh-pfc-r8a7794-Add-can_clk-function.patch
new file mode 100644
index 00000000000000..946f2efa922ca9
--- /dev/null
+++ b/patches/0489-pinctrl-sh-pfc-r8a7794-Add-can_clk-function.patch
@@ -0,0 +1,68 @@
+From 8a9a7859a706953e9d67f621111298f391e1bbf3 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 14 Nov 2017 15:41:16 +0000
+Subject: [PATCH 0489/1795] pinctrl: sh-pfc: r8a7794: Add can_clk function
+
+This patch adds can_clk function to r8a7745/r8a7794 which is cleaner,
+and allows for independent configuration.
+We keep the can_clk* pins definitions from within can0_groups and
+can1_groups for uniformity and backwards compatibility.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7c4a3906475cba91c51e10a79e681b4f9ec6ec14)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index e5b3d5fa4aa0..c557bc8da10d 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -3858,6 +3858,10 @@ static const char * const can0_groups[] = {
+ 	"can0_data_b",
+ 	"can0_data_c",
+ 	"can0_data_d",
++	/*
++	 * Retained for backwards compatibility, use can_clk_groups in new
++	 * designs.
++	 */
+ 	"can_clk",
+ 	"can_clk_b",
+ 	"can_clk_c",
+@@ -3869,6 +3873,21 @@ static const char * const can1_groups[] = {
+ 	"can1_data_b",
+ 	"can1_data_c",
+ 	"can1_data_d",
++	/*
++	 * Retained for backwards compatibility, use can_clk_groups in new
++	 * designs.
++	 */
++	"can_clk",
++	"can_clk_b",
++	"can_clk_c",
++	"can_clk_d",
++};
++
++/*
++ * can_clk_groups allows for independent configuration, use can_clk function
++ * in new designs.
++ */
++static const char * const can_clk_groups[] = {
+ 	"can_clk",
+ 	"can_clk_b",
+ 	"can_clk_c",
+@@ -4248,6 +4267,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(can0),
+ 	SH_PFC_FUNCTION(can1),
++	SH_PFC_FUNCTION(can_clk),
+ 	SH_PFC_FUNCTION(du0),
+ 	SH_PFC_FUNCTION(du1),
+ 	SH_PFC_FUNCTION(eth),
+-- 
+2.19.0
+
diff --git a/patches/0490-pinctrl-sh-pfc-r8a77995-Add-missing-pins-SCL0-and-SD.patch b/patches/0490-pinctrl-sh-pfc-r8a77995-Add-missing-pins-SCL0-and-SD.patch
new file mode 100644
index 00000000000000..3d270a9d1d3872
--- /dev/null
+++ b/patches/0490-pinctrl-sh-pfc-r8a77995-Add-missing-pins-SCL0-and-SD.patch
@@ -0,0 +1,33 @@
+From e2ee43525f2ee23bf71338f47976ec277949cfc5 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 15 Nov 2017 16:25:21 +0100
+Subject: [PATCH 0490/1795] pinctrl: sh-pfc: r8a77995: Add missing pins SCL0
+ and SDA0 to pinmux data
+
+Required for I2C0 operation.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit af4b609e6f7010094a8f14ff620588fad87e8553)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 89b7541ab1ed..2c9a71a59fc3 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -518,6 +518,8 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_SINGLE(QSPI0_MISO_IO1),
+ 	PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ 	PINMUX_SINGLE(QSPI0_SPCLK),
++	PINMUX_SINGLE(SCL0),
++	PINMUX_SINGLE(SDA0),
+ 
+ 	/* IPSR0 */
+ 	PINMUX_IPSR_MSEL(IP0_3_0,	IRQ0_A, SEL_IRQ_0_0),
+-- 
+2.19.0
+
diff --git a/patches/0491-pinctrl-sh-pfc-r8a7795-Add-GP-1-28-port-pin-support.patch b/patches/0491-pinctrl-sh-pfc-r8a7795-Add-GP-1-28-port-pin-support.patch
new file mode 100644
index 00000000000000..eddec43b71b402
--- /dev/null
+++ b/patches/0491-pinctrl-sh-pfc-r8a7795-Add-GP-1-28-port-pin-support.patch
@@ -0,0 +1,98 @@
+From 9f4836e8f2d125ca0a122499f3a14fbd09f587e9 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 12:14:51 +0900
+Subject: [PATCH 0491/1795] pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin
+ support
+
+This patch supports GP-1-28 port pin of R8A7795 ES2.0 SoC added in
+Rev.0.54E of the R-Car Gen3 Hardware User's Manual or later version.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+[geert: Update forgotten PUEN2 entry]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 82d2de5a4f646f7265ac5bc779f4a58164f2c0e9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 34a2dc471e5a..a1358a1e67b7 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -20,7 +20,7 @@
+ 
+ #define CPU_ALL_PORT(fn, sfx)						\
+ 	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
+-	PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
+ 	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
+ 	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
+ 	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
+@@ -55,6 +55,7 @@
+ #define GPSR0_0		F_(D0,			IP5_15_12)
+ 
+ /* GPSR1 */
++#define GPSR1_28	FM(CLKOUT)
+ #define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
+ #define GPSR1_26	F_(WE1_N,		IP5_7_4)
+ #define GPSR1_25	F_(WE0_N,		IP5_3_0)
+@@ -368,7 +369,7 @@
+ 												GPSR6_31 \
+ 												GPSR6_30 \
+ 												GPSR6_29 \
+-												GPSR6_28 \
++		GPSR1_28									GPSR6_28 \
+ 		GPSR1_27									GPSR6_27 \
+ 		GPSR1_26									GPSR6_26 \
+ 		GPSR1_25							GPSR5_25	GPSR6_25 \
+@@ -548,7 +549,7 @@ MOD_SEL0_4_3		MOD_SEL1_4 \
+ 	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
+ 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
+ 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
+-	FM(CLKOUT) FM(PRESETOUT) \
++	FM(PRESETOUT) \
+ 	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
+ 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
+ 
+@@ -587,6 +588,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_SINGLE(AVS1),
+ 	PINMUX_SINGLE(AVS2),
++	PINMUX_SINGLE(CLKOUT),
+ 	PINMUX_SINGLE(HDMI0_CEC),
+ 	PINMUX_SINGLE(HDMI1_CEC),
+ 	PINMUX_SINGLE(I2C_SEL_0_1),
+@@ -4733,7 +4735,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ 		0, 0,
+ 		0, 0,
+ 		0, 0,
+-		0, 0,
++		GP_1_28_FN,	GPSR1_28,
+ 		GP_1_27_FN,	GPSR1_27,
+ 		GP_1_26_FN,	GPSR1_26,
+ 		GP_1_25_FN,	GPSR1_25,
+@@ -5335,7 +5337,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
+ 	} },
+ 	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
+-		{ PIN_NUMBER('F', 1), 28, 3 },	/* CLKOUT */
++		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
+ 		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
+ 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
+ 		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
+@@ -5596,7 +5598,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ 		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
+ 	} },
+ 	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
+-		[ 0] = PIN_NUMBER('F', 1),	/* CLKOUT */
++		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
+ 		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
+ 		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
+ 		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
+-- 
+2.19.0
+
diff --git a/patches/0492-pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu.patch b/patches/0492-pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu.patch
new file mode 100644
index 00000000000000..978c511187b6fc
--- /dev/null
+++ b/patches/0492-pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu.patch
@@ -0,0 +1,91 @@
+From 729cd27d51f41d55faeaa4cbd85d3a480754df3e Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 12:16:48 +0900
+Subject: [PATCH 0492/1795] pinctrl: sh-pfc: r8a7795: Fix to delete A20..A25
+ pins function definitions
+
+This patch fixes the macro definitions of A20..A25 pins function deleted.
+
+This is a correction because IPSR register specification for R8A7795 ES2.0
+SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7716c51b5e96a289df954b1fe91faf711fb51da9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index a1358a1e67b7..a97256cd25df 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -219,12 +219,12 @@
+ #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	FM(A25)			FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	FM(A24)			FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	FM(A23)			FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)FM(A22)			F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	FM(A21)			FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	FM(A20)			FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -652,7 +652,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
+-	PINMUX_IPSR_GPSR(IP1_7_4,	A25),
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
+ 	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
+@@ -660,7 +659,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
+-	PINMUX_IPSR_GPSR(IP1_11_8,	A24),
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
+ 	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
+@@ -668,7 +666,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
+-	PINMUX_IPSR_GPSR(IP1_15_12,	A23),
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
+ 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
+@@ -677,18 +674,15 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
+ 	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
+-	PINMUX_IPSR_GPSR(IP1_19_16,	A22),
+ 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
+ 
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	PWM1_A,			SEL_PWM1_0),
+-	PINMUX_IPSR_GPSR(IP1_23_20,	A21),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	HRX3_D,			SEL_HSCIF3_3),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	VI4_DATA7_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	IERX_B,			SEL_IEBUS_1),
+ 
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	PWM2_A,			SEL_PWM2_0),
+-	PINMUX_IPSR_GPSR(IP1_27_24,	A20),
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	HTX3_D,			SEL_HSCIF3_3),
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	IETX_B,			SEL_IEBUS_1),
+ 
+-- 
+2.19.0
+
diff --git a/patches/0493-pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu.patch b/patches/0493-pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu.patch
new file mode 100644
index 00000000000000..da63285a6601ca
--- /dev/null
+++ b/patches/0493-pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu.patch
@@ -0,0 +1,91 @@
+From f0af9da8957627f57c213fd0e3e9afe923fbab42 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 12:17:18 +0900
+Subject: [PATCH 0493/1795] pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25
+ pins function definitions
+
+This patch fixes the macro definitions of A20..A25 pins function deleted.
+
+This is a correction because IPSR register specification for R8A7796 SoC
+was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit fbd81e345c9393b96e8ad252eef390f8c6f9cf60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index d8dc984cde6d..5df98f99970c 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -224,12 +224,12 @@
+ #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	FM(A25)			FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	FM(A24)			FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	FM(A23)			FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)FM(A22)			F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	FM(A21)			FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	FM(A20)			FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -654,7 +654,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
+-	PINMUX_IPSR_GPSR(IP1_7_4,	A25),
+ 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
+ 	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
+@@ -662,7 +661,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
+-	PINMUX_IPSR_GPSR(IP1_11_8,	A24),
+ 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
+ 	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
+@@ -670,7 +668,6 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
+-	PINMUX_IPSR_GPSR(IP1_15_12,	A23),
+ 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
+ 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
+@@ -678,18 +675,15 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
+ 	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
+-	PINMUX_IPSR_GPSR(IP1_19_16,	A22),
+ 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
+ 
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	PWM1_A,			SEL_PWM1_0),
+-	PINMUX_IPSR_GPSR(IP1_23_20,	A21),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	HRX3_D,			SEL_HSCIF3_3),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	VI4_DATA7_B,		SEL_VIN4_1),
+ 	PINMUX_IPSR_MSEL(IP1_23_20,	IERX_B,			SEL_IEBUS_1),
+ 
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	PWM2_A,			SEL_PWM2_0),
+-	PINMUX_IPSR_GPSR(IP1_27_24,	A20),
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	HTX3_D,			SEL_HSCIF3_3),
+ 	PINMUX_IPSR_MSEL(IP1_27_24,	IETX_B,			SEL_IEBUS_1),
+ 
+-- 
+2.19.0
+
diff --git a/patches/0494-pinctrl-sh-pfc-r8a7795-Rename-RTS-0-1-3-4-pin-functi.patch b/patches/0494-pinctrl-sh-pfc-r8a7795-Rename-RTS-0-1-3-4-pin-functi.patch
new file mode 100644
index 00000000000000..fbcda3bb5cf328
--- /dev/null
+++ b/patches/0494-pinctrl-sh-pfc-r8a7795-Rename-RTS-0-1-3-4-pin-functi.patch
@@ -0,0 +1,232 @@
+From 57c13d5b21fb98f12602fdf6c69613f3778c4230 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 23:58:40 +0900
+Subject: [PATCH 0494/1795] pinctrl: sh-pfc: r8a7795: Rename RTS{0,1,3,4}# pin
+ function definitions
+
+This patch renames the pin function macro definitions of the GPSR and
+IPSR registers value for the RTS{0,1,3,4}# pin.
+
+This is a correction because GPSR and IPSR register specification for
+R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual
+Rev.0.54E.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+[geert: Drop remaining "_TANS" from comments]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 8714a9c1bdd388aa6cff6cd01e357c349300158e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 48 ++++++++++++++--------------
+ 1 file changed, 24 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index a97256cd25df..7eddd0f2f847 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -158,11 +158,11 @@
+ #define GPSR5_11	F_(RX2_A,		IP13_7_4)
+ #define GPSR5_10	F_(TX2_A,		IP13_3_0)
+ #define GPSR5_9		F_(SCK2,		IP12_31_28)
+-#define GPSR5_8		F_(RTS1_N_TANS,		IP12_27_24)
++#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
+ #define GPSR5_7		F_(CTS1_N,		IP12_23_20)
+ #define GPSR5_6		F_(TX1_A,		IP12_19_16)
+ #define GPSR5_5		F_(RX1_A,		IP12_15_12)
+-#define GPSR5_4		F_(RTS0_N_TANS,		IP12_11_8)
++#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
+ #define GPSR5_3		F_(CTS0_N,		IP12_7_4)
+ #define GPSR5_2		F_(TX0,			IP12_3_0)
+ #define GPSR5_1		F_(RX0,			IP11_31_28)
+@@ -215,7 +215,7 @@
+ #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_TANS_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -237,7 +237,7 @@
+ #define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_TANS_B)		F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -253,7 +253,7 @@
+ #define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N_TANS)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -266,7 +266,7 @@
+ #define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_TANS_C)FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -313,11 +313,11 @@
+ #define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP12_11_8	FM(RTS0_N_TANS)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP12_27_24	FM(RTS1_N_TANS)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -624,7 +624,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	SEL_ETHERAVB_0),
+ 	PINMUX_IPSR_MSEL(IP0_23_20,	MSIOF2_TXD_C,		SEL_MSIOF2_2),
+-	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_TANS_A,		SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_A,		SEL_SCIF4_0),
+ 
+ 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
+ 	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
+@@ -762,7 +762,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
+ 	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
+-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_TANS_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
+ 	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
+ 
+ 	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
+@@ -865,7 +865,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
+ 	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
+-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N_TANS),
++	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
+ 	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
+@@ -946,7 +946,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
+-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_TANS_C,		SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
+ 	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
+ 
+ 	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
+@@ -1155,7 +1155,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
+ 	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
+ 
+-	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N_TANS),
++	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADG_A_1),
+@@ -1184,7 +1184,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
+ 	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
+ 
+-	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N_TANS),
++	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
+@@ -3247,7 +3247,7 @@ static const unsigned int scif0_ctrl_pins[] = {
+ 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+ };
+ static const unsigned int scif0_ctrl_mux[] = {
+-	RTS0_N_TANS_MARK, CTS0_N_MARK,
++	RTS0_N_MARK, CTS0_N_MARK,
+ };
+ /* - SCIF1 ------------------------------------------------------------------ */
+ static const unsigned int scif1_data_a_pins[] = {
+@@ -3269,7 +3269,7 @@ static const unsigned int scif1_ctrl_pins[] = {
+ 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
+ };
+ static const unsigned int scif1_ctrl_mux[] = {
+-	RTS1_N_TANS_MARK, CTS1_N_MARK,
++	RTS1_N_MARK, CTS1_N_MARK,
+ };
+ 
+ static const unsigned int scif1_data_b_pins[] = {
+@@ -3321,7 +3321,7 @@ static const unsigned int scif3_ctrl_pins[] = {
+ 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+ };
+ static const unsigned int scif3_ctrl_mux[] = {
+-	RTS3_N_TANS_MARK, CTS3_N_MARK,
++	RTS3_N_MARK, CTS3_N_MARK,
+ };
+ static const unsigned int scif3_data_b_pins[] = {
+ 	/* RX, TX */
+@@ -3350,7 +3350,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
+ 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+ };
+ static const unsigned int scif4_ctrl_a_mux[] = {
+-	RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
++	RTS4_N_A_MARK, CTS4_N_A_MARK,
+ };
+ static const unsigned int scif4_data_b_pins[] = {
+ 	/* RX, TX */
+@@ -3371,7 +3371,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
+ 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+ };
+ static const unsigned int scif4_ctrl_b_mux[] = {
+-	RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
++	RTS4_N_B_MARK, CTS4_N_B_MARK,
+ };
+ static const unsigned int scif4_data_c_pins[] = {
+ 	/* RX, TX */
+@@ -3392,7 +3392,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
+ 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ };
+ static const unsigned int scif4_ctrl_c_mux[] = {
+-	RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
++	RTS4_N_C_MARK, CTS4_N_C_MARK,
+ };
+ /* - SCIF5 ------------------------------------------------------------------ */
+ static const unsigned int scif5_data_a_pins[] = {
+@@ -5427,11 +5427,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
+ 	} },
+ 	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
+-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0_TANS */
++		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
+ 		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
+ 		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
+ 		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
+-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1_TANS */
++		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
+ 		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
+ 		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
+ 		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
+@@ -5676,11 +5676,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ 		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
+ 		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
+ 		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
+-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N_TANS */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
+ 		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
+ 		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
+ 		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
+-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N_TANS */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
+ 		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
+ 		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
+ 		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
+-- 
+2.19.0
+
diff --git a/patches/0495-pinctrl-sh-pfc-r8a7796-Rename-RTS-0-1-3-4-pin-functi.patch b/patches/0495-pinctrl-sh-pfc-r8a7796-Rename-RTS-0-1-3-4-pin-functi.patch
new file mode 100644
index 00000000000000..7c547cdd04af5c
--- /dev/null
+++ b/patches/0495-pinctrl-sh-pfc-r8a7796-Rename-RTS-0-1-3-4-pin-functi.patch
@@ -0,0 +1,229 @@
+From cc26998575a18e71df4b8c168783c70c8710839e Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 23:59:21 +0900
+Subject: [PATCH 0495/1795] pinctrl: sh-pfc: r8a7796: Rename RTS{0,1,3,4}# pin
+ function definitions
+
+This patch renames the pin function macro definitions of the GPSR5 and
+IPSR{0,3,5,6,12} registers value for the RTS{0,1,3,4}# pin.
+
+This is a correction because GPSR and IPSR register specification for
+R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0f4713d71f22d3b0ec3de6ae4a126cceecdea82b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 48 ++++++++++++++--------------
+ 1 file changed, 24 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 5df98f99970c..74ee48303156 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -163,11 +163,11 @@
+ #define GPSR5_11	F_(RX2_A,		IP13_7_4)
+ #define GPSR5_10	F_(TX2_A,		IP13_3_0)
+ #define GPSR5_9		F_(SCK2,		IP12_31_28)
+-#define GPSR5_8		F_(RTS1_N_TANS,		IP12_27_24)
++#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
+ #define GPSR5_7		F_(CTS1_N,		IP12_23_20)
+ #define GPSR5_6		F_(TX1_A,		IP12_19_16)
+ #define GPSR5_5		F_(RX1_A,		IP12_15_12)
+-#define GPSR5_4		F_(RTS0_N_TANS,		IP12_11_8)
++#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
+ #define GPSR5_3		F_(CTS0_N,		IP12_7_4)
+ #define GPSR5_2		F_(TX0,			IP12_3_0)
+ #define GPSR5_1		F_(RX0,			IP11_31_28)
+@@ -220,7 +220,7 @@
+ #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_TANS_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -240,7 +240,7 @@
+ #define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_TANS_B)		F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ 
+ /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
+@@ -258,7 +258,7 @@
+ #define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N_TANS)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -271,7 +271,7 @@
+ #define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_TANS_C)FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ 
+ /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
+@@ -318,11 +318,11 @@
+ #define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP12_11_8	FM(RTS0_N_TANS)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP12_27_24	FM(RTS1_N_TANS)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -626,7 +626,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	SEL_ETHERAVB_0),
+ 	PINMUX_IPSR_MSEL(IP0_23_20,	MSIOF2_TXD_C,		SEL_MSIOF2_2),
+-	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_TANS_A,		SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_A,		SEL_SCIF4_0),
+ 
+ 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
+ 	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
+@@ -763,7 +763,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
+ 	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
+-	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_TANS_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
+ 	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
+ 
+ 	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
+@@ -866,7 +866,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
+ 	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
+-	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N_TANS),
++	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
+ 	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
+ 	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
+@@ -947,7 +947,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
+ 	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
+-	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_TANS_C,		SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
+ 	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
+ 
+ 	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
+@@ -1155,7 +1155,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
+ 	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
+ 
+-	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N_TANS),
++	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADG_A_1),
+@@ -1184,7 +1184,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
+ 	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
+ 
+-	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N_TANS),
++	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
+ 	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
+@@ -3249,7 +3249,7 @@ static const unsigned int scif0_ctrl_pins[] = {
+ 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+ };
+ static const unsigned int scif0_ctrl_mux[] = {
+-	RTS0_N_TANS_MARK, CTS0_N_MARK,
++	RTS0_N_MARK, CTS0_N_MARK,
+ };
+ /* - SCIF1 ------------------------------------------------------------------ */
+ static const unsigned int scif1_data_a_pins[] = {
+@@ -3271,7 +3271,7 @@ static const unsigned int scif1_ctrl_pins[] = {
+ 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
+ };
+ static const unsigned int scif1_ctrl_mux[] = {
+-	RTS1_N_TANS_MARK, CTS1_N_MARK,
++	RTS1_N_MARK, CTS1_N_MARK,
+ };
+ 
+ static const unsigned int scif1_data_b_pins[] = {
+@@ -3323,7 +3323,7 @@ static const unsigned int scif3_ctrl_pins[] = {
+ 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+ };
+ static const unsigned int scif3_ctrl_mux[] = {
+-	RTS3_N_TANS_MARK, CTS3_N_MARK,
++	RTS3_N_MARK, CTS3_N_MARK,
+ };
+ static const unsigned int scif3_data_b_pins[] = {
+ 	/* RX, TX */
+@@ -3352,7 +3352,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
+ 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+ };
+ static const unsigned int scif4_ctrl_a_mux[] = {
+-	RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
++	RTS4_N_A_MARK, CTS4_N_A_MARK,
+ };
+ static const unsigned int scif4_data_b_pins[] = {
+ 	/* RX, TX */
+@@ -3373,7 +3373,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
+ 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+ };
+ static const unsigned int scif4_ctrl_b_mux[] = {
+-	RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
++	RTS4_N_B_MARK, CTS4_N_B_MARK,
+ };
+ static const unsigned int scif4_data_c_pins[] = {
+ 	/* RX, TX */
+@@ -3394,7 +3394,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
+ 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ };
+ static const unsigned int scif4_ctrl_c_mux[] = {
+-	RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
++	RTS4_N_C_MARK, CTS4_N_C_MARK,
+ };
+ /* - SCIF5 ------------------------------------------------------------------ */
+ static const unsigned int scif5_data_a_pins[] = {
+@@ -5400,11 +5400,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+ 		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
+ 	} },
+ 	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
+-		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0_TANS */
++		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
+ 		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
+ 		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
+ 		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
+-		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1_TANS */
++		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
+ 		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
+ 		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
+ 		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
+@@ -5649,11 +5649,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ 		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
+ 		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
+ 		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
+-		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N_TANS */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
+ 		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
+ 		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
+ 		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
+-		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N_TANS */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
+ 		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
+ 		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
+ 		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
+-- 
+2.19.0
+
diff --git a/patches/0496-pinctrl-sh-pfc-r8a77995-Add-CAN-support.patch b/patches/0496-pinctrl-sh-pfc-r8a77995-Add-CAN-support.patch
new file mode 100644
index 00000000000000..a8e5390517f76f
--- /dev/null
+++ b/patches/0496-pinctrl-sh-pfc-r8a77995-Add-CAN-support.patch
@@ -0,0 +1,110 @@
+From 723728ce0762b394f5b5599d9b6d95a350287f54 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 17 Nov 2017 11:41:23 +0100
+Subject: [PATCH 0496/1795] pinctrl: sh-pfc: r8a77995: Add CAN support
+
+This patch adds CAN[0-1] pinmux support to the r8a77995 SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c45985d359c40899ef05e44bb24a63241afaec10)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 59 +++++++++++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 2c9a71a59fc3..c4ea718e172e 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1059,6 +1059,45 @@ static const unsigned int avb0_avtp_capture_b_mux[] = {
+ 	AVB0_AVTP_CAPTURE_B_MARK,
+ };
+ 
++/* - CAN ------------------------------------------------------------------ */
++static const unsigned int can0_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
++};
++static const unsigned int can0_data_a_mux[] = {
++	CAN0_TX_A_MARK, CAN0_RX_A_MARK,
++};
++static const unsigned int can0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int can0_data_b_mux[] = {
++	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
++};
++static const unsigned int can1_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
++};
++static const unsigned int can1_data_a_mux[] = {
++	CAN1_TX_A_MARK, CAN1_RX_A_MARK,
++};
++static const unsigned int can1_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
++};
++static const unsigned int can1_data_b_mux[] = {
++	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
++};
++
++/* - CAN Clock -------------------------------------------------------------- */
++static const unsigned int can_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(5, 2),
++};
++static const unsigned int can_clk_mux[] = {
++	CAN_CLK_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c0_pins[] = {
+ 	/* SCL, SDA */
+@@ -1506,6 +1545,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
+ 	SH_PFC_PIN_GROUP(avb0_avtp_match_b),
+ 	SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
++	SH_PFC_PIN_GROUP(can0_data_a),
++	SH_PFC_PIN_GROUP(can0_data_b),
++	SH_PFC_PIN_GROUP(can1_data_a),
++	SH_PFC_PIN_GROUP(can1_data_b),
++	SH_PFC_PIN_GROUP(can_clk),
+ 	SH_PFC_PIN_GROUP(i2c0),
+ 	SH_PFC_PIN_GROUP(i2c1),
+ 	SH_PFC_PIN_GROUP(i2c2_a),
+@@ -1583,6 +1627,18 @@ static const char * const avb0_groups[] = {
+ 	"avb0_avtp_capture_b",
+ };
+ 
++static const char * const can0_groups[] = {
++	"can0_data_a",
++	"can0_data_b",
++};
++static const char * const can1_groups[] = {
++	"can1_data_a",
++	"can1_data_b",
++};
++static const char * const can_clk_groups[] = {
++	"can_clk",
++};
++
+ static const char * const i2c0_groups[] = {
+ 	"i2c0",
+ };
+@@ -1693,6 +1749,9 @@ static const char * const usb0_groups[] = {
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb0),
++	SH_PFC_FUNCTION(can0),
++	SH_PFC_FUNCTION(can1),
++	SH_PFC_FUNCTION(can_clk),
+ 	SH_PFC_FUNCTION(i2c0),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+-- 
+2.19.0
+
diff --git a/patches/0497-pinctrl-sh-pfc-r8a77995-Add-CAN-FD-support.patch b/patches/0497-pinctrl-sh-pfc-r8a77995-Add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..d6043ceecf90b6
--- /dev/null
+++ b/patches/0497-pinctrl-sh-pfc-r8a77995-Add-CAN-FD-support.patch
@@ -0,0 +1,78 @@
+From add219aa23388e66f0bc7f0c76923764165f7877 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 17 Nov 2017 11:41:24 +0100
+Subject: [PATCH 0497/1795] pinctrl: sh-pfc: r8a77995: Add CAN FD support
+
+This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 527890f72892b127b67567af6bdbdc5288c211c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index c4ea718e172e..a4927b78a17b 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1098,6 +1098,22 @@ static const unsigned int can_clk_mux[] = {
+ 	CAN_CLK_MARK,
+ };
+ 
++/* - CAN FD ----------------------------------------------------------------- */
++static const unsigned int canfd0_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
++};
++static const unsigned int canfd0_data_mux[] = {
++	CANFD0_TX_MARK, CANFD0_RX_MARK,
++};
++static const unsigned int canfd1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
++};
++static const unsigned int canfd1_data_mux[] = {
++	CANFD1_TX_MARK, CANFD1_RX_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c0_pins[] = {
+ 	/* SCL, SDA */
+@@ -1550,6 +1566,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(can1_data_a),
+ 	SH_PFC_PIN_GROUP(can1_data_b),
+ 	SH_PFC_PIN_GROUP(can_clk),
++	SH_PFC_PIN_GROUP(canfd0_data),
++	SH_PFC_PIN_GROUP(canfd1_data),
+ 	SH_PFC_PIN_GROUP(i2c0),
+ 	SH_PFC_PIN_GROUP(i2c1),
+ 	SH_PFC_PIN_GROUP(i2c2_a),
+@@ -1639,6 +1657,13 @@ static const char * const can_clk_groups[] = {
+ 	"can_clk",
+ };
+ 
++static const char * const canfd0_groups[] = {
++	"canfd0_data",
++};
++static const char * const canfd1_groups[] = {
++	"canfd1_data",
++};
++
+ static const char * const i2c0_groups[] = {
+ 	"i2c0",
+ };
+@@ -1752,6 +1777,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(can0),
+ 	SH_PFC_FUNCTION(can1),
+ 	SH_PFC_FUNCTION(can_clk),
++	SH_PFC_FUNCTION(canfd0),
++	SH_PFC_FUNCTION(canfd1),
+ 	SH_PFC_FUNCTION(i2c0),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+-- 
+2.19.0
+
diff --git a/patches/0498-pinctrl-sh-pfc-r8a7794-Add-PWM-0123456-support.patch b/patches/0498-pinctrl-sh-pfc-r8a7794-Add-PWM-0123456-support.patch
new file mode 100644
index 00000000000000..074da1e378d98e
--- /dev/null
+++ b/patches/0498-pinctrl-sh-pfc-r8a7794-Add-PWM-0123456-support.patch
@@ -0,0 +1,218 @@
+From 439a78a7080c6a3e1fb33cf0838ae2c0c3e89924 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 14 Dec 2017 10:57:03 +0000
+Subject: [PATCH 0498/1795] pinctrl: sh-pfc: r8a7794: Add PWM[0123456] support
+
+This patch adds PFC PWM[0123456] pin groups and functions, enabling
+PWM on the r8a7794 and r8a7745.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 20796a2caf011b9a94763e26b89be7a13a2756f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 165 +++++++++++++++++++++++++++
+ 1 file changed, 165 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index c557bc8da10d..dccc20ae1130 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -2546,6 +2546,109 @@ static const unsigned int msiof2_tx_b_pins[] = {
+ static const unsigned int msiof2_tx_b_mux[] = {
+ 	MSIOF2_TXD_B_MARK,
+ };
++/* - PWM -------------------------------------------------------------------- */
++static const unsigned int pwm0_pins[] = {
++	RCAR_GP_PIN(1, 14),
++};
++static const unsigned int pwm0_mux[] = {
++	PWM0_MARK,
++};
++static const unsigned int pwm0_b_pins[] = {
++	RCAR_GP_PIN(5, 3),
++};
++static const unsigned int pwm0_b_mux[] = {
++	PWM0_B_MARK,
++};
++static const unsigned int pwm1_pins[] = {
++	RCAR_GP_PIN(4, 5),
++};
++static const unsigned int pwm1_mux[] = {
++	PWM1_MARK,
++};
++static const unsigned int pwm1_b_pins[] = {
++	RCAR_GP_PIN(5, 10),
++};
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++static const unsigned int pwm1_c_pins[] = {
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int pwm1_c_mux[] = {
++	PWM1_C_MARK,
++};
++static const unsigned int pwm2_pins[] = {
++	RCAR_GP_PIN(4, 10),
++};
++static const unsigned int pwm2_mux[] = {
++	PWM2_MARK,
++};
++static const unsigned int pwm2_b_pins[] = {
++	RCAR_GP_PIN(5, 17),
++};
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++static const unsigned int pwm2_c_pins[] = {
++	RCAR_GP_PIN(0, 13),
++};
++static const unsigned int pwm2_c_mux[] = {
++	PWM2_C_MARK,
++};
++static const unsigned int pwm3_pins[] = {
++	RCAR_GP_PIN(4, 13),
++};
++static const unsigned int pwm3_mux[] = {
++	PWM3_MARK,
++};
++static const unsigned int pwm3_b_pins[] = {
++	RCAR_GP_PIN(0, 16),
++};
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++static const unsigned int pwm4_pins[] = {
++	RCAR_GP_PIN(1, 3),
++};
++static const unsigned int pwm4_mux[] = {
++	PWM4_MARK,
++};
++static const unsigned int pwm4_b_pins[] = {
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int pwm4_b_mux[] = {
++	PWM4_B_MARK,
++};
++static const unsigned int pwm5_pins[] = {
++	RCAR_GP_PIN(3, 30),
++};
++static const unsigned int pwm5_mux[] = {
++	PWM5_MARK,
++};
++static const unsigned int pwm5_b_pins[] = {
++	RCAR_GP_PIN(4, 0),
++};
++static const unsigned int pwm5_b_mux[] = {
++	PWM5_B_MARK,
++};
++static const unsigned int pwm5_c_pins[] = {
++	RCAR_GP_PIN(0, 10),
++};
++static const unsigned int pwm5_c_mux[] = {
++	PWM5_C_MARK,
++};
++static const unsigned int pwm6_pins[] = {
++	RCAR_GP_PIN(4, 8),
++};
++static const unsigned int pwm6_mux[] = {
++	PWM6_MARK,
++};
++static const unsigned int pwm6_b_pins[] = {
++	RCAR_GP_PIN(0, 7),
++};
++static const unsigned int pwm6_b_mux[] = {
++	PWM6_B_MARK,
++};
+ /* - QSPI ------------------------------------------------------------------- */
+ static const unsigned int qspi_ctrl_pins[] = {
+ 	/* SPCLK, SSL */
+@@ -3689,6 +3792,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ 	SH_PFC_PIN_GROUP(msiof2_rx_b),
+ 	SH_PFC_PIN_GROUP(msiof2_tx_b),
++	SH_PFC_PIN_GROUP(pwm0),
++	SH_PFC_PIN_GROUP(pwm0_b),
++	SH_PFC_PIN_GROUP(pwm1),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm1_c),
++	SH_PFC_PIN_GROUP(pwm2),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm2_c),
++	SH_PFC_PIN_GROUP(pwm3),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm4),
++	SH_PFC_PIN_GROUP(pwm4_b),
++	SH_PFC_PIN_GROUP(pwm5),
++	SH_PFC_PIN_GROUP(pwm5_b),
++	SH_PFC_PIN_GROUP(pwm5_c),
++	SH_PFC_PIN_GROUP(pwm6),
++	SH_PFC_PIN_GROUP(pwm6_b),
+ 	SH_PFC_PIN_GROUP(qspi_ctrl),
+ 	SH_PFC_PIN_GROUP(qspi_data2),
+ 	SH_PFC_PIN_GROUP(qspi_data4),
+@@ -4050,6 +4170,44 @@ static const char * const msiof2_groups[] = {
+ 	"msiof2_tx_b",
+ };
+ 
++static const char * const pwm0_groups[] = {
++	"pwm0",
++	"pwm0_b",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1",
++	"pwm1_b",
++	"pwm1_c",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2",
++	"pwm2_b",
++	"pwm2_c",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3",
++	"pwm3_b",
++};
++
++static const char * const pwm4_groups[] = {
++	"pwm4",
++	"pwm4_b",
++};
++
++static const char * const pwm5_groups[] = {
++	"pwm5",
++	"pwm5_b",
++	"pwm5_c",
++};
++
++static const char * const pwm6_groups[] = {
++	"pwm6",
++	"pwm6_b",
++};
++
+ static const char * const qspi_groups[] = {
+ 	"qspi_ctrl",
+ 	"qspi_data2",
+@@ -4284,6 +4442,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+ 	SH_PFC_FUNCTION(msiof2),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
++	SH_PFC_FUNCTION(pwm4),
++	SH_PFC_FUNCTION(pwm5),
++	SH_PFC_FUNCTION(pwm6),
+ 	SH_PFC_FUNCTION(qspi),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+-- 
+2.19.0
+
diff --git a/patches/0499-pinctrl-sh-pfc-r8a7794-Add-tpu-groups-and-function.patch b/patches/0499-pinctrl-sh-pfc-r8a7794-Add-tpu-groups-and-function.patch
new file mode 100644
index 00000000000000..524781eca83063
--- /dev/null
+++ b/patches/0499-pinctrl-sh-pfc-r8a7794-Add-tpu-groups-and-function.patch
@@ -0,0 +1,154 @@
+From e702e00569017a56d339f751d311c94d6d432204 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:06:50 +0000
+Subject: [PATCH 0499/1795] pinctrl: sh-pfc: r8a7794: Add tpu groups and
+ function
+
+This patch adds tpu groups and function to r8a7745/r8a7794.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 64dbebc87d5f91435bf4fb8b04a688f570121b7f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 101 +++++++++++++++++++++++++++
+ 1 file changed, 101 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index dccc20ae1130..f133b4f323a2 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -3493,6 +3493,79 @@ static const unsigned int ssi9_ctrl_b_pins[] = {
+ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
++/* - TPU -------------------------------------------------------------------- */
++static const unsigned int tpu_to0_pins[] = {
++	RCAR_GP_PIN(3, 31),
++};
++static const unsigned int tpu_to0_mux[] = {
++	TPUTO0_MARK,
++};
++static const unsigned int tpu_to0_b_pins[] = {
++	RCAR_GP_PIN(3, 30),
++};
++static const unsigned int tpu_to0_b_mux[] = {
++	TPUTO0_B_MARK,
++};
++static const unsigned int tpu_to0_c_pins[] = {
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int tpu_to0_c_mux[] = {
++	TPUTO0_C_MARK,
++};
++static const unsigned int tpu_to1_pins[] = {
++	RCAR_GP_PIN(4, 9),
++};
++static const unsigned int tpu_to1_mux[] = {
++	TPUTO1_MARK,
++};
++static const unsigned int tpu_to1_b_pins[] = {
++	RCAR_GP_PIN(4, 0),
++};
++static const unsigned int tpu_to1_b_mux[] = {
++	TPUTO1_B_MARK,
++};
++static const unsigned int tpu_to1_c_pins[] = {
++	RCAR_GP_PIN(4, 4),
++};
++static const unsigned int tpu_to1_c_mux[] = {
++	TPUTO1_C_MARK,
++};
++static const unsigned int tpu_to2_pins[] = {
++	RCAR_GP_PIN(1, 3),
++};
++static const unsigned int tpu_to2_mux[] = {
++	TPUTO2_MARK,
++};
++static const unsigned int tpu_to2_b_pins[] = {
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int tpu_to2_b_mux[] = {
++	TPUTO2_B_MARK,
++};
++static const unsigned int tpu_to2_c_pins[] = {
++	RCAR_GP_PIN(0, 22),
++};
++static const unsigned int tpu_to2_c_mux[] = {
++	TPUTO2_C_MARK,
++};
++static const unsigned int tpu_to3_pins[] = {
++	RCAR_GP_PIN(1, 14),
++};
++static const unsigned int tpu_to3_mux[] = {
++	TPUTO3_MARK,
++};
++static const unsigned int tpu_to3_b_pins[] = {
++	RCAR_GP_PIN(1, 13),
++};
++static const unsigned int tpu_to3_b_mux[] = {
++	TPUTO3_B_MARK,
++};
++static const unsigned int tpu_to3_c_pins[] = {
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int tpu_to3_c_mux[] = {
++	TPUTO3_C_MARK,
++};
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	RCAR_GP_PIN(5, 24), /* PWEN */
+@@ -3926,6 +3999,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl),
+ 	SH_PFC_PIN_GROUP(ssi9_data_b),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
++	SH_PFC_PIN_GROUP(tpu_to0),
++	SH_PFC_PIN_GROUP(tpu_to0_b),
++	SH_PFC_PIN_GROUP(tpu_to0_c),
++	SH_PFC_PIN_GROUP(tpu_to1),
++	SH_PFC_PIN_GROUP(tpu_to1_b),
++	SH_PFC_PIN_GROUP(tpu_to1_c),
++	SH_PFC_PIN_GROUP(tpu_to2),
++	SH_PFC_PIN_GROUP(tpu_to2_b),
++	SH_PFC_PIN_GROUP(tpu_to2_c),
++	SH_PFC_PIN_GROUP(tpu_to3),
++	SH_PFC_PIN_GROUP(tpu_to3_b),
++	SH_PFC_PIN_GROUP(tpu_to3_c),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	VIN_DATA_PIN_GROUP(vin0_data, 24),
+@@ -4388,6 +4473,21 @@ static const char * const ssi_groups[] = {
+ 	"ssi9_ctrl_b",
+ };
+ 
++static const char * const tpu_groups[] = {
++	"tpu_to0",
++	"tpu_to0_b",
++	"tpu_to0_c",
++	"tpu_to1",
++	"tpu_to1_b",
++	"tpu_to1_c",
++	"tpu_to2",
++	"tpu_to2_b",
++	"tpu_to2_c",
++	"tpu_to3",
++	"tpu_to3_b",
++	"tpu_to3_c",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -4470,6 +4570,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(sdhi1),
+ 	SH_PFC_FUNCTION(sdhi2),
+ 	SH_PFC_FUNCTION(ssi),
++	SH_PFC_FUNCTION(tpu),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(vin0),
+-- 
+2.19.0
+
diff --git a/patches/0500-pinctrl-sh-pfc-r8a7794-Add-i2c5-pin-groups-and-funct.patch b/patches/0500-pinctrl-sh-pfc-r8a7794-Add-i2c5-pin-groups-and-funct.patch
new file mode 100644
index 00000000000000..310741217ee2a0
--- /dev/null
+++ b/patches/0500-pinctrl-sh-pfc-r8a7794-Add-i2c5-pin-groups-and-funct.patch
@@ -0,0 +1,94 @@
+From 2ffca994097eef0af2d39b2701e839050c1638ff Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:04:03 +0000
+Subject: [PATCH 0500/1795] pinctrl: sh-pfc: r8a7794: Add i2c5 pin groups and
+ function
+
+Add i2c5 pin groups and function to r8a7745 PFC driver.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0d68d46035a196c91ee70df2ba204ed708bba315)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 41 ++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+index f133b4f323a2..164002437594 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -2228,6 +2228,35 @@ static const unsigned int i2c4_e_pins[] = {
+ static const unsigned int i2c4_e_mux[] = {
+ 	I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
+ };
++/* - I2C5 ------------------------------------------------------------------- */
++static const unsigned int i2c5_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
++};
++static const unsigned int i2c5_mux[] = {
++	I2C5_SCL_MARK, I2C5_SDA_MARK,
++};
++static const unsigned int i2c5_b_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int i2c5_b_mux[] = {
++	I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
++};
++static const unsigned int i2c5_c_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
++};
++static const unsigned int i2c5_c_mux[] = {
++	I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
++};
++static const unsigned int i2c5_d_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
++};
++static const unsigned int i2c5_d_mux[] = {
++	I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
++};
+ /* - INTC ------------------------------------------------------------------- */
+ static const unsigned int intc_irq0_pins[] = {
+ 	/* IRQ0 */
+@@ -3821,6 +3850,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(i2c4_c),
+ 	SH_PFC_PIN_GROUP(i2c4_d),
+ 	SH_PFC_PIN_GROUP(i2c4_e),
++	SH_PFC_PIN_GROUP(i2c5),
++	SH_PFC_PIN_GROUP(i2c5_b),
++	SH_PFC_PIN_GROUP(i2c5_c),
++	SH_PFC_PIN_GROUP(i2c5_d),
+ 	SH_PFC_PIN_GROUP(intc_irq0),
+ 	SH_PFC_PIN_GROUP(intc_irq1),
+ 	SH_PFC_PIN_GROUP(intc_irq2),
+@@ -4196,6 +4229,13 @@ static const char * const i2c4_groups[] = {
+ 	"i2c4_e",
+ };
+ 
++static const char * const i2c5_groups[] = {
++	"i2c5",
++	"i2c5_b",
++	"i2c5_c",
++	"i2c5_d",
++};
++
+ static const char * const intc_groups[] = {
+ 	"intc_irq0",
+ 	"intc_irq1",
+@@ -4537,6 +4577,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c3),
+ 	SH_PFC_FUNCTION(i2c4),
++	SH_PFC_FUNCTION(i2c5),
+ 	SH_PFC_FUNCTION(intc),
+ 	SH_PFC_FUNCTION(mmc),
+ 	SH_PFC_FUNCTION(msiof0),
+-- 
+2.19.0
+
diff --git a/patches/0501-pinctrl-sh-pfc-r8a7791-Add-tpu-groups-and-function.patch b/patches/0501-pinctrl-sh-pfc-r8a7791-Add-tpu-groups-and-function.patch
new file mode 100644
index 00000000000000..4205cf814189f2
--- /dev/null
+++ b/patches/0501-pinctrl-sh-pfc-r8a7791-Add-tpu-groups-and-function.patch
@@ -0,0 +1,109 @@
+From ce2cc5aa41ce911962b440ddb47154b55e8b1c40 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 17:52:07 +0000
+Subject: [PATCH 0501/1795] pinctrl: sh-pfc: r8a7791: Add tpu groups and
+ function
+
+This patch adds tpu groups and function to r8a7743/r8a7791/r8a7793.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 21047d5736918b19a3efe11e8ace856cb1b4b403)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 42 ++++++++++++++++++++++++++--
+ 1 file changed, 40 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+index c01ef02d326b..5811784d88cb 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -4145,6 +4145,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
+ 
++/* - TPU -------------------------------------------------------------------- */
++static const unsigned int tpu_to0_pins[] = {
++	RCAR_GP_PIN(6, 14),
++};
++static const unsigned int tpu_to0_mux[] = {
++	TPU_TO0_MARK,
++};
++static const unsigned int tpu_to1_pins[] = {
++	RCAR_GP_PIN(1, 17),
++};
++static const unsigned int tpu_to1_mux[] = {
++	TPU_TO1_MARK,
++};
++static const unsigned int tpu_to2_pins[] = {
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int tpu_to2_mux[] = {
++	TPU_TO2_MARK,
++};
++static const unsigned int tpu_to3_pins[] = {
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int tpu_to3_mux[] = {
++	TPU_TO3_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	RCAR_GP_PIN(7, 23), /* PWEN */
+@@ -4431,7 +4457,7 @@ static const unsigned int vin2_clk_mux[] = {
+ };
+ 
+ static const struct {
+-	struct sh_pfc_pin_group common[342];
++	struct sh_pfc_pin_group common[346];
+ 	struct sh_pfc_pin_group r8a779x[9];
+ } pinmux_groups = {
+ 	.common = {
+@@ -4743,6 +4769,10 @@ static const struct {
+ 		SH_PFC_PIN_GROUP(ssi9_data_b),
+ 		SH_PFC_PIN_GROUP(ssi9_ctrl),
+ 		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
++		SH_PFC_PIN_GROUP(tpu_to0),
++		SH_PFC_PIN_GROUP(tpu_to1),
++		SH_PFC_PIN_GROUP(tpu_to2),
++		SH_PFC_PIN_GROUP(tpu_to3),
+ 		SH_PFC_PIN_GROUP(usb0),
+ 		SH_PFC_PIN_GROUP(usb1),
+ 		VIN_DATA_PIN_GROUP(vin0_data, 24),
+@@ -5278,6 +5308,13 @@ static const char * const ssi_groups[] = {
+ 	"ssi9_ctrl_b",
+ };
+ 
++static const char * const tpu_groups[] = {
++	"tpu_to0",
++	"tpu_to1",
++	"tpu_to2",
++	"tpu_to3",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -5327,7 +5364,7 @@ static const char * const vin2_groups[] = {
+ };
+ 
+ static const struct {
+-	struct sh_pfc_function common[57];
++	struct sh_pfc_function common[58];
+ 	struct sh_pfc_function r8a779x[2];
+ } pinmux_functions = {
+ 	.common = {
+@@ -5383,6 +5420,7 @@ static const struct {
+ 		SH_PFC_FUNCTION(sdhi1),
+ 		SH_PFC_FUNCTION(sdhi2),
+ 		SH_PFC_FUNCTION(ssi),
++		SH_PFC_FUNCTION(tpu),
+ 		SH_PFC_FUNCTION(usb0),
+ 		SH_PFC_FUNCTION(usb1),
+ 		SH_PFC_FUNCTION(vin0),
+-- 
+2.19.0
+
diff --git a/patches/0502-pinctrl-sh-pfc-r8a7795-Add-SATA-pins-groups-and-func.patch b/patches/0502-pinctrl-sh-pfc-r8a7795-Add-SATA-pins-groups-and-func.patch
new file mode 100644
index 00000000000000..c7c3af75415eed
--- /dev/null
+++ b/patches/0502-pinctrl-sh-pfc-r8a7795-Add-SATA-pins-groups-and-func.patch
@@ -0,0 +1,76 @@
+From 28650dfe8b56785c8a32cb4dabd5d57a35cc2c62 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 20 Dec 2017 22:59:22 +0100
+Subject: [PATCH 0502/1795] pinctrl: sh-pfc: r8a7795: Add SATA pins, groups,
+ and functions
+
+Tested with a Salvator-XS and H3 ES2.0.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 297e5b2b7a8398b4b850d6bdb63f3a3544670b9e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 7eddd0f2f847..18aeee592fdc 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3227,6 +3227,22 @@ static const unsigned int pwm6_b_mux[] = {
+ 	PWM6_B_MARK,
+ };
+ 
++/* - SATA --------------------------------------------------------------------*/
++static const unsigned int sata0_devslp_a_pins[] = {
++	/* DEVSLP */
++	RCAR_GP_PIN(6, 16),
++};
++static const unsigned int sata0_devslp_a_mux[] = {
++	SATA_DEVSLP_A_MARK,
++};
++static const unsigned int sata0_devslp_b_pins[] = {
++	/* DEVSLP */
++	RCAR_GP_PIN(4, 6),
++};
++static const unsigned int sata0_devslp_b_mux[] = {
++	SATA_DEVSLP_B_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -4092,6 +4108,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(pwm5_b),
+ 	SH_PFC_PIN_GROUP(pwm6_a),
+ 	SH_PFC_PIN_GROUP(pwm6_b),
++	SH_PFC_PIN_GROUP(sata0_devslp_a),
++	SH_PFC_PIN_GROUP(sata0_devslp_b),
+ 	SH_PFC_PIN_GROUP(scif0_data),
+ 	SH_PFC_PIN_GROUP(scif0_clk),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl),
+@@ -4500,6 +4518,11 @@ static const char * const pwm6_groups[] = {
+ 	"pwm6_b",
+ };
+ 
++static const char * const sata0_groups[] = {
++	"sata0_devslp_a",
++	"sata0_devslp_b",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data",
+ 	"scif0_clk",
+@@ -4669,6 +4692,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(pwm4),
+ 	SH_PFC_FUNCTION(pwm5),
+ 	SH_PFC_FUNCTION(pwm6),
++	SH_PFC_FUNCTION(sata0),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/0503-pinctrl-sh-pfc-r8a7795-remove-duplicate-of-CLKOUT-pi.patch b/patches/0503-pinctrl-sh-pfc-r8a7795-remove-duplicate-of-CLKOUT-pi.patch
new file mode 100644
index 00000000000000..0f2f63c541b355
--- /dev/null
+++ b/patches/0503-pinctrl-sh-pfc-r8a7795-remove-duplicate-of-CLKOUT-pi.patch
@@ -0,0 +1,84 @@
+From 3ad9aebf2cee7058d6027ba94243da3db8fa4574 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 22 Feb 2018 00:32:50 +0100
+Subject: [PATCH 0503/1795] pinctrl: sh-pfc: r8a7795: remove duplicate of
+ CLKOUT pin in pinmux_pins[]
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When adding GP-1-28 port pin support it was forgotten to remove the
+CLKOUT pin from the list of pins that are not associated with a GPIO
+port in pinmux_pins[]. This results in a warning when reading the
+pinctrl files in sysfs as the CLKOUT pin is still added as a none GPIO
+pin. Fix this by removing the duplicated entry which is no longer
+needed.
+
+~ # cat /sys/kernel/debug/pinctrl/e6060000.pin-controller/pinconf-pins
+[   89.432081] ------------[ cut here ]------------
+[   89.436904] Pin 496 is not in bias info list
+[   89.441252] WARNING: CPU: 1 PID: 456 at drivers/pinctrl/sh-pfc/core.c:408 sh_pfc_pin_to_bias_reg+0xb0/0xb8
+[   89.451002] CPU: 1 PID: 456 Comm: cat Not tainted 4.16.0-rc1-arm64-renesas-00048-gdfafc344a4f24dde #12
+[   89.460394] Hardware name: Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+ (DT)
+[   89.468910] pstate: 80000085 (Nzcv daIf -PAN -UAO)
+[   89.473747] pc : sh_pfc_pin_to_bias_reg+0xb0/0xb8
+[   89.478495] lr : sh_pfc_pin_to_bias_reg+0xb0/0xb8
+[   89.483241] sp : ffff00000aff3ab0
+[   89.486587] x29: ffff00000aff3ab0 x28: ffff00000893c698
+[   89.491955] x27: ffff000008ad7d98 x26: 0000000000000000
+[   89.497323] x25: ffff8006fb3f5028 x24: ffff8006fb3f5018
+[   89.502690] x23: 0000000000000001 x22: 00000000000001f0
+[   89.508057] x21: ffff8006fb3f5018 x20: ffff000008bef000
+[   89.513423] x19: 0000000000000000 x18: ffffffffffffffff
+[   89.518790] x17: 0000000000006c4a x16: ffff000008d67c98
+[   89.524157] x15: 0000000000000001 x14: ffff00000896ca98
+[   89.529524] x13: 00000000cce5f611 x12: ffff8006f8d3b5a8
+[   89.534891] x11: ffff00000981e000 x10: ffff000008befa08
+[   89.540258] x9 : ffff8006f9b987a0 x8 : ffff000008befa08
+[   89.545625] x7 : ffff000008137094 x6 : 0000000000000000
+[   89.550991] x5 : 0000000000000000 x4 : 0000000000000001
+[   89.556357] x3 : 0000000000000007 x2 : 0000000000000007
+[   89.561723] x1 : 1ff24f80f1818600 x0 : 0000000000000000
+[   89.567091] Call trace:
+[   89.569561]  sh_pfc_pin_to_bias_reg+0xb0/0xb8
+[   89.573960]  r8a7795_pinmux_get_bias+0x30/0xc0
+[   89.578445]  sh_pfc_pinconf_get+0x1e0/0x2d8
+[   89.582669]  pin_config_get_for_pin+0x20/0x30
+[   89.587067]  pinconf_generic_dump_one+0x180/0x1c8
+[   89.591815]  pinconf_generic_dump_pins+0x84/0xd8
+[   89.596476]  pinconf_pins_show+0xc8/0x130
+[   89.600528]  seq_read+0xe4/0x510
+[   89.603789]  full_proxy_read+0x60/0x90
+[   89.607576]  __vfs_read+0x30/0x140
+[   89.611010]  vfs_read+0x90/0x170
+[   89.614269]  SyS_read+0x60/0xd8
+[   89.617443]  __sys_trace_return+0x0/0x4
+[   89.621314] ---[ end trace 99c8d0d39c13e794 ]---
+
+Fixes: 82d2de5a4f646f72 ("pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin support")
+Reviewed-and-tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 625504aeff11eeb95f78ad9dde22d911c6839c71)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 18aeee592fdc..35951e7b89d2 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1538,7 +1538,6 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
+ 	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
+ 	SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
+-	SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),
+ 	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
+ 	SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
+ 	SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
+-- 
+2.19.0
+
diff --git a/patches/0504-treewide-Use-DEVICE_ATTR_RW.patch b/patches/0504-treewide-Use-DEVICE_ATTR_RW.patch
new file mode 100644
index 00000000000000..c1b2fd0f9d1e77
--- /dev/null
+++ b/patches/0504-treewide-Use-DEVICE_ATTR_RW.patch
@@ -0,0 +1,488 @@
+From bcab75c273e43097627dcd47b59f87939070199b Mon Sep 17 00:00:00 2001
+From: Joe Perches <joe@perches.com>
+Date: Tue, 19 Dec 2017 10:15:07 -0800
+Subject: [PATCH 0504/1795] treewide: Use DEVICE_ATTR_RW
+
+Convert DEVICE_ATTR uses to DEVICE_ATTR_RW where possible.
+
+Done with perl script:
+
+$ git grep -w --name-only DEVICE_ATTR | \
+  xargs perl -i -e 'local $/; while (<>) { s/\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?(\s*S_IRUGO\s*\|\s*S_IWUSR|\s*S_IWUSR\s*\|\s*S_IRUGO\s*|\s*0644\s*)\)?\s*,\s*\1_show\s*,\s*\1_store\s*\)/DEVICE_ATTR_RW(\1)/g; print;}'
+
+Signed-off-by: Joe Perches <joe@perches.com>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+Acked-by: Zhang Rui <rui.zhang@intel.com>
+Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
+Acked-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit b6b996b6cdeecf7e1646c87422e04e446ddce124)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/s390/kernel/topology.c          |  3 +-
+ arch/tile/kernel/sysfs.c             |  2 +-
+ drivers/gpu/drm/i915/i915_sysfs.c    |  6 ++--
+ drivers/platform/x86/compal-laptop.c | 18 ++++--------
+ drivers/s390/cio/device.c            |  2 +-
+ drivers/scsi/lpfc/lpfc_attr.c        | 43 +++++++++-------------------
+ drivers/thermal/thermal_sysfs.c      |  9 +++---
+ drivers/tty/serial/sh-sci.c          |  2 +-
+ drivers/usb/phy/phy-tahvo.c          |  2 +-
+ drivers/video/fbdev/auo_k190x.c      |  4 +--
+ drivers/video/fbdev/w100fb.c         |  4 +--
+ lib/test_firmware.c                  | 14 ++++-----
+ lib/test_kmod.c                      | 14 ++++-----
+ sound/soc/omap/mcbsp.c               |  4 +--
+ 14 files changed, 48 insertions(+), 79 deletions(-)
+
+diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
+index ed0bdd220e1a..11e7a57c1185 100644
+--- a/arch/s390/kernel/topology.c
++++ b/arch/s390/kernel/topology.c
+@@ -394,8 +394,7 @@ static ssize_t dispatching_store(struct device *dev,
+ 	put_online_cpus();
+ 	return rc ? rc : count;
+ }
+-static DEVICE_ATTR(dispatching, 0644, dispatching_show,
+-			 dispatching_store);
++static DEVICE_ATTR_RW(dispatching);
+ 
+ static ssize_t cpu_polarization_show(struct device *dev,
+ 				     struct device_attribute *attr, char *buf)
+diff --git a/arch/tile/kernel/sysfs.c b/arch/tile/kernel/sysfs.c
+index 825867c53853..af5024f0fb5a 100644
+--- a/arch/tile/kernel/sysfs.c
++++ b/arch/tile/kernel/sysfs.c
+@@ -184,7 +184,7 @@ static ssize_t hv_stats_store(struct device *dev,
+ 	return n < 0 ? n : count;
+ }
+ 
+-static DEVICE_ATTR(hv_stats, 0644, hv_stats_show, hv_stats_store);
++static DEVICE_ATTR_RW(hv_stats);
+ 
+ static int hv_stats_device_add(struct device *dev, struct subsys_interface *sif)
+ {
+diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
+index d61c8727f756..aed3a6dedfc1 100644
+--- a/drivers/gpu/drm/i915/i915_sysfs.c
++++ b/drivers/gpu/drm/i915/i915_sysfs.c
+@@ -433,9 +433,9 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
+ 
+ static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
+ static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+-static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
+-static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
+-static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
++static DEVICE_ATTR_RW(gt_boost_freq_mhz);
++static DEVICE_ATTR_RW(gt_max_freq_mhz);
++static DEVICE_ATTR_RW(gt_min_freq_mhz);
+ 
+ static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
+ 
+diff --git a/drivers/platform/x86/compal-laptop.c b/drivers/platform/x86/compal-laptop.c
+index 6bcb750e1865..4f9bc72f0584 100644
+--- a/drivers/platform/x86/compal-laptop.c
++++ b/drivers/platform/x86/compal-laptop.c
+@@ -679,18 +679,12 @@ static int bat_writeable_property(struct power_supply *psy,
+ /* ============== */
+ /* Driver Globals */
+ /* ============== */
+-static DEVICE_ATTR(wake_up_pme,
+-		0644, wake_up_pme_show,		wake_up_pme_store);
+-static DEVICE_ATTR(wake_up_modem,
+-		0644, wake_up_modem_show,	wake_up_modem_store);
+-static DEVICE_ATTR(wake_up_lan,
+-		0644, wake_up_lan_show,	wake_up_lan_store);
+-static DEVICE_ATTR(wake_up_wlan,
+-		0644, wake_up_wlan_show,	wake_up_wlan_store);
+-static DEVICE_ATTR(wake_up_key,
+-		0644, wake_up_key_show,	wake_up_key_store);
+-static DEVICE_ATTR(wake_up_mouse,
+-		0644, wake_up_mouse_show,	wake_up_mouse_store);
++static DEVICE_ATTR_RW(wake_up_pme);
++static DEVICE_ATTR_RW(wake_up_modem);
++static DEVICE_ATTR_RW(wake_up_lan);
++static DEVICE_ATTR_RW(wake_up_wlan);
++static DEVICE_ATTR_RW(wake_up_key);
++static DEVICE_ATTR_RW(wake_up_mouse);
+ 
+ static DEVICE_ATTR(fan1_input,  S_IRUGO, fan_show,          NULL);
+ static DEVICE_ATTR(temp1_input, S_IRUGO, temp_cpu,          NULL);
+diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c
+index e5c32f4b5287..93f1ee9810f6 100644
+--- a/drivers/s390/cio/device.c
++++ b/drivers/s390/cio/device.c
+@@ -601,7 +601,7 @@ static ssize_t vpm_show(struct device *dev, struct device_attribute *attr,
+ static DEVICE_ATTR(devtype, 0444, devtype_show, NULL);
+ static DEVICE_ATTR(cutype, 0444, cutype_show, NULL);
+ static DEVICE_ATTR(modalias, 0444, modalias_show, NULL);
+-static DEVICE_ATTR(online, 0644, online_show, online_store);
++static DEVICE_ATTR_RW(online);
+ static DEVICE_ATTR(availability, 0444, available_show, NULL);
+ static DEVICE_ATTR(logging, 0200, NULL, initiate_logging);
+ static DEVICE_ATTR(vpm, 0444, vpm_show, NULL);
+diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c
+index 3da242201cb4..a4765f0be925 100644
+--- a/drivers/scsi/lpfc/lpfc_attr.c
++++ b/drivers/scsi/lpfc/lpfc_attr.c
+@@ -2490,8 +2490,7 @@ lpfc_soft_wwpn_store(struct device *dev, struct device_attribute *attr,
+ 				"reinit adapter - %d\n", stat2);
+ 	return (stat1 || stat2) ? -EIO : count;
+ }
+-static DEVICE_ATTR(lpfc_soft_wwpn, S_IRUGO | S_IWUSR,
+-		   lpfc_soft_wwpn_show, lpfc_soft_wwpn_store);
++static DEVICE_ATTR_RW(lpfc_soft_wwpn);
+ 
+ /**
+  * lpfc_soft_wwnn_show - Return the cfg soft ww node name for the adapter
+@@ -2554,8 +2553,7 @@ lpfc_soft_wwnn_store(struct device *dev, struct device_attribute *attr,
+ 
+ 	return count;
+ }
+-static DEVICE_ATTR(lpfc_soft_wwnn, S_IRUGO | S_IWUSR,
+-		   lpfc_soft_wwnn_show, lpfc_soft_wwnn_store);
++static DEVICE_ATTR_RW(lpfc_soft_wwnn);
+ 
+ /**
+  * lpfc_oas_tgt_show - Return wwpn of target whose luns maybe enabled for
+@@ -3073,8 +3071,7 @@ MODULE_PARM_DESC(lpfc_poll, "FCP ring polling mode control:"
+ 		 " 1 - poll with interrupts enabled"
+ 		 " 3 - poll and disable FCP ring interrupts");
+ 
+-static DEVICE_ATTR(lpfc_poll, S_IRUGO | S_IWUSR,
+-		   lpfc_poll_show, lpfc_poll_store);
++static DEVICE_ATTR_RW(lpfc_poll);
+ 
+ int lpfc_no_hba_reset_cnt;
+ unsigned long lpfc_no_hba_reset[MAX_HBAS_NO_RESET] = {
+@@ -3302,8 +3299,7 @@ lpfc_nodev_tmo_set(struct lpfc_vport *vport, int val)
+ 
+ lpfc_vport_param_store(nodev_tmo)
+ 
+-static DEVICE_ATTR(lpfc_nodev_tmo, S_IRUGO | S_IWUSR,
+-		   lpfc_nodev_tmo_show, lpfc_nodev_tmo_store);
++static DEVICE_ATTR_RW(lpfc_nodev_tmo);
+ 
+ /*
+ # lpfc_devloss_tmo: If set, it will hold all I/O errors on devices that
+@@ -3352,8 +3348,7 @@ lpfc_devloss_tmo_set(struct lpfc_vport *vport, int val)
+ }
+ 
+ lpfc_vport_param_store(devloss_tmo)
+-static DEVICE_ATTR(lpfc_devloss_tmo, S_IRUGO | S_IWUSR,
+-		   lpfc_devloss_tmo_show, lpfc_devloss_tmo_store);
++static DEVICE_ATTR_RW(lpfc_devloss_tmo);
+ 
+ /*
+  * lpfc_suppress_rsp: Enable suppress rsp feature is firmware supports it
+@@ -3545,8 +3540,7 @@ lpfc_restrict_login_set(struct lpfc_vport *vport, int val)
+ 	return 0;
+ }
+ lpfc_vport_param_store(restrict_login);
+-static DEVICE_ATTR(lpfc_restrict_login, S_IRUGO | S_IWUSR,
+-		   lpfc_restrict_login_show, lpfc_restrict_login_store);
++static DEVICE_ATTR_RW(lpfc_restrict_login);
+ 
+ /*
+ # Some disk devices have a "select ID" or "select Target" capability.
+@@ -3660,8 +3654,7 @@ lpfc_topology_store(struct device *dev, struct device_attribute *attr,
+ }
+ 
+ lpfc_param_show(topology)
+-static DEVICE_ATTR(lpfc_topology, S_IRUGO | S_IWUSR,
+-		lpfc_topology_show, lpfc_topology_store);
++static DEVICE_ATTR_RW(lpfc_topology);
+ 
+ /**
+  * lpfc_static_vport_show: Read callback function for
+@@ -3919,8 +3912,7 @@ lpfc_stat_data_ctrl_show(struct device *dev, struct device_attribute *attr,
+ /*
+  * Sysfs attribute to control the statistical data collection.
+  */
+-static DEVICE_ATTR(lpfc_stat_data_ctrl, S_IRUGO | S_IWUSR,
+-		   lpfc_stat_data_ctrl_show, lpfc_stat_data_ctrl_store);
++static DEVICE_ATTR_RW(lpfc_stat_data_ctrl);
+ 
+ /*
+  * lpfc_drvr_stat_data: sysfs attr to get driver statistical data.
+@@ -4159,8 +4151,7 @@ lpfc_link_speed_init(struct lpfc_hba *phba, int val)
+ 	return -EINVAL;
+ }
+ 
+-static DEVICE_ATTR(lpfc_link_speed, S_IRUGO | S_IWUSR,
+-		   lpfc_link_speed_show, lpfc_link_speed_store);
++static DEVICE_ATTR_RW(lpfc_link_speed);
+ 
+ /*
+ # lpfc_aer_support: Support PCIe device Advanced Error Reporting (AER)
+@@ -4253,8 +4244,7 @@ lpfc_aer_support_store(struct device *dev, struct device_attribute *attr,
+ 	return rc;
+ }
+ 
+-static DEVICE_ATTR(lpfc_aer_support, S_IRUGO | S_IWUSR,
+-		   lpfc_aer_support_show, lpfc_aer_support_store);
++static DEVICE_ATTR_RW(lpfc_aer_support);
+ 
+ /**
+  * lpfc_aer_cleanup_state - Clean up aer state to the aer enabled device
+@@ -4401,8 +4391,7 @@ LPFC_ATTR(sriov_nr_virtfn, LPFC_DEF_VFN_PER_PFN, 0, LPFC_MAX_VFN_PER_PFN,
+ 	"Enable PCIe device SR-IOV virtual fn");
+ 
+ lpfc_param_show(sriov_nr_virtfn)
+-static DEVICE_ATTR(lpfc_sriov_nr_virtfn, S_IRUGO | S_IWUSR,
+-		   lpfc_sriov_nr_virtfn_show, lpfc_sriov_nr_virtfn_store);
++static DEVICE_ATTR_RW(lpfc_sriov_nr_virtfn);
+ 
+ /**
+  * lpfc_request_firmware_store - Request for Linux generic firmware upgrade
+@@ -4576,8 +4565,7 @@ lpfc_fcp_imax_init(struct lpfc_hba *phba, int val)
+ 	return 0;
+ }
+ 
+-static DEVICE_ATTR(lpfc_fcp_imax, S_IRUGO | S_IWUSR,
+-		   lpfc_fcp_imax_show, lpfc_fcp_imax_store);
++static DEVICE_ATTR_RW(lpfc_fcp_imax);
+ 
+ /*
+  * lpfc_auto_imax: Controls Auto-interrupt coalescing values support.
+@@ -4737,8 +4725,7 @@ lpfc_fcp_cpu_map_init(struct lpfc_hba *phba, int val)
+ 	return 0;
+ }
+ 
+-static DEVICE_ATTR(lpfc_fcp_cpu_map, S_IRUGO | S_IWUSR,
+-		   lpfc_fcp_cpu_map_show, lpfc_fcp_cpu_map_store);
++static DEVICE_ATTR_RW(lpfc_fcp_cpu_map);
+ 
+ /*
+ # lpfc_fcp_class:  Determines FC class to use for the FCP protocol.
+@@ -4824,9 +4811,7 @@ lpfc_max_scsicmpl_time_set(struct lpfc_vport *vport, int val)
+ 	return 0;
+ }
+ lpfc_vport_param_store(max_scsicmpl_time);
+-static DEVICE_ATTR(lpfc_max_scsicmpl_time, S_IRUGO | S_IWUSR,
+-		   lpfc_max_scsicmpl_time_show,
+-		   lpfc_max_scsicmpl_time_store);
++static DEVICE_ATTR_RW(lpfc_max_scsicmpl_time);
+ 
+ /*
+ # lpfc_ack0: Use ACK0, instead of ACK1 for class 2 acknowledgement. Value
+diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c
+index fb80c96d8f73..c008af7fb480 100644
+--- a/drivers/thermal/thermal_sysfs.c
++++ b/drivers/thermal/thermal_sysfs.c
+@@ -398,14 +398,13 @@ create_s32_tzp_attr(offset);
+  */
+ static DEVICE_ATTR(type, 0444, type_show, NULL);
+ static DEVICE_ATTR(temp, 0444, temp_show, NULL);
+-static DEVICE_ATTR(policy, S_IRUGO | S_IWUSR, policy_show, policy_store);
++static DEVICE_ATTR_RW(policy);
+ static DEVICE_ATTR(available_policies, S_IRUGO, available_policies_show, NULL);
+-static DEVICE_ATTR(sustainable_power, S_IWUSR | S_IRUGO, sustainable_power_show,
+-		   sustainable_power_store);
++static DEVICE_ATTR_RW(sustainable_power);
+ 
+ /* These thermal zone device attributes are created based on conditions */
+-static DEVICE_ATTR(mode, 0644, mode_show, mode_store);
+-static DEVICE_ATTR(passive, S_IRUGO | S_IWUSR, passive_show, passive_store);
++static DEVICE_ATTR_RW(mode);
++static DEVICE_ATTR_RW(passive);
+ 
+ /* These attributes are unconditionally added to a thermal zone */
+ static struct attribute *thermal_zone_dev_attrs[] = {
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 78f862df4f6e..86b928e71dd9 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -1147,7 +1147,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev,
+ 	return count;
+ }
+ 
+-static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
++static DEVICE_ATTR_RW(rx_fifo_timeout);
+ 
+ 
+ #ifdef CONFIG_SERIAL_SH_SCI_DMA
+diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c
+index 3a437bf5e004..4143756e3b19 100644
+--- a/drivers/usb/phy/phy-tahvo.c
++++ b/drivers/usb/phy/phy-tahvo.c
+@@ -319,7 +319,7 @@ static ssize_t otg_mode_store(struct device *device,
+ 
+ 	return r;
+ }
+-static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
++static DEVICE_ATTR_RW(otg_mode);
+ 
+ static struct attribute *tahvo_attributes[] = {
+ 	&dev_attr_vbus.attr,
+diff --git a/drivers/video/fbdev/auo_k190x.c b/drivers/video/fbdev/auo_k190x.c
+index 0d06038324e0..1e383c547633 100644
+--- a/drivers/video/fbdev/auo_k190x.c
++++ b/drivers/video/fbdev/auo_k190x.c
+@@ -708,8 +708,8 @@ static ssize_t temp_show(struct device *dev, struct device_attribute *attr,
+ 	return sprintf(buf, "%d\n", temp);
+ }
+ 
+-static DEVICE_ATTR(update_mode, 0644, update_mode_show, update_mode_store);
+-static DEVICE_ATTR(flash, 0644, flash_show, flash_store);
++static DEVICE_ATTR_RW(update_mode);
++static DEVICE_ATTR_RW(flash);
+ static DEVICE_ATTR(temp, 0644, temp_show, NULL);
+ 
+ static struct attribute *auok190x_attributes[] = {
+diff --git a/drivers/video/fbdev/w100fb.c b/drivers/video/fbdev/w100fb.c
+index d570e19a2864..035ff6e02894 100644
+--- a/drivers/video/fbdev/w100fb.c
++++ b/drivers/video/fbdev/w100fb.c
+@@ -110,7 +110,7 @@ static ssize_t flip_store(struct device *dev, struct device_attribute *attr, con
+ 	return count;
+ }
+ 
+-static DEVICE_ATTR(flip, 0644, flip_show, flip_store);
++static DEVICE_ATTR_RW(flip);
+ 
+ static ssize_t w100fb_reg_read(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+ {
+@@ -166,7 +166,7 @@ static ssize_t fastpllclk_store(struct device *dev, struct device_attribute *att
+ 	return count;
+ }
+ 
+-static DEVICE_ATTR(fastpllclk, 0644, fastpllclk_show, fastpllclk_store);
++static DEVICE_ATTR_RW(fastpllclk);
+ 
+ /*
+  * Some touchscreens need hsync information from the video driver to
+diff --git a/lib/test_firmware.c b/lib/test_firmware.c
+index e7008688769b..464764772adc 100644
+--- a/lib/test_firmware.c
++++ b/lib/test_firmware.c
+@@ -359,7 +359,7 @@ static ssize_t config_name_show(struct device *dev,
+ {
+ 	return config_test_show_str(buf, test_fw_config->name);
+ }
+-static DEVICE_ATTR(config_name, 0644, config_name_show, config_name_store);
++static DEVICE_ATTR_RW(config_name);
+ 
+ static ssize_t config_num_requests_store(struct device *dev,
+ 					 struct device_attribute *attr,
+@@ -389,8 +389,7 @@ static ssize_t config_num_requests_show(struct device *dev,
+ {
+ 	return test_dev_config_show_u8(buf, test_fw_config->num_requests);
+ }
+-static DEVICE_ATTR(config_num_requests, 0644, config_num_requests_show,
+-		   config_num_requests_store);
++static DEVICE_ATTR_RW(config_num_requests);
+ 
+ static ssize_t config_sync_direct_store(struct device *dev,
+ 					struct device_attribute *attr,
+@@ -412,8 +411,7 @@ static ssize_t config_sync_direct_show(struct device *dev,
+ {
+ 	return test_dev_config_show_bool(buf, test_fw_config->sync_direct);
+ }
+-static DEVICE_ATTR(config_sync_direct, 0644, config_sync_direct_show,
+-		   config_sync_direct_store);
++static DEVICE_ATTR_RW(config_sync_direct);
+ 
+ static ssize_t config_send_uevent_store(struct device *dev,
+ 					struct device_attribute *attr,
+@@ -429,8 +427,7 @@ static ssize_t config_send_uevent_show(struct device *dev,
+ {
+ 	return test_dev_config_show_bool(buf, test_fw_config->send_uevent);
+ }
+-static DEVICE_ATTR(config_send_uevent, 0644, config_send_uevent_show,
+-		   config_send_uevent_store);
++static DEVICE_ATTR_RW(config_send_uevent);
+ 
+ static ssize_t config_read_fw_idx_store(struct device *dev,
+ 					struct device_attribute *attr,
+@@ -446,8 +443,7 @@ static ssize_t config_read_fw_idx_show(struct device *dev,
+ {
+ 	return test_dev_config_show_u8(buf, test_fw_config->read_fw_idx);
+ }
+-static DEVICE_ATTR(config_read_fw_idx, 0644, config_read_fw_idx_show,
+-		   config_read_fw_idx_store);
++static DEVICE_ATTR_RW(config_read_fw_idx);
+ 
+ 
+ static ssize_t trigger_request_store(struct device *dev,
+diff --git a/lib/test_kmod.c b/lib/test_kmod.c
+index 96c304fd656a..47604dfd428e 100644
+--- a/lib/test_kmod.c
++++ b/lib/test_kmod.c
+@@ -694,8 +694,7 @@ static ssize_t config_test_driver_show(struct device *dev,
+ 	return config_test_show_str(&test_dev->config_mutex, buf,
+ 				    config->test_driver);
+ }
+-static DEVICE_ATTR(config_test_driver, 0644, config_test_driver_show,
+-		   config_test_driver_store);
++static DEVICE_ATTR_RW(config_test_driver);
+ 
+ static ssize_t config_test_fs_store(struct device *dev,
+ 				    struct device_attribute *attr,
+@@ -726,8 +725,7 @@ static ssize_t config_test_fs_show(struct device *dev,
+ 	return config_test_show_str(&test_dev->config_mutex, buf,
+ 				    config->test_fs);
+ }
+-static DEVICE_ATTR(config_test_fs, 0644, config_test_fs_show,
+-		   config_test_fs_store);
++static DEVICE_ATTR_RW(config_test_fs);
+ 
+ static int trigger_config_run_type(struct kmod_test_device *test_dev,
+ 				   enum kmod_test_case test_case,
+@@ -1014,8 +1012,7 @@ static ssize_t config_num_threads_show(struct device *dev,
+ 
+ 	return test_dev_config_show_int(test_dev, buf, config->num_threads);
+ }
+-static DEVICE_ATTR(config_num_threads, 0644, config_num_threads_show,
+-		   config_num_threads_store);
++static DEVICE_ATTR_RW(config_num_threads);
+ 
+ static ssize_t config_test_case_store(struct device *dev,
+ 				      struct device_attribute *attr,
+@@ -1039,8 +1036,7 @@ static ssize_t config_test_case_show(struct device *dev,
+ 
+ 	return test_dev_config_show_uint(test_dev, buf, config->test_case);
+ }
+-static DEVICE_ATTR(config_test_case, 0644, config_test_case_show,
+-		   config_test_case_store);
++static DEVICE_ATTR_RW(config_test_case);
+ 
+ static ssize_t test_result_show(struct device *dev,
+ 				struct device_attribute *attr,
+@@ -1051,7 +1047,7 @@ static ssize_t test_result_show(struct device *dev,
+ 
+ 	return test_dev_config_show_int(test_dev, buf, config->test_result);
+ }
+-static DEVICE_ATTR(test_result, 0644, test_result_show, test_result_store);
++static DEVICE_ATTR_RW(test_result);
+ 
+ #define TEST_KMOD_DEV_ATTR(name)		&dev_attr_##name.attr
+ 
+diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
+index 7a54e3083203..79d4dc785e5c 100644
+--- a/sound/soc/omap/mcbsp.c
++++ b/sound/soc/omap/mcbsp.c
+@@ -854,7 +854,7 @@ static ssize_t dma_op_mode_store(struct device *dev,
+ 	return size;
+ }
+ 
+-static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
++static DEVICE_ATTR_RW(dma_op_mode);
+ 
+ static const struct attribute *additional_attrs[] = {
+ 	&dev_attr_max_tx_thres.attr,
+@@ -923,7 +923,7 @@ static ssize_t st_taps_store(struct device *dev,
+ 	return size;
+ }
+ 
+-static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
++static DEVICE_ATTR_RW(st_taps);
+ 
+ static const struct attribute *sidetone_attrs[] = {
+ 	&dev_attr_st_taps.attr,
+-- 
+2.19.0
+
diff --git a/patches/0505-usb-gadget-udc-renesas_usb3-fix-oops-in-renesas_usb3.patch b/patches/0505-usb-gadget-udc-renesas_usb3-fix-oops-in-renesas_usb3.patch
new file mode 100644
index 00000000000000..2b1588003d2764
--- /dev/null
+++ b/patches/0505-usb-gadget-udc-renesas_usb3-fix-oops-in-renesas_usb3.patch
@@ -0,0 +1,36 @@
+From a8340390d5d9257a54426fe1d7fd2901e521136d Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 12 Jan 2018 20:00:56 +0900
+Subject: [PATCH 0505/1795] usb: gadget: udc: renesas_usb3: fix oops in
+ renesas_usb3_remove()
+
+This patch fixes an issue that the renesas_usb3_remove() causes
+NULL pointer dereference because the usb3_to_dev() macro will use
+the gadget instance and it will be deleted before.
+
+Fixes: cf06df3fae28 ("usb: gadget: udc: renesas_usb3: move pm_runtime_{en,dis}able()")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit e3190868e5f52fb26544f16463593d54ce46ce61)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 7e04b5c0fd32..94224101033e 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2423,7 +2423,7 @@ static int renesas_usb3_remove(struct platform_device *pdev)
+ 	__renesas_usb3_ep_free_request(usb3->ep0_req);
+ 	if (usb3->phy)
+ 		phy_put(usb3->phy);
+-	pm_runtime_disable(usb3_to_dev(usb3));
++	pm_runtime_disable(&pdev->dev);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0506-usb-gadget-udc-renesas_usb3-add-binging-for-r8a77965.patch b/patches/0506-usb-gadget-udc-renesas_usb3-add-binging-for-r8a77965.patch
new file mode 100644
index 00000000000000..916be60efc2c60
--- /dev/null
+++ b/patches/0506-usb-gadget-udc-renesas_usb3-add-binging-for-r8a77965.patch
@@ -0,0 +1,32 @@
+From 9c0b9a1c1083ec6fc4ccda9390d547db1f5243f7 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 27 Feb 2018 17:16:03 +0900
+Subject: [PATCH 0506/1795] usb: gadget: udc: renesas_usb3: add binging for
+ r8a77965
+
+This patch adds binding for r8a77965 (R-Car M3-N).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit c6ba5084ce0d00d4a005b0577d9e764d39b638e1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/renesas_usb3.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usb3.txt b/Documentation/devicetree/bindings/usb/renesas_usb3.txt
+index 87a45e2f9b7f..2c071bb5801e 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usb3.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usb3.txt
+@@ -4,6 +4,7 @@ Required properties:
+   - compatible: Must contain one of the following:
+ 	- "renesas,r8a7795-usb3-peri"
+ 	- "renesas,r8a7796-usb3-peri"
++	- "renesas,r8a77965-usb3-peri"
+ 	- "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 compatible
+ 	  device
+ 
+-- 
+2.19.0
+
diff --git a/patches/0507-usb-renesas_usbhs-remove-redundant-polling-in-usbhsf.patch b/patches/0507-usb-renesas_usbhs-remove-redundant-polling-in-usbhsf.patch
new file mode 100644
index 00000000000000..baf61a58ccbf43
--- /dev/null
+++ b/patches/0507-usb-renesas_usbhs-remove-redundant-polling-in-usbhsf.patch
@@ -0,0 +1,55 @@
+From 89382618fafdd570f1c4b66614b0324469a6404f Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 6 Dec 2017 17:18:31 +0900
+Subject: [PATCH 0507/1795] usb: renesas_usbhs: remove redundant polling in
+ usbhsf_fifo_barrier()
+
+The datasheet doesn't mention that needs to poll of FRDY is set or not.
+So, this patch removes such handling in the usbhsf_fifo_barrier().
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 469e297813440bec9bdf98766f932eb79d2a3a94)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/fifo.c | 16 +++++-----------
+ 1 file changed, 5 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
+index b295e204a575..d967908cda7c 100644
+--- a/drivers/usb/renesas_usbhs/fifo.c
++++ b/drivers/usb/renesas_usbhs/fifo.c
+@@ -256,15 +256,9 @@ static void usbhsf_send_terminator(struct usbhs_pipe *pipe,
+ static int usbhsf_fifo_barrier(struct usbhs_priv *priv,
+ 			       struct usbhs_fifo *fifo)
+ {
+-	int timeout = 1024;
+-
+-	do {
+-		/* The FIFO port is accessible */
+-		if (usbhs_read(priv, fifo->ctr) & FRDY)
+-			return 0;
+-
+-		udelay(10);
+-	} while (timeout--);
++	/* The FIFO port is accessible */
++	if (usbhs_read(priv, fifo->ctr) & FRDY)
++		return 0;
+ 
+ 	return -EBUSY;
+ }
+@@ -278,8 +272,8 @@ static void usbhsf_fifo_clear(struct usbhs_pipe *pipe,
+ 	if (!usbhs_pipe_is_dcp(pipe)) {
+ 		/*
+ 		 * This driver checks the pipe condition first to avoid -EBUSY
+-		 * from usbhsf_fifo_barrier() with about 10 msec delay in
+-		 * the interrupt handler if the pipe is RX direction and empty.
++		 * from usbhsf_fifo_barrier() if the pipe is RX direction and
++		 * empty.
+ 		 */
+ 		if (usbhs_pipe_is_dir_in(pipe))
+ 			ret = usbhs_pipe_is_accessible(pipe);
+-- 
+2.19.0
+
diff --git a/patches/0508-usb-renesas_usbhs-add-usbhs_pipe_clear_without_seque.patch b/patches/0508-usb-renesas_usbhs-add-usbhs_pipe_clear_without_seque.patch
new file mode 100644
index 00000000000000..917e9fbe7fa590
--- /dev/null
+++ b/patches/0508-usb-renesas_usbhs-add-usbhs_pipe_clear_without_seque.patch
@@ -0,0 +1,77 @@
+From ae709040337cd251060e70b73f2c7e97ab0c77d1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 6 Dec 2017 17:18:32 +0900
+Subject: [PATCH 0508/1795] usb: renesas_usbhs: add
+ usbhs_pipe_clear_without_sequence() function
+
+This patch adds usbhs_pipe_clear_without_sequence() function.
+The controller has the pipe buffer and the PIPEnCTR.ACLRM can clear
+it completely. But, it's also clear the data sequence. So, the driver
+needs to get the sequence before.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 8d8a0435d10225499ddc8ad36446773ddecaf484)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/pipe.c | 19 ++++++++++++++-----
+ drivers/usb/renesas_usbhs/pipe.h |  2 ++
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/pipe.c b/drivers/usb/renesas_usbhs/pipe.c
+index 093cd8e87335..9677e0e31475 100644
+--- a/drivers/usb/renesas_usbhs/pipe.c
++++ b/drivers/usb/renesas_usbhs/pipe.c
+@@ -590,10 +590,22 @@ void usbhs_pipe_clear(struct usbhs_pipe *pipe)
+ 	}
+ }
+ 
+-void usbhs_pipe_config_change_bfre(struct usbhs_pipe *pipe, int enable)
++/* Should call usbhsp_pipe_select() before */
++void usbhs_pipe_clear_without_sequence(struct usbhs_pipe *pipe,
++				       int needs_bfre, int bfre_enable)
+ {
+ 	int sequence;
+ 
++	usbhsp_pipe_select(pipe);
++	sequence = usbhs_pipe_get_data_sequence(pipe);
++	if (needs_bfre)
++		usbhsp_pipe_cfg_set(pipe, BFRE, bfre_enable ? BFRE : 0);
++	usbhs_pipe_clear(pipe);
++	usbhs_pipe_data_sequence(pipe, sequence);
++}
++
++void usbhs_pipe_config_change_bfre(struct usbhs_pipe *pipe, int enable)
++{
+ 	if (usbhs_pipe_is_dcp(pipe))
+ 		return;
+ 
+@@ -602,10 +614,7 @@ void usbhs_pipe_config_change_bfre(struct usbhs_pipe *pipe, int enable)
+ 	if (!(enable ^ !!(usbhsp_pipe_cfg_get(pipe) & BFRE)))
+ 		return;
+ 
+-	sequence = usbhs_pipe_get_data_sequence(pipe);
+-	usbhsp_pipe_cfg_set(pipe, BFRE, enable ? BFRE : 0);
+-	usbhs_pipe_clear(pipe);
+-	usbhs_pipe_data_sequence(pipe, sequence);
++	usbhs_pipe_clear_without_sequence(pipe, 1, enable);
+ }
+ 
+ static struct usbhs_pipe *usbhsp_get_pipe(struct usbhs_priv *priv, u32 type)
+diff --git a/drivers/usb/renesas_usbhs/pipe.h b/drivers/usb/renesas_usbhs/pipe.h
+index d3d002244891..3080423e600c 100644
+--- a/drivers/usb/renesas_usbhs/pipe.h
++++ b/drivers/usb/renesas_usbhs/pipe.h
+@@ -80,6 +80,8 @@ void usbhs_pipe_init(struct usbhs_priv *priv,
+ 					 struct usbhs_pkt *pkt, int map));
+ int usbhs_pipe_get_maxpacket(struct usbhs_pipe *pipe);
+ void usbhs_pipe_clear(struct usbhs_pipe *pipe);
++void usbhs_pipe_clear_without_sequence(struct usbhs_pipe *pipe,
++				       int needs_bfre, int bfre_enable);
+ int usbhs_pipe_is_accessible(struct usbhs_pipe *pipe);
+ void usbhs_pipe_enable(struct usbhs_pipe *pipe);
+ void usbhs_pipe_disable(struct usbhs_pipe *pipe);
+-- 
+2.19.0
+
diff --git a/patches/0509-usb-renesas_usbhs-use-PIPEnCLR.ACLRM-instead-of-C-Dn.patch b/patches/0509-usb-renesas_usbhs-use-PIPEnCLR.ACLRM-instead-of-C-Dn.patch
new file mode 100644
index 00000000000000..5b0d2fd2530b0d
--- /dev/null
+++ b/patches/0509-usb-renesas_usbhs-use-PIPEnCLR.ACLRM-instead-of-C-Dn.patch
@@ -0,0 +1,49 @@
+From f3b2915e6892324ec0c06f7ed0bba9a41ba23bd1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 6 Dec 2017 17:18:33 +0900
+Subject: [PATCH 0509/1795] usb: renesas_usbhs: use PIPEnCLR.ACLRM instead of
+ {C,Dn}FIFOCTR.BCLR in usbhs_pkt_pop()
+
+This patch uses usbhs_pipe_clear_without_sequence() instead of
+usbhsf_fifo_clear() because usbhsf_fifo_clear() may not clear the pipe
+buffer completely. This patch also changes the clearing condition from
+DMA only to both DMA and PIO.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 5785e87a3db80a033c16e19de7741bc444f50f1a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/fifo.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
+index d967908cda7c..39fa2fc1b8b7 100644
+--- a/drivers/usb/renesas_usbhs/fifo.c
++++ b/drivers/usb/renesas_usbhs/fifo.c
+@@ -94,8 +94,6 @@ static struct usbhs_pkt *__usbhsf_pkt_get(struct usbhs_pipe *pipe)
+ 	return list_first_entry_or_null(&pipe->list, struct usbhs_pkt, node);
+ }
+ 
+-static void usbhsf_fifo_clear(struct usbhs_pipe *pipe,
+-			      struct usbhs_fifo *fifo);
+ static void usbhsf_fifo_unselect(struct usbhs_pipe *pipe,
+ 				 struct usbhs_fifo *fifo);
+ static struct dma_chan *usbhsf_dma_chan_get(struct usbhs_fifo *fifo,
+@@ -124,10 +122,11 @@ struct usbhs_pkt *usbhs_pkt_pop(struct usbhs_pipe *pipe, struct usbhs_pkt *pkt)
+ 			chan = usbhsf_dma_chan_get(fifo, pkt);
+ 		if (chan) {
+ 			dmaengine_terminate_all(chan);
+-			usbhsf_fifo_clear(pipe, fifo);
+ 			usbhsf_dma_unmap(pkt);
+ 		}
+ 
++		usbhs_pipe_clear_without_sequence(pipe, 0, 0);
++
+ 		__usbhsf_pkt_del(pkt);
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0510-usb-renesas_usbhs-Add-a-function-to-write-the-UGCTRL.patch b/patches/0510-usb-renesas_usbhs-Add-a-function-to-write-the-UGCTRL.patch
new file mode 100644
index 00000000000000..90bf4def0360f8
--- /dev/null
+++ b/patches/0510-usb-renesas_usbhs-Add-a-function-to-write-the-UGCTRL.patch
@@ -0,0 +1,55 @@
+From 8389168f97247173c7e981c000ec221c0b62aa2a Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Dec 2017 15:46:57 +0900
+Subject: [PATCH 0510/1795] usb: renesas_usbhs: Add a function to write the
+ UGCTRL2 register
+
+To cleanup the code, this patch adds a function to write the UGCTRL2
+register.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 05e37b626f7911865ec1f7c19864d1e1edc9f1d0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/rcar3.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index c929d296c77b..50e5fb55c8a0 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -44,13 +44,17 @@ static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
+ 	return ioread32(priv->base + reg);
+ }
+ 
++static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
++{
++	usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
++}
++
+ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
+ 				void __iomem *base, int enable)
+ {
+ 	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+ 
+-	usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG |
+-		      UGCTRL2_VBUSSEL);
++	usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
+ 
+ 	if (enable) {
+ 		usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
+@@ -73,8 +77,7 @@ static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
+ 
+ 	if (enable) {
+ 		usbhs_write32(priv, UGCTRL, 0);	/* release PLLRESET */
+-		usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 |
+-			      UGCTRL2_USB0SEL_HSUSB);
++		usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
+ 
+ 		usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
+ 		do {
+-- 
+2.19.0
+
diff --git a/patches/0511-usb-renesas_usbhs-add-a-new-callback-for-extcon-noti.patch b/patches/0511-usb-renesas_usbhs-add-a-new-callback-for-extcon-noti.patch
new file mode 100644
index 00000000000000..4e58b6a9d94518
--- /dev/null
+++ b/patches/0511-usb-renesas_usbhs-add-a-new-callback-for-extcon-noti.patch
@@ -0,0 +1,47 @@
+From aa9b01347908dff34d0537c1f10c3840b26a27a3 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Dec 2017 15:46:58 +0900
+Subject: [PATCH 0511/1795] usb: renesas_usbhs: add a new callback for extcon
+ notifier
+
+To set host/peripheral mode by using extcon notifier, this patch
+adds a new callback as "notifier" in renesas_usbhs_platform_callback.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit f16323fdbd40a4062fb6c89d563e26d93854caa0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/usb/renesas_usbhs.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h
+index 67102f3d59d4..9482735d4ca5 100644
+--- a/include/linux/usb/renesas_usbhs.h
++++ b/include/linux/usb/renesas_usbhs.h
+@@ -17,6 +17,7 @@
+  */
+ #ifndef RENESAS_USB_H
+ #define RENESAS_USB_H
++#include <linux/notifier.h>
+ #include <linux/platform_device.h>
+ #include <linux/usb/ch9.h>
+ 
+@@ -98,6 +99,13 @@ struct renesas_usbhs_platform_callback {
+ 	 * VBUS control is needed for Host
+ 	 */
+ 	int (*set_vbus)(struct platform_device *pdev, int enable);
++
++	/*
++	 * option:
++	 * extcon notifier to set host/peripheral mode.
++	 */
++	int (*notifier)(struct notifier_block *nb, unsigned long event,
++			void *data);
+ };
+ 
+ /*
+-- 
+2.19.0
+
diff --git a/patches/0512-usb-renesas_usbhs-set-the-mode-by-using-extcon-state.patch b/patches/0512-usb-renesas_usbhs-set-the-mode-by-using-extcon-state.patch
new file mode 100644
index 00000000000000..8fd61c103b5853
--- /dev/null
+++ b/patches/0512-usb-renesas_usbhs-set-the-mode-by-using-extcon-state.patch
@@ -0,0 +1,67 @@
+From 40476e5e83bb2c993932c9a5cf0ed570bf43c6c1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Dec 2017 15:46:59 +0900
+Subject: [PATCH 0512/1795] usb: renesas_usbhs: set the mode by using extcon
+ state for non-otg channel
+
+The usbhs_rcar3_power_and_pll_ctrl() will be used by non-otg channel
+(e.g. R-Car D3) and the previous code has hardcoded as peripheral mode.
+So, this patch sets the mode by using extcon state.
+If the channel doesn't get any extcon devices, this driver's behavior
+is the same as before.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit cd14247d5c14b9b20bb3d3dfcaa899ca22c8dccc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/rcar3.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index 50e5fb55c8a0..b9a8453a5e68 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -27,6 +27,7 @@
+  * Remarks: bit[31:11] and bit[9:6] should be 0
+  */
+ #define UGCTRL2_RESERVED_3	0x00000001	/* bit[3:0] should be B'0001 */
++#define UGCTRL2_USB0SEL_EHCI	0x00000010
+ #define UGCTRL2_USB0SEL_HSUSB	0x00000020
+ #define UGCTRL2_USB0SEL_OTG	0x00000030
+ #define UGCTRL2_VBUSSEL		0x00000400
+@@ -49,6 +50,14 @@ static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
+ 	usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
+ }
+ 
++static void usbhs_rcar3_set_usbsel(struct usbhs_priv *priv, bool ehci)
++{
++	if (ehci)
++		usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_EHCI);
++	else
++		usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
++}
++
+ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
+ 				void __iomem *base, int enable)
+ {
+@@ -74,10 +83,14 @@ static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
+ 	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+ 	u32 val;
+ 	int timeout = 1000;
++	bool is_host = false;
+ 
+ 	if (enable) {
+ 		usbhs_write32(priv, UGCTRL, 0);	/* release PLLRESET */
+-		usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
++		if (priv->edev)
++			is_host = extcon_get_state(priv->edev, EXTCON_USB_HOST);
++
++		usbhs_rcar3_set_usbsel(priv, is_host);
+ 
+ 		usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
+ 		do {
+-- 
+2.19.0
+
diff --git a/patches/0513-usb-renesas_usbhs-add-extcon-notifier-to-set-mode-fo.patch b/patches/0513-usb-renesas_usbhs-add-extcon-notifier-to-set-mode-fo.patch
new file mode 100644
index 00000000000000..64b3884d016e04
--- /dev/null
+++ b/patches/0513-usb-renesas_usbhs-add-extcon-notifier-to-set-mode-fo.patch
@@ -0,0 +1,92 @@
+From b5f1bef8e829bebe2eecd8e73870e9883ce4878b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 13 Dec 2017 15:47:00 +0900
+Subject: [PATCH 0513/1795] usb: renesas_usbhs: add extcon notifier to set mode
+ for non-otg channel
+
+This patch adds extcon notifier callback to set the mode of
+host/peripheral by using extcon state (e.g phy-rcar-gen3-usb2) for
+non-otg channel (e.g. R-Car D3).
+
+[Fengguang Wu: fixed sparse warning]
+
+Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+
+usb: renesas_usbhs: usbhs_rcar3_notifier() can be static
+
+Fixes: 3a7cce26122e ("usb: renesas_usbhs: add extcon notifier to set mode for non-otg channel")
+Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 8ada211d0383b72878582bd312b984a9eae62b30)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.c |  9 +++++++++
+ drivers/usb/renesas_usbhs/common.h |  1 +
+ drivers/usb/renesas_usbhs/rcar3.c  | 11 +++++++++++
+ 3 files changed, 21 insertions(+)
+
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index 56079bb6759a..c5289b3ecf8d 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -581,6 +581,15 @@ static int usbhs_probe(struct platform_device *pdev)
+ 		break;
+ 	case USBHS_TYPE_RCAR_GEN3_WITH_PLL:
+ 		priv->pfunc = usbhs_rcar3_with_pll_ops;
++		if (!IS_ERR_OR_NULL(priv->edev)) {
++			priv->nb.notifier_call = priv->pfunc.notifier;
++			ret = devm_extcon_register_notifier(&pdev->dev,
++							    priv->edev,
++							    EXTCON_USB_HOST,
++							    &priv->nb);
++			if (ret < 0)
++				dev_err(&pdev->dev, "no notifier registered\n");
++		}
+ 		break;
+ 	default:
+ 		if (!info->platform_callback.get_id) {
+diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
+index 64797784a6df..c9747f064601 100644
+--- a/drivers/usb/renesas_usbhs/common.h
++++ b/drivers/usb/renesas_usbhs/common.h
+@@ -249,6 +249,7 @@ struct usbhs_priv {
+ 	struct platform_device *pdev;
+ 
+ 	struct extcon_dev *edev;
++	struct notifier_block nb;
+ 
+ 	spinlock_t		lock;
+ 
+diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c
+index b9a8453a5e68..d0ea4ff89622 100644
+--- a/drivers/usb/renesas_usbhs/rcar3.c
++++ b/drivers/usb/renesas_usbhs/rcar3.c
+@@ -112,6 +112,16 @@ static int usbhs_rcar3_get_id(struct platform_device *pdev)
+ 	return USBHS_GADGET;
+ }
+ 
++static int usbhs_rcar3_notifier(struct notifier_block *nb, unsigned long event,
++				void *data)
++{
++	struct usbhs_priv *priv = container_of(nb, struct usbhs_priv, nb);
++
++	usbhs_rcar3_set_usbsel(priv, !!event);
++
++	return NOTIFY_DONE;
++}
++
+ const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
+ 	.power_ctrl = usbhs_rcar3_power_ctrl,
+ 	.get_id = usbhs_rcar3_get_id,
+@@ -120,4 +130,5 @@ const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
+ const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = {
+ 	.power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
+ 	.get_id = usbhs_rcar3_get_id,
++	.notifier = usbhs_rcar3_notifier,
+ };
+-- 
+2.19.0
+
diff --git a/patches/0514-usb-renesas_usbhs-Add-support-for-RZ-A1.patch b/patches/0514-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
new file mode 100644
index 00000000000000..f21f09b73ba790
--- /dev/null
+++ b/patches/0514-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
@@ -0,0 +1,195 @@
+From 473415493f0586afb96f8fa08a312d33731bea47 Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Mon, 8 Jan 2018 07:30:53 -0500
+Subject: [PATCH 0514/1795] usb: renesas_usbhs: Add support for RZ/A1
+
+This patch adds the capability to support RZ/A1 SoCs.
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit aec2927b5944df70bca4bdeea6c4e7c3195dc37a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/Makefile |  2 +-
+ drivers/usb/renesas_usbhs/common.c | 13 ++++++++
+ drivers/usb/renesas_usbhs/common.h |  6 ++++
+ drivers/usb/renesas_usbhs/rza.c    | 52 ++++++++++++++++++++++++++++++
+ drivers/usb/renesas_usbhs/rza.h    |  4 +++
+ include/linux/usb/renesas_usbhs.h  |  1 +
+ 6 files changed, 77 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/usb/renesas_usbhs/rza.c
+ create mode 100644 drivers/usb/renesas_usbhs/rza.h
+
+diff --git a/drivers/usb/renesas_usbhs/Makefile b/drivers/usb/renesas_usbhs/Makefile
+index fac147a3ad23..5c5b51bb48ef 100644
+--- a/drivers/usb/renesas_usbhs/Makefile
++++ b/drivers/usb/renesas_usbhs/Makefile
+@@ -5,7 +5,7 @@
+ 
+ obj-$(CONFIG_USB_RENESAS_USBHS)	+= renesas_usbhs.o
+ 
+-renesas_usbhs-y			:= common.o mod.o pipe.o fifo.o rcar2.o rcar3.o
++renesas_usbhs-y			:= common.o mod.o pipe.o fifo.o rcar2.o rcar3.o rza.o
+ 
+ ifneq ($(CONFIG_USB_RENESAS_USBHS_HCD),)
+ 	renesas_usbhs-y		+= mod_host.o
+diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
+index c5289b3ecf8d..4310df46639d 100644
+--- a/drivers/usb/renesas_usbhs/common.c
++++ b/drivers/usb/renesas_usbhs/common.c
+@@ -17,6 +17,7 @@
+ #include "common.h"
+ #include "rcar2.h"
+ #include "rcar3.h"
++#include "rza.h"
+ 
+ /*
+  *		image of renesas_usbhs
+@@ -488,6 +489,10 @@ static const struct of_device_id usbhs_of_match[] = {
+ 		.compatible = "renesas,rcar-gen3-usbhs",
+ 		.data = (void *)USBHS_TYPE_RCAR_GEN3,
+ 	},
++	{
++		.compatible = "renesas,rza1-usbhs",
++		.data = (void *)USBHS_TYPE_RZA1,
++	},
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, usbhs_of_match);
+@@ -520,6 +525,11 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
+ 		dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+ 	}
+ 
++	if (dparam->type == USBHS_TYPE_RZA1) {
++		dparam->pipe_configs = usbhsc_new_pipe;
++		dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
++	}
++
+ 	return info;
+ }
+ 
+@@ -591,6 +601,9 @@ static int usbhs_probe(struct platform_device *pdev)
+ 				dev_err(&pdev->dev, "no notifier registered\n");
+ 		}
+ 		break;
++	case USBHS_TYPE_RZA1:
++		priv->pfunc = usbhs_rza1_ops;
++		break;
+ 	default:
+ 		if (!info->platform_callback.get_id) {
+ 			dev_err(&pdev->dev, "no platform callbacks");
+diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
+index c9747f064601..f619afeae2b8 100644
+--- a/drivers/usb/renesas_usbhs/common.h
++++ b/drivers/usb/renesas_usbhs/common.h
+@@ -98,6 +98,7 @@ struct usbhs_priv;
+ #define D2FIFOCTR	0x00F2	/* for R-Car Gen2 */
+ #define D3FIFOSEL	0x00F4	/* for R-Car Gen2 */
+ #define D3FIFOCTR	0x00F6	/* for R-Car Gen2 */
++#define SUSPMODE	0x0102	/* for RZ/A */
+ 
+ /* SYSCFG */
+ #define SCKE	(1 << 10)	/* USB Module Clock Enable */
+@@ -106,6 +107,8 @@ struct usbhs_priv;
+ #define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
+ #define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
+ #define USBE	(1 << 0)	/* USB Module Operation Enable */
++#define UCKSEL	(1 << 2)	/* Clock Select for RZ/A1 */
++#define UPLLE	(1 << 1)	/* USB PLL Enable for RZ/A1 */
+ 
+ /* DVSTCTR */
+ #define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
+@@ -233,6 +236,9 @@ struct usbhs_priv;
+ #define USBSPD_SPEED_FULL	0x2
+ #define USBSPD_SPEED_HIGH	0x3
+ 
++/* SUSPMODE */
++#define SUSPM		(1 << 14)	/* SuspendM Control */
++
+ /*
+  *		struct
+  */
+diff --git a/drivers/usb/renesas_usbhs/rza.c b/drivers/usb/renesas_usbhs/rza.c
+new file mode 100644
+index 000000000000..5b287257ec11
+--- /dev/null
++++ b/drivers/usb/renesas_usbhs/rza.c
+@@ -0,0 +1,52 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Renesas USB driver RZ/A initialization and power control
++ *
++ * Copyright (C) 2018 Chris Brandt
++ * Copyright (C) 2018 Renesas Electronics Corporation
++ */
++
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/of_device.h>
++#include "common.h"
++#include "rza.h"
++
++static int usbhs_rza1_hardware_init(struct platform_device *pdev)
++{
++	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
++	struct device_node *usb_x1_clk, *extal_clk;
++	u32 freq_usb = 0, freq_extal = 0;
++
++	/* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
++	usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
++	extal_clk = of_find_node_by_name(NULL, "extal");
++	of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
++	of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
++	if (freq_usb == 0) {
++		if (freq_extal == 12000000) {
++			/* Select 12MHz XTAL */
++			usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
++		} else {
++			dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
++			return -EIO;
++		}
++	}
++
++	/* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
++	usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
++	udelay(1000);
++	usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
++
++	return 0;
++}
++
++static int usbhs_rza_get_id(struct platform_device *pdev)
++{
++	return USBHS_GADGET;
++}
++
++const struct renesas_usbhs_platform_callback usbhs_rza1_ops = {
++	.hardware_init = usbhs_rza1_hardware_init,
++	.get_id = usbhs_rza_get_id,
++};
+diff --git a/drivers/usb/renesas_usbhs/rza.h b/drivers/usb/renesas_usbhs/rza.h
+new file mode 100644
+index 000000000000..ca917ca54f6d
+--- /dev/null
++++ b/drivers/usb/renesas_usbhs/rza.h
+@@ -0,0 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
++#include "common.h"
++
++extern const struct renesas_usbhs_platform_callback usbhs_rza1_ops;
+diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h
+index 9482735d4ca5..53924f8e840c 100644
+--- a/include/linux/usb/renesas_usbhs.h
++++ b/include/linux/usb/renesas_usbhs.h
+@@ -195,6 +195,7 @@ struct renesas_usbhs_driver_param {
+ #define USBHS_TYPE_RCAR_GEN2		1
+ #define USBHS_TYPE_RCAR_GEN3		2
+ #define USBHS_TYPE_RCAR_GEN3_WITH_PLL	3
++#define USBHS_TYPE_RZA1			4
+ 
+ /*
+  * option:
+-- 
+2.19.0
+
diff --git a/patches/0515-dt-bindings-usb-renesas_usbhs-Add-support-for-RZ-A1.patch b/patches/0515-dt-bindings-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
new file mode 100644
index 00000000000000..3d0469d4a80228
--- /dev/null
+++ b/patches/0515-dt-bindings-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
@@ -0,0 +1,37 @@
+From f5c1ff427a0bb6dab935a06d9cb787771e9c4499 Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Mon, 8 Jan 2018 07:30:54 -0500
+Subject: [PATCH 0515/1795] dt-bindings: usb: renesas_usbhs: Add support for
+ RZ/A1
+
+Document support for RZ/A1 SoCs
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit e7053e6c29f6ca116f6378c895805ad3f44c77aa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+index 47394ab788e3..d060172f1529 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+@@ -13,8 +13,10 @@ Required properties:
+ 	- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
+ 	- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
+ 	- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
++	- "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
+ 	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
+ 	- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
++	- "renesas,rza1-usbhs" for RZ/A1 compatible device
+ 
+ 	When compatible with the generic version, nodes must list the
+ 	SoC-specific version corresponding to the platform first followed
+-- 
+2.19.0
+
diff --git a/patches/0516-usb-renesas_usbhs-add-binding-for-r8a77965.patch b/patches/0516-usb-renesas_usbhs-add-binding-for-r8a77965.patch
new file mode 100644
index 00000000000000..fbe7f1f9c703de
--- /dev/null
+++ b/patches/0516-usb-renesas_usbhs-add-binding-for-r8a77965.patch
@@ -0,0 +1,31 @@
+From 50a25ced16c378f1c12667074d103910618c68e3 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 27 Feb 2018 17:16:02 +0900
+Subject: [PATCH 0516/1795] usb: renesas_usbhs: add binding for r8a77965
+
+This patch adds binding for r8a77965 (R-Car M3-N).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 54f02945f703404cdf17c9618316b3d3387fa072)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+index d060172f1529..43960faf5a88 100644
+--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
++++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+@@ -12,6 +12,7 @@ Required properties:
+ 	- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
+ 	- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
+ 	- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
++	- "renesas,usbhs-r8a77965" for r8a77965 (R-Car M3-N) compatible device
+ 	- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
+ 	- "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
+ 	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
+-- 
+2.19.0
+
diff --git a/patches/0517-v4l-vsp1-Start-and-stop-DRM-pipeline-independently-o.patch b/patches/0517-v4l-vsp1-Start-and-stop-DRM-pipeline-independently-o.patch
new file mode 100644
index 00000000000000..3ba56b81c448ed
--- /dev/null
+++ b/patches/0517-v4l-vsp1-Start-and-stop-DRM-pipeline-independently-o.patch
@@ -0,0 +1,95 @@
+From c062161d4e59f646a0a5ca2ef38022fe89a693c8 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 Aug 2017 14:20:11 +0300
+Subject: [PATCH 0517/1795] v4l: vsp1: Start and stop DRM pipeline
+ independently of planes
+
+The KMS API supports enabling a CRTC without any plane. To enable that
+use case, we need to start the pipeline when configuring the LIF,
+instead of when enabling the first plane.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit dd286a531461748ff1b1b3f1d7255389a131ed27)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 37 +++++++++++++++++++-------
+ 1 file changed, 27 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index d3cd57f6ba52..ac85942162c1 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -84,8 +84,12 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_drm_pipeline *drm_pipe;
+ 	struct vsp1_pipeline *pipe;
+ 	struct vsp1_bru *bru;
++	struct vsp1_entity *entity;
++	struct vsp1_entity *next;
++	struct vsp1_dl_list *dl;
+ 	struct v4l2_subdev_format format;
+ 	const char *bru_name;
++	unsigned long flags;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -250,6 +254,29 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
+ 	vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
+ 
++	/* Configure all entities in the pipeline. */
++	dl = vsp1_dl_list_get(pipe->output->dlm);
++
++	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
++		vsp1_entity_route_setup(entity, pipe, dl);
++
++		if (entity->ops->configure) {
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_INIT);
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_RUNTIME);
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_PARTITION);
++		}
++	}
++
++	vsp1_dl_list_commit(dl);
++
++	/* Start the pipeline. */
++	spin_lock_irqsave(&pipe->irqlock, flags);
++	vsp1_pipeline_run(pipe);
++	spin_unlock_irqrestore(&pipe->irqlock, flags);
++
+ 	dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
+ 
+ 	return 0;
+@@ -488,7 +515,6 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 	struct vsp1_entity *next;
+ 	struct vsp1_dl_list *dl;
+ 	const char *bru_name;
+-	unsigned long flags;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -579,15 +605,6 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 	}
+ 
+ 	vsp1_dl_list_commit(dl);
+-
+-	/* Start or stop the pipeline if needed. */
+-	if (!drm_pipe->enabled && pipe->num_inputs) {
+-		spin_lock_irqsave(&pipe->irqlock, flags);
+-		vsp1_pipeline_run(pipe);
+-		spin_unlock_irqrestore(&pipe->irqlock, flags);
+-	} else if (drm_pipe->enabled && !pipe->num_inputs) {
+-		vsp1_pipeline_stop(pipe);
+-	}
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0518-dt-bindings-watchdog-renesas-wdt-Add-support-for-the.patch b/patches/0518-dt-bindings-watchdog-renesas-wdt-Add-support-for-the.patch
new file mode 100644
index 00000000000000..f4680975057d17
--- /dev/null
+++ b/patches/0518-dt-bindings-watchdog-renesas-wdt-Add-support-for-the.patch
@@ -0,0 +1,43 @@
+From 54cff5ae226ab68f8f61901a6da87ef37b29ab85 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 16:43:19 +0100
+Subject: [PATCH 0518/1795] dt-bindings: watchdog: renesas-wdt: Add support for
+ the r8a77970 wdt
+
+Document support for the Watchdog Timer (WDT) Controller in the Renesas
+R-Car V3M (r8a77970) SoC.  Restore sort order while at it.
+
+No driver update is needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+(cherry picked from commit c94ad30add4e741ab260874e898a6448cdd4ff30)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/watchdog/renesas-wdt.txt | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+index bf6d1ca58af7..74b2f03c1515 100644
+--- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
++++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+@@ -4,10 +4,11 @@ Required properties:
+ - compatible : Should be "renesas,<soctype>-wdt", and
+ 	       "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback.
+ 	       Examples with soctypes are:
++	         - "renesas,r7s72100-wdt" (RZ/A1)
+ 	         - "renesas,r8a7795-wdt" (R-Car H3)
+ 	         - "renesas,r8a7796-wdt" (R-Car M3-W)
++	         - "renesas,r8a77970-wdt" (R-Car V3M)
+ 	         - "renesas,r8a77995-wdt" (R-Car D3)
+-	         - "renesas,r7s72100-wdt" (RZ/A1)
+ 
+   When compatible with the generic version, nodes must list the SoC-specific
+   version corresponding to the platform first, followed by the generic
+-- 
+2.19.0
+
diff --git a/patches/0519-usb-xhci-remove-unused-variable-last_freed_endpoint.patch b/patches/0519-usb-xhci-remove-unused-variable-last_freed_endpoint.patch
new file mode 100644
index 00000000000000..216ee23ca9bc36
--- /dev/null
+++ b/patches/0519-usb-xhci-remove-unused-variable-last_freed_endpoint.patch
@@ -0,0 +1,50 @@
+From e8e404ddb3c26fb9fa8279226b962662ddf1d04a Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Fri, 8 Dec 2017 17:59:02 +0200
+Subject: [PATCH 0519/1795] usb: xhci: remove unused variable
+ last_freed_endpoint
+
+Fix the build warning about variable 'last_freed_endpoint'
+set but not used [-Wunused-but-set-variable]
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 78a0db2a61b0f59a2faa090df75fe722f25d27f1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 05d45079a259..39e263780383 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3405,7 +3405,6 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
+ 	unsigned int slot_id;
+ 	struct xhci_virt_device *virt_dev;
+ 	struct xhci_command *reset_device_cmd;
+-	int last_freed_endpoint;
+ 	struct xhci_slot_ctx *slot_ctx;
+ 	int old_active_eps = 0;
+ 
+@@ -3520,7 +3519,6 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
+ 	}
+ 
+ 	/* Everything but endpoint 0 is disabled, so free the rings. */
+-	last_freed_endpoint = 1;
+ 	for (i = 1; i < 31; i++) {
+ 		struct xhci_virt_ep *ep = &virt_dev->eps[i];
+ 
+@@ -3535,7 +3533,6 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
+ 		if (ep->ring) {
+ 			xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
+ 			xhci_free_endpoint_ring(xhci, virt_dev, i);
+-			last_freed_endpoint = i;
+ 		}
+ 		if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
+ 			xhci_drop_ep_from_interval_table(xhci,
+-- 
+2.19.0
+
diff --git a/patches/0520-usb-xhci-remove-unused-variable-ep.patch b/patches/0520-usb-xhci-remove-unused-variable-ep.patch
new file mode 100644
index 00000000000000..fa46c6f7fe8fe1
--- /dev/null
+++ b/patches/0520-usb-xhci-remove-unused-variable-ep.patch
@@ -0,0 +1,37 @@
+From d3c04830368ccc587bfb7cf400b9f8811d56deee Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Fri, 8 Dec 2017 17:59:03 +0200
+Subject: [PATCH 0520/1795] usb: xhci: remove unused variable ep
+
+Fix the build warning: variable 'ep' set but not used
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit bed53019d9d811e06203914ef39cea44bfdad74a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 39e263780383..0653680e62a8 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -2880,12 +2880,10 @@ void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
+ 			       unsigned int stream_id, struct xhci_td *td)
+ {
+ 	struct xhci_dequeue_state deq_state;
+-	struct xhci_virt_ep *ep;
+ 	struct usb_device *udev = td->urb->dev;
+ 
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
+ 			"Cleaning up stalled endpoint ring");
+-	ep = &xhci->devs[udev->slot_id]->eps[ep_index];
+ 	/* We need to move the HW's dequeue pointer past this TD,
+ 	 * or it will attempt to resend it on the next doorbell ring.
+ 	 */
+-- 
+2.19.0
+
diff --git a/patches/0521-usb-xhci-remove-unused-variable-urb_priv.patch b/patches/0521-usb-xhci-remove-unused-variable-urb_priv.patch
new file mode 100644
index 00000000000000..f0ded6313670d6
--- /dev/null
+++ b/patches/0521-usb-xhci-remove-unused-variable-urb_priv.patch
@@ -0,0 +1,37 @@
+From 836db5f3510e8bbd7816b21f7a987d5881176167 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Fri, 8 Dec 2017 17:59:04 +0200
+Subject: [PATCH 0521/1795] usb: xhci: remove unused variable urb_priv
+
+Fix the build warning: variable 'urb_priv' set but not used
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ce5b2a6857cc674b1a8ebf9c4bce5851a84991ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index c5cbc685c691..01720b89ed96 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1878,12 +1878,10 @@ int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
+ static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
+ 		struct xhci_ring *ep_ring, int *status)
+ {
+-	struct urb_priv	*urb_priv;
+ 	struct urb *urb = NULL;
+ 
+ 	/* Clean up the endpoint's TD list */
+ 	urb = td->urb;
+-	urb_priv = urb->hcpriv;
+ 
+ 	/* if a bounce buffer was used to align this td then unmap it */
+ 	xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
+-- 
+2.19.0
+
diff --git a/patches/0522-usb-xhci-remove-unused-variable-ep_ring.patch b/patches/0522-usb-xhci-remove-unused-variable-ep_ring.patch
new file mode 100644
index 00000000000000..a4dfe8ca32f310
--- /dev/null
+++ b/patches/0522-usb-xhci-remove-unused-variable-ep_ring.patch
@@ -0,0 +1,42 @@
+From 6746cf35999aca051c3bc280ce8a738d7fc62a8a Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Fri, 8 Dec 2017 17:59:05 +0200
+Subject: [PATCH 0522/1795] usb: xhci: remove unused variable ep_ring
+
+Fix the build warning about variable 'ep_ring' set but not used
+
+[Minor commit message change -Mathias]
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+(cherry picked from commit 58e8a4dad3c06f568bbde585d04ae84b47ddba02)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 01720b89ed96..2ae63f0bcc14 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1992,7 +1992,6 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 	struct xhci_virt_ep *ep, int *status)
+ {
+ 	struct xhci_virt_device *xdev;
+-	struct xhci_ring *ep_ring;
+ 	unsigned int slot_id;
+ 	int ep_index;
+ 	struct xhci_ep_ctx *ep_ctx;
+@@ -2004,7 +2003,6 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
+ 	xdev = xhci->devs[slot_id];
+ 	ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
+-	ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
+ 	ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
+ 	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
+ 	requested = td->urb->transfer_buffer_length;
+-- 
+2.19.0
+
diff --git a/patches/0523-dt-bindings-usb-xhci-Document-r8a7743-support.patch b/patches/0523-dt-bindings-usb-xhci-Document-r8a7743-support.patch
new file mode 100644
index 00000000000000..6a26c02fa6914c
--- /dev/null
+++ b/patches/0523-dt-bindings-usb-xhci-Document-r8a7743-support.patch
@@ -0,0 +1,44 @@
+From 58303bd5e5ff921b68579e945e6e3c84216ca6a6 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Fri, 8 Dec 2017 17:59:06 +0200
+Subject: [PATCH 0523/1795] dt-bindings: usb-xhci: Document r8a7743 support
+
+Document r8a7743 xhci support. The driver will use the fallback
+compatible string "renesas,rcar-gen2-xhci", therefore no driver
+change is needed.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5fd29937dec4b64aa91a3207742cd8c720cd0595)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/usb/usb-xhci.txt | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+index 4143ef222540..ff4747219638 100644
+--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+@@ -7,13 +7,15 @@ Required properties:
+     - "marvell,armada3700-xhci" for Armada 37xx SoCs
+     - "marvell,armada-375-xhci" for Armada 375 SoCs
+     - "marvell,armada-380-xhci" for Armada 38x SoCs
++    - "renesas,xhci-r8a7743" for r8a7743 SoC
+     - "renesas,xhci-r8a7790" for r8a7790 SoC
+     - "renesas,xhci-r8a7791" for r8a7791 SoC
+     - "renesas,xhci-r8a7793" for r8a7793 SoC
+     - "renesas,xhci-r8a7795" for r8a7795 SoC
+     - "renesas,xhci-r8a7796" for r8a7796 SoC
+     - "renesas,xhci-r8a77965" for r8a77965 SoC
+-    - "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 compatible device
++    - "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible
++      device
+     - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device
+     - "xhci-platform" (deprecated)
+ 
+-- 
+2.19.0
+
diff --git a/patches/0524-xhci-add-helper-to-allocate-command-with-input-conte.patch b/patches/0524-xhci-add-helper-to-allocate-command-with-input-conte.patch
new file mode 100644
index 00000000000000..0dbcd9628bd0e5
--- /dev/null
+++ b/patches/0524-xhci-add-helper-to-allocate-command-with-input-conte.patch
@@ -0,0 +1,110 @@
+From 0bb78c1d7838a1fdd52134989d162212dc291b3a Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:07 +0200
+Subject: [PATCH 0524/1795] xhci: add helper to allocate command with input
+ context
+
+Add a xhci_alloc_command_with_ctx() helper to get rid of
+one of the boolean parameters telling if a context should
+be allocated with the command.
+
+No functional changes, improves core readability
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 14d49b7a0bfe76ef694a61e0c7b5f091ea780b91)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-mem.c | 24 ++++++++++++++++++++++--
+ drivers/usb/host/xhci.c     |  4 ++--
+ drivers/usb/host/xhci.h     |  2 ++
+ 3 files changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index c44f09f17f5e..2d91faf3f128 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -650,7 +650,7 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ 
+ 	/* Allocate everything needed to free the stream rings later */
+ 	stream_info->free_streams_command =
+-		xhci_alloc_command(xhci, true, true, mem_flags);
++		xhci_alloc_command_with_ctx(xhci, true, mem_flags);
+ 	if (!stream_info->free_streams_command)
+ 		goto cleanup_ctx;
+ 
+@@ -1752,6 +1752,26 @@ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+ 	return command;
+ }
+ 
++struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
++		bool allocate_completion, gfp_t mem_flags)
++{
++	struct xhci_command *command;
++
++	command = xhci_alloc_command(xhci, false, allocate_completion,
++				     mem_flags);
++	if (!command)
++		return NULL;
++
++	command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
++						   mem_flags);
++	if (!command->in_ctx) {
++		kfree(command->completion);
++		kfree(command);
++		return NULL;
++	}
++	return command;
++}
++
+ void xhci_urb_free_priv(struct urb_priv *urb_priv)
+ {
+ 	kfree(urb_priv);
+@@ -2425,7 +2445,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
+ 	xhci_dbg_cmd_ptrs(xhci);
+ 
+-	xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
++	xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags);
+ 	if (!xhci->lpm_command)
+ 		goto fail;
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 0653680e62a8..47f77085d5ce 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3132,7 +3132,7 @@ static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
+ 		return -ENOSYS;
+ 	}
+ 
+-	config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
++	config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
+ 	if (!config_cmd)
+ 		return -ENOMEM;
+ 
+@@ -4718,7 +4718,7 @@ static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
+ 		return -EINVAL;
+ 	}
+ 
+-	config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
++	config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
+ 	if (!config_cmd)
+ 		return -ENOMEM;
+ 
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 5f1fe671b694..e3f8ca79867c 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2000,6 +2000,8 @@ struct xhci_ring *xhci_stream_id_to_ring(
+ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+ 		bool allocate_in_ctx, bool allocate_completion,
+ 		gfp_t mem_flags);
++struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
++		bool allocate_completion, gfp_t mem_flags);
+ void xhci_urb_free_priv(struct urb_priv *urb_priv);
+ void xhci_free_command(struct xhci_hcd *xhci,
+ 		struct xhci_command *command);
+-- 
+2.19.0
+
diff --git a/patches/0525-xhci-remove-unnecessary-boolean-parameter-from-xhci_.patch b/patches/0525-xhci-remove-unnecessary-boolean-parameter-from-xhci_.patch
new file mode 100644
index 00000000000000..a332e7340854a3
--- /dev/null
+++ b/patches/0525-xhci-remove-unnecessary-boolean-parameter-from-xhci_.patch
@@ -0,0 +1,217 @@
+From c64d1747ddeecbec978a19f2d1b520ca8483a127 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:08 +0200
+Subject: [PATCH 0525/1795] xhci: remove unnecessary boolean parameter from
+ xhci_alloc_command
+
+commands with input contexts are allocated with the
+xhci_alloc_command_with_ctx helper.
+
+No functional changes
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 103afda0e6ac58927bc85dc5a7ebc0f51892f407)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c  |  5 ++---
+ drivers/usb/host/xhci-mem.c  | 17 ++---------------
+ drivers/usb/host/xhci-ring.c |  6 +++---
+ drivers/usb/host/xhci.c      | 16 ++++++++--------
+ drivers/usb/host/xhci.h      |  3 +--
+ 5 files changed, 16 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 0fb3fec94e04..a6ac7c5200fe 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -388,7 +388,7 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
+ 
+ 	trace_xhci_stop_device(virt_dev);
+ 
+-	cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
++	cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
+ 	if (!cmd)
+ 		return -ENOMEM;
+ 
+@@ -404,8 +404,7 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
+ 			if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
+ 				continue;
+ 
+-			command = xhci_alloc_command(xhci, false, false,
+-						     GFP_NOWAIT);
++			command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
+ 			if (!command) {
+ 				spin_unlock_irqrestore(&xhci->lock, flags);
+ 				ret = -ENOMEM;
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 2d91faf3f128..bb104b8d217e 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -1717,8 +1717,7 @@ static void scratchpad_free(struct xhci_hcd *xhci)
+ }
+ 
+ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+-		bool allocate_in_ctx, bool allocate_completion,
+-		gfp_t mem_flags)
++		bool allocate_completion, gfp_t mem_flags)
+ {
+ 	struct xhci_command *command;
+ 
+@@ -1726,21 +1725,10 @@ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+ 	if (!command)
+ 		return NULL;
+ 
+-	if (allocate_in_ctx) {
+-		command->in_ctx =
+-			xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
+-					mem_flags);
+-		if (!command->in_ctx) {
+-			kfree(command);
+-			return NULL;
+-		}
+-	}
+-
+ 	if (allocate_completion) {
+ 		command->completion =
+ 			kzalloc(sizeof(struct completion), mem_flags);
+ 		if (!command->completion) {
+-			xhci_free_container_ctx(xhci, command->in_ctx);
+ 			kfree(command);
+ 			return NULL;
+ 		}
+@@ -1757,8 +1745,7 @@ struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
+ {
+ 	struct xhci_command *command;
+ 
+-	command = xhci_alloc_command(xhci, false, allocate_completion,
+-				     mem_flags);
++	command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
+ 	if (!command)
+ 		return NULL;
+ 
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 2ae63f0bcc14..af079f492a9e 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1141,7 +1141,7 @@ static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
+ 	if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
+ 		struct xhci_command *command;
+ 
+-		command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
++		command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
+ 		if (!command)
+ 			return;
+ 
+@@ -1821,7 +1821,7 @@ static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
+ {
+ 	struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
+ 	struct xhci_command *command;
+-	command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
++	command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
+ 	if (!command)
+ 		return;
+ 
+@@ -4040,7 +4040,7 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
+ 	}
+ 
+ 	/* This function gets called from contexts where it cannot sleep */
+-	cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
++	cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
+ 	if (!cmd)
+ 		return;
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 47f77085d5ce..7dafd44cf1c2 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -610,7 +610,7 @@ int xhci_run(struct usb_hcd *hcd)
+ 	if (xhci->quirks & XHCI_NEC_HOST) {
+ 		struct xhci_command *command;
+ 
+-		command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
++		command = xhci_alloc_command(xhci, false, GFP_KERNEL);
+ 		if (!command)
+ 			return -ENOMEM;
+ 
+@@ -1285,7 +1285,7 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
+ 		 * changes max packet sizes.
+ 		 */
+ 
+-		command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
++		command = xhci_alloc_command(xhci, true, GFP_KERNEL);
+ 		if (!command)
+ 			return -ENOMEM;
+ 
+@@ -1540,7 +1540,7 @@ static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+ 	 * the first cancellation to be handled.
+ 	 */
+ 	if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
+-		command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
++		command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
+ 		if (!command) {
+ 			ret = -ENOMEM;
+ 			goto done;
+@@ -2725,7 +2725,7 @@ static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+ 	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
+ 	virt_dev = xhci->devs[udev->slot_id];
+ 
+-	command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
++	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
+ 	if (!command)
+ 		return -ENOMEM;
+ 
+@@ -3455,7 +3455,7 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
+ 	 * reset as part of error handling, so use GFP_NOIO instead of
+ 	 * GFP_KERNEL.
+ 	 */
+-	reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
++	reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
+ 	if (!reset_device_cmd) {
+ 		xhci_dbg(xhci, "Couldn't allocate command structure.\n");
+ 		return -ENOMEM;
+@@ -3604,7 +3604,7 @@ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
+ 	u32 state;
+ 	int ret = 0;
+ 
+-	command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
++	command = xhci_alloc_command(xhci, false, GFP_KERNEL);
+ 	if (!command)
+ 		return -ENOMEM;
+ 
+@@ -3666,7 +3666,7 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 	int ret, slot_id;
+ 	struct xhci_command *command;
+ 
+-	command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
++	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
+ 	if (!command)
+ 		return 0;
+ 
+@@ -3799,7 +3799,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
+ 		}
+ 	}
+ 
+-	command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
++	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
+ 	if (!command) {
+ 		ret = -ENOMEM;
+ 		goto out;
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index e3f8ca79867c..98c68f76ef44 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1998,8 +1998,7 @@ struct xhci_ring *xhci_stream_id_to_ring(
+ 		unsigned int ep_index,
+ 		unsigned int stream_id);
+ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+-		bool allocate_in_ctx, bool allocate_completion,
+-		gfp_t mem_flags);
++		bool allocate_completion, gfp_t mem_flags);
+ struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
+ 		bool allocate_completion, gfp_t mem_flags);
+ void xhci_urb_free_priv(struct urb_priv *urb_priv);
+-- 
+2.19.0
+
diff --git a/patches/0526-usb-xhci-Make-some-static-functions-global.patch b/patches/0526-usb-xhci-Make-some-static-functions-global.patch
new file mode 100644
index 00000000000000..ea0a9a53da8638
--- /dev/null
+++ b/patches/0526-usb-xhci-Make-some-static-functions-global.patch
@@ -0,0 +1,237 @@
+From de70ba532cc1f377f747ff735dfb14d4811b7ffd Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:09 +0200
+Subject: [PATCH 0526/1795] usb: xhci: Make some static functions global
+
+This patch makes some static functions global to avoid duplications
+in different files. These functions can be used in the implementation
+of xHCI debug capability. There is no functional change.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 67d2ea9fde2aa96f36af0537e4004efb123319fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-mem.c  | 94 +++++++++++++++++++++---------------
+ drivers/usb/host/xhci-ring.c |  4 +-
+ drivers/usb/host/xhci.h      | 16 +++++-
+ 3 files changed, 72 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index bb104b8d217e..7d6b33c89a2e 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -357,7 +357,7 @@ static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
+  * Set the end flag and the cycle toggle bit on the last segment.
+  * See section 4.9.1 and figures 15 and 16.
+  */
+-static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
++struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
+ 		unsigned int num_segs, unsigned int cycle_state,
+ 		enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
+ {
+@@ -454,7 +454,7 @@ int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
+ 	return 0;
+ }
+ 
+-static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
++struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
+ 						    int type, gfp_t flags)
+ {
+ 	struct xhci_container_ctx *ctx;
+@@ -479,7 +479,7 @@ static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci
+ 	return ctx;
+ }
+ 
+-static void xhci_free_container_ctx(struct xhci_hcd *xhci,
++void xhci_free_container_ctx(struct xhci_hcd *xhci,
+ 			     struct xhci_container_ctx *ctx)
+ {
+ 	if (!ctx)
+@@ -1773,21 +1773,61 @@ void xhci_free_command(struct xhci_hcd *xhci,
+ 	kfree(command);
+ }
+ 
++int xhci_alloc_erst(struct xhci_hcd *xhci,
++		    struct xhci_ring *evt_ring,
++		    struct xhci_erst *erst,
++		    gfp_t flags)
++{
++	size_t size;
++	unsigned int val;
++	struct xhci_segment *seg;
++	struct xhci_erst_entry *entry;
++
++	size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs;
++	erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
++					   size,
++					   &erst->erst_dma_addr,
++					   flags);
++	if (!erst->entries)
++		return -ENOMEM;
++
++	memset(erst->entries, 0, size);
++	erst->num_entries = evt_ring->num_segs;
++
++	seg = evt_ring->first_seg;
++	for (val = 0; val < evt_ring->num_segs; val++) {
++		entry = &erst->entries[val];
++		entry->seg_addr = cpu_to_le64(seg->dma);
++		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
++		entry->rsvd = 0;
++		seg = seg->next;
++	}
++
++	return 0;
++}
++
++void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
++{
++	size_t size;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
++
++	size = sizeof(struct xhci_erst_entry) * (erst->num_entries);
++	if (erst->entries)
++		dma_free_coherent(dev, size,
++				erst->entries,
++				erst->erst_dma_addr);
++	erst->entries = NULL;
++}
++
+ void xhci_mem_cleanup(struct xhci_hcd *xhci)
+ {
+ 	struct device	*dev = xhci_to_hcd(xhci)->self.sysdev;
+-	int size;
+ 	int i, j, num_ports;
+ 
+ 	cancel_delayed_work_sync(&xhci->cmd_timer);
+ 
+-	/* Free the Event Ring Segment Table and the actual Event Ring */
+-	size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
+-	if (xhci->erst.entries)
+-		dma_free_coherent(dev, size,
+-				xhci->erst.entries, xhci->erst.erst_dma_addr);
+-	xhci->erst.entries = NULL;
+-	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST");
++	xhci_free_erst(xhci, &xhci->erst);
++
+ 	if (xhci->event_ring)
+ 		xhci_ring_free(xhci, xhci->event_ring);
+ 	xhci->event_ring = NULL;
+@@ -2324,9 +2364,8 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 	struct device	*dev = xhci_to_hcd(xhci)->self.sysdev;
+ 	unsigned int	val, val2;
+ 	u64		val_64;
+-	struct xhci_segment	*seg;
+-	u32 page_size, temp;
+-	int i;
++	u32		page_size, temp;
++	int		i, ret;
+ 
+ 	INIT_LIST_HEAD(&xhci->cmd_list);
+ 
+@@ -2465,32 +2504,9 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 	if (xhci_check_trb_in_td_math(xhci) < 0)
+ 		goto fail;
+ 
+-	xhci->erst.entries = dma_alloc_coherent(dev,
+-			sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
+-			flags);
+-	if (!xhci->erst.entries)
++	ret = xhci_alloc_erst(xhci, xhci->event_ring, &xhci->erst, flags);
++	if (ret)
+ 		goto fail;
+-	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+-			"// Allocated event ring segment table at 0x%llx",
+-			(unsigned long long)dma);
+-
+-	memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
+-	xhci->erst.num_entries = ERST_NUM_SEGS;
+-	xhci->erst.erst_dma_addr = dma;
+-	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+-			"Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
+-			xhci->erst.num_entries,
+-			xhci->erst.entries,
+-			(unsigned long long)xhci->erst.erst_dma_addr);
+-
+-	/* set ring base address and size for each segment table entry */
+-	for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
+-		struct xhci_erst_entry *entry = &xhci->erst.entries[val];
+-		entry->seg_addr = cpu_to_le64(seg->dma);
+-		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
+-		entry->rsvd = 0;
+-		seg = seg->next;
+-	}
+ 
+ 	/* set ERST count with the number of entries in the segment table */
+ 	val = readl(&xhci->ir_set->erst_size);
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index af079f492a9e..daa94c3aed80 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -153,7 +153,7 @@ static void next_trb(struct xhci_hcd *xhci,
+  * See Cycle bit rules. SW is the consumer for the event ring only.
+  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
+  */
+-static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
++void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
+ {
+ 	/* event ring doesn't have link trbs, check for last trb */
+ 	if (ring->type == TYPE_EVENT) {
+@@ -2961,7 +2961,7 @@ static int prepare_transfer(struct xhci_hcd *xhci,
+ 	return 0;
+ }
+ 
+-static unsigned int count_trbs(u64 addr, u64 len)
++unsigned int count_trbs(u64 addr, u64 len)
+ {
+ 	unsigned int num_trbs;
+ 
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 98c68f76ef44..8fa92c813026 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1971,9 +1971,17 @@ void xhci_slot_copy(struct xhci_hcd *xhci,
+ int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
+ 		struct usb_device *udev, struct usb_host_endpoint *ep,
+ 		gfp_t mem_flags);
++struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
++		unsigned int num_segs, unsigned int cycle_state,
++		enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
+ void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
+ int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
+-				unsigned int num_trbs, gfp_t flags);
++		unsigned int num_trbs, gfp_t flags);
++int xhci_alloc_erst(struct xhci_hcd *xhci,
++		struct xhci_ring *evt_ring,
++		struct xhci_erst *erst,
++		gfp_t flags);
++void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
+ void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
+ 		struct xhci_virt_device *virt_dev,
+ 		unsigned int ep_index);
+@@ -2004,6 +2012,10 @@ struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
+ void xhci_urb_free_priv(struct urb_priv *urb_priv);
+ void xhci_free_command(struct xhci_hcd *xhci,
+ 		struct xhci_command *command);
++struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
++		int type, gfp_t flags);
++void xhci_free_container_ctx(struct xhci_hcd *xhci,
++		struct xhci_container_ctx *ctx);
+ 
+ /* xHCI host controller glue */
+ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
+@@ -2077,6 +2089,8 @@ void xhci_handle_command_timeout(struct work_struct *work);
+ void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
+ 		unsigned int ep_index, unsigned int stream_id);
+ void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
++void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
++unsigned int count_trbs(u64 addr, u64 len);
+ 
+ /* xHCI roothub code */
+ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+-- 
+2.19.0
+
diff --git a/patches/0527-usb-xhci-Add-DbC-support-in-xHCI-driver.patch b/patches/0527-usb-xhci-Add-DbC-support-in-xHCI-driver.patch
new file mode 100644
index 00000000000000..a6f5c9f12b74bb
--- /dev/null
+++ b/patches/0527-usb-xhci-Add-DbC-support-in-xHCI-driver.patch
@@ -0,0 +1,2003 @@
+From 54a50fd39ad8c7b40bf8b431d06c214e70c42390 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:10 +0200
+Subject: [PATCH 0527/1795] usb: xhci: Add DbC support in xHCI driver
+
+xHCI compatible USB host controllers(i.e. super-speed USB3 controllers)
+can be implemented with the Debug Capability(DbC). It presents a debug
+device which is fully compliant with the USB framework and provides the
+equivalent of a very high performance full-duplex serial link. The debug
+capability operation model and registers interface are defined in 7.6.8
+of the xHCI specification, revision 1.1.
+
+The DbC debug device shares a root port with the xHCI host. By default,
+the debug capability is disabled and the root port is assigned to xHCI.
+When the DbC is enabled, the root port will be assigned to the DbC debug
+device, and the xHCI sees nothing on this port. This implementation uses
+a sysfs node named <dbc> under the xHCI device to manage the enabling
+and disabling of the debug capability.
+
+When the debug capability is enabled, it will present a debug device
+through the debug port. This debug device is fully compliant with the
+USB3 framework, and it can be enumerated by a debug host on the other
+end of the USB link. As soon as the debug device is configured, a TTY
+serial device named /dev/ttyDBC0 will be created.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit dfba2174dc421ecad8dc50741054a305cd3ba681)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/host/xhci-trace.h
+---
+ .../testing/sysfs-bus-pci-drivers-xhci_hcd    |  25 +
+ drivers/usb/host/Kconfig                      |   8 +
+ drivers/usb/host/Makefile                     |   5 +
+ drivers/usb/host/xhci-dbgcap.c                | 996 ++++++++++++++++++
+ drivers/usb/host/xhci-dbgcap.h                | 229 ++++
+ drivers/usb/host/xhci-dbgtty.c                | 497 +++++++++
+ drivers/usb/host/xhci-trace.h                 |  59 ++
+ drivers/usb/host/xhci.c                       |   9 +
+ drivers/usb/host/xhci.h                       |   1 +
+ 9 files changed, 1829 insertions(+)
+ create mode 100644 Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd
+ create mode 100644 drivers/usb/host/xhci-dbgcap.c
+ create mode 100644 drivers/usb/host/xhci-dbgcap.h
+ create mode 100644 drivers/usb/host/xhci-dbgtty.c
+
+diff --git a/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd b/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd
+new file mode 100644
+index 000000000000..0088aba4caa8
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd
+@@ -0,0 +1,25 @@
++What:		/sys/bus/pci/drivers/xhci_hcd/.../dbc
++Date:		June 2017
++Contact:	Lu Baolu <baolu.lu@linux.intel.com>
++Description:
++		xHCI compatible USB host controllers (i.e. super-speed
++		USB3 controllers) are often implemented with the Debug
++		Capability (DbC). It can present a debug device which
++		is fully compliant with the USB framework and provides
++		the equivalent of a very high performance full-duplex
++		serial link for debug purpose.
++
++		The DbC debug device shares a root port with xHCI host.
++		When the DbC is enabled, the root port will be assigned
++		to the Debug Capability. Otherwise, it will be assigned
++		to xHCI.
++
++		Writing "enable" to this attribute will enable the DbC
++		functionality and the shared root port will be assigned
++		to the DbC device. Writing "disable" to this attribute
++		will disable the DbC functionality and the shared root
++		port will roll back to the xHCI.
++
++		Reading this attribute gives the state of the DbC. It
++		can be one of the following states: disabled, enabled,
++		initialized, connected, configured and stalled.
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 92b19721b595..f1349a743963 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -27,6 +27,14 @@ config USB_XHCI_HCD
+ 	  module will be called xhci-hcd.
+ 
+ if USB_XHCI_HCD
++config USB_XHCI_DBGCAP
++	bool "xHCI support for debug capability"
++	depends on TTY
++	---help---
++	  Say 'Y' to enable the support for the xHCI debug capability. Make
++	  sure that your xHCI host supports the extended debug capability and
++	  you want a TTY serial device based on the xHCI debug capability
++	  before enabling this option. If unsure, say 'N'.
+ 
+ config USB_XHCI_PCI
+        tristate
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index 81bfd7c70bd2..e77fe32e7b35 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -14,6 +14,11 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
+ xhci-hcd-y := xhci.o xhci-mem.o
+ xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
+ xhci-hcd-y += xhci-trace.o
++
++ifneq ($(CONFIG_USB_XHCI_DBGCAP), )
++	xhci-hcd-y += xhci-dbgcap.o xhci-dbgtty.o
++endif
++
+ ifneq ($(CONFIG_USB_XHCI_MTK), )
+ 	xhci-hcd-y += xhci-mtk-sch.o
+ endif
+diff --git a/drivers/usb/host/xhci-dbgcap.c b/drivers/usb/host/xhci-dbgcap.c
+new file mode 100644
+index 000000000000..671e5023e683
+--- /dev/null
++++ b/drivers/usb/host/xhci-dbgcap.c
+@@ -0,0 +1,996 @@
++/**
++ * xhci-dbgcap.c - xHCI debug capability support
++ *
++ * Copyright (C) 2017 Intel Corporation
++ *
++ * Author: Lu Baolu <baolu.lu@linux.intel.com>
++ */
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/nls.h>
++
++#include "xhci.h"
++#include "xhci-trace.h"
++#include "xhci-dbgcap.h"
++
++static inline void *
++dbc_dma_alloc_coherent(struct xhci_hcd *xhci, size_t size,
++		       dma_addr_t *dma_handle, gfp_t flags)
++{
++	void		*vaddr;
++
++	vaddr = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
++				   size, dma_handle, flags);
++	memset(vaddr, 0, size);
++	return vaddr;
++}
++
++static inline void
++dbc_dma_free_coherent(struct xhci_hcd *xhci, size_t size,
++		      void *cpu_addr, dma_addr_t dma_handle)
++{
++	if (cpu_addr)
++		dma_free_coherent(xhci_to_hcd(xhci)->self.sysdev,
++				  size, cpu_addr, dma_handle);
++}
++
++static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
++{
++	struct usb_string_descriptor	*s_desc;
++	u32				string_length;
++
++	/* Serial string: */
++	s_desc = (struct usb_string_descriptor *)strings->serial;
++	utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
++			UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
++			DBC_MAX_STRING_LENGTH);
++
++	s_desc->bLength		= (strlen(DBC_STRING_SERIAL) + 1) * 2;
++	s_desc->bDescriptorType	= USB_DT_STRING;
++	string_length		= s_desc->bLength;
++	string_length		<<= 8;
++
++	/* Product string: */
++	s_desc = (struct usb_string_descriptor *)strings->product;
++	utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
++			UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
++			DBC_MAX_STRING_LENGTH);
++
++	s_desc->bLength		= (strlen(DBC_STRING_PRODUCT) + 1) * 2;
++	s_desc->bDescriptorType	= USB_DT_STRING;
++	string_length		+= s_desc->bLength;
++	string_length		<<= 8;
++
++	/* Manufacture string: */
++	s_desc = (struct usb_string_descriptor *)strings->manufacturer;
++	utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
++			strlen(DBC_STRING_MANUFACTURER),
++			UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
++			DBC_MAX_STRING_LENGTH);
++
++	s_desc->bLength		= (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
++	s_desc->bDescriptorType	= USB_DT_STRING;
++	string_length		+= s_desc->bLength;
++	string_length		<<= 8;
++
++	/* String0: */
++	strings->string0[0]	= 4;
++	strings->string0[1]	= USB_DT_STRING;
++	strings->string0[2]	= 0x09;
++	strings->string0[3]	= 0x04;
++	string_length		+= 4;
++
++	return string_length;
++}
++
++static void xhci_dbc_init_contexts(struct xhci_hcd *xhci, u32 string_length)
++{
++	struct xhci_dbc		*dbc;
++	struct dbc_info_context	*info;
++	struct xhci_ep_ctx	*ep_ctx;
++	u32			dev_info;
++	dma_addr_t		deq, dma;
++	unsigned int		max_burst;
++
++	dbc = xhci->dbc;
++	if (!dbc)
++		return;
++
++	/* Populate info Context: */
++	info			= (struct dbc_info_context *)dbc->ctx->bytes;
++	dma			= dbc->string_dma;
++	info->string0		= cpu_to_le64(dma);
++	info->manufacturer	= cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
++	info->product		= cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
++	info->serial		= cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
++	info->length		= cpu_to_le32(string_length);
++
++	/* Populate bulk out endpoint context: */
++	ep_ctx			= dbc_bulkout_ctx(dbc);
++	max_burst		= DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
++	deq			= dbc_bulkout_enq(dbc);
++	ep_ctx->ep_info		= 0;
++	ep_ctx->ep_info2	= dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
++	ep_ctx->deq		= cpu_to_le64(deq | dbc->ring_out->cycle_state);
++
++	/* Populate bulk in endpoint context: */
++	ep_ctx			= dbc_bulkin_ctx(dbc);
++	deq			= dbc_bulkin_enq(dbc);
++	ep_ctx->ep_info		= 0;
++	ep_ctx->ep_info2	= dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
++	ep_ctx->deq		= cpu_to_le64(deq | dbc->ring_in->cycle_state);
++
++	/* Set DbC context and info registers: */
++	xhci_write_64(xhci, dbc->ctx->dma, &dbc->regs->dccp);
++
++	dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
++	writel(dev_info, &dbc->regs->devinfo1);
++
++	dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
++	writel(dev_info, &dbc->regs->devinfo2);
++}
++
++static void xhci_dbc_giveback(struct dbc_request *req, int status)
++	__releases(&dbc->lock)
++	__acquires(&dbc->lock)
++{
++	struct dbc_ep		*dep = req->dep;
++	struct xhci_dbc		*dbc = dep->dbc;
++	struct xhci_hcd		*xhci = dbc->xhci;
++	struct device		*dev = xhci_to_hcd(dbc->xhci)->self.sysdev;
++
++	list_del_init(&req->list_pending);
++	req->trb_dma = 0;
++	req->trb = NULL;
++
++	if (req->status == -EINPROGRESS)
++		req->status = status;
++
++	trace_xhci_dbc_giveback_request(req);
++
++	dma_unmap_single(dev,
++			 req->dma,
++			 req->length,
++			 dbc_ep_dma_direction(dep));
++
++	/* Give back the transfer request: */
++	spin_unlock(&dbc->lock);
++	req->complete(xhci, req);
++	spin_lock(&dbc->lock);
++}
++
++static void xhci_dbc_flush_single_request(struct dbc_request *req)
++{
++	union xhci_trb	*trb = req->trb;
++
++	trb->generic.field[0]	= 0;
++	trb->generic.field[1]	= 0;
++	trb->generic.field[2]	= 0;
++	trb->generic.field[3]	&= cpu_to_le32(TRB_CYCLE);
++	trb->generic.field[3]	|= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
++
++	xhci_dbc_giveback(req, -ESHUTDOWN);
++}
++
++static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
++{
++	struct dbc_request	*req, *tmp;
++
++	list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
++		xhci_dbc_flush_single_request(req);
++}
++
++static void xhci_dbc_flush_reqests(struct xhci_dbc *dbc)
++{
++	xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
++	xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
++}
++
++struct dbc_request *
++dbc_alloc_request(struct dbc_ep *dep, gfp_t gfp_flags)
++{
++	struct dbc_request	*req;
++
++	req = kzalloc(sizeof(*req), gfp_flags);
++	if (!req)
++		return NULL;
++
++	req->dep = dep;
++	INIT_LIST_HEAD(&req->list_pending);
++	INIT_LIST_HEAD(&req->list_pool);
++	req->direction = dep->direction;
++
++	trace_xhci_dbc_alloc_request(req);
++
++	return req;
++}
++
++void
++dbc_free_request(struct dbc_ep *dep, struct dbc_request *req)
++{
++	trace_xhci_dbc_free_request(req);
++
++	kfree(req);
++}
++
++static void
++xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
++		   u32 field2, u32 field3, u32 field4)
++{
++	union xhci_trb		*trb, *next;
++
++	trb = ring->enqueue;
++	trb->generic.field[0]	= cpu_to_le32(field1);
++	trb->generic.field[1]	= cpu_to_le32(field2);
++	trb->generic.field[2]	= cpu_to_le32(field3);
++	trb->generic.field[3]	= cpu_to_le32(field4);
++
++	trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
++
++	ring->num_trbs_free--;
++	next = ++(ring->enqueue);
++	if (TRB_TYPE_LINK_LE32(next->link.control)) {
++		next->link.control ^= cpu_to_le32(TRB_CYCLE);
++		ring->enqueue = ring->enq_seg->trbs;
++		ring->cycle_state ^= 1;
++	}
++}
++
++static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
++				  struct dbc_request *req)
++{
++	u64			addr;
++	union xhci_trb		*trb;
++	unsigned int		num_trbs;
++	struct xhci_dbc		*dbc = dep->dbc;
++	struct xhci_ring	*ring = dep->ring;
++	u32			length, control, cycle;
++
++	num_trbs = count_trbs(req->dma, req->length);
++	WARN_ON(num_trbs != 1);
++	if (ring->num_trbs_free < num_trbs)
++		return -EBUSY;
++
++	addr	= req->dma;
++	trb	= ring->enqueue;
++	cycle	= ring->cycle_state;
++	length	= TRB_LEN(req->length);
++	control	= TRB_TYPE(TRB_NORMAL) | TRB_IOC;
++
++	if (cycle)
++		control &= cpu_to_le32(~TRB_CYCLE);
++	else
++		control |= cpu_to_le32(TRB_CYCLE);
++
++	req->trb = ring->enqueue;
++	req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
++	xhci_dbc_queue_trb(ring,
++			   lower_32_bits(addr),
++			   upper_32_bits(addr),
++			   length, control);
++
++	/*
++	 * Add a barrier between writes of trb fields and flipping
++	 * the cycle bit:
++	 */
++	wmb();
++
++	if (cycle)
++		trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
++	else
++		trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
++
++	writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
++
++	return 0;
++}
++
++static int
++dbc_ep_do_queue(struct dbc_ep *dep, struct dbc_request *req)
++{
++	int			ret;
++	struct device		*dev;
++	struct xhci_dbc		*dbc = dep->dbc;
++	struct xhci_hcd		*xhci = dbc->xhci;
++
++	dev = xhci_to_hcd(xhci)->self.sysdev;
++
++	if (!req->length || !req->buf)
++		return -EINVAL;
++
++	req->actual		= 0;
++	req->status		= -EINPROGRESS;
++
++	req->dma = dma_map_single(dev,
++				  req->buf,
++				  req->length,
++				  dbc_ep_dma_direction(dep));
++	if (dma_mapping_error(dev, req->dma)) {
++		xhci_err(xhci, "failed to map buffer\n");
++		return -EFAULT;
++	}
++
++	ret = xhci_dbc_queue_bulk_tx(dep, req);
++	if (ret) {
++		xhci_err(xhci, "failed to queue trbs\n");
++		dma_unmap_single(dev,
++				 req->dma,
++				 req->length,
++				 dbc_ep_dma_direction(dep));
++		return -EFAULT;
++	}
++
++	list_add_tail(&req->list_pending, &dep->list_pending);
++
++	return 0;
++}
++
++int dbc_ep_queue(struct dbc_ep *dep, struct dbc_request *req,
++		 gfp_t gfp_flags)
++{
++	struct xhci_dbc		*dbc = dep->dbc;
++	int			ret = -ESHUTDOWN;
++
++	spin_lock(&dbc->lock);
++	if (dbc->state == DS_CONFIGURED)
++		ret = dbc_ep_do_queue(dep, req);
++	spin_unlock(&dbc->lock);
++
++	mod_delayed_work(system_wq, &dbc->event_work, 0);
++
++	trace_xhci_dbc_queue_request(req);
++
++	return ret;
++}
++
++static inline void xhci_dbc_do_eps_init(struct xhci_hcd *xhci, bool direction)
++{
++	struct dbc_ep		*dep;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	dep			= &dbc->eps[direction];
++	dep->dbc		= dbc;
++	dep->direction		= direction;
++	dep->ring		= direction ? dbc->ring_in : dbc->ring_out;
++
++	INIT_LIST_HEAD(&dep->list_pending);
++}
++
++static void xhci_dbc_eps_init(struct xhci_hcd *xhci)
++{
++	xhci_dbc_do_eps_init(xhci, BULK_OUT);
++	xhci_dbc_do_eps_init(xhci, BULK_IN);
++}
++
++static void xhci_dbc_eps_exit(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	memset(dbc->eps, 0, ARRAY_SIZE(dbc->eps));
++}
++
++static int xhci_dbc_mem_init(struct xhci_hcd *xhci, gfp_t flags)
++{
++	int			ret;
++	dma_addr_t		deq;
++	u32			string_length;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	/* Allocate various rings for events and transfers: */
++	dbc->ring_evt = xhci_ring_alloc(xhci, 1, 1, TYPE_EVENT, 0, flags);
++	if (!dbc->ring_evt)
++		goto evt_fail;
++
++	dbc->ring_in = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
++	if (!dbc->ring_in)
++		goto in_fail;
++
++	dbc->ring_out = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
++	if (!dbc->ring_out)
++		goto out_fail;
++
++	/* Allocate and populate ERST: */
++	ret = xhci_alloc_erst(xhci, dbc->ring_evt, &dbc->erst, flags);
++	if (ret)
++		goto erst_fail;
++
++	/* Allocate context data structure: */
++	dbc->ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
++	if (!dbc->ctx)
++		goto ctx_fail;
++
++	/* Allocate the string table: */
++	dbc->string_size = sizeof(struct dbc_str_descs);
++	dbc->string = dbc_dma_alloc_coherent(xhci,
++					     dbc->string_size,
++					     &dbc->string_dma,
++					     flags);
++	if (!dbc->string)
++		goto string_fail;
++
++	/* Setup ERST register: */
++	writel(dbc->erst.erst_size, &dbc->regs->ersts);
++	xhci_write_64(xhci, dbc->erst.erst_dma_addr, &dbc->regs->erstba);
++	deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
++				   dbc->ring_evt->dequeue);
++	xhci_write_64(xhci, deq, &dbc->regs->erdp);
++
++	/* Setup strings and contexts: */
++	string_length = xhci_dbc_populate_strings(dbc->string);
++	xhci_dbc_init_contexts(xhci, string_length);
++
++	mmiowb();
++
++	xhci_dbc_eps_init(xhci);
++	dbc->state = DS_INITIALIZED;
++
++	return 0;
++
++string_fail:
++	xhci_free_container_ctx(xhci, dbc->ctx);
++	dbc->ctx = NULL;
++ctx_fail:
++	xhci_free_erst(xhci, &dbc->erst);
++erst_fail:
++	xhci_ring_free(xhci, dbc->ring_out);
++	dbc->ring_out = NULL;
++out_fail:
++	xhci_ring_free(xhci, dbc->ring_in);
++	dbc->ring_in = NULL;
++in_fail:
++	xhci_ring_free(xhci, dbc->ring_evt);
++	dbc->ring_evt = NULL;
++evt_fail:
++	return -ENOMEM;
++}
++
++static void xhci_dbc_mem_cleanup(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	if (!dbc)
++		return;
++
++	xhci_dbc_eps_exit(xhci);
++
++	if (dbc->string) {
++		dbc_dma_free_coherent(xhci,
++				      dbc->string_size,
++				      dbc->string, dbc->string_dma);
++		dbc->string = NULL;
++	}
++
++	xhci_free_container_ctx(xhci, dbc->ctx);
++	dbc->ctx = NULL;
++
++	xhci_free_erst(xhci, &dbc->erst);
++	xhci_ring_free(xhci, dbc->ring_out);
++	xhci_ring_free(xhci, dbc->ring_in);
++	xhci_ring_free(xhci, dbc->ring_evt);
++	dbc->ring_in = NULL;
++	dbc->ring_out = NULL;
++	dbc->ring_evt = NULL;
++}
++
++static int xhci_do_dbc_start(struct xhci_hcd *xhci)
++{
++	int			ret;
++	u32			ctrl;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	if (dbc->state != DS_DISABLED)
++		return -EINVAL;
++
++	writel(0, &dbc->regs->control);
++	ret = xhci_handshake(&dbc->regs->control,
++			     DBC_CTRL_DBC_ENABLE,
++			     0, 1000);
++	if (ret)
++		return ret;
++
++	ret = xhci_dbc_mem_init(xhci, GFP_ATOMIC);
++	if (ret)
++		return ret;
++
++	ctrl = readl(&dbc->regs->control);
++	writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
++	       &dbc->regs->control);
++	ret = xhci_handshake(&dbc->regs->control,
++			     DBC_CTRL_DBC_ENABLE,
++			     DBC_CTRL_DBC_ENABLE, 1000);
++	if (ret)
++		return ret;
++
++	dbc->state = DS_ENABLED;
++
++	return 0;
++}
++
++static void xhci_do_dbc_stop(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	if (dbc->state == DS_DISABLED)
++		return;
++
++	writel(0, &dbc->regs->control);
++	xhci_dbc_mem_cleanup(xhci);
++	dbc->state = DS_DISABLED;
++}
++
++static int xhci_dbc_start(struct xhci_hcd *xhci)
++{
++	int			ret;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	WARN_ON(!dbc);
++
++	pm_runtime_get_sync(xhci_to_hcd(xhci)->self.controller);
++
++	spin_lock(&dbc->lock);
++	ret = xhci_do_dbc_start(xhci);
++	spin_unlock(&dbc->lock);
++
++	if (ret) {
++		pm_runtime_put(xhci_to_hcd(xhci)->self.controller);
++		return ret;
++	}
++
++	return mod_delayed_work(system_wq, &dbc->event_work, 1);
++}
++
++static void xhci_dbc_stop(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++	struct dbc_port		*port = &dbc->port;
++
++	WARN_ON(!dbc);
++
++	cancel_delayed_work_sync(&dbc->event_work);
++
++	if (port->registered)
++		xhci_dbc_tty_unregister_device(xhci);
++
++	spin_lock(&dbc->lock);
++	xhci_do_dbc_stop(xhci);
++	spin_unlock(&dbc->lock);
++
++	pm_runtime_put_sync(xhci_to_hcd(xhci)->self.controller);
++}
++
++static void
++dbc_handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
++{
++	u32			portsc;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	portsc = readl(&dbc->regs->portsc);
++	if (portsc & DBC_PORTSC_CONN_CHANGE)
++		xhci_info(xhci, "DbC port connect change\n");
++
++	if (portsc & DBC_PORTSC_RESET_CHANGE)
++		xhci_info(xhci, "DbC port reset change\n");
++
++	if (portsc & DBC_PORTSC_LINK_CHANGE)
++		xhci_info(xhci, "DbC port link status change\n");
++
++	if (portsc & DBC_PORTSC_CONFIG_CHANGE)
++		xhci_info(xhci, "DbC config error change\n");
++
++	/* Port reset change bit will be cleared in other place: */
++	writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
++}
++
++static void dbc_handle_xfer_event(struct xhci_hcd *xhci, union xhci_trb *event)
++{
++	struct dbc_ep		*dep;
++	struct xhci_ring	*ring;
++	int			ep_id;
++	int			status;
++	u32			comp_code;
++	size_t			remain_length;
++	struct dbc_request	*req = NULL, *r;
++
++	comp_code	= GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
++	remain_length	= EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
++	ep_id		= TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
++	dep		= (ep_id == EPID_OUT) ?
++				get_out_ep(xhci) : get_in_ep(xhci);
++	ring		= dep->ring;
++
++	switch (comp_code) {
++	case COMP_SUCCESS:
++		remain_length = 0;
++	/* FALLTHROUGH */
++	case COMP_SHORT_PACKET:
++		status = 0;
++		break;
++	case COMP_TRB_ERROR:
++	case COMP_BABBLE_DETECTED_ERROR:
++	case COMP_USB_TRANSACTION_ERROR:
++	case COMP_STALL_ERROR:
++		xhci_warn(xhci, "tx error %d detected\n", comp_code);
++		status = -comp_code;
++		break;
++	default:
++		xhci_err(xhci, "unknown tx error %d\n", comp_code);
++		status = -comp_code;
++		break;
++	}
++
++	/* Match the pending request: */
++	list_for_each_entry(r, &dep->list_pending, list_pending) {
++		if (r->trb_dma == event->trans_event.buffer) {
++			req = r;
++			break;
++		}
++	}
++
++	if (!req) {
++		xhci_warn(xhci, "no matched request\n");
++		return;
++	}
++
++	trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
++
++	ring->num_trbs_free++;
++	req->actual = req->length - remain_length;
++	xhci_dbc_giveback(req, status);
++}
++
++static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
++{
++	dma_addr_t		deq;
++	struct dbc_ep		*dep;
++	union xhci_trb		*evt;
++	u32			ctrl, portsc;
++	struct xhci_hcd		*xhci = dbc->xhci;
++	bool			update_erdp = false;
++
++	/* DbC state machine: */
++	switch (dbc->state) {
++	case DS_DISABLED:
++	case DS_INITIALIZED:
++
++		return EVT_ERR;
++	case DS_ENABLED:
++		portsc = readl(&dbc->regs->portsc);
++		if (portsc & DBC_PORTSC_CONN_STATUS) {
++			dbc->state = DS_CONNECTED;
++			xhci_info(xhci, "DbC connected\n");
++		}
++
++		return EVT_DONE;
++	case DS_CONNECTED:
++		ctrl = readl(&dbc->regs->control);
++		if (ctrl & DBC_CTRL_DBC_RUN) {
++			dbc->state = DS_CONFIGURED;
++			xhci_info(xhci, "DbC configured\n");
++			portsc = readl(&dbc->regs->portsc);
++			writel(portsc, &dbc->regs->portsc);
++			return EVT_GSER;
++		}
++
++		return EVT_DONE;
++	case DS_CONFIGURED:
++		/* Handle cable unplug event: */
++		portsc = readl(&dbc->regs->portsc);
++		if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
++		    !(portsc & DBC_PORTSC_CONN_STATUS)) {
++			xhci_info(xhci, "DbC cable unplugged\n");
++			dbc->state = DS_ENABLED;
++			xhci_dbc_flush_reqests(dbc);
++
++			return EVT_DISC;
++		}
++
++		/* Handle debug port reset event: */
++		if (portsc & DBC_PORTSC_RESET_CHANGE) {
++			xhci_info(xhci, "DbC port reset\n");
++			writel(portsc, &dbc->regs->portsc);
++			dbc->state = DS_ENABLED;
++			xhci_dbc_flush_reqests(dbc);
++
++			return EVT_DISC;
++		}
++
++		/* Handle endpoint stall event: */
++		ctrl = readl(&dbc->regs->control);
++		if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
++		    (ctrl & DBC_CTRL_HALT_OUT_TR)) {
++			xhci_info(xhci, "DbC Endpoint stall\n");
++			dbc->state = DS_STALLED;
++
++			if (ctrl & DBC_CTRL_HALT_IN_TR) {
++				dep = get_in_ep(xhci);
++				xhci_dbc_flush_endpoint_requests(dep);
++			}
++
++			if (ctrl & DBC_CTRL_HALT_OUT_TR) {
++				dep = get_out_ep(xhci);
++				xhci_dbc_flush_endpoint_requests(dep);
++			}
++
++			return EVT_DONE;
++		}
++
++		/* Clear DbC run change bit: */
++		if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
++			writel(ctrl, &dbc->regs->control);
++			ctrl = readl(&dbc->regs->control);
++		}
++
++		break;
++	case DS_STALLED:
++		ctrl = readl(&dbc->regs->control);
++		if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
++		    !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
++		    (ctrl & DBC_CTRL_DBC_RUN)) {
++			dbc->state = DS_CONFIGURED;
++			break;
++		}
++
++		return EVT_DONE;
++	default:
++		xhci_err(xhci, "Unknown DbC state %d\n", dbc->state);
++		break;
++	}
++
++	/* Handle the events in the event ring: */
++	evt = dbc->ring_evt->dequeue;
++	while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
++			dbc->ring_evt->cycle_state) {
++		/*
++		 * Add a barrier between reading the cycle flag and any
++		 * reads of the event's flags/data below:
++		 */
++		rmb();
++
++		trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
++
++		switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
++		case TRB_TYPE(TRB_PORT_STATUS):
++			dbc_handle_port_status(xhci, evt);
++			break;
++		case TRB_TYPE(TRB_TRANSFER):
++			dbc_handle_xfer_event(xhci, evt);
++			break;
++		default:
++			break;
++		}
++
++		inc_deq(xhci, dbc->ring_evt);
++		evt = dbc->ring_evt->dequeue;
++		update_erdp = true;
++	}
++
++	/* Update event ring dequeue pointer: */
++	if (update_erdp) {
++		deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
++					   dbc->ring_evt->dequeue);
++		xhci_write_64(xhci, deq, &dbc->regs->erdp);
++	}
++
++	return EVT_DONE;
++}
++
++static void xhci_dbc_handle_events(struct work_struct *work)
++{
++	int			ret;
++	enum evtreturn		evtr;
++	struct xhci_dbc		*dbc;
++	struct xhci_hcd		*xhci;
++
++	dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
++	xhci = dbc->xhci;
++
++	spin_lock(&dbc->lock);
++	evtr = xhci_dbc_do_handle_events(dbc);
++	spin_unlock(&dbc->lock);
++
++	switch (evtr) {
++	case EVT_GSER:
++		ret = xhci_dbc_tty_register_device(xhci);
++		if (ret) {
++			xhci_err(xhci, "failed to alloc tty device\n");
++			break;
++		}
++
++		xhci_info(xhci, "DbC now attached to /dev/ttyDBC0\n");
++		break;
++	case EVT_DISC:
++		xhci_dbc_tty_unregister_device(xhci);
++		break;
++	case EVT_DONE:
++		break;
++	default:
++		xhci_info(xhci, "stop handling dbc events\n");
++		return;
++	}
++
++	mod_delayed_work(system_wq, &dbc->event_work, 1);
++}
++
++static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
++{
++	unsigned long		flags;
++
++	spin_lock_irqsave(&xhci->lock, flags);
++	kfree(xhci->dbc);
++	xhci->dbc = NULL;
++	spin_unlock_irqrestore(&xhci->lock, flags);
++}
++
++static int xhci_do_dbc_init(struct xhci_hcd *xhci)
++{
++	u32			reg;
++	struct xhci_dbc		*dbc;
++	unsigned long		flags;
++	void __iomem		*base;
++	int			dbc_cap_offs;
++
++	base = &xhci->cap_regs->hc_capbase;
++	dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
++	if (!dbc_cap_offs)
++		return -ENODEV;
++
++	dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
++	if (!dbc)
++		return -ENOMEM;
++
++	dbc->regs = base + dbc_cap_offs;
++
++	/* We will avoid using DbC in xhci driver if it's in use. */
++	reg = readl(&dbc->regs->control);
++	if (reg & DBC_CTRL_DBC_ENABLE) {
++		kfree(dbc);
++		return -EBUSY;
++	}
++
++	spin_lock_irqsave(&xhci->lock, flags);
++	if (xhci->dbc) {
++		spin_unlock_irqrestore(&xhci->lock, flags);
++		kfree(dbc);
++		return -EBUSY;
++	}
++	xhci->dbc = dbc;
++	spin_unlock_irqrestore(&xhci->lock, flags);
++
++	dbc->xhci = xhci;
++	INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
++	spin_lock_init(&dbc->lock);
++
++	return 0;
++}
++
++static ssize_t dbc_show(struct device *dev,
++			struct device_attribute *attr,
++			char *buf)
++{
++	const char		*p;
++	struct xhci_dbc		*dbc;
++	struct xhci_hcd		*xhci;
++
++	xhci = hcd_to_xhci(dev_get_drvdata(dev));
++	dbc = xhci->dbc;
++
++	switch (dbc->state) {
++	case DS_DISABLED:
++		p = "disabled";
++		break;
++	case DS_INITIALIZED:
++		p = "initialized";
++		break;
++	case DS_ENABLED:
++		p = "enabled";
++		break;
++	case DS_CONNECTED:
++		p = "connected";
++		break;
++	case DS_CONFIGURED:
++		p = "configured";
++		break;
++	case DS_STALLED:
++		p = "stalled";
++		break;
++	default:
++		p = "unknown";
++	}
++
++	return sprintf(buf, "%s\n", p);
++}
++
++static ssize_t dbc_store(struct device *dev,
++			 struct device_attribute *attr,
++			 const char *buf, size_t count)
++{
++	struct xhci_dbc		*dbc;
++	struct xhci_hcd		*xhci;
++
++	xhci = hcd_to_xhci(dev_get_drvdata(dev));
++	dbc = xhci->dbc;
++
++	if (!strncmp(buf, "enable", 6))
++		xhci_dbc_start(xhci);
++	else if (!strncmp(buf, "disable", 7))
++		xhci_dbc_stop(xhci);
++	else
++		return -EINVAL;
++
++	return count;
++}
++
++static DEVICE_ATTR(dbc, 0644, dbc_show, dbc_store);
++
++int xhci_dbc_init(struct xhci_hcd *xhci)
++{
++	int			ret;
++	struct device		*dev = xhci_to_hcd(xhci)->self.controller;
++
++	ret = xhci_do_dbc_init(xhci);
++	if (ret)
++		goto init_err3;
++
++	ret = xhci_dbc_tty_register_driver(xhci);
++	if (ret)
++		goto init_err2;
++
++	ret = device_create_file(dev, &dev_attr_dbc);
++	if (ret)
++		goto init_err1;
++
++	return 0;
++
++init_err1:
++	xhci_dbc_tty_unregister_driver();
++init_err2:
++	xhci_do_dbc_exit(xhci);
++init_err3:
++	return ret;
++}
++
++void xhci_dbc_exit(struct xhci_hcd *xhci)
++{
++	struct device		*dev = xhci_to_hcd(xhci)->self.controller;
++
++	if (!xhci->dbc)
++		return;
++
++	device_remove_file(dev, &dev_attr_dbc);
++	xhci_dbc_tty_unregister_driver();
++	xhci_dbc_stop(xhci);
++	xhci_do_dbc_exit(xhci);
++}
++
++#ifdef CONFIG_PM
++int xhci_dbc_suspend(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	if (!dbc)
++		return 0;
++
++	if (dbc->state == DS_CONFIGURED)
++		dbc->resume_required = 1;
++
++	xhci_dbc_stop(xhci);
++
++	return 0;
++}
++
++int xhci_dbc_resume(struct xhci_hcd *xhci)
++{
++	int			ret = 0;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	if (!dbc)
++		return 0;
++
++	if (dbc->resume_required) {
++		dbc->resume_required = 0;
++		xhci_dbc_start(xhci);
++	}
++
++	return ret;
++}
++#endif /* CONFIG_PM */
+diff --git a/drivers/usb/host/xhci-dbgcap.h b/drivers/usb/host/xhci-dbgcap.h
+new file mode 100644
+index 000000000000..e66ea0748ba3
+--- /dev/null
++++ b/drivers/usb/host/xhci-dbgcap.h
+@@ -0,0 +1,229 @@
++
++/**
++ * xhci-dbgcap.h - xHCI debug capability support
++ *
++ * Copyright (C) 2017 Intel Corporation
++ *
++ * Author: Lu Baolu <baolu.lu@linux.intel.com>
++ */
++#ifndef __LINUX_XHCI_DBGCAP_H
++#define __LINUX_XHCI_DBGCAP_H
++
++#include <linux/tty.h>
++#include <linux/kfifo.h>
++
++struct dbc_regs {
++	__le32	capability;
++	__le32	doorbell;
++	__le32	ersts;		/* Event Ring Segment Table Size*/
++	__le32	__reserved_0;	/* 0c~0f reserved bits */
++	__le64	erstba;		/* Event Ring Segment Table Base Address */
++	__le64	erdp;		/* Event Ring Dequeue Pointer */
++	__le32	control;
++	__le32	status;
++	__le32	portsc;		/* Port status and control */
++	__le32	__reserved_1;	/* 2b~28 reserved bits */
++	__le64	dccp;		/* Debug Capability Context Pointer */
++	__le32	devinfo1;	/* Device Descriptor Info Register 1 */
++	__le32	devinfo2;	/* Device Descriptor Info Register 2 */
++};
++
++struct dbc_info_context {
++	__le64	string0;
++	__le64	manufacturer;
++	__le64	product;
++	__le64	serial;
++	__le32	length;
++	__le32	__reserved_0[7];
++};
++
++#define DBC_CTRL_DBC_RUN		BIT(0)
++#define DBC_CTRL_PORT_ENABLE		BIT(1)
++#define DBC_CTRL_HALT_OUT_TR		BIT(2)
++#define DBC_CTRL_HALT_IN_TR		BIT(3)
++#define DBC_CTRL_DBC_RUN_CHANGE		BIT(4)
++#define DBC_CTRL_DBC_ENABLE		BIT(31)
++#define DBC_CTRL_MAXBURST(p)		(((p) >> 16) & 0xff)
++#define DBC_DOOR_BELL_TARGET(p)		(((p) & 0xff) << 8)
++
++#define DBC_MAX_PACKET			1024
++#define DBC_MAX_STRING_LENGTH		64
++#define DBC_STRING_MANUFACTURER		"Linux Foundation"
++#define DBC_STRING_PRODUCT		"Linux USB Debug Target"
++#define DBC_STRING_SERIAL		"0001"
++#define	DBC_CONTEXT_SIZE		64
++
++/*
++ * Port status:
++ */
++#define DBC_PORTSC_CONN_STATUS		BIT(0)
++#define DBC_PORTSC_PORT_ENABLED		BIT(1)
++#define DBC_PORTSC_CONN_CHANGE		BIT(17)
++#define DBC_PORTSC_RESET_CHANGE		BIT(21)
++#define DBC_PORTSC_LINK_CHANGE		BIT(22)
++#define DBC_PORTSC_CONFIG_CHANGE	BIT(23)
++
++struct dbc_str_descs {
++	char	string0[DBC_MAX_STRING_LENGTH];
++	char	manufacturer[DBC_MAX_STRING_LENGTH];
++	char	product[DBC_MAX_STRING_LENGTH];
++	char	serial[DBC_MAX_STRING_LENGTH];
++};
++
++#define DBC_PROTOCOL			1	/* GNU Remote Debug Command */
++#define DBC_VENDOR_ID			0x1d6b	/* Linux Foundation 0x1d6b */
++#define DBC_PRODUCT_ID			0x0010	/* device 0010 */
++#define DBC_DEVICE_REV			0x0010	/* 0.10 */
++
++enum dbc_state {
++	DS_DISABLED = 0,
++	DS_INITIALIZED,
++	DS_ENABLED,
++	DS_CONNECTED,
++	DS_CONFIGURED,
++	DS_STALLED,
++};
++
++struct dbc_request {
++	void				*buf;
++	unsigned int			length;
++	dma_addr_t			dma;
++	void				(*complete)(struct xhci_hcd *xhci,
++						    struct dbc_request *req);
++	struct list_head		list_pool;
++	int				status;
++	unsigned int			actual;
++
++	struct dbc_ep			*dep;
++	struct list_head		list_pending;
++	dma_addr_t			trb_dma;
++	union xhci_trb			*trb;
++	unsigned			direction:1;
++};
++
++struct dbc_ep {
++	struct xhci_dbc			*dbc;
++	struct list_head		list_pending;
++	struct xhci_ring		*ring;
++	unsigned			direction:1;
++};
++
++#define DBC_QUEUE_SIZE			16
++#define DBC_WRITE_BUF_SIZE		8192
++
++/*
++ * Private structure for DbC hardware state:
++ */
++struct dbc_port {
++	struct tty_port			port;
++	spinlock_t			port_lock;	/* port access */
++
++	struct list_head		read_pool;
++	struct list_head		read_queue;
++	unsigned int			n_read;
++	struct tasklet_struct		push;
++
++	struct list_head		write_pool;
++	struct kfifo			write_fifo;
++
++	bool				registered;
++	struct dbc_ep			*in;
++	struct dbc_ep			*out;
++};
++
++struct xhci_dbc {
++	spinlock_t			lock;		/* device access */
++	struct xhci_hcd			*xhci;
++	struct dbc_regs __iomem		*regs;
++	struct xhci_ring		*ring_evt;
++	struct xhci_ring		*ring_in;
++	struct xhci_ring		*ring_out;
++	struct xhci_erst		erst;
++	struct xhci_container_ctx	*ctx;
++
++	struct dbc_str_descs		*string;
++	dma_addr_t			string_dma;
++	size_t				string_size;
++
++	enum dbc_state			state;
++	struct delayed_work		event_work;
++	unsigned			resume_required:1;
++	struct dbc_ep			eps[2];
++
++	struct dbc_port			port;
++};
++
++#define dbc_bulkout_ctx(d)		\
++	((struct xhci_ep_ctx *)((d)->ctx->bytes + DBC_CONTEXT_SIZE))
++#define dbc_bulkin_ctx(d)		\
++	((struct xhci_ep_ctx *)((d)->ctx->bytes + DBC_CONTEXT_SIZE * 2))
++#define dbc_bulkout_enq(d)		\
++	xhci_trb_virt_to_dma((d)->ring_out->enq_seg, (d)->ring_out->enqueue)
++#define dbc_bulkin_enq(d)		\
++	xhci_trb_virt_to_dma((d)->ring_in->enq_seg, (d)->ring_in->enqueue)
++#define dbc_epctx_info2(t, p, b)	\
++	cpu_to_le32(EP_TYPE(t) | MAX_PACKET(p) | MAX_BURST(b))
++#define dbc_ep_dma_direction(d)		\
++	((d)->direction ? DMA_FROM_DEVICE : DMA_TO_DEVICE)
++
++#define BULK_OUT			0
++#define BULK_IN				1
++#define EPID_OUT			2
++#define EPID_IN				3
++
++enum evtreturn {
++	EVT_ERR	= -1,
++	EVT_DONE,
++	EVT_GSER,
++	EVT_DISC,
++};
++
++static inline struct dbc_ep *get_in_ep(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	return &dbc->eps[BULK_IN];
++}
++
++static inline struct dbc_ep *get_out_ep(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	return &dbc->eps[BULK_OUT];
++}
++
++#ifdef CONFIG_USB_XHCI_DBGCAP
++int xhci_dbc_init(struct xhci_hcd *xhci);
++void xhci_dbc_exit(struct xhci_hcd *xhci);
++int xhci_dbc_tty_register_driver(struct xhci_hcd *xhci);
++void xhci_dbc_tty_unregister_driver(void);
++int xhci_dbc_tty_register_device(struct xhci_hcd *xhci);
++void xhci_dbc_tty_unregister_device(struct xhci_hcd *xhci);
++struct dbc_request *dbc_alloc_request(struct dbc_ep *dep, gfp_t gfp_flags);
++void dbc_free_request(struct dbc_ep *dep, struct dbc_request *req);
++int dbc_ep_queue(struct dbc_ep *dep, struct dbc_request *req, gfp_t gfp_flags);
++#ifdef CONFIG_PM
++int xhci_dbc_suspend(struct xhci_hcd *xhci);
++int xhci_dbc_resume(struct xhci_hcd *xhci);
++#endif /* CONFIG_PM */
++#else
++static inline int xhci_dbc_init(struct xhci_hcd *xhci)
++{
++	return 0;
++}
++
++static inline void xhci_dbc_exit(struct xhci_hcd *xhci)
++{
++}
++
++static inline int xhci_dbc_suspend(struct xhci_hcd *xhci)
++{
++	return 0;
++}
++
++static inline int xhci_dbc_resume(struct xhci_hcd *xhci)
++{
++	return 0;
++}
++#endif /* CONFIG_USB_XHCI_DBGCAP */
++#endif /* __LINUX_XHCI_DBGCAP_H */
+diff --git a/drivers/usb/host/xhci-dbgtty.c b/drivers/usb/host/xhci-dbgtty.c
+new file mode 100644
+index 000000000000..48811d72a94c
+--- /dev/null
++++ b/drivers/usb/host/xhci-dbgtty.c
+@@ -0,0 +1,497 @@
++/**
++ * xhci-dbgtty.c - tty glue for xHCI debug capability
++ *
++ * Copyright (C) 2017 Intel Corporation
++ *
++ * Author: Lu Baolu <baolu.lu@linux.intel.com>
++ */
++
++#include <linux/slab.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++
++#include "xhci.h"
++#include "xhci-dbgcap.h"
++
++static unsigned int
++dbc_send_packet(struct dbc_port *port, char *packet, unsigned int size)
++{
++	unsigned int		len;
++
++	len = kfifo_len(&port->write_fifo);
++	if (len < size)
++		size = len;
++	if (size != 0)
++		size = kfifo_out(&port->write_fifo, packet, size);
++	return size;
++}
++
++static int dbc_start_tx(struct dbc_port *port)
++	__releases(&port->port_lock)
++	__acquires(&port->port_lock)
++{
++	int			len;
++	struct dbc_request	*req;
++	int			status = 0;
++	bool			do_tty_wake = false;
++	struct list_head	*pool = &port->write_pool;
++
++	while (!list_empty(pool)) {
++		req = list_entry(pool->next, struct dbc_request, list_pool);
++		len = dbc_send_packet(port, req->buf, DBC_MAX_PACKET);
++		if (len == 0)
++			break;
++		do_tty_wake = true;
++
++		req->length = len;
++		list_del(&req->list_pool);
++
++		spin_unlock(&port->port_lock);
++		status = dbc_ep_queue(port->out, req, GFP_ATOMIC);
++		spin_lock(&port->port_lock);
++
++		if (status) {
++			list_add(&req->list_pool, pool);
++			break;
++		}
++	}
++
++	if (do_tty_wake && port->port.tty)
++		tty_wakeup(port->port.tty);
++
++	return status;
++}
++
++static void dbc_start_rx(struct dbc_port *port)
++	__releases(&port->port_lock)
++	__acquires(&port->port_lock)
++{
++	struct dbc_request	*req;
++	int			status;
++	struct list_head	*pool = &port->read_pool;
++
++	while (!list_empty(pool)) {
++		if (!port->port.tty)
++			break;
++
++		req = list_entry(pool->next, struct dbc_request, list_pool);
++		list_del(&req->list_pool);
++		req->length = DBC_MAX_PACKET;
++
++		spin_unlock(&port->port_lock);
++		status = dbc_ep_queue(port->in, req, GFP_ATOMIC);
++		spin_lock(&port->port_lock);
++
++		if (status) {
++			list_add(&req->list_pool, pool);
++			break;
++		}
++	}
++}
++
++static void
++dbc_read_complete(struct xhci_hcd *xhci, struct dbc_request *req)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++	struct dbc_port		*port = &dbc->port;
++
++	spin_lock(&port->port_lock);
++	list_add_tail(&req->list_pool, &port->read_queue);
++	tasklet_schedule(&port->push);
++	spin_unlock(&port->port_lock);
++}
++
++static void dbc_write_complete(struct xhci_hcd *xhci, struct dbc_request *req)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++	struct dbc_port		*port = &dbc->port;
++
++	spin_lock(&port->port_lock);
++	list_add(&req->list_pool, &port->write_pool);
++	switch (req->status) {
++	case 0:
++		dbc_start_tx(port);
++		break;
++	case -ESHUTDOWN:
++		break;
++	default:
++		xhci_warn(xhci, "unexpected write complete status %d\n",
++			  req->status);
++		break;
++	}
++	spin_unlock(&port->port_lock);
++}
++
++void xhci_dbc_free_req(struct dbc_ep *dep, struct dbc_request *req)
++{
++	kfree(req->buf);
++	dbc_free_request(dep, req);
++}
++
++static int
++xhci_dbc_alloc_requests(struct dbc_ep *dep, struct list_head *head,
++			void (*fn)(struct xhci_hcd *, struct dbc_request *))
++{
++	int			i;
++	struct dbc_request	*req;
++
++	for (i = 0; i < DBC_QUEUE_SIZE; i++) {
++		req = dbc_alloc_request(dep, GFP_ATOMIC);
++		if (!req)
++			break;
++
++		req->length = DBC_MAX_PACKET;
++		req->buf = kmalloc(req->length, GFP_KERNEL);
++		if (!req->buf) {
++			xhci_dbc_free_req(dep, req);
++			break;
++		}
++
++		req->complete = fn;
++		list_add_tail(&req->list_pool, head);
++	}
++
++	return list_empty(head) ? -ENOMEM : 0;
++}
++
++static void
++xhci_dbc_free_requests(struct dbc_ep *dep, struct list_head *head)
++{
++	struct dbc_request	*req;
++
++	while (!list_empty(head)) {
++		req = list_entry(head->next, struct dbc_request, list_pool);
++		list_del(&req->list_pool);
++		xhci_dbc_free_req(dep, req);
++	}
++}
++
++static int dbc_tty_install(struct tty_driver *driver, struct tty_struct *tty)
++{
++	struct dbc_port		*port = driver->driver_state;
++
++	tty->driver_data = port;
++
++	return tty_port_install(&port->port, driver, tty);
++}
++
++static int dbc_tty_open(struct tty_struct *tty, struct file *file)
++{
++	struct dbc_port		*port = tty->driver_data;
++
++	return tty_port_open(&port->port, tty, file);
++}
++
++static void dbc_tty_close(struct tty_struct *tty, struct file *file)
++{
++	struct dbc_port		*port = tty->driver_data;
++
++	tty_port_close(&port->port, tty, file);
++}
++
++static int dbc_tty_write(struct tty_struct *tty,
++			 const unsigned char *buf,
++			 int count)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	if (count)
++		count = kfifo_in(&port->write_fifo, buf, count);
++	dbc_start_tx(port);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return count;
++}
++
++static int dbc_tty_put_char(struct tty_struct *tty, unsigned char ch)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++	int			status;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	status = kfifo_put(&port->write_fifo, ch);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return status;
++}
++
++static void dbc_tty_flush_chars(struct tty_struct *tty)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	dbc_start_tx(port);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++}
++
++static int dbc_tty_write_room(struct tty_struct *tty)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++	int			room = 0;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	room = kfifo_avail(&port->write_fifo);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return room;
++}
++
++static int dbc_tty_chars_in_buffer(struct tty_struct *tty)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++	int			chars = 0;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	chars = kfifo_len(&port->write_fifo);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return chars;
++}
++
++static void dbc_tty_unthrottle(struct tty_struct *tty)
++{
++	struct dbc_port		*port = tty->driver_data;
++	unsigned long		flags;
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	tasklet_schedule(&port->push);
++	spin_unlock_irqrestore(&port->port_lock, flags);
++}
++
++static const struct tty_operations dbc_tty_ops = {
++	.install		= dbc_tty_install,
++	.open			= dbc_tty_open,
++	.close			= dbc_tty_close,
++	.write			= dbc_tty_write,
++	.put_char		= dbc_tty_put_char,
++	.flush_chars		= dbc_tty_flush_chars,
++	.write_room		= dbc_tty_write_room,
++	.chars_in_buffer	= dbc_tty_chars_in_buffer,
++	.unthrottle		= dbc_tty_unthrottle,
++};
++
++static struct tty_driver *dbc_tty_driver;
++
++int xhci_dbc_tty_register_driver(struct xhci_hcd *xhci)
++{
++	int			status;
++	struct xhci_dbc		*dbc = xhci->dbc;
++
++	dbc_tty_driver = tty_alloc_driver(1, TTY_DRIVER_REAL_RAW |
++					  TTY_DRIVER_DYNAMIC_DEV);
++	if (IS_ERR(dbc_tty_driver)) {
++		status = PTR_ERR(dbc_tty_driver);
++		dbc_tty_driver = NULL;
++		return status;
++	}
++
++	dbc_tty_driver->driver_name = "dbc_serial";
++	dbc_tty_driver->name = "ttyDBC";
++
++	dbc_tty_driver->type = TTY_DRIVER_TYPE_SERIAL;
++	dbc_tty_driver->subtype = SERIAL_TYPE_NORMAL;
++	dbc_tty_driver->init_termios = tty_std_termios;
++	dbc_tty_driver->init_termios.c_cflag =
++			B9600 | CS8 | CREAD | HUPCL | CLOCAL;
++	dbc_tty_driver->init_termios.c_ispeed = 9600;
++	dbc_tty_driver->init_termios.c_ospeed = 9600;
++	dbc_tty_driver->driver_state = &dbc->port;
++
++	tty_set_operations(dbc_tty_driver, &dbc_tty_ops);
++
++	status = tty_register_driver(dbc_tty_driver);
++	if (status) {
++		xhci_err(xhci,
++			 "can't register dbc tty driver, err %d\n", status);
++		put_tty_driver(dbc_tty_driver);
++		dbc_tty_driver = NULL;
++	}
++
++	return status;
++}
++
++void xhci_dbc_tty_unregister_driver(void)
++{
++	tty_unregister_driver(dbc_tty_driver);
++	put_tty_driver(dbc_tty_driver);
++	dbc_tty_driver = NULL;
++}
++
++static void dbc_rx_push(unsigned long _port)
++{
++	struct dbc_request	*req;
++	struct tty_struct	*tty;
++	bool			do_push = false;
++	bool			disconnect = false;
++	struct dbc_port		*port = (void *)_port;
++	struct list_head	*queue = &port->read_queue;
++
++	spin_lock_irq(&port->port_lock);
++	tty = port->port.tty;
++	while (!list_empty(queue)) {
++		req = list_first_entry(queue, struct dbc_request, list_pool);
++
++		if (tty && tty_throttled(tty))
++			break;
++
++		switch (req->status) {
++		case 0:
++			break;
++		case -ESHUTDOWN:
++			disconnect = true;
++			break;
++		default:
++			pr_warn("ttyDBC0: unexpected RX status %d\n",
++				req->status);
++			break;
++		}
++
++		if (req->actual) {
++			char		*packet = req->buf;
++			unsigned int	n, size = req->actual;
++			int		count;
++
++			n = port->n_read;
++			if (n) {
++				packet += n;
++				size -= n;
++			}
++
++			count = tty_insert_flip_string(&port->port, packet,
++						       size);
++			if (count)
++				do_push = true;
++			if (count != size) {
++				port->n_read += count;
++				break;
++			}
++			port->n_read = 0;
++		}
++
++		list_move(&req->list_pool, &port->read_pool);
++	}
++
++	if (do_push)
++		tty_flip_buffer_push(&port->port);
++
++	if (!list_empty(queue) && tty) {
++		if (!tty_throttled(tty)) {
++			if (do_push)
++				tasklet_schedule(&port->push);
++			else
++				pr_warn("ttyDBC0: RX not scheduled?\n");
++		}
++	}
++
++	if (!disconnect)
++		dbc_start_rx(port);
++
++	spin_unlock_irq(&port->port_lock);
++}
++
++static int dbc_port_activate(struct tty_port *_port, struct tty_struct *tty)
++{
++	struct dbc_port	*port = container_of(_port, struct dbc_port, port);
++
++	spin_lock_irq(&port->port_lock);
++	dbc_start_rx(port);
++	spin_unlock_irq(&port->port_lock);
++
++	return 0;
++}
++
++static const struct tty_port_operations dbc_port_ops = {
++	.activate =	dbc_port_activate,
++};
++
++static void
++xhci_dbc_tty_init_port(struct xhci_hcd *xhci, struct dbc_port *port)
++{
++	tty_port_init(&port->port);
++	spin_lock_init(&port->port_lock);
++	tasklet_init(&port->push, dbc_rx_push, (unsigned long)port);
++	INIT_LIST_HEAD(&port->read_pool);
++	INIT_LIST_HEAD(&port->read_queue);
++	INIT_LIST_HEAD(&port->write_pool);
++
++	port->in =		get_in_ep(xhci);
++	port->out =		get_out_ep(xhci);
++	port->port.ops =	&dbc_port_ops;
++	port->n_read =		0;
++}
++
++static void
++xhci_dbc_tty_exit_port(struct dbc_port *port)
++{
++	tasklet_kill(&port->push);
++	tty_port_destroy(&port->port);
++}
++
++int xhci_dbc_tty_register_device(struct xhci_hcd *xhci)
++{
++	int			ret;
++	struct device		*tty_dev;
++	struct xhci_dbc		*dbc = xhci->dbc;
++	struct dbc_port		*port = &dbc->port;
++
++	xhci_dbc_tty_init_port(xhci, port);
++	tty_dev = tty_port_register_device(&port->port,
++					   dbc_tty_driver, 0, NULL);
++	ret = IS_ERR_OR_NULL(tty_dev);
++	if (ret)
++		goto register_fail;
++
++	ret = kfifo_alloc(&port->write_fifo, DBC_WRITE_BUF_SIZE, GFP_KERNEL);
++	if (ret)
++		goto buf_alloc_fail;
++
++	ret = xhci_dbc_alloc_requests(port->in, &port->read_pool,
++				      dbc_read_complete);
++	if (ret)
++		goto request_fail;
++
++	ret = xhci_dbc_alloc_requests(port->out, &port->write_pool,
++				      dbc_write_complete);
++	if (ret)
++		goto request_fail;
++
++	port->registered = true;
++
++	return 0;
++
++request_fail:
++	xhci_dbc_free_requests(port->in, &port->read_pool);
++	xhci_dbc_free_requests(port->out, &port->write_pool);
++	kfifo_free(&port->write_fifo);
++
++buf_alloc_fail:
++	tty_unregister_device(dbc_tty_driver, 0);
++
++register_fail:
++	xhci_dbc_tty_exit_port(port);
++
++	xhci_err(xhci, "can't register tty port, err %d\n", ret);
++
++	return ret;
++}
++
++void xhci_dbc_tty_unregister_device(struct xhci_hcd *xhci)
++{
++	struct xhci_dbc		*dbc = xhci->dbc;
++	struct dbc_port		*port = &dbc->port;
++
++	tty_unregister_device(dbc_tty_driver, 0);
++	xhci_dbc_tty_exit_port(port);
++	port->registered = false;
++
++	kfifo_free(&port->write_fifo);
++	xhci_dbc_free_requests(get_out_ep(xhci), &port->read_pool);
++	xhci_dbc_free_requests(get_out_ep(xhci), &port->read_queue);
++	xhci_dbc_free_requests(get_in_ep(xhci), &port->write_pool);
++}
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index f6cbf6190c60..d09a838058ee 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -23,6 +23,7 @@
+ 
+ #include <linux/tracepoint.h>
+ #include "xhci.h"
++#include "xhci-dbgcap.h"
+ 
+ #define XHCI_MSG_MAX	500
+ 
+@@ -155,6 +156,21 @@ DEFINE_EVENT(xhci_log_trb, xhci_queue_trb,
+ 	TP_ARGS(ring, trb)
+ );
+ 
++DEFINE_EVENT(xhci_log_trb, xhci_dbc_handle_event,
++	TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb),
++	TP_ARGS(ring, trb)
++);
++
++DEFINE_EVENT(xhci_log_trb, xhci_dbc_handle_transfer,
++	TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb),
++	TP_ARGS(ring, trb)
++);
++
++DEFINE_EVENT(xhci_log_trb, xhci_dbc_gadget_ep_queue,
++	TP_PROTO(struct xhci_ring *ring, struct xhci_generic_trb *trb),
++	TP_ARGS(ring, trb)
++);
++
+ DECLARE_EVENT_CLASS(xhci_log_free_virt_dev,
+ 	TP_PROTO(struct xhci_virt_device *vdev),
+ 	TP_ARGS(vdev),
+@@ -504,6 +520,49 @@ DEFINE_EVENT(xhci_log_portsc, xhci_handle_port_status,
+ 	     TP_ARGS(portnum, portsc)
+ );
+ 
++DECLARE_EVENT_CLASS(xhci_dbc_log_request,
++	TP_PROTO(struct dbc_request *req),
++	TP_ARGS(req),
++	TP_STRUCT__entry(
++		__field(struct dbc_request *, req)
++		__field(bool, dir)
++		__field(unsigned int, actual)
++		__field(unsigned int, length)
++		__field(int, status)
++	),
++	TP_fast_assign(
++		__entry->req = req;
++		__entry->dir = req->direction;
++		__entry->actual = req->actual;
++		__entry->length = req->length;
++		__entry->status = req->status;
++	),
++	TP_printk("%s: req %p length %u/%u ==> %d",
++		__entry->dir ? "bulk-in" : "bulk-out",
++		__entry->req, __entry->actual,
++		__entry->length, __entry->status
++	)
++);
++
++DEFINE_EVENT(xhci_dbc_log_request, xhci_dbc_alloc_request,
++	TP_PROTO(struct dbc_request *req),
++	TP_ARGS(req)
++);
++
++DEFINE_EVENT(xhci_dbc_log_request, xhci_dbc_free_request,
++	TP_PROTO(struct dbc_request *req),
++	TP_ARGS(req)
++);
++
++DEFINE_EVENT(xhci_dbc_log_request, xhci_dbc_queue_request,
++	TP_PROTO(struct dbc_request *req),
++	TP_ARGS(req)
++);
++
++DEFINE_EVENT(xhci_dbc_log_request, xhci_dbc_giveback_request,
++	TP_PROTO(struct dbc_request *req),
++	TP_ARGS(req)
++);
+ #endif /* __XHCI_TRACE_H */
+ 
+ /* this part must be outside header guard */
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 7dafd44cf1c2..86a0aa13cc6e 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -21,6 +21,7 @@
+ #include "xhci-trace.h"
+ #include "xhci-mtk.h"
+ #include "xhci-debugfs.h"
++#include "xhci-dbgcap.h"
+ 
+ #define DRIVER_AUTHOR "Sarah Sharp"
+ #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
+@@ -622,6 +623,8 @@ int xhci_run(struct usb_hcd *hcd)
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"Finished xhci_run for USB2 roothub");
+ 
++	xhci_dbc_init(xhci);
++
+ 	xhci_debugfs_init(xhci);
+ 
+ 	return 0;
+@@ -654,6 +657,8 @@ static void xhci_stop(struct usb_hcd *hcd)
+ 
+ 	xhci_debugfs_exit(xhci);
+ 
++	xhci_dbc_exit(xhci);
++
+ 	spin_lock_irq(&xhci->lock);
+ 	xhci->xhc_state |= XHCI_STATE_HALTED;
+ 	xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
+@@ -905,6 +910,8 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
+ 			xhci->shared_hcd->state != HC_STATE_SUSPENDED)
+ 		return -EINVAL;
+ 
++	xhci_dbc_suspend(xhci);
++
+ 	/* Clear root port wake on bits if wakeup not allowed. */
+ 	if (!do_wakeup)
+ 		xhci_disable_port_wake_on_bits(xhci);
+@@ -1108,6 +1115,8 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
+ 
+ 	spin_unlock_irq(&xhci->lock);
+ 
++	xhci_dbc_resume(xhci);
++
+  done:
+ 	if (retval == 0) {
+ 		/* Resume root hubs only when have pending events. */
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 8fa92c813026..2852ed52575b 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1862,6 +1862,7 @@ struct xhci_hcd {
+ 	struct dentry		*debugfs_slots;
+ 	struct list_head	regset_list;
+ 
++	void			*dbc;
+ 	/* platform-specific data -- must come last */
+ 	unsigned long		priv[0] __aligned(sizeof(s64));
+ };
+-- 
+2.19.0
+
diff --git a/patches/0528-usb-xhci-Cleanup-printk-debug-message-for-registers.patch b/patches/0528-usb-xhci-Cleanup-printk-debug-message-for-registers.patch
new file mode 100644
index 00000000000000..b5aa976af97463
--- /dev/null
+++ b/patches/0528-usb-xhci-Cleanup-printk-debug-message-for-registers.patch
@@ -0,0 +1,378 @@
+From 38ab74d2df8639f0a4490a18f30b99381f04f480 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:11 +0200
+Subject: [PATCH 0528/1795] usb: xhci: Cleanup printk debug message for
+ registers
+
+The content of each register has been exposed through debugfs.
+There is no need to dump register content with printk in code
+lines. Remove them to make code more concise and readable.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 4c116cb138977838786257f039003eb76a05dc7a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-dbg.c | 243 ------------------------------------
+ drivers/usb/host/xhci-mem.c |   4 -
+ drivers/usb/host/xhci.c     |   6 -
+ drivers/usb/host/xhci.h     |   5 -
+ 4 files changed, 258 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
+index 584d7b9a3683..f20ef2ef1cb2 100644
+--- a/drivers/usb/host/xhci-dbg.c
++++ b/drivers/usb/host/xhci-dbg.c
+@@ -10,238 +10,6 @@
+ 
+ #include "xhci.h"
+ 
+-#define XHCI_INIT_VALUE 0x0
+-
+-/* Add verbose debugging later, just print everything for now */
+-
+-void xhci_dbg_regs(struct xhci_hcd *xhci)
+-{
+-	u32 temp;
+-
+-	xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
+-			xhci->cap_regs);
+-	temp = readl(&xhci->cap_regs->hc_capbase);
+-	xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
+-			&xhci->cap_regs->hc_capbase, temp);
+-	xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
+-			(unsigned int) HC_LENGTH(temp));
+-	xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
+-			(unsigned int) HC_VERSION(temp));
+-
+-	xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
+-
+-	temp = readl(&xhci->cap_regs->run_regs_off);
+-	xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
+-			&xhci->cap_regs->run_regs_off,
+-			(unsigned int) temp & RTSOFF_MASK);
+-	xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
+-
+-	temp = readl(&xhci->cap_regs->db_off);
+-	xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
+-	xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
+-}
+-
+-static void xhci_print_cap_regs(struct xhci_hcd *xhci)
+-{
+-	u32 temp;
+-	u32 hci_version;
+-
+-	xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
+-
+-	temp = readl(&xhci->cap_regs->hc_capbase);
+-	hci_version = HC_VERSION(temp);
+-	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
+-			(unsigned int) temp);
+-	xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
+-			(unsigned int) HC_LENGTH(temp));
+-	xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);
+-
+-	temp = readl(&xhci->cap_regs->hcs_params1);
+-	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
+-			(unsigned int) temp);
+-	xhci_dbg(xhci, "  Max device slots: %u\n",
+-			(unsigned int) HCS_MAX_SLOTS(temp));
+-	xhci_dbg(xhci, "  Max interrupters: %u\n",
+-			(unsigned int) HCS_MAX_INTRS(temp));
+-	xhci_dbg(xhci, "  Max ports: %u\n",
+-			(unsigned int) HCS_MAX_PORTS(temp));
+-
+-	temp = readl(&xhci->cap_regs->hcs_params2);
+-	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
+-			(unsigned int) temp);
+-	xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
+-			(unsigned int) HCS_IST(temp));
+-	xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
+-			(unsigned int) HCS_ERST_MAX(temp));
+-
+-	temp = readl(&xhci->cap_regs->hcs_params3);
+-	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
+-			(unsigned int) temp);
+-	xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
+-			(unsigned int) HCS_U1_LATENCY(temp));
+-	xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
+-			(unsigned int) HCS_U2_LATENCY(temp));
+-
+-	temp = readl(&xhci->cap_regs->hcc_params);
+-	xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
+-	xhci_dbg(xhci, "  HC generates %s bit addresses\n",
+-			HCC_64BIT_ADDR(temp) ? "64" : "32");
+-	xhci_dbg(xhci, "  HC %s Contiguous Frame ID Capability\n",
+-			HCC_CFC(temp) ? "has" : "hasn't");
+-	xhci_dbg(xhci, "  HC %s generate Stopped - Short Package event\n",
+-			HCC_SPC(temp) ? "can" : "can't");
+-	/* FIXME */
+-	xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
+-
+-	temp = readl(&xhci->cap_regs->run_regs_off);
+-	xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
+-
+-	/* xhci 1.1 controllers have the HCCPARAMS2 register */
+-	if (hci_version > 0x100) {
+-		temp = readl(&xhci->cap_regs->hcc_params2);
+-		xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);
+-		xhci_dbg(xhci, "  HC %s Force save context capability",
+-			 HCC2_FSC(temp) ? "supports" : "doesn't support");
+-		xhci_dbg(xhci, "  HC %s Large ESIT Payload Capability",
+-			 HCC2_LEC(temp) ? "supports" : "doesn't support");
+-		xhci_dbg(xhci, "  HC %s Extended TBC capability",
+-			 HCC2_ETC(temp) ? "supports" : "doesn't support");
+-	}
+-}
+-
+-static void xhci_print_command_reg(struct xhci_hcd *xhci)
+-{
+-	u32 temp;
+-
+-	temp = readl(&xhci->op_regs->command);
+-	xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
+-	xhci_dbg(xhci, "  HC is %s\n",
+-			(temp & CMD_RUN) ? "running" : "being stopped");
+-	xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
+-			(temp & CMD_RESET) ? "not " : "");
+-	xhci_dbg(xhci, "  Event Interrupts %s\n",
+-			(temp & CMD_EIE) ? "enabled " : "disabled");
+-	xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
+-			(temp & CMD_HSEIE) ? "enabled " : "disabled");
+-	xhci_dbg(xhci, "  HC has %sfinished light reset\n",
+-			(temp & CMD_LRESET) ? "not " : "");
+-}
+-
+-static void xhci_print_status(struct xhci_hcd *xhci)
+-{
+-	u32 temp;
+-
+-	temp = readl(&xhci->op_regs->status);
+-	xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
+-	xhci_dbg(xhci, "  Event ring is %sempty\n",
+-			(temp & STS_EINT) ? "not " : "");
+-	xhci_dbg(xhci, "  %sHost System Error\n",
+-			(temp & STS_FATAL) ? "WARNING: " : "No ");
+-	xhci_dbg(xhci, "  HC is %s\n",
+-			(temp & STS_HALT) ? "halted" : "running");
+-}
+-
+-static void xhci_print_op_regs(struct xhci_hcd *xhci)
+-{
+-	xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
+-	xhci_print_command_reg(xhci);
+-	xhci_print_status(xhci);
+-}
+-
+-static void xhci_print_ports(struct xhci_hcd *xhci)
+-{
+-	__le32 __iomem *addr;
+-	int i, j;
+-	int ports;
+-	char *names[NUM_PORT_REGS] = {
+-		"status",
+-		"power",
+-		"link",
+-		"reserved",
+-	};
+-
+-	ports = HCS_MAX_PORTS(xhci->hcs_params1);
+-	addr = &xhci->op_regs->port_status_base;
+-	for (i = 0; i < ports; i++) {
+-		for (j = 0; j < NUM_PORT_REGS; j++) {
+-			xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
+-					addr, names[j],
+-					(unsigned int) readl(addr));
+-			addr++;
+-		}
+-	}
+-}
+-
+-void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
+-{
+-	struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
+-	void __iomem *addr;
+-	u32 temp;
+-	u64 temp_64;
+-
+-	addr = &ir_set->irq_pending;
+-	temp = readl(addr);
+-	if (temp == XHCI_INIT_VALUE)
+-		return;
+-
+-	xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
+-
+-	xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
+-			(unsigned int)temp);
+-
+-	addr = &ir_set->irq_control;
+-	temp = readl(addr);
+-	xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
+-			(unsigned int)temp);
+-
+-	addr = &ir_set->erst_size;
+-	temp = readl(addr);
+-	xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
+-			(unsigned int)temp);
+-
+-	addr = &ir_set->rsvd;
+-	temp = readl(addr);
+-	if (temp != XHCI_INIT_VALUE)
+-		xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
+-				addr, (unsigned int)temp);
+-
+-	addr = &ir_set->erst_base;
+-	temp_64 = xhci_read_64(xhci, addr);
+-	xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
+-			addr, temp_64);
+-
+-	addr = &ir_set->erst_dequeue;
+-	temp_64 = xhci_read_64(xhci, addr);
+-	xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
+-			addr, temp_64);
+-}
+-
+-void xhci_print_run_regs(struct xhci_hcd *xhci)
+-{
+-	u32 temp;
+-	int i;
+-
+-	xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
+-	temp = readl(&xhci->run_regs->microframe_index);
+-	xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
+-			&xhci->run_regs->microframe_index,
+-			(unsigned int) temp);
+-	for (i = 0; i < 7; i++) {
+-		temp = readl(&xhci->run_regs->rsvd[i]);
+-		if (temp != XHCI_INIT_VALUE)
+-			xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
+-					&xhci->run_regs->rsvd[i],
+-					i, (unsigned int) temp);
+-	}
+-}
+-
+-void xhci_print_registers(struct xhci_hcd *xhci)
+-{
+-	xhci_print_cap_regs(xhci);
+-	xhci_print_op_regs(xhci);
+-	xhci_print_ports(xhci);
+-}
+-
+ void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
+ {
+ 	u64 addr = erst->erst_dma_addr;
+@@ -260,17 +28,6 @@ void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
+ 	}
+ }
+ 
+-void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
+-{
+-	u64 val;
+-
+-	val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
+-	xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
+-			lower_32_bits(val));
+-	xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
+-			upper_32_bits(val));
+-}
+-
+ char *xhci_get_slot_state(struct xhci_hcd *xhci,
+ 		struct xhci_container_ctx *ctx)
+ {
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 7d6b33c89a2e..42247bf87b21 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -2469,7 +2469,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"// Setting command ring address to 0x%016llx", val_64);
+ 	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
+-	xhci_dbg_cmd_ptrs(xhci);
+ 
+ 	xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags);
+ 	if (!xhci->lpm_command)
+@@ -2487,8 +2486,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 			"// Doorbell array is located at offset 0x%x"
+ 			" from cap regs base addr", val);
+ 	xhci->dba = (void __iomem *) xhci->cap_regs + val;
+-	xhci_dbg_regs(xhci);
+-	xhci_print_run_regs(xhci);
+ 	/* Set ir_set to interrupt register set 0 */
+ 	xhci->ir_set = &xhci->run_regs->ir_set[0];
+ 
+@@ -2532,7 +2529,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+ 	xhci_set_hc_event_deq(xhci);
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"Wrote ERST address to ir_set 0.");
+-	xhci_print_ir_set(xhci, 0);
+ 
+ 	/*
+ 	 * XXX: Might need to set the Interrupter Moderation Register to
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 86a0aa13cc6e..b2238ca1c925 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -574,8 +574,6 @@ int xhci_run(struct usb_hcd *hcd)
+ 	if (ret)
+ 		return ret;
+ 
+-	xhci_dbg_cmd_ptrs(xhci);
+-
+ 	xhci_dbg(xhci, "ERST memory map follows:\n");
+ 	xhci_dbg_erst(xhci, &xhci->erst);
+ 	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
+@@ -606,7 +604,6 @@ int xhci_run(struct usb_hcd *hcd)
+ 			"// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
+ 			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
+ 	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
+-	xhci_print_ir_set(xhci, 0);
+ 
+ 	if (xhci->quirks & XHCI_NEC_HOST) {
+ 		struct xhci_command *command;
+@@ -686,7 +683,6 @@ static void xhci_stop(struct usb_hcd *hcd)
+ 	writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
+ 	temp = readl(&xhci->ir_set->irq_pending);
+ 	writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
+-	xhci_print_ir_set(xhci, 0);
+ 
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
+ 	xhci_mem_cleanup(xhci);
+@@ -1064,7 +1060,6 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
+ 		writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
+ 		temp = readl(&xhci->ir_set->irq_pending);
+ 		writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
+-		xhci_print_ir_set(xhci, 0);
+ 
+ 		xhci_dbg(xhci, "cleaning up memory\n");
+ 		xhci_mem_cleanup(xhci);
+@@ -4883,7 +4878,6 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 	xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
+ 	if (xhci->hci_version > 0x100)
+ 		xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
+-	xhci_print_registers(xhci);
+ 
+ 	xhci->quirks |= quirks;
+ 
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 2852ed52575b..9760e54ecd4d 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1931,12 +1931,7 @@ static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
+ }
+ 
+ /* xHCI debugging */
+-void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
+-void xhci_print_registers(struct xhci_hcd *xhci);
+-void xhci_dbg_regs(struct xhci_hcd *xhci);
+-void xhci_print_run_regs(struct xhci_hcd *xhci);
+ void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
+-void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
+ char *xhci_get_slot_state(struct xhci_hcd *xhci,
+ 		struct xhci_container_ctx *ctx);
+ void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
+-- 
+2.19.0
+
diff --git a/patches/0529-usb-xhci-Cleanup-printk-debug-message-for-ERST.patch b/patches/0529-usb-xhci-Cleanup-printk-debug-message-for-ERST.patch
new file mode 100644
index 00000000000000..cc4d1dc8634785
--- /dev/null
+++ b/patches/0529-usb-xhci-Cleanup-printk-debug-message-for-ERST.patch
@@ -0,0 +1,78 @@
+From 33440e3b5db548f59d032496475aa12c482c7146 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:12 +0200
+Subject: [PATCH 0529/1795] usb: xhci: Cleanup printk debug message for ERST
+
+Each event segment has been exposed through debugfs. There is no
+need to dump ERST content with printk in code. Remove it to make
+code more concise and readable.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 3054ea45fb8758b7c1a4849001e213e1267452fa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-dbg.c | 18 ------------------
+ drivers/usb/host/xhci.c     |  2 --
+ drivers/usb/host/xhci.h     |  1 -
+ 3 files changed, 21 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
+index f20ef2ef1cb2..386abf26641d 100644
+--- a/drivers/usb/host/xhci-dbg.c
++++ b/drivers/usb/host/xhci-dbg.c
+@@ -10,24 +10,6 @@
+ 
+ #include "xhci.h"
+ 
+-void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
+-{
+-	u64 addr = erst->erst_dma_addr;
+-	int i;
+-	struct xhci_erst_entry *entry;
+-
+-	for (i = 0; i < erst->num_entries; i++) {
+-		entry = &erst->entries[i];
+-		xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
+-			 addr,
+-			 lower_32_bits(le64_to_cpu(entry->seg_addr)),
+-			 upper_32_bits(le64_to_cpu(entry->seg_addr)),
+-			 le32_to_cpu(entry->seg_size),
+-			 le32_to_cpu(entry->rsvd));
+-		addr += sizeof(*entry);
+-	}
+-}
+-
+ char *xhci_get_slot_state(struct xhci_hcd *xhci,
+ 		struct xhci_container_ctx *ctx)
+ {
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index b2238ca1c925..786cca0eb73c 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -574,8 +574,6 @@ int xhci_run(struct usb_hcd *hcd)
+ 	if (ret)
+ 		return ret;
+ 
+-	xhci_dbg(xhci, "ERST memory map follows:\n");
+-	xhci_dbg_erst(xhci, &xhci->erst);
+ 	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
+ 	temp_64 &= ~ERST_PTR_MASK;
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 9760e54ecd4d..68f314e49d07 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1931,7 +1931,6 @@ static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
+ }
+ 
+ /* xHCI debugging */
+-void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
+ char *xhci_get_slot_state(struct xhci_hcd *xhci,
+ 		struct xhci_container_ctx *ctx);
+ void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
+-- 
+2.19.0
+
diff --git a/patches/0530-usb-xhci-allow-imod-interval-to-be-configurable.patch b/patches/0530-usb-xhci-allow-imod-interval-to-be-configurable.patch
new file mode 100644
index 00000000000000..4052532f3f95b0
--- /dev/null
+++ b/patches/0530-usb-xhci-allow-imod-interval-to-be-configurable.patch
@@ -0,0 +1,158 @@
+From 48c4d3e94ccc93e9f060794186a0fba0f540113e Mon Sep 17 00:00:00 2001
+From: Adam Wallis <awallis@codeaurora.org>
+Date: Fri, 8 Dec 2017 17:59:13 +0200
+Subject: [PATCH 0530/1795] usb: xhci: allow imod-interval to be configurable
+
+The xHCI driver currently has the IMOD set to 160, which
+translates to an IMOD interval of 40,000ns (160 * 250)ns
+
+Commit 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller")
+introduced a QUIRK for the MTK platform to adjust this interval to 20,
+which translates to an IMOD interval of 5,000ns (20 * 250)ns. This is
+due to the fact that the MTK controller IMOD interval is 8 times
+as much as defined in xHCI spec.
+
+Instead of adding more quirk bits for additional platforms, this patch
+introduces the ability for vendors to set the IMOD_INTERVAL as is
+optimal for their platform. By using device_property_read_u32() on
+"imod-interval-ns", the IMOD INTERVAL can be specified in nano seconds.
+If no interval is specified, the default of 40,000ns (IMOD=160) will be
+used.
+
+No bounds checking has been implemented due to the fact that a vendor
+may have violated the spec and would need to specify a value outside of
+the max 8,000 IRQs/second limit specified in the xHCI spec.
+
+Tested-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Adam Wallis <awallis@codeaurora.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ab725cbec3e83dc29cc00b733bd26063b588fa98)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/usb/mediatek,mtk-xhci.txt        | 2 ++
+ Documentation/devicetree/bindings/usb/usb-xhci.txt       | 1 +
+ drivers/usb/host/xhci-mtk.c                              | 9 +++++++++
+ drivers/usb/host/xhci-pci.c                              | 3 +++
+ drivers/usb/host/xhci-plat.c                             | 5 +++++
+ drivers/usb/host/xhci.c                                  | 6 +-----
+ drivers/usb/host/xhci.h                                  | 2 ++
+ 7 files changed, 23 insertions(+), 5 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+index 5611a2e4ddf0..c008e8d9aa99 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+@@ -43,6 +43,7 @@ Optional properties:
+  - pinctrl-names : a pinctrl state named "default" must be defined
+  - pinctrl-0 : pin control group
+ 	See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
++ - imod-interval-ns: default interrupt moderation interval is 5000ns
+ 
+ Example:
+ usb30: usb@11270000 {
+@@ -65,6 +66,7 @@ usb30: usb@11270000 {
+ 	usb3-lpm-capable;
+ 	mediatek,syscon-wakeup = <&pericfg>;
+ 	mediatek,wakeup-src = <1>;
++	imod-interval-ns = <10000>;
+ };
+ 
+ 2nd: dual-role mode with xHCI driver
+diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+index ff4747219638..1651483a7048 100644
+--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+@@ -32,6 +32,7 @@ Optional properties:
+   - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
+   - usb3-lpm-capable: determines if platform is USB3 LPM capable
+   - quirk-broken-port-ped: set if the controller has broken port disable mechanism
++  - imod-interval-ns: default interrupt moderation interval is 5000ns
+ 
+ Example:
+ 	usb@f0931000 {
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 95f583f41bfd..c9eb0fc18f4d 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -661,6 +661,15 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+ 
+ 	xhci = hcd_to_xhci(hcd);
+ 	xhci->main_hcd = hcd;
++
++	/*
++	 * imod_interval is the interrupt moderation value in nanoseconds.
++	 * The increment interval is 8 times as much as that defined in
++	 * the xHCI spec on MTK's controller.
++	 */
++	xhci->imod_interval = 5000;
++	device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
++
+ 	xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
+ 			dev_name(dev), hcd);
+ 	if (!xhci->shared_hcd) {
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index c3ae5784649a..93ce34bce7b5 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -254,6 +254,9 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
+ 	if (!xhci->sbrn)
+ 		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
+ 
++	/* imod_interval is the interrupt moderation value in nanoseconds. */
++	xhci->imod_interval = 40000;
++
+ 	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
+ 	if (retval)
+ 		return retval;
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 833ca511fd35..c435df29cdb8 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -269,6 +269,11 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
+ 		xhci->quirks |= XHCI_BROKEN_PORT_PED;
+ 
++	/* imod_interval is the interrupt moderation value in nanoseconds. */
++	xhci->imod_interval = 40000;
++	device_property_read_u32(sysdev, "imod-interval-ns",
++				 &xhci->imod_interval);
++
+ 	hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 0);
+ 	if (IS_ERR(hcd->usb_phy)) {
+ 		ret = PTR_ERR(hcd->usb_phy);
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 786cca0eb73c..34bc8a678bd5 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -583,11 +583,7 @@ int xhci_run(struct usb_hcd *hcd)
+ 			"// Set the interrupt modulation register");
+ 	temp = readl(&xhci->ir_set->irq_control);
+ 	temp &= ~ER_IRQ_INTERVAL_MASK;
+-	/*
+-	 * the increment interval is 8 times as much as that defined
+-	 * in xHCI spec on MTK's controller
+-	 */
+-	temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
++	temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
+ 	writel(temp, &xhci->ir_set->irq_control);
+ 
+ 	/* Set the HCD state before we enable the irqs */
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 68f314e49d07..2961d1020981 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1722,6 +1722,8 @@ struct xhci_hcd {
+ 	u8		max_interrupters;
+ 	u8		max_ports;
+ 	u8		isoc_threshold;
++	/* imod_interval in ns (I * 250ns) */
++	u32		imod_interval;
+ 	int		event_ring_max;
+ 	/* 4KB min, 128MB max */
+ 	int		page_size;
+-- 
+2.19.0
+
diff --git a/patches/0531-xhci-add-port-status-tracing-for-Get-Port-Status-hub.patch b/patches/0531-xhci-add-port-status-tracing-for-Get-Port-Status-hub.patch
new file mode 100644
index 00000000000000..4795a6d91f9a39
--- /dev/null
+++ b/patches/0531-xhci-add-port-status-tracing-for-Get-Port-Status-hub.patch
@@ -0,0 +1,50 @@
+From e5c75dbff074ac8c050940aeacfe02ea15726a1a Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:14 +0200
+Subject: [PATCH 0531/1795] xhci: add port status tracing for Get Port Status
+ hub requests
+
+Add tracing showing the port status register content each time
+the xhci roothub receives a Get Port Status request.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 28c06e58602fe48eb03ec8d4bdd005094fb6a31f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c   | 1 +
+ drivers/usb/host/xhci-trace.h | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index a6ac7c5200fe..cb725a2c9529 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -1076,6 +1076,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			retval = -ENODEV;
+ 			break;
+ 		}
++		trace_xhci_get_port_status(wIndex, temp);
+ 		status = xhci_get_port_status(hcd, bus_state, port_array,
+ 				wIndex, temp, flags);
+ 		if (status == 0xffffffff)
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index d09a838058ee..3d5b6bde9168 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -520,6 +520,11 @@ DEFINE_EVENT(xhci_log_portsc, xhci_handle_port_status,
+ 	     TP_ARGS(portnum, portsc)
+ );
+ 
++DEFINE_EVENT(xhci_log_portsc, xhci_get_port_status,
++	     TP_PROTO(u32 portnum, u32 portsc),
++	     TP_ARGS(portnum, portsc)
++);
++
+ DECLARE_EVENT_CLASS(xhci_dbc_log_request,
+ 	TP_PROTO(struct dbc_request *req),
+ 	TP_ARGS(req),
+-- 
+2.19.0
+
diff --git a/patches/0532-xhci-add-port-status-tracing-for-Get-Hub-Status-requ.patch b/patches/0532-xhci-add-port-status-tracing-for-Get-Hub-Status-requ.patch
new file mode 100644
index 00000000000000..0687b96ebb272c
--- /dev/null
+++ b/patches/0532-xhci-add-port-status-tracing-for-Get-Hub-Status-requ.patch
@@ -0,0 +1,51 @@
+From 3dd8f8c52ec822e55cd7f0b4fdb19420c2a43976 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 8 Dec 2017 17:59:15 +0200
+Subject: [PATCH 0532/1795] xhci: add port status tracing for Get Hub Status
+ requests
+
+Trace the port status of each port of a roothub when
+the xhci roothub receives a Get Hub Status request.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 3f8499ac7cd838199eacd9d9a002e37227f1f2c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c   | 2 ++
+ drivers/usb/host/xhci-trace.h | 5 +++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index cb725a2c9529..b66440501d0c 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -1443,6 +1443,8 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+ 			retval = -ENODEV;
+ 			break;
+ 		}
++		trace_xhci_hub_status_data(i, temp);
++
+ 		if ((temp & mask) != 0 ||
+ 			(bus_state->port_c_suspend & 1 << i) ||
+ 			(bus_state->resume_done[i] && time_after_eq(
+diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h
+index 3d5b6bde9168..88b427434bd8 100644
+--- a/drivers/usb/host/xhci-trace.h
++++ b/drivers/usb/host/xhci-trace.h
+@@ -525,6 +525,11 @@ DEFINE_EVENT(xhci_log_portsc, xhci_get_port_status,
+ 	     TP_ARGS(portnum, portsc)
+ );
+ 
++DEFINE_EVENT(xhci_log_portsc, xhci_hub_status_data,
++	     TP_PROTO(u32 portnum, u32 portsc),
++	     TP_ARGS(portnum, portsc)
++);
++
+ DECLARE_EVENT_CLASS(xhci_dbc_log_request,
+ 	TP_PROTO(struct dbc_request *req),
+ 	TP_ARGS(req),
+-- 
+2.19.0
+
diff --git a/patches/0533-USB-host-Use-zeroing-memory-allocator-rather-than-al.patch b/patches/0533-USB-host-Use-zeroing-memory-allocator-rather-than-al.patch
new file mode 100644
index 00000000000000..cbb6beeedf92f9
--- /dev/null
+++ b/patches/0533-USB-host-Use-zeroing-memory-allocator-rather-than-al.patch
@@ -0,0 +1,71 @@
+From e035c77ade411e8b3911c20f1fb710f0fff82014 Mon Sep 17 00:00:00 2001
+From: Himanshu Jha <himanshujha199640@gmail.com>
+Date: Sun, 31 Dec 2017 01:33:52 +0530
+Subject: [PATCH 0533/1795] USB: host: Use zeroing memory allocator rather than
+ allocator/memset
+
+Use dma_zalloc_coherent for allocating zeroed
+memory and remove unnecessary memset function.
+
+Done using Coccinelle.
+Generated-by: scripts/coccinelle/api/alloc/kzalloc-simple.cocci
+0-day tested with no failures.
+
+Suggested-by: Luis R. Rodriguez <mcgrof@kernel.org>
+Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com>
+Acked-by: Alan Stern <stern@rowland.harvard.edu>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 2b80a29bf83d2baed1a22193647bafcc6a0426af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/uhci-hcd.c | 3 +--
+ drivers/usb/host/xhci-mem.c | 7 ++-----
+ 2 files changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
+index babeefd84ffd..a064e37b8178 100644
+--- a/drivers/usb/host/uhci-hcd.c
++++ b/drivers/usb/host/uhci-hcd.c
+@@ -601,7 +601,7 @@ static int uhci_start(struct usb_hcd *hcd)
+ 	uhci->dentry = dentry;
+ #endif
+ 
+-	uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
++	uhci->frame = dma_zalloc_coherent(uhci_dev(uhci),
+ 			UHCI_NUMFRAMES * sizeof(*uhci->frame),
+ 			&uhci->frame_dma_handle, GFP_KERNEL);
+ 	if (!uhci->frame) {
+@@ -609,7 +609,6 @@ static int uhci_start(struct usb_hcd *hcd)
+ 			"unable to allocate consistent memory for frame list\n");
+ 		goto err_alloc_frame;
+ 	}
+-	memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
+ 
+ 	uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
+ 			GFP_KERNEL);
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 42247bf87b21..0b424a4b58ec 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -1784,14 +1784,11 @@ int xhci_alloc_erst(struct xhci_hcd *xhci,
+ 	struct xhci_erst_entry *entry;
+ 
+ 	size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs;
+-	erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
+-					   size,
+-					   &erst->erst_dma_addr,
+-					   flags);
++	erst->entries = dma_zalloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
++					    size, &erst->erst_dma_addr, flags);
+ 	if (!erst->entries)
+ 		return -ENOMEM;
+ 
+-	memset(erst->entries, 0, size);
+ 	erst->num_entries = evt_ring->num_segs;
+ 
+ 	seg = evt_ring->first_seg;
+-- 
+2.19.0
+
diff --git a/patches/0534-xhci-Don-t-print-a-warning-when-setting-link-state-f.patch b/patches/0534-xhci-Don-t-print-a-warning-when-setting-link-state-f.patch
new file mode 100644
index 00000000000000..465ceeb7856e90
--- /dev/null
+++ b/patches/0534-xhci-Don-t-print-a-warning-when-setting-link-state-f.patch
@@ -0,0 +1,64 @@
+From 146e27738ef892bf2ff09b33e16748a54d4c0eb7 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 12 Feb 2018 14:24:47 +0200
+Subject: [PATCH 0534/1795] xhci: Don't print a warning when setting link state
+ for disabled ports
+
+When disabling a USB3 port the hub driver will set the port link state to
+U3 to prevent "ejected" or "safely removed" devices that are still
+physically connected from immediately re-enumerating.
+
+If the device was really unplugged, then error messages were printed
+as the hub tries to set the U3 link state for a port that is no longer
+enabled.
+
+xhci-hcd ee000000.usb: Cannot set link state.
+usb usb8-port1: cannot disable (err = -32)
+
+Don't print error message in xhci-hub if hub tries to set port link state
+for a disabled port. Return -ENODEV instead which also silences hub driver.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1208d8a84fdcae6b395c57911cdf907450d30e70)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index b66440501d0c..32cd52ca8318 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -1224,17 +1224,17 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 				temp = readl(port_array[wIndex]);
+ 				break;
+ 			}
+-
+-			/* Software should not attempt to set
+-			 * port link state above '3' (U3) and the port
+-			 * must be enabled.
+-			 */
+-			if ((temp & PORT_PE) == 0 ||
+-				(link_state > USB_SS_PORT_LS_U3)) {
+-				xhci_warn(xhci, "Cannot set link state.\n");
++			/* Port must be enabled */
++			if (!(temp & PORT_PE)) {
++				retval = -ENODEV;
++				break;
++			}
++			/* Can't set port link state above '3' (U3) */
++			if (link_state > USB_SS_PORT_LS_U3) {
++				xhci_warn(xhci, "Cannot set port %d link state %d\n",
++					 wIndex, link_state);
+ 				goto error;
+ 			}
+-
+ 			if (link_state == USB_SS_PORT_LS_U3) {
+ 				slot_id = xhci_find_slot_id_by_port(hcd, xhci,
+ 						wIndex + 1);
+-- 
+2.19.0
+
diff --git a/patches/0535-xhci-Fix-xhci-debugfs-devices-node-disappearance-aft.patch b/patches/0535-xhci-Fix-xhci-debugfs-devices-node-disappearance-aft.patch
new file mode 100644
index 00000000000000..270c4a0710676c
--- /dev/null
+++ b/patches/0535-xhci-Fix-xhci-debugfs-devices-node-disappearance-aft.patch
@@ -0,0 +1,43 @@
+From 179be30727d6b52c3a93e2579eceb3d830953d40 Mon Sep 17 00:00:00 2001
+From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Date: Mon, 12 Feb 2018 14:24:49 +0200
+Subject: [PATCH 0535/1795] xhci: Fix xhci debugfs devices node disappearance
+ after hibernation
+
+During system resume from hibernation, xhci host is reset, all the
+nodes in devices folder are removed in xhci_mem_cleanup function.
+Later nodes in /sys/kernel/debug/usb/xhci/* are created again in
+function xhci_run, but the nodes already exist, so the nodes still
+keep the old ones, finally device nodes in xhci debugfs folder
+/sys/kernel/debug/usb/xhci/*/devices/* are disappeared.
+
+This fix removed xhci debugfs nodes before the nodes are re-created,
+so all the nodes in xhci debugfs can be re-created successfully.
+
+Fixes: 02b6fdc2a153 ("usb: xhci: Add debugfs interface for xHCI driver")
+Cc: <stable@vger.kernel.org> # v4.15
+Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d91676717261578f429d3577dbe9154b26e8abf7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 34bc8a678bd5..a25e0827941e 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -1057,6 +1057,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
+ 
+ 		xhci_dbg(xhci, "cleaning up memory\n");
+ 		xhci_mem_cleanup(xhci);
++		xhci_debugfs_exit(xhci);
+ 		xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
+ 			    readl(&xhci->op_regs->status));
+ 
+-- 
+2.19.0
+
diff --git a/patches/0536-xhci-xhci-debugfs-device-nodes-weren-t-removed-after.patch b/patches/0536-xhci-xhci-debugfs-device-nodes-weren-t-removed-after.patch
new file mode 100644
index 00000000000000..92486468530db4
--- /dev/null
+++ b/patches/0536-xhci-xhci-debugfs-device-nodes-weren-t-removed-after.patch
@@ -0,0 +1,47 @@
+From be0b3125f282dc83b0b33f76fc62734cef2436e1 Mon Sep 17 00:00:00 2001
+From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Date: Mon, 12 Feb 2018 14:24:50 +0200
+Subject: [PATCH 0536/1795] xhci: xhci debugfs device nodes weren't removed
+ after device plugged out
+
+There is a bug after plugged out USB device, the device and its ep00
+nodes are still kept, we need to remove the nodes in xhci_free_dev when
+USB device is plugged out.
+
+Fixes: 052f71e25a7e ("xhci: Fix xhci debugfs NULL pointer dereference in resume from hibernate")
+Cc: <stable@vger.kernel.org> # v4.15
+Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 8c5a93ebf7ac56d47f879b3c7c2f8c83b40c2cdb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/host/xhci.c
+---
+ drivers/usb/host/xhci.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index a25e0827941e..72ab7148c99b 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3588,12 +3588,11 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 		del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
+ 	}
+ 
++	xhci_debugfs_remove_slot(xhci, udev->slot_id);
+ 	virt_dev->udev = NULL;
+ 	ret = xhci_disable_slot(xhci, udev->slot_id);
+-	if (ret) {
+-		xhci_debugfs_remove_slot(xhci, udev->slot_id);
++	if (ret)
+ 		xhci_free_virt_device(xhci, udev->slot_id);
+-	}
+ }
+ 
+ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
+-- 
+2.19.0
+
diff --git a/patches/0537-xhci-fix-xhci-debugfs-errors-in-xhci_stop.patch b/patches/0537-xhci-fix-xhci-debugfs-errors-in-xhci_stop.patch
new file mode 100644
index 00000000000000..1cb71f14f4dcdf
--- /dev/null
+++ b/patches/0537-xhci-fix-xhci-debugfs-errors-in-xhci_stop.patch
@@ -0,0 +1,52 @@
+From 8532b5b51a4678830633cf3fabc2ce78f4c5caff Mon Sep 17 00:00:00 2001
+From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Date: Mon, 12 Feb 2018 14:24:51 +0200
+Subject: [PATCH 0537/1795] xhci: fix xhci debugfs errors in xhci_stop
+
+In function xhci_stop, xhci_debugfs_exit called before xhci_mem_cleanup.
+xhci_debugfs_exit removed the xhci debugfs root nodes, xhci_mem_cleanup
+called function xhci_free_virt_devices_depth_first which in turn called
+function xhci_debugfs_remove_slot.
+Function xhci_debugfs_remove_slot removed the nodes for devices, the nodes
+folders are sub folder of xhci debugfs.
+
+It is unreasonable to remove xhci debugfs root folder before
+xhci debugfs sub folder. Function xhci_mem_cleanup should be called
+before function xhci_debugfs_exit.
+
+Fixes: 02b6fdc2a153 ("usb: xhci: Add debugfs interface for xHCI driver")
+Cc: <stable@vger.kernel.org> # v4.15
+Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 11cd764dc9a030991880ad4d51db93918afa5822)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 72ab7148c99b..b365d37aacbf 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -646,8 +646,6 @@ static void xhci_stop(struct usb_hcd *hcd)
+ 		return;
+ 	}
+ 
+-	xhci_debugfs_exit(xhci);
+-
+ 	xhci_dbc_exit(xhci);
+ 
+ 	spin_lock_irq(&xhci->lock);
+@@ -680,6 +678,7 @@ static void xhci_stop(struct usb_hcd *hcd)
+ 
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
+ 	xhci_mem_cleanup(xhci);
++	xhci_debugfs_exit(xhci);
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"xhci_stop completed - status = %x",
+ 			readl(&xhci->op_regs->status));
+-- 
+2.19.0
+
diff --git a/patches/0538-drm-Check-crtc_state-enable-rather-than-crtc-enabled.patch b/patches/0538-drm-Check-crtc_state-enable-rather-than-crtc-enabled.patch
new file mode 100644
index 00000000000000..34a73028014d6e
--- /dev/null
+++ b/patches/0538-drm-Check-crtc_state-enable-rather-than-crtc-enabled.patch
@@ -0,0 +1,372 @@
+From 34bf5a3ee4e40f20273dd41373fedd96d01822e8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Wed, 1 Nov 2017 22:15:58 +0200
+Subject: [PATCH 0538/1795] drm: Check crtc_state->enable rather than
+ crtc->enabled in drm_plane_helper_check_state()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+drm_plane_helper_check_state() is supposed to do things the atomic way,
+so it should not be inspecting crtc->enabled. Rather we should be
+looking at crtc_state->enable.
+
+We have a slight complication due to drm_plane_helper_check_update()
+reusing drm_plane_helper_check_state() for non-atomic drivers. Thus
+we'll have to pass the crtc_state in manally and construct a fake
+crtc_state in drm_plane_helper_check_update().
+
+v2: Fix the WARNs about plane_state->crtc matching crtc_state->crtc
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171101201558.6059-1-ville.syrjala@linux.intel.com
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit 10b47ee02d1ae66160058241cf5b962f64e81b47)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+---
+ drivers/gpu/drm/arm/hdlcd_crtc.c            |  2 +-
+ drivers/gpu/drm/arm/malidp_planes.c         |  3 +-
+ drivers/gpu/drm/drm_plane_helper.c          | 51 ++++++++++++---------
+ drivers/gpu/drm/drm_simple_kms_helper.c     |  2 +-
+ drivers/gpu/drm/i915/intel_display.c        |  2 +
+ drivers/gpu/drm/imx/ipuv3-plane.c           |  2 +-
+ drivers/gpu/drm/mediatek/mtk_drm_plane.c    |  2 +-
+ drivers/gpu/drm/meson/meson_plane.c         |  2 +-
+ drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  4 +-
+ drivers/gpu/drm/nouveau/nv50_display.c      |  6 ++-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  2 +-
+ drivers/gpu/drm/tegra/dc.c                  |  4 +-
+ drivers/gpu/drm/zte/zx_plane.c              |  4 +-
+ include/drm/drm_plane_helper.h              |  3 +-
+ 14 files changed, 51 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
+index 72b22b805412..14721723fa8a 100644
+--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
++++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
+@@ -252,7 +252,7 @@ static int hdlcd_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, &clip,
++	return drm_plane_helper_check_state(state, crtc_state, &clip,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    false, true);
+diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
+index 16b8b310ae5c..1a24fe75007a 100644
+--- a/drivers/gpu/drm/arm/malidp_planes.c
++++ b/drivers/gpu/drm/arm/malidp_planes.c
+@@ -151,7 +151,8 @@ static int malidp_se_check_scaling(struct malidp_plane *mp,
+ 
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+-	ret = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, true, true);
++	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
++					   0, INT_MAX, true, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
+index 06aee1741e96..859be4b65307 100644
+--- a/drivers/gpu/drm/drm_plane_helper.c
++++ b/drivers/gpu/drm/drm_plane_helper.c
+@@ -101,7 +101,8 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
+ 
+ /**
+  * drm_plane_helper_check_state() - Check plane state for validity
+- * @state: plane state to check
++ * @plane_state: plane state to check
++ * @crtc_state: crtc state to check
+  * @clip: integer clipping coordinates
+  * @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
+  * @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
+@@ -120,35 +121,37 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
+  * RETURNS:
+  * Zero if update appears valid, error code on failure
+  */
+-int drm_plane_helper_check_state(struct drm_plane_state *state,
++int drm_plane_helper_check_state(struct drm_plane_state *plane_state,
++				 const struct drm_crtc_state *crtc_state,
+ 				 const struct drm_rect *clip,
+ 				 int min_scale,
+ 				 int max_scale,
+ 				 bool can_position,
+ 				 bool can_update_disabled)
+ {
+-	struct drm_crtc *crtc = state->crtc;
+-	struct drm_framebuffer *fb = state->fb;
+-	struct drm_rect *src = &state->src;
+-	struct drm_rect *dst = &state->dst;
+-	unsigned int rotation = state->rotation;
++	struct drm_framebuffer *fb = plane_state->fb;
++	struct drm_rect *src = &plane_state->src;
++	struct drm_rect *dst = &plane_state->dst;
++	unsigned int rotation = plane_state->rotation;
+ 	int hscale, vscale;
+ 
+-	*src = drm_plane_state_src(state);
+-	*dst = drm_plane_state_dest(state);
++	WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);
++
++	*src = drm_plane_state_src(plane_state);
++	*dst = drm_plane_state_dest(plane_state);
+ 
+ 	if (!fb) {
+-		state->visible = false;
++		plane_state->visible = false;
+ 		return 0;
+ 	}
+ 
+ 	/* crtc should only be NULL when disabling (i.e., !fb) */
+-	if (WARN_ON(!crtc)) {
+-		state->visible = false;
++	if (WARN_ON(!plane_state->crtc)) {
++		plane_state->visible = false;
+ 		return 0;
+ 	}
+ 
+-	if (!crtc->enabled && !can_update_disabled) {
++	if (!crtc_state->enable && !can_update_disabled) {
+ 		DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
+ 		return -EINVAL;
+ 	}
+@@ -160,16 +163,16 @@ int drm_plane_helper_check_state(struct drm_plane_state *state,
+ 	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+ 	if (hscale < 0 || vscale < 0) {
+ 		DRM_DEBUG_KMS("Invalid scaling of plane\n");
+-		drm_rect_debug_print("src: ", &state->src, true);
+-		drm_rect_debug_print("dst: ", &state->dst, false);
++		drm_rect_debug_print("src: ", &plane_state->src, true);
++		drm_rect_debug_print("dst: ", &plane_state->dst, false);
+ 		return -ERANGE;
+ 	}
+ 
+-	state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
++	plane_state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
+ 
+ 	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+ 
+-	if (!state->visible)
++	if (!plane_state->visible)
+ 		/*
+ 		 * Plane isn't visible; some drivers can handle this
+ 		 * so we just return success here.  Drivers that can't
+@@ -230,7 +233,7 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
+ 				  bool can_update_disabled,
+ 				  bool *visible)
+ {
+-	struct drm_plane_state state = {
++	struct drm_plane_state plane_state = {
+ 		.plane = plane,
+ 		.crtc = crtc,
+ 		.fb = fb,
+@@ -245,18 +248,22 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
+ 		.rotation = rotation,
+ 		.visible = *visible,
+ 	};
++	struct drm_crtc_state crtc_state = {
++		.crtc = crtc,
++		.enable = crtc->enabled,
++	};
+ 	int ret;
+ 
+-	ret = drm_plane_helper_check_state(&state, clip,
++	ret = drm_plane_helper_check_state(&plane_state, &crtc_state, clip,
+ 					   min_scale, max_scale,
+ 					   can_position,
+ 					   can_update_disabled);
+ 	if (ret)
+ 		return ret;
+ 
+-	*src = state.src;
+-	*dst = state.dst;
+-	*visible = state.visible;
++	*src = plane_state.src;
++	*dst = plane_state.dst;
++	*visible = plane_state.visible;
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/drm_simple_kms_helper.c b/drivers/gpu/drm/drm_simple_kms_helper.c
+index dc9fd109de14..d428c805025c 100644
+--- a/drivers/gpu/drm/drm_simple_kms_helper.c
++++ b/drivers/gpu/drm/drm_simple_kms_helper.c
+@@ -103,7 +103,7 @@ static int drm_simple_kms_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	ret = drm_plane_helper_check_state(plane_state, &clip,
++	ret = drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   false, true);
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index cf648c526e12..6f33d4465774 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -9401,6 +9401,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
+ 	int ret;
+ 
+ 	ret = drm_plane_helper_check_state(&plane_state->base,
++					   &crtc_state->base,
+ 					   &plane_state->clip,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+@@ -12871,6 +12872,7 @@ intel_check_primary_plane(struct intel_plane *plane,
+ 	}
+ 
+ 	ret = drm_plane_helper_check_state(&state->base,
++					   &crtc_state->base,
+ 					   &state->clip,
+ 					   min_scale, max_scale,
+ 					   can_position, true);
+diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
+index cf98596c7ce1..4ae6ee46a416 100644
+--- a/drivers/gpu/drm/imx/ipuv3-plane.c
++++ b/drivers/gpu/drm/imx/ipuv3-plane.c
+@@ -341,7 +341,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
+ 	clip.y1 = 0;
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+-	ret = drm_plane_helper_check_state(state, &clip,
++	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   can_position, true);
+diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+index 6f121891430f..7ebb33657704 100644
+--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
++++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+@@ -111,7 +111,7 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->mode.hdisplay;
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, &clip,
++	return drm_plane_helper_check_state(state, crtc_state, &clip,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    true, true);
+diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
+index 0b6011b8d632..b4cc8166ca02 100644
+--- a/drivers/gpu/drm/meson/meson_plane.c
++++ b/drivers/gpu/drm/meson/meson_plane.c
+@@ -61,7 +61,7 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->mode.hdisplay;
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, &clip,
++	return drm_plane_helper_check_state(state, crtc_state, &clip,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    true, true);
+diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+index 4b22ac3413a1..1c194a9453d9 100644
+--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
++++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+@@ -348,8 +348,8 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
+ 	min_scale = FRAC_16_16(1, 8);
+ 	max_scale = FRAC_16_16(8, 1);
+ 
+-	ret = drm_plane_helper_check_state(state, &clip, min_scale,
+-					   max_scale, true, true);
++	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
++					   min_scale, max_scale, true, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
+index e558fa480682..deffd6212b51 100644
+--- a/drivers/gpu/drm/nouveau/nv50_display.c
++++ b/drivers/gpu/drm/nouveau/nv50_display.c
+@@ -1143,7 +1143,8 @@ nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
+ {
+ 	int ret;
+ 
+-	ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
++	ret = drm_plane_helper_check_state(&asyw->state, &asyh->state,
++					   &asyw->clip,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   true, true);
+@@ -1432,7 +1433,8 @@ nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
+ 	if (!fb->format->depth)
+ 		return -EINVAL;
+ 
+-	ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
++	ret = drm_plane_helper_check_state(&asyw->state, &asyh->state,
++					   &asyw->clip,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   DRM_PLANE_HELPER_NO_SCALING,
+ 					   false, true);
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index f1fa8d5c9b52..9716b2735fd0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -658,7 +658,7 @@ static int vop_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	ret = drm_plane_helper_check_state(state, &clip,
++	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+ 					   min_scale, max_scale,
+ 					   true, true);
+ 	if (ret)
+diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
+index 4df39112e38e..08b899fd74fc 100644
+--- a/drivers/gpu/drm/tegra/dc.c
++++ b/drivers/gpu/drm/tegra/dc.c
+@@ -500,8 +500,8 @@ static int tegra_plane_state_add(struct tegra_plane *plane,
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+ 	/* Check plane state for visibility and calculate clipping bounds */
+-	err = drm_plane_helper_check_state(state, &clip, 0, INT_MAX,
+-					   true, true);
++	err = drm_plane_helper_check_state(state, crtc_state, &clip,
++					   0, INT_MAX, true, true);
+ 	if (err < 0)
+ 		return err;
+ 
+diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c
+index 18e763493264..ee0002529b8f 100644
+--- a/drivers/gpu/drm/zte/zx_plane.c
++++ b/drivers/gpu/drm/zte/zx_plane.c
+@@ -80,7 +80,7 @@ static int zx_vl_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(plane_state, &clip,
++	return drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+ 					    min_scale, max_scale,
+ 					    true, true);
+ }
+@@ -315,7 +315,7 @@ static int zx_gl_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(plane_state, &clip,
++	return drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    DRM_PLANE_HELPER_NO_SCALING,
+ 					    false, true);
+diff --git a/include/drm/drm_plane_helper.h b/include/drm/drm_plane_helper.h
+index 7c8a00ceadb7..41b8309b0a57 100644
+--- a/include/drm/drm_plane_helper.h
++++ b/include/drm/drm_plane_helper.h
+@@ -38,7 +38,8 @@
+  */
+ #define DRM_PLANE_HELPER_NO_SCALING (1<<16)
+ 
+-int drm_plane_helper_check_state(struct drm_plane_state *state,
++int drm_plane_helper_check_state(struct drm_plane_state *plane_state,
++				 const struct drm_crtc_state *crtc_state,
+ 				 const struct drm_rect *clip,
+ 				 int min_scale, int max_scale,
+ 				 bool can_position,
+-- 
+2.19.0
+
diff --git a/patches/0539-drm-Move-drm_plane_helper_check_state-into-drm_atomi.patch b/patches/0539-drm-Move-drm_plane_helper_check_state-into-drm_atomi.patch
new file mode 100644
index 00000000000000..b70a3c2e8b9730
--- /dev/null
+++ b/patches/0539-drm-Move-drm_plane_helper_check_state-into-drm_atomi.patch
@@ -0,0 +1,578 @@
+From 0f8f8d61840254ad8c0b1647b0492fe4efd4e54d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Wed, 1 Nov 2017 22:16:19 +0200
+Subject: [PATCH 0539/1795] drm: Move drm_plane_helper_check_state() into
+ drm_atomic_helper.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+drm_plane_helper_check_update() isn't a transitional helper, so let's
+rename it to drm_atomic_helper_check_plane_state() and move it into
+drm_atomic_helper.c.
+
+v2: Fix the WARNs about plane_state->crtc matching crtc_state->crtc
+
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Suggested-by: Daniel Vetter <daniel@ffwll.ch>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171101201619.6175-1-ville.syrjala@linux.intel.com
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit a01cb8ba3f6282934cff65e89ab36b18b14cbe27)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+---
+ drivers/gpu/drm/arm/hdlcd_crtc.c            |   8 +-
+ drivers/gpu/drm/arm/malidp_planes.c         |   4 +-
+ drivers/gpu/drm/drm_atomic_helper.c         |  94 ++++++++++++++++++
+ drivers/gpu/drm/drm_plane_helper.c          | 102 +-------------------
+ drivers/gpu/drm/drm_simple_kms_helper.c     |   9 +-
+ drivers/gpu/drm/i915/intel_display.c        |  22 ++---
+ drivers/gpu/drm/imx/ipuv3-plane.c           |   8 +-
+ drivers/gpu/drm/mediatek/mtk_drm_plane.c    |   8 +-
+ drivers/gpu/drm/meson/meson_plane.c         |   8 +-
+ drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |   5 +-
+ drivers/gpu/drm/nouveau/nv50_display.c      |  20 ++--
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   6 +-
+ drivers/gpu/drm/tegra/dc.c                  |   4 +-
+ drivers/gpu/drm/zte/zx_plane.c              |  15 +--
+ include/drm/drm_atomic_helper.h             |   7 ++
+ include/drm/drm_plane_helper.h              |   6 --
+ 16 files changed, 165 insertions(+), 161 deletions(-)
+
+diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
+index 14721723fa8a..63511a3bbf6c 100644
+--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
++++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
+@@ -252,10 +252,10 @@ static int hdlcd_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, crtc_state, &clip,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    false, true);
++	return drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   false, true);
+ }
+ 
+ static void hdlcd_plane_atomic_update(struct drm_plane *plane,
+diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
+index 1a24fe75007a..ae41bced6550 100644
+--- a/drivers/gpu/drm/arm/malidp_planes.c
++++ b/drivers/gpu/drm/arm/malidp_planes.c
+@@ -151,8 +151,8 @@ static int malidp_se_check_scaling(struct malidp_plane *mp,
+ 
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+-	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+-					   0, INT_MAX, true, true);
++	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  0, INT_MAX, true, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
+index 1f08d597b87a..ca3e44daa4b3 100644
+--- a/drivers/gpu/drm/drm_atomic_helper.c
++++ b/drivers/gpu/drm/drm_atomic_helper.c
+@@ -695,6 +695,100 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
+ }
+ EXPORT_SYMBOL(drm_atomic_helper_check_modeset);
+ 
++/**
++ * drm_atomic_helper_check_plane_state() - Check plane state for validity
++ * @plane_state: plane state to check
++ * @crtc_state: crtc state to check
++ * @clip: integer clipping coordinates
++ * @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
++ * @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
++ * @can_position: is it legal to position the plane such that it
++ *                doesn't cover the entire crtc?  This will generally
++ *                only be false for primary planes.
++ * @can_update_disabled: can the plane be updated while the crtc
++ *                       is disabled?
++ *
++ * Checks that a desired plane update is valid, and updates various
++ * bits of derived state (clipped coordinates etc.). Drivers that provide
++ * their own plane handling rather than helper-provided implementations may
++ * still wish to call this function to avoid duplication of error checking
++ * code.
++ *
++ * RETURNS:
++ * Zero if update appears valid, error code on failure
++ */
++int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,
++					const struct drm_crtc_state *crtc_state,
++					const struct drm_rect *clip,
++					int min_scale,
++					int max_scale,
++					bool can_position,
++					bool can_update_disabled)
++{
++	struct drm_framebuffer *fb = plane_state->fb;
++	struct drm_rect *src = &plane_state->src;
++	struct drm_rect *dst = &plane_state->dst;
++	unsigned int rotation = plane_state->rotation;
++	int hscale, vscale;
++
++	WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);
++
++	*src = drm_plane_state_src(plane_state);
++	*dst = drm_plane_state_dest(plane_state);
++
++	if (!fb) {
++		plane_state->visible = false;
++		return 0;
++	}
++
++	/* crtc should only be NULL when disabling (i.e., !fb) */
++	if (WARN_ON(!plane_state->crtc)) {
++		plane_state->visible = false;
++		return 0;
++	}
++
++	if (!crtc_state->enable && !can_update_disabled) {
++		DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
++		return -EINVAL;
++	}
++
++	drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
++
++	/* Check scaling */
++	hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
++	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
++	if (hscale < 0 || vscale < 0) {
++		DRM_DEBUG_KMS("Invalid scaling of plane\n");
++		drm_rect_debug_print("src: ", &plane_state->src, true);
++		drm_rect_debug_print("dst: ", &plane_state->dst, false);
++		return -ERANGE;
++	}
++
++	plane_state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
++
++	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
++
++	if (!plane_state->visible)
++		/*
++		 * Plane isn't visible; some drivers can handle this
++		 * so we just return success here.  Drivers that can't
++		 * (including those that use the primary plane helper's
++		 * update function) will return an error from their
++		 * update_plane handler.
++		 */
++		return 0;
++
++	if (!can_position && !drm_rect_equals(dst, clip)) {
++		DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
++		drm_rect_debug_print("dst: ", dst, false);
++		drm_rect_debug_print("clip: ", clip, false);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_atomic_helper_check_plane_state);
++
+ /**
+  * drm_atomic_helper_check_planes - validate state object for planes changes
+  * @dev: DRM device
+diff --git a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
+index 859be4b65307..afc6c6a365cb 100644
+--- a/drivers/gpu/drm/drm_plane_helper.c
++++ b/drivers/gpu/drm/drm_plane_helper.c
+@@ -99,100 +99,6 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
+ 	return count;
+ }
+ 
+-/**
+- * drm_plane_helper_check_state() - Check plane state for validity
+- * @plane_state: plane state to check
+- * @crtc_state: crtc state to check
+- * @clip: integer clipping coordinates
+- * @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
+- * @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
+- * @can_position: is it legal to position the plane such that it
+- *                doesn't cover the entire crtc?  This will generally
+- *                only be false for primary planes.
+- * @can_update_disabled: can the plane be updated while the crtc
+- *                       is disabled?
+- *
+- * Checks that a desired plane update is valid, and updates various
+- * bits of derived state (clipped coordinates etc.). Drivers that provide
+- * their own plane handling rather than helper-provided implementations may
+- * still wish to call this function to avoid duplication of error checking
+- * code.
+- *
+- * RETURNS:
+- * Zero if update appears valid, error code on failure
+- */
+-int drm_plane_helper_check_state(struct drm_plane_state *plane_state,
+-				 const struct drm_crtc_state *crtc_state,
+-				 const struct drm_rect *clip,
+-				 int min_scale,
+-				 int max_scale,
+-				 bool can_position,
+-				 bool can_update_disabled)
+-{
+-	struct drm_framebuffer *fb = plane_state->fb;
+-	struct drm_rect *src = &plane_state->src;
+-	struct drm_rect *dst = &plane_state->dst;
+-	unsigned int rotation = plane_state->rotation;
+-	int hscale, vscale;
+-
+-	WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);
+-
+-	*src = drm_plane_state_src(plane_state);
+-	*dst = drm_plane_state_dest(plane_state);
+-
+-	if (!fb) {
+-		plane_state->visible = false;
+-		return 0;
+-	}
+-
+-	/* crtc should only be NULL when disabling (i.e., !fb) */
+-	if (WARN_ON(!plane_state->crtc)) {
+-		plane_state->visible = false;
+-		return 0;
+-	}
+-
+-	if (!crtc_state->enable && !can_update_disabled) {
+-		DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
+-		return -EINVAL;
+-	}
+-
+-	drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
+-
+-	/* Check scaling */
+-	hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
+-	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+-	if (hscale < 0 || vscale < 0) {
+-		DRM_DEBUG_KMS("Invalid scaling of plane\n");
+-		drm_rect_debug_print("src: ", &plane_state->src, true);
+-		drm_rect_debug_print("dst: ", &plane_state->dst, false);
+-		return -ERANGE;
+-	}
+-
+-	plane_state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
+-
+-	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+-
+-	if (!plane_state->visible)
+-		/*
+-		 * Plane isn't visible; some drivers can handle this
+-		 * so we just return success here.  Drivers that can't
+-		 * (including those that use the primary plane helper's
+-		 * update function) will return an error from their
+-		 * update_plane handler.
+-		 */
+-		return 0;
+-
+-	if (!can_position && !drm_rect_equals(dst, clip)) {
+-		DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+-		drm_rect_debug_print("dst: ", dst, false);
+-		drm_rect_debug_print("clip: ", clip, false);
+-		return -EINVAL;
+-	}
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(drm_plane_helper_check_state);
+-
+ /**
+  * drm_plane_helper_check_update() - Check plane update for validity
+  * @plane: plane object to update
+@@ -254,10 +160,10 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
+ 	};
+ 	int ret;
+ 
+-	ret = drm_plane_helper_check_state(&plane_state, &crtc_state, clip,
+-					   min_scale, max_scale,
+-					   can_position,
+-					   can_update_disabled);
++	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
++						  clip, min_scale, max_scale,
++						  can_position,
++						  can_update_disabled);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/drm_simple_kms_helper.c b/drivers/gpu/drm/drm_simple_kms_helper.c
+index d428c805025c..9f3b1c94802b 100644
+--- a/drivers/gpu/drm/drm_simple_kms_helper.c
++++ b/drivers/gpu/drm/drm_simple_kms_helper.c
+@@ -103,10 +103,11 @@ static int drm_simple_kms_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	ret = drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   false, true);
++	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
++						  &clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  false, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 6f33d4465774..9b69b6048507 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -9400,12 +9400,12 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
+ 	u32 offset;
+ 	int ret;
+ 
+-	ret = drm_plane_helper_check_state(&plane_state->base,
+-					   &crtc_state->base,
+-					   &plane_state->clip,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   true, true);
++	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
++						  &crtc_state->base,
++						  &plane_state->clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  true, true);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -12871,11 +12871,11 @@ intel_check_primary_plane(struct intel_plane *plane,
+ 		can_position = true;
+ 	}
+ 
+-	ret = drm_plane_helper_check_state(&state->base,
+-					   &crtc_state->base,
+-					   &state->clip,
+-					   min_scale, max_scale,
+-					   can_position, true);
++	ret = drm_atomic_helper_check_plane_state(&state->base,
++						  &crtc_state->base,
++						  &state->clip,
++						  min_scale, max_scale,
++						  can_position, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
+index 4ae6ee46a416..ed422d9cb219 100644
+--- a/drivers/gpu/drm/imx/ipuv3-plane.c
++++ b/drivers/gpu/drm/imx/ipuv3-plane.c
+@@ -341,10 +341,10 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
+ 	clip.y1 = 0;
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+-	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   can_position, true);
++	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  can_position, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+index 7ebb33657704..5ef898b93d8d 100644
+--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
++++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+@@ -111,10 +111,10 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->mode.hdisplay;
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, crtc_state, &clip,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    true, true);
++	return drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   true, true);
+ }
+ 
+ static void mtk_plane_atomic_update(struct drm_plane *plane,
+diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
+index b4cc8166ca02..27bd3503e1e4 100644
+--- a/drivers/gpu/drm/meson/meson_plane.c
++++ b/drivers/gpu/drm/meson/meson_plane.c
+@@ -61,10 +61,10 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->mode.hdisplay;
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(state, crtc_state, &clip,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    true, true);
++	return drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   true, true);
+ }
+ 
+ /* Takes a fixed 16.16 number and converts it to integer. */
+diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+index 1c194a9453d9..df3360acacca 100644
+--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
++++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+@@ -348,8 +348,9 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
+ 	min_scale = FRAC_16_16(1, 8);
+ 	max_scale = FRAC_16_16(8, 1);
+ 
+-	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+-					   min_scale, max_scale, true, true);
++	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  min_scale, max_scale,
++						  true, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
+index deffd6212b51..aa129b8b7d03 100644
+--- a/drivers/gpu/drm/nouveau/nv50_display.c
++++ b/drivers/gpu/drm/nouveau/nv50_display.c
+@@ -1143,11 +1143,11 @@ nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
+ {
+ 	int ret;
+ 
+-	ret = drm_plane_helper_check_state(&asyw->state, &asyh->state,
+-					   &asyw->clip,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   true, true);
++	ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
++						  &asyw->clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  true, true);
+ 	asyh->curs.visible = asyw->state.visible;
+ 	if (ret || !asyh->curs.visible)
+ 		return ret;
+@@ -1433,11 +1433,11 @@ nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
+ 	if (!fb->format->depth)
+ 		return -EINVAL;
+ 
+-	ret = drm_plane_helper_check_state(&asyw->state, &asyh->state,
+-					   &asyw->clip,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   DRM_PLANE_HELPER_NO_SCALING,
+-					   false, true);
++	ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
++						  &asyw->clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  false, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 9716b2735fd0..1534df106020 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -658,9 +658,9 @@ static int vop_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	ret = drm_plane_helper_check_state(state, crtc_state, &clip,
+-					   min_scale, max_scale,
+-					   true, true);
++	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  min_scale, max_scale,
++						  true, true);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
+index 08b899fd74fc..91919d52b207 100644
+--- a/drivers/gpu/drm/tegra/dc.c
++++ b/drivers/gpu/drm/tegra/dc.c
+@@ -500,8 +500,8 @@ static int tegra_plane_state_add(struct tegra_plane *plane,
+ 	clip.y2 = crtc_state->mode.vdisplay;
+ 
+ 	/* Check plane state for visibility and calculate clipping bounds */
+-	err = drm_plane_helper_check_state(state, crtc_state, &clip,
+-					   0, INT_MAX, true, true);
++	err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  0, INT_MAX, true, true);
+ 	if (err < 0)
+ 		return err;
+ 
+diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c
+index ee0002529b8f..68fd2e2dc78a 100644
+--- a/drivers/gpu/drm/zte/zx_plane.c
++++ b/drivers/gpu/drm/zte/zx_plane.c
+@@ -80,9 +80,9 @@ static int zx_vl_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+-					    min_scale, max_scale,
+-					    true, true);
++	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
++						   &clip, min_scale, max_scale,
++						   true, true);
+ }
+ 
+ static int zx_vl_get_fmt(uint32_t format)
+@@ -315,10 +315,11 @@ static int zx_gl_plane_atomic_check(struct drm_plane *plane,
+ 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
+ 
+-	return drm_plane_helper_check_state(plane_state, crtc_state, &clip,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    DRM_PLANE_HELPER_NO_SCALING,
+-					    false, true);
++	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
++						   &clip,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   DRM_PLANE_HELPER_NO_SCALING,
++						   false, true);
+ }
+ 
+ static int zx_gl_get_fmt(uint32_t format)
+diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
+index d2b56cc657e9..4842ee9485ce 100644
+--- a/include/drm/drm_atomic_helper.h
++++ b/include/drm/drm_atomic_helper.h
+@@ -38,6 +38,13 @@ struct drm_private_state;
+ 
+ int drm_atomic_helper_check_modeset(struct drm_device *dev,
+ 				struct drm_atomic_state *state);
++int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,
++					const struct drm_crtc_state *crtc_state,
++					const struct drm_rect *clip,
++					int min_scale,
++					int max_scale,
++					bool can_position,
++					bool can_update_disabled);
+ int drm_atomic_helper_check_planes(struct drm_device *dev,
+ 			       struct drm_atomic_state *state);
+ int drm_atomic_helper_check(struct drm_device *dev,
+diff --git a/include/drm/drm_plane_helper.h b/include/drm/drm_plane_helper.h
+index 41b8309b0a57..8aa49c0ecd4d 100644
+--- a/include/drm/drm_plane_helper.h
++++ b/include/drm/drm_plane_helper.h
+@@ -38,12 +38,6 @@
+  */
+ #define DRM_PLANE_HELPER_NO_SCALING (1<<16)
+ 
+-int drm_plane_helper_check_state(struct drm_plane_state *plane_state,
+-				 const struct drm_crtc_state *crtc_state,
+-				 const struct drm_rect *clip,
+-				 int min_scale, int max_scale,
+-				 bool can_position,
+-				 bool can_update_disabled);
+ int drm_plane_helper_check_update(struct drm_plane *plane,
+ 				  struct drm_crtc *crtc,
+ 				  struct drm_framebuffer *fb,
+-- 
+2.19.0
+
diff --git a/patches/0540-drm-rcar-du-Clip-planes-to-screen-boundaries.patch b/patches/0540-drm-rcar-du-Clip-planes-to-screen-boundaries.patch
new file mode 100644
index 00000000000000..cd8a2eff08e172
--- /dev/null
+++ b/patches/0540-drm-rcar-du-Clip-planes-to-screen-boundaries.patch
@@ -0,0 +1,226 @@
+From bae9695927d00469a50fba764e4c9b834492e3e9 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 Aug 2017 18:52:04 +0300
+Subject: [PATCH 0540/1795] drm: rcar-du: Clip planes to screen boundaries
+
+Unlike the KMS API, the hardware doesn't support planes exceeding the
+screen boundaries or planes being located fully off-screen. We need to
+clip plane coordinates to support the use case.
+
+Fortunately the DRM core offers a drm_atomic_helper_check_plane_state()
+helper that validates the scaling factor and clips the plane
+coordinates. Use it to implement the plane atomic check and use the
+clipped source and destination rectangles from the plane state instead
+of the unclipped source and CRTC coordinates to configure the device.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+(cherry picked from commit 401712e035c699d569dbd37024f4b21dc76cc870)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c  |  3 +-
+ drivers/gpu/drm/rcar-du/rcar_du_plane.c | 50 ++++++++++++++++++-------
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c   | 42 +++++++++++----------
+ 3 files changed, 62 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index b492063a6e1f..5685d5af6998 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -319,7 +319,8 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
+ 		struct rcar_du_plane *plane = &rcrtc->group->planes[i];
+ 		unsigned int j;
+ 
+-		if (plane->plane.state->crtc != &rcrtc->crtc)
++		if (plane->plane.state->crtc != &rcrtc->crtc ||
++		    !plane->plane.state->visible)
+ 			continue;
+ 
+ 		/* Insert the plane in the sorted planes array. */
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+index 4f076c364f25..4a3d16cf3ed6 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+@@ -332,8 +332,8 @@ static void rcar_du_plane_write(struct rcar_du_group *rgrp,
+ static void rcar_du_plane_setup_scanout(struct rcar_du_group *rgrp,
+ 					const struct rcar_du_plane_state *state)
+ {
+-	unsigned int src_x = state->state.src_x >> 16;
+-	unsigned int src_y = state->state.src_y >> 16;
++	unsigned int src_x = state->state.src.x1 >> 16;
++	unsigned int src_y = state->state.src.y1 >> 16;
+ 	unsigned int index = state->hwindex;
+ 	unsigned int pitch;
+ 	bool interlaced;
+@@ -357,7 +357,7 @@ static void rcar_du_plane_setup_scanout(struct rcar_du_group *rgrp,
+ 			dma[i] = gem->paddr + fb->offsets[i];
+ 		}
+ 	} else {
+-		pitch = state->state.src_w >> 16;
++		pitch = drm_rect_width(&state->state.src) >> 16;
+ 		dma[0] = 0;
+ 		dma[1] = 0;
+ 	}
+@@ -521,6 +521,7 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
+ 				       const struct rcar_du_plane_state *state)
+ {
+ 	struct rcar_du_device *rcdu = rgrp->dev;
++	const struct drm_rect *dst = &state->state.dst;
+ 
+ 	if (rcdu->info->gen < 3)
+ 		rcar_du_plane_setup_format_gen2(rgrp, index, state);
+@@ -528,10 +529,10 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
+ 		rcar_du_plane_setup_format_gen3(rgrp, index, state);
+ 
+ 	/* Destination position and size */
+-	rcar_du_plane_write(rgrp, index, PnDSXR, state->state.crtc_w);
+-	rcar_du_plane_write(rgrp, index, PnDSYR, state->state.crtc_h);
+-	rcar_du_plane_write(rgrp, index, PnDPXR, state->state.crtc_x);
+-	rcar_du_plane_write(rgrp, index, PnDPYR, state->state.crtc_y);
++	rcar_du_plane_write(rgrp, index, PnDSXR, drm_rect_width(dst));
++	rcar_du_plane_write(rgrp, index, PnDSYR, drm_rect_height(dst));
++	rcar_du_plane_write(rgrp, index, PnDPXR, dst->x1);
++	rcar_du_plane_write(rgrp, index, PnDPYR, dst->y1);
+ 
+ 	if (rcdu->info->gen < 3) {
+ 		/* Wrap-around and blinking, disabled */
+@@ -570,16 +571,39 @@ int __rcar_du_plane_atomic_check(struct drm_plane *plane,
+ 				 const struct rcar_du_format_info **format)
+ {
+ 	struct drm_device *dev = plane->dev;
++	struct drm_crtc_state *crtc_state;
++	struct drm_rect clip;
++	int ret;
+ 
+-	if (!state->fb || !state->crtc) {
++	if (!state->crtc) {
++		/*
++		 * The visible field is not reset by the DRM core but only
++		 * updated by drm_plane_helper_check_state(), set it manually.
++		 */
++		state->visible = false;
+ 		*format = NULL;
+ 		return 0;
+ 	}
+ 
+-	if (state->src_w >> 16 != state->crtc_w ||
+-	    state->src_h >> 16 != state->crtc_h) {
+-		dev_dbg(dev->dev, "%s: scaling not supported\n", __func__);
+-		return -EINVAL;
++	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
++	if (IS_ERR(crtc_state))
++		return PTR_ERR(crtc_state);
++
++	clip.x1 = 0;
++	clip.y1 = 0;
++	clip.x2 = crtc_state->mode.hdisplay;
++	clip.y2 = crtc_state->mode.vdisplay;
++
++	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  DRM_PLANE_HELPER_NO_SCALING,
++						  true, true);
++	if (ret < 0)
++		return ret;
++
++	if (!state->visible) {
++		*format = NULL;
++		return 0;
+ 	}
+ 
+ 	*format = rcar_du_format_info(state->fb->format->format);
+@@ -607,7 +631,7 @@ static void rcar_du_plane_atomic_update(struct drm_plane *plane,
+ 	struct rcar_du_plane_state *old_rstate;
+ 	struct rcar_du_plane_state *new_rstate;
+ 
+-	if (!plane->state->crtc)
++	if (!plane->state->visible)
+ 		return;
+ 
+ 	rcar_du_plane_setup(rplane);
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index dd66dcb8da23..2c260c33840b 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -55,14 +55,14 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
+ 	struct rcar_du_plane_state state = {
+ 		.state = {
+ 			.crtc = &crtc->crtc,
+-			.crtc_x = 0,
+-			.crtc_y = 0,
+-			.crtc_w = mode->hdisplay,
+-			.crtc_h = mode->vdisplay,
+-			.src_x = 0,
+-			.src_y = 0,
+-			.src_w = mode->hdisplay << 16,
+-			.src_h = mode->vdisplay << 16,
++			.dst.x1 = 0,
++			.dst.y1 = 0,
++			.dst.x2 = mode->hdisplay,
++			.dst.y2 = mode->vdisplay,
++			.src.x1 = 0,
++			.src.y1 = 0,
++			.src.x2 = mode->hdisplay << 16,
++			.src.y2 = mode->vdisplay << 16,
+ 			.zpos = 0,
+ 		},
+ 		.format = rcar_du_format_info(DRM_FORMAT_ARGB8888),
+@@ -178,15 +178,15 @@ static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
+ 	};
+ 	unsigned int i;
+ 
+-	cfg.src.left = state->state.src_x >> 16;
+-	cfg.src.top = state->state.src_y >> 16;
+-	cfg.src.width = state->state.src_w >> 16;
+-	cfg.src.height = state->state.src_h >> 16;
++	cfg.src.left = state->state.src.x1 >> 16;
++	cfg.src.top = state->state.src.y1 >> 16;
++	cfg.src.width = drm_rect_width(&state->state.src) >> 16;
++	cfg.src.height = drm_rect_height(&state->state.src) >> 16;
+ 
+-	cfg.dst.left = state->state.crtc_x;
+-	cfg.dst.top = state->state.crtc_y;
+-	cfg.dst.width = state->state.crtc_w;
+-	cfg.dst.height = state->state.crtc_h;
++	cfg.dst.left = state->state.dst.x1;
++	cfg.dst.top = state->state.dst.y1;
++	cfg.dst.width = drm_rect_width(&state->state.dst);
++	cfg.dst.height = drm_rect_height(&state->state.dst);
+ 
+ 	for (i = 0; i < state->format->planes; ++i)
+ 		cfg.mem[i] = sg_dma_address(state->sg_tables[i].sgl)
+@@ -212,7 +212,11 @@ static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
+ 	unsigned int i;
+ 	int ret;
+ 
+-	if (!state->fb)
++	/*
++	 * There's no need to prepare (and unprepare) the framebuffer when the
++	 * plane is not visible, as it will not be displayed.
++	 */
++	if (!state->visible)
+ 		return 0;
+ 
+ 	for (i = 0; i < rstate->format->planes; ++i) {
+@@ -253,7 +257,7 @@ static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
+ 	struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
+ 	unsigned int i;
+ 
+-	if (!state->fb)
++	if (!state->visible)
+ 		return;
+ 
+ 	for (i = 0; i < rstate->format->planes; ++i) {
+@@ -278,7 +282,7 @@ static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
+ 	struct rcar_du_vsp_plane *rplane = to_rcar_vsp_plane(plane);
+ 	struct rcar_du_crtc *crtc = to_rcar_crtc(old_state->crtc);
+ 
+-	if (plane->state->crtc)
++	if (plane->state->visible)
+ 		rcar_du_vsp_plane_setup(rplane);
+ 	else
+ 		vsp1_du_atomic_update(rplane->vsp->vsp, crtc->vsp_pipe,
+-- 
+2.19.0
+
diff --git a/patches/0541-i2c-add-helpers-to-ease-DMA-handling.patch b/patches/0541-i2c-add-helpers-to-ease-DMA-handling.patch
new file mode 100644
index 00000000000000..2db541d9440858
--- /dev/null
+++ b/patches/0541-i2c-add-helpers-to-ease-DMA-handling.patch
@@ -0,0 +1,94 @@
+From e296c508c0ed3fcbd0c99d66d732af6159e02462 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 4 Nov 2017 21:20:02 +0100
+Subject: [PATCH 0541/1795] i2c: add helpers to ease DMA handling
+
+One helper checks if DMA is suitable and optionally creates a bounce
+buffer, if not. The other function returns the bounce buffer and makes
+sure the data is properly copied back to the message.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit e94bc5d18be03dac8e9d73d30c5523728edeff76)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 46 +++++++++++++++++++++++++++++++++++++
+ include/linux/i2c.h         |  3 +++
+ 2 files changed, 49 insertions(+)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 6334f8837371..bdab78795d1e 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -2248,6 +2248,52 @@ void i2c_put_adapter(struct i2c_adapter *adap)
+ }
+ EXPORT_SYMBOL(i2c_put_adapter);
+ 
++/**
++ * i2c_get_dma_safe_msg_buf() - get a DMA safe buffer for the given i2c_msg
++ * @msg: the message to be checked
++ * @threshold: the minimum number of bytes for which using DMA makes sense
++ *
++ * Return: NULL if a DMA safe buffer was not obtained. Use msg->buf with PIO.
++ *	   Or a valid pointer to be used with DMA. After use, release it by
++ *	   calling i2c_release_dma_safe_msg_buf().
++ *
++ * This function must only be called from process context!
++ */
++u8 *i2c_get_dma_safe_msg_buf(struct i2c_msg *msg, unsigned int threshold)
++{
++	if (msg->len < threshold)
++		return NULL;
++
++	if (msg->flags & I2C_M_DMA_SAFE)
++		return msg->buf;
++
++	pr_debug("using bounce buffer for addr=0x%02x, len=%d\n",
++		 msg->addr, msg->len);
++
++	if (msg->flags & I2C_M_RD)
++		return kzalloc(msg->len, GFP_KERNEL);
++	else
++		return kmemdup(msg->buf, msg->len, GFP_KERNEL);
++}
++EXPORT_SYMBOL_GPL(i2c_get_dma_safe_msg_buf);
++
++/**
++ * i2c_release_dma_safe_msg_buf - release DMA safe buffer and sync with i2c_msg
++ * @msg: the message to be synced with
++ * @buf: the buffer obtained from i2c_get_dma_safe_msg_buf(). May be NULL.
++ */
++void i2c_release_dma_safe_msg_buf(struct i2c_msg *msg, u8 *buf)
++{
++	if (!buf || buf == msg->buf)
++		return;
++
++	if (msg->flags & I2C_M_RD)
++		memcpy(msg->buf, buf, msg->len);
++
++	kfree(buf);
++}
++EXPORT_SYMBOL_GPL(i2c_release_dma_safe_msg_buf);
++
+ MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>");
+ MODULE_DESCRIPTION("I2C-Bus main module");
+ MODULE_LICENSE("GPL");
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index d501d3956f13..1e99342f180f 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -767,6 +767,9 @@ static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
+ 	return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
+ }
+ 
++u8 *i2c_get_dma_safe_msg_buf(struct i2c_msg *msg, unsigned int threshold);
++void i2c_release_dma_safe_msg_buf(struct i2c_msg *msg, u8 *buf);
++
+ int i2c_handle_smbus_host_notify(struct i2c_adapter *adap, unsigned short addr);
+ /**
+  * module_i2c_driver() - Helper macro for registering a modular I2C driver
+-- 
+2.19.0
+
diff --git a/patches/0542-i2c-add-a-message-flag-for-DMA-safe-buffers.patch b/patches/0542-i2c-add-a-message-flag-for-DMA-safe-buffers.patch
new file mode 100644
index 00000000000000..6e1b4871002199
--- /dev/null
+++ b/patches/0542-i2c-add-a-message-flag-for-DMA-safe-buffers.patch
@@ -0,0 +1,36 @@
+From 6a7637c91a845182ebcc18178abcead4341a3f17 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 4 Nov 2017 21:20:01 +0100
+Subject: [PATCH 0542/1795] i2c: add a message flag for DMA safe buffers
+
+I2C has no requirement that the buffer of a message needs to be DMA
+safe. In case it is, it can now be flagged, so drivers wishing to
+do DMA can use the buffer directly.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 521a72e1f2e8141d78e7699eaacda24e308ed428)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/uapi/linux/i2c.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h
+index fe648032d6b9..f71a1751cacf 100644
+--- a/include/uapi/linux/i2c.h
++++ b/include/uapi/linux/i2c.h
+@@ -72,6 +72,9 @@ struct i2c_msg {
+ #define I2C_M_RD		0x0001	/* read data, from slave to master */
+ 					/* I2C_M_RD is guaranteed to be 0x0001! */
+ #define I2C_M_TEN		0x0010	/* this is a ten bit chip address */
++#define I2C_M_DMA_SAFE		0x0200	/* the buffer of this message is DMA safe */
++					/* makes only sense in kernelspace */
++					/* userspace buffers are copied anyway */
+ #define I2C_M_RECV_LEN		0x0400	/* length will be first received byte */
+ #define I2C_M_NO_RD_ACK		0x0800	/* if I2C_FUNC_PROTOCOL_MANGLING */
+ #define I2C_M_IGNORE_NAK	0x1000	/* if I2C_FUNC_PROTOCOL_MANGLING */
+-- 
+2.19.0
+
diff --git a/patches/0543-i2c-sh_mobile-use-core-helper-to-decide-when-to-use-.patch b/patches/0543-i2c-sh_mobile-use-core-helper-to-decide-when-to-use-.patch
new file mode 100644
index 00000000000000..b9b5d2ff209829
--- /dev/null
+++ b/patches/0543-i2c-sh_mobile-use-core-helper-to-decide-when-to-use-.patch
@@ -0,0 +1,63 @@
+From 44f55eb0472b8711fbee7cb4f916b0219013fb5b Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 4 Nov 2017 21:20:08 +0100
+Subject: [PATCH 0543/1795] i2c: sh_mobile: use core helper to decide when to
+ use DMA
+
+This ensures that we fall back to PIO if the message length is too small
+for DMA being useful. Otherwise, we use DMA. A bounce buffer might be
+applied by the helper if the original message buffer is not DMA safe.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit fe23aa9a1670b8800b251fc0400425e765c81880)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index bc1605a31534..b01607b4fce2 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -144,6 +144,7 @@ struct sh_mobile_i2c_data {
+ 	struct dma_chan *dma_rx;
+ 	struct scatterlist sg;
+ 	enum dma_data_direction dma_direction;
++	u8 *dma_buf;
+ };
+ 
+ struct sh_mobile_dt_config {
+@@ -501,6 +502,8 @@ static void sh_mobile_i2c_dma_callback(void *data)
+ 	pd->pos = pd->msg->len;
+ 	pd->stop_after_dma = true;
+ 
++	i2c_release_dma_safe_msg_buf(pd->msg, pd->dma_buf);
++
+ 	iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
+ }
+ 
+@@ -561,7 +564,7 @@ static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
+ 	if (IS_ERR(chan))
+ 		return;
+ 
+-	dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
++	dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
+ 	if (dma_mapping_error(chan->device->dev, dma_addr)) {
+ 		dev_dbg(pd->dev, "dma map failed, using PIO\n");
+ 		return;
+@@ -618,7 +621,8 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
+ 	pd->pos = -1;
+ 	pd->sr = 0;
+ 
+-	if (pd->msg->len > 8)
++	pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
++	if (pd->dma_buf)
+ 		sh_mobile_i2c_xfer_dma(pd);
+ 
+ 	/* Enable all interrupts to begin with */
+-- 
+2.19.0
+
diff --git a/patches/0544-i2c-sh_mobile-move-type-detection-upwards.patch b/patches/0544-i2c-sh_mobile-move-type-detection-upwards.patch
new file mode 100644
index 00000000000000..ada0bfe261e111
--- /dev/null
+++ b/patches/0544-i2c-sh_mobile-move-type-detection-upwards.patch
@@ -0,0 +1,48 @@
+From 275bf45e69de0faa2531f0752333b4dedcb2caa0 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:57:56 +0100
+Subject: [PATCH 0544/1795] i2c: sh_mobile: move type detection upwards
+
+For refactoring reasons, we will need this information before the setup
+callback. Also, simplify the comment to a oneliner.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 9e422131167583092a560c1ac4837a12aa11da96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index b01607b4fce2..1ac896e46b39 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -873,6 +873,10 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
+ 	pd->clks_per_count = 1;
+ 
++	/* Newer variants come with two new bits in ICIC */
++	if (resource_size(res) > 0x17)
++		pd->flags |= IIC_FLAG_HAS_ICIC67;
++
+ 	config = of_device_get_match_data(&dev->dev);
+ 	if (config) {
+ 		pd->clks_per_count = config->clks_per_count;
+@@ -881,12 +885,6 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 			config->setup(pd);
+ 	}
+ 
+-	/* The IIC blocks on SH-Mobile ARM processors
+-	 * come with two new bits in ICIC.
+-	 */
+-	if (resource_size(res) > 0x17)
+-		pd->flags |= IIC_FLAG_HAS_ICIC67;
+-
+ 	ret = sh_mobile_i2c_init(pd);
+ 	if (ret)
+ 		return ret;
+-- 
+2.19.0
+
diff --git a/patches/0545-i2c-sh_mobile-allow-setup-callback-to-return-errno.patch b/patches/0545-i2c-sh_mobile-allow-setup-callback-to-return-errno.patch
new file mode 100644
index 00000000000000..561d4c56279d10
--- /dev/null
+++ b/patches/0545-i2c-sh_mobile-allow-setup-callback-to-return-errno.patch
@@ -0,0 +1,66 @@
+From c6293f771b1ccf19f8ddfd009484c2c565b1ad8a Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:57:57 +0100
+Subject: [PATCH 0545/1795] i2c: sh_mobile: allow setup callback to return
+ errno
+
+The setup callback will be more generic and, thus, need to be able to
+return error codes. Change the return type to 'int' for that.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 12742b6ac1215496a60fcf33d1d8397af7512840)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 1ac896e46b39..a3a377a10fa7 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -149,7 +149,7 @@ struct sh_mobile_i2c_data {
+ 
+ struct sh_mobile_dt_config {
+ 	int clks_per_count;
+-	void (*setup)(struct sh_mobile_i2c_data *pd);
++	int (*setup)(struct sh_mobile_i2c_data *pd);
+ };
+ 
+ #define IIC_FLAG_HAS_ICIC67	(1 << 0)
+@@ -749,7 +749,7 @@ static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
+  * r8a7740 chip has lasting errata on I2C I/O pad reset.
+  * this is work-around for it.
+  */
+-static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
++static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
+ {
+ 	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
+ 	iic_rd(pd, ICCR); /* dummy read */
+@@ -770,6 +770,8 @@ static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
+ 	udelay(10);
+ 	iic_wr(pd, ICCR, ICCR_TRS);
+ 	udelay(10);
++
++	return 0;
+ }
+ 
+ static const struct sh_mobile_dt_config default_dt_config = {
+@@ -881,8 +883,11 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	if (config) {
+ 		pd->clks_per_count = config->clks_per_count;
+ 
+-		if (config->setup)
+-			config->setup(pd);
++		if (config->setup) {
++			ret = config->setup(pd);
++			if (ret)
++				return ret;
++		}
+ 	}
+ 
+ 	ret = sh_mobile_i2c_init(pd);
+-- 
+2.19.0
+
diff --git a/patches/0546-i2c-sh_mobile-require-setup-callback.patch b/patches/0546-i2c-sh_mobile-require-setup-callback.patch
new file mode 100644
index 00000000000000..614ad3489dfdd7
--- /dev/null
+++ b/patches/0546-i2c-sh_mobile-require-setup-callback.patch
@@ -0,0 +1,62 @@
+From cfa544fbc5834e789105e7a0f8d5f3f38ea6dff3 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:57:58 +0100
+Subject: [PATCH 0546/1795] i2c: sh_mobile: require setup callback
+
+Require the setup callback and move the frequency calculation into it.
+This is in preparation for supporting multiple formulas.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit b3750b6278b2f37618931352df8de6e7ddbecd1e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 15 ++++++---------
+ 1 file changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index a3a377a10fa7..88af45225003 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -771,15 +771,17 @@ static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
+ 	iic_wr(pd, ICCR, ICCR_TRS);
+ 	udelay(10);
+ 
+-	return 0;
++	return sh_mobile_i2c_init(pd);
+ }
+ 
+ static const struct sh_mobile_dt_config default_dt_config = {
+ 	.clks_per_count = 1,
++	.setup = sh_mobile_i2c_init,
+ };
+ 
+ static const struct sh_mobile_dt_config fast_clock_dt_config = {
+ 	.clks_per_count = 2,
++	.setup = sh_mobile_i2c_init,
+ };
+ 
+ static const struct sh_mobile_dt_config r8a7740_dt_config = {
+@@ -882,15 +884,10 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	config = of_device_get_match_data(&dev->dev);
+ 	if (config) {
+ 		pd->clks_per_count = config->clks_per_count;
+-
+-		if (config->setup) {
+-			ret = config->setup(pd);
+-			if (ret)
+-				return ret;
+-		}
++		ret = config->setup(pd);
++	} else {
++		ret = sh_mobile_i2c_init(pd);
+ 	}
+-
+-	ret = sh_mobile_i2c_init(pd);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0547-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch b/patches/0547-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
new file mode 100644
index 00000000000000..85ac5191256bd1
--- /dev/null
+++ b/patches/0547-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
@@ -0,0 +1,88 @@
+From 0503b5369bccd984c0a2d002ee34bf5daace1194 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:57:59 +0100
+Subject: [PATCH 0547/1795] i2c: sh_mobile: let RuntimePM do the clock handling
+
+Start RuntimePM a bit earlier, so we can use it to enable the clock
+during probe for frequency calculations. Make sure it is enabled before
+calling setup().
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 023c22fd82ce0c62d7490ace6388191375ef4133)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 35 +++++++++++++++---------------
+ 1 file changed, 17 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index 88af45225003..f1a9b971e2c1 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -252,11 +252,7 @@ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
+ 	u32 tHIGH, tLOW, tf;
+ 	uint16_t max_val;
+ 
+-	/* Get clock rate after clock is enabled */
+-	clk_prepare_enable(pd->clk);
+-	i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
+-	clk_disable_unprepare(pd->clk);
+-	i2c_clk_khz /= pd->clks_per_count;
++	i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
+ 
+ 	if (pd->bus_speed == STANDARD_MODE) {
+ 		tLOW	= 47;	/* tLOW = 4.7 us */
+@@ -881,6 +877,20 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	if (resource_size(res) > 0x17)
+ 		pd->flags |= IIC_FLAG_HAS_ICIC67;
+ 
++	/* Enable Runtime PM for this device.
++	 *
++	 * Also tell the Runtime PM core to ignore children
++	 * for this device since it is valid for us to suspend
++	 * this I2C master driver even though the slave devices
++	 * on the I2C bus may not be suspended.
++	 *
++	 * The state of the I2C hardware bus is unaffected by
++	 * the Runtime PM state.
++	 */
++	pm_suspend_ignore_children(&dev->dev, true);
++	pm_runtime_enable(&dev->dev);
++	pm_runtime_get_sync(&dev->dev);
++
+ 	config = of_device_get_match_data(&dev->dev);
+ 	if (config) {
+ 		pd->clks_per_count = config->clks_per_count;
+@@ -888,6 +898,8 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	} else {
+ 		ret = sh_mobile_i2c_init(pd);
+ 	}
++
++	pm_runtime_put_sync(&dev->dev);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -896,19 +908,6 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	pd->dma_direction = DMA_NONE;
+ 	pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
+ 
+-	/* Enable Runtime PM for this device.
+-	 *
+-	 * Also tell the Runtime PM core to ignore children
+-	 * for this device since it is valid for us to suspend
+-	 * this I2C master driver even though the slave devices
+-	 * on the I2C bus may not be suspended.
+-	 *
+-	 * The state of the I2C hardware bus is unaffected by
+-	 * the Runtime PM state.
+-	 */
+-	pm_suspend_ignore_children(&dev->dev, true);
+-	pm_runtime_enable(&dev->dev);
+-
+ 	/* setup the private data */
+ 	adap = &pd->adap;
+ 	i2c_set_adapdata(adap, pd);
+-- 
+2.19.0
+
diff --git a/patches/0548-i2c-sh_mobile-add-helper-to-check-frequency-calculat.patch b/patches/0548-i2c-sh_mobile-add-helper-to-check-frequency-calculat.patch
new file mode 100644
index 00000000000000..90865b8ef8e7eb
--- /dev/null
+++ b/patches/0548-i2c-sh_mobile-add-helper-to-check-frequency-calculat.patch
@@ -0,0 +1,92 @@
+From fd3cedf712fcc352f91c350571ee55cb1bda12cb Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:58:00 +0100
+Subject: [PATCH 0548/1795] i2c: sh_mobile: add helper to check frequency
+ calculations
+
+Because we will add a second formula soon, put the sanity checks for the
+computed results into a separate function.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit c3449f73a80b2b04a3f7ff69be871c153ea1a9fa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 49 ++++++++++++++++--------------
+ 1 file changed, 27 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index f1a9b971e2c1..b111191a449a 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -246,11 +246,36 @@ static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
+ 	return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
+ }
+ 
++static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
++{
++	u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
++
++	if (pd->iccl > max_val || pd->icch > max_val) {
++		dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
++			pd->iccl, pd->icch);
++		return -EINVAL;
++	}
++
++	/* one more bit of ICCL in ICIC */
++	if (pd->iccl & 0x100)
++		pd->icic |= ICIC_ICCLB8;
++	else
++		pd->icic &= ~ICIC_ICCLB8;
++
++	/* one more bit of ICCH in ICIC */
++	if (pd->icch & 0x100)
++		pd->icic |= ICIC_ICCHB8;
++	else
++		pd->icic &= ~ICIC_ICCHB8;
++
++	dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
++	return 0;
++}
++
+ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
+ {
+ 	unsigned long i2c_clk_khz;
+ 	u32 tHIGH, tLOW, tf;
+-	uint16_t max_val;
+ 
+ 	i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
+ 
+@@ -271,27 +296,7 @@ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
+ 	pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
+ 	pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
+ 
+-	max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
+-	if (pd->iccl > max_val || pd->icch > max_val) {
+-		dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
+-			pd->iccl, pd->icch);
+-		return -EINVAL;
+-	}
+-
+-	/* one more bit of ICCL in ICIC */
+-	if (pd->iccl & 0x100)
+-		pd->icic |= ICIC_ICCLB8;
+-	else
+-		pd->icic &= ~ICIC_ICCLB8;
+-
+-	/* one more bit of ICCH in ICIC */
+-	if (pd->icch & 0x100)
+-		pd->icic |= ICIC_ICCHB8;
+-	else
+-		pd->icic &= ~ICIC_ICCHB8;
+-
+-	dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
+-	return 0;
++	return sh_mobile_i2c_check_timing(pd);
+ }
+ 
+ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
+-- 
+2.19.0
+
diff --git a/patches/0549-i2c-sh_mobile-add-new-frequency-calculation-for-late.patch b/patches/0549-i2c-sh_mobile-add-new-frequency-calculation-for-late.patch
new file mode 100644
index 00000000000000..d6d360ce07c1a9
--- /dev/null
+++ b/patches/0549-i2c-sh_mobile-add-new-frequency-calculation-for-late.patch
@@ -0,0 +1,68 @@
+From 49547e39734081068ce9f97349ca8207aed46679 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:58:01 +0100
+Subject: [PATCH 0549/1795] i2c: sh_mobile: add new frequency calculation for
+ later SoC
+
+The formula to generate the desired bus speeds has changed a little over
+time. Implement the new formula and allow drivers to opt-in by changing
+to this new config set. Ensure in probe that we don't divide by zero.
+The returned values on a R-Car H2 (r8a7790/Lager board) match the
+suggested values in the datasheet.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 4ecfb9d3b229fff538c706650a8208fa03660c22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index b111191a449a..a0fddfe3c449 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -299,6 +299,18 @@ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
+ 	return sh_mobile_i2c_check_timing(pd);
+ }
+ 
++static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
++{
++	unsigned long clks_per_cycle;
++
++	/* L = 5, H = 4, L + H = 9 */
++	clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
++	pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
++	pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
++
++	return sh_mobile_i2c_check_timing(pd);
++}
++
+ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
+ 			    enum sh_mobile_i2c_op op, unsigned char data)
+ {
+@@ -785,6 +797,11 @@ static const struct sh_mobile_dt_config fast_clock_dt_config = {
+ 	.setup = sh_mobile_i2c_init,
+ };
+ 
++static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
++	.clks_per_count = 2,
++	.setup = sh_mobile_i2c_v2_init,
++};
++
+ static const struct sh_mobile_dt_config r8a7740_dt_config = {
+ 	.clks_per_count = 1,
+ 	.setup = sh_mobile_i2c_r8a7740_workaround,
+@@ -875,7 +892,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 		return PTR_ERR(pd->reg);
+ 
+ 	ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
+-	pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
++	pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
+ 	pd->clks_per_count = 1;
+ 
+ 	/* Newer variants come with two new bits in ICIC */
+-- 
+2.19.0
+
diff --git a/patches/0550-i2c-sh_mobile-let-r8a7790-R-Car-H2-use-the-new-formu.patch b/patches/0550-i2c-sh_mobile-let-r8a7790-R-Car-H2-use-the-new-formu.patch
new file mode 100644
index 00000000000000..0b3d7814d5cc21
--- /dev/null
+++ b/patches/0550-i2c-sh_mobile-let-r8a7790-R-Car-H2-use-the-new-formu.patch
@@ -0,0 +1,33 @@
+From ae71eaa782fa26a7309f2eb9978c513be32f329b Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 18 Dec 2017 22:58:02 +0100
+Subject: [PATCH 0550/1795] i2c: sh_mobile: let r8a7790 (R-Car H2) use the new
+ formula
+
+Make use of the new formula for more precise bus frequencies.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 6e318d9e3768b91707d8325068eeef88999aa8ae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-sh_mobile.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index a0fddfe3c449..d856bc211715 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -810,7 +810,7 @@ static const struct sh_mobile_dt_config r8a7740_dt_config = {
+ static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
+ 	{ .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
+ 	{ .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
+-	{ .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
++	{ .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
+ 	{ .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
+ 	{ .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
+ 	{ .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
+-- 
+2.19.0
+
diff --git a/patches/0551-mmc-slot-gpio-add-a-helper-to-check-capability-of-GP.patch b/patches/0551-mmc-slot-gpio-add-a-helper-to-check-capability-of-GP.patch
new file mode 100644
index 00000000000000..b23afe24da5ad7
--- /dev/null
+++ b/patches/0551-mmc-slot-gpio-add-a-helper-to-check-capability-of-GP.patch
@@ -0,0 +1,49 @@
+From 752e9164e76bd3939fee866686a9d3b255f28cbe Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:05 +0900
+Subject: [PATCH 0551/1795] mmc: slot-gpio: add a helper to check capability of
+ GPIO WP detection
+
+Like mmc_can_gpio_cd(), mmc_can_gpio_ro() will also be useful for host
+drivers to know whether GPIO write-protect detection is supported.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 85f9ef8cdfb463e6e8ff9fe8cdcc0aed438b526e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/core/slot-gpio.c  | 8 ++++++++
+ include/linux/mmc/slot-gpio.h | 1 +
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/mmc/core/slot-gpio.c b/drivers/mmc/core/slot-gpio.c
+index 863f1dbbfc1b..5ce102358a44 100644
+--- a/drivers/mmc/core/slot-gpio.c
++++ b/drivers/mmc/core/slot-gpio.c
+@@ -307,3 +307,11 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id,
+ 	return 0;
+ }
+ EXPORT_SYMBOL(mmc_gpiod_request_ro);
++
++bool mmc_can_gpio_ro(struct mmc_host *host)
++{
++	struct mmc_gpio *ctx = host->slot.handler_priv;
++
++	return ctx->ro_gpio ? true : false;
++}
++EXPORT_SYMBOL(mmc_can_gpio_ro);
+diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h
+index 82f0d289f110..91f1ba0663c8 100644
+--- a/include/linux/mmc/slot-gpio.h
++++ b/include/linux/mmc/slot-gpio.h
+@@ -33,5 +33,6 @@ void mmc_gpio_set_cd_isr(struct mmc_host *host,
+ 			 irqreturn_t (*isr)(int irq, void *dev_id));
+ void mmc_gpiod_request_cd_irq(struct mmc_host *host);
+ bool mmc_can_gpio_cd(struct mmc_host *host);
++bool mmc_can_gpio_ro(struct mmc_host *host);
+ 
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0552-mmc-tmio-refactor-.get_ro-hook.patch b/patches/0552-mmc-tmio-refactor-.get_ro-hook.patch
new file mode 100644
index 00000000000000..f98deafc83b362
--- /dev/null
+++ b/patches/0552-mmc-tmio-refactor-.get_ro-hook.patch
@@ -0,0 +1,57 @@
+From d01f455066d08fa491673905bf017f81c6cf1ec0 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:06 +0900
+Subject: [PATCH 0552/1795] mmc: tmio: refactor .get_ro hook
+
+This IP provides the write protect signal level in the status
+register, but it is also possible to use GPIO for WP.  They are
+exclusive, so it is not efficient to call mmc_gpio_get_ro() every
+time from tmio_mmc_get_ro() if we know gpio_ro is not used.
+
+Check the capability of gpio_ro just once in the probe function,
+then set mmc_gpio_get_ro to .get_ro if it is the case.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 1910b87f7a9e6d9f9085d36e45dce1e5547c692d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 13 +++++--------
+ 1 file changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 1417574a47e7..e7ac38abcc05 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1076,15 +1076,9 @@ static int tmio_mmc_get_ro(struct mmc_host *mmc)
+ {
+ 	struct tmio_mmc_host *host = mmc_priv(mmc);
+ 	struct tmio_mmc_data *pdata = host->pdata;
+-	int ret = mmc_gpio_get_ro(mmc);
+ 
+-	if (ret >= 0)
+-		return ret;
+-
+-	ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
+-		(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
+-
+-	return ret;
++	return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
++		 (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
+ }
+ 
+ static int tmio_multi_io_quirk(struct mmc_card *card,
+@@ -1247,6 +1241,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 	}
+ 	mmc->max_seg_size = mmc->max_req_size;
+ 
++	if (mmc_can_gpio_ro(mmc))
++		_host->ops.get_ro = mmc_gpio_get_ro;
++
+ 	_host->native_hotplug = !(mmc_can_gpio_cd(mmc) ||
+ 				  mmc->caps & MMC_CAP_NEEDS_POLL ||
+ 				  !mmc_card_is_removable(mmc));
+-- 
+2.19.0
+
diff --git a/patches/0553-mmc-tmio-hide-unused-tmio_mmc_clk_disable-tmio_mmc_c.patch b/patches/0553-mmc-tmio-hide-unused-tmio_mmc_clk_disable-tmio_mmc_c.patch
new file mode 100644
index 00000000000000..340701339926e3
--- /dev/null
+++ b/patches/0553-mmc-tmio-hide-unused-tmio_mmc_clk_disable-tmio_mmc_c.patch
@@ -0,0 +1,81 @@
+From ade046386fc1b5281537a2cfe43488bf13d29564 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 19 Jan 2018 15:54:44 +0100
+Subject: [PATCH 0553/1795] mmc: tmio: hide unused
+ tmio_mmc_clk_disable/tmio_mmc_clk_enable functions
+
+When CONFIG_PM is disabled, we get a warning about the clock handling
+being unused:
+
+drivers/mmc/host/tmio_mmc_core.c:937:13: error: 'tmio_mmc_clk_disable' defined but not used [-Werror=unused-function]
+ static void tmio_mmc_clk_disable(struct tmio_mmc_host *host)
+             ^~~~~~~~~~~~~~~~~~~~
+drivers/mmc/host/tmio_mmc_core.c:929:12: error: 'tmio_mmc_clk_enable' defined but not used [-Werror=unused-function]
+ static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
+            ^~~~~~~~~~~~~~~~~~~
+
+As the clock handling is now done elsewhere, this is only used when
+power management is enabled. We could make the functions as __maybe_unused,
+but since there is already an #ifdef section, it seems easier to move
+the helpers closer to their callers.
+
+Fixes: b21fc294387e ("mmc: tmio: move clk_enable/disable out of tmio_mmc_host_probe()")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 4a09d0b86bad0999a2bb0e2ee126a3c5246d1f51)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index e7ac38abcc05..8fce18253465 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -926,20 +926,6 @@ static void tmio_mmc_done_work(struct work_struct *work)
+ 	tmio_mmc_finish_request(host);
+ }
+ 
+-static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
+-{
+-	if (!host->clk_enable)
+-		return -ENOTSUPP;
+-
+-	return host->clk_enable(host);
+-}
+-
+-static void tmio_mmc_clk_disable(struct tmio_mmc_host *host)
+-{
+-	if (host->clk_disable)
+-		host->clk_disable(host);
+-}
+-
+ static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
+ {
+ 	struct mmc_host *mmc = host->mmc;
+@@ -1337,6 +1323,20 @@ void tmio_mmc_host_remove(struct tmio_mmc_host *host)
+ EXPORT_SYMBOL_GPL(tmio_mmc_host_remove);
+ 
+ #ifdef CONFIG_PM
++static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
++{
++	if (!host->clk_enable)
++		return -ENOTSUPP;
++
++	return host->clk_enable(host);
++}
++
++static void tmio_mmc_clk_disable(struct tmio_mmc_host *host)
++{
++	if (host->clk_disable)
++		host->clk_disable(host);
++}
++
+ int tmio_mmc_host_runtime_suspend(struct device *dev)
+ {
+ 	struct tmio_mmc_host *host = dev_get_drvdata(dev);
+-- 
+2.19.0
+
diff --git a/patches/0554-net-phy-Add-general-dummy-stubs-for-MMD-register-acc.patch b/patches/0554-net-phy-Add-general-dummy-stubs-for-MMD-register-acc.patch
new file mode 100644
index 00000000000000..3c9f523b58ade2
--- /dev/null
+++ b/patches/0554-net-phy-Add-general-dummy-stubs-for-MMD-register-acc.patch
@@ -0,0 +1,69 @@
+From 7406ffc54e986b006993220da8d1c298efb9ddb7 Mon Sep 17 00:00:00 2001
+From: Kevin Hao <haokexin@gmail.com>
+Date: Tue, 20 Mar 2018 09:44:52 +0800
+Subject: [PATCH 0554/1795] net: phy: Add general dummy stubs for MMD register
+ access
+
+For some phy devices, even though they don't support the MMD extended
+register access, it does have some side effect if we are trying to
+read/write the MMD registers via indirect method. So introduce general
+dummy stubs for MMD register access which these devices can use to avoid
+such side effect.
+
+Fixes: b6b5e8a69118 ("gianfar: Disable EEE autoneg by default")
+Signed-off-by: Kevin Hao <haokexin@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 5df7af85ecd88e8b5f1f31d6456c3cf38a8bbdda)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/phy_device.c | 17 +++++++++++++++++
+ include/linux/phy.h          |  4 ++++
+ 2 files changed, 21 insertions(+)
+
+diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
+index a174d05a9752..fe76e2c4022a 100644
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1641,6 +1641,23 @@ int genphy_config_init(struct phy_device *phydev)
+ }
+ EXPORT_SYMBOL(genphy_config_init);
+ 
++/* This is used for the phy device which doesn't support the MMD extended
++ * register access, but it does have side effect when we are trying to access
++ * the MMD register via indirect method.
++ */
++int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum)
++{
++	return -EOPNOTSUPP;
++}
++EXPORT_SYMBOL(genphy_read_mmd_unsupported);
++
++int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
++				 u16 regnum, u16 val)
++{
++	return -EOPNOTSUPP;
++}
++EXPORT_SYMBOL(genphy_write_mmd_unsupported);
++
+ int genphy_suspend(struct phy_device *phydev)
+ {
+ 	int value;
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index dca9e926b88f..efc04c2d92c9 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -879,6 +879,10 @@ static inline int genphy_no_soft_reset(struct phy_device *phydev)
+ {
+ 	return 0;
+ }
++int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
++				u16 regnum);
++int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
++				 u16 regnum, u16 val);
+ 
+ /* Clause 45 PHY */
+ int genphy_c45_restart_aneg(struct phy_device *phydev);
+-- 
+2.19.0
+
diff --git a/patches/0555-net-phy-micrel-Use-the-general-dummy-stubs-for-MMD-r.patch b/patches/0555-net-phy-micrel-Use-the-general-dummy-stubs-for-MMD-r.patch
new file mode 100644
index 00000000000000..cca51ac6b3653a
--- /dev/null
+++ b/patches/0555-net-phy-micrel-Use-the-general-dummy-stubs-for-MMD-r.patch
@@ -0,0 +1,62 @@
+From 8dafee8491f175240b786bb737efea54813f64d3 Mon Sep 17 00:00:00 2001
+From: Kevin Hao <haokexin@gmail.com>
+Date: Tue, 20 Mar 2018 09:44:54 +0800
+Subject: [PATCH 0555/1795] net: phy: micrel: Use the general dummy stubs for
+ MMD register access
+
+The new general dummy stubs for MMD register access were introduced.
+Use that for the codes reuse.
+
+Signed-off-by: Kevin Hao <haokexin@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit c846a2b7bd0e6900a726afb7c0a066f3a93617cf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/micrel.c | 23 ++---------------------
+ 1 file changed, 2 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index 0bcb51cd95ca..e8831418075e 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -635,25 +635,6 @@ static int ksz8873mll_config_aneg(struct phy_device *phydev)
+ 	return 0;
+ }
+ 
+-/* This routine returns -1 as an indication to the caller that the
+- * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
+- * MMD extended PHY registers.
+- */
+-static int
+-ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
+-{
+-	return -1;
+-}
+-
+-/* This routine does nothing since the Micrel ksz9021 does not support
+- * standard IEEE MMD extended PHY registers.
+- */
+-static int
+-ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
+-{
+-	return -1;
+-}
+-
+ static int kszphy_get_sset_count(struct phy_device *phydev)
+ {
+ 	return ARRAY_SIZE(kszphy_hw_stats);
+@@ -965,8 +946,8 @@ static struct phy_driver ksphy_driver[] = {
+ 	.get_stats	= kszphy_get_stats,
+ 	.suspend	= genphy_suspend,
+ 	.resume		= genphy_resume,
+-	.read_mmd	= ksz9021_rd_mmd_phyreg,
+-	.write_mmd	= ksz9021_wr_mmd_phyreg,
++	.read_mmd	= genphy_read_mmd_unsupported,
++	.write_mmd	= genphy_write_mmd_unsupported,
+ }, {
+ 	.phy_id		= PHY_ID_KSZ9031,
+ 	.phy_id_mask	= MICREL_PHY_ID_MASK,
+-- 
+2.19.0
+
diff --git a/patches/0556-ALSA-add-snd_card_disconnect_sync.patch b/patches/0556-ALSA-add-snd_card_disconnect_sync.patch
new file mode 100644
index 00000000000000..a3b043a3e2751f
--- /dev/null
+++ b/patches/0556-ALSA-add-snd_card_disconnect_sync.patch
@@ -0,0 +1,125 @@
+From c75e1ddf9bbd27d74427ba2e2c7f4253ce43dd24 Mon Sep 17 00:00:00 2001
+From: Takashi Iwai <tiwai@suse.de>
+Date: Wed, 11 Oct 2017 06:36:13 +0000
+Subject: [PATCH 0556/1795] ALSA: add snd_card_disconnect_sync()
+
+In case of user unbind ALSA driver during playing back / capturing,
+each driver needs to stop and remove it correctly. One note here is
+that we can't cancel from remove function in such case, because
+unbind operation doesn't check return value from remove function.
+So, we *must* stop and remove in this case.
+
+For this purpose, we need to sync (= wait) until the all top-level
+operations are canceled at remove function.
+For example, snd_card_free() processes the disconnection procedure at
+first, then waits for the completion. That's how the hot-unplug works
+safely. It's implemented, at least, in the top-level driver removal.
+
+Now for the lower level driver, we need a similar strategy. Notify to
+the toplevel for hot-unplug (disconnect in ALSA), and sync with the
+stop operation, then continue the rest of its own remove procedure.
+
+This patch adds snd_card_disconnect_sync(), and driver can use it from
+remove function.
+
+Note: the "lower level" driver here refers to a middle layer driver
+(e.g. ASoC components) that can be unbound freely during operation.
+Most of legacy ALSA helper drivers don't have such a problem because
+they can't be unbound.
+
+Note#2: snd_card_disconnect_sync() merely calls snd_card_disconnect()
+and syncs with closing all pending files.  It takes only the files
+opened by user-space into account, and doesn't care about object
+refcounts.  (The latter is handled by snd_card_free() completion call,
+BTW.)  Also, the function doesn't free resources by itself.
+
+Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+(cherry picked from commit c44027c89e19adafccd404bbe6f9686722ff4217)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/sound/core.h |  2 ++
+ sound/core/init.c    | 32 ++++++++++++++++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+
+diff --git a/include/sound/core.h b/include/sound/core.h
+index 4104a9d1001f..5f181b875c2f 100644
+--- a/include/sound/core.h
++++ b/include/sound/core.h
+@@ -133,6 +133,7 @@ struct snd_card {
+ 	struct device card_dev;		/* cardX object for sysfs */
+ 	const struct attribute_group *dev_groups[4]; /* assigned sysfs attr */
+ 	bool registered;		/* card_dev is registered? */
++	wait_queue_head_t remove_sleep;
+ 
+ #ifdef CONFIG_PM
+ 	unsigned int power_state;	/* power state */
+@@ -240,6 +241,7 @@ int snd_card_new(struct device *parent, int idx, const char *xid,
+ 		 struct snd_card **card_ret);
+ 
+ int snd_card_disconnect(struct snd_card *card);
++void snd_card_disconnect_sync(struct snd_card *card);
+ int snd_card_free(struct snd_card *card);
+ int snd_card_free_when_closed(struct snd_card *card);
+ void snd_card_set_id(struct snd_card *card, const char *id);
+diff --git a/sound/core/init.c b/sound/core/init.c
+index 32ebe2f6bc59..168ae03d3a1c 100644
+--- a/sound/core/init.c
++++ b/sound/core/init.c
+@@ -255,6 +255,7 @@ int snd_card_new(struct device *parent, int idx, const char *xid,
+ #ifdef CONFIG_PM
+ 	init_waitqueue_head(&card->power_sleep);
+ #endif
++	init_waitqueue_head(&card->remove_sleep);
+ 
+ 	device_initialize(&card->card_dev);
+ 	card->card_dev.parent = parent;
+@@ -452,6 +453,35 @@ int snd_card_disconnect(struct snd_card *card)
+ }
+ EXPORT_SYMBOL(snd_card_disconnect);
+ 
++/**
++ * snd_card_disconnect_sync - disconnect card and wait until files get closed
++ * @card: card object to disconnect
++ *
++ * This calls snd_card_disconnect() for disconnecting all belonging components
++ * and waits until all pending files get closed.
++ * It assures that all accesses from user-space finished so that the driver
++ * can release its resources gracefully.
++ */
++void snd_card_disconnect_sync(struct snd_card *card)
++{
++	int err;
++
++	err = snd_card_disconnect(card);
++	if (err < 0) {
++		dev_err(card->dev,
++			"snd_card_disconnect error (%d), skipping sync\n",
++			err);
++		return;
++	}
++
++	spin_lock_irq(&card->files_lock);
++	wait_event_lock_irq(card->remove_sleep,
++			    list_empty(&card->files_list),
++			    card->files_lock);
++	spin_unlock_irq(&card->files_lock);
++}
++EXPORT_SYMBOL_GPL(snd_card_disconnect_sync);
++
+ static int snd_card_do_free(struct snd_card *card)
+ {
+ #if IS_ENABLED(CONFIG_SND_MIXER_OSS)
+@@ -957,6 +987,8 @@ int snd_card_file_remove(struct snd_card *card, struct file *file)
+ 			break;
+ 		}
+ 	}
++	if (list_empty(&card->files_list))
++		wake_up_all(&card->remove_sleep);
+ 	spin_unlock(&card->files_lock);
+ 	if (!found) {
+ 		dev_err(card->dev, "card file remove problem (%p)\n", file);
+-- 
+2.19.0
+
diff --git a/patches/0557-ASoC-soc-core-add-component-lookup-functions.patch b/patches/0557-ASoC-soc-core-add-component-lookup-functions.patch
new file mode 100644
index 00000000000000..3cf049e0bc6e13
--- /dev/null
+++ b/patches/0557-ASoC-soc-core-add-component-lookup-functions.patch
@@ -0,0 +1,82 @@
+From 87522cc7ac0dde898788a16e7c8f36aa4cfe8257 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 2 Oct 2017 05:09:52 +0000
+Subject: [PATCH 0557/1795] ASoC: soc-core: add component lookup functions
+
+ALSA SoC platform/codec will be replaced to component soon.
+This means 1 device might have multiple components. But current
+unregister component function only checks "dev" to find it.
+This means, unexpected component might be unregistered by current
+function.
+But, it is no problem if driver registered only 1 component.
+
+To prepare avoid this issue, this patch adds new component
+lookup function. it finds component by "dev" and "driver name".
+
+Here, the reason why it uses "driver name" is that "component name"
+was created by fmt_single_name() and difficult to use it from driver.
+Driver of course knows its "driver name", thus, using it is more easy.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 7dd5d0d954611c05a38bdf843054c639f45ce08b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/sound/soc.h  |  2 ++
+ sound/soc/soc-core.c | 26 ++++++++++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+
+diff --git a/include/sound/soc.h b/include/sound/soc.h
+index d22de9712c45..c289e1b1ad84 100644
+--- a/include/sound/soc.h
++++ b/include/sound/soc.h
+@@ -475,6 +475,8 @@ int devm_snd_soc_register_component(struct device *dev,
+ 			 const struct snd_soc_component_driver *component_driver,
+ 			 struct snd_soc_dai_driver *dai_drv, int num_dai);
+ void snd_soc_unregister_component(struct device *dev);
++struct snd_soc_component *snd_soc_lookup_component(struct device *dev,
++						   const char *driver_name);
+ int snd_soc_cache_init(struct snd_soc_codec *codec);
+ int snd_soc_cache_exit(struct snd_soc_codec *codec);
+ 
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index fee4b0ef5566..a9066320b672 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -3448,6 +3448,32 @@ void snd_soc_unregister_component(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(snd_soc_unregister_component);
+ 
++struct snd_soc_component *snd_soc_lookup_component(struct device *dev,
++						   const char *driver_name)
++{
++	struct snd_soc_component *component;
++	struct snd_soc_component *ret;
++
++	ret = NULL;
++	mutex_lock(&client_mutex);
++	list_for_each_entry(component, &component_list, list) {
++		if (dev != component->dev)
++			continue;
++
++		if (driver_name &&
++		    (driver_name != component->driver->name) &&
++		    (strcmp(component->driver->name, driver_name) != 0))
++			continue;
++
++		ret = component;
++		break;
++	}
++	mutex_unlock(&client_mutex);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(snd_soc_lookup_component);
++
+ static int snd_soc_platform_drv_probe(struct snd_soc_component *component)
+ {
+ 	struct snd_soc_platform *platform = snd_soc_component_to_platform(component);
+-- 
+2.19.0
+
diff --git a/patches/0558-ASoC-add-snd_soc_disconnect_sync.patch b/patches/0558-ASoC-add-snd_soc_disconnect_sync.patch
new file mode 100644
index 00000000000000..9d4e1e65352e6e
--- /dev/null
+++ b/patches/0558-ASoC-add-snd_soc_disconnect_sync.patch
@@ -0,0 +1,55 @@
+From a55be0f7c7d79a20a7ab1ab853d0eb2f4210e78d Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 28 Nov 2017 06:27:09 +0000
+Subject: [PATCH 0558/1795] ASoC: add snd_soc_disconnect_sync()
+
+Now, we have snd_card_disconnect_sync() on ALSA framework.
+snd_soc_disconnect_sync() is ASoC version of it.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit ef2e8175eb19011f756469d4d14f4207bf7f289c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/sound/soc.h  |  2 ++
+ sound/soc/soc-core.c | 10 ++++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/include/sound/soc.h b/include/sound/soc.h
+index c289e1b1ad84..8a7ca360b9af 100644
+--- a/include/sound/soc.h
++++ b/include/sound/soc.h
+@@ -489,6 +489,8 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num);
+ int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num);
+ #endif
+ 
++void snd_soc_disconnect_sync(struct device *dev);
++
+ struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card,
+ 		const char *dai_link, int stream);
+ struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card,
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index a9066320b672..88403ccdf18b 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -1388,6 +1388,16 @@ static int soc_init_dai_link(struct snd_soc_card *card,
+ 	return 0;
+ }
+ 
++void snd_soc_disconnect_sync(struct device *dev)
++{
++	struct snd_soc_component *component = snd_soc_lookup_component(dev, NULL);
++
++	if (!component || !component->card)
++		return;
++
++	snd_card_disconnect_sync(component->card->snd_card);
++}
++
+ /**
+  * snd_soc_add_dai_link - Add a DAI link dynamically
+  * @card: The ASoC card to which the DAI link is added
+-- 
+2.19.0
+
diff --git a/patches/0559-ASoC-soc-core-add-missing-EXPORT_SYMBOL_GPL-for-snd_.patch b/patches/0559-ASoC-soc-core-add-missing-EXPORT_SYMBOL_GPL-for-snd_.patch
new file mode 100644
index 00000000000000..e9b5ec6f67dccb
--- /dev/null
+++ b/patches/0559-ASoC-soc-core-add-missing-EXPORT_SYMBOL_GPL-for-snd_.patch
@@ -0,0 +1,30 @@
+From b1de5d3e892708877e851dc1dfd03ae028950b10 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 29 Nov 2017 02:38:27 +0000
+Subject: [PATCH 0559/1795] ASoC: soc-core: add missing EXPORT_SYMBOL_GPL() for
+ snd_soc_disconnect_sync
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit df532185e8720baff120f55eb46058d270445d56)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/soc-core.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index 88403ccdf18b..b0a197270add 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -1397,6 +1397,7 @@ void snd_soc_disconnect_sync(struct device *dev)
+ 
+ 	snd_card_disconnect_sync(component->card->snd_card);
+ }
++EXPORT_SYMBOL_GPL(snd_soc_disconnect_sync);
+ 
+ /**
+  * snd_soc_add_dai_link - Add a DAI link dynamically
+-- 
+2.19.0
+
diff --git a/patches/0560-ASoC-rsnd-call-snd_soc_disconnect_sync-when-remove.patch b/patches/0560-ASoC-rsnd-call-snd_soc_disconnect_sync-when-remove.patch
new file mode 100644
index 00000000000000..e93b3d4996fbd1
--- /dev/null
+++ b/patches/0560-ASoC-rsnd-call-snd_soc_disconnect_sync-when-remove.patch
@@ -0,0 +1,43 @@
+From 0cd5f47bd95e33b8efc07eb90b0afaa7bfa63c69 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 6 Nov 2017 08:41:37 +0000
+Subject: [PATCH 0560/1795] ASoC: rsnd: call snd_soc_disconnect_sync() when
+ remove
+
+Renesas R-Car sound driver should be stopped if unbinded during
+playbacking/capturing. Otherwise clock open/close counter mismatch
+happen.
+
+One note is that we can't skip from remove function (= return -Exxx)
+in such case if user used unbind. Because unbind function doesn't
+check return value from each driver's remove function.
+This means we must to stop and remove driver in remove function.
+
+Now ASoC has snd_soc_disconnect_sync() for this purpose.
+Let's use it.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 180d9ef58104dfae78622d01910b9b7756701134)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index f12a88a21dfa..bd64dc6ec1c3 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1496,6 +1496,8 @@ static int rsnd_remove(struct platform_device *pdev)
+ 	};
+ 	int ret = 0, i;
+ 
++	snd_soc_disconnect_sync(&pdev->dev);
++
+ 	pm_runtime_disable(&pdev->dev);
+ 
+ 	for_each_rsnd_dai(rdai, priv, i) {
+-- 
+2.19.0
+
diff --git a/patches/0561-ASoC-rsnd-TDM-6ch-needs-8ch-clock-for-hw-refine.patch b/patches/0561-ASoC-rsnd-TDM-6ch-needs-8ch-clock-for-hw-refine.patch
new file mode 100644
index 00000000000000..ebc9b5cabb4a90
--- /dev/null
+++ b/patches/0561-ASoC-rsnd-TDM-6ch-needs-8ch-clock-for-hw-refine.patch
@@ -0,0 +1,260 @@
+From b4fba81581fa57de8e1f1fab501e9c5c9f38ac47 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 29 Nov 2017 03:07:51 +0000
+Subject: [PATCH 0561/1795] ASoC: rsnd: TDM 6ch needs 8ch clock for hw refine
+
+Renesas sound needs 8ch clock if TDM 6ch mode, and needs 2ch clock for
+6ch or 8ch sound if Multi SSI mode. And these are related to before/after
+CTU (= Channel Transfer Unit).
+To calculate these we already has rsnd_runtime_channel_for_ssi() which
+returns runtime necessary channels.
+But, it based on runtime->channels  which is not yet set when hw refine.
+We need to use hw_params instead of runtime->xxx when hw refine,
+and it is not needed after runtime was set.
+This patch adds new hw_params on rsnd_dai_stream, and it will be removed
+on rsnd_hw_params().
+This is very temporary durty code, but it seems no choice at this point.
+
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b2fb31bb7454d5479b1c7214ccd10c1af85a6245)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 92 +++++++++++++++++++++++++++++-----------
+ sound/soc/sh/rcar/rsnd.h | 15 +++++--
+ 2 files changed, 80 insertions(+), 27 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index bd64dc6ec1c3..d76ad46a6fd9 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -197,16 +197,27 @@ int rsnd_io_is_working(struct rsnd_dai_stream *io)
+ 	return 0;
+ }
+ 
+-int rsnd_runtime_channel_original(struct rsnd_dai_stream *io)
++int rsnd_runtime_channel_original_with_params(struct rsnd_dai_stream *io,
++					      struct snd_pcm_hw_params *params)
+ {
+ 	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+ 
+-	return runtime->channels;
++	/*
++	 * params will be added when refine
++	 * see
++	 *	__rsnd_soc_hw_rule_rate()
++	 *	__rsnd_soc_hw_rule_channels()
++	 */
++	if (params)
++		return params_channels(params);
++	else
++		return runtime->channels;
+ }
+ 
+-int rsnd_runtime_channel_after_ctu(struct rsnd_dai_stream *io)
++int rsnd_runtime_channel_after_ctu_with_params(struct rsnd_dai_stream *io,
++					       struct snd_pcm_hw_params *params)
+ {
+-	int chan = rsnd_runtime_channel_original(io);
++	int chan = rsnd_runtime_channel_original_with_params(io, params);
+ 	struct rsnd_mod *ctu_mod = rsnd_io_to_mod_ctu(io);
+ 
+ 	if (ctu_mod) {
+@@ -219,12 +230,13 @@ int rsnd_runtime_channel_after_ctu(struct rsnd_dai_stream *io)
+ 	return chan;
+ }
+ 
+-int rsnd_runtime_channel_for_ssi(struct rsnd_dai_stream *io)
++int rsnd_runtime_channel_for_ssi_with_params(struct rsnd_dai_stream *io,
++					     struct snd_pcm_hw_params *params)
+ {
+ 	struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
+ 	int chan = rsnd_io_is_play(io) ?
+-		rsnd_runtime_channel_after_ctu(io) :
+-		rsnd_runtime_channel_original(io);
++		rsnd_runtime_channel_after_ctu_with_params(io, params) :
++		rsnd_runtime_channel_original_with_params(io, params);
+ 
+ 	/* Use Multi SSI */
+ 	if (rsnd_runtime_is_ssi_multi(io))
+@@ -616,8 +628,6 @@ static int rsnd_soc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+ 	switch (cmd) {
+ 	case SNDRV_PCM_TRIGGER_START:
+ 	case SNDRV_PCM_TRIGGER_RESUME:
+-		rsnd_dai_stream_init(io, substream);
+-
+ 		ret = rsnd_dai_call(init, io, priv);
+ 		if (ret < 0)
+ 			goto dai_trigger_end;
+@@ -639,7 +649,6 @@ static int rsnd_soc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+ 
+ 		ret |= rsnd_dai_call(quit, io, priv);
+ 
+-		rsnd_dai_stream_quit(io);
+ 		break;
+ 	default:
+ 		ret = -EINVAL;
+@@ -784,8 +793,9 @@ static int rsnd_soc_hw_rule(struct rsnd_priv *priv,
+ 	return snd_interval_refine(iv, &p);
+ }
+ 
+-static int rsnd_soc_hw_rule_rate(struct snd_pcm_hw_params *params,
+-				 struct snd_pcm_hw_rule *rule)
++static int __rsnd_soc_hw_rule_rate(struct snd_pcm_hw_params *params,
++				   struct snd_pcm_hw_rule *rule,
++				   int is_play)
+ {
+ 	struct snd_interval *ic_ = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
+ 	struct snd_interval *ir = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
+@@ -793,25 +803,37 @@ static int rsnd_soc_hw_rule_rate(struct snd_pcm_hw_params *params,
+ 	struct snd_soc_dai *dai = rule->private;
+ 	struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
+ 	struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
++	struct rsnd_dai_stream *io = is_play ? &rdai->playback : &rdai->capture;
+ 
+ 	/*
+ 	 * possible sampling rate limitation is same as
+ 	 * 2ch if it supports multi ssi
++	 * and same as 8ch if TDM 6ch (see rsnd_ssi_config_init())
+ 	 */
+ 	ic = *ic_;
+-	if (1 < rsnd_rdai_ssi_lane_get(rdai)) {
+-		ic.min = 2;
+-		ic.max = 2;
+-	}
++	ic.min =
++	ic.max = rsnd_runtime_channel_for_ssi_with_params(io, params);
+ 
+ 	return rsnd_soc_hw_rule(priv, rsnd_soc_hw_rate_list,
+ 				ARRAY_SIZE(rsnd_soc_hw_rate_list),
+ 				&ic, ir);
+ }
+ 
++static int rsnd_soc_hw_rule_rate_playback(struct snd_pcm_hw_params *params,
++				 struct snd_pcm_hw_rule *rule)
++{
++	return __rsnd_soc_hw_rule_rate(params, rule, 1);
++}
++
++static int rsnd_soc_hw_rule_rate_capture(struct snd_pcm_hw_params *params,
++					  struct snd_pcm_hw_rule *rule)
++{
++	return __rsnd_soc_hw_rule_rate(params, rule, 0);
++}
+ 
+-static int rsnd_soc_hw_rule_channels(struct snd_pcm_hw_params *params,
+-				     struct snd_pcm_hw_rule *rule)
++static int __rsnd_soc_hw_rule_channels(struct snd_pcm_hw_params *params,
++				       struct snd_pcm_hw_rule *rule,
++				       int is_play)
+ {
+ 	struct snd_interval *ic_ = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
+ 	struct snd_interval *ir = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
+@@ -819,22 +841,34 @@ static int rsnd_soc_hw_rule_channels(struct snd_pcm_hw_params *params,
+ 	struct snd_soc_dai *dai = rule->private;
+ 	struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
+ 	struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
++	struct rsnd_dai_stream *io = is_play ? &rdai->playback : &rdai->capture;
+ 
+ 	/*
+ 	 * possible sampling rate limitation is same as
+ 	 * 2ch if it supports multi ssi
++	 * and same as 8ch if TDM 6ch (see rsnd_ssi_config_init())
+ 	 */
+ 	ic = *ic_;
+-	if (1 < rsnd_rdai_ssi_lane_get(rdai)) {
+-		ic.min = 2;
+-		ic.max = 2;
+-	}
++	ic.min =
++	ic.max = rsnd_runtime_channel_for_ssi_with_params(io, params);
+ 
+ 	return rsnd_soc_hw_rule(priv, rsnd_soc_hw_channels_list,
+ 				ARRAY_SIZE(rsnd_soc_hw_channels_list),
+ 				ir, &ic);
+ }
+ 
++static int rsnd_soc_hw_rule_channels_playback(struct snd_pcm_hw_params *params,
++					      struct snd_pcm_hw_rule *rule)
++{
++	return __rsnd_soc_hw_rule_channels(params, rule, 1);
++}
++
++static int rsnd_soc_hw_rule_channels_capture(struct snd_pcm_hw_params *params,
++					     struct snd_pcm_hw_rule *rule)
++{
++	return __rsnd_soc_hw_rule_channels(params, rule, 0);
++}
++
+ static const struct snd_pcm_hardware rsnd_pcm_hardware = {
+ 	.info =		SNDRV_PCM_INFO_INTERLEAVED	|
+ 			SNDRV_PCM_INFO_MMAP		|
+@@ -859,6 +893,8 @@ static int rsnd_soc_dai_startup(struct snd_pcm_substream *substream,
+ 	int ret;
+ 	int i;
+ 
++	rsnd_dai_stream_init(io, substream);
++
+ 	/*
+ 	 * Channel Limitation
+ 	 * It depends on Platform design
+@@ -886,11 +922,17 @@ static int rsnd_soc_dai_startup(struct snd_pcm_substream *substream,
+ 	 * It depends on Clock Master Mode
+ 	 */
+ 	if (rsnd_rdai_is_clk_master(rdai)) {
++		int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++
+ 		snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
+-				    rsnd_soc_hw_rule_rate, dai,
++				    is_play ? rsnd_soc_hw_rule_rate_playback :
++					      rsnd_soc_hw_rule_rate_capture,
++				    dai,
+ 				    SNDRV_PCM_HW_PARAM_CHANNELS, -1);
+ 		snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
+-				    rsnd_soc_hw_rule_channels, dai,
++				    is_play ? rsnd_soc_hw_rule_channels_playback :
++					      rsnd_soc_hw_rule_channels_capture,
++				    dai,
+ 				    SNDRV_PCM_HW_PARAM_RATE, -1);
+ 	}
+ 
+@@ -915,6 +957,8 @@ static void rsnd_soc_dai_shutdown(struct snd_pcm_substream *substream,
+ 	 * call rsnd_dai_call without spinlock
+ 	 */
+ 	rsnd_dai_call(nolock_stop, io, priv);
++
++	rsnd_dai_stream_quit(io);
+ }
+ 
+ static const struct snd_soc_dai_ops rsnd_soc_dai_ops = {
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 57cd2bc773c2..ad6523595b0a 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -399,9 +399,18 @@ void rsnd_parse_connect_common(struct rsnd_dai *rdai,
+ 		struct device_node *playback,
+ 		struct device_node *capture);
+ 
+-int rsnd_runtime_channel_original(struct rsnd_dai_stream *io);
+-int rsnd_runtime_channel_after_ctu(struct rsnd_dai_stream *io);
+-int rsnd_runtime_channel_for_ssi(struct rsnd_dai_stream *io);
++#define rsnd_runtime_channel_original(io) \
++	rsnd_runtime_channel_original_with_params(io, NULL)
++int rsnd_runtime_channel_original_with_params(struct rsnd_dai_stream *io,
++				struct snd_pcm_hw_params *params);
++#define rsnd_runtime_channel_after_ctu(io)			\
++	rsnd_runtime_channel_after_ctu_with_params(io, NULL)
++int rsnd_runtime_channel_after_ctu_with_params(struct rsnd_dai_stream *io,
++				struct snd_pcm_hw_params *params);
++#define rsnd_runtime_channel_for_ssi(io) \
++	rsnd_runtime_channel_for_ssi_with_params(io, NULL)
++int rsnd_runtime_channel_for_ssi_with_params(struct rsnd_dai_stream *io,
++				 struct snd_pcm_hw_params *params);
+ int rsnd_runtime_is_ssi_multi(struct rsnd_dai_stream *io);
+ int rsnd_runtime_is_ssi_tdm(struct rsnd_dai_stream *io);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0562-ASoC-rsnd-dma.c-spin-lock-is-no-longer-needed-in-IRQ.patch b/patches/0562-ASoC-rsnd-dma.c-spin-lock-is-no-longer-needed-in-IRQ.patch
new file mode 100644
index 00000000000000..59932b9a434b30
--- /dev/null
+++ b/patches/0562-ASoC-rsnd-dma.c-spin-lock-is-no-longer-needed-in-IRQ.patch
@@ -0,0 +1,51 @@
+From 2bf86be33f364709618828a27d000ebd21e444de Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 29 Nov 2017 03:08:35 +0000
+Subject: [PATCH 0562/1795] ASoC: rsnd: dma.c: spin lock is no longer needed in
+ IRQ handler
+
+DMA handler had needed to calculate pointer before, but it doesn't
+need now. Thus, we can remove unnecessary spin lock from DMAC handler.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 65bedda1feec4f57e1322a200853cc29079b01c6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/dma.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 4d750bdf8e24..41de23417c4a 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -71,25 +71,7 @@ static struct rsnd_mod mem = {
+ static void __rsnd_dmaen_complete(struct rsnd_mod *mod,
+ 				  struct rsnd_dai_stream *io)
+ {
+-	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
+-	bool elapsed = false;
+-	unsigned long flags;
+-
+-	/*
+-	 * Renesas sound Gen1 needs 1 DMAC,
+-	 * Gen2 needs 2 DMAC.
+-	 * In Gen2 case, it are Audio-DMAC, and Audio-DMAC-peri-peri.
+-	 * But, Audio-DMAC-peri-peri doesn't have interrupt,
+-	 * and this driver is assuming that here.
+-	 */
+-	spin_lock_irqsave(&priv->lock, flags);
+-
+ 	if (rsnd_io_is_working(io))
+-		elapsed = true;
+-
+-	spin_unlock_irqrestore(&priv->lock, flags);
+-
+-	if (elapsed)
+ 		rsnd_dai_period_elapsed(io);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0563-ASoC-rsnd-ssi-remove-unnesessary-period_pos.patch b/patches/0563-ASoC-rsnd-ssi-remove-unnesessary-period_pos.patch
new file mode 100644
index 00000000000000..e790b5ba463269
--- /dev/null
+++ b/patches/0563-ASoC-rsnd-ssi-remove-unnesessary-period_pos.patch
@@ -0,0 +1,62 @@
+From 33dad168d5257bfdcb6f97812ea4d2d81b936b43 Mon Sep 17 00:00:00 2001
+From: Jiada Wang <jiada_wang@mentor.com>
+Date: Thu, 7 Dec 2017 22:15:39 -0800
+Subject: [PATCH 0563/1795] ASoC: rsnd: ssi: remove unnesessary period_pos
+
+period_pos can always be calculated by byte_pos and
+byte_per_period, there is no reason to maintain this
+variable in rsnd_dai_stream.
+
+This patch removes period_pos from rsnd_ssi and calculates
+next_period_byte with consideration of actual byte_pos value.
+
+Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 2e2d53da81af6b2222c6b4e025a5d01b37b4449b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index cbf3bf312d23..f21202429000 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -80,7 +80,6 @@ struct rsnd_ssi {
+ 	unsigned int usrcnt;
+ 
+ 	int byte_pos;
+-	int period_pos;
+ 	int byte_per_period;
+ 	int next_period_byte;
+ };
+@@ -421,7 +420,6 @@ static void rsnd_ssi_pointer_init(struct rsnd_mod *mod,
+ 	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+ 
+ 	ssi->byte_pos		= 0;
+-	ssi->period_pos		= 0;
+ 	ssi->byte_per_period	= runtime->period_size *
+ 				  runtime->channels *
+ 				  samples_to_bytes(runtime, 1);
+@@ -453,13 +451,12 @@ static bool rsnd_ssi_pointer_update(struct rsnd_mod *mod,
+ 
+ 	if (byte_pos >= ssi->next_period_byte) {
+ 		struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
++		int period_pos = byte_pos / ssi->byte_per_period;
+ 
+-		ssi->period_pos++;
+-		ssi->next_period_byte += ssi->byte_per_period;
++		ssi->next_period_byte = (period_pos + 1) * ssi->byte_per_period;
+ 
+-		if (ssi->period_pos >= runtime->periods) {
++		if (period_pos >= runtime->periods) {
+ 			byte_pos = 0;
+-			ssi->period_pos = 0;
+ 			ssi->next_period_byte = ssi->byte_per_period;
+ 		}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0564-ASoC-rsnd-more-clear-rsnd_get_dalign-for-DALIGN.patch b/patches/0564-ASoC-rsnd-more-clear-rsnd_get_dalign-for-DALIGN.patch
new file mode 100644
index 00000000000000..e1f867b78d28d9
--- /dev/null
+++ b/patches/0564-ASoC-rsnd-more-clear-rsnd_get_dalign-for-DALIGN.patch
@@ -0,0 +1,78 @@
+From 816716fd70ed7b6a8b58c4b71a2237011c90c810 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 8 Dec 2017 06:23:11 +0000
+Subject: [PATCH 0564/1795] ASoC: rsnd: more clear rsnd_get_dalign() for DALIGN
+
+On Renesas sound device, DALIGN which exchanges channel position
+is needed because SW and HW are using defferent data order if
+16bit data. It is not needed when 24bit data.
+rsnd_get_dalign() returns necessary value, but it was confusable
+code. This patch makes it more simple.
+
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit a914e44693d41ba43604afa8c435c98a6d2c7cb1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 33 ++++++++++-----------------------
+ 1 file changed, 10 insertions(+), 23 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index d76ad46a6fd9..8e50b284230d 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -294,11 +294,12 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
+ 	struct rsnd_mod *ssiu = rsnd_io_to_mod_ssiu(io);
+ 	struct rsnd_mod *target;
+ 	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+-	u32 val = 0x76543210;
+-	u32 mask = ~0;
+ 
+ 	/*
+-	 * *Hardware* L/R and *Software* L/R are inverted.
++	 * *Hardware* L/R and *Software* L/R are inverted for 16bit data.
++	 *	    31..16 15...0
++	 *	HW: [L ch] [R ch]
++	 *	SW: [R ch] [L ch]
+ 	 * We need to care about inversion timing to control
+ 	 * Playback/Capture correctly.
+ 	 * The point is [DVC] needs *Hardware* L/R, [MEM] needs *Software* L/R
+@@ -325,27 +326,13 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
+ 		target = cmd ? cmd : ssiu;
+ 	}
+ 
+-	mask <<= runtime->channels * 4;
+-	val = val & mask;
+-
+-	switch (runtime->sample_bits) {
+-	case 16:
+-		val |= 0x67452301 & ~mask;
+-		break;
+-	case 32:
+-		val |= 0x76543210 & ~mask;
+-		break;
+-	}
+-
+-	/*
+-	 * exchange channeles on SRC if possible,
+-	 * otherwise, R/L volume settings on DVC
+-	 * changes inverted channels
+-	 */
+-	if (mod == target)
+-		return val;
+-	else
++	/* Non target mod or 24bit data needs normal DALIGN */
++	if ((runtime->sample_bits != 16) ||
++	    (mod != target))
+ 		return 0x76543210;
++	/* Target mod needs inverted DALIGN when 16bit */
++	else
++		return 0x67452301;
+ }
+ 
+ u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod)
+-- 
+2.19.0
+
diff --git a/patches/0565-ASoC-rsnd-don-t-use-runtime-sample_bits.patch b/patches/0565-ASoC-rsnd-don-t-use-runtime-sample_bits.patch
new file mode 100644
index 00000000000000..239aed5162875e
--- /dev/null
+++ b/patches/0565-ASoC-rsnd-don-t-use-runtime-sample_bits.patch
@@ -0,0 +1,95 @@
+From d44783a99b5f0319133e9da9e94a6a13b75880ff Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 11 Dec 2017 02:24:23 +0000
+Subject: [PATCH 0565/1795] ASoC: rsnd: don't use runtime->sample_bits
+
+Current rsnd driver is judging 16bit/24bit data by using
+runtime->sample_bits, but it is indicating physical size,
+not format size. This is confusable code.
+This patch uses snd_pcm_format_width() to be more correct code.
+
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 41acc8ec04f32abb16e035ca1c9fe4d52819601e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 12 ++++--------
+ sound/soc/sh/rcar/ssi.c  |  9 +++------
+ 2 files changed, 7 insertions(+), 14 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 8e50b284230d..a96ebebd96de 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -274,10 +274,10 @@ u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
+ 	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+ 	struct device *dev = rsnd_priv_to_dev(priv);
+ 
+-	switch (runtime->sample_bits) {
++	switch (snd_pcm_format_width(runtime->format)) {
+ 	case 16:
+ 		return 8 << 16;
+-	case 32:
++	case 24:
+ 		return 0 << 16;
+ 	}
+ 
+@@ -327,7 +327,7 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
+ 	}
+ 
+ 	/* Non target mod or 24bit data needs normal DALIGN */
+-	if ((runtime->sample_bits != 16) ||
++	if ((snd_pcm_format_width(runtime->format) != 16) ||
+ 	    (mod != target))
+ 		return 0x76543210;
+ 	/* Target mod needs inverted DALIGN when 16bit */
+@@ -362,12 +362,8 @@ u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod)
+ 	 * HW    24bit data is located as 0x******00
+ 	 *
+ 	 */
+-	switch (runtime->sample_bits) {
+-	case 16:
++	if (snd_pcm_format_width(runtime->format) == 16)
+ 		return 0;
+-	case 32:
+-		break;
+-	}
+ 
+ 	for (i = 0; i < ARRAY_SIZE(playback_mods); i++) {
+ 		tmod = rsnd_io_to_mod(io, mods[i]);
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index f21202429000..5a70fdc3c680 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -370,11 +370,11 @@ static void rsnd_ssi_config_init(struct rsnd_mod *mod,
+ 	if (rsnd_io_is_play(io))
+ 		cr_own |= TRMD;
+ 
+-	switch (runtime->sample_bits) {
++	switch (snd_pcm_format_width(runtime->format)) {
+ 	case 16:
+ 		cr_own |= DWL_16;
+ 		break;
+-	case 32:
++	case 24:
+ 		cr_own |= DWL_24;
+ 		break;
+ 	}
+@@ -677,11 +677,8 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
+ 				   rsnd_ssi_pointer_offset(mod, io, 0));
+ 		int shift = 0;
+ 
+-		switch (runtime->sample_bits) {
+-		case 32:
++		if (snd_pcm_format_width(runtime->format) == 24)
+ 			shift = 8;
+-			break;
+-		}
+ 
+ 		/*
+ 		 * 8/16/32 data can be assesse to TDR/RDR register
+-- 
+2.19.0
+
diff --git a/patches/0566-ASoC-rsnd-PIO-related-function-cleanup.patch b/patches/0566-ASoC-rsnd-PIO-related-function-cleanup.patch
new file mode 100644
index 00000000000000..b727ce3de83cbc
--- /dev/null
+++ b/patches/0566-ASoC-rsnd-PIO-related-function-cleanup.patch
@@ -0,0 +1,234 @@
+From df1da8b1334df058f4f8e245d3b992df488fd9b0 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 11 Dec 2017 02:40:22 +0000
+Subject: [PATCH 0566/1795] ASoC: rsnd: PIO related function cleanup
+
+SSI had shared counting pointer position method between PIO/DMA mode
+before. But now DMA mode is using DMAEngine feature to get it.
+Thus, this counting pointer position method is needed for only PIO mode.
+We don't need to share code anymore.
+This patch names PIO related functions as rsnd_ssi_pio_xxx(), and
+merged/cleanuped each feature.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit d8d9b9730cd62c9c7d24d5277542da98c09ea728)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 153 +++++++++++++++++++---------------------
+ 1 file changed, 72 insertions(+), 81 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index 5a70fdc3c680..97a9db892a8f 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -79,6 +79,7 @@ struct rsnd_ssi {
+ 	int irq;
+ 	unsigned int usrcnt;
+ 
++	/* for PIO */
+ 	int byte_pos;
+ 	int byte_per_period;
+ 	int next_period_byte;
+@@ -413,61 +414,6 @@ static void rsnd_ssi_register_setup(struct rsnd_mod *mod)
+ 					ssi->cr_en);
+ }
+ 
+-static void rsnd_ssi_pointer_init(struct rsnd_mod *mod,
+-				  struct rsnd_dai_stream *io)
+-{
+-	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
+-	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+-
+-	ssi->byte_pos		= 0;
+-	ssi->byte_per_period	= runtime->period_size *
+-				  runtime->channels *
+-				  samples_to_bytes(runtime, 1);
+-	ssi->next_period_byte	= ssi->byte_per_period;
+-}
+-
+-static int rsnd_ssi_pointer_offset(struct rsnd_mod *mod,
+-				   struct rsnd_dai_stream *io,
+-				   int additional)
+-{
+-	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
+-	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+-	int pos = ssi->byte_pos + additional;
+-
+-	pos %= (runtime->periods * ssi->byte_per_period);
+-
+-	return pos;
+-}
+-
+-static bool rsnd_ssi_pointer_update(struct rsnd_mod *mod,
+-				    struct rsnd_dai_stream *io,
+-				    int byte)
+-{
+-	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
+-	bool ret = false;
+-	int byte_pos;
+-
+-	byte_pos = ssi->byte_pos + byte;
+-
+-	if (byte_pos >= ssi->next_period_byte) {
+-		struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+-		int period_pos = byte_pos / ssi->byte_per_period;
+-
+-		ssi->next_period_byte = (period_pos + 1) * ssi->byte_per_period;
+-
+-		if (period_pos >= runtime->periods) {
+-			byte_pos = 0;
+-			ssi->next_period_byte = ssi->byte_per_period;
+-		}
+-
+-		ret = true;
+-	}
+-
+-	WRITE_ONCE(ssi->byte_pos, byte_pos);
+-
+-	return ret;
+-}
+-
+ /*
+  *	SSI mod common functions
+  */
+@@ -481,8 +427,6 @@ static int rsnd_ssi_init(struct rsnd_mod *mod,
+ 	if (!rsnd_ssi_is_run_mods(mod, io))
+ 		return 0;
+ 
+-	rsnd_ssi_pointer_init(mod, io);
+-
+ 	ssi->usrcnt++;
+ 
+ 	rsnd_mod_power_on(mod);
+@@ -653,6 +597,8 @@ static int rsnd_ssi_irq(struct rsnd_mod *mod,
+ 	return 0;
+ }
+ 
++static bool rsnd_ssi_pio_interrupt(struct rsnd_mod *mod,
++				   struct rsnd_dai_stream *io);
+ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
+ 				 struct rsnd_dai_stream *io)
+ {
+@@ -671,27 +617,8 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
+ 	status = rsnd_ssi_status_get(mod);
+ 
+ 	/* PIO only */
+-	if (!is_dma && (status & DIRQ)) {
+-		struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+-		u32 *buf = (u32 *)(runtime->dma_area +
+-				   rsnd_ssi_pointer_offset(mod, io, 0));
+-		int shift = 0;
+-
+-		if (snd_pcm_format_width(runtime->format) == 24)
+-			shift = 8;
+-
+-		/*
+-		 * 8/16/32 data can be assesse to TDR/RDR register
+-		 * directly as 32bit data
+-		 * see rsnd_ssi_init()
+-		 */
+-		if (rsnd_io_is_play(io))
+-			rsnd_mod_write(mod, SSITDR, (*buf) << shift);
+-		else
+-			*buf = (rsnd_mod_read(mod, SSIRDR) >> shift);
+-
+-		elapsed = rsnd_ssi_pointer_update(mod, io, sizeof(*buf));
+-	}
++	if (!is_dma && (status & DIRQ))
++		elapsed = rsnd_ssi_pio_interrupt(mod, io);
+ 
+ 	/* DMA only */
+ 	if (is_dma && (status & (UIRQ | OIRQ)))
+@@ -829,7 +756,71 @@ static int rsnd_ssi_common_remove(struct rsnd_mod *mod,
+ 	return 0;
+ }
+ 
+-static int rsnd_ssi_pointer(struct rsnd_mod *mod,
++/*
++ *	SSI PIO functions
++ */
++static bool rsnd_ssi_pio_interrupt(struct rsnd_mod *mod,
++				   struct rsnd_dai_stream *io)
++{
++	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
++	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
++	u32 *buf = (u32 *)(runtime->dma_area + ssi->byte_pos);
++	int shift = 0;
++	int byte_pos;
++	bool elapsed = false;
++
++	if (snd_pcm_format_width(runtime->format) == 24)
++		shift = 8;
++
++	/*
++	 * 8/16/32 data can be assesse to TDR/RDR register
++	 * directly as 32bit data
++	 * see rsnd_ssi_init()
++	 */
++	if (rsnd_io_is_play(io))
++		rsnd_mod_write(mod, SSITDR, (*buf) << shift);
++	else
++		*buf = (rsnd_mod_read(mod, SSIRDR) >> shift);
++
++	byte_pos = ssi->byte_pos + sizeof(*buf);
++
++	if (byte_pos >= ssi->next_period_byte) {
++		int period_pos = byte_pos / ssi->byte_per_period;
++
++		if (period_pos >= runtime->periods) {
++			byte_pos = 0;
++			period_pos = 0;
++		}
++
++		ssi->next_period_byte = (period_pos + 1) * ssi->byte_per_period;
++
++		elapsed = true;
++	}
++
++	WRITE_ONCE(ssi->byte_pos, byte_pos);
++
++	return elapsed;
++}
++
++static int rsnd_ssi_pio_init(struct rsnd_mod *mod,
++			     struct rsnd_dai_stream *io,
++			     struct rsnd_priv *priv)
++{
++	struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
++	struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
++
++	if (!rsnd_ssi_is_parent(mod, io)) {
++		ssi->byte_pos		= 0;
++		ssi->byte_per_period	= runtime->period_size *
++					  runtime->channels *
++					  samples_to_bytes(runtime, 1);
++		ssi->next_period_byte	= ssi->byte_per_period;
++	}
++
++	return rsnd_ssi_init(mod, io, priv);
++}
++
++static int rsnd_ssi_pio_pointer(struct rsnd_mod *mod,
+ 			    struct rsnd_dai_stream *io,
+ 			    snd_pcm_uframes_t *pointer)
+ {
+@@ -845,12 +836,12 @@ static struct rsnd_mod_ops rsnd_ssi_pio_ops = {
+ 	.name	= SSI_NAME,
+ 	.probe	= rsnd_ssi_common_probe,
+ 	.remove	= rsnd_ssi_common_remove,
+-	.init	= rsnd_ssi_init,
++	.init	= rsnd_ssi_pio_init,
+ 	.quit	= rsnd_ssi_quit,
+ 	.start	= rsnd_ssi_start,
+ 	.stop	= rsnd_ssi_stop,
+ 	.irq	= rsnd_ssi_irq,
+-	.pointer= rsnd_ssi_pointer,
++	.pointer = rsnd_ssi_pio_pointer,
+ 	.pcm_new = rsnd_ssi_pcm_new,
+ 	.hw_params = rsnd_ssi_hw_params,
+ };
+-- 
+2.19.0
+
diff --git a/patches/0567-ASoC-rsnd-remove-unneeded-is_graph-from-__rsnd_dai_p.patch b/patches/0567-ASoC-rsnd-remove-unneeded-is_graph-from-__rsnd_dai_p.patch
new file mode 100644
index 00000000000000..1b25e2f98fd98c
--- /dev/null
+++ b/patches/0567-ASoC-rsnd-remove-unneeded-is_graph-from-__rsnd_dai_p.patch
@@ -0,0 +1,47 @@
+From b4eb398f566c86b3d785baa48c9e83ece43b7931 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 11 Dec 2017 02:43:41 +0000
+Subject: [PATCH 0567/1795] ASoC: rsnd: remove unneeded "is_graph" from
+ __rsnd_dai_probe()
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 9f761183947b91aacc4ed5c2a1a39ac08b938b6c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index a96ebebd96de..64d5ecb86528 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1017,7 +1017,7 @@ static struct device_node *rsnd_dai_of_node(struct rsnd_priv *priv,
+ 
+ static void __rsnd_dai_probe(struct rsnd_priv *priv,
+ 			     struct device_node *dai_np,
+-			     int dai_i, int is_graph)
++			     int dai_i)
+ {
+ 	struct device_node *playback, *capture;
+ 	struct rsnd_dai_stream *io_playback;
+@@ -1116,13 +1116,13 @@ static int rsnd_dai_probe(struct rsnd_priv *priv)
+ 	dai_i = 0;
+ 	if (is_graph) {
+ 		for_each_endpoint_of_node(dai_node, dai_np) {
+-			__rsnd_dai_probe(priv, dai_np, dai_i, is_graph);
++			__rsnd_dai_probe(priv, dai_np, dai_i);
+ 			rsnd_ssi_parse_hdmi_connection(priv, dai_np, dai_i);
+ 			dai_i++;
+ 		}
+ 	} else {
+ 		for_each_child_of_node(dai_node, dai_np)
+-			__rsnd_dai_probe(priv, dai_np, dai_i++, is_graph);
++			__rsnd_dai_probe(priv, dai_np, dai_i++);
+ 	}
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0568-ASoC-rsnd-Add-device-tree-support-for-r8a774-35.patch b/patches/0568-ASoC-rsnd-Add-device-tree-support-for-r8a774-35.patch
new file mode 100644
index 00000000000000..259522831bdad3
--- /dev/null
+++ b/patches/0568-ASoC-rsnd-Add-device-tree-support-for-r8a774-35.patch
@@ -0,0 +1,50 @@
+From c5131327874d0008d473d008cdc7218cc4431402 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:09:15 +0000
+Subject: [PATCH 0568/1795] ASoC: rsnd: Add device tree support for r8a774[35]
+
+Document r8a774[35] specific compatible strings. The Renesas RZ/G1[ME]
+(r8a774[35]) sound modules are identical to the R-Car Gen2 family.
+No driver change is needed as the fallback compatible string
+"renesas,rcar_sound-gen2" activates the right code in the driver.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit b0a858a47a7889757dbc9ac9872685955eaa5cc0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+index 085bec364caf..b3c28bdcc268 100644
+--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
++++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+@@ -4,7 +4,7 @@ Renesas R-Car sound
+ * Modules
+ =============================================
+ 
+-Renesas R-Car sound is constructed from below modules
++Renesas R-Car and RZ/G sound is constructed from below modules
+ (for Gen2 or later)
+ 
+  SCU		: Sampling Rate Converter Unit
+@@ -334,9 +334,11 @@ Required properties:
+ 
+ - compatible			: "renesas,rcar_sound-<soctype>", fallbacks
+ 				  "renesas,rcar_sound-gen1" if generation1, and
+-				  "renesas,rcar_sound-gen2" if generation2
++				  "renesas,rcar_sound-gen2" if generation2 (or RZ/G1)
+ 				  "renesas,rcar_sound-gen3" if generation3
+ 				  Examples with soctypes are:
++				    - "renesas,rcar_sound-r8a7743" (RZ/G1M)
++				    - "renesas,rcar_sound-r8a7745" (RZ/G1E)
+ 				    - "renesas,rcar_sound-r8a7778" (R-Car M1A)
+ 				    - "renesas,rcar_sound-r8a7779" (R-Car H1)
+ 				    - "renesas,rcar_sound-r8a7790" (R-Car H2)
+-- 
+2.19.0
+
diff --git a/patches/0569-ASoC-rcar-tidyup-simple-card-example-for-CPU-node.patch b/patches/0569-ASoC-rcar-tidyup-simple-card-example-for-CPU-node.patch
new file mode 100644
index 00000000000000..866fb567935865
--- /dev/null
+++ b/patches/0569-ASoC-rcar-tidyup-simple-card-example-for-CPU-node.patch
@@ -0,0 +1,48 @@
+From 2c469e9c9ee8d464501df31a356ff50f45cc4299 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 22 Dec 2017 05:29:03 +0000
+Subject: [PATCH 0569/1795] ASoC: rcar: tidyup simple-card example for CPU node
+
+commit a5702e1cb3c ("ASoC: rsnd: Drop unit-addresses without reg
+properties") modifies simple-card multi CPU nodes.
+But, naming of "cpu-x" breaks probing.
+Let's add reg = <x>; instead of renaming node.
+
+Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+CC: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 2ca69d73bc05a55edb95689d436ce87974a3162e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+index b3c28bdcc268..5bed9a595772 100644
+--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
++++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+@@ -197,12 +197,17 @@ Ex)
+ 	[MEM] -> [SRC2] -> [CTU03] -+
+ 
+ 	sound {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
+ 		compatible = "simple-scu-audio-card";
+ 		...
+-		simple-audio-card,cpu-0 {
++		simple-audio-card,cpu@0 {
++			reg = <0>;
+ 			sound-dai = <&rcar_sound 0>;
+ 		};
+-		simple-audio-card,cpu-1 {
++		simple-audio-card,cpu@1 {
++			reg = <1>;
+ 			sound-dai = <&rcar_sound 1>;
+ 		};
+ 		simple-audio-card,codec {
+-- 
+2.19.0
+
diff --git a/patches/0570-mtd-spi-nor-add-spi_nor_init-function.patch b/patches/0570-mtd-spi-nor-add-spi_nor_init-function.patch
new file mode 100644
index 00000000000000..5cd4d0d2111215
--- /dev/null
+++ b/patches/0570-mtd-spi-nor-add-spi_nor_init-function.patch
@@ -0,0 +1,175 @@
+From 416bf00ddf78aba78ba2c99805e9cedabf5691a2 Mon Sep 17 00:00:00 2001
+From: Kamal Dasu <kdasu.kdev@gmail.com>
+Date: Tue, 22 Aug 2017 16:45:21 -0400
+Subject: [PATCH 0570/1795] mtd: spi-nor: add spi_nor_init() function
+
+This patch extracts some chunks from spi_nor_init_params and spi_nor_scan()
+ and moves them into a new spi_nor_init() function.
+
+Indeed, spi_nor_init() regroups all the required SPI flash commands to be
+sent to the SPI flash memory before performing any runtime operations
+(Fast Read, Page Program, Sector Erase, ...). Hence spi_nor_init():
+1) removes the flash protection if applicable for certain vendors.
+2) sets the Quad Enable bit, if needed, before using Quad SPI protocols.
+3) makes the memory enter its (stateful) 4-byte address mode, if needed,
+   for SPI flash memory > 128Mbits not supporting the 4-byte address
+   instruction set.
+
+spi_nor_scan() now ends by calling spi_nor_init() once the probe phase has
+completed. Further patches could also use spi_nor_init() to implement the
+mtd->_resume() handler for the spi-nor framework.
+
+Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+(cherry picked from commit 46dde01f6bab35d99af111fcc02ca3ee1146050f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 56 ++++++++++++++++++++++++-----------
+ include/linux/mtd/spi-nor.h   | 10 +++++++
+ 2 files changed, 48 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index 52056198f457..4daec97e9997 100644
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -2631,14 +2631,44 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
+ 	/* Enable Quad I/O if needed. */
+ 	enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ 			  spi_nor_get_protocol_width(nor->write_proto) == 4);
+-	if (enable_quad_io && params->quad_enable) {
+-		err = params->quad_enable(nor);
++	if (enable_quad_io && params->quad_enable)
++		nor->quad_enable = params->quad_enable;
++	else
++		nor->quad_enable = NULL;
++
++	return 0;
++}
++
++static int spi_nor_init(struct spi_nor *nor)
++{
++	int err;
++
++	/*
++	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
++	 * with the software protection bits set
++	 */
++	if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
++	    JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
++	    JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
++	    nor->info->flags & SPI_NOR_HAS_LOCK) {
++		write_enable(nor);
++		write_sr(nor, 0);
++		spi_nor_wait_till_ready(nor);
++	}
++
++	if (nor->quad_enable) {
++		err = nor->quad_enable(nor);
+ 		if (err) {
+ 			dev_err(nor->dev, "quad mode not supported\n");
+ 			return err;
+ 		}
+ 	}
+ 
++	if ((nor->addr_width == 4) &&
++	    (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
++	    !(nor->info->flags & SPI_NOR_4B_OPCODES))
++		set_4byte(nor, nor->info, 1);
++
+ 	return 0;
+ }
+ 
+@@ -2709,20 +2739,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
+ 	if (ret)
+ 		return ret;
+ 
+-	/*
+-	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
+-	 * with the software protection bits set
+-	 */
+-
+-	if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
+-	    JEDEC_MFR(info) == SNOR_MFR_INTEL ||
+-	    JEDEC_MFR(info) == SNOR_MFR_SST ||
+-	    info->flags & SPI_NOR_HAS_LOCK) {
+-		write_enable(nor);
+-		write_sr(nor, 0);
+-		spi_nor_wait_till_ready(nor);
+-	}
+-
+ 	if (!mtd->name)
+ 		mtd->name = dev_name(dev);
+ 	mtd->priv = nor;
+@@ -2805,8 +2821,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
+ 		if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
+ 		    info->flags & SPI_NOR_4B_OPCODES)
+ 			spi_nor_set_4byte_opcodes(nor, info);
+-		else
+-			set_4byte(nor, info, 1);
+ 	} else {
+ 		nor->addr_width = 3;
+ 	}
+@@ -2823,6 +2837,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
+ 			return ret;
+ 	}
+ 
++	/* Send all the required SPI flash commands to initialize device */
++	nor->info = info;
++	ret = spi_nor_init(nor);
++	if (ret)
++		return ret;
++
+ 	dev_info(dev, "%s (%lld Kbytes)\n", info->name,
+ 			(long long)mtd->size >> 10);
+ 
+diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
+index 1f0a7fc7772f..d0c66a0975cf 100644
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -231,11 +231,18 @@ enum spi_nor_option_flags {
+ 	SNOR_F_USE_CLSR		= BIT(5),
+ };
+ 
++/**
++ * struct flash_info - Forward declaration of a structure used internally by
++ *		       spi_nor_scan()
++ */
++struct flash_info;
++
+ /**
+  * struct spi_nor - Structure for defining a the SPI NOR layer
+  * @mtd:		point to a mtd_info structure
+  * @lock:		the lock for the read/write/erase/lock/unlock operations
+  * @dev:		point to a spi device, or a spi nor controller device.
++ * @info:		spi-nor part JDEC MFR id and other info
+  * @page_size:		the page size of the SPI NOR
+  * @addr_width:		number of address bytes
+  * @erase_opcode:	the opcode for erasing a sector
+@@ -262,6 +269,7 @@ enum spi_nor_option_flags {
+  * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
+  * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
+  * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
++ * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
+  *			completely locked
+  * @priv:		the private data
+  */
+@@ -269,6 +277,7 @@ struct spi_nor {
+ 	struct mtd_info		mtd;
+ 	struct mutex		lock;
+ 	struct device		*dev;
++	const struct flash_info	*info;
+ 	u32			page_size;
+ 	u8			addr_width;
+ 	u8			erase_opcode;
+@@ -296,6 +305,7 @@ struct spi_nor {
+ 	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+ 	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+ 	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
++	int (*quad_enable)(struct spi_nor *nor);
+ 
+ 	void *priv;
+ };
+-- 
+2.19.0
+
diff --git a/patches/0571-mtd-spi-nor-add-an-API-to-restore-the-status-of-SPI-.patch b/patches/0571-mtd-spi-nor-add-an-API-to-restore-the-status-of-SPI-.patch
new file mode 100644
index 00000000000000..94ecef242bac46
--- /dev/null
+++ b/patches/0571-mtd-spi-nor-add-an-API-to-restore-the-status-of-SPI-.patch
@@ -0,0 +1,71 @@
+From 332f6b3068078bfc3b9235ebf8dae07d126564c3 Mon Sep 17 00:00:00 2001
+From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Date: Wed, 6 Dec 2017 10:53:41 +0800
+Subject: [PATCH 0571/1795] mtd: spi-nor: add an API to restore the status of
+ SPI flash chip
+
+Add this API to restore the status of SPI flash chip to the default
+such as addressing mode, whenever detach the driver from device or
+reboot the system.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+(cherry picked from commit 8dee1d971af9af2f7b5f54c2eac4ebd04c5c237c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/mtd/spi-nor.txt |  3 +++
+ drivers/mtd/spi-nor/spi-nor.c | 10 ++++++++++
+ include/linux/mtd/spi-nor.h   |  6 ++++++
+ 3 files changed, 19 insertions(+)
+
+diff --git a/Documentation/mtd/spi-nor.txt b/Documentation/mtd/spi-nor.txt
+index 548d6306ebca..da1fbff5a24c 100644
+--- a/Documentation/mtd/spi-nor.txt
++++ b/Documentation/mtd/spi-nor.txt
+@@ -60,3 +60,6 @@ The main API is spi_nor_scan(). Before you call the hook, a driver should
+ initialize the necessary fields for spi_nor{}. Please see
+ drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to fsl-quadspi.c
+ when you want to write a new driver for a SPI NOR controller.
++Another API is spi_nor_restore(), this is used to restore the status of SPI
++flash chip such as addressing mode. Call it whenever detach the driver from
++device or reboot the system.
+diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index 4daec97e9997..d458523716d7 100644
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -2672,6 +2672,16 @@ static int spi_nor_init(struct spi_nor *nor)
+ 	return 0;
+ }
+ 
++void spi_nor_restore(struct spi_nor *nor)
++{
++	/* restore the addressing mode */
++	if ((nor->addr_width == 4) &&
++	    (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
++	    !(nor->info->flags & SPI_NOR_4B_OPCODES))
++		set_4byte(nor, nor->info, 0);
++}
++EXPORT_SYMBOL_GPL(spi_nor_restore);
++
+ int spi_nor_scan(struct spi_nor *nor, const char *name,
+ 		 const struct spi_nor_hwcaps *hwcaps)
+ {
+diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
+index d0c66a0975cf..db78a3c22126 100644
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -399,4 +399,10 @@ struct spi_nor_hwcaps {
+ int spi_nor_scan(struct spi_nor *nor, const char *name,
+ 		 const struct spi_nor_hwcaps *hwcaps);
+ 
++/**
++ * spi_nor_restore_addr_mode() - restore the status of SPI NOR
++ * @nor:	the spi_nor structure
++ */
++void spi_nor_restore(struct spi_nor *nor);
++
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0572-mtd-m25p80-restore-the-status-of-SPI-flash-when-exit.patch b/patches/0572-mtd-m25p80-restore-the-status-of-SPI-flash-when-exit.patch
new file mode 100644
index 00000000000000..414cf29f627d4b
--- /dev/null
+++ b/patches/0572-mtd-m25p80-restore-the-status-of-SPI-flash-when-exit.patch
@@ -0,0 +1,58 @@
+From 22aeb2a52c1c2e27cc8d8aa0bef88026ac83c109 Mon Sep 17 00:00:00 2001
+From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Date: Wed, 6 Dec 2017 10:53:42 +0800
+Subject: [PATCH 0572/1795] mtd: m25p80: restore the status of SPI flash when
+ exiting
+
+Restore the status to be compatible with legacy devices.
+Take Freescale eSPI boot for example, it copies (in 3 Byte
+addressing mode) the RCW and bootloader images from SPI flash
+without firing a reset signal previously, so the reboot command
+will fail without resetting the addressing mode of SPI flash.
+This patch implements .shutdown function to restore the status
+in reboot process, and add the same operation to the .remove
+function.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+(cherry picked from commit 59b356ffd0b00ed986c0aa1b401dd9b466ee619d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mtd/devices/m25p80.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index dbe6a1de2bb8..a4e18f6aaa33 100644
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -307,10 +307,18 @@ static int m25p_remove(struct spi_device *spi)
+ {
+ 	struct m25p	*flash = spi_get_drvdata(spi);
+ 
++	spi_nor_restore(&flash->spi_nor);
++
+ 	/* Clean up MTD stuff. */
+ 	return mtd_device_unregister(&flash->spi_nor.mtd);
+ }
+ 
++static void m25p_shutdown(struct spi_device *spi)
++{
++	struct m25p *flash = spi_get_drvdata(spi);
++
++	spi_nor_restore(&flash->spi_nor);
++}
+ /*
+  * Do NOT add to this array without reading the following:
+  *
+@@ -386,6 +394,7 @@ static struct spi_driver m25p80_driver = {
+ 	.id_table	= m25p_ids,
+ 	.probe	= m25p_probe,
+ 	.remove	= m25p_remove,
++	.shutdown	= m25p_shutdown,
+ 
+ 	/* REVISIT: many of these chips have deep power-down modes, which
+ 	 * should clearly be entered on suspend() to minimize power use.
+-- 
+2.19.0
+
diff --git a/patches/0573-tty-serial-sh-sci-Hide-number-of-ports-config-questi.patch b/patches/0573-tty-serial-sh-sci-Hide-number-of-ports-config-questi.patch
new file mode 100644
index 00000000000000..20eaf447f12443
--- /dev/null
+++ b/patches/0573-tty-serial-sh-sci-Hide-number-of-ports-config-questi.patch
@@ -0,0 +1,44 @@
+From 85a689b37a4907ec754bdfaf4cbbbcc2cce1162e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 14:11:58 +0100
+Subject: [PATCH 0573/1795] tty: serial: sh-sci: Hide number of ports config
+ question
+
+Auto-configure the maximum number of serial ports based on how many can
+be present on the architecture:
+  - 3 on H8/300,
+  - 10 on SuperH,
+  - 18 on Reneas ARM.
+
+The default can still be overridden if CONFIG_EXPERT is enabled.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit f6731485a51978ca0931c787fcb8a0bc4dcc9303)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index b788fee54249..bd96046d7f94 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -761,9 +761,11 @@ config SERIAL_SH_SCI
+ 	select SERIAL_MCTRL_GPIO if GPIOLIB
+ 
+ config SERIAL_SH_SCI_NR_UARTS
+-	int "Maximum number of SCI(F) serial ports"
++	int "Maximum number of SCI(F) serial ports" if EXPERT
+ 	depends on SERIAL_SH_SCI
+-	default "2"
++	default "3" if H8300
++	default "10" if SUPERH
++	default "18" if ARCH_RENESAS
+ 
+ config SERIAL_SH_SCI_CONSOLE
+ 	bool "Support for console on SuperH SCI(F)"
+-- 
+2.19.0
+
diff --git a/patches/0574-tty-serial-sh-sci-Hide-serial-console-config-questio.patch b/patches/0574-tty-serial-sh-sci-Hide-serial-console-config-questio.patch
new file mode 100644
index 00000000000000..c0073ec685f62c
--- /dev/null
+++ b/patches/0574-tty-serial-sh-sci-Hide-serial-console-config-questio.patch
@@ -0,0 +1,38 @@
+From 168965ed2b54f666a226c8f153ca0c2feebf5bc1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 14:11:59 +0100
+Subject: [PATCH 0574/1795] tty: serial: sh-sci: Hide serial console config
+ question
+
+Most users will want to use a serial console.
+
+Hence make that the default, unless CONFIG_EXPERT is enabled.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit c5bb576d5e21e91a6380b8dd927ee4ceadbc23d5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index bd96046d7f94..0c75562d620f 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -768,9 +768,10 @@ config SERIAL_SH_SCI_NR_UARTS
+ 	default "18" if ARCH_RENESAS
+ 
+ config SERIAL_SH_SCI_CONSOLE
+-	bool "Support for console on SuperH SCI(F)"
++	bool "Support for console on SuperH SCI(F)" if EXPERT
+ 	depends on SERIAL_SH_SCI=y
+ 	select SERIAL_CORE_CONSOLE
++	default y
+ 
+ config SERIAL_SH_SCI_EARLYCON
+ 	bool "Support for early console on SuperH SCI(F)"
+-- 
+2.19.0
+
diff --git a/patches/0575-tty-serial-sh-sci-Hide-earlycon-config-question.patch b/patches/0575-tty-serial-sh-sci-Hide-earlycon-config-question.patch
new file mode 100644
index 00000000000000..b2e515b6df890f
--- /dev/null
+++ b/patches/0575-tty-serial-sh-sci-Hide-earlycon-config-question.patch
@@ -0,0 +1,42 @@
+From 740e582fbd1208ee098aa315de5d7291a33bf135 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 14:12:00 +0100
+Subject: [PATCH 0575/1795] tty: serial: sh-sci: Hide earlycon config question
+
+Renesas H8/300 and ARM platforms use DT and support earlycon, so most
+users want earlycon support to be enabled.
+
+On SuperH platforms, earlycon is not yet supported.
+
+Hence follow the above rationale to configure the default, unless
+CONFIG_EXPERT is enabled.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 3a987e7354eae9c1a0a298bc523647aa421149e5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index 0c75562d620f..952a2c6a9da0 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -774,10 +774,11 @@ config SERIAL_SH_SCI_CONSOLE
+ 	default y
+ 
+ config SERIAL_SH_SCI_EARLYCON
+-	bool "Support for early console on SuperH SCI(F)"
++	bool "Support for early console on SuperH SCI(F)" if EXPERT
+ 	depends on SERIAL_SH_SCI=y
+ 	select SERIAL_CORE_CONSOLE
+ 	select SERIAL_EARLYCON
++	default ARCH_RENESAS || H8300
+ 
+ config SERIAL_SH_SCI_DMA
+ 	bool "DMA support"
+-- 
+2.19.0
+
diff --git a/patches/0576-tty-serial-sh-sci-Hide-DMA-config-question.patch b/patches/0576-tty-serial-sh-sci-Hide-DMA-config-question.patch
new file mode 100644
index 00000000000000..deaf726a529fdf
--- /dev/null
+++ b/patches/0576-tty-serial-sh-sci-Hide-DMA-config-question.patch
@@ -0,0 +1,43 @@
+From c1de089e8370890dd3ba6eb5acbbc19884d4169b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 14:12:01 +0100
+Subject: [PATCH 0576/1795] tty: serial: sh-sci: Hide DMA config question
+
+On most Renesas ARM platforms, the SCIF serial ports can be used with
+DMA, so most users will want DMA support to be enabled.
+
+On SuperH platforms, SCI(F) serial ports cannot be used with DMA yet
+(see also commit 219fb0c1436e4893 ("serial: sh-sci: Remove the platform
+data dma slave rx/tx channel IDs")), so users will want it disabled to
+reduce kernel size.
+
+Hence follow the above rationale to configure the default, unless
+CONFIG_EXPERT is enabled.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit be7e251d20e6c800b3b9ee79d1da6059438c34f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index 952a2c6a9da0..4e6dfb0a762b 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -781,8 +781,9 @@ config SERIAL_SH_SCI_EARLYCON
+ 	default ARCH_RENESAS || H8300
+ 
+ config SERIAL_SH_SCI_DMA
+-	bool "DMA support"
++	bool "DMA support" if EXPERT
+ 	depends on SERIAL_SH_SCI && DMA_ENGINE
++	default ARCH_RENESAS
+ 
+ config SERIAL_PNX8XXX
+ 	bool "Enable PNX8XXX SoCs' UART Support"
+-- 
+2.19.0
+
diff --git a/patches/0577-tty-serial-sh-sci-Add-default-for-number-of-ports-fo.patch b/patches/0577-tty-serial-sh-sci-Add-default-for-number-of-ports-fo.patch
new file mode 100644
index 00000000000000..051dddbff39be2
--- /dev/null
+++ b/patches/0577-tty-serial-sh-sci-Add-default-for-number-of-ports-fo.patch
@@ -0,0 +1,43 @@
+From 90d7ac9741fc59aab6fa1b1d5e2dc163f288247c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 18 Dec 2017 09:50:57 +0100
+Subject: [PATCH 0577/1795] tty: serial: sh-sci: Add default for number of
+ ports for compile-testing
+
+When compile-testing an allmodconfig kernel for a platform without
+sh-sci serial ports, the SERIAL_SH_SCI_NR_UARTS symbol of type "int"
+doesn't get assigned a numerical default value, but an empty string,
+leading to a build failure:
+
+   .config:3814:warning: symbol value '' invalid for SERIAL_SH_SCI_NR_UARTS
+   ...
+   make[3]: *** [silentoldconfig] Error 1
+
+Fix this by explicitly providing a default value of 2, like before.
+
+Reported-by: kbuild test robot <fengguang.wu@intel.com>
+Fixes: f6731485a51978ca ("tty: serial: sh-sci: Hide number of ports config question")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 19ac50f655373c45f3cb548f510510282186a3dd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index 4e6dfb0a762b..3682fd3e960c 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -766,6 +766,7 @@ config SERIAL_SH_SCI_NR_UARTS
+ 	default "3" if H8300
+ 	default "10" if SUPERH
+ 	default "18" if ARCH_RENESAS
++	default "2"
+ 
+ config SERIAL_SH_SCI_CONSOLE
+ 	bool "Support for console on SuperH SCI(F)" if EXPERT
+-- 
+2.19.0
+
diff --git a/patches/0578-ARM-shmobile-Document-Renesas-M3-W-based-Salvator-XS.patch b/patches/0578-ARM-shmobile-Document-Renesas-M3-W-based-Salvator-XS.patch
new file mode 100644
index 00000000000000..0a80d45aa043da
--- /dev/null
+++ b/patches/0578-ARM-shmobile-Document-Renesas-M3-W-based-Salvator-XS.patch
@@ -0,0 +1,39 @@
+From 6ad0535cd94f8e506af144c9442de4c42f61d88e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 18:29:57 +0100
+Subject: [PATCH 0578/1795] ARM: shmobile: Document Renesas M3-W-based
+ Salvator-XS board DT bindings
+
+The Renesas Salvator-XS (Salvator-X 2nd version) development board can
+be equipped with either an R-Car H3 ES2.0 or M3-W ES1.x SiP, which are
+pin-compatible.
+
+Document board part number and compatible values for the version with
+R-Car M3-W.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0021ca8ef7cad34a8077073ec3aaf638117681f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 020d758fc0c5..062520a0e74c 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -104,6 +104,8 @@ Boards:
+     compatible = "renesas,salvator-x", "renesas,r8a7796"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+     compatible = "renesas,salvator-xs", "renesas,r8a7795"
++  - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
++    compatible = "renesas,salvator-xs", "renesas,r8a7796"
+   - SILK (RTP0RC7794LCB00011S)
+     compatible = "renesas,silk", "renesas,r8a7794"
+   - SK-RZG1E (YR8A77450S000BE)
+-- 
+2.19.0
+
diff --git a/patches/0579-arm64-dts-renesas-salvator-set-driver-type-for-eMMC.patch b/patches/0579-arm64-dts-renesas-salvator-set-driver-type-for-eMMC.patch
new file mode 100644
index 00000000000000..307b02d4451330
--- /dev/null
+++ b/patches/0579-arm64-dts-renesas-salvator-set-driver-type-for-eMMC.patch
@@ -0,0 +1,33 @@
+From 6de188e038072da6fb96799b8da360d9b9b9c250 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sun, 15 Oct 2017 14:46:15 +0200
+Subject: [PATCH 0579/1795] arm64: dts: renesas: salvator: set driver type for
+ eMMC
+
+These boards are known to have eMMC issues with the default driver type.
+Specify a working one.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d3decc2c34c8e69828918e69a63b35e927af709c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 8a2bcc73d5f0..41942184b372 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -602,6 +602,7 @@
+ 	bus-width = <8>;
+ 	mmc-hs200-1_8v;
+ 	non-removable;
++	fixed-emmc-driver-type = <1>;
+ 	status = "okay";
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0580-arm64-dts-renesas-r8a7795-Use-R-Car-SDHI-Gen3-fallba.patch b/patches/0580-arm64-dts-renesas-r8a7795-Use-R-Car-SDHI-Gen3-fallba.patch
new file mode 100644
index 00000000000000..310ad668bc1f2e
--- /dev/null
+++ b/patches/0580-arm64-dts-renesas-r8a7795-Use-R-Car-SDHI-Gen3-fallba.patch
@@ -0,0 +1,67 @@
+From 48a2e65d84118e9900ba36d5dce3f2a8492af84c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:49 +0200
+Subject: [PATCH 0580/1795] arm64: dts: renesas: r8a7795: Use R-Car SDHI Gen3
+ fallback compat string
+
+Use newly added R-Car SDHI Gen3 fallback compat string
+in the DT of the r8a7795 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e4428a726d57fb6068346a736c79953657bc8da6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 15ef292a8d9f..42c51f2ec30b 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1539,7 +1539,8 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7795";
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee100000 0 0x2000>;
+ 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 314>;
+@@ -1550,7 +1551,8 @@
+ 		};
+ 
+ 		sdhi1: sd@ee120000 {
+-			compatible = "renesas,sdhi-r8a7795";
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee120000 0 0x2000>;
+ 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 313>;
+@@ -1561,7 +1563,8 @@
+ 		};
+ 
+ 		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7795";
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee140000 0 0x2000>;
+ 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 312>;
+@@ -1572,7 +1575,8 @@
+ 		};
+ 
+ 		sdhi3: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7795";
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee160000 0 0x2000>;
+ 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0581-arm64-dts-renesas-r8a7796-Use-R-Car-SDHI-Gen3-fallba.patch b/patches/0581-arm64-dts-renesas-r8a7796-Use-R-Car-SDHI-Gen3-fallba.patch
new file mode 100644
index 00000000000000..1d3e9ca3eaa60a
--- /dev/null
+++ b/patches/0581-arm64-dts-renesas-r8a7796-Use-R-Car-SDHI-Gen3-fallba.patch
@@ -0,0 +1,67 @@
+From 75644720c003983e03c4253359051fbcb798c5de Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:50 +0200
+Subject: [PATCH 0581/1795] arm64: dts: renesas: r8a7796: Use R-Car SDHI Gen3
+ fallback compat string
+
+Use newly added R-Car SDHI Gen3 fallback compat string
+in the DT of the r8a7796 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e871efc9a4f48c9b52d0a2980bf0cac9ecfd310c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index f2b2e40c655e..8c94a313d9e1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1380,7 +1380,8 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7796";
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee100000 0 0x2000>;
+ 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 314>;
+@@ -1391,7 +1392,8 @@
+ 		};
+ 
+ 		sdhi1: sd@ee120000 {
+-			compatible = "renesas,sdhi-r8a7796";
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee120000 0 0x2000>;
+ 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 313>;
+@@ -1402,7 +1404,8 @@
+ 		};
+ 
+ 		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7796";
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee140000 0 0x2000>;
+ 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 312>;
+@@ -1413,7 +1416,8 @@
+ 		};
+ 
+ 		sdhi3: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7796";
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee160000 0 0x2000>;
+ 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0582-arm64-dts-renesas-r8a77970-Add-RWDT-node.patch b/patches/0582-arm64-dts-renesas-r8a77970-Add-RWDT-node.patch
new file mode 100644
index 00000000000000..a4f8dcfa50a5c7
--- /dev/null
+++ b/patches/0582-arm64-dts-renesas-r8a77970-Add-RWDT-node.patch
@@ -0,0 +1,41 @@
+From 3b0e97c70cd518b1669b9967e5f75fdbc7a832cd Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 16:56:27 +0100
+Subject: [PATCH 0582/1795] arm64: dts: renesas: r8a77970: Add RWDT node
+
+Add a device node for the Watchdog Timer (WDT) controller on the
+Renesas R-Car V3M (r8a77970) SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 206d082e55850797b7152a7c56ccc5c4a41b72ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 97e6981938e7..75d09f1724f0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -103,6 +103,16 @@
+ 						  IRQ_TYPE_LEVEL_LOW)>;
+ 		};
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a77970-wdt",
++				     "renesas,rcar-gen3-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a77970-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/0583-arm64-dts-renesas-eagle-Move-avb-node-to-preserve-so.patch b/patches/0583-arm64-dts-renesas-eagle-Move-avb-node-to-preserve-so.patch
new file mode 100644
index 00000000000000..eebadd8ee47d33
--- /dev/null
+++ b/patches/0583-arm64-dts-renesas-eagle-Move-avb-node-to-preserve-so.patch
@@ -0,0 +1,55 @@
+From 2c8c57bea5994b648303700b393b0dd4c2677a2e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 16:56:28 +0100
+Subject: [PATCH 0583/1795] arm64: dts: renesas: eagle: Move avb node to
+ preserve sort order
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d0ff035f89f18424fd7665b9a29c547adafdea38)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 22 +++++++++----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index a711e77cc6a5..9e37f6e7b265 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -33,6 +33,17 @@
+ 	};
+ };
+ 
++&avb {
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+@@ -44,14 +55,3 @@
+ &scif0 {
+ 	status = "okay";
+ };
+-
+-&avb {
+-	renesas,no-ether-link;
+-	phy-handle = <&phy0>;
+-	status = "okay";
+-
+-	phy0: ethernet-phy@0 {
+-		rxc-skew-ps = <1500>;
+-		reg = <0>;
+-	};
+-};
+-- 
+2.19.0
+
diff --git a/patches/0584-arm64-dts-renesas-eagle-Enable-watchdog-timer.patch b/patches/0584-arm64-dts-renesas-eagle-Enable-watchdog-timer.patch
new file mode 100644
index 00000000000000..3864f3e355a269
--- /dev/null
+++ b/patches/0584-arm64-dts-renesas-eagle-Enable-watchdog-timer.patch
@@ -0,0 +1,36 @@
+From 0f42ba5d24d587ad7ea4cf5394e3b3ca7ec36d61 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 16:56:29 +0100
+Subject: [PATCH 0584/1795] arm64: dts: renesas: eagle: Enable watchdog timer
+
+Enable the Watchdog Timer (WDT) controller on the Renesas Eagle
+board equipped with an R-Car V3M (r8a77970) SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fd363f54979df670ad8ea844c1b69b021ba1039d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index 9e37f6e7b265..8fe5c193e049 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -52,6 +52,11 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &scif0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0585-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch b/patches/0585-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
new file mode 100644
index 00000000000000..c7d1daa08bc081
--- /dev/null
+++ b/patches/0585-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
@@ -0,0 +1,101 @@
+From 50376b4e1333d292c9e1a55e6721a6712657e957 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 30 Oct 2017 18:29:59 +0100
+Subject: [PATCH 0585/1795] arm64: dts: renesas: Add support for Salvator-XS
+ with R-Car M3-W
+
+Add initial support for the Renesas Salvator-XS (Salvator-X 2nd version)
+development board equipped with an R-Car M3-W SiP.
+
+Based on work for the Salvator-X and -XS boards with M3-W resp. H3 SiPs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 79eba26e170dbb9dc381e5d842da06394ad17c59)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../boot/dts/renesas/r8a7796-salvator-xs.dts  | 58 +++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index ebb836b2d9e9..f58e4f180ed0 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
++dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+new file mode 100644
+index 000000000000..2c37055efa94
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+@@ -0,0 +1,58 @@
++/*
++ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W
++ *
++ * Copyright (C) 2015-2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a7796.dtsi"
++#include "salvator-xs.dtsi"
++
++/ {
++	model = "Renesas Salvator-X 2nd version board based on r8a7796";
++	compatible = "renesas,salvator-xs", "renesas,r8a7796";
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x78000000>;
++	};
++
++	memory@600000000 {
++		device_type = "memory";
++		reg = <0x6 0x00000000 0x0 0x80000000>;
++	};
++};
++
++&du {
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 727>,
++		 <&versaclock6 1>,
++		 <&x21_clk>,
++		 <&versaclock6 2>;
++	clock-names = "du.0", "du.1", "du.2", "lvds.0",
++		      "dclkin.0", "dclkin.1", "dclkin.2";
++};
++
++&hdmi0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			reg = <1>;
++			rcar_dw_hdmi0_out: endpoint {
++				remote-endpoint = <&hdmi0_con>;
++			};
++		};
++	};
++};
++
++&hdmi0_con {
++	remote-endpoint = <&rcar_dw_hdmi0_out>;
++};
+-- 
+2.19.0
+
diff --git a/patches/0586-arm64-dts-renesas-r8a7796-Add-IPMMU-device-nodes.patch b/patches/0586-arm64-dts-renesas-r8a7796-Add-IPMMU-device-nodes.patch
new file mode 100644
index 00000000000000..55ceca35d96f3d
--- /dev/null
+++ b/patches/0586-arm64-dts-renesas-r8a7796-Add-IPMMU-device-nodes.patch
@@ -0,0 +1,132 @@
+From 90c83fead059fb8a5599f0004b12c1e1e072e7c6 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:26:06 +0100
+Subject: [PATCH 0586/1795] arm64: dts: renesas: r8a7796: Add IPMMU device
+ nodes
+
+Add r8a7796 IPMMU nodes and keep all disabled by default.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 389baa409617cda237ae8ae6dd4e897a2d072710)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 100 +++++++++++++++++++++++
+ 1 file changed, 100 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 8c94a313d9e1..9e7604108215 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -357,6 +357,106 @@
+ 					     <&a53_3>;
+ 		};
+ 
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 8>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 5>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv1: mmu@fd950000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfd950000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A7796_PD_A3IR>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7796-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/0587-arm64-dts-renesas-r8a7796-Tie-SYS-DMAC-to-IPMMU-DS0-.patch b/patches/0587-arm64-dts-renesas-r8a7796-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
new file mode 100644
index 00000000000000..20ae8b685ef14d
--- /dev/null
+++ b/patches/0587-arm64-dts-renesas-r8a7796-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
@@ -0,0 +1,71 @@
+From cbf3e2763f9e7146fde6fcd52701777fcf47ba37 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:26:07 +0100
+Subject: [PATCH 0587/1795] arm64: dts: renesas: r8a7796: Tie SYS-DMAC to
+ IPMMU-DS0/1
+
+Hook up r8a7796 DMAC nodes to the IPMMUs. In particular SYS-DMAC0
+gets tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 24120522e6ebd3bcf61c84766943a42dec7fad32)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 9e7604108215..84f38056f8e6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1201,6 +1201,14 @@
+ 			resets = <&cpg 219>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
++			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
++			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
++			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
++			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
++			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
++			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
++			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+ 		};
+ 
+ 		dmac1: dma-controller@e7300000 {
+@@ -1235,6 +1243,14 @@
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
++			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
++			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
++			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
++			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
++			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
++			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
++			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+ 		};
+ 
+ 		dmac2: dma-controller@e7310000 {
+@@ -1269,6 +1285,14 @@
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
++			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
++			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
++			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
++			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
++			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
++			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
++			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ 		};
+ 
+ 		audma0: dma-controller@ec700000 {
+-- 
+2.19.0
+
diff --git a/patches/0588-arm64-dts-renesas-r8a7796-Tie-Audio-DMAC-to-IPMMU-MP.patch b/patches/0588-arm64-dts-renesas-r8a7796-Tie-Audio-DMAC-to-IPMMU-MP.patch
new file mode 100644
index 00000000000000..fd75bc1e10c30d
--- /dev/null
+++ b/patches/0588-arm64-dts-renesas-r8a7796-Tie-Audio-DMAC-to-IPMMU-MP.patch
@@ -0,0 +1,56 @@
+From a2c7f93f6bd118f570434eaa95b84165934052e9 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:08 +0100
+Subject: [PATCH 0588/1795] arm64: dts: renesas: r8a7796: Tie Audio-DMAC to
+ IPMMU-MP
+
+Hook up r8a7796 Audio-DMAC nodes to the IPMMU-MP.
+
+Based on work for the r8a7795 by Magnus Damm.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 13312527a220d077984cc1d20d1ec73db22a866a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 84f38056f8e6..fd875b5ea861 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1327,6 +1327,14 @@
+ 			resets = <&cpg 502>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
++			       <&ipmmu_mp 2>, <&ipmmu_mp 3>,
++			       <&ipmmu_mp 4>, <&ipmmu_mp 5>,
++			       <&ipmmu_mp 6>, <&ipmmu_mp 7>,
++			       <&ipmmu_mp 8>, <&ipmmu_mp 9>,
++			       <&ipmmu_mp 10>, <&ipmmu_mp 11>,
++			       <&ipmmu_mp 12>, <&ipmmu_mp 13>,
++			       <&ipmmu_mp 14>, <&ipmmu_mp 15>;
+ 		};
+ 
+ 		audma1: dma-controller@ec720000 {
+@@ -1361,6 +1369,14 @@
+ 			resets = <&cpg 501>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
++			       <&ipmmu_mp 18>, <&ipmmu_mp 19>,
++			       <&ipmmu_mp 20>, <&ipmmu_mp 21>,
++			       <&ipmmu_mp 22>, <&ipmmu_mp 23>,
++			       <&ipmmu_mp 24>, <&ipmmu_mp 25>,
++			       <&ipmmu_mp 26>, <&ipmmu_mp 27>,
++			       <&ipmmu_mp 28>, <&ipmmu_mp 29>,
++			       <&ipmmu_mp 30>, <&ipmmu_mp 31>;
+ 		};
+ 
+ 		usb_dmac0: dma-controller@e65a0000 {
+-- 
+2.19.0
+
diff --git a/patches/0589-arm64-dts-renesas-r8a7796-Point-FDP1-via-FCPF-to-IPM.patch b/patches/0589-arm64-dts-renesas-r8a7796-Point-FDP1-via-FCPF-to-IPM.patch
new file mode 100644
index 00000000000000..6edc4cefac2656
--- /dev/null
+++ b/patches/0589-arm64-dts-renesas-r8a7796-Point-FDP1-via-FCPF-to-IPM.patch
@@ -0,0 +1,50 @@
+From 3f53841fbe466fefbbff9d06a5bd269e8cb970f7 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:09 +0100
+Subject: [PATCH 0589/1795] arm64: dts: renesas: r8a7796: Point FDP1 via FCPF
+ to IPMMU-VI0
+
+Hook up the FCPF devices to allow use of FDP1 with IPMMU-VI0.
+
+Based on work by Magnus Damm for the r8a7795.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 69490bc9665d08b8ba221542b368c662a550a7a4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index fd875b5ea861..859dde64311e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1903,6 +1903,7 @@
+ 			clocks = <&cpg CPG_MOD 603>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
+ 		};
+ 
+ 		vspd1: vsp@fea28000 {
+@@ -1922,6 +1923,7 @@
+ 			clocks = <&cpg CPG_MOD 602>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			resets = <&cpg 602>;
++			iommus = <&ipmmu_vi0 9>;
+ 		};
+ 
+ 		vspd2: vsp@fea30000 {
+@@ -1941,6 +1943,7 @@
+ 			clocks = <&cpg CPG_MOD 601>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			resets = <&cpg 601>;
++			iommus = <&ipmmu_vi0 10>;
+ 		};
+ 
+ 		hdmi0: hdmi@fead0000 {
+-- 
+2.19.0
+
diff --git a/patches/0590-arm64-dts-renesas-r8a7796-Point-VSPI-via-FCPVI-to-IP.patch b/patches/0590-arm64-dts-renesas-r8a7796-Point-VSPI-via-FCPVI-to-IP.patch
new file mode 100644
index 00000000000000..0b78a33d9126ff
--- /dev/null
+++ b/patches/0590-arm64-dts-renesas-r8a7796-Point-VSPI-via-FCPVI-to-IP.patch
@@ -0,0 +1,34 @@
+From d41a338ffc39371c5c9330322bef00a54ef49d50 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:10 +0100
+Subject: [PATCH 0590/1795] arm64: dts: renesas: r8a7796: Point VSPI via FCPVI
+ to IPMMU-VC0
+
+Hook up the FCPVI devices to allow use of VSPI with IPMMU-VC0.
+
+Based on work for the r8a7795 by Magnus Damm.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit cef942d0bd89dc42145f6e55eaad5e710a0c83f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 859dde64311e..3b7a727b94be 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1884,6 +1884,7 @@
+ 			clocks = <&cpg CPG_MOD 611>;
+ 			power-domains = <&sysc R8A7796_PD_A3VC>;
+ 			resets = <&cpg 611>;
++			iommus = <&ipmmu_vc0 19>;
+ 		};
+ 
+ 		vspd0: vsp@fea20000 {
+-- 
+2.19.0
+
diff --git a/patches/0591-arm64-dts-renesas-r8a7796-Connect-Ethernet-AVB-to-IP.patch b/patches/0591-arm64-dts-renesas-r8a7796-Connect-Ethernet-AVB-to-IP.patch
new file mode 100644
index 00000000000000..07d9511b8b7c5b
--- /dev/null
+++ b/patches/0591-arm64-dts-renesas-r8a7796-Connect-Ethernet-AVB-to-IP.patch
@@ -0,0 +1,34 @@
+From 1b3bde628406efafe7904a38f6b311448b177a87 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:11 +0100
+Subject: [PATCH 0591/1795] arm64: dts: renesas: r8a7796: Connect Ethernet-AVB
+ to IPMMU-DS0
+
+Add IPMMU-DS0 to the Ethernet-AVB device node.
+
+Based on work by Magnus Damm for the r8a7795.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 03f70d172611b1eb7edf4f690186ec226df86a46)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 3b7a727b94be..7e5fef780786 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -917,6 +917,7 @@
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii-txid";
++			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/0592-arm64-dts-renesas-r8a7796-Enable-IPMMU-DS0-DS1-MP-VI.patch b/patches/0592-arm64-dts-renesas-r8a7796-Enable-IPMMU-DS0-DS1-MP-VI.patch
new file mode 100644
index 00000000000000..2fe9b57f8664ed
--- /dev/null
+++ b/patches/0592-arm64-dts-renesas-r8a7796-Enable-IPMMU-DS0-DS1-MP-VI.patch
@@ -0,0 +1,74 @@
+From 5d25a9b08a561c9a4701cab466c9db1e2498c184 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:26:12 +0100
+Subject: [PATCH 0592/1795] arm64: dts: renesas: r8a7796: Enable IPMMU-DS0,
+ DS1, MP, VI0, VC0 and MM
+
+Enable the r8a7795 device nodes for IPMMU-DS0, IPMMU-DS1, IPMMU-MP,
+IPMMU-VI0, IPMMU-VC0 and the shared IPMMU-MM device.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 88d1eb0c99cc1c055b3a65fe1afafe36478abb57)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 7e5fef780786..cc0cca7c0494 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -363,7 +363,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 9>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc0: mmu@fe6b0000 {
+@@ -381,7 +380,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 5>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv1: mmu@fd950000 {
+@@ -426,7 +424,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 4>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ds0: mmu@e6740000 {
+@@ -435,7 +432,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ds1: mmu@e7740000 {
+@@ -444,7 +440,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -454,7 +449,6 @@
+ 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		cpg: clock-controller@e6150000 {
+-- 
+2.19.0
+
diff --git a/patches/0593-arm64-dts-renesas-ulcb-kf-enable-USB2-PHY-of-channel.patch b/patches/0593-arm64-dts-renesas-ulcb-kf-enable-USB2-PHY-of-channel.patch
new file mode 100644
index 00000000000000..9980e014a7e840
--- /dev/null
+++ b/patches/0593-arm64-dts-renesas-ulcb-kf-enable-USB2-PHY-of-channel.patch
@@ -0,0 +1,79 @@
+From fca5b5e5eb84eff54803caf31fa1d174243d7373 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Wed, 8 Nov 2017 15:21:38 +0300
+Subject: [PATCH 0593/1795] arm64: dts: renesas: ulcb-kf: enable USB2 PHY of
+ channel 0
+
+This supports USB2 PHY channel #0 on ULCB Kingfisher board
+
+The dedicated USB0_PWEN pin is used to control CN13 VBUS source from U43
+power supply.
+MAX3355 can also provide VBUS, hence it should be disabled via OTG_OFFVBUSn
+node coming from gpio expander TCA9539.
+Set MAX3355 enabled using OTG_EXTLPn node to be able to read OTG ID of
+CN13.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 80785024767c03ff28861db0faf274fffb8d713a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 26 ++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 657ad1041965..48a2e8f48e3f 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -67,6 +67,20 @@
+ 			output-high;
+ 			line-name = "HUB rst";
+ 		};
++
++		otg_offvbusn {
++			gpio-hog;
++			gpios = <8 GPIO_ACTIVE_HIGH>;
++			output-low;
++			line-name = "OTG OFFVBUSn";
++		};
++
++		otg_extlpn {
++			gpio-hog;
++			gpios = <9 GPIO_ACTIVE_HIGH>;
++			output-high;
++			line-name = "OTG EXTLPn";
++		};
+ 	};
+ 
+ 	gpio_exp_75: gpio@75 {
+@@ -154,6 +168,11 @@
+ 		groups = "scif1_data_b", "scif1_ctrl";
+ 		function = "scif1";
+ 	};
++
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
+ };
+ 
+ &scif1 {
+@@ -164,6 +183,13 @@
+ 	status = "okay";
+ };
+ 
++&usb2_phy0 {
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &xhci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0594-arm64-dts-renesas-ulcb-kf-add-dr_mode-property-for-U.patch b/patches/0594-arm64-dts-renesas-ulcb-kf-add-dr_mode-property-for-U.patch
new file mode 100644
index 00000000000000..8554245fa0f873
--- /dev/null
+++ b/patches/0594-arm64-dts-renesas-ulcb-kf-add-dr_mode-property-for-U.patch
@@ -0,0 +1,51 @@
+From 77acc47eaee85a58e4a2b4093f646c61115c5ad8 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Wed, 8 Nov 2017 16:09:00 +0300
+Subject: [PATCH 0594/1795] arm64: dts: renesas: ulcb-kf: add dr_mode property
+ for USB2.0 channel 0
+
+ULCB-KF has a USB2.0 dual-role channel (CN13).
+This adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB)
+as "otg".
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 499468cf063923dbcbab92c4916b6183348c551f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+index 48a2e8f48e3f..a4e715cbde87 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+@@ -29,6 +29,7 @@
+ };
+ 
+ &ehci0 {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+@@ -41,6 +42,7 @@
+ };
+ 
+ &hsusb {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+@@ -133,6 +135,7 @@
+ };
+ 
+ &ohci0 {
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0595-arm64-dts-renesas-r8a77995-add-SYS-DMAC-nodes.patch b/patches/0595-arm64-dts-renesas-r8a77995-add-SYS-DMAC-nodes.patch
new file mode 100644
index 00000000000000..6af559ae64ea7b
--- /dev/null
+++ b/patches/0595-arm64-dts-renesas-r8a77995-add-SYS-DMAC-nodes.patch
@@ -0,0 +1,104 @@
+From 40ba9927d66d9cd64096df7d83ea335e4469c455 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 15 Nov 2017 16:25:08 +0100
+Subject: [PATCH 0595/1795] arm64: dts: renesas: r8a77995: add SYS-DMAC nodes
+
+Differs from other Gen3 SoCs in that each controller only supports eight
+channels.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 942164ca49897397a9f21048d83517ea8af6d044)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 72 +++++++++++++++++++++++
+ 1 file changed, 72 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 788e3afae6e3..04a392a9d9de 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -155,6 +155,78 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a77995",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x10000>;
++			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++		};
++
++		dmac1: dma-controller@e7300000 {
++			compatible = "renesas,dmac-r8a77995",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++		};
++
++		dmac2: dma-controller@e7310000 {
++			compatible = "renesas,dmac-r8a77995",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 217>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 217>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a77995",
+ 				     "renesas,rcar-gen3-gpio",
+-- 
+2.19.0
+
diff --git a/patches/0596-arm64-dts-renesas-r8a77995-Add-SDHI-MMC-support.patch b/patches/0596-arm64-dts-renesas-r8a77995-Add-SDHI-MMC-support.patch
new file mode 100644
index 00000000000000..9bcd18bdb6118c
--- /dev/null
+++ b/patches/0596-arm64-dts-renesas-r8a77995-Add-SDHI-MMC-support.patch
@@ -0,0 +1,44 @@
+From bb0da07e2ce66b3b9e4d24cb0781e9a6dfe6edef Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 15 Nov 2017 16:25:47 +0100
+Subject: [PATCH 0596/1795] arm64: dts: renesas: r8a77995: Add SDHI (MMC)
+ support
+
+R-Car D3 has only one SDHI controller.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 83f18749c2f65ae699d909f6f9a6242681344176)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 04a392a9d9de..98b70542b812 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -438,6 +438,18 @@
+ 			status = "disabled";
+ 		};
+ 
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a77995",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
+ 		ehci0: usb@ee080100 {
+ 			compatible = "generic-ehci";
+ 			reg = <0 0xee080100 0 0x100>;
+-- 
+2.19.0
+
diff --git a/patches/0597-arm64-dts-renesas-r8a7795-Add-IPMMU-device-nodes.patch b/patches/0597-arm64-dts-renesas-r8a7795-Add-IPMMU-device-nodes.patch
new file mode 100644
index 00000000000000..fcb7f30d464c02
--- /dev/null
+++ b/patches/0597-arm64-dts-renesas-r8a7795-Add-IPMMU-device-nodes.patch
@@ -0,0 +1,227 @@
+From cbc98efc01b527c6760d0bbfe768cbd7141353de Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:18 +0100
+Subject: [PATCH 0597/1795] arm64: dts: renesas: r8a7795: Add IPMMU device
+ nodes
+
+Add r8a7795 IPMMU nodes and keep all disabled by default.
+
+This includes all IPMMU devices for r8a7795 ES2.0. Those
+not present in r8a7795 ES1.x are removed from the DT for those
+SoCs using delete-node. A follow-up patch will add IPMMU devices
+to ES1.x which are not also present in ES2.0.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3b7e7848f0e88b369519e8f479cdabf6eb998af5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi |  25 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 145 +++++++++++++++++++
+ 2 files changed, 170 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 655dd30639c5..246323eacb56 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -21,6 +21,11 @@
+ 		status = "disabled";
+ 	};
+ 
++	/delete-node/ mmu@febe0000;
++	/delete-node/ mmu@fe980000;
++	/delete-node/ mmu@fd960000;
++	/delete-node/ mmu@fd970000;
++
+ 	/delete-node/ usb-phy@ee0e0200;
+ 	/delete-node/ usb@ee0e0100;
+ 	/delete-node/ usb@ee0e0000;
+@@ -86,6 +91,26 @@
+ 	};
+ };
+ 
++&ipmmu_vi0 {
++	renesas,ipmmu-main = <&ipmmu_mm 11>;
++};
++
++&ipmmu_vp0 {
++	renesas,ipmmu-main = <&ipmmu_mm 12>;
++};
++
++&ipmmu_vc0 {
++	renesas,ipmmu-main = <&ipmmu_mm 9>;
++};
++
++&ipmmu_vc1 {
++	renesas,ipmmu-main = <&ipmmu_mm 10>;
++};
++
++&ipmmu_rt {
++	renesas,ipmmu-main = <&ipmmu_mm 7>;
++};
++
+ &du {
+ 	vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 42c51f2ec30b..1a091bb41b7f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -421,6 +421,151 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 14>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vi1: mmu@febe0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfebe0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 15>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vp0: mmu@fe990000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe990000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 16>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vp1: mmu@fe980000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe980000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 17>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 12>;
++			power-domains = <&sysc R8A7795_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc1: mmu@fe6f0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe6f0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 13>;
++			power-domains = <&sysc R8A7795_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv2: mmu@fd960000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd960000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 8>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv3: mmu@fd970000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd970000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A7795_PD_A3IR>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 10>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp0: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		dmac0: dma-controller@e6700000 {
+ 			compatible = "renesas,dmac-r8a7795",
+ 				     "renesas,rcar-dmac";
+-- 
+2.19.0
+
diff --git a/patches/0598-arm64-dts-renesas-r8a7795-es1-Add-IPMMU-device-nodes.patch b/patches/0598-arm64-dts-renesas-r8a7795-es1-Add-IPMMU-device-nodes.patch
new file mode 100644
index 00000000000000..6d4d90d31ab5f5
--- /dev/null
+++ b/patches/0598-arm64-dts-renesas-r8a7795-es1-Add-IPMMU-device-nodes.patch
@@ -0,0 +1,54 @@
+From 9c66ba7d0c171268ed86843e73900559012ad62a Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:19 +0100
+Subject: [PATCH 0598/1795] arm64: dts: renesas: r8a7795-es1: Add IPMMU device
+ nodes
+
+Add r8a7795 ES1.x IPMMU nodes and keep all disabled by default.
+
+This is a follow-up to a patch that adds IPMMU device nodes that
+are common to r8a7795 ES1.x and ES2.0
+
+Power domains are omitted as they appear to be undocumented.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit e4b9a493df45075bf3ae2d41fdc1a29e57fe024b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 246323eacb56..38b7cfb3b428 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -26,6 +26,22 @@
+ 	/delete-node/ mmu@fd960000;
+ 	/delete-node/ mmu@fd970000;
+ 
++	ipmmu_mp1: mmu@ec680000 {
++		compatible = "renesas,ipmmu-r8a7795";
++		reg = <0 0xec680000 0 0x1000>;
++		renesas,ipmmu-main = <&ipmmu_mm 5>;
++		#iommu-cells = <1>;
++		status = "disabled";
++	};
++
++	ipmmu_sy: mmu@e7730000 {
++		compatible = "renesas,ipmmu-r8a7795";
++		reg = <0 0xe7730000 0 0x1000>;
++		renesas,ipmmu-main = <&ipmmu_mm 8>;
++		#iommu-cells = <1>;
++		status = "disabled";
++	};
++
+ 	/delete-node/ usb-phy@ee0e0200;
+ 	/delete-node/ usb@ee0e0100;
+ 	/delete-node/ usb@ee0e0000;
+-- 
+2.19.0
+
diff --git a/patches/0599-arm64-dts-renesas-r8a7795-Tie-SYS-DMAC-to-IPMMU-DS0-.patch b/patches/0599-arm64-dts-renesas-r8a7795-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
new file mode 100644
index 00000000000000..326158a657abd3
--- /dev/null
+++ b/patches/0599-arm64-dts-renesas-r8a7795-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
@@ -0,0 +1,72 @@
+From 028ece6320db18f39289eee6d65f3fb9bda6e2e2 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:20 +0100
+Subject: [PATCH 0599/1795] arm64: dts: renesas: r8a7795: Tie SYS-DMAC to
+ IPMMU-DS0/1
+
+Hook up r8a7795 SYS-DMAC nodes to the IPMMUs. In particular SYS-DMAC0 gets
+tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit bf2ca657f1fc280531eb62d56467c259125d26ff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 1a091bb41b7f..af200aa55fce 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -598,6 +598,14 @@
+ 			resets = <&cpg 219>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
++			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
++			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
++			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
++			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
++			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
++			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
++			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+ 		};
+ 
+ 		dmac1: dma-controller@e7300000 {
+@@ -632,6 +640,14 @@
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
++			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
++			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
++			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
++			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
++			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
++			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
++			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+ 		};
+ 
+ 		dmac2: dma-controller@e7310000 {
+@@ -666,6 +682,14 @@
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
++			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
++			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
++			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
++			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
++			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
++			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
++			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ 		};
+ 
+ 		audma0: dma-controller@ec700000 {
+-- 
+2.19.0
+
diff --git a/patches/0600-arm64-dts-renesas-r8a7795-Tie-Audio-DMAC-to-IPMMU-MP.patch b/patches/0600-arm64-dts-renesas-r8a7795-Tie-Audio-DMAC-to-IPMMU-MP.patch
new file mode 100644
index 00000000000000..7df8bd8809d193
--- /dev/null
+++ b/patches/0600-arm64-dts-renesas-r8a7795-Tie-Audio-DMAC-to-IPMMU-MP.patch
@@ -0,0 +1,91 @@
+From 1ebd1d9dc1fb2460153474c8ce99e255108f116b Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:21 +0100
+Subject: [PATCH 0600/1795] arm64: dts: renesas: r8a7795: Tie Audio-DMAC to
+ IPMMU-MP0/1
+
+Hook up r8a7795 ES2.0 Audio-DMAC nodes to the IPMMU-MP0.
+Hook up r8a7795 ES1.x Audio-DMAC nodes to the IPMMU-MP1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c2b57f76a725b65a24bae0fd1486b58addb7d75f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 22 ++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 16 ++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 38b7cfb3b428..2dfe8108072c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -127,6 +127,28 @@
+ 	renesas,ipmmu-main = <&ipmmu_mm 7>;
+ };
+ 
++&audma0 {
++	iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
++	       <&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
++	       <&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
++	       <&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
++	       <&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
++	       <&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
++	       <&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
++	       <&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
++};
++
++&audma1 {
++	iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
++	       <&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
++	       <&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
++	       <&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
++	       <&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
++	       <&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
++	       <&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
++	       <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
++};
++
+ &du {
+ 	vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index af200aa55fce..2ca746c304d5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -724,6 +724,14 @@
+ 			resets = <&cpg 502>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
++			       <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
++			       <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
++			       <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
++			       <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
++			       <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
++			       <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
++			       <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
+ 		};
+ 
+ 		audma1: dma-controller@ec720000 {
+@@ -758,6 +766,14 @@
+ 			resets = <&cpg 501>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
++			iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
++			       <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
++			       <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
++			       <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
++			       <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
++			       <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
++			       <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
++			       <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+-- 
+2.19.0
+
diff --git a/patches/0601-arm64-dts-renesas-r8a7795-Point-DU-VSPD-via-FCPVD-to.patch b/patches/0601-arm64-dts-renesas-r8a7795-Point-DU-VSPD-via-FCPVD-to.patch
new file mode 100644
index 00000000000000..32a8f932f81b94
--- /dev/null
+++ b/patches/0601-arm64-dts-renesas-r8a7795-Point-DU-VSPD-via-FCPVD-to.patch
@@ -0,0 +1,66 @@
+From 76b5e2a98a5f5ab89930266b4c176769c9ee3057 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:22 +0100
+Subject: [PATCH 0601/1795] arm64: dts: renesas: r8a7795: Point DU/VSPD via
+ FCPVD to IPMMU-VI0/1
+
+Hook up the FCPVD devices to allow use of the VSP and DU
+together with IPMMU-VI1 and IPMMU-VI1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 45b894a9fc324291adabaeadb5e9e0d28192860d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 4 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 3 +++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 2dfe8108072c..71499d193ddb 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -149,6 +149,10 @@
+ 	       <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
+ };
+ 
++&fcpvd2 {
++	iommus = <&ipmmu_vi0 10>;
++};
++
+ &du {
+ 	vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 2ca746c304d5..6187e9c33e88 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2154,6 +2154,7 @@
+ 			clocks = <&cpg CPG_MOD 603>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
+ 		};
+ 
+ 		vspd1: vsp@fea28000 {
+@@ -2173,6 +2174,7 @@
+ 			clocks = <&cpg CPG_MOD 602>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 602>;
++			iommus = <&ipmmu_vi0 9>;
+ 		};
+ 
+ 		vspd2: vsp@fea30000 {
+@@ -2192,6 +2194,7 @@
+ 			clocks = <&cpg CPG_MOD 601>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 601>;
++			iommus = <&ipmmu_vi1 10>;
+ 		};
+ 
+ 		fdp1@fe940000 {
+-- 
+2.19.0
+
diff --git a/patches/0602-arm64-dts-renesas-r8a7795-es1-Point-DU-VSPD-via-FCPV.patch b/patches/0602-arm64-dts-renesas-r8a7795-es1-Point-DU-VSPD-via-FCPV.patch
new file mode 100644
index 00000000000000..fc01a535b8b90a
--- /dev/null
+++ b/patches/0602-arm64-dts-renesas-r8a7795-es1-Point-DU-VSPD-via-FCPV.patch
@@ -0,0 +1,34 @@
+From f261072aac3fa20de1d83ed9709506cd4c5ff4d8 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:23 +0100
+Subject: [PATCH 0602/1795] arm64: dts: renesas: r8a7795-es1: Point DU/VSPD via
+ FCPVD to IPMMU-VI0
+
+Hook up the FCPVD devices to allow use of the VSP and DU
+together with IPMMU-VI0.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f54de024ef009502a7a767b8263e93edb05a13bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 71499d193ddb..1eafa5382e86 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -94,6 +94,7 @@
+ 		clocks = <&cpg CPG_MOD 600>;
+ 		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 		resets = <&cpg 600>;
++		iommus = <&ipmmu_vi0 11>;
+ 	};
+ 
+ 	fdp1@fe948000 {
+-- 
+2.19.0
+
diff --git a/patches/0603-arm64-dts-renesas-r8a7795-Point-FDP1-via-FCPF-to-IPM.patch b/patches/0603-arm64-dts-renesas-r8a7795-Point-FDP1-via-FCPF-to-IPM.patch
new file mode 100644
index 00000000000000..06ef05142442f5
--- /dev/null
+++ b/patches/0603-arm64-dts-renesas-r8a7795-Point-FDP1-via-FCPF-to-IPM.patch
@@ -0,0 +1,57 @@
+From aff47526fd70c1a5240450a256da4509fb213963 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:24 +0100
+Subject: [PATCH 0603/1795] arm64: dts: renesas: r8a7795: Point FDP1 via FCPF
+ to IPMMU-VP0/1
+
+Hook up the FCPF devices to allow use of FDP1 with IPMMU-VP.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit afdeb149aaecdd7151f4e43f2531dee59e53ced0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 4 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 1eafa5382e86..6b4dfa42f5b2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -150,6 +150,10 @@
+ 	       <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
+ };
+ 
++&fcpf1 {
++	iommus = <&ipmmu_vp0 1>;
++};
++
+ &fcpvd2 {
+ 	iommus = <&ipmmu_vi0 10>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 6187e9c33e88..f7d7c98a7f73 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2070,6 +2070,7 @@
+ 			clocks = <&cpg CPG_MOD 615>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 615>;
++			iommus = <&ipmmu_vp0 0>;
+ 		};
+ 
+ 		fcpf1: fcp@fe951000 {
+@@ -2078,6 +2079,7 @@
+ 			clocks = <&cpg CPG_MOD 614>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 614>;
++			iommus = <&ipmmu_vp1 1>;
+ 		};
+ 
+ 		vspbd: vsp@fe960000 {
+-- 
+2.19.0
+
diff --git a/patches/0604-arm64-dts-renesas-r8a7795-es1-Point-FDP1-via-FCPF-to.patch b/patches/0604-arm64-dts-renesas-r8a7795-es1-Point-FDP1-via-FCPF-to.patch
new file mode 100644
index 00000000000000..21226371ef5742
--- /dev/null
+++ b/patches/0604-arm64-dts-renesas-r8a7795-es1-Point-FDP1-via-FCPF-to.patch
@@ -0,0 +1,33 @@
+From 431f834137aa9d63360497b6e7210c5436c2409a Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:25 +0100
+Subject: [PATCH 0604/1795] arm64: dts: renesas: r8a7795-es1: Point FDP1 via
+ FCPF to IPMMU-VP0
+
+Hook up the FCPF devices to allow use of FDP1 with IPMMU-VP0.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f54d63fe7ed6d37df15ec8903302dd05375168f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 6b4dfa42f5b2..736281335653 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -56,6 +56,7 @@
+ 		clocks = <&cpg CPG_MOD 613>;
+ 		power-domains = <&sysc R8A7795_PD_A3VP>;
+ 		resets = <&cpg 613>;
++		iommus = <&ipmmu_vp0 2>;
+ 	};
+ 
+ 	vspi2: vsp@fe9c0000 {
+-- 
+2.19.0
+
diff --git a/patches/0605-arm64-dts-renesas-r8a7795-Point-VSPBC-VSPBD-via-FCPV.patch b/patches/0605-arm64-dts-renesas-r8a7795-Point-VSPBC-VSPBD-via-FCPV.patch
new file mode 100644
index 00000000000000..055d93f7125547
--- /dev/null
+++ b/patches/0605-arm64-dts-renesas-r8a7795-Point-VSPBC-VSPBD-via-FCPV.patch
@@ -0,0 +1,58 @@
+From 1b918f7f3004e7ca30f7a33b62ff7ddcdc85d63f Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:26 +0100
+Subject: [PATCH 0605/1795] arm64: dts: renesas: r8a7795: Point VSPBC/VSPBD via
+ FCPVB to IPMMU-VP0/1
+
+Hook up the FCPVB devices to allow use of VSPBC/VSPBD with
+IPMMU-VP0 and IPMMU-VP1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit cdd919ba225433a334b2f2c2ef71c7e70f80173e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 4 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 736281335653..3d50627c0670 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -151,6 +151,10 @@
+ 	       <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
+ };
+ 
++&fcpvb1 {
++	iommus = <&ipmmu_vp0 7>;
++};
++
+ &fcpf1 {
+ 	iommus = <&ipmmu_vp0 1>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index f7d7c98a7f73..35efacd1ec21 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2062,6 +2062,7 @@
+ 			clocks = <&cpg CPG_MOD 606>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 606>;
++			iommus = <&ipmmu_vp1 7>;
+ 		};
+ 
+ 		fcpf0: fcp@fe950000 {
+@@ -2099,6 +2100,7 @@
+ 			clocks = <&cpg CPG_MOD 607>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 607>;
++			iommus = <&ipmmu_vp0 5>;
+ 		};
+ 
+ 		vspi0: vsp@fe9a0000 {
+-- 
+2.19.0
+
diff --git a/patches/0606-arm64-dts-renesas-r8a7795-Point-VSPI-via-FCPVI-to-IP.patch b/patches/0606-arm64-dts-renesas-r8a7795-Point-VSPI-via-FCPVI-to-IP.patch
new file mode 100644
index 00000000000000..a392bf3c6163b9
--- /dev/null
+++ b/patches/0606-arm64-dts-renesas-r8a7795-Point-VSPI-via-FCPVI-to-IP.patch
@@ -0,0 +1,58 @@
+From d9ad39ac96ee611ba280df32a9e265272c3a645c Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:27 +0100
+Subject: [PATCH 0606/1795] arm64: dts: renesas: r8a7795: Point VSPI via FCPVI
+ to IPMMU-VP0/1
+
+Hook up the FCPVI devices to allow use of VSPI with
+IPMMU-VP0 and IPMMU-VP1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a02aac487325b5bba09a7fd48569d36eb2394a51)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 4 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 3d50627c0670..b2d2f04c5e1c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -159,6 +159,10 @@
+ 	iommus = <&ipmmu_vp0 1>;
+ };
+ 
++&fcpvi1 {
++	iommus = <&ipmmu_vp0 9>;
++};
++
+ &fcpvd2 {
+ 	iommus = <&ipmmu_vi0 10>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 35efacd1ec21..10c7728d1b25 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2120,6 +2120,7 @@
+ 			clocks = <&cpg CPG_MOD 611>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 611>;
++			iommus = <&ipmmu_vp0 8>;
+ 		};
+ 
+ 		vspi1: vsp@fe9b0000 {
+@@ -2139,6 +2140,7 @@
+ 			clocks = <&cpg CPG_MOD 610>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			resets = <&cpg 610>;
++			iommus = <&ipmmu_vp1 9>;
+ 		};
+ 
+ 		vspd0: vsp@fea20000 {
+-- 
+2.19.0
+
diff --git a/patches/0607-arm64-dts-renesas-r8a7795-es1-Point-VSPI-via-FCPVI-t.patch b/patches/0607-arm64-dts-renesas-r8a7795-es1-Point-VSPI-via-FCPVI-t.patch
new file mode 100644
index 00000000000000..03391edfba1f84
--- /dev/null
+++ b/patches/0607-arm64-dts-renesas-r8a7795-es1-Point-VSPI-via-FCPVI-t.patch
@@ -0,0 +1,33 @@
+From b19f3d2ecee2ecd63b44c4966ffc787a0d84c911 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:28 +0100
+Subject: [PATCH 0607/1795] arm64: dts: renesas: r8a7795-es1: Point VSPI via
+ FCPVI to IPMMU-VP
+
+Hook up the FCPVI devices to allow use of VSPI with IPMMU-VP.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8f0940b0330c67ed8d6e7dad1210f9b519967ca0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index b2d2f04c5e1c..6713eeeab52a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -76,6 +76,7 @@
+ 		clocks = <&cpg CPG_MOD 609>;
+ 		power-domains = <&sysc R8A7795_PD_A3VP>;
+ 		resets = <&cpg 609>;
++		iommus = <&ipmmu_vp0 10>;
+ 	};
+ 
+ 	vspd3: vsp@fea38000 {
+-- 
+2.19.0
+
diff --git a/patches/0608-arm64-dts-renesas-r8a7795-Connect-Ethernet-AVB-to-IP.patch b/patches/0608-arm64-dts-renesas-r8a7795-Connect-Ethernet-AVB-to-IP.patch
new file mode 100644
index 00000000000000..50406cbc040997
--- /dev/null
+++ b/patches/0608-arm64-dts-renesas-r8a7795-Connect-Ethernet-AVB-to-IP.patch
@@ -0,0 +1,33 @@
+From f847124345aa9374728f18f8391bb91d4cbd5ca2 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:29 +0100
+Subject: [PATCH 0608/1795] arm64: dts: renesas: r8a7795: Connect Ethernet-AVB
+ to IPMMU-DS0
+
+Add IPMMU-DS0 to the Ethernet-AVB device node.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ca8740f419440a456d1aa1bbfe91a57c07b09975)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 10c7728d1b25..f5ab1c3370e6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -816,6 +816,7 @@
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii-txid";
++			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/0609-arm64-dts-renesas-r8a7795-Connect-SATA-to-IPMMU-HC.patch b/patches/0609-arm64-dts-renesas-r8a7795-Connect-SATA-to-IPMMU-HC.patch
new file mode 100644
index 00000000000000..a3b03a963b66c0
--- /dev/null
+++ b/patches/0609-arm64-dts-renesas-r8a7795-Connect-SATA-to-IPMMU-HC.patch
@@ -0,0 +1,33 @@
+From 7b1d7a71e92304e1c533f4f2e930043cc732af19 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:30 +0100
+Subject: [PATCH 0609/1795] arm64: dts: renesas: r8a7795: Connect SATA to
+ IPMMU-HC
+
+Add IPMMU-HC to the SATA device node.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0703824ca960ef855e5bc1239e03be520748fb5a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index f5ab1c3370e6..08c125cfa5d6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1645,6 +1645,7 @@
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 815>;
+ 			status = "disabled";
++			iommus = <&ipmmu_hc 2>;
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
+-- 
+2.19.0
+
diff --git a/patches/0610-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-MP1.patch b/patches/0610-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-MP1.patch
new file mode 100644
index 00000000000000..9ed1586953ca5a
--- /dev/null
+++ b/patches/0610-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-MP1.patch
@@ -0,0 +1,32 @@
+From d2a20c47da62339a6ee9eee24952d129f59d468a Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:32 +0100
+Subject: [PATCH 0610/1795] arm64: dts: renesas: r8a7795-es1: Enable IPMMU-MP1
+
+Enable the r8a7795 ES1.x device node for IPMMU-MP1.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0e467ade5e289625a637ebf3255f99c77d6192a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 6713eeeab52a..29b52d89c78a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -31,7 +31,6 @@
+ 		reg = <0 0xec680000 0 0x1000>;
+ 		renesas,ipmmu-main = <&ipmmu_mm 5>;
+ 		#iommu-cells = <1>;
+-		status = "disabled";
+ 	};
+ 
+ 	ipmmu_sy: mmu@e7730000 {
+-- 
+2.19.0
+
diff --git a/patches/0611-arm64-dts-renesas-r8a7795-Enable-IPMMU-VI0-VP1-DS0-D.patch b/patches/0611-arm64-dts-renesas-r8a7795-Enable-IPMMU-VI0-VP1-DS0-D.patch
new file mode 100644
index 00000000000000..255d2cd1d4e85b
--- /dev/null
+++ b/patches/0611-arm64-dts-renesas-r8a7795-Enable-IPMMU-VI0-VP1-DS0-D.patch
@@ -0,0 +1,66 @@
+From b9709927ea754c0db7baf95a965a8c835ff3f19e Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Fri, 10 Nov 2017 14:25:31 +0100
+Subject: [PATCH 0611/1795] arm64: dts: renesas: r8a7795: Enable IPMMU-VI0,
+ VP1, DS0, DS1 and MM
+
+Enable the r8a7795 device nodes for IPMMU-VI0, IPMMU-VP1, IPMMU-DS0,
+IPMMU-DS1 and the shared IPMMU-MM device.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 27767b784b5a7b13aedc248029570da0487722f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 08c125cfa5d6..a438d58f1b50 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -427,7 +427,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 14>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vi1: mmu@febe0000 {
+@@ -454,7 +453,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 17>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc0: mmu@fe6b0000 {
+@@ -544,7 +542,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ds1: mmu@e7740000 {
+@@ -553,7 +550,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -563,7 +559,6 @@
+ 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+-- 
+2.19.0
+
diff --git a/patches/0612-arm64-dts-renesas-salvator-common-Add-BD9571-PMIC.patch b/patches/0612-arm64-dts-renesas-salvator-common-Add-BD9571-PMIC.patch
new file mode 100644
index 00000000000000..96efaf57fd89b2
--- /dev/null
+++ b/patches/0612-arm64-dts-renesas-salvator-common-Add-BD9571-PMIC.patch
@@ -0,0 +1,71 @@
+From 199e76f17820001c7d0455b27d5e31d39e1e98e0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:34:10 +0100
+Subject: [PATCH 0612/1795] arm64: dts: renesas: salvator-common: Add BD9571
+ PMIC
+
+Add a device node for the ROHM BD9571MWV PMIC.
+
+This was based on the example in the DT binding documentation, but using
+IRQ0 instead of a GPIO interrupt, as that matches the schematics, and
+because INTC-EX is a simpler block.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f80f4920b78dbcbebbe5e0a1383bce7849cd08af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/salvator-common.dtsi     | 29 +++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 41942184b372..eba86c05b2b2 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -353,6 +353,30 @@
+ 
+ &i2c_dvfs {
+ 	status = "okay";
++
++	pmic: pmic@30 {
++		pinctrl-0 = <&irq0_pins>;
++		pinctrl-names = "default";
++
++		compatible = "rohm,bd9571mwv";
++		reg = <0x30>;
++		interrupt-parent = <&intc_ex>;
++		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		regulators {
++			dvfs: dvfs {
++				regulator-name = "dvfs";
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1030000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++		};
++	};
+ };
+ 
+ &ohci0 {
+@@ -408,6 +432,11 @@
+ 		function = "i2c2";
+ 	};
+ 
++	irq0_pins: irq0 {
++		groups = "intc_ex_irq0";
++		function = "intc_ex";
++	};
++
+ 	pwm1_pins: pwm1 {
+ 		groups = "pwm1_a";
+ 		function = "pwm1";
+-- 
+2.19.0
+
diff --git a/patches/0613-arm64-dts-renesas-r8a7795-es1-salvator-x-Add-SoC-nam.patch b/patches/0613-arm64-dts-renesas-r8a7795-es1-salvator-x-Add-SoC-nam.patch
new file mode 100644
index 00000000000000..adbae793f83cc9
--- /dev/null
+++ b/patches/0613-arm64-dts-renesas-r8a7795-es1-salvator-x-Add-SoC-nam.patch
@@ -0,0 +1,32 @@
+From 634e1c3d5414218acf0e5447a00ec8343a6495f9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:44:18 +0100
+Subject: [PATCH 0613/1795] arm64: dts: renesas: r8a7795-es1-salvator-x: Add
+ SoC name to file header
+
+Document clearly which SoC this DTS applies to, to distinguish from
+Salvator-X boards equipped with other SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aa8c6e451e96cb0db85e19d31da0b9bcc04e7217)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+index 3f7d5f51e428..7f2a3d923f21 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Device Tree Source for the Salvator-X board
++ * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
+  *
+  * Copyright (C) 2015 Renesas Electronics Corp.
+  *
+-- 
+2.19.0
+
diff --git a/patches/0614-arm64-dts-renesas-r8a7795-salvator-x-Add-SoC-name-to.patch b/patches/0614-arm64-dts-renesas-r8a7795-salvator-x-Add-SoC-name-to.patch
new file mode 100644
index 00000000000000..e213675b321ebc
--- /dev/null
+++ b/patches/0614-arm64-dts-renesas-r8a7795-salvator-x-Add-SoC-name-to.patch
@@ -0,0 +1,32 @@
+From 28ad7015c1423d67d0183164e8d0e45ed8d82d9f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:44:19 +0100
+Subject: [PATCH 0614/1795] arm64: dts: renesas: r8a7795-salvator-x: Add SoC
+ name to file header
+
+Document clearly which SoC this DTS applies to, to distinguish from
+Salvator-X boards equipped with other SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3d5863e6112adb8265456ca201d90bd9dc4eb886)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+index 17953070f38d..af467419266a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Device Tree Source for the Salvator-X board
++ * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
+  *
+  * Copyright (C) 2015 Renesas Electronics Corp.
+  *
+-- 
+2.19.0
+
diff --git a/patches/0615-arm64-dts-renesas-r8a7796-salvator-x-Add-SoC-name-to.patch b/patches/0615-arm64-dts-renesas-r8a7796-salvator-x-Add-SoC-name-to.patch
new file mode 100644
index 00000000000000..06889a52fadf5d
--- /dev/null
+++ b/patches/0615-arm64-dts-renesas-r8a7796-salvator-x-Add-SoC-name-to.patch
@@ -0,0 +1,32 @@
+From f9bb0b4574424106a42542fa12006d9e2adc880f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:44:20 +0100
+Subject: [PATCH 0615/1795] arm64: dts: renesas: r8a7796-salvator-x: Add SoC
+ name to file header
+
+Document clearly which SoC this DTS applies to, to distinguish from
+Salvator-X boards equipped with other SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8af1da9e8a804ef81a034f96f0e9a778e5f3cc6e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+index b317be03306e..498c9e807dc4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Device Tree Source for the Salvator-X board
++ * Device Tree Source for the Salvator-X board with R-Car M3-W
+  *
+  * Copyright (C) 2016 Renesas Electronics Corp.
+  *
+-- 
+2.19.0
+
diff --git a/patches/0616-arm64-dts-renesas-r8a7795-salvator-xs-Add-SoC-name-t.patch b/patches/0616-arm64-dts-renesas-r8a7795-salvator-xs-Add-SoC-name-t.patch
new file mode 100644
index 00000000000000..bd363b0cc96355
--- /dev/null
+++ b/patches/0616-arm64-dts-renesas-r8a7795-salvator-xs-Add-SoC-name-t.patch
@@ -0,0 +1,32 @@
+From b897eef5ac4f3679b71dd4512bfb1afa4bd6047b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:44:21 +0100
+Subject: [PATCH 0616/1795] arm64: dts: renesas: r8a7795-salvator-xs: Add SoC
+ name to file header
+
+Document clearly which SoC this DTS applies to, to distinguish from
+Salvator-XS boards equipped with other SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 61799464a4c01139fefe11aca2533e97ac579e00)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+index 7675de5d4f2c..8b50ceb746e8 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Device Tree Source for the Salvator-X 2nd version board
++ * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0
+  *
+  * Copyright (C) 2015-2017 Renesas Electronics Corp.
+  *
+-- 
+2.19.0
+
diff --git a/patches/0617-arm64-dts-renesas-r8a77995-Add-CAN-external-clock-su.patch b/patches/0617-arm64-dts-renesas-r8a77995-Add-CAN-external-clock-su.patch
new file mode 100644
index 00000000000000..2560dff5d9227e
--- /dev/null
+++ b/patches/0617-arm64-dts-renesas-r8a77995-Add-CAN-external-clock-su.patch
@@ -0,0 +1,42 @@
+From aedcbe76f27eefe2af44b4d028a935231d3570d6 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 17 Nov 2017 11:41:25 +0100
+Subject: [PATCH 0617/1795] arm64: dts: renesas: r8a77995: Add CAN external
+ clock support
+
+Adds external CAN clock node for r8a77995. This clock can be used as
+fCAN clock of CAN and CAN FD controller.
+
+Based on a patch for r8a7796 by Chris Paterson.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5ba27becdf2c0a62a22d2225b1e205c2eee0ef37)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 98b70542b812..0f78592d993c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -51,6 +51,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/0618-arm64-dts-renesas-r8a77995-Add-CAN-support.patch b/patches/0618-arm64-dts-renesas-r8a77995-Add-CAN-support.patch
new file mode 100644
index 00000000000000..289231ff719e8e
--- /dev/null
+++ b/patches/0618-arm64-dts-renesas-r8a77995-Add-CAN-support.patch
@@ -0,0 +1,65 @@
+From 39e715a45e1e189730afe6d62578d20e7143d6ef Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 17 Nov 2017 11:41:26 +0100
+Subject: [PATCH 0618/1795] arm64: dts: renesas: r8a77995: Add CAN support
+
+Adds CAN controller nodes for r8a77995.
+
+Based on a patch for r8a7796 by Chris Paterson.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit acaa51a35828d1188e1917d08a3c8c0447d3109b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 32 +++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 0f78592d993c..b2c8db15db53 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -346,6 +346,38 @@
+ 			resets = <&cpg 906>;
+ 		};
+ 
++		can0: can@e6c30000 {
++			compatible = "renesas,can-r8a77995",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c30000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
++
++		can1: can@e6c38000 {
++			compatible = "renesas,can-r8a77995",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c38000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
++
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77995",
+ 				     "renesas,etheravb-rcar-gen3";
+-- 
+2.19.0
+
diff --git a/patches/0619-arm64-dts-renesas-r8a77995-Add-CAN-FD-support.patch b/patches/0619-arm64-dts-renesas-r8a77995-Add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..f2c7d910fccacd
--- /dev/null
+++ b/patches/0619-arm64-dts-renesas-r8a77995-Add-CAN-FD-support.patch
@@ -0,0 +1,58 @@
+From c4986796371a495c438b9b35cbb6ef92cd693d9e Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 17 Nov 2017 11:41:27 +0100
+Subject: [PATCH 0619/1795] arm64: dts: renesas: r8a77995: Add CAN FD support
+
+Adds CAN FD controller node for r8a77995.
+
+Based on a patch for r8a7796 by Chris Paterson.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e2767b0f21d95e3df33b290e1cf79f295c02e44f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 25 +++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index b2c8db15db53..73149c73ef87 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -378,6 +378,31 @@
+ 			status = "disabled";
+ 		};
+ 
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a77995-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77995",
+ 				     "renesas,etheravb-rcar-gen3";
+-- 
+2.19.0
+
diff --git a/patches/0620-arm64-dts-renesas-r8a7795-Increase-the-number-of-GPI.patch b/patches/0620-arm64-dts-renesas-r8a7795-Increase-the-number-of-GPI.patch
new file mode 100644
index 00000000000000..1733e4da74efbb
--- /dev/null
+++ b/patches/0620-arm64-dts-renesas-r8a7795-Increase-the-number-of-GPI.patch
@@ -0,0 +1,54 @@
+From 07dadd7e1fd9a891f970bf987641efebc3b1a284 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 23 Nov 2017 11:58:50 +0100
+Subject: [PATCH 0620/1795] arm64: dts: renesas: r8a7795: Increase the number
+ of GPIO bank 1 ports to 29
+
+This patch changes the number of GPIO bank 1 ports to 29 because GP-1-28
+port pin of R8A7795 ES2.0 SoC support was added.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Fixes: 291e0c4994d0813f ("arm64: dts: r8a7795: Add support for R-Car H3 ES2.0")
+[geert: Keep 28 GPIOs on H3 ES1.x after r8a7795.dtsi sharing]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit eb14ed1ad7b6750b6b82e7f556f2c1c340f35b8f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 4 ++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 2 +-
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 29b52d89c78a..26769a11a190 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -109,6 +109,10 @@
+ 	};
+ };
+ 
++&gpio1 {
++	gpio-ranges = <&pfc 0 32 28>;
++};
++
+ &ipmmu_vi0 {
+ 	renesas,ipmmu-main = <&ipmmu_mm 11>;
+ };
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index a438d58f1b50..6db4f10376a1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -240,7 +240,7 @@
+ 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			#gpio-cells = <2>;
+ 			gpio-controller;
+-			gpio-ranges = <&pfc 0 32 28>;
++			gpio-ranges = <&pfc 0 32 29>;
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 911>;
+-- 
+2.19.0
+
diff --git a/patches/0621-arm64-dts-renesas-r8a77970-sort-includes.patch b/patches/0621-arm64-dts-renesas-r8a77970-sort-includes.patch
new file mode 100644
index 00000000000000..5f396440446b0a
--- /dev/null
+++ b/patches/0621-arm64-dts-renesas-r8a77970-sort-includes.patch
@@ -0,0 +1,36 @@
+From 5c2396e8c3c220a763e7e43ae8a1c1a6b2ea00cf Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:25:49 +0100
+Subject: [PATCH 0621/1795] arm64: dts: renesas: r8a77970: sort includes
+
+Sort includes used in r8a77970 DTS to improve maintainability
+and for consistency with other R-Car DTS files.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 830241c1e8cea1557b1de099756775e9fa0ab561)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 75d09f1724f0..8b97842aedb7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -9,9 +9,9 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/interrupt-controller/irq.h>
+-#include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/irq.h>
+ 
+ / {
+ 	compatible = "renesas,r8a77970";
+-- 
+2.19.0
+
diff --git a/patches/0622-arm64-dts-renesas-r8a77995-add-DMA-for-SCIF2.patch b/patches/0622-arm64-dts-renesas-r8a77995-add-DMA-for-SCIF2.patch
new file mode 100644
index 00000000000000..32f1525cb898ff
--- /dev/null
+++ b/patches/0622-arm64-dts-renesas-r8a77995-add-DMA-for-SCIF2.patch
@@ -0,0 +1,34 @@
+From 0cfaa96fe4e96703e3c869f40ecbfef4eed7c0f8 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 20 Nov 2017 16:46:35 +0100
+Subject: [PATCH 0622/1795] arm64: dts: renesas: r8a77995: add DMA for SCIF2
+
+Tested on Draak.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit af2ea3df851ffa68ad07ff59d4dabadbf33b45ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 73149c73ef87..21b832fb20b2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -457,6 +457,9 @@
+ 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
++			       <&dmac2 0x13>, <&dmac2 0x12>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 310>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/0623-arm64-dts-renesas-r8a77970-Add-IPMMU-device-nodes.patch b/patches/0623-arm64-dts-renesas-r8a77970-Add-IPMMU-device-nodes.patch
new file mode 100644
index 00000000000000..f8239df6520c52
--- /dev/null
+++ b/patches/0623-arm64-dts-renesas-r8a77970-Add-IPMMU-device-nodes.patch
@@ -0,0 +1,87 @@
+From 91749d68b0ecc5722ef5d8a5f6e210d96ead49a3 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:25:50 +0100
+Subject: [PATCH 0623/1795] arm64: dts: renesas: r8a77970: Add IPMMU device
+ nodes
+
+Add r8a77970 IPMMU nodes and keep all disabled by default.
+
+Based on work for the r8a7796 by Magnus Damm
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ce3b52a1595b25b05df86388d08aa454a885349d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 47 +++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 8b97842aedb7..5f73ee2dfd6d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -12,6 +12,7 @@
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/power/r8a77970-sysc.h>
+ 
+ / {
+ 	compatible = "renesas,r8a77970";
+@@ -134,6 +135,52 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A77970_PD_A3IR>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0624-arm64-dts-renesas-r8a77970-Tie-SYS-DMAC-to-IPMMU-DS1.patch b/patches/0624-arm64-dts-renesas-r8a77970-Tie-SYS-DMAC-to-IPMMU-DS1.patch
new file mode 100644
index 00000000000000..08032625043cc9
--- /dev/null
+++ b/patches/0624-arm64-dts-renesas-r8a77970-Tie-SYS-DMAC-to-IPMMU-DS1.patch
@@ -0,0 +1,49 @@
+From ddc7f7234d261e67989cb6b38742535be4a4f30f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:25:51 +0100
+Subject: [PATCH 0624/1795] arm64: dts: renesas: r8a77970: Tie SYS-DMAC to
+ IPMMU-DS1
+
+Hook up r8a77970 DMAC nodes to the IPMMU. In particular
+SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1.
+
+Based on work for the r8a7796 by Magnus Damm.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0071fcd1a9598996bd0fe3d5f746de0d55d97b11)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 5f73ee2dfd6d..108c6159c847 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -224,6 +224,10 @@
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <8>;
++			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
++			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
++			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
++			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
+ 		};
+ 
+ 		dmac2: dma-controller@e7310000 {
+@@ -248,6 +252,10 @@
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <8>;
++			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
++			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
++			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
++			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
+ 		};
+ 
+ 		hscif0: serial@e6540000 {
+-- 
+2.19.0
+
diff --git a/patches/0625-arm64-dts-renesas-r8a77970-Connect-Ethernet-AVB-to-I.patch b/patches/0625-arm64-dts-renesas-r8a77970-Connect-Ethernet-AVB-to-I.patch
new file mode 100644
index 00000000000000..e0f022ec9f952f
--- /dev/null
+++ b/patches/0625-arm64-dts-renesas-r8a77970-Connect-Ethernet-AVB-to-I.patch
@@ -0,0 +1,34 @@
+From 1d1eb59b066c7b665ddbb8b0f84e40c508f1925b Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:25:52 +0100
+Subject: [PATCH 0625/1795] arm64: dts: renesas: r8a77970: Connect Ethernet-AVB
+ to IPMMU-RT
+
+Add IPMMU-RT to the Ethernet-AVB device node.
+
+Based on work by Magnus Damm for the r8a7795.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0639be574ea246d65565b0bfe490a84baaee3d61)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 108c6159c847..0f93484e650a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -440,6 +440,7 @@
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii-id";
++			iommus = <&ipmmu_rt 3>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0626-arm64-dts-renesas-r8a77970-Enable-IPMMU-DS1-RT-and-M.patch b/patches/0626-arm64-dts-renesas-r8a77970-Enable-IPMMU-DS1-RT-and-M.patch
new file mode 100644
index 00000000000000..fc17874d454b2e
--- /dev/null
+++ b/patches/0626-arm64-dts-renesas-r8a77970-Enable-IPMMU-DS1-RT-and-M.patch
@@ -0,0 +1,51 @@
+From dc0e62eb65612a17f9b110c6ab05d867df0d8818 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:25:53 +0100
+Subject: [PATCH 0626/1795] arm64: dts: renesas: r8a77970: Enable IPMMU-DS1, RT
+ and MM
+
+Enable the r8a77970 device nodes for IPMMU-DS1, IPMMU-RT
+and the shared IPMMU-MM device.
+
+Based on work for the r8a7796 by Magnus Damm.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 572d48fadf597650cf397eb3a7b1f58991f733ce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 0f93484e650a..636b57a2edde 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -159,7 +159,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 7>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ds1: mmu@e7740000 {
+@@ -168,7 +167,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -178,7 +176,6 @@
+ 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
+-- 
+2.19.0
+
diff --git a/patches/0627-arm64-dts-renesas-r8a77995-Add-IPMMU-device-nodes.patch b/patches/0627-arm64-dts-renesas-r8a77995-Add-IPMMU-device-nodes.patch
new file mode 100644
index 00000000000000..faa63d9dbeaea4
--- /dev/null
+++ b/patches/0627-arm64-dts-renesas-r8a77995-Add-IPMMU-device-nodes.patch
@@ -0,0 +1,115 @@
+From 74d1762f0571e48c5edb0e2664cbb3b1a86e7bab Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:04 +0100
+Subject: [PATCH 0627/1795] arm64: dts: renesas: r8a77995: Add IPMMU device
+ nodes
+
+Add r8a77995 IPMMU nodes and keep all disabled by default.
+
+Based on work for the r8a7795 and r8a7796 by Magnus Damm
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a3901e7398e1d7045dfb21c607ddc1063600fc6d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 82 +++++++++++++++++++++++
+ 1 file changed, 82 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 21b832fb20b2..f02bf81e5a5a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -115,6 +115,88 @@
+ 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 14>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vp0: mmu@fe990000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfe990000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 16>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 12>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 10>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a77995-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/0628-arm64-dts-renesas-r8a77995-Connect-Ethernet-AVB-to-I.patch b/patches/0628-arm64-dts-renesas-r8a77995-Connect-Ethernet-AVB-to-I.patch
new file mode 100644
index 00000000000000..e957e6b8568ff2
--- /dev/null
+++ b/patches/0628-arm64-dts-renesas-r8a77995-Connect-Ethernet-AVB-to-I.patch
@@ -0,0 +1,34 @@
+From 4bb6710c5faffb8658a8abc589440b12ed00f8cc Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 10 Nov 2017 14:26:05 +0100
+Subject: [PATCH 0628/1795] arm64: dts: renesas: r8a77995: Connect Ethernet-AVB
+ to IPMMU-RT
+
+Add IPMMU-RT to the Ethernet-AVB device node.
+
+Based on work by Magnus Damm for the r8a7795.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 2ebdfea2bbf12c7e5c636fbb4d8616f2027e86f7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index f02bf81e5a5a..cff42cd1a6c8 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -525,6 +525,7 @@
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii-txid";
++			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/0629-arm64-renesas-document-V3MSK-board-bindings.patch b/patches/0629-arm64-renesas-document-V3MSK-board-bindings.patch
new file mode 100644
index 00000000000000..78505ce209ede7
--- /dev/null
+++ b/patches/0629-arm64-renesas-document-V3MSK-board-bindings.patch
@@ -0,0 +1,37 @@
+From ad5608b27263b16a1683578be3b45368385ede26 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 24 Nov 2017 23:47:39 +0300
+Subject: [PATCH 0629/1795] arm64: renesas: document V3MSK board bindings
+
+Document the V3M Starter Kit device tree bindings, listing it as
+a supported board.
+
+This allows to use checkpatch.pl to validate .dts files referring to
+the V3MSK board.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eebd0732136fd293c8f15a435978c1c34cd7f32f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 062520a0e74c..5c3af7ef0761 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -112,6 +112,8 @@ Boards:
+     compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
+   - SK-RZG1M (YR8A77430S000BE)
+     compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
++  - V3MSK
++    compatible = "renesas,v3msk", "renesas,r8a77970"
+   - Wheat
+     compatible = "renesas,wheat", "renesas,r8a7792"
+ 
+-- 
+2.19.0
+
diff --git a/patches/0630-arm64-dts-renesas-initial-V3MSK-board-device-tree.patch b/patches/0630-arm64-dts-renesas-initial-V3MSK-board-device-tree.patch
new file mode 100644
index 00000000000000..b1ed3150a7fbd1
--- /dev/null
+++ b/patches/0630-arm64-dts-renesas-initial-V3MSK-board-device-tree.patch
@@ -0,0 +1,91 @@
+From 348b317e0069cd0e0ef5c40362578bff69ea6046 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 24 Nov 2017 23:59:44 +0300
+Subject: [PATCH 0630/1795] arm64: dts: renesas: initial V3MSK board device
+ tree
+
+Add the initial device  tree for the V3M Starter Kit board.
+The board has 1 debug serial port (SCIF0); include support for it,
+so that the serial console can work.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cc3e267e9bb0ce7fead857f9258268ffa5f51b91)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  2 +-
+ .../arm64/boot/dts/renesas/r8a77970-v3msk.dts | 44 +++++++++++++++++++
+ 2 files changed, 45 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index f58e4f180ed0..c8da452fbc9c 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -7,7 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+-dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
++dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+ always		:= $(dtb-y)
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+new file mode 100644
+index 000000000000..50f49212f54e
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -0,0 +1,44 @@
++/*
++ * Device Tree Source for the V3M Starter Kit board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a77970.dtsi"
++
++/ {
++	model = "Renesas V3M Starter Kit board";
++	compatible = "renesas,v3msk", "renesas,r8a77970";
++
++	aliases {
++		serial0 = &scif0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x38000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <16666666>;
++};
++
++&extalr_clk {
++	clock-frequency = <32768>;
++};
++
++&scif0 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0631-arm64-dts-renesas-v3msk-add-EtherAVB-support.patch b/patches/0631-arm64-dts-renesas-v3msk-add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..f4c050a6276f23
--- /dev/null
+++ b/patches/0631-arm64-dts-renesas-v3msk-add-EtherAVB-support.patch
@@ -0,0 +1,46 @@
+From a01080febfe61abb3301b1280b947d6a85c598c4 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 24 Nov 2017 23:59:45 +0300
+Subject: [PATCH 0631/1795] arm64: dts: renesas: v3msk: add EtherAVB support
+
+Define the V3M Starter Kit board dependent part of the EtherAVB
+device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a6b1b7359074229504b2a81837eaf6ec54d3b300)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+index 50f49212f54e..8624ca87d6b2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -31,6 +31,17 @@
+ 	};
+ };
+ 
++&avb {
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/0632-arm64-dts-renesas-r8a77970-use-CPG-core-clock-macros.patch b/patches/0632-arm64-dts-renesas-r8a77970-use-CPG-core-clock-macros.patch
new file mode 100644
index 00000000000000..6c10483eafdc93
--- /dev/null
+++ b/patches/0632-arm64-dts-renesas-r8a77970-use-CPG-core-clock-macros.patch
@@ -0,0 +1,118 @@
+From 2ae7c67cf75b99dd8825387a97820126c3c36e48 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 28 Nov 2017 23:15:44 +0300
+Subject: [PATCH 0632/1795] arm64: dts: renesas: r8a77970: use CPG core clock
+ macros
+
+Now that the commit ecadea00f588 ("dt-bindings: clock: Add R8A77970 CPG
+core clock definitions") has hit Linus' tree, we  can replace the bare
+numbers (we had to use to avoid a cross tree dependency) with these macro
+definitions...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e221dab085d89bbd49ed6713b07201a5262aad7f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 636b57a2edde..7bb224595c95 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -9,7 +9,7 @@
+  * kind, whether express or implied.
+  */
+ 
+-#include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a77970-sysc.h>
+@@ -32,7 +32,7 @@
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0>;
+-			clocks = <&cpg CPG_CORE 0>;
++			clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
+ 			power-domains = <&sysc 5>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
+@@ -262,7 +262,7 @@
+ 			reg = <0 0xe6540000 0 96>;
+ 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 520>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+@@ -280,7 +280,7 @@
+ 			reg = <0 0xe6550000 0 96>;
+ 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 519>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+@@ -298,7 +298,7 @@
+ 			reg = <0 0xe6560000 0 96>;
+ 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 518>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+@@ -315,7 +315,7 @@
+ 			reg = <0 0xe66a0000 0 96>;
+ 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 517>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+@@ -333,7 +333,7 @@
+ 			reg = <0 0xe6e60000 0 64>;
+ 			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 207>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+@@ -351,7 +351,7 @@
+ 			reg = <0 0xe6e68000 0 64>;
+ 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 206>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+@@ -369,7 +369,7 @@
+ 			reg = <0 0xe6c50000 0 64>;
+ 			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 204>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+@@ -386,7 +386,7 @@
+ 			reg = <0 0xe6c40000 0 64>;
+ 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 203>,
+-				 <&cpg CPG_CORE 9>,
++				 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+-- 
+2.19.0
+
diff --git a/patches/0633-arm64-dts-renesas-r8a77970-use-SYSC-power-domain-mac.patch b/patches/0633-arm64-dts-renesas-r8a77970-use-SYSC-power-domain-mac.patch
new file mode 100644
index 00000000000000..bdf6b3c7a176bb
--- /dev/null
+++ b/patches/0633-arm64-dts-renesas-r8a77970-use-SYSC-power-domain-mac.patch
@@ -0,0 +1,171 @@
+From 8ae5b58033e0907490308a5e9cb7d290b5ca2162 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 28 Nov 2017 23:15:45 +0300
+Subject: [PATCH 0633/1795] arm64: dts: renesas: r8a77970: use SYSC power
+ domain macros
+
+Now that the commit 833bdb47c826 ("dt-bindings: power: add R8A77970 SYSC
+power domain definitions") has hit Linus' tree, we can replace the  bare
+numbers  (we had to use to avoid a cross tree dependency) with these macro
+definitions...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8aba250d7800702bbd2f6a91174e01b9a84ed2dd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 7bb224595c95..c35a117fc447 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -33,14 +33,14 @@
+ 			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0>;
+ 			clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
+-			power-domains = <&sysc 5>;
++			power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
+ 		};
+ 
+ 		L2_CA53: cache-controller {
+ 			compatible = "cache";
+-			power-domains = <&sysc 21>;
++			power-domains = <&sysc R8A77970_PD_CA53_SCU>;
+ 			cache-unified;
+ 			cache-level = <2>;
+ 		};
+@@ -88,7 +88,7 @@
+ 				      IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 408>;
+ 		};
+ 
+@@ -109,7 +109,7 @@
+ 				     "renesas,rcar-gen3-wdt";
+ 			reg = <0 0xe6020000 0 0x0c>;
+ 			clocks = <&cpg CPG_MOD 402>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 402>;
+ 			status = "disabled";
+ 		};
+@@ -190,7 +190,7 @@
+ 				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ 				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 407>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 407>;
+ 		};
+ 
+@@ -217,7 +217,7 @@
+ 					  "ch4", "ch5", "ch6", "ch7";
+ 			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <8>;
+@@ -245,7 +245,7 @@
+ 					  "ch4", "ch5", "ch6", "ch7";
+ 			clocks = <&cpg CPG_MOD 217>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <8>;
+@@ -268,7 +268,7 @@
+ 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ 			       <&dmac2 0x31>, <&dmac2 0x30>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 520>;
+ 			status = "disabled";
+ 		};
+@@ -286,7 +286,7 @@
+ 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ 			       <&dmac2 0x33>, <&dmac2 0x32>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 519>;
+ 			status = "disabled";
+ 		};
+@@ -304,7 +304,7 @@
+ 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ 			       <&dmac2 0x35>, <&dmac2 0x34>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 518>;
+ 			status = "disabled";
+ 		};
+@@ -321,7 +321,7 @@
+ 			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ 			       <&dmac2 0x37>, <&dmac2 0x36>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 517>;
+ 			status = "disabled";
+ 		};
+@@ -339,7 +339,7 @@
+ 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ 			       <&dmac2 0x51>, <&dmac2 0x50>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 207>;
+ 			status = "disabled";
+ 		};
+@@ -357,7 +357,7 @@
+ 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ 			       <&dmac2 0x53>, <&dmac2 0x52>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 206>;
+ 			status = "disabled";
+ 		};
+@@ -375,7 +375,7 @@
+ 			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ 			       <&dmac2 0x57>, <&dmac2 0x56>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 204>;
+ 			status = "disabled";
+ 		};
+@@ -392,7 +392,7 @@
+ 			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ 			       <&dmac2 0x59>, <&dmac2 0x58>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
+@@ -434,7 +434,7 @@
+ 					  "ch20", "ch21", "ch22", "ch23",
+ 					  "ch24";
+ 			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii-id";
+ 			iommus = <&ipmmu_rt 3>;
+-- 
+2.19.0
+
diff --git a/patches/0634-arm64-defconfig-enable-MUSB-HDRC-along-with-Allwinne.patch b/patches/0634-arm64-defconfig-enable-MUSB-HDRC-along-with-Allwinne.patch
new file mode 100644
index 00000000000000..1d985394ba51d6
--- /dev/null
+++ b/patches/0634-arm64-defconfig-enable-MUSB-HDRC-along-with-Allwinne.patch
@@ -0,0 +1,37 @@
+From ae453f9a41c52de4cf3aaf918818368571d953c0 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagannadh.teki@gmail.com>
+Date: Wed, 6 Dec 2017 23:19:58 +0530
+Subject: [PATCH 0634/1795] arm64: defconfig: enable MUSB HDRC along with
+ Allwinner glue
+
+Allwinner SoCs typically have a Mentor Graphics Inventra MUSB
+dual role controller for USB OTG. This is need for verifying
+gadget functions, so enable them by default.
+
+Tested 'otg' mode with mass storage function.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+(cherry picked from commit 051db633571b10c7112be00df83d5aee8d0f706e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index cad81b1723d8..89257ac3f54a 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -431,6 +431,8 @@ CONFIG_USB_OHCI_EXYNOS=y
+ CONFIG_USB_OHCI_HCD_PLATFORM=y
+ CONFIG_USB_RENESAS_USBHS=m
+ CONFIG_USB_STORAGE=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
+ CONFIG_USB_DWC3=y
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_CHIPIDEA=y
+-- 
+2.19.0
+
diff --git a/patches/0635-arm64-dts-renesas-r8a7795-Move-nodes-which-have-no-r.patch b/patches/0635-arm64-dts-renesas-r8a7795-Move-nodes-which-have-no-r.patch
new file mode 100644
index 00000000000000..d4485d94929383
--- /dev/null
+++ b/patches/0635-arm64-dts-renesas-r8a7795-Move-nodes-which-have-no-r.patch
@@ -0,0 +1,234 @@
+From 82e1cb537de3beb5943c4c1876d8d999a80f0303 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 30 Nov 2017 11:25:39 +0100
+Subject: [PATCH 0635/1795] arm64: dts: renesas: r8a7795: Move nodes which have
+ no reg property out of bus
+
+Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
+The nodes that have been moved do not have any register properties and thus
+shouldn't be placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4f5dc77b83503b5a0f8c974dcbd85749850514f3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 138 ++++++++++++-----------
+ 1 file changed, 71 insertions(+), 67 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 6db4f10376a1..a851c88e1e04 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -184,6 +184,30 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++		                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>,
++				     <&a57_1>,
++				     <&a57_2>,
++				     <&a57_3>;
++	};
++
++	pmu_a53 {
++		compatible = "arm,cortex-a53-pmu";
++		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a53_0>,
++				     <&a53_1>,
++				     <&a53_2>,
++				     <&a53_3>;
++	};
++
+ 	soc: soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -338,42 +362,6 @@
+ 			resets = <&cpg 905>;
+ 		};
+ 
+-		pmu_a57 {
+-			compatible = "arm,cortex-a57-pmu";
+-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-affinity = <&a57_0>,
+-					     <&a57_1>,
+-					     <&a57_2>,
+-					     <&a57_3>;
+-		};
+-
+-		pmu_a53 {
+-			compatible = "arm,cortex-a53-pmu";
+-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-affinity = <&a53_0>,
+-					     <&a53_1>,
+-					     <&a53_2>,
+-					     <&a53_3>;
+-		};
+-
+-		timer {
+-			compatible = "arm,armv8-timer";
+-			interrupts = <GIC_PPI 13
+-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14
+-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11
+-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10
+-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7795-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+@@ -2331,47 +2319,63 @@
+ 			#thermal-sensor-cells = <1>;
+ 			status = "okay";
+ 		};
++	};
+ 
+-		thermal-zones {
+-			sensor_thermal1: sensor-thermal1 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 0>;
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13
++				       (GIC_CPU_MASK_SIMPLE(8) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14
++				       (GIC_CPU_MASK_SIMPLE(8) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11
++				       (GIC_CPU_MASK_SIMPLE(8) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10
++				       (GIC_CPU_MASK_SIMPLE(8) |
++				       IRQ_TYPE_LEVEL_LOW)>;
++	};
+ 
+-				trips {
+-					sensor1_crit: sensor1-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
++	thermal-zones {
++		sensor_thermal1: sensor-thermal1 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 0>;
++
++			trips {
++				sensor1_crit: sensor1-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
+ 				};
+ 			};
++		};
+ 
+-			sensor_thermal2: sensor-thermal2 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 1>;
++		sensor_thermal2: sensor-thermal2 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 1>;
+ 
+-				trips {
+-					sensor2_crit: sensor2-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
++			trips {
++				sensor2_crit: sensor2-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
+ 				};
+ 			};
++		};
+ 
+-			sensor_thermal3: sensor-thermal3 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 2>;
++		sensor_thermal3: sensor-thermal3 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 2>;
+ 
+-				trips {
+-					sensor3_crit: sensor3-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
++			trips {
++				sensor3_crit: sensor3-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
+ 				};
+ 			};
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0636-arm64-dts-renesas-ulcb-Add-EthernetAVB-PHY-reset.patch b/patches/0636-arm64-dts-renesas-ulcb-Add-EthernetAVB-PHY-reset.patch
new file mode 100644
index 00000000000000..c0c30a5982e9a4
--- /dev/null
+++ b/patches/0636-arm64-dts-renesas-ulcb-Add-EthernetAVB-PHY-reset.patch
@@ -0,0 +1,41 @@
+From 3b99624a3baddf8fc01a9f0ed3460c2dacd84530 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 4 Dec 2017 11:34:52 +0100
+Subject: [PATCH 0636/1795] arm64: dts: renesas: ulcb: Add EthernetAVB PHY
+ reset
+
+Describe the GPIO used to reset the Ethernet PHY for EthernetAVB.
+This allows the driver to reset the PHY during probe and after system
+resume.
+
+On ULCB, the enable pin of the regulator providing PHY power is always
+pulled high, but the driver may still need to reset the PHY if this
+wasn't done by the bootloader before.
+
+Inspired by patches in the BSP for the individual Salvator-X/XS boards
+by Kazuya Mizuguchi.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ef4a3bc8dab721a3dbea871f35e0217643aa860c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index 73439cf48659..3e7a6b94e9f8 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -153,6 +153,7 @@
+ 		reg = <0>;
+ 		interrupt-parent = <&gpio2>;
+ 		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0637-arm64-dts-renesas-r8a7795-sort-subnodes-of-root-node.patch b/patches/0637-arm64-dts-renesas-r8a7795-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..70ba82ef11bce7
--- /dev/null
+++ b/patches/0637-arm64-dts-renesas-r8a7795-sort-subnodes-of-root-node.patch
@@ -0,0 +1,49 @@
+From 81a2feed7f9220ed8f3bbbcefdcb933e0eaf07c2 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 12 Dec 2017 09:27:52 +0100
+Subject: [PATCH 0637/1795] arm64: dts: renesas: r8a7795: sort subnodes of root
+ node alphabetically
+
+Sort root sub-nodes alphabetically for allow for easier maintenance
+of this file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 86af5aac311733d11c1c965522bd3d7fc6ee51c6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index a851c88e1e04..62dfc7781cc1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -30,11 +30,6 @@
+ 		i2c7 = &i2c_dvfs;
+ 	};
+ 
+-	psci {
+-		compatible = "arm,psci-1.0", "arm,psci-0.2";
+-		method = "smc";
+-	};
+-
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -208,6 +203,11 @@
+ 				     <&a53_3>;
+ 	};
+ 
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
+ 	soc: soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+-- 
+2.19.0
+
diff --git a/patches/0638-arm64-dts-renesas-r8a7796-sort-subnodes-of-root-node.patch b/patches/0638-arm64-dts-renesas-r8a7796-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..cfb1f2918b1d14
--- /dev/null
+++ b/patches/0638-arm64-dts-renesas-r8a7796-sort-subnodes-of-root-node.patch
@@ -0,0 +1,117 @@
+From 2239818e0d14ac7259145283e864948aed2304e7 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 12 Dec 2017 09:24:34 +0100
+Subject: [PATCH 0638/1795] arm64: dts: renesas: r8a7796: sort subnodes of root
+ node alphabetically
+
+Sort root sub-nodes alphabetically for allow for easier maintenance
+of this file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9d51ffc55dc1762a6300eaffd270c0aadd7b353b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 66 ++++++++++++------------
+ 1 file changed, 33 insertions(+), 33 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index cc0cca7c0494..c1b0d0344329 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -30,9 +30,34 @@
+ 		i2c7 = &i2c_dvfs;
+ 	};
+ 
+-	psci {
+-		compatible = "arm,psci-1.0", "arm,psci-0.2";
+-		method = "smc";
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
+ 	};
+ 
+ 	cpus {
+@@ -122,34 +147,16 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_c: audio_clk_c {
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* External CAN clock - to be overridden by boards that provide it */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
+ 	};
+ 
+ 	/* External SCIF clock - to be overridden by boards that provide it */
+@@ -159,13 +166,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* External PCIe clock - can be overridden by the board */
+-	pcie_bus_clk: pcie_bus {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+-- 
+2.19.0
+
diff --git a/patches/0639-arm64-dts-renesas-r8a7796-move-nodes-which-have-no-r.patch b/patches/0639-arm64-dts-renesas-r8a7796-move-nodes-which-have-no-r.patch
new file mode 100644
index 00000000000000..f20a55699ba561
--- /dev/null
+++ b/patches/0639-arm64-dts-renesas-r8a7796-move-nodes-which-have-no-r.patch
@@ -0,0 +1,236 @@
+From 710e28e2fa2a606a2da05284ffd48838d8f8386f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 12 Dec 2017 09:24:35 +0100
+Subject: [PATCH 0639/1795] arm64: dts: renesas: r8a7796: move nodes which have
+ no reg property out of bus
+
+Move pmu_a5[73], timer and thermal-zones nodes from soc node to root node.
+The nodes that have been moved do not have any register properties and thus
+shouldn't be placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb
+...
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb
+...
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb
+...
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb
+...
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a57 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+...
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9b9b8fd7e7c057fc8fd8148416296e71df70af44)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 144 +++++++++++------------
+ 1 file changed, 68 insertions(+), 76 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index c1b0d0344329..49c5893f8a35 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -154,6 +154,22 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>, <&a57_1>;
++	};
++
++	pmu_a53 {
++		compatible = "arm,cortex-a53-pmu";
++		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -190,18 +206,6 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv8-timer";
+-			interrupts = <GIC_PPI 13
+-					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14
+-					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11
+-					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10
+-					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		wdt0: watchdog@e6020000 {
+ 			compatible = "renesas,r8a7796-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -337,26 +341,6 @@
+ 			reg = <0 0xe6060000 0 0x50c>;
+ 		};
+ 
+-		pmu_a57 {
+-			compatible = "arm,cortex-a57-pmu";
+-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-affinity = <&a57_0>,
+-					     <&a57_1>;
+-		};
+-
+-		pmu_a53 {
+-			compatible = "arm,cortex-a53-pmu";
+-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-affinity = <&a53_0>,
+-					     <&a53_1>,
+-					     <&a53_2>,
+-					     <&a53_3>;
+-		};
+-
+ 		ipmmu_vi0: mmu@febd0000 {
+ 			compatible = "renesas,ipmmu-r8a7796";
+ 			reg = <0 0xfebd0000 0 0x1000>;
+@@ -1577,50 +1561,6 @@
+ 			status = "okay";
+ 		};
+ 
+-		thermal-zones {
+-			sensor_thermal1: sensor-thermal1 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 0>;
+-
+-				trips {
+-					sensor1_crit: sensor1-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
+-				};
+-			};
+-
+-			sensor_thermal2: sensor-thermal2 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 1>;
+-
+-				trips {
+-					sensor2_crit: sensor2-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
+-				};
+-			};
+-
+-			sensor_thermal3: sensor-thermal3 {
+-				polling-delay-passive = <250>;
+-				polling-delay = <1000>;
+-				thermal-sensors = <&tsc 2>;
+-
+-				trips {
+-					sensor3_crit: sensor3-crit {
+-						temperature = <120000>;
+-						hysteresis = <2000>;
+-						type = "critical";
+-					};
+-				};
+-			};
+-		};
+-
+ 		rcar_sound: sound@ec500000 {
+ 			/*
+ 			 * #sound-dai-cells is required
+@@ -2027,4 +1967,56 @@
+ 			resets = <&cpg 822>;
+ 		};
+ 	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	thermal-zones {
++		sensor_thermal1: sensor-thermal1 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 0>;
++
++			trips {
++				sensor1_crit: sensor1-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++
++		sensor_thermal2: sensor-thermal2 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 1>;
++
++			trips {
++				sensor2_crit: sensor2-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++
++		sensor_thermal3: sensor-thermal3 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 2>;
++
++			trips {
++				sensor3_crit: sensor3-crit {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0640-arm64-dts-renesas-r8a7796-add-reg-properties-to-pcie.patch b/patches/0640-arm64-dts-renesas-r8a7796-add-reg-properties-to-pcie.patch
new file mode 100644
index 00000000000000..17b5f9c4c2bc29
--- /dev/null
+++ b/patches/0640-arm64-dts-renesas-r8a7796-add-reg-properties-to-pcie.patch
@@ -0,0 +1,61 @@
+From 470fdd1a81f659a9e6a9913bda71c4a1cd45c35c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 12 Dec 2017 09:24:36 +0100
+Subject: [PATCH 0640/1795] arm64: dts: renesas: r8a7796: add reg properties to
+ pciec[01] nodes
+
+Add reg properties to pciec[01] placeholder nodes
+
+This is to stop the compiler complaining as follows:
+$ make
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@fe000000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@ee800000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pcie@fe000000 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (simple_bus_reg): Node /soc/pcie@ee800000 missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@fe000000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@ee800000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pcie@fe000000 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dtb: Warning (simple_bus_reg): Node /soc/pcie@ee800000 missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@fe000000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@ee800000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pcie@fe000000 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dtb: Warning (simple_bus_reg): Node /soc/pcie@ee800000 missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@fe000000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): Node /soc/pcie@ee800000 has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pcie@fe000000 missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (simple_bus_reg): Node /soc/pcie@ee800000 missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4316989537a6ed530807244fd2b69f274bf195ff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 49c5893f8a35..a339047acdc7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1758,10 +1758,12 @@
+ 		};
+ 
+ 		pciec0: pcie@fe000000 {
++			reg = <0 0xfe000000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pciec1: pcie@ee800000 {
++			reg = <0 0xee800000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0641-arm64-dts-renesas-r8a7795-add-usb3_phy-node.patch b/patches/0641-arm64-dts-renesas-r8a7795-add-usb3_phy-node.patch
new file mode 100644
index 00000000000000..b6df48b2209272
--- /dev/null
+++ b/patches/0641-arm64-dts-renesas-r8a7795-add-usb3_phy-node.patch
@@ -0,0 +1,61 @@
+From 76ddd1dd9c0a01c360448b1deb94b54c00d9dd46 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 7 Dec 2017 18:55:39 +0900
+Subject: [PATCH 0641/1795] arm64: dts: renesas: r8a7795: add usb3_phy node
+
+This patch adds USB3.0 PHY node for r8a7795.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7c1e5ea6bc17390db0bc66cff0ecbff9265b34a6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 26 ++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 62dfc7781cc1..d12df6f2ff09 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1631,6 +1631,19 @@
+ 			iommus = <&ipmmu_hc 2>;
+ 		};
+ 
++		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a7795-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
++			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
+ 		xhci0: usb@ee000000 {
+ 			compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
+ 			reg = <0 0xee000000 0 0xc00>;
+@@ -2380,4 +2393,17 @@
+ 			};
+ 		};
+ 	};
++
++	/* External USB clocks - can be overridden by the board */
++	usb3s0_clk: usb3s0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0642-arm64-dts-renesas-r8a7796-add-usb3_phy-node.patch b/patches/0642-arm64-dts-renesas-r8a7796-add-usb3_phy-node.patch
new file mode 100644
index 00000000000000..826fd3d66eeec0
--- /dev/null
+++ b/patches/0642-arm64-dts-renesas-r8a7796-add-usb3_phy-node.patch
@@ -0,0 +1,61 @@
+From 31295e4131d201bb2ca5222332fce5436de4c834 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 7 Dec 2017 18:55:40 +0900
+Subject: [PATCH 0642/1795] arm64: dts: renesas: r8a7796: add usb3_phy node
+
+This patch adds USB3.0 PHY node for r8a7796.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 488153d9fb3aa3d5b2e3acac34191917b83dbcd9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index a339047acdc7..c5192d513d7d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1403,6 +1403,19 @@
+ 			status = "disabled";
+ 		};
+ 
++		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a7796-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
++			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
+ 		xhci0: usb@ee000000 {
+ 			compatible = "renesas,xhci-r8a7796",
+ 				     "renesas,rcar-gen3-xhci";
+@@ -2021,4 +2034,17 @@
+ 			};
+ 		};
+ 	};
++
++	/* External USB clocks - can be overridden by the board */
++	usb3s0_clk: usb3s0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0643-arm64-dts-renesas-salvator-common-enable-usb3_phy0-n.patch b/patches/0643-arm64-dts-renesas-salvator-common-enable-usb3_phy0-n.patch
new file mode 100644
index 00000000000000..0a66697ee26033
--- /dev/null
+++ b/patches/0643-arm64-dts-renesas-salvator-common-enable-usb3_phy0-n.patch
@@ -0,0 +1,50 @@
+From 39ac228510902aaba28af08c5ba5dd574f48dce1 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 7 Dec 2017 18:55:41 +0900
+Subject: [PATCH 0643/1795] arm64: dts: renesas: salvator-common: enable
+ usb3_phy0 node
+
+This patch enables usb3_phy0 node for Salvator-X[S].
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d27f4ba7cc1556dd0e7806fd45b5430cbd6f9538)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index eba86c05b2b2..24385a5edd7e 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -653,6 +653,10 @@
+ 	shared-pin;
+ };
+ 
++&usb_extal_clk {
++	clock-frequency = <50000000>;
++};
++
+ &usb2_phy0 {
+ 	pinctrl-0 = <&usb0_pins>;
+ 	pinctrl-names = "default";
+@@ -668,6 +672,14 @@
+ 	status = "okay";
+ };
+ 
++&usb3_phy0 {
++	status = "okay";
++};
++
++&usb3s0_clk {
++	clock-frequency = <100000000>;
++};
++
+ &wdt0 {
+ 	timeout-sec = <60>;
+ 	status = "okay";
+-- 
+2.19.0
+
diff --git a/patches/0644-arm64-dts-renesas-salvator-common-enable-usb3_peri0.patch b/patches/0644-arm64-dts-renesas-salvator-common-enable-usb3_peri0.patch
new file mode 100644
index 00000000000000..0248895ced25d7
--- /dev/null
+++ b/patches/0644-arm64-dts-renesas-salvator-common-enable-usb3_peri0.patch
@@ -0,0 +1,47 @@
+From 4e2485667252d96f29384848dfd8b5cd41d4a134 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Thu, 7 Dec 2017 18:55:42 +0900
+Subject: [PATCH 0644/1795] arm64: dts: renesas: salvator-common: enable
+ usb3_peri0
+
+This patch enables usb3_peri0 that uses usb3_phy0 to enable VBUS
+detection for the USB3.0 peripheral.
+
+The Salvator-X[S] has USB3.0 type-A connector and supplies VBUS
+if USB3.0 host runs. So, you need a special cable for it, and
+to stop the VBUS supplies from the board, after you installs
+a gadget driver, you should run the following command to avoid
+conflict VBUS supply:
+
+	# echo 1 > /sys/kernel/debug/ee020000.usb/b_device
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 68b2c029e6200933fa3f6c06c8e6de33e8c78c51)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 24385a5edd7e..97b1c1cfa222 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -672,6 +672,13 @@
+ 	status = "okay";
+ };
+ 
++&usb3_peri0 {
++	phys = <&usb3_phy0>;
++	phy-names = "usb";
++
++	status = "okay";
++};
++
+ &usb3_phy0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0645-arm64-defconfig-enable-ARM_ARMADA_37XX_CPUFREQ.patch b/patches/0645-arm64-defconfig-enable-ARM_ARMADA_37XX_CPUFREQ.patch
new file mode 100644
index 00000000000000..fcdfb4a3b42ad5
--- /dev/null
+++ b/patches/0645-arm64-defconfig-enable-ARM_ARMADA_37XX_CPUFREQ.patch
@@ -0,0 +1,31 @@
+From b498552bf4d61bdd0a452ca3a38b99fb09b5814e Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Date: Fri, 15 Dec 2017 16:25:01 +0100
+Subject: [PATCH 0645/1795] arm64: defconfig: enable ARM_ARMADA_37XX_CPUFREQ
+
+Add the cpu frequency scaling support for Armada 37xx by default, this
+should allow a better coverage in kernel continuous integration tests.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+(cherry picked from commit ee0b915ba83212dc2288b08f1120c27c694a0d9b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 89257ac3f54a..1d87dab399c4 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -99,6 +99,7 @@ CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+ CONFIG_ARM_CPUIDLE=y
+ CONFIG_CPU_FREQ=y
+ CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+ CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+ CONFIG_ARM_SCPI_CPUFREQ=y
+ CONFIG_ACPI_CPPC_CPUFREQ=m
+-- 
+2.19.0
+
diff --git a/patches/0646-arm64-defconfig-enable-new-trigger-modes-for-leds.patch b/patches/0646-arm64-defconfig-enable-new-trigger-modes-for-leds.patch
new file mode 100644
index 00000000000000..a30e381c9dfe4f
--- /dev/null
+++ b/patches/0646-arm64-defconfig-enable-new-trigger-modes-for-leds.patch
@@ -0,0 +1,36 @@
+From 571e06e80b633c42200ac8b4d674e3893ccf0077 Mon Sep 17 00:00:00 2001
+From: Amit Kucheria <amit.kucheria@linaro.org>
+Date: Mon, 6 Nov 2017 12:38:13 +0530
+Subject: [PATCH 0646/1795] arm64: defconfig: enable new trigger modes for leds
+
+Most development boards and devices have one or more LEDs. It is useful
+during debugging if they can be wired to show different behaviours such as
+disk or cpu activity or a load-average dependent heartbeat. Enable panic
+and disk activity triggers so they can be tied to LED activity during
+debugging as well.
+
+Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit c6ff8d79268ddfb022e0855f1db0d54915ec7cf7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 1d87dab399c4..fdc6a07a08c1 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -478,6 +478,8 @@ CONFIG_LEDS_SYSCON=y
+ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+ CONFIG_LEDS_TRIGGER_CPU=y
+ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_DISK=y
+ CONFIG_EDAC=y
+ CONFIG_RTC_CLASS=y
+ CONFIG_RTC_DRV_MAX77686=y
+-- 
+2.19.0
+
diff --git a/patches/0647-arm64-defconfig-enable-CONFIG_UNIPHIER_EFUSE.patch b/patches/0647-arm64-defconfig-enable-CONFIG_UNIPHIER_EFUSE.patch
new file mode 100644
index 00000000000000..9a7962b3494473
--- /dev/null
+++ b/patches/0647-arm64-defconfig-enable-CONFIG_UNIPHIER_EFUSE.patch
@@ -0,0 +1,32 @@
+From 9a865d9910fa51d2236b381307d7abcfad93d105 Mon Sep 17 00:00:00 2001
+From: Keiji Hayashibara <hayashibara.keiji@socionext.com>
+Date: Thu, 30 Nov 2017 10:26:55 +0900
+Subject: [PATCH 0647/1795] arm64: defconfig: enable CONFIG_UNIPHIER_EFUSE
+
+Enable the efuse driver for UniPhier SoC
+
+Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 1e2138c5a310d22c443e80876971b9c480683f49)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index fdc6a07a08c1..ec12061a6bbb 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -565,6 +565,7 @@ CONFIG_PHY_XGENE=y
+ CONFIG_PHY_TEGRA_XUSB=y
+ CONFIG_QCOM_L2_PMU=y
+ CONFIG_QCOM_L3_PMU=y
++CONFIG_UNIPHIER_EFUSE=y
+ CONFIG_TEE=y
+ CONFIG_OPTEE=y
+ CONFIG_ARM_SCPI_PROTOCOL=y
+-- 
+2.19.0
+
diff --git a/patches/0648-arm64-defconfig-remove-CONFIG_USB_EHCI_MSM.patch b/patches/0648-arm64-defconfig-remove-CONFIG_USB_EHCI_MSM.patch
new file mode 100644
index 00000000000000..0d0421646e26fd
--- /dev/null
+++ b/patches/0648-arm64-defconfig-remove-CONFIG_USB_EHCI_MSM.patch
@@ -0,0 +1,36 @@
+From f3612cd1157dbbc18802fd397b281ca885066e06 Mon Sep 17 00:00:00 2001
+From: Alex Elder <elder@linaro.org>
+Date: Tue, 31 Oct 2017 07:58:06 -0500
+Subject: [PATCH 0648/1795] arm64: defconfig: remove CONFIG_USB_EHCI_MSM
+
+No Qualcomm SoC requires the "ehci-msm.c" code any more.  So remove
+the code, and remove the config option from the arm64 defconfig.
+
+Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Alex Elder <elder@linaro.org>
+Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Acked-by: Andy Gross <andy.gross@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit 17102eaae46a43ec0342294e2ce45b4a2c651379)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index ec12061a6bbb..c4e944423fc2 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -424,7 +424,6 @@ CONFIG_USB_OTG=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_TEGRA=y
+ CONFIG_USB_EHCI_HCD=y
+-CONFIG_USB_EHCI_MSM=y
+ CONFIG_USB_EHCI_EXYNOS=y
+ CONFIG_USB_EHCI_HCD_PLATFORM=y
+ CONFIG_USB_OHCI_HCD=y
+-- 
+2.19.0
+
diff --git a/patches/0649-arm64-defconfig-remove-CONFIG_USB_MSM_OTG.patch b/patches/0649-arm64-defconfig-remove-CONFIG_USB_MSM_OTG.patch
new file mode 100644
index 00000000000000..23dc64fbc8c948
--- /dev/null
+++ b/patches/0649-arm64-defconfig-remove-CONFIG_USB_MSM_OTG.patch
@@ -0,0 +1,37 @@
+From e40b5d2aea3c47f940141b825ec96381912335e3 Mon Sep 17 00:00:00 2001
+From: Alex Elder <elder@linaro.org>
+Date: Tue, 31 Oct 2017 07:58:07 -0500
+Subject: [PATCH 0649/1795] arm64: defconfig: remove CONFIG_USB_MSM_OTG
+
+No Qualcomm SoC requires the "phy-msm-usb.c" USB phy driver support
+any more.  Remove the code, and remove the config option from the
+arm64 defconfig.
+
+Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Alex Elder <elder@linaro.org>
+Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Acked-by: Andy Gross <andy.gross@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit 90a628613d6bd0d1398fd765643cb1b6ffb7dec8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index c4e944423fc2..a7e58ddba9d5 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -442,7 +442,6 @@ CONFIG_USB_CHIPIDEA_ULPI=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_HSIC_USB3503=y
+ CONFIG_NOP_USB_XCEIV=y
+-CONFIG_USB_MSM_OTG=y
+ CONFIG_USB_QCOM_8X16_PHY=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_GADGET=y
+-- 
+2.19.0
+
diff --git a/patches/0650-arm64-defconfig-remove-CONFIG_USB_QCOM_8X16_PHY.patch b/patches/0650-arm64-defconfig-remove-CONFIG_USB_QCOM_8X16_PHY.patch
new file mode 100644
index 00000000000000..dde00c49e030ba
--- /dev/null
+++ b/patches/0650-arm64-defconfig-remove-CONFIG_USB_QCOM_8X16_PHY.patch
@@ -0,0 +1,37 @@
+From e7df2f53c0d157a13c196422c969cc90899fca83 Mon Sep 17 00:00:00 2001
+From: Alex Elder <elder@linaro.org>
+Date: Tue, 31 Oct 2017 07:58:08 -0500
+Subject: [PATCH 0650/1795] arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY
+
+No Qualcomm SoC requires the "phy-qcom-8x16-usb.c" USB phy driver
+support any more.  Remove the code, and remove the config option
+from the arm64 defconfig.
+
+Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Alex Elder <elder@linaro.org>
+Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Acked-by: Andy Gross <andy.gross@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit d2fa1f37d21bf9729ae9ee79cb6bfc8de1f0a9a4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index a7e58ddba9d5..49509f18585c 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -442,7 +442,6 @@ CONFIG_USB_CHIPIDEA_ULPI=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_HSIC_USB3503=y
+ CONFIG_NOP_USB_XCEIV=y
+-CONFIG_USB_QCOM_8X16_PHY=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_RENESAS_USBHS_UDC=m
+-- 
+2.19.0
+
diff --git a/patches/0651-mtd-nand-use-reworked-NAND-controller-driver-with-Ma.patch b/patches/0651-mtd-nand-use-reworked-NAND-controller-driver-with-Ma.patch
new file mode 100644
index 00000000000000..ea2a50b542097a
--- /dev/null
+++ b/patches/0651-mtd-nand-use-reworked-NAND-controller-driver-with-Ma.patch
@@ -0,0 +1,51 @@
+From e3340a906f20577986a2c70fe7624a4100bdd602 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Tue, 9 Jan 2018 11:36:34 +0100
+Subject: [PATCH 0651/1795] mtd: nand: use reworked NAND controller driver with
+ Marvell EBU SoCs
+
+Choose to compile and embed marvell_nand.c as NAND controller driver
+instead of the legacy pxa3xx_nand.c for platforms with Marvell EBU
+SoCs.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+(cherry picked from commit dd533734395f0e14db12d82fc64a879c805743dd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/mvebu_v7_defconfig | 2 +-
+ arch/arm64/configs/defconfig        | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
+index 69553704f2dc..4b6e4fd47e5d 100644
+--- a/arch/arm/configs/mvebu_v7_defconfig
++++ b/arch/arm/configs/mvebu_v7_defconfig
+@@ -57,7 +57,7 @@ CONFIG_MTD_CFI_STAA=y
+ CONFIG_MTD_PHYSMAP_OF=y
+ CONFIG_MTD_M25P80=y
+ CONFIG_MTD_NAND=y
+-CONFIG_MTD_NAND_PXA3xx=y
++CONFIG_MTD_NAND_MARVELL=y
+ CONFIG_MTD_SPI_NOR=y
+ CONFIG_SRAM=y
+ CONFIG_MTD_UBI=y
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 49509f18585c..aa15c8ab8c95 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -162,7 +162,7 @@ CONFIG_MTD_BLOCK=y
+ CONFIG_MTD_M25P80=y
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_DENALI_DT=y
+-CONFIG_MTD_NAND_PXA3xx=y
++CONFIG_MTD_NAND_MARVELL=y
+ CONFIG_MTD_SPI_NOR=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_NBD=m
+-- 
+2.19.0
+
diff --git a/patches/0652-arm64-defconfig-enable-CONFIG_ACPI_APEI_MEMORY_FAILU.patch b/patches/0652-arm64-defconfig-enable-CONFIG_ACPI_APEI_MEMORY_FAILU.patch
new file mode 100644
index 00000000000000..60b96bd8f2fcfd
--- /dev/null
+++ b/patches/0652-arm64-defconfig-enable-CONFIG_ACPI_APEI_MEMORY_FAILU.patch
@@ -0,0 +1,42 @@
+From d436edbb72ee572ae0f1a08c80d71b07cded4b35 Mon Sep 17 00:00:00 2001
+From: "shiju.jose@huawei.com" <shiju.jose@huawei.com>
+Date: Tue, 16 Jan 2018 15:45:11 +0000
+Subject: [PATCH 0652/1795] arm64: defconfig: enable
+ CONFIG_ACPI_APEI_MEMORY_FAILURE
+
+Enable ACPI APEI MEMORY FAILURE option for ARM64,
+so that memory errors will be handled.
+
+Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
+Acked-by: Timur Tabi <timur@codeaurora.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 67cefd346fb14ed16db1cff983dead8ad58ac451)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index aa15c8ab8c95..03adccfcad69 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -86,6 +86,7 @@ CONFIG_SCHED_MC=y
+ CONFIG_NUMA=y
+ CONFIG_PREEMPT=y
+ CONFIG_KSM=y
++CONFIG_MEMORY_FAILURE=y
+ CONFIG_TRANSPARENT_HUGEPAGE=y
+ CONFIG_CMA=y
+ CONFIG_SECCOMP=y
+@@ -572,6 +573,7 @@ CONFIG_ACPI=y
+ CONFIG_ACPI_APEI=y
+ CONFIG_ACPI_APEI_GHES=y
+ CONFIG_ACPI_APEI_PCIEAER=y
++CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+ CONFIG_EXT2_FS=y
+ CONFIG_EXT3_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
+-- 
+2.19.0
+
diff --git a/patches/0653-arm64-defconfig-enable-EDAC-GHES-option.patch b/patches/0653-arm64-defconfig-enable-EDAC-GHES-option.patch
new file mode 100644
index 00000000000000..bc184e8e90c27e
--- /dev/null
+++ b/patches/0653-arm64-defconfig-enable-EDAC-GHES-option.patch
@@ -0,0 +1,33 @@
+From c8702e19b11bf7d1a1e47193d3d6f4545f35978c Mon Sep 17 00:00:00 2001
+From: "shiju.jose@huawei.com" <shiju.jose@huawei.com>
+Date: Tue, 16 Jan 2018 15:45:22 +0000
+Subject: [PATCH 0653/1795] arm64: defconfig: enable EDAC GHES option
+
+Enable CONFIG_EDAC_GHES option for ARM64,so that the memory errors
+are processed and reported to the user space.
+
+Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
+Acked-by: Timur Tabi <timur@codeaurora.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 001cd7f6667d82de9c29a76951605ab5cf7e8548)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 03adccfcad69..e26e7f7f50d3 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -479,6 +479,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+ CONFIG_LEDS_TRIGGER_PANIC=y
+ CONFIG_LEDS_TRIGGER_DISK=y
+ CONFIG_EDAC=y
++CONFIG_EDAC_GHES=y
+ CONFIG_RTC_CLASS=y
+ CONFIG_RTC_DRV_MAX77686=y
+ CONFIG_RTC_DRV_RK808=m
+-- 
+2.19.0
+
diff --git a/patches/0654-arm64-defconfig-enable-CONFIG_ACPI_APEI_EINJ.patch b/patches/0654-arm64-defconfig-enable-CONFIG_ACPI_APEI_EINJ.patch
new file mode 100644
index 00000000000000..227bbb5edd4043
--- /dev/null
+++ b/patches/0654-arm64-defconfig-enable-CONFIG_ACPI_APEI_EINJ.patch
@@ -0,0 +1,32 @@
+From 401ed8b586c1761b9052f642b1246efff4bcb38b Mon Sep 17 00:00:00 2001
+From: "shiju.jose@huawei.com" <shiju.jose@huawei.com>
+Date: Tue, 16 Jan 2018 15:45:34 +0000
+Subject: [PATCH 0654/1795] arm64: defconfig: enable CONFIG_ACPI_APEI_EINJ
+
+Enable APEI EINJ for ARM64 to support the error injection.
+
+Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
+Acked-by: Timur Tabi <timur@codeaurora.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 59779be03ee38e47ca48808f2d08997a81c3f095)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index e26e7f7f50d3..5a08e51c7ad0 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -575,6 +575,7 @@ CONFIG_ACPI_APEI=y
+ CONFIG_ACPI_APEI_GHES=y
+ CONFIG_ACPI_APEI_PCIEAER=y
+ CONFIG_ACPI_APEI_MEMORY_FAILURE=y
++CONFIG_ACPI_APEI_EINJ=y
+ CONFIG_EXT2_FS=y
+ CONFIG_EXT3_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
+-- 
+2.19.0
+
diff --git a/patches/0655-soc-renesas-rcar-sysc-Keep-wakeup-sources-active-dur.patch b/patches/0655-soc-renesas-rcar-sysc-Keep-wakeup-sources-active-dur.patch
new file mode 100644
index 00000000000000..c7ec44e692b0a2
--- /dev/null
+++ b/patches/0655-soc-renesas-rcar-sysc-Keep-wakeup-sources-active-dur.patch
@@ -0,0 +1,44 @@
+From 10e5e5269b3511bfae47bf69a552bee3bd86b088 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 9 Nov 2017 14:27:02 +0100
+Subject: [PATCH 0655/1795] soc: renesas: rcar-sysc: Keep wakeup sources active
+ during system suspend
+
+If an R-Car SYSC slave device is part of the CPG/MSTP or CPG/MSSR Clock
+Domain and to be used as a wakeup source, it must be kept active during
+system suspend.
+
+Currently this is handled in device-specific drivers by explicitly
+increasing the use count of the module clock when the device is
+configured as a wakeup source.  However, the proper way to prevent the
+device from being stopped is to inform this requirement to the genpd
+core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
+
+Note that this will only affect devices configured as wakeup sources.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 91c719f5ec6671f7b63762d78897af5583dd7693)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/rcar-sysc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 55a47e509e49..52c25a5e2646 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -224,7 +224,7 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+ 
+ 	if (!(pd->flags & (PD_CPU | PD_SCU))) {
+ 		/* Enable Clock Domain for I/O devices */
+-		genpd->flags |= GENPD_FLAG_PM_CLK;
++		genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ 		if (has_cpg_mstp) {
+ 			genpd->attach_dev = cpg_mstp_attach_dev;
+ 			genpd->detach_dev = cpg_mstp_detach_dev;
+-- 
+2.19.0
+
diff --git a/patches/0656-ARM-Fix-i2c-gpio-GPIO-descriptor-tables.patch b/patches/0656-ARM-Fix-i2c-gpio-GPIO-descriptor-tables.patch
new file mode 100644
index 00000000000000..366e07f9d0b90e
--- /dev/null
+++ b/patches/0656-ARM-Fix-i2c-gpio-GPIO-descriptor-tables.patch
@@ -0,0 +1,180 @@
+From ce49de7c4690358221c55084066e2d596e223987 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 26 May 2018 18:37:34 +0200
+Subject: [PATCH 0656/1795] ARM: Fix i2c-gpio GPIO descriptor tables
+
+I used bad names in my clumsiness when rewriting many board
+files to use GPIO descriptors instead of platform data. A few
+had the platform_device ID set to -1 which would indeed give
+the device name "i2c-gpio".
+
+But several had it set to >=0 which gives the names
+"i2c-gpio.0", "i2c-gpio.1" ...
+
+Fix the offending instances in the ARM tree. Sorry for the
+mess.
+
+Fixes: b2e63555592f ("i2c: gpio: Convert to use descriptors")
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: Simon Guinot <simon.guinot@sequanux.org>
+Reported-by: Simon Guinot <simon.guinot@sequanux.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+(cherry picked from commit f59c303b59b7404e5da70b80b6340b199cb95650)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-ep93xx/core.c          | 2 +-
+ arch/arm/mach-ixp4xx/avila-setup.c   | 2 +-
+ arch/arm/mach-ixp4xx/dsmg600-setup.c | 2 +-
+ arch/arm/mach-ixp4xx/fsg-setup.c     | 2 +-
+ arch/arm/mach-ixp4xx/ixdp425-setup.c | 2 +-
+ arch/arm/mach-ixp4xx/nas100d-setup.c | 2 +-
+ arch/arm/mach-ixp4xx/nslu2-setup.c   | 2 +-
+ arch/arm/mach-pxa/palmz72.c          | 2 +-
+ arch/arm/mach-pxa/viper.c            | 4 ++--
+ arch/arm/mach-sa1100/simpad.c        | 2 +-
+ 10 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index e70feec6fad5..0581ffbedddd 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -323,7 +323,7 @@ void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
+ 
+ /* All EP93xx devices use the same two GPIO pins for I2C bit-banging */
+ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		/* Use local offsets on gpiochip/port "G" */
+ 		GPIO_LOOKUP_IDX("G", 1, NULL, 0,
+diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
+index 77def6169f50..44cbbce6bda6 100644
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -51,7 +51,7 @@ static struct platform_device avila_flash = {
+ };
+ 
+ static struct gpiod_lookup_table avila_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", AVILA_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+index 8751cc273ce0..c2c0f975d52f 100644
+--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
++++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
+@@ -70,7 +70,7 @@ static struct platform_device dsmg600_flash = {
+ };
+ 
+ static struct gpiod_lookup_table dsmg600_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", DSMG600_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
+index 033f79b35d51..f0a152e365b1 100644
+--- a/arch/arm/mach-ixp4xx/fsg-setup.c
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -56,7 +56,7 @@ static struct platform_device fsg_flash = {
+ };
+ 
+ static struct gpiod_lookup_table fsg_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", FSG_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+index b168e2fbdbeb..3ec829d52cdd 100644
+--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
+@@ -124,7 +124,7 @@ static struct platform_device ixdp425_flash_nand = {
+ #endif	/* CONFIG_MTD_NAND_PLATFORM */
+ 
+ static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index 216a11b0e9b2..f403fc7ae5f9 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -102,7 +102,7 @@ static struct platform_device nas100d_leds = {
+ };
+ 
+ static struct gpiod_lookup_table nas100d_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NAS100D_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index 91da63a7d7b5..341b263482ef 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -70,7 +70,7 @@ static struct platform_device nslu2_flash = {
+ };
+ 
+ static struct gpiod_lookup_table nslu2_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", NSLU2_SDA_PIN,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
+index 5877e547cecd..0adb1bd6208e 100644
+--- a/arch/arm/mach-pxa/palmz72.c
++++ b/arch/arm/mach-pxa/palmz72.c
+@@ -322,7 +322,7 @@ static struct soc_camera_link palmz72_iclink = {
+ };
+ 
+ static struct gpiod_lookup_table palmz72_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.0",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("gpio-pxa", 118, NULL, 0,
+ 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
+index 4185e7ff073f..2b009fc59bcf 100644
+--- a/arch/arm/mach-pxa/viper.c
++++ b/arch/arm/mach-pxa/viper.c
+@@ -460,7 +460,7 @@ static struct platform_device smc91x_device = {
+ 
+ /* i2c */
+ static struct gpiod_lookup_table viper_i2c_gpiod_table = {
+-	.dev_id		= "i2c-gpio",
++	.dev_id		= "i2c-gpio.1",
+ 	.table		= {
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SDA_GPIO,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+@@ -789,7 +789,7 @@ static int __init viper_tpm_setup(char *str)
+ __setup("tpm=", viper_tpm_setup);
+ 
+ struct gpiod_lookup_table viper_tpm_i2c_gpiod_table = {
+-	.dev_id = "i2c-gpio",
++	.dev_id = "i2c-gpio.2",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SDA_GPIO,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
+index 7d4feb8a49ac..a75f23cac55c 100644
+--- a/arch/arm/mach-sa1100/simpad.c
++++ b/arch/arm/mach-sa1100/simpad.c
+@@ -326,7 +326,7 @@ static struct platform_device simpad_gpio_leds = {
+  * i2c
+  */
+ static struct gpiod_lookup_table simpad_i2c_gpiod_table = {
+-	.dev_id = "i2c-gpio",
++	.dev_id = "i2c-gpio.0",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("gpio", 21, NULL, 0,
+ 				GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+-- 
+2.19.0
+
diff --git a/patches/0657-MIPS-pb44-Fix-i2c-gpio-GPIO-descriptor-table.patch b/patches/0657-MIPS-pb44-Fix-i2c-gpio-GPIO-descriptor-table.patch
new file mode 100644
index 00000000000000..02cd190cca3b77
--- /dev/null
+++ b/patches/0657-MIPS-pb44-Fix-i2c-gpio-GPIO-descriptor-table.patch
@@ -0,0 +1,49 @@
+From 73157704109e91356b44b215f247dd0ee1e4ccc5 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 26 May 2018 19:12:51 +0200
+Subject: [PATCH 0657/1795] MIPS: pb44: Fix i2c-gpio GPIO descriptor table
+
+I used bad names in my clumsiness when rewriting many board
+files to use GPIO descriptors instead of platform data. A few
+had the platform_device ID set to -1 which would indeed give
+the device name "i2c-gpio".
+
+But several had it set to >=0 which gives the names
+"i2c-gpio.0", "i2c-gpio.1" ...
+
+Fix the one affected board in the MIPS tree. Sorry.
+
+Fixes: b2e63555592f ("i2c: gpio: Convert to use descriptors")
+Reported-by: Simon Guinot <simon.guinot@sequanux.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Paul Burton <paul.burton@mips.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: Simon Guinot <simon.guinot@sequanux.org>
+Cc: linux-mips@linux-mips.org
+Cc: <stable@vger.kernel.org> # 4.15+
+Patchwork: https://patchwork.linux-mips.org/patch/19387/
+Signed-off-by: James Hogan <jhogan@kernel.org>
+(cherry picked from commit 326345f995a83e326fa2e01d54bfa9a6a307bd4d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/mips/ath79/mach-pb44.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
+index 6b2c6f3baefa..75fb96ca61db 100644
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -34,7 +34,7 @@
+ #define PB44_KEYS_DEBOUNCE_INTERVAL	(3 * PB44_KEYS_POLL_INTERVAL)
+ 
+ static struct gpiod_lookup_table pb44_i2c_gpiod_table = {
+-	.dev_id = "i2c-gpio",
++	.dev_id = "i2c-gpio.0",
+ 	.table = {
+ 		GPIO_LOOKUP_IDX("ath79-gpio", PB44_GPIO_I2C_SDA,
+ 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+-- 
+2.19.0
+
diff --git a/patches/0658-i2c-gpio-initialize-SCL-to-HIGH-again.patch b/patches/0658-i2c-gpio-initialize-SCL-to-HIGH-again.patch
new file mode 100644
index 00000000000000..f13a2580123890
--- /dev/null
+++ b/patches/0658-i2c-gpio-initialize-SCL-to-HIGH-again.patch
@@ -0,0 +1,40 @@
+From be0cc22890e5273683664c5c786bf05416f60a8a Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 16 Jun 2018 21:56:36 +0900
+Subject: [PATCH 0658/1795] i2c: gpio: initialize SCL to HIGH again
+
+It seems that during the conversion from gpio* to gpiod*, the initial
+state of SCL was wrongly switched to LOW. Fix it to be HIGH again.
+
+Fixes: 7bb75029ef34 ("i2c: gpio: Enforce open drain through gpiolib")
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Cc: stable@kernel.org
+(cherry picked from commit 12b731dd46d9ee646318e6e9dc587314a3908a46)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-gpio.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index d80ea6ce91bb..6b75e591a6c7 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -172,9 +172,9 @@ static int i2c_gpio_probe(struct platform_device *pdev)
+ 	 * required for an I2C bus.
+ 	 */
+ 	if (pdata->scl_is_open_drain)
+-		gflags = GPIOD_OUT_LOW;
++		gflags = GPIOD_OUT_HIGH;
+ 	else
+-		gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
++		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
+ 	priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags);
+ 	if (IS_ERR(priv->scl))
+ 		return PTR_ERR(priv->scl);
+-- 
+2.19.0
+
diff --git a/patches/0659-ARM-dts-r8a7743-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0659-ARM-dts-r8a7743-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..4e62b466fcaa71
--- /dev/null
+++ b/patches/0659-ARM-dts-r8a7743-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From 9e4e0005c1717d5d51077516d192ae9c9d16ee24 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:22 +0200
+Subject: [PATCH 0659/1795] ARM: dts: r8a7743: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7743 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 81270ea7371cc77e47d121883aa54ade04222e41)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 7bbba4a36f31..f647b86c0205 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -827,7 +827,8 @@
+ 		};
+ 
+ 		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7743";
++			compatible = "renesas,ether-r8a7743",
++				     "renesas,rcar-gen2-ether";
+ 			reg = <0 0xee700000 0 0x400>;
+ 			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0660-ARM-dts-r8a7745-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0660-ARM-dts-r8a7745-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..0682a8f3ff0ab5
--- /dev/null
+++ b/patches/0660-ARM-dts-r8a7745-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From 23895f9555eaa41448b586d4f1ae1cfccc52f6d1 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:23 +0200
+Subject: [PATCH 0660/1795] ARM: dts: r8a7745: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7745 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit d5960269113e286d14e56cd9c2956135309953c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 3a50f703601c..6ad93f0deb8f 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -615,7 +615,8 @@
+ 		};
+ 
+ 		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7745";
++			compatible = "renesas,ether-r8a7745",
++				     "renesas,rcar-gen2-ether";
+ 			reg = <0 0xee700000 0 0x400>;
+ 			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0661-ARM-dts-r8a7778-Use-R-Car-Gen1-Ether-fallback-compat.patch b/patches/0661-ARM-dts-r8a7778-Use-R-Car-Gen1-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..1829df86c05229
--- /dev/null
+++ b/patches/0661-ARM-dts-r8a7778-Use-R-Car-Gen1-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From f7c564ce4fc2fea477da79a6c396117ae1f74e08 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:24 +0200
+Subject: [PATCH 0661/1795] ARM: dts: r8a7778: Use R-Car Gen1 Ether fallback
+ compat string
+
+Use newly added R-Car Gen1 Ether fallback compat string
+in the DT of the r8a7778 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 1bfd944483b209c577fa50cc981b4f959a287f83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7778.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
+index a39472aab867..d6e3c0400ec3 100644
+--- a/arch/arm/boot/dts/r8a7778.dtsi
++++ b/arch/arm/boot/dts/r8a7778.dtsi
+@@ -51,7 +51,8 @@
+ 	};
+ 
+ 	ether: ethernet@fde00000 {
+-		compatible = "renesas,ether-r8a7778";
++		compatible = "renesas,ether-r8a7778",
++			     "renesas,rcar-gen1-ether";
+ 		reg = <0xfde00000 0x400>;
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+-- 
+2.19.0
+
diff --git a/patches/0662-ARM-dts-r8a7790-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0662-ARM-dts-r8a7790-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..3d5d1fefe10687
--- /dev/null
+++ b/patches/0662-ARM-dts-r8a7790-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From 61e2379c5ce5958b7fbb61c78d1831b52722d6b5 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:25 +0200
+Subject: [PATCH 0662/1795] ARM: dts: r8a7790: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7790 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit adf65f3f575a06b4180b4b9ab8485603303e7596)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 62baabd757b6..55fc267bc59d 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -906,7 +906,8 @@
+ 	};
+ 
+ 	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7790";
++		compatible = "renesas,ether-r8a7790",
++			     "renesas,rcar-gen2-ether";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0663-ARM-dts-r8a7791-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0663-ARM-dts-r8a7791-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..786871f9fa9c4b
--- /dev/null
+++ b/patches/0663-ARM-dts-r8a7791-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From 5e19b6220923c821a94ac0dce5f8f155c4e059cc Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:26 +0200
+Subject: [PATCH 0663/1795] ARM: dts: r8a7791: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7791 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit fc2d62f04dfd03eefc0061f3db9c00ded83db19e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 67831d0405f3..9815a933e4cc 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -961,7 +961,8 @@
+ 	};
+ 
+ 	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7791";
++		compatible = "renesas,ether-r8a7791",
++			     "renesas,rcar-gen2-ether";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0664-ARM-dts-r8a7793-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0664-ARM-dts-r8a7793-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..b511e940425654
--- /dev/null
+++ b/patches/0664-ARM-dts-r8a7793-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From ae942d2888ad766c45efe90fa65c49f673a758e2 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:27 +0200
+Subject: [PATCH 0664/1795] ARM: dts: r8a7793: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7793 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ce900af9befa4fdb3a6abbbc212e7b8e75fcc9a0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 0cd1035de1a4..cdc59da5d4d8 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -916,7 +916,8 @@
+ 	};
+ 
+ 	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7793";
++		compatible = "renesas,ether-r8a7793",
++			     "renesas,rcar-gen2-ether";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0665-ARM-dts-r8a7794-Use-R-Car-Gen2-Ether-fallback-compat.patch b/patches/0665-ARM-dts-r8a7794-Use-R-Car-Gen2-Ether-fallback-compat.patch
new file mode 100644
index 00000000000000..2e63c259f14aeb
--- /dev/null
+++ b/patches/0665-ARM-dts-r8a7794-Use-R-Car-Gen2-Ether-fallback-compat.patch
@@ -0,0 +1,38 @@
+From 93ca3d6b008856fde93a51b0a82ee34324774b9e Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 18 Oct 2017 09:27:28 +0200
+Subject: [PATCH 0665/1795] ARM: dts: r8a7794: Use R-Car Gen2 Ether fallback
+ compat string
+
+Use newly added R-Car Gen2 Ether fallback compat string
+in the DT of the r8a7794 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 2ccbeaa92276aa3216f3db9ccf856e32f3822034)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 5643976c1356..6807f6a75acf 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -640,7 +640,8 @@
+ 	};
+ 
+ 	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7794";
++		compatible = "renesas,ether-r8a7794",
++			     "renesas,rcar-gen2-ether";
+ 		reg = <0 0xee700000 0 0x400>;
+ 		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 813>;
+-- 
+2.19.0
+
diff --git a/patches/0666-ARM-dts-r8a7743-Add-DU-support.patch b/patches/0666-ARM-dts-r8a7743-Add-DU-support.patch
new file mode 100644
index 00000000000000..421811891ff5ce
--- /dev/null
+++ b/patches/0666-ARM-dts-r8a7743-Add-DU-support.patch
@@ -0,0 +1,63 @@
+From 7643a512d935637757f38c3f1bd7453a845a678d Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 19:09:21 +0100
+Subject: [PATCH 0666/1795] ARM: dts: r8a7743: Add DU support
+
+Add du node to r8a7743 SoC DT. Boards that want to enable the DU
+need to specify the output topology.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0d975e29a51011c244d41e16a59a26fddf6ea281)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index f647b86c0205..112a72baa7a4 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1034,6 +1034,36 @@
+ 			};
+ 		};
+ 
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7743";
++			reg = <0 0xfeb00000 0 0x40000>,
++			      <0 0xfeb90000 0 0x1c>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 726>;
++			clock-names = "du.0", "du.1", "lvds.0";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
++
+ 		pci0: pci@ee090000 {
+ 			compatible = "renesas,pci-r8a7743",
+ 				     "renesas,pci-rcar-gen2";
+-- 
+2.19.0
+
diff --git a/patches/0667-ARM-dts-iwg22d-Use-dev-ttySC3-as-debug-console.patch b/patches/0667-ARM-dts-iwg22d-Use-dev-ttySC3-as-debug-console.patch
new file mode 100644
index 00000000000000..cb9a143f351998
--- /dev/null
+++ b/patches/0667-ARM-dts-iwg22d-Use-dev-ttySC3-as-debug-console.patch
@@ -0,0 +1,41 @@
+From fc06f4bf836400616f0b18ba31622b76a0098970 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:22 +0100
+Subject: [PATCH 0667/1795] ARM: dts: iwg22d: Use /dev/ttySC3 as debug console
+
+The BSP release from iWave uses /dev/ttySC3 as debug console, this patch
+renames the alias accordingly for compatibility.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4c1d14ce4a03af24c2bac21c4a19f17d20b4a763)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 52153ec3638c..edadeee8f1ec 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -16,13 +16,13 @@
+ 	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
+ 
+ 	aliases {
+-		serial0 = &scif4;
++		serial3 = &scif4;
+ 		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+ 		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+-		stdout-path = "serial0:115200n8";
++		stdout-path = "serial3:115200n8";
+ 	};
+ 
+ 	vccq_sdhi0: regulator-vccq-sdhi0 {
+-- 
+2.19.0
+
diff --git a/patches/0668-ARM-dts-iwg22d-Add-dev-ttySC5-support.patch b/patches/0668-ARM-dts-iwg22d-Add-dev-ttySC5-support.patch
new file mode 100644
index 00000000000000..79229ff947f94f
--- /dev/null
+++ b/patches/0668-ARM-dts-iwg22d-Add-dev-ttySC5-support.patch
@@ -0,0 +1,55 @@
+From 3b4aadd3d75bb7a0c796408047e4f40749ed14ab Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:23 +0100
+Subject: [PATCH 0668/1795] ARM: dts: iwg22d: Add /dev/ttySC5 support
+
+Add support for HSCIF1 as /dev/ttySC5, keeping the same naming
+scheme adopted by iWave in their BSP release. This interface
+uses RTS/CTS.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c7a5ddfbf171c222772087ba8697b163e8785caa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index edadeee8f1ec..82587d7b2056 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -17,6 +17,7 @@
+ 
+ 	aliases {
+ 		serial3 = &scif4;
++		serial5 = &hscif1;
+ 		ethernet0 = &avb;
+ 	};
+ 
+@@ -39,7 +40,20 @@
+ 	};
+ };
+ 
++&hscif1 {
++	pinctrl-0 = <&hscif1_pins>;
++	pinctrl-names = "default";
++
++	uart-has-rtscts;
++	status = "okay";
++};
++
+ &pfc {
++	hscif1_pins: hscif1 {
++		groups = "hscif1_data", "hscif1_ctrl";
++		function = "hscif1";
++	};
++
+ 	scif4_pins: scif4 {
+ 		groups = "scif4_data_b";
+ 		function = "scif4";
+-- 
+2.19.0
+
diff --git a/patches/0669-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-device-tree-for-HD.patch b/patches/0669-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-device-tree-for-HD.patch
new file mode 100644
index 00000000000000..ab95f1c5c9021e
--- /dev/null
+++ b/patches/0669-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-device-tree-for-HD.patch
@@ -0,0 +1,106 @@
+From a0d122a820d4f40d6393f1db549cc05345ec17db Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:24 +0100
+Subject: [PATCH 0669/1795] ARM: dts: iwg22d-sodimm-dbhd-ca: Add device tree
+ for HDMI DB
+
+Add file r8a7745-iwg22d-sodimm-dbhd-ca.dts to provide support for
+iW-RainboW-G22D with HDMI daughter board plugged in.
+
+The interfaces defined in the new .dts file are: scif1, scif5,
+and hscif2.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ea03afbeb80edfb460570082855b4b1dd19fc7e7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/Makefile                    |  1 +
+ .../dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts     | 61 +++++++++++++++++++
+ 2 files changed, 62 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index b6c97b70e85f..58fae9c03b82 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -728,6 +728,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
+ 	r8a7743-iwg20d-q7-dbcm-ca.dtb \
+ 	r8a7743-sk-rzg1m.dtb \
+ 	r8a7745-iwg22d-sodimm.dtb \
++	r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
+ 	r8a7745-sk-rzg1e.dtb \
+ 	r8a7778-bockw.dtb \
+ 	r8a7779-marzen.dtb \
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+new file mode 100644
+index 000000000000..f925388454da
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+@@ -0,0 +1,61 @@
++/*
++ * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter
++ * board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7745-iwg22d-sodimm.dts"
++
++/ {
++	model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on";
++	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
++
++	aliases {
++		serial0 = &scif1;
++		serial4 = &scif5;
++		serial6 = &hscif2;
++	};
++};
++
++&hscif2 {
++	pinctrl-0 = <&hscif2_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&pfc {
++	hscif2_pins: hscif2 {
++		groups = "hscif2_data";
++		function = "hscif2";
++	};
++
++	scif1_pins: scif1 {
++		groups = "scif1_data";
++		function = "scif1";
++	};
++
++	scif5_pins: scif5 {
++		groups = "scif5_data_d";
++		function = "scif5";
++	};
++};
++
++&scif1 {
++	pinctrl-0 = <&scif1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&scif5 {
++	pinctrl-0 = <&scif5_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/0670-ARM-dts-iwg22d-sodimm-sort-dt-nodes.patch b/patches/0670-ARM-dts-iwg22d-sodimm-sort-dt-nodes.patch
new file mode 100644
index 00000000000000..2bda4066af602c
--- /dev/null
+++ b/patches/0670-ARM-dts-iwg22d-sodimm-sort-dt-nodes.patch
@@ -0,0 +1,132 @@
+From f2de9565daaa6e691951548688d27cda0ff9889a Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:25 +0100
+Subject: [PATCH 0670/1795] ARM: dts: iwg22d-sodimm: sort dt nodes
+
+Improve the layout of r8a7745-iwg22d-sodimm.dts by sorting the
+nodes alphabetically.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 738a368d558f24d2c34ef420fc0d8ab8499b0ebe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 62 ++++++++++-----------
+ 1 file changed, 31 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 82587d7b2056..3eb4f83297d4 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -16,9 +16,9 @@
+ 	compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
+ 
+ 	aliases {
++		ethernet0 = &avb;
+ 		serial3 = &scif4;
+ 		serial5 = &hscif1;
+-		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+@@ -40,6 +40,25 @@
+ 	};
+ };
+ 
++&avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
++	phy-handle = <&phy3>;
++	phy-mode = "gmii";
++	renesas,no-ether-link;
++	status = "okay";
++
++	phy3: ethernet-phy@3 {
++	/*
++	 * On some older versions of the platform (before R4.0) the phy address
++	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
++	 */
++		reg = <3>;
++		micrel,led-mode = <1>;
++	};
++};
++
+ &hscif1 {
+ 	pinctrl-0 = <&hscif1_pins>;
+ 	pinctrl-names = "default";
+@@ -48,7 +67,18 @@
+ 	status = "okay";
+ };
+ 
++&pci1 {
++	status = "okay";
++	pinctrl-0 = <&usb1_pins>;
++	pinctrl-names = "default";
++};
++
+ &pfc {
++	avb_pins: avb {
++		groups = "avb_mdio", "avb_gmii";
++		function = "avb";
++	};
++
+ 	hscif1_pins: hscif1 {
+ 		groups = "hscif1_data", "hscif1_ctrl";
+ 		function = "hscif1";
+@@ -59,11 +89,6 @@
+ 		function = "scif4";
+ 	};
+ 
+-	avb_pins: avb {
+-		groups = "avb_mdio", "avb_gmii";
+-		function = "avb";
+-	};
+-
+ 	sdhi0_pins: sd0 {
+ 		groups = "sdhi0_data4", "sdhi0_ctrl";
+ 		function = "sdhi0";
+@@ -83,25 +108,6 @@
+ 	status = "okay";
+ };
+ 
+-&avb {
+-	pinctrl-0 = <&avb_pins>;
+-	pinctrl-names = "default";
+-
+-	phy-handle = <&phy3>;
+-	phy-mode = "gmii";
+-	renesas,no-ether-link;
+-	status = "okay";
+-
+-	phy3: ethernet-phy@3 {
+-	/*
+-	 * On some older versions of the platform (before R4.0) the phy address
+-	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+-	 */
+-		reg = <3>;
+-		micrel,led-mode = <1>;
+-	};
+-};
+-
+ &sdhi0 {
+ 	pinctrl-0 = <&sdhi0_pins>;
+ 	pinctrl-names = "default";
+@@ -112,12 +118,6 @@
+ 	status = "okay";
+ };
+ 
+-&pci1 {
+-	status = "okay";
+-	pinctrl-0 = <&usb1_pins>;
+-	pinctrl-names = "default";
+-};
+-
+ &usbphy {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0671-ARM-dts-r8a7745-Add-HS-USB-device-node.patch b/patches/0671-ARM-dts-r8a7745-Add-HS-USB-device-node.patch
new file mode 100644
index 00000000000000..cbd1acda05f3b0
--- /dev/null
+++ b/patches/0671-ARM-dts-r8a7745-Add-HS-USB-device-node.patch
@@ -0,0 +1,48 @@
+From 6e88dc0b6e211c3ca53862b9cc3ea1a4627e9f64 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:26 +0100
+Subject: [PATCH 0671/1795] ARM: dts: r8a7745: Add HS-USB device node
+
+From: Biju Das <biju.das@bp.renesas.com>
+
+Define the R8A7745 generic part of the HS-USB device node. It is up to the
+board file to enable the device.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c5a541b81bc02d0746bf78ca7bfa9080d91c3aff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 6ad93f0deb8f..432aa48ea395 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -917,6 +917,20 @@
+ 			};
+ 		};
+ 
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7745",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
+ 		usbphy: usb-phy@e6590100 {
+ 			compatible = "renesas,usb-phy-r8a7745",
+ 				     "renesas,rcar-gen2-usb-phy";
+-- 
+2.19.0
+
diff --git a/patches/0672-ARM-dts-r8a7745-Add-USB-DMAC-device-nodes.patch b/patches/0672-ARM-dts-r8a7745-Add-USB-DMAC-device-nodes.patch
new file mode 100644
index 00000000000000..ebbdb1f23f6a44
--- /dev/null
+++ b/patches/0672-ARM-dts-r8a7745-Add-USB-DMAC-device-nodes.patch
@@ -0,0 +1,59 @@
+From 78be19d498fb8bc4c3ed03e7d2d8408526503b27 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:27 +0100
+Subject: [PATCH 0672/1795] ARM: dts: r8a7745: Add USB-DMAC device nodes
+
+From: Biju Das <biju.das@bp.renesas.com>
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fbdf17b307dae407b2e673806386f84660d01b63)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 432aa48ea395..6e0c69bb375d 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -312,6 +312,34 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7745-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7745-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
+ 		scifa0: serial@e6c40000 {
+ 			compatible = "renesas,scifa-r8a7745",
+ 				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-- 
+2.19.0
+
diff --git a/patches/0673-ARM-dts-r8a7745-Enable-DMA-for-HSUSB.patch b/patches/0673-ARM-dts-r8a7745-Enable-DMA-for-HSUSB.patch
new file mode 100644
index 00000000000000..90a028c659f35d
--- /dev/null
+++ b/patches/0673-ARM-dts-r8a7745-Enable-DMA-for-HSUSB.patch
@@ -0,0 +1,36 @@
+From 83c505f5414c9335c1e20ca99a0d64ce192acf47 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:28 +0100
+Subject: [PATCH 0673/1795] ARM: dts: r8a7745: Enable DMA for HSUSB
+
+From: Biju Das <biju.das@bp.renesas.com>
+
+This patch adds DMA properties to the HSUSB node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d4595f040881976d5a232922d8592a0d576ce3a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 6e0c69bb375d..948dd1fc2d9c 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -951,6 +951,9 @@
+ 			reg = <0 0xe6590000 0 0x100>;
+ 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ 			resets = <&cpg 704>;
+ 			renesas,buswait = <4>;
+-- 
+2.19.0
+
diff --git a/patches/0674-ARM-dts-iwg22d-sodimm-Enable-HS-USB.patch b/patches/0674-ARM-dts-iwg22d-sodimm-Enable-HS-USB.patch
new file mode 100644
index 00000000000000..971f40d07e6edc
--- /dev/null
+++ b/patches/0674-ARM-dts-iwg22d-sodimm-Enable-HS-USB.patch
@@ -0,0 +1,51 @@
+From bd52a0c699e432b6586bc5dcc1de207ac5175aa5 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:29 +0100
+Subject: [PATCH 0674/1795] ARM: dts: iwg22d-sodimm: Enable HS-USB
+
+From: Biju Das <biju.das@bp.renesas.com>
+
+Enable HS-USB on iWave RZ/G1E carrier board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b73ae2bdd83af78e5057d20ab2884cfd004c8543)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 3eb4f83297d4..80c82aa94c06 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -67,6 +67,12 @@
+ 	status = "okay";
+ };
+ 
++&hsusb {
++	status = "okay";
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++};
++
+ &pci1 {
+ 	status = "okay";
+ 	pinctrl-0 = <&usb1_pins>;
+@@ -95,6 +101,11 @@
+ 		power-source = <3300>;
+ 	};
+ 
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
++
+ 	usb1_pins: usb1 {
+ 		groups = "usb1";
+ 		function = "usb1";
+-- 
+2.19.0
+
diff --git a/patches/0675-ARM-dts-r8a7745-Add-IIC-cores-to-dtsi.patch b/patches/0675-ARM-dts-r8a7745-Add-IIC-cores-to-dtsi.patch
new file mode 100644
index 00000000000000..7289d4ecc997d4
--- /dev/null
+++ b/patches/0675-ARM-dts-r8a7745-Add-IIC-cores-to-dtsi.patch
@@ -0,0 +1,76 @@
+From a603ba8ab96408b5aa3b6919be993d64ec4c231a Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 23 Oct 2017 18:09:30 +0100
+Subject: [PATCH 0675/1795] ARM: dts: r8a7745: Add IIC cores to dtsi
+
+Add iic0 and iic1 nodes to SoC dtsi. Also, define aliases i2c6
+and i2c7. Board specific DT files will enable the interfaces
+if needed.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0ee0aff583ddb6e92a5d05a1f2147a772413ab40)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 948dd1fc2d9c..16dc4895b455 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -25,6 +25,8 @@
+ 		i2c3 = &i2c3;
+ 		i2c4 = &i2c4;
+ 		i2c5 = &i2c5;
++		i2c6 = &iic0;
++		i2c7 = &iic1;
+ 		spi0 = &qspi;
+ 		spi1 = &msiof0;
+ 		spi2 = &msiof1;
+@@ -753,6 +755,40 @@
+ 			status = "disabled";
+ 		};
+ 
++		iic0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7745",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
++
++		iic1: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7745",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
++
+ 		mmcif0: mmc@ee200000 {
+ 			compatible = "renesas,mmcif-r8a7745",
+ 				     "renesas,sh-mmcif";
+-- 
+2.19.0
+
diff --git a/patches/0676-ARM-dts-r8a7743-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0676-ARM-dts-r8a7743-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..14bd05bf66a7aa
--- /dev/null
+++ b/patches/0676-ARM-dts-r8a7743-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From d76b778c841fbcacdf4c4c0c69cc249c603f5742 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:51 +0200
+Subject: [PATCH 0676/1795] ARM: dts: r8a7743: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7743 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 67eee4eeb3cd4df684a18f3824ea8030ea37d442)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 112a72baa7a4..6aa86b75b80c 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -954,7 +954,8 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7743";
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee100000 0 0x328>;
+ 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 314>;
+@@ -968,7 +969,8 @@
+ 		};
+ 
+ 		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7743";
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee140000 0 0x100>;
+ 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 312>;
+@@ -982,7 +984,8 @@
+ 		};
+ 
+ 		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7743";
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee160000 0 0x100>;
+ 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0677-ARM-dts-r8a7745-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0677-ARM-dts-r8a7745-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..5908b8a6a043c7
--- /dev/null
+++ b/patches/0677-ARM-dts-r8a7745-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From e9b9c9c028bd9dbcc53836bda89115534296e172 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:52 +0200
+Subject: [PATCH 0677/1795] ARM: dts: r8a7745: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7745 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 35098dd2e37d51cdab26637479fb892c254c2555)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 16dc4895b455..846c27a00c54 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -870,7 +870,8 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7745";
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee100000 0 0x328>;
+ 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 314>;
+@@ -884,7 +885,8 @@
+ 		};
+ 
+ 		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7745";
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee140000 0 0x100>;
+ 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 312>;
+@@ -898,7 +900,8 @@
+ 		};
+ 
+ 		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7745";
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee160000 0 0x100>;
+ 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0678-ARM-dts-r8a7778-Use-R-Car-SDHI-Gen1-fallback-compat-.patch b/patches/0678-ARM-dts-r8a7778-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
new file mode 100644
index 00000000000000..3b781235a949cc
--- /dev/null
+++ b/patches/0678-ARM-dts-r8a7778-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From d9ff9d67f342d1690d9d25ef851556abc66a7ecb Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:53 +0200
+Subject: [PATCH 0678/1795] ARM: dts: r8a7778: Use R-Car SDHI Gen1 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen1 fallback compat string
+in the DT of the r8a7778 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bce90b30fc0b65fb4a7c89135a563f5cffdf64cd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7778.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
+index d6e3c0400ec3..3b49f9ed2e2b 100644
+--- a/arch/arm/boot/dts/r8a7778.dtsi
++++ b/arch/arm/boot/dts/r8a7778.dtsi
+@@ -380,7 +380,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ffe4c000 {
+-		compatible = "renesas,sdhi-r8a7778";
++		compatible = "renesas,sdhi-r8a7778",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4c000 0x100>;
+ 		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+@@ -389,7 +390,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ffe4d000 {
+-		compatible = "renesas,sdhi-r8a7778";
++		compatible = "renesas,sdhi-r8a7778",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4d000 0x100>;
+ 		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+@@ -398,7 +400,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ffe4f000 {
+-		compatible = "renesas,sdhi-r8a7778";
++		compatible = "renesas,sdhi-r8a7778",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4f000 0x100>;
+ 		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+-- 
+2.19.0
+
diff --git a/patches/0679-ARM-dts-r8a7779-Use-R-Car-SDHI-Gen1-fallback-compat-.patch b/patches/0679-ARM-dts-r8a7779-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
new file mode 100644
index 00000000000000..57dfe5c380c700
--- /dev/null
+++ b/patches/0679-ARM-dts-r8a7779-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
@@ -0,0 +1,67 @@
+From 676a43729ef0910109f3db7c0fded84c3e6b70d9 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:54 +0200
+Subject: [PATCH 0679/1795] ARM: dts: r8a7779: Use R-Car SDHI Gen1 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen1 fallback compat string
+in the DT of the r8a7779 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0863a6ef429790f4a44031b52f313480e25fb9f0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
+index e8eb94748b27..e79ae306eedd 100644
+--- a/arch/arm/boot/dts/r8a7779.dtsi
++++ b/arch/arm/boot/dts/r8a7779.dtsi
+@@ -355,7 +355,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ffe4c000 {
+-		compatible = "renesas,sdhi-r8a7779";
++		compatible = "renesas,sdhi-r8a7779",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4c000 0x100>;
+ 		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
+@@ -364,7 +365,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ffe4d000 {
+-		compatible = "renesas,sdhi-r8a7779";
++		compatible = "renesas,sdhi-r8a7779",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4d000 0x100>;
+ 		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
+@@ -373,7 +375,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ffe4e000 {
+-		compatible = "renesas,sdhi-r8a7779";
++		compatible = "renesas,sdhi-r8a7779",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4e000 0x100>;
+ 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
+@@ -382,7 +385,8 @@
+ 	};
+ 
+ 	sdhi3: sd@ffe4f000 {
+-		compatible = "renesas,sdhi-r8a7779";
++		compatible = "renesas,sdhi-r8a7779",
++			     "renesas,rcar-gen1-sdhi";
+ 		reg = <0xffe4f000 0x100>;
+ 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
+-- 
+2.19.0
+
diff --git a/patches/0680-ARM-dts-r8a7790-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0680-ARM-dts-r8a7790-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..63ba62211ac3a1
--- /dev/null
+++ b/patches/0680-ARM-dts-r8a7790-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,67 @@
+From a39bf642a1a2accefe9f6d47d711045ea559a47d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:55 +0200
+Subject: [PATCH 0680/1795] ARM: dts: r8a7790: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7790 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e0ac55614d1013efcd46e018612a7a11ea79f1c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 55fc267bc59d..5477a62f4642 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -662,7 +662,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 314>;
+@@ -676,7 +677,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ee120000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee120000 0 0x328>;
+ 		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 313>;
+@@ -690,7 +692,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 312>;
+@@ -704,7 +707,8 @@
+ 	};
+ 
+ 	sdhi3: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7790";
++		compatible = "renesas,sdhi-r8a7790",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0681-ARM-dts-r8a7791-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0681-ARM-dts-r8a7791-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..7e6c91eb93843e
--- /dev/null
+++ b/patches/0681-ARM-dts-r8a7791-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From efc8dd0c7c03c05cf8c5248cf0f50df6173b90d4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:56 +0200
+Subject: [PATCH 0681/1795] ARM: dts: r8a7791: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7791 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8423f640cfff6a32f95983e4e60795f77369dca2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 9815a933e4cc..e888b5b0e135 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -612,7 +612,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7791";
++		compatible = "renesas,sdhi-r8a7791",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 314>;
+@@ -626,7 +627,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7791";
++		compatible = "renesas,sdhi-r8a7791",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 312>;
+@@ -640,7 +642,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7791";
++		compatible = "renesas,sdhi-r8a7791",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0682-ARM-dts-r8a7792-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0682-ARM-dts-r8a7792-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..5e6e5837651555
--- /dev/null
+++ b/patches/0682-ARM-dts-r8a7792-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,37 @@
+From dbf894ac8f7e83eb1c68f3bcb5026cc8731c7c3b Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:57 +0200
+Subject: [PATCH 0682/1795] ARM: dts: r8a7792: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7792 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 40fcacbe2f6c7a7efea9be683e62bde34afe7c13)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 3d080e07374c..ac05fdb91798 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -507,7 +507,8 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7792";
++			compatible = "renesas,sdhi-r8a7792",
++				     "renesas,rcar-gen2-sdhi";
+ 			reg = <0 0xee100000 0 0x328>;
+ 			interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-- 
+2.19.0
+
diff --git a/patches/0683-ARM-dts-r8a7793-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0683-ARM-dts-r8a7793-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..e5ff352f1a0742
--- /dev/null
+++ b/patches/0683-ARM-dts-r8a7793-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From f5a9cbb9ab1d59251c1bdd17271d309273c4e0fa Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:58 +0200
+Subject: [PATCH 0683/1795] ARM: dts: r8a7793: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7793 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 21b997ea9dcabe7af05eb0c7272955f95b473452)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index cdc59da5d4d8..f3aeed4f6656 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -562,7 +562,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7793";
++		compatible = "renesas,sdhi-r8a7793",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 314>;
+@@ -576,7 +577,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7793";
++		compatible = "renesas,sdhi-r8a7793",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 312>;
+@@ -590,7 +592,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7793";
++		compatible = "renesas,sdhi-r8a7793",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0684-ARM-dts-r8a7794-Use-R-Car-SDHI-Gen2-fallback-compat-.patch b/patches/0684-ARM-dts-r8a7794-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
new file mode 100644
index 00000000000000..3957da11df9e03
--- /dev/null
+++ b/patches/0684-ARM-dts-r8a7794-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
@@ -0,0 +1,57 @@
+From e420f5a8ff1a90202622fa7abfd7769e7b4ca95f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 17 Oct 2017 08:09:59 +0200
+Subject: [PATCH 0684/1795] ARM: dts: r8a7794: Use R-Car SDHI Gen2 fallback
+ compat string
+
+Use newly added R-Car SDHI Gen2 fallback compat string
+in the DT of the r8a7794 SoC.
+
+This should have no run-time effect as the driver matches against
+the per-SoC compat string before considering the fallback compat string.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 53b2d8f7e8a18232f513c7bafa90d7fda9b36062)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 6807f6a75acf..ef7fb1d2c3a3 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -792,7 +792,8 @@
+ 	};
+ 
+ 	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7794";
++		compatible = "renesas,sdhi-r8a7794",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee100000 0 0x328>;
+ 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 314>;
+@@ -806,7 +807,8 @@
+ 	};
+ 
+ 	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7794";
++		compatible = "renesas,sdhi-r8a7794",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee140000 0 0x100>;
+ 		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 312>;
+@@ -820,7 +822,8 @@
+ 	};
+ 
+ 	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7794";
++		compatible = "renesas,sdhi-r8a7794",
++			     "renesas,rcar-gen2-sdhi";
+ 		reg = <0 0xee160000 0 0x100>;
+ 		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 311>;
+-- 
+2.19.0
+
diff --git a/patches/0685-ARM-dts-iwg20d-q7-Add-support-for-ttySC3.patch b/patches/0685-ARM-dts-iwg20d-q7-Add-support-for-ttySC3.patch
new file mode 100644
index 00000000000000..694f40cbf5743f
--- /dev/null
+++ b/patches/0685-ARM-dts-iwg20d-q7-Add-support-for-ttySC3.patch
@@ -0,0 +1,58 @@
+From 1207e7ff69e25c53087fb1c80d39e3b5ac34294c Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 9 Oct 2017 10:06:21 +0100
+Subject: [PATCH 0685/1795] ARM: dts: iwg20d-q7: Add support for ttySC3
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 77014a7c654c76e1c0cf82563cc48e07c546461c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index efd8af9242d1..c865499ad2a1 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -11,6 +11,7 @@
+ / {
+ 	aliases {
+ 		serial0 = &scif0;
++		serial3 = &scifb1;
+ 		ethernet0 = &avb;
+ 	};
+ 
+@@ -104,6 +105,11 @@
+ 		function = "scif0";
+ 	};
+ 
++	scifb1_pins: scifb1 {
++		groups = "scifb1_data_d", "scifb1_ctrl";
++		function = "scifb1";
++	};
++
+ 	sdhi1_pins: sd1 {
+ 		groups = "sdhi1_data4", "sdhi1_ctrl";
+ 		function = "sdhi1";
+@@ -134,6 +140,14 @@
+ 	status = "okay";
+ };
+ 
++&scifb1 {
++	pinctrl-0 = <&scifb1_pins>;
++	pinctrl-names = "default";
++
++	uart-has-rtscts;
++	status = "okay";
++};
++
+ &sdhi1 {
+ 	pinctrl-0 = <&sdhi1_pins>;
+ 	pinctrl-1 = <&sdhi1_pins_uhs>;
+-- 
+2.19.0
+
diff --git a/patches/0686-ARM-dts-r8a7745-Add-DU-support.patch b/patches/0686-ARM-dts-r8a7745-Add-DU-support.patch
new file mode 100644
index 00000000000000..c4f03e1e45c982
--- /dev/null
+++ b/patches/0686-ARM-dts-r8a7745-Add-DU-support.patch
@@ -0,0 +1,60 @@
+From 81917c38cddbaf4d4247aa8ab81358ecd9f9dbe9 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 6 Nov 2017 18:26:53 +0000
+Subject: [PATCH 0686/1795] ARM: dts: r8a7745: Add DU support
+
+Add du node to r8a7745 SoC DT. Boards that want to enable the DU
+need to specify the output topology.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5841b8b32b56f8c9a289032614936ce334227c67)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 846c27a00c54..53eb1ce446a4 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -821,6 +821,33 @@
+ 			status = "disabled";
+ 		};
+ 
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7745";
++			reg = <0 0xfeb00000 0 0x40000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb0: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_rgb1: endpoint {
++					};
++				};
++			};
++		};
++
+ 		msiof0: spi@e6e20000 {
+ 			compatible = "renesas,msiof-r8a7745",
+ 				     "renesas,rcar-gen2-msiof";
+-- 
+2.19.0
+
diff --git a/patches/0687-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-HDMI-video-output.patch b/patches/0687-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-HDMI-video-output.patch
new file mode 100644
index 00000000000000..40037379a9db85
--- /dev/null
+++ b/patches/0687-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-HDMI-video-output.patch
@@ -0,0 +1,131 @@
+From c0a0a6a13540e2418fb7b75894886f27743295b2 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 6 Nov 2017 18:26:54 +0000
+Subject: [PATCH 0687/1795] ARM: dts: iwg22d-sodimm-dbhd-ca: Add HDMI video
+ output
+
+This patch enables the HDMI interface found on the expansion board.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 97b94d256d432ba9e1b37f9b21c3b285caf11de6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts     | 85 +++++++++++++++++++
+ 1 file changed, 85 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+index f925388454da..a8a4ec87378d 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+@@ -20,6 +20,38 @@
+ 		serial4 = &scif5;
+ 		serial6 = &hscif2;
+ 	};
++
++	cec_clock: cec-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <12000000>;
++	};
++
++	hdmi-out {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con: endpoint {
++				remote-endpoint = <&adv7511_out>;
++			};
++		};
++	};
++};
++
++&du {
++	pinctrl-0 = <&du0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++
++	ports {
++		port@0 {
++			endpoint {
++				remote-endpoint = <&adv7511_in>;
++			};
++		};
++	};
+ };
+ 
+ &hscif2 {
+@@ -29,12 +61,65 @@
+ 	status = "okay";
+ };
+ 
++&i2c1 {
++	pinctrl-0 = <&i2c1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	hdmi@39 {
++		compatible = "adi,adv7511w";
++		reg = <0x39>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&cec_clock>;
++		clock-names = "cec";
++		pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
++
++		adi,input-depth = <8>;
++		adi,input-colorspace = "rgb";
++		adi,input-clock = "1x";
++		adi,input-style = <1>;
++		adi,input-justification = "evenly";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7511_in: endpoint {
++					remote-endpoint = <&du_out_rgb0>;
++				};
++			};
++
++			port@1 {
++				reg = <1>;
++				adv7511_out: endpoint {
++					remote-endpoint = <&hdmi_con>;
++				};
++			};
++		};
++	};
++};
++
+ &pfc {
++	du0_pins: du0 {
++		groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
++		function = "du0";
++	};
++
+ 	hscif2_pins: hscif2 {
+ 		groups = "hscif2_data";
+ 		function = "hscif2";
+ 	};
+ 
++	i2c1_pins: i2c1 {
++		groups = "i2c1_d";
++		function = "i2c1";
++	};
++
+ 	scif1_pins: scif1 {
+ 		groups = "scif1_data";
+ 		function = "scif1";
+-- 
+2.19.0
+
diff --git a/patches/0688-ARM-dts-r8a7745-Add-CAN-01-SoC-support.patch b/patches/0688-ARM-dts-r8a7745-Add-CAN-01-SoC-support.patch
new file mode 100644
index 00000000000000..653b536662a8ac
--- /dev/null
+++ b/patches/0688-ARM-dts-r8a7745-Add-CAN-01-SoC-support.patch
@@ -0,0 +1,74 @@
+From 6d267fb0fbb3f8209acd826f2adc7dd1940c8f93 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:44 +0000
+Subject: [PATCH 0688/1795] ARM: dts: r8a7745: Add CAN[01] SoC support
+
+Add the definitions for can0 and can1 to the SoC .dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 85d3122659be310c632ef1908532157ce82900ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 53eb1ce446a4..52f13246fc8a 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -1049,6 +1049,34 @@
+ 				#phy-cells = <1>;
+ 			};
+ 		};
++
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7745",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
++
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7745",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+@@ -1066,6 +1094,14 @@
+ 		clock-frequency = <48000000>;
+ 	};
+ 
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0689-ARM-dts-iwg22d-sodimm-Add-can0-support-to-carrier-bo.patch b/patches/0689-ARM-dts-iwg22d-sodimm-Add-can0-support-to-carrier-bo.patch
new file mode 100644
index 00000000000000..8fe9fadfcfd06e
--- /dev/null
+++ b/patches/0689-ARM-dts-iwg22d-sodimm-Add-can0-support-to-carrier-bo.patch
@@ -0,0 +1,52 @@
+From 6142fae48418fea0564d8db5f637cb689909a81f Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:45 +0000
+Subject: [PATCH 0689/1795] ARM: dts: iwg22d-sodimm: Add can0 support to
+ carrier board
+
+This patch enables CAN0 interface exposed through connector J15 on the
+carrier board.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 805a5263f4212e431a44c4a04738022a2498f652)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 80c82aa94c06..39ce7e7101c7 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -59,6 +59,13 @@
+ 	};
+ };
+ 
++&can0 {
++	pinctrl-0 = <&can0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &hscif1 {
+ 	pinctrl-0 = <&hscif1_pins>;
+ 	pinctrl-names = "default";
+@@ -85,6 +92,11 @@
+ 		function = "avb";
+ 	};
+ 
++	can0_pins: can0 {
++		groups = "can0_data";
++		function = "can0";
++	};
++
+ 	hscif1_pins: hscif1 {
+ 		groups = "hscif1_data", "hscif1_ctrl";
+ 		function = "hscif1";
+-- 
+2.19.0
+
diff --git a/patches/0690-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-can1-support-to-HD.patch b/patches/0690-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-can1-support-to-HD.patch
new file mode 100644
index 00000000000000..80c8e4698b4cf4
--- /dev/null
+++ b/patches/0690-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-can1-support-to-HD.patch
@@ -0,0 +1,53 @@
+From 68f5b470343d8b8851c45f5e396ec56f1d321682 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:46 +0000
+Subject: [PATCH 0690/1795] ARM: dts: iwg22d-sodimm-dbhd-ca: Add can1 support
+ to HDMI DB
+
+CAN1 interface is exposed via connector J1 found on the HDMI daughter
+board. This patch enables can1 DT node from within the daughter board
+specific device tree.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d6033e7c6589c74299635eb3d84c56ccac8db5e4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+index a8a4ec87378d..d34de8266ccd 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+@@ -54,6 +54,13 @@
+ 	};
+ };
+ 
++&can1 {
++	pinctrl-0 = <&can1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &hscif2 {
+ 	pinctrl-0 = <&hscif2_pins>;
+ 	pinctrl-names = "default";
+@@ -105,6 +112,11 @@
+ };
+ 
+ &pfc {
++	can1_pins: can1 {
++		groups = "can1_data_b";
++		function = "can1";
++	};
++
+ 	du0_pins: du0 {
+ 		groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+ 		function = "du0";
+-- 
+2.19.0
+
diff --git a/patches/0691-ARM-dts-r8a7743-Add-CAN-01-SoC-support.patch b/patches/0691-ARM-dts-r8a7743-Add-CAN-01-SoC-support.patch
new file mode 100644
index 00000000000000..26c519dcc44c39
--- /dev/null
+++ b/patches/0691-ARM-dts-r8a7743-Add-CAN-01-SoC-support.patch
@@ -0,0 +1,74 @@
+From 8aa1839999b3e2aa88b1ef36e760a8966b692dfe Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:47 +0000
+Subject: [PATCH 0691/1795] ARM: dts: r8a7743: Add CAN[01] SoC support
+
+Add the definitions for can0 and can1 to the SoC .dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6ee6959fb85c3e03ec0674d329dc96c733f51dce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 6aa86b75b80c..12c7b9267fd7 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1067,6 +1067,34 @@
+ 			};
+ 		};
+ 
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7743",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
++
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7743",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
++
+ 		pci0: pci@ee090000 {
+ 			compatible = "renesas,pci-r8a7743",
+ 				     "renesas,pci-rcar-gen2";
+@@ -1153,6 +1181,14 @@
+ 		clock-frequency = <48000000>;
+ 	};
+ 
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0692-ARM-dts-iwg20d-q7-common-Add-can0-support-to-carrier.patch b/patches/0692-ARM-dts-iwg20d-q7-common-Add-can0-support-to-carrier.patch
new file mode 100644
index 00000000000000..60869d8bca0946
--- /dev/null
+++ b/patches/0692-ARM-dts-iwg20d-q7-common-Add-can0-support-to-carrier.patch
@@ -0,0 +1,52 @@
+From b9cc2f04328e1945097db18c5d0efda5426c0927 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 7 Nov 2017 15:10:48 +0000
+Subject: [PATCH 0692/1795] ARM: dts: iwg20d-q7-common: Add can0 support to
+ carrier board
+
+This patch enables CAN0 interface exposed through connector J20 on the
+carrier board.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 47f3c7b66b6d316f86b0ce957c99958da0268e36)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index c865499ad2a1..3e4bc4d6b9d3 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -59,6 +59,13 @@
+ 	};
+ };
+ 
++&can0 {
++	pinctrl-0 = <&can0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
+ &hsusb {
+ 	status = "okay";
+ 	pinctrl-0 = <&usb0_pins>;
+@@ -90,6 +97,11 @@
+ };
+ 
+ &pfc {
++	can0_pins: can0 {
++		groups = "can0_data_d";
++		function = "can0";
++	};
++
+ 	avb_pins: avb {
+ 		groups = "avb_mdio", "avb_gmii";
+ 		function = "avb";
+-- 
+2.19.0
+
diff --git a/patches/0693-ARM-dts-r8a7743-Add-default-PCIe-bus-clock.patch b/patches/0693-ARM-dts-r8a7743-Add-default-PCIe-bus-clock.patch
new file mode 100644
index 00000000000000..23f906250968ff
--- /dev/null
+++ b/patches/0693-ARM-dts-r8a7743-Add-default-PCIe-bus-clock.patch
@@ -0,0 +1,38 @@
+From a1b6a51cde2f52021683814ad3b382db37da852d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 13 Nov 2017 17:43:10 +0000
+Subject: [PATCH 0693/1795] ARM: dts: r8a7743: Add default PCIe bus clock
+
+This patch adds a default PCIe bus clock node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a827886558d4b975903824d9786c331e08c60e9b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 12c7b9267fd7..de4b8c64d56b 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1189,6 +1189,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0694-ARM-dts-r8a7743-Add-PCIe-Controller-device-node.patch b/patches/0694-ARM-dts-r8a7743-Add-PCIe-Controller-device-node.patch
new file mode 100644
index 00000000000000..ecb657f9a38f4f
--- /dev/null
+++ b/patches/0694-ARM-dts-r8a7743-Add-PCIe-Controller-device-node.patch
@@ -0,0 +1,57 @@
+From 155abe9f8a5ce86a749022510ca60958c1f345ef Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 13 Nov 2017 17:43:11 +0000
+Subject: [PATCH 0694/1795] ARM: dts: r8a7743: Add PCIe Controller device node
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4c5c952e61190e5a0e06128156eef84d290a0045)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index de4b8c64d56b..9e26c40976ff 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1164,6 +1164,34 @@
+ 				phy-names = "usb";
+ 			};
+ 		};
++
++		pciec: pcie@fe000000 {
++			compatible = "renesas,pcie-r8a7743",
++				     "renesas,pcie-rcar-gen2";
++			reg = <0 0xfe000000 0 0x80000>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			bus-range = <0x00 0xff>;
++			device_type = "pci";
++			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
++				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
++				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
++				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
++			/* Map all possible DDR as inbound ranges */
++			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
++				      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
++			clock-names = "pcie", "pcie_bus";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 319>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0695-ARM-dts-iwg20d-q7-Enable-PCIe-Controller.patch b/patches/0695-ARM-dts-iwg20d-q7-Enable-PCIe-Controller.patch
new file mode 100644
index 00000000000000..98e43ce6444564
--- /dev/null
+++ b/patches/0695-ARM-dts-iwg20d-q7-Enable-PCIe-Controller.patch
@@ -0,0 +1,39 @@
+From 54e31317d4f0e0659acd8c0592de80efc497294e Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 13 Nov 2017 17:43:12 +0000
+Subject: [PATCH 0695/1795] ARM: dts: iwg20d-q7: Enable PCIe Controller
+
+Enable PCIe Controller & set PCIe bus clock frequency.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b3a0317e312cc6d6359c7a0854d763cde528391d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 3e4bc4d6b9d3..54470c6de891 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -96,6 +96,14 @@
+ 	pinctrl-names = "default";
+ };
+ 
++&pcie_bus_clk {
++	clock-frequency = <100000000>;
++};
++
++&pciec {
++	status = "okay";
++};
++
+ &pfc {
+ 	can0_pins: can0 {
+ 		groups = "can0_data_d";
+-- 
+2.19.0
+
diff --git a/patches/0696-ARM-dts-r8a7743-add-VIN-dt-support.patch b/patches/0696-ARM-dts-r8a7743-add-VIN-dt-support.patch
new file mode 100644
index 00000000000000..b418f25882a0de
--- /dev/null
+++ b/patches/0696-ARM-dts-r8a7743-add-VIN-dt-support.patch
@@ -0,0 +1,74 @@
+From 8ad032894f8e6e771f1c5c9ff7eb60063c3377e1 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 16 Nov 2017 18:22:50 +0000
+Subject: [PATCH 0696/1795] ARM: dts: r8a7743: add VIN dt support
+
+Add VIN[012] support to SoC dt. Also, add aliases.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 001b32ae64dbf780d89fbc258c3f1007ee7b34e8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 9e26c40976ff..c09c6672ca37 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -32,6 +32,9 @@
+ 		spi1 = &msiof0;
+ 		spi2 = &msiof1;
+ 		spi3 = &msiof2;
++		vin0 = &vin0;
++		vin1 = &vin1;
++		vin2 = &vin2;
+ 	};
+ 
+ 	cpus {
+@@ -1037,6 +1040,39 @@
+ 			};
+ 		};
+ 
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7743",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7743",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
++		};
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7743",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			status = "disabled";
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7743";
+ 			reg = <0 0xfeb00000 0 0x40000>,
+-- 
+2.19.0
+
diff --git a/patches/0697-ARM-dts-r8a7745-add-VIN-dt-support.patch b/patches/0697-ARM-dts-r8a7745-add-VIN-dt-support.patch
new file mode 100644
index 00000000000000..dddff08b2f49d3
--- /dev/null
+++ b/patches/0697-ARM-dts-r8a7745-add-VIN-dt-support.patch
@@ -0,0 +1,62 @@
+From da4bfad076cb557e72978816f51167505ec42931 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 16 Nov 2017 18:22:51 +0000
+Subject: [PATCH 0697/1795] ARM: dts: r8a7745: add VIN dt support
+
+Add VIN[01] support to SoC dt. Also, add aliases.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1a20f21899e7ae886675874b5b5fb03eb43ea69b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 52f13246fc8a..de13e156f071 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -31,6 +31,8 @@
+ 		spi1 = &msiof0;
+ 		spi2 = &msiof1;
+ 		spi3 = &msiof2;
++		vin0 = &vin0;
++		vin1 = &vin1;
+ 	};
+ 
+ 	cpus {
+@@ -821,6 +823,28 @@
+ 			status = "disabled";
+ 		};
+ 
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7745",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7745",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7745";
+ 			reg = <0 0xfeb00000 0 0x40000>;
+-- 
+2.19.0
+
diff --git a/patches/0698-ARM-dts-koelsch-Correct-primary-compatible-value-for.patch b/patches/0698-ARM-dts-koelsch-Correct-primary-compatible-value-for.patch
new file mode 100644
index 00000000000000..523ec6a5594281
--- /dev/null
+++ b/patches/0698-ARM-dts-koelsch-Correct-primary-compatible-value-for.patch
@@ -0,0 +1,37 @@
+From 0137de90ed9c0aad522d8386f87a740f2487afad Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:51:35 +0100
+Subject: [PATCH 0698/1795] ARM: dts: koelsch: Correct primary compatible value
+ for eeprom
+
+The Renesas part number of the two-wire serial interface EEPROM is not
+24C02, but R1EX24002ATAS0G.
+
+Hence change its primary compatible value to "renesas,r1ex24002", like
+on Gose.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8834d8667b8509e5968e5689790c4ac5410b47db)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index 4126de417922..fac9cdea4965 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -708,7 +708,7 @@
+ 	};
+ 
+ 	eeprom@50 {
+-		compatible = "renesas,24c02", "atmel,24c02";
++		compatible = "renesas,r1ex24002", "atmel,24c02";
+ 		reg = <0x50>;
+ 		pagesize = <16>;
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0699-ARM-dts-genmai-Correct-primary-compatible-value-for-.patch b/patches/0699-ARM-dts-genmai-Correct-primary-compatible-value-for-.patch
new file mode 100644
index 00000000000000..6b87a9a6654a10
--- /dev/null
+++ b/patches/0699-ARM-dts-genmai-Correct-primary-compatible-value-for-.patch
@@ -0,0 +1,36 @@
+From 0a9f07a35b9d371c9cbd3cb5b6a6242c37ad3310 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 16 Nov 2017 14:51:36 +0100
+Subject: [PATCH 0699/1795] ARM: dts: genmai: Correct primary compatible value
+ for eeprom
+
+The Renesas part number of the two-wire serial interface EEPROM is not
+24C128, but R1EX24128ASA00A.
+
+Hence change its primary compatible value to "renesas,r1ex24128".
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8edeee392f5971054bfbad43715d0c0d077e13bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100-genmai.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
+index cd4d5ff7749e..5af2a0116ff2 100644
+--- a/arch/arm/boot/dts/r7s72100-genmai.dts
++++ b/arch/arm/boot/dts/r7s72100-genmai.dts
+@@ -123,7 +123,7 @@
+ 	pinctrl-0 = <&i2c2_pins>;
+ 
+ 	eeprom@50 {
+-		compatible = "renesas,24c128", "atmel,24c128";
++		compatible = "renesas,r1ex24128", "atmel,24c128";
+ 		reg = <0x50>;
+ 		pagesize = <64>;
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0700-ARM-dts-r8a7794-Add-SMP-support.patch b/patches/0700-ARM-dts-r8a7794-Add-SMP-support.patch
new file mode 100644
index 00000000000000..41487529073eef
--- /dev/null
+++ b/patches/0700-ARM-dts-r8a7794-Add-SMP-support.patch
@@ -0,0 +1,48 @@
+From 489cc07033a789486d86a1b6038526186ae6a715 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 28 Nov 2017 14:39:01 +0100
+Subject: [PATCH 0700/1795] ARM: dts: r8a7794: Add SMP support
+
+Add the device tree node for the Advanced Power Management Unit (APMU).
+Use the "enable-method" prop to  point out that the APMU should be used
+for the SMP support.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 655b9ff016149fd3a438f4205187c9de8a9c5b48)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index ef7fb1d2c3a3..2437598ca2f5 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -37,6 +37,7 @@
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
++		enable-method = "renesas,apmu";
+ 
+ 		cpu0: cpu@0 {
+ 			device_type = "cpu";
+@@ -66,6 +67,12 @@
+ 		};
+ 	};
+ 
++	apmu@e6151000 {
++		compatible = "renesas,r8a7794-apmu", "renesas,apmu";
++		reg = <0 0xe6151000 0 0x188>;
++		cpus = <&cpu0 &cpu1>;
++	};
++
+ 	gic: interrupt-controller@f1001000 {
+ 		compatible = "arm,gic-400";
+ 		#interrupt-cells = <3>;
+-- 
+2.19.0
+
diff --git a/patches/0701-ARM-dts-r8a73a4-Update-CMT-compat-string.patch b/patches/0701-ARM-dts-r8a73a4-Update-CMT-compat-string.patch
new file mode 100644
index 00000000000000..191e566266cd15
--- /dev/null
+++ b/patches/0701-ARM-dts-r8a73a4-Update-CMT-compat-string.patch
@@ -0,0 +1,37 @@
+From 3f143d7e88bd72a9a736e95a3ece53709a41cdc4 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:25 +0100
+Subject: [PATCH 0701/1795] ARM: dts: r8a73a4: Update CMT compat string
+
+Use the recently updated r8a73a4 CMT1 compat string.
+
+With this change in place we can keep device-specific configuration in
+the driver and the driver can be able to support CMT1 specific features.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 86656e9cc618c14d44f722786c568d1236211364)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
+index dd4d09712a2a..805b0fd70f53 100644
+--- a/arch/arm/boot/dts/r8a73a4.dtsi
++++ b/arch/arm/boot/dts/r8a73a4.dtsi
+@@ -132,7 +132,7 @@
+ 	};
+ 
+ 	cmt1: timer@e6130000 {
+-		compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
+ 		reg = <0 0xe6130000 0 0x1004>;
+ 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
+-- 
+2.19.0
+
diff --git a/patches/0702-ARM-dts-r8a7790-Update-CMT-compat-strings.patch b/patches/0702-ARM-dts-r8a7790-Update-CMT-compat-strings.patch
new file mode 100644
index 00000000000000..5c6b8bf757db54
--- /dev/null
+++ b/patches/0702-ARM-dts-r8a7790-Update-CMT-compat-strings.patch
@@ -0,0 +1,46 @@
+From 92651eb75fb1c362d814ad44e8d8fcd4b3433a87 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:26 +0100
+Subject: [PATCH 0702/1795] ARM: dts: r8a7790: Update CMT compat strings
+
+Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
+
+With this change in place we can keep device-specific configuration in
+the driver and the driver can be able to support CMT1 specific features.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a7f7c96c6c5c7cc9b4e28467814068ad8b32cf9c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 5477a62f4642..696522da2f99 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -311,7 +311,7 @@
+ 	};
+ 
+ 	cmt0: timer@ffca0000 {
+-		compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+@@ -326,7 +326,7 @@
+ 	};
+ 
+ 	cmt1: timer@e6130000 {
+-		compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
+ 		reg = <0 0xe6130000 0 0x1004>;
+ 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0703-ARM-dts-r8a7791-Update-CMT-compat-strings.patch b/patches/0703-ARM-dts-r8a7791-Update-CMT-compat-strings.patch
new file mode 100644
index 00000000000000..4b0f75289dc8dc
--- /dev/null
+++ b/patches/0703-ARM-dts-r8a7791-Update-CMT-compat-strings.patch
@@ -0,0 +1,46 @@
+From 35b00ef1bf37c4c27f19b71002d6ad00775dd455 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:27 +0100
+Subject: [PATCH 0703/1795] ARM: dts: r8a7791: Update CMT compat strings
+
+Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
+
+With this change in place we can keep device-specific configuration in
+the driver and the driver can be able to support CMT1 specific features.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bf50e0ab4f5062bb9d4bb5dcb81a6673ea7e2473)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index e888b5b0e135..a69d6f883b34 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -257,7 +257,7 @@
+ 	};
+ 
+ 	cmt0: timer@ffca0000 {
+-		compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+@@ -272,7 +272,7 @@
+ 	};
+ 
+ 	cmt1: timer@e6130000 {
+-		compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
+ 		reg = <0 0xe6130000 0 0x1004>;
+ 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0704-ARM-dts-r8a7793-Update-CMT-compat-strings.patch b/patches/0704-ARM-dts-r8a7793-Update-CMT-compat-strings.patch
new file mode 100644
index 00000000000000..135f07a7638a8a
--- /dev/null
+++ b/patches/0704-ARM-dts-r8a7793-Update-CMT-compat-strings.patch
@@ -0,0 +1,46 @@
+From bde8ce264f82409c2f898731a2fc6d587b84773e Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:28 +0100
+Subject: [PATCH 0704/1795] ARM: dts: r8a7793: Update CMT compat strings
+
+Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
+
+With this change in place we can keep device-specific configuration in
+the driver and the driver can be able to support CMT1 specific features.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3a4c5d6a8cb0ca0081fe4f1e69df7779075d6fd6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index f3aeed4f6656..035b5a7639bc 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -248,7 +248,7 @@
+ 	};
+ 
+ 	cmt0: timer@ffca0000 {
+-		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+@@ -263,7 +263,7 @@
+ 	};
+ 
+ 	cmt1: timer@e6130000 {
+-		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
+ 		reg = <0 0xe6130000 0 0x1004>;
+ 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0705-ARM-dts-r8a7794-Update-CMT-compat-strings.patch b/patches/0705-ARM-dts-r8a7794-Update-CMT-compat-strings.patch
new file mode 100644
index 00000000000000..05b33098dc0315
--- /dev/null
+++ b/patches/0705-ARM-dts-r8a7794-Update-CMT-compat-strings.patch
@@ -0,0 +1,46 @@
+From 2054fd5404b681bc91962e4ed7d0a0514490f0e7 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:29 +0100
+Subject: [PATCH 0705/1795] ARM: dts: r8a7794: Update CMT compat strings
+
+Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
+
+With this change in place we can keep device-specific configuration in
+the driver and the driver can be able to support CMT1 specific features.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 98b6b8b493a99d828e6665e6e67d6ca077c1aee0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 2437598ca2f5..c141c9198b3a 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -188,7 +188,7 @@
+ 	};
+ 
+ 	cmt0: timer@ffca0000 {
+-		compatible = "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
+ 		reg = <0 0xffca0000 0 0x1004>;
+ 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+@@ -203,7 +203,7 @@
+ 	};
+ 
+ 	cmt1: timer@e6130000 {
+-		compatible = "renesas,cmt-48-gen2";
++		compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
+ 		reg = <0 0xe6130000 0 0x1004>;
+ 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0706-ARM-dts-r8a73a4-Remove-CMT-renesas-channels-mask.patch b/patches/0706-ARM-dts-r8a73a4-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..c60d7111e60a85
--- /dev/null
+++ b/patches/0706-ARM-dts-r8a73a4-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,38 @@
+From 91a4b0372e93fea27c5320b66ff3f5b56789a3e1 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:30 +0100
+Subject: [PATCH 0706/1795] ARM: dts: r8a73a4: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 287883993e3e98579bdaa92ce6136a9d25ce0be9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a73a4.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
+index 805b0fd70f53..8e48090e4fdc 100644
+--- a/arch/arm/boot/dts/r8a73a4.dtsi
++++ b/arch/arm/boot/dts/r8a73a4.dtsi
+@@ -138,9 +138,6 @@
+ 		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
+ 		clock-names = "fck";
+ 		power-domains = <&pd_c5>;
+-
+-		renesas,channels-mask = <0xff>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0707-ARM-dts-r8a7740-Remove-CMT-renesas-channels-mask.patch b/patches/0707-ARM-dts-r8a7740-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..8cd249313f6984
--- /dev/null
+++ b/patches/0707-ARM-dts-r8a7740-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,38 @@
+From e89e07b58bfba5fadd4f4645a5c5348c56f8349d Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:31 +0100
+Subject: [PATCH 0707/1795] ARM: dts: r8a7740: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 33a616cc7c8b8cb68c2922eee9a8fff5d8b1962f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7740.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
+index d37d22682a63..95c408b11991 100644
+--- a/arch/arm/boot/dts/r8a7740.dtsi
++++ b/arch/arm/boot/dts/r8a7740.dtsi
+@@ -74,9 +74,6 @@
+ 		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
+ 		clock-names = "fck";
+ 		power-domains = <&pd_c5>;
+-
+-		renesas,channels-mask = <0x3f>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0708-ARM-dts-r8a7790-Remove-CMT-renesas-channels-mask.patch b/patches/0708-ARM-dts-r8a7790-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..95e021238a810d
--- /dev/null
+++ b/patches/0708-ARM-dts-r8a7790-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,46 @@
+From 6cf95d79e33fd874087ae2ab70441252ba5093aa Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:32 +0100
+Subject: [PATCH 0708/1795] ARM: dts: r8a7790: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b5c3dacdd90608c96db5daa74665a60333adfe82)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 696522da2f99..450bfc0e9796 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -320,8 +320,6 @@
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 124>;
+ 
+-		renesas,channels-mask = <0x60>;
+-
+ 		status = "disabled";
+ 	};
+ 
+@@ -341,8 +339,6 @@
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 329>;
+ 
+-		renesas,channels-mask = <0xff>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0709-ARM-dts-r8a7791-Remove-CMT-renesas-channels-mask.patch b/patches/0709-ARM-dts-r8a7791-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..cb47b65e9d8101
--- /dev/null
+++ b/patches/0709-ARM-dts-r8a7791-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,46 @@
+From d43bce8066c60923bf1c7cdf69852fc2ece8323d Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:33 +0100
+Subject: [PATCH 0709/1795] ARM: dts: r8a7791: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d3fb90537855bb7f27d6256446197675ffb4a1bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index a69d6f883b34..dfc1c406179f 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -266,8 +266,6 @@
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		resets = <&cpg 124>;
+ 
+-		renesas,channels-mask = <0x60>;
+-
+ 		status = "disabled";
+ 	};
+ 
+@@ -287,8 +285,6 @@
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ 		resets = <&cpg 329>;
+ 
+-		renesas,channels-mask = <0xff>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0710-ARM-dts-r8a7793-Remove-CMT-renesas-channels-mask.patch b/patches/0710-ARM-dts-r8a7793-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..841ad5f42247f1
--- /dev/null
+++ b/patches/0710-ARM-dts-r8a7793-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,46 @@
+From 5ef64d7a1880d84b44c55d39d3f42151791cdeb3 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:34 +0100
+Subject: [PATCH 0710/1795] ARM: dts: r8a7793: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5fdbea7147da1ad43b97c43d685b30d0e6b92d0a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 035b5a7639bc..61dd291d907d 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -257,8 +257,6 @@
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		resets = <&cpg 124>;
+ 
+-		renesas,channels-mask = <0x60>;
+-
+ 		status = "disabled";
+ 	};
+ 
+@@ -278,8 +276,6 @@
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 		resets = <&cpg 329>;
+ 
+-		renesas,channels-mask = <0xff>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0711-ARM-dts-r8a7794-Remove-CMT-renesas-channels-mask.patch b/patches/0711-ARM-dts-r8a7794-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..55a282f90decac
--- /dev/null
+++ b/patches/0711-ARM-dts-r8a7794-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,46 @@
+From 91f49dd9a11857b93e5e4fe7b392c7020680f1ec Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:35 +0100
+Subject: [PATCH 0711/1795] ARM: dts: r8a7794: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bc28e52b4d5ec51d9bde87838a1ab1673807536c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index c141c9198b3a..106b4e1649ff 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -197,8 +197,6 @@
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		resets = <&cpg 124>;
+ 
+-		renesas,channels-mask = <0x60>;
+-
+ 		status = "disabled";
+ 	};
+ 
+@@ -218,8 +216,6 @@
+ 		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ 		resets = <&cpg 329>;
+ 
+-		renesas,channels-mask = <0xff>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0712-ARM-dts-sh73a0-Remove-CMT-renesas-channels-mask.patch b/patches/0712-ARM-dts-sh73a0-Remove-CMT-renesas-channels-mask.patch
new file mode 100644
index 00000000000000..203419acf8f0d7
--- /dev/null
+++ b/patches/0712-ARM-dts-sh73a0-Remove-CMT-renesas-channels-mask.patch
@@ -0,0 +1,38 @@
+From 0bcb029691347e4a025456952a843faa01c2525a Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 28 Nov 2017 14:47:36 +0100
+Subject: [PATCH 0712/1795] ARM: dts: sh73a0: Remove CMT renesas,channels-mask
+
+Update the DTS to remove the now deprecated "renesas,channels-mask"
+property.
+
+The channel information is now kept in the device driver and can easily
+be determined based on the compat string.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 206f477ec546865b32d1c498dadb45f1237673a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/sh73a0.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
+index 52e63075fdb4..b0c20544df20 100644
+--- a/arch/arm/boot/dts/sh73a0.dtsi
++++ b/arch/arm/boot/dts/sh73a0.dtsi
+@@ -101,9 +101,6 @@
+ 		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
+ 		clock-names = "fck";
+ 		power-domains = <&pd_c5>;
+-
+-		renesas,channels-mask = <0x3f>;
+-
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0713-ARM-dts-armadillo800eva-Convert-to-named-i2c-gpio-bi.patch b/patches/0713-ARM-dts-armadillo800eva-Convert-to-named-i2c-gpio-bi.patch
new file mode 100644
index 00000000000000..2a7fba0760f3fd
--- /dev/null
+++ b/patches/0713-ARM-dts-armadillo800eva-Convert-to-named-i2c-gpio-bi.patch
@@ -0,0 +1,48 @@
+From 44bda3439740db2707016761cfe77d88c77258e9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 13:57:23 +0100
+Subject: [PATCH 0713/1795] ARM: dts: armadillo800eva: Convert to named
+ i2c-gpio bindings
+
+Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
+named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
+gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
+more error-prone unnamed variant.
+
+Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
+flags, which were implicitly assumed before.
+
+The latter gets rid of the message:
+
+    gpio-208 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
+    gpio-91 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4f1cfdc250900e275a3f2341d57ba1c7ce41188a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+index 1788e186a512..03b00d87b39b 100644
+--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
++++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+@@ -131,9 +131,8 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+-		gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
+-			 &pfc 91 GPIO_ACTIVE_HIGH /* scl */
+-			>;
++		sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0714-ARM-dts-lager-Convert-to-named-i2c-gpio-bindings.patch b/patches/0714-ARM-dts-lager-Convert-to-named-i2c-gpio-bindings.patch
new file mode 100644
index 00000000000000..86516cd9198597
--- /dev/null
+++ b/patches/0714-ARM-dts-lager-Convert-to-named-i2c-gpio-bindings.patch
@@ -0,0 +1,42 @@
+From 2a51095cae7f24051a86db68d264fd0ba7504076 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 13:57:24 +0100
+Subject: [PATCH 0714/1795] ARM: dts: lager: Convert to named i2c-gpio bindings
+
+Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
+named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
+gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
+more error-prone unnamed variant.
+
+Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
+flags, which were implicitly assumed before.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e99185b298ba0288e88ea0a935342f01c8387b76)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index e3d27783b6b5..f2ea632381e7 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -272,9 +272,8 @@
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
+-			 &gpio1 16 GPIO_ACTIVE_HIGH /* scl */
+-			>;
++		sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0715-ARM-dts-koelsch-Convert-to-named-i2c-gpio-bindings.patch b/patches/0715-ARM-dts-koelsch-Convert-to-named-i2c-gpio-bindings.patch
new file mode 100644
index 00000000000000..7184da22799d06
--- /dev/null
+++ b/patches/0715-ARM-dts-koelsch-Convert-to-named-i2c-gpio-bindings.patch
@@ -0,0 +1,43 @@
+From 3b59655115cfcf717be24df6fbd68f2bfe3127b8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 13:57:25 +0100
+Subject: [PATCH 0715/1795] ARM: dts: koelsch: Convert to named i2c-gpio
+ bindings
+
+Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
+named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
+gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
+more error-prone unnamed variant.
+
+Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
+flags, which were implicitly assumed before.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c14f3ec4ebb0c685b5261380559782caa76bd161)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index fac9cdea4965..a50924d12b6f 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -312,9 +312,8 @@
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
+-			 &gpio7 15 GPIO_ACTIVE_HIGH /* scl */
+-			>;
++		sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0716-ARM-dts-alt-Convert-to-named-i2c-gpio-bindings.patch b/patches/0716-ARM-dts-alt-Convert-to-named-i2c-gpio-bindings.patch
new file mode 100644
index 00000000000000..65aa301537dbee
--- /dev/null
+++ b/patches/0716-ARM-dts-alt-Convert-to-named-i2c-gpio-bindings.patch
@@ -0,0 +1,42 @@
+From 97c0aa1141398396390283932bdef4f2f26b50fb Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 30 Nov 2017 13:57:26 +0100
+Subject: [PATCH 0716/1795] ARM: dts: alt: Convert to named i2c-gpio bindings
+
+Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
+named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
+gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
+more error-prone unnamed variant.
+
+Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
+flags, which were implicitly assumed before.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7f32eddb81ecc06131a643babe2d0f961fbd7f08)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index bd98790d964e..60c6515c4996 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -143,9 +143,8 @@
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
+-			 &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
+-			>;
++		sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0717-ARM-dts-r8a7745-Add-APMU-node-and-second-CPU-core.patch b/patches/0717-ARM-dts-r8a7745-Add-APMU-node-and-second-CPU-core.patch
new file mode 100644
index 00000000000000..e323426aa978e5
--- /dev/null
+++ b/patches/0717-ARM-dts-r8a7745-Add-APMU-node-and-second-CPU-core.patch
@@ -0,0 +1,65 @@
+From 287f5e6cf3e65bd09d87c96e0bb5e499288e4da1 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 6 Dec 2017 12:05:29 +0000
+Subject: [PATCH 0717/1795] ARM: dts: r8a7745: Add APMU node and second CPU
+ core
+
+Add DT node for the Advanced Power Management Unit (APMU), add the
+second CPU core, and use "renesas,apmu" as "enable-method".
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aaca1ff0dbfcb341c453abf160511d3419545431)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index de13e156f071..0fa78612746f 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -38,6 +38,7 @@
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
++		enable-method = "renesas,apmu";
+ 
+ 		cpu0: cpu@0 {
+ 			device_type = "cpu";
+@@ -49,6 +50,15 @@
+ 			next-level-cache = <&L2_CA7>;
+ 		};
+ 
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <1>;
++			clock-frequency = <1000000000>;
++			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
++			next-level-cache = <&L2_CA7>;
++		};
++
+ 		L2_CA7: cache-controller-0 {
+ 			compatible = "cache";
+ 			cache-unified;
+@@ -65,6 +75,12 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		apmu@e6151000 {
++			compatible = "renesas,r8a7745-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
++
+ 		gic: interrupt-controller@f1001000 {
+ 			compatible = "arm,gic-400";
+ 			#interrupt-cells = <3>;
+-- 
+2.19.0
+
diff --git a/patches/0718-ARM-shmobile-defconfig-Enable-SGTL5000-audio-codec.patch b/patches/0718-ARM-shmobile-defconfig-Enable-SGTL5000-audio-codec.patch
new file mode 100644
index 00000000000000..5a2f6beddbcc7e
--- /dev/null
+++ b/patches/0718-ARM-shmobile-defconfig-Enable-SGTL5000-audio-codec.patch
@@ -0,0 +1,36 @@
+From 3db0eacc7d4486787ad12eddf2176edd052c95a5 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:25:07 +0000
+Subject: [PATCH 0718/1795] ARM: shmobile: defconfig: Enable SGTL5000 audio
+ codec
+
+The iWave RZ/G1M Q7 carrier board supports I2S audio codec "SGTL5000".
+
+To increase hardware support enable the driver in the shmobile_defconfig
+multiplatform configuration.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 66d7b080aade3be61f7b41de800215c85a8d3593)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index 7b4fc0143148..d60dbe1f108f 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -173,6 +173,7 @@ CONFIG_SND_SOC=y
+ CONFIG_SND_SOC_SH4_FSI=y
+ CONFIG_SND_SOC_RCAR=y
+ CONFIG_SND_SOC_AK4642=y
++CONFIG_SND_SOC_SGTL5000=y
+ CONFIG_SND_SOC_WM8978=y
+ CONFIG_SND_SIMPLE_SCU_CARD=y
+ CONFIG_USB=y
+-- 
+2.19.0
+
diff --git a/patches/0719-ARM-dts-r8a7743-Add-audio-clocks.patch b/patches/0719-ARM-dts-r8a7743-Add-audio-clocks.patch
new file mode 100644
index 00000000000000..036ae720a39c6e
--- /dev/null
+++ b/patches/0719-ARM-dts-r8a7743-Add-audio-clocks.patch
@@ -0,0 +1,55 @@
+From dd538cb6fbcc1a3138230ec104827297a7f3edd6 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:25:08 +0000
+Subject: [PATCH 0719/1795] ARM: dts: r8a7743: Add audio clocks
+
+Describe the external audio clocks required by the sound driver.
+Boards that provide audio clocks need to override the clock frequencies.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f27244593782059ad9e4d176006814609f4abfa1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index c09c6672ca37..2f0ec9d64b1d 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1238,6 +1238,29 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0720-ARM-dts-r8a7743-Add-audio-DMAC-support.patch b/patches/0720-ARM-dts-r8a7743-Add-audio-DMAC-support.patch
new file mode 100644
index 00000000000000..0352ad59a0210c
--- /dev/null
+++ b/patches/0720-ARM-dts-r8a7743-Add-audio-DMAC-support.patch
@@ -0,0 +1,93 @@
+From d04714d2b0beef143a46e47136e646e62c916897 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:25:09 +0000
+Subject: [PATCH 0720/1795] ARM: dts: r8a7743: Add audio DMAC support
+
+Instantiate the two audio DMA controllers on the r8a7743 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1a86529ed8bc982c690a540ab472cd5a2d93c6cb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 62 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 2f0ec9d64b1d..b60527a2ffac 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -359,6 +359,68 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
+ 		usb_dmac0: dma-controller@e65a0000 {
+ 			compatible = "renesas,r8a7743-usb-dmac",
+ 				     "renesas,usb-dmac";
+-- 
+2.19.0
+
diff --git a/patches/0721-ARM-dts-r8a7743-Add-sound-support.patch b/patches/0721-ARM-dts-r8a7743-Add-sound-support.patch
new file mode 100644
index 00000000000000..e12087c29b5c1c
--- /dev/null
+++ b/patches/0721-ARM-dts-r8a7743-Add-sound-support.patch
@@ -0,0 +1,218 @@
+From 0df60823163a355a4d990d88b331429bcdd92757 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:25:10 +0000
+Subject: [PATCH 0721/1795] ARM: dts: r8a7743: Add sound support
+
+Define the generic r8a7743(RZ/G1M) part of  the sound device node.
+
+This patch is based on the r8a7791 sound work by Kuninori Morimoto.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit de812613376a202d70c8ce37211044a29aae33b2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 185 +++++++++++++++++++++++++++++++++
+ 1 file changed, 185 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index b60527a2ffac..59860c8ef362 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1290,6 +1290,191 @@
+ 			resets = <&cpg 319>;
+ 			status = "disabled";
+ 		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7743",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++				 <&cpg CPG_CORE R8A7743_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++				      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
++				      "src.9", "src.8", "src.7", "src.6", "src.5",
++				      "src.4", "src.3", "src.2", "src.1", "src.0",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
++				      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma1 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma1 0xbe>;
++					dma-names = "tx";
++				};
++			};
++
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
++
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
++
++			rcar_sound,src {
++				src0: src-0 {
++					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x85>, <&audma1 0x9a>;
++					dma-names = "rx", "tx";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma1 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma1 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma1 0xb4>;
++					dma-names = "rx", "tx";
++				};
++				src7: src-7 {
++					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x93>, <&audma1 0xb6>;
++					dma-names = "rx", "tx";
++				};
++				src8: src-8 {
++					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x95>, <&audma1 0xb8>;
++					dma-names = "rx", "tx";
++				};
++				src9: src-9 {
++					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x97>, <&audma1 0xba>;
++					dma-names = "rx", "tx";
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++			};
++		};
+ 	};
+ 
+ 	/* External root clock */
+-- 
+2.19.0
+
diff --git a/patches/0722-ARM-dts-r8a7790-Correct-critical-CPU-temperature.patch b/patches/0722-ARM-dts-r8a7790-Correct-critical-CPU-temperature.patch
new file mode 100644
index 00000000000000..cc344b24259af7
--- /dev/null
+++ b/patches/0722-ARM-dts-r8a7790-Correct-critical-CPU-temperature.patch
@@ -0,0 +1,42 @@
+From f2b4f11fdb54eade32efb266d03073750ed9aa4e Mon Sep 17 00:00:00 2001
+From: Chris Paterson <chris.paterson2@renesas.com>
+Date: Thu, 14 Dec 2017 09:08:39 +0000
+Subject: [PATCH 0722/1795] ARM: dts: r8a7790: Correct critical CPU temperature
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The R-Car H2 hardware manual states that Tc = –40°C to +105°C. The
+thermal sensor has an accuracy of ±5°C and there can be a temperature
+difference of 1 or 2 degrees between Tjmax and the thermal sensor due
+to the location of the latter.
+
+This means that 95°C is a safer value to use.
+
+Fixes: a8b805f3606f7af7 ("ARM: dts: r8a7790: enable to use thermal-zone")
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fcab5651fae4258a993170b7aaf443adbd3d4d84)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 450bfc0e9796..ed9a68538a55 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -168,7 +168,7 @@
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <115000>;
++					temperature	= <95000>;
+ 					hysteresis	= <0>;
+ 					type		= "critical";
+ 				};
+-- 
+2.19.0
+
diff --git a/patches/0723-ARM-dts-r8a7791-Correct-critical-CPU-temperature.patch b/patches/0723-ARM-dts-r8a7791-Correct-critical-CPU-temperature.patch
new file mode 100644
index 00000000000000..9bc66240e09802
--- /dev/null
+++ b/patches/0723-ARM-dts-r8a7791-Correct-critical-CPU-temperature.patch
@@ -0,0 +1,42 @@
+From 41b7dbfd9d2dfc36ad681d500d3628d8a88d29a2 Mon Sep 17 00:00:00 2001
+From: Chris Paterson <chris.paterson2@renesas.com>
+Date: Thu, 14 Dec 2017 09:08:40 +0000
+Subject: [PATCH 0723/1795] ARM: dts: r8a7791: Correct critical CPU temperature
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The R-Car M2W hardware manual states that Tc = –40°C to +105°C. The
+thermal sensor has an accuracy of ±5°C and there can be a temperature
+difference of 1 or 2 degrees between Tjmax and the thermal sensor due
+to the location of the latter.
+
+This means that 95°C is a safer value to use.
+
+Fixes: cac68a56e34b9810 ("ARM: dts: r8a7791: enable to use thermal-zone")
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e4fdf59bcce3b490bbc7197145bcb9f9d5a18cd3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index dfc1c406179f..008a260f86a5 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -92,7 +92,7 @@
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <115000>;
++					temperature	= <95000>;
+ 					hysteresis	= <0>;
+ 					type		= "critical";
+ 				};
+-- 
+2.19.0
+
diff --git a/patches/0724-ARM-dts-r8a7793-Correct-critical-CPU-temperature.patch b/patches/0724-ARM-dts-r8a7793-Correct-critical-CPU-temperature.patch
new file mode 100644
index 00000000000000..45fe7c5c73844d
--- /dev/null
+++ b/patches/0724-ARM-dts-r8a7793-Correct-critical-CPU-temperature.patch
@@ -0,0 +1,42 @@
+From 10c34dc968aa45e6098cf77a52978349e363b87c Mon Sep 17 00:00:00 2001
+From: Chris Paterson <chris.paterson2@renesas.com>
+Date: Thu, 14 Dec 2017 09:08:41 +0000
+Subject: [PATCH 0724/1795] ARM: dts: r8a7793: Correct critical CPU temperature
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The R-Car M2N hardware manual states that Tc = –40°C to +105°C. The
+thermal sensor has an accuracy of ±5°C and there can be a temperature
+difference of 1 or 2 degrees between Tjmax and the thermal sensor due
+to the location of the latter.
+
+This means that 95°C is a safer value to use.
+
+Fixes: 57f9156bc620ac56 ("ARM: dts: r8a7793: enable to use thermal-zone")
+Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1dfc65cef481ac6af64380f26186d5cc585b46eb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 61dd291d907d..039b22517526 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -89,7 +89,7 @@
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <115000>;
++					temperature	= <95000>;
+ 					hysteresis	= <0>;
+ 					type		= "critical";
+ 				};
+-- 
+2.19.0
+
diff --git a/patches/0725-ARM-shmobile-defconfig-Enable-PWM.patch b/patches/0725-ARM-shmobile-defconfig-Enable-PWM.patch
new file mode 100644
index 00000000000000..e95c010556a025
--- /dev/null
+++ b/patches/0725-ARM-shmobile-defconfig-Enable-PWM.patch
@@ -0,0 +1,33 @@
+From 4a42f2774ae7e43f2af46ec2e445e81a1a4f3ad9 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:34:56 +0000
+Subject: [PATCH 0725/1795] ARM: shmobile: defconfig: Enable PWM
+
+RZ/G1 and R-Car platforms have PWM timers. This patch enables PWM support
+by default.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1943cbd3b39ee3310494d5b531a906e836bb9f7f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index d60dbe1f108f..578434cfd1a0 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -208,6 +208,7 @@ CONFIG_STAGING_BOARD=y
+ CONFIG_IIO=y
+ CONFIG_AK8975=y
+ CONFIG_PWM=y
++CONFIG_PWM_RCAR=y
+ CONFIG_PWM_RENESAS_TPU=y
+ CONFIG_GENERIC_PHY=y
+ CONFIG_PHY_RCAR_GEN2=y
+-- 
+2.19.0
+
diff --git a/patches/0726-ARM-dts-r8a7743-Add-PWM-SoC-support.patch b/patches/0726-ARM-dts-r8a7743-Add-PWM-SoC-support.patch
new file mode 100644
index 00000000000000..9fd047a6a23426
--- /dev/null
+++ b/patches/0726-ARM-dts-r8a7743-Add-PWM-SoC-support.patch
@@ -0,0 +1,102 @@
+From 0a5001cd26c3e28f84842012131e25df2611dd14 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:34:58 +0000
+Subject: [PATCH 0726/1795] ARM: dts: r8a7743: Add PWM SoC support
+
+Add the definitions for pwm[0123456] to the SoC .dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ea16b5896267a2358fc17cf5340b27b906513119)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 70 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 70 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 59860c8ef362..758887494cb9 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1018,6 +1018,76 @@
+ 			status = "disabled";
+ 		};
+ 
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e35000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
++			reg = <0 0xe6e36000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7743",
+ 				     "renesas,rcar-gen2-sdhi";
+-- 
+2.19.0
+
diff --git a/patches/0727-ARM-dts-r8a7743-Add-TPU-support.patch b/patches/0727-ARM-dts-r8a7743-Add-TPU-support.patch
new file mode 100644
index 00000000000000..7580ed53d51ae1
--- /dev/null
+++ b/patches/0727-ARM-dts-r8a7743-Add-TPU-support.patch
@@ -0,0 +1,42 @@
+From 06a2a1cb43f0c08b523ec22832a76be88f70e5aa Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:35:00 +0000
+Subject: [PATCH 0727/1795] ARM: dts: r8a7743: Add TPU support
+
+Add TPU support to SoC DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ba8f6bda525121e310cec7532bf218d0bace4ff1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 758887494cb9..fcdf620d6637 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1088,6 +1088,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		tpu: pwm@e60f0000 {
++			compatible = "renesas,tpu-r8a7743", "renesas,tpu";
++			reg = <0 0xe60f0000 0 0x148>;
++			clocks = <&cpg CPG_MOD 304>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 304>;
++			#pwm-cells = <3>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7743",
+ 				     "renesas,rcar-gen2-sdhi";
+-- 
+2.19.0
+
diff --git a/patches/0728-ARM-dts-r8a7743-Add-thermal-device-to-DT.patch b/patches/0728-ARM-dts-r8a7743-Add-thermal-device-to-DT.patch
new file mode 100644
index 00000000000000..bc7cc1e2d61ed8
--- /dev/null
+++ b/patches/0728-ARM-dts-r8a7743-Add-thermal-device-to-DT.patch
@@ -0,0 +1,68 @@
+From 460d21394750ebd5d86d1122e6f1d78419a137f9 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:17:29 +0000
+Subject: [PATCH 0728/1795] ARM: dts: r8a7743: Add thermal device to DT
+
+This patch instantiates the thermal sensor module with thermal-zone
+support.
+
+This patch is based on the commit cac68a56e34b
+("ARM: dts: r8a7791: enable to use thermal-zone") by Kuninori Morimoto.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6c76b4f7d89e89f0ae405dfc7a64c6d2b5d02813)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index fcdf620d6637..acf9ce2e4057 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -250,6 +250,38 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7743",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <0>;
++				polling-delay = <0>;
++
++				thermal-sensors = <&thermal>;
++
++				trips {
++					cpu-crit {
++						temperature = <95000>;
++						hysteresis = <0>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++				};
++			};
++		};
++
+ 		timer {
+ 			compatible = "arm,armv7-timer";
+ 			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+-- 
+2.19.0
+
diff --git a/patches/0729-ARM-dts-r8a7745-Add-PWM-SoC-support.patch b/patches/0729-ARM-dts-r8a7745-Add-PWM-SoC-support.patch
new file mode 100644
index 00000000000000..0fe0da014c6174
--- /dev/null
+++ b/patches/0729-ARM-dts-r8a7745-Add-PWM-SoC-support.patch
@@ -0,0 +1,102 @@
+From ae7e4d4758d9c13110795a4793e6c3facef1223f Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:06:49 +0000
+Subject: [PATCH 0729/1795] ARM: dts: r8a7745: Add PWM SoC support
+
+Add the definitions for pwm[0123456] to the SoC .dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3711d0ede24d2e3c90ae10e1a79746ac87169609)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 70 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 70 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 0fa78612746f..173d8a2cc6e2 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -936,6 +936,76 @@
+ 			status = "disabled";
+ 		};
+ 
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e35000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
++		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
++			reg = <0 0xe6e36000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7745",
+ 				     "renesas,rcar-gen2-sdhi";
+-- 
+2.19.0
+
diff --git a/patches/0730-ARM-dts-r8a7745-Add-TPU-support.patch b/patches/0730-ARM-dts-r8a7745-Add-TPU-support.patch
new file mode 100644
index 00000000000000..bd2c130defa2b7
--- /dev/null
+++ b/patches/0730-ARM-dts-r8a7745-Add-TPU-support.patch
@@ -0,0 +1,42 @@
+From 301b94ee22209041ab52d00efac840ebed790c08 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:06:51 +0000
+Subject: [PATCH 0730/1795] ARM: dts: r8a7745: Add TPU support
+
+Add TPU support to SoC DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b9db514555274eb325c9b13a0b0587c0e600d75a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 173d8a2cc6e2..b46043567a1e 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -1006,6 +1006,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		tpu: pwm@e60f0000 {
++			compatible = "renesas,tpu-r8a7745", "renesas,tpu";
++			reg = <0 0xe60f0000 0 0x148>;
++			clocks = <&cpg CPG_MOD 304>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 304>;
++			#pwm-cells = <3>;
++			status = "disabled";
++		};
++
+ 		sdhi0: sd@ee100000 {
+ 			compatible = "renesas,sdhi-r8a7745",
+ 				     "renesas,rcar-gen2-sdhi";
+-- 
+2.19.0
+
diff --git a/patches/0731-ARM-dts-r8a7743-Add-CMT-SoC-specific-support.patch b/patches/0731-ARM-dts-r8a7743-Add-CMT-SoC-specific-support.patch
new file mode 100644
index 00000000000000..ab0cb82f2c4be0
--- /dev/null
+++ b/patches/0731-ARM-dts-r8a7743-Add-CMT-SoC-specific-support.patch
@@ -0,0 +1,64 @@
+From 90aaf45090ecdf1f9a20e0c07a0926074d0fb25b Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 17:39:02 +0000
+Subject: [PATCH 0731/1795] ARM: dts: r8a7743: Add CMT SoC specific support
+
+Add CMT[01] support to SoC DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3114c70c532ae2555948739f645ace268554228d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index acf9ce2e4057..f24f36d50e40 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -294,6 +294,38 @@
+ 						  IRQ_TYPE_LEVEL_LOW)>;
+ 		};
+ 
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7743-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7743-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++			status = "disabled";
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7743-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/0732-ARM-dts-r8a7745-Add-CMT-SoC-specific-support.patch b/patches/0732-ARM-dts-r8a7745-Add-CMT-SoC-specific-support.patch
new file mode 100644
index 00000000000000..3a4051fed0ab84
--- /dev/null
+++ b/patches/0732-ARM-dts-r8a7745-Add-CMT-SoC-specific-support.patch
@@ -0,0 +1,64 @@
+From e342d750a865e9bee0026fc1e4373a04e2fe2b4a Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 17:39:03 +0000
+Subject: [PATCH 0732/1795] ARM: dts: r8a7745: Add CMT SoC specific support
+
+Add CMT[01] support to SoC DT.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9680c97b516cbb70efe73dde05d497b1203bde6d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index b46043567a1e..668e644815eb 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -235,6 +235,38 @@
+ 						  IRQ_TYPE_LEVEL_LOW)>;
+ 		};
+ 
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7745-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7745-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++			status = "disabled";
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7745-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/0733-ARM-dts-r8a7745-sort-root-sub-nodes-alphabetically.patch b/patches/0733-ARM-dts-r8a7745-sort-root-sub-nodes-alphabetically.patch
new file mode 100644
index 00000000000000..d0b3f61c5333f5
--- /dev/null
+++ b/patches/0733-ARM-dts-r8a7745-sort-root-sub-nodes-alphabetically.patch
@@ -0,0 +1,98 @@
+From 1bc63cf63b965e2e50dca6dcf7cda6f74071ef86 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 18 Dec 2017 22:50:43 +0100
+Subject: [PATCH 0733/1795] ARM: dts: r8a7745: sort root sub-nodes
+ alphabetically
+
+Sort root sub-nodes alphabetically to allow for easier maintenance
+of this file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit d913ef1faebaf46c8925b7442b8d837a20b8bf6e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 48 +++++++++++++++++-----------------
+ 1 file changed, 24 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 668e644815eb..8fa919a7476d 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -35,6 +35,14 @@
+ 		vin1 = &vin1;
+ 	};
+ 
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -67,6 +75,22 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1231,34 +1255,10 @@
+ 		};
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0734-ARM-dts-r8a7745-move-timer-node-out-of-bus.patch b/patches/0734-ARM-dts-r8a7745-move-timer-node-out-of-bus.patch
new file mode 100644
index 00000000000000..6e52c8cccee6d7
--- /dev/null
+++ b/patches/0734-ARM-dts-r8a7745-move-timer-node-out-of-bus.patch
@@ -0,0 +1,66 @@
+From eb01f2ea066bcc064a6b51c43f82eb029b7e3cf1 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 18 Dec 2017 22:46:57 +0100
+Subject: [PATCH 0734/1795] ARM: dts: r8a7745: move timer node out of bus
+
+The timer node does not have any register properties and thus shouldn't be
+placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make dtbs W=1
+...
+arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+  DTC     arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb
+arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7bee3795c8145678ec101f9dd033ef7f7f858f48)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 8fa919a7476d..2be7485c4efe 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -247,18 +247,6 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv7-timer";
+-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		cmt0: timer@ffca0000 {
+ 			compatible = "renesas,r8a7745-cmt0",
+ 				     "renesas,rcar-gen2-cmt0";
+@@ -1255,6 +1243,14 @@
+ 		};
+ 	};
+ 
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0735-ARM-dts-r8a7792-sort-root-sub-nodes-alphabetically.patch b/patches/0735-ARM-dts-r8a7792-sort-root-sub-nodes-alphabetically.patch
new file mode 100644
index 00000000000000..9ecde8f6510347
--- /dev/null
+++ b/patches/0735-ARM-dts-r8a7792-sort-root-sub-nodes-alphabetically.patch
@@ -0,0 +1,92 @@
+From 1663e94c4fb80819f0725869ae084f157f3d21e1 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 18 Dec 2017 22:27:01 +0100
+Subject: [PATCH 0735/1795] ARM: dts: r8a7792: sort root sub-nodes
+ alphabetically
+
+Sort root sub-nodes alphabetically to allow for easier maintenance
+of this file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c3d2c8d7c20e9702acead1490dd278768ce333c4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 48 +++++++++++++++++-----------------
+ 1 file changed, 24 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index ac05fdb91798..c063cd3f268e 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -36,6 +36,14 @@
+ 		vin5 = &vin5;
+ 	};
+ 
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -69,6 +77,22 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -833,28 +857,4 @@
+ 			#reset-cells = <1>;
+ 		};
+ 	};
+-
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0736-ARM-dts-r8a7792-move-timer-node-out-of-bus.patch b/patches/0736-ARM-dts-r8a7792-move-timer-node-out-of-bus.patch
new file mode 100644
index 00000000000000..c2b88c5823649a
--- /dev/null
+++ b/patches/0736-ARM-dts-r8a7792-move-timer-node-out-of-bus.patch
@@ -0,0 +1,63 @@
+From 53dfbbf8185d5d03e662f2117fa3976559b16ebc Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 18 Dec 2017 22:32:33 +0100
+Subject: [PATCH 0736/1795] ARM: dts: r8a7792: move timer node out of bus
+
+The timer node does not have any register properties and thus shouldn't be
+placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make dtbs W=1
+...
+  DTC     arch/arm/boot/dts/r8a7792-wheat.dtb
+arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3da25909eadbc5ae8dcdec77b19dd1c893d64813)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index c063cd3f268e..3be15a158bad 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -137,18 +137,6 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv7-timer";
+-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+-				      IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+-				      IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+-				      IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+-				      IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		rst: reset-controller@e6160000 {
+ 			compatible = "renesas,r8a7792-rst";
+ 			reg = <0 0xe6160000 0 0x0100>;
+@@ -857,4 +845,12 @@
+ 			#reset-cells = <1>;
+ 		};
+ 	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0737-ARM-dts-iwg20d-q7-common-Enable-SGTL5000-audio-codec.patch b/patches/0737-ARM-dts-iwg20d-q7-common-Enable-SGTL5000-audio-codec.patch
new file mode 100644
index 00000000000000..a109f8cc7ca95c
--- /dev/null
+++ b/patches/0737-ARM-dts-iwg20d-q7-common-Enable-SGTL5000-audio-codec.patch
@@ -0,0 +1,63 @@
+From f0c277df6d229845c39fb7b8ce81d5d13ec78106 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 12 Dec 2017 18:25:11 +0000
+Subject: [PATCH 0737/1795] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio
+ codec
+
+This patch enables SGTL5000 audio codec on the carrier board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3091626868981e086f57d580cb1711b4553c5663)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 54470c6de891..03d41a736afd 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -20,6 +20,20 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	audio_clock: audio_clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <26000000>;
++	};
++
++	reg_1p5v: 1p5v {
++		compatible = "regulator-fixed";
++		regulator-name = "1P5V";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		regulator-always-on;
++	};
++
+ 	vcc_sdhi1: regulator-vcc-sdhi1 {
+ 		compatible = "regulator-fixed";
+ 
+@@ -83,6 +97,16 @@
+ 		compatible = "ti,bq32000";
+ 		reg = <0x68>;
+ 	};
++
++	sgtl5000: codec@a {
++		compatible = "fsl,sgtl5000";
++		#sound-dai-cells = <0>;
++		reg = <0x0a>;
++		clocks = <&audio_clock>;
++		VDDA-supply = <&reg_3p3v>;
++		VDDIO-supply = <&reg_3p3v>;
++		VDDD-supply = <&reg_1p5v>;
++	};
+ };
+ 
+ &pci0 {
+-- 
+2.19.0
+
diff --git a/patches/0738-ARM-dts-iwg20d-q7-common-Sound-PIO-support.patch b/patches/0738-ARM-dts-iwg20d-q7-common-Sound-PIO-support.patch
new file mode 100644
index 00000000000000..9adc929e49a2e5
--- /dev/null
+++ b/patches/0738-ARM-dts-iwg20d-q7-common-Sound-PIO-support.patch
@@ -0,0 +1,99 @@
+From 103cbe8780d7c3de67827bd3ea7c0d9b01b8c027 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:22:37 +0000
+Subject: [PATCH 0738/1795] ARM: dts: iwg20d-q7-common: Sound PIO support
+
+Enable sound PIO support on carrier board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cfa2e2f7cf22d0523a88c6284606baa9b2698866)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 46 +++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 03d41a736afd..f6b0eead6f92 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -34,6 +34,22 @@
+ 		regulator-always-on;
+ 	};
+ 
++	rsnd_sgtl5000: sound {
++		compatible = "simple-audio-card";
++
++		simple-audio-card,format = "i2s";
++		simple-audio-card,bitclock-master = <&sndcodec>;
++		simple-audio-card,frame-master = <&sndcodec>;
++
++		sndcpu: simple-audio-card,cpu {
++			sound-dai = <&rcar_sound>;
++		};
++
++		sndcodec: simple-audio-card,codec {
++			sound-dai = <&sgtl5000>;
++		};
++	};
++
+ 	vcc_sdhi1: regulator-vcc-sdhi1 {
+ 		compatible = "regulator-fixed";
+ 
+@@ -166,6 +182,11 @@
+ 		power-source = <1800>;
+ 	};
+ 
++	sound_pins: sound {
++		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
++		function = "ssi";
++	};
++
+ 	usb0_pins: usb0 {
+ 		groups = "usb0";
+ 		function = "usb0";
+@@ -177,6 +198,22 @@
+ 	};
+ };
+ 
++&rcar_sound {
++	pinctrl-0 = <&sound_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* Single DAI */
++	#sound-dai-cells = <0>;
++
++	rcar_sound,dai {
++		dai0 {
++			playback = <&ssi1>;
++			capture = <&ssi0>;
++		};
++	};
++};
++
+ &scif0 {
+ 	pinctrl-0 = <&scif0_pins>;
+ 	pinctrl-names = "default";
+@@ -205,6 +242,15 @@
+ 	status = "okay";
+ };
+ 
++&ssi0 {
++	pio-transfer;
++};
++
++&ssi1 {
++	pio-transfer;
++	shared-pin;
++};
++
+ &usbphy {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0739-ARM-dts-iwg20d-q7-common-Sound-DMA-support-on-DTS.patch b/patches/0739-ARM-dts-iwg20d-q7-common-Sound-DMA-support-on-DTS.patch
new file mode 100644
index 00000000000000..9a1701ecd69abb
--- /dev/null
+++ b/patches/0739-ARM-dts-iwg20d-q7-common-Sound-DMA-support-on-DTS.patch
@@ -0,0 +1,46 @@
+From 841077c937e58828fcba7544d68aed24edc206a9 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:22:38 +0000
+Subject: [PATCH 0739/1795] ARM: dts: iwg20d-q7-common: Sound DMA support on
+ DTS
+
+DMA transfer to/from SSI
+
+     DMA
+[MEM] -> [SSI]
+
+     DMA
+[MEM] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eeecf0b2a04e118c6404da7fbca3c8f82b0302a3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index f6b0eead6f92..0c0f08649fda 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -243,11 +243,11 @@
+ };
+ 
+ &ssi0 {
+-	pio-transfer;
++	no-busif;
+ };
+ 
+ &ssi1 {
+-	pio-transfer;
++	no-busif;
+ 	shared-pin;
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0740-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-BUSIF.patch b/patches/0740-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-BUSIF.patch
new file mode 100644
index 00000000000000..63061c692f2a51
--- /dev/null
+++ b/patches/0740-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-BUSIF.patch
@@ -0,0 +1,45 @@
+From 7d72c8aaaa3f5baa66799e0b2a22dff2f23f66bb Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:22:39 +0000
+Subject: [PATCH 0740/1795] ARM: dts: iwg20d-q7-common: Sound DMA support via
+ BUSIF on DTS
+
+DMA transfer to/from SSIU
+
+     DMA
+[MEM] -> [SSIU] -> [SSI]
+
+     DMA
+[MEM] <- [SSIU] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 354cce5a1c8700afa8cff8f85c93c84feb342815)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 0c0f08649fda..00b5b1351b26 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -242,12 +242,7 @@
+ 	status = "okay";
+ };
+ 
+-&ssi0 {
+-	no-busif;
+-};
+-
+ &ssi1 {
+-	no-busif;
+ 	shared-pin;
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0741-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-SRC-o.patch b/patches/0741-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-SRC-o.patch
new file mode 100644
index 00000000000000..2f912c7726ae8c
--- /dev/null
+++ b/patches/0741-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-SRC-o.patch
@@ -0,0 +1,48 @@
+From 3eaee96295a762440aa3648eedee8c0b81ead372 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:22:40 +0000
+Subject: [PATCH 0741/1795] ARM: dts: iwg20d-q7-common: Sound DMA support via
+ SRC on DTS
+
+DMA transfer to/from SRC
+
+     DMA      DMApp
+[MEM] -> [SRC] -> [SSIU] -> [SSI]
+
+     DMA      DMApp
+[MEM] <- [SRC] <- [SSIU] <- [SSI]
+
+Current sound driver is supporting SSI/SRC random connection.
+So, this patch is trying
+SSI1 -> SRC3
+SSI0 <- SRC2
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b4b2094511166d904e6f15df8eff9d2776bf138c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 00b5b1351b26..952b79e1b391 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -208,8 +208,8 @@
+ 
+ 	rcar_sound,dai {
+ 		dai0 {
+-			playback = <&ssi1>;
+-			capture = <&ssi0>;
++			playback = <&ssi1 &src3>;
++			capture = <&ssi0 &src2>;
+ 		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0742-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-DVC-o.patch b/patches/0742-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-DVC-o.patch
new file mode 100644
index 00000000000000..d16978f9d6962b
--- /dev/null
+++ b/patches/0742-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-DVC-o.patch
@@ -0,0 +1,73 @@
+From fc3fee4c22dba6c6161e3bb3384297fc5f9dacc8 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 18 Dec 2017 18:22:41 +0000
+Subject: [PATCH 0742/1795] ARM: dts: iwg20d-q7-common: Sound DMA support via
+ DVC on DTS
+
+DMA transfer uses DVC
+
+     DMA               DMApp
+[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]
+
+     DMA               DMApp
+[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0ed33948cb43193ba3dbdff8e521f84326669405)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 27 +++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+index 952b79e1b391..66954aaf2c47 100644
+--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
++++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+@@ -8,6 +8,29 @@
+  * kind, whether express or implied.
+  */
+ 
++/*
++ * SSI-SGTL5000
++ *
++ * This command is required when Playback/Capture
++ *
++ *      amixer set "DVC Out" 100%
++ *      amixer set "DVC In" 100%
++ *
++ * You can use Mute
++ *
++ *      amixer set "DVC Out Mute" on
++ *      amixer set "DVC In Mute" on
++ *
++ * You can use Volume Ramp
++ *
++ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
++ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
++ *      amixer set "DVC Out Ramp" on
++ *      aplay xxx.wav &
++ *      amixer set "DVC Out"  80%  // Volume Down
++ *      amixer set "DVC Out" 100%  // Volume Up
++ */
++
+ / {
+ 	aliases {
+ 		serial0 = &scif0;
+@@ -208,8 +231,8 @@
+ 
+ 	rcar_sound,dai {
+ 		dai0 {
+-			playback = <&ssi1 &src3>;
+-			capture = <&ssi0 &src2>;
++			playback = <&ssi1 &src3 &dvc1>;
++			capture = <&ssi0 &src2 &dvc0>;
+ 		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0743-ARM-dts-r8a7743-sort-root-sub-nodes-alphabetically.patch b/patches/0743-ARM-dts-r8a7743-sort-root-sub-nodes-alphabetically.patch
new file mode 100644
index 00000000000000..83e930331c4883
--- /dev/null
+++ b/patches/0743-ARM-dts-r8a7743-sort-root-sub-nodes-alphabetically.patch
@@ -0,0 +1,158 @@
+From 6b2feb9c3c69da693d4626ac23d12288aba6d3ea Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 7 Dec 2017 11:05:39 +0100
+Subject: [PATCH 0743/1795] ARM: dts: r8a7743: sort root sub-nodes
+ alphabetically
+
+Sort root sub-nodes alphabetically to allow for easier maintenance
+of this file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3c2d908f056fed6743691a30438b9f10cb3d2867)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 108 ++++++++++++++++-----------------
+ 1 file changed, 54 insertions(+), 54 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index f24f36d50e40..ecbd39e5f630 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -37,6 +37,37 @@
+ 		vin2 = &vin2;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -79,6 +110,29 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1621,64 +1675,10 @@
+ 		};
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External PCIe clock - can be overridden by the board */
+-	pcie_bus_clk: pcie_bus {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0744-ARM-dts-r8a7743-move-timer-and-thermal-zones-nodes-o.patch b/patches/0744-ARM-dts-r8a7743-move-timer-and-thermal-zones-nodes-o.patch
new file mode 100644
index 00000000000000..5eb00445c42fad
--- /dev/null
+++ b/patches/0744-ARM-dts-r8a7743-move-timer-and-thermal-zones-nodes-o.patch
@@ -0,0 +1,110 @@
+From 5cd787ef64a4bcec73a3bb9799c99159e7b861c3 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 7 Dec 2017 11:10:58 +0100
+Subject: [PATCH 0744/1795] ARM: dts: r8a7743: move timer and thermal-zones
+ nodes out of bus
+
+The timer and thermal-zones nodes do not have any register properties and
+thus shouldn't be placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make
+  DTC     arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
+arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+  DTC     arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
+arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
+arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b9db3affbcdc1824d7481262858171938c936e77)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 60 ++++++++++++++++------------------
+ 1 file changed, 28 insertions(+), 32 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index ecbd39e5f630..0b74c6c7d21d 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -316,38 +316,6 @@
+ 			#thermal-sensor-cells = <0>;
+ 		};
+ 
+-		thermal-zones {
+-			cpu_thermal: cpu-thermal {
+-				polling-delay-passive = <0>;
+-				polling-delay = <0>;
+-
+-				thermal-sensors = <&thermal>;
+-
+-				trips {
+-					cpu-crit {
+-						temperature = <95000>;
+-						hysteresis = <0>;
+-						type = "critical";
+-					};
+-				};
+-
+-				cooling-maps {
+-				};
+-			};
+-		};
+-
+-		timer {
+-			compatible = "arm,armv7-timer";
+-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+-						  IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		cmt0: timer@ffca0000 {
+ 			compatible = "renesas,r8a7743-cmt0",
+ 				     "renesas,rcar-gen2-cmt0";
+@@ -1675,6 +1643,34 @@
+ 		};
+ 	};
+ 
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
++
++			thermal-sensors = <&thermal>;
++
++			trips {
++				cpu-crit {
++					temperature = <95000>;
++					hysteresis = <0>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++			};
++		};
++	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0745-ARM-dts-r8a7740-Correct-TPU-register-block-size.patch b/patches/0745-ARM-dts-r8a7740-Correct-TPU-register-block-size.patch
new file mode 100644
index 00000000000000..f07e90c8c1fb3f
--- /dev/null
+++ b/patches/0745-ARM-dts-r8a7740-Correct-TPU-register-block-size.patch
@@ -0,0 +1,33 @@
+From baf3f5f9ea48ddc7b0984690ef436d1f98acf8b1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 19 Dec 2017 17:02:05 +0100
+Subject: [PATCH 0745/1795] ARM: dts: r8a7740: Correct TPU register block size
+
+The Timer Pulse Unit has registers that lie outside the declared
+register block.  Enlarge the register block size to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2211a3062c8dd3d8081ac208240ab48d7786f353)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7740.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
+index 95c408b11991..afd3bc5e6cf2 100644
+--- a/arch/arm/boot/dts/r8a7740.dtsi
++++ b/arch/arm/boot/dts/r8a7740.dtsi
+@@ -317,7 +317,7 @@
+ 
+ 	tpu: pwm@e6600000 {
+ 		compatible = "renesas,tpu-r8a7740", "renesas,tpu";
+-		reg = <0xe6600000 0x100>;
++		reg = <0xe6600000 0x148>;
+ 		clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
+ 		power-domains = <&pd_a3sp>;
+ 		status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/0746-ARM-dts-r8a7745-Add-audio-clocks.patch b/patches/0746-ARM-dts-r8a7745-Add-audio-clocks.patch
new file mode 100644
index 00000000000000..a8a5ce806973aa
--- /dev/null
+++ b/patches/0746-ARM-dts-r8a7745-Add-audio-clocks.patch
@@ -0,0 +1,54 @@
+From da952c2bb153bed88a4137e3b9ce81df48a3455f Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:01:57 +0000
+Subject: [PATCH 0746/1795] ARM: dts: r8a7745: Add audio clocks
+
+Describe the external audio clocks required by the sound driver.
+Boards that provide audio clocks need to override the clock frequencies.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 44da63157d86b5ca5c4dec2b160bdeb71c6bd48e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 2be7485c4efe..6d085f004721 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -35,6 +35,27 @@
+ 		vin1 = &vin1;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured  as 0 Hz fixed
++	 * frequency clocks by default.  Boards that provide audio
++	 * clocks should override them.
++	 */
++	audio_clka: audio_clka {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkb: audio_clkb {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkc: audio_clkc {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	/* External CAN clock */
+ 	can_clk: can {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0747-ARM-dts-r8a7745-Add-audio-DMAC-support.patch b/patches/0747-ARM-dts-r8a7745-Add-audio-DMAC-support.patch
new file mode 100644
index 00000000000000..798f1c574371e1
--- /dev/null
+++ b/patches/0747-ARM-dts-r8a7745-Add-audio-DMAC-support.patch
@@ -0,0 +1,63 @@
+From 445b3cfb40de56693aed58494c9fa779d91ca614 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:01:58 +0000
+Subject: [PATCH 0747/1795] ARM: dts: r8a7745: Add audio DMAC support
+
+Instantiate the audio DMA controller on the r8a7745 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a14a05c2f32143431615116f94cf455727cce235)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 6d085f004721..d9488a116236 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -397,6 +397,37 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7745",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
+ 		usb_dmac0: dma-controller@e65a0000 {
+ 			compatible = "renesas,r8a7745-usb-dmac",
+ 				     "renesas,usb-dmac";
+-- 
+2.19.0
+
diff --git a/patches/0748-ARM-dts-r8a7745-Add-sound-support.patch b/patches/0748-ARM-dts-r8a7745-Add-sound-support.patch
new file mode 100644
index 00000000000000..4896b46f7307e3
--- /dev/null
+++ b/patches/0748-ARM-dts-r8a7745-Add-sound-support.patch
@@ -0,0 +1,214 @@
+From b7219f499465e4921e8b4c4779a0396b8306e5e1 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:01:59 +0000
+Subject: [PATCH 0748/1795] ARM: dts: r8a7745: Add sound support
+
+Define the generic r8a7745(RZ/G1E) part of the sound device node.
+
+This patch is based on the r8a7794 sound work by Sergei Shtylyov.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 17d2e479d09e597c9915f0ab853edfa8f5010476)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 180 +++++++++++++++++++++++++++++++++
+ 1 file changed, 180 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index d9488a116236..835a2821477b 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -1293,6 +1293,186 @@
+ 			resets = <&cpg 915>;
+ 			status = "disabled";
+ 		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7745",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
++				 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
++				 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
++				 <&cpg CPG_CORE R8A7745_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0",
++				      "src.6", "src.5", "src.4", "src.3",
++				      "src.2", "src.1",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
++				 <&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
++				 <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
++
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma0 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma0 0xbe>;
++					dma-names = "tx";
++				};
++			};
++
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
++
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
++
++			rcar_sound,src {
++				src-0 {
++					status = "disabled";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma0 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma0 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma0 0xb4>;
++					dma-names = "rx", "tx";
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma0 0x02>,
++					       <&audma0 0x15>, <&audma0 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma0 0x04>,
++					       <&audma0 0x49>, <&audma0 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma0 0x06>,
++					       <&audma0 0x63>, <&audma0 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma0 0x08>,
++					       <&audma0 0x6f>, <&audma0 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma0 0x0a>,
++					       <&audma0 0x71>, <&audma0 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
++					       <&audma0 0x73>, <&audma0 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
++					       <&audma0 0x75>, <&audma0 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma0 0x10>,
++					       <&audma0 0x79>, <&audma0 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma0 0x12>,
++					       <&audma0 0x7b>, <&audma0 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma0 0x14>,
++					       <&audma0 0x7d>, <&audma0 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++			};
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/0749-ARM-dts-iwg22d-sodimm-Enable-SGTL5000-audio-codec.patch b/patches/0749-ARM-dts-iwg22d-sodimm-Enable-SGTL5000-audio-codec.patch
new file mode 100644
index 00000000000000..40026cc8aaeaf3
--- /dev/null
+++ b/patches/0749-ARM-dts-iwg22d-sodimm-Enable-SGTL5000-audio-codec.patch
@@ -0,0 +1,75 @@
+From 4d37a7c2070380b5590324a9792cb1419a3ea3cf Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:00 +0000
+Subject: [PATCH 0749/1795] ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio
+ codec
+
+This patch enables SGTL5000 audio codec on the carrier board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 55e37da0309a2237cc8f14a43ba04b2fd2083c1c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 28 +++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 39ce7e7101c7..5d4b7d203f8d 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -26,6 +26,12 @@
+ 		stdout-path = "serial3:115200n8";
+ 	};
+ 
++	audio_clock: audio_clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <26000000>;
++	};
++
+ 	vccq_sdhi0: regulator-vccq-sdhi0 {
+ 		compatible = "regulator-gpio";
+ 
+@@ -80,6 +86,23 @@
+ 	pinctrl-names = "default";
+ };
+ 
++&i2c5 {
++	pinctrl-0 = <&i2c5_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	sgtl5000: codec@a {
++		compatible = "fsl,sgtl5000";
++		#sound-dai-cells = <0>;
++		reg = <0x0a>;
++		clocks = <&audio_clock>;
++		VDDA-supply = <&reg_3p3v>;
++		VDDIO-supply = <&reg_3p3v>;
++	};
++};
++
+ &pci1 {
+ 	status = "okay";
+ 	pinctrl-0 = <&usb1_pins>;
+@@ -102,6 +125,11 @@
+ 		function = "hscif1";
+ 	};
+ 
++	i2c5_pins: i2c5 {
++		groups = "i2c5_b";
++		function = "i2c5";
++	};
++
+ 	scif4_pins: scif4 {
+ 		groups = "scif4_data_b";
+ 		function = "scif4";
+-- 
+2.19.0
+
diff --git a/patches/0750-ARM-dts-iwg22d-sodimm-Sound-PIO-support.patch b/patches/0750-ARM-dts-iwg22d-sodimm-Sound-PIO-support.patch
new file mode 100644
index 00000000000000..654b3b1b14aa31
--- /dev/null
+++ b/patches/0750-ARM-dts-iwg22d-sodimm-Sound-PIO-support.patch
@@ -0,0 +1,98 @@
+From 0516bce4ddbc333e7f96f88ec02faff73dbd299d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:01 +0000
+Subject: [PATCH 0750/1795] ARM: dts: iwg22d-sodimm: Sound PIO support
+
+Enable sound PIO support on carrier board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3838ef590119420031ad2a51ea19a9be2ea9acef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 46 +++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 5d4b7d203f8d..b6521da8b766 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -32,6 +32,21 @@
+ 		clock-frequency = <26000000>;
+ 	};
+ 
++	rsnd_sgtl5000: sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,bitclock-master = <&sndcodec>;
++		simple-audio-card,frame-master = <&sndcodec>;
++
++		sndcpu: simple-audio-card,cpu {
++			sound-dai = <&rcar_sound>;
++		};
++
++		sndcodec: simple-audio-card,codec {
++			sound-dai = <&sgtl5000>;
++		};
++	};
++
+ 	vccq_sdhi0: regulator-vccq-sdhi0 {
+ 		compatible = "regulator-gpio";
+ 
+@@ -141,6 +156,11 @@
+ 		power-source = <3300>;
+ 	};
+ 
++	sound_pins: sound {
++		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
++		function = "ssi";
++	};
++
+ 	usb0_pins: usb0 {
+ 		groups = "usb0";
+ 		function = "usb0";
+@@ -152,6 +172,23 @@
+ 	};
+ };
+ 
++&rcar_sound {
++	pinctrl-0 = <&sound_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	/* Single DAI */
++
++	#sound-dai-cells = <0>;
++
++	rcar_sound,dai {
++		dai0 {
++			playback = <&ssi3>;
++			capture = <&ssi4>;
++		};
++	};
++};
++
+ &scif4 {
+ 	pinctrl-0 = <&scif4_pins>;
+ 	pinctrl-names = "default";
+@@ -169,6 +206,15 @@
+ 	status = "okay";
+ };
+ 
++&ssi3 {
++	pio-transfer;
++};
++
++&ssi4 {
++	pio-transfer;
++	shared-pin;
++};
++
+ &usbphy {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0751-ARM-dts-iwg22d-sodimm-Sound-DMA-support-on-DTS.patch b/patches/0751-ARM-dts-iwg22d-sodimm-Sound-DMA-support-on-DTS.patch
new file mode 100644
index 00000000000000..f51de32e4fa4b8
--- /dev/null
+++ b/patches/0751-ARM-dts-iwg22d-sodimm-Sound-DMA-support-on-DTS.patch
@@ -0,0 +1,44 @@
+From 14c58bc8884c3398735ce8d6fdc08c699d52387d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:02 +0000
+Subject: [PATCH 0751/1795] ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
+
+DMA transfer to/from SSI
+
+     DMA
+[MEM] -> [SSI]
+
+     DMA
+[MEM] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b3f36c455ccce0acd33b6d055dead4396a1b1b43)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index b6521da8b766..a9ba46d804bc 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -207,11 +207,11 @@
+ };
+ 
+ &ssi3 {
+-	pio-transfer;
++	no-busif;
+ };
+ 
+ &ssi4 {
+-	pio-transfer;
++	no-busif;
+ 	shared-pin;
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0752-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-BUSIF-on.patch b/patches/0752-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-BUSIF-on.patch
new file mode 100644
index 00000000000000..fd32c2c12ef021
--- /dev/null
+++ b/patches/0752-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-BUSIF-on.patch
@@ -0,0 +1,44 @@
+From 2c9cef7ed0a9f565c739a5f12ee6b7c8d769cd4d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:03 +0000
+Subject: [PATCH 0752/1795] ARM: dts: iwg22d-sodimm: Sound DMA support via
+ BUSIF on DTS
+
+DMA transfer to/from SSIU
+
+     DMA
+[MEM] -> [SSIU] -> [SSI]
+
+     DMA
+[MEM] <- [SSIU] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 996d68a1f4fd6f95ab340d84871cbdcb34bc74f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index a9ba46d804bc..0f880c1e7afa 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -206,12 +206,7 @@
+ 	status = "okay";
+ };
+ 
+-&ssi3 {
+-	no-busif;
+-};
+-
+ &ssi4 {
+-	no-busif;
+ 	shared-pin;
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0753-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-SRC-on-D.patch b/patches/0753-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-SRC-on-D.patch
new file mode 100644
index 00000000000000..2a3d77056582b0
--- /dev/null
+++ b/patches/0753-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-SRC-on-D.patch
@@ -0,0 +1,47 @@
+From 7b3cd0b9c51b9774a142b72b085c792004e2c743 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:04 +0000
+Subject: [PATCH 0753/1795] ARM: dts: iwg22d-sodimm: Sound DMA support via SRC
+ on DTS
+
+DMA transfer to/from SRC
+
+     DMA      DMApp
+[MEM] -> [SRC] -> [SSIU] -> [SSI]
+
+     DMA      DMApp
+[MEM] <- [SRC] <- [SSIU] <- [SSI]
+
+Current sound driver is supporting SSI/SRC random connection.
+So, this patch is trying
+SSI3 -> SRC3
+SSI4 <- SRC4
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5ce5faa6fcf8b643ab91f48b972fd850f33d8f57)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 0f880c1e7afa..2cac57c7c44d 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -183,8 +183,8 @@
+ 
+ 	rcar_sound,dai {
+ 		dai0 {
+-			playback = <&ssi3>;
+-			capture = <&ssi4>;
++			playback = <&ssi3 &src3>;
++			capture = <&ssi4 &src4>;
+ 		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0754-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-DVC-on-D.patch b/patches/0754-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-DVC-on-D.patch
new file mode 100644
index 00000000000000..12420250f8296c
--- /dev/null
+++ b/patches/0754-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-DVC-on-D.patch
@@ -0,0 +1,72 @@
+From f87de542993a477775e8e66bf7881a6c21ef8066 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 20 Dec 2017 20:02:05 +0000
+Subject: [PATCH 0754/1795] ARM: dts: iwg22d-sodimm: Sound DMA support via DVC
+ on DTS
+
+DMA transfer uses DVC
+
+     DMA               DMApp
+[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]
+
+     DMA               DMApp
+[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6f41d5e0872e4b55a5352ff79ab2452bff306753)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 27 +++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+index 2cac57c7c44d..a4058f4cfbcd 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
++++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+@@ -8,6 +8,29 @@
+  * kind, whether express or implied.
+  */
+ 
++/*
++ * SSI-SGTL5000
++ *
++ * This command is required when Playback/Capture
++ *
++ *      amixer set "DVC Out" 100%
++ *      amixer set "DVC In" 100%
++ *
++ * You can use Mute
++ *
++ *      amixer set "DVC Out Mute" on
++ *      amixer set "DVC In Mute" on
++ *
++ * You can use Volume Ramp
++ *
++ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
++ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
++ *      amixer set "DVC Out Ramp" on
++ *      aplay xxx.wav &
++ *      amixer set "DVC Out"  80%  // Volume Down
++ *      amixer set "DVC Out" 100%  // Volume Up
++ */
++
+ /dts-v1/;
+ #include "r8a7745-iwg22m.dtsi"
+ 
+@@ -183,8 +206,8 @@
+ 
+ 	rcar_sound,dai {
+ 		dai0 {
+-			playback = <&ssi3 &src3>;
+-			capture = <&ssi4 &src4>;
++			playback = <&ssi3 &src3 &dvc0>;
++			capture = <&ssi4 &src4 &dvc1>;
+ 		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0755-ARM-dts-r8a7745-Add-missing-clock-for-secondary-CA7-.patch b/patches/0755-ARM-dts-r8a7745-Add-missing-clock-for-secondary-CA7-.patch
new file mode 100644
index 00000000000000..a46f987fca52e8
--- /dev/null
+++ b/patches/0755-ARM-dts-r8a7745-Add-missing-clock-for-secondary-CA7-.patch
@@ -0,0 +1,34 @@
+From 8d63ebe74aa10cbb168c40706ad46690e6adc04e Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Thu, 21 Dec 2017 14:52:25 +0000
+Subject: [PATCH 0755/1795] ARM: dts: r8a7745: Add missing clock for secondary
+ CA7 CPU core
+
+Add the missing clock to CA7 CPU1 node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5b062010675b3d74c9a6c6896e2becf932a4ca74)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 835a2821477b..ae918e9cce21 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -84,6 +84,7 @@
+ 			compatible = "arm,cortex-a7";
+ 			reg = <1>;
+ 			clock-frequency = <1000000000>;
++			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
+ 			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+ 			next-level-cache = <&L2_CA7>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/0756-macb-Kill-PHY-reset-code.patch b/patches/0756-macb-Kill-PHY-reset-code.patch
new file mode 100644
index 00000000000000..e5707e8a7b4691
--- /dev/null
+++ b/patches/0756-macb-Kill-PHY-reset-code.patch
@@ -0,0 +1,89 @@
+From d16386159ba6c2710b93c5116134a242cdec0bb5 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Mon, 4 Dec 2017 11:34:50 +0100
+Subject: [PATCH 0756/1795] macb: Kill PHY reset code
+
+With the phylib now being aware of the "reset-gpios" PHY node property,
+there should be no need to frob the PHY reset in this driver anymore...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 096457b5523bbbb371c0099d4db5663fa084494a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/cadence/macb.h      |  1 -
+ drivers/net/ethernet/cadence/macb_main.c | 21 ---------------------
+ 2 files changed, 22 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
+index c93f3a2dc6c1..146cb24ebf44 100644
+--- a/drivers/net/ethernet/cadence/macb.h
++++ b/drivers/net/ethernet/cadence/macb.h
+@@ -1032,7 +1032,6 @@ struct macb {
+ 	unsigned int		dma_burst_length;
+ 
+ 	phy_interface_t		phy_interface;
+-	struct gpio_desc	*reset_gpio;
+ 
+ 	/* AT91RM9200 transmit */
+ 	struct sk_buff *skb;			/* holds skb until xmit interrupt completes */
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index dfef4ec167c1..26da92fca367 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -3396,7 +3396,6 @@ static int macb_probe(struct platform_device *pdev)
+ 					      = macb_config->clk_init;
+ 	int (*init)(struct platform_device *) = macb_config->init;
+ 	struct device_node *np = pdev->dev.of_node;
+-	struct device_node *phy_node;
+ 	struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
+ 	unsigned int queue_mask, num_queues;
+ 	struct macb_platform_data *pdata;
+@@ -3502,18 +3501,6 @@ static int macb_probe(struct platform_device *pdev)
+ 	else
+ 		macb_get_hwaddr(bp);
+ 
+-	/* Power up the PHY if there is a GPIO reset */
+-	phy_node =  of_get_next_available_child(np, NULL);
+-	if (phy_node) {
+-		int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
+-
+-		if (gpio_is_valid(gpio)) {
+-			bp->reset_gpio = gpio_to_desc(gpio);
+-			gpiod_direction_output(bp->reset_gpio, 1);
+-		}
+-	}
+-	of_node_put(phy_node);
+-
+ 	err = of_get_phy_mode(np);
+ 	if (err < 0) {
+ 		pdata = dev_get_platdata(&pdev->dev);
+@@ -3557,10 +3544,6 @@ static int macb_probe(struct platform_device *pdev)
+ 	mdiobus_unregister(bp->mii_bus);
+ 	mdiobus_free(bp->mii_bus);
+ 
+-	/* Shutdown the PHY if there is a GPIO reset */
+-	if (bp->reset_gpio)
+-		gpiod_set_value(bp->reset_gpio, 0);
+-
+ err_out_free_netdev:
+ 	free_netdev(dev);
+ 
+@@ -3588,10 +3571,6 @@ static int macb_remove(struct platform_device *pdev)
+ 		dev->phydev = NULL;
+ 		mdiobus_free(bp->mii_bus);
+ 
+-		/* Shutdown the PHY if there is a GPIO reset */
+-		if (bp->reset_gpio)
+-			gpiod_set_value(bp->reset_gpio, 0);
+-
+ 		unregister_netdev(dev);
+ 		clk_disable_unprepare(bp->tx_clk);
+ 		clk_disable_unprepare(bp->hclk);
+-- 
+2.19.0
+
diff --git a/patches/0757-phylib-Add-device-reset-GPIO-support.patch b/patches/0757-phylib-Add-device-reset-GPIO-support.patch
new file mode 100644
index 00000000000000..550f52610376fe
--- /dev/null
+++ b/patches/0757-phylib-Add-device-reset-GPIO-support.patch
@@ -0,0 +1,352 @@
+From 00890e3032af8577bbec15098bc390274f0e34c7 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Mon, 4 Dec 2017 13:35:05 +0100
+Subject: [PATCH 0757/1795] phylib: Add device reset GPIO support
+
+The PHY devices sometimes do have their reset signal (maybe even power
+supply?) tied to some GPIO and sometimes it also does happen that a boot
+loader does not leave it deasserted. So far this issue has been attacked
+from (as I believe) a wrong angle: by teaching the MAC driver to manipulate
+the GPIO in question; that solution, when applied to the device trees, led
+to adding the PHY reset GPIO properties to the MAC device node, with one
+exception: Cadence MACB driver which could handle the "reset-gpios" prop
+in a PHY device subnode. I believe that the correct approach is to teach
+the 'phylib' to get the MDIO device reset GPIO from the device tree node
+corresponding to this device -- which this patch is doing...
+
+Note that I had to modify the AT803x PHY driver as it would stop working
+otherwise -- it made use of the reset GPIO for its own purposes...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+[geert: Propagate actual errors from fwnode_get_named_gpiod()]
+[geert: Avoid destroying initial setup]
+[geert: Consolidate GPIO descriptor acquiring code]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Richard Leitner <richard.leitner@skidata.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit bafbdd527d569c8200521f2f7579f65a044271be)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	include/linux/phy.h
+---
+ Documentation/devicetree/bindings/net/phy.txt |  2 ++
+ drivers/net/phy/at803x.c                      | 18 ++---------
+ drivers/net/phy/mdio_bus.c                    | 21 ++++++++++++
+ drivers/net/phy/mdio_device.c                 | 25 +++++++++++++--
+ drivers/net/phy/phy_device.c                  | 32 +++++++++++++++++--
+ include/linux/mdio.h                          |  3 ++
+ include/linux/phy.h                           |  5 +++
+ 7 files changed, 87 insertions(+), 19 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
+index 77d0b2a61ffa..c05479f5ac7c 100644
+--- a/Documentation/devicetree/bindings/net/phy.txt
++++ b/Documentation/devicetree/bindings/net/phy.txt
+@@ -53,6 +53,8 @@ Optional Properties:
+   to ensure the integrated PHY is used. The absence of this property indicates
+   the muxers should be configured so that the external PHY is used.
+ 
++- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
++
+ Example:
+ 
+ ethernet-phy@0 {
+diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
+index e911e4990b20..c391676463ad 100644
+--- a/drivers/net/phy/at803x.c
++++ b/drivers/net/phy/at803x.c
+@@ -71,7 +71,6 @@ MODULE_LICENSE("GPL");
+ 
+ struct at803x_priv {
+ 	bool phy_reset:1;
+-	struct gpio_desc *gpiod_reset;
+ };
+ 
+ struct at803x_context {
+@@ -250,22 +249,11 @@ static int at803x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+ 	struct at803x_priv *priv;
+-	struct gpio_desc *gpiod_reset;
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	if (phydev->drv->phy_id != ATH8030_PHY_ID)
+-		goto does_not_require_reset_workaround;
+-
+-	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+-	if (IS_ERR(gpiod_reset))
+-		return PTR_ERR(gpiod_reset);
+-
+-	priv->gpiod_reset = gpiod_reset;
+-
+-does_not_require_reset_workaround:
+ 	phydev->priv = priv;
+ 
+ 	return 0;
+@@ -339,14 +327,14 @@ static void at803x_link_change_notify(struct phy_device *phydev)
+ 	 * cannot recover from by software.
+ 	 */
+ 	if (phydev->state == PHY_NOLINK) {
+-		if (priv->gpiod_reset && !priv->phy_reset) {
++		if (phydev->mdio.reset && !priv->phy_reset) {
+ 			struct at803x_context context;
+ 
+ 			at803x_context_save(phydev, &context);
+ 
+-			gpiod_set_value(priv->gpiod_reset, 1);
++			phy_device_reset(phydev, 1);
+ 			msleep(1);
+-			gpiod_set_value(priv->gpiod_reset, 0);
++			phy_device_reset(phydev, 0);
+ 			msleep(1);
+ 
+ 			at803x_context_restore(phydev, &context);
+diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
+index 2df7b62c1a36..8f8b7747c54b 100644
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -38,6 +38,7 @@
+ #include <linux/phy.h>
+ #include <linux/io.h>
+ #include <linux/uaccess.h>
++#include <linux/gpio/consumer.h>
+ 
+ #include <asm/irq.h>
+ 
+@@ -48,9 +49,26 @@
+ 
+ int mdiobus_register_device(struct mdio_device *mdiodev)
+ {
++	struct gpio_desc *gpiod = NULL;
++
+ 	if (mdiodev->bus->mdio_map[mdiodev->addr])
+ 		return -EBUSY;
+ 
++	/* Deassert the optional reset signal */
++	if (mdiodev->dev.of_node)
++		gpiod = fwnode_get_named_gpiod(&mdiodev->dev.of_node->fwnode,
++					       "reset-gpios", 0, GPIOD_OUT_LOW,
++					       "PHY reset");
++	if (PTR_ERR(gpiod) == -ENOENT)
++		gpiod = NULL;
++	else if (IS_ERR(gpiod))
++		return PTR_ERR(gpiod);
++
++	mdiodev->reset = gpiod;
++
++	/* Assert the reset signal again */
++	mdio_device_reset(mdiodev, 1);
++
+ 	mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
+ 
+ 	return 0;
+@@ -420,6 +438,9 @@ void mdiobus_unregister(struct mii_bus *bus)
+ 		if (!mdiodev)
+ 			continue;
+ 
++		if (mdiodev->reset)
++			gpiod_put(mdiodev->reset);
++
+ 		mdiodev->device_remove(mdiodev);
+ 		mdiodev->device_free(mdiodev);
+ 	}
+diff --git a/drivers/net/phy/mdio_device.c b/drivers/net/phy/mdio_device.c
+index e24f28924af8..75d97dd9fb28 100644
+--- a/drivers/net/phy/mdio_device.c
++++ b/drivers/net/phy/mdio_device.c
+@@ -12,6 +12,8 @@
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+ 
+ #include <linux/errno.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+@@ -114,6 +116,13 @@ void mdio_device_remove(struct mdio_device *mdiodev)
+ }
+ EXPORT_SYMBOL(mdio_device_remove);
+ 
++void mdio_device_reset(struct mdio_device *mdiodev, int value)
++{
++	if (mdiodev->reset)
++		gpiod_set_value(mdiodev->reset, value);
++}
++EXPORT_SYMBOL(mdio_device_reset);
++
+ /**
+  * mdio_probe - probe an MDIO device
+  * @dev: device to probe
+@@ -128,8 +137,16 @@ static int mdio_probe(struct device *dev)
+ 	struct mdio_driver *mdiodrv = to_mdio_driver(drv);
+ 	int err = 0;
+ 
+-	if (mdiodrv->probe)
++	if (mdiodrv->probe) {
++		/* Deassert the reset signal */
++		mdio_device_reset(mdiodev, 0);
++
+ 		err = mdiodrv->probe(mdiodev);
++		if (err) {
++			/* Assert the reset signal */
++			mdio_device_reset(mdiodev, 1);
++		}
++	}
+ 
+ 	return err;
+ }
+@@ -140,9 +157,13 @@ static int mdio_remove(struct device *dev)
+ 	struct device_driver *drv = mdiodev->dev.driver;
+ 	struct mdio_driver *mdiodrv = to_mdio_driver(drv);
+ 
+-	if (mdiodrv->remove)
++	if (mdiodrv->remove) {
+ 		mdiodrv->remove(mdiodev);
+ 
++		/* Assert the reset signal */
++		mdio_device_reset(mdiodev, 1);
++	}
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
+index fe76e2c4022a..1a0bd7e2ae7e 100644
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -632,6 +632,9 @@ int phy_device_register(struct phy_device *phydev)
+ 	if (err)
+ 		return err;
+ 
++	/* Deassert the reset signal */
++	phy_device_reset(phydev, 0);
++
+ 	/* Run all of the fixups for this PHY */
+ 	err = phy_scan_fixups(phydev);
+ 	if (err) {
+@@ -650,6 +653,9 @@ int phy_device_register(struct phy_device *phydev)
+ 	return 0;
+ 
+  out:
++	/* Assert the reset signal */
++	phy_device_reset(phydev, 1);
++
+ 	mdiobus_unregister_device(&phydev->mdio);
+ 	return err;
+ }
+@@ -666,6 +672,10 @@ EXPORT_SYMBOL(phy_device_register);
+ void phy_device_remove(struct phy_device *phydev)
+ {
+ 	device_del(&phydev->mdio.dev);
++
++	/* Assert the reset signal */
++	phy_device_reset(phydev, 1);
++
+ 	mdiobus_unregister_device(&phydev->mdio);
+ }
+ EXPORT_SYMBOL(phy_device_remove);
+@@ -849,6 +859,9 @@ int phy_init_hw(struct phy_device *phydev)
+ {
+ 	int ret = 0;
+ 
++	/* Deassert the reset signal */
++	phy_device_reset(phydev, 0);
++
+ 	if (!phydev->drv || !phydev->drv->config_init)
+ 		return 0;
+ 
+@@ -1133,6 +1146,9 @@ void phy_detach(struct phy_device *phydev)
+ 	put_device(&phydev->mdio.dev);
+ 	if (ndev_owner != bus->owner)
+ 		module_put(bus->owner);
++
++	/* Assert the reset signal */
++	phy_device_reset(phydev, 1);
+ }
+ EXPORT_SYMBOL(phy_detach);
+ 
+@@ -1842,8 +1858,16 @@ static int phy_probe(struct device *dev)
+ 	/* Set the state to READY by default */
+ 	phydev->state = PHY_READY;
+ 
+-	if (phydev->drv->probe)
++	if (phydev->drv->probe) {
++		/* Deassert the reset signal */
++		phy_device_reset(phydev, 0);
++
+ 		err = phydev->drv->probe(phydev);
++		if (err) {
++			/* Assert the reset signal */
++			phy_device_reset(phydev, 1);
++		}
++	}
+ 
+ 	mutex_unlock(&phydev->lock);
+ 
+@@ -1860,8 +1884,12 @@ static int phy_remove(struct device *dev)
+ 	phydev->state = PHY_DOWN;
+ 	mutex_unlock(&phydev->lock);
+ 
+-	if (phydev->drv && phydev->drv->remove)
++	if (phydev->drv && phydev->drv->remove) {
+ 		phydev->drv->remove(phydev);
++
++		/* Assert the reset signal */
++		phy_device_reset(phydev, 1);
++	}
+ 	phydev->drv = NULL;
+ 
+ 	return 0;
+diff --git a/include/linux/mdio.h b/include/linux/mdio.h
+index ca08ab16ecdc..92d4e55ffe67 100644
+--- a/include/linux/mdio.h
++++ b/include/linux/mdio.h
+@@ -12,6 +12,7 @@
+ #include <uapi/linux/mdio.h>
+ #include <linux/mod_devicetable.h>
+ 
++struct gpio_desc;
+ struct mii_bus;
+ 
+ /* Multiple levels of nesting are possible. However typically this is
+@@ -39,6 +40,7 @@ struct mdio_device {
+ 	/* Bus address of the MDIO device (0-31) */
+ 	int addr;
+ 	int flags;
++	struct gpio_desc *reset;
+ };
+ #define to_mdio_device(d) container_of(d, struct mdio_device, dev)
+ 
+@@ -71,6 +73,7 @@ void mdio_device_free(struct mdio_device *mdiodev);
+ struct mdio_device *mdio_device_create(struct mii_bus *bus, int addr);
+ int mdio_device_register(struct mdio_device *mdiodev);
+ void mdio_device_remove(struct mdio_device *mdiodev);
++void mdio_device_reset(struct mdio_device *mdiodev, int value);
+ int mdio_driver_register(struct mdio_driver *drv);
+ void mdio_driver_unregister(struct mdio_driver *drv);
+ int mdio_device_bus_match(struct device *dev, struct device_driver *drv);
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index efc04c2d92c9..9129627c6498 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -840,6 +840,11 @@ int phy_aneg_done(struct phy_device *phydev);
+ int phy_stop_interrupts(struct phy_device *phydev);
+ int phy_restart_aneg(struct phy_device *phydev);
+ 
++static inline void phy_device_reset(struct phy_device *phydev, int value)
++{
++	mdio_device_reset(&phydev->mdio, value);
++}
++
+ static inline int phy_read_status(struct phy_device *phydev)
+ {
+ 	if (!phydev->drv)
+-- 
+2.19.0
+
diff --git a/patches/0758-net-mdio-Only-perform-gpio-reset-for-PHYs.patch b/patches/0758-net-mdio-Only-perform-gpio-reset-for-PHYs.patch
new file mode 100644
index 00000000000000..ebfaca3893f7f9
--- /dev/null
+++ b/patches/0758-net-mdio-Only-perform-gpio-reset-for-PHYs.patch
@@ -0,0 +1,70 @@
+From 7f5b6ec8d8fa7babd74434b6608d4add70196440 Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Tue, 2 Jan 2018 17:40:26 +0100
+Subject: [PATCH 0758/1795] net: mdio: Only perform gpio reset for PHYs
+
+Ethernet switch on the MDIO bus have historically performed their own
+handling of the GPIO reset line. The resent patch to have the MDIO
+core handle the reset has broken the switch drivers, in that they
+cannot claim the GPIO. Some switch drivers need more control over the
+GPIO line than what the MDIO core provides. So restore the historical
+behaviour by only performing a reset of PHYs, not switches.
+
+Fixes: bafbdd527d56 ("phylib: Add device reset GPIO support")
+Reported-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit ee7e16b66a766e8f922aafe5edf9353b9f37a424)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/mdio_bus.c | 21 +++++++++++++++++----
+ 1 file changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
+index 8f8b7747c54b..9440349ffbaf 100644
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -47,13 +47,10 @@
+ 
+ #include "mdio-boardinfo.h"
+ 
+-int mdiobus_register_device(struct mdio_device *mdiodev)
++static int mdiobus_register_gpiod(struct mdio_device *mdiodev)
+ {
+ 	struct gpio_desc *gpiod = NULL;
+ 
+-	if (mdiodev->bus->mdio_map[mdiodev->addr])
+-		return -EBUSY;
+-
+ 	/* Deassert the optional reset signal */
+ 	if (mdiodev->dev.of_node)
+ 		gpiod = fwnode_get_named_gpiod(&mdiodev->dev.of_node->fwnode,
+@@ -69,6 +66,22 @@ int mdiobus_register_device(struct mdio_device *mdiodev)
+ 	/* Assert the reset signal again */
+ 	mdio_device_reset(mdiodev, 1);
+ 
++	return 0;
++}
++
++int mdiobus_register_device(struct mdio_device *mdiodev)
++{
++	int err;
++
++	if (mdiodev->bus->mdio_map[mdiodev->addr])
++		return -EBUSY;
++
++	if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY) {
++		err = mdiobus_register_gpiod(mdiodev);
++		if (err)
++			return err;
++	}
++
+ 	mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0759-net-phy-Handle-not-having-GPIO-enabled-in-the-kernel.patch b/patches/0759-net-phy-Handle-not-having-GPIO-enabled-in-the-kernel.patch
new file mode 100644
index 00000000000000..7c067a8f868ac7
--- /dev/null
+++ b/patches/0759-net-phy-Handle-not-having-GPIO-enabled-in-the-kernel.patch
@@ -0,0 +1,40 @@
+From 11819413b999ec3689792a9e0469eeb15e5aeff9 Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Mon, 5 Feb 2018 19:17:23 +0100
+Subject: [PATCH 0759/1795] net: phy: Handle not having GPIO enabled in the
+ kernel
+
+If CONFIG_GPIOLIB is disabled, fwnode_get_named_gpiod() becomes a stub
+function, which return -ENOSYS. Handle this in the same way as
+-ENOENT, i.e. assume there is no GPIO used to reset the PHYs.
+
+Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
+Tested-by: Christian Zigotzky <chzigotzky@xenosoft.de>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Fixes: bafbdd527d56 ("phylib: Add device reset GPIO support")
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit a56c69803f5a2c1cab0228cf1aebf76821ace965)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/phy/mdio_bus.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
+index 9440349ffbaf..a9c17c20d0b1 100644
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -56,7 +56,8 @@ static int mdiobus_register_gpiod(struct mdio_device *mdiodev)
+ 		gpiod = fwnode_get_named_gpiod(&mdiodev->dev.of_node->fwnode,
+ 					       "reset-gpios", 0, GPIOD_OUT_LOW,
+ 					       "PHY reset");
+-	if (PTR_ERR(gpiod) == -ENOENT)
++	if (PTR_ERR(gpiod) == -ENOENT ||
++	    PTR_ERR(gpiod) == -ENOSYS)
+ 		gpiod = NULL;
+ 	else if (IS_ERR(gpiod))
+ 		return PTR_ERR(gpiod);
+-- 
+2.19.0
+
diff --git a/patches/0760-PCI-OF-Add-generic-function-to-parse-and-allocate-PC.patch b/patches/0760-PCI-OF-Add-generic-function-to-parse-and-allocate-PC.patch
new file mode 100644
index 00000000000000..0aa9b833223809
--- /dev/null
+++ b/patches/0760-PCI-OF-Add-generic-function-to-parse-and-allocate-PC.patch
@@ -0,0 +1,189 @@
+From 368a7ca08c38fd107a4afe5e49639d3338b13d3e Mon Sep 17 00:00:00 2001
+From: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+Date: Tue, 30 Jan 2018 21:56:50 +0100
+Subject: [PATCH 0760/1795] PCI: OF: Add generic function to parse and allocate
+ PCI resources
+
+The patch moves the gen_pci_parse_request_of_pci_ranges() function from
+drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
+common source code between PCI host drivers.
+
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+(cherry picked from commit 3a8f77e48666a39adb3ac4d5ce8261563e039e31)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/pci/host/pci-host-common.c
+	drivers/pci/of.c
+---
+ drivers/pci/host/pci-host-common.c | 49 ++--------------------------
+ drivers/pci/of.c                   | 51 ++++++++++++++++++++++++++++++
+ include/linux/pci.h                |  9 ++++++
+ 3 files changed, 62 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/host/pci-host-common.c
+index eabaaa325bd2..a613ea310e76 100644
+--- a/drivers/pci/host/pci-host-common.c
++++ b/drivers/pci/host/pci-host-common.c
+@@ -24,50 +24,6 @@
+ #include <linux/pci-ecam.h>
+ #include <linux/platform_device.h>
+ 
+-static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
+-		       struct list_head *resources, struct resource **bus_range)
+-{
+-	int err, res_valid = 0;
+-	struct device_node *np = dev->of_node;
+-	resource_size_t iobase;
+-	struct resource_entry *win, *tmp;
+-
+-	err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
+-	if (err)
+-		return err;
+-
+-	err = devm_request_pci_bus_resources(dev, resources);
+-	if (err)
+-		return err;
+-
+-	resource_list_for_each_entry_safe(win, tmp, resources) {
+-		struct resource *res = win->res;
+-
+-		switch (resource_type(res)) {
+-		case IORESOURCE_IO:
+-			err = devm_pci_remap_iospace(dev, res, iobase);
+-			if (err) {
+-				dev_warn(dev, "error %d: failed to map resource %pR\n",
+-					 err, res);
+-				resource_list_destroy_entry(win);
+-			}
+-			break;
+-		case IORESOURCE_MEM:
+-			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
+-			break;
+-		case IORESOURCE_BUS:
+-			*bus_range = res;
+-			break;
+-		}
+-	}
+-
+-	if (res_valid)
+-		return 0;
+-
+-	dev_err(dev, "non-prefetchable memory resource required\n");
+-	return -EINVAL;
+-}
+-
+ static void gen_pci_unmap_cfg(void *ptr)
+ {
+ 	pci_ecam_free((struct pci_config_window *)ptr);
+@@ -82,9 +38,9 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
+ 	struct pci_config_window *cfg;
+ 
+ 	/* Parse our PCI ranges and request their resources */
+-	err = gen_pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
++	err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
+ 	if (err)
+-		goto err_out;
++		return ERR_PTR(err);
+ 
+ 	err = of_address_to_resource(dev->of_node, 0, &cfgres);
+ 	if (err) {
+@@ -135,7 +91,6 @@ int pci_host_common_probe(struct platform_device *pdev,
+ 	of_pci_check_probe_only();
+ 
+ 	/* Parse and map our Configuration Space windows */
+-	INIT_LIST_HEAD(&resources);
+ 	cfg = gen_pci_init(dev, &resources, ops);
+ 	if (IS_ERR(cfg))
+ 		return PTR_ERR(cfg);
+diff --git a/drivers/pci/of.c b/drivers/pci/of.c
+index e112da11630e..068fa8dbb967 100644
+--- a/drivers/pci/of.c
++++ b/drivers/pci/of.c
+@@ -88,3 +88,54 @@ struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus)
+ 	return NULL;
+ #endif
+ }
++
++int pci_parse_request_of_pci_ranges(struct device *dev,
++				    struct list_head *resources,
++				    struct resource **bus_range)
++{
++	int err, res_valid = 0;
++	struct device_node *np = dev->of_node;
++	resource_size_t iobase;
++	struct resource_entry *win, *tmp;
++
++	INIT_LIST_HEAD(resources);
++	err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
++	if (err)
++		return err;
++
++	err = devm_request_pci_bus_resources(dev, resources);
++	if (err)
++		goto out_release_res;
++
++	resource_list_for_each_entry_safe(win, tmp, resources) {
++		struct resource *res = win->res;
++
++		switch (resource_type(res)) {
++		case IORESOURCE_IO:
++			err = devm_pci_remap_iospace(dev, res, iobase);
++			if (err) {
++				dev_warn(dev, "error %d: failed to map resource %pR\n",
++					 err, res);
++				resource_list_destroy_entry(win);
++			}
++			break;
++		case IORESOURCE_MEM:
++			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
++			break;
++		case IORESOURCE_BUS:
++			if (bus_range)
++				*bus_range = res;
++			break;
++		}
++	}
++
++	if (res_valid)
++		return 0;
++
++	dev_err(dev, "non-prefetchable memory resource required\n");
++	err = -EINVAL;
++
++ out_release_res:
++	pci_free_resource_list(resources);
++	return err;
++}
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index b1abbcc614cf..cf3cd98f5616 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -2193,6 +2193,9 @@ void pci_release_of_node(struct pci_dev *dev);
+ void pci_set_bus_of_node(struct pci_bus *bus);
+ void pci_release_bus_of_node(struct pci_bus *bus);
+ struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
++int pci_parse_request_of_pci_ranges(struct device *dev,
++				    struct list_head *resources,
++				    struct resource **bus_range);
+ 
+ /* Arch may override this (weak) */
+ struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
+@@ -2217,6 +2220,12 @@ static inline struct device_node *
+ pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
+ static inline struct irq_domain *
+ pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
++static inline int pci_parse_request_of_pci_ranges(struct device *dev,
++						  struct list_head *resources,
++						  struct resource **bus_range)
++{
++	return -EINVAL;
++}
+ #endif  /* CONFIG_OF */
+ 
+ #ifdef CONFIG_ACPI
+-- 
+2.19.0
+
diff --git a/patches/0761-PM-domains-Don-t-skip-driver-s-suspend-resume_noirq-.patch b/patches/0761-PM-domains-Don-t-skip-driver-s-suspend-resume_noirq-.patch
new file mode 100644
index 00000000000000..db3b7c64b22055
--- /dev/null
+++ b/patches/0761-PM-domains-Don-t-skip-driver-s-suspend-resume_noirq-.patch
@@ -0,0 +1,110 @@
+From 40afee53a7b5f1660d217aa6b341bce2127928c0 Mon Sep 17 00:00:00 2001
+From: Ulf Hansson <ulf.hansson@linaro.org>
+Date: Wed, 10 Jan 2018 21:31:56 +0100
+Subject: [PATCH 0761/1795] PM / domains: Don't skip driver's
+ ->suspend|resume_noirq() callbacks
+
+Commit 10da65423fdb (PM / Domains: Call driver's noirq callbacks)
+started to respect driver's noirq callbacks, but while doing that it
+also introduced a few potential problems.
+
+More precisely, in genpd_finish_suspend() and genpd_resume_noirq()
+the noirq callbacks at the driver level should be invoked, no matter
+of whether dev->power.wakeup_path is set or not.
+
+Additionally, the commit in question also made genpd_resume_noirq()
+to ignore the return value from pm_runtime_force_resume().
+
+Let's fix both these issues!
+
+Fixes: 10da65423fdb (PM / Domains: Call driver's noirq callbacks)
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit a935424bb658f9ca37eb5e94119b857998341356)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/base/power/domain.c | 30 +++++++++++++++++-------------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
+index 104f3d928b13..68bf1ddfb7c7 100644
+--- a/drivers/base/power/domain.c
++++ b/drivers/base/power/domain.c
+@@ -940,15 +940,12 @@ static int pm_genpd_prepare(struct device *dev)
+ static int genpd_finish_suspend(struct device *dev, bool poweroff)
+ {
+ 	struct generic_pm_domain *genpd;
+-	int ret;
++	int ret = 0;
+ 
+ 	genpd = dev_to_genpd(dev);
+ 	if (IS_ERR(genpd))
+ 		return -EINVAL;
+ 
+-	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
+-		return 0;
+-
+ 	if (poweroff)
+ 		ret = pm_generic_poweroff_noirq(dev);
+ 	else
+@@ -956,10 +953,18 @@ static int genpd_finish_suspend(struct device *dev, bool poweroff)
+ 	if (ret)
+ 		return ret;
+ 
++	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
++		return 0;
++
+ 	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+ 		ret = pm_runtime_force_suspend(dev);
+-		if (ret)
++		if (ret) {
++			if (poweroff)
++				pm_generic_restore_noirq(dev);
++			else
++				pm_generic_resume_noirq(dev);
+ 			return ret;
++		}
+ 	}
+ 
+ 	genpd_lock(genpd);
+@@ -993,7 +998,7 @@ static int pm_genpd_suspend_noirq(struct device *dev)
+ static int pm_genpd_resume_noirq(struct device *dev)
+ {
+ 	struct generic_pm_domain *genpd;
+-	int ret = 0;
++	int ret;
+ 
+ 	dev_dbg(dev, "%s()\n", __func__);
+ 
+@@ -1002,21 +1007,20 @@ static int pm_genpd_resume_noirq(struct device *dev)
+ 		return -EINVAL;
+ 
+ 	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
+-		return 0;
++		return pm_generic_resume_noirq(dev);
+ 
+ 	genpd_lock(genpd);
+ 	genpd_sync_power_on(genpd, true, 0);
+ 	genpd->suspended_count--;
+ 	genpd_unlock(genpd);
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start)
++	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+ 		ret = pm_runtime_force_resume(dev);
++		if (ret)
++			return ret;
++	}
+ 
+-	ret = pm_generic_resume_noirq(dev);
+-	if (ret)
+-		return ret;
+-
+-	return ret;
++	return pm_generic_resume_noirq(dev);
+ }
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/0762-PM-genpd-Stop-start-devices-without-pm_runtime_force.patch b/patches/0762-PM-genpd-Stop-start-devices-without-pm_runtime_force.patch
new file mode 100644
index 00000000000000..d035c9a9b57f3e
--- /dev/null
+++ b/patches/0762-PM-genpd-Stop-start-devices-without-pm_runtime_force.patch
@@ -0,0 +1,185 @@
+From 40f0f10ac2e53b989e023caf16f0d3f4ddf63564 Mon Sep 17 00:00:00 2001
+From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
+Date: Fri, 12 Jan 2018 14:10:38 +0100
+Subject: [PATCH 0762/1795] PM / genpd: Stop/start devices without
+ pm_runtime_force_suspend/resume()
+
+There are problems with calling pm_runtime_force_suspend/resume()
+to "stop" and "start" devices in genpd_finish_suspend() and
+genpd_resume_noirq() (and in analogous hibernation-specific genpd
+callbacks) after commit 122a22377a3d (PM / Domains: Stop/start
+devices during system PM suspend/resume in genpd) as those routines
+do much more than just "stopping" and "starting" devices (which was
+the stated purpose of that commit) unnecessarily and may not play
+well with system-wide PM driver callbacks.
+
+First, consider the pm_runtime_force_suspend() in
+genpd_finish_suspend().  If the current runtime PM status of the
+device is "suspended", that function most likely does the right thing
+by ignoring the device, because it should have been "stopped" already
+and whatever needed to be done to deactivate it shoud have been done.
+In turn, if the runtime PM status of the device is "active",
+genpd_runtime_suspend() is called for it (indirectly) and (1) runs
+the ->runtime_suspend callback provided by the device's driver
+(assuming no bus type with ->runtime_suspend of its own), (2) "stops"
+the device and (3) checks if the domain can be powered down, and then
+(4) the device's runtime PM status is changed to "suspended".  Out of
+the four actions above (1) is not necessary and it may be outright
+harmful, (3) is pointless and (4) is questionable.  The only
+operation that needs to be carried out here is (2).
+
+The reason why (1) is not necessary is because the system-wide
+PM callbacks provided by the device driver for the transition in
+question have been run and they should have taken care of the
+driver's part of device suspend already.  Moreover, it may be
+harmful, because the ->runtime_suspend callback may want to
+access the device which is partially suspended at that point
+and may not be responsive.  Also, system-wide PM callbacks may
+have been run already (in the previous phases of the system
+transition under way) for the device's parent or for its supplier
+devices (if any) and the device may not be accessible because of
+that.
+
+There also is no reason to do (3), because genpd_finish_suspend()
+will repeat it anyway, and (4) potentially causes confusion to ensue
+during the subsequent system transition to the working state.
+
+Consider pm_runtime_force_resume() in genpd_resume_noirq() now.
+It runs genpd_runtime_resume() for all devices with runtime PM
+status set to "suspended", which includes all of the devices
+whose runtime PM status was changed by pm_runtime_force_suspend()
+before and may include some devices already suspended when the
+pm_runtime_force_suspend() was running, which may be confusing.  The
+genpd_runtime_resume() first tries to power up the domain, which
+(again) is pointless, because genpd_resume_noirq() has done that
+already.  Then, it "starts" the device and runs the ->runtime_resume
+callback (from the driver, say) for it.  If all is well, the device
+is left with the runtime PM status set to "active".
+
+Unfortunately, running the driver's ->runtime_resume callback
+before its system-wide PM callbacks and possibly before some
+system-wide PM callbacks of the parent device's driver (let
+alone supplier drivers) is asking for trouble, especially if
+the device had been suspended before pm_runtime_force_suspend()
+ran previously or if the callbacks in question expect to be run
+back-to-back with their suspend-side counterparts.  It also should
+not be necessary, because the system-wide PM driver callbacks that
+will be invoked for the device subsequently should take care of
+resuming it just fine.
+
+[Running the driver's ->runtime_resume callback in the "noirq"
+phase of the transition to the working state may be problematic
+even for devices whose drivers do use pm_runtime_force_resume()
+in (or as) their system-wide PM callbacks if they have suppliers
+other than their parents, because it may cause the supplier to
+be resumed after the consumer in some cases.]
+
+Because of the above, modify genpd as follows:
+
+ 1. Change genpd_finish_suspend() to only "stop" devices with
+    runtime PM status set to "active" (without invoking runtime PM
+    callbacks for them, changing their runtime PM status and so on).
+
+    That doesn't change the handling of devices whose drivers use
+    pm_runtime_force_suspend/resume() in (or as) their system-wide
+    PM callbacks and addresses the issues described above for the
+    other devices.
+
+ 2. Change genpd_resume_noirq() to only "start" devices with
+    runtime PM status set to "active" (without invoking runtime PM
+    callbacks for them, changing their runtime PM status and so on).
+
+    Again, that doesn't change the handling of devices whose drivers
+    use pm_runtime_force_suspend/resume() in (or as) their system-wide
+    PM callbacks and addresses the described issues for the other
+    devices.  Devices with runtime PM status set to "suspended"
+    are not started with the assumption that they will be resumed
+    later, either by pm_runtime_force_resume() or via runtime PM.
+
+ 3. Change genpd_restore_noirq() to follow genpd_resume_noirq().
+
+    That causes devices already suspended before hibernation to be
+    left alone (which also is the case without the change) and
+    avoids running the ->runtime_resume driver callback too early
+    for the other devices.
+
+ 4. Change genpd_freeze_noirq() and genpd_thaw_noirq() in accordance
+    with the above modifications.
+
+Fixes: 122a22377a3d (PM / Domains: Stop/start devices during system PM suspend/resume in genpd)
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 17218e0092f8c7b7edce7ff08c8b23212eac7271)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/base/power/domain.c | 25 +++++++++++++++----------
+ 1 file changed, 15 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
+index 68bf1ddfb7c7..c09c437a0298 100644
+--- a/drivers/base/power/domain.c
++++ b/drivers/base/power/domain.c
+@@ -956,8 +956,9 @@ static int genpd_finish_suspend(struct device *dev, bool poweroff)
+ 	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
+ 		return 0;
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+-		ret = pm_runtime_force_suspend(dev);
++	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
++	    !pm_runtime_status_suspended(dev)) {
++		ret = genpd_stop_dev(genpd, dev);
+ 		if (ret) {
+ 			if (poweroff)
+ 				pm_generic_restore_noirq(dev);
+@@ -1014,8 +1015,9 @@ static int pm_genpd_resume_noirq(struct device *dev)
+ 	genpd->suspended_count--;
+ 	genpd_unlock(genpd);
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+-		ret = pm_runtime_force_resume(dev);
++	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
++	    !pm_runtime_status_suspended(dev)) {
++		ret = genpd_start_dev(genpd, dev);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -1047,8 +1049,9 @@ static int pm_genpd_freeze_noirq(struct device *dev)
+ 	if (ret)
+ 		return ret;
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start)
+-		ret = pm_runtime_force_suspend(dev);
++	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
++	    !pm_runtime_status_suspended(dev))
++		ret = genpd_stop_dev(genpd, dev);
+ 
+ 	return ret;
+ }
+@@ -1071,8 +1074,9 @@ static int pm_genpd_thaw_noirq(struct device *dev)
+ 	if (IS_ERR(genpd))
+ 		return -EINVAL;
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+-		ret = pm_runtime_force_resume(dev);
++	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
++	    !pm_runtime_status_suspended(dev)) {
++		ret = genpd_start_dev(genpd, dev);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -1129,8 +1133,9 @@ static int pm_genpd_restore_noirq(struct device *dev)
+ 	genpd_sync_power_on(genpd, true, 0);
+ 	genpd_unlock(genpd);
+ 
+-	if (genpd->dev_ops.stop && genpd->dev_ops.start) {
+-		ret = pm_runtime_force_resume(dev);
++	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
++	    !pm_runtime_status_suspended(dev)) {
++		ret = genpd_start_dev(genpd, dev);
+ 		if (ret)
+ 			return ret;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/0763-PM-wakeup-Add-device_set_wakeup_path-helper-to-contr.patch b/patches/0763-PM-wakeup-Add-device_set_wakeup_path-helper-to-contr.patch
new file mode 100644
index 00000000000000..b28139e9241e13
--- /dev/null
+++ b/patches/0763-PM-wakeup-Add-device_set_wakeup_path-helper-to-contr.patch
@@ -0,0 +1,71 @@
+From 9092588be8f38234cb63731713387b591db6d8bc Mon Sep 17 00:00:00 2001
+From: Ulf Hansson <ulf.hansson@linaro.org>
+Date: Tue, 2 Jan 2018 17:08:52 +0100
+Subject: [PATCH 0763/1795] PM / wakeup: Add device_set_wakeup_path() helper to
+ control wakeup path
+
+During system suspend, a driver may find that the wakeup setting is
+enabled for its device and therefore configures it to deliver system
+wakeup signals.
+
+Additionally, sometimes the driver and its device, relies on some
+further consumed resource, like an irqchip or a phy for example, to
+stay powered on, as to be able to deliver system wakeup signals.
+
+In general the driver deals with this, via raising an "enable count"
+of the consumed resource or via a subsystem specific API, like
+irq_set_irq_wake() or enable|disable_irq_wake() for an irqchip.
+However, this may not be sufficient in cases when the resource's
+device may be attached to a PM domain (genpd for example) or is
+handled by a non-trivial middle layer (PCI for example).
+
+To address cases like these, the existing ->dev.power.wakeup_path
+status flag is there to help.  As a matter of fact, genpd already
+monitors the flag during system suspend and acts accordingly.
+
+However, so far it has not been clear, if anybody else but the PM
+core is allowed to set the ->dev.power.wakeup_path status flag,
+which is required to make this work.  For this reason, introduce
+a new helper function, device_set_wakeup_path() for that.
+
+Typically, a driver that manages a resource needed in the wakeup path
+should call device_set_wakeup_path() from its ->suspend() or
+->suspend_late() callback.
+
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit cf04ce7841fabc7af0d6ee273711ec29658bee7b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/pm_wakeup.h | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
+index 4c2cba7ec1d4..4238dde0aaf0 100644
+--- a/include/linux/pm_wakeup.h
++++ b/include/linux/pm_wakeup.h
+@@ -88,6 +88,11 @@ static inline bool device_may_wakeup(struct device *dev)
+ 	return dev->power.can_wakeup && !!dev->power.wakeup;
+ }
+ 
++static inline void device_set_wakeup_path(struct device *dev)
++{
++	dev->power.wakeup_path = true;
++}
++
+ /* drivers/base/power/wakeup.c */
+ extern void wakeup_source_prepare(struct wakeup_source *ws, const char *name);
+ extern struct wakeup_source *wakeup_source_create(const char *name);
+@@ -174,6 +179,8 @@ static inline bool device_may_wakeup(struct device *dev)
+ 	return dev->power.can_wakeup && dev->power.should_wakeup;
+ }
+ 
++static inline void device_set_wakeup_path(struct device *dev) {}
++
+ static inline void __pm_stay_awake(struct wakeup_source *ws) {}
+ 
+ static inline void pm_stay_awake(struct device *dev) {}
+-- 
+2.19.0
+
diff --git a/patches/0764-dt-bindings-gpio-rcar-Correct-SoC-family-name-for-R8.patch b/patches/0764-dt-bindings-gpio-rcar-Correct-SoC-family-name-for-R8.patch
new file mode 100644
index 00000000000000..9d7fb94c61856b
--- /dev/null
+++ b/patches/0764-dt-bindings-gpio-rcar-Correct-SoC-family-name-for-R8.patch
@@ -0,0 +1,35 @@
+From fce40c6aa956bef7986f1b7ba2f131f17f582f89 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 19 Dec 2017 17:03:42 +0100
+Subject: [PATCH 0764/1795] dt-bindings: gpio: rcar: Correct SoC family name
+ for R8A7778
+
+R8A7778 is R-Car (not R-Mobile) M1.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit caa92ee84ba02aa2619b087d81a9e2e54a2235fd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index a7ac460ad657..9474138d776e 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -5,7 +5,7 @@ Required Properties:
+   - compatible: should contain one or more of the following:
+     - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+     - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
+-    - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
++    - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
+     - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
+     - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
+     - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/0765-gpio-rcar-Use-wakeup_path-i.s.o.-explicit-clock-hand.patch b/patches/0765-gpio-rcar-Use-wakeup_path-i.s.o.-explicit-clock-hand.patch
new file mode 100644
index 00000000000000..b7a241b57737de
--- /dev/null
+++ b/patches/0765-gpio-rcar-Use-wakeup_path-i.s.o.-explicit-clock-hand.patch
@@ -0,0 +1,141 @@
+From a64be665ae51b4b4aaaa034fc321367320d080f7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Feb 2018 14:55:13 +0100
+Subject: [PATCH 0765/1795] gpio: rcar: Use wakeup_path i.s.o. explicit clock
+ handling
+
+Since commit ab82fa7da4dce5c7 ("gpio: rcar: Prevent module clock disable
+when wake-up is enabled"), when a GPIO is used for wakeup, the GPIO
+block's module clock (if exists) is manually kept running during system
+suspend, to make sure the device stays active.
+
+However, this explicit clock handling is merely a workaround for a
+failure to properly communicate wakeup information to the device core.
+
+Instead, set the device's power.wakeup_path field, to indicate this
+device is part of the wakeup path.  Depending on the PM Domain's
+active_wakeup configuration, the genpd core code will keep the device
+enabled (and the clock running) during system suspend when needed.
+This allows for the removal of all explicit clock handling code from the
+driver.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 9ac79ba9c77d8595157bbdc4327919f8ee062426)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-rcar.c | 38 ++++++++++++++++----------------------
+ 1 file changed, 16 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index 2cf5f458928b..4a0dc495efcd 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -14,7 +14,6 @@
+  * GNU General Public License for more details.
+  */
+ 
+-#include <linux/clk.h>
+ #include <linux/err.h>
+ #include <linux/gpio.h>
+ #include <linux/init.h>
+@@ -37,10 +36,9 @@ struct gpio_rcar_priv {
+ 	struct platform_device *pdev;
+ 	struct gpio_chip gpio_chip;
+ 	struct irq_chip irq_chip;
+-	struct clk *clk;
+ 	unsigned int irq_parent;
++	atomic_t wakeup_path;
+ 	bool has_both_edge_trigger;
+-	bool needs_clk;
+ };
+ 
+ #define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
+@@ -186,13 +184,10 @@ static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
+ 		}
+ 	}
+ 
+-	if (!p->clk)
+-		return 0;
+-
+ 	if (on)
+-		clk_enable(p->clk);
++		atomic_inc(&p->wakeup_path);
+ 	else
+-		clk_disable(p->clk);
++		atomic_dec(&p->wakeup_path);
+ 
+ 	return 0;
+ }
+@@ -330,17 +325,14 @@ static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
+ 
+ struct gpio_rcar_info {
+ 	bool has_both_edge_trigger;
+-	bool needs_clk;
+ };
+ 
+ static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
+ 	.has_both_edge_trigger = false,
+-	.needs_clk = false,
+ };
+ 
+ static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
+ 	.has_both_edge_trigger = true,
+-	.needs_clk = true,
+ };
+ 
+ static const struct of_device_id gpio_rcar_of_table[] = {
+@@ -403,7 +395,6 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
+ 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
+ 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
+ 	p->has_both_edge_trigger = info->has_both_edge_trigger;
+-	p->needs_clk = info->needs_clk;
+ 
+ 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
+ 		dev_warn(&p->pdev->dev,
+@@ -440,16 +431,6 @@ static int gpio_rcar_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, p);
+ 
+-	p->clk = devm_clk_get(dev, NULL);
+-	if (IS_ERR(p->clk)) {
+-		if (p->needs_clk) {
+-			dev_err(dev, "unable to get clock\n");
+-			ret = PTR_ERR(p->clk);
+-			goto err0;
+-		}
+-		p->clk = NULL;
+-	}
+-
+ 	pm_runtime_enable(dev);
+ 
+ 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+@@ -531,11 +512,24 @@ static int gpio_rcar_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static int __maybe_unused gpio_rcar_suspend(struct device *dev)
++{
++	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
++
++	if (atomic_read(&p->wakeup_path))
++		device_set_wakeup_path(dev);
++
++	return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, NULL);
++
+ static struct platform_driver gpio_rcar_device_driver = {
+ 	.probe		= gpio_rcar_probe,
+ 	.remove		= gpio_rcar_remove,
+ 	.driver		= {
+ 		.name	= "gpio_rcar",
++		.pm     = &gpio_rcar_pm_ops,
+ 		.of_match_table = of_match_ptr(gpio_rcar_of_table),
+ 	}
+ };
+-- 
+2.19.0
+
diff --git a/patches/0766-clk-renesas-r8a77970-Add-LVDS-clock.patch b/patches/0766-clk-renesas-r8a77970-Add-LVDS-clock.patch
new file mode 100644
index 00000000000000..fbe69ddae5f49c
--- /dev/null
+++ b/patches/0766-clk-renesas-r8a77970-Add-LVDS-clock.patch
@@ -0,0 +1,37 @@
+From 1e6d3f82e23c1c8af51622649f9230d35274abd3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 6 Dec 2017 00:43:35 +0300
+Subject: [PATCH 0766/1795] clk: renesas: r8a77970: Add LVDS clock
+
+I seem to have omitted the LVDS clock from the R8A77970 CPG/MSSR support
+patch for some reason -- add it back...
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Fixes: 8d46e28fb5081b49 ("clk: renesas: cpg-mssr: Add R8A77970 support")
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 64082568dd1e05d349a0d9dfda2bdf6ace3f9f6c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
+index 72f98527473a..f55842917e8d 100644
+--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
+@@ -105,6 +105,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
+ 	DEF_MOD("vspd0",		 623,	R8A77970_CLK_S2D1),
+ 	DEF_MOD("csi40",		 716,	R8A77970_CLK_CSI0),
+ 	DEF_MOD("du0",			 724,	R8A77970_CLK_S2D1),
++	DEF_MOD("lvds",			 727,	R8A77970_CLK_S2D1),
+ 	DEF_MOD("vin3",			 808,	R8A77970_CLK_S2D1),
+ 	DEF_MOD("vin2",			 809,	R8A77970_CLK_S2D1),
+ 	DEF_MOD("vin1",			 810,	R8A77970_CLK_S2D1),
+-- 
+2.19.0
+
diff --git a/patches/0767-clk-renesas-mstp-Keep-wakeup-sources-active-during-s.patch b/patches/0767-clk-renesas-mstp-Keep-wakeup-sources-active-during-s.patch
new file mode 100644
index 00000000000000..5164ba2f59085b
--- /dev/null
+++ b/patches/0767-clk-renesas-mstp-Keep-wakeup-sources-active-during-s.patch
@@ -0,0 +1,42 @@
+From 7507d04fd1939a56d81969620ce2af31ab0d54cc Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 13 Oct 2017 14:22:28 +0200
+Subject: [PATCH 0767/1795] clk: renesas: mstp: Keep wakeup sources active
+ during system suspend
+
+If a device is part of the CPG/MSTP Clock Domain and to be used as a
+wakeup source, it must be kept active during system suspend.
+
+Currently this is handled in device-specific drivers by explicitly
+increasing the use count of the module clock when the device is
+configured as a wakeup source.  However, the proper way to prevent the
+device from being stopped is to inform this requirement to the genpd
+core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
+
+Note that this will only affect devices configured as wakeup sources.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 744dddcae84441b153101bc23505a1996da5e503)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-mstp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
+index c944cc421e30..858c24d4da8f 100644
+--- a/drivers/clk/renesas/clk-mstp.c
++++ b/drivers/clk/renesas/clk-mstp.c
+@@ -341,7 +341,7 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
+ 		return;
+ 
+ 	pd->name = np->name;
+-	pd->flags = GENPD_FLAG_PM_CLK;
++	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ 	pd->attach_dev = cpg_mstp_attach_dev;
+ 	pd->detach_dev = cpg_mstp_detach_dev;
+ 	pm_genpd_init(pd, &pm_domain_always_on_gov, false);
+-- 
+2.19.0
+
diff --git a/patches/0768-clk-renesas-cpg-mssr-Keep-wakeup-sources-active-duri.patch b/patches/0768-clk-renesas-cpg-mssr-Keep-wakeup-sources-active-duri.patch
new file mode 100644
index 00000000000000..cd7604704292d9
--- /dev/null
+++ b/patches/0768-clk-renesas-cpg-mssr-Keep-wakeup-sources-active-duri.patch
@@ -0,0 +1,42 @@
+From 4b39af206e691b29c808ec87fe4976006b3168e5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 13 Oct 2017 14:24:22 +0200
+Subject: [PATCH 0768/1795] clk: renesas: cpg-mssr: Keep wakeup sources active
+ during system suspend
+
+If a device is part of the CPG/MSSR Clock Domain and to be used as a
+wakeup source, it must be kept active during system suspend.
+
+Currently this is handled in device-specific drivers by explicitly
+increasing the use count of the module clock when the device is
+configured as a wakeup source.  However, the proper way to prevent the
+device from being stopped is to inform this requirement to the genpd
+core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
+
+Note that this will only affect devices configured as wakeup sources.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 7aff266552d6042b43d3d5a9b13f0009ef862033)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/renesas-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 998a2f4b5db5..2c9988fef656 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -514,7 +514,7 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
+ 
+ 	genpd = &pd->genpd;
+ 	genpd->name = np->name;
+-	genpd->flags = GENPD_FLAG_PM_CLK;
++	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ 	genpd->attach_dev = cpg_mssr_attach_dev;
+ 	genpd->detach_dev = cpg_mssr_detach_dev;
+ 	pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+-- 
+2.19.0
+
diff --git a/patches/0769-clk-renesas-r8a7796-Add-FDP-clock.patch b/patches/0769-clk-renesas-r8a7796-Add-FDP-clock.patch
new file mode 100644
index 00000000000000..d67b822eebc316
--- /dev/null
+++ b/patches/0769-clk-renesas-r8a7796-Add-FDP-clock.patch
@@ -0,0 +1,35 @@
+From a680903f31890b79c1d7306fb26575829872bea5 Mon Sep 17 00:00:00 2001
+From: ABE Hiroshige <hiroshige.abe.zc@renesas.com>
+Date: Thu, 14 Dec 2017 22:50:55 +0900
+Subject: [PATCH 0769/1795] clk: renesas: r8a7796: Add FDP clock
+
+This patch adds FDP1-0 clock to the R8A7796 SoC.
+
+Signed-off-by: ABE Hiroshige <hiroshige.abe.zc@renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[geert: s/fdp0/fdp1-0/]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+(cherry picked from commit a115f6362cee01813c66e10e397b25f2a06aecfb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+index b3767472088a..41e29734126b 100644
+--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+@@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
+ };
+ 
+ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
++	DEF_MOD("fdp1-0",		 119,	R8A7796_CLK_S0D1),
+ 	DEF_MOD("scif5",		 202,	R8A7796_CLK_S3D4),
+ 	DEF_MOD("scif4",		 203,	R8A7796_CLK_S3D4),
+ 	DEF_MOD("scif3",		 204,	R8A7796_CLK_S3D4),
+-- 
+2.19.0
+
diff --git a/patches/0770-i2c-Switch-to-using-gpiod-interface-for-gpio-bus-rec.patch b/patches/0770-i2c-Switch-to-using-gpiod-interface-for-gpio-bus-rec.patch
new file mode 100644
index 00000000000000..6c9b6610ff653c
--- /dev/null
+++ b/patches/0770-i2c-Switch-to-using-gpiod-interface-for-gpio-bus-rec.patch
@@ -0,0 +1,120 @@
+From b56e31cdfff3cde13627059f2d52afb8290b8cd8 Mon Sep 17 00:00:00 2001
+From: Phil Reid <preid@electromag.com.au>
+Date: Thu, 2 Nov 2017 10:40:24 +0800
+Subject: [PATCH 0770/1795] i2c: Switch to using gpiod interface for gpio bus
+ recovery
+
+Currently the i2c gpio recovery code uses gpio integer interface
+instead of the gpiod. This change switch the core code to use
+the gpiod while still retaining compatibility with the gpio integer
+interface. This will allow individual driver to be updated and tested
+individual to switch to using the gpiod interface.
+
+Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 3991c5c80beaf7eb9bce61e0b2f8f449e351a38e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 21 +++++++++++++++++----
+ include/linux/i2c.h         |  4 ++++
+ 2 files changed, 21 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index bdab78795d1e..5745345f6a9e 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -133,17 +133,17 @@ static int i2c_device_uevent(struct device *dev, struct kobj_uevent_env *env)
+ /* i2c bus recovery routines */
+ static int get_scl_gpio_value(struct i2c_adapter *adap)
+ {
+-	return gpio_get_value(adap->bus_recovery_info->scl_gpio);
++	return gpiod_get_value_cansleep(adap->bus_recovery_info->scl_gpiod);
+ }
+ 
+ static void set_scl_gpio_value(struct i2c_adapter *adap, int val)
+ {
+-	gpio_set_value(adap->bus_recovery_info->scl_gpio, val);
++	gpiod_set_value_cansleep(adap->bus_recovery_info->scl_gpiod, val);
+ }
+ 
+ static int get_sda_gpio_value(struct i2c_adapter *adap)
+ {
+-	return gpio_get_value(adap->bus_recovery_info->sda_gpio);
++	return gpiod_get_value_cansleep(adap->bus_recovery_info->sda_gpiod);
+ }
+ 
+ static int i2c_get_gpios_for_recovery(struct i2c_adapter *adap)
+@@ -158,6 +158,7 @@ static int i2c_get_gpios_for_recovery(struct i2c_adapter *adap)
+ 		dev_warn(dev, "Can't get SCL gpio: %d\n", bri->scl_gpio);
+ 		return ret;
+ 	}
++	bri->scl_gpiod = gpio_to_desc(bri->scl_gpio);
+ 
+ 	if (bri->get_sda) {
+ 		if (gpio_request_one(bri->sda_gpio, GPIOF_IN, "i2c-sda")) {
+@@ -166,6 +167,7 @@ static int i2c_get_gpios_for_recovery(struct i2c_adapter *adap)
+ 					bri->sda_gpio);
+ 			bri->get_sda = NULL;
+ 		}
++		bri->sda_gpiod = gpio_to_desc(bri->sda_gpio);
+ 	}
+ 
+ 	return ret;
+@@ -175,10 +177,13 @@ static void i2c_put_gpios_for_recovery(struct i2c_adapter *adap)
+ {
+ 	struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
+ 
+-	if (bri->get_sda)
++	if (bri->get_sda) {
+ 		gpio_free(bri->sda_gpio);
++		bri->sda_gpiod = NULL;
++	}
+ 
+ 	gpio_free(bri->scl_gpio);
++	bri->scl_gpiod = NULL;
+ }
+ 
+ /*
+@@ -276,6 +281,14 @@ static void i2c_init_recovery(struct i2c_adapter *adap)
+ 		goto err;
+ 	}
+ 
++	if (bri->scl_gpiod && bri->recover_bus == i2c_generic_scl_recovery) {
++		bri->get_scl = get_scl_gpio_value;
++		bri->set_scl = set_scl_gpio_value;
++		if (bri->sda_gpiod)
++			bri->get_sda = get_sda_gpio_value;
++		return;
++	}
++
+ 	/* Generic GPIO recovery */
+ 	if (bri->recover_bus == i2c_generic_gpio_recovery) {
+ 		if (!gpio_is_valid(bri->scl_gpio)) {
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index 1e99342f180f..3f74ad12d7d0 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -497,6 +497,8 @@ struct i2c_timings {
+  *	may configure padmux here for SDA/SCL line or something else they want.
+  * @scl_gpio: gpio number of the SCL line. Only required for GPIO recovery.
+  * @sda_gpio: gpio number of the SDA line. Only required for GPIO recovery.
++ * @scl_gpiod: gpiod of the SCL line. Only required for GPIO recovery.
++ * @sda_gpiod: gpiod of the SDA line. Only required for GPIO recovery.
+  */
+ struct i2c_bus_recovery_info {
+ 	int (*recover_bus)(struct i2c_adapter *);
+@@ -511,6 +513,8 @@ struct i2c_bus_recovery_info {
+ 	/* gpio recovery */
+ 	int scl_gpio;
+ 	int sda_gpio;
++	struct gpio_desc *scl_gpiod;
++	struct gpio_desc *sda_gpiod;
+ };
+ 
+ int i2c_recover_bus(struct i2c_adapter *adap);
+-- 
+2.19.0
+
diff --git a/patches/0771-i2c-make-kerneldoc-about-bus-recovery-more-precise.patch b/patches/0771-i2c-make-kerneldoc-about-bus-recovery-more-precise.patch
new file mode 100644
index 00000000000000..5b14c3aefcdac7
--- /dev/null
+++ b/patches/0771-i2c-make-kerneldoc-about-bus-recovery-more-precise.patch
@@ -0,0 +1,44 @@
+From cab4f273fd670a1a9686e27ace9f526e64ec2379 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:54 +0100
+Subject: [PATCH 0771/1795] i2c: make kerneldoc about bus recovery more precise
+
+"Used internally" is vague. What it actually means is that those fields
+are populated by the core if valid GPIOs are provided. Change the
+comments to reflect that.
+
+Tested-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 766a4f27f328979c10efd7272b05261166296435)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/i2c.h | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index 3f74ad12d7d0..294adee26d79 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -485,12 +485,12 @@ struct i2c_timings {
+  * @recover_bus: Recover routine. Either pass driver's recover_bus() routine, or
+  *	i2c_generic_scl_recovery() or i2c_generic_gpio_recovery().
+  * @get_scl: This gets current value of SCL line. Mandatory for generic SCL
+- *      recovery. Used internally for generic GPIO recovery.
+- * @set_scl: This sets/clears SCL line. Mandatory for generic SCL recovery. Used
+- *      internally for generic GPIO recovery.
++ *      recovery. Populated internally for generic GPIO recovery.
++ * @set_scl: This sets/clears the SCL line. Mandatory for generic SCL recovery.
++ *      Populated internally for generic GPIO recovery.
+  * @get_sda: This gets current value of SDA line. Optional for generic SCL
+- *      recovery. Used internally, if sda_gpio is a valid GPIO, for generic GPIO
+- *      recovery.
++ *      recovery. Populated internally, if sda_gpio is a valid GPIO, for generic
++ *      GPIO recovery.
+  * @prepare_recovery: This will be called before starting recovery. Platform may
+  *	configure padmux here for SDA/SCL line or something else they want.
+  * @unprepare_recovery: This will be called after completing recovery. Platform
+-- 
+2.19.0
+
diff --git a/patches/0772-i2c-add-identifier-in-declarations-for-i2c_bus_recov.patch b/patches/0772-i2c-add-identifier-in-declarations-for-i2c_bus_recov.patch
new file mode 100644
index 00000000000000..d9e3fa3b063849
--- /dev/null
+++ b/patches/0772-i2c-add-identifier-in-declarations-for-i2c_bus_recov.patch
@@ -0,0 +1,46 @@
+From 8862f18a6d56c68eb8017b8f2fec3f53d6d2be36 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:55 +0100
+Subject: [PATCH 0772/1795] i2c: add identifier in declarations for
+ i2c_bus_recovery
+
+No reason to have them undefined, so let's add them.
+
+Tested-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 6c92204e446694306198c7c394f3692bde46b696)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/i2c.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index 294adee26d79..c4a8788ff005 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -501,14 +501,14 @@ struct i2c_timings {
+  * @sda_gpiod: gpiod of the SDA line. Only required for GPIO recovery.
+  */
+ struct i2c_bus_recovery_info {
+-	int (*recover_bus)(struct i2c_adapter *);
++	int (*recover_bus)(struct i2c_adapter *adap);
+ 
+-	int (*get_scl)(struct i2c_adapter *);
+-	void (*set_scl)(struct i2c_adapter *, int val);
+-	int (*get_sda)(struct i2c_adapter *);
++	int (*get_scl)(struct i2c_adapter *adap);
++	void (*set_scl)(struct i2c_adapter *adap, int val);
++	int (*get_sda)(struct i2c_adapter *adap);
+ 
+-	void (*prepare_recovery)(struct i2c_adapter *);
+-	void (*unprepare_recovery)(struct i2c_adapter *);
++	void (*prepare_recovery)(struct i2c_adapter *adap);
++	void (*unprepare_recovery)(struct i2c_adapter *adap);
+ 
+ 	/* gpio recovery */
+ 	int scl_gpio;
+-- 
+2.19.0
+
diff --git a/patches/0773-i2c-add-set_sda-to-bus_recovery_info.patch b/patches/0773-i2c-add-set_sda-to-bus_recovery_info.patch
new file mode 100644
index 00000000000000..253ebfdb7ff3ce
--- /dev/null
+++ b/patches/0773-i2c-add-set_sda-to-bus_recovery_info.patch
@@ -0,0 +1,79 @@
+From 38bb23ab01aceeb75e270ff13d669c64b50e0d5c Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:56 +0100
+Subject: [PATCH 0773/1795] i2c: add 'set_sda' to bus_recovery_info
+
+This will be needed when we want to create STOP conditions, too, later.
+Create the needed fields and populate them for the GPIO case if the GPIO
+is set to output.
+
+Tested-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 8092178ffe67dbd1f987e2e308e871c774774a16)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/i2c/i2c-core-base.c
+---
+ drivers/i2c/i2c-core-base.c | 11 ++++++++++-
+ include/linux/i2c.h         |  4 ++++
+ 2 files changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 5745345f6a9e..90aeeea84095 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -186,6 +186,11 @@ static void i2c_put_gpios_for_recovery(struct i2c_adapter *adap)
+ 	bri->scl_gpiod = NULL;
+ }
+ 
++static void set_sda_gpio_value(struct i2c_adapter *adap, int val)
++{
++	gpiod_set_value_cansleep(adap->bus_recovery_info->sda_gpiod, val);
++}
++
+ /*
+  * We are generating clock pulses. ndelay() determines durating of clk pulses.
+  * We will generate clock with rate 100 KHz and so duration of both clock levels
+@@ -284,8 +289,12 @@ static void i2c_init_recovery(struct i2c_adapter *adap)
+ 	if (bri->scl_gpiod && bri->recover_bus == i2c_generic_scl_recovery) {
+ 		bri->get_scl = get_scl_gpio_value;
+ 		bri->set_scl = set_scl_gpio_value;
+-		if (bri->sda_gpiod)
++		if (bri->sda_gpiod) {
+ 			bri->get_sda = get_sda_gpio_value;
++			/* FIXME: add proper flag instead of '0' once available */
++			if (gpiod_get_direction(bri->sda_gpiod) == 0)
++				bri->set_sda = set_sda_gpio_value;
++		}
+ 		return;
+ 	}
+ 
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index c4a8788ff005..fef505ecab2b 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -491,6 +491,9 @@ struct i2c_timings {
+  * @get_sda: This gets current value of SDA line. Optional for generic SCL
+  *      recovery. Populated internally, if sda_gpio is a valid GPIO, for generic
+  *      GPIO recovery.
++ * @set_sda: This sets/clears the SDA line. Optional for generic SCL recovery.
++ *	Populated internally, if sda_gpio is a valid GPIO, for generic GPIO
++ *	recovery.
+  * @prepare_recovery: This will be called before starting recovery. Platform may
+  *	configure padmux here for SDA/SCL line or something else they want.
+  * @unprepare_recovery: This will be called after completing recovery. Platform
+@@ -506,6 +509,7 @@ struct i2c_bus_recovery_info {
+ 	int (*get_scl)(struct i2c_adapter *adap);
+ 	void (*set_scl)(struct i2c_adapter *adap, int val);
+ 	int (*get_sda)(struct i2c_adapter *adap);
++	void (*set_sda)(struct i2c_adapter *adap, int val);
+ 
+ 	void (*prepare_recovery)(struct i2c_adapter *adap);
+ 	void (*unprepare_recovery)(struct i2c_adapter *adap);
+-- 
+2.19.0
+
diff --git a/patches/0774-i2c-ensure-SDA-is-released-in-recovery-if-SDA-is-con.patch b/patches/0774-i2c-ensure-SDA-is-released-in-recovery-if-SDA-is-con.patch
new file mode 100644
index 00000000000000..bc9bcf7120fec3
--- /dev/null
+++ b/patches/0774-i2c-ensure-SDA-is-released-in-recovery-if-SDA-is-con.patch
@@ -0,0 +1,35 @@
+From 82d1221dd8caae9115b1d283f41c00da8827638e Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:57 +0100
+Subject: [PATCH 0774/1795] i2c: ensure SDA is released in recovery if SDA is
+ controllable
+
+If we have a function to control SDA, we should ensure that SDA is not
+held down by us. So, release the GPIO in this case.
+
+Tested-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 72b08fcc15dc6a2d211880e4dc7cf5314e9ab750)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 90aeeea84095..1b67768f01b2 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -208,6 +208,8 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 		bri->prepare_recovery(adap);
+ 
+ 	bri->set_scl(adap, val);
++	if (bri->set_sda)
++		bri->set_sda(adap, 1);
+ 	ndelay(RECOVERY_NDELAY);
+ 
+ 	/*
+-- 
+2.19.0
+
diff --git a/patches/0775-i2c-send-STOP-after-successful-bus-recovery.patch b/patches/0775-i2c-send-STOP-after-successful-bus-recovery.patch
new file mode 100644
index 00000000000000..e8aeba57161bb2
--- /dev/null
+++ b/patches/0775-i2c-send-STOP-after-successful-bus-recovery.patch
@@ -0,0 +1,44 @@
+From 582a4447399c7e6f653df70f35b80777a906ce88 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:58 +0100
+Subject: [PATCH 0775/1795] i2c: send STOP after successful bus recovery
+
+If we managed to get a client release SDA again, send a STOP afterwards
+to make sure we have a consistent state on the bus again.
+
+Tested-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 2806e6ad77c71dd2538cb698aad476e8cf3af004)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 1b67768f01b2..b9f39122a059 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -238,6 +238,18 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 	if (bri->get_sda && !bri->get_sda(adap))
+ 		ret = -EBUSY;
+ 
++	/* If all went well, send STOP for a sane bus state. */
++	if (ret == 0 && bri->set_sda) {
++		bri->set_scl(adap, 0);
++		ndelay(RECOVERY_NDELAY / 2);
++		bri->set_sda(adap, 0);
++		ndelay(RECOVERY_NDELAY / 2);
++		bri->set_scl(adap, 1);
++		ndelay(RECOVERY_NDELAY / 2);
++		bri->set_sda(adap, 1);
++		ndelay(RECOVERY_NDELAY / 2);
++	}
++
+ 	if (bri->unprepare_recovery)
+ 		bri->unprepare_recovery(adap);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0776-i2c-core-fix-compile-issue-related-to-incorrect-gpio.patch b/patches/0776-i2c-core-fix-compile-issue-related-to-incorrect-gpio.patch
new file mode 100644
index 00000000000000..e197cc2ac80406
--- /dev/null
+++ b/patches/0776-i2c-core-fix-compile-issue-related-to-incorrect-gpio.patch
@@ -0,0 +1,38 @@
+From 93ddef2b562af51470f2066c6396721cf4f86c15 Mon Sep 17 00:00:00 2001
+From: Phil Reid <preid@electromag.com.au>
+Date: Tue, 28 Nov 2017 11:09:10 +0800
+Subject: [PATCH 0776/1795] i2c: core: fix compile issue related to incorrect
+ gpio header
+
+The correct header to include for the gpiod interface is
+<linux/gpio/consumer.h>.
+
+Fixes: 3991c5c80beaf7eb9 ("i2c: Switch to using gpiod interface for gpio bus recovery")
+Signed-off-by: Phil Reid <preid@electromag.com.au>
+Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 10c9ef045a7e19e9fd4c829c7321f9d2048808c0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/i2c/i2c-core-base.c
+---
+ drivers/i2c/i2c-core-base.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index b9f39122a059..268f12f421af 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -28,6 +28,7 @@
+ #include <linux/err.h>
+ #include <linux/errno.h>
+ #include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/i2c.h>
+ #include <linux/idr.h>
+ #include <linux/init.h>
+-- 
+2.19.0
+
diff --git a/patches/0777-i2c-rcar-skip-DMA-if-buffer-is-not-safe.patch b/patches/0777-i2c-rcar-skip-DMA-if-buffer-is-not-safe.patch
new file mode 100644
index 00000000000000..54360deeb6b463
--- /dev/null
+++ b/patches/0777-i2c-rcar-skip-DMA-if-buffer-is-not-safe.patch
@@ -0,0 +1,35 @@
+From c4469ce3fc1776bc3c44ad3f9087f6b542cf4db9 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 4 Nov 2017 21:20:09 +0100
+Subject: [PATCH 0777/1795] i2c: rcar: skip DMA if buffer is not safe
+
+This HW is prone to races, so it needs to setup new messages in irq
+context. That means we can't alloc bounce buffers if a message buffer is
+not DMA safe. So, in that case, simply fall back to PIO.
+
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit adbd77b589d0345cfc42f1ae0b3414e62a2bf866)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 15d764afec3b..8a2ae3e6c561 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -359,7 +359,7 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
+ 	int len;
+ 
+ 	/* Do not use DMA if it's not available or for messages < 8 bytes */
+-	if (IS_ERR(chan) || msg->len < 8)
++	if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE))
+ 		return;
+ 
+ 	if (read) {
+-- 
+2.19.0
+
diff --git a/patches/0778-i2c-rcar-implement-bus-recovery.patch b/patches/0778-i2c-rcar-implement-bus-recovery.patch
new file mode 100644
index 00000000000000..7141fc6666602c
--- /dev/null
+++ b/patches/0778-i2c-rcar-implement-bus-recovery.patch
@@ -0,0 +1,114 @@
+From a78e6a2d7068f75aefa656794e6721b874199dc4 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 9 Jan 2018 14:58:59 +0100
+Subject: [PATCH 0778/1795] i2c: rcar: implement bus recovery
+
+We can force levels of SCL and SDA, so we can use that for bus recovery.
+Note that we cannot read SDA back, because we will only get the internal
+state of the bus free detection.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 7d2c17f021c656a9429df05e27a359041c1bada8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 54 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 52 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 8a2ae3e6c561..d4b7b5380c29 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -132,6 +132,7 @@ struct rcar_i2c_priv {
+ 	int pos;
+ 	u32 icccr;
+ 	u32 flags;
++	u8 recovery_icmcr;	/* protected by adapter lock */
+ 	enum rcar_i2c_type devtype;
+ 	struct i2c_client *slave;
+ 
+@@ -158,6 +159,46 @@ static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
+ 	return readl(priv->io + reg);
+ }
+ 
++static int rcar_i2c_get_scl(struct i2c_adapter *adap)
++{
++	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
++
++	return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
++
++};
++
++static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
++{
++	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
++
++	if (val)
++		priv->recovery_icmcr |= FSCL;
++	else
++		priv->recovery_icmcr &= ~FSCL;
++
++	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
++};
++
++/* No get_sda, because the HW only reports its bus free logic, not SDA itself */
++
++static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
++{
++	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
++
++	if (val)
++		priv->recovery_icmcr |= FSDA;
++	else
++		priv->recovery_icmcr &= ~FSDA;
++
++	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
++};
++
++static struct i2c_bus_recovery_info rcar_i2c_bri = {
++	.get_scl = rcar_i2c_get_scl,
++	.set_scl = rcar_i2c_set_scl,
++	.set_sda = rcar_i2c_set_sda,
++	.recover_bus = i2c_generic_scl_recovery,
++};
+ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
+ {
+ 	/* reset master mode */
+@@ -170,7 +211,7 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
+ 
+ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
+ {
+-	int i;
++	int i, ret;
+ 
+ 	for (i = 0; i < LOOP_TIMEOUT; i++) {
+ 		/* make sure that bus is not busy */
+@@ -179,7 +220,15 @@ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
+ 		udelay(1);
+ 	}
+ 
+-	return -EBUSY;
++	/* Waiting did not help, try to recover */
++	priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
++	ret = i2c_recover_bus(&priv->adap);
++
++	/* No failure when recovering, so check bus busy bit again */
++	if (ret == 0)
++		ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0;
++
++	return ret;
+ }
+ 
+ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
+@@ -851,6 +900,7 @@ static int rcar_i2c_probe(struct platform_device *pdev)
+ 	adap->retries = 3;
+ 	adap->dev.parent = dev;
+ 	adap->dev.of_node = dev->of_node;
++	adap->bus_recovery_info = &rcar_i2c_bri;
+ 	i2c_set_adapdata(adap, priv);
+ 	strlcpy(adap->name, pdev->name, sizeof(adap->name));
+ 
+-- 
+2.19.0
+
diff --git a/patches/0779-i2c-rcar-fix-some-trivial-typos-in-comments.patch b/patches/0779-i2c-rcar-fix-some-trivial-typos-in-comments.patch
new file mode 100644
index 00000000000000..31157aa4525e4f
--- /dev/null
+++ b/patches/0779-i2c-rcar-fix-some-trivial-typos-in-comments.patch
@@ -0,0 +1,50 @@
+From 67d66a67d9fb0eaf569a61813617fd6ba9a6ddf9 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sun, 21 Jan 2018 15:45:11 +0100
+Subject: [PATCH 0779/1795] i2c: rcar: fix some trivial typos in comments
+
+Nothing big, but they get annoying after a while ;)
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit fe34fbf93f87e9e0f78eeeb6f21b2fc310cb6080)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index d4b7b5380c29..4159ebcec2bb 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -62,7 +62,7 @@
+ #define MIE	(1 << 3)	/* master if enable */
+ #define TSBE	(1 << 2)
+ #define FSB	(1 << 1)	/* force stop bit */
+-#define ESG	(1 << 0)	/* en startbit gen */
++#define ESG	(1 << 0)	/* enable start bit gen */
+ 
+ /* ICSSR (also for ICSIER) */
+ #define GCAR	(1 << 6)	/* general call received */
+@@ -331,7 +331,7 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
+ 
+ 	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
+ 	/*
+-	 * We don't have a testcase but the HW engineers say that the write order
++	 * We don't have a test case but the HW engineers say that the write order
+ 	 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
+ 	 * it didn't cause a drawback for me, let's rather be safe than sorry.
+ 	 */
+@@ -489,7 +489,7 @@ static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
+ 
+ 		/*
+ 		 * Try to use DMA to transmit the rest of the data if
+-		 * address transfer pashe just finished.
++		 * address transfer phase just finished.
+ 		 */
+ 		if (msr & MAT)
+ 			rcar_i2c_dma(priv);
+-- 
+2.19.0
+
diff --git a/patches/0780-dt-bindings-at24-add-compatible-for-nxp-se97b.patch b/patches/0780-dt-bindings-at24-add-compatible-for-nxp-se97b.patch
new file mode 100644
index 00000000000000..0ebd1a8ef4c3c4
--- /dev/null
+++ b/patches/0780-dt-bindings-at24-add-compatible-for-nxp-se97b.patch
@@ -0,0 +1,33 @@
+From c0e332f703acb1a8aab0af51ec4eec431b18647f Mon Sep 17 00:00:00 2001
+From: Peter Rosin <peda@axentia.se>
+Date: Tue, 16 Jan 2018 17:06:16 +0100
+Subject: [PATCH 0780/1795] dt-bindings: at24: add compatible for nxp,se97b
+
+The datasheet talks about the chip being an spd, but the chip is writable
+so atmel,24c02 is more appropriate as fallback.
+
+Signed-off-by: Peter Rosin <peda@axentia.se>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit c0a2676c911c73cf7c753083fdd8f775063d324b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index abfae1beca2b..edf9247613f6 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -46,6 +46,7 @@ Required properties:
+                 Some vendors use different model names for chips which are just
+                 variants of the above. Known such exceptions are listed below:
+ 
++                "nxp,se97b" - the fallback is "atmel,24c02",
+                 "renesas,r1ex24002" - the fallback is "atmel,24c02"
+ 
+   - reg: The I2C address of the EEPROM.
+-- 
+2.19.0
+
diff --git a/patches/0781-dt-bindings-at24-add-bindings-for-Rohm-BR24T01.patch b/patches/0781-dt-bindings-at24-add-bindings-for-Rohm-BR24T01.patch
new file mode 100644
index 00000000000000..e806b3813f79e9
--- /dev/null
+++ b/patches/0781-dt-bindings-at24-add-bindings-for-Rohm-BR24T01.patch
@@ -0,0 +1,42 @@
+From 02591c8744a2484bf57c22a916830729e8b0f245 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Fri, 2 Mar 2018 11:14:16 +0100
+Subject: [PATCH 0781/1795] dt-bindings: at24: add bindings for Rohm BR24T01
+
+Both manufacturer and name variant.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit 3644784caa017cc3cf4188fb0bfbf3421e8aa7ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index edf9247613f6..a201a1183118 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -41,6 +41,7 @@ Required properties:
+                 "nxp",
+                 "ramtron",
+                 "renesas",
++                "rohm",
+                 "st",
+ 
+                 Some vendors use different model names for chips which are just
+@@ -48,6 +49,7 @@ Required properties:
+ 
+                 "nxp,se97b" - the fallback is "atmel,24c02",
+                 "renesas,r1ex24002" - the fallback is "atmel,24c02"
++                "rohm,br24t01" - the fallback is "atmel,24c01"
+ 
+   - reg: The I2C address of the EEPROM.
+ 
+-- 
+2.19.0
+
diff --git a/patches/0782-dt-bindings-at24-add-Renesas-R1EX24128.patch b/patches/0782-dt-bindings-at24-add-Renesas-R1EX24128.patch
new file mode 100644
index 00000000000000..5db3dfbe2a33cd
--- /dev/null
+++ b/patches/0782-dt-bindings-at24-add-Renesas-R1EX24128.patch
@@ -0,0 +1,35 @@
+From 18b771dcd6e60543471399b8100652bfd22bb295 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 17:56:37 +0100
+Subject: [PATCH 0782/1795] dt-bindings: at24: add Renesas R1EX24128
+
+Document the compatible value for the Renesas R1EX24128ASAS0A two-wire
+serial interface EEPROM, so it can be used in DTS files without causing
+checkpatch warnings.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
+(cherry picked from commit 84e10623c0b9c81557918804f309d66aec86a233)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/eeprom/at24.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
+index a201a1183118..61d833abafbf 100644
+--- a/Documentation/devicetree/bindings/eeprom/at24.txt
++++ b/Documentation/devicetree/bindings/eeprom/at24.txt
+@@ -49,6 +49,7 @@ Required properties:
+ 
+                 "nxp,se97b" - the fallback is "atmel,24c02",
+                 "renesas,r1ex24002" - the fallback is "atmel,24c02"
++                "renesas,r1ex24128" - the fallback is "atmel,24c128"
+                 "rohm,br24t01" - the fallback is "atmel,24c01"
+ 
+   - reg: The I2C address of the EEPROM.
+-- 
+2.19.0
+
diff --git a/patches/0783-drm-bridge-synopsys-dw-hdmi-Export-some-PHY-related-.patch b/patches/0783-drm-bridge-synopsys-dw-hdmi-Export-some-PHY-related-.patch
new file mode 100644
index 00000000000000..6d832c34ad5d44
--- /dev/null
+++ b/patches/0783-drm-bridge-synopsys-dw-hdmi-Export-some-PHY-related-.patch
@@ -0,0 +1,193 @@
+From c1b412372a6d3f26dc962d7746831a3fc6de1978 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Wed, 14 Feb 2018 21:08:58 +0100
+Subject: [PATCH 0783/1795] drm/bridge/synopsys: dw-hdmi: Export some PHY
+ related functions
+
+Parts of PHY code could be useful also for custom PHYs. For example,
+Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
+with few additional memory mapped registers, so most of the Synopsys PHY
+related code could be reused.
+
+Functions exported here are actually not specific to Synopsys PHYs but
+to DWC HDMI controller PHY interface. This means that even if the PHY is
+completely custom, i.e. not designed by Synopsys, exported functions can
+be useful.
+
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180214200906.31509-5-jernej.skrabec@siol.net
+(cherry picked from commit 5765916afa4e859b92457a4a14f82ef2a9876758)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 44 +++++++++++++++--------
+ drivers/gpu/drm/meson/meson_dw_hdmi.c     |  8 ++---
+ include/drm/bridge/dw_hdmi.h              | 11 ++++++
+ 3 files changed, 45 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index bc848885735a..71e93f623e84 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -1037,19 +1037,21 @@ static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
+ 			 HDMI_PHY_CONF0_SVSRET_MASK);
+ }
+ 
+-static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
++void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
+ {
+ 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+ 			 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
+ 			 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
+ }
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
+ 
+-static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
++void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
+ {
+ 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+ 			 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
+ 			 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
+ }
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
+ 
+ static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
+ {
+@@ -1065,6 +1067,22 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
+ 			 HDMI_PHY_CONF0_SELDIPIF_MASK);
+ }
+ 
++void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
++{
++	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
++	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
++	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
++
++void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
++{
++	hdmi_phy_test_clear(hdmi, 1);
++	hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
++	hdmi_phy_test_clear(hdmi, 0);
++}
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
++
+ static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
+ {
+ 	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
+@@ -1203,16 +1221,11 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi)
+ 	if (phy->has_svsret)
+ 		dw_hdmi_phy_enable_svsret(hdmi, 1);
+ 
+-	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
+-	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
+-	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
++	dw_hdmi_phy_reset(hdmi);
+ 
+ 	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+ 
+-	hdmi_phy_test_clear(hdmi, 1);
+-	hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+-		    HDMI_PHY_I2CM_SLAVE_ADDR);
+-	hdmi_phy_test_clear(hdmi, 0);
++	dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
+ 
+ 	/* Write to the PHY as configured by the platform */
+ 	if (pdata->configure_phy)
+@@ -1251,15 +1264,16 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
+ 	dw_hdmi_phy_power_off(hdmi);
+ }
+ 
+-static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
+-						      void *data)
++enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
++					       void *data)
+ {
+ 	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
+ 		connector_status_connected : connector_status_disconnected;
+ }
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
+ 
+-static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+-				   bool force, bool disabled, bool rxsense)
++void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
++			    bool force, bool disabled, bool rxsense)
+ {
+ 	u8 old_mask = hdmi->phy_mask;
+ 
+@@ -1271,8 +1285,9 @@ static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+ 	if (old_mask != hdmi->phy_mask)
+ 		hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
+ }
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
+ 
+-static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
++void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
+ {
+ 	/*
+ 	 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
+@@ -1291,6 +1306,7 @@ static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
+ 	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
+ 		    HDMI_IH_MUTE_PHY_STAT0);
+ }
++EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
+ 
+ static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
+ 	.init = dw_hdmi_phy_init,
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index cef414466f9f..5ce6f1541a5e 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -300,7 +300,7 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
+ 	}
+ }
+ 
+-static inline void dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
++static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
+ {
+ 	struct meson_drm *priv = dw_hdmi->priv;
+ 
+@@ -407,9 +407,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
+ 	msleep(100);
+ 
+ 	/* Reset PHY 3 times in a row */
+-	dw_hdmi_phy_reset(dw_hdmi);
+-	dw_hdmi_phy_reset(dw_hdmi);
+-	dw_hdmi_phy_reset(dw_hdmi);
++	meson_dw_hdmi_phy_reset(dw_hdmi);
++	meson_dw_hdmi_phy_reset(dw_hdmi);
++	meson_dw_hdmi_phy_reset(dw_hdmi);
+ 
+ 	/* Temporary Disable VENC video stream */
+ 	if (priv->venc.hdmi_use_enci)
+diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
+index 182f83283e24..f3f3f0e1b2d3 100644
+--- a/include/drm/bridge/dw_hdmi.h
++++ b/include/drm/bridge/dw_hdmi.h
+@@ -157,7 +157,18 @@ void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
+ void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
+ 
+ /* PHY configuration */
++void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
+ void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
+ 			   unsigned char addr);
+ 
++void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
++void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
++void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
++
++enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
++					       void *data);
++void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
++			    bool force, bool disabled, bool rxsense);
++void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
++
+ #endif /* __IMX_HDMI_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0784-drm-bridge-synopsys-dw-hdmi-don-t-clobber-drvdata.patch b/patches/0784-drm-bridge-synopsys-dw-hdmi-don-t-clobber-drvdata.patch
new file mode 100644
index 00000000000000..5f8fe8383b1b3c
--- /dev/null
+++ b/patches/0784-drm-bridge-synopsys-dw-hdmi-don-t-clobber-drvdata.patch
@@ -0,0 +1,300 @@
+From 314e70d111403e3c8af06920cc74b82fc90f535d Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Wed, 14 Feb 2018 21:08:59 +0100
+Subject: [PATCH 0784/1795] drm/bridge/synopsys: dw-hdmi: don't clobber drvdata
+
+dw_hdmi shouldn't set drvdata since some drivers might need to store
+it's own data there. Rework dw_hdmi in a way to return struct dw_hdmi
+instead to store it in drvdata. This way drivers are responsible to
+store and pass structure when needed.
+
+Idea was taken from the following commit:
+8242ecbd597d ("drm/bridge/synopsys: stop clobbering drvdata")
+
+Cc: p.zabel@pengutronix.de
+Cc: Laurent.pinchart@ideasonboard.com
+Cc: hjc@rock-chips.com
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180214200906.31509-6-jernej.skrabec@siol.net
+(cherry picked from commit eea034af90c64802fd747a9dc534c26a7ebe7754)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c   | 31 +++++++++------------
+ drivers/gpu/drm/imx/dw_hdmi-imx.c           | 13 +++++++--
+ drivers/gpu/drm/meson/meson_dw_hdmi.c       | 14 +++++++---
+ drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c      | 12 ++++++--
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 13 +++++++--
+ include/drm/bridge/dw_hdmi.h                | 13 +++++----
+ 6 files changed, 60 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 71e93f623e84..f7d89a9dc4a1 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2542,8 +2542,6 @@ __dw_hdmi_probe(struct platform_device *pdev,
+ 	if (hdmi->i2c)
+ 		dw_hdmi_i2c_init(hdmi);
+ 
+-	platform_set_drvdata(pdev, hdmi);
+-
+ 	return hdmi;
+ 
+ err_iahb:
+@@ -2593,25 +2591,23 @@ static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
+ /* -----------------------------------------------------------------------------
+  * Probe/remove API, used from platforms based on the DRM bridge API.
+  */
+-int dw_hdmi_probe(struct platform_device *pdev,
+-		  const struct dw_hdmi_plat_data *plat_data)
++struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
++			      const struct dw_hdmi_plat_data *plat_data)
+ {
+ 	struct dw_hdmi *hdmi;
+ 
+ 	hdmi = __dw_hdmi_probe(pdev, plat_data);
+ 	if (IS_ERR(hdmi))
+-		return PTR_ERR(hdmi);
++		return hdmi;
+ 
+ 	drm_bridge_add(&hdmi->bridge);
+ 
+-	return 0;
++	return hdmi;
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_probe);
+ 
+-void dw_hdmi_remove(struct platform_device *pdev)
++void dw_hdmi_remove(struct dw_hdmi *hdmi)
+ {
+-	struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
+-
+ 	drm_bridge_remove(&hdmi->bridge);
+ 
+ 	__dw_hdmi_remove(hdmi);
+@@ -2621,31 +2617,30 @@ EXPORT_SYMBOL_GPL(dw_hdmi_remove);
+ /* -----------------------------------------------------------------------------
+  * Bind/unbind API, used from platforms based on the component framework.
+  */
+-int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+-		 const struct dw_hdmi_plat_data *plat_data)
++struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
++			     struct drm_encoder *encoder,
++			     const struct dw_hdmi_plat_data *plat_data)
+ {
+ 	struct dw_hdmi *hdmi;
+ 	int ret;
+ 
+ 	hdmi = __dw_hdmi_probe(pdev, plat_data);
+ 	if (IS_ERR(hdmi))
+-		return PTR_ERR(hdmi);
++		return hdmi;
+ 
+ 	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
+ 	if (ret) {
+-		dw_hdmi_remove(pdev);
++		dw_hdmi_remove(hdmi);
+ 		DRM_ERROR("Failed to initialize bridge with drm\n");
+-		return ret;
++		return ERR_PTR(ret);
+ 	}
+ 
+-	return 0;
++	return hdmi;
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_bind);
+ 
+-void dw_hdmi_unbind(struct device *dev)
++void dw_hdmi_unbind(struct dw_hdmi *hdmi)
+ {
+-	struct dw_hdmi *hdmi = dev_get_drvdata(dev);
+-
+ 	__dw_hdmi_remove(hdmi);
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
+diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
+index b62763aa8706..fe6becdcc29e 100644
+--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
++++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
+@@ -25,6 +25,7 @@
+ struct imx_hdmi {
+ 	struct device *dev;
+ 	struct drm_encoder encoder;
++	struct dw_hdmi *hdmi;
+ 	struct regmap *regmap;
+ };
+ 
+@@ -239,14 +240,18 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
+ 	drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
+ 			 DRM_MODE_ENCODER_TMDS, NULL);
+ 
+-	ret = dw_hdmi_bind(pdev, encoder, plat_data);
++	platform_set_drvdata(pdev, hdmi);
++
++	hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
+ 
+ 	/*
+ 	 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ 	 * which would have called the encoder cleanup.  Do it manually.
+ 	 */
+-	if (ret)
++	if (IS_ERR(hdmi->hdmi)) {
++		ret = PTR_ERR(hdmi->hdmi);
+ 		drm_encoder_cleanup(encoder);
++	}
+ 
+ 	return ret;
+ }
+@@ -254,7 +259,9 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
+ static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
+ 			       void *data)
+ {
+-	return dw_hdmi_unbind(dev);
++	struct imx_hdmi *hdmi = dev_get_drvdata(dev);
++
++	dw_hdmi_unbind(hdmi->hdmi);
+ }
+ 
+ static const struct component_ops dw_hdmi_imx_ops = {
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index 5ce6f1541a5e..bc18e3fc7a68 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -138,6 +138,7 @@ struct meson_dw_hdmi {
+ 	struct clk *hdmi_pclk;
+ 	struct clk *venci_clk;
+ 	u32 irq_stat;
++	struct dw_hdmi *hdmi;
+ };
+ #define encoder_to_meson_dw_hdmi(x) \
+ 	container_of(x, struct meson_dw_hdmi, encoder)
+@@ -865,9 +866,12 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
+ 	dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
+ 	dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
+ 
+-	ret = dw_hdmi_bind(pdev, encoder, &meson_dw_hdmi->dw_plat_data);
+-	if (ret)
+-		return ret;
++	platform_set_drvdata(pdev, meson_dw_hdmi);
++
++	meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder,
++					   &meson_dw_hdmi->dw_plat_data);
++	if (IS_ERR(meson_dw_hdmi->hdmi))
++		return PTR_ERR(meson_dw_hdmi->hdmi);
+ 
+ 	DRM_DEBUG_DRIVER("HDMI controller initialized\n");
+ 
+@@ -877,7 +881,9 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
+ static void meson_dw_hdmi_unbind(struct device *dev, struct device *master,
+ 				   void *data)
+ {
+-	dw_hdmi_unbind(dev);
++	struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
++
++	dw_hdmi_unbind(meson_dw_hdmi->hdmi);
+ }
+ 
+ static const struct component_ops meson_dw_hdmi_ops = {
+diff --git a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
+index dc85b53d58ef..3bebc6821e9c 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
++++ b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
+@@ -68,12 +68,20 @@ static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
+ 
+ static int rcar_dw_hdmi_probe(struct platform_device *pdev)
+ {
+-	return dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data);
++	struct dw_hdmi *hdmi;
++
++	hdmi = dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data);
++	if (IS_ERR(hdmi))
++		return PTR_ERR(hdmi);
++
++	platform_set_drvdata(pdev, hdmi);
+ }
+ 
+ static int rcar_dw_hdmi_remove(struct platform_device *pdev)
+ {
+-	dw_hdmi_remove(pdev);
++	struct dw_hdmi *hdmi = platform_get_drvdata(dev);
++
++	dw_hdmi_remove(hdmi);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index ccd5d595ada7..070c7ec4c5cd 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -48,6 +48,7 @@ struct rockchip_hdmi {
+ 	const struct rockchip_hdmi_chip_data *chip_data;
+ 	struct clk *vpll_clk;
+ 	struct clk *grf_clk;
++	struct dw_hdmi *hdmi;
+ };
+ 
+ #define to_rockchip_hdmi(x)	container_of(x, struct rockchip_hdmi, x)
+@@ -376,14 +377,18 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
+ 			 DRM_MODE_ENCODER_TMDS, NULL);
+ 
+-	ret = dw_hdmi_bind(pdev, encoder, plat_data);
++	platform_set_drvdata(pdev, hdmi);
++
++	hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
+ 
+ 	/*
+ 	 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ 	 * which would have called the encoder cleanup.  Do it manually.
+ 	 */
+-	if (ret)
++	if (IS_ERR(hdmi->hdmi)) {
++		ret = PTR_ERR(hdmi->hdmi);
+ 		drm_encoder_cleanup(encoder);
++	}
+ 
+ 	return ret;
+ }
+@@ -391,7 +396,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
+ 				    void *data)
+ {
+-	return dw_hdmi_unbind(dev);
++	struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
++
++	dw_hdmi_unbind(hdmi->hdmi);
+ }
+ 
+ static const struct component_ops dw_hdmi_rockchip_ops = {
+diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
+index f3f3f0e1b2d3..dd2a8cf7d20b 100644
+--- a/include/drm/bridge/dw_hdmi.h
++++ b/include/drm/bridge/dw_hdmi.h
+@@ -143,12 +143,13 @@ struct dw_hdmi_plat_data {
+ 			     unsigned long mpixelclock);
+ };
+ 
+-int dw_hdmi_probe(struct platform_device *pdev,
+-		  const struct dw_hdmi_plat_data *plat_data);
+-void dw_hdmi_remove(struct platform_device *pdev);
+-void dw_hdmi_unbind(struct device *dev);
+-int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+-		 const struct dw_hdmi_plat_data *plat_data);
++struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
++			      const struct dw_hdmi_plat_data *plat_data);
++void dw_hdmi_remove(struct dw_hdmi *hdmi);
++void dw_hdmi_unbind(struct dw_hdmi *hdmi);
++struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
++			     struct drm_encoder *encoder,
++			     const struct dw_hdmi_plat_data *plat_data);
+ 
+ void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0785-gpio-em-Use-the-right-include.patch b/patches/0785-gpio-em-Use-the-right-include.patch
new file mode 100644
index 00000000000000..29504df0e45cbd
--- /dev/null
+++ b/patches/0785-gpio-em-Use-the-right-include.patch
@@ -0,0 +1,33 @@
+From 21c20a053700c55fe2903a57e619313db6b65f94 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 9 Feb 2018 00:45:50 +0100
+Subject: [PATCH 0785/1795] gpio: em: Use the right include
+
+The Emma Mobile (EM) GPIO driver uses the too generic include
+<linux/gpio.h>. It is a driver so it should just use
+<linux/gpio/driver.h>.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 7275cb75b96f5cec924ea95685d906d09b6a82f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-em.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
+index b86e09e1b13b..2b466b80e70a 100644
+--- a/drivers/gpio/gpio-em.c
++++ b/drivers/gpio/gpio-em.c
+@@ -27,7 +27,7 @@
+ #include <linux/irqdomain.h>
+ #include <linux/bitops.h>
+ #include <linux/err.h>
+-#include <linux/gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/slab.h>
+ #include <linux/module.h>
+ #include <linux/pinctrl/consumer.h>
+-- 
+2.19.0
+
diff --git a/patches/0786-Input-gpio-keys-add-support-for-wakeup-event-action.patch b/patches/0786-Input-gpio-keys-add-support-for-wakeup-event-action.patch
new file mode 100644
index 00000000000000..fb894e003ce7f2
--- /dev/null
+++ b/patches/0786-Input-gpio-keys-add-support-for-wakeup-event-action.patch
@@ -0,0 +1,302 @@
+From c92fcd890e67fe678f7c85d231a9f32f6761b93c Mon Sep 17 00:00:00 2001
+From: Jeffy Chen <jeffy.chen@rock-chips.com>
+Date: Thu, 8 Mar 2018 16:03:27 -0800
+Subject: [PATCH 0786/1795] Input: gpio-keys - add support for wakeup event
+ action
+
+Add support for specifying event actions to trigger wakeup when using
+the gpio-keys input device as a wakeup source.
+
+This would allow the device to configure when to wakeup the system. For
+example a gpio-keys input device for pen insert, may only want to wakeup
+the system when ejecting the pen.
+
+Suggested-by: Brian Norris <briannorris@chromium.org>
+Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+(cherry picked from commit 83fc580dcc2f0f36114477c4ac7adbe5c32329a3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/input/gpio-keys.txt   |   8 +
+ drivers/input/keyboard/gpio_keys.c            | 145 ++++++++++++++++--
+ include/dt-bindings/input/gpio-keys.h         |  13 ++
+ include/linux/gpio_keys.h                     |   2 +
+ 4 files changed, 154 insertions(+), 14 deletions(-)
+ create mode 100644 include/dt-bindings/input/gpio-keys.h
+
+diff --git a/Documentation/devicetree/bindings/input/gpio-keys.txt b/Documentation/devicetree/bindings/input/gpio-keys.txt
+index a94940481e55..996ce84352cb 100644
+--- a/Documentation/devicetree/bindings/input/gpio-keys.txt
++++ b/Documentation/devicetree/bindings/input/gpio-keys.txt
+@@ -26,6 +26,14 @@ Optional subnode-properties:
+ 	  If not specified defaults to 5.
+ 	- wakeup-source: Boolean, button can wake-up the system.
+ 			 (Legacy property supported: "gpio-key,wakeup")
++	- wakeup-event-action: Specifies whether the key should wake the
++	  system when asserted, when deasserted, or both. This property is
++	  only valid for keys that wake up the system (e.g., when the
++	  "wakeup-source" property is also provided).
++	  Supported values are defined in linux-event-codes.h:
++		EV_ACT_ASSERTED		- asserted
++		EV_ACT_DEASSERTED	- deasserted
++		EV_ACT_ANY		- both asserted and deasserted
+ 	- linux,can-disable: Boolean, indicates that button is connected
+ 	  to dedicated (not shared) interrupt which can be disabled to
+ 	  suppress events from the button.
+diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
+index 87e613dc33b8..052e37675086 100644
+--- a/drivers/input/keyboard/gpio_keys.c
++++ b/drivers/input/keyboard/gpio_keys.c
+@@ -30,6 +30,7 @@
+ #include <linux/of.h>
+ #include <linux/of_irq.h>
+ #include <linux/spinlock.h>
++#include <dt-bindings/input/gpio-keys.h>
+ 
+ struct gpio_button_data {
+ 	const struct gpio_keys_button *button;
+@@ -45,6 +46,7 @@ struct gpio_button_data {
+ 	unsigned int software_debounce;	/* in msecs, for GPIO-driven buttons */
+ 
+ 	unsigned int irq;
++	unsigned int wakeup_trigger_type;
+ 	spinlock_t lock;
+ 	bool disabled;
+ 	bool key_pressed;
+@@ -540,6 +542,8 @@ static int gpio_keys_setup_key(struct platform_device *pdev,
+ 	}
+ 
+ 	if (bdata->gpiod) {
++		bool active_low = gpiod_is_active_low(bdata->gpiod);
++
+ 		if (button->debounce_interval) {
+ 			error = gpiod_set_debounce(bdata->gpiod,
+ 					button->debounce_interval * 1000);
+@@ -568,6 +572,24 @@ static int gpio_keys_setup_key(struct platform_device *pdev,
+ 		isr = gpio_keys_gpio_isr;
+ 		irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+ 
++		switch (button->wakeup_event_action) {
++		case EV_ACT_ASSERTED:
++			bdata->wakeup_trigger_type = active_low ?
++				IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
++			break;
++		case EV_ACT_DEASSERTED:
++			bdata->wakeup_trigger_type = active_low ?
++				IRQ_TYPE_EDGE_RISING : IRQ_TYPE_EDGE_FALLING;
++			break;
++		case EV_ACT_ANY:
++			/* fall through */
++		default:
++			/*
++			 * For other cases, we are OK letting suspend/resume
++			 * not reconfigure the trigger type.
++			 */
++			break;
++		}
+ 	} else {
+ 		if (!button->irq) {
+ 			dev_err(dev, "Found button without gpio or irq\n");
+@@ -586,6 +608,11 @@ static int gpio_keys_setup_key(struct platform_device *pdev,
+ 
+ 		isr = gpio_keys_irq_isr;
+ 		irqflags = 0;
++
++		/*
++		 * For IRQ buttons, there is no interrupt for release.
++		 * So we don't need to reconfigure the trigger type for wakeup.
++		 */
+ 	}
+ 
+ 	bdata->code = &ddata->keymap[idx];
+@@ -718,6 +745,9 @@ gpio_keys_get_devtree_pdata(struct device *dev)
+ 			/* legacy name */
+ 			fwnode_property_read_bool(child, "gpio-key,wakeup");
+ 
++		fwnode_property_read_u32(child, "wakeup-event-action",
++					 &button->wakeup_event_action);
++
+ 		button->can_disable =
+ 			fwnode_property_read_bool(child, "linux,can-disable");
+ 
+@@ -845,19 +875,112 @@ static int gpio_keys_probe(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static int __maybe_unused
++gpio_keys_button_enable_wakeup(struct gpio_button_data *bdata)
++{
++	int error;
++
++	error = enable_irq_wake(bdata->irq);
++	if (error) {
++		dev_err(bdata->input->dev.parent,
++			"failed to configure IRQ %d as wakeup source: %d\n",
++			bdata->irq, error);
++		return error;
++	}
++
++	if (bdata->wakeup_trigger_type) {
++		error = irq_set_irq_type(bdata->irq,
++					 bdata->wakeup_trigger_type);
++		if (error) {
++			dev_err(bdata->input->dev.parent,
++				"failed to set wakeup trigger %08x for IRQ %d: %d\n",
++				bdata->wakeup_trigger_type, bdata->irq, error);
++			disable_irq_wake(bdata->irq);
++			return error;
++		}
++	}
++
++	return 0;
++}
++
++static void __maybe_unused
++gpio_keys_button_disable_wakeup(struct gpio_button_data *bdata)
++{
++	int error;
++
++	/*
++	 * The trigger type is always both edges for gpio-based keys and we do
++	 * not support changing wakeup trigger for interrupt-based keys.
++	 */
++	if (bdata->wakeup_trigger_type) {
++		error = irq_set_irq_type(bdata->irq, IRQ_TYPE_EDGE_BOTH);
++		if (error)
++			dev_warn(bdata->input->dev.parent,
++				 "failed to restore interrupt trigger for IRQ %d: %d\n",
++				 bdata->irq, error);
++	}
++
++	error = disable_irq_wake(bdata->irq);
++	if (error)
++		dev_warn(bdata->input->dev.parent,
++			 "failed to disable IRQ %d as wake source: %d\n",
++			 bdata->irq, error);
++}
++
++static int __maybe_unused
++gpio_keys_enable_wakeup(struct gpio_keys_drvdata *ddata)
++{
++	struct gpio_button_data *bdata;
++	int error;
++	int i;
++
++	for (i = 0; i < ddata->pdata->nbuttons; i++) {
++		bdata = &ddata->data[i];
++		if (bdata->button->wakeup) {
++			error = gpio_keys_button_enable_wakeup(bdata);
++			if (error)
++				goto err_out;
++		}
++		bdata->suspended = true;
++	}
++
++	return 0;
++
++err_out:
++	while (i--) {
++		bdata = &ddata->data[i];
++		if (bdata->button->wakeup)
++			gpio_keys_button_disable_wakeup(bdata);
++		bdata->suspended = false;
++	}
++
++	return error;
++}
++
++static void __maybe_unused
++gpio_keys_disable_wakeup(struct gpio_keys_drvdata *ddata)
++{
++	struct gpio_button_data *bdata;
++	int i;
++
++	for (i = 0; i < ddata->pdata->nbuttons; i++) {
++		bdata = &ddata->data[i];
++		bdata->suspended = false;
++		if (irqd_is_wakeup_set(irq_get_irq_data(bdata->irq)))
++			gpio_keys_button_disable_wakeup(bdata);
++	}
++}
++
+ static int __maybe_unused gpio_keys_suspend(struct device *dev)
+ {
+ 	struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev);
+ 	struct input_dev *input = ddata->input;
+-	int i;
++	int error;
+ 
+ 	if (device_may_wakeup(dev)) {
+-		for (i = 0; i < ddata->pdata->nbuttons; i++) {
+-			struct gpio_button_data *bdata = &ddata->data[i];
+-			if (bdata->button->wakeup)
+-				enable_irq_wake(bdata->irq);
+-			bdata->suspended = true;
+-		}
++		error = gpio_keys_enable_wakeup(ddata);
++		if (error)
++			return error;
+ 	} else {
+ 		mutex_lock(&input->mutex);
+ 		if (input->users)
+@@ -873,15 +996,9 @@ static int __maybe_unused gpio_keys_resume(struct device *dev)
+ 	struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev);
+ 	struct input_dev *input = ddata->input;
+ 	int error = 0;
+-	int i;
+ 
+ 	if (device_may_wakeup(dev)) {
+-		for (i = 0; i < ddata->pdata->nbuttons; i++) {
+-			struct gpio_button_data *bdata = &ddata->data[i];
+-			if (bdata->button->wakeup)
+-				disable_irq_wake(bdata->irq);
+-			bdata->suspended = false;
+-		}
++		gpio_keys_disable_wakeup(ddata);
+ 	} else {
+ 		mutex_lock(&input->mutex);
+ 		if (input->users)
+diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h
+new file mode 100644
+index 000000000000..8962df79e753
+--- /dev/null
++++ b/include/dt-bindings/input/gpio-keys.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * This header provides constants for gpio keys bindings.
++ */
++
++#ifndef _DT_BINDINGS_GPIO_KEYS_H
++#define _DT_BINDINGS_GPIO_KEYS_H
++
++#define EV_ACT_ANY		0x00	/* asserted or deasserted */
++#define EV_ACT_ASSERTED		0x01	/* asserted */
++#define EV_ACT_DEASSERTED	0x02	/* deasserted */
++
++#endif /* _DT_BINDINGS_GPIO_KEYS_H */
+diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h
+index d06bf77400f1..7160df54a6fe 100644
+--- a/include/linux/gpio_keys.h
++++ b/include/linux/gpio_keys.h
+@@ -13,6 +13,7 @@ struct device;
+  * @desc:		label that will be attached to button's gpio
+  * @type:		input event type (%EV_KEY, %EV_SW, %EV_ABS)
+  * @wakeup:		configure the button as a wake-up source
++ * @wakeup_event_action:	event action to trigger wakeup
+  * @debounce_interval:	debounce ticks interval in msecs
+  * @can_disable:	%true indicates that userspace is allowed to
+  *			disable button via sysfs
+@@ -26,6 +27,7 @@ struct gpio_keys_button {
+ 	const char *desc;
+ 	unsigned int type;
+ 	int wakeup;
++	int wakeup_event_action;
+ 	int debounce_interval;
+ 	bool can_disable;
+ 	int value;
+-- 
+2.19.0
+
diff --git a/patches/0787-regulator-dt-regulator-name-is-required-property.patch b/patches/0787-regulator-dt-regulator-name-is-required-property.patch
new file mode 100644
index 00000000000000..98dca4ea460618
--- /dev/null
+++ b/patches/0787-regulator-dt-regulator-name-is-required-property.patch
@@ -0,0 +1,47 @@
+From 343b70aeba282f147a4c0322c7e624ab45c11701 Mon Sep 17 00:00:00 2001
+From: Harald Geyer <harald@ccbib.org>
+Date: Tue, 13 Feb 2018 14:43:08 +0000
+Subject: [PATCH 0787/1795] regulator: dt: regulator-name is required property
+
+These two drivers fail to probe if no name is provided. For details see:
+https://www.spinics.net/lists/kernel/msg2457515.html
+
+Signed-off-by: Harald Geyer <harald@ccbib.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 4b75291621830acad2c66a1d21d7840a7ca169d3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/regulator/fixed-regulator.txt | 1 +
+ Documentation/devicetree/bindings/regulator/gpio-regulator.txt  | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+index 4fae41d54798..0c2a6c8a1536 100644
+--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
++++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+@@ -2,6 +2,7 @@ Fixed Voltage regulators
+ 
+ Required properties:
+ - compatible: Must be "regulator-fixed";
++- regulator-name: Defined in regulator.txt as optional, but required here.
+ 
+ Optional properties:
+ - gpio: gpio to use for enable control
+diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
+index dd1ed789728e..1f496159e2bb 100644
+--- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
++++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
+@@ -2,6 +2,8 @@ GPIO controlled regulators
+ 
+ Required properties:
+ - compatible		: Must be "regulator-gpio".
++- regulator-name	: Defined in regulator.txt as optional, but required
++			  here.
+ - states		: Selection of available voltages and GPIO configs.
+                           if there are no states, then use a fixed regulator
+ 
+-- 
+2.19.0
+
diff --git a/patches/0788-regulator-giving-regulator-controlling-gpios-a-non-e.patch b/patches/0788-regulator-giving-regulator-controlling-gpios-a-non-e.patch
new file mode 100644
index 00000000000000..4dcf26a1df17d6
--- /dev/null
+++ b/patches/0788-regulator-giving-regulator-controlling-gpios-a-non-e.patch
@@ -0,0 +1,36 @@
+From cec290b6c9c04cf606ddf442bea120d92b4221f2 Mon Sep 17 00:00:00 2001
+From: Nicholas Lowell <nlowell@lexmark.com>
+Date: Mon, 19 Mar 2018 09:23:14 -0400
+Subject: [PATCH 0788/1795] regulator: giving regulator controlling gpios a
+ non-empty label when used through the devicetree.
+
+When the label is empty, it causes missing information and limits diagnostics
+for instances such as 'cat /sys/kernel/debug/gpio'
+
+Setting the label to the regulator supply_name will point to the device
+using the gpio(s).
+
+Signed-off-by: Nicholas Lowell <nlowell@lexmark.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 37ad490bab09b7c218e37b570069cf188f2616e7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/regulator/gpio-regulator.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/regulator/gpio-regulator.c b/drivers/regulator/gpio-regulator.c
+index a2eb50719c7b..a86b8997bb54 100644
+--- a/drivers/regulator/gpio-regulator.c
++++ b/drivers/regulator/gpio-regulator.c
+@@ -196,6 +196,7 @@ of_get_gpio_regulator_config(struct device *dev, struct device_node *np,
+ 				break;
+ 			}
+ 			config->gpios[i].gpio = gpio;
++			config->gpios[i].label = config->supply_name;
+ 			if (proplen > 0) {
+ 				of_property_read_u32_index(np, "gpios-states",
+ 							   i, &ret);
+-- 
+2.19.0
+
diff --git a/patches/0789-dt-bindings-i2c-sh_mobile-Document-R-Car-M3-N-suppor.patch b/patches/0789-dt-bindings-i2c-sh_mobile-Document-R-Car-M3-N-suppor.patch
new file mode 100644
index 00000000000000..0b412a6b84dd30
--- /dev/null
+++ b/patches/0789-dt-bindings-i2c-sh_mobile-Document-R-Car-M3-N-suppor.patch
@@ -0,0 +1,36 @@
+From 738a844b8f0b22f755954d2c4eb24684fd670db9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 16:26:43 +0100
+Subject: [PATCH 0789/1795] dt-bindings: i2c: sh_mobile: Document R-Car M3-N
+ support
+
+Document support for the IIC Bus Interface for DVFS (IIC for DVFS) in
+the Renesas M3-N (r8a77965) SoC.
+
+No driver update is needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 84cb55c422816d96e8871f7663194949eca98fa6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+index 224390999e81..fc7e17802746 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+@@ -13,6 +13,7 @@ Required properties:
+ 			- "renesas,iic-r8a7794" (R-Car E2)
+ 			- "renesas,iic-r8a7795" (R-Car H3)
+ 			- "renesas,iic-r8a7796" (R-Car M3-W)
++			- "renesas,iic-r8a77965" (R-Car M3-N)
+ 			- "renesas,iic-sh73a0" (SH-Mobile AG5)
+ 			- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
+ 							compatible device)
+-- 
+2.19.0
+
diff --git a/patches/0790-dt-bindings-iommu-ipmmu-vmsa-Add-device-tree-support.patch b/patches/0790-dt-bindings-iommu-ipmmu-vmsa-Add-device-tree-support.patch
new file mode 100644
index 00000000000000..ad365d4c8cea0a
--- /dev/null
+++ b/patches/0790-dt-bindings-iommu-ipmmu-vmsa-Add-device-tree-support.patch
@@ -0,0 +1,47 @@
+From 4159ae10332968b4a91bfa39b1c2a1c196fbd7e0 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 24 Jan 2018 15:42:00 +0000
+Subject: [PATCH 0790/1795] dt-bindings: iommu: ipmmu-vmsa: Add device tree
+ support for r8a774[35]
+
+Document r8a774[35] specific compatible strings. The Renesas RZ/G1[ME]
+(r8a774[35]) IPMMU are identical to the R-Car Gen2 family.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+(cherry picked from commit 9fe77e0166ae453d61954e8200b90ac7000242de)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt         | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+index 1fd5d69647ca..ffadb7c6f1f3 100644
+--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
++++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+@@ -11,6 +11,8 @@ Required Properties:
+     the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
+ 
+     - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
++    - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
++    - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
+     - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
+     - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
+     - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
+@@ -19,7 +21,8 @@ Required Properties:
+     - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
+     - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
+     - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
+-    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
++    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
++			   IPMMU.
+ 
+   - reg: Base address and size of the IPMMU registers.
+   - interrupts: Specifiers for the MMU fault interrupts. For instances that
+-- 
+2.19.0
+
diff --git a/patches/0791-irqchip-gic-v2-Reset-APRn-registers-at-boot-time.patch b/patches/0791-irqchip-gic-v2-Reset-APRn-registers-at-boot-time.patch
new file mode 100644
index 00000000000000..e2087aee7f63b6
--- /dev/null
+++ b/patches/0791-irqchip-gic-v2-Reset-APRn-registers-at-boot-time.patch
@@ -0,0 +1,68 @@
+From 54ed30f424292bf74356493cccaf9b7b03ae2b05 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Fri, 9 Mar 2018 14:53:19 +0000
+Subject: [PATCH 0791/1795] irqchip/gic-v2: Reset APRn registers at boot time
+
+Booting a crash kernel while in an interrupt handler is likely
+to leave the Active Priority Registers with some state that
+is not relevant to the new kernel, and is likely to lead
+to erratic behaviours such as interrupts not firing as their
+priority is already active.
+
+As a sanity measure, wipe the APRs clean on startup.
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit c5e1035c9687025373b7c48a08efb37f5329916b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-gic.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
+index 121af5cf688f..79801c24800b 100644
+--- a/drivers/irqchip/irq-gic.c
++++ b/drivers/irqchip/irq-gic.c
+@@ -453,15 +453,26 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
+ 	return mask;
+ }
+ 
++static bool gic_check_gicv2(void __iomem *base)
++{
++	u32 val = readl_relaxed(base + GIC_CPU_IDENT);
++	return (val & 0xff0fff) == 0x02043B;
++}
++
+ static void gic_cpu_if_up(struct gic_chip_data *gic)
+ {
+ 	void __iomem *cpu_base = gic_data_cpu_base(gic);
+ 	u32 bypass = 0;
+ 	u32 mode = 0;
++	int i;
+ 
+ 	if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
+ 		mode = GIC_CPU_CTRL_EOImodeNS;
+ 
++	if (gic_check_gicv2(cpu_base))
++		for (i = 0; i < 4; i++)
++			writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
++
+ 	/*
+ 	* Preserve bypass disable bits to be written back later
+ 	*/
+@@ -1264,12 +1275,6 @@ static int __init gicv2_force_probe_cfg(char *buf)
+ }
+ early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
+ 
+-static bool gic_check_gicv2(void __iomem *base)
+-{
+-	u32 val = readl_relaxed(base + GIC_CPU_IDENT);
+-	return (val & 0xff0fff) == 0x02043B;
+-}
+-
+ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
+ {
+ 	struct resource cpuif_res;
+-- 
+2.19.0
+
diff --git a/patches/0792-irqchip-gic-Loudly-complain-about-the-use-of-IRQ_TYP.patch b/patches/0792-irqchip-gic-Loudly-complain-about-the-use-of-IRQ_TYP.patch
new file mode 100644
index 00000000000000..1ce05094f7ad8b
--- /dev/null
+++ b/patches/0792-irqchip-gic-Loudly-complain-about-the-use-of-IRQ_TYP.patch
@@ -0,0 +1,48 @@
+From 5e11ca5fc414ac5f305042ae167d90d165776a37 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Fri, 16 Mar 2018 14:35:17 +0000
+Subject: [PATCH 0792/1795] irqchip/gic: Loudly complain about the use of
+ IRQ_TYPE_NONE
+
+There is a huge number of broken device trees out there. Just
+grepping through the tree for the use of IRQ_TYPE_NONE in conjunction
+with the GIC is scary.
+
+People just don't realise that IRQ_TYPE_NONE just doesn't exist, and
+you just get whatever junk was there before. So let's make them aware
+of the issue.
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit 83a86fbb5b56b5eed8a476cc3fe214077d7c4f49)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-gic.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
+index 79801c24800b..ac2e62d613d1 100644
+--- a/drivers/irqchip/irq-gic.c
++++ b/drivers/irqchip/irq-gic.c
+@@ -1011,6 +1011,9 @@ static int gic_irq_domain_translate(struct irq_domain *d,
+ 			*hwirq += 16;
+ 
+ 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
++
++		/* Make it clear that broken DTs are... broken */
++		WARN_ON(*type == IRQ_TYPE_NONE);
+ 		return 0;
+ 	}
+ 
+@@ -1020,6 +1023,8 @@ static int gic_irq_domain_translate(struct irq_domain *d,
+ 
+ 		*hwirq = fwspec->param[0];
+ 		*type = fwspec->param[1];
++
++		WARN_ON(*type == IRQ_TYPE_NONE);
+ 		return 0;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0793-irqchip-gic-Update-supports_deactivate-static-key-to.patch b/patches/0793-irqchip-gic-Update-supports_deactivate-static-key-to.patch
new file mode 100644
index 00000000000000..dd95176fd41096
--- /dev/null
+++ b/patches/0793-irqchip-gic-Update-supports_deactivate-static-key-to.patch
@@ -0,0 +1,220 @@
+From cbe8b6c690aab2be82b16f4384fe73bc9668b938 Mon Sep 17 00:00:00 2001
+From: Davidlohr Bueso <dave@stgolabs.net>
+Date: Mon, 26 Mar 2018 14:09:25 -0700
+Subject: [PATCH 0793/1795] irqchip/gic: Update supports_deactivate static key
+ to modern api
+
+No changes in semantics -- key init is true; replace
+
+static_key_slow_dec       with   static_branch_disable
+static_key_true           with   static_branch_likely
+
+The first is because we never actually do any couterpart incs,
+thus there is really no reference counting semantics going on.
+Use the more proper static_branch_disable() construct.
+
+Also added a '_key' suffix to supports_deactivate, for better
+self documentation.
+
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Davidlohr Bueso <dbueso@suse.de>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit d01d327406d9c36e066181240ac078b636871de8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-gic-v3.c | 20 ++++++++++----------
+ drivers/irqchip/irq-gic.c    | 22 +++++++++++-----------
+ 2 files changed, 21 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
+index 2437497eaf4d..ee52a9c46b70 100644
+--- a/drivers/irqchip/irq-gic-v3.c
++++ b/drivers/irqchip/irq-gic-v3.c
+@@ -60,7 +60,7 @@ struct gic_chip_data {
+ };
+ 
+ static struct gic_chip_data gic_data __read_mostly;
+-static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
++static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
+ 
+ static struct gic_kvm_info gic_v3_kvm_info;
+ 
+@@ -351,7 +351,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
+ 		if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
+ 			int err;
+ 
+-			if (static_key_true(&supports_deactivate))
++			if (static_branch_likely(&supports_deactivate_key))
+ 				gic_write_eoir(irqnr);
+ 			else
+ 				isb();
+@@ -359,7 +359,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
+ 			err = handle_domain_irq(gic_data.domain, irqnr, regs);
+ 			if (err) {
+ 				WARN_ONCE(true, "Unexpected interrupt received!\n");
+-				if (static_key_true(&supports_deactivate)) {
++				if (static_branch_likely(&supports_deactivate_key)) {
+ 					if (irqnr < 8192)
+ 						gic_write_dir(irqnr);
+ 				} else {
+@@ -370,7 +370,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
+ 		}
+ 		if (irqnr < 16) {
+ 			gic_write_eoir(irqnr);
+-			if (static_key_true(&supports_deactivate))
++			if (static_branch_likely(&supports_deactivate_key))
+ 				gic_write_dir(irqnr);
+ #ifdef CONFIG_SMP
+ 			/*
+@@ -547,7 +547,7 @@ static void gic_cpu_sys_reg_init(void)
+ 	 */
+ 	gic_write_bpr1(0);
+ 
+-	if (static_key_true(&supports_deactivate)) {
++	if (static_branch_likely(&supports_deactivate_key)) {
+ 		/* EOI drops priority only (mode 1) */
+ 		gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
+ 	} else {
+@@ -795,7 +795,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ {
+ 	struct irq_chip *chip = &gic_chip;
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		chip = &gic_eoimode1_chip;
+ 
+ 	/* SGIs are private to the core kernel */
+@@ -974,9 +974,9 @@ static int __init gic_init_bases(void __iomem *dist_base,
+ 	int err;
+ 
+ 	if (!is_hyp_mode_available())
+-		static_key_slow_dec(&supports_deactivate);
++		static_branch_disable(&supports_deactivate_key);
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		pr_info("GIC: Using split EOI/Deactivate mode\n");
+ 
+ 	gic_data.fwnode = handle;
+@@ -1232,7 +1232,7 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
+ 
+ 	gic_populate_ppi_partitions(node);
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		gic_of_setup_kvm_info(node);
+ 	return 0;
+ 
+@@ -1534,7 +1534,7 @@ gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
+ 
+ 	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		gic_acpi_setup_kvm_info();
+ 
+ 	return 0;
+diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
+index ac2e62d613d1..ced10c44b68a 100644
+--- a/drivers/irqchip/irq-gic.c
++++ b/drivers/irqchip/irq-gic.c
+@@ -121,7 +121,7 @@ static DEFINE_RAW_SPINLOCK(cpu_map_lock);
+ #define NR_GIC_CPU_IF 8
+ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+ 
+-static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
++static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
+ 
+ static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
+ 
+@@ -361,7 +361,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+ 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
+ 
+ 		if (likely(irqnr > 15 && irqnr < 1020)) {
+-			if (static_key_true(&supports_deactivate))
++			if (static_branch_likely(&supports_deactivate_key))
+ 				writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+ 			isb();
+ 			handle_domain_irq(gic->domain, irqnr, regs);
+@@ -369,7 +369,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+ 		}
+ 		if (irqnr < 16) {
+ 			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+-			if (static_key_true(&supports_deactivate))
++			if (static_branch_likely(&supports_deactivate_key))
+ 				writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
+ #ifdef CONFIG_SMP
+ 			/*
+@@ -466,7 +466,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
+ 	u32 mode = 0;
+ 	int i;
+ 
+-	if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
++	if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
+ 		mode = GIC_CPU_CTRL_EOImodeNS;
+ 
+ 	if (gic_check_gicv2(cpu_base))
+@@ -1219,11 +1219,11 @@ static int __init __gic_init_bases(struct gic_chip_data *gic,
+ 					  "irqchip/arm/gic:starting",
+ 					  gic_starting_cpu, NULL);
+ 		set_handle_irq(gic_handle_irq);
+-		if (static_key_true(&supports_deactivate))
++		if (static_branch_likely(&supports_deactivate_key))
+ 			pr_info("GIC: Using split EOI/Deactivate mode\n");
+ 	}
+ 
+-	if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
++	if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
+ 		name = kasprintf(GFP_KERNEL, "GICv2");
+ 		gic_init_chip(gic, NULL, name, true);
+ 	} else {
+@@ -1250,7 +1250,7 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
+ 	 * Non-DT/ACPI systems won't run a hypervisor, so let's not
+ 	 * bother with these...
+ 	 */
+-	static_key_slow_dec(&supports_deactivate);
++	static_branch_disable(&supports_deactivate_key);
+ 
+ 	gic = &gic_data[gic_nr];
+ 	gic->raw_dist_base = dist_base;
+@@ -1430,7 +1430,7 @@ static void __init gic_of_setup_kvm_info(struct device_node *node)
+ 	if (ret)
+ 		return;
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		gic_set_kvm_info(&gic_v2_kvm_info);
+ }
+ 
+@@ -1457,7 +1457,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
+ 	 * or the CPU interface is too small.
+ 	 */
+ 	if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
+-		static_key_slow_dec(&supports_deactivate);
++		static_branch_disable(&supports_deactivate_key);
+ 
+ 	ret = __gic_init_bases(gic, -1, &node->fwnode);
+ 	if (ret) {
+@@ -1638,7 +1638,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
+ 	 * interface will always be the right size.
+ 	 */
+ 	if (!is_hyp_mode_available())
+-		static_key_slow_dec(&supports_deactivate);
++		static_branch_disable(&supports_deactivate_key);
+ 
+ 	/*
+ 	 * Initialize GIC instance zero (no multi-GIC support).
+@@ -1663,7 +1663,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
+ 	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
+ 		gicv2m_init(NULL, gic_data[0].domain);
+ 
+-	if (static_key_true(&supports_deactivate))
++	if (static_branch_likely(&supports_deactivate_key))
+ 		gic_acpi_setup_kvm_info();
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/0794-PCI-rcar-gen2-Remove-duplicated-bit-wise-or-of-RCAR_.patch b/patches/0794-PCI-rcar-gen2-Remove-duplicated-bit-wise-or-of-RCAR_.patch
new file mode 100644
index 00000000000000..9f3196492c37da
--- /dev/null
+++ b/patches/0794-PCI-rcar-gen2-Remove-duplicated-bit-wise-or-of-RCAR_.patch
@@ -0,0 +1,34 @@
+From 41701fa17208c3ccc28919580d9dbfcd3c03886e Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 23 Feb 2018 12:29:49 +0000
+Subject: [PATCH 0794/1795] PCI: rcar-gen2: Remove duplicated bit-wise or of
+ RCAR_PCI_INT_SIGRETABORT
+
+Bit pattern RCAR_PCI_INT_SIGRETABORT is being bit-wise or'd twice;
+remove the redundant 2nd RCAR_PCI_INT_SIGRETABORT.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 38b35992b7d2729095a6e78a0f06f2f04c5a4e90)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pci-rcar-gen2.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
+index e46de69f0380..8b8eb14cecd5 100644
+--- a/drivers/pci/host/pci-rcar-gen2.c
++++ b/drivers/pci/host/pci-rcar-gen2.c
+@@ -55,7 +55,6 @@
+ #define RCAR_PCI_INT_B			(1 << 17)
+ #define RCAR_PCI_INT_PME		(1 << 19)
+ #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT		| \
+-				RCAR_PCI_INT_SIGRETABORT	| \
+ 				RCAR_PCI_INT_SIGRETABORT	| \
+ 				RCAR_PCI_INT_REMABORT		| \
+ 				RCAR_PCI_INT_PERR		| \
+-- 
+2.19.0
+
diff --git a/patches/0795-dt-bindings-PCI-rcar-Add-device-tree-support-for-r8a.patch b/patches/0795-dt-bindings-PCI-rcar-Add-device-tree-support-for-r8a.patch
new file mode 100644
index 00000000000000..86c405be7ac127
--- /dev/null
+++ b/patches/0795-dt-bindings-PCI-rcar-Add-device-tree-support-for-r8a.patch
@@ -0,0 +1,54 @@
+From cee03fb3254b9124e2fceb34881b28ff9fdfea20 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 14 Nov 2017 09:59:03 +0000
+Subject: [PATCH 0795/1795] dt-bindings: PCI: rcar: Add device tree support for
+ r8a7743
+
+Add support for r8a7743. The Renesas RZ/G1M(R8A7743)PCIe controller
+is identical to the R-Car Gen2 family.
+
+No driver change is needed due to the fallback compatible value
+"renesas,pcie-rcar-gen2".
+Adding the SoC-specific compatible values here has three purposes:
+1. Document which SoCs have this hardware module,
+2. Allow checkpatch to validate compatible values.
+3. Allow the driver to support SoC specific implementations in future
+   as necessary.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2380ca5f1f46412d08c96ebea996e049548829bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pci/rcar-pci.txt | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+index 76ba3a61d1a3..1fb614e615da 100644
+--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
++++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+@@ -1,13 +1,15 @@
+ * Renesas R-Car PCIe interface
+ 
+ Required properties:
+-compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
++compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
++	    "renesas,pcie-r8a7779" for the R8A7779 SoC;
+ 	    "renesas,pcie-r8a7790" for the R8A7790 SoC;
+ 	    "renesas,pcie-r8a7791" for the R8A7791 SoC;
+ 	    "renesas,pcie-r8a7793" for the R8A7793 SoC;
+ 	    "renesas,pcie-r8a7795" for the R8A7795 SoC;
+ 	    "renesas,pcie-r8a7796" for the R8A7796 SoC;
+-	    "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
++	    "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
++				     RZ/G1 compatible device.
+ 	    "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
+ 
+ 	    When compatible with the generic version, nodes must list the
+-- 
+2.19.0
+
diff --git a/patches/0796-PCI-rcar-Remove-unnecessary-semicolon.patch b/patches/0796-PCI-rcar-Remove-unnecessary-semicolon.patch
new file mode 100644
index 00000000000000..54093628d7e251
--- /dev/null
+++ b/patches/0796-PCI-rcar-Remove-unnecessary-semicolon.patch
@@ -0,0 +1,36 @@
+From e74c4019c97c74266b03557ec6ddfddddeee037d Mon Sep 17 00:00:00 2001
+From: Fengguang Wu <fengguang.wu@intel.com>
+Date: Wed, 7 Mar 2018 09:42:39 -0600
+Subject: [PATCH 0796/1795] PCI: rcar: Remove unnecessary semicolon
+
+Remove unneeded semicolon.
+
+Generated by: scripts/coccinelle/misc/semicolon.cocci
+
+Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
+Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
+Signed-off-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+(cherry picked from commit d17086728ca115cdb7efa40f9f4e0092648fee41)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 0c8b19e6a4c8..c37699d0dcf9 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -438,7 +438,7 @@ static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
+ 		}
+ 
+ 		msleep(1);
+-	};
++	}
+ 
+ 	dev_err(dev, "Speed change timed out\n");
+ 
+-- 
+2.19.0
+
diff --git a/patches/0797-net-phy-micrel-add-125MHz-reference-clock-workaround.patch b/patches/0797-net-phy-micrel-add-125MHz-reference-clock-workaround.patch
new file mode 100644
index 00000000000000..7320fd010f5b08
--- /dev/null
+++ b/patches/0797-net-phy-micrel-add-125MHz-reference-clock-workaround.patch
@@ -0,0 +1,104 @@
+From 19ddf4c6fa8607232fae16edfb339bbe2ee68bba Mon Sep 17 00:00:00 2001
+From: Markus Niebel <Markus.Niebel@tqs.de>
+Date: Tue, 15 May 2018 10:18:56 +0200
+Subject: [PATCH 0797/1795] net: phy: micrel: add 125MHz reference clock
+ workaround
+
+The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
+used as reference clock for the MAC unit. The clock signal must meet the
+RGMII requirements to ensure the correct data transmission between the
+MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
+requirement if the phy is configured as slave. For a complete
+describtion look at the errata sheets: DS80000691D or DS80000692D.
+
+The errata sheet recommends to force the phy into master mode whenever
+there is a 1000Base-T link-up as work around. Only set the
+"micrel,force-master" property if you use the phy reference clock provided
+by CLK125_NDO pin as MAC reference clock in your application.
+
+Attenation, this workaround is only usable if the link partner can
+be configured to slave mode for 1000Base-T.
+
+Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
+[m.felsch@pengutronix.de: fix dt-binding documentation]
+[m.felsch@pengutronix.de: use already existing result var for read/write]
+[m.felsch@pengutronix.de: add error handling]
+[m.felsch@pengutronix.de: add more comments]
+Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+
+(cherry picked from commit e1b505a60366399d735312ca38b0a6753a684123)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/net/micrel-ksz90x1.txt           |  7 +++++
+ drivers/net/phy/micrel.c                      | 31 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
+index 42a248301615..e22d8cfea687 100644
+--- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
++++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
+@@ -57,6 +57,13 @@ KSZ9031:
+       - txd2-skew-ps : Skew control of TX data 2 pad
+       - txd3-skew-ps : Skew control of TX data 3 pad
+ 
++    - micrel,force-master:
++        Boolean, force phy to master mode. Only set this option if the phy
++        reference clock provided at CLK125_NDO pin is used as MAC reference
++        clock because the clock jitter in slave mode is to high (errata#2).
++        Attention: The link partner must be configurable as slave otherwise
++        no link will be established.
++
+ Examples:
+ 
+ 	mdio {
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index e8831418075e..02dfb5fcd32e 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -573,9 +573,40 @@ static int ksz9031_config_init(struct phy_device *phydev)
+ 		ksz9031_of_load_skew_values(phydev, of_node,
+ 				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
+ 				tx_data_skews, 4);
++
++		/* Silicon Errata Sheet (DS80000691D or DS80000692D):
++		 * When the device links in the 1000BASE-T slave mode only,
++		 * the optional 125MHz reference output clock (CLK125_NDO)
++		 * has wide duty cycle variation.
++		 *
++		 * The optional CLK125_NDO clock does not meet the RGMII
++		 * 45/55 percent (min/max) duty cycle requirement and therefore
++		 * cannot be used directly by the MAC side for clocking
++		 * applications that have setup/hold time requirements on
++		 * rising and falling clock edges.
++		 *
++		 * Workaround:
++		 * Force the phy to be the master to receive a stable clock
++		 * which meets the duty cycle requirement.
++		 */
++		if (of_property_read_bool(of_node, "micrel,force-master")) {
++			result = phy_read(phydev, MII_CTRL1000);
++			if (result < 0)
++				goto err_force_master;
++
++			/* enable master mode, config & prefer master */
++			result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
++			result = phy_write(phydev, MII_CTRL1000, result);
++			if (result < 0)
++				goto err_force_master;
++		}
+ 	}
+ 
+ 	return ksz9031_center_flp_timing(phydev);
++
++err_force_master:
++	phydev_err(phydev, "failed to force the phy to master mode\n");
++	return result;
+ }
+ 
+ #define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
+-- 
+2.19.0
+
diff --git a/patches/0798-dt-bindings-rcar-gen3-phy-usb2-Add-bindings-for-r8a7.patch b/patches/0798-dt-bindings-rcar-gen3-phy-usb2-Add-bindings-for-r8a7.patch
new file mode 100644
index 00000000000000..c817042e1fb96f
--- /dev/null
+++ b/patches/0798-dt-bindings-rcar-gen3-phy-usb2-Add-bindings-for-r8a7.patch
@@ -0,0 +1,35 @@
+From 2dc2305f6f6f7b60bb98e6a3351c9a019345732b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 5 Mar 2018 14:32:43 +0900
+Subject: [PATCH 0798/1795] dt-bindings: rcar-gen3-phy-usb2: Add bindings for
+ r8a77965
+
+This patch adds support for r8a77965 (R-Car M3-N).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit b1ba68f33c0caa937032615833e3321d03d877b4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+index 99b651b33110..dbd137c079e2 100644
+--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
++++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+@@ -8,6 +8,8 @@ Required properties:
+ 	      SoC.
+ 	      "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
+ 	      SoC.
++	      "renesas,usb2-phy-r8a77965" if the device is a part of an
++	      R8A77965 SoC.
+ 	      "renesas,usb2-phy-r8a77995" if the device is a part of an
+ 	      R8A77995 SoC.
+ 	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
+-- 
+2.19.0
+
diff --git a/patches/0799-phy-rcar-gen3-usb2-Add-support-for-r8a77965.patch b/patches/0799-phy-rcar-gen3-usb2-Add-support-for-r8a77965.patch
new file mode 100644
index 00000000000000..12bef439ca8f3c
--- /dev/null
+++ b/patches/0799-phy-rcar-gen3-usb2-Add-support-for-r8a77965.patch
@@ -0,0 +1,36 @@
+From 8fcbf888583188443b2f8f91e1504643aae2e9e8 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 5 Mar 2018 14:32:44 +0900
+Subject: [PATCH 0799/1795] phy: rcar-gen3-usb2: Add support for r8a77965
+
+This patch adds support for r8a77965 (R-Car M3-N). This SoC has
+dedicated pins.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+(cherry picked from commit 44e42df6b91813c9d271044e35a7642402abf98c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+index 9c90e7d67e0a..fb8f05e39cf7 100644
+--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
++++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+@@ -396,6 +396,10 @@ static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
+ 		.compatible = "renesas,usb2-phy-r8a7796",
+ 		.data = (void *)RCAR_GEN3_PHY_HAS_DEDICATED_PINS,
+ 	},
++	{
++		.compatible = "renesas,usb2-phy-r8a77965",
++		.data = (void *)RCAR_GEN3_PHY_HAS_DEDICATED_PINS,
++	},
+ 	{
+ 		.compatible = "renesas,rcar-gen3-usb2-phy",
+ 	},
+-- 
+2.19.0
+
diff --git a/patches/0800-dt-bindings-pwm-rcar-Document-r8a774-35-PWM-bindings.patch b/patches/0800-dt-bindings-pwm-rcar-Document-r8a774-35-PWM-bindings.patch
new file mode 100644
index 00000000000000..17dba7fbfb39bb
--- /dev/null
+++ b/patches/0800-dt-bindings-pwm-rcar-Document-r8a774-35-PWM-bindings.patch
@@ -0,0 +1,63 @@
+From 1dabda99882aa96b4b40fbd70672571ea25bdc1e Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 20 Dec 2017 11:15:43 +0000
+Subject: [PATCH 0800/1795] dt-bindings: pwm: rcar: Document r8a774[35] PWM
+ bindings
+
+This patch adds compatible strings specific to r8a774[35], no driver
+change is needed as the fallback compatible string will activate the
+right code.
+
+Also, this patch replaces the example with a DT snippet used
+for adding PWM0 support to an r8a7743 based platform as the r8a7743 is
+now the first platform fully compatible with this driver and its PWM DT
+nodes refer to up-to-date code.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit 9d7e72858d9d84abbbb49e98e2dafeee2f7fd9b6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pwm/renesas,pwm-rcar.txt       | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+index 74c118015980..f3bba592d419 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+@@ -2,6 +2,8 @@
+ 
+ Required Properties:
+ - compatible: should be "renesas,pwm-rcar" and one of the following.
++ - "renesas,pwm-r8a7743": for RZ/G1M
++ - "renesas,pwm-r8a7745": for RZ/G1E
+  - "renesas,pwm-r8a7778": for R-Car M1A
+  - "renesas,pwm-r8a7779": for R-Car H1
+  - "renesas,pwm-r8a7790": for R-Car H2
+@@ -17,13 +19,15 @@ Required Properties:
+ - pinctrl-0: phandle, referring to a default pin configuration node.
+ - pinctrl-names: Set to "default".
+ 
+-Example: R8A7790 (R-Car H2) PWM Timer node
++Example: R8A7743 (RZ/G1M) PWM Timer node
+ 
+ 	pwm0: pwm@e6e30000 {
+-		compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
++		compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
+ 		reg = <0 0xe6e30000 0 0x8>;
++		clocks = <&cpg CPG_MOD 523>;
++		power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++		resets = <&cpg 523>;
+ 		#pwm-cells = <2>;
+-		clocks = <&mstp5_clks R8A7790_CLK_PWM>;
+ 		pinctrl-0 = <&pwm0_pins>;
+ 		pinctrl-names = "default";
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0801-dt-bindings-pwm-rcar-Add-bindings-for-R-Car-M3N-supp.patch b/patches/0801-dt-bindings-pwm-rcar-Add-bindings-for-R-Car-M3N-supp.patch
new file mode 100644
index 00000000000000..e35740cbede3b1
--- /dev/null
+++ b/patches/0801-dt-bindings-pwm-rcar-Add-bindings-for-R-Car-M3N-supp.patch
@@ -0,0 +1,35 @@
+From fceda974a23be3863dfada7661db034202356dee Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 9 Mar 2018 20:53:17 +0900
+Subject: [PATCH 0801/1795] dt-bindings: pwm: rcar: Add bindings for R-Car M3N
+ support
+
+This patch adds bindings for R-Car M3N. No driver update is needed.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit aa7c49328bd84cda3c4674b70eb10db0a94f89ab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+index f3bba592d419..35a3b9761ee5 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+@@ -11,6 +11,7 @@ Required Properties:
+  - "renesas,pwm-r8a7794": for R-Car E2
+  - "renesas,pwm-r8a7795": for R-Car H3
+  - "renesas,pwm-r8a7796": for R-Car M3-W
++ - "renesas,pwm-r8a77965": for R-Car M3-N
+  - "renesas,pwm-r8a77995": for R-Car D3
+ - reg: base address and length of the registers block for the PWM.
+ - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+-- 
+2.19.0
+
diff --git a/patches/0802-pwm-rcar-Use-PM-Runtime-to-control-module-clock.patch b/patches/0802-pwm-rcar-Use-PM-Runtime-to-control-module-clock.patch
new file mode 100644
index 00000000000000..6483ab09df6927
--- /dev/null
+++ b/patches/0802-pwm-rcar-Use-PM-Runtime-to-control-module-clock.patch
@@ -0,0 +1,46 @@
+From 431ddf5dddf1928a8fb902ebb18493f4289ab057 Mon Sep 17 00:00:00 2001
+From: Hien Dang <hien.dang.eb@renesas.com>
+Date: Tue, 13 Mar 2018 17:18:17 +0900
+Subject: [PATCH 0802/1795] pwm: rcar: Use PM Runtime to control module clock
+
+Runtime PM API (pm_runtime_get_sync/pm_runtime_put) should be used
+to control module clock instead of clk_prepare_enable and
+clk_disable_unprepare.
+
+Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit f2e6142cdc10b1b7edea8d65b07293f152e4d110)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pwm/pwm-rcar.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
+index 0fcf94ffad32..f4d8767f804e 100644
+--- a/drivers/pwm/pwm-rcar.c
++++ b/drivers/pwm/pwm-rcar.c
+@@ -134,16 +134,12 @@ static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
+ 
+ static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+ {
+-	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
+-
+-	return clk_prepare_enable(rp->clk);
++	return pm_runtime_get_sync(chip->dev);
+ }
+ 
+ static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+ {
+-	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
+-
+-	clk_disable_unprepare(rp->clk);
++	pm_runtime_put(chip->dev);
+ }
+ 
+ static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+-- 
+2.19.0
+
diff --git a/patches/0803-pwm-rcar-Add-suspend-resume-support.patch b/patches/0803-pwm-rcar-Add-suspend-resume-support.patch
new file mode 100644
index 00000000000000..c3e4517d75309e
--- /dev/null
+++ b/patches/0803-pwm-rcar-Add-suspend-resume-support.patch
@@ -0,0 +1,77 @@
+From fc761bff77fdab12ed9f0e5c798080c55405fd59 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 13 Mar 2018 17:18:18 +0900
+Subject: [PATCH 0803/1795] pwm: rcar: Add suspend/resume support
+
+This patch adds suspend/resume support for Renesas PWM driver.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit 6873842235d678a245a378669f35e145df2441b9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pwm/pwm-rcar.c | 42 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
+index f4d8767f804e..91d11f2e2fef 100644
+--- a/drivers/pwm/pwm-rcar.c
++++ b/drivers/pwm/pwm-rcar.c
+@@ -258,11 +258,53 @@ static const struct of_device_id rcar_pwm_of_table[] = {
+ };
+ MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
+ 
++#ifdef CONFIG_PM_SLEEP
++static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
++	struct pwm_chip *chip = &rcar_pwm->chip;
++
++	return &chip->pwms[0];
++}
++
++static int rcar_pwm_suspend(struct device *dev)
++{
++	struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
++
++	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
++		return 0;
++
++	pm_runtime_put(dev);
++
++	return 0;
++}
++
++static int rcar_pwm_resume(struct device *dev)
++{
++	struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
++
++	if (!test_bit(PWMF_REQUESTED, &pwm->flags))
++		return 0;
++
++	pm_runtime_get_sync(dev);
++
++	rcar_pwm_config(pwm->chip, pwm, pwm->state.duty_cycle,
++			pwm->state.period);
++	if (pwm_is_enabled(pwm))
++		rcar_pwm_enable(pwm->chip, pwm);
++
++	return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume);
++
+ static struct platform_driver rcar_pwm_driver = {
+ 	.probe = rcar_pwm_probe,
+ 	.remove = rcar_pwm_remove,
+ 	.driver = {
+ 		.name = "pwm-rcar",
++		.pm	= &rcar_pwm_pm_ops,
+ 		.of_match_table = of_match_ptr(rcar_pwm_of_table),
+ 	}
+ };
+-- 
+2.19.0
+
diff --git a/patches/0804-dt-bindings-pwm-renesas-tpu-Document-r8a774-35-suppo.patch b/patches/0804-dt-bindings-pwm-renesas-tpu-Document-r8a774-35-suppo.patch
new file mode 100644
index 00000000000000..9123816293b36d
--- /dev/null
+++ b/patches/0804-dt-bindings-pwm-renesas-tpu-Document-r8a774-35-suppo.patch
@@ -0,0 +1,42 @@
+From 186ac4a972eef82cebdd05d567a28bd913ff728f Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 19 Dec 2017 13:34:59 +0000
+Subject: [PATCH 0804/1795] dt-bindings: pwm: renesas-tpu: Document r8a774[35]
+ support
+
+Document r8a774[35] specific compatible strings. No driver change is
+needed as the fallback compatible string "renesas,tpu" activates the
+right code in the driver.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit 3ba111a0182265b65e303c969294b8033ce9d122)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+index 1aadc804dae4..16e574821668 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+@@ -5,8 +5,10 @@ Required Properties:
+   - compatible: should be one of the following.
+     - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
+     - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
++    - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
++    - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
+     - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
+-    - "renesas,tpu": for generic R-Car TPU PWM controller.
++    - "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller.
+ 
+   - reg: Base address and length of each memory resource used by the PWM
+     controller hardware module.
+-- 
+2.19.0
+
diff --git a/patches/0805-dt-bindings-pwm-renesas-tpu-Correct-example-TPU-regi.patch b/patches/0805-dt-bindings-pwm-renesas-tpu-Correct-example-TPU-regi.patch
new file mode 100644
index 00000000000000..ae88049caee3b9
--- /dev/null
+++ b/patches/0805-dt-bindings-pwm-renesas-tpu-Correct-example-TPU-regi.patch
@@ -0,0 +1,35 @@
+From 7ebfa14da3e16407bd80358c2082913ec87b2023 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 19 Dec 2017 17:02:06 +0100
+Subject: [PATCH 0805/1795] dt-bindings: pwm: renesas-tpu: Correct example TPU
+ register block size
+
+The Timer Pulse Unit on R-Mobile A1 has registers that lie outside the
+declared register block.  Enlarge the register block size to fix this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <simon.horman@netronome.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit 3b8ad2c1effedf2fed4ad989612386b5cff11289)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+index 16e574821668..d52e30ed8072 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+@@ -24,6 +24,6 @@ Example: R8A7740 (R-Car A1) TPU controller node
+ 
+ 	tpu: pwm@e6600000 {
+ 		compatible = "renesas,tpu-r8a7740", "renesas,tpu";
+-		reg = <0xe6600000 0x100>;
++		reg = <0xe6600000 0x148>;
+ 		#pwm-cells = <3>;
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/0806-dt-bindings-pwm-renesas-tpu-Correct-SoC-part-numbers.patch b/patches/0806-dt-bindings-pwm-renesas-tpu-Correct-SoC-part-numbers.patch
new file mode 100644
index 00000000000000..2ff9b4a5796c05
--- /dev/null
+++ b/patches/0806-dt-bindings-pwm-renesas-tpu-Correct-SoC-part-numbers.patch
@@ -0,0 +1,45 @@
+From 811e0897dc1a22beef454a69af3c8aa9242ddb89 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 15:39:45 +0100
+Subject: [PATCH 0806/1795] dt-bindings: pwm: renesas-tpu: Correct SoC part
+ numbers and family names
+
+R8A73A4 (not R8A77A4) is R-Mobile APE6,
+R8A7740 is R-Mobile (not R-Car) A1.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+(cherry picked from commit 204e17baa6fd2ec02deca08cdcb60aad77cbd043)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+index d52e30ed8072..d53a16715da6 100644
+--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
++++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+@@ -3,7 +3,7 @@
+ Required Properties:
+ 
+   - compatible: should be one of the following.
+-    - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
++    - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller.
+     - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
+     - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
+     - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
+@@ -20,7 +20,7 @@ Required Properties:
+ Please refer to pwm.txt in this directory for details of the common PWM bindings
+ used by client devices.
+ 
+-Example: R8A7740 (R-Car A1) TPU controller node
++Example: R8A7740 (R-Mobile A1) TPU controller node
+ 
+ 	tpu: pwm@e6600000 {
+ 		compatible = "renesas,tpu-r8a7740", "renesas,tpu";
+-- 
+2.19.0
+
diff --git a/patches/0807-ravb-add-support-for-changing-MTU.patch b/patches/0807-ravb-add-support-for-changing-MTU.patch
new file mode 100644
index 00000000000000..4cde55bfe0047c
--- /dev/null
+++ b/patches/0807-ravb-add-support-for-changing-MTU.patch
@@ -0,0 +1,144 @@
+From 7586f40495ecb60bee2f1f81641e08fa2860619a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 16 Feb 2018 17:10:08 +0100
+Subject: [PATCH 0807/1795] ravb: add support for changing MTU
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Allow for changing the MTU within the limit of the maximum size of a
+descriptor (2048 bytes). Add the callback to change MTU from user-space
+and take the configurable MTU into account when configuring the
+hardware.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 75efa06f457bbed3931bf693b7137cf4da3b5c80)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb.h      |  1 +
+ drivers/net/ethernet/renesas/ravb_main.c | 34 +++++++++++++++++++-----
+ 2 files changed, 28 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
+index 96a27b00c90e..b81f4faf7b10 100644
+--- a/drivers/net/ethernet/renesas/ravb.h
++++ b/drivers/net/ethernet/renesas/ravb.h
+@@ -1018,6 +1018,7 @@ struct ravb_private {
+ 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
+ 	u32 cur_tx[NUM_TX_QUEUE];
+ 	u32 dirty_tx[NUM_TX_QUEUE];
++	u32 rx_buf_sz;			/* Based on MTU+slack. */
+ 	struct napi_struct napi[NUM_RX_QUEUE];
+ 	struct work_struct work;
+ 	/* MII transceiver section. */
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index e38d25d981e3..ab6cce5d144c 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -238,7 +238,7 @@ static void ravb_ring_free(struct net_device *ndev, int q)
+ 					       le32_to_cpu(desc->dptr)))
+ 				dma_unmap_single(ndev->dev.parent,
+ 						 le32_to_cpu(desc->dptr),
+-						 PKT_BUF_SZ,
++						 priv->rx_buf_sz,
+ 						 DMA_FROM_DEVICE);
+ 		}
+ 		ring_size = sizeof(struct ravb_ex_rx_desc) *
+@@ -300,9 +300,9 @@ static void ravb_ring_format(struct net_device *ndev, int q)
+ 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
+ 		/* RX descriptor */
+ 		rx_desc = &priv->rx_ring[q][i];
+-		rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
++		rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
+ 		dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
+-					  PKT_BUF_SZ,
++					  priv->rx_buf_sz,
+ 					  DMA_FROM_DEVICE);
+ 		/* We just set the data size to 0 for a failed mapping which
+ 		 * should prevent DMA from happening...
+@@ -346,6 +346,10 @@ static int ravb_ring_init(struct net_device *ndev, int q)
+ 	int ring_size;
+ 	int i;
+ 
++	/* +16 gets room from the status from the card. */
++	priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
++		ETH_HLEN + VLAN_HLEN;
++
+ 	/* Allocate RX and TX skb rings */
+ 	priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
+ 				  sizeof(*priv->rx_skb[q]), GFP_KERNEL);
+@@ -355,7 +359,7 @@ static int ravb_ring_init(struct net_device *ndev, int q)
+ 		goto error;
+ 
+ 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
+-		skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
++		skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1);
+ 		if (!skb)
+ 			goto error;
+ 		ravb_set_buffer_align(skb);
+@@ -586,7 +590,7 @@ static bool ravb_rx(struct net_device *ndev, int *quota, int q)
+ 			skb = priv->rx_skb[q][entry];
+ 			priv->rx_skb[q][entry] = NULL;
+ 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
+-					 PKT_BUF_SZ,
++					 priv->rx_buf_sz,
+ 					 DMA_FROM_DEVICE);
+ 			get_ts &= (q == RAVB_NC) ?
+ 					RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
+@@ -619,11 +623,12 @@ static bool ravb_rx(struct net_device *ndev, int *quota, int q)
+ 	for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
+ 		entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
+ 		desc = &priv->rx_ring[q][entry];
+-		desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
++		desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
+ 
+ 		if (!priv->rx_skb[q][entry]) {
+ 			skb = netdev_alloc_skb(ndev,
+-					       PKT_BUF_SZ + RAVB_ALIGN - 1);
++					       priv->rx_buf_sz +
++					       RAVB_ALIGN - 1);
+ 			if (!skb)
+ 				break;	/* Better luck next round. */
+ 			ravb_set_buffer_align(skb);
+@@ -1830,6 +1835,17 @@ static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+ 	return phy_mii_ioctl(phydev, req, cmd);
+ }
+ 
++static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
++{
++	if (netif_running(ndev))
++		return -EBUSY;
++
++	ndev->mtu = new_mtu;
++	netdev_update_features(ndev);
++
++	return 0;
++}
++
+ static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
+ {
+ 	struct ravb_private *priv = netdev_priv(ndev);
+@@ -1871,6 +1887,7 @@ static const struct net_device_ops ravb_netdev_ops = {
+ 	.ndo_set_rx_mode	= ravb_set_rx_mode,
+ 	.ndo_tx_timeout		= ravb_tx_timeout,
+ 	.ndo_do_ioctl		= ravb_do_ioctl,
++	.ndo_change_mtu		= ravb_change_mtu,
+ 	.ndo_validate_addr	= eth_validate_addr,
+ 	.ndo_set_mac_address	= eth_mac_addr,
+ 	.ndo_set_features	= ravb_set_features,
+@@ -2093,6 +2110,9 @@ static int ravb_probe(struct platform_device *pdev)
+ 		goto out_release;
+ 	}
+ 
++	ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
++	ndev->min_mtu = ETH_MIN_MTU;
++
+ 	/* Set function */
+ 	ndev->netdev_ops = &ravb_netdev_ops;
+ 	ndev->ethtool_ops = &ravb_ethtool_ops;
+-- 
+2.19.0
+
diff --git a/patches/0808-ravb-remove-erroneous-comment.patch b/patches/0808-ravb-remove-erroneous-comment.patch
new file mode 100644
index 00000000000000..ba5adfbf829d2b
--- /dev/null
+++ b/patches/0808-ravb-remove-erroneous-comment.patch
@@ -0,0 +1,40 @@
+From 9a289b0175a13afd0016c49d2b686ef952035a89 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 3 Mar 2018 23:39:54 +0100
+Subject: [PATCH 0808/1795] ravb: remove erroneous comment
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When addressing a review comment in a early version of the offending
+patch a comment where left in which should have been removed. Remove the
+comment to keep it consistent with the code.
+
+Fixes: 75efa06f457bbed3 ("ravb: add support for changing MTU")
+Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 5c3d0fd4b2c047cedb1cbdad6e2d6bc9abfec256)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index ab6cce5d144c..40266fe01186 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -346,7 +346,6 @@ static int ravb_ring_init(struct net_device *ndev, int q)
+ 	int ring_size;
+ 	int i;
+ 
+-	/* +16 gets room from the status from the card. */
+ 	priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
+ 		ETH_HLEN + VLAN_HLEN;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0809-dt-bindings-net-renesas-ravb-Add-support-for-r8a7747.patch b/patches/0809-dt-bindings-net-renesas-ravb-Add-support-for-r8a7747.patch
new file mode 100644
index 00000000000000..4a179b26d0fb88
--- /dev/null
+++ b/patches/0809-dt-bindings-net-renesas-ravb-Add-support-for-r8a7747.patch
@@ -0,0 +1,35 @@
+From 88b4731d1c787a43c26b84d08790bbcc57e518be Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Thu, 29 Mar 2018 11:02:55 +0100
+Subject: [PATCH 0809/1795] dt-bindings: net: renesas-ravb: Add support for
+ r8a77470 SoC
+
+Add a new compatible string for the RZ/G1C (R8A77470) SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 9b85756341c53fd13b4b5e25104c22849274cd0d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index b4dc455eb155..c306f55d335b 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -7,6 +7,7 @@ Required properties:
+ - compatible: Must contain one or more of the following:
+       - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
+       - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
++      - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
+       - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
+       - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
+       - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
+-- 
+2.19.0
+
diff --git a/patches/0810-dt-bindings-net-ravb-Add-support-for-r8a77965-SoC.patch b/patches/0810-dt-bindings-net-ravb-Add-support-for-r8a77965-SoC.patch
new file mode 100644
index 00000000000000..910c83bc6adcce
--- /dev/null
+++ b/patches/0810-dt-bindings-net-ravb-Add-support-for-r8a77965-SoC.patch
@@ -0,0 +1,36 @@
+From 962077fc31cbaac0aaf1ad853ec0e94eb4550850 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Mon, 16 Apr 2018 15:55:17 +0200
+Subject: [PATCH 0810/1795] dt-bindings: net: ravb: Add support for r8a77965
+ SoC
+
+Add documentation for r8a77965 compatible string to renesas ravb device
+tree bindings documentation.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 1a862488729a6ea9cfd285d2c90f8738949ae7d2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index c306f55d335b..890526dbfc26 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -18,6 +18,7 @@ Required properties:
+ 
+       - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+       - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
++      - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
+       - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
+       - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+       - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
+-- 
+2.19.0
+
diff --git a/patches/0811-dt-bindings-can-rcar_can-Fix-R8A7796-SoC-name.patch b/patches/0811-dt-bindings-can-rcar_can-Fix-R8A7796-SoC-name.patch
new file mode 100644
index 00000000000000..cbab3462f1daa3
--- /dev/null
+++ b/patches/0811-dt-bindings-can-rcar_can-Fix-R8A7796-SoC-name.patch
@@ -0,0 +1,33 @@
+From 5bb6d556b64b69a60af83042a0ce6d11775c30fe Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 15:02:33 +0200
+Subject: [PATCH 0811/1795] dt-bindings: can: rcar_can: Fix R8A7796 SoC name
+
+R8A7796 is R-Car M3-W.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+(cherry picked from commit 1469c5f033a287dc25d113ea65c498c0603fbaa1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+index 93c3a6ae32f9..1a4ee1d2506d 100644
+--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
++++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+@@ -5,7 +5,7 @@ Required properties:
+ - compatible: Must contain one or more of the following:
+   - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+   - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+-  - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3) compatible controller.
++  - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
+ 
+   When compatible with the generic version, nodes must list the
+   SoC-specific version corresponding to the platform first, followed by the
+-- 
+2.19.0
+
diff --git a/patches/0812-DT-net-can-rcar_canfd-document-R8A77970-bindings.patch b/patches/0812-DT-net-can-rcar_canfd-document-R8A77970-bindings.patch
new file mode 100644
index 00000000000000..7f1c0084028313
--- /dev/null
+++ b/patches/0812-DT-net-can-rcar_canfd-document-R8A77970-bindings.patch
@@ -0,0 +1,34 @@
+From 7549299922ff8953f3a8c61428d5d81d45ec9019 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 26 Apr 2018 22:41:14 +0300
+Subject: [PATCH 0812/1795] DT: net: can: rcar_canfd: document R8A77970
+ bindings
+
+Document the R-Car V3M (R8A77970) SoC support in the R-Car CAN-FD bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+(cherry picked from commit 0a4fe40efb04686529d998716d1680429d0b586b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+index 1a4ee1d2506d..59dd13aab97f 100644
+--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
++++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+@@ -6,6 +6,7 @@ Required properties:
+   - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+   - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+   - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
++  - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
+ 
+   When compatible with the generic version, nodes must list the
+   SoC-specific version corresponding to the platform first, followed by the
+-- 
+2.19.0
+
diff --git a/patches/0813-DT-net-can-rcar_canfd-document-R8A77980-bindings.patch b/patches/0813-DT-net-can-rcar_canfd-document-R8A77980-bindings.patch
new file mode 100644
index 00000000000000..39bff4a1dfeef1
--- /dev/null
+++ b/patches/0813-DT-net-can-rcar_canfd-document-R8A77980-bindings.patch
@@ -0,0 +1,33 @@
+From 5bbbfdf5d5db5e9c4ccb530dd124eaaea48500eb Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 27 Apr 2018 21:53:33 +0300
+Subject: [PATCH 0813/1795] DT: net: can: rcar_canfd: document R8A77980
+ bindings
+
+Document the R-Car V3H (R8A77980) SoC support in the R-Car CAN-FD bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+(cherry picked from commit 7a25ac2f71a409e77dd5c85cf3cbe1cbf2ae77f3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+index 59dd13aab97f..ac71daa46195 100644
+--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
++++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+@@ -7,6 +7,7 @@ Required properties:
+   - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+   - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
+   - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
++  - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
+ 
+   When compatible with the generic version, nodes must list the
+   SoC-specific version corresponding to the platform first, followed by the
+-- 
+2.19.0
+
diff --git a/patches/0814-DT-dmaengine-renesas-rcar-dmac-document-R8A77980-sup.patch b/patches/0814-DT-dmaengine-renesas-rcar-dmac-document-R8A77980-sup.patch
new file mode 100644
index 00000000000000..38101c18a3a4f1
--- /dev/null
+++ b/patches/0814-DT-dmaengine-renesas-rcar-dmac-document-R8A77980-sup.patch
@@ -0,0 +1,36 @@
+From 5842f2ebab37a950a268dcdd31e85571796a3846 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 1 Feb 2018 22:09:25 +0300
+Subject: [PATCH 0814/1795] DT: dmaengine: renesas,rcar-dmac: document R8A77980
+ support
+
+Renesas  R-Car V3H SoC has the R-Car gen3 compatible DMA controllers.
+Document R-Car V3H (also known as R8A77980) SoC bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+(cherry picked from commit 9bfda6636edd5db9b3cdbb2df6483ceb7618ec6a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+index 98d7898fcd78..b7f3e6044ed7 100644
+--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
++++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+@@ -27,6 +27,7 @@ Required Properties:
+ 		- "renesas,dmac-r8a7796" (R-Car M3-W)
+ 		- "renesas,dmac-r8a77965" (R-Car M3-N)
+ 		- "renesas,dmac-r8a77970" (R-Car V3M)
++		- "renesas,dmac-r8a77980" (R-Car V3H)
+ 
+ - reg: base address and length of the registers block for the DMAC
+ 
+-- 
+2.19.0
+
diff --git a/patches/0815-dmaengine-rcar-dmac-Fix-too-early-late-system-suspen.patch b/patches/0815-dmaengine-rcar-dmac-Fix-too-early-late-system-suspen.patch
new file mode 100644
index 00000000000000..aa36f38871e5c9
--- /dev/null
+++ b/patches/0815-dmaengine-rcar-dmac-Fix-too-early-late-system-suspen.patch
@@ -0,0 +1,50 @@
+From 2dac38fe2015e2bd4c23ea1f6398e7dcee1ce5ba Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 18:53:32 +0200
+Subject: [PATCH 0815/1795] dmaengine: rcar-dmac: Fix too early/late system
+ suspend/resume callbacks
+
+If serial console wake-up is enabled ("echo enabled >
+/sys/.../ttySC0/power/wakeup"), and any serial input is received while
+the system is suspended, serial port input no longer works after system
+resume.
+
+Note that:
+  1) The system can still be woken up using the serial console,
+  2) Serial port input keeps working if the system is woken up in some
+     other way (e.g. Wake-on-LAN or gpio-keys), and no serial input was
+     received while suspended.
+
+To fix this, replace SET_LATE_SYSTEM_SLEEP_PM_OPS() by
+SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(), as the callbacks installed by the
+former happen too early resp. late in the suspend resp. resume process.
+
+Reported-by: RVC test team via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Fixes: 1131b0a4af911de5 ("dmaengine: rcar-dmac: Make DMAC reinit during system resume explicit")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+(cherry picked from commit 73dcc666d6bd0db56cd556010f93d8f04c1cc70c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index ed8d934d5f48..2a2ccd9c78e4 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -1686,8 +1686,8 @@ static const struct dev_pm_ops rcar_dmac_pm = {
+ 	 *   - Wait for the current transfer to complete and stop the device,
+ 	 *   - Resume transfers, if any.
+ 	 */
+-	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+-				     pm_runtime_force_resume)
++	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				      pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
+ 			   NULL)
+ };
+-- 
+2.19.0
+
diff --git a/patches/0816-dt-bindings-rcar-dmac-Document-r8a77470-support.patch b/patches/0816-dt-bindings-rcar-dmac-Document-r8a77470-support.patch
new file mode 100644
index 00000000000000..48714712d0a6e7
--- /dev/null
+++ b/patches/0816-dt-bindings-rcar-dmac-Document-r8a77470-support.patch
@@ -0,0 +1,35 @@
+From f895671ef6265d22d5fbd73b793d4b76f7d6f4a1 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Thu, 29 Mar 2018 11:11:06 +0100
+Subject: [PATCH 0816/1795] dt-bindings: rcar-dmac: Document r8a77470 support
+
+Renesas  RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
+Document RZ/G1C (also known as R8A77470) SoC bindings.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+(cherry picked from commit a0b007e1ef1cb5b7f8d4be296beeb0a097af57ac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+index b7f3e6044ed7..61315eaa7660 100644
+--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
++++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+@@ -18,6 +18,7 @@ Required Properties:
+ 	      Examples with soctypes are:
+ 		- "renesas,dmac-r8a7743" (RZ/G1M)
+ 		- "renesas,dmac-r8a7745" (RZ/G1E)
++		- "renesas,dmac-r8a77470" (RZ/G1C)
+ 		- "renesas,dmac-r8a7790" (R-Car H2)
+ 		- "renesas,dmac-r8a7791" (R-Car M2-W)
+ 		- "renesas,dmac-r8a7792" (R-Car V2H)
+-- 
+2.19.0
+
diff --git a/patches/0817-soc-renesas-rcar-rst-add-R8A77980-support.patch b/patches/0817-soc-renesas-rcar-rst-add-R8A77980-support.patch
new file mode 100644
index 00000000000000..5b0725b6a71c3b
--- /dev/null
+++ b/patches/0817-soc-renesas-rcar-rst-add-R8A77980-support.patch
@@ -0,0 +1,60 @@
+From 9d9fbc6c852474f4be413f55494c88699e7dd5e9 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:27:01 +0300
+Subject: [PATCH 0817/1795] soc: renesas: rcar-rst: add R8A77980 support
+
+Add support for R-Car V3H (R8A77980) to the R-Car RST driver -- this driver
+is needed for the clock driver to work.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7d7b619e16d420b723d6618c60a0aaf0ba4e3666)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
+ drivers/soc/renesas/Kconfig                             | 2 +-
+ drivers/soc/renesas/rcar-rst.c                          | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+index a8014f3ab8ba..a55b88658446 100644
+--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
++++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+@@ -27,6 +27,7 @@ Required properties:
+ 		  - "renesas,r8a7795-rst" (R-Car H3)
+ 		  - "renesas,r8a7796-rst" (R-Car M3-W)
+ 		  - "renesas,r8a77970-rst" (R-Car V3M)
++		  - "renesas,r8a77980-rst" (R-Car V3H)
+ 		  - "renesas,r8a77995-rst" (R-Car D3)
+   - reg: Address start and address range for the device.
+ 
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 09550b1da56d..6efd7bef8577 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -4,7 +4,7 @@ config SOC_RENESAS
+ 	select SOC_BUS
+ 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
+ 			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \
+-			   ARCH_R8A77995
++			   ARCH_R8A77980 || ARCH_R8A77995
+ 	select SYSC_R8A7743 if ARCH_R8A7743
+ 	select SYSC_R8A7745 if ARCH_R8A7745
+ 	select SYSC_R8A7779 if ARCH_R8A7779
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index 3316b028f231..e2340eb9ea9c 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -42,6 +42,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 },
++	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
+ 	{ /* sentinel */ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/0818-soc-renesas-rcar-rst-Enable-watchdog-as-reset-trigge.patch b/patches/0818-soc-renesas-rcar-rst-Enable-watchdog-as-reset-trigge.patch
new file mode 100644
index 00000000000000..cbeaf09c3a5737
--- /dev/null
+++ b/patches/0818-soc-renesas-rcar-rst-Enable-watchdog-as-reset-trigge.patch
@@ -0,0 +1,93 @@
+From 195ea4963c712a668de671735fb5a12ccc597e7e Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Tue, 13 Feb 2018 13:02:44 +0000
+Subject: [PATCH 0818/1795] soc: renesas: rcar-rst: Enable watchdog as reset
+ trigger for Gen2
+
+This patch allows for platform specific quirks as some of the SoC need
+further customization for the watchdog to work properly, like for R-Car
+Gen2 and for RZ/G.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 69e0d1b8db8f8cc319f966ec3eb2fffce28c4f28)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/rcar-rst.c | 37 +++++++++++++++++++++++++++-------
+ 1 file changed, 30 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index e2340eb9ea9c..34136664ece4 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -13,8 +13,18 @@
+ #include <linux/of_address.h>
+ #include <linux/soc/renesas/rcar-rst.h>
+ 
++#define WDTRSTCR_RESET		0xA55A0002
++#define WDTRSTCR		0x0054
++
++static int rcar_rst_enable_wdt_reset(void __iomem *base)
++{
++	iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
++	return 0;
++}
++
+ struct rst_config {
+-	unsigned int modemr;	/* Mode Monitoring Register Offset */
++	unsigned int modemr;		/* Mode Monitoring Register Offset */
++	int (*configure)(void *base);	/* Platform specific configuration */
+ };
+ 
+ static const struct rst_config rcar_rst_gen1 __initconst = {
+@@ -23,6 +33,11 @@ static const struct rst_config rcar_rst_gen1 __initconst = {
+ 
+ static const struct rst_config rcar_rst_gen2 __initconst = {
+ 	.modemr = 0x60,
++	.configure = rcar_rst_enable_wdt_reset,
++};
++
++static const struct rst_config rcar_rst_gen3 __initconst = {
++	.modemr = 0x60,
+ };
+ 
+ static const struct of_device_id rcar_rst_matches[] __initconst = {
+@@ -38,12 +53,12 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	{ .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
+-	/* R-Car Gen3 is handled like R-Car Gen2 */
+-	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
+-	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
+-	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 },
+-	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen2 },
+-	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
++	/* R-Car Gen3 */
++	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
+ 	{ /* sentinel */ }
+ };
+ 
+@@ -72,6 +87,14 @@ static int __init rcar_rst_init(void)
+ 	rcar_rst_base = base;
+ 	cfg = match->data;
+ 	saved_mode = ioread32(base + cfg->modemr);
++	if (cfg->configure) {
++		error = cfg->configure(base);
++		if (error) {
++			pr_warn("%pOF: Cannot run SoC specific configuration\n",
++				np);
++			goto out_put;
++		}
++	}
+ 
+ 	pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0819-soc-renesas-rcar-rst-Add-support-for-R-Car-M3-N.patch b/patches/0819-soc-renesas-rcar-rst-Add-support-for-R-Car-M3-N.patch
new file mode 100644
index 00000000000000..8b734d3ab70cfa
--- /dev/null
+++ b/patches/0819-soc-renesas-rcar-rst-Add-support-for-R-Car-M3-N.patch
@@ -0,0 +1,59 @@
+From a6df0f48845282c35bb934b4eb9648399e16d1e4 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:04 +0100
+Subject: [PATCH 0819/1795] soc: renesas: rcar-rst: Add support for R-Car M3-N
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bf79cd635db50fab2319add2462cf803ff76d346)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
+ drivers/soc/renesas/Kconfig                             | 4 ++--
+ drivers/soc/renesas/rcar-rst.c                          | 1 +
+ 3 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+index a55b88658446..294a0dae106a 100644
+--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
++++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+@@ -26,6 +26,7 @@ Required properties:
+ 		  - "renesas,r8a7794-rst" (R-Car E2)
+ 		  - "renesas,r8a7795-rst" (R-Car H3)
+ 		  - "renesas,r8a7796-rst" (R-Car M3-W)
++		  - "renesas,r8a77965-rst" (R-Car M3-N)
+ 		  - "renesas,r8a77970-rst" (R-Car V3M)
+ 		  - "renesas,r8a77980-rst" (R-Car V3H)
+ 		  - "renesas,r8a77995-rst" (R-Car D3)
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 6efd7bef8577..741b7cd8f311 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -3,8 +3,8 @@ config SOC_RENESAS
+ 	default y if ARCH_RENESAS
+ 	select SOC_BUS
+ 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
+-			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \
+-			   ARCH_R8A77980 || ARCH_R8A77995
++			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
++			   ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77995
+ 	select SYSC_R8A7743 if ARCH_R8A7743
+ 	select SYSC_R8A7745 if ARCH_R8A7745
+ 	select SYSC_R8A7779 if ARCH_R8A7779
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index 34136664ece4..8e9cb7996ab0 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -56,6 +56,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	/* R-Car Gen3 */
+ 	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
+-- 
+2.19.0
+
diff --git a/patches/0820-media-dt-bindings-media-rcar_vin-Use-status-okay.patch b/patches/0820-media-dt-bindings-media-rcar_vin-Use-status-okay.patch
new file mode 100644
index 00000000000000..b281f64a8fdd20
--- /dev/null
+++ b/patches/0820-media-dt-bindings-media-rcar_vin-Use-status-okay.patch
@@ -0,0 +1,49 @@
+From c30941e914b553c76664461435e2eece916e32ba Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 9 Mar 2018 04:34:40 -0500
+Subject: [PATCH 0820/1795] media: dt-bindings: media: rcar_vin: Use status
+ "okay"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+According to the Devicetree Specification, "ok" is not a valid status.
+
+Fixes: 47c71bd61b772cd7 ("[media] rcar_vin: add devicetree support")
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 1dd5e986a9b9794a314ee59aca3fbbbf209c2076)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/media/rcar_vin.txt | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
+index 6e4ef8caf759..033246ab9a01 100644
+--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
++++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
+@@ -56,7 +56,7 @@ Board setup example (vin1 composite video input)
+ ------------------------------------------------
+ 
+ &i2c2   {
+-        status = "ok";
++        status = "okay";
+         pinctrl-0 = <&i2c2_pins>;
+         pinctrl-names = "default";
+ 
+@@ -79,7 +79,7 @@ Board setup example (vin1 composite video input)
+         pinctrl-0 = <&vin1_pins>;
+         pinctrl-names = "default";
+ 
+-        status = "ok";
++        status = "okay";
+ 
+         port {
+                 #address-cells = <1>;
+-- 
+2.19.0
+
diff --git a/patches/0821-media-rcar-vin-allocate-a-scratch-buffer-at-stream-s.patch b/patches/0821-media-rcar-vin-allocate-a-scratch-buffer-at-stream-s.patch
new file mode 100644
index 00000000000000..87b2cdb7b10094
--- /dev/null
+++ b/patches/0821-media-rcar-vin-allocate-a-scratch-buffer-at-stream-s.patch
@@ -0,0 +1,99 @@
+From 23043a90a1fd7f49acf114ee2735805ab4599d21 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 13 Mar 2018 22:49:09 -0400
+Subject: [PATCH 0821/1795] media: rcar-vin: allocate a scratch buffer at
+ stream start
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Before starting a capture, allocate a scratch buffer which can be used
+by the driver to give to the hardware if no buffers are available from
+userspace. The buffer is not used in this patch but prepares for future
+refactoring where the scratch buffer can be used to avoid the need to
+fallback on single capture mode if userspace can't queue buffers as fast
+as the VIN driver consumes them.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 6a8ffa8b4c519419f7b926904f02c8d1fec5b488)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 19 +++++++++++++++++++
+ drivers/media/platform/rcar-vin/rcar-vin.h |  4 ++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 23fdff7a7370..1f91b056188e 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -1076,6 +1076,17 @@ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 	unsigned long flags;
+ 	int ret;
+ 
++	/* Allocate scratch buffer. */
++	vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
++					  &vin->scratch_phys, GFP_KERNEL);
++	if (!vin->scratch) {
++		spin_lock_irqsave(&vin->qlock, flags);
++		return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
++		spin_unlock_irqrestore(&vin->qlock, flags);
++		vin_err(vin, "Failed to allocate scratch buffer\n");
++		return -ENOMEM;
++	}
++
+ 	sd = vin_to_source(vin);
+ 	v4l2_subdev_call(sd, video, s_stream, 1);
+ 
+@@ -1091,6 +1102,10 @@ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+ 
++	if (ret)
++		dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
++				  vin->scratch_phys);
++
+ 	return ret;
+ }
+ 
+@@ -1141,6 +1156,10 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
+ 
+ 	/* disable interrupts */
+ 	rvin_disable_interrupts(vin);
++
++	/* Free scratch buffer. */
++	dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
++			  vin->scratch_phys);
+ }
+ 
+ static const struct vb2_ops rvin_qops = {
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 5382078143fb..00b405f78d09 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -102,6 +102,8 @@ struct rvin_graph_entity {
+  *
+  * @lock:		protects @queue
+  * @queue:		vb2 buffers queue
++ * @scratch:		cpu address for scratch buffer
++ * @scratch_phys:	physical address of the scratch buffer
+  *
+  * @qlock:		protects @queue_buf, @buf_list, @continuous, @sequence
+  *			@state
+@@ -130,6 +132,8 @@ struct rvin_dev {
+ 
+ 	struct mutex lock;
+ 	struct vb2_queue queue;
++	void *scratch;
++	dma_addr_t scratch_phys;
+ 
+ 	spinlock_t qlock;
+ 	struct vb2_v4l2_buffer *queue_buf[HW_BUFFER_NUM];
+-- 
+2.19.0
+
diff --git a/patches/0822-media-rcar-vin-use-scratch-buffer-and-always-run-in-.patch b/patches/0822-media-rcar-vin-use-scratch-buffer-and-always-run-in-.patch
new file mode 100644
index 00000000000000..303cc7dbe47613
--- /dev/null
+++ b/patches/0822-media-rcar-vin-use-scratch-buffer-and-always-run-in-.patch
@@ -0,0 +1,348 @@
+From dd44cf6d8af9ed79a0efded4ae8f84a63a3ceec4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 13 Mar 2018 22:49:10 -0400
+Subject: [PATCH 0822/1795] media: rcar-vin: use scratch buffer and always run
+ in continuous mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Instead of switching capture mode depending on how many buffers are
+available use a scratch buffer and always run in continuous mode. By
+using a scratch buffer the responsiveness of the capture loop is
+increased as it can keep running even if there are no buffers available
+from userspace.
+
+As soon as a userspace queues a buffer it is inserted into the capture
+loop and returned as soon as it is filled. This is a improvement on the
+previous logic where the whole capture loop was stopped and switched to
+single capture mode if userspace did not feed the VIN driver buffers at
+the same time it consumed them. To make matters worse it was difficult
+for the driver to reenter continuous mode if it entered single mode even
+if userspace started to queue buffers faster. This resulted in
+suboptimal performance where if userspace where delayed for a short
+period the ongoing capture would be slowed down and run in single mode
+until the capturing process where restarted.
+
+An additional effect of this change is that the capture logic can be
+made much simple as we know that continuous mode will always be used.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit dc9aec795f53c0cff46ee03e28309f75637b5f60)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 187 ++++++---------------
+ drivers/media/platform/rcar-vin/rcar-vin.h |   6 +-
+ 2 files changed, 52 insertions(+), 141 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 1f91b056188e..4a40e6ad1be7 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -168,12 +168,8 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	case V4L2_FIELD_ALTERNATE:
+ 	case V4L2_FIELD_NONE:
+-		if (vin->continuous) {
+-			vnmc = VNMC_IM_ODD_EVEN;
+-			progressive = true;
+-		} else {
+-			vnmc = VNMC_IM_ODD;
+-		}
++		vnmc = VNMC_IM_ODD_EVEN;
++		progressive = true;
+ 		break;
+ 	default:
+ 		vnmc = VNMC_IM_ODD;
+@@ -298,14 +294,6 @@ static bool rvin_capture_active(struct rvin_dev *vin)
+ 	return rvin_read(vin, VNMS_REG) & VNMS_CA;
+ }
+ 
+-static int rvin_get_active_slot(struct rvin_dev *vin, u32 vnms)
+-{
+-	if (vin->continuous)
+-		return (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
+-
+-	return 0;
+-}
+-
+ static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
+ {
+ 	if (vin->format.field == V4L2_FIELD_ALTERNATE) {
+@@ -344,76 +332,47 @@ static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
+ 	rvin_write(vin, offset, VNMB_REG(slot));
+ }
+ 
+-/* Moves a buffer from the queue to the HW slots */
+-static bool rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
++/*
++ * Moves a buffer from the queue to the HW slot. If no buffer is
++ * available use the scratch buffer. The scratch buffer is never
++ * returned to userspace, its only function is to enable the capture
++ * loop to keep running.
++ */
++static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
+ {
+ 	struct rvin_buffer *buf;
+ 	struct vb2_v4l2_buffer *vbuf;
+-	dma_addr_t phys_addr_top;
+-
+-	if (vin->queue_buf[slot] != NULL)
+-		return true;
++	dma_addr_t phys_addr;
+ 
+-	if (list_empty(&vin->buf_list))
+-		return false;
++	/* A already populated slot shall never be overwritten. */
++	if (WARN_ON(vin->queue_buf[slot] != NULL))
++		return;
+ 
+ 	vin_dbg(vin, "Filling HW slot: %d\n", slot);
+ 
+-	/* Keep track of buffer we give to HW */
+-	buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
+-	vbuf = &buf->vb;
+-	list_del_init(to_buf_list(vbuf));
+-	vin->queue_buf[slot] = vbuf;
+-
+-	/* Setup DMA */
+-	phys_addr_top = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
+-	rvin_set_slot_addr(vin, slot, phys_addr_top);
+-
+-	return true;
+-}
+-
+-static bool rvin_fill_hw(struct rvin_dev *vin)
+-{
+-	int slot, limit;
+-
+-	limit = vin->continuous ? HW_BUFFER_NUM : 1;
+-
+-	for (slot = 0; slot < limit; slot++)
+-		if (!rvin_fill_hw_slot(vin, slot))
+-			return false;
+-	return true;
+-}
+-
+-static void rvin_capture_on(struct rvin_dev *vin)
+-{
+-	vin_dbg(vin, "Capture on in %s mode\n",
+-		vin->continuous ? "continuous" : "single");
++	if (list_empty(&vin->buf_list)) {
++		vin->queue_buf[slot] = NULL;
++		phys_addr = vin->scratch_phys;
++	} else {
++		/* Keep track of buffer we give to HW */
++		buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
++		vbuf = &buf->vb;
++		list_del_init(to_buf_list(vbuf));
++		vin->queue_buf[slot] = vbuf;
++
++		/* Setup DMA */
++		phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
++	}
+ 
+-	if (vin->continuous)
+-		/* Continuous Frame Capture Mode */
+-		rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
+-	else
+-		/* Single Frame Capture Mode */
+-		rvin_write(vin, VNFC_S_FRAME, VNFC_REG);
++	rvin_set_slot_addr(vin, slot, phys_addr);
+ }
+ 
+ static int rvin_capture_start(struct rvin_dev *vin)
+ {
+-	struct rvin_buffer *buf, *node;
+-	int bufs, ret;
++	int slot, ret;
+ 
+-	/* Count number of free buffers */
+-	bufs = 0;
+-	list_for_each_entry_safe(buf, node, &vin->buf_list, list)
+-		bufs++;
+-
+-	/* Continuous capture requires more buffers then there are HW slots */
+-	vin->continuous = bufs > HW_BUFFER_NUM;
+-
+-	if (!rvin_fill_hw(vin)) {
+-		vin_err(vin, "HW not ready to start, not enough buffers available\n");
+-		return -EINVAL;
+-	}
++	for (slot = 0; slot < HW_BUFFER_NUM; slot++)
++		rvin_fill_hw_slot(vin, slot);
+ 
+ 	rvin_crop_scale_comp(vin);
+ 
+@@ -421,7 +380,10 @@ static int rvin_capture_start(struct rvin_dev *vin)
+ 	if (ret)
+ 		return ret;
+ 
+-	rvin_capture_on(vin);
++	vin_dbg(vin, "Starting to capture\n");
++
++	/* Continuous Frame Capture Mode */
++	rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
+ 
+ 	vin->state = RUNNING;
+ 
+@@ -904,7 +866,7 @@ static irqreturn_t rvin_irq(int irq, void *data)
+ 	struct rvin_dev *vin = data;
+ 	u32 int_status, vnms;
+ 	int slot;
+-	unsigned int i, sequence, handled = 0;
++	unsigned int handled = 0;
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&vin->qlock, flags);
+@@ -930,65 +892,25 @@ static irqreturn_t rvin_irq(int irq, void *data)
+ 
+ 	/* Prepare for capture and update state */
+ 	vnms = rvin_read(vin, VNMS_REG);
+-	slot = rvin_get_active_slot(vin, vnms);
+-	sequence = vin->sequence++;
+-
+-	vin_dbg(vin, "IRQ %02d: %d\tbuf0: %c buf1: %c buf2: %c\tmore: %d\n",
+-		sequence, slot,
+-		slot == 0 ? 'x' : vin->queue_buf[0] != NULL ? '1' : '0',
+-		slot == 1 ? 'x' : vin->queue_buf[1] != NULL ? '1' : '0',
+-		slot == 2 ? 'x' : vin->queue_buf[2] != NULL ? '1' : '0',
+-		!list_empty(&vin->buf_list));
+-
+-	/* HW have written to a slot that is not prepared we are in trouble */
+-	if (WARN_ON((vin->queue_buf[slot] == NULL)))
+-		goto done;
++	slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
+ 
+ 	/* Capture frame */
+-	vin->queue_buf[slot]->field = rvin_get_active_field(vin, vnms);
+-	vin->queue_buf[slot]->sequence = sequence;
+-	vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
+-	vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf, VB2_BUF_STATE_DONE);
+-	vin->queue_buf[slot] = NULL;
+-
+-	/* Prepare for next frame */
+-	if (!rvin_fill_hw(vin)) {
+-
+-		/*
+-		 * Can't supply HW with new buffers fast enough. Halt
+-		 * capture until more buffers are available.
+-		 */
+-		vin->state = STALLED;
+-
+-		/*
+-		 * The continuous capturing requires an explicit stop
+-		 * operation when there is no buffer to be set into
+-		 * the VnMBm registers.
+-		 */
+-		if (vin->continuous) {
+-			rvin_capture_stop(vin);
+-			vin_dbg(vin, "IRQ %02d: hw not ready stop\n", sequence);
+-
+-			/* Maybe we can continue in single capture mode */
+-			for (i = 0; i < HW_BUFFER_NUM; i++) {
+-				if (vin->queue_buf[i]) {
+-					list_add(to_buf_list(vin->queue_buf[i]),
+-						 &vin->buf_list);
+-					vin->queue_buf[i] = NULL;
+-				}
+-			}
+-
+-			if (!list_empty(&vin->buf_list))
+-				rvin_capture_start(vin);
+-		}
++	if (vin->queue_buf[slot]) {
++		vin->queue_buf[slot]->field = rvin_get_active_field(vin, vnms);
++		vin->queue_buf[slot]->sequence = vin->sequence;
++		vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
++		vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf,
++				VB2_BUF_STATE_DONE);
++		vin->queue_buf[slot] = NULL;
+ 	} else {
+-		/*
+-		 * The single capturing requires an explicit capture
+-		 * operation to fetch the next frame.
+-		 */
+-		if (!vin->continuous)
+-			rvin_capture_on(vin);
++		/* Scratch buffer was used, dropping frame. */
++		vin_dbg(vin, "Dropping frame %u\n", vin->sequence);
+ 	}
++
++	vin->sequence++;
++
++	/* Prepare for next frame */
++	rvin_fill_hw_slot(vin, slot);
+ done:
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+ 
+@@ -1059,13 +981,6 @@ static void rvin_buffer_queue(struct vb2_buffer *vb)
+ 
+ 	list_add_tail(to_buf_list(vbuf), &vin->buf_list);
+ 
+-	/*
+-	 * If capture is stalled add buffer to HW and restart
+-	 * capturing if HW is ready to continue.
+-	 */
+-	if (vin->state == STALLED)
+-		rvin_capture_start(vin);
+-
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+ }
+ 
+@@ -1208,7 +1123,7 @@ int rvin_dma_probe(struct rvin_dev *vin, int irq)
+ 	q->ops = &rvin_qops;
+ 	q->mem_ops = &vb2_dma_contig_memops;
+ 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+-	q->min_buffers_needed = 1;
++	q->min_buffers_needed = 4;
+ 	q->dev = vin->dev;
+ 
+ 	ret = vb2_queue_init(q);
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 00b405f78d09..95897127cc41 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -38,13 +38,11 @@ enum chip_id {
+ /**
+  * STOPPED  - No operation in progress
+  * RUNNING  - Operation in progress have buffers
+- * STALLED  - No operation in progress have no buffers
+  * STOPPING - Stopping operation
+  */
+ enum rvin_dma_state {
+ 	STOPPED = 0,
+ 	RUNNING,
+-	STALLED,
+ 	STOPPING,
+ };
+ 
+@@ -105,11 +103,10 @@ struct rvin_graph_entity {
+  * @scratch:		cpu address for scratch buffer
+  * @scratch_phys:	physical address of the scratch buffer
+  *
+- * @qlock:		protects @queue_buf, @buf_list, @continuous, @sequence
++ * @qlock:		protects @queue_buf, @buf_list, @sequence
+  *			@state
+  * @queue_buf:		Keeps track of buffers given to HW slot
+  * @buf_list:		list of queued buffers
+- * @continuous:		tracks if active operation is continuous or single mode
+  * @sequence:		V4L2 buffers sequence number
+  * @state:		keeps track of operation state
+  *
+@@ -138,7 +135,6 @@ struct rvin_dev {
+ 	spinlock_t qlock;
+ 	struct vb2_v4l2_buffer *queue_buf[HW_BUFFER_NUM];
+ 	struct list_head buf_list;
+-	bool continuous;
+ 	unsigned int sequence;
+ 	enum rvin_dma_state state;
+ 
+-- 
+2.19.0
+
diff --git a/patches/0823-mmc-renesas_sdhi-use-MMC_CAP2_NO_WRITE_PROTECT-inste.patch b/patches/0823-mmc-renesas_sdhi-use-MMC_CAP2_NO_WRITE_PROTECT-inste.patch
new file mode 100644
index 00000000000000..8f58d66500b60d
--- /dev/null
+++ b/patches/0823-mmc-renesas_sdhi-use-MMC_CAP2_NO_WRITE_PROTECT-inste.patch
@@ -0,0 +1,108 @@
+From dda240a000fa109c67d82d313ca37f548e54d2db Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:07 +0900
+Subject: [PATCH 0823/1795] mmc: renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT
+ instead of TMIO own flag
+
+TMIO_MMC_WRPROTECT_DISABLE is equivalent to MMC_CAP2_NO_WRITE_PROTECT.
+
+The flag is propagated as follows:
+       renesas_sdhi_of_data::capabilities2
+    -> tmio_mmc_data::capabilities2
+    -> mmc_host::caps2
+
+Only the difference is the TMIO_... makes tmio_mmc_get_ro() return 0
+(i.e. it does not affect mmc_gpio_get_ro() at all), while MMC_CAP2_...
+returns 0 before calling ->get_ro() hook (i.e. it affects both IP own
+logic and GPIO detection).
+
+The TMIO MMC drivers do not set-up gpio_ro by themselves.  Only the
+possibility, if any, would be DT specifies "wp-gpios" property, and
+gpio_ro is set by mmc_gpiod_request_ro() called from mmc_of_parse().
+However, it does not make sense to specify "wp-gpios" property and
+TMIO_MMC_WRPROTECT_DISABLE at the same time.
+
+I checked under arch/arm/boot/dts/ and arch/arm64/boot/dts/renesas/,
+and I did not see any Renesas boards with "wp-gpios".  So, this
+conversion should be safe.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit 2ad1db059b9a4874b05bac49dba22c8b8e68afd4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c |  6 +++---
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 16 ++++++++--------
+ 2 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index d679f1a28f29..1d4d2dcc4f32 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -71,11 +71,11 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+ };
+ 
+ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+-			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY |
+-			  TMIO_MMC_MIN_RCAR2,
++	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
++			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index 82d757c480b2..434afa9dd9a1 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -40,9 +40,9 @@ static const struct renesas_sdhi_of_data of_rz_compatible = {
+ };
+ 
+ static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
+-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+-			  TMIO_MMC_CLK_ACTUAL,
++	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ };
+ 
+ /* Definitions for sampling clocks */
+@@ -58,11 +58,11 @@ static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
+ };
+ 
+ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
+-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+-			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY |
+-			  TMIO_MMC_MIN_RCAR2,
++	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
++			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.dma_buswidth	= DMA_SLAVE_BUSWIDTH_4_BYTES,
+ 	.dma_rx_offset	= 0x2000,
+ 	.scc_offset	= 0x0300,
+@@ -79,11 +79,11 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+ };
+ 
+ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+-			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY |
+-			  TMIO_MMC_MIN_RCAR2,
++	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
++			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+-- 
+2.19.0
+
diff --git a/patches/0824-mmc-tmio-use-MMC_CAP2_NO_WRITE_PROTECT-instead-of-TM.patch b/patches/0824-mmc-tmio-use-MMC_CAP2_NO_WRITE_PROTECT-instead-of-TM.patch
new file mode 100644
index 00000000000000..e478047e639a97
--- /dev/null
+++ b/patches/0824-mmc-tmio-use-MMC_CAP2_NO_WRITE_PROTECT-instead-of-TM.patch
@@ -0,0 +1,68 @@
+From 5c85b41835d1baa4f0b9daab7d5d18d35cfa66b3 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:09 +0900
+Subject: [PATCH 0824/1795] mmc: tmio: use MMC_CAP2_NO_WRITE_PROTECT instead of
+ TMIO own flag
+
+TMIO_MMC_WRPROTECT_DISABLE is equivalent to MMC_CAP2_NO_WRITE_PROTECT.
+
+Only the difference is the TMIO_... makes tmio_mmc_get_ro() return 0
+(i.e. it does not affect mmc_gpio_get_ro() at all), while MMC_CAP2_...
+returns 0 before calling ->get_ro() hook (i.e. it affects both IP own
+logic and GPIO detection).
+
+The TMIO MMC drivers do not set-up gpio_ro by themselves.  Only the
+possibility, if any, would be DT specifies "wp-gpios" property, and
+gpio_ro is set by mmc_gpiod_request_ro() called from mmc_of_parse().
+However, it does not make sense to specify "wp-gpios" property and
+"toshiba,mmc-wrprotect-disable" at the same time.
+
+I checked under arch/arm/boot/dts/ and arch/arm64/boot/dts/renesas/,
+and I did not see any Renesas boards with "wp-gpios".  So, this
+conversion should be safe.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit 7c53b79766a463a97dd013715a1cc8a2802f6448)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 8fce18253465..95c9134f7c33 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1114,7 +1114,7 @@ static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
+ }
+ 
+ static void tmio_mmc_of_parse(struct platform_device *pdev,
+-			      struct tmio_mmc_data *pdata)
++			      struct mmc_host *mmc)
+ {
+ 	const struct device_node *np = pdev->dev.of_node;
+ 
+@@ -1122,7 +1122,7 @@ static void tmio_mmc_of_parse(struct platform_device *pdev,
+ 		return;
+ 
+ 	if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
+-		pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
++		mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
+ }
+ 
+ struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
+@@ -1157,7 +1157,7 @@ struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
+ 		goto free;
+ 	}
+ 
+-	tmio_mmc_of_parse(pdev, pdata);
++	tmio_mmc_of_parse(pdev, mmc);
+ 
+ 	platform_set_drvdata(pdev, host);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0825-mmc-tmio-remove-TMIO_MMC_WRPROTECT_DISABLE.patch b/patches/0825-mmc-tmio-remove-TMIO_MMC_WRPROTECT_DISABLE.patch
new file mode 100644
index 00000000000000..ea1f31bafc9642
--- /dev/null
+++ b/patches/0825-mmc-tmio-remove-TMIO_MMC_WRPROTECT_DISABLE.patch
@@ -0,0 +1,53 @@
+From e7f9819570e98b0c950209567a9e297f62dcbe8f Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:10 +0900
+Subject: [PATCH 0825/1795] mmc: tmio: remove TMIO_MMC_WRPROTECT_DISABLE
+
+The use of this flag has been replaced with MMC_CAP2_NO_WRITE_PROTECT.
+No platform defines this flag any more.  Remove.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit 218f6024abec04ec78e56b6761f70d404bab8637)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 5 ++---
+ include/linux/mfd/tmio.h         | 1 -
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 95c9134f7c33..4aec461f9f28 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1061,10 +1061,9 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ static int tmio_mmc_get_ro(struct mmc_host *mmc)
+ {
+ 	struct tmio_mmc_host *host = mmc_priv(mmc);
+-	struct tmio_mmc_data *pdata = host->pdata;
+ 
+-	return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
+-		 (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
++	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
++		 TMIO_STAT_WRPROTECT);
+ }
+ 
+ static int tmio_multi_io_quirk(struct mmc_card *card,
+diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
+index 396a103c8bc6..91f92215ca74 100644
+--- a/include/linux/mfd/tmio.h
++++ b/include/linux/mfd/tmio.h
+@@ -36,7 +36,6 @@
+ 	} while (0)
+ 
+ /* tmio MMC platform flags */
+-#define TMIO_MMC_WRPROTECT_DISABLE	BIT(0)
+ /*
+  * Some controllers can support a 2-byte block size when the bus width
+  * is configured in 4-bit mode.
+-- 
+2.19.0
+
diff --git a/patches/0826-mmc-tmio-deprecate-toshiba-mmc-wrprotect-disable-DT-.patch b/patches/0826-mmc-tmio-deprecate-toshiba-mmc-wrprotect-disable-DT-.patch
new file mode 100644
index 00000000000000..9ee40ef8f0834d
--- /dev/null
+++ b/patches/0826-mmc-tmio-deprecate-toshiba-mmc-wrprotect-disable-DT-.patch
@@ -0,0 +1,64 @@
+From 53578d7dc0ddd72421c7bb5711e1147a154dc705 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:11 +0900
+Subject: [PATCH 0826/1795] mmc: tmio: deprecate "toshiba,
+ mmc-wrprotect-disable" DT property
+
+This property is equivalent to "disable-wp" defined in
+Documentation/devicetree/bindings/mmc/mmc.txt
+
+The TMIO MMC core calls mmc_of_parse(), and it sets
+MMC_CAP2_NO_WRITE_PROTECT if "disable-wp" property is present.
+
+We do not need a vendor-specific property to do the same thing.
+
+Let's remove the description from the dt-binding to prevent new boards
+from using it.
+
+I am keeping the driver code for existing DT files, but added
+comments that this is deprecated.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit 788778b0d21a6d5cd5bc6c880591119e17932327)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 -
+ drivers/mmc/host/tmio_mmc_core.c                   | 5 +++++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index d8685cb83325..2d5287eeed95 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -50,7 +50,6 @@ Required properties:
+ 	  2: R7S72100
+ 
+ Optional properties:
+-- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
+ - pinctrl-names: should be "default", "state_uhs"
+ - pinctrl-0: should contain default/high speed pin ctrl
+ - pinctrl-1: should contain uhs mode pin ctrl
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 4aec461f9f28..15a6baf302dc 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1120,6 +1120,11 @@ static void tmio_mmc_of_parse(struct platform_device *pdev,
+ 	if (!np)
+ 		return;
+ 
++	/*
++	 * DEPRECATED:
++	 * For new platforms, please use "disable-wp" instead of
++	 * "toshiba,mmc-wrprotect-disable"
++	 */
+ 	if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
+ 		mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0827-mmc-tmio-support-IP-builtin-card-detection-logic.patch b/patches/0827-mmc-tmio-support-IP-builtin-card-detection-logic.patch
new file mode 100644
index 00000000000000..a8c761046dafcd
--- /dev/null
+++ b/patches/0827-mmc-tmio-support-IP-builtin-card-detection-logic.patch
@@ -0,0 +1,65 @@
+From 602dc2043111e5f0866c662e3462f996691d3aef Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:12 +0900
+Subject: [PATCH 0827/1795] mmc: tmio: support IP-builtin card detection logic
+
+A card detect GPIO is set up only for platforms with "cd-gpios"
+DT property or TMIO_MMC_USE_GPIO_CD flag.  However, the driver
+core always uses mmc_gpio_get_cd, which just fails with -ENOSYS
+if ctx->cd_gpio is unset.
+
+The bit 5 of the status register provides the current signal level
+of the CD line.  Allow to use it if the GPIO is unused.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit 497d1f965c207f1d670066e9c87a2ffad1ce4e5e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 15a6baf302dc..1bcd63a0669e 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1066,6 +1066,14 @@ static int tmio_mmc_get_ro(struct mmc_host *mmc)
+ 		 TMIO_STAT_WRPROTECT);
+ }
+ 
++static int tmio_mmc_get_cd(struct mmc_host *mmc)
++{
++	struct tmio_mmc_host *host = mmc_priv(mmc);
++
++	return !!(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
++		  TMIO_STAT_SIGSTATE);
++}
++
+ static int tmio_multi_io_quirk(struct mmc_card *card,
+ 			       unsigned int direction, int blk_size)
+ {
+@@ -1081,7 +1089,7 @@ static const struct mmc_host_ops tmio_mmc_ops = {
+ 	.request	= tmio_mmc_request,
+ 	.set_ios	= tmio_mmc_set_ios,
+ 	.get_ro         = tmio_mmc_get_ro,
+-	.get_cd		= mmc_gpio_get_cd,
++	.get_cd		= tmio_mmc_get_cd,
+ 	.enable_sdio_irq = tmio_mmc_enable_sdio_irq,
+ 	.multi_io_quirk	= tmio_multi_io_quirk,
+ 	.hw_reset	= tmio_mmc_hw_reset,
+@@ -1234,6 +1242,9 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 	if (mmc_can_gpio_ro(mmc))
+ 		_host->ops.get_ro = mmc_gpio_get_ro;
+ 
++	if (mmc_can_gpio_cd(mmc))
++		_host->ops.get_cd = mmc_gpio_get_cd;
++
+ 	_host->native_hotplug = !(mmc_can_gpio_cd(mmc) ||
+ 				  mmc->caps & MMC_CAP_NEEDS_POLL ||
+ 				  !mmc_card_is_removable(mmc));
+-- 
+2.19.0
+
diff --git a/patches/0828-mmc-tmio-fix-never-detected-card-insertion-bug.patch b/patches/0828-mmc-tmio-fix-never-detected-card-insertion-bug.patch
new file mode 100644
index 00000000000000..718e484a3bec6b
--- /dev/null
+++ b/patches/0828-mmc-tmio-fix-never-detected-card-insertion-bug.patch
@@ -0,0 +1,79 @@
+From bd17c40fa3c9135638f0ee320ad1a98da1a640d4 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:13 +0900
+Subject: [PATCH 0828/1795] mmc: tmio: fix never-detected card insertion bug
+
+The TMIO mmc cannot detect the card insertion in native_hotplug mode
+if the driver is probed without a card inserted.
+
+The reason is obvious; all IRQs are disabled by tmio_mmc_host_probe(),
+as follows:
+
+  tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
+
+The card event IRQs are first enabled by tmio_mmc_start_command() as
+follows:
+
+  if (!host->native_hotplug)
+          irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
+  tmio_mmc_enable_mmc_irqs(host, irq_mask);
+
+If the driver is probed without a card, tmio_mmc_start_command() is
+never called in the first place.  So, the card is never detected.
+
+The card event IRQs must be enabled in probe/resume functions.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit c7cd630a9751b9ec8bba37edbba06a29e7d9a14b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 1bcd63a0669e..63767fd1da24 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -350,8 +350,6 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host,
+ 			c |= TRANSFER_READ;
+ 	}
+ 
+-	if (!host->native_hotplug)
+-		irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
+ 	tmio_mmc_enable_mmc_irqs(host, irq_mask);
+ 
+ 	/* Fire off the command */
+@@ -1280,11 +1278,13 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 		irq_mask |= TMIO_MASK_READOP;
+ 	if (!_host->chan_tx)
+ 		irq_mask |= TMIO_MASK_WRITEOP;
+-	if (!_host->native_hotplug)
+-		irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
+ 
+ 	_host->sdcard_irq_mask &= ~irq_mask;
+ 
++	if (_host->native_hotplug)
++		tmio_mmc_enable_mmc_irqs(_host,
++				TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
++
+ 	spin_lock_init(&_host->lock);
+ 	mutex_init(&_host->ios_lock);
+ 
+@@ -1382,6 +1382,10 @@ int tmio_mmc_host_runtime_resume(struct device *dev)
+ 	if (host->clk_cache)
+ 		tmio_mmc_set_clock(host, host->clk_cache);
+ 
++	if (host->native_hotplug)
++		tmio_mmc_enable_mmc_irqs(host,
++				TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
++
+ 	tmio_mmc_enable_dma(host, true);
+ 
+ 	if (tmio_mmc_can_retune(host) && host->select_tuning(host))
+-- 
+2.19.0
+
diff --git a/patches/0829-mmc-tmio-move-TMIO_MASK_-READOP-WRITEOP-handling-to-.patch b/patches/0829-mmc-tmio-move-TMIO_MASK_-READOP-WRITEOP-handling-to-.patch
new file mode 100644
index 00000000000000..bc16574abbddef
--- /dev/null
+++ b/patches/0829-mmc-tmio-move-TMIO_MASK_-READOP-WRITEOP-handling-to-.patch
@@ -0,0 +1,147 @@
+From a4cd588eee924157183daa6174d04d4433260cf4 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:14 +0900
+Subject: [PATCH 0829/1795] mmc: tmio: move TMIO_MASK_{READOP, WRITEOP}
+ handling to correct place
+
+As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ}
+are asserted for DMA mode as well as for PIO.  I need to disable the
+those IRQs in dma_ops->start hook, otherwise the DMA transfer fails
+with the following error message:
+  PIO IRQ in DMA mode!
+
+Renesas chips are the same cases since I see their dma_ops->start
+hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!).
+
+If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling
+should be entirely moved to the core.  tmio_mmc_cmd_irq() will
+be a suitable place to disable them.
+
+The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd.
+
+    /* Unmask the IRQs we want to know about */
+    if (!_host->chan_rx)
+            irq_mask |= TMIO_MASK_READOP;
+    if (!_host->chan_tx)
+            irq_mask |= TMIO_MASK_WRITEOP;
+
+At this point, _host->{chan_rx,chan_tx} are _always_ NULL because
+tmio_mmc_request_dma() is called after this code.  Consequently,
+TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not.
+Remove this pointless code.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+(cherry picked from commit b12a7a28f860c3ab078ae306e13a659ec70b3c33)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c |  6 ------
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      |  4 ----
+ drivers/mmc/host/tmio_mmc_core.c              | 20 +++++++++----------
+ 3 files changed, 10 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 1d4d2dcc4f32..9f66baaded94 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -145,7 +145,6 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+ 	enum dma_data_direction dir;
+ 	int ret;
+-	u32 irq_mask;
+ 
+ 	/* This DMAC cannot handle if sg_len is not 1 */
+ 	WARN_ON(host->sg_len > 1);
+@@ -157,11 +156,9 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 	if (data->flags & MMC_DATA_READ) {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+ 		dir = DMA_FROM_DEVICE;
+-		irq_mask = TMIO_STAT_RXRDY;
+ 	} else {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+ 		dir = DMA_TO_DEVICE;
+-		irq_mask = TMIO_STAT_TXRQ;
+ 	}
+ 
+ 	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
+@@ -170,9 +167,6 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 
+ 	renesas_sdhi_internal_dmac_enable_dma(host, true);
+ 
+-	/* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
+-	tmio_mmc_disable_mmc_irqs(host, irq_mask);
+-
+ 	/* set dma parameters */
+ 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
+ 					    dtran_mode);
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index 434afa9dd9a1..4bb46c489d71 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -205,8 +205,6 @@ static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
+ 		return;
+ 	}
+ 
+-	tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_RXRDY);
+-
+ 	/* The only sg element can be unaligned, use our bounce buffer then */
+ 	if (!aligned) {
+ 		sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
+@@ -280,8 +278,6 @@ static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
+ 		return;
+ 	}
+ 
+-	tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_TXRQ);
+-
+ 	/* The only sg element can be unaligned, use our bounce buffer then */
+ 	if (!aligned) {
+ 		unsigned long flags;
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 63767fd1da24..477fafa3094f 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -621,15 +621,21 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, unsigned int stat)
+ 	 */
+ 	if (host->data && (!cmd->error || cmd->error == -EILSEQ)) {
+ 		if (host->data->flags & MMC_DATA_READ) {
+-			if (host->force_pio || !host->chan_rx)
++			if (host->force_pio || !host->chan_rx) {
+ 				tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
+-			else
++			} else {
++				tmio_mmc_disable_mmc_irqs(host,
++							  TMIO_MASK_READOP);
+ 				tasklet_schedule(&host->dma_issue);
++			}
+ 		} else {
+-			if (host->force_pio || !host->chan_tx)
++			if (host->force_pio || !host->chan_tx) {
+ 				tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
+-			else
++			} else {
++				tmio_mmc_disable_mmc_irqs(host,
++							  TMIO_MASK_WRITEOP);
+ 				tasklet_schedule(&host->dma_issue);
++			}
+ 		}
+ 	} else {
+ 		schedule_work(&host->done);
+@@ -1273,12 +1279,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 	_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
+ 	tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
+ 
+-	/* Unmask the IRQs we want to know about */
+-	if (!_host->chan_rx)
+-		irq_mask |= TMIO_MASK_READOP;
+-	if (!_host->chan_tx)
+-		irq_mask |= TMIO_MASK_WRITEOP;
+-
+ 	_host->sdcard_irq_mask &= ~irq_mask;
+ 
+ 	if (_host->native_hotplug)
+-- 
+2.19.0
+
diff --git a/patches/0830-mmc-tmio-clear-force_pio-flag-before-starting-data-t.patch b/patches/0830-mmc-tmio-clear-force_pio-flag-before-starting-data-t.patch
new file mode 100644
index 00000000000000..ef37cc4ff11c13
--- /dev/null
+++ b/patches/0830-mmc-tmio-clear-force_pio-flag-before-starting-data-t.patch
@@ -0,0 +1,71 @@
+From 434c32ba0f265203705c3754f2b558a1bbb3cf49 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:15 +0900
+Subject: [PATCH 0830/1795] mmc: tmio: clear force_pio flag before starting
+ data transfer
+
+Currently, force_pio is cleared when the driver exits.  Then, it
+resulted in clearing it in multiple places since MMC drivers in
+general have multiple exit points.
+
+ tmio_mmc_reset_work - bails out on timeout
+ tmio_process_mrq - error out when it cannot send a command
+ tmio_mmc_finish_request - successful exit
+
+This is error-prone since we may miss to cover all bail-out points.
+
+To simplify the code, the data structure should be initialized just
+before used since we have a single entrance.  force_pio is only used
+for data transfer, so tmio_mmc_start_data() will be a suitable place
+to clear this flag.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 9b3ab55dbabd8bc8ac226a603f02ad39e6202521)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index 477fafa3094f..cbaea0fcba73 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -278,7 +278,6 @@ static void tmio_mmc_reset_work(struct work_struct *work)
+ 
+ 	host->cmd = NULL;
+ 	host->data = NULL;
+-	host->force_pio = false;
+ 
+ 	spin_unlock_irqrestore(&host->lock, flags);
+ 
+@@ -759,6 +758,7 @@ static int tmio_mmc_start_data(struct tmio_mmc_host *host,
+ 
+ 	tmio_mmc_init_sg(host, data);
+ 	host->data = data;
++	host->force_pio = false;
+ 
+ 	/* Set transfer length / blocksize */
+ 	sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
+@@ -850,7 +850,6 @@ static void tmio_process_mrq(struct tmio_mmc_host *host,
+ 	return;
+ 
+ fail:
+-	host->force_pio = false;
+ 	host->mrq = NULL;
+ 	mrq->cmd->error = ret;
+ 	mmc_request_done(host->mmc, mrq);
+@@ -900,7 +899,6 @@ static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
+ 	if (host->cmd != mrq->sbc) {
+ 		host->cmd = NULL;
+ 		host->data = NULL;
+-		host->force_pio = false;
+ 		host->mrq = NULL;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0831-mmc-tmio-remove-useless-TMIO_MASK_CMD-handling-in-tm.patch b/patches/0831-mmc-tmio-remove-useless-TMIO_MASK_CMD-handling-in-tm.patch
new file mode 100644
index 00000000000000..05d5a9d15cd32a
--- /dev/null
+++ b/patches/0831-mmc-tmio-remove-useless-TMIO_MASK_CMD-handling-in-tm.patch
@@ -0,0 +1,54 @@
+From 8a5c713863f9462614ae461c4484d6e8b2bc21b4 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 18 Jan 2018 01:28:16 +0900
+Subject: [PATCH 0831/1795] mmc: tmio: remove useless TMIO_MASK_CMD handling in
+ tmio_mmc_host_probe()
+
+TMIO_MASK_CMD is properly enabled in tmio_mmc_start_command().
+
+We have no reason to set it up in tmio_mmc_host_probe().  (If we
+really wanted to set it in the probe, we would have to do likewise
+when resuming.)
+
+Even worse, the following code is extremely confusing:
+
+  _host->sdcard_irq_mask &= ~irq_mask;
+
+The logic is opposite between "->sdcard_irq_mask" and "irq_mask".
+The intention is not clear at a glance.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit c9b929edf4e1f96c550584fe8445755b6d600e71)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/tmio_mmc_core.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
+index cbaea0fcba73..308029930304 100644
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -1195,7 +1195,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 	struct tmio_mmc_data *pdata = _host->pdata;
+ 	struct mmc_host *mmc = _host->mmc;
+ 	int ret;
+-	u32 irq_mask = TMIO_MASK_CMD;
+ 
+ 	/*
+ 	 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
+@@ -1277,8 +1276,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
+ 	_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
+ 	tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
+ 
+-	_host->sdcard_irq_mask &= ~irq_mask;
+-
+ 	if (_host->native_hotplug)
+ 		tmio_mmc_enable_mmc_irqs(_host,
+ 				TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
+-- 
+2.19.0
+
diff --git a/patches/0832-mmc-renesas_sdhi-fix-WP-detection.patch b/patches/0832-mmc-renesas_sdhi-fix-WP-detection.patch
new file mode 100644
index 00000000000000..3adf196ac00f7d
--- /dev/null
+++ b/patches/0832-mmc-renesas_sdhi-fix-WP-detection.patch
@@ -0,0 +1,65 @@
+From fe6cfca99ad266c6b5872db91f350caf492cac11 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 5 Mar 2018 21:48:42 +0100
+Subject: [PATCH 0832/1795] mmc: renesas_sdhi: fix WP detection
+
+Commit "mmc: renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT instead of
+TMIO own flag" activated MMC_CAP2_NO_WRITE_PROTECT for Renesas SDHI
+which incorrectly disabled WP altogether instead of only disabling the
+internal mechanism. Since the whole WP handling has been reworked, we
+can simply disable this capability to re-enable WP GPIOs.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit e060d376cc6185dde7e852c028de36614e2201fa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 -
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 3 ---
+ 2 files changed, 4 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 9f66baaded94..028548ad2f42 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -75,7 +75,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
+-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index 4bb46c489d71..848e50c1638a 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -42,7 +42,6 @@ static const struct renesas_sdhi_of_data of_rz_compatible = {
+ static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
+ 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
+-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ };
+ 
+ /* Definitions for sampling clocks */
+@@ -62,7 +61,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
+-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.dma_buswidth	= DMA_SLAVE_BUSWIDTH_4_BYTES,
+ 	.dma_rx_offset	= 0x2000,
+ 	.scc_offset	= 0x0300,
+@@ -83,7 +81,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
+-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+-- 
+2.19.0
+
diff --git a/patches/0833-mmc-renesas_sdhi-replace-EXT_ACC-with-HOST_MODE.patch b/patches/0833-mmc-renesas_sdhi-replace-EXT_ACC-with-HOST_MODE.patch
new file mode 100644
index 00000000000000..17a0d21014b158
--- /dev/null
+++ b/patches/0833-mmc-renesas_sdhi-replace-EXT_ACC-with-HOST_MODE.patch
@@ -0,0 +1,52 @@
+From b7aa56f0102a0ed4cf25e95e8d3eeabb40ffa4b4 Mon Sep 17 00:00:00 2001
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Date: Tue, 20 Mar 2018 22:42:58 +0100
+Subject: [PATCH 0833/1795] mmc: renesas_sdhi: replace EXT_ACC with HOST_MODE
+
+All our documentation says HOST_MODE, we don't really know where EXT_ACC
+came from. Rename it to reduce the confusion.
+
+Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 4472f0fc248e3f0573301f725eff9dc9cde5cb62)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 80943fa07db6..51e01f03fb99 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -38,7 +38,7 @@
+ #include "renesas_sdhi.h"
+ #include "tmio_mmc.h"
+ 
+-#define EXT_ACC           0xe4
++#define HOST_MODE		0xe4
+ 
+ #define SDHI_VER_GEN2_SDR50	0x490c
+ #define SDHI_VER_RZ_A1		0x820b
+@@ -76,7 +76,7 @@ static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
+ 		return;
+ 	}
+ 
+-	sd_ctrl_write16(host, EXT_ACC, val);
++	sd_ctrl_write16(host, HOST_MODE, val);
+ }
+ 
+ static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
+@@ -417,7 +417,7 @@ static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
+ 	case CTL_SD_MEM_CARD_OPT:
+ 	case CTL_TRANSACTION_CTL:
+ 	case CTL_DMA_ENABLE:
+-	case EXT_ACC:
++	case HOST_MODE:
+ 		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
+ 			bit = TMIO_STAT_CMD_BUSY;
+ 		/* fallthrough */
+-- 
+2.19.0
+
diff --git a/patches/0834-mmc-renesas_sdhi_internal_dmac-limit-DMA-RX-for-old-.patch b/patches/0834-mmc-renesas_sdhi_internal_dmac-limit-DMA-RX-for-old-.patch
new file mode 100644
index 00000000000000..8caa20de8d6ee9
--- /dev/null
+++ b/patches/0834-mmc-renesas_sdhi_internal_dmac-limit-DMA-RX-for-old-.patch
@@ -0,0 +1,117 @@
+From 5d0165a23f584680a6204d675269bf4abad66c13 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 18 Apr 2018 20:20:57 +0200
+Subject: [PATCH 0834/1795] mmc: renesas_sdhi_internal_dmac: limit DMA RX for
+ old SoCs
+
+Early revisions of certain SoCs cannot do multiple DMA RX streams in
+parallel. To avoid data corruption, only allow one DMA RX channel and
+fall back to PIO, if needed.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: stable@vger.kernel.org
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 0cbc94daa55441c21999e96a07061952d873dcb7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 39 ++++++++++++++++---
+ 1 file changed, 33 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 028548ad2f42..07a642cd33af 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -9,6 +9,7 @@
+  * published by the Free Software Foundation.
+  */
+ 
++#include <linux/bitops.h>
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io-64-nonatomic-hi-lo.h>
+@@ -62,6 +63,17 @@
+  *   need a custom accessor.
+  */
+ 
++static unsigned long global_flags;
++/*
++ * Workaround for avoiding to use RX DMAC by multiple channels.
++ * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
++ * RX DMAC simultaneously, sometimes hundreds of bytes data are not
++ * stored into the system memory even if the DMAC interrupt happened.
++ * So, this driver then uses one RX DMAC channel only.
++ */
++#define SDHI_INTERNAL_DMAC_ONE_RX_ONLY	0
++#define SDHI_INTERNAL_DMAC_RX_IN_USE	1
++
+ /* Definitions for sampling clocks */
+ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+ 	{
+@@ -126,6 +138,9 @@ renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+ 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+ 					    RST_RESERVED_BITS | val);
+ 
++	if (host->data && host->data->flags & MMC_DATA_READ)
++		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
++
+ 	renesas_sdhi_internal_dmac_enable_dma(host, true);
+ }
+ 
+@@ -155,6 +170,9 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 	if (data->flags & MMC_DATA_READ) {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+ 		dir = DMA_FROM_DEVICE;
++		if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
++		    test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
++			goto force_pio;
+ 	} else {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+ 		dir = DMA_TO_DEVICE;
+@@ -208,6 +226,9 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
+ 	renesas_sdhi_internal_dmac_enable_dma(host, false);
+ 	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
+ 
++	if (dir == DMA_FROM_DEVICE)
++		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
++
+ 	tmio_mmc_do_data_irq(host);
+ out:
+ 	spin_unlock_irq(&host->lock);
+@@ -251,18 +272,24 @@ static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
+  * implementation as others may use a different implementation.
+  */
+ static const struct soc_device_attribute gen3_soc_whitelist[] = {
+-        { .soc_id = "r8a7795", .revision = "ES1.*" },
+-        { .soc_id = "r8a7795", .revision = "ES2.0" },
+-        { .soc_id = "r8a7796", .revision = "ES1.0" },
+-        { .soc_id = "r8a77995", .revision = "ES1.0" },
+-        { /* sentinel */ }
++	{ .soc_id = "r8a7795", .revision = "ES1.*",
++	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
++	{ .soc_id = "r8a7795", .revision = "ES2.0" },
++	{ .soc_id = "r8a7796", .revision = "ES1.0",
++	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
++	{ .soc_id = "r8a77995", .revision = "ES1.0" },
++	{ /* sentinel */ }
+ };
+ 
+ static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
+ {
+-	if (!soc_device_match(gen3_soc_whitelist))
++	const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
++
++	if (!soc)
+ 		return -ENODEV;
+ 
++	global_flags |= (unsigned long)soc->data;
++
+ 	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0835-soc-renesas-identify-R-Car-V3H.patch b/patches/0835-soc-renesas-identify-R-Car-V3H.patch
new file mode 100644
index 00000000000000..2174099de8002b
--- /dev/null
+++ b/patches/0835-soc-renesas-identify-R-Car-V3H.patch
@@ -0,0 +1,46 @@
+From 5813dbe30be21a9068bbce1ba1ea2cbca83d5942 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:22:14 +0300
+Subject: [PATCH 0835/1795] soc: renesas: identify R-Car V3H
+
+Add support for identifying the R-Car V3H (R8A77980) SoC.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8447756d1e582a401cdae33c9ed5d68fdb6e0410)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 926b7fd6db2d..000834321774 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -149,6 +149,11 @@ static const struct renesas_soc soc_rcar_v3m __initconst __maybe_unused = {
+ 	.id	= 0x54,
+ };
+ 
++static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
++	.family	= &fam_rcar_gen3,
++	.id	= 0x56,
++};
++
+ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
+ 	.family	= &fam_rcar_gen3,
+ 	.id	= 0x58,
+@@ -212,6 +217,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
+ #ifdef CONFIG_ARCH_R8A77970
+ 	{ .compatible = "renesas,r8a77970",	.data = &soc_rcar_v3m },
+ #endif
++#ifdef CONFIG_ARCH_R8A77980
++	{ .compatible = "renesas,r8a77980",	.data = &soc_rcar_v3h },
++#endif
+ #ifdef CONFIG_ARCH_R8A77995
+ 	{ .compatible = "renesas,r8a77995",	.data = &soc_rcar_d3 },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0836-soc-renesas-Identify-R-Car-M3-N.patch b/patches/0836-soc-renesas-Identify-R-Car-M3-N.patch
new file mode 100644
index 00000000000000..37293e9511a850
--- /dev/null
+++ b/patches/0836-soc-renesas-Identify-R-Car-M3-N.patch
@@ -0,0 +1,46 @@
+From 79ae181d4417e6ced63d8ea8bae5c47f9591184f Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:05 +0100
+Subject: [PATCH 0836/1795] soc: renesas: Identify R-Car M3-N
+
+Add support for indentifying R-Car M3-N (R8A77965) SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bfd8398339ccd824a3c5dfaee2a2b489a85b132f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 000834321774..ea71c413c926 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -144,6 +144,11 @@ static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
+ 	.id	= 0x52,
+ };
+ 
++static const struct renesas_soc soc_rcar_m3_n __initconst __maybe_unused = {
++	.family = &fam_rcar_gen3,
++	.id     = 0x55,
++};
++
+ static const struct renesas_soc soc_rcar_v3m __initconst __maybe_unused = {
+ 	.family	= &fam_rcar_gen3,
+ 	.id	= 0x54,
+@@ -214,6 +219,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
+ #ifdef CONFIG_ARCH_R8A7796
+ 	{ .compatible = "renesas,r8a7796",	.data = &soc_rcar_m3_w },
+ #endif
++#ifdef CONFIG_ARCH_R8A77965
++	{ .compatible = "renesas,r8a77965",	.data = &soc_rcar_m3_n },
++#endif
+ #ifdef CONFIG_ARCH_R8A77970
+ 	{ .compatible = "renesas,r8a77970",	.data = &soc_rcar_v3m },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0837-spi-rspi-use-correct-enum-for-DMA-transfer-direction.patch b/patches/0837-spi-rspi-use-correct-enum-for-DMA-transfer-direction.patch
new file mode 100644
index 00000000000000..857560d35f8d10
--- /dev/null
+++ b/patches/0837-spi-rspi-use-correct-enum-for-DMA-transfer-direction.patch
@@ -0,0 +1,56 @@
+From 8cc716f850cd4dbee1ce4e10f7cc5b6f7bf807a3 Mon Sep 17 00:00:00 2001
+From: Stefan Agner <stefan@agner.ch>
+Date: Mon, 19 Mar 2018 23:16:22 +0100
+Subject: [PATCH 0837/1795] spi: rspi: use correct enum for DMA transfer
+ direction
+
+Use enum dma_transfer_direction as required by dmaengine_prep_slave_sg
+instead of enum dma_data_direction. This won't change behavior in
+practice as the enum values are equivalent.
+
+This fixes two warnings when building with clang:
+  drivers/spi/spi-rspi.c:538:26: warning: implicit conversion from enumeration
+      type 'enum dma_data_direction' to different enumeration type
+      'enum dma_transfer_direction' [-Wenum-conversion]
+                                        rx->sgl, rx->nents, DMA_FROM_DEVICE,
+                                                            ^~~~~~~~~~~~~~~
+  drivers/spi/spi-rspi.c:558:26: warning: implicit conversion from enumeration
+      type 'enum dma_data_direction' to different enumeration type
+      'enum dma_transfer_direction' [-Wenum-conversion]
+                                        tx->sgl, tx->nents, DMA_TO_DEVICE,
+                                                            ^~~~~~~~~~~~~
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 768d59f5d0139a6ff09e4430ec29cdc8b436421a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-rspi.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
+index 0835a8d88fb8..95dc4d78618d 100644
+--- a/drivers/spi/spi-rspi.c
++++ b/drivers/spi/spi-rspi.c
+@@ -535,7 +535,7 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
+ 	/* First prepare and submit the DMA request(s), as this may fail */
+ 	if (rx) {
+ 		desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
+-					rx->sgl, rx->nents, DMA_FROM_DEVICE,
++					rx->sgl, rx->nents, DMA_DEV_TO_MEM,
+ 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 		if (!desc_rx) {
+ 			ret = -EAGAIN;
+@@ -555,7 +555,7 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
+ 
+ 	if (tx) {
+ 		desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
+-					tx->sgl, tx->nents, DMA_TO_DEVICE,
++					tx->sgl, tx->nents, DMA_MEM_TO_DEV,
+ 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 		if (!desc_tx) {
+ 			ret = -EAGAIN;
+-- 
+2.19.0
+
diff --git a/patches/0838-sh_eth-simplify-sh_eth_check_reset.patch b/patches/0838-sh_eth-simplify-sh_eth_check_reset.patch
new file mode 100644
index 00000000000000..c2016d7d7daf62
--- /dev/null
+++ b/patches/0838-sh_eth-simplify-sh_eth_check_reset.patch
@@ -0,0 +1,52 @@
+From 3e2a002b8666045fccafa3fc3580bc03a8331b41 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 18 Feb 2018 18:21:05 +0300
+Subject: [PATCH 0838/1795] sh_eth: simplify sh_eth_check_reset()
+
+The *while* loop in this function  can be turned into a normal *for* loop.
+And getting rid  of the  single return point saves us a few more LoCs...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 607ea03221ff84943e840d3707dbeb0b4b88959f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 16 ++++++----------
+ 1 file changed, 6 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 4e2f46fa8353..20ad727d3677 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -976,20 +976,16 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
+ 
+ static int sh_eth_check_reset(struct net_device *ndev)
+ {
+-	int ret = 0;
+-	int cnt = 100;
++	int cnt;
+ 
+-	while (cnt > 0) {
++	for (cnt = 100; cnt > 0; cnt--) {
+ 		if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
+-			break;
++			return 0;
+ 		mdelay(1);
+-		cnt--;
+-	}
+-	if (cnt <= 0) {
+-		netdev_err(ndev, "Device reset failed\n");
+-		ret = -ETIMEDOUT;
+ 	}
+-	return ret;
++
++	netdev_err(ndev, "Device reset failed\n");
++	return -ETIMEDOUT;
+ }
+ 
+ static int sh_eth_reset(struct net_device *ndev)
+-- 
+2.19.0
+
diff --git a/patches/0839-sh_eth-TSU_QTAG0-1-registers-the-same-as-TSU_QTAGM0-.patch b/patches/0839-sh_eth-TSU_QTAG0-1-registers-the-same-as-TSU_QTAGM0-.patch
new file mode 100644
index 00000000000000..f2f42100158656
--- /dev/null
+++ b/patches/0839-sh_eth-TSU_QTAG0-1-registers-the-same-as-TSU_QTAGM0-.patch
@@ -0,0 +1,82 @@
+From 08816978072e148572cbab4b90648f5b40fff0b6 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Feb 2018 20:28:16 +0300
+Subject: [PATCH 0839/1795] sh_eth: TSU_QTAG0/1 registers the same as
+ TSU_QTAGM0/1
+
+The TSU_QTAG0/1 registers found in the Gigabit Ether controllers actually
+have the same long name  as the TSU_QTAGM0/1 registers in the early Ether
+controllers:  Qtag Addition/Deletion Set Register (Port 0/1 to 1/0); thus
+there's no need to make a difference in sh_eth_tsu_init() between those
+controllers. Unfortunately, we can't just remove TSU_QTAG0/1 from the
+register *enum* because that would break the ethtool register dump...
+
+Fixes: b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4869a1476df5ef2d09fa52acc9cfcc21b47194c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 15 ++++-----------
+ drivers/net/ethernet/renesas/sh_eth.h |  4 ++--
+ 2 files changed, 6 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 20ad727d3677..379270388ef7 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -123,8 +123,8 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[TSU_FWSL0]	= 0x0030,
+ 	[TSU_FWSL1]	= 0x0034,
+ 	[TSU_FWSLC]	= 0x0038,
+-	[TSU_QTAG0]	= 0x0040,
+-	[TSU_QTAG1]	= 0x0044,
++	[TSU_QTAGM0]	= 0x0040,
++	[TSU_QTAGM1]	= 0x0044,
+ 	[TSU_FWSR]	= 0x0050,
+ 	[TSU_FWINMK]	= 0x0054,
+ 	[TSU_ADQT0]	= 0x0048,
+@@ -2093,8 +2093,6 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
+ 		add_tsu_reg(TSU_FWSL0);
+ 		add_tsu_reg(TSU_FWSL1);
+ 		add_tsu_reg(TSU_FWSLC);
+-		add_tsu_reg(TSU_QTAG0);
+-		add_tsu_reg(TSU_QTAG1);
+ 		add_tsu_reg(TSU_QTAGM0);
+ 		add_tsu_reg(TSU_QTAGM1);
+ 		add_tsu_reg(TSU_FWSR);
+@@ -2922,13 +2920,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp)
+ 	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
+ 	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
+ 	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
+-	if (sh_eth_is_gether(mdp)) {
+-		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
+-		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
+-	} else {
+-		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
+-		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
+-	}
++	sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
++	sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
+ 	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
+ 	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
+ 	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index fdd6d71c03d1..21047d58a93f 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -118,8 +118,8 @@ enum {
+ 	TSU_FWSL0,
+ 	TSU_FWSL1,
+ 	TSU_FWSLC,
+-	TSU_QTAG0,
+-	TSU_QTAG1,
++	TSU_QTAG0,			/* Same as TSU_QTAGM0 */
++	TSU_QTAG1,			/* Same as TSU_QTAGM1 */
+ 	TSU_QTAGM0,
+ 	TSU_QTAGM1,
+ 	TSU_FWSR,
+-- 
+2.19.0
+
diff --git a/patches/0840-sh_eth-add-sh_eth_cpu_data-soft_reset-method.patch b/patches/0840-sh_eth-add-sh_eth_cpu_data-soft_reset-method.patch
new file mode 100644
index 00000000000000..ffbae5d179a120
--- /dev/null
+++ b/patches/0840-sh_eth-add-sh_eth_cpu_data-soft_reset-method.patch
@@ -0,0 +1,283 @@
+From 211c453a2cdf4d34d182c3ef0d72f0c711e76fa5 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Mar 2018 23:07:41 +0300
+Subject: [PATCH 0840/1795] sh_eth: add sh_eth_cpu_data::soft_reset() method
+
+sh_eth_reset() performs a software reset which is implemented in a
+completely different way for the GEther-like controllers vs the other
+controllers due to a different layout of EDMR (and other factors) --
+it therefore makes sense to convert this function to a mandatory
+sh_eth_cpu_data::soft_reset() method and thus get rid of the runtime
+controller type check via sh_eth_is_{gether|rz_fast_ether}().
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4ceedeb1b68e376ccfec9f8d2e46bcd541702aba)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 135 +++++++++++++++-----------
+ drivers/net/ethernet/renesas/sh_eth.h |   3 +
+ 2 files changed, 83 insertions(+), 55 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 379270388ef7..5e802453b6ec 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -501,6 +501,62 @@ static void sh_eth_chip_reset(struct net_device *ndev)
+ 	mdelay(1);
+ }
+ 
++static int sh_eth_soft_reset(struct net_device *ndev)
++{
++	sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
++	mdelay(3);
++	sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
++
++	return 0;
++}
++
++static int sh_eth_check_soft_reset(struct net_device *ndev)
++{
++	int cnt;
++
++	for (cnt = 100; cnt > 0; cnt--) {
++		if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
++			return 0;
++		mdelay(1);
++	}
++
++	netdev_err(ndev, "Device reset failed\n");
++	return -ETIMEDOUT;
++}
++
++static int sh_eth_soft_reset_gether(struct net_device *ndev)
++{
++	struct sh_eth_private *mdp = netdev_priv(ndev);
++	int ret;
++
++	sh_eth_write(ndev, EDSR_ENALL, EDSR);
++	sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
++
++	ret = sh_eth_check_soft_reset(ndev);
++	if (ret)
++		return ret;
++
++	/* Table Init */
++	sh_eth_write(ndev, 0, TDLAR);
++	sh_eth_write(ndev, 0, TDFAR);
++	sh_eth_write(ndev, 0, TDFXR);
++	sh_eth_write(ndev, 0, TDFFR);
++	sh_eth_write(ndev, 0, RDLAR);
++	sh_eth_write(ndev, 0, RDFAR);
++	sh_eth_write(ndev, 0, RDFXR);
++	sh_eth_write(ndev, 0, RDFFR);
++
++	/* Reset HW CRC register */
++	if (mdp->cd->hw_checksum)
++		sh_eth_write(ndev, 0, CSMR);
++
++	/* Select MII mode */
++	if (mdp->cd->select_mii)
++		sh_eth_select_mii(ndev);
++
++	return ret;
++}
++
+ static void sh_eth_set_rate_gether(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+@@ -521,6 +577,8 @@ static void sh_eth_set_rate_gether(struct net_device *ndev)
+ #ifdef CONFIG_OF
+ /* R7S72100 */
+ static struct sh_eth_cpu_data r7s72100_data = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
+ 	.chip_reset	= sh_eth_chip_reset,
+ 	.set_duplex	= sh_eth_set_duplex,
+ 
+@@ -565,6 +623,8 @@ static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
+ 
+ /* R8A7740 */
+ static struct sh_eth_cpu_data r8a7740_data = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
+ 	.chip_reset	= sh_eth_chip_reset_r8a7740,
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_gether,
+@@ -620,6 +680,8 @@ static void sh_eth_set_rate_rcar(struct net_device *ndev)
+ 
+ /* R-Car Gen1 */
+ static struct sh_eth_cpu_data rcar_gen1_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_rcar,
+ 
+@@ -647,6 +709,8 @@ static struct sh_eth_cpu_data rcar_gen1_data = {
+ 
+ /* R-Car Gen2 and RZ/G1 */
+ static struct sh_eth_cpu_data rcar_gen2_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_rcar,
+ 
+@@ -694,6 +758,8 @@ static void sh_eth_set_rate_sh7724(struct net_device *ndev)
+ 
+ /* SH7724 */
+ static struct sh_eth_cpu_data sh7724_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_sh7724,
+ 
+@@ -736,6 +802,8 @@ static void sh_eth_set_rate_sh7757(struct net_device *ndev)
+ 
+ /* SH7757 */
+ static struct sh_eth_cpu_data sh7757_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_sh7757,
+ 
+@@ -808,6 +876,8 @@ static void sh_eth_set_rate_giga(struct net_device *ndev)
+ 
+ /* SH7757(GETHERC) */
+ static struct sh_eth_cpu_data sh7757_data_giga = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
+ 	.chip_reset	= sh_eth_chip_reset_giga,
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_giga,
+@@ -847,6 +917,8 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
+ 
+ /* SH7734 */
+ static struct sh_eth_cpu_data sh7734_data = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
+ 	.chip_reset	= sh_eth_chip_reset,
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_gether,
+@@ -883,6 +955,8 @@ static struct sh_eth_cpu_data sh7734_data = {
+ 
+ /* SH7763 */
+ static struct sh_eth_cpu_data sh7763_data = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
+ 	.chip_reset	= sh_eth_chip_reset,
+ 	.set_duplex	= sh_eth_set_duplex,
+ 	.set_rate	= sh_eth_set_rate_gether,
+@@ -917,6 +991,8 @@ static struct sh_eth_cpu_data sh7763_data = {
+ };
+ 
+ static struct sh_eth_cpu_data sh7619_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
+ 
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -935,6 +1011,8 @@ static struct sh_eth_cpu_data sh7619_data = {
+ };
+ 
+ static struct sh_eth_cpu_data sh771x_data = {
++	.soft_reset	= sh_eth_soft_reset,
++
+ 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
+ 
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -974,59 +1052,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
+ 		cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
+ }
+ 
+-static int sh_eth_check_reset(struct net_device *ndev)
+-{
+-	int cnt;
+-
+-	for (cnt = 100; cnt > 0; cnt--) {
+-		if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
+-			return 0;
+-		mdelay(1);
+-	}
+-
+-	netdev_err(ndev, "Device reset failed\n");
+-	return -ETIMEDOUT;
+-}
+-
+-static int sh_eth_reset(struct net_device *ndev)
+-{
+-	struct sh_eth_private *mdp = netdev_priv(ndev);
+-	int ret = 0;
+-
+-	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
+-		sh_eth_write(ndev, EDSR_ENALL, EDSR);
+-		sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
+-
+-		ret = sh_eth_check_reset(ndev);
+-		if (ret)
+-			return ret;
+-
+-		/* Table Init */
+-		sh_eth_write(ndev, 0x0, TDLAR);
+-		sh_eth_write(ndev, 0x0, TDFAR);
+-		sh_eth_write(ndev, 0x0, TDFXR);
+-		sh_eth_write(ndev, 0x0, TDFFR);
+-		sh_eth_write(ndev, 0x0, RDLAR);
+-		sh_eth_write(ndev, 0x0, RDFAR);
+-		sh_eth_write(ndev, 0x0, RDFXR);
+-		sh_eth_write(ndev, 0x0, RDFFR);
+-
+-		/* Reset HW CRC register */
+-		if (mdp->cd->hw_checksum)
+-			sh_eth_write(ndev, 0x0, CSMR);
+-
+-		/* Select MII mode */
+-		if (mdp->cd->select_mii)
+-			sh_eth_select_mii(ndev);
+-	} else {
+-		sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
+-		mdelay(3);
+-		sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
+-	}
+-
+-	return ret;
+-}
+-
+ static void sh_eth_set_receive_align(struct sk_buff *skb)
+ {
+ 	uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
+@@ -1362,7 +1387,7 @@ static int sh_eth_dev_init(struct net_device *ndev)
+ 	int ret;
+ 
+ 	/* Soft Reset */
+-	ret = sh_eth_reset(ndev);
++	ret = mdp->cd->soft_reset(ndev);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1463,7 +1488,7 @@ static void sh_eth_dev_exit(struct net_device *ndev)
+ 	 */
+ 	msleep(2); /* max frame time at 10 Mbps < 1250 us */
+ 	sh_eth_get_stats(ndev);
+-	sh_eth_reset(ndev);
++	mdp->cd->soft_reset(ndev);
+ 
+ 	/* Set MAC address again */
+ 	update_mac_address(ndev);
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 21047d58a93f..ff3520b0d86f 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -469,6 +469,9 @@ struct sh_eth_rxdesc {
+ 
+ /* This structure is used by each CPU dependency handling. */
+ struct sh_eth_cpu_data {
++	/* mandatory functions */
++	int (*soft_reset)(struct net_device *ndev);
++
+ 	/* optional functions */
+ 	void (*chip_reset)(struct net_device *ndev);
+ 	void (*set_duplex)(struct net_device *ndev);
+-- 
+2.19.0
+
diff --git a/patches/0841-sh_eth-add-sh_eth_cpu_data-edtrr_trns-value.patch b/patches/0841-sh_eth-add-sh_eth_cpu_data-edtrr_trns-value.patch
new file mode 100644
index 00000000000000..ed284f98c932b3
--- /dev/null
+++ b/patches/0841-sh_eth-add-sh_eth_cpu_data-edtrr_trns-value.patch
@@ -0,0 +1,166 @@
+From ba8e227d5783afc4a26f65275f862ab9ad35d55a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Mar 2018 23:08:42 +0300
+Subject: [PATCH 0841/1795] sh_eth: add sh_eth_cpu_data::edtrr_trns value
+
+sh_eth_get_edtrr_trns() returns the value to be written to EDTRR in order
+to start TX DMA -- this value is different between the GEther-like and
+the other controllers. We can replace this function (and thus get rid of
+the calls to sh_eth_is_{gether|rz_fast_ether}() by it) with a new field
+'edtrr_trns' in the 'struct sh_eth_cpu_data'.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 3e416992e2fae2c3177bed157534503691dc3510)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 27 +++++++++++++++------------
+ drivers/net/ethernet/renesas/sh_eth.h |  1 +
+ 2 files changed, 16 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 5e802453b6ec..18260155f9c4 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -584,6 +584,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_RZ,
+ 
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
+ 	.ecsr_value	= ECSR_ICD,
+ 	.ecsipr_value	= ECSIPR_ICDIP,
+ 	.eesipr_value	= EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
+@@ -631,6 +632,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
+ 
+ 	.register_type	= SH_ETH_REG_GIGABIT,
+ 
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
+ 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
+ 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -687,6 +689,7 @@ static struct sh_eth_cpu_data rcar_gen1_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_RCAR,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
+ 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
+@@ -716,6 +719,7 @@ static struct sh_eth_cpu_data rcar_gen2_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_RCAR,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
+ 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
+ 			  ECSIPR_MPDIP,
+@@ -765,6 +769,7 @@ static struct sh_eth_cpu_data sh7724_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_SH4,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
+ 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
+@@ -809,6 +814,7 @@ static struct sh_eth_cpu_data sh7757_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_SH4,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+ 			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+ 			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+@@ -884,6 +890,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
+ 
+ 	.register_type	= SH_ETH_REG_GIGABIT,
+ 
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
+ 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
+ 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -925,6 +932,7 @@ static struct sh_eth_cpu_data sh7734_data = {
+ 
+ 	.register_type	= SH_ETH_REG_GIGABIT,
+ 
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
+ 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
+ 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -963,6 +971,7 @@ static struct sh_eth_cpu_data sh7763_data = {
+ 
+ 	.register_type	= SH_ETH_REG_GIGABIT,
+ 
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
+ 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
+ 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+@@ -995,6 +1004,7 @@ static struct sh_eth_cpu_data sh7619_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+ 			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+ 			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+@@ -1015,6 +1025,7 @@ static struct sh_eth_cpu_data sh771x_data = {
+ 
+ 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
+ 
++	.edtrr_trns	= EDTRR_TRNS_ETHER,
+ 	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+ 			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+ 			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+@@ -1094,14 +1105,6 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac)
+ 	}
+ }
+ 
+-static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
+-{
+-	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
+-		return EDTRR_TRNS_GETHER;
+-	else
+-		return EDTRR_TRNS_ETHER;
+-}
+-
+ struct bb_info {
+ 	void (*set_gate)(void *addr);
+ 	struct mdiobb_ctrl ctrl;
+@@ -1741,9 +1744,9 @@ static void sh_eth_error(struct net_device *ndev, u32 intr_status)
+ 		sh_eth_tx_free(ndev, true);
+ 
+ 		/* SH7712 BUG */
+-		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
++		if (edtrr ^ mdp->cd->edtrr_trns) {
+ 			/* tx dma start */
+-			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
++			sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
+ 		}
+ 		/* wakeup */
+ 		netif_wake_queue(ndev);
+@@ -2475,8 +2478,8 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+ 
+ 	mdp->cur_tx++;
+ 
+-	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
+-		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
++	if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
++		sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
+ 
+ 	return NETDEV_TX_OK;
+ }
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index ff3520b0d86f..aa3c45153c9a 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -479,6 +479,7 @@ struct sh_eth_cpu_data {
+ 
+ 	/* mandatory initialize value */
+ 	int register_type;
++	u32 edtrr_trns;
+ 	u32 eesipr_value;
+ 
+ 	/* optional initialize value */
+-- 
+2.19.0
+
diff --git a/patches/0842-sh_eth-add-sh_eth_cpu_data-xdfar_rw-flag.patch b/patches/0842-sh_eth-add-sh_eth_cpu_data-xdfar_rw-flag.patch
new file mode 100644
index 00000000000000..f83f54a95b66a2
--- /dev/null
+++ b/patches/0842-sh_eth-add-sh_eth_cpu_data-xdfar_rw-flag.patch
@@ -0,0 +1,100 @@
+From 6b1cc4eddd846daa44e04845f42e62afd8304d13 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Mar 2018 23:09:55 +0300
+Subject: [PATCH 0842/1795] sh_eth: add sh_eth_cpu_data::xdfar_rw flag
+
+The GEther-like controllers have writeable RDFAR/TDFAR, on the others
+they are read-only or just absent (on R-Car). Currently we are calling
+sh_eth_is_{gether|rz_fast_ether}() in order to check if these registers
+can be written to, however it would be simpler to check the new 'xdfar_rw'
+bitfield in the 'struct sh_eth_cpu_data'...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 246e30cc4fd8db8390e83617fa5ff29ad5280ad9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 11 +++++++----
+ drivers/net/ethernet/renesas/sh_eth.h |  1 +
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 18260155f9c4..5b1f9f1cf612 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -611,6 +611,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
+ 	.rpadir_value   = 2 << 16,
+ 	.no_trimd	= 1,
+ 	.no_ade		= 1,
++	.xdfar_rw	= 1,
+ 	.hw_checksum	= 1,
+ 	.tsu		= 1,
+ };
+@@ -659,6 +660,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
+ 	.rpadir_value   = 2 << 16,
+ 	.no_trimd	= 1,
+ 	.no_ade		= 1,
++	.xdfar_rw	= 1,
+ 	.hw_checksum	= 1,
+ 	.tsu		= 1,
+ 	.select_mii	= 1,
+@@ -918,6 +920,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
+ 	.rpadir_value   = 2 << 16,
+ 	.no_trimd	= 1,
+ 	.no_ade		= 1,
++	.xdfar_rw	= 1,
+ 	.tsu		= 1,
+ 	.dual_port	= 1,
+ };
+@@ -955,6 +958,7 @@ static struct sh_eth_cpu_data sh7734_data = {
+ 	.hw_swap	= 1,
+ 	.no_trimd	= 1,
+ 	.no_ade		= 1,
++	.xdfar_rw	= 1,
+ 	.tsu		= 1,
+ 	.hw_checksum	= 1,
+ 	.select_mii	= 1,
+@@ -993,6 +997,7 @@ static struct sh_eth_cpu_data sh7763_data = {
+ 	.hw_swap	= 1,
+ 	.no_trimd	= 1,
+ 	.no_ade		= 1,
++	.xdfar_rw	= 1,
+ 	.tsu		= 1,
+ 	.irq_flags	= IRQF_SHARED,
+ 	.magic		= 1,
+@@ -1301,8 +1306,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
+ 		/* Rx descriptor address set */
+ 		if (i == 0) {
+ 			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
+-			if (sh_eth_is_gether(mdp) ||
+-			    sh_eth_is_rz_fast_ether(mdp))
++			if (mdp->cd->xdfar_rw)
+ 				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
+ 		}
+ 	}
+@@ -1324,8 +1328,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
+ 		if (i == 0) {
+ 			/* Tx descriptor address set */
+ 			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
+-			if (sh_eth_is_gether(mdp) ||
+-			    sh_eth_is_rz_fast_ether(mdp))
++			if (mdp->cd->xdfar_rw)
+ 				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
+ 		}
+ 	}
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index aa3c45153c9a..25c0b1db060a 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -508,6 +508,7 @@ struct sh_eth_cpu_data {
+ 	unsigned rpadir:1;	/* E-DMAC have RPADIR */
+ 	unsigned no_trimd:1;	/* E-DMAC DO NOT have TRIMD */
+ 	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
++	unsigned xdfar_rw:1;	/* E-DMAC has writeable RDFAR/TDFAR */
+ 	unsigned hw_checksum:1;	/* E-DMAC has CSMR */
+ 	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
+ 	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
+-- 
+2.19.0
+
diff --git a/patches/0843-sh_eth-add-sh_eth_cpu_data-no_tx_cntrs-flag.patch b/patches/0843-sh_eth-add-sh_eth_cpu_data-no_tx_cntrs-flag.patch
new file mode 100644
index 00000000000000..1e9cf7d307447a
--- /dev/null
+++ b/patches/0843-sh_eth-add-sh_eth_cpu_data-no_tx_cntrs-flag.patch
@@ -0,0 +1,71 @@
+From 74dfcc4e0eb243d7e79054b459721d682b3a6e64 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Mar 2018 23:11:19 +0300
+Subject: [PATCH 0843/1795] sh_eth: add sh_eth_cpu_data::no_tx_cntrs flag
+
+RZ/A1H (R7S72100) Ether controller doesn't  seem to have the TX counter
+registers like TROCR/CDCR/LCCR (or at least they are still undocumented
+like some TSU registers), so we bail out of sh_eth_get_stats() early in
+this case.  Currently we are calling sh_eth_is_rz_fast_ether() in order
+to check for this, but it would be simpler to check the new 'no_tx_cntrs'
+bitfield in the 'struct sh_eth_cpu_data'; then we'd be able  to remove
+sh_eth_is_rz_fast_ether() as there would be no callers left...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit ce9134dff6d90c9f9c6bfd3d32dffdadf8a8e668)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 8 ++------
+ drivers/net/ethernet/renesas/sh_eth.h | 1 +
+ 2 files changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 5b1f9f1cf612..ea0ac1349994 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -455,11 +455,6 @@ static bool sh_eth_is_gether(struct sh_eth_private *mdp)
+ 	return mdp->reg_offset == sh_eth_offset_gigabit;
+ }
+ 
+-static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
+-{
+-	return mdp->reg_offset == sh_eth_offset_fast_rz;
+-}
+-
+ static void sh_eth_select_mii(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+@@ -614,6 +609,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
+ 	.xdfar_rw	= 1,
+ 	.hw_checksum	= 1,
+ 	.tsu		= 1,
++	.no_tx_cntrs	= 1,
+ };
+ 
+ static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
+@@ -2507,7 +2503,7 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+ 
+-	if (sh_eth_is_rz_fast_ether(mdp))
++	if (mdp->cd->no_tx_cntrs)
+ 		return &ndev->stats;
+ 
+ 	if (!mdp->is_opened)
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 25c0b1db060a..7ea162a56c77 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -514,6 +514,7 @@ struct sh_eth_cpu_data {
+ 	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
+ 	unsigned rtrate:1;	/* EtherC has RTRATE register */
+ 	unsigned magic:1;	/* EtherC has ECMR.MPDE and ECSR.MPD */
++	unsigned no_tx_cntrs:1;	/* EtherC DOES NOT have TX error counters */
+ 	unsigned dual_port:1;	/* Dual EtherC/E-DMAC */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0844-sh_eth-add-sh_eth_cpu_data-cexcr-flag.patch b/patches/0844-sh_eth-add-sh_eth_cpu_data-cexcr-flag.patch
new file mode 100644
index 00000000000000..e7c28bcaee4622
--- /dev/null
+++ b/patches/0844-sh_eth-add-sh_eth_cpu_data-cexcr-flag.patch
@@ -0,0 +1,93 @@
+From a7841b88c91ff3fe92c5347719b04dd5d34ebee4 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 24 Mar 2018 23:12:54 +0300
+Subject: [PATCH 0844/1795] sh_eth: add sh_eth_cpu_data::cexcr flag
+
+GEther controllers have CERCR/CEECR instead of CNDCR on the others.
+Currently we are calling sh_eth_is_gether() in order to check for this,
+however it would be simpler  to check the new 'cexcr' bitfield in the
+'struct sh_eth_cpu_data';  then we'd be able to remove sh_eth_is_gether()
+as there would be no callers left...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4c1d45850d5327049bce461743179b46adc33f9e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 11 +++++------
+ drivers/net/ethernet/renesas/sh_eth.h |  1 +
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index ea0ac1349994..0c3e87df8fe2 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -450,11 +450,6 @@ static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
+ 	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
+ }
+ 
+-static bool sh_eth_is_gether(struct sh_eth_private *mdp)
+-{
+-	return mdp->reg_offset == sh_eth_offset_gigabit;
+-}
+-
+ static void sh_eth_select_mii(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+@@ -661,6 +656,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
+ 	.tsu		= 1,
+ 	.select_mii	= 1,
+ 	.magic		= 1,
++	.cexcr		= 1,
+ };
+ 
+ /* There is CPU dependent code */
+@@ -918,6 +914,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
+ 	.no_ade		= 1,
+ 	.xdfar_rw	= 1,
+ 	.tsu		= 1,
++	.cexcr		= 1,
+ 	.dual_port	= 1,
+ };
+ 
+@@ -959,6 +956,7 @@ static struct sh_eth_cpu_data sh7734_data = {
+ 	.hw_checksum	= 1,
+ 	.select_mii	= 1,
+ 	.magic		= 1,
++	.cexcr		= 1,
+ };
+ 
+ /* SH7763 */
+@@ -997,6 +995,7 @@ static struct sh_eth_cpu_data sh7763_data = {
+ 	.tsu		= 1,
+ 	.irq_flags	= IRQF_SHARED,
+ 	.magic		= 1,
++	.cexcr		= 1,
+ 	.dual_port	= 1,
+ };
+ 
+@@ -2513,7 +2512,7 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
+ 	sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
+ 	sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
+ 
+-	if (sh_eth_is_gether(mdp)) {
++	if (mdp->cd->cexcr) {
+ 		sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
+ 				   CERCR);
+ 		sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 7ea162a56c77..a0416e04306a 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -515,6 +515,7 @@ struct sh_eth_cpu_data {
+ 	unsigned rtrate:1;	/* EtherC has RTRATE register */
+ 	unsigned magic:1;	/* EtherC has ECMR.MPDE and ECSR.MPD */
+ 	unsigned no_tx_cntrs:1;	/* EtherC DOES NOT have TX error counters */
++	unsigned cexcr:1;	/* EtherC has CERCR/CEECR */
+ 	unsigned dual_port:1;	/* Dual EtherC/E-DMAC */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0845-sh_eth-add-sh_eth_cpu_data-no_xdfar-flag.patch b/patches/0845-sh_eth-add-sh_eth_cpu_data-no_xdfar-flag.patch
new file mode 100644
index 00000000000000..2a8df6c888d190
--- /dev/null
+++ b/patches/0845-sh_eth-add-sh_eth_cpu_data-no_xdfar-flag.patch
@@ -0,0 +1,68 @@
+From 0e3fa3833575a249cc98caabfb1c461d0f237d28 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 1 Apr 2018 00:22:08 +0300
+Subject: [PATCH 0845/1795] sh_eth: add sh_eth_cpu_data::no_xdfar flag
+
+The commit 6ded286555c2 ("sh_eth: Fix RX recovery on R-Car in case of RX
+ring underrun") added a check for an bad RDFAR offset in sh_eth_rx(), so
+that the code could work on the R-Car Ether controllers which don't have
+this register (and TDFAR), then the commit 3365711df02 ("sh_eth: WARN on
+access to a register not implemented in a particular chip") replaced
+offset 0 with 0xffff. Adding/checking the 'no_xdfar' bit field in the
+'struct sh_eth_cpu_data' instead results in less object code...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 6e80e55bd37a90b412f168b1667ffa7d2debd46b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 5 +++--
+ drivers/net/ethernet/renesas/sh_eth.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 0c3e87df8fe2..48d334ceaa95 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -702,6 +702,7 @@ static struct sh_eth_cpu_data rcar_gen1_data = {
+ 	.mpr		= 1,
+ 	.tpauser	= 1,
+ 	.hw_swap	= 1,
++	.no_xdfar	= 1,
+ };
+ 
+ /* R-Car Gen2 and RZ/G1 */
+@@ -735,6 +736,7 @@ static struct sh_eth_cpu_data rcar_gen2_data = {
+ 	.mpr		= 1,
+ 	.tpauser	= 1,
+ 	.hw_swap	= 1,
++	.no_xdfar	= 1,
+ 	.rmiimode	= 1,
+ 	.magic		= 1,
+ };
+@@ -1615,8 +1617,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
+ 	/* If we don't need to check status, don't. -KDU */
+ 	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
+ 		/* fix the values for the next receiving if RDE is set */
+-		if (intr_status & EESR_RDE &&
+-		    mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
++		if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
+ 			u32 count = (sh_eth_read(ndev, RDFAR) -
+ 				     sh_eth_read(ndev, RDLAR)) >> 4;
+ 
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index a0416e04306a..a5b792ce2ae7 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -508,6 +508,7 @@ struct sh_eth_cpu_data {
+ 	unsigned rpadir:1;	/* E-DMAC have RPADIR */
+ 	unsigned no_trimd:1;	/* E-DMAC DO NOT have TRIMD */
+ 	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
++	unsigned no_xdfar:1;	/* E-DMAC DOES NOT have RDFAR/TDFAR */
+ 	unsigned xdfar_rw:1;	/* E-DMAC has writeable RDFAR/TDFAR */
+ 	unsigned hw_checksum:1;	/* E-DMAC has CSMR */
+ 	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
+-- 
+2.19.0
+
diff --git a/patches/0846-sh_eth-kill-useless-check-in-__sh_eth_get_regs.patch b/patches/0846-sh_eth-kill-useless-check-in-__sh_eth_get_regs.patch
new file mode 100644
index 00000000000000..0c37acf6887a36
--- /dev/null
+++ b/patches/0846-sh_eth-kill-useless-check-in-__sh_eth_get_regs.patch
@@ -0,0 +1,58 @@
+From d6832ff45e57b7c921048c8d48fa561535059242 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 1 Apr 2018 00:23:51 +0300
+Subject: [PATCH 0846/1795] sh_eth: kill useless check in __sh_eth_get_regs()
+
+Iff TSU registers exist on a given [G]Ether controller, they always include
+the CAM entry table registers (TSU_ADR{H|L}<n>), thus the check for invalid
+TSU_ADRH0 offset in __sh_eth_get_regs() is useless...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit e14549a50a6c5e3320bb941440b1c3ae4812ea69)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 25 ++++++++++---------------
+ 1 file changed, 10 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 48d334ceaa95..d14914495a65 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2134,22 +2134,17 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
+ 		add_tsu_reg(TSU_POST2);
+ 		add_tsu_reg(TSU_POST3);
+ 		add_tsu_reg(TSU_POST4);
+-		if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
+-			/* This is the start of a table, not just a single
+-			 * register.
+-			 */
+-			if (buf) {
+-				unsigned int i;
+-
+-				mark_reg_valid(TSU_ADRH0);
+-				for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
+-					*buf++ = ioread32(
+-						mdp->tsu_addr +
+-						mdp->reg_offset[TSU_ADRH0] +
+-						i * 4);
+-			}
+-			len += SH_ETH_TSU_CAM_ENTRIES * 2;
++		/* This is the start of a table, not just a single register. */
++		if (buf) {
++			unsigned int i;
++
++			mark_reg_valid(TSU_ADRH0);
++			for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
++				*buf++ = ioread32(mdp->tsu_addr +
++						  mdp->reg_offset[TSU_ADRH0] +
++						  i * 4);
+ 		}
++		len += SH_ETH_TSU_CAM_ENTRIES * 2;
+ 	}
+ 
+ #undef mark_reg_valid
+-- 
+2.19.0
+
diff --git a/patches/0847-sh_eth-Change-platform-check-to-CONFIG_ARCH_RENESAS.patch b/patches/0847-sh_eth-Change-platform-check-to-CONFIG_ARCH_RENESAS.patch
new file mode 100644
index 00000000000000..08cea59c8afecc
--- /dev/null
+++ b/patches/0847-sh_eth-Change-platform-check-to-CONFIG_ARCH_RENESAS.patch
@@ -0,0 +1,44 @@
+From 45c57620579d154de67115ba6ebc580bf00967a2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 May 2018 12:52:51 +0200
+Subject: [PATCH 0847/1795] sh_eth: Change platform check to
+ CONFIG_ARCH_RENESAS
+
+Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
+is CONFIG_ARCH_RENESAS a more appropriate platform check than the legacy
+CONFIG_ARCH_SHMOBILE, hence use the former.
+
+Renesas SuperH SH-Mobile SoCs are still covered by the CONFIG_CPU_SH4
+check.
+
+This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
+future.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit b16a960ddbf0d4fd6aaabee42d7ec4c4c3ec836d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index a5b792ce2ae7..1bf930d4a1e5 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -163,7 +163,7 @@ enum {
+ };
+ 
+ /* Driver's parameters */
+-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
++#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
+ #define SH_ETH_RX_ALIGN		32
+ #else
+ #define SH_ETH_RX_ALIGN		2
+-- 
+2.19.0
+
diff --git a/patches/0848-mmc-sh_mmcif-remove-some-cruft.patch b/patches/0848-mmc-sh_mmcif-remove-some-cruft.patch
new file mode 100644
index 00000000000000..dea342ff6db2d9
--- /dev/null
+++ b/patches/0848-mmc-sh_mmcif-remove-some-cruft.patch
@@ -0,0 +1,48 @@
+From 65400b0bd3c8c8939f81b4b13b6033bac8d45455 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 5 Feb 2018 14:28:22 +0100
+Subject: [PATCH 0848/1795] mmc: sh_mmcif: remove some cruft
+
+The TODO section from 2010 is obsolete. We have DMA and PM meanwhile and
+we always want to handle errors better, if possible. Also DRIVER_VERSION
+is not used anymore these days.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 5a871bf081dd7915ed7b9942a5484ff0c742e2cc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/sh_mmcif.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
+index 7bb00c68a756..4c2a1f8ddbf3 100644
+--- a/drivers/mmc/host/sh_mmcif.c
++++ b/drivers/mmc/host/sh_mmcif.c
+@@ -7,13 +7,6 @@
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License.
+- *
+- *
+- * TODO
+- *  1. DMA
+- *  2. Power management
+- *  3. Handle MMC errors better
+- *
+  */
+ 
+ /*
+@@ -67,7 +60,6 @@
+ #include <linux/module.h>
+ 
+ #define DRIVER_NAME	"sh_mmcif"
+-#define DRIVER_VERSION	"2010-04-28"
+ 
+ /* CE_CMD_SET */
+ #define CMD_MASK		0x3f000000
+-- 
+2.19.0
+
diff --git a/patches/0849-spi-sh-msiof-Use-correct-enum-for-DMA-transfer-direc.patch b/patches/0849-spi-sh-msiof-Use-correct-enum-for-DMA-transfer-direc.patch
new file mode 100644
index 00000000000000..2bd69c38ce67ae
--- /dev/null
+++ b/patches/0849-spi-sh-msiof-Use-correct-enum-for-DMA-transfer-direc.patch
@@ -0,0 +1,60 @@
+From 65fdee792519b1d2f91941b06f7bdcd2dbd42635 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 21 Mar 2018 09:07:23 +0100
+Subject: [PATCH 0849/1795] spi: sh-msiof: Use correct enum for DMA transfer
+ direction
+
+Use enum dma_transfer_direction as required by dmaengine_prep_slave_sg()
+instead of enum dma_data_direction.  This won't change behavior in
+practice as the enum values are equivalent.
+
+This fixes two warnings when building with clang:
+  drivers/spi/spi-sh-msiof.c:755:27: warning: implicit conversion from enumeration
+      type 'enum dma_data_direction' to different enumeration type
+      'enum dma_transfer_direction' [-Wenum-conversion]
+					rx->sgl, rx->nents, DMA_FROM_DEVICE,
+							    ^~~~~~~~~~~~~~~
+  drivers/spi/spi-sh-msiof.c:772:27: warning: implicit conversion from enumeration
+      type 'enum dma_data_direction' to different enumeration type
+      'enum dma_transfer_direction' [-Wenum-conversion]
+					tx->sgl, tx->nents, DMA_TO_DEVICE,
+							    ^~~~~~~~~~~~~
+
+Based on commit 768d59f5d0139a6f ("spi: rspi: use correct enum for DMA
+transfer direction").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit da779513d33575fc43a9ae87a95af6b4354cebaa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-sh-msiof.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index e607e224bb7c..c1ea7965fe27 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -739,7 +739,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
+ 	if (rx) {
+ 		ier_bits |= IER_RDREQE | IER_RDMAE;
+ 		desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
+-					p->rx_dma_addr, len, DMA_FROM_DEVICE,
++					p->rx_dma_addr, len, DMA_DEV_TO_MEM,
+ 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 		if (!desc_rx)
+ 			return -EAGAIN;
+@@ -756,7 +756,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
+ 		dma_sync_single_for_device(p->master->dma_tx->device->dev,
+ 					   p->tx_dma_addr, len, DMA_TO_DEVICE);
+ 		desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
+-					p->tx_dma_addr, len, DMA_TO_DEVICE,
++					p->tx_dma_addr, len, DMA_MEM_TO_DEV,
+ 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 		if (!desc_tx) {
+ 			ret = -EAGAIN;
+-- 
+2.19.0
+
diff --git a/patches/0850-spi-sh-msiof-Document-R-Car-M3-N-support.patch b/patches/0850-spi-sh-msiof-Document-R-Car-M3-N-support.patch
new file mode 100644
index 00000000000000..477f4650d92ba4
--- /dev/null
+++ b/patches/0850-spi-sh-msiof-Document-R-Car-M3-N-support.patch
@@ -0,0 +1,35 @@
+From 1e6c27c8ce4bb3d35bd652b5ebdd259b5360276b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 27 Mar 2018 15:04:25 +0200
+Subject: [PATCH 0850/1795] spi: sh-msiof: Document R-Car M3-N support
+
+Document support for the MSIOF module in the Renesas M3-N (r8a77965) SoC.
+
+No driver update is needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 7bb5e54515dbcef7c390506c1339bff6bf220b1c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
+index bdd83959019c..2c8b25a6830b 100644
+--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
++++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
+@@ -10,6 +10,7 @@ Required properties:
+ 			 "renesas,msiof-r8a7794" (R-Car E2)
+ 			 "renesas,msiof-r8a7795" (R-Car H3)
+ 			 "renesas,msiof-r8a7796" (R-Car M3-W)
++			 "renesas,msiof-r8a77965" (R-Car M3-N)
+ 			 "renesas,msiof-sh73a0" (SH-Mobile AG5)
+ 			 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
+ 			 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
+-- 
+2.19.0
+
diff --git a/patches/0851-dt-bindings-pinctrl-sh-pfc-Correct-SoC-family-name-f.patch b/patches/0851-dt-bindings-pinctrl-sh-pfc-Correct-SoC-family-name-f.patch
new file mode 100644
index 00000000000000..70d4a7a627933b
--- /dev/null
+++ b/patches/0851-dt-bindings-pinctrl-sh-pfc-Correct-SoC-family-name-f.patch
@@ -0,0 +1,33 @@
+From 3b12b8b634e29170e1acffd712257ab162fa5c56 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 19 Dec 2017 15:38:12 +0100
+Subject: [PATCH 0851/1795] dt-bindings: pinctrl: sh-pfc: Correct SoC family
+ name for R8A7778
+
+R8A7778 is R-Car (not R-Mobile) M1.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit edc4e74d96982ef9304dc7239a294e3e0ac2144a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt         | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index bb1790e0b176..dd64dbb4cb0e 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -15,7 +15,7 @@ Required Properties:
+     - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+     - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+     - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
+-    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
++    - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
+     - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+     - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+     - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
+-- 
+2.19.0
+
diff --git a/patches/0852-pinctrl-sh-pfc-Use-seq_puts-in-sh_pfc_pin_dbg_show.patch b/patches/0852-pinctrl-sh-pfc-Use-seq_puts-in-sh_pfc_pin_dbg_show.patch
new file mode 100644
index 00000000000000..3412ad62fee510
--- /dev/null
+++ b/patches/0852-pinctrl-sh-pfc-Use-seq_puts-in-sh_pfc_pin_dbg_show.patch
@@ -0,0 +1,36 @@
+From 1bbbf4ed1d19a041d49f7d124cbfa14a02ccbdc6 Mon Sep 17 00:00:00 2001
+From: Markus Elfring <elfring@users.sourceforge.net>
+Date: Sat, 6 Jan 2018 21:50:20 +0100
+Subject: [PATCH 0852/1795] pinctrl: sh-pfc: Use seq_puts() in
+ sh_pfc_pin_dbg_show()
+
+A string which did not contain a data format specification should be put
+into a sequence. Thus use the corresponding function "seq_puts".
+
+This issue was detected by using the Coccinelle software.
+
+Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 2580b1ceb7b0969e33e08ce17929aad3667bdd36)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pinctrl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
+index 736634aee500..70db21638901 100644
+--- a/drivers/pinctrl/sh-pfc/pinctrl.c
++++ b/drivers/pinctrl/sh-pfc/pinctrl.c
+@@ -75,7 +75,7 @@ static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ 				unsigned offset)
+ {
+-	seq_printf(s, "%s", DRV_NAME);
++	seq_puts(s, DRV_NAME);
+ }
+ 
+ #ifdef CONFIG_OF
+-- 
+2.19.0
+
diff --git a/patches/0853-pinctrl-sh-pfc-r8a77995-Add-DU-pins-groups-and-funct.patch b/patches/0853-pinctrl-sh-pfc-r8a77995-Add-DU-pins-groups-and-funct.patch
new file mode 100644
index 00000000000000..641df307bca861
--- /dev/null
+++ b/patches/0853-pinctrl-sh-pfc-r8a77995-Add-DU-pins-groups-and-funct.patch
@@ -0,0 +1,154 @@
+From ef08d9e4023b7c035424e786069c7e1c902a244b Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Thu, 15 Feb 2018 13:01:31 +0100
+Subject: [PATCH 0853/1795] pinctrl: sh-pfc: r8a77995: Add DU pins, groups and
+ function
+
+This patch adds DU pins, groups and function for the R8A77995 (D3) SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 65a90f046ba11c5b5cc5f89d732deaa8b08068e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 101 ++++++++++++++++++++++++++
+ 1 file changed, 101 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index a4927b78a17b..1d42d2534375 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1114,6 +1114,87 @@ static const unsigned int canfd1_data_mux[] = {
+ 	CANFD1_TX_MARK, CANFD1_RX_MARK,
+ };
+ 
++/* - DU --------------------------------------------------------------------- */
++static const unsigned int du_rgb666_pins[] = {
++	/* R[7:2], G[7:2], B[7:2] */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
++	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
++	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
++};
++static const unsigned int du_rgb666_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
++	DU_DR3_MARK, DU_DR2_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
++	DU_DG3_MARK, DU_DG2_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
++	DU_DB3_MARK, DU_DB2_MARK,
++};
++static const unsigned int du_rgb888_pins[] = {
++	/* R[7:0], G[7:0], B[7:0] */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
++	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
++	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
++	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),
++	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
++	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
++};
++static const unsigned int du_rgb888_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
++	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
++	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
++	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
++};
++static const unsigned int du_clk_in_1_pins[] = {
++	/* CLKIN */
++	RCAR_GP_PIN(1, 28),
++};
++static const unsigned int du_clk_in_1_mux[] = {
++	DU_DOTCLKIN1_MARK
++};
++static const unsigned int du_clk_out_0_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int du_clk_out_0_mux[] = {
++	DU_DOTCLKOUT0_MARK
++};
++static const unsigned int du_sync_pins[] = {
++	/* VSYNC, HSYNC */
++	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
++};
++static const unsigned int du_sync_mux[] = {
++	DU_VSYNC_MARK, DU_HSYNC_MARK
++};
++static const unsigned int du_disp_cde_pins[] = {
++	/* DISP_CDE */
++	RCAR_GP_PIN(1, 28),
++};
++static const unsigned int du_disp_cde_mux[] = {
++	DU_DISP_CDE_MARK,
++};
++static const unsigned int du_cde_pins[] = {
++	/* CDE */
++	RCAR_GP_PIN(1, 29),
++};
++static const unsigned int du_cde_mux[] = {
++	DU_CDE_MARK,
++};
++static const unsigned int du_disp_pins[] = {
++	/* DISP */
++	RCAR_GP_PIN(1, 27),
++};
++static const unsigned int du_disp_mux[] = {
++	DU_DISP_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c0_pins[] = {
+ 	/* SCL, SDA */
+@@ -1568,6 +1649,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(can_clk),
+ 	SH_PFC_PIN_GROUP(canfd0_data),
+ 	SH_PFC_PIN_GROUP(canfd1_data),
++	SH_PFC_PIN_GROUP(du_rgb666),
++	SH_PFC_PIN_GROUP(du_rgb888),
++	SH_PFC_PIN_GROUP(du_clk_in_1),
++	SH_PFC_PIN_GROUP(du_clk_out_0),
++	SH_PFC_PIN_GROUP(du_sync),
++	SH_PFC_PIN_GROUP(du_disp_cde),
++	SH_PFC_PIN_GROUP(du_cde),
++	SH_PFC_PIN_GROUP(du_disp),
+ 	SH_PFC_PIN_GROUP(i2c0),
+ 	SH_PFC_PIN_GROUP(i2c1),
+ 	SH_PFC_PIN_GROUP(i2c2_a),
+@@ -1664,6 +1753,17 @@ static const char * const canfd1_groups[] = {
+ 	"canfd1_data",
+ };
+ 
++static const char * const du_groups[] = {
++	"du_rgb666",
++	"du_rgb888",
++	"du_clk_in_1",
++	"du_clk_out_0",
++	"du_sync",
++	"du_disp_cde",
++	"du_cde",
++	"du_disp",
++};
++
+ static const char * const i2c0_groups[] = {
+ 	"i2c0",
+ };
+@@ -1779,6 +1879,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(can_clk),
+ 	SH_PFC_FUNCTION(canfd0),
+ 	SH_PFC_FUNCTION(canfd1),
++	SH_PFC_FUNCTION(du),
+ 	SH_PFC_FUNCTION(i2c0),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+-- 
+2.19.0
+
diff --git a/patches/0854-pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi.patch b/patches/0854-pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi.patch
new file mode 100644
index 00000000000000..2c341d180f1445
--- /dev/null
+++ b/patches/0854-pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi.patch
@@ -0,0 +1,193 @@
+From 6b0636f3855c97e915aed8c96d4046dc36a03c52 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:02 +0100
+Subject: [PATCH 0854/1795] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin
+ assignment for SSI pins group
+
+This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
+for SSI pins group.
+
+This is a correction because MOD_SEL register specification for R8A7795
+ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 740a4a3aa76ed46a425909ba34cc82c4ddb91252)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 ++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 35951e7b89d2..4faf759a4c17 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1,7 +1,7 @@
+ /*
+  * R8A7795 ES2.0+ processor support - PFC hardware block.
+  *
+- * Copyright (C) 2015-2016 Renesas Electronics Corporation
++ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -472,7 +472,7 @@ FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
+ #define MOD_SEL1_26		FM(SEL_TIMER_TMU1_0)	FM(SEL_TIMER_TMU1_1)
+ #define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
+ #define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
+-#define MOD_SEL1_20		FM(SEL_SSI_0)		FM(SEL_SSI_1)
++#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
+ #define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
+ #define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
+ #define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
+@@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
+ 	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
+ 	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADG_B_0),
+-	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
+ 	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
+ 	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
+ 	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
+@@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
+ 	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
+-	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
+ 	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
+ 	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
+ 	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
+ 
+ 	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
+ 	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
+-	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
+ 	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
+ 	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
+ 	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
+@@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
+ 	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
+ 	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
+-	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
+ 	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
+ 	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
+ 	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
+@@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
+ 	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
+ 	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
+-	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
+ 	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
+ 	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
+ 	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
+@@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
+ 	PINMUX_IPSR_GPSR(IP14_3_0,	NFWP_N_A),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADG_A_2),
+-	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
+ 	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU1_1),
+@@ -1274,7 +1274,7 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
+ 	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
+ 	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADG_C_0),
+-	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
+ 	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
+ 	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
+ 	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
+@@ -1302,10 +1302,10 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
+ 
+ 	/* IPSR15 */
+-	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
+ 
+-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI_0),
+-	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
+ 	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
+@@ -1394,11 +1394,11 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
+ 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
+ 
+-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
+ 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
+ 	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
+ 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
+-	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
+ 	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
+ 	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
+ 	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
+@@ -1430,7 +1430,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
+ 	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
+-	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
+ 	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
+ 	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
+ 	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
+@@ -1440,7 +1440,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
+ 	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
+-	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI_0),
++	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
+ 	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
+ 	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
+ 	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
+@@ -1450,7 +1450,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
+ 	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
+-	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
+ 	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
+ 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
+ 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
+@@ -1462,7 +1462,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
+ 	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
+-	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
+ 	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
+ 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
+ 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
+@@ -1473,7 +1473,7 @@ static const u16 pinmux_data[] = {
+ 	/* IPSR18 */
+ 	PINMUX_IPSR_GPSR(IP18_3_0,	USB2_CH3_PWEN),
+ 	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
+-	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
+ 	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
+ 	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
+ 	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
+@@ -1483,7 +1483,7 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP18_7_4,	USB2_CH3_OVC),
+ 	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
+-	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI_1),
++	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
+ 	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
+ 	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
+ 	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
+-- 
+2.19.0
+
diff --git a/patches/0855-pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register.patch b/patches/0855-pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register.patch
new file mode 100644
index 00000000000000..06ea780763962a
--- /dev/null
+++ b/patches/0855-pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register.patch
@@ -0,0 +1,113 @@
+From a87df1deaa0a212bc590fd597d8da78acaf3c264 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:04 +0100
+Subject: [PATCH 0855/1795] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL
+ register pin assignment for NDFC pins group
+
+This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
+NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
+definition name to SEL_NDFC.
+
+This is a correction to the incorrect implementation of MOD_SEL register
+pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
+User's Manual Rev.0.53E.
+
+Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8b446c4d388dc25d325f63a6642391f00ec44c4c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 74ee48303156..48f371ed352e 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -502,7 +502,7 @@ FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
+ #define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
+ #define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
+ #define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
+-#define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
++#define MOD_SEL2_22		FM(SEL_NDFC_0)		FM(SEL_NDFC_1)
+ #define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
+ #define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
+ #define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
+@@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
+ 	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
+-	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDFC_1),
+ 	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
+ 	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
+ 	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
+ 	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
+-	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDFC_1),
+ 	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
+ 	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
+ 	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
+ 	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
+-	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDFC_1),
+ 	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
+ 	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
+ 	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
+ 	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
+-	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
++	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDFC_1),
+ 	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
+ 	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
+ 	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
+ 	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
+-	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
++	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDFC_1),
+ 	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
+ 	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
+ 
+@@ -1110,16 +1110,20 @@ static const u16 pinmux_data[] = {
+ 	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
+ 
+ 	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
++	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDFC_0),
+ 	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
+ 	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
+ 
+ 	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
++	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDFC_0),
+ 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP11_19_16,	SD1_CD),
++	PINMUX_IPSR_MSEL(IP11_19_16,	NFRB_N_A,		SEL_NDFC_0),
+ 	PINMUX_IPSR_MSEL(IP11_19_16,	SIM0_CLK_B,		SEL_SIMCARD_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP11_23_20,	SD1_WP),
++	PINMUX_IPSR_MSEL(IP11_23_20,	NFCE_N_A,		SEL_NDFC_0),
+ 	PINMUX_IPSR_MSEL(IP11_23_20,	SIM0_D_B,		SEL_SIMCARD_1),
+ 
+ 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
+@@ -1263,7 +1267,7 @@ static const u16 pinmux_data[] = {
+ 	/* IPSR14 */
+ 	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
+-	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
++	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDFC_0),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADG_A_2),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
+ 	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
+-- 
+2.19.0
+
diff --git a/patches/0856-pinctrl-sh-pfc-r8a7795-Add-HDMI-pins-groups-and-func.patch b/patches/0856-pinctrl-sh-pfc-r8a7795-Add-HDMI-pins-groups-and-func.patch
new file mode 100644
index 00000000000000..a4f235485de4b3
--- /dev/null
+++ b/patches/0856-pinctrl-sh-pfc-r8a7795-Add-HDMI-pins-groups-and-func.patch
@@ -0,0 +1,84 @@
+From 9c6659165e808445ca775b3349c0cfaa6cb42c9f Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:40 +0100
+Subject: [PATCH 0856/1795] pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and
+ functions
+
+This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[uli: fixed typo in comment]
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 5722110e2f8ecf1cf8dac7b0c3c864c5fcf5491f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 4faf759a4c17..51afa1ce07fc 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2127,6 +2127,22 @@ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
+ 
++/* - HDMI ------------------------------------------------------------------- */
++static const unsigned int hdmi0_cec_pins[] = {
++	/* HDMI0_CEC */
++	RCAR_GP_PIN(7, 2),
++};
++static const unsigned int hdmi0_cec_mux[] = {
++	HDMI0_CEC_MARK,
++};
++static const unsigned int hdmi1_cec_pins[] = {
++	/* HDMI1_CEC */
++	RCAR_GP_PIN(7, 3),
++};
++static const unsigned int hdmi1_cec_mux[] = {
++	HDMI1_CEC_MARK,
++};
++
+ /* - HSCIF0 ----------------------------------------------------------------- */
+ static const unsigned int hscif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -3954,6 +3970,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hdmi0_cec),
++	SH_PFC_PIN_GROUP(hdmi1_cec),
+ 	SH_PFC_PIN_GROUP(hscif0_data),
+ 	SH_PFC_PIN_GROUP(hscif0_clk),
+ 	SH_PFC_PIN_GROUP(hscif0_ctrl),
+@@ -4304,6 +4322,14 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const hdmi0_groups[] = {
++	"hdmi0_cec",
++};
++
++static const char * const hdmi1_groups[] = {
++	"hdmi1_cec",
++};
++
+ static const char * const hscif0_groups[] = {
+ 	"hscif0_data",
+ 	"hscif0_clk",
+@@ -4671,6 +4697,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(drif2),
+ 	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hdmi0),
++	SH_PFC_FUNCTION(hdmi1),
+ 	SH_PFC_FUNCTION(hscif0),
+ 	SH_PFC_FUNCTION(hscif1),
+ 	SH_PFC_FUNCTION(hscif2),
+-- 
+2.19.0
+
diff --git a/patches/0857-pinctrl-sh-pfc-r8a7795-es1-Add-HDMI-pins-groups-and-.patch b/patches/0857-pinctrl-sh-pfc-r8a7795-es1-Add-HDMI-pins-groups-and-.patch
new file mode 100644
index 00000000000000..de31ad442e5a22
--- /dev/null
+++ b/patches/0857-pinctrl-sh-pfc-r8a7795-es1-Add-HDMI-pins-groups-and-.patch
@@ -0,0 +1,94 @@
+From 72e10df55c1cdf7404bafdd3ef976e4e2def6a58 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:41 +0100
+Subject: [PATCH 0857/1795] pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups
+ and functions
+
+This patch adds HDMI0 CEC pin, group and function to
+the R8A7795 ES1.x SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[uli: fixed typo in comment]
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 12404148598d7b1829b5e36e29facc1c1d07c4bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 30 +++++++++++++++++++++++-
+ 1 file changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 292e35d4d2f4..81bfcafdcd8a 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -1,7 +1,7 @@
+ /*
+  * R8A7795 ES1.x processor support - PFC hardware block.
+  *
+- * Copyright (C) 2015  Renesas Electronics Corporation
++ * Copyright (C) 2015-2017  Renesas Electronics Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -2067,6 +2067,22 @@ static const unsigned int du_disp_pins[] = {
+ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
++/* - HDMI ------------------------------------------------------------------- */
++static const unsigned int hdmi0_cec_pins[] = {
++	/* HDMI0_CEC */
++	RCAR_GP_PIN(7, 2),
++};
++static const unsigned int hdmi0_cec_mux[] = {
++	HDMI0_CEC_MARK,
++};
++static const unsigned int hdmi1_cec_pins[] = {
++	/* HDMI1_CEC */
++	RCAR_GP_PIN(7, 3),
++};
++static const unsigned int hdmi1_cec_mux[] = {
++	HDMI1_CEC_MARK,
++};
++
+ /* - HSCIF0 ----------------------------------------------------------------- */
+ static const unsigned int hscif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -3865,6 +3881,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hdmi0_cec),
++	SH_PFC_PIN_GROUP(hdmi1_cec),
+ 	SH_PFC_PIN_GROUP(hscif0_data),
+ 	SH_PFC_PIN_GROUP(hscif0_clk),
+ 	SH_PFC_PIN_GROUP(hscif0_ctrl),
+@@ -4210,6 +4228,14 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const hdmi0_groups[] = {
++	"hdmi0_cec",
++};
++
++static const char * const hdmi1_groups[] = {
++	"hdmi1_cec",
++};
++
+ static const char * const hscif0_groups[] = {
+ 	"hscif0_data",
+ 	"hscif0_clk",
+@@ -4578,6 +4604,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(drif2),
+ 	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hdmi0),
++	SH_PFC_FUNCTION(hdmi1),
+ 	SH_PFC_FUNCTION(hscif0),
+ 	SH_PFC_FUNCTION(hscif1),
+ 	SH_PFC_FUNCTION(hscif2),
+-- 
+2.19.0
+
diff --git a/patches/0858-pinctrl-sh-pfc-r8a7796-Add-HDMI-pins-groups-and-func.patch b/patches/0858-pinctrl-sh-pfc-r8a7796-Add-HDMI-pins-groups-and-func.patch
new file mode 100644
index 00000000000000..0f08d2de52cac1
--- /dev/null
+++ b/patches/0858-pinctrl-sh-pfc-r8a7796-Add-HDMI-pins-groups-and-func.patch
@@ -0,0 +1,69 @@
+From 666758a675e362b41c743033c0da3ae883bd585d Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:42 +0100
+Subject: [PATCH 0858/1795] pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and
+ functions
+
+This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 71c236adf037543284990e22f0241abec57cf860)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 48f371ed352e..8d1046262ed4 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -2133,6 +2133,15 @@ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
+ 
++/* - HDMI ------------------------------------------------------------------- */
++static const unsigned int hdmi0_cec_pins[] = {
++	/* HDMI0_CEC */
++	RCAR_GP_PIN(7, 2),
++};
++static const unsigned int hdmi0_cec_mux[] = {
++	HDMI0_CEC_MARK,
++};
++
+ /* - HSCIF0 ----------------------------------------------------------------- */
+ static const unsigned int hscif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -3930,6 +3939,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hdmi0_cec),
+ 	SH_PFC_PIN_GROUP(hscif0_data),
+ 	SH_PFC_PIN_GROUP(hscif0_clk),
+ 	SH_PFC_PIN_GROUP(hscif0_ctrl),
+@@ -4276,6 +4286,10 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const hdmi0_groups[] = {
++	"hdmi0_cec",
++};
++
+ static const char * const hscif0_groups[] = {
+ 	"hscif0_data",
+ 	"hscif0_clk",
+@@ -4630,6 +4644,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(drif2),
+ 	SH_PFC_FUNCTION(drif3),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hdmi0),
+ 	SH_PFC_FUNCTION(hscif0),
+ 	SH_PFC_FUNCTION(hscif1),
+ 	SH_PFC_FUNCTION(hscif2),
+-- 
+2.19.0
+
diff --git a/patches/0859-pinctrl-sh-pfc-r8a7795-Add-TMU-pins-groups-and-funct.patch b/patches/0859-pinctrl-sh-pfc-r8a7795-Add-TMU-pins-groups-and-funct.patch
new file mode 100644
index 00000000000000..60e5a58b641b5a
--- /dev/null
+++ b/patches/0859-pinctrl-sh-pfc-r8a7795-Add-TMU-pins-groups-and-funct.patch
@@ -0,0 +1,97 @@
+From 4aee30ddff7423764e2b44bbc25a19e5af160d58 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:26:09 +0100
+Subject: [PATCH 0859/1795] pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and
+ functions
+
+This patch adds TMU TCLK{1,2} pins, groups and functions to
+the R8A7795 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit edcc14c82dd5d3261c540da23d2a675db434dd09)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 ++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 51afa1ce07fc..4898676ad79b 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3855,6 +3855,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
+ 
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 28),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+@@ -4207,6 +4237,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi9_data_b),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
+@@ -4664,6 +4698,13 @@ static const char * const ssi_groups[] = {
+ 	"ssi9_ctrl_b",
+ };
+ 
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -4732,6 +4773,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(sdhi2),
+ 	SH_PFC_FUNCTION(sdhi3),
+ 	SH_PFC_FUNCTION(ssi),
++	SH_PFC_FUNCTION(tmu),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
+-- 
+2.19.0
+
diff --git a/patches/0860-pinctrl-sh-pfc-r8a7795-es1-Add-TMU-pins-groups-and-f.patch b/patches/0860-pinctrl-sh-pfc-r8a7795-es1-Add-TMU-pins-groups-and-f.patch
new file mode 100644
index 00000000000000..9ac9b02ed79093
--- /dev/null
+++ b/patches/0860-pinctrl-sh-pfc-r8a7795-es1-Add-TMU-pins-groups-and-f.patch
@@ -0,0 +1,97 @@
+From c840151db4ba209a9920cce4cc6c5c7fb85da187 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:26:10 +0100
+Subject: [PATCH 0860/1795] pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups
+ and functions
+
+This patch adds TMU TCLK{1,2} pins, groups and functions to
+the R8A7795 ES1.x SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f0442cf27c5b6d7f4f666dcdc56cbd5396bbe994)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 42 ++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 81bfcafdcd8a..0cf0b8512482 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -3766,6 +3766,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
+ 
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 28),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+@@ -4113,6 +4143,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi9_data_b),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb2),
+@@ -4571,6 +4605,13 @@ static const char * const ssi_groups[] = {
+ 	"ssi9_ctrl_b",
+ };
+ 
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -4641,6 +4682,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(sdhi2),
+ 	SH_PFC_FUNCTION(sdhi3),
+ 	SH_PFC_FUNCTION(ssi),
++	SH_PFC_FUNCTION(tmu),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb2),
+-- 
+2.19.0
+
diff --git a/patches/0861-pinctrl-sh-pfc-r8a7796-Add-TMU-pins-groups-and-funct.patch b/patches/0861-pinctrl-sh-pfc-r8a7796-Add-TMU-pins-groups-and-funct.patch
new file mode 100644
index 00000000000000..7ea118f13e8b24
--- /dev/null
+++ b/patches/0861-pinctrl-sh-pfc-r8a7796-Add-TMU-pins-groups-and-funct.patch
@@ -0,0 +1,97 @@
+From fb684239dcdd1677a63d0b90e6158a9c931e3b24 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:26:11 +0100
+Subject: [PATCH 0861/1795] pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and
+ functions
+
+This patch adds TMU TCLK{1,2} pins, groups and functions to
+the R8A7796 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 74965de1cacc6c13c31ef37e6548e553e05440d4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 42 ++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 8d1046262ed4..ad4a7883518a 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -3840,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
+ 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+ };
+ 
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK */
++	RCAR_GP_PIN(6, 28),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+@@ -4173,6 +4203,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi9_data_b),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_a),
+ 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb30),
+@@ -4619,6 +4653,13 @@ static const char * const ssi_groups[] = {
+ 	"ssi9_ctrl_b",
+ };
+ 
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -4677,6 +4718,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(sdhi2),
+ 	SH_PFC_FUNCTION(sdhi3),
+ 	SH_PFC_FUNCTION(ssi),
++	SH_PFC_FUNCTION(tmu),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb30),
+-- 
+2.19.0
+
diff --git a/patches/0862-pinctrl-sh-pfc-Initial-R-Car-M3-N-support.patch b/patches/0862-pinctrl-sh-pfc-Initial-R-Car-M3-N-support.patch
new file mode 100644
index 00000000000000..f3e68085aac4a6
--- /dev/null
+++ b/patches/0862-pinctrl-sh-pfc-Initial-R-Car-M3-N-support.patch
@@ -0,0 +1,2828 @@
+From db3cc2c1f5a55dcdb9c5452af083e3132ba27ec4 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:07 +0100
+Subject: [PATCH 0862/1795] pinctrl: sh-pfc: Initial R-Car M3-N support
+
+Add initial PFC support for R-Car M3-N (r8a77965) SoC.
+No groups or functions defined, just pin and registers enumeration.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 490e687eb8b274b5d942e1cf61fb01392b86ecce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/pinctrl/renesas,pfc-pinctrl.txt  |    1 +
+ drivers/pinctrl/sh-pfc/Kconfig                |    5 +
+ drivers/pinctrl/sh-pfc/Makefile               |    1 +
+ drivers/pinctrl/sh-pfc/core.c                 |    6 +
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c         | 2726 +++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h               |    1 +
+ 6 files changed, 2740 insertions(+)
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index dd64dbb4cb0e..bd5370a71666 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -24,6 +24,7 @@ Required Properties:
+     - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
+     - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
+     - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
++    - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
+     - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
+     - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
+     - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index 4ed3761418f9..0621cb51c016 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
+         depends on ARCH_R8A7796
+         select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A77965
++        def_bool y
++        depends on ARCH_R8A77965
++        select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_R8A77970
+ 	def_bool y
+ 	depends on ARCH_R8A77970
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index 22e758ce1fc2..05b4379f0c98 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794)	+= pfc-r8a7794.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795-es1.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
++obj-$(CONFIG_PINCTRL_PFC_R8A77965)	+= pfc-r8a77965.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77970)	+= pfc-r8a77970.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index e9eb7a7c6fac..7461af941659 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 		.data = &r8a7796_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A77965
++	{
++		.compatible = "renesas,pfc-r8a77965",
++		.data = &r8a77965_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_R8A77970
+ 	{
+ 		.compatible = "renesas,pfc-r8a77970",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+new file mode 100644
+index 000000000000..3583e2018534
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -0,0 +1,2726 @@
++// SPDX-License-Identifier: GPL-2.
++/*
++ * R8A77965 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ * Copyright (C) 2016 Renesas Electronics Corp.
++ *
++ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++ *
++ * R-Car Gen3 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2015  Renesas Electronics Corporation
++ */
++
++#include <linux/kernel.h>
++
++#include "core.h"
++#include "sh_pfc.h"
++
++#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
++		   SH_PFC_PIN_CFG_PULL_UP | \
++		   SH_PFC_PIN_CFG_PULL_DOWN)
++
++#define CPU_ALL_PORT(fn, sfx)						\
++	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
++	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
++	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
++	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
++/*
++ * F_() : just information
++ * FM() : macro for FN_xxx / xxx_MARK
++ */
++
++/* GPSR0 */
++#define GPSR0_15	F_(D15,			IP7_11_8)
++#define GPSR0_14	F_(D14,			IP7_7_4)
++#define GPSR0_13	F_(D13,			IP7_3_0)
++#define GPSR0_12	F_(D12,			IP6_31_28)
++#define GPSR0_11	F_(D11,			IP6_27_24)
++#define GPSR0_10	F_(D10,			IP6_23_20)
++#define GPSR0_9		F_(D9,			IP6_19_16)
++#define GPSR0_8		F_(D8,			IP6_15_12)
++#define GPSR0_7		F_(D7,			IP6_11_8)
++#define GPSR0_6		F_(D6,			IP6_7_4)
++#define GPSR0_5		F_(D5,			IP6_3_0)
++#define GPSR0_4		F_(D4,			IP5_31_28)
++#define GPSR0_3		F_(D3,			IP5_27_24)
++#define GPSR0_2		F_(D2,			IP5_23_20)
++#define GPSR0_1		F_(D1,			IP5_19_16)
++#define GPSR0_0		F_(D0,			IP5_15_12)
++
++/* GPSR1 */
++#define GPSR1_28	FM(CLKOUT)
++#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
++#define GPSR1_26	F_(WE1_N,		IP5_7_4)
++#define GPSR1_25	F_(WE0_N,		IP5_3_0)
++#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
++#define GPSR1_23	F_(RD_N,		IP4_27_24)
++#define GPSR1_22	F_(BS_N,		IP4_23_20)
++#define GPSR1_21	F_(CS1_N,		IP4_19_16)
++#define GPSR1_20	F_(CS0_N,		IP4_15_12)
++#define GPSR1_19	F_(A19,			IP4_11_8)
++#define GPSR1_18	F_(A18,			IP4_7_4)
++#define GPSR1_17	F_(A17,			IP4_3_0)
++#define GPSR1_16	F_(A16,			IP3_31_28)
++#define GPSR1_15	F_(A15,			IP3_27_24)
++#define GPSR1_14	F_(A14,			IP3_23_20)
++#define GPSR1_13	F_(A13,			IP3_19_16)
++#define GPSR1_12	F_(A12,			IP3_15_12)
++#define GPSR1_11	F_(A11,			IP3_11_8)
++#define GPSR1_10	F_(A10,			IP3_7_4)
++#define GPSR1_9		F_(A9,			IP3_3_0)
++#define GPSR1_8		F_(A8,			IP2_31_28)
++#define GPSR1_7		F_(A7,			IP2_27_24)
++#define GPSR1_6		F_(A6,			IP2_23_20)
++#define GPSR1_5		F_(A5,			IP2_19_16)
++#define GPSR1_4		F_(A4,			IP2_15_12)
++#define GPSR1_3		F_(A3,			IP2_11_8)
++#define GPSR1_2		F_(A2,			IP2_7_4)
++#define GPSR1_1		F_(A1,			IP2_3_0)
++#define GPSR1_0		F_(A0,			IP1_31_28)
++
++/* GPSR2 */
++#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
++#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
++#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
++#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
++#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
++#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
++#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
++#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
++#define GPSR2_6		F_(PWM0,		IP1_19_16)
++#define GPSR2_5		F_(IRQ5,		IP1_15_12)
++#define GPSR2_4		F_(IRQ4,		IP1_11_8)
++#define GPSR2_3		F_(IRQ3,		IP1_7_4)
++#define GPSR2_2		F_(IRQ2,		IP1_3_0)
++#define GPSR2_1		F_(IRQ1,		IP0_31_28)
++#define GPSR2_0		F_(IRQ0,		IP0_27_24)
++
++/* GPSR3 */
++#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
++#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
++#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
++#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
++#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
++#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
++#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
++#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
++#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
++#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
++#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
++#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
++#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
++#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
++#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
++#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
++
++/* GPSR4 */
++#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
++#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
++#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
++#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
++#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
++#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
++#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
++#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
++#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
++#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
++#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
++#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
++#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
++#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
++#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
++#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
++#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
++#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
++
++/* GPSR5 */
++#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
++#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
++#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
++#define GPSR5_22	FM(MSIOF0_RXD)
++#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
++#define GPSR5_20	FM(MSIOF0_TXD)
++#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
++#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
++#define GPSR5_17	FM(MSIOF0_SCK)
++#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
++#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
++#define GPSR5_14	F_(HTX0,		IP13_19_16)
++#define GPSR5_13	F_(HRX0,		IP13_15_12)
++#define GPSR5_12	F_(HSCK0,		IP13_11_8)
++#define GPSR5_11	F_(RX2_A,		IP13_7_4)
++#define GPSR5_10	F_(TX2_A,		IP13_3_0)
++#define GPSR5_9		F_(SCK2,		IP12_31_28)
++#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
++#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
++#define GPSR5_6		F_(TX1_A,		IP12_19_16)
++#define GPSR5_5		F_(RX1_A,		IP12_15_12)
++#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
++#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
++#define GPSR5_2		F_(TX0,			IP12_3_0)
++#define GPSR5_1		F_(RX0,			IP11_31_28)
++#define GPSR5_0		F_(SCK0,		IP11_27_24)
++
++/* GPSR6 */
++#define GPSR6_31	F_(GP6_31,		IP18_7_4)
++#define GPSR6_30	F_(GP6_30,		IP18_3_0)
++#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
++#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
++#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
++#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
++#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
++#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
++#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
++#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
++#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
++#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
++#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
++#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
++#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
++#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
++#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
++#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
++#define GPSR6_13	FM(SSI_SDATA5)
++#define GPSR6_12	FM(SSI_WS5)
++#define GPSR6_11	FM(SSI_SCK5)
++#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
++#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
++#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
++#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
++#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
++#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
++#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
++#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
++#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
++#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
++#define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
++
++/* GPSR7 */
++#define GPSR7_3		FM(GP7_03)
++#define GPSR7_2		FM(HDMI0_CEC)
++#define GPSR7_1		FM(AVS2)
++#define GPSR7_0		FM(AVS1)
++
++
++/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
++#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
++#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
++#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
++#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
++#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
++#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(CC5_OSCOUT)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
++#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
++#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
++#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
++#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
++#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
++#define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
++
++#define PINMUX_GPSR	\
++\
++												GPSR6_31 \
++												GPSR6_30 \
++												GPSR6_29 \
++		GPSR1_28									GPSR6_28 \
++		GPSR1_27									GPSR6_27 \
++		GPSR1_26									GPSR6_26 \
++		GPSR1_25							GPSR5_25	GPSR6_25 \
++		GPSR1_24							GPSR5_24	GPSR6_24 \
++		GPSR1_23							GPSR5_23	GPSR6_23 \
++		GPSR1_22							GPSR5_22	GPSR6_22 \
++		GPSR1_21							GPSR5_21	GPSR6_21 \
++		GPSR1_20							GPSR5_20	GPSR6_20 \
++		GPSR1_19							GPSR5_19	GPSR6_19 \
++		GPSR1_18							GPSR5_18	GPSR6_18 \
++		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
++		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
++GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
++GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
++GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
++GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
++GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
++GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
++GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
++GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
++GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
++GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
++GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
++GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
++GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
++GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
++GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
++GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
++
++#define PINMUX_IPSR				\
++\
++FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
++FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
++FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
++FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
++FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
++FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
++FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
++FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
++\
++FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
++FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
++FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
++FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
++FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
++FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
++FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
++FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
++\
++FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
++FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
++FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
++FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
++FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
++FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
++FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
++FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
++\
++FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
++FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
++FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
++FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
++FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
++FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
++FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
++FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
++\
++FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
++FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
++FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
++FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
++FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
++FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
++FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
++FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
++
++/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
++#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
++#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
++#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
++#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
++#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
++#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
++#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
++#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
++#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
++#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
++#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
++#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
++#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
++#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
++#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
++#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
++#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
++#define MOD_SEL0_4_3		FM(SEL_ADG_A_0)		FM(SEL_ADG_A_1)		FM(SEL_ADG_A_2)		FM(SEL_ADG_A_3)
++
++/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
++#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
++#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
++#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
++#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
++#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
++#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
++#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
++#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
++#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
++#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
++#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
++#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
++#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
++#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
++#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
++#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
++#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
++#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
++#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
++#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
++#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
++#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
++
++/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
++#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
++#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
++#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
++#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
++#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
++#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
++#define MOD_SEL2_22		FM(SEL_NDFC_0)		FM(SEL_NDFC_1)
++#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
++#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
++#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
++#define MOD_SEL2_18		FM(SEL_ADG_B_0)		FM(SEL_ADG_B_1)
++#define MOD_SEL2_17		FM(SEL_ADG_C_0)		FM(SEL_ADG_C_1)
++#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
++
++#define PINMUX_MOD_SELS	\
++\
++MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
++						MOD_SEL2_30 \
++			MOD_SEL1_29_28_27	MOD_SEL2_29 \
++MOD_SEL0_28_27					MOD_SEL2_28_27 \
++MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
++			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
++MOD_SEL0_23		MOD_SEL1_23_22_21 \
++MOD_SEL0_22					MOD_SEL2_22 \
++MOD_SEL0_21					MOD_SEL2_21 \
++MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
++MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
++MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
++						MOD_SEL2_17 \
++MOD_SEL0_16		MOD_SEL1_16 \
++			MOD_SEL1_15_14 \
++MOD_SEL0_14_13 \
++			MOD_SEL1_13 \
++MOD_SEL0_12		MOD_SEL1_12 \
++MOD_SEL0_11		MOD_SEL1_11 \
++MOD_SEL0_10		MOD_SEL1_10 \
++MOD_SEL0_9_8		MOD_SEL1_9 \
++MOD_SEL0_7_6 \
++			MOD_SEL1_6 \
++MOD_SEL0_5		MOD_SEL1_5 \
++MOD_SEL0_4_3		MOD_SEL1_4 \
++			MOD_SEL1_3 \
++			MOD_SEL1_2 \
++			MOD_SEL1_1 \
++			MOD_SEL1_0		MOD_SEL2_0
++
++/*
++ * These pins are not able to be muxed but have other properties
++ * that can be set, such as drive-strength or pull-up/pull-down enable.
++ */
++#define PINMUX_STATIC \
++	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
++	FM(QSPI0_IO2) FM(QSPI0_IO3) \
++	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
++	FM(QSPI1_IO2) FM(QSPI1_IO3) \
++	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
++	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
++	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
++	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
++	FM(PRESETOUT) \
++	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
++	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++#define F_(x, y)
++#define FM(x)	FN_##x,
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_FUNCTION_END,
++#undef F_
++#undef FM
++
++#define F_(x, y)
++#define FM(x)	x##_MARK,
++	PINMUX_MARK_BEGIN,
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_STATIC
++	PINMUX_MARK_END,
++#undef F_
++#undef FM
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(),
++
++	PINMUX_SINGLE(AVS1),
++	PINMUX_SINGLE(AVS2),
++	PINMUX_SINGLE(CLKOUT),
++	PINMUX_SINGLE(GP7_03),
++	PINMUX_SINGLE(HDMI0_CEC),
++	PINMUX_SINGLE(MSIOF0_RXD),
++	PINMUX_SINGLE(MSIOF0_SCK),
++	PINMUX_SINGLE(MSIOF0_TXD),
++	PINMUX_SINGLE(SSI_SCK5),
++	PINMUX_SINGLE(SSI_SDATA5),
++	PINMUX_SINGLE(SSI_WS5),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
++	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
++
++	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
++	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
++	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
++	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
++	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
++
++	PINMUX_IPSR_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	SEL_ETHERAVB_0),
++	PINMUX_IPSR_MSEL(IP0_19_16,	MSIOF2_RXD_C,		SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP0_19_16,	CTS4_N_A,		SEL_SCIF4_0),
++
++	PINMUX_IPSR_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	SEL_ETHERAVB_0),
++	PINMUX_IPSR_MSEL(IP0_23_20,	MSIOF2_TXD_C,		SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_A,		SEL_SCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
++	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
++	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
++	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
++	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
++	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
++
++	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
++	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
++	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
++	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
++	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
++	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
++	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
++	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
++	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
++
++	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
++	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
++	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
++	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
++	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
++
++	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
++	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
++	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
++	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
++	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
++
++	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
++	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
++	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
++	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
++	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
++	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
++
++	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
++	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
++	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
++
++	PINMUX_IPSR_MSEL(IP1_23_20,	PWM1_A,			SEL_PWM1_0),
++	PINMUX_IPSR_MSEL(IP1_23_20,	HRX3_D,			SEL_HSCIF3_3),
++	PINMUX_IPSR_MSEL(IP1_23_20,	VI4_DATA7_B,		SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP1_23_20,	IERX_B,			SEL_IEBUS_1),
++
++	PINMUX_IPSR_MSEL(IP1_27_24,	PWM2_A,			SEL_PWM2_0),
++	PINMUX_IPSR_MSEL(IP1_27_24,	HTX3_D,			SEL_HSCIF3_3),
++	PINMUX_IPSR_MSEL(IP1_27_24,	IETX_B,			SEL_IEBUS_1),
++
++	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
++	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
++	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
++	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
++	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
++	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
++	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
++	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
++	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
++
++	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
++	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
++	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
++	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
++	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
++
++	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
++	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
++	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
++	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
++	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
++
++	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
++	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
++	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
++	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
++	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
++
++	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
++	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
++	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
++	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
++	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
++	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
++
++	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
++	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
++	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
++	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
++	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
++
++	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
++	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
++	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
++	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
++	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
++
++	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
++	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
++	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
++	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
++	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
++	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
++	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
++
++	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
++	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
++
++	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
++	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
++	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
++	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
++	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
++	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
++	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
++	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
++
++	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
++	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
++	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
++	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
++	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
++	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
++
++	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
++	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
++	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
++	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
++	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
++	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
++
++	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
++	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
++	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
++	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
++	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
++	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
++
++	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
++	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
++	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
++	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
++	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
++	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
++
++	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
++	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
++	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
++	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
++	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
++	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
++
++	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
++	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
++	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
++
++	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
++	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
++	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
++	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
++
++	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
++	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
++
++	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
++	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
++	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
++
++	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
++	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
++	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
++	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
++	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
++	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
++	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
++	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
++
++	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
++	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
++	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
++	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
++	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
++
++	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
++	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
++	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
++	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
++	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
++	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
++	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
++	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
++	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
++	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
++	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
++
++	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
++	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
++	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
++	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
++	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
++	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
++	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
++	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
++
++	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
++	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
++	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
++	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
++
++	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
++	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
++	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
++
++	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
++	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
++	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
++
++	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
++	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
++	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
++
++	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
++	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
++	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
++
++	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
++	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
++	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
++	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
++	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
++
++	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
++	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
++	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
++
++	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
++	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
++	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
++
++	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
++	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
++	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
++
++	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
++	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
++	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
++
++	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
++	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
++	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
++	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
++	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
++	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
++
++	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
++	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
++	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
++	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
++	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
++	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
++
++	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
++	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
++	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
++	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
++	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
++	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
++
++	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
++	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
++	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
++	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
++
++	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
++	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
++	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
++	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
++	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
++	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
++
++	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
++	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
++
++	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
++	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
++
++	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
++	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
++	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
++
++	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
++	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
++	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
++
++	/* IPSR8 */
++	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
++	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
++	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
++
++	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
++	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
++	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
++	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
++
++	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
++	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
++
++	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
++	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDFC_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
++	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
++
++	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
++	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
++	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDFC_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
++
++	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
++	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
++	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDFC_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
++
++	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
++	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
++	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDFC_1),
++	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
++	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
++
++	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
++	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
++	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
++	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDFC_1),
++	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
++	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
++
++	/* IPSR9 */
++	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
++	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
++
++	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
++	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
++
++	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
++	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
++
++	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
++	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
++
++	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
++	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
++
++	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
++	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
++
++	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
++	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
++	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
++
++	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
++	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
++
++	/* IPSR10 */
++	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
++	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
++
++	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
++	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
++
++	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
++	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
++
++	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
++	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
++
++	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
++	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
++
++	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
++	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
++	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
++
++	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
++	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
++	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
++
++	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
++	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
++	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
++
++	/* IPSR11 */
++	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
++	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
++	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
++
++	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
++	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
++
++	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
++	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDFC_0),
++	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
++	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
++
++	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
++	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDFC_0),
++	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
++
++	PINMUX_IPSR_GPSR(IP11_19_16,	SD1_CD),
++	PINMUX_IPSR_MSEL(IP11_19_16,	NFRB_N_A,		SEL_NDFC_0),
++	PINMUX_IPSR_MSEL(IP11_19_16,	SIM0_CLK_B,		SEL_SIMCARD_1),
++
++	PINMUX_IPSR_GPSR(IP11_23_20,	SD1_WP),
++	PINMUX_IPSR_MSEL(IP11_23_20,	NFCE_N_A,		SEL_NDFC_0),
++	PINMUX_IPSR_MSEL(IP11_23_20,	SIM0_D_B,		SEL_SIMCARD_1),
++
++	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
++	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADG_C_1),
++	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
++	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
++	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
++	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
++	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
++	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
++
++	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
++	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
++	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
++	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
++
++	/* IPSR12 */
++	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
++	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
++	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
++	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
++
++	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
++	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
++	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
++	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
++	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
++	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
++
++	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
++	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADG_A_1),
++	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
++	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
++	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
++	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
++
++	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
++	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
++	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
++
++	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
++	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
++	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
++
++	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
++	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
++	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
++	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
++	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
++
++	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
++	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
++	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
++	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
++	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
++
++	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
++	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
++	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
++	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
++	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
++	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
++	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
++
++	/* IPSR13 */
++	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
++	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
++	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
++	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
++	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
++	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
++
++	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
++	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
++	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
++	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
++	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
++	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
++
++	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
++	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADG_B_0),
++	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
++	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
++	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
++	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
++	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
++
++	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
++	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
++	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
++	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
++	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
++
++	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
++	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
++	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
++	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
++	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
++
++	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
++	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
++	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
++	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
++	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
++	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
++
++	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
++	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
++	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
++	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
++	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
++
++	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
++	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
++	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
++	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
++
++	/* IPSR14 */
++	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
++	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
++	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDFC_0),
++	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADG_A_2),
++	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
++	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
++	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
++
++	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
++	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
++	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
++	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADG_C_0),
++	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
++	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
++	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
++
++	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
++	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
++	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
++
++	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
++	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
++	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
++	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
++
++	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
++	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
++	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
++
++	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
++	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
++
++	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
++	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
++
++	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
++	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
++
++	/* IPSR15 */
++	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
++
++	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
++
++	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
++	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
++
++	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
++	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
++
++	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
++	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
++	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
++	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
++
++	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
++	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
++	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
++	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
++
++	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
++	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
++	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
++	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
++
++	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
++	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
++	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
++	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
++
++	/* IPSR16 */
++	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
++	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
++
++	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
++	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
++
++	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
++	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
++	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
++
++	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
++	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
++	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
++	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
++	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
++
++	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
++	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
++	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
++	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
++	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
++
++	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
++	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
++	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
++	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
++	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
++	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
++
++	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
++	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
++	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
++	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
++	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
++
++	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
++	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
++	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
++	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
++
++	/* IPSR17 */
++	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADG_A_0),
++	PINMUX_IPSR_GPSR(IP17_3_0,	CC5_OSCOUT),
++
++	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADG_B_1),
++	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
++	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
++	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
++	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
++
++	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
++	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
++	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
++	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
++	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
++	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
++
++	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
++	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
++	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
++	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
++	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
++
++	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
++	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
++	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
++	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
++	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
++	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
++	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
++	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
++
++	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
++	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
++	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
++	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
++	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
++	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
++	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
++	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
++
++	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
++	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
++	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
++	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
++	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
++	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
++	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
++	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
++	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
++
++	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
++	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
++	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
++	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
++	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
++	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
++	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
++	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
++
++	/* IPSR18 */
++	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
++	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
++	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
++	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
++	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
++	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
++	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
++	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
++
++	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
++	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
++	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
++	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
++	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
++	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
++	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
++	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
++	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
++
++	/* I2C */
++	PINMUX_IPSR_NOGP(0,		I2C_SEL_0_1),
++	PINMUX_IPSR_NOGP(0,		I2C_SEL_3_1),
++	PINMUX_IPSR_NOGP(0,		I2C_SEL_5_1),
++
++/*
++ * Static pins can not be muxed between different functions but
++ * still needs a mark entry in the pinmux list. Add each static
++ * pin to the list without an associated function. The sh-pfc
++ * core will do the right thing and skip trying to mux then pin
++ * while still applying configuration to it
++ */
++#define FM(x)   PINMUX_DATA(x##_MARK, 0),
++	PINMUX_STATIC
++#undef FM
++};
++
++/*
++ * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
++ * Physical layout rows: A - AW, cols: 1 - 39.
++ */
++#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
++#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
++#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
++#define PIN_NONE U16_MAX
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++
++	/*
++	 * Pins not associated with a GPIO port.
++	 *
++	 * The pin positions are different between different r8a77965
++	 * packages, all that is needed for the pfc driver is a unique
++	 * number for each pin. To this end use the pin layout from
++	 * R-Car M3SiP to calculate a unique number for each pin.
++	 */
++	SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++#define F_(x, y)	FN_##y
++#define FM(x)		FN_##x
++	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_15_FN,	GPSR0_15,
++		GP_0_14_FN,	GPSR0_14,
++		GP_0_13_FN,	GPSR0_13,
++		GP_0_12_FN,	GPSR0_12,
++		GP_0_11_FN,	GPSR0_11,
++		GP_0_10_FN,	GPSR0_10,
++		GP_0_9_FN,	GPSR0_9,
++		GP_0_8_FN,	GPSR0_8,
++		GP_0_7_FN,	GPSR0_7,
++		GP_0_6_FN,	GPSR0_6,
++		GP_0_5_FN,	GPSR0_5,
++		GP_0_4_FN,	GPSR0_4,
++		GP_0_3_FN,	GPSR0_3,
++		GP_0_2_FN,	GPSR0_2,
++		GP_0_1_FN,	GPSR0_1,
++		GP_0_0_FN,	GPSR0_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_28_FN,	GPSR1_28,
++		GP_1_27_FN,	GPSR1_27,
++		GP_1_26_FN,	GPSR1_26,
++		GP_1_25_FN,	GPSR1_25,
++		GP_1_24_FN,	GPSR1_24,
++		GP_1_23_FN,	GPSR1_23,
++		GP_1_22_FN,	GPSR1_22,
++		GP_1_21_FN,	GPSR1_21,
++		GP_1_20_FN,	GPSR1_20,
++		GP_1_19_FN,	GPSR1_19,
++		GP_1_18_FN,	GPSR1_18,
++		GP_1_17_FN,	GPSR1_17,
++		GP_1_16_FN,	GPSR1_16,
++		GP_1_15_FN,	GPSR1_15,
++		GP_1_14_FN,	GPSR1_14,
++		GP_1_13_FN,	GPSR1_13,
++		GP_1_12_FN,	GPSR1_12,
++		GP_1_11_FN,	GPSR1_11,
++		GP_1_10_FN,	GPSR1_10,
++		GP_1_9_FN,	GPSR1_9,
++		GP_1_8_FN,	GPSR1_8,
++		GP_1_7_FN,	GPSR1_7,
++		GP_1_6_FN,	GPSR1_6,
++		GP_1_5_FN,	GPSR1_5,
++		GP_1_4_FN,	GPSR1_4,
++		GP_1_3_FN,	GPSR1_3,
++		GP_1_2_FN,	GPSR1_2,
++		GP_1_1_FN,	GPSR1_1,
++		GP_1_0_FN,	GPSR1_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_2_14_FN,	GPSR2_14,
++		GP_2_13_FN,	GPSR2_13,
++		GP_2_12_FN,	GPSR2_12,
++		GP_2_11_FN,	GPSR2_11,
++		GP_2_10_FN,	GPSR2_10,
++		GP_2_9_FN,	GPSR2_9,
++		GP_2_8_FN,	GPSR2_8,
++		GP_2_7_FN,	GPSR2_7,
++		GP_2_6_FN,	GPSR2_6,
++		GP_2_5_FN,	GPSR2_5,
++		GP_2_4_FN,	GPSR2_4,
++		GP_2_3_FN,	GPSR2_3,
++		GP_2_2_FN,	GPSR2_2,
++		GP_2_1_FN,	GPSR2_1,
++		GP_2_0_FN,	GPSR2_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_15_FN,	GPSR3_15,
++		GP_3_14_FN,	GPSR3_14,
++		GP_3_13_FN,	GPSR3_13,
++		GP_3_12_FN,	GPSR3_12,
++		GP_3_11_FN,	GPSR3_11,
++		GP_3_10_FN,	GPSR3_10,
++		GP_3_9_FN,	GPSR3_9,
++		GP_3_8_FN,	GPSR3_8,
++		GP_3_7_FN,	GPSR3_7,
++		GP_3_6_FN,	GPSR3_6,
++		GP_3_5_FN,	GPSR3_5,
++		GP_3_4_FN,	GPSR3_4,
++		GP_3_3_FN,	GPSR3_3,
++		GP_3_2_FN,	GPSR3_2,
++		GP_3_1_FN,	GPSR3_1,
++		GP_3_0_FN,	GPSR3_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_17_FN,	GPSR4_17,
++		GP_4_16_FN,	GPSR4_16,
++		GP_4_15_FN,	GPSR4_15,
++		GP_4_14_FN,	GPSR4_14,
++		GP_4_13_FN,	GPSR4_13,
++		GP_4_12_FN,	GPSR4_12,
++		GP_4_11_FN,	GPSR4_11,
++		GP_4_10_FN,	GPSR4_10,
++		GP_4_9_FN,	GPSR4_9,
++		GP_4_8_FN,	GPSR4_8,
++		GP_4_7_FN,	GPSR4_7,
++		GP_4_6_FN,	GPSR4_6,
++		GP_4_5_FN,	GPSR4_5,
++		GP_4_4_FN,	GPSR4_4,
++		GP_4_3_FN,	GPSR4_3,
++		GP_4_2_FN,	GPSR4_2,
++		GP_4_1_FN,	GPSR4_1,
++		GP_4_0_FN,	GPSR4_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_25_FN,	GPSR5_25,
++		GP_5_24_FN,	GPSR5_24,
++		GP_5_23_FN,	GPSR5_23,
++		GP_5_22_FN,	GPSR5_22,
++		GP_5_21_FN,	GPSR5_21,
++		GP_5_20_FN,	GPSR5_20,
++		GP_5_19_FN,	GPSR5_19,
++		GP_5_18_FN,	GPSR5_18,
++		GP_5_17_FN,	GPSR5_17,
++		GP_5_16_FN,	GPSR5_16,
++		GP_5_15_FN,	GPSR5_15,
++		GP_5_14_FN,	GPSR5_14,
++		GP_5_13_FN,	GPSR5_13,
++		GP_5_12_FN,	GPSR5_12,
++		GP_5_11_FN,	GPSR5_11,
++		GP_5_10_FN,	GPSR5_10,
++		GP_5_9_FN,	GPSR5_9,
++		GP_5_8_FN,	GPSR5_8,
++		GP_5_7_FN,	GPSR5_7,
++		GP_5_6_FN,	GPSR5_6,
++		GP_5_5_FN,	GPSR5_5,
++		GP_5_4_FN,	GPSR5_4,
++		GP_5_3_FN,	GPSR5_3,
++		GP_5_2_FN,	GPSR5_2,
++		GP_5_1_FN,	GPSR5_1,
++		GP_5_0_FN,	GPSR5_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
++		GP_6_31_FN,	GPSR6_31,
++		GP_6_30_FN,	GPSR6_30,
++		GP_6_29_FN,	GPSR6_29,
++		GP_6_28_FN,	GPSR6_28,
++		GP_6_27_FN,	GPSR6_27,
++		GP_6_26_FN,	GPSR6_26,
++		GP_6_25_FN,	GPSR6_25,
++		GP_6_24_FN,	GPSR6_24,
++		GP_6_23_FN,	GPSR6_23,
++		GP_6_22_FN,	GPSR6_22,
++		GP_6_21_FN,	GPSR6_21,
++		GP_6_20_FN,	GPSR6_20,
++		GP_6_19_FN,	GPSR6_19,
++		GP_6_18_FN,	GPSR6_18,
++		GP_6_17_FN,	GPSR6_17,
++		GP_6_16_FN,	GPSR6_16,
++		GP_6_15_FN,	GPSR6_15,
++		GP_6_14_FN,	GPSR6_14,
++		GP_6_13_FN,	GPSR6_13,
++		GP_6_12_FN,	GPSR6_12,
++		GP_6_11_FN,	GPSR6_11,
++		GP_6_10_FN,	GPSR6_10,
++		GP_6_9_FN,	GPSR6_9,
++		GP_6_8_FN,	GPSR6_8,
++		GP_6_7_FN,	GPSR6_7,
++		GP_6_6_FN,	GPSR6_6,
++		GP_6_5_FN,	GPSR6_5,
++		GP_6_4_FN,	GPSR6_4,
++		GP_6_3_FN,	GPSR6_3,
++		GP_6_2_FN,	GPSR6_2,
++		GP_6_1_FN,	GPSR6_1,
++		GP_6_0_FN,	GPSR6_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_7_3_FN, GPSR7_3,
++		GP_7_2_FN, GPSR7_2,
++		GP_7_1_FN, GPSR7_1,
++		GP_7_0_FN, GPSR7_0, }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
++		IP0_31_28
++		IP0_27_24
++		IP0_23_20
++		IP0_19_16
++		IP0_15_12
++		IP0_11_8
++		IP0_7_4
++		IP0_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
++		IP1_31_28
++		IP1_27_24
++		IP1_23_20
++		IP1_19_16
++		IP1_15_12
++		IP1_11_8
++		IP1_7_4
++		IP1_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
++		IP2_31_28
++		IP2_27_24
++		IP2_23_20
++		IP2_19_16
++		IP2_15_12
++		IP2_11_8
++		IP2_7_4
++		IP2_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
++		IP3_31_28
++		IP3_27_24
++		IP3_23_20
++		IP3_19_16
++		IP3_15_12
++		IP3_11_8
++		IP3_7_4
++		IP3_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
++		IP4_31_28
++		IP4_27_24
++		IP4_23_20
++		IP4_19_16
++		IP4_15_12
++		IP4_11_8
++		IP4_7_4
++		IP4_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
++		IP5_31_28
++		IP5_27_24
++		IP5_23_20
++		IP5_19_16
++		IP5_15_12
++		IP5_11_8
++		IP5_7_4
++		IP5_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
++		IP6_31_28
++		IP6_27_24
++		IP6_23_20
++		IP6_19_16
++		IP6_15_12
++		IP6_11_8
++		IP6_7_4
++		IP6_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
++		IP7_31_28
++		IP7_27_24
++		IP7_23_20
++		IP7_19_16
++		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		IP7_11_8
++		IP7_7_4
++		IP7_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
++		IP9_31_28
++		IP9_27_24
++		IP9_23_20
++		IP9_19_16
++		IP9_15_12
++		IP9_11_8
++		IP9_7_4
++		IP9_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
++		IP10_31_28
++		IP10_27_24
++		IP10_23_20
++		IP10_19_16
++		IP10_15_12
++		IP10_11_8
++		IP10_7_4
++		IP10_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
++		IP11_31_28
++		IP11_27_24
++		IP11_23_20
++		IP11_19_16
++		IP11_15_12
++		IP11_11_8
++		IP11_7_4
++		IP11_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
++		IP12_31_28
++		IP12_27_24
++		IP12_23_20
++		IP12_19_16
++		IP12_15_12
++		IP12_11_8
++		IP12_7_4
++		IP12_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
++		IP13_31_28
++		IP13_27_24
++		IP13_23_20
++		IP13_19_16
++		IP13_15_12
++		IP13_11_8
++		IP13_7_4
++		IP13_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
++		IP14_31_28
++		IP14_27_24
++		IP14_23_20
++		IP14_19_16
++		IP14_15_12
++		IP14_11_8
++		IP14_7_4
++		IP14_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
++		IP15_31_28
++		IP15_27_24
++		IP15_23_20
++		IP15_19_16
++		IP15_15_12
++		IP15_11_8
++		IP15_7_4
++		IP15_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
++		IP16_31_28
++		IP16_27_24
++		IP16_23_20
++		IP16_19_16
++		IP16_15_12
++		IP16_11_8
++		IP16_7_4
++		IP16_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
++		IP17_31_28
++		IP17_27_24
++		IP17_23_20
++		IP17_19_16
++		IP17_15_12
++		IP17_11_8
++		IP17_7_4
++		IP17_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
++		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		IP18_7_4
++		IP18_3_0 }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
++			     3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
++			     1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
++		MOD_SEL0_31_30_29
++		MOD_SEL0_28_27
++		MOD_SEL0_26_25_24
++		MOD_SEL0_23
++		MOD_SEL0_22
++		MOD_SEL0_21
++		MOD_SEL0_20
++		MOD_SEL0_19
++		MOD_SEL0_18_17
++		MOD_SEL0_16
++		0, 0, /* RESERVED 15 */
++		MOD_SEL0_14_13
++		MOD_SEL0_12
++		MOD_SEL0_11
++		MOD_SEL0_10
++		MOD_SEL0_9_8
++		MOD_SEL0_7_6
++		MOD_SEL0_5
++		MOD_SEL0_4_3
++		/* RESERVED 2, 1, 0 */
++		0, 0, 0, 0, 0, 0, 0, 0 }
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
++			     2, 3, 1, 2, 3, 1, 1, 2, 1,
++			     2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
++		MOD_SEL1_31_30
++		MOD_SEL1_29_28_27
++		MOD_SEL1_26
++		MOD_SEL1_25_24
++		MOD_SEL1_23_22_21
++		MOD_SEL1_20
++		MOD_SEL1_19
++		MOD_SEL1_18_17
++		MOD_SEL1_16
++		MOD_SEL1_15_14
++		MOD_SEL1_13
++		MOD_SEL1_12
++		MOD_SEL1_11
++		MOD_SEL1_10
++		MOD_SEL1_9
++		0, 0, 0, 0, /* RESERVED 8, 7 */
++		MOD_SEL1_6
++		MOD_SEL1_5
++		MOD_SEL1_4
++		MOD_SEL1_3
++		MOD_SEL1_2
++		MOD_SEL1_1
++		MOD_SEL1_0 }
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
++			     1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
++			     4, 4, 4, 3, 1) {
++		MOD_SEL2_31
++		MOD_SEL2_30
++		MOD_SEL2_29
++		MOD_SEL2_28_27
++		MOD_SEL2_26
++		MOD_SEL2_25_24_23
++		MOD_SEL2_22
++		MOD_SEL2_21
++		MOD_SEL2_20
++		MOD_SEL2_19
++		MOD_SEL2_18
++		MOD_SEL2_17
++		/* RESERVED 16 */
++		0, 0,
++		/* RESERVED 15, 14, 13, 12 */
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 11, 10, 9, 8 */
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 7, 6, 5, 4 */
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 3, 2, 1 */
++		0, 0, 0, 0, 0, 0, 0, 0,
++		MOD_SEL2_0 }
++	},
++	{ },
++};
++
++static const struct pinmux_drive_reg pinmux_drive_regs[] = {
++	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
++		{ PIN_NUMBER('W', 3),   28, 2 },	/* QSPI0_SPCLK */
++		{ PIN_A_NUMBER('C', 5), 24, 2 },	/* QSPI0_MOSI_IO0 */
++		{ PIN_A_NUMBER('B', 4), 20, 2 },	/* QSPI0_MISO_IO1 */
++		{ PIN_NUMBER('Y', 6),   16, 2 },	/* QSPI0_IO2 */
++		{ PIN_A_NUMBER('B', 6), 12, 2 },	/* QSPI0_IO3 */
++		{ PIN_NUMBER('Y', 3),    8, 2 },	/* QSPI0_SSL */
++		{ PIN_NUMBER('V', 3),    4, 2 },	/* QSPI1_SPCLK */
++		{ PIN_A_NUMBER('C', 7),  0, 2 },	/* QSPI1_MOSI_IO0 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
++		{ PIN_A_NUMBER('E', 5), 28, 2 },	/* QSPI1_MISO_IO1 */
++		{ PIN_A_NUMBER('E', 4), 24, 2 },	/* QSPI1_IO2 */
++		{ PIN_A_NUMBER('C', 3), 20, 2 },	/* QSPI1_IO3 */
++		{ PIN_NUMBER('V', 5),   16, 2 },	/* QSPI1_SSL */
++		{ PIN_NUMBER('Y', 7),   12, 2 },	/* RPC_INT# */
++		{ PIN_NUMBER('V', 6),    8, 2 },	/* RPC_WP# */
++		{ PIN_NUMBER('V', 7),    4, 2 },	/* RPC_RESET# */
++		{ PIN_NUMBER('A', 16),   0, 3 },	/* AVB_RX_CTL */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
++		{ PIN_NUMBER('B', 19),  28, 3 },	/* AVB_RXC */
++		{ PIN_NUMBER('A', 13),  24, 3 },	/* AVB_RD0 */
++		{ PIN_NUMBER('B', 13),  20, 3 },	/* AVB_RD1 */
++		{ PIN_NUMBER('A', 14),  16, 3 },	/* AVB_RD2 */
++		{ PIN_NUMBER('B', 14),  12, 3 },	/* AVB_RD3 */
++		{ PIN_NUMBER('A', 8),    8, 3 },	/* AVB_TX_CTL */
++		{ PIN_NUMBER('A', 19),   4, 3 },	/* AVB_TXC */
++		{ PIN_NUMBER('A', 18),   0, 3 },	/* AVB_TD0 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
++		{ PIN_NUMBER('B', 18),  28, 3 },	/* AVB_TD1 */
++		{ PIN_NUMBER('A', 17),  24, 3 },	/* AVB_TD2 */
++		{ PIN_NUMBER('B', 17),  20, 3 },	/* AVB_TD3 */
++		{ PIN_NUMBER('A', 12),  16, 3 },	/* AVB_TXCREFCLK */
++		{ PIN_NUMBER('A', 9),   12, 3 },	/* AVB_MDIO */
++		{ RCAR_GP_PIN(2,  9),    8, 3 },	/* AVB_MDC */
++		{ RCAR_GP_PIN(2, 10),    4, 3 },	/* AVB_MAGIC */
++		{ RCAR_GP_PIN(2, 11),    0, 3 },	/* AVB_PHY_INT */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
++		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
++		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
++		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
++		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
++		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
++		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
++		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
++		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
++		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
++		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
++		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
++		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
++		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
++		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
++		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
++		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
++		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
++		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
++		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
++		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
++		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
++		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
++		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
++		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
++		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
++		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
++		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
++		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
++		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
++		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
++		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
++		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
++		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
++		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
++		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
++		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
++		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
++		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
++		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
++		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
++		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
++		{ PIN_NUMBER('C', 1), 24, 3 },	/* PRESETOUT# */
++		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
++		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
++		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
++		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
++		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
++		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
++		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
++		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
++		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
++		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
++		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
++		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
++		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
++		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
++		{ RCAR_GP_PIN(0, 14),   28, 3 },	/* D14 */
++		{ RCAR_GP_PIN(0, 15),   24, 3 },	/* D15 */
++		{ RCAR_GP_PIN(7,  0),   20, 3 },	/* AVS1 */
++		{ RCAR_GP_PIN(7,  1),   16, 3 },	/* AVS2 */
++		{ RCAR_GP_PIN(7,  2),   12, 3 },	/* HDMI0_CEC */
++		{ RCAR_GP_PIN(7,  3),    8, 3 },	/* GP7_03 */
++		{ PIN_A_NUMBER('P', 7),  4, 2 },	/* DU_DOTCLKIN0 */
++		{ PIN_A_NUMBER('P', 8),  0, 2 },	/* DU_DOTCLKIN1 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
++		{ PIN_A_NUMBER('R', 8),  28, 2 },	/* DU_DOTCLKIN3 */
++		{ PIN_A_NUMBER('D', 38), 20, 2 },	/* FSCLKST */
++		{ PIN_A_NUMBER('R', 30),  4, 2 },	/* TMS */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
++		{ PIN_A_NUMBER('T', 28), 28, 2 },	/* TDO */
++		{ PIN_A_NUMBER('T', 30), 24, 2 },	/* ASEBRK */
++		{ RCAR_GP_PIN(3,  0),    20, 3 },	/* SD0_CLK */
++		{ RCAR_GP_PIN(3,  1),    16, 3 },	/* SD0_CMD */
++		{ RCAR_GP_PIN(3,  2),    12, 3 },	/* SD0_DAT0 */
++		{ RCAR_GP_PIN(3,  3),     8, 3 },	/* SD0_DAT1 */
++		{ RCAR_GP_PIN(3,  4),     4, 3 },	/* SD0_DAT2 */
++		{ RCAR_GP_PIN(3,  5),     0, 3 },	/* SD0_DAT3 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
++		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
++		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
++		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
++		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
++		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
++		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
++		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
++		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
++		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
++		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
++		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
++		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
++		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
++		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
++		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
++		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
++		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
++		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
++		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
++		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
++		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
++		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
++		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
++		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
++		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
++		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
++		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
++		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
++		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
++		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
++		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
++		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
++		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
++		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
++		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
++		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
++		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
++		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
++		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
++		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
++		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
++		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
++		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
++		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
++		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
++		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
++		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
++		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
++		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
++		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
++		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
++		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
++		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
++		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
++		{ PIN_NUMBER('H', 37),  4, 3 },	/* MLB_REF */
++		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
++		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
++		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
++		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
++		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
++		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
++		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
++		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
++		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
++		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
++		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
++		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
++		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
++		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
++		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
++		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
++		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
++		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
++		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
++		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
++		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
++		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
++		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
++		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
++		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
++	} },
++	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
++		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
++		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
++		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
++		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
++		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
++		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
++		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
++	} },
++	{ },
++};
++
++enum ioctrl_regs {
++	POCCTRL,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[POCCTRL] = { 0xe6060380, },
++	{ /* sentinel */ },
++};
++
++static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
++{
++	int bit = -EINVAL;
++
++	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
++
++	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
++		bit = pin & 0x1f;
++
++	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
++		bit = (pin & 0x1f) + 12;
++
++	return bit;
++}
++
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
++		[ 0] = PIN_NUMBER('W', 3),	/* QSPI0_SPCLK */
++		[ 1] = PIN_A_NUMBER('C', 5),	/* QSPI0_MOSI_IO0 */
++		[ 2] = PIN_A_NUMBER('B', 4),	/* QSPI0_MISO_IO1 */
++		[ 3] = PIN_NUMBER('Y', 6),	/* QSPI0_IO2 */
++		[ 4] = PIN_A_NUMBER('B', 6),	/* QSPI0_IO3 */
++		[ 5] = PIN_NUMBER('Y', 3),	/* QSPI0_SSL */
++		[ 6] = PIN_NUMBER('V', 3),	/* QSPI1_SPCLK */
++		[ 7] = PIN_A_NUMBER('C', 7),	/* QSPI1_MOSI_IO0 */
++		[ 8] = PIN_A_NUMBER('E', 5),	/* QSPI1_MISO_IO1 */
++		[ 9] = PIN_A_NUMBER('E', 4),	/* QSPI1_IO2 */
++		[10] = PIN_A_NUMBER('C', 3),	/* QSPI1_IO3 */
++		[11] = PIN_NUMBER('V', 5),	/* QSPI1_SSL */
++		[12] = PIN_NUMBER('Y', 7),	/* RPC_INT# */
++		[13] = PIN_NUMBER('V', 6),	/* RPC_WP# */
++		[14] = PIN_NUMBER('V', 7),	/* RPC_RESET# */
++		[15] = PIN_NUMBER('A', 16),	/* AVB_RX_CTL */
++		[16] = PIN_NUMBER('B', 19),	/* AVB_RXC */
++		[17] = PIN_NUMBER('A', 13),	/* AVB_RD0 */
++		[18] = PIN_NUMBER('B', 13),	/* AVB_RD1 */
++		[19] = PIN_NUMBER('A', 14),	/* AVB_RD2 */
++		[20] = PIN_NUMBER('B', 14),	/* AVB_RD3 */
++		[21] = PIN_NUMBER('A', 8),	/* AVB_TX_CTL */
++		[22] = PIN_NUMBER('A', 19),	/* AVB_TXC */
++		[23] = PIN_NUMBER('A', 18),	/* AVB_TD0 */
++		[24] = PIN_NUMBER('B', 18),	/* AVB_TD1 */
++		[25] = PIN_NUMBER('A', 17),	/* AVB_TD2 */
++		[26] = PIN_NUMBER('B', 17),	/* AVB_TD3 */
++		[27] = PIN_NUMBER('A', 12),	/* AVB_TXCREFCLK */
++		[28] = PIN_NUMBER('A', 9),	/* AVB_MDIO */
++		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
++		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
++		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
++	} },
++	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
++		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
++		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
++		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
++		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
++		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
++		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
++		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
++		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
++		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
++		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
++		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
++		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
++		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
++		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
++		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
++		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
++		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
++		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
++		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
++		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
++		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
++		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
++		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
++		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
++		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
++		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
++		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
++		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
++		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
++		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
++		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
++		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
++		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
++		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
++		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
++		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
++		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
++		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
++		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
++		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
++		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
++		[ 9] = PIN_NUMBER('C', 1),	/* PRESETOUT# */
++		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
++		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
++		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
++		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
++		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
++		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
++		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
++		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
++		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
++		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
++		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
++		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
++		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
++		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
++		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
++		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
++		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
++		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
++		[28] = RCAR_GP_PIN(7,  2),	/* HDMI0_CEC */
++		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
++		[30] = PIN_A_NUMBER('P', 7),	/* DU_DOTCLKIN0 */
++		[31] = PIN_A_NUMBER('P', 8),	/* DU_DOTCLKIN1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
++		[ 0] = PIN_A_NUMBER('R', 8),	/* DU_DOTCLKIN2 */
++		[ 1] = PIN_NONE,
++		[ 2] = PIN_A_NUMBER('D', 38),	/* FSCLKST */
++		[ 3] = PIN_A_NUMBER('D', 39),	/* EXTALR*/
++		[ 4] = PIN_A_NUMBER('R', 26),	/* TRST# */
++		[ 5] = PIN_A_NUMBER('T', 27),	/* TCK */
++		[ 6] = PIN_A_NUMBER('R', 30),	/* TMS */
++		[ 7] = PIN_A_NUMBER('R', 29),	/* TDI */
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_A_NUMBER('T', 30),	/* ASEBRK */
++		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
++		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
++		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
++		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
++		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
++		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
++		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
++		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
++		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
++		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
++		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
++		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
++		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
++		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
++		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
++		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
++		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
++		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
++		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
++		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
++		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
++		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
++		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
++		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
++		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
++		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
++		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
++		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
++		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
++		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
++		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
++		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
++		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
++		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
++		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
++		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
++		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
++		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
++		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
++		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
++		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
++		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
++		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
++		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
++		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
++		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
++		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
++		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
++		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
++		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
++		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
++		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
++		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
++		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
++		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
++		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
++		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
++		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
++		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
++		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
++		[ 6] = PIN_NUMBER('H', 37),	/* MLB_REF */
++		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
++		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
++		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
++		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
++		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
++		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
++		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
++		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
++		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
++		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
++		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
++		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
++		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
++		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
++		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
++		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
++		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
++		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
++		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
++		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
++		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
++		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
++		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
++		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
++		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
++	} },
++	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
++		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
++		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
++		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
++		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
++		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
++		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
++		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
++		[ 7] = PIN_NONE,
++		[ 8] = PIN_NONE,
++		[ 9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = PIN_NONE,
++		[31] = PIN_NONE,
++	} },
++	{ /* sentinel */ },
++};
++
++static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
++					    unsigned int pin)
++{
++	const struct pinmux_bias_reg *reg;
++	unsigned int bit;
++
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
++		return PIN_CONFIG_BIAS_DISABLE;
++
++	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
++		return PIN_CONFIG_BIAS_DISABLE;
++	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
++		return PIN_CONFIG_BIAS_PULL_UP;
++	else
++		return PIN_CONFIG_BIAS_PULL_DOWN;
++}
++
++static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
++				   unsigned int bias)
++{
++	const struct pinmux_bias_reg *reg;
++	u32 enable, updown;
++	unsigned int bit;
++
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
++		return;
++
++	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
++	if (bias != PIN_CONFIG_BIAS_DISABLE)
++		enable |= BIT(bit);
++
++	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
++	if (bias == PIN_CONFIG_BIAS_PULL_UP)
++		updown |= BIT(bit);
++
++	sh_pfc_write(pfc, reg->pud, updown);
++	sh_pfc_write(pfc, reg->puen, enable);
++}
++
++static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
++	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
++	.get_bias = r8a77965_pinmux_get_bias,
++	.set_bias = r8a77965_pinmux_set_bias,
++};
++
++const struct sh_pfc_soc_info r8a77965_pinmux_info = {
++	.name = "r8a77965_pfc",
++	.ops = &r8a77965_pinmux_ops,
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++	.drive_regs = pinmux_drive_regs,
++	.bias_regs = pinmux_bias_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 5747ab0472df..7253a8cbb0ea 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
++extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+-- 
+2.19.0
+
diff --git a/patches/0863-pinctrl-sh-pfc-r8a77965-Add-SCIFs-groups-functions.patch b/patches/0863-pinctrl-sh-pfc-r8a77965-Add-SCIFs-groups-functions.patch
new file mode 100644
index 00000000000000..ce73a68c3f243a
--- /dev/null
+++ b/patches/0863-pinctrl-sh-pfc-r8a77965-Add-SCIFs-groups-functions.patch
@@ -0,0 +1,331 @@
+From e21a99128fc688cbe1859a5caca65f80b02cc8cd Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:15 +0100
+Subject: [PATCH 0863/1795] pinctrl: sh-pfc: r8a77965: Add SCIFs
+ groups/functions
+
+Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 58cfd7f37e1a7e1626915b59279681361a70a68a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 296 ++++++++++++++++++++++++++
+ 1 file changed, 296 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 3583e2018534..735fb4380101 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1575,10 +1575,306 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+ };
+ 
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
++};
++static const unsigned int scif0_data_mux[] = {
++	RX0_MARK, TX0_MARK,
++};
++static const unsigned int scif0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int scif0_clk_mux[] = {
++	SCK0_MARK,
++};
++static const unsigned int scif0_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
++};
++static const unsigned int scif0_ctrl_mux[] = {
++	RTS0_N_MARK, CTS0_N_MARK,
++};
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
++};
++static const unsigned int scif1_data_a_mux[] = {
++	RX1_A_MARK, TX1_A_MARK,
++};
++static const unsigned int scif1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int scif1_clk_mux[] = {
++	SCK1_MARK,
++};
++static const unsigned int scif1_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
++};
++static const unsigned int scif1_ctrl_mux[] = {
++	RTS1_N_MARK, CTS1_N_MARK,
++};
++static const unsigned int scif1_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
++};
++static const unsigned int scif1_data_b_mux[] = {
++	RX1_B_MARK, TX1_B_MARK,
++};
++/* - SCIF2 ------------------------------------------------------------------ */
++static const unsigned int scif2_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
++};
++static const unsigned int scif2_data_a_mux[] = {
++	RX2_A_MARK, TX2_A_MARK,
++};
++static const unsigned int scif2_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 9),
++};
++static const unsigned int scif2_clk_mux[] = {
++	SCK2_MARK,
++};
++static const unsigned int scif2_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
++};
++static const unsigned int scif2_data_b_mux[] = {
++	RX2_B_MARK, TX2_B_MARK,
++};
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
++};
++static const unsigned int scif3_data_a_mux[] = {
++	RX3_A_MARK, TX3_A_MARK,
++};
++static const unsigned int scif3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int scif3_clk_mux[] = {
++	SCK3_MARK,
++};
++static const unsigned int scif3_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
++};
++static const unsigned int scif3_ctrl_mux[] = {
++	RTS3_N_MARK, CTS3_N_MARK,
++};
++static const unsigned int scif3_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
++};
++static const unsigned int scif3_data_b_mux[] = {
++	RX3_B_MARK, TX3_B_MARK,
++};
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++};
++static const unsigned int scif4_data_a_mux[] = {
++	RX4_A_MARK, TX4_A_MARK,
++};
++static const unsigned int scif4_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 10),
++};
++static const unsigned int scif4_clk_a_mux[] = {
++	SCK4_A_MARK,
++};
++static const unsigned int scif4_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int scif4_ctrl_a_mux[] = {
++	RTS4_N_A_MARK, CTS4_N_A_MARK,
++};
++static const unsigned int scif4_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int scif4_data_b_mux[] = {
++	RX4_B_MARK, TX4_B_MARK,
++};
++static const unsigned int scif4_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 5),
++};
++static const unsigned int scif4_clk_b_mux[] = {
++	SCK4_B_MARK,
++};
++static const unsigned int scif4_ctrl_b_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
++};
++static const unsigned int scif4_ctrl_b_mux[] = {
++	RTS4_N_B_MARK, CTS4_N_B_MARK,
++};
++static const unsigned int scif4_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++};
++static const unsigned int scif4_data_c_mux[] = {
++	RX4_C_MARK, TX4_C_MARK,
++};
++static const unsigned int scif4_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 8),
++};
++static const unsigned int scif4_clk_c_mux[] = {
++	SCK4_C_MARK,
++};
++static const unsigned int scif4_ctrl_c_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
++};
++static const unsigned int scif4_ctrl_c_mux[] = {
++	RTS4_N_C_MARK, CTS4_N_C_MARK,
++};
++/* - SCIF5 ------------------------------------------------------------------ */
++static const unsigned int scif5_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
++};
++static const unsigned int scif5_data_a_mux[] = {
++	RX5_A_MARK, TX5_A_MARK,
++};
++static const unsigned int scif5_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int scif5_clk_a_mux[] = {
++	SCK5_A_MARK,
++};
++static const unsigned int scif5_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
++};
++static const unsigned int scif5_data_b_mux[] = {
++	RX5_B_MARK, TX5_B_MARK,
++};
++static const unsigned int scif5_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int scif5_clk_b_mux[] = {
++	SCK5_B_MARK,
++};
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(6, 23),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(5, 9),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(scif0_data),
++	SH_PFC_PIN_GROUP(scif0_clk),
++	SH_PFC_PIN_GROUP(scif0_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_a),
++	SH_PFC_PIN_GROUP(scif1_clk),
++	SH_PFC_PIN_GROUP(scif1_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_b),
++	SH_PFC_PIN_GROUP(scif2_data_a),
++	SH_PFC_PIN_GROUP(scif2_clk),
++	SH_PFC_PIN_GROUP(scif2_data_b),
++	SH_PFC_PIN_GROUP(scif3_data_a),
++	SH_PFC_PIN_GROUP(scif3_clk),
++	SH_PFC_PIN_GROUP(scif3_ctrl),
++	SH_PFC_PIN_GROUP(scif3_data_b),
++	SH_PFC_PIN_GROUP(scif4_data_a),
++	SH_PFC_PIN_GROUP(scif4_clk_a),
++	SH_PFC_PIN_GROUP(scif4_ctrl_a),
++	SH_PFC_PIN_GROUP(scif4_data_b),
++	SH_PFC_PIN_GROUP(scif4_clk_b),
++	SH_PFC_PIN_GROUP(scif4_ctrl_b),
++	SH_PFC_PIN_GROUP(scif4_data_c),
++	SH_PFC_PIN_GROUP(scif4_clk_c),
++	SH_PFC_PIN_GROUP(scif4_ctrl_c),
++	SH_PFC_PIN_GROUP(scif5_data_a),
++	SH_PFC_PIN_GROUP(scif5_clk_a),
++	SH_PFC_PIN_GROUP(scif5_data_b),
++	SH_PFC_PIN_GROUP(scif5_clk_b),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data",
++	"scif0_clk",
++	"scif0_ctrl",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data_a",
++	"scif1_clk",
++	"scif1_ctrl",
++	"scif1_data_b",
++};
++static const char * const scif2_groups[] = {
++	"scif2_data_a",
++	"scif2_clk",
++	"scif2_data_b",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data_a",
++	"scif3_clk",
++	"scif3_ctrl",
++	"scif3_data_b",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data_a",
++	"scif4_clk_a",
++	"scif4_ctrl_a",
++	"scif4_data_b",
++	"scif4_clk_b",
++	"scif4_ctrl_b",
++	"scif4_data_c",
++	"scif4_clk_c",
++	"scif4_ctrl_c",
++};
++
++static const char * const scif5_groups[] = {
++	"scif5_data_a",
++	"scif5_clk_a",
++	"scif5_data_b",
++	"scif5_clk_b",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif2),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(scif5),
++	SH_PFC_FUNCTION(scif_clk),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0864-pinctrl-sh-pfc-r8a77965-Add-EtherAVB-groups-function.patch b/patches/0864-pinctrl-sh-pfc-r8a77965-Add-EtherAVB-groups-function.patch
new file mode 100644
index 00000000000000..7f6debf39d34e4
--- /dev/null
+++ b/patches/0864-pinctrl-sh-pfc-r8a77965-Add-EtherAVB-groups-function.patch
@@ -0,0 +1,162 @@
+From cd5926b15d96d8706511f8e03b36aee1f3c65fc2 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:20 +0100
+Subject: [PATCH 0864/1795] pinctrl: sh-pfc: r8a77965: Add EtherAVB
+ groups/functions
+
+Add EtherAVB groups and functions definitions for R-Car M3-N.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit fa3e8b71b955af8691aa773da0e0d21f1cdc529b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 110 ++++++++++++++++++++++++++
+ 1 file changed, 110 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 735fb4380101..acd57d5b2fb1 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1575,6 +1575,92 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+ };
+ 
++/* - EtherAVB --------------------------------------------------------------- */
++static const unsigned int avb_link_pins[] = {
++	/* AVB_LINK */
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int avb_link_mux[] = {
++	AVB_LINK_MARK,
++};
++static const unsigned int avb_magic_pins[] = {
++	/* AVB_MAGIC_ */
++	RCAR_GP_PIN(2, 10),
++};
++static const unsigned int avb_magic_mux[] = {
++	AVB_MAGIC_MARK,
++};
++static const unsigned int avb_phy_int_pins[] = {
++	/* AVB_PHY_INT */
++	RCAR_GP_PIN(2, 11),
++};
++static const unsigned int avb_phy_int_mux[] = {
++	AVB_PHY_INT_MARK,
++};
++static const unsigned int avb_mdc_pins[] = {
++	/* AVB_MDC, AVB_MDIO */
++	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
++};
++static const unsigned int avb_mdc_mux[] = {
++	AVB_MDC_MARK, AVB_MDIO_MARK,
++};
++static const unsigned int avb_mii_pins[] = {
++	/*
++	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
++	 * AVB_TD1, AVB_TD2, AVB_TD3,
++	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
++	 * AVB_RD1, AVB_RD2, AVB_RD3,
++	 * AVB_TXCREFCLK
++	 */
++	PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
++	PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
++	PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
++	PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
++	PIN_NUMBER('A', 12),
++
++};
++static const unsigned int avb_mii_mux[] = {
++	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
++	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
++	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
++	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
++	AVB_TXCREFCLK_MARK,
++};
++static const unsigned int avb_avtp_pps_pins[] = {
++	/* AVB_AVTP_PPS */
++	RCAR_GP_PIN(2, 6),
++};
++static const unsigned int avb_avtp_pps_mux[] = {
++	AVB_AVTP_PPS_MARK,
++};
++static const unsigned int avb_avtp_match_a_pins[] = {
++	/* AVB_AVTP_MATCH_A */
++	RCAR_GP_PIN(2, 13),
++};
++static const unsigned int avb_avtp_match_a_mux[] = {
++	AVB_AVTP_MATCH_A_MARK,
++};
++static const unsigned int avb_avtp_capture_a_pins[] = {
++	/* AVB_AVTP_CAPTURE_A */
++	RCAR_GP_PIN(2, 14),
++};
++static const unsigned int avb_avtp_capture_a_mux[] = {
++	AVB_AVTP_CAPTURE_A_MARK,
++};
++static const unsigned int avb_avtp_match_b_pins[] = {
++	/*  AVB_AVTP_MATCH_B */
++	RCAR_GP_PIN(1, 8),
++};
++static const unsigned int avb_avtp_match_b_mux[] = {
++	AVB_AVTP_MATCH_B_MARK,
++};
++static const unsigned int avb_avtp_capture_b_pins[] = {
++	/* AVB_AVTP_CAPTURE_B */
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int avb_avtp_capture_b_mux[] = {
++	AVB_AVTP_CAPTURE_B_MARK,
++};
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -1787,6 +1873,16 @@ static const unsigned int scif_clk_b_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb_link),
++	SH_PFC_PIN_GROUP(avb_magic),
++	SH_PFC_PIN_GROUP(avb_phy_int),
++	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP(avb_mii),
++	SH_PFC_PIN_GROUP(avb_avtp_pps),
++	SH_PFC_PIN_GROUP(avb_avtp_match_a),
++	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
++	SH_PFC_PIN_GROUP(avb_avtp_match_b),
++	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ 	SH_PFC_PIN_GROUP(scif0_data),
+ 	SH_PFC_PIN_GROUP(scif0_clk),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl),
+@@ -1818,6 +1914,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
+ };
+ 
++static const char * const avb_groups[] = {
++	"avb_link",
++	"avb_magic",
++	"avb_phy_int",
++	"avb_mdc",
++	"avb_mii",
++	"avb_avtp_pps",
++	"avb_avtp_match_a",
++	"avb_avtp_capture_a",
++	"avb_avtp_match_b",
++	"avb_avtp_capture_b",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data",
+ 	"scif0_clk",
+@@ -1868,6 +1977,7 @@ static const char * const scif_clk_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/0865-pinctrl-sh-pfc-r8a7796-Add-VIN4-VIN5-pins-groups-and.patch b/patches/0865-pinctrl-sh-pfc-r8a7796-Add-VIN4-VIN5-pins-groups-and.patch
new file mode 100644
index 00000000000000..c580b9203732e3
--- /dev/null
+++ b/patches/0865-pinctrl-sh-pfc-r8a7796-Add-VIN4-VIN5-pins-groups-and.patch
@@ -0,0 +1,507 @@
+From d56d25cad719aa50d8cf0be072a118b15f606590 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Thu, 15 Feb 2018 13:01:28 +0100
+Subject: [PATCH 0865/1795] pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins,
+ groups and functions
+
+This patch adds VIN4 and VIN5 pins, groups and functions for the
+R8A7796 SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8db6cbabac4f2a02ccbce1dbf6845245f38d11f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 454 +++++++++++++++++++++++++++
+ 1 file changed, 454 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index ad4a7883518a..e6fff5518a97 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -3896,6 +3896,400 @@ static const unsigned int usb30_mux[] = {
+ 	USB30_PWEN_MARK, USB30_OVC_MARK,
+ };
+ 
++/* - VIN4 ------------------------------------------------------------------- */
++static const unsigned int vin4_data8_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int vin4_data8_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++};
++static const unsigned int vin4_data8_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++};
++static const unsigned int vin4_data8_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++};
++static const unsigned int vin4_data10_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++};
++static const unsigned int vin4_data10_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++};
++static const unsigned int vin4_data10_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++};
++static const unsigned int vin4_data10_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++};
++static const unsigned int vin4_data12_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++};
++static const unsigned int vin4_data12_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++};
++static const unsigned int vin4_data12_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++};
++static const unsigned int vin4_data12_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++};
++static const unsigned int vin4_data16_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin4_data16_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++};
++static const unsigned int vin4_data16_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin4_data16_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++};
++static const unsigned int vin4_data18_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++};
++static const unsigned int vin4_data18_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++};
++static const unsigned int vin4_data18_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++};
++static const unsigned int vin4_data18_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++};
++static const unsigned int vin4_data20_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int vin4_data20_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++};
++static const unsigned int vin4_data20_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int vin4_data20_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++};
++static const unsigned int vin4_data24_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin4_data24_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
++};
++static const unsigned int vin4_data24_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin4_data24_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
++};
++static const unsigned int vin4_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
++};
++static const unsigned int vin4_sync_mux[] = {
++	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
++};
++static const unsigned int vin4_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(1, 16),
++};
++static const unsigned int vin4_field_mux[] = {
++	VI4_FIELD_MARK,
++};
++static const unsigned int vin4_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int vin4_clkenb_mux[] = {
++	VI4_CLKENB_MARK,
++};
++static const unsigned int vin4_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 27),
++};
++static const unsigned int vin4_clk_mux[] = {
++	VI4_CLK_MARK,
++};
++
++/* - VIN5 ------------------------------------------------------------------- */
++static const unsigned int vin5_data8_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin5_data8_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++};
++static const unsigned int vin5_data10_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++};
++static const unsigned int vin5_data10_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++};
++static const unsigned int vin5_data12_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
++};
++static const unsigned int vin5_data12_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++	VI5_DATA10_MARK, VI5_DATA11_MARK,
++};
++static const unsigned int vin5_data16_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin5_data16_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++	VI5_DATA10_MARK, VI5_DATA11_MARK,
++	VI5_DATA12_MARK, VI5_DATA13_MARK,
++	VI5_DATA14_MARK, VI5_DATA15_MARK,
++};
++static const unsigned int vin5_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
++};
++static const unsigned int vin5_sync_mux[] = {
++	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
++};
++static const unsigned int vin5_field_pins[] = {
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int vin5_field_mux[] = {
++	/* FIELD */
++	VI5_FIELD_MARK,
++};
++static const unsigned int vin5_clkenb_pins[] = {
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int vin5_clkenb_mux[] = {
++	/* CLKENB */
++	VI5_CLKENB_MARK,
++};
++static const unsigned int vin5_clk_pins[] = {
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int vin5_clk_mux[] = {
++	/* CLK */
++	VI5_CLK_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(audio_clk_a_a),
+ 	SH_PFC_PIN_GROUP(audio_clk_a_b),
+@@ -4210,6 +4604,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb30),
++	SH_PFC_PIN_GROUP(vin4_data8_a),
++	SH_PFC_PIN_GROUP(vin4_data10_a),
++	SH_PFC_PIN_GROUP(vin4_data12_a),
++	SH_PFC_PIN_GROUP(vin4_data16_a),
++	SH_PFC_PIN_GROUP(vin4_data18_a),
++	SH_PFC_PIN_GROUP(vin4_data20_a),
++	SH_PFC_PIN_GROUP(vin4_data24_a),
++	SH_PFC_PIN_GROUP(vin4_data8_b),
++	SH_PFC_PIN_GROUP(vin4_data10_b),
++	SH_PFC_PIN_GROUP(vin4_data12_b),
++	SH_PFC_PIN_GROUP(vin4_data16_b),
++	SH_PFC_PIN_GROUP(vin4_data18_b),
++	SH_PFC_PIN_GROUP(vin4_data20_b),
++	SH_PFC_PIN_GROUP(vin4_data24_b),
++	SH_PFC_PIN_GROUP(vin4_sync),
++	SH_PFC_PIN_GROUP(vin4_field),
++	SH_PFC_PIN_GROUP(vin4_clkenb),
++	SH_PFC_PIN_GROUP(vin4_clk),
++	SH_PFC_PIN_GROUP(vin5_data8),
++	SH_PFC_PIN_GROUP(vin5_data10),
++	SH_PFC_PIN_GROUP(vin5_data12),
++	SH_PFC_PIN_GROUP(vin5_data16),
++	SH_PFC_PIN_GROUP(vin5_sync),
++	SH_PFC_PIN_GROUP(vin5_field),
++	SH_PFC_PIN_GROUP(vin5_clkenb),
++	SH_PFC_PIN_GROUP(vin5_clk),
+ };
+ 
+ static const char * const audio_clk_groups[] = {
+@@ -4672,6 +5092,38 @@ static const char * const usb30_groups[] = {
+ 	"usb30",
+ };
+ 
++static const char * const vin4_groups[] = {
++	"vin4_data8_a",
++	"vin4_data10_a",
++	"vin4_data12_a",
++	"vin4_data16_a",
++	"vin4_data18_a",
++	"vin4_data20_a",
++	"vin4_data24_a",
++	"vin4_data8_b",
++	"vin4_data10_b",
++	"vin4_data12_b",
++	"vin4_data16_b",
++	"vin4_data18_b",
++	"vin4_data20_b",
++	"vin4_data24_b",
++	"vin4_sync",
++	"vin4_field",
++	"vin4_clkenb",
++	"vin4_clk",
++};
++
++static const char * const vin5_groups[] = {
++	"vin5_data8",
++	"vin5_data10",
++	"vin5_data12",
++	"vin5_data16",
++	"vin5_sync",
++	"vin5_field",
++	"vin5_clkenb",
++	"vin5_clk",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
+@@ -4722,6 +5174,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb30),
++	SH_PFC_FUNCTION(vin4),
++	SH_PFC_FUNCTION(vin5),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0866-pinctrl-sh-pfc-r8a7795-Add-VIN4-VIN5-pins-groups-and.patch b/patches/0866-pinctrl-sh-pfc-r8a7795-Add-VIN4-VIN5-pins-groups-and.patch
new file mode 100644
index 00000000000000..368c78f2905cba
--- /dev/null
+++ b/patches/0866-pinctrl-sh-pfc-r8a7795-Add-VIN4-VIN5-pins-groups-and.patch
@@ -0,0 +1,507 @@
+From 39efd5a29333a810e4cf72f1f6bf677b3c3cbba7 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Thu, 15 Feb 2018 13:01:29 +0100
+Subject: [PATCH 0866/1795] pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins,
+ groups and functions
+
+This patch adds VIN4 and VIN5 pins, groups and functions for the
+R8A7795 SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6b4de408105fc51e85e55937e049503f30f8c633)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 454 +++++++++++++++++++++++++++
+ 1 file changed, 454 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 4898676ad79b..706ffe153087 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3927,6 +3927,400 @@ static const unsigned int usb30_mux[] = {
+ 	USB30_PWEN_MARK, USB30_OVC_MARK,
+ };
+ 
++/* - VIN4 ------------------------------------------------------------------- */
++static const unsigned int vin4_data8_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int vin4_data8_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++};
++static const unsigned int vin4_data8_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++};
++static const unsigned int vin4_data8_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++};
++static const unsigned int vin4_data10_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++};
++static const unsigned int vin4_data10_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++};
++static const unsigned int vin4_data10_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++};
++static const unsigned int vin4_data10_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++};
++static const unsigned int vin4_data12_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++};
++static const unsigned int vin4_data12_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++};
++static const unsigned int vin4_data12_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++};
++static const unsigned int vin4_data12_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++};
++static const unsigned int vin4_data16_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin4_data16_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++};
++static const unsigned int vin4_data16_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin4_data16_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++};
++static const unsigned int vin4_data18_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++};
++static const unsigned int vin4_data18_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++};
++static const unsigned int vin4_data18_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++};
++static const unsigned int vin4_data18_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++};
++static const unsigned int vin4_data20_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int vin4_data20_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++};
++static const unsigned int vin4_data20_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int vin4_data20_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++};
++static const unsigned int vin4_data24_a_pins[] = {
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin4_data24_a_mux[] = {
++	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
++};
++static const unsigned int vin4_data24_b_pins[] = {
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin4_data24_b_mux[] = {
++	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
++};
++static const unsigned int vin4_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
++};
++static const unsigned int vin4_sync_mux[] = {
++	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
++};
++static const unsigned int vin4_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(1, 16),
++};
++static const unsigned int vin4_field_mux[] = {
++	VI4_FIELD_MARK,
++};
++static const unsigned int vin4_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int vin4_clkenb_mux[] = {
++	VI4_CLKENB_MARK,
++};
++static const unsigned int vin4_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 27),
++};
++static const unsigned int vin4_clk_mux[] = {
++	VI4_CLK_MARK,
++};
++
++/* - VIN5 ------------------------------------------------------------------- */
++static const unsigned int vin5_data8_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int vin5_data8_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++};
++static const unsigned int vin5_data10_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++};
++static const unsigned int vin5_data10_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++};
++static const unsigned int vin5_data12_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
++};
++static const unsigned int vin5_data12_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++	VI5_DATA10_MARK, VI5_DATA11_MARK,
++};
++static const unsigned int vin5_data16_pins[] = {
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++static const unsigned int vin5_data16_mux[] = {
++	VI5_DATA0_MARK, VI5_DATA1_MARK,
++	VI5_DATA2_MARK, VI5_DATA3_MARK,
++	VI5_DATA4_MARK, VI5_DATA5_MARK,
++	VI5_DATA6_MARK, VI5_DATA7_MARK,
++	VI5_DATA8_MARK,  VI5_DATA9_MARK,
++	VI5_DATA10_MARK, VI5_DATA11_MARK,
++	VI5_DATA12_MARK, VI5_DATA13_MARK,
++	VI5_DATA14_MARK, VI5_DATA15_MARK,
++};
++static const unsigned int vin5_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
++};
++static const unsigned int vin5_sync_mux[] = {
++	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
++};
++static const unsigned int vin5_field_pins[] = {
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int vin5_field_mux[] = {
++	/* FIELD */
++	VI5_FIELD_MARK,
++};
++static const unsigned int vin5_clkenb_pins[] = {
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int vin5_clkenb_mux[] = {
++	/* CLKENB */
++	VI5_CLKENB_MARK,
++};
++static const unsigned int vin5_clk_pins[] = {
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int vin5_clk_mux[] = {
++	/* CLK */
++	VI5_CLK_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(audio_clk_a_a),
+ 	SH_PFC_PIN_GROUP(audio_clk_a_b),
+@@ -4246,6 +4640,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb2),
+ 	SH_PFC_PIN_GROUP(usb2_ch3),
+ 	SH_PFC_PIN_GROUP(usb30),
++	SH_PFC_PIN_GROUP(vin4_data8_a),
++	SH_PFC_PIN_GROUP(vin4_data10_a),
++	SH_PFC_PIN_GROUP(vin4_data12_a),
++	SH_PFC_PIN_GROUP(vin4_data16_a),
++	SH_PFC_PIN_GROUP(vin4_data18_a),
++	SH_PFC_PIN_GROUP(vin4_data20_a),
++	SH_PFC_PIN_GROUP(vin4_data24_a),
++	SH_PFC_PIN_GROUP(vin4_data8_b),
++	SH_PFC_PIN_GROUP(vin4_data10_b),
++	SH_PFC_PIN_GROUP(vin4_data12_b),
++	SH_PFC_PIN_GROUP(vin4_data16_b),
++	SH_PFC_PIN_GROUP(vin4_data18_b),
++	SH_PFC_PIN_GROUP(vin4_data20_b),
++	SH_PFC_PIN_GROUP(vin4_data24_b),
++	SH_PFC_PIN_GROUP(vin4_sync),
++	SH_PFC_PIN_GROUP(vin4_field),
++	SH_PFC_PIN_GROUP(vin4_clkenb),
++	SH_PFC_PIN_GROUP(vin4_clk),
++	SH_PFC_PIN_GROUP(vin5_data8),
++	SH_PFC_PIN_GROUP(vin5_data10),
++	SH_PFC_PIN_GROUP(vin5_data12),
++	SH_PFC_PIN_GROUP(vin5_data16),
++	SH_PFC_PIN_GROUP(vin5_sync),
++	SH_PFC_PIN_GROUP(vin5_field),
++	SH_PFC_PIN_GROUP(vin5_clkenb),
++	SH_PFC_PIN_GROUP(vin5_clk),
+ };
+ 
+ static const char * const audio_clk_groups[] = {
+@@ -4725,6 +5145,38 @@ static const char * const usb30_groups[] = {
+ 	"usb30",
+ };
+ 
++static const char * const vin4_groups[] = {
++	"vin4_data8_a",
++	"vin4_data10_a",
++	"vin4_data12_a",
++	"vin4_data16_a",
++	"vin4_data18_a",
++	"vin4_data20_a",
++	"vin4_data24_a",
++	"vin4_data8_b",
++	"vin4_data10_b",
++	"vin4_data12_b",
++	"vin4_data16_b",
++	"vin4_data18_b",
++	"vin4_data20_b",
++	"vin4_data24_b",
++	"vin4_sync",
++	"vin4_field",
++	"vin4_clkenb",
++	"vin4_clk",
++};
++
++static const char * const vin5_groups[] = {
++	"vin5_data8",
++	"vin5_data10",
++	"vin5_data12",
++	"vin5_data16",
++	"vin5_sync",
++	"vin5_field",
++	"vin5_clkenb",
++	"vin5_clk",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb),
+@@ -4779,6 +5231,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(usb2),
+ 	SH_PFC_FUNCTION(usb2_ch3),
+ 	SH_PFC_FUNCTION(usb30),
++	SH_PFC_FUNCTION(vin4),
++	SH_PFC_FUNCTION(vin5),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0867-pinctrl-sh-pfc-r8a77995-Add-VIN4-pins-groups-and-fun.patch b/patches/0867-pinctrl-sh-pfc-r8a77995-Add-VIN4-pins-groups-and-fun.patch
new file mode 100644
index 00000000000000..c59e1df8ca0ccd
--- /dev/null
+++ b/patches/0867-pinctrl-sh-pfc-r8a77995-Add-VIN4-pins-groups-and-fun.patch
@@ -0,0 +1,245 @@
+From 6243925c2687c92ab4d1d31055f13522708307da Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Thu, 15 Feb 2018 13:01:30 +0100
+Subject: [PATCH 0867/1795] pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups
+ and function
+
+This patch adds VIN4 pins, groups and function for the
+R8A77995 (D3) SoC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit fbd452aeb49e552e7278c25c63198caa918deb04)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 192 ++++++++++++++++++++++++++
+ 1 file changed, 192 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 1d42d2534375..27b9417be59b 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1626,6 +1626,172 @@ static const unsigned int usb0_mux[] = {
+ 	USB0_PWEN_MARK, USB0_OVC_MARK,
+ };
+ 
++/* - VIN4 ------------------------------------------------------------------- */
++static const unsigned int vin4_data8_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++};
++static const unsigned int vin4_data8_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++};
++static const unsigned int vin4_data10_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int vin4_data10_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++};
++static const unsigned int vin4_data12_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++};
++static const unsigned int vin4_data12_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++};
++static const unsigned int vin4_data16_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
++	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++};
++static const unsigned int vin4_data16_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++};
++static const unsigned int vin4_data18_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
++	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++};
++static const unsigned int vin4_data18_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++};
++static const unsigned int vin4_data20_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
++	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++};
++static const unsigned int vin4_data20_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++};
++static const unsigned int vin4_data24_pins[] = {
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
++	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++};
++static const unsigned int vin4_data24_mux[] = {
++	VI4_DATA0_MARK, VI4_DATA1_MARK,
++	VI4_DATA2_MARK, VI4_DATA3_MARK,
++	VI4_DATA4_MARK, VI4_DATA5_MARK,
++	VI4_DATA6_MARK, VI4_DATA7_MARK,
++	VI4_DATA8_MARK,  VI4_DATA9_MARK,
++	VI4_DATA10_MARK, VI4_DATA11_MARK,
++	VI4_DATA12_MARK, VI4_DATA13_MARK,
++	VI4_DATA14_MARK, VI4_DATA15_MARK,
++	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
++};
++static const unsigned int vin4_sync_pins[] = {
++	/* HSYNC#, VSYNC# */
++	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
++};
++static const unsigned int vin4_sync_mux[] = {
++	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
++};
++static const unsigned int vin4_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(2, 27),
++};
++static const unsigned int vin4_field_mux[] = {
++	VI4_FIELD_MARK,
++};
++static const unsigned int vin4_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(2, 28),
++};
++static const unsigned int vin4_clkenb_mux[] = {
++	VI4_CLKENB_MARK,
++};
++static const unsigned int vin4_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int vin4_clk_mux[] = {
++	VI4_CLK_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(audio_clk_a),
+ 	SH_PFC_PIN_GROUP(audio_clk_b),
+@@ -1711,6 +1877,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+ 	SH_PFC_PIN_GROUP(ssi4_data_b),
+ 	SH_PFC_PIN_GROUP(usb0),
++	SH_PFC_PIN_GROUP(vin4_data8),
++	SH_PFC_PIN_GROUP(vin4_data10),
++	SH_PFC_PIN_GROUP(vin4_data12),
++	SH_PFC_PIN_GROUP(vin4_data16),
++	SH_PFC_PIN_GROUP(vin4_data18),
++	SH_PFC_PIN_GROUP(vin4_data20),
++	SH_PFC_PIN_GROUP(vin4_data24),
++	SH_PFC_PIN_GROUP(vin4_sync),
++	SH_PFC_PIN_GROUP(vin4_field),
++	SH_PFC_PIN_GROUP(vin4_clkenb),
++	SH_PFC_PIN_GROUP(vin4_clk),
+ };
+ 
+ static const char * const audio_clk_groups[] = {
+@@ -1871,6 +2048,20 @@ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+ 
++static const char * const vin4_groups[] = {
++	"vin4_data8",
++	"vin4_data10",
++	"vin4_data12",
++	"vin4_data16",
++	"vin4_data18",
++	"vin4_data20",
++	"vin4_data24",
++	"vin4_sync",
++	"vin4_field",
++	"vin4_clkenb",
++	"vin4_clk",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(audio_clk),
+ 	SH_PFC_FUNCTION(avb0),
+@@ -1898,6 +2089,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif_clk),
+ 	SH_PFC_FUNCTION(ssi),
+ 	SH_PFC_FUNCTION(usb0),
++	SH_PFC_FUNCTION(vin4),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0868-pinctrl-sh-pfc-r8a77965-Add-support-for-INTC-EX-IRQ-.patch b/patches/0868-pinctrl-sh-pfc-r8a77965-Add-support-for-INTC-EX-IRQ-.patch
new file mode 100644
index 00000000000000..50c21b34610e67
--- /dev/null
+++ b/patches/0868-pinctrl-sh-pfc-r8a77965-Add-support-for-INTC-EX-IRQ-.patch
@@ -0,0 +1,121 @@
+From 17d1f20122208951e8afb2f617f085836da2df5d Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 26 Feb 2018 16:30:11 +0100
+Subject: [PATCH 0868/1795] pinctrl: sh-pfc: r8a77965: Add support for INTC-EX
+ IRQ pins
+
+Most pins on the R8A77965 SoC can be configured in GPIO mode for
+interrupt and GPIO functionality, while a couple of them can also
+be routed to the INTC-EX hardware block (formerly known as IRQC).
+
+On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
+this patch adds support for them to the PFC driver as "intc_ex_irqN".
+
+Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
+<damm+renesas@opensource.se>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a8ab4f2bd8a5298679dabe16910322625a0df247)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 61 +++++++++++++++++++++++++++
+ 1 file changed, 61 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index acd57d5b2fb1..363ccc3b1bdc 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1661,6 +1661,51 @@ static const unsigned int avb_avtp_capture_b_pins[] = {
+ static const unsigned int avb_avtp_capture_b_mux[] = {
+ 	AVB_AVTP_CAPTURE_B_MARK,
+ };
++
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -1883,6 +1928,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
+ 	SH_PFC_PIN_GROUP(scif0_data),
+ 	SH_PFC_PIN_GROUP(scif0_clk),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl),
+@@ -1927,6 +1978,15 @@ static const char * const avb_groups[] = {
+ 	"avb_avtp_capture_b",
+ };
+ 
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data",
+ 	"scif0_clk",
+@@ -1978,6 +2038,7 @@ static const char * const scif_clk_groups[] = {
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(intc_ex),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/0869-pinctrl-sh-pfc-r8a77965-Add-USB2.0-host-pins-groups-.patch b/patches/0869-pinctrl-sh-pfc-r8a77965-Add-USB2.0-host-pins-groups-.patch
new file mode 100644
index 00000000000000..b631ecb548f5f6
--- /dev/null
+++ b/patches/0869-pinctrl-sh-pfc-r8a77965-Add-USB2.0-host-pins-groups-.patch
@@ -0,0 +1,86 @@
+From 8d76055f6c1e40f996a3cb7474a73b56431c81cc Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Tue, 27 Feb 2018 17:08:01 +0900
+Subject: [PATCH 0869/1795] pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins,
+ groups and functions
+
+This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to
+the R8A77965 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0d75f8dae3e1a086f72a887b2053dfd0de70c9cd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 32 +++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 363ccc3b1bdc..f669944e0f70 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1917,6 +1917,26 @@ static const unsigned int scif_clk_b_mux[] = {
+ 	SCIF_CLK_B_MARK,
+ };
+ 
++/* - USB0 ------------------------------------------------------------------- */
++static const unsigned int usb0_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
++};
++
++static const unsigned int usb0_mux[] = {
++	USB0_PWEN_MARK, USB0_OVC_MARK,
++};
++
++/* - USB1 ------------------------------------------------------------------- */
++static const unsigned int usb1_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
++};
++
++static const unsigned int usb1_mux[] = {
++	USB1_PWEN_MARK, USB1_OVC_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+@@ -1963,6 +1983,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif5_clk_b),
+ 	SH_PFC_PIN_GROUP(scif_clk_a),
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(usb0),
++	SH_PFC_PIN_GROUP(usb1),
+ };
+ 
+ static const char * const avb_groups[] = {
+@@ -2036,6 +2058,14 @@ static const char * const scif_clk_groups[] = {
+ 	"scif_clk_b",
+ };
+ 
++static const char * const usb0_groups[] = {
++	"usb0",
++};
++
++static const char * const usb1_groups[] = {
++	"usb1",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(intc_ex),
+@@ -2046,6 +2076,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif4),
+ 	SH_PFC_FUNCTION(scif5),
+ 	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(usb0),
++	SH_PFC_FUNCTION(usb1),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0870-pinctrl-sh-pfc-r8a77965-Add-USB3.0-host-pins-groups-.patch b/patches/0870-pinctrl-sh-pfc-r8a77965-Add-USB3.0-host-pins-groups-.patch
new file mode 100644
index 00000000000000..3f1cfcd8171866
--- /dev/null
+++ b/patches/0870-pinctrl-sh-pfc-r8a77965-Add-USB3.0-host-pins-groups-.patch
@@ -0,0 +1,70 @@
+From 55c05f0737600c0467001a83c5ba1fc5110e3111 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Tue, 27 Feb 2018 17:08:02 +0900
+Subject: [PATCH 0870/1795] pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins,
+ groups and functions
+
+This patch adds USB30 (USB3.0 host) pin, group and function to
+the R8A77965 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c490b28f36ac225799df3f36eca03b4801bd0eec)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index f669944e0f70..ce2e85033ff4 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1937,6 +1937,16 @@ static const unsigned int usb1_mux[] = {
+ 	USB1_PWEN_MARK, USB1_OVC_MARK,
+ };
+ 
++/* - USB30 ------------------------------------------------------------------ */
++static const unsigned int usb30_pins[] = {
++	/* PWEN, OVC */
++	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
++};
++
++static const unsigned int usb30_mux[] = {
++	USB30_PWEN_MARK, USB30_OVC_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+@@ -1985,6 +1995,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
++	SH_PFC_PIN_GROUP(usb30),
+ };
+ 
+ static const char * const avb_groups[] = {
+@@ -2066,6 +2077,10 @@ static const char * const usb1_groups[] = {
+ 	"usb1",
+ };
+ 
++static const char * const usb30_groups[] = {
++	"usb30",
++};
++
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(intc_ex),
+@@ -2078,6 +2093,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif_clk),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
++	SH_PFC_FUNCTION(usb30),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/0871-pinctrl-sh-pfc-Add-PORT_GP_CFG_25-helper-macro.patch b/patches/0871-pinctrl-sh-pfc-Add-PORT_GP_CFG_25-helper-macro.patch
new file mode 100644
index 00000000000000..7c96b6f8328d7e
--- /dev/null
+++ b/patches/0871-pinctrl-sh-pfc-Add-PORT_GP_CFG_25-helper-macro.patch
@@ -0,0 +1,43 @@
+From 0d3ad13314c749d09bc1b3c229376a8d15c73bf1 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 8 Mar 2018 22:12:47 +0300
+Subject: [PATCH 0871/1795] pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macro
+
+They follow the style of the existing PORT_GP_CFG_<n>() macros and
+will be used by a follow-up patch for the R8A77980 SoC.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c21a3e30e88bd2084891a2c4cf6278ebc5304dcb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 7253a8cbb0ea..05a3ff81e4a4 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -471,9 +471,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
+ 	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
+ #define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)
+ 
+-#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
++#define PORT_GP_CFG_25(bank, fn, sfx, cfg)				\
+ 	PORT_GP_CFG_24(bank, fn, sfx, cfg),				\
+-	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg),				\
++	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
++#define PORT_GP_25(bank, fn, sfx)	PORT_GP_CFG_25(bank, fn, sfx, 0)
++
++#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
++	PORT_GP_CFG_25(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
+ #define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)
+ 
+-- 
+2.19.0
+
diff --git a/patches/0872-pinctrl-sh-pfc-Add-R8A77980-PFC-support.patch b/patches/0872-pinctrl-sh-pfc-Add-R8A77980-PFC-support.patch
new file mode 100644
index 00000000000000..f1c6d4ecbd98e0
--- /dev/null
+++ b/patches/0872-pinctrl-sh-pfc-Add-R8A77980-PFC-support.patch
@@ -0,0 +1,2905 @@
+From 75f62b686f4c055d9ff42a7219ce738c4cbf8517 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 8 Mar 2018 22:14:32 +0300
+Subject: [PATCH 0872/1795] pinctrl: sh-pfc: Add R8A77980 PFC support
+
+Add the PFC support for the R8A77980 SoC including pin groups for some
+on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC,
+MSIOF, PWM, and VIN...
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f59125248a691dfef62f0450ce7b0238b63b6dbd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/pinctrl/renesas,pfc-pinctrl.txt  |    1 +
+ drivers/pinctrl/sh-pfc/Kconfig                |    5 +
+ drivers/pinctrl/sh-pfc/Makefile               |    1 +
+ drivers/pinctrl/sh-pfc/core.c                 |    6 +
+ drivers/pinctrl/sh-pfc/pfc-r8a77980.c         | 2799 +++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h               |    1 +
+ 6 files changed, 2813 insertions(+)
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index bd5370a71666..892d8fd7b700 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -26,6 +26,7 @@ Required Properties:
+     - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
+     - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
+     - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
++    - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
+     - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
+     - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+ 
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index 0621cb51c016..c11b789ec583 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -99,6 +99,11 @@ config PINCTRL_PFC_R8A77970
+ 	depends on ARCH_R8A77970
+ 	select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A77980
++	def_bool y
++	depends on ARCH_R8A77980
++	select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_R8A77995
+         def_bool y
+         depends on ARCH_R8A77995
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index 05b4379f0c98..463775f28cf1 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795-es1.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77965)	+= pfc-r8a77965.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77970)	+= pfc-r8a77970.o
++obj-$(CONFIG_PINCTRL_PFC_R8A77980)	+= pfc-r8a77980.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 7461af941659..74861b7b5b0d 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -569,6 +569,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 		.data = &r8a77970_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A77980
++	{
++		.compatible = "renesas,pfc-r8a77980",
++		.data = &r8a77980_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_R8A77995
+ 	{
+ 		.compatible = "renesas,pfc-r8a77995",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+new file mode 100644
+index 000000000000..84c8f1c2f1d1
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+@@ -0,0 +1,2799 @@
++// SPDX-Lincense-Identifier: GPL 2.0
++/*
++ * R8A77980 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++ *
++ * R-Car Gen3 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2015 Renesas Electronics Corporation
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++
++#include "core.h"
++#include "sh_pfc.h"
++
++#define CPU_ALL_PORT(fn, sfx)	\
++	PORT_GP_22(0, fn, sfx),	\
++	PORT_GP_28(1, fn, sfx),	\
++	PORT_GP_30(2, fn, sfx),	\
++	PORT_GP_17(3, fn, sfx),	\
++	PORT_GP_25(4, fn, sfx),	\
++	PORT_GP_15(5, fn, sfx)
++
++/*
++ * F_() : just information
++ * FM() : macro for FN_xxx / xxx_MARK
++ */
++
++/* GPSR0 */
++#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
++#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
++#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
++#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
++#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
++#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
++#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
++#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
++#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
++#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
++#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
++#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
++#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
++#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
++#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
++#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
++#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
++#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
++#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
++#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
++#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
++#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
++
++/* GPSR1 */
++#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
++#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
++#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20)
++#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
++#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
++#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
++#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
++#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
++#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
++#define GPSR1_18	FM(AVB_LINK)
++#define GPSR1_17	FM(AVB_PHY_INT)
++#define GPSR1_16	FM(AVB_MAGIC)
++#define GPSR1_15	FM(AVB_MDC)
++#define GPSR1_14	FM(AVB_MDIO)
++#define GPSR1_13	FM(AVB_TXCREFCLK)
++#define GPSR1_12	FM(AVB_TD3)
++#define GPSR1_11	FM(AVB_TD2)
++#define GPSR1_10	FM(AVB_TD1)
++#define GPSR1_9		FM(AVB_TD0)
++#define GPSR1_8		FM(AVB_TXC)
++#define GPSR1_7		FM(AVB_TX_CTL)
++#define GPSR1_6		FM(AVB_RD3)
++#define GPSR1_5		FM(AVB_RD2)
++#define GPSR1_4		FM(AVB_RD1)
++#define GPSR1_3		FM(AVB_RD0)
++#define GPSR1_2		FM(AVB_RXC)
++#define GPSR1_1		FM(AVB_RX_CTL)
++#define GPSR1_0		F_(IRQ0,		IP2_27_24)
++
++/* GPSR2 */
++#define GPSR2_29	F_(FSO_TOE_N,  		IP10_19_16)
++#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
++#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
++#define GPSR2_26	F_(SDA3,		IP10_7_4)
++#define GPSR2_25	F_(SCL3,		IP10_3_0)
++#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
++#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
++#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
++#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
++#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
++#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
++#define GPSR2_18	F_(IRQ5,		IP9_7_4)
++#define GPSR2_17	F_(IRQ4,		IP9_3_0)
++#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
++#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
++#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
++#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
++#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
++#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
++#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
++#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
++#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
++#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
++#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
++#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
++#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
++#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
++#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
++#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
++#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
++
++/* GPSR3 */
++#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
++#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
++#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
++#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
++#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
++#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
++#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
++#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
++#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
++#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
++#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
++#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
++#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
++#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
++#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
++#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
++#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
++
++/* GPSR4 */
++#define GPSR4_24	FM(GETHER_LINK_A)
++#define GPSR4_23	FM(GETHER_PHY_INT_A)
++#define GPSR4_22	FM(GETHER_MAGIC)
++#define GPSR4_21	FM(GETHER_MDC_A)
++#define GPSR4_20	FM(GETHER_MDIO_A)
++#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
++#define GPSR4_18	FM(GETHER_TXCREFCLK)
++#define GPSR4_17	FM(GETHER_TD3)
++#define GPSR4_16	FM(GETHER_TD2)
++#define GPSR4_15	FM(GETHER_TD1)
++#define GPSR4_14	FM(GETHER_TD0)
++#define GPSR4_13	FM(GETHER_TXC)
++#define GPSR4_12	FM(GETHER_TX_CTL)
++#define GPSR4_11	FM(GETHER_RD3)
++#define GPSR4_10	FM(GETHER_RD2)
++#define GPSR4_9		FM(GETHER_RD1)
++#define GPSR4_8		FM(GETHER_RD0)
++#define GPSR4_7		FM(GETHER_RXC)
++#define GPSR4_6		FM(GETHER_RX_CTL)
++#define GPSR4_5		F_(SDA2,		IP7_27_24)
++#define GPSR4_4		F_(SCL2,		IP7_23_20)
++#define GPSR4_3		F_(SDA1,		IP7_19_16)
++#define GPSR4_2		F_(SCL1,		IP7_15_12)
++#define GPSR4_1		F_(SDA0,		IP7_11_8)
++#define GPSR4_0		F_(SCL0,		IP7_7_4)
++
++/* GPSR5 */
++#define GPSR5_14	FM(RPC_INT_N)
++#define GPSR5_13	FM(RPC_WP_N)
++#define GPSR5_12	FM(RPC_RESET_N)
++#define GPSR5_11	FM(QSPI1_SSL)
++#define GPSR5_10	FM(QSPI1_IO3)
++#define GPSR5_9		FM(QSPI1_IO2)
++#define GPSR5_8		FM(QSPI1_MISO_IO1)
++#define GPSR5_7		FM(QSPI1_MOSI_IO0)
++#define GPSR5_6		FM(QSPI1_SPCLK)
++#define GPSR5_5		FM(QSPI0_SSL)
++#define GPSR5_4		FM(QSPI0_IO3)
++#define GPSR5_3		FM(QSPI0_IO2)
++#define GPSR5_2		FM(QSPI0_MISO_IO1)
++#define GPSR5_1		FM(QSPI0_MOSI_IO0)
++#define GPSR5_0		FM(QSPI0_SPCLK)
++
++
++/* IPSRx */		/* 0 */				/* 1 */			/* 2 */			/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
++#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)	FM(A0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)	FM(A1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)	FM(A2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)	FM(A3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N_TANS)		FM(GETHER_RMII_TXD_EN)	FM(A4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)	FM(A5)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)	FM(A6)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)	FM(A7)		FM(PWMFSW0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)		FM(A8)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)	FM(A9)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)	FM(A10)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)		FM(A11)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)		FM(A12)		FM(IRQ1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)		FM(A13)		FM(IRQ2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)		FM(A14)		FM(IRQ3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)		FM(A15)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)		FM(A16)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)		FM(A17)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)	FM(A18)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)	FM(A19)		FM(FXR_TXENA_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_27_24	FM(IRQ0)			FM(CC5_OSCOUT)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)			FM(RD_WR_N)	FM(HCTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)			F_(0, 0)	FM(HRTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)		F_(0, 0)	FM(HTX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N_TANS)		F_(0, 0)	FM(HRX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N_TANS)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)		FM(CS1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)		FM(CS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)		FM(D0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)		FM(D1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)		FM(D2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)		FM(D3)		FM(MMC_WP)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)		FM(D4)		FM(MMC_CD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)		FM(D5)		FM(MMC_DS)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)		FM(D6)		FM(MMC_CMD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)		FM(D7)		FM(MMC_D0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)		FM(D8)		FM(MMC_D1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)		FM(D9)		FM(MMC_D2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)		FM(D10)		FM(MMC_D3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)		FM(D11)		FM(MMC_CLK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)		FM(D12)		FM(MMC_D4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)		FM(D13)		FM(MMC_D5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)		FM(D14)		FM(MMC_D6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)		FM(D15)		FM(MMC_D7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)		FM(CLKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)		FM(BS_N)	FM(SCK0)	FM(HSCK0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)		FM(RD_N)	FM(CTS0_N)	FM(HCTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)		FM(WE0_N)	FM(RTS0_N_TANS)	FM(HRTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)		FM(WE1_N)	FM(RX0)		FM(HRX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)		FM(EX_WAIT0)	FM(TX0)		FM(HTX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)		FM(DU_DISP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)		FM(DU_CDE)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)		FM(TCLK1_B)	FM(TX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)		FM(TCLK2_B)	FM(RX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_23_20	FM(CANFD_CLK_A) 		FM(CLK_EXTFXR)		FM(PWM4_B)		FM(SPEEDIN_B)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA12)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_7_4 	FM(IRQ5)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA13)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)		FM(VI0_DATA14)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)		FM(VI0_DATA15)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)		FM(VI0_DATA16)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)		FM(VI0_DATA17)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)		FM(VI0_DATA18)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)		FM(VI0_DATA19)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA20)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA21)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++#define PINMUX_GPSR	\
++\
++				GPSR2_29 \
++				GPSR2_28 \
++		GPSR1_27	GPSR2_27 \
++		GPSR1_26	GPSR2_26 \
++		GPSR1_25	GPSR2_25 \
++		GPSR1_24	GPSR2_24			GPSR4_24 \
++		GPSR1_23	GPSR2_23			GPSR4_23 \
++		GPSR1_22	GPSR2_22			GPSR4_22 \
++GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
++GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
++GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
++GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
++GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
++GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
++GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
++GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
++GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
++GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
++GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
++GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
++GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
++GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
++GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
++GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
++GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
++GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
++GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
++GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
++GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
++GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
++
++#define PINMUX_IPSR	\
++\
++FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
++FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
++FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
++FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
++FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
++FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
++FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
++FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
++\
++FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
++FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
++FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
++FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
++FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
++FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
++FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
++FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
++\
++FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
++FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
++FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
++FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
++FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
++FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \
++FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \
++FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28
++
++/* MOD_SEL0 */		/* 0 */			/* 1 */
++#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
++#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
++#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
++#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
++#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
++#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
++#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
++#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
++#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
++#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
++#define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
++
++#define PINMUX_MOD_SELS \
++\
++MOD_SEL0_11 \
++MOD_SEL0_10 \
++MOD_SEL0_9 \
++MOD_SEL0_8 \
++MOD_SEL0_7 \
++MOD_SEL0_6 \
++MOD_SEL0_5 \
++MOD_SEL0_4 \
++MOD_SEL0_2 \
++MOD_SEL0_1 \
++MOD_SEL0_0
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++#define F_(x, y)
++#define FM(x)   FN_##x,
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_FUNCTION_END,
++#undef F_
++#undef FM
++
++#define F_(x, y)
++#define FM(x)	x##_MARK,
++	PINMUX_MARK_BEGIN,
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_MARK_END,
++#undef F_
++#undef FM
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(),
++
++	PINMUX_SINGLE(AVB_RX_CTL),
++	PINMUX_SINGLE(AVB_RXC),
++	PINMUX_SINGLE(AVB_RD0),
++	PINMUX_SINGLE(AVB_RD1),
++	PINMUX_SINGLE(AVB_RD2),
++	PINMUX_SINGLE(AVB_RD3),
++	PINMUX_SINGLE(AVB_TX_CTL),
++	PINMUX_SINGLE(AVB_TXC),
++	PINMUX_SINGLE(AVB_TD0),
++	PINMUX_SINGLE(AVB_TD1),
++	PINMUX_SINGLE(AVB_TD2),
++	PINMUX_SINGLE(AVB_TD3),
++	PINMUX_SINGLE(AVB_TXCREFCLK),
++	PINMUX_SINGLE(AVB_MDIO),
++	PINMUX_SINGLE(AVB_MDC),
++	PINMUX_SINGLE(AVB_MAGIC),
++	PINMUX_SINGLE(AVB_PHY_INT),
++	PINMUX_SINGLE(AVB_LINK),
++
++	PINMUX_SINGLE(GETHER_RX_CTL),
++	PINMUX_SINGLE(GETHER_RXC),
++	PINMUX_SINGLE(GETHER_RD0),
++	PINMUX_SINGLE(GETHER_RD1),
++	PINMUX_SINGLE(GETHER_RD2),
++	PINMUX_SINGLE(GETHER_RD3),
++	PINMUX_SINGLE(GETHER_TX_CTL),
++	PINMUX_SINGLE(GETHER_TXC),
++	PINMUX_SINGLE(GETHER_TD0),
++	PINMUX_SINGLE(GETHER_TD1),
++	PINMUX_SINGLE(GETHER_TD2),
++	PINMUX_SINGLE(GETHER_TD3),
++	PINMUX_SINGLE(GETHER_TXCREFCLK),
++	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
++	PINMUX_SINGLE(GETHER_MDIO_A),
++	PINMUX_SINGLE(GETHER_MDC_A),
++	PINMUX_SINGLE(GETHER_MAGIC),
++	PINMUX_SINGLE(GETHER_PHY_INT_A),
++	PINMUX_SINGLE(GETHER_LINK_A),
++
++	PINMUX_SINGLE(QSPI0_SPCLK),
++	PINMUX_SINGLE(QSPI0_MOSI_IO0),
++	PINMUX_SINGLE(QSPI0_MISO_IO1),
++	PINMUX_SINGLE(QSPI0_IO2),
++	PINMUX_SINGLE(QSPI0_IO3),
++	PINMUX_SINGLE(QSPI0_SSL),
++	PINMUX_SINGLE(QSPI1_SPCLK),
++	PINMUX_SINGLE(QSPI1_MOSI_IO0),
++	PINMUX_SINGLE(QSPI1_MISO_IO1),
++	PINMUX_SINGLE(QSPI1_IO2),
++	PINMUX_SINGLE(QSPI1_IO3),
++	PINMUX_SINGLE(QSPI1_SSL),
++	PINMUX_SINGLE(RPC_RESET_N),
++	PINMUX_SINGLE(RPC_WP_N),
++	PINMUX_SINGLE(RPC_INT_N),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
++	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
++	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
++	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
++
++	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
++	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
++	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
++	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
++
++	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
++	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
++	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
++	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
++
++	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
++	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
++	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
++	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
++
++	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
++	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N_TANS),
++	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
++	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
++
++	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
++	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
++	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
++
++	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
++	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
++	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
++
++	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
++	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
++	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
++	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
++	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
++	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
++	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
++
++	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
++	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
++	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
++
++	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
++	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
++
++	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
++	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
++
++	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
++	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
++	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
++
++	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
++	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
++	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
++
++	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
++	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
++	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
++
++	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
++	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
++	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
++	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
++	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
++
++	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
++	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
++	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
++
++	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
++	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
++	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
++
++	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
++	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
++	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
++	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
++
++	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
++	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
++	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
++
++	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
++
++	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
++	PINMUX_IPSR_GPSR(IP2_27_24,	CC5_OSCOUT),
++
++	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
++	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
++	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
++	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
++	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
++	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
++	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
++
++	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
++	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
++	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N_TANS),
++	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
++
++	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
++	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
++	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
++	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
++
++	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
++	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
++
++	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
++	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
++
++	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
++	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
++	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
++	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
++	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
++
++	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
++	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
++	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
++
++	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
++	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
++	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N_TANS),
++
++	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
++	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
++
++	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
++	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
++	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
++
++	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
++	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
++	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
++
++	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
++	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
++	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
++
++	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
++	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
++	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
++	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
++	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
++	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
++
++	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
++	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
++	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
++
++	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
++	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
++
++	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
++	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
++
++	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
++	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
++	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
++	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
++
++	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
++	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
++
++	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
++	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
++	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
++
++	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
++	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
++	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
++	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
++	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
++
++	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
++	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
++	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
++
++	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
++	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
++	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
++
++	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
++	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
++	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
++
++	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
++	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
++	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
++
++	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
++	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU_0),
++	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
++	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
++
++	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
++	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU_0),
++	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
++	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
++
++	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
++	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
++	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
++	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
++	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
++	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
++	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
++
++	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
++
++	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
++	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
++	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
++	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
++	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
++	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
++
++	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
++	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
++	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
++	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N_TANS),
++	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
++	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
++	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
++	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
++	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
++	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
++	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
++	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
++
++	/* IPSR8 */
++	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
++	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
++
++	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
++	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
++	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
++
++	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
++	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
++
++	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
++	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
++	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
++
++	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
++	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
++
++	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
++
++	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
++	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
++
++	/* IPSR9 */
++	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
++	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
++
++	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
++	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
++
++	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
++	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
++	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
++
++	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
++	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
++	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
++
++	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
++	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
++	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
++
++	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
++	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
++	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
++
++	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
++	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
++	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
++	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
++
++	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
++	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
++	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
++	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
++
++	/* IPSR10 */
++	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
++	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
++
++	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
++	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
++
++	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
++	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
++
++	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
++	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
++
++	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
++};
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++};
++
++/* - AVB -------------------------------------------------------------------- */
++static const unsigned int avb_link_pins[] = {
++	/* AVB_LINK */
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int avb_link_mux[] = {
++	AVB_LINK_MARK,
++};
++static const unsigned int avb_magic_pins[] = {
++	/* AVB_MAGIC */
++	RCAR_GP_PIN(1, 16),
++};
++static const unsigned int avb_magic_mux[] = {
++	AVB_MAGIC_MARK,
++};
++static const unsigned int avb_phy_int_pins[] = {
++	/* AVB_PHY_INT */
++	RCAR_GP_PIN(1, 17),
++};
++static const unsigned int avb_phy_int_mux[] = {
++	AVB_PHY_INT_MARK,
++};
++static const unsigned int avb_mdio_pins[] = {
++	/* AVB_MDC, AVB_MDIO */
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
++};
++static const unsigned int avb_mdio_mux[] = {
++	AVB_MDC_MARK, AVB_MDIO_MARK,
++};
++static const unsigned int avb_rgmii_pins[] = {
++	/*
++	 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
++	 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
++	 */
++	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
++	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
++	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
++	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
++	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
++	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
++};
++static const unsigned int avb_rgmii_mux[] = {
++	AVB_TX_CTL_MARK, AVB_TXC_MARK,
++	AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
++	AVB_RX_CTL_MARK, AVB_RXC_MARK,
++	AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
++};
++static const unsigned int avb_txcrefclk_pins[] = {
++	/* AVB_TXCREFCLK */
++	RCAR_GP_PIN(1, 13),
++};
++static const unsigned int avb_txcrefclk_mux[] = {
++	AVB_TXCREFCLK_MARK,
++};
++static const unsigned int avb_avtp_pps_pins[] = {
++	/* AVB_AVTP_PPS */
++	RCAR_GP_PIN(2, 6),
++};
++static const unsigned int avb_avtp_pps_mux[] = {
++	AVB_AVTP_PPS_MARK,
++};
++static const unsigned int avb_avtp_capture_pins[] = {
++	/* AVB_AVTP_CAPTURE */
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int avb_avtp_capture_mux[] = {
++	AVB_AVTP_CAPTURE_MARK,
++};
++static const unsigned int avb_avtp_match_pins[] = {
++	/* AVB_AVTP_MATCH */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int avb_avtp_match_mux[] = {
++	AVB_AVTP_MATCH_MARK,
++};
++
++/* - CANFD0 ----------------------------------------------------------------- */
++static const unsigned int canfd0_data_a_pins[] = {
++	/* CANFD0_TX, CANFD0_RX */
++	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
++};
++static const unsigned int canfd0_data_a_mux[] = {
++	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
++};
++static const unsigned int canfd0_data_b_pins[] = {
++	/* CANFD0_TX, CANFD0_RX */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int canfd0_data_b_mux[] = {
++	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
++};
++
++/* - CANFD1 ----------------------------------------------------------------- */
++static const unsigned int canfd1_data_pins[] = {
++	/* CANFD1_TX, CANFD1_RX */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
++};
++static const unsigned int canfd1_data_mux[] = {
++	CANFD1_TX_MARK, CANFD1_RX_MARK,
++};
++
++/* - CANFD Clock ------------------------------------------------------------ */
++static const unsigned int canfd_clk_a_pins[] = {
++	/* CANFD_CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int canfd_clk_a_mux[] = {
++	CANFD_CLK_A_MARK,
++};
++static const unsigned int canfd_clk_b_pins[] = {
++	/* CANFD_CLK */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int canfd_clk_b_mux[] = {
++	CANFD_CLK_B_MARK,
++};
++
++/* - DU --------------------------------------------------------------------- */
++static const unsigned int du_rgb666_pins[] = {
++	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
++};
++static const unsigned int du_rgb666_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
++	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
++	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
++	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
++};
++static const unsigned int du_rgb888_pins[] = {
++	/* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
++	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
++	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
++	RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
++	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
++	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
++};
++static const unsigned int du_rgb888_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
++	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
++	DU_DR1_MARK, DU_DR0_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
++	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
++	DU_DG1_MARK, DU_DG0_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
++	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
++	DU_DB1_MARK, DU_DB0_MARK,
++};
++static const unsigned int du_clk_out_pins[] = {
++	/* DU_DOTCLKOUT */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int du_clk_out_mux[] = {
++	DU_DOTCLKOUT_MARK,
++};
++static const unsigned int du_sync_pins[] = {
++	/* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
++	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
++};
++static const unsigned int du_sync_mux[] = {
++	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
++};
++static const unsigned int du_oddf_pins[] = {
++	/* DU_EXODDF/DU_ODDF/DISP/CDE */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int du_oddf_mux[] = {
++	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
++};
++static const unsigned int du_cde_pins[] = {
++	/* DU_CDE */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int du_cde_mux[] = {
++	DU_CDE_MARK,
++};
++static const unsigned int du_disp_pins[] = {
++	/* DU_DISP */
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int du_disp_mux[] = {
++	DU_DISP_MARK,
++};
++
++/* - GETHER ----------------------------------------------------------------- */
++static const unsigned int gether_link_a_pins[] = {
++	/* GETHER_LINK */
++	RCAR_GP_PIN(4, 24),
++};
++static const unsigned int gether_link_a_mux[] = {
++	GETHER_LINK_A_MARK,
++};
++static const unsigned int gether_phy_int_a_pins[] = {
++	/* GETHER_PHY_INT */
++	RCAR_GP_PIN(4, 23),
++};
++static const unsigned int gether_phy_int_a_mux[] = {
++	GETHER_PHY_INT_A_MARK,
++};
++static const unsigned int gether_mdio_a_pins[] = {
++	/* GETHER_MDC, GETHER_MDIO */
++	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
++};
++static const unsigned int gether_mdio_a_mux[] = {
++	GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
++};
++static const unsigned int gether_link_b_pins[] = {
++	/* GETHER_LINK */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int gether_link_b_mux[] = {
++	GETHER_LINK_B_MARK,
++};
++static const unsigned int gether_phy_int_b_pins[] = {
++	/* GETHER_PHY_INT */
++	RCAR_GP_PIN(0, 19),
++};
++static const unsigned int gether_phy_int_b_mux[] = {
++	GETHER_PHY_INT_B_MARK,
++};
++static const unsigned int gether_mdio_b_mux[] = {
++	GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
++};
++static const unsigned int gether_mdio_b_pins[] = {
++	/* GETHER_MDC, GETHER_MDIO */
++	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
++};
++static const unsigned int gether_magic_pins[] = {
++	/* GETHER_MAGIC */
++	RCAR_GP_PIN(4, 22),
++};
++static const unsigned int gether_magic_mux[] = {
++	GETHER_MAGIC_MARK,
++};
++static const unsigned int gether_rgmii_pins[] = {
++	/*
++	 * GETHER_TX_CTL, GETHER_TXC,
++	 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
++	 * GETHER_RX_CTL, GETHER_RXC,
++	 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
++	 */
++	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
++	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
++	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
++	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
++	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
++	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
++};
++static const unsigned int gether_rgmii_mux[] = {
++	GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
++	GETHER_TD0_MARK, GETHER_TD1_MARK,
++	GETHER_TD2_MARK, GETHER_TD3_MARK,
++	GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
++	GETHER_RD0_MARK, AVB_RD1_MARK,
++	GETHER_RD2_MARK, AVB_RD3_MARK,
++};
++static const unsigned int gether_txcrefclk_pins[] = {
++	/* GETHER_TXCREFCLK */
++	RCAR_GP_PIN(4, 18),
++};
++static const unsigned int gether_txcrefclk_mux[] = {
++	GETHER_TXCREFCLK_MARK,
++};
++static const unsigned int gether_txcrefclk_mega_pins[] = {
++	/* GETHER_TXCREFCLK_MEGA */
++	RCAR_GP_PIN(4, 19),
++};
++static const unsigned int gether_txcrefclk_mega_mux[] = {
++	GETHER_TXCREFCLK_MEGA_MARK,
++};
++static const unsigned int gether_rmii_pins[] = {
++	/*
++	 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
++	 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
++	 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
++	 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
++	 */
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int gether_rmii_mux[] = {
++	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
++	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
++	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
++	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
++};
++
++/* - HSCIF0 ----------------------------------------------------------------- */
++static const unsigned int hscif0_data_a_pins[] = {
++	/* HRX0, HTX0 */
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int hscif0_data_a_mux[] = {
++	HRX0_A_MARK, HTX0_A_MARK,
++};
++static const unsigned int hscif0_clk_a_pins[] = {
++	/* HSCK0 */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int hscif0_clk_a_mux[] = {
++	HSCK0_A_MARK,
++};
++static const unsigned int hscif0_ctrl_a_pins[] = {
++	/* HRTS0#, HCTS0# */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int hscif0_ctrl_a_mux[] = {
++	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
++};
++static const unsigned int hscif0_data_b_pins[] = {
++	/* HRX0, HTX0 */
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int hscif0_data_b_mux[] = {
++	HRX0_B_MARK, HTX0_B_MARK,
++};
++static const unsigned int hscif0_clk_b_pins[] = {
++	/* HSCK0 */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int hscif0_clk_b_mux[] = {
++	HSCK0_B_MARK,
++};
++static const unsigned int hscif0_ctrl_b_pins[] = {
++	/* HRTS0#, HCTS0# */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int hscif0_ctrl_b_mux[] = {
++	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
++};
++
++/* - HSCIF1 ----------------------------------------------------------------- */
++static const unsigned int hscif1_data_pins[] = {
++	/* HRX1, HTX1 */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int hscif1_data_mux[] = {
++	HRX1_MARK, HTX1_MARK,
++};
++static const unsigned int hscif1_clk_pins[] = {
++	/* HSCK1 */
++	RCAR_GP_PIN(2, 7),
++};
++static const unsigned int hscif1_clk_mux[] = {
++	HSCK1_MARK,
++};
++static const unsigned int hscif1_ctrl_pins[] = {
++	/* HRTS1#, HCTS1# */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int hscif1_ctrl_mux[] = {
++	HRTS1_N_MARK, HCTS1_N_MARK,
++};
++
++/* - HSCIF2 ----------------------------------------------------------------- */
++static const unsigned int hscif2_data_pins[] = {
++	/* HRX2, HTX2 */
++	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
++};
++static const unsigned int hscif2_data_mux[] = {
++	HRX2_MARK, HTX2_MARK,
++};
++static const unsigned int hscif2_clk_pins[] = {
++	/* HSCK2 */
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int hscif2_clk_mux[] = {
++	HSCK2_MARK,
++};
++static const unsigned int hscif2_ctrl_pins[] = {
++	/* HRTS2#, HCTS2# */
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int hscif2_ctrl_mux[] = {
++	HRTS2_N_MARK, HCTS2_N_MARK,
++};
++
++/* - HSCIF3 ----------------------------------------------------------------- */
++static const unsigned int hscif3_data_pins[] = {
++	/* HRX3, HTX3 */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int hscif3_data_mux[] = {
++	HRX3_MARK, HTX3_MARK,
++};
++static const unsigned int hscif3_clk_pins[] = {
++	/* HSCK3 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int hscif3_clk_mux[] = {
++	HSCK3_MARK,
++};
++static const unsigned int hscif3_ctrl_pins[] = {
++	/* HRTS3#, HCTS3# */
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
++};
++static const unsigned int hscif3_ctrl_mux[] = {
++	HRTS3_N_MARK, HCTS3_N_MARK,
++};
++
++/* - I2C0 ------------------------------------------------------------------- */
++static const unsigned int i2c0_pins[] = {
++	/* SDA0, SCL0 */
++	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
++};
++static const unsigned int i2c0_mux[] = {
++	SDA0_MARK, SCL0_MARK,
++};
++
++/* - I2C1 ------------------------------------------------------------------- */
++static const unsigned int i2c1_pins[] = {
++	/* SDA1, SCL1 */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int i2c1_mux[] = {
++	SDA1_MARK, SCL1_MARK,
++};
++
++/* - I2C2 ------------------------------------------------------------------- */
++static const unsigned int i2c2_pins[] = {
++	/* SDA2, SCL2 */
++	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
++};
++static const unsigned int i2c2_mux[] = {
++	SDA2_MARK, SCL2_MARK,
++};
++
++/* - I2C3 ------------------------------------------------------------------- */
++static const unsigned int i2c3_pins[] = {
++	/* SDA3, SCL3 */
++	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
++};
++static const unsigned int i2c3_mux[] = {
++	SDA3_MARK, SCL3_MARK,
++};
++
++/* - I2C4 ------------------------------------------------------------------- */
++static const unsigned int i2c4_pins[] = {
++	/* SDA4, SCL4 */
++	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int i2c4_mux[] = {
++	SDA4_MARK, SCL4_MARK,
++};
++
++/* - I2C5 ------------------------------------------------------------------- */
++static const unsigned int i2c5_pins[] = {
++	/* SDA5, SCL5 */
++	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
++};
++static const unsigned int i2c5_mux[] = {
++	SDA5_MARK, SCL5_MARK,
++};
++
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(0, 13),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(0, 14),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(2, 17),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(2, 18),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
++/* - MMC -------------------------------------------------------------------- */
++static const unsigned int mmc_data1_pins[] = {
++	/* MMC_D0 */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int mmc_data1_mux[] = {
++	MMC_D0_MARK,
++};
++static const unsigned int mmc_data4_pins[] = {
++	/* MMC_D[0:3] */
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int mmc_data4_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++};
++static const unsigned int mmc_data8_pins[] = {
++	/* MMC_D[0:7] */
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
++	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
++};
++static const unsigned int mmc_data8_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++	MMC_D4_MARK, MMC_D5_MARK,
++	MMC_D6_MARK, MMC_D7_MARK,
++};
++static const unsigned int mmc_ctrl_pins[] = {
++	/* MMC_CLK, MMC_CMD */
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int mmc_ctrl_mux[] = {
++	MMC_CLK_MARK, MMC_CMD_MARK,
++};
++static const unsigned int mmc_cd_pins[] = {
++	/* MMC_CD */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int mmc_cd_mux[] = {
++	MMC_CD_MARK,
++};
++static const unsigned int mmc_wp_pins[] = {
++	/* MMC_WP */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int mmc_wp_mux[] = {
++	MMC_WP_MARK,
++};
++static const unsigned int mmc_ds_pins[] = {
++	/* MMC_DS */
++	RCAR_GP_PIN(3, 6),
++};
++static const unsigned int mmc_ds_mux[] = {
++	MMC_DS_MARK,
++};
++
++/* - MSIOF0 ----------------------------------------------------------------- */
++static const unsigned int msiof0_clk_pins[] = {
++	/* MSIOF0_SCK */
++	RCAR_GP_PIN(2, 21),
++};
++static const unsigned int msiof0_clk_mux[] = {
++	MSIOF0_SCK_MARK,
++};
++static const unsigned int msiof0_sync_pins[] = {
++	/* MSIOF0_SYNC */
++	RCAR_GP_PIN(2, 22),
++};
++static const unsigned int msiof0_sync_mux[] = {
++	MSIOF0_SYNC_MARK,
++};
++static const unsigned int msiof0_ss1_pins[] = {
++	/* MSIOF0_SS1 */
++	RCAR_GP_PIN(2, 23),
++};
++static const unsigned int msiof0_ss1_mux[] = {
++	MSIOF0_SS1_MARK,
++};
++static const unsigned int msiof0_ss2_pins[] = {
++	/* MSIOF0_SS2 */
++	RCAR_GP_PIN(2, 24),
++};
++static const unsigned int msiof0_ss2_mux[] = {
++	MSIOF0_SS2_MARK,
++};
++static const unsigned int msiof0_txd_pins[] = {
++	/* MSIOF0_TXD */
++	RCAR_GP_PIN(2, 20),
++};
++static const unsigned int msiof0_txd_mux[] = {
++	MSIOF0_TXD_MARK,
++};
++static const unsigned int msiof0_rxd_pins[] = {
++	/* MSIOF0_RXD */
++	RCAR_GP_PIN(2, 19),
++};
++static const unsigned int msiof0_rxd_mux[] = {
++	MSIOF0_RXD_MARK,
++};
++
++/* - MSIOF1 ----------------------------------------------------------------- */
++static const unsigned int msiof1_clk_pins[] = {
++	/* MSIOF1_SCK */
++	RCAR_GP_PIN(3, 2),
++};
++static const unsigned int msiof1_clk_mux[] = {
++	MSIOF1_SCK_MARK,
++};
++static const unsigned int msiof1_sync_pins[] = {
++	/* MSIOF1_SYNC */
++	RCAR_GP_PIN(3, 3),
++};
++static const unsigned int msiof1_sync_mux[] = {
++	MSIOF1_SYNC_MARK,
++};
++static const unsigned int msiof1_ss1_pins[] = {
++	/* MSIOF1_SS1 */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int msiof1_ss1_mux[] = {
++	MSIOF1_SS1_MARK,
++};
++static const unsigned int msiof1_ss2_pins[] = {
++	/* MSIOF1_SS2 */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int msiof1_ss2_mux[] = {
++	MSIOF1_SS2_MARK,
++};
++static const unsigned int msiof1_txd_pins[] = {
++	/* MSIOF1_TXD */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int msiof1_txd_mux[] = {
++	MSIOF1_TXD_MARK,
++};
++static const unsigned int msiof1_rxd_pins[] = {
++	/* MSIOF1_RXD */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int msiof1_rxd_mux[] = {
++	MSIOF1_RXD_MARK,
++};
++
++/* - MSIOF2 ----------------------------------------------------------------- */
++static const unsigned int msiof2_clk_pins[] = {
++	/* MSIOF2_SCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int msiof2_clk_mux[] = {
++	MSIOF2_SCK_MARK,
++};
++static const unsigned int msiof2_sync_pins[] = {
++	/* MSIOF2_SYNC */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int msiof2_sync_mux[] = {
++	MSIOF2_SYNC_MARK,
++};
++static const unsigned int msiof2_ss1_pins[] = {
++	/* MSIOF2_SS1 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int msiof2_ss1_mux[] = {
++	MSIOF2_SS1_MARK,
++};
++static const unsigned int msiof2_ss2_pins[] = {
++	/* MSIOF2_SS2 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int msiof2_ss2_mux[] = {
++	MSIOF2_SS2_MARK,
++};
++static const unsigned int msiof2_txd_pins[] = {
++	/* MSIOF2_TXD */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int msiof2_txd_mux[] = {
++	MSIOF2_TXD_MARK,
++};
++static const unsigned int msiof2_rxd_pins[] = {
++	/* MSIOF2_RXD */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int msiof2_rxd_mux[] = {
++	MSIOF2_RXD_MARK,
++};
++
++/* - MSIOF3 ----------------------------------------------------------------- */
++static const unsigned int msiof3_clk_pins[] = {
++	/* MSIOF3_SCK */
++	RCAR_GP_PIN(0, 20),
++};
++static const unsigned int msiof3_clk_mux[] = {
++	MSIOF3_SCK_MARK,
++};
++static const unsigned int msiof3_sync_pins[] = {
++	/* MSIOF3_SYNC */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int msiof3_sync_mux[] = {
++	MSIOF3_SYNC_MARK,
++};
++static const unsigned int msiof3_ss1_pins[] = {
++	/* MSIOF3_SS1 */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int msiof3_ss1_mux[] = {
++	MSIOF3_SS1_MARK,
++};
++static const unsigned int msiof3_ss2_pins[] = {
++	/* MSIOF3_SS2 */
++	RCAR_GP_PIN(0, 19),
++};
++static const unsigned int msiof3_ss2_mux[] = {
++	MSIOF3_SS2_MARK,
++};
++static const unsigned int msiof3_txd_pins[] = {
++	/* MSIOF3_TXD */
++	RCAR_GP_PIN(0, 17),
++};
++static const unsigned int msiof3_txd_mux[] = {
++	MSIOF3_TXD_MARK,
++};
++static const unsigned int msiof3_rxd_pins[] = {
++	/* MSIOF3_RXD */
++	RCAR_GP_PIN(0, 16),
++};
++static const unsigned int msiof3_rxd_mux[] = {
++	MSIOF3_RXD_MARK,
++};
++
++/* - PWM0 ------------------------------------------------------------------- */
++static const unsigned int pwm0_a_pins[] = {
++	/* PWM0 */
++	RCAR_GP_PIN(0, 15),
++};
++static const unsigned int pwm0_a_mux[] = {
++	PWM0_A_MARK,
++};
++static const unsigned int pwm0_b_pins[] = {
++	/* PWM0 */
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int pwm0_b_mux[] = {
++	PWM0_B_MARK,
++};
++
++/* - PWM1 ------------------------------------------------------------------- */
++static const unsigned int pwm1_a_pins[] = {
++	/* PWM1 */
++	RCAR_GP_PIN(2, 13),
++};
++static const unsigned int pwm1_a_mux[] = {
++	PWM1_A_MARK,
++};
++static const unsigned int pwm1_b_pins[] = {
++	/* PWM1 */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++
++/* - PWM2 ------------------------------------------------------------------- */
++static const unsigned int pwm2_a_pins[] = {
++	/* PWM2 */
++	RCAR_GP_PIN(2, 14),
++};
++static const unsigned int pwm2_a_mux[] = {
++	PWM2_A_MARK,
++};
++static const unsigned int pwm2_b_pins[] = {
++	/* PWM2 */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++
++/* - PWM3 ------------------------------------------------------------------- */
++static const unsigned int pwm3_a_pins[] = {
++	/* PWM3 */
++	RCAR_GP_PIN(2, 15),
++};
++static const unsigned int pwm3_a_mux[] = {
++	PWM3_A_MARK,
++};
++static const unsigned int pwm3_b_pins[] = {
++	/* PWM3 */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++
++/* - PWM4 ------------------------------------------------------------------- */
++static const unsigned int pwm4_a_pins[] = {
++	/* PWM4 */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int pwm4_a_mux[] = {
++	PWM4_A_MARK,
++};
++static const unsigned int pwm4_b_pins[] = {
++	/* PWM4 */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int pwm4_b_mux[] = {
++	PWM4_B_MARK,
++};
++
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_pins[] = {
++	/* RX0, TX0 */
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int scif0_data_mux[] = {
++	RX0_MARK, TX0_MARK,
++};
++static const unsigned int scif0_clk_pins[] = {
++	/* SCK0 */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int scif0_clk_mux[] = {
++	SCK0_MARK,
++};
++static const unsigned int scif0_ctrl_pins[] = {
++	/* RTS0#/TANS, CTS0# */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int scif0_ctrl_mux[] = {
++	RTS0_N_TANS_MARK, CTS0_N_MARK,
++};
++
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_a_pins[] = {
++	/* RX1, TX1 */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int scif1_data_a_mux[] = {
++	RX1_A_MARK, TX1_A_MARK,
++};
++static const unsigned int scif1_clk_pins[] = {
++	/* SCK1 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int scif1_clk_mux[] = {
++	SCK1_MARK,
++};
++static const unsigned int scif1_ctrl_pins[] = {
++	/* RTS1#/TANS, CTS1# */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int scif1_ctrl_mux[] = {
++	RTS1_N_TANS_MARK, CTS1_N_MARK,
++};
++static const unsigned int scif1_data_b_pins[] = {
++	/* RX1, TX1 */
++	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
++};
++static const unsigned int scif1_data_b_mux[] = {
++	RX1_B_MARK, TX1_B_MARK,
++};
++
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_pins[] = {
++	/* RX3, TX3 */
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++};
++static const unsigned int scif3_data_mux[] = {
++	RX3_MARK, TX3_MARK,
++};
++static const unsigned int scif3_clk_pins[] = {
++	/* SCK3 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int scif3_clk_mux[] = {
++	SCK3_MARK,
++};
++static const unsigned int scif3_ctrl_pins[] = {
++	/* RTS3#/TANS, CTS3# */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int scif3_ctrl_mux[] = {
++	RTS3_N_TANS_MARK, CTS3_N_MARK,
++};
++
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_pins[] = {
++	/* RX4, TX4 */
++	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
++};
++static const unsigned int scif4_data_mux[] = {
++	RX4_MARK, TX4_MARK,
++};
++static const unsigned int scif4_clk_pins[] = {
++	/* SCK4 */
++	RCAR_GP_PIN(0, 0),
++};
++static const unsigned int scif4_clk_mux[] = {
++	SCK4_MARK,
++};
++static const unsigned int scif4_ctrl_pins[] = {
++	/* RTS4#/TANS, CTS4# */
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int scif4_ctrl_mux[] = {
++	RTS4_N_TANS_MARK, CTS4_N_MARK,
++};
++
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(0, 10),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(3, 13),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(3, 14),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
++/* - TPU ------------------------------------------------------------------- */
++static const unsigned int tpu_to0_pins[] = {
++	/* TPU0TO0 */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int tpu_to0_mux[] = {
++	TPU0TO0_MARK,
++};
++static const unsigned int tpu_to1_pins[] = {
++	/* TPU0TO1 */
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int tpu_to1_mux[] = {
++	TPU0TO1_MARK,
++};
++static const unsigned int tpu_to2_pins[] = {
++	/* TPU0TO2 */
++	RCAR_GP_PIN(4, 2),
++};
++static const unsigned int tpu_to2_mux[] = {
++	TPU0TO2_MARK,
++};
++static const unsigned int tpu_to3_pins[] = {
++	/* TPU0TO3 */
++	RCAR_GP_PIN(4, 3),
++};
++static const unsigned int tpu_to3_mux[] = {
++	TPU0TO3_MARK,
++};
++
++/* - VIN0 ------------------------------------------------------------------- */
++static const union vin_data vin0_data_pins = {
++	.data24 = {
++		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++		RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
++		RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
++	},
++};
++static const union vin_data vin0_data_mux = {
++	.data24 = {
++		VI0_DATA0_MARK, VI0_DATA1_MARK,
++		VI0_DATA2_MARK, VI0_DATA3_MARK,
++		VI0_DATA4_MARK, VI0_DATA5_MARK,
++		VI0_DATA6_MARK, VI0_DATA7_MARK,
++		VI0_DATA8_MARK, VI0_DATA9_MARK,
++		VI0_DATA10_MARK, VI0_DATA11_MARK,
++		VI0_DATA12_MARK, VI0_DATA13_MARK,
++		VI0_DATA14_MARK, VI0_DATA15_MARK,
++		VI0_DATA16_MARK, VI0_DATA17_MARK,
++		VI0_DATA18_MARK, VI0_DATA19_MARK,
++		VI0_DATA20_MARK, VI0_DATA21_MARK,
++		VI0_DATA22_MARK, VI0_DATA23_MARK,
++	},
++};
++static const unsigned int vin0_data18_pins[] = {
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
++	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
++};
++static const unsigned int vin0_data18_mux[] = {
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++	VI0_DATA12_MARK, VI0_DATA13_MARK,
++	VI0_DATA14_MARK, VI0_DATA15_MARK,
++	VI0_DATA18_MARK, VI0_DATA19_MARK,
++	VI0_DATA20_MARK, VI0_DATA21_MARK,
++	VI0_DATA22_MARK, VI0_DATA23_MARK,
++};
++static const unsigned int vin0_sync_pins[] = {
++	/* VI0_VSYNC#, VI0_HSYNC# */
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
++};
++static const unsigned int vin0_sync_mux[] = {
++	VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
++};
++static const unsigned int vin0_field_pins[] = {
++	/* VI0_FIELD */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int vin0_field_mux[] = {
++	VI0_FIELD_MARK,
++};
++static const unsigned int vin0_clkenb_pins[] = {
++	/* VI0_CLKENB */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int vin0_clkenb_mux[] = {
++	VI0_CLKENB_MARK,
++};
++static const unsigned int vin0_clk_pins[] = {
++	/* VI0_CLK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int vin0_clk_mux[] = {
++	VI0_CLK_MARK,
++};
++
++/* - VIN1 ------------------------------------------------------------------- */
++static const unsigned int vin1_data8_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int vin1_data8_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++};
++static const unsigned int vin1_data10_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++};
++static const unsigned int vin1_data10_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK, VI1_DATA9_MARK,
++};
++static const unsigned int vin1_data12_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int vin1_data12_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK,  VI1_DATA9_MARK,
++	VI1_DATA10_MARK, VI1_DATA11_MARK,
++};
++static const unsigned int vin1_sync_pins[] = {
++	/* VI1_VSYNC#, VI1_HSYNC# */
++	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
++};
++static const unsigned int vin1_sync_mux[] = {
++	VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
++};
++static const unsigned int vin1_field_pins[] = {
++	/* VI1_FIELD */
++	RCAR_GP_PIN(3, 16),
++};
++static const unsigned int vin1_field_mux[] = {
++	VI1_FIELD_MARK,
++};
++static const unsigned int vin1_clkenb_pins[] = {
++	/* VI1_CLKENB */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int vin1_clkenb_mux[] = {
++	VI1_CLKENB_MARK,
++};
++static const unsigned int vin1_clk_pins[] = {
++	/* VI1_CLK */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int vin1_clk_mux[] = {
++	VI1_CLK_MARK,
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb_link),
++	SH_PFC_PIN_GROUP(avb_magic),
++	SH_PFC_PIN_GROUP(avb_phy_int),
++	SH_PFC_PIN_GROUP(avb_mdio),
++	SH_PFC_PIN_GROUP(avb_rgmii),
++	SH_PFC_PIN_GROUP(avb_txcrefclk),
++	SH_PFC_PIN_GROUP(avb_avtp_pps),
++	SH_PFC_PIN_GROUP(avb_avtp_capture),
++	SH_PFC_PIN_GROUP(avb_avtp_match),
++	SH_PFC_PIN_GROUP(canfd0_data_a),
++	SH_PFC_PIN_GROUP(canfd0_data_b),
++	SH_PFC_PIN_GROUP(canfd1_data),
++	SH_PFC_PIN_GROUP(canfd_clk_a),
++	SH_PFC_PIN_GROUP(canfd_clk_b),
++	SH_PFC_PIN_GROUP(du_rgb666),
++	SH_PFC_PIN_GROUP(du_rgb888),
++	SH_PFC_PIN_GROUP(du_clk_out),
++	SH_PFC_PIN_GROUP(du_sync),
++	SH_PFC_PIN_GROUP(du_oddf),
++	SH_PFC_PIN_GROUP(du_cde),
++	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(gether_link_a),
++	SH_PFC_PIN_GROUP(gether_phy_int_a),
++	SH_PFC_PIN_GROUP(gether_mdio_a),
++	SH_PFC_PIN_GROUP(gether_link_b),
++	SH_PFC_PIN_GROUP(gether_phy_int_b),
++	SH_PFC_PIN_GROUP(gether_mdio_b),
++	SH_PFC_PIN_GROUP(gether_magic),
++	SH_PFC_PIN_GROUP(gether_rgmii),
++	SH_PFC_PIN_GROUP(gether_txcrefclk),
++	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
++	SH_PFC_PIN_GROUP(gether_rmii),
++	SH_PFC_PIN_GROUP(hscif0_data_a),
++	SH_PFC_PIN_GROUP(hscif0_clk_a),
++	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
++	SH_PFC_PIN_GROUP(hscif0_data_b),
++	SH_PFC_PIN_GROUP(hscif0_clk_b),
++	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
++	SH_PFC_PIN_GROUP(hscif1_data),
++	SH_PFC_PIN_GROUP(hscif1_clk),
++	SH_PFC_PIN_GROUP(hscif1_ctrl),
++	SH_PFC_PIN_GROUP(hscif2_data),
++	SH_PFC_PIN_GROUP(hscif2_clk),
++	SH_PFC_PIN_GROUP(hscif2_ctrl),
++	SH_PFC_PIN_GROUP(hscif3_data),
++	SH_PFC_PIN_GROUP(hscif3_clk),
++	SH_PFC_PIN_GROUP(hscif3_ctrl),
++	SH_PFC_PIN_GROUP(i2c0),
++	SH_PFC_PIN_GROUP(i2c1),
++	SH_PFC_PIN_GROUP(i2c2),
++	SH_PFC_PIN_GROUP(i2c3),
++	SH_PFC_PIN_GROUP(i2c4),
++	SH_PFC_PIN_GROUP(i2c5),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
++	SH_PFC_PIN_GROUP(mmc_data1),
++	SH_PFC_PIN_GROUP(mmc_data4),
++	SH_PFC_PIN_GROUP(mmc_data8),
++	SH_PFC_PIN_GROUP(mmc_ctrl),
++	SH_PFC_PIN_GROUP(mmc_cd),
++	SH_PFC_PIN_GROUP(mmc_wp),
++	SH_PFC_PIN_GROUP(mmc_ds),
++	SH_PFC_PIN_GROUP(msiof0_clk),
++	SH_PFC_PIN_GROUP(msiof0_sync),
++	SH_PFC_PIN_GROUP(msiof0_ss1),
++	SH_PFC_PIN_GROUP(msiof0_ss2),
++	SH_PFC_PIN_GROUP(msiof0_txd),
++	SH_PFC_PIN_GROUP(msiof0_rxd),
++	SH_PFC_PIN_GROUP(msiof1_clk),
++	SH_PFC_PIN_GROUP(msiof1_sync),
++	SH_PFC_PIN_GROUP(msiof1_ss1),
++	SH_PFC_PIN_GROUP(msiof1_ss2),
++	SH_PFC_PIN_GROUP(msiof1_txd),
++	SH_PFC_PIN_GROUP(msiof1_rxd),
++	SH_PFC_PIN_GROUP(msiof2_clk),
++	SH_PFC_PIN_GROUP(msiof2_sync),
++	SH_PFC_PIN_GROUP(msiof2_ss1),
++	SH_PFC_PIN_GROUP(msiof2_ss2),
++	SH_PFC_PIN_GROUP(msiof2_txd),
++	SH_PFC_PIN_GROUP(msiof2_rxd),
++	SH_PFC_PIN_GROUP(msiof3_clk),
++	SH_PFC_PIN_GROUP(msiof3_sync),
++	SH_PFC_PIN_GROUP(msiof3_ss1),
++	SH_PFC_PIN_GROUP(msiof3_ss2),
++	SH_PFC_PIN_GROUP(msiof3_txd),
++	SH_PFC_PIN_GROUP(msiof3_rxd),
++	SH_PFC_PIN_GROUP(pwm0_a),
++	SH_PFC_PIN_GROUP(pwm0_b),
++	SH_PFC_PIN_GROUP(pwm1_a),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm2_a),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm3_a),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm4_a),
++	SH_PFC_PIN_GROUP(pwm4_b),
++	SH_PFC_PIN_GROUP(scif0_data),
++	SH_PFC_PIN_GROUP(scif0_clk),
++	SH_PFC_PIN_GROUP(scif0_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_a),
++	SH_PFC_PIN_GROUP(scif1_clk),
++	SH_PFC_PIN_GROUP(scif1_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_b),
++	SH_PFC_PIN_GROUP(scif3_data),
++	SH_PFC_PIN_GROUP(scif3_clk),
++	SH_PFC_PIN_GROUP(scif3_ctrl),
++	SH_PFC_PIN_GROUP(scif4_data),
++	SH_PFC_PIN_GROUP(scif4_clk),
++	SH_PFC_PIN_GROUP(scif4_ctrl),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
++	SH_PFC_PIN_GROUP(tpu_to0),
++	SH_PFC_PIN_GROUP(tpu_to1),
++	SH_PFC_PIN_GROUP(tpu_to2),
++	SH_PFC_PIN_GROUP(tpu_to3),
++	VIN_DATA_PIN_GROUP(vin0_data, 8),
++	VIN_DATA_PIN_GROUP(vin0_data, 10),
++	VIN_DATA_PIN_GROUP(vin0_data, 12),
++	VIN_DATA_PIN_GROUP(vin0_data, 16),
++	SH_PFC_PIN_GROUP(vin0_data18),
++	VIN_DATA_PIN_GROUP(vin0_data, 20),
++	VIN_DATA_PIN_GROUP(vin0_data, 24),
++	SH_PFC_PIN_GROUP(vin0_sync),
++	SH_PFC_PIN_GROUP(vin0_field),
++	SH_PFC_PIN_GROUP(vin0_clkenb),
++	SH_PFC_PIN_GROUP(vin0_clk),
++	SH_PFC_PIN_GROUP(vin1_data8),
++	SH_PFC_PIN_GROUP(vin1_data10),
++	SH_PFC_PIN_GROUP(vin1_data12),
++	SH_PFC_PIN_GROUP(vin1_sync),
++	SH_PFC_PIN_GROUP(vin1_field),
++	SH_PFC_PIN_GROUP(vin1_clkenb),
++	SH_PFC_PIN_GROUP(vin1_clk),
++};
++
++static const char * const avb_groups[] = {
++	"avb_link",
++	"avb_magic",
++	"avb_phy_int",
++	"avb_mdio",
++	"avb_rgmii",
++	"avb_txcrefclk",
++	"avb_avtp_pps",
++	"avb_avtp_capture",
++	"avb_avtp_match",
++};
++
++static const char * const canfd0_groups[] = {
++	"canfd0_data_a",
++	"canfd0_data_b",
++};
++
++static const char * const canfd1_groups[] = {
++	"canfd1_data",
++};
++
++static const char * const canfd_clk_groups[] = {
++	"canfd_clk_a",
++	"canfd_clk_b",
++};
++
++static const char * const du_groups[] = {
++	"du_rgb666",
++	"du_rgb888",
++	"du_clk_out",
++	"du_sync",
++	"du_oddf",
++	"du_cde",
++	"du_disp",
++};
++
++static const char * const gether_groups[] = {
++	"gether_link_a",
++	"gether_phy_int_a",
++	"gether_mdio_a",
++	"gether_link_b",
++	"gether_phy_int_b",
++	"gether_mdio_b",
++	"gether_magic",
++	"gether_rgmii",
++	"gether_txcrefclk",
++	"gether_txcrefclk_mega",
++	"gether_rmii",
++};
++
++static const char * const hscif0_groups[] = {
++	"hscif0_data_a",
++	"hscif0_clk_a",
++	"hscif0_ctrl_a",
++	"hscif0_data_b",
++	"hscif0_clk_b",
++	"hscif0_ctrl_b",
++};
++
++static const char * const hscif1_groups[] = {
++	"hscif1_data",
++	"hscif1_clk",
++	"hscif1_ctrl",
++};
++
++static const char * const hscif2_groups[] = {
++	"hscif2_data",
++	"hscif2_clk",
++	"hscif2_ctrl",
++};
++
++static const char * const hscif3_groups[] = {
++	"hscif3_data",
++	"hscif3_clk",
++	"hscif3_ctrl",
++};
++
++static const char * const i2c0_groups[] = {
++	"i2c0",
++};
++
++static const char * const i2c1_groups[] = {
++	"i2c1",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2",
++};
++
++static const char * const i2c3_groups[] = {
++	"i2c3",
++};
++
++static const char * const i2c4_groups[] = {
++	"i2c4",
++};
++
++static const char * const i2c5_groups[] = {
++	"i2c5",
++};
++
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
++static const char * const mmc_groups[] = {
++	"mmc_data1",
++	"mmc_data4",
++	"mmc_data8",
++	"mmc_ctrl",
++	"mmc_cd",
++	"mmc_wp",
++	"mmc_ds",
++};
++
++static const char * const msiof0_groups[] = {
++	"msiof0_clk",
++	"msiof0_sync",
++	"msiof0_ss1",
++	"msiof0_ss2",
++	"msiof0_txd",
++	"msiof0_rxd",
++};
++
++static const char * const msiof1_groups[] = {
++	"msiof1_clk",
++	"msiof1_sync",
++	"msiof1_ss1",
++	"msiof1_ss2",
++	"msiof1_txd",
++	"msiof1_rxd",
++};
++
++static const char * const msiof2_groups[] = {
++	"msiof2_clk",
++	"msiof2_sync",
++	"msiof2_ss1",
++	"msiof2_ss2",
++	"msiof2_txd",
++	"msiof2_rxd",
++};
++
++static const char * const msiof3_groups[] = {
++	"msiof3_clk",
++	"msiof3_sync",
++	"msiof3_ss1",
++	"msiof3_ss2",
++	"msiof3_txd",
++	"msiof3_rxd",
++};
++
++static const char * const pwm0_groups[] = {
++	"pwm0_a",
++	"pwm0_b",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1_a",
++	"pwm1_b",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2_a",
++	"pwm2_b",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3_a",
++	"pwm3_b",
++};
++
++static const char * const pwm4_groups[] = {
++	"pwm4_a",
++	"pwm4_b",
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data",
++	"scif0_clk",
++	"scif0_ctrl",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data_a",
++	"scif1_clk",
++	"scif1_ctrl",
++	"scif1_data_b",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data",
++	"scif3_clk",
++	"scif3_ctrl",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data",
++	"scif4_clk",
++	"scif4_ctrl",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
++};
++
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
++static const char * const tpu_groups[] = {
++	"tpu_to0",
++	"tpu_to1",
++	"tpu_to2",
++	"tpu_to3",
++};
++
++static const char * const vin0_groups[] = {
++	"vin0_data8",
++	"vin0_data10",
++	"vin0_data12",
++	"vin0_data16",
++	"vin0_data18",
++	"vin0_data20",
++	"vin0_data24",
++	"vin0_sync",
++	"vin0_field",
++	"vin0_clkenb",
++	"vin0_clk",
++};
++
++static const char * const vin1_groups[] = {
++	"vin1_data8",
++	"vin1_data10",
++	"vin1_data12",
++	"vin1_sync",
++	"vin1_field",
++	"vin1_clkenb",
++	"vin1_clk",
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(canfd0),
++	SH_PFC_FUNCTION(canfd1),
++	SH_PFC_FUNCTION(canfd_clk),
++	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(gether),
++	SH_PFC_FUNCTION(hscif0),
++	SH_PFC_FUNCTION(hscif1),
++	SH_PFC_FUNCTION(hscif2),
++	SH_PFC_FUNCTION(hscif3),
++	SH_PFC_FUNCTION(i2c0),
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c3),
++	SH_PFC_FUNCTION(i2c4),
++	SH_PFC_FUNCTION(i2c5),
++	SH_PFC_FUNCTION(intc_ex),
++	SH_PFC_FUNCTION(mmc),
++	SH_PFC_FUNCTION(msiof0),
++	SH_PFC_FUNCTION(msiof1),
++	SH_PFC_FUNCTION(msiof2),
++	SH_PFC_FUNCTION(msiof3),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
++	SH_PFC_FUNCTION(pwm4),
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(tmu),
++	SH_PFC_FUNCTION(tpu),
++	SH_PFC_FUNCTION(vin0),
++	SH_PFC_FUNCTION(vin1),
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++#define F_(x, y)	FN_##y
++#define FM(x)		FN_##x
++	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_21_FN,	GPSR0_21,
++		GP_0_20_FN,	GPSR0_20,
++		GP_0_19_FN,	GPSR0_19,
++		GP_0_18_FN,	GPSR0_18,
++		GP_0_17_FN,	GPSR0_17,
++		GP_0_16_FN,	GPSR0_16,
++		GP_0_15_FN,	GPSR0_15,
++		GP_0_14_FN,	GPSR0_14,
++		GP_0_13_FN,	GPSR0_13,
++		GP_0_12_FN,	GPSR0_12,
++		GP_0_11_FN,	GPSR0_11,
++		GP_0_10_FN,	GPSR0_10,
++		GP_0_9_FN,	GPSR0_9,
++		GP_0_8_FN,	GPSR0_8,
++		GP_0_7_FN,	GPSR0_7,
++		GP_0_6_FN,	GPSR0_6,
++		GP_0_5_FN,	GPSR0_5,
++		GP_0_4_FN,	GPSR0_4,
++		GP_0_3_FN,	GPSR0_3,
++		GP_0_2_FN,	GPSR0_2,
++		GP_0_1_FN,	GPSR0_1,
++		GP_0_0_FN,	GPSR0_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_27_FN,	GPSR1_27,
++		GP_1_26_FN,	GPSR1_26,
++		GP_1_25_FN,	GPSR1_25,
++		GP_1_24_FN,	GPSR1_24,
++		GP_1_23_FN,	GPSR1_23,
++		GP_1_22_FN,	GPSR1_22,
++		GP_1_21_FN,	GPSR1_21,
++		GP_1_20_FN,	GPSR1_20,
++		GP_1_19_FN,	GPSR1_19,
++		GP_1_18_FN,	GPSR1_18,
++		GP_1_17_FN,	GPSR1_17,
++		GP_1_16_FN,	GPSR1_16,
++		GP_1_15_FN,	GPSR1_15,
++		GP_1_14_FN,	GPSR1_14,
++		GP_1_13_FN,	GPSR1_13,
++		GP_1_12_FN,	GPSR1_12,
++		GP_1_11_FN,	GPSR1_11,
++		GP_1_10_FN,	GPSR1_10,
++		GP_1_9_FN,	GPSR1_9,
++		GP_1_8_FN,	GPSR1_8,
++		GP_1_7_FN,	GPSR1_7,
++		GP_1_6_FN,	GPSR1_6,
++		GP_1_5_FN,	GPSR1_5,
++		GP_1_4_FN,	GPSR1_4,
++		GP_1_3_FN,	GPSR1_3,
++		GP_1_2_FN,	GPSR1_2,
++		GP_1_1_FN,	GPSR1_1,
++		GP_1_0_FN,	GPSR1_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		GP_2_29_FN,	GPSR2_29,
++		GP_2_28_FN,	GPSR2_28,
++		GP_2_27_FN,	GPSR2_27,
++		GP_2_26_FN,	GPSR2_26,
++		GP_2_25_FN,	GPSR2_25,
++		GP_2_24_FN,	GPSR2_24,
++		GP_2_23_FN,	GPSR2_23,
++		GP_2_22_FN,	GPSR2_22,
++		GP_2_21_FN,	GPSR2_21,
++		GP_2_20_FN,	GPSR2_20,
++		GP_2_19_FN,	GPSR2_19,
++		GP_2_18_FN,	GPSR2_18,
++		GP_2_17_FN,	GPSR2_17,
++		GP_2_16_FN,	GPSR2_16,
++		GP_2_15_FN,	GPSR2_15,
++		GP_2_14_FN,	GPSR2_14,
++		GP_2_13_FN,	GPSR2_13,
++		GP_2_12_FN,	GPSR2_12,
++		GP_2_11_FN,	GPSR2_11,
++		GP_2_10_FN,	GPSR2_10,
++		GP_2_9_FN,	GPSR2_9,
++		GP_2_8_FN,	GPSR2_8,
++		GP_2_7_FN,	GPSR2_7,
++		GP_2_6_FN,	GPSR2_6,
++		GP_2_5_FN,	GPSR2_5,
++		GP_2_4_FN,	GPSR2_4,
++		GP_2_3_FN,	GPSR2_3,
++		GP_2_2_FN,	GPSR2_2,
++		GP_2_1_FN,	GPSR2_1,
++		GP_2_0_FN,	GPSR2_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_FN,	GPSR3_16,
++		GP_3_15_FN,	GPSR3_15,
++		GP_3_14_FN,	GPSR3_14,
++		GP_3_13_FN,	GPSR3_13,
++		GP_3_12_FN,	GPSR3_12,
++		GP_3_11_FN,	GPSR3_11,
++		GP_3_10_FN,	GPSR3_10,
++		GP_3_9_FN,	GPSR3_9,
++		GP_3_8_FN,	GPSR3_8,
++		GP_3_7_FN,	GPSR3_7,
++		GP_3_6_FN,	GPSR3_6,
++		GP_3_5_FN,	GPSR3_5,
++		GP_3_4_FN,	GPSR3_4,
++		GP_3_3_FN,	GPSR3_3,
++		GP_3_2_FN,	GPSR3_2,
++		GP_3_1_FN,	GPSR3_1,
++		GP_3_0_FN,	GPSR3_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_24_FN,	GPSR4_24,
++		GP_4_23_FN,	GPSR4_23,
++		GP_4_22_FN,	GPSR4_22,
++		GP_4_21_FN,	GPSR4_21,
++		GP_4_20_FN,	GPSR4_20,
++		GP_4_19_FN,	GPSR4_19,
++		GP_4_18_FN,	GPSR4_18,
++		GP_4_17_FN,	GPSR4_17,
++		GP_4_16_FN,	GPSR4_16,
++		GP_4_15_FN,	GPSR4_15,
++		GP_4_14_FN,	GPSR4_14,
++		GP_4_13_FN,	GPSR4_13,
++		GP_4_12_FN,	GPSR4_12,
++		GP_4_11_FN,	GPSR4_11,
++		GP_4_10_FN,	GPSR4_10,
++		GP_4_9_FN,	GPSR4_9,
++		GP_4_8_FN,	GPSR4_8,
++		GP_4_7_FN,	GPSR4_7,
++		GP_4_6_FN,	GPSR4_6,
++		GP_4_5_FN,	GPSR4_5,
++		GP_4_4_FN,	GPSR4_4,
++		GP_4_3_FN,	GPSR4_3,
++		GP_4_2_FN,	GPSR4_2,
++		GP_4_1_FN,	GPSR4_1,
++		GP_4_0_FN,	GPSR4_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_14_FN,	GPSR5_14,
++		GP_5_13_FN,	GPSR5_13,
++		GP_5_12_FN,	GPSR5_12,
++		GP_5_11_FN,	GPSR5_11,
++		GP_5_10_FN,	GPSR5_10,
++		GP_5_9_FN,	GPSR5_9,
++		GP_5_8_FN,	GPSR5_8,
++		GP_5_7_FN,	GPSR5_7,
++		GP_5_6_FN,	GPSR5_6,
++		GP_5_5_FN,	GPSR5_5,
++		GP_5_4_FN,	GPSR5_4,
++		GP_5_3_FN,	GPSR5_3,
++		GP_5_2_FN,	GPSR5_2,
++		GP_5_1_FN,	GPSR5_1,
++		GP_5_0_FN,	GPSR5_0, }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
++		IP0_31_28
++		IP0_27_24
++		IP0_23_20
++		IP0_19_16
++		IP0_15_12
++		IP0_11_8
++		IP0_7_4
++		IP0_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
++		IP1_31_28
++		IP1_27_24
++		IP1_23_20
++		IP1_19_16
++		IP1_15_12
++		IP1_11_8
++		IP1_7_4
++		IP1_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
++		IP2_31_28
++		IP2_27_24
++		IP2_23_20
++		IP2_19_16
++		IP2_15_12
++		IP2_11_8
++		IP2_7_4
++		IP2_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
++		IP3_31_28
++		IP3_27_24
++		IP3_23_20
++		IP3_19_16
++		IP3_15_12
++		IP3_11_8
++		IP3_7_4
++		IP3_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
++		IP4_31_28
++		IP4_27_24
++		IP4_23_20
++		IP4_19_16
++		IP4_15_12
++		IP4_11_8
++		IP4_7_4
++		IP4_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
++		IP5_31_28
++		IP5_27_24
++		IP5_23_20
++		IP5_19_16
++		IP5_15_12
++		IP5_11_8
++		IP5_7_4
++		IP5_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
++		IP6_31_28
++		IP6_27_24
++		IP6_23_20
++		IP6_19_16
++		IP6_15_12
++		IP6_11_8
++		IP6_7_4
++		IP6_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
++		IP7_31_28
++		IP7_27_24
++		IP7_23_20
++		IP7_19_16
++		IP7_15_12
++		IP7_11_8
++		IP7_7_4
++		IP7_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
++		IP9_31_28
++		IP9_27_24
++		IP9_23_20
++		IP9_19_16
++		IP9_15_12
++		IP9_11_8
++		IP9_7_4
++		IP9_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
++		IP10_31_28
++		IP10_27_24
++		IP10_23_20
++		IP10_19_16
++		IP10_15_12
++		IP10_11_8
++		IP10_7_4
++		IP10_3_0 }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
++			     4, 4, 4, 4,
++			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
++		/* RESERVED 31, 30, 29, 28 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 27, 26, 25, 24 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 23, 22, 21, 20 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 19, 18, 17, 16 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		/* RESERVED 15, 14, 13, 12 */
++		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
++		MOD_SEL0_11
++		MOD_SEL0_10
++		MOD_SEL0_9
++		MOD_SEL0_8
++		MOD_SEL0_7
++		MOD_SEL0_6
++		MOD_SEL0_5
++		MOD_SEL0_4
++		0, 0,
++		MOD_SEL0_2
++		MOD_SEL0_1
++		MOD_SEL0_0 }
++	},
++	{ },
++};
++
++const struct sh_pfc_soc_info r8a77980_pinmux_info = {
++	.name = "r8a77980_pfc",
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 05a3ff81e4a4..62d36804becc 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -285,6 +285,7 @@ extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
++extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+-- 
+2.19.0
+
diff --git a/patches/0873-pinctrl-sh-pfc-r8a77970-Add-EtherAVB-pin-groups.patch b/patches/0873-pinctrl-sh-pfc-r8a77970-Add-EtherAVB-pin-groups.patch
new file mode 100644
index 00000000000000..ea84b023c42ff7
--- /dev/null
+++ b/patches/0873-pinctrl-sh-pfc-r8a77970-Add-EtherAVB-pin-groups.patch
@@ -0,0 +1,149 @@
+From 34919ac691f5eabea484e4829498dd008c3f562b Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 13 Mar 2018 22:54:42 +0300
+Subject: [PATCH 0873/1795] pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groups
+
+Add the EtherAVB pin groups to the R8A77970 PFC driver.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b3cbd8a56774610f5361c8007d66bf8cc695ad53)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 98 +++++++++++++++++++++++++++
+ 1 file changed, 98 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+index 794f12d74449..b1bb7263532b 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+@@ -728,6 +728,82 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
+ };
+ 
++/* - AVB0 ------------------------------------------------------------------- */
++static const unsigned int avb0_link_pins[] = {
++	/* AVB0_LINK */
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int avb0_link_mux[] = {
++	AVB0_LINK_MARK,
++};
++static const unsigned int avb0_magic_pins[] = {
++	/* AVB0_MAGIC */
++	RCAR_GP_PIN(1, 16),
++};
++static const unsigned int avb0_magic_mux[] = {
++	AVB0_MAGIC_MARK,
++};
++static const unsigned int avb0_phy_int_pins[] = {
++	/* AVB0_PHY_INT */
++	RCAR_GP_PIN(1, 17),
++};
++static const unsigned int avb0_phy_int_mux[] = {
++	AVB0_PHY_INT_MARK,
++};
++static const unsigned int avb0_mdio_pins[] = {
++	/* AVB0_MDC, AVB0_MDIO */
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
++};
++static const unsigned int avb0_mdio_mux[] = {
++	AVB0_MDC_MARK, AVB0_MDIO_MARK,
++};
++static const unsigned int avb0_rgmii_pins[] = {
++	/*
++	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
++	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
++	 */
++	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
++	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
++	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
++	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
++	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
++	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
++};
++static const unsigned int avb0_rgmii_mux[] = {
++	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
++	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
++	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
++	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
++};
++static const unsigned int avb0_txcrefclk_pins[] = {
++	/* AVB0_TXCREFCLK */
++	RCAR_GP_PIN(1, 13),
++};
++static const unsigned int avb0_txcrefclk_mux[] = {
++	AVB0_TXCREFCLK_MARK,
++};
++static const unsigned int avb0_avtp_pps_pins[] = {
++	/* AVB0_AVTP_PPS */
++	RCAR_GP_PIN(2, 6),
++};
++static const unsigned int avb0_avtp_pps_mux[] = {
++	AVB0_AVTP_PPS_MARK,
++};
++static const unsigned int avb0_avtp_capture_pins[] = {
++	/* AVB0_AVTP_CAPTURE */
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int avb0_avtp_capture_mux[] = {
++	AVB0_AVTP_CAPTURE_MARK,
++};
++static const unsigned int avb0_avtp_match_pins[] = {
++	/* AVB0_AVTP_MATCH */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int avb0_avtp_match_mux[] = {
++	AVB0_AVTP_MATCH_MARK,
++};
++
+ /* - CANFD Clock ------------------------------------------------------------ */
+ static const unsigned int canfd_clk_a_pins[] = {
+ 	/* CANFD_CLK */
+@@ -1599,6 +1675,15 @@ static const unsigned int vin1_clk_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb0_link),
++	SH_PFC_PIN_GROUP(avb0_magic),
++	SH_PFC_PIN_GROUP(avb0_phy_int),
++	SH_PFC_PIN_GROUP(avb0_mdio),
++	SH_PFC_PIN_GROUP(avb0_rgmii),
++	SH_PFC_PIN_GROUP(avb0_txcrefclk),
++	SH_PFC_PIN_GROUP(avb0_avtp_pps),
++	SH_PFC_PIN_GROUP(avb0_avtp_capture),
++	SH_PFC_PIN_GROUP(avb0_avtp_match),
+ 	SH_PFC_PIN_GROUP(canfd_clk_a),
+ 	SH_PFC_PIN_GROUP(canfd_clk_b),
+ 	SH_PFC_PIN_GROUP(canfd0_data_a),
+@@ -1709,6 +1794,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(vin1_clk),
+ };
+ 
++static const char * const avb0_groups[] = {
++	"avb0_link",
++	"avb0_magic",
++	"avb0_phy_int",
++	"avb0_mdio",
++	"avb0_rgmii",
++	"avb0_txcrefclk",
++	"avb0_avtp_pps",
++	"avb0_avtp_capture",
++	"avb0_avtp_match",
++};
++
+ static const char * const canfd_clk_groups[] = {
+ 	"canfd_clk_a",
+ 	"canfd_clk_b",
+@@ -1914,6 +2011,7 @@ static const char * const vin1_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb0),
+ 	SH_PFC_FUNCTION(canfd_clk),
+ 	SH_PFC_FUNCTION(canfd0),
+ 	SH_PFC_FUNCTION(canfd1),
+-- 
+2.19.0
+
diff --git a/patches/0874-pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_.patch b/patches/0874-pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_.patch
new file mode 100644
index 00000000000000..a82366ec8ed04c
--- /dev/null
+++ b/patches/0874-pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_.patch
@@ -0,0 +1,54 @@
+From dd483c3cea2cef737fa74f3bc62ca3908c8f513e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 13:13:47 +0100
+Subject: [PATCH 0874/1795] pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to
+ avb_mii group
+
+The pin controller drivers for all R-Car Gen2 SoCs have entries for the
+EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.
+
+Add the missing pin to restore consistency.
+
+Note that technically TX_ER is an optional signal in the MII bus, and
+thus could have its own group, but this is currently not supported by
+any R-Car Gen2 pin controller driver.
+
+Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 66e9fe1ec73929a9f7326856699d262bab8e9fb0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+index b769c05480da..f6332f247368 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+@@ -1835,8 +1835,8 @@ static const unsigned int avb_mii_pins[] = {
+ 	RCAR_GP_PIN(2, 2),
+ 
+ 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
+-	RCAR_GP_PIN(3, 12),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
+ };
+ static const unsigned int avb_mii_mux[] = {
+ 	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+@@ -1846,8 +1846,8 @@ static const unsigned int avb_mii_mux[] = {
+ 	AVB_RXD3_MARK,
+ 
+ 	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+-	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
+-	AVB_COL_MARK,
++	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
++	AVB_TX_CLK_MARK, AVB_COL_MARK,
+ };
+ static const unsigned int avb_gmii_pins[] = {
+ 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+-- 
+2.19.0
+
diff --git a/patches/0875-pinctrl-sh-pfc-Add-SH_PFC_PIN_GROUP_ALIAS.patch b/patches/0875-pinctrl-sh-pfc-Add-SH_PFC_PIN_GROUP_ALIAS.patch
new file mode 100644
index 00000000000000..c43c63e8f57037
--- /dev/null
+++ b/patches/0875-pinctrl-sh-pfc-Add-SH_PFC_PIN_GROUP_ALIAS.patch
@@ -0,0 +1,46 @@
+From f2f1b6aab18b517a311f2b487b936a68469b7f42 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:42:09 +0100
+Subject: [PATCH 0875/1795] pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add a macro to refer to another pin group with a different name.
+
+This will be used to rename wrongly-named pin groups, while retaining
+backwards compatibility with old DTBs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 43a51cd5d623c6142ca050dffc25d5e9972a7a12)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 62d36804becc..7fad897cd9f5 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -39,13 +39,14 @@ struct sh_pfc_pin {
+ 	unsigned int configs;
+ };
+ 
+-#define SH_PFC_PIN_GROUP(n)				\
++#define SH_PFC_PIN_GROUP_ALIAS(alias, n)		\
+ 	{						\
+-		.name = #n,				\
++		.name = #alias,				\
+ 		.pins = n##_pins,			\
+ 		.mux = n##_mux,				\
+ 		.nr_pins = ARRAY_SIZE(n##_pins),	\
+ 	}
++#define SH_PFC_PIN_GROUP(n)	SH_PFC_PIN_GROUP_ALIAS(n, n)
+ 
+ struct sh_pfc_pin_group {
+ 	const char *name;
+-- 
+2.19.0
+
diff --git a/patches/0876-pinctrl-sh-pfc-r8a7795-Rename-EtherAVB-mdc-pin-group.patch b/patches/0876-pinctrl-sh-pfc-r8a7795-Rename-EtherAVB-mdc-pin-group.patch
new file mode 100644
index 00000000000000..8b84da834fb56f
--- /dev/null
+++ b/patches/0876-pinctrl-sh-pfc-r8a7795-Rename-EtherAVB-mdc-pin-group.patch
@@ -0,0 +1,64 @@
+From 4b891b3f0290954c4380f105e3cc0d0e7f24feaa Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:45:09 +0100
+Subject: [PATCH 0876/1795] pinctrl: sh-pfc: r8a7795: Rename EtherAVB "mdc" pin
+ group to "mdio"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, while retaining backwards
+compatibility with old DTBs using a pin group alias.
+
+Fixes: 30c078de6f3785fe ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit cbe0dd9ad5b2290ef5946890545446d008496966)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 706ffe153087..ee7e38c78097 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1711,11 +1711,11 @@ static const unsigned int avb_phy_int_pins[] = {
+ static const unsigned int avb_phy_int_mux[] = {
+ 	AVB_PHY_INT_MARK,
+ };
+-static const unsigned int avb_mdc_pins[] = {
++static const unsigned int avb_mdio_pins[] = {
+ 	/* AVB_MDC, AVB_MDIO */
+ 	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ };
+-static const unsigned int avb_mdc_mux[] = {
++static const unsigned int avb_mdio_mux[] = {
+ 	AVB_MDC_MARK, AVB_MDIO_MARK,
+ };
+ static const unsigned int avb_mii_pins[] = {
+@@ -4342,7 +4342,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+ 	SH_PFC_PIN_GROUP(avb_phy_int),
+-	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
++	SH_PFC_PIN_GROUP(avb_mdio),
+ 	SH_PFC_PIN_GROUP(avb_mii),
+ 	SH_PFC_PIN_GROUP(avb_avtp_pps),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
+@@ -4692,7 +4693,8 @@ static const char * const avb_groups[] = {
+ 	"avb_link",
+ 	"avb_magic",
+ 	"avb_phy_int",
+-	"avb_mdc",
++	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
++	"avb_mdio",
+ 	"avb_mii",
+ 	"avb_avtp_pps",
+ 	"avb_avtp_match_a",
+-- 
+2.19.0
+
diff --git a/patches/0877-pinctrl-sh-pfc-r8a7795-es1-Rename-EtherAVB-mdc-pin-g.patch b/patches/0877-pinctrl-sh-pfc-r8a7795-es1-Rename-EtherAVB-mdc-pin-g.patch
new file mode 100644
index 00000000000000..8f8f7f0d9c39c7
--- /dev/null
+++ b/patches/0877-pinctrl-sh-pfc-r8a7795-es1-Rename-EtherAVB-mdc-pin-g.patch
@@ -0,0 +1,65 @@
+From d1722bc751e70f6647f11f9cc640ce49b5e080ad Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:47:54 +0100
+Subject: [PATCH 0877/1795] pinctrl: sh-pfc: r8a7795-es1: Rename EtherAVB "mdc"
+ pin group to "mdio"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, while retaining backwards
+compatibility with old DTBs using a pin group alias.
+
+Fixes: b25719eb938eb39a ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins")
+Fixes: 819fd4bfcc84805c ("pinctrl: sh-pfc: r8a7795: add EtherAVB support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 24cfe1a9704711a62eef3bc7b921c976abd27cd2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 0cf0b8512482..82a1c411c952 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -1652,11 +1652,11 @@ static const unsigned int avb_phy_int_pins[] = {
+ static const unsigned int avb_phy_int_mux[] = {
+ 	AVB_PHY_INT_MARK,
+ };
+-static const unsigned int avb_mdc_pins[] = {
++static const unsigned int avb_mdio_pins[] = {
+ 	/* AVB_MDC, AVB_MDIO */
+ 	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ };
+-static const unsigned int avb_mdc_mux[] = {
++static const unsigned int avb_mdio_mux[] = {
+ 	AVB_MDC_MARK, AVB_MDIO_MARK,
+ };
+ static const unsigned int avb_mii_pins[] = {
+@@ -3859,7 +3859,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+ 	SH_PFC_PIN_GROUP(avb_phy_int),
+-	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
++	SH_PFC_PIN_GROUP(avb_mdio),
+ 	SH_PFC_PIN_GROUP(avb_mii),
+ 	SH_PFC_PIN_GROUP(avb_avtp_pps),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
+@@ -4178,7 +4179,8 @@ static const char * const avb_groups[] = {
+ 	"avb_link",
+ 	"avb_magic",
+ 	"avb_phy_int",
+-	"avb_mdc",
++	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
++	"avb_mdio",
+ 	"avb_mii",
+ 	"avb_avtp_pps",
+ 	"avb_avtp_match_a",
+-- 
+2.19.0
+
diff --git a/patches/0878-pinctrl-sh-pfc-r8a7796-Rename-EtherAVB-mdc-pin-group.patch b/patches/0878-pinctrl-sh-pfc-r8a7796-Rename-EtherAVB-mdc-pin-group.patch
new file mode 100644
index 00000000000000..aa8d3fe5406100
--- /dev/null
+++ b/patches/0878-pinctrl-sh-pfc-r8a7796-Rename-EtherAVB-mdc-pin-group.patch
@@ -0,0 +1,65 @@
+From 5e922e8fd19b3f774ef3889757da4b6b4e1e4269 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:53:13 +0100
+Subject: [PATCH 0878/1795] pinctrl: sh-pfc: r8a7796: Rename EtherAVB "mdc" pin
+ group to "mdio"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, while retaining backwards
+compatibility with old DTBs using a pin group alias.
+
+Fixes: 41397032c4a17dff ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins")
+Fixes: 9c99a63ec74f34f7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 350aba9a74cc3e74ce53642daa9c94326d08c6c3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index e6fff5518a97..d502b0cafeb0 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -1717,11 +1717,11 @@ static const unsigned int avb_phy_int_pins[] = {
+ static const unsigned int avb_phy_int_mux[] = {
+ 	AVB_PHY_INT_MARK,
+ };
+-static const unsigned int avb_mdc_pins[] = {
++static const unsigned int avb_mdio_pins[] = {
+ 	/* AVB_MDC, AVB_MDIO */
+ 	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ };
+-static const unsigned int avb_mdc_mux[] = {
++static const unsigned int avb_mdio_mux[] = {
+ 	AVB_MDC_MARK, AVB_MDIO_MARK,
+ };
+ static const unsigned int avb_mii_pins[] = {
+@@ -4311,7 +4311,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+ 	SH_PFC_PIN_GROUP(avb_phy_int),
+-	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
++	SH_PFC_PIN_GROUP(avb_mdio),
+ 	SH_PFC_PIN_GROUP(avb_mii),
+ 	SH_PFC_PIN_GROUP(avb_avtp_pps),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
+@@ -4656,7 +4657,8 @@ static const char * const avb_groups[] = {
+ 	"avb_link",
+ 	"avb_magic",
+ 	"avb_phy_int",
+-	"avb_mdc",
++	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
++	"avb_mdio",
+ 	"avb_mii",
+ 	"avb_avtp_pps",
+ 	"avb_avtp_match_a",
+-- 
+2.19.0
+
diff --git a/patches/0879-pinctrl-sh-pfc-r8a77965-Rename-EtherAVB-mdc-pin-grou.patch b/patches/0879-pinctrl-sh-pfc-r8a77965-Rename-EtherAVB-mdc-pin-grou.patch
new file mode 100644
index 00000000000000..8a939c03e405bb
--- /dev/null
+++ b/patches/0879-pinctrl-sh-pfc-r8a77965-Rename-EtherAVB-mdc-pin-grou.patch
@@ -0,0 +1,64 @@
+From 747a0d28204f5f3025274d96fc22d0c6d156fb1b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:55:44 +0100
+Subject: [PATCH 0879/1795] pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc"
+ pin group to "mdio"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, while retaining backwards
+compatibility with old DTBs using a pin group alias.
+
+Fixes: fa3e8b71b955af86 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit f7ce295cfdf67404a9332e22127ee296c3512155)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index ce2e85033ff4..cea9d0599c12 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1597,11 +1597,11 @@ static const unsigned int avb_phy_int_pins[] = {
+ static const unsigned int avb_phy_int_mux[] = {
+ 	AVB_PHY_INT_MARK,
+ };
+-static const unsigned int avb_mdc_pins[] = {
++static const unsigned int avb_mdio_pins[] = {
+ 	/* AVB_MDC, AVB_MDIO */
+ 	RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ };
+-static const unsigned int avb_mdc_mux[] = {
++static const unsigned int avb_mdio_mux[] = {
+ 	AVB_MDC_MARK, AVB_MDIO_MARK,
+ };
+ static const unsigned int avb_mii_pins[] = {
+@@ -1951,7 +1951,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_link),
+ 	SH_PFC_PIN_GROUP(avb_magic),
+ 	SH_PFC_PIN_GROUP(avb_phy_int),
+-	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
++	SH_PFC_PIN_GROUP(avb_mdio),
+ 	SH_PFC_PIN_GROUP(avb_mii),
+ 	SH_PFC_PIN_GROUP(avb_avtp_pps),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
+@@ -2002,7 +2003,8 @@ static const char * const avb_groups[] = {
+ 	"avb_link",
+ 	"avb_magic",
+ 	"avb_phy_int",
+-	"avb_mdc",
++	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
++	"avb_mdio",
+ 	"avb_mii",
+ 	"avb_avtp_pps",
+ 	"avb_avtp_match_a",
+-- 
+2.19.0
+
diff --git a/patches/0880-pinctrl-sh-pfc-r8a77995-Rename-EtherAVB-mdc-pin-grou.patch b/patches/0880-pinctrl-sh-pfc-r8a77995-Rename-EtherAVB-mdc-pin-grou.patch
new file mode 100644
index 00000000000000..4ba9579ecebf61
--- /dev/null
+++ b/patches/0880-pinctrl-sh-pfc-r8a77995-Rename-EtherAVB-mdc-pin-grou.patch
@@ -0,0 +1,64 @@
+From 2e44694b99955e384ca20f4d489c33eb8feb9499 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 14:54:47 +0100
+Subject: [PATCH 0880/1795] pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc"
+ pin group to "mdio"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, while retaining backwards
+compatibility with old DTBs using a pin group alias.
+
+Fixes: 66abd968d0ef3eb1 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 3b047a9597e4e252991899f019bbfd0271cda814)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 27b9417be59b..cc80dbe1841d 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -988,11 +988,11 @@ static const unsigned int avb0_phy_int_pins[] = {
+ static const unsigned int avb0_phy_int_mux[] = {
+ 	AVB0_PHY_INT_MARK,
+ };
+-static const unsigned int avb0_mdc_pins[] = {
++static const unsigned int avb0_mdio_pins[] = {
+ 	/* AVB0_MDC, AVB0_MDIO */
+ 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
+ };
+-static const unsigned int avb0_mdc_mux[] = {
++static const unsigned int avb0_mdio_mux[] = {
+ 	AVB0_MDC_MARK, AVB0_MDIO_MARK,
+ };
+ static const unsigned int avb0_mii_pins[] = {
+@@ -1800,7 +1800,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb0_link),
+ 	SH_PFC_PIN_GROUP(avb0_magic),
+ 	SH_PFC_PIN_GROUP(avb0_phy_int),
+-	SH_PFC_PIN_GROUP(avb0_mdc),
++	SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio),	/* Deprecated */
++	SH_PFC_PIN_GROUP(avb0_mdio),
+ 	SH_PFC_PIN_GROUP(avb0_mii),
+ 	SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
+ 	SH_PFC_PIN_GROUP(avb0_avtp_match_a),
+@@ -1901,7 +1902,8 @@ static const char * const avb0_groups[] = {
+ 	"avb0_link",
+ 	"avb0_magic",
+ 	"avb0_phy_int",
+-	"avb0_mdc",
++	"avb0_mdc",	/* Deprecated, please use "avb0_mdio" instead */
++	"avb0_mdio",
+ 	"avb0_mii",
+ 	"avb0_avtp_pps_a",
+ 	"avb0_avtp_match_a",
+-- 
+2.19.0
+
diff --git a/patches/0881-pinctrl-sh-pfc-r8a7795-Correct-VIN4-18-bit-pins.patch b/patches/0881-pinctrl-sh-pfc-r8a7795-Correct-VIN4-18-bit-pins.patch
new file mode 100644
index 00000000000000..06d168688fa32e
--- /dev/null
+++ b/patches/0881-pinctrl-sh-pfc-r8a7795-Correct-VIN4-18-bit-pins.patch
@@ -0,0 +1,85 @@
+From 4fde70e4847096f64feefa316287836a3b4464c4 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:18 +0100
+Subject: [PATCH 0881/1795] pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pins
+
+RGB666 has a pin assignment that differs from the other formats.
+
+Fixes: 6b4de408105fc51e ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions")
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b538dc5bbb40dbf214987cc2f30915275057c948)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index ee7e38c78097..3efc3fc56d48 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -4053,48 +4053,48 @@ static const unsigned int vin4_data16_b_mux[] = {
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+ };
+ static const unsigned int vin4_data18_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ };
+ static const unsigned int vin4_data18_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+ 	VI4_DATA10_MARK, VI4_DATA11_MARK,
+ 	VI4_DATA12_MARK, VI4_DATA13_MARK,
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+ static const unsigned int vin4_data18_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ };
+ static const unsigned int vin4_data18_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+ 	VI4_DATA10_MARK, VI4_DATA11_MARK,
+ 	VI4_DATA12_MARK, VI4_DATA13_MARK,
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+ static const unsigned int vin4_data20_a_pins[] = {
+ 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-- 
+2.19.0
+
diff --git a/patches/0882-pinctrl-sh-pfc-r8a7796-Correct-VIN4-18-bit-pins.patch b/patches/0882-pinctrl-sh-pfc-r8a7796-Correct-VIN4-18-bit-pins.patch
new file mode 100644
index 00000000000000..e442d95860ece2
--- /dev/null
+++ b/patches/0882-pinctrl-sh-pfc-r8a7796-Correct-VIN4-18-bit-pins.patch
@@ -0,0 +1,85 @@
+From 7c9b9d89e0b7bc9b3fed6cd5dbfcf7a951ec70d3 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:19 +0100
+Subject: [PATCH 0882/1795] pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pins
+
+RGB666 has a pin assignment that differs from the other formats.
+
+Fixes: 8db6cbabac4f2a02 ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions")
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a66b68ba7f288093ea17802442622ac7c0691c92)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index d502b0cafeb0..4294652402dd 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -4022,48 +4022,48 @@ static const unsigned int vin4_data16_b_mux[] = {
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+ };
+ static const unsigned int vin4_data18_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ };
+ static const unsigned int vin4_data18_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+ 	VI4_DATA10_MARK, VI4_DATA11_MARK,
+ 	VI4_DATA12_MARK, VI4_DATA13_MARK,
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+ static const unsigned int vin4_data18_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ };
+ static const unsigned int vin4_data18_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+ 	VI4_DATA10_MARK, VI4_DATA11_MARK,
+ 	VI4_DATA12_MARK, VI4_DATA13_MARK,
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+ static const unsigned int vin4_data20_a_pins[] = {
+ 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-- 
+2.19.0
+
diff --git a/patches/0883-pinctrl-sh-pfc-r8a77995-Correct-VIN4-18-bit-pins.patch b/patches/0883-pinctrl-sh-pfc-r8a77995-Correct-VIN4-18-bit-pins.patch
new file mode 100644
index 00000000000000..f644c9d5f25d5a
--- /dev/null
+++ b/patches/0883-pinctrl-sh-pfc-r8a77995-Correct-VIN4-18-bit-pins.patch
@@ -0,0 +1,57 @@
+From a05b671e628ef88bf2dfd6bb75459f2c35902e54 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:20 +0100
+Subject: [PATCH 0883/1795] pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pins
+
+RGB666 has a pin assignment that differs from the other formats.
+
+Fixes: fbd452aeb49e552e ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function")
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4fd82963e17b9aaa32b12a136583ceaac532caf6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index cc80dbe1841d..2a83a908a0f7 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1690,26 +1690,26 @@ static const unsigned int vin4_data16_mux[] = {
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+ };
+ static const unsigned int vin4_data18_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ 	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+ 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+ 	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+ 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ };
+ static const unsigned int vin4_data18_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+ 	VI4_DATA2_MARK, VI4_DATA3_MARK,
+ 	VI4_DATA4_MARK, VI4_DATA5_MARK,
+ 	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+ 	VI4_DATA10_MARK, VI4_DATA11_MARK,
+ 	VI4_DATA12_MARK, VI4_DATA13_MARK,
+ 	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
++	VI4_DATA18_MARK, VI4_DATA19_MARK,
++	VI4_DATA20_MARK, VI4_DATA21_MARK,
++	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+ static const unsigned int vin4_data20_pins[] = {
+ 	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-- 
+2.19.0
+
diff --git a/patches/0884-pinctrl-sh-pfc-r8a7795-Deduplicate-VIN4-pin-definiti.patch b/patches/0884-pinctrl-sh-pfc-r8a7795-Deduplicate-VIN4-pin-definiti.patch
new file mode 100644
index 00000000000000..47c36b501c00e9
--- /dev/null
+++ b/patches/0884-pinctrl-sh-pfc-r8a7795-Deduplicate-VIN4-pin-definiti.patch
@@ -0,0 +1,359 @@
+From 21909c51b08e3bf3127f582c6e460449c4544759 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:43 +0100
+Subject: [PATCH 0884/1795] pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin
+ definitions
+
+Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
+in pin definitions.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9942a5b52990b8d556d85dc8a84ddebb85d9a467)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 308 +++++++--------------------
+ 1 file changed, 72 insertions(+), 236 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 3efc3fc56d48..7100a2dd65f8 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3928,130 +3928,6 @@ static const unsigned int usb30_mux[] = {
+ };
+ 
+ /* - VIN4 ------------------------------------------------------------------- */
+-static const unsigned int vin4_data8_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-};
+-static const unsigned int vin4_data8_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-};
+-static const unsigned int vin4_data8_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-};
+-static const unsigned int vin4_data8_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-};
+-static const unsigned int vin4_data10_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-};
+-static const unsigned int vin4_data10_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-};
+-static const unsigned int vin4_data10_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-};
+-static const unsigned int vin4_data10_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-};
+-static const unsigned int vin4_data12_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-};
+-static const unsigned int vin4_data12_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-};
+-static const unsigned int vin4_data12_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-};
+-static const unsigned int vin4_data12_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-};
+-static const unsigned int vin4_data16_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-};
+-static const unsigned int vin4_data16_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-};
+-static const unsigned int vin4_data16_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-};
+-static const unsigned int vin4_data16_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-};
+ static const unsigned int vin4_data18_a_pins[] = {
+ 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+@@ -4096,109 +3972,69 @@ static const unsigned int vin4_data18_b_mux[] = {
+ 	VI4_DATA20_MARK, VI4_DATA21_MARK,
+ 	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+-static const unsigned int vin4_data20_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-};
+-static const unsigned int vin4_data20_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-};
+-static const unsigned int vin4_data20_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-};
+-static const unsigned int vin4_data20_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-};
+-static const unsigned int vin4_data24_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++static const union vin_data vin4_data_a_pins = {
++	.data24 = {
++		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	},
+ };
+-static const unsigned int vin4_data24_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-	VI4_DATA20_MARK, VI4_DATA21_MARK,
+-	VI4_DATA22_MARK, VI4_DATA23_MARK,
++static const union vin_data vin4_data_a_mux = {
++	.data24 = {
++		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++		VI4_DATA8_MARK,  VI4_DATA9_MARK,
++		VI4_DATA10_MARK, VI4_DATA11_MARK,
++		VI4_DATA12_MARK, VI4_DATA13_MARK,
++		VI4_DATA14_MARK, VI4_DATA15_MARK,
++		VI4_DATA16_MARK, VI4_DATA17_MARK,
++		VI4_DATA18_MARK, VI4_DATA19_MARK,
++		VI4_DATA20_MARK, VI4_DATA21_MARK,
++		VI4_DATA22_MARK, VI4_DATA23_MARK,
++	},
+ };
+-static const unsigned int vin4_data24_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++static const union vin_data vin4_data_b_pins = {
++	.data24 = {
++		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	},
+ };
+-static const unsigned int vin4_data24_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-	VI4_DATA20_MARK, VI4_DATA21_MARK,
+-	VI4_DATA22_MARK, VI4_DATA23_MARK,
++static const union vin_data vin4_data_b_mux = {
++	.data24 = {
++		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++		VI4_DATA8_MARK,  VI4_DATA9_MARK,
++		VI4_DATA10_MARK, VI4_DATA11_MARK,
++		VI4_DATA12_MARK, VI4_DATA13_MARK,
++		VI4_DATA14_MARK, VI4_DATA15_MARK,
++		VI4_DATA16_MARK, VI4_DATA17_MARK,
++		VI4_DATA18_MARK, VI4_DATA19_MARK,
++		VI4_DATA20_MARK, VI4_DATA21_MARK,
++		VI4_DATA22_MARK, VI4_DATA23_MARK,
++	},
+ };
+ static const unsigned int vin4_sync_pins[] = {
+ 	/* HSYNC#, VSYNC# */
+@@ -4641,20 +4477,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb2),
+ 	SH_PFC_PIN_GROUP(usb2_ch3),
+ 	SH_PFC_PIN_GROUP(usb30),
+-	SH_PFC_PIN_GROUP(vin4_data8_a),
+-	SH_PFC_PIN_GROUP(vin4_data10_a),
+-	SH_PFC_PIN_GROUP(vin4_data12_a),
+-	SH_PFC_PIN_GROUP(vin4_data16_a),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 8),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 10),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 12),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ 	SH_PFC_PIN_GROUP(vin4_data18_a),
+-	SH_PFC_PIN_GROUP(vin4_data20_a),
+-	SH_PFC_PIN_GROUP(vin4_data24_a),
+-	SH_PFC_PIN_GROUP(vin4_data8_b),
+-	SH_PFC_PIN_GROUP(vin4_data10_b),
+-	SH_PFC_PIN_GROUP(vin4_data12_b),
+-	SH_PFC_PIN_GROUP(vin4_data16_b),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 20),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 24),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 8),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 10),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 12),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ 	SH_PFC_PIN_GROUP(vin4_data18_b),
+-	SH_PFC_PIN_GROUP(vin4_data20_b),
+-	SH_PFC_PIN_GROUP(vin4_data24_b),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 20),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ 	SH_PFC_PIN_GROUP(vin4_sync),
+ 	SH_PFC_PIN_GROUP(vin4_field),
+ 	SH_PFC_PIN_GROUP(vin4_clkenb),
+-- 
+2.19.0
+
diff --git a/patches/0885-pinctrl-sh-pfc-r8a7796-Deduplicate-VIN4-pin-definiti.patch b/patches/0885-pinctrl-sh-pfc-r8a7796-Deduplicate-VIN4-pin-definiti.patch
new file mode 100644
index 00000000000000..ff411ecf17e16e
--- /dev/null
+++ b/patches/0885-pinctrl-sh-pfc-r8a7796-Deduplicate-VIN4-pin-definiti.patch
@@ -0,0 +1,359 @@
+From ed2a45b3f130d9c9fd88279d70a6235e6ffaa319 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:44 +0100
+Subject: [PATCH 0885/1795] pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin
+ definitions
+
+Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
+in pin definitions.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a5c2949ff7bd9e04be2cdd1b52af1acf9be82ba0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 308 +++++++--------------------
+ 1 file changed, 72 insertions(+), 236 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 4294652402dd..4bc5b1f820c1 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -3897,130 +3897,6 @@ static const unsigned int usb30_mux[] = {
+ };
+ 
+ /* - VIN4 ------------------------------------------------------------------- */
+-static const unsigned int vin4_data8_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-};
+-static const unsigned int vin4_data8_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-};
+-static const unsigned int vin4_data8_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-};
+-static const unsigned int vin4_data8_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-};
+-static const unsigned int vin4_data10_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-};
+-static const unsigned int vin4_data10_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-};
+-static const unsigned int vin4_data10_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-};
+-static const unsigned int vin4_data10_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-};
+-static const unsigned int vin4_data12_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-};
+-static const unsigned int vin4_data12_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-};
+-static const unsigned int vin4_data12_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-};
+-static const unsigned int vin4_data12_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-};
+-static const unsigned int vin4_data16_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-};
+-static const unsigned int vin4_data16_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-};
+-static const unsigned int vin4_data16_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-};
+-static const unsigned int vin4_data16_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-};
+ static const unsigned int vin4_data18_a_pins[] = {
+ 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+@@ -4065,109 +3941,69 @@ static const unsigned int vin4_data18_b_mux[] = {
+ 	VI4_DATA20_MARK, VI4_DATA21_MARK,
+ 	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+-static const unsigned int vin4_data20_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-};
+-static const unsigned int vin4_data20_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-};
+-static const unsigned int vin4_data20_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-};
+-static const unsigned int vin4_data20_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-};
+-static const unsigned int vin4_data24_a_pins[] = {
+-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+-	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+-	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++static const union vin_data vin4_data_a_pins = {
++	.data24 = {
++		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
++		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
++		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
++		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
++		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	},
+ };
+-static const unsigned int vin4_data24_a_mux[] = {
+-	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+-	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+-	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+-	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-	VI4_DATA20_MARK, VI4_DATA21_MARK,
+-	VI4_DATA22_MARK, VI4_DATA23_MARK,
++static const union vin_data vin4_data_a_mux = {
++	.data24 = {
++		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
++		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
++		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
++		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
++		VI4_DATA8_MARK,  VI4_DATA9_MARK,
++		VI4_DATA10_MARK, VI4_DATA11_MARK,
++		VI4_DATA12_MARK, VI4_DATA13_MARK,
++		VI4_DATA14_MARK, VI4_DATA15_MARK,
++		VI4_DATA16_MARK, VI4_DATA17_MARK,
++		VI4_DATA18_MARK, VI4_DATA19_MARK,
++		VI4_DATA20_MARK, VI4_DATA21_MARK,
++		VI4_DATA22_MARK, VI4_DATA23_MARK,
++	},
+ };
+-static const unsigned int vin4_data24_b_pins[] = {
+-	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+-	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++static const union vin_data vin4_data_b_pins = {
++	.data24 = {
++		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
++		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++	},
+ };
+-static const unsigned int vin4_data24_b_mux[] = {
+-	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+-	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+-	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+-	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-	VI4_DATA20_MARK, VI4_DATA21_MARK,
+-	VI4_DATA22_MARK, VI4_DATA23_MARK,
++static const union vin_data vin4_data_b_mux = {
++	.data24 = {
++		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
++		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
++		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
++		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
++		VI4_DATA8_MARK,  VI4_DATA9_MARK,
++		VI4_DATA10_MARK, VI4_DATA11_MARK,
++		VI4_DATA12_MARK, VI4_DATA13_MARK,
++		VI4_DATA14_MARK, VI4_DATA15_MARK,
++		VI4_DATA16_MARK, VI4_DATA17_MARK,
++		VI4_DATA18_MARK, VI4_DATA19_MARK,
++		VI4_DATA20_MARK, VI4_DATA21_MARK,
++		VI4_DATA22_MARK, VI4_DATA23_MARK,
++	},
+ };
+ static const unsigned int vin4_sync_pins[] = {
+ 	/* HSYNC#, VSYNC# */
+@@ -4605,20 +4441,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb30),
+-	SH_PFC_PIN_GROUP(vin4_data8_a),
+-	SH_PFC_PIN_GROUP(vin4_data10_a),
+-	SH_PFC_PIN_GROUP(vin4_data12_a),
+-	SH_PFC_PIN_GROUP(vin4_data16_a),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 8),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 10),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 12),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ 	SH_PFC_PIN_GROUP(vin4_data18_a),
+-	SH_PFC_PIN_GROUP(vin4_data20_a),
+-	SH_PFC_PIN_GROUP(vin4_data24_a),
+-	SH_PFC_PIN_GROUP(vin4_data8_b),
+-	SH_PFC_PIN_GROUP(vin4_data10_b),
+-	SH_PFC_PIN_GROUP(vin4_data12_b),
+-	SH_PFC_PIN_GROUP(vin4_data16_b),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 20),
++	VIN_DATA_PIN_GROUP(vin4_data_a, 24),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 8),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 10),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 12),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ 	SH_PFC_PIN_GROUP(vin4_data18_b),
+-	SH_PFC_PIN_GROUP(vin4_data20_b),
+-	SH_PFC_PIN_GROUP(vin4_data24_b),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 20),
++	VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ 	SH_PFC_PIN_GROUP(vin4_sync),
+ 	SH_PFC_PIN_GROUP(vin4_field),
+ 	SH_PFC_PIN_GROUP(vin4_clkenb),
+-- 
+2.19.0
+
diff --git a/patches/0886-pinctrl-sh-pfc-r8a77995-Deduplicate-VIN4-pin-definit.patch b/patches/0886-pinctrl-sh-pfc-r8a77995-Deduplicate-VIN4-pin-definit.patch
new file mode 100644
index 00000000000000..42a9d4285fbf5b
--- /dev/null
+++ b/patches/0886-pinctrl-sh-pfc-r8a77995-Deduplicate-VIN4-pin-definit.patch
@@ -0,0 +1,202 @@
+From abb3d5d7422baa92010ba3de7799490bca0c5159 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 19 Mar 2018 17:37:45 +0100
+Subject: [PATCH 0886/1795] pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin
+ definitions
+
+Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
+in pin definitions.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit a6fff41f410bf030d5cd178154b8397536e714f9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 154 ++++++--------------------
+ 1 file changed, 36 insertions(+), 118 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+index 2a83a908a0f7..adade5b7ffbc 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+@@ -1627,68 +1627,6 @@ static const unsigned int usb0_mux[] = {
+ };
+ 
+ /* - VIN4 ------------------------------------------------------------------- */
+-static const unsigned int vin4_data8_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-};
+-static const unsigned int vin4_data8_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-};
+-static const unsigned int vin4_data10_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+-};
+-static const unsigned int vin4_data10_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-};
+-static const unsigned int vin4_data12_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+-};
+-static const unsigned int vin4_data12_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-};
+-static const unsigned int vin4_data16_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+-};
+-static const unsigned int vin4_data16_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-};
+ static const unsigned int vin4_data18_pins[] = {
+ 	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+@@ -1711,57 +1649,37 @@ static const unsigned int vin4_data18_mux[] = {
+ 	VI4_DATA20_MARK, VI4_DATA21_MARK,
+ 	VI4_DATA22_MARK, VI4_DATA23_MARK,
+ };
+-static const unsigned int vin4_data20_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+-};
+-static const unsigned int vin4_data20_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-};
+-static const unsigned int vin4_data24_pins[] = {
+-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+-	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+-	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+-	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+-	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+-	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+-	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++static const union vin_data vin4_data_pins = {
++	.data24 = {
++		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
++		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
++		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
++		RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
++		RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
++		RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
++		RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++	},
+ };
+-static const unsigned int vin4_data24_mux[] = {
+-	VI4_DATA0_MARK, VI4_DATA1_MARK,
+-	VI4_DATA2_MARK, VI4_DATA3_MARK,
+-	VI4_DATA4_MARK, VI4_DATA5_MARK,
+-	VI4_DATA6_MARK, VI4_DATA7_MARK,
+-	VI4_DATA8_MARK,  VI4_DATA9_MARK,
+-	VI4_DATA10_MARK, VI4_DATA11_MARK,
+-	VI4_DATA12_MARK, VI4_DATA13_MARK,
+-	VI4_DATA14_MARK, VI4_DATA15_MARK,
+-	VI4_DATA16_MARK, VI4_DATA17_MARK,
+-	VI4_DATA18_MARK, VI4_DATA19_MARK,
+-	VI4_DATA20_MARK, VI4_DATA21_MARK,
+-	VI4_DATA22_MARK, VI4_DATA23_MARK,
++static const union vin_data vin4_data_mux = {
++	.data24 = {
++		VI4_DATA0_MARK, VI4_DATA1_MARK,
++		VI4_DATA2_MARK, VI4_DATA3_MARK,
++		VI4_DATA4_MARK, VI4_DATA5_MARK,
++		VI4_DATA6_MARK, VI4_DATA7_MARK,
++		VI4_DATA8_MARK,  VI4_DATA9_MARK,
++		VI4_DATA10_MARK, VI4_DATA11_MARK,
++		VI4_DATA12_MARK, VI4_DATA13_MARK,
++		VI4_DATA14_MARK, VI4_DATA15_MARK,
++		VI4_DATA16_MARK, VI4_DATA17_MARK,
++		VI4_DATA18_MARK, VI4_DATA19_MARK,
++		VI4_DATA20_MARK, VI4_DATA21_MARK,
++		VI4_DATA22_MARK, VI4_DATA23_MARK,
++	},
+ };
+ static const unsigned int vin4_sync_pins[] = {
+ 	/* HSYNC#, VSYNC# */
+@@ -1878,13 +1796,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+ 	SH_PFC_PIN_GROUP(ssi4_data_b),
+ 	SH_PFC_PIN_GROUP(usb0),
+-	SH_PFC_PIN_GROUP(vin4_data8),
+-	SH_PFC_PIN_GROUP(vin4_data10),
+-	SH_PFC_PIN_GROUP(vin4_data12),
+-	SH_PFC_PIN_GROUP(vin4_data16),
++	VIN_DATA_PIN_GROUP(vin4_data, 8),
++	VIN_DATA_PIN_GROUP(vin4_data, 10),
++	VIN_DATA_PIN_GROUP(vin4_data, 12),
++	VIN_DATA_PIN_GROUP(vin4_data, 16),
+ 	SH_PFC_PIN_GROUP(vin4_data18),
+-	SH_PFC_PIN_GROUP(vin4_data20),
+-	SH_PFC_PIN_GROUP(vin4_data24),
++	VIN_DATA_PIN_GROUP(vin4_data, 20),
++	VIN_DATA_PIN_GROUP(vin4_data, 24),
+ 	SH_PFC_PIN_GROUP(vin4_sync),
+ 	SH_PFC_PIN_GROUP(vin4_field),
+ 	SH_PFC_PIN_GROUP(vin4_clkenb),
+-- 
+2.19.0
+
diff --git a/patches/0887-media-v4l-vsp1-Print-the-correct-blending-unit-name-.patch b/patches/0887-media-v4l-vsp1-Print-the-correct-blending-unit-name-.patch
new file mode 100644
index 00000000000000..c6158dd8c6f6e1
--- /dev/null
+++ b/patches/0887-media-v4l-vsp1-Print-the-correct-blending-unit-name-.patch
@@ -0,0 +1,119 @@
+From 25157f6964fa4d6ddf570055e86b744415f3f73c Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sat, 2 Dec 2017 14:39:51 -0500
+Subject: [PATCH 0887/1795] media: v4l: vsp1: Print the correct blending unit
+ name in debug messages
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The DRM pipelines can use either the BRU or the BRS for blending. Make
+sure the right name is used in debugging messages to avoid confusion.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 5b78f0361caec7e2b809af35facd767da1b9030d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 21 ++++++++-------------
+ 1 file changed, 8 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index ac85942162c1..b8fee1834253 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -27,6 +27,7 @@
+ #include "vsp1_pipe.h"
+ #include "vsp1_rwpf.h"
+ 
++#define BRU_NAME(e)	(e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
+ 
+ /* -----------------------------------------------------------------------------
+  * Interrupt Handling
+@@ -88,7 +89,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_entity *next;
+ 	struct vsp1_dl_list *dl;
+ 	struct v4l2_subdev_format format;
+-	const char *bru_name;
+ 	unsigned long flags;
+ 	unsigned int i;
+ 	int ret;
+@@ -99,7 +99,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	drm_pipe = &vsp1->drm->pipe[pipe_index];
+ 	pipe = &drm_pipe->pipe;
+ 	bru = to_bru(&pipe->bru->subdev);
+-	bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
+ 
+ 	if (!cfg) {
+ 		/*
+@@ -165,7 +164,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 
+ 		dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+ 			__func__, format.format.width, format.format.height,
+-			format.format.code, bru_name, i);
++			format.format.code, BRU_NAME(pipe->bru), i);
+ 	}
+ 
+ 	format.pad = pipe->bru->source_pad;
+@@ -181,7 +180,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 
+ 	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+ 		__func__, format.format.width, format.format.height,
+-		format.format.code, bru_name, i);
++		format.format.code, BRU_NAME(pipe->bru), i);
+ 
+ 	format.pad = RWPF_PAD_SINK;
+ 	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
+@@ -473,9 +472,9 @@ static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+ 		__func__, format.format.width, format.format.height,
+-		format.format.code, format.pad);
++		format.format.code, BRU_NAME(pipe->bru), format.pad);
+ 
+ 	sel.pad = bru_input;
+ 	sel.target = V4L2_SEL_TGT_COMPOSE;
+@@ -486,10 +485,9 @@ static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	dev_dbg(vsp1->dev,
+-		"%s: set selection (%u,%u)/%ux%u on BRU pad %u\n",
++	dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
+ 		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
+-		sel.pad);
++		BRU_NAME(pipe->bru), sel.pad);
+ 
+ 	return 0;
+ }
+@@ -514,12 +512,9 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 	struct vsp1_entity *entity;
+ 	struct vsp1_entity *next;
+ 	struct vsp1_dl_list *dl;
+-	const char *bru_name;
+ 	unsigned int i;
+ 	int ret;
+ 
+-	bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
+-
+ 	/* Prepare the display list. */
+ 	dl = vsp1_dl_list_get(pipe->output->dlm);
+ 
+@@ -570,7 +565,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 		rpf->entity.sink_pad = i;
+ 
+ 		dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
+-			__func__, rpf->entity.index, bru_name, i);
++			__func__, rpf->entity.index, BRU_NAME(pipe->bru), i);
+ 
+ 		ret = vsp1_du_setup_rpf_pipe(vsp1, pipe, rpf, i);
+ 		if (ret < 0)
+-- 
+2.19.0
+
diff --git a/patches/0888-media-v4l-vsp1-Fix-mask-creation-for-MULT_ALPHA_RATI.patch b/patches/0888-media-v4l-vsp1-Fix-mask-creation-for-MULT_ALPHA_RATI.patch
new file mode 100644
index 00000000000000..e860f03b9dcad3
--- /dev/null
+++ b/patches/0888-media-v4l-vsp1-Fix-mask-creation-for-MULT_ALPHA_RATI.patch
@@ -0,0 +1,36 @@
+From 329519899471251125af688a84e205b63c5b8042 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 5 Feb 2018 15:09:58 -0500
+Subject: [PATCH 0888/1795] media: v4l: vsp1: Fix mask creation for
+ MULT_ALPHA_RATIO
+
+Due to a typo, the mask was destroyed by a comparison instead of a bit
+shift. No regression since the mask has not been used yet.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 06227008670afddd5eb66cc6a85c27fd5e72f41e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_regs.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h
+index 26c4ffad2f46..b1912c83a1da 100644
+--- a/drivers/media/platform/vsp1/vsp1_regs.h
++++ b/drivers/media/platform/vsp1/vsp1_regs.h
+@@ -225,7 +225,7 @@
+ #define VI6_RPF_MULT_ALPHA_P_MMD_RATIO	(1 << 8)
+ #define VI6_RPF_MULT_ALPHA_P_MMD_IMAGE	(2 << 8)
+ #define VI6_RPF_MULT_ALPHA_P_MMD_BOTH	(3 << 8)
+-#define VI6_RPF_MULT_ALPHA_RATIO_MASK	(0xff < 0)
++#define VI6_RPF_MULT_ALPHA_RATIO_MASK	(0xff << 0)
+ #define VI6_RPF_MULT_ALPHA_RATIO_SHIFT	0
+ 
+ /* -----------------------------------------------------------------------------
+-- 
+2.19.0
+
diff --git a/patches/0889-media-v4l-vsp1-Fix-video-output-on-R8A77970.patch b/patches/0889-media-v4l-vsp1-Fix-video-output-on-R8A77970.patch
new file mode 100644
index 00000000000000..1cee60b59bf821
--- /dev/null
+++ b/patches/0889-media-v4l-vsp1-Fix-video-output-on-R8A77970.patch
@@ -0,0 +1,79 @@
+From f3c57ef9b7759606444f276e486a2ae585a1e98d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 18 Jan 2018 09:05:51 -0500
+Subject: [PATCH 0889/1795] media: v4l: vsp1: Fix video output on R8A77970
+
+Commit d455b45f8393 ("v4l: vsp1: Add support for new VSP2-BS, VSP2-DL,
+and VSP2-D instances") added support for the VSP2-D found in the R-Car
+V3M (R8A77970) but the video output that VSP2-D sends to DU has a greenish
+garbage-like line repeated every 8 screen rows. It turns out that R-Car
+V3M has the LIF0 buffer attribute register that you need to set to a non-
+default value in order to get rid of the output artifacts.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Fixes: d455b45f8393 ("v4l: vsp1: Add support for new VSP2-BS, VSP2-DL and VSP2-D instances")
+[Removed braces, added VI6_IP_VERSION_MASK to improve readabiliy]
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 7f43ff953f4009655a8b19a6f2fd1f665f4d7c2e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_lif.c  | 12 ++++++++++++
+ drivers/media/platform/vsp1/vsp1_regs.h |  6 ++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index e6fa16d7fda8..704920753998 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -155,6 +155,18 @@ static void lif_configure(struct vsp1_entity *entity,
+ 			(obth << VI6_LIF_CTRL_OBTH_SHIFT) |
+ 			(format->code == 0 ? VI6_LIF_CTRL_CFMT : 0) |
+ 			VI6_LIF_CTRL_REQSEL | VI6_LIF_CTRL_LIF_EN);
++
++	/*
++	 * On R-Car V3M the LIF0 buffer attribute register has to be set to a
++	 * non-default value to guarantee proper operation (otherwise artifacts
++	 * may appear on the output). The value required by the manual is not
++	 * explained but is likely a buffer size or threshold.
++	 */
++	if ((entity->vsp1->version & VI6_IP_VERSION_MASK) ==
++	    (VI6_IP_VERSION_MODEL_VSPD_V3 | VI6_IP_VERSION_SOC_V3M))
++		vsp1_lif_write(lif, dl, VI6_LIF_LBA,
++			       VI6_LIF_LBA_LBA0 |
++			       (1536 << VI6_LIF_LBA_LBA1_SHIFT));
+ }
+ 
+ static const struct vsp1_entity_operations lif_entity_ops = {
+diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h
+index b1912c83a1da..dae0c1901297 100644
+--- a/drivers/media/platform/vsp1/vsp1_regs.h
++++ b/drivers/media/platform/vsp1/vsp1_regs.h
+@@ -693,6 +693,11 @@
+ #define VI6_LIF_CSBTH_LBTH_MASK		(0x7ff << 0)
+ #define VI6_LIF_CSBTH_LBTH_SHIFT	0
+ 
++#define VI6_LIF_LBA			0x3b0c
++#define VI6_LIF_LBA_LBA0		(1 << 31)
++#define VI6_LIF_LBA_LBA1_MASK		(0xfff << 16)
++#define VI6_LIF_LBA_LBA1_SHIFT		16
++
+ /* -----------------------------------------------------------------------------
+  * Security Control Registers
+  */
+@@ -705,6 +710,7 @@
+  */
+ 
+ #define VI6_IP_VERSION			0x3f00
++#define VI6_IP_VERSION_MASK		(0xffff << 0)
+ #define VI6_IP_VERSION_MODEL_MASK	(0xff << 8)
+ #define VI6_IP_VERSION_MODEL_VSPS_H2	(0x09 << 8)
+ #define VI6_IP_VERSION_MODEL_VSPR_H2	(0x0a << 8)
+-- 
+2.19.0
+
diff --git a/patches/0890-watchdog-renesas_wdt-Add-suspend-resume-support.patch b/patches/0890-watchdog-renesas_wdt-Add-suspend-resume-support.patch
new file mode 100644
index 00000000000000..8ba2e14c3d16a0
--- /dev/null
+++ b/patches/0890-watchdog-renesas_wdt-Add-suspend-resume-support.patch
@@ -0,0 +1,80 @@
+From 2d31113f45366078043c89eb2f898a8d919d9c75 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 5 Mar 2018 15:30:24 +0000
+Subject: [PATCH 0890/1795] watchdog: renesas_wdt: Add suspend/resume support
+
+On R-Car Gen2 and RZ/G1 the watchdog IP clock needs to be always ON,
+on R-Car Gen3 we power the IP down during suspend.
+
+This commit adds suspend/resume support, so that the watchdog counting
+"pauses" during suspend on all of the SoCs compatible with this driver
+and on those we are now adding support for (R-Car Gen2 and RZ/G1).
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+(cherry picked from commit 07278ca1ccc9a1241f14a8aaa4f2430b7b217c3f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/watchdog/renesas_wdt.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
+index 831ef83f6de1..024d54eda11e 100644
+--- a/drivers/watchdog/renesas_wdt.c
++++ b/drivers/watchdog/renesas_wdt.c
+@@ -49,6 +49,7 @@ struct rwdt_priv {
+ 	void __iomem *base;
+ 	struct watchdog_device wdev;
+ 	unsigned long clk_rate;
++	u16 time_left;
+ 	u8 cks;
+ };
+ 
+@@ -203,6 +204,30 @@ static int rwdt_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static int __maybe_unused rwdt_suspend(struct device *dev)
++{
++	struct rwdt_priv *priv = dev_get_drvdata(dev);
++
++	if (watchdog_active(&priv->wdev)) {
++		priv->time_left = readw(priv->base + RWTCNT);
++		rwdt_stop(&priv->wdev);
++	}
++	return 0;
++}
++
++static int __maybe_unused rwdt_resume(struct device *dev)
++{
++	struct rwdt_priv *priv = dev_get_drvdata(dev);
++
++	if (watchdog_active(&priv->wdev)) {
++		rwdt_start(&priv->wdev);
++		rwdt_write(priv, priv->time_left, RWTCNT);
++	}
++	return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
++
+ /*
+  * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
+  * to work there, one also needs a RESET (RST) driver which does not exist yet
+@@ -218,6 +243,7 @@ static struct platform_driver rwdt_driver = {
+ 	.driver = {
+ 		.name = "renesas_wdt",
+ 		.of_match_table = rwdt_ids,
++		.pm = &rwdt_pm_ops,
+ 	},
+ 	.probe = rwdt_probe,
+ 	.remove = rwdt_remove,
+-- 
+2.19.0
+
diff --git a/patches/0891-watchdog-renesas_wdt-Add-R-Car-Gen2-support.patch b/patches/0891-watchdog-renesas_wdt-Add-R-Car-Gen2-support.patch
new file mode 100644
index 00000000000000..bfc9d602437c78
--- /dev/null
+++ b/patches/0891-watchdog-renesas_wdt-Add-R-Car-Gen2-support.patch
@@ -0,0 +1,132 @@
+From e3cabcd484fc0c36f73e482743225be9875f4f2b Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 5 Mar 2018 15:30:25 +0000
+Subject: [PATCH 0891/1795] watchdog: renesas_wdt: Add R-Car Gen2 support
+
+Due to commits:
+* "ARM: shmobile: Add watchdog support",
+* "ARM: shmobile: rcar-gen2: Add watchdog support", and
+* "soc: renesas: rcar-rst: Enable watchdog as reset trigger for Gen2",
+we now have everything we needed for the watchdog to work on Gen2 and
+RZ/G1.
+
+However, on early revisions of some R-Car Gen2 SoCs, and depending on SMP
+configuration, the system may fail to restart on watchdog time-out, and
+lock up instead.
+
+Specifically:
+  - On R-Car H2 ES1.0 and M2-W ES1.0, watchdog restart fails unless
+    only the first CPU core is in use (using e.g. the "maxcpus=1" kernel
+    commandline option).
+  - On R-Car V2H ES1.1, watchdog restart fails unless SMP is disabled
+    completely (using CONFIG_SMP=n during build configuration, or using
+    the "nosmp" or "maxcpus=0" kernel commandline options).
+
+This commit adds "renesas,rcar-gen2-wdt" as compatible string for R-Car
+Gen2 and RZ/G1, but also prevents the system from using the watchdog
+driver in cases where the system would fail to restart by blacklisting
+the affected SoCs, using the minimum known working revisions (ES2.0 on R-Car
+H2, and ES3.0 on M2-W), and taking the actual SMP software configuration
+into account.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+[Geert: blacklisting logic]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+
+(cherry picked from commit 3fe95e6c68e6258410e85488af9e1b1ff545b831)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/watchdog/renesas_wdt.c | 49 ++++++++++++++++++++++++++++++----
+ 1 file changed, 44 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
+index 024d54eda11e..0dede5beb3f1 100644
+--- a/drivers/watchdog/renesas_wdt.c
++++ b/drivers/watchdog/renesas_wdt.c
+@@ -16,6 +16,8 @@
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/smp.h>
++#include <linux/sys_soc.h>
+ #include <linux/watchdog.h>
+ 
+ #define RWTCNT		0
+@@ -121,6 +123,44 @@ static const struct watchdog_ops rwdt_ops = {
+ 	.get_timeleft = rwdt_get_timeleft,
+ };
+ 
++#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
++/*
++ * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
++ */
++static const struct soc_device_attribute rwdt_quirks_match[] = {
++	{
++		.soc_id = "r8a7790",
++		.revision = "ES1.*",
++		.data = (void *)1,	/* needs single CPU */
++	}, {
++		.soc_id = "r8a7791",
++		.revision = "ES[12].*",
++		.data = (void *)1,	/* needs single CPU */
++	}, {
++		.soc_id = "r8a7792",
++		.revision = "*",
++		.data = (void *)0,	/* needs SMP disabled */
++	},
++	{ /* sentinel */ }
++};
++
++static bool rwdt_blacklisted(struct device *dev)
++{
++	const struct soc_device_attribute *attr;
++
++	attr = soc_device_match(rwdt_quirks_match);
++	if (attr && setup_max_cpus > (uintptr_t)attr->data) {
++		dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
++			 attr->revision);
++		return true;
++	}
++
++	return false;
++}
++#else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
++static inline bool rwdt_blacklisted(struct device *dev) { return false; }
++#endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
++
+ static int rwdt_probe(struct platform_device *pdev)
+ {
+ 	struct rwdt_priv *priv;
+@@ -129,6 +169,9 @@ static int rwdt_probe(struct platform_device *pdev)
+ 	unsigned long clks_per_sec;
+ 	int ret, i;
+ 
++	if (rwdt_blacklisted(&pdev->dev))
++		return -ENODEV;
++
+ 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
+@@ -228,12 +271,8 @@ static int __maybe_unused rwdt_resume(struct device *dev)
+ 
+ static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
+ 
+-/*
+- * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
+- * to work there, one also needs a RESET (RST) driver which does not exist yet
+- * due to HW issues. This needs to be solved before adding compatibles here.
+- */
+ static const struct of_device_id rwdt_ids[] = {
++	{ .compatible = "renesas,rcar-gen2-wdt", },
+ 	{ .compatible = "renesas,rcar-gen3-wdt", },
+ 	{ /* sentinel */ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/0892-watchdog-renesas_wdt-Add-restart-handler.patch b/patches/0892-watchdog-renesas_wdt-Add-restart-handler.patch
new file mode 100644
index 00000000000000..46a7be64228e23
--- /dev/null
+++ b/patches/0892-watchdog-renesas_wdt-Add-restart-handler.patch
@@ -0,0 +1,65 @@
+From 43f62fde9ae9a0a0899cb26f4e49208e82bb8424 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 5 Mar 2018 15:30:26 +0000
+Subject: [PATCH 0892/1795] watchdog: renesas_wdt: Add restart handler
+
+On iWave's boards iwg20d and iwg22d the only way to reboot the system is
+by means of the watchdog.
+This patch adds a restart handler to rwdt_ops, and also makes sure we
+keep its priority to the lowest level, in order to not override other
+more effective handlers.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+(cherry picked from commit 089bcaa87e772beb005068a5ef28c71bb895d01d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/watchdog/renesas_wdt.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
+index 0dede5beb3f1..6b8c6ddfe30b 100644
+--- a/drivers/watchdog/renesas_wdt.c
++++ b/drivers/watchdog/renesas_wdt.c
+@@ -110,6 +110,16 @@ static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
+ 	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
+ }
+ 
++static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
++			void *data)
++{
++	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
++
++	rwdt_start(wdev);
++	rwdt_write(priv, 0xffff, RWTCNT);
++	return 0;
++}
++
+ static const struct watchdog_info rwdt_ident = {
+ 	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
+ 	.identity = "Renesas WDT Watchdog",
+@@ -121,6 +131,7 @@ static const struct watchdog_ops rwdt_ops = {
+ 	.stop = rwdt_stop,
+ 	.ping = rwdt_init_timeout,
+ 	.get_timeleft = rwdt_get_timeleft,
++	.restart = rwdt_restart,
+ };
+ 
+ #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
+@@ -220,6 +231,7 @@ static int rwdt_probe(struct platform_device *pdev)
+ 	platform_set_drvdata(pdev, priv);
+ 	watchdog_set_drvdata(&priv->wdev, priv);
+ 	watchdog_set_nowayout(&priv->wdev, nowayout);
++	watchdog_set_restart_priority(&priv->wdev, 0);
+ 
+ 	/* This overrides the default timeout only if DT configuration was found */
+ 	ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0893-watchdog-renesas-wdt-Add-support-for-WDIOF_CARDRESET.patch b/patches/0893-watchdog-renesas-wdt-Add-support-for-WDIOF_CARDRESET.patch
new file mode 100644
index 00000000000000..81886a02cd8f1a
--- /dev/null
+++ b/patches/0893-watchdog-renesas-wdt-Add-support-for-WDIOF_CARDRESET.patch
@@ -0,0 +1,59 @@
+From e051f1d1ea050ec3831cb31b3579b832e9a51560 Mon Sep 17 00:00:00 2001
+From: Veeraiyan Chidambaram <veeraiyan.chidambaram@in.bosch.com>
+Date: Fri, 13 Apr 2018 16:19:24 +0200
+Subject: [PATCH 0893/1795] watchdog: renesas-wdt: Add support for
+ WDIOF_CARDRESET
+
+This patch adds the WDIOF_CARDRESET support for the Renesas platform
+watchdog, to know if the board reboot is due to a watchdog reset.
+
+This is done via the WOVF bit (bit 4) of the RWTCSRA register, which
+indicates if RWTCNT overflowed, triggering the reset in last boot.
+
+Signed-off-by: Veeraiyan Chidambaram <veeraiyan.chidambaram@in.bosch.com>
+[takeshi.kihara.df: changed to read the RWTCSRA register while clock is
+ enabled]
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+
+(cherry picked from commit fdac6a90d2d151abdbb7e5ec14bb9ab64e2931ec)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/watchdog/renesas_wdt.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
+index 6b8c6ddfe30b..514db5cc1595 100644
+--- a/drivers/watchdog/renesas_wdt.c
++++ b/drivers/watchdog/renesas_wdt.c
+@@ -121,7 +121,8 @@ static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
+ }
+ 
+ static const struct watchdog_info rwdt_ident = {
+-	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
++	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
++		WDIOF_CARDRESET,
+ 	.identity = "Renesas WDT Watchdog",
+ };
+ 
+@@ -197,9 +198,10 @@ static int rwdt_probe(struct platform_device *pdev)
+ 		return PTR_ERR(clk);
+ 
+ 	pm_runtime_enable(&pdev->dev);
+-
+ 	pm_runtime_get_sync(&pdev->dev);
+ 	priv->clk_rate = clk_get_rate(clk);
++	priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
++				RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
+ 	pm_runtime_put(&pdev->dev);
+ 
+ 	if (!priv->clk_rate) {
+-- 
+2.19.0
+
diff --git a/patches/0894-usb-add-a-flag-to-skip-PHY-initialization-to-struct-.patch b/patches/0894-usb-add-a-flag-to-skip-PHY-initialization-to-struct-.patch
new file mode 100644
index 00000000000000..c5d188cd221cf2
--- /dev/null
+++ b/patches/0894-usb-add-a-flag-to-skip-PHY-initialization-to-struct-.patch
@@ -0,0 +1,185 @@
+From 5caf43318aa2f14f82d496ca2debff200fead56a Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 3 Mar 2018 22:43:03 +0100
+Subject: [PATCH 0894/1795] usb: add a flag to skip PHY initialization to
+ struct usb_hcd
+
+The USB HCD core driver parses the device-tree node for "phys" and
+"usb-phys" properties. It also manages the power state of these PHYs
+automatically.
+However, drivers may opt-out of this behavior by setting "phy" or
+"usb_phy" in struct usb_hcd to a non-null value. An example where this
+is required is the "Qualcomm USB2 controller", implemented by the
+chipidea driver. The hardware requires that the PHY is only powered on
+after the "reset completed" event from the controller is received.
+
+A follow-up patch will allow the USB HCD core driver to manage more than
+one PHY. Add a new "skip_phy_initialization" bitflag to struct usb_hcd
+so drivers can opt-out of any PHY management provided by the USB HCD
+core driver.
+
+This also updates the existing drivers so they use the new flag if they
+want to opt out of the PHY management provided by the USB HCD core
+driver. This means that for these drivers the new "multiple PHY"
+handling (which will be added in a follow-up patch) will be disabled as
+well.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Acked-by: Peter Chen <peter.chen@nxp.com>
+Tested-by: Neil Armstrong <narmstrong@baylibre.con>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 4e88d4c083016454f179686529ae65d70b933b58)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/chipidea/host.c      | 6 ++----
+ drivers/usb/core/hcd.c           | 4 ++--
+ drivers/usb/host/ehci-fsl.c      | 2 ++
+ drivers/usb/host/ehci-platform.c | 4 ++--
+ drivers/usb/host/ehci-tegra.c    | 1 +
+ drivers/usb/host/ohci-omap.c     | 1 +
+ drivers/usb/host/ohci-platform.c | 4 ++--
+ drivers/usb/host/xhci-plat.c     | 1 +
+ include/linux/usb/hcd.h          | 6 ++++++
+ 9 files changed, 19 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
+index a49e8567ac7d..9e26951f696c 100644
+--- a/drivers/usb/chipidea/host.c
++++ b/drivers/usb/chipidea/host.c
+@@ -137,10 +137,8 @@ static int host_start(struct ci_hdrc *ci)
+ 
+ 	hcd->power_budget = ci->platdata->power_budget;
+ 	hcd->tpl_support = ci->platdata->tpl_support;
+-	if (ci->phy)
+-		hcd->phy = ci->phy;
+-	else
+-		hcd->usb_phy = ci->usb_phy;
++	if (ci->phy || ci->usb_phy)
++		hcd->skip_phy_initialization = 1;
+ 
+ 	ehci = hcd_to_ehci(hcd);
+ 	ehci->caps = ci->hw_bank.cap;
+diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
+index 9fa30a6ada6e..d92c366d58b3 100644
+--- a/drivers/usb/core/hcd.c
++++ b/drivers/usb/core/hcd.c
+@@ -2742,7 +2742,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
+ 	int retval;
+ 	struct usb_device *rhdev;
+ 
+-	if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->usb_phy) {
++	if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->skip_phy_initialization) {
+ 		struct usb_phy *phy = usb_get_phy_dev(hcd->self.sysdev, 0);
+ 
+ 		if (IS_ERR(phy)) {
+@@ -2760,7 +2760,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
+ 		}
+ 	}
+ 
+-	if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->phy) {
++	if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->skip_phy_initialization) {
+ 		struct phy *phy = phy_get(hcd->self.sysdev, "usb");
+ 
+ 		if (IS_ERR(phy)) {
+diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
+index 7c4bb32230d2..0831917321fe 100644
+--- a/drivers/usb/host/ehci-fsl.c
++++ b/drivers/usb/host/ehci-fsl.c
+@@ -169,6 +169,8 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
+ 			retval = -ENODEV;
+ 			goto err2;
+ 		}
++
++		hcd->skip_phy_initialization = 1;
+ 	}
+ #endif
+ 	return retval;
+diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
+index cb77af3a71c1..86d535fe5b44 100644
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -222,9 +222,9 @@ static int ehci_platform_probe(struct platform_device *dev)
+ 			if (IS_ERR(priv->phys[phy_num])) {
+ 				err = PTR_ERR(priv->phys[phy_num]);
+ 					goto err_put_hcd;
+-			} else if (!hcd->phy) {
++			} else {
+ 				/* Avoiding phy_get() in usb_add_hcd() */
+-				hcd->phy = priv->phys[phy_num];
++				hcd->skip_phy_initialization = 1;
+ 			}
+ 		}
+ 
+diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
+index fe8423e17877..ae5439f96530 100644
+--- a/drivers/usb/host/ehci-tegra.c
++++ b/drivers/usb/host/ehci-tegra.c
+@@ -472,6 +472,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
+ 		goto cleanup_clk_en;
+ 	}
+ 	hcd->usb_phy = u_phy;
++	hcd->skip_phy_initialization = 1;
+ 
+ 	tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
+ 		"nvidia,needs-double-reset");
+diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
+index 0201c49bc4fc..d8d35d456456 100644
+--- a/drivers/usb/host/ohci-omap.c
++++ b/drivers/usb/host/ohci-omap.c
+@@ -230,6 +230,7 @@ static int ohci_omap_reset(struct usb_hcd *hcd)
+ 		} else {
+ 			return -EPROBE_DEFER;
+ 		}
++		hcd->skip_phy_initialization = 1;
+ 		ohci->start_hnp = start_hnp;
+ 	}
+ #endif
+diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
+index 908ebcfbc350..488b811b565f 100644
+--- a/drivers/usb/host/ohci-platform.c
++++ b/drivers/usb/host/ohci-platform.c
+@@ -189,9 +189,9 @@ static int ohci_platform_probe(struct platform_device *dev)
+ 			if (IS_ERR(priv->phys[phy_num])) {
+ 				err = PTR_ERR(priv->phys[phy_num]);
+ 				goto err_put_hcd;
+-			} else if (!hcd->phy) {
++			} else {
+ 				/* Avoiding phy_get() in usb_add_hcd() */
+-				hcd->phy = priv->phys[phy_num];
++				hcd->skip_phy_initialization = 1;
+ 			}
+ 		}
+ 
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index c435df29cdb8..ea089fdda611 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -284,6 +284,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 		ret = usb_phy_init(hcd->usb_phy);
+ 		if (ret)
+ 			goto put_usb3_hcd;
++		hcd->skip_phy_initialization = 1;
+ 	}
+ 
+ 	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
+diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
+index 176900528822..693502c84c04 100644
+--- a/include/linux/usb/hcd.h
++++ b/include/linux/usb/hcd.h
+@@ -151,6 +151,12 @@ struct usb_hcd {
+ 	unsigned		msix_enabled:1;	/* driver has MSI-X enabled? */
+ 	unsigned		msi_enabled:1;	/* driver has MSI enabled? */
+ 	unsigned		remove_phy:1;	/* auto-remove USB phy */
++	/*
++	 * do not manage the PHY state in the HCD core, instead let the driver
++	 * handle this (for example if the PHY can only be turned on after a
++	 * specific event)
++	 */
++	unsigned		skip_phy_initialization:1;
+ 
+ 	/* The next flag is a stopgap, to be removed when all the HCDs
+ 	 * support the new root-hub polling mechanism. */
+-- 
+2.19.0
+
diff --git a/patches/0895-usb-xhci-Remove-ep_trb-from-xhci_cleanup_halted_endp.patch b/patches/0895-usb-xhci-Remove-ep_trb-from-xhci_cleanup_halted_endp.patch
new file mode 100644
index 00000000000000..cdc8975148b364
--- /dev/null
+++ b/patches/0895-usb-xhci-Remove-ep_trb-from-xhci_cleanup_halted_endp.patch
@@ -0,0 +1,65 @@
+From a267b520cbcab072122b2c62f2a35f7a17d20c5e Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 16 Mar 2018 16:32:59 +0200
+Subject: [PATCH 0895/1795] usb: xhci: Remove ep_trb from
+ xhci_cleanup_halted_endpoint()
+
+Function argument ep_trb for xhci_cleanup_halted_endpoint() isn't
+needed anymore. Cleanup it.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5fee5a5afa9ff1e4a242a492d5ce181974fbd969)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 11 ++++-------
+ 1 file changed, 4 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index daa94c3aed80..642a07022e7a 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1815,8 +1815,7 @@ struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
+ 
+ static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
+ 		unsigned int slot_id, unsigned int ep_index,
+-		unsigned int stream_id,
+-		struct xhci_td *td, union xhci_trb *ep_trb,
++		unsigned int stream_id, struct xhci_td *td,
+ 		enum xhci_ep_reset_type reset_type)
+ {
+ 	struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
+@@ -1957,8 +1956,7 @@ static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 		 * The class driver clears the device side halt later.
+ 		 */
+ 		xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
+-					ep_ring->stream_id, td, ep_trb,
+-					EP_HARD_RESET);
++					ep_ring->stream_id, td, EP_HARD_RESET);
+ 	} else {
+ 		/* Update ring dequeue pointer */
+ 		while (ep_ring->dequeue != td->last_trb)
+@@ -2318,7 +2316,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
+ 		case COMP_INVALID_STREAM_TYPE_ERROR:
+ 		case COMP_INVALID_STREAM_ID_ERROR:
+ 			xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
+-						     NULL, NULL, EP_SOFT_RESET);
++						     NULL, EP_SOFT_RESET);
+ 			goto cleanup;
+ 		case COMP_RING_UNDERRUN:
+ 		case COMP_RING_OVERRUN:
+@@ -2584,8 +2582,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
+ 				xhci_cleanup_halted_endpoint(xhci, slot_id,
+ 							     ep_index,
+ 							     ep_ring->stream_id,
+-							     td, ep_trb,
+-							     EP_HARD_RESET);
++							     td, EP_HARD_RESET);
+ 			goto cleanup;
+ 		}
+ 
+-- 
+2.19.0
+
diff --git a/patches/0896-usb-xhci-Remove-ep_trb-from-finish_td.patch b/patches/0896-usb-xhci-Remove-ep_trb-from-finish_td.patch
new file mode 100644
index 00000000000000..4da4e6d20d546b
--- /dev/null
+++ b/patches/0896-usb-xhci-Remove-ep_trb-from-finish_td.patch
@@ -0,0 +1,61 @@
+From 4933e6e31d74f66dee89b39fb73a07bb528c7157 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Fri, 16 Mar 2018 16:33:00 +0200
+Subject: [PATCH 0896/1795] usb: xhci: Remove ep_trb from finish_td()
+
+Function argument ep_trb for finish_td() isn't needed anymore.
+Cleanup it.
+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 0c341910cb3d2376cd438b074634b173af8a2a52)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 642a07022e7a..88071c4444c6 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1921,7 +1921,7 @@ static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
+ }
+ 
+ static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
+-	union xhci_trb *ep_trb, struct xhci_transfer_event *event,
++	struct xhci_transfer_event *event,
+ 	struct xhci_virt_ep *ep, int *status)
+ {
+ 	struct xhci_virt_device *xdev;
+@@ -2081,7 +2081,7 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 		td->urb->actual_length = requested;
+ 
+ finish_td:
+-	return finish_td(xhci, td, ep_trb, event, ep, status);
++	return finish_td(xhci, td, event, ep, status);
+ }
+ 
+ /*
+@@ -2168,7 +2168,7 @@ static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 
+ 	td->urb->actual_length += frame->actual_length;
+ 
+-	return finish_td(xhci, td, ep_trb, event, ep, status);
++	return finish_td(xhci, td, event, ep, status);
+ }
+ 
+ static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
+@@ -2258,7 +2258,7 @@ static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
+ 			  remaining);
+ 		td->urb->actual_length = 0;
+ 	}
+-	return finish_td(xhci, td, ep_trb, event, ep, status);
++	return finish_td(xhci, td, event, ep, status);
+ }
+ 
+ /*
+-- 
+2.19.0
+
diff --git a/patches/0897-xhci-Don-t-always-run-the-default-stop-endpoint-comm.patch b/patches/0897-xhci-Don-t-always-run-the-default-stop-endpoint-comm.patch
new file mode 100644
index 00000000000000..09bc7c56a27401
--- /dev/null
+++ b/patches/0897-xhci-Don-t-always-run-the-default-stop-endpoint-comm.patch
@@ -0,0 +1,40 @@
+From 6979ba73713e701e572acd5f918010fa8c57bd4a Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 16 Mar 2018 16:33:02 +0200
+Subject: [PATCH 0897/1795] xhci: Don't always run the default stop endpoint
+ command completion handler
+
+The default stop endpoint completion handler will give back cancelled
+URBs, and clean, or move past those canceller TRBs on the ring.
+
+This is not always the preferred action.
+
+If the stop endpoint command issuer is waiting for a completion
+skip the default handler and just call the completion.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit a38fe33889095c5d7b1eb094d977fc3f2bab7ebd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 88071c4444c6..86476c6a8abc 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1436,7 +1436,8 @@ static void handle_cmd_completion(struct xhci_hcd *xhci,
+ 	case TRB_STOP_RING:
+ 		WARN_ON(slot_id != TRB_TO_SLOT_ID(
+ 				le32_to_cpu(cmd_trb->generic.field[3])));
+-		xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
++		if (!cmd->completion)
++			xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
+ 		break;
+ 	case TRB_SET_DEQ:
+ 		WARN_ON(slot_id != TRB_TO_SLOT_ID(
+-- 
+2.19.0
+
diff --git a/patches/0898-xhci-refactor-xhci_urb_enqueue-a-bit-with-minor-chan.patch b/patches/0898-xhci-refactor-xhci_urb_enqueue-a-bit-with-minor-chan.patch
new file mode 100644
index 00000000000000..98e62d49a1a926
--- /dev/null
+++ b/patches/0898-xhci-refactor-xhci_urb_enqueue-a-bit-with-minor-chan.patch
@@ -0,0 +1,86 @@
+From f10da191e1b0620a485da492814e3c43572155c9 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 16 Mar 2018 16:33:03 +0200
+Subject: [PATCH 0898/1795] xhci: refactor xhci_urb_enqueue a bit with minor
+ changes
+
+make the local ep_state variable a pointer to the actual ring ep_state.
+This allows us to read fresh ep_state values every time, will be useful
+later.
+
+Also move the streams check out from bulk only case. Even if only
+bulk tranfers can use streams we shouldn't continue if those flags
+are set. Main reason for this change is really code readability and
+grouping functionality
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 15febf5eede9ff9d3180d257441e9a2fbb3f0ae6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 20 +++++++++-----------
+ 1 file changed, 9 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index b365d37aacbf..c233ffc72b53 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -1329,7 +1329,8 @@ static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ 	unsigned long flags;
+ 	int ret = 0;
+-	unsigned int slot_id, ep_index, ep_state;
++	unsigned int slot_id, ep_index;
++	unsigned int *ep_state;
+ 	struct urb_priv	*urb_priv;
+ 	int num_tds;
+ 
+@@ -1339,6 +1340,7 @@ static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 
+ 	slot_id = urb->dev->slot_id;
+ 	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
++	ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
+ 
+ 	if (!HCD_HW_ACCESSIBLE(hcd)) {
+ 		if (!in_interrupt())
+@@ -1390,6 +1392,12 @@ static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 		ret = -ESHUTDOWN;
+ 		goto free_priv;
+ 	}
++	if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
++		xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
++			  *ep_state);
++		ret = -EINVAL;
++		goto free_priv;
++	}
+ 
+ 	switch (usb_endpoint_type(&urb->ep->desc)) {
+ 
+@@ -1398,23 +1406,13 @@ static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 					 slot_id, ep_index);
+ 		break;
+ 	case USB_ENDPOINT_XFER_BULK:
+-		ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
+-		if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
+-			xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
+-				  ep_state);
+-			ret = -EINVAL;
+-			break;
+-		}
+ 		ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
+ 					 slot_id, ep_index);
+ 		break;
+-
+-
+ 	case USB_ENDPOINT_XFER_INT:
+ 		ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
+ 				slot_id, ep_index);
+ 		break;
+-
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 		ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
+ 				slot_id, ep_index);
+-- 
+2.19.0
+
diff --git a/patches/0899-xhci-Clear-the-host-side-toggle-manually-when-endpoi.patch b/patches/0899-xhci-Clear-the-host-side-toggle-manually-when-endpoi.patch
new file mode 100644
index 00000000000000..4a461cc748b895
--- /dev/null
+++ b/patches/0899-xhci-Clear-the-host-side-toggle-manually-when-endpoi.patch
@@ -0,0 +1,198 @@
+From a386b6706d86cfd40bede3c6eb5098051c069f6a Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 16 Mar 2018 16:33:04 +0200
+Subject: [PATCH 0899/1795] xhci: Clear the host side toggle manually when
+ endpoint is soft reset
+
+Some devices use a clear endpoint halt request as a soft reset, even if
+the endpoint is not halted. This will clear the toggle and sequence on the
+device side.
+
+xHCI however refuses to reset a non-halted endpoint, so instead
+we need to issue a configure endpoint command on xHCI to clear its host
+side toggle and sequence, and get it in sync with the device side.
+
+This is a respin of a old patch that was reverted as it had a stale
+endpoint context dequeue value which caused regression.
+commit 27082e2654dc ("xhci: Clear the host side toggle manually when
+endpoint is 'soft reset'")
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit f5249461b504d35aa1a40140983b7ec415807d9e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c |   5 +-
+ drivers/usb/host/xhci.c      | 105 ++++++++++++++++++++++++++++++-----
+ drivers/usb/host/xhci.h      |   2 +
+ 3 files changed, 95 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 86476c6a8abc..91a1a824673d 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1829,9 +1829,10 @@ static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
+ 
+ 	xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
+ 
+-	if (reset_type == EP_HARD_RESET)
++	if (reset_type == EP_HARD_RESET) {
++		ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
+ 		xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
+-
++	}
+ 	xhci_ring_cmd_db(xhci);
+ }
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index c233ffc72b53..5466d4db6ffe 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -1398,6 +1398,11 @@ static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag
+ 		ret = -EINVAL;
+ 		goto free_priv;
+ 	}
++	if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
++		xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
++		ret = -EINVAL;
++		goto free_priv;
++	}
+ 
+ 	switch (usb_endpoint_type(&urb->ep->desc)) {
+ 
+@@ -2911,33 +2916,103 @@ void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
+ 	}
+ }
+ 
+-/* Called when clearing halted device. The core should have sent the control
+- * message to clear the device halt condition. The host side of the halt should
+- * already be cleared with a reset endpoint command issued when the STALL tx
+- * event was received.
++/*
++ * Called after usb core issues a clear halt control message.
++ * The host side of the halt should already be cleared by a reset endpoint
++ * command issued when the STALL event was received.
+  *
+- * Context: in_interrupt
++ * The reset endpoint command may only be issued to endpoints in the halted
++ * state. For software that wishes to reset the data toggle or sequence number
++ * of an endpoint that isn't in the halted state this function will issue a
++ * configure endpoint command with the Drop and Add bits set for the target
++ * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
+  */
+ 
+ static void xhci_endpoint_reset(struct usb_hcd *hcd,
+-		struct usb_host_endpoint *ep)
++		struct usb_host_endpoint *host_ep)
+ {
+ 	struct xhci_hcd *xhci;
++	struct usb_device *udev;
++	struct xhci_virt_device *vdev;
++	struct xhci_virt_ep *ep;
++	struct xhci_input_control_ctx *ctrl_ctx;
++	struct xhci_command *stop_cmd, *cfg_cmd;
++	unsigned int ep_index;
++	unsigned long flags;
++	u32 ep_flag;
+ 
+ 	xhci = hcd_to_xhci(hcd);
++	if (!host_ep->hcpriv)
++		return;
++	udev = (struct usb_device *) host_ep->hcpriv;
++	vdev = xhci->devs[udev->slot_id];
++	ep_index = xhci_get_endpoint_index(&host_ep->desc);
++	ep = &vdev->eps[ep_index];
++
++	/* Bail out if toggle is already being cleared by a endpoint reset */
++	if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
++		ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
++		return;
++	}
++	/* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
++	if (usb_endpoint_xfer_control(&host_ep->desc) ||
++	    usb_endpoint_xfer_isoc(&host_ep->desc))
++		return;
++
++	ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
++
++	if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
++		return;
++
++	stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
++	if (!stop_cmd)
++		return;
++
++	cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
++	if (!cfg_cmd)
++		goto cleanup;
++
++	spin_lock_irqsave(&xhci->lock, flags);
++
++	/* block queuing new trbs and ringing ep doorbell */
++	ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
+ 
+ 	/*
+-	 * We might need to implement the config ep cmd in xhci 4.8.1 note:
+-	 * The Reset Endpoint Command may only be issued to endpoints in the
+-	 * Halted state. If software wishes reset the Data Toggle or Sequence
+-	 * Number of an endpoint that isn't in the Halted state, then software
+-	 * may issue a Configure Endpoint Command with the Drop and Add bits set
+-	 * for the target endpoint. that is in the Stopped state.
++	 * Make sure endpoint ring is empty before resetting the toggle/seq.
++	 * Driver is required to synchronously cancel all transfer request.
++	 * Stop the endpoint to force xHC to update the output context
+ 	 */
+ 
+-	/* For now just print debug to follow the situation */
+-	xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
+-		 ep->desc.bEndpointAddress);
++	if (!list_empty(&ep->ring->td_list)) {
++		dev_err(&udev->dev, "EP not empty, refuse reset\n");
++		spin_unlock_irqrestore(&xhci->lock, flags);
++		goto cleanup;
++	}
++	xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
++	xhci_ring_cmd_db(xhci);
++	spin_unlock_irqrestore(&xhci->lock, flags);
++
++	wait_for_completion(stop_cmd->completion);
++
++	spin_lock_irqsave(&xhci->lock, flags);
++
++	/* config ep command clears toggle if add and drop ep flags are set */
++	ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
++	xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
++					   ctrl_ctx, ep_flag, ep_flag);
++	xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
++
++	xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
++				      udev->slot_id, false);
++	xhci_ring_cmd_db(xhci);
++	spin_unlock_irqrestore(&xhci->lock, flags);
++
++	wait_for_completion(cfg_cmd->completion);
++
++	ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
++	xhci_free_command(xhci, cfg_cmd);
++cleanup:
++	xhci_free_command(xhci, stop_cmd);
+ }
+ 
+ static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 2961d1020981..c09563702d2f 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -926,6 +926,8 @@ struct xhci_virt_ep {
+ #define EP_HAS_STREAMS		(1 << 4)
+ /* Transitioning the endpoint to not using streams, don't enqueue URBs */
+ #define EP_GETTING_NO_STREAMS	(1 << 5)
++#define EP_HARD_CLEAR_TOGGLE	(1 << 6)
++#define EP_SOFT_CLEAR_TOGGLE	(1 << 7)
+ 	/* ----  Related to URB cancellation ---- */
+ 	struct list_head	cancelled_td_list;
+ 	/* Watchdog timer for stop endpoint command to cancel URBs */
+-- 
+2.19.0
+
diff --git a/patches/0900-xhci-Add-Intel-extended-cap-otg-phy-mux-handling.patch b/patches/0900-xhci-Add-Intel-extended-cap-otg-phy-mux-handling.patch
new file mode 100644
index 00000000000000..051cfbf5db4f0f
--- /dev/null
+++ b/patches/0900-xhci-Add-Intel-extended-cap-otg-phy-mux-handling.patch
@@ -0,0 +1,206 @@
+From 6ef1215b04d0c26cec47cb208f8b14c33da790cd Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Tue, 20 Mar 2018 15:57:09 +0300
+Subject: [PATCH 0900/1795] xhci: Add Intel extended cap / otg phy mux handling
+
+The xHCI controller on various Intel SoCs has an extended cap mmio-range
+which contains registers to control the muxing to the xHCI (host mode)
+or the dwc3 (device mode) and vbus-detection for the otg usb-phy.
+
+Having a role-sw driver included in the xHCI code (under drivers/usb/host)
+is not desirable. So this commit adds a simple handler for this extended
+capability, which creates a platform device with the caps mmio region as
+resource, this allows us to write a separate platform role-sw driver for
+the role-switch.
+
+Note this commit adds a call to the new xhci_ext_cap_init() function
+to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must
+be called only once. If in the future we also want to handle ext-caps
+on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also
+be added to other bus probe paths.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fa31b3cb2ae143aa6e26974fcbe75689da60bdbe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/Makefile        |  2 +-
+ drivers/usb/host/xhci-ext-caps.c | 90 ++++++++++++++++++++++++++++++++
+ drivers/usb/host/xhci-ext-caps.h |  2 +
+ drivers/usb/host/xhci-pci.c      |  5 ++
+ drivers/usb/host/xhci.h          |  2 +
+ 5 files changed, 100 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/usb/host/xhci-ext-caps.c
+
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index e77fe32e7b35..b5a32e5e2e66 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -11,7 +11,7 @@ fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o
+ 
+ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
+ 
+-xhci-hcd-y := xhci.o xhci-mem.o
++xhci-hcd-y := xhci.o xhci-mem.o xhci-ext-caps.o
+ xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
+ xhci-hcd-y += xhci-trace.o
+ 
+diff --git a/drivers/usb/host/xhci-ext-caps.c b/drivers/usb/host/xhci-ext-caps.c
+new file mode 100644
+index 000000000000..399113f9fc5c
+--- /dev/null
++++ b/drivers/usb/host/xhci-ext-caps.c
+@@ -0,0 +1,90 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * XHCI extended capability handling
++ *
++ * Copyright (c) 2017 Hans de Goede <hdegoede@redhat.com>
++ */
++
++#include <linux/platform_device.h>
++#include "xhci.h"
++
++#define USB_SW_DRV_NAME		"intel_xhci_usb_sw"
++#define USB_SW_RESOURCE_SIZE	0x400
++
++static void xhci_intel_unregister_pdev(void *arg)
++{
++	platform_device_unregister(arg);
++}
++
++static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset)
++{
++	struct usb_hcd *hcd = xhci_to_hcd(xhci);
++	struct device *dev = hcd->self.controller;
++	struct platform_device *pdev;
++	struct resource	res = { 0, };
++	int ret;
++
++	pdev = platform_device_alloc(USB_SW_DRV_NAME, PLATFORM_DEVID_NONE);
++	if (!pdev) {
++		xhci_err(xhci, "couldn't allocate %s platform device\n",
++			 USB_SW_DRV_NAME);
++		return -ENOMEM;
++	}
++
++	res.start = hcd->rsrc_start + cap_offset;
++	res.end	  = res.start + USB_SW_RESOURCE_SIZE - 1;
++	res.name  = USB_SW_DRV_NAME;
++	res.flags = IORESOURCE_MEM;
++
++	ret = platform_device_add_resources(pdev, &res, 1);
++	if (ret) {
++		dev_err(dev, "couldn't add resources to intel_xhci_usb_sw pdev\n");
++		platform_device_put(pdev);
++		return ret;
++	}
++
++	pdev->dev.parent = dev;
++
++	ret = platform_device_add(pdev);
++	if (ret) {
++		dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n");
++		platform_device_put(pdev);
++		return ret;
++	}
++
++	ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev);
++	if (ret) {
++		dev_err(dev, "couldn't add unregister action for intel_xhci_usb_sw pdev\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++int xhci_ext_cap_init(struct xhci_hcd *xhci)
++{
++	void __iomem *base = &xhci->cap_regs->hc_capbase;
++	u32 offset, val;
++	int ret;
++
++	offset = xhci_find_next_ext_cap(base, 0, 0);
++
++	while (offset) {
++		val = readl(base + offset);
++
++		switch (XHCI_EXT_CAPS_ID(val)) {
++		case XHCI_EXT_CAPS_VENDOR_INTEL:
++			if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) {
++				ret = xhci_create_intel_xhci_sw_pdev(xhci,
++								     offset);
++				if (ret)
++					return ret;
++			}
++			break;
++		}
++		offset = xhci_find_next_ext_cap(base, offset, 0);
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(xhci_ext_cap_init);
+diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
+index bf7316e130d3..3147f3b467af 100644
+--- a/drivers/usb/host/xhci-ext-caps.h
++++ b/drivers/usb/host/xhci-ext-caps.h
+@@ -39,6 +39,8 @@
+ #define XHCI_EXT_CAPS_ROUTE	5
+ /* IDs 6-9 reserved */
+ #define XHCI_EXT_CAPS_DEBUG	10
++/* Vendor caps */
++#define XHCI_EXT_CAPS_VENDOR_INTEL	192
+ /* USB Legacy Support Capability - section 7.1.1 */
+ #define XHCI_HC_BIOS_OWNED	(1 << 16)
+ #define XHCI_HC_OS_OWNED	(1 << 24)
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index 93ce34bce7b5..85ffda85f8ab 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -181,6 +181,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
+ 	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
+ 		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
+ 		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
++		xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
+ 	}
+ 	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
+ 	    (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
+@@ -314,6 +315,10 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+ 		goto dealloc_usb2_hcd;
+ 	}
+ 
++	retval = xhci_ext_cap_init(xhci);
++	if (retval)
++		goto put_usb3_hcd;
++
+ 	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
+ 			IRQF_SHARED);
+ 	if (retval)
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index c09563702d2f..3c3106b11559 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1833,6 +1833,7 @@ struct xhci_hcd {
+ #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL	(1 << 28)
+ #define XHCI_HW_LPM_DISABLE	(1 << 29)
+ #define XHCI_SUSPEND_DELAY	(1 << 30)
++#define XHCI_INTEL_USB_ROLE_SW	(1 << 31)
+ 
+ 	unsigned int		num_active_eps;
+ 	unsigned int		limit_active_eps;
+@@ -2028,6 +2029,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
+ void xhci_init_driver(struct hc_driver *drv,
+ 		      const struct xhci_driver_overrides *over);
+ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
++int xhci_ext_cap_init(struct xhci_hcd *xhci);
+ 
+ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
+ int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
+-- 
+2.19.0
+
diff --git a/patches/0901-usb-host-xhci-plat-Remove-useless-test-before-clk_di.patch b/patches/0901-usb-host-xhci-plat-Remove-useless-test-before-clk_di.patch
new file mode 100644
index 00000000000000..15dfe2628b41d3
--- /dev/null
+++ b/patches/0901-usb-host-xhci-plat-Remove-useless-test-before-clk_di.patch
@@ -0,0 +1,46 @@
+From 833b4136057f2df8e88868fa22bc6871af892cbd Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@bootlin.com>
+Date: Fri, 20 Apr 2018 16:52:51 +0300
+Subject: [PATCH 0901/1795] usb: host: xhci-plat: Remove useless test before
+ clk_disable_unprepare
+
+clk_disable_unprepare() already checks that the clock pointer is valid.
+No need to test it before calling it.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 2d79609bf21eedb2142f9dff7d4af9919cd7399a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-plat.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index ea089fdda611..373caf024631 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -320,8 +320,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	usb_put_hcd(xhci->shared_hcd);
+ 
+ disable_clk:
+-	if (!IS_ERR(clk))
+-		clk_disable_unprepare(clk);
++	clk_disable_unprepare(clk);
+ 
+ put_hcd:
+ 	usb_put_hcd(hcd);
+@@ -347,8 +346,7 @@ static int xhci_plat_remove(struct platform_device *dev)
+ 	usb_remove_hcd(hcd);
+ 	usb_put_hcd(xhci->shared_hcd);
+ 
+-	if (!IS_ERR(clk))
+-		clk_disable_unprepare(clk);
++	clk_disable_unprepare(clk);
+ 	usb_put_hcd(hcd);
+ 
+ 	pm_runtime_set_suspended(&dev->dev);
+-- 
+2.19.0
+
diff --git a/patches/0902-usb-host-xhci-plat-Fix-clock-resource-by-adding-a-re.patch b/patches/0902-usb-host-xhci-plat-Fix-clock-resource-by-adding-a-re.patch
new file mode 100644
index 00000000000000..ebe19614638776
--- /dev/null
+++ b/patches/0902-usb-host-xhci-plat-Fix-clock-resource-by-adding-a-re.patch
@@ -0,0 +1,139 @@
+From 0a615cb850400a8e5b58e68e5d53312936d59065 Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@bootlin.com>
+Date: Fri, 20 Apr 2018 16:52:52 +0300
+Subject: [PATCH 0902/1795] usb: host: xhci-plat: Fix clock resource by adding
+ a register clock
+
+On Armada 7K/8K we need to explicitly enable the register clock. This
+clock is optional because not all the SoCs using this IP need it but at
+least for Armada 7K/8K it is actually mandatory.
+
+The change was done at xhci-plat level and not at a xhci-mvebu.c because,
+it is expected that other SoC would have this kind of constraint.
+
+The binding documentation is updating accordingly.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 3ae2da7b28b393d4f6faef3d384cc725ef39716b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/usb/usb-xhci.txt      |  5 +++-
+ drivers/usb/host/xhci-plat.c                  | 25 ++++++++++++++++---
+ drivers/usb/host/xhci.h                       |  3 ++-
+ 3 files changed, 27 insertions(+), 6 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+index 1651483a7048..24c1b8e6a0ef 100644
+--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+@@ -28,7 +28,10 @@ Required properties:
+   - interrupts: one XHCI interrupt should be described here.
+ 
+ Optional properties:
+-  - clocks: reference to a clock
++  - clocks: reference to the clocks
++  - clock-names: mandatory if there is a second clock, in this case
++    the name must be "core" for the first clock and "reg" for the
++    second one
+   - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
+   - usb3-lpm-capable: determines if platform is USB3 LPM capable
+   - quirk-broken-port-ped: set if the controller has broken port disable mechanism
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 373caf024631..c1b22fc64e38 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -157,6 +157,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	struct resource         *res;
+ 	struct usb_hcd		*hcd;
+ 	struct clk              *clk;
++	struct clk              *reg_clk;
+ 	int			ret;
+ 	int			irq;
+ 
+@@ -226,17 +227,27 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	hcd->rsrc_len = resource_size(res);
+ 
+ 	/*
+-	 * Not all platforms have a clk so it is not an error if the
+-	 * clock does not exists.
++	 * Not all platforms have clks so it is not an error if the
++	 * clock do not exist.
+ 	 */
++	reg_clk = devm_clk_get(&pdev->dev, "reg");
++	if (!IS_ERR(reg_clk)) {
++		ret = clk_prepare_enable(reg_clk);
++		if (ret)
++			goto put_hcd;
++	} else if (PTR_ERR(reg_clk) == -EPROBE_DEFER) {
++		ret = -EPROBE_DEFER;
++		goto put_hcd;
++	}
++
+ 	clk = devm_clk_get(&pdev->dev, NULL);
+ 	if (!IS_ERR(clk)) {
+ 		ret = clk_prepare_enable(clk);
+ 		if (ret)
+-			goto put_hcd;
++			goto disable_reg_clk;
+ 	} else if (PTR_ERR(clk) == -EPROBE_DEFER) {
+ 		ret = -EPROBE_DEFER;
+-		goto put_hcd;
++		goto disable_reg_clk;
+ 	}
+ 
+ 	xhci = hcd_to_xhci(hcd);
+@@ -252,6 +263,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 	device_wakeup_enable(hcd->self.controller);
+ 
+ 	xhci->clk = clk;
++	xhci->reg_clk = reg_clk;
+ 	xhci->main_hcd = hcd;
+ 	xhci->shared_hcd = __usb_create_hcd(driver, sysdev, &pdev->dev,
+ 			dev_name(&pdev->dev), hcd);
+@@ -322,6 +334,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ disable_clk:
+ 	clk_disable_unprepare(clk);
+ 
++disable_reg_clk:
++	clk_disable_unprepare(reg_clk);
++
+ put_hcd:
+ 	usb_put_hcd(hcd);
+ 
+@@ -337,6 +352,7 @@ static int xhci_plat_remove(struct platform_device *dev)
+ 	struct usb_hcd	*hcd = platform_get_drvdata(dev);
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+ 	struct clk *clk = xhci->clk;
++	struct clk *reg_clk = xhci->reg_clk;
+ 
+ 	xhci->xhc_state |= XHCI_STATE_REMOVING;
+ 
+@@ -347,6 +363,7 @@ static int xhci_plat_remove(struct platform_device *dev)
+ 	usb_put_hcd(xhci->shared_hcd);
+ 
+ 	clk_disable_unprepare(clk);
++	clk_disable_unprepare(reg_clk);
+ 	usb_put_hcd(hcd);
+ 
+ 	pm_runtime_set_suspended(&dev->dev);
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 3c3106b11559..9751c1373fbb 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1733,8 +1733,9 @@ struct xhci_hcd {
+ 	int		page_shift;
+ 	/* msi-x vectors */
+ 	int		msix_count;
+-	/* optional clock */
++	/* optional clocks */
+ 	struct clk		*clk;
++	struct clk		*reg_clk;
+ 	/* data structures */
+ 	struct xhci_device_context_array *dcbaa;
+ 	struct xhci_ring	*cmd_ring;
+-- 
+2.19.0
+
diff --git a/patches/0903-of-unittest-Remove-redundant-OF_DETACHED-flag-settin.patch b/patches/0903-of-unittest-Remove-redundant-OF_DETACHED-flag-settin.patch
new file mode 100644
index 00000000000000..c0bdf0153cfc88
--- /dev/null
+++ b/patches/0903-of-unittest-Remove-redundant-OF_DETACHED-flag-settin.patch
@@ -0,0 +1,43 @@
+From f3a207d0ce61f6c38a50ae1e3a7e6a499c342518 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <stephen.boyd@linaro.org>
+Date: Fri, 13 Oct 2017 00:44:51 -0700
+Subject: [PATCH 0903/1795] of: unittest: Remove redundant OF_DETACHED flag
+ setting
+
+of_fdt_unflatten_tree() already sets the flag on the node to
+OF_DETACHED, because of_fdt_unflatten_tree() calls
+__unflatten_device_tree() with the detached bool set to true.
+
+Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
+Reviewed-by: Frank Rowand <frowand.list@gmail.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit e0f4145685ec7b477f6166ee819125107388a249)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/unittest.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index 985a85f281a8..4db57549baf8 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -994,7 +994,6 @@ static int __init unittest_data_add(void)
+ 		pr_warn("%s: No tree to attach; not running tests\n", __func__);
+ 		return -ENODATA;
+ 	}
+-	of_node_set_flag(unittest_data_node, OF_DETACHED);
+ 	rc = of_resolve_phandles(unittest_data_node);
+ 	if (rc) {
+ 		pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
+@@ -2144,7 +2143,6 @@ static int __init overlay_data_add(int onum)
+ 		ret = 0;
+ 		goto out_free_data;
+ 	}
+-	of_node_set_flag(info->np_overlay, OF_DETACHED);
+ 
+ 	ret = of_resolve_phandles(info->np_overlay);
+ 	if (ret) {
+-- 
+2.19.0
+
diff --git a/patches/0904-of-overlay-fix-memory-leak-related-to-duplicated-pro.patch b/patches/0904-of-overlay-fix-memory-leak-related-to-duplicated-pro.patch
new file mode 100644
index 00000000000000..dc806d57bd3734
--- /dev/null
+++ b/patches/0904-of-overlay-fix-memory-leak-related-to-duplicated-pro.patch
@@ -0,0 +1,54 @@
+From b00e4189c00853c9d563ba7e71305f5a533cfde7 Mon Sep 17 00:00:00 2001
+From: Lixin Wang <alan.1.wang@nokia-sbell.com>
+Date: Mon, 16 Oct 2017 17:54:32 +0800
+Subject: [PATCH 0904/1795] of: overlay: fix memory leak related to duplicated
+ property
+
+Function of_changeset_add_property or of_changeset_update_property may
+fails. In this case the property just allocated is never deallocated.
+
+Signed-off-by: Lixin Wang <alan.1.wang@nokia-sbell.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit ac0f3e30d87e593dc1460d5f0407662073281d93)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 8ecfee31ab6d..af3b9a16df26 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -162,6 +162,7 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 		bool is_symbols_node)
+ {
+ 	struct property *propn = NULL, *tprop;
++	int ret = 0;
+ 
+ 	/* NOTE: Multiple changes of single properties not supported */
+ 	tprop = of_find_property(target, prop->name, NULL);
+@@ -186,10 +187,16 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 
+ 	/* not found? add */
+ 	if (tprop == NULL)
+-		return of_changeset_add_property(&ov->cset, target, propn);
+-
+-	/* found? update */
+-	return of_changeset_update_property(&ov->cset, target, propn);
++		ret = of_changeset_add_property(&ov->cset, target, propn);
++	else /* found? update */
++		ret = of_changeset_update_property(&ov->cset, target, propn);
++
++	if (ret) {
++		kfree(propn->name);
++		kfree(propn->value);
++		kfree(propn);
++	}
++	return ret;
+ }
+ 
+ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+-- 
+2.19.0
+
diff --git a/patches/0905-of-overlay.c-Remove-comments-that-state-the-obvious-.patch b/patches/0905-of-overlay.c-Remove-comments-that-state-the-obvious-.patch
new file mode 100644
index 00000000000000..700452b331c903
--- /dev/null
+++ b/patches/0905-of-overlay.c-Remove-comments-that-state-the-obvious-.patch
@@ -0,0 +1,252 @@
+From c5a504520ba1526a5469e1b2b10ad8e3ff8575f7 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:21 -0700
+Subject: [PATCH 0905/1795] of: overlay.c: Remove comments that state the
+ obvious, to reduce clutter
+
+Follows recommendations in Documentation/process/coding-style.rst,
+section 8, Commenting.
+
+Some in function comments are promoted to function header comments.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 646afc4ad7f01d582d00e43a4f35b1ebdb70cb4e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 47 +++++++++++++++++---------------------------
+ 1 file changed, 18 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index af3b9a16df26..a42dd7b094c4 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -143,7 +143,6 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov,
+ 	strcpy(new->value, target_path);
+ 	strcpy(new->value + target_path_len, label_path);
+ 
+-	/* mark the property as dynamic */
+ 	of_property_set_flag(new, OF_DYNAMIC);
+ 
+ 	return new;
+@@ -157,6 +156,10 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov,
+ 
+ }
+ 
++/*
++ * Some special properties are not updated (no error returned).
++ * Update of property in symbols node is not allowed.
++ */
+ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 		struct device_node *target, struct property *prop,
+ 		bool is_symbols_node)
+@@ -164,17 +167,14 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 	struct property *propn = NULL, *tprop;
+ 	int ret = 0;
+ 
+-	/* NOTE: Multiple changes of single properties not supported */
+ 	tprop = of_find_property(target, prop->name, NULL);
+ 
+-	/* special properties are not meant to be updated (silent NOP) */
+ 	if (of_prop_cmp(prop->name, "name") == 0 ||
+ 	    of_prop_cmp(prop->name, "phandle") == 0 ||
+ 	    of_prop_cmp(prop->name, "linux,phandle") == 0)
+ 		return 0;
+ 
+ 	if (is_symbols_node) {
+-		/* changing a property in __symbols__ node not allowed */
+ 		if (tprop)
+ 			return -EINVAL;
+ 		propn = dup_and_fixup_symbol_prop(ov, prop);
+@@ -185,10 +185,9 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 	if (propn == NULL)
+ 		return -ENOMEM;
+ 
+-	/* not found? add */
+ 	if (tprop == NULL)
+ 		ret = of_changeset_add_property(&ov->cset, target, propn);
+-	else /* found? update */
++	else
+ 		ret = of_changeset_update_property(&ov->cset, target, propn);
+ 
+ 	if (ret) {
+@@ -210,13 +209,11 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+ 	if (cname == NULL)
+ 		return -ENOMEM;
+ 
+-	/* NOTE: Multiple mods of created nodes not supported */
+ 	for_each_child_of_node(target, tchild)
+ 		if (!of_node_cmp(cname, kbasename(tchild->full_name)))
+ 			break;
+ 
+ 	if (tchild != NULL) {
+-		/* new overlay phandle value conflicts with existing value */
+ 		if (child->phandle)
+ 			return -EINVAL;
+ 
+@@ -224,12 +221,10 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+ 		ret = of_overlay_apply_one(ov, tchild, child, 0);
+ 		of_node_put(tchild);
+ 	} else {
+-		/* create empty tree as a target */
+ 		tchild = __of_node_dup(child, "%pOF/%s", target, cname);
+ 		if (!tchild)
+ 			return -ENOMEM;
+ 
+-		/* point to parent */
+ 		tchild->parent = target;
+ 
+ 		ret = of_changeset_attach_node(&ov->cset, tchild);
+@@ -250,6 +245,8 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+  * Note that the in case of an error the target node is left
+  * in a inconsistent state. Error recovery should be performed
+  * by using the changeset.
++ *
++ * Do not allow symbols node to have any children.
+  */
+ static int of_overlay_apply_one(struct of_overlay *ov,
+ 		struct device_node *target, const struct device_node *overlay,
+@@ -269,7 +266,6 @@ static int of_overlay_apply_one(struct of_overlay *ov,
+ 		}
+ 	}
+ 
+-	/* do not allow symbols node to have any children */
+ 	if (is_symbols_node)
+ 		return 0;
+ 
+@@ -299,7 +295,6 @@ static int of_overlay_apply(struct of_overlay *ov)
+ {
+ 	int i, err;
+ 
+-	/* first we apply the overlays atomically */
+ 	for (i = 0; i < ov->count; i++) {
+ 		struct of_overlay_info *ovinfo = &ov->ovinfo_tab[i];
+ 
+@@ -316,10 +311,10 @@ static int of_overlay_apply(struct of_overlay *ov)
+ 
+ /*
+  * Find the target node using a number of different strategies
+- * in order of preference
++ * in order of preference:
+  *
+- * "target" property containing the phandle of the target
+- * "target-path" property containing the path of the target
++ * 1) "target" property containing the phandle of the target
++ * 2) "target-path" property containing the path of the target
+  */
+ static struct device_node *find_target_node(struct device_node *info_node)
+ {
+@@ -327,12 +322,10 @@ static struct device_node *find_target_node(struct device_node *info_node)
+ 	u32 val;
+ 	int ret;
+ 
+-	/* first try to go by using the target as a phandle */
+ 	ret = of_property_read_u32(info_node, "target", &val);
+ 	if (ret == 0)
+ 		return of_find_node_by_phandle(val);
+ 
+-	/* now try to locate by path */
+ 	ret = of_property_read_string(info_node, "target-path", &path);
+ 	if (ret == 0)
+ 		return of_find_node_by_path(path);
+@@ -397,7 +390,6 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 	struct of_overlay_info *ovinfo;
+ 	int cnt, err;
+ 
+-	/* worst case; every child is a node */
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node)
+ 		cnt++;
+@@ -430,7 +422,6 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 		cnt++;
+ 	}
+ 
+-	/* if nothing filled, return error */
+ 	if (cnt == 0) {
+ 		kfree(ovinfo);
+ 		return -ENODEV;
+@@ -486,7 +477,6 @@ int of_overlay_create(struct device_node *tree)
+ 	struct of_overlay *ov;
+ 	int err, id;
+ 
+-	/* allocate the overlay structure */
+ 	ov = kzalloc(sizeof(*ov), GFP_KERNEL);
+ 	if (ov == NULL)
+ 		return -ENOMEM;
+@@ -505,7 +495,6 @@ int of_overlay_create(struct device_node *tree)
+ 	}
+ 	ov->id = id;
+ 
+-	/* build the overlay info structures */
+ 	err = of_build_overlay_info(ov, tree);
+ 	if (err) {
+ 		pr_err("of_build_overlay_info() failed for tree@%pOF\n",
+@@ -520,18 +509,15 @@ int of_overlay_create(struct device_node *tree)
+ 		goto err_free_idr;
+ 	}
+ 
+-	/* apply the overlay */
+ 	err = of_overlay_apply(ov);
+ 	if (err)
+ 		goto err_abort_trans;
+ 
+-	/* apply the changeset */
+ 	err = __of_changeset_apply(&ov->cset);
+ 	if (err)
+ 		goto err_revert_overlay;
+ 
+ 
+-	/* add to the tail of the overlay list */
+ 	list_add_tail(&ov->node, &ov_list);
+ 
+ 	of_overlay_notify(ov, OF_OVERLAY_POST_APPLY);
+@@ -554,13 +540,15 @@ int of_overlay_create(struct device_node *tree)
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_create);
+ 
+-/* check whether the given node, lies under the given tree */
++/*
++ * check whether the given node, lies under the given tree
++ * return 1 if under tree, else 0
++ */
+ static int overlay_subtree_check(struct device_node *tree,
+ 		struct device_node *dn)
+ {
+ 	struct device_node *child;
+ 
+-	/* match? */
+ 	if (tree == dn)
+ 		return 1;
+ 
+@@ -574,7 +562,10 @@ static int overlay_subtree_check(struct device_node *tree,
+ 	return 0;
+ }
+ 
+-/* check whether this overlay is the topmost */
++/*
++ * check whether this overlay is the topmost
++ * return 1 if topmost, else 0
++ */
+ static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn)
+ {
+ 	struct of_overlay *ovt;
+@@ -595,7 +586,6 @@ static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn)
+ 		}
+ 	}
+ 
+-	/* overlay is topmost */
+ 	return 1;
+ }
+ 
+@@ -645,7 +635,6 @@ int of_overlay_destroy(int id)
+ 		goto out;
+ 	}
+ 
+-	/* check whether the overlay is safe to remove */
+ 	if (!overlay_removal_is_ok(ov)) {
+ 		err = -EBUSY;
+ 		goto out;
+-- 
+2.19.0
+
diff --git a/patches/0906-of-overlay.c-Convert-comparisons-to-zero-or-NULL-to-.patch b/patches/0906-of-overlay.c-Convert-comparisons-to-zero-or-NULL-to-.patch
new file mode 100644
index 00000000000000..8f4aafb5f202bc
--- /dev/null
+++ b/patches/0906-of-overlay.c-Convert-comparisons-to-zero-or-NULL-to-.patch
@@ -0,0 +1,159 @@
+From fefe6771217e72666379f0696ee36a5add27c1de Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:22 -0700
+Subject: [PATCH 0906/1795] of: overlay.c: Convert comparisons to zero or NULL
+ to logical expressions
+
+Use normal shorthand for comparing a variable to zero.
+For variable "XXX":
+   convert (XXX == 0) to (!XXX)
+   convert (XXX != 0) to (XXX)
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit bbed8794d53b7043d7989e22bc2e1e399da305eb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 36 ++++++++++++++++++------------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index a42dd7b094c4..d3f4a5974a11 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -169,9 +169,9 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 
+ 	tprop = of_find_property(target, prop->name, NULL);
+ 
+-	if (of_prop_cmp(prop->name, "name") == 0 ||
+-	    of_prop_cmp(prop->name, "phandle") == 0 ||
+-	    of_prop_cmp(prop->name, "linux,phandle") == 0)
++	if (!of_prop_cmp(prop->name, "name") ||
++	    !of_prop_cmp(prop->name, "phandle") ||
++	    !of_prop_cmp(prop->name, "linux,phandle"))
+ 		return 0;
+ 
+ 	if (is_symbols_node) {
+@@ -182,10 +182,10 @@ static int of_overlay_apply_single_property(struct of_overlay *ov,
+ 		propn = __of_prop_dup(prop, GFP_KERNEL);
+ 	}
+ 
+-	if (propn == NULL)
++	if (!propn)
+ 		return -ENOMEM;
+ 
+-	if (tprop == NULL)
++	if (!tprop)
+ 		ret = of_changeset_add_property(&ov->cset, target, propn);
+ 	else
+ 		ret = of_changeset_update_property(&ov->cset, target, propn);
+@@ -206,14 +206,14 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+ 	int ret = 0;
+ 
+ 	cname = kbasename(child->full_name);
+-	if (cname == NULL)
++	if (!cname)
+ 		return -ENOMEM;
+ 
+ 	for_each_child_of_node(target, tchild)
+ 		if (!of_node_cmp(cname, kbasename(tchild->full_name)))
+ 			break;
+ 
+-	if (tchild != NULL) {
++	if (tchild) {
+ 		if (child->phandle)
+ 			return -EINVAL;
+ 
+@@ -271,7 +271,7 @@ static int of_overlay_apply_one(struct of_overlay *ov,
+ 
+ 	for_each_child_of_node(overlay, child) {
+ 		ret = of_overlay_apply_single_device_node(ov, target, child);
+-		if (ret != 0) {
++		if (ret) {
+ 			pr_err("Failed to apply single node @%pOF/%s\n",
+ 			       target, child->name);
+ 			of_node_put(child);
+@@ -300,7 +300,7 @@ static int of_overlay_apply(struct of_overlay *ov)
+ 
+ 		err = of_overlay_apply_one(ov, ovinfo->target, ovinfo->overlay,
+ 					   ovinfo->is_symbols_node);
+-		if (err != 0) {
++		if (err) {
+ 			pr_err("apply failed '%pOF'\n", ovinfo->target);
+ 			return err;
+ 		}
+@@ -323,11 +323,11 @@ static struct device_node *find_target_node(struct device_node *info_node)
+ 	int ret;
+ 
+ 	ret = of_property_read_u32(info_node, "target", &val);
+-	if (ret == 0)
++	if (!ret)
+ 		return of_find_node_by_phandle(val);
+ 
+ 	ret = of_property_read_string(info_node, "target-path", &path);
+-	if (ret == 0)
++	if (!ret)
+ 		return of_find_node_by_path(path);
+ 
+ 	pr_err("Failed to find target for node %p (%s)\n",
+@@ -354,11 +354,11 @@ static int of_fill_overlay_info(struct of_overlay *ov,
+ 		struct device_node *info_node, struct of_overlay_info *ovinfo)
+ {
+ 	ovinfo->overlay = of_get_child_by_name(info_node, "__overlay__");
+-	if (ovinfo->overlay == NULL)
++	if (!ovinfo->overlay)
+ 		goto err_fail;
+ 
+ 	ovinfo->target = find_target_node(info_node);
+-	if (ovinfo->target == NULL)
++	if (!ovinfo->target)
+ 		goto err_fail;
+ 
+ 	return 0;
+@@ -398,13 +398,13 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 		cnt++;
+ 
+ 	ovinfo = kcalloc(cnt, sizeof(*ovinfo), GFP_KERNEL);
+-	if (ovinfo == NULL)
++	if (!ovinfo)
+ 		return -ENOMEM;
+ 
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node) {
+ 		err = of_fill_overlay_info(ov, node, &ovinfo[cnt]);
+-		if (err == 0)
++		if (!err)
+ 			cnt++;
+ 	}
+ 
+@@ -422,7 +422,7 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 		cnt++;
+ 	}
+ 
+-	if (cnt == 0) {
++	if (!cnt) {
+ 		kfree(ovinfo);
+ 		return -ENODEV;
+ 	}
+@@ -478,7 +478,7 @@ int of_overlay_create(struct device_node *tree)
+ 	int err, id;
+ 
+ 	ov = kzalloc(sizeof(*ov), GFP_KERNEL);
+-	if (ov == NULL)
++	if (!ov)
+ 		return -ENOMEM;
+ 	ov->id = -1;
+ 
+@@ -629,7 +629,7 @@ int of_overlay_destroy(int id)
+ 	mutex_lock(&of_mutex);
+ 
+ 	ov = idr_find(&ov_idr, id);
+-	if (ov == NULL) {
++	if (!ov) {
+ 		err = -ENODEV;
+ 		pr_err("destroy: Could not find overlay #%d\n", id);
+ 		goto out;
+-- 
+2.19.0
+
diff --git a/patches/0907-of-overlay-rename-identifiers-to-more-reflect-what-t.patch b/patches/0907-of-overlay-rename-identifiers-to-more-reflect-what-t.patch
new file mode 100644
index 00000000000000..d424afd2eb721a
--- /dev/null
+++ b/patches/0907-of-overlay-rename-identifiers-to-more-reflect-what-t.patch
@@ -0,0 +1,1085 @@
+From d094f62a029c78fbd94b1ffa27135304d1391959 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:23 -0700
+Subject: [PATCH 0907/1795] of: overlay: rename identifiers to more reflect
+ what they do
+
+This patch is aimed primarily at drivers/of/overlay.c, but those
+changes also have a small impact in a few other files.
+
+overlay.c is difficult to read and maintain.  Improve readability:
+  - Rename functions, types and variables to better reflect what
+    they do and to be consistent with names in other places,
+    such as the device tree overlay FDT (flattened device tree),
+    and make the algorithms more clear
+  - Use the same names consistently throughout the file
+  - Update comments for name changes
+  - Fix incorrect comments
+
+This patch is intended to not introduce any functional change.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 0290c4ca2536a35e55c53cfb9058465b1f987b17)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/overlay-notes.txt   |  12 +-
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c |   5 +-
+ drivers/of/dynamic.c                         |   2 +-
+ drivers/of/overlay.c                         | 530 ++++++++++---------
+ drivers/of/unittest.c                        |  20 +-
+ include/linux/of.h                           |  12 +-
+ 6 files changed, 310 insertions(+), 271 deletions(-)
+
+diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt
+index eb7f2685fda1..c4aa0adf13ec 100644
+--- a/Documentation/devicetree/overlay-notes.txt
++++ b/Documentation/devicetree/overlay-notes.txt
+@@ -87,15 +87,15 @@ Overlay in-kernel API
+ 
+ The API is quite easy to use.
+ 
+-1. Call of_overlay_create() to create and apply an overlay. The return value
+-is a cookie identifying this overlay.
++1. Call of_overlay_apply() to create and apply an overlay changeset. The return
++value is an error or a cookie identifying this overlay.
+ 
+-2. Call of_overlay_destroy() to remove and cleanup the overlay previously
+-created via the call to of_overlay_create(). Removal of an overlay that
+-is stacked by another will not be permitted.
++2. Call of_overlay_remove() to remove and cleanup the overlay changeset
++previously created via the call to of_overlay_apply(). Removal of an overlay
++changeset that is stacked by another will not be permitted.
+ 
+ Finally, if you need to remove all overlays in one-go, just call
+-of_overlay_destroy_all() which will remove every single one in the correct
++of_overlay_remove_all() which will remove every single one in the correct
+ order.
+ 
+ Overlay DTS Format
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+index 623a9140493c..5f5b7ba35f1d 100644
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
++++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+@@ -247,9 +247,10 @@ static void __init tilcdc_convert_slave_node(void)
+ 
+ 	tilcdc_node_disable(slave);
+ 
+-	ret = of_overlay_create(overlay);
++	ret = of_overlay_apply(overlay);
+ 	if (ret)
+-		pr_err("%s: Creating overlay failed: %d\n", __func__, ret);
++		pr_err("%s: Applying overlay changeset failed: %d\n",
++			__func__, ret);
+ 	else
+ 		pr_info("%s: ti,tilcdc,slave node successfully converted\n",
+ 			__func__);
+diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c
+index 301b6db2b48d..124510d56421 100644
+--- a/drivers/of/dynamic.c
++++ b/drivers/of/dynamic.c
+@@ -775,7 +775,7 @@ int of_changeset_revert(struct of_changeset *ocs)
+ EXPORT_SYMBOL_GPL(of_changeset_revert);
+ 
+ /**
+- * of_changeset_action - Perform a changeset action
++ * of_changeset_action - Add an action to the tail of the changeset list
+  *
+  * @ocs:	changeset pointer
+  * @action:	action to perform
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index d3f4a5974a11..69610637af88 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -25,67 +25,63 @@
+ #include "of_private.h"
+ 
+ /**
+- * struct of_overlay_info - Holds a single overlay info
++ * struct fragment - info about fragment nodes in overlay expanded device tree
+  * @target:	target of the overlay operation
+- * @overlay:	pointer to the overlay contents node
+- *
+- * Holds a single overlay state, including all the overlay logs &
+- * records.
++ * @overlay:	pointer to the __overlay__ node
+  */
+-struct of_overlay_info {
++struct fragment {
+ 	struct device_node *target;
+ 	struct device_node *overlay;
+ 	bool is_symbols_node;
+ };
+ 
+ /**
+- * struct of_overlay - Holds a complete overlay transaction
+- * @node:	List on which we are located
+- * @count:	Count of ovinfo structures
+- * @ovinfo_tab:	Overlay info table (count sized)
+- * @cset:	Changeset to be used
+- *
+- * Holds a complete overlay transaction
++ * struct overlay_changeset
++ * @ovcs_list:	list on which we are located
++ * @count:	count of @fragments structures
++ * @fragments:	info about fragment nodes in overlay expanded device tree
++ * @cset:	changeset to apply fragments to live device tree
+  */
+-struct of_overlay {
++struct overlay_changeset {
+ 	int id;
+-	struct list_head node;
++	struct list_head ovcs_list;
+ 	int count;
+-	struct of_overlay_info *ovinfo_tab;
++	struct fragment *fragments;
+ 	struct of_changeset cset;
+ };
+ 
+-static int of_overlay_apply_one(struct of_overlay *ov,
+-		struct device_node *target, const struct device_node *overlay,
++static int build_changeset_next_level(struct overlay_changeset *ovcs,
++		struct device_node *target_node,
++		const struct device_node *overlay_node,
+ 		bool is_symbols_node);
+ 
+-static BLOCKING_NOTIFIER_HEAD(of_overlay_chain);
++static BLOCKING_NOTIFIER_HEAD(overlay_notify_chain);
+ 
+ int of_overlay_notifier_register(struct notifier_block *nb)
+ {
+-	return blocking_notifier_chain_register(&of_overlay_chain, nb);
++	return blocking_notifier_chain_register(&overlay_notify_chain, nb);
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_notifier_register);
+ 
+ int of_overlay_notifier_unregister(struct notifier_block *nb)
+ {
+-	return blocking_notifier_chain_unregister(&of_overlay_chain, nb);
++	return blocking_notifier_chain_unregister(&overlay_notify_chain, nb);
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_notifier_unregister);
+ 
+-static int of_overlay_notify(struct of_overlay *ov,
+-			     enum of_overlay_notify_action action)
++static int overlay_notify(struct overlay_changeset *ovcs,
++		enum of_overlay_notify_action action)
+ {
+ 	struct of_overlay_notify_data nd;
+ 	int i, ret;
+ 
+-	for (i = 0; i < ov->count; i++) {
+-		struct of_overlay_info *ovinfo = &ov->ovinfo_tab[i];
++	for (i = 0; i < ovcs->count; i++) {
++		struct fragment *fragment = &ovcs->fragments[i];
+ 
+-		nd.target = ovinfo->target;
+-		nd.overlay = ovinfo->overlay;
++		nd.target = fragment->target;
++		nd.overlay = fragment->overlay;
+ 
+-		ret = blocking_notifier_call_chain(&of_overlay_chain,
++		ret = blocking_notifier_call_chain(&overlay_notify_chain,
+ 						   action, &nd);
+ 		if (ret)
+ 			return notifier_to_errno(ret);
+@@ -94,10 +90,10 @@ static int of_overlay_notify(struct of_overlay *ov,
+ 	return 0;
+ }
+ 
+-static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov,
+-		const struct property *prop)
++static struct property *dup_and_fixup_symbol_prop(
++		struct overlay_changeset *ovcs, const struct property *prop)
+ {
+-	struct of_overlay_info *ovinfo;
++	struct fragment *fragment;
+ 	struct property *new;
+ 	const char *overlay_name;
+ 	char *label_path;
+@@ -116,18 +112,18 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov,
+ 	if (!new)
+ 		return NULL;
+ 
+-	for (k = 0; k < ov->count; k++) {
+-		ovinfo = &ov->ovinfo_tab[k];
+-		overlay_name = ovinfo->overlay->full_name;
++	for (k = 0; k < ovcs->count; k++) {
++		fragment = &ovcs->fragments[k];
++		overlay_name = fragment->overlay->full_name;
+ 		overlay_name_len = strlen(overlay_name);
+ 		if (!strncasecmp(symbol_path, overlay_name, overlay_name_len))
+ 			break;
+ 	}
+ 
+-	if (k >= ov->count)
++	if (k >= ovcs->count)
+ 		goto err_free;
+ 
+-	target_path = ovinfo->target->full_name;
++	target_path = fragment->target->full_name;
+ 	target_path_len = strlen(target_path);
+ 
+ 	label_path = symbol_path + overlay_name_len;
+@@ -156,82 +152,119 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov,
+ 
+ }
+ 
+-/*
++/**
++ * add_changeset_property() - add @overlay_prop to overlay changeset
++ * @ovcs:		overlay changeset
++ * @target_node:	where to place @overlay_prop in live tree
++ * @overlay_prop:	property to add or update, from overlay tree
++ * is_symbols_node:	1 if @target_node is "/__symbols__"
++ *
++ * If @overlay_prop does not already exist in @target_node, add changeset entry
++ * to add @overlay_prop in @target_node, else add changeset entry to update
++ * value of @overlay_prop.
++ *
+  * Some special properties are not updated (no error returned).
++ *
+  * Update of property in symbols node is not allowed.
++ *
++ * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
++ * invalid @overlay.
+  */
+-static int of_overlay_apply_single_property(struct of_overlay *ov,
+-		struct device_node *target, struct property *prop,
++static int add_changeset_property(struct overlay_changeset *ovcs,
++		struct device_node *target_node,
++		struct property *overlay_prop,
+ 		bool is_symbols_node)
+ {
+-	struct property *propn = NULL, *tprop;
++	struct property *new_prop = NULL, *prop;
+ 	int ret = 0;
+ 
+-	tprop = of_find_property(target, prop->name, NULL);
++	prop = of_find_property(target_node, overlay_prop->name, NULL);
+ 
+-	if (!of_prop_cmp(prop->name, "name") ||
+-	    !of_prop_cmp(prop->name, "phandle") ||
+-	    !of_prop_cmp(prop->name, "linux,phandle"))
++	if (!of_prop_cmp(overlay_prop->name, "name") ||
++	    !of_prop_cmp(overlay_prop->name, "phandle") ||
++	    !of_prop_cmp(overlay_prop->name, "linux,phandle"))
+ 		return 0;
+ 
+ 	if (is_symbols_node) {
+-		if (tprop)
++		if (prop)
+ 			return -EINVAL;
+-		propn = dup_and_fixup_symbol_prop(ov, prop);
++		new_prop = dup_and_fixup_symbol_prop(ovcs, overlay_prop);
+ 	} else {
+-		propn = __of_prop_dup(prop, GFP_KERNEL);
++		new_prop = __of_prop_dup(overlay_prop, GFP_KERNEL);
+ 	}
+ 
+-	if (!propn)
++	if (!new_prop)
+ 		return -ENOMEM;
+ 
+-	if (!tprop)
+-		ret = of_changeset_add_property(&ov->cset, target, propn);
++	if (!prop)
++		ret = of_changeset_add_property(&ovcs->cset, target_node,
++						new_prop);
+ 	else
+-		ret = of_changeset_update_property(&ov->cset, target, propn);
++		ret = of_changeset_update_property(&ovcs->cset, target_node,
++						   new_prop);
+ 
+ 	if (ret) {
+-		kfree(propn->name);
+-		kfree(propn->value);
+-		kfree(propn);
++		kfree(new_prop->name);
++		kfree(new_prop->value);
++		kfree(new_prop);
+ 	}
+ 	return ret;
+ }
+ 
+-static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+-		struct device_node *target, struct device_node *child)
++/**
++ * add_changeset_node() - add @node (and children) to overlay changeset
++ * @ovcs:		overlay changeset
++ * @target_node:	where to place @node in live tree
++ * @node:		node from within overlay device tree fragment
++ *
++ * If @node does not already exist in @target_node, add changeset entry
++ * to add @node in @target_node.
++ *
++ * If @node already exists in @target_node, and the existing node has
++ * a phandle, the overlay node is not allowed to have a phandle.
++ *
++ * If @node has child nodes, add the children recursively via
++ * build_changeset_next_level().
++ *
++ * NOTE: Multiple mods of created nodes not supported.
++ *
++ * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
++ * invalid @overlay.
++ */
++static int add_changeset_node(struct overlay_changeset *ovcs,
++		struct device_node *target_node, struct device_node *node)
+ {
+-	const char *cname;
++	const char *node_kbasename;
+ 	struct device_node *tchild;
+ 	int ret = 0;
+ 
+-	cname = kbasename(child->full_name);
+-	if (!cname)
++	node_kbasename = kbasename(node->full_name);
++	if (!node_kbasename)
+ 		return -ENOMEM;
+ 
+-	for_each_child_of_node(target, tchild)
+-		if (!of_node_cmp(cname, kbasename(tchild->full_name)))
++	for_each_child_of_node(target_node, tchild)
++		if (!of_node_cmp(node_kbasename, kbasename(tchild->full_name)))
+ 			break;
+ 
+ 	if (tchild) {
+-		if (child->phandle)
++		if (node->phandle)
+ 			return -EINVAL;
+ 
+-		/* apply overlay recursively */
+-		ret = of_overlay_apply_one(ov, tchild, child, 0);
++		ret = build_changeset_next_level(ovcs, tchild, node, 0);
+ 		of_node_put(tchild);
+ 	} else {
+-		tchild = __of_node_dup(child, "%pOF/%s", target, cname);
++		tchild = __of_node_dup(node, "%pOF/%s",
++				       target_node, node_kbasename);
+ 		if (!tchild)
+ 			return -ENOMEM;
+ 
+-		tchild->parent = target;
++		tchild->parent = target_node;
+ 
+-		ret = of_changeset_attach_node(&ov->cset, tchild);
++		ret = of_changeset_attach_node(&ovcs->cset, tchild);
+ 		if (ret)
+ 			return ret;
+ 
+-		ret = of_overlay_apply_one(ov, tchild, child, 0);
++		ret = build_changeset_next_level(ovcs, tchild, node, 0);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -239,29 +272,37 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov,
+ 	return ret;
+ }
+ 
+-/*
+- * Apply a single overlay node recursively.
++/**
++ * build_changeset_next_level() - add level of overlay changeset
++ * @ovcs:		overlay changeset
++ * @target_node:	where to place @overlay_node in live tree
++ * @overlay_node:	node from within an overlay device tree fragment
++ * @is_symbols_node:	@overlay_node is node "/__symbols__"
+  *
+- * Note that the in case of an error the target node is left
+- * in a inconsistent state. Error recovery should be performed
+- * by using the changeset.
++ * Add the properties (if any) and nodes (if any) from @overlay_node to the
++ * @ovcs->cset changeset.  If an added node has child nodes, they will
++ * be added recursively.
+  *
+  * Do not allow symbols node to have any children.
++ *
++ * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
++ * invalid @overlay_node.
+  */
+-static int of_overlay_apply_one(struct of_overlay *ov,
+-		struct device_node *target, const struct device_node *overlay,
++static int build_changeset_next_level(struct overlay_changeset *ovcs,
++		struct device_node *target_node,
++		const struct device_node *overlay_node,
+ 		bool is_symbols_node)
+ {
+ 	struct device_node *child;
+ 	struct property *prop;
+ 	int ret;
+ 
+-	for_each_property_of_node(overlay, prop) {
+-		ret = of_overlay_apply_single_property(ov, target, prop,
+-						       is_symbols_node);
++	for_each_property_of_node(overlay_node, prop) {
++		ret = add_changeset_property(ovcs, target_node, prop,
++					     is_symbols_node);
+ 		if (ret) {
+ 			pr_err("Failed to apply prop @%pOF/%s\n",
+-			       target, prop->name);
++			       target_node, prop->name);
+ 			return ret;
+ 		}
+ 	}
+@@ -269,11 +310,11 @@ static int of_overlay_apply_one(struct of_overlay *ov,
+ 	if (is_symbols_node)
+ 		return 0;
+ 
+-	for_each_child_of_node(overlay, child) {
+-		ret = of_overlay_apply_single_device_node(ov, target, child);
++	for_each_child_of_node(overlay_node, child) {
++		ret = add_changeset_node(ovcs, target_node, child);
+ 		if (ret) {
+-			pr_err("Failed to apply single node @%pOF/%s\n",
+-			       target, child->name);
++			pr_err("Failed to apply node @%pOF/%s\n",
++			       target_node, child->name);
+ 			of_node_put(child);
+ 			return ret;
+ 		}
+@@ -283,26 +324,30 @@ static int of_overlay_apply_one(struct of_overlay *ov,
+ }
+ 
+ /**
+- * of_overlay_apply() - Apply @count overlays pointed at by @ovinfo_tab
+- * @ov:		Overlay to apply
++ * build_changeset() - populate overlay changeset in @ovcs from @ovcs->fragments
++ * @ovcs:	Overlay changeset
+  *
+- * Applies the overlays given, while handling all error conditions
+- * appropriately. Either the operation succeeds, or if it fails the
+- * live tree is reverted to the state before the attempt.
+- * Returns 0, or an error if the overlay attempt failed.
++ * Create changeset @ovcs->cset to contain the nodes and properties of the
++ * overlay device tree fragments in @ovcs->fragments[].  If an error occurs,
++ * any portions of the changeset that were successfully created will remain
++ * in @ovcs->cset.
++ *
++ * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
++ * invalid overlay in @ovcs->fragments[].
+  */
+-static int of_overlay_apply(struct of_overlay *ov)
++static int build_changeset(struct overlay_changeset *ovcs)
+ {
+-	int i, err;
++	int i, ret;
+ 
+-	for (i = 0; i < ov->count; i++) {
+-		struct of_overlay_info *ovinfo = &ov->ovinfo_tab[i];
++	for (i = 0; i < ovcs->count; i++) {
++		struct fragment *fragment = &ovcs->fragments[i];
+ 
+-		err = of_overlay_apply_one(ov, ovinfo->target, ovinfo->overlay,
+-					   ovinfo->is_symbols_node);
+-		if (err) {
+-			pr_err("apply failed '%pOF'\n", ovinfo->target);
+-			return err;
++		ret = build_changeset_next_level(ovcs, fragment->target,
++					       fragment->overlay,
++					       fragment->is_symbols_node);
++		if (ret) {
++			pr_err("apply failed '%pOF'\n", fragment->target);
++			return ret;
+ 		}
+ 	}
+ 
+@@ -350,45 +395,46 @@ static struct device_node *find_target_node(struct device_node *info_node)
+  *
+  * Returns 0 on success, or a negative error value.
+  */
+-static int of_fill_overlay_info(struct of_overlay *ov,
+-		struct device_node *info_node, struct of_overlay_info *ovinfo)
++static int of_fill_overlay_info(struct overlay_changeset *ovcset,
++		struct device_node *info_node, struct fragment *fragment)
+ {
+-	ovinfo->overlay = of_get_child_by_name(info_node, "__overlay__");
+-	if (!ovinfo->overlay)
++	fragment->overlay = of_get_child_by_name(info_node, "__overlay__");
++	if (!fragment->overlay)
+ 		goto err_fail;
+ 
+-	ovinfo->target = find_target_node(info_node);
+-	if (!ovinfo->target)
++	fragment->target = find_target_node(info_node);
++	if (!fragment->target)
+ 		goto err_fail;
+ 
+ 	return 0;
+ 
+ err_fail:
+-	of_node_put(ovinfo->target);
+-	of_node_put(ovinfo->overlay);
++	of_node_put(fragment->target);
++	of_node_put(fragment->overlay);
+ 
+-	memset(ovinfo, 0, sizeof(*ovinfo));
++	memset(fragment, 0, sizeof(*fragment));
+ 	return -EINVAL;
+ }
+ 
+ /**
+- * of_build_overlay_info() - Build an overlay info array
+- * @ov		Overlay to build
+- * @tree:	Device node containing all the overlays
++ * init_overlay_changeset() - initialize overlay changeset from overlay tree
++ * @ovcs	Overlay changeset to build
++ * @tree:	Contains all the overlay fragments and overlay fixup nodes
+  *
+- * Helper function that given a tree containing overlay information,
+- * allocates and builds an overlay info array containing it, ready
+- * for use using of_overlay_apply.
++ * Initialize @ovcs.  Populate @ovcs->fragments with node information from
++ * the top level of @tree.  The relevant top level nodes are the fragment
++ * nodes and the __symbols__ node.  Any other top level node will be ignored.
+  *
+- * Returns 0 on success with the @cntp @ovinfop pointers valid,
+- * while on error a negative error value is returned.
++ * Returns 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error
++ * detected in @tree, or -ENODEV if no valid nodes found.
+  */
+-static int of_build_overlay_info(struct of_overlay *ov,
++static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		struct device_node *tree)
+ {
+ 	struct device_node *node;
+-	struct of_overlay_info *ovinfo;
+-	int cnt, err;
++	struct fragment *fragment;
++	struct fragment *fragments;
++	int cnt, ret;
+ 
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node)
+@@ -397,24 +443,25 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 	if (of_get_child_by_name(tree, "__symbols__"))
+ 		cnt++;
+ 
+-	ovinfo = kcalloc(cnt, sizeof(*ovinfo), GFP_KERNEL);
+-	if (!ovinfo)
++	fragments = kcalloc(cnt, sizeof(*fragments), GFP_KERNEL);
++	if (!fragments)
+ 		return -ENOMEM;
+ 
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node) {
+-		err = of_fill_overlay_info(ov, node, &ovinfo[cnt]);
+-		if (!err)
++		ret = of_fill_overlay_info(ovcs, node, &fragments[cnt]);
++		if (!ret)
+ 			cnt++;
+ 	}
+ 
+ 	node = of_get_child_by_name(tree, "__symbols__");
+ 	if (node) {
+-		ovinfo[cnt].overlay = node;
+-		ovinfo[cnt].target = of_find_node_by_path("/__symbols__");
+-		ovinfo[cnt].is_symbols_node = 1;
++		fragment = &fragments[cnt];
++		fragment->overlay = node;
++		fragment->target = of_find_node_by_path("/__symbols__");
++		fragment->is_symbols_node = 1;
+ 
+-		if (!ovinfo[cnt].target) {
++		if (!fragment->target) {
+ 			pr_err("no symbols in root of device tree.\n");
+ 			return -EINVAL;
+ 		}
+@@ -423,137 +470,127 @@ static int of_build_overlay_info(struct of_overlay *ov,
+ 	}
+ 
+ 	if (!cnt) {
+-		kfree(ovinfo);
++		kfree(fragments);
+ 		return -ENODEV;
+ 	}
+ 
+-	ov->count = cnt;
+-	ov->ovinfo_tab = ovinfo;
++	ovcs->count = cnt;
++	ovcs->fragments = fragments;
+ 
+ 	return 0;
+ }
+ 
+ /**
+- * of_free_overlay_info() - Free an overlay info array
+- * @ov		Overlay to free the overlay info from
+- * @ovinfo_tab:	Array of overlay_info's to free
++ * free_overlay_fragments() - Free a fragments array
++ * @ovcs	Overlay to free the overlay info from
+  *
+- * Releases the memory of a previously allocated ovinfo array
+- * by of_build_overlay_info.
+- * Returns 0, or an error if the arguments are bogus.
++ * Frees the memory of an ovcs->fragments[] array.
+  */
+-static int of_free_overlay_info(struct of_overlay *ov)
++static void free_overlay_fragments(struct overlay_changeset *ovcs)
+ {
+-	struct of_overlay_info *ovinfo;
+ 	int i;
+ 
+ 	/* do it in reverse */
+-	for (i = ov->count - 1; i >= 0; i--) {
+-		ovinfo = &ov->ovinfo_tab[i];
+-
+-		of_node_put(ovinfo->target);
+-		of_node_put(ovinfo->overlay);
++	for (i = ovcs->count - 1; i >= 0; i--) {
++		of_node_put(ovcs->fragments[i].target);
++		of_node_put(ovcs->fragments[i].overlay);
+ 	}
+-	kfree(ov->ovinfo_tab);
+ 
+-	return 0;
++	kfree(ovcs->fragments);
+ }
+ 
+-static LIST_HEAD(ov_list);
+-static DEFINE_IDR(ov_idr);
++static LIST_HEAD(ovcs_list);
++static DEFINE_IDR(ovcs_idr);
+ 
+ /**
+- * of_overlay_create() - Create and apply an overlay
+- * @tree:	Device node containing all the overlays
++ * of_overlay_apply() - Create and apply an overlay changeset
++ * @tree:	Expanded overlay device tree
+  *
+- * Creates and applies an overlay while also keeping track
+- * of the overlay in a list. This list can be used to prevent
+- * illegal overlay removals.
++ * Creates and applies an overlay changeset.  If successful, the overlay
++ * changeset is added to the overlay changeset list.
+  *
+- * Returns the id of the created overlay, or a negative error number
++ * Returns the id of the created overlay changeset, or a negative error number
+  */
+-int of_overlay_create(struct device_node *tree)
++int of_overlay_apply(struct device_node *tree)
+ {
+-	struct of_overlay *ov;
+-	int err, id;
++	struct overlay_changeset *ovcs;
++	int id, ret;
+ 
+-	ov = kzalloc(sizeof(*ov), GFP_KERNEL);
+-	if (!ov)
++	ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
++	if (!ovcs)
+ 		return -ENOMEM;
+-	ov->id = -1;
++	ovcs->id = -1;
+ 
+-	INIT_LIST_HEAD(&ov->node);
++	INIT_LIST_HEAD(&ovcs->ovcs_list);
+ 
+-	of_changeset_init(&ov->cset);
++	of_changeset_init(&ovcs->cset);
+ 
+ 	mutex_lock(&of_mutex);
+ 
+-	id = idr_alloc(&ov_idr, ov, 0, 0, GFP_KERNEL);
++	id = idr_alloc(&ovcs_idr, ovcs, 0, 0, GFP_KERNEL);
+ 	if (id < 0) {
+-		err = id;
++		ret = id;
+ 		goto err_destroy_trans;
+ 	}
+-	ov->id = id;
++	ovcs->id = id;
+ 
+-	err = of_build_overlay_info(ov, tree);
+-	if (err) {
+-		pr_err("of_build_overlay_info() failed for tree@%pOF\n",
++	ret = init_overlay_changeset(ovcs, tree);
++	if (ret) {
++		pr_err("init_overlay_changeset() failed for tree@%pOF\n",
+ 		       tree);
+ 		goto err_free_idr;
+ 	}
+ 
+-	err = of_overlay_notify(ov, OF_OVERLAY_PRE_APPLY);
+-	if (err < 0) {
+-		pr_err("%s: Pre-apply notifier failed (err=%d)\n",
+-		       __func__, err);
+-		goto err_free_idr;
++	ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY);
++	if (ret < 0) {
++		pr_err("%s: Pre-apply notifier failed (ret=%d)\n",
++		       __func__, ret);
++		goto err_free_overlay_fragments;
+ 	}
+ 
+-	err = of_overlay_apply(ov);
+-	if (err)
+-		goto err_abort_trans;
+-
+-	err = __of_changeset_apply(&ov->cset);
+-	if (err)
+-		goto err_revert_overlay;
++	ret = build_changeset(ovcs);
++	if (ret)
++		goto err_free_overlay_fragments;
+ 
++	ret = __of_changeset_apply(&ovcs->cset);
++	if (ret)
++		goto err_free_overlay_fragments;
+ 
+-	list_add_tail(&ov->node, &ov_list);
++	list_add_tail(&ovcs->ovcs_list, &ovcs_list);
+ 
+-	of_overlay_notify(ov, OF_OVERLAY_POST_APPLY);
++	overlay_notify(ovcs, OF_OVERLAY_POST_APPLY);
+ 
+ 	mutex_unlock(&of_mutex);
+ 
+ 	return id;
+ 
+-err_revert_overlay:
+-err_abort_trans:
+-	of_free_overlay_info(ov);
++err_free_overlay_fragments:
++	free_overlay_fragments(ovcs);
+ err_free_idr:
+-	idr_remove(&ov_idr, ov->id);
++	idr_remove(&ovcs_idr, ovcs->id);
+ err_destroy_trans:
+-	of_changeset_destroy(&ov->cset);
+-	kfree(ov);
++	of_changeset_destroy(&ovcs->cset);
++	kfree(ovcs);
+ 	mutex_unlock(&of_mutex);
+ 
+-	return err;
++	return ret;
+ }
+-EXPORT_SYMBOL_GPL(of_overlay_create);
++EXPORT_SYMBOL_GPL(of_overlay_apply);
+ 
+ /*
+- * check whether the given node, lies under the given tree
+- * return 1 if under tree, else 0
++ * Find @np in @tree.
++ *
++ * Returns 1 if @np is @tree or is contained in @tree, else 0
+  */
+-static int overlay_subtree_check(struct device_node *tree,
+-		struct device_node *dn)
++static int find_node(struct device_node *tree, struct device_node *np)
+ {
+ 	struct device_node *child;
+ 
+-	if (tree == dn)
++	if (tree == np)
+ 		return 1;
+ 
+ 	for_each_child_of_node(tree, child) {
+-		if (overlay_subtree_check(child, dn)) {
++		if (find_node(child, np)) {
+ 			of_node_put(child);
+ 			return 1;
+ 		}
+@@ -563,30 +600,32 @@ static int overlay_subtree_check(struct device_node *tree,
+ }
+ 
+ /*
+- * check whether this overlay is the topmost
+- * return 1 if topmost, else 0
++ * Is @remove_ce_np a child of or the same as any
++ * node in an overlay changeset more topmost than @remove_ovcs?
++ *
++ * Returns 1 if found, else 0
+  */
+-static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn)
++static int node_in_later_cs(struct overlay_changeset *remove_ovcs,
++		struct device_node *remove_ce_np)
+ {
+-	struct of_overlay *ovt;
++	struct overlay_changeset *ovcs;
+ 	struct of_changeset_entry *ce;
+ 
+-	list_for_each_entry_reverse(ovt, &ov_list, node) {
+-		/* if we hit ourselves, we're done */
+-		if (ovt == ov)
++	list_for_each_entry_reverse(ovcs, &ovcs_list, ovcs_list) {
++		if (ovcs == remove_ovcs)
+ 			break;
+ 
+-		/* check against each subtree affected by this overlay */
+-		list_for_each_entry(ce, &ovt->cset.entries, node) {
+-			if (overlay_subtree_check(ce->np, dn)) {
++		list_for_each_entry(ce, &ovcs->cset.entries, node) {
++			if (find_node(ce->np, remove_ce_np)) {
+ 				pr_err("%s: #%d clashes #%d @%pOF\n",
+-					__func__, ov->id, ovt->id, dn);
+-				return 0;
++					__func__, remove_ovcs->id, ovcs->id,
++					remove_ce_np);
++				return 1;
+ 			}
+ 		}
+ 	}
+ 
+-	return 1;
++	return 0;
+ }
+ 
+ /*
+@@ -599,13 +638,13 @@ static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn)
+  * the one closest to the tail. If another overlay has affected this
+  * device node and is closest to the tail, then removal is not permited.
+  */
+-static int overlay_removal_is_ok(struct of_overlay *ov)
++static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+ {
+-	struct of_changeset_entry *ce;
++	struct of_changeset_entry *remove_ce;
+ 
+-	list_for_each_entry(ce, &ov->cset.entries, node) {
+-		if (!overlay_is_topmost(ov, ce->np)) {
+-			pr_err("overlay #%d is not topmost\n", ov->id);
++	list_for_each_entry(remove_ce, &remove_ovcs->cset.entries, node) {
++		if (node_in_later_cs(remove_ovcs, remove_ce->np)) {
++			pr_err("overlay #%d is not topmost\n", remove_ovcs->id);
+ 			return 0;
+ 		}
+ 	}
+@@ -614,74 +653,73 @@ static int overlay_removal_is_ok(struct of_overlay *ov)
+ }
+ 
+ /**
+- * of_overlay_destroy() - Removes an overlay
+- * @id:	Overlay id number returned by a previous call to of_overlay_create
++ * of_overlay_remove() - Revert and free an overlay changeset
++ * @ovcs_id:	Overlay changeset id number
+  *
+- * Removes an overlay if it is permissible.
++ * Removes an overlay if it is permissible.  ovcs_id was previously returned
++ * by of_overlay_apply().
+  *
+  * Returns 0 on success, or a negative error number
+  */
+-int of_overlay_destroy(int id)
++int of_overlay_remove(int ovcs_id)
+ {
+-	struct of_overlay *ov;
+-	int err;
++	struct overlay_changeset *ovcs;
++	int ret = 0;
+ 
+ 	mutex_lock(&of_mutex);
+ 
+-	ov = idr_find(&ov_idr, id);
+-	if (!ov) {
+-		err = -ENODEV;
+-		pr_err("destroy: Could not find overlay #%d\n", id);
++	ovcs = idr_find(&ovcs_idr, ovcs_id);
++	if (!ovcs) {
++		ret = -ENODEV;
++		pr_err("remove: Could not find overlay #%d\n", ovcs_id);
+ 		goto out;
+ 	}
+ 
+-	if (!overlay_removal_is_ok(ov)) {
+-		err = -EBUSY;
++	if (!overlay_removal_is_ok(ovcs)) {
++		ret = -EBUSY;
+ 		goto out;
+ 	}
+ 
+-	of_overlay_notify(ov, OF_OVERLAY_PRE_REMOVE);
+-	list_del(&ov->node);
+-	__of_changeset_revert(&ov->cset);
+-	of_overlay_notify(ov, OF_OVERLAY_POST_REMOVE);
+-	of_free_overlay_info(ov);
+-	idr_remove(&ov_idr, id);
+-	of_changeset_destroy(&ov->cset);
+-	kfree(ov);
+-
+-	err = 0;
++	overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE);
++	list_del(&ovcs->ovcs_list);
++	__of_changeset_revert(&ovcs->cset);
++	overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
++	free_overlay_fragments(ovcs);
++	idr_remove(&ovcs_idr, ovcs_id);
++	of_changeset_destroy(&ovcs->cset);
++	kfree(ovcs);
+ 
+ out:
+ 	mutex_unlock(&of_mutex);
+ 
+-	return err;
++	return ret;
+ }
+-EXPORT_SYMBOL_GPL(of_overlay_destroy);
++EXPORT_SYMBOL_GPL(of_overlay_remove);
+ 
+ /**
+- * of_overlay_destroy_all() - Removes all overlays from the system
++ * of_overlay_remove_all() - Reverts and frees all overlay changesets
+  *
+  * Removes all overlays from the system in the correct order.
+  *
+  * Returns 0 on success, or a negative error number
+  */
+-int of_overlay_destroy_all(void)
++int of_overlay_remove_all(void)
+ {
+-	struct of_overlay *ov, *ovn;
++	struct overlay_changeset *ovcs, *ovcs_n;
+ 
+ 	mutex_lock(&of_mutex);
+ 
+ 	/* the tail of list is guaranteed to be safe to remove */
+-	list_for_each_entry_safe_reverse(ov, ovn, &ov_list, node) {
+-		list_del(&ov->node);
+-		__of_changeset_revert(&ov->cset);
+-		of_free_overlay_info(ov);
+-		idr_remove(&ov_idr, ov->id);
+-		kfree(ov);
++	list_for_each_entry_safe_reverse(ovcs, ovcs_n, &ovcs_list, ovcs_list) {
++		list_del(&ovcs->ovcs_list);
++		__of_changeset_revert(&ovcs->cset);
++		free_overlay_fragments(ovcs);
++		idr_remove(&ovcs_idr, ovcs->id);
++		kfree(ovcs);
+ 	}
+ 
+ 	mutex_unlock(&of_mutex);
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL_GPL(of_overlay_destroy_all);
++EXPORT_SYMBOL_GPL(of_overlay_remove_all);
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index 4db57549baf8..2a557bfd0a2c 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -1231,7 +1231,7 @@ static void of_unittest_destroy_tracked_overlays(void)
+ 			if (!(overlay_id_bits[BIT_WORD(id)] & BIT_MASK(id)))
+ 				continue;
+ 
+-			ret = of_overlay_destroy(id + overlay_first_id);
++			ret = of_overlay_remove(id + overlay_first_id);
+ 			if (ret == -ENODEV) {
+ 				pr_warn("%s: no overlay to destroy for #%d\n",
+ 					__func__, id + overlay_first_id);
+@@ -1263,7 +1263,7 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ 		goto out;
+ 	}
+ 
+-	ret = of_overlay_create(np);
++	ret = of_overlay_apply(np);
+ 	if (ret < 0) {
+ 		unittest(0, "could not create overlay from \"%s\"\n",
+ 				overlay_path(overlay_nr));
+@@ -1348,7 +1348,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = of_overlay_destroy(ov_id);
++	ret = of_overlay_remove(ov_id);
+ 	if (ret != 0) {
+ 		unittest(0, "overlay @\"%s\" failed to be destroyed @\"%s\"\n",
+ 				overlay_path(overlay_nr),
+@@ -1477,7 +1477,7 @@ static void of_unittest_overlay_6(void)
+ 			return;
+ 		}
+ 
+-		ret = of_overlay_create(np);
++		ret = of_overlay_apply(np);
+ 		if (ret < 0)  {
+ 			unittest(0, "could not create overlay from \"%s\"\n",
+ 					overlay_path(overlay_nr + i));
+@@ -1501,7 +1501,7 @@ static void of_unittest_overlay_6(void)
+ 	}
+ 
+ 	for (i = 1; i >= 0; i--) {
+-		ret = of_overlay_destroy(ov_id[i]);
++		ret = of_overlay_remove(ov_id[i]);
+ 		if (ret != 0) {
+ 			unittest(0, "overlay @\"%s\" failed destroy @\"%s\"\n",
+ 					overlay_path(overlay_nr + i),
+@@ -1547,7 +1547,7 @@ static void of_unittest_overlay_8(void)
+ 			return;
+ 		}
+ 
+-		ret = of_overlay_create(np);
++		ret = of_overlay_apply(np);
+ 		if (ret < 0)  {
+ 			unittest(0, "could not create overlay from \"%s\"\n",
+ 					overlay_path(overlay_nr + i));
+@@ -1558,7 +1558,7 @@ static void of_unittest_overlay_8(void)
+ 	}
+ 
+ 	/* now try to remove first overlay (it should fail) */
+-	ret = of_overlay_destroy(ov_id[0]);
++	ret = of_overlay_remove(ov_id[0]);
+ 	if (ret == 0) {
+ 		unittest(0, "overlay @\"%s\" was destroyed @\"%s\"\n",
+ 				overlay_path(overlay_nr + 0),
+@@ -1569,7 +1569,7 @@ static void of_unittest_overlay_8(void)
+ 
+ 	/* removing them in order should work */
+ 	for (i = 1; i >= 0; i--) {
+-		ret = of_overlay_destroy(ov_id[i]);
++		ret = of_overlay_remove(ov_id[i]);
+ 		if (ret != 0) {
+ 			unittest(0, "overlay @\"%s\" not destroyed @\"%s\"\n",
+ 					overlay_path(overlay_nr + i),
+@@ -2150,9 +2150,9 @@ static int __init overlay_data_add(int onum)
+ 		goto out_free_np_overlay;
+ 	}
+ 
+-	ret = of_overlay_create(info->np_overlay);
++	ret = of_overlay_apply(info->np_overlay);
+ 	if (ret < 0) {
+-		pr_err("of_overlay_create() (ret=%d), %d\n", ret, onum);
++		pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum);
+ 		goto out_free_np_overlay;
+ 	} else {
+ 		info->overlay_id = ret;
+diff --git a/include/linux/of.h b/include/linux/of.h
+index b240ed69dc96..211be870600e 100644
+--- a/include/linux/of.h
++++ b/include/linux/of.h
+@@ -1316,26 +1316,26 @@ struct of_overlay_notify_data {
+ #ifdef CONFIG_OF_OVERLAY
+ 
+ /* ID based overlays; the API for external users */
+-int of_overlay_create(struct device_node *tree);
+-int of_overlay_destroy(int id);
+-int of_overlay_destroy_all(void);
++int of_overlay_apply(struct device_node *tree);
++int of_overlay_remove(int id);
++int of_overlay_remove_all(void);
+ 
+ int of_overlay_notifier_register(struct notifier_block *nb);
+ int of_overlay_notifier_unregister(struct notifier_block *nb);
+ 
+ #else
+ 
+-static inline int of_overlay_create(struct device_node *tree)
++static inline int of_overlay_apply(struct device_node *tree)
+ {
+ 	return -ENOTSUPP;
+ }
+ 
+-static inline int of_overlay_destroy(int id)
++static inline int of_overlay_remove(int id)
+ {
+ 	return -ENOTSUPP;
+ }
+ 
+-static inline int of_overlay_destroy_all(void)
++static inline int of_overlay_remove_all(void)
+ {
+ 	return -ENOTSUPP;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0908-of-overlay-rename-identifiers-in-dup_and_fixup_symbo.patch b/patches/0908-of-overlay-rename-identifiers-in-dup_and_fixup_symbo.patch
new file mode 100644
index 00000000000000..68bcbc83b5180a
--- /dev/null
+++ b/patches/0908-of-overlay-rename-identifiers-in-dup_and_fixup_symbo.patch
@@ -0,0 +1,79 @@
+From f1cc5136a231fe1afe09b0f0360f2befa014f0a9 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:24 -0700
+Subject: [PATCH 0908/1795] of: overlay: rename identifiers in
+ dup_and_fixup_symbol_prop()
+
+More renaming of identifiers to better reflect what they do.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 42b2e94fe83c354b4373992c8ea28ef0ace2e633)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 69610637af88..bb8867cae05b 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -90,17 +90,29 @@ static int overlay_notify(struct overlay_changeset *ovcs,
+ 	return 0;
+ }
+ 
++/*
++ * The properties in the "/__symbols__" node are "symbols".
++ *
++ * The value of properties in the "/__symbols__" node is the path of a
++ * node in the subtree of a fragment node's "__overlay__" node, for
++ * example "/fragment@0/__overlay__/symbol_path_tail".  Symbol_path_tail
++ * can be a single node or it may be a multi-node path.
++ *
++ * The duplicated property value will be modified by replacing the
++ * "/fragment_name/__overlay/" portion of the value  with the target
++ * path from the fragment node.
++ */
+ static struct property *dup_and_fixup_symbol_prop(
+ 		struct overlay_changeset *ovcs, const struct property *prop)
+ {
+ 	struct fragment *fragment;
+ 	struct property *new;
+ 	const char *overlay_name;
+-	char *label_path;
++	char *symbol_path_tail;
+ 	char *symbol_path;
+ 	const char *target_path;
+ 	int k;
+-	int label_path_len;
++	int symbol_path_tail_len;
+ 	int overlay_name_len;
+ 	int target_path_len;
+ 
+@@ -126,18 +138,18 @@ static struct property *dup_and_fixup_symbol_prop(
+ 	target_path = fragment->target->full_name;
+ 	target_path_len = strlen(target_path);
+ 
+-	label_path = symbol_path + overlay_name_len;
+-	label_path_len = strlen(label_path);
++	symbol_path_tail = symbol_path + overlay_name_len;
++	symbol_path_tail_len = strlen(symbol_path_tail);
+ 
+ 	new->name = kstrdup(prop->name, GFP_KERNEL);
+-	new->length = target_path_len + label_path_len + 1;
++	new->length = target_path_len + symbol_path_tail_len + 1;
+ 	new->value = kzalloc(new->length, GFP_KERNEL);
+ 
+ 	if (!new->name || !new->value)
+ 		goto err_free;
+ 
+ 	strcpy(new->value, target_path);
+-	strcpy(new->value + target_path_len, label_path);
++	strcpy(new->value + target_path_len, symbol_path_tail);
+ 
+ 	of_property_set_flag(new, OF_DYNAMIC);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0909-of-overlay-minor-restructuring.patch b/patches/0909-of-overlay-minor-restructuring.patch
new file mode 100644
index 00000000000000..608a9fb046b3e2
--- /dev/null
+++ b/patches/0909-of-overlay-minor-restructuring.patch
@@ -0,0 +1,386 @@
+From 71919f535451b91fd723581a47c346f3d6e6d36f Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:25 -0700
+Subject: [PATCH 0909/1795] of: overlay: minor restructuring
+
+Continue improving the readability of overlay.c.  The previous patches
+renamed identifiers.  This patch is split out from the previous patches
+to make the previous patches easier to review.
+
+Changes are:
+  - minor code restructuring
+  - some initialization of an overlay changeset occurred outside of
+    init_overlay_changeset(), move that into init_overlay_changeset()
+  - consolidate freeing an overlay changeset into free_overlay_changeset()
+
+This patch is intended to not introduce any functional change.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 61b4de4e0b384f4a22c55c3bada604da49cec4e1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 205 +++++++++++++++++++------------------------
+ 1 file changed, 92 insertions(+), 113 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index bb8867cae05b..905916e17eec 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -55,6 +55,9 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		const struct device_node *overlay_node,
+ 		bool is_symbols_node);
+ 
++static LIST_HEAD(ovcs_list);
++static DEFINE_IDR(ovcs_idr);
++
+ static BLOCKING_NOTIFIER_HEAD(overlay_notify_chain);
+ 
+ int of_overlay_notifier_register(struct notifier_block *nb)
+@@ -160,8 +163,6 @@ static struct property *dup_and_fixup_symbol_prop(
+ 	kfree(new->value);
+ 	kfree(new);
+ 	return NULL;
+-
+-
+ }
+ 
+ /**
+@@ -258,13 +259,7 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+ 		if (!of_node_cmp(node_kbasename, kbasename(tchild->full_name)))
+ 			break;
+ 
+-	if (tchild) {
+-		if (node->phandle)
+-			return -EINVAL;
+-
+-		ret = build_changeset_next_level(ovcs, tchild, node, 0);
+-		of_node_put(tchild);
+-	} else {
++	if (!tchild) {
+ 		tchild = __of_node_dup(node, "%pOF/%s",
+ 				       target_node, node_kbasename);
+ 		if (!tchild)
+@@ -276,11 +271,15 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+ 		if (ret)
+ 			return ret;
+ 
+-		ret = build_changeset_next_level(ovcs, tchild, node, 0);
+-		if (ret)
+-			return ret;
++		return build_changeset_next_level(ovcs, tchild, node, 0);
+ 	}
+ 
++	if (node->phandle)
++		return -EINVAL;
++
++	ret = build_changeset_next_level(ovcs, tchild, node, 0);
++	of_node_put(tchild);
++
+ 	return ret;
+ }
+ 
+@@ -393,41 +392,6 @@ static struct device_node *find_target_node(struct device_node *info_node)
+ 	return NULL;
+ }
+ 
+-/**
+- * of_fill_overlay_info() - Fill an overlay info structure
+- * @ov		Overlay to fill
+- * @info_node:	Device node containing the overlay
+- * @ovinfo:	Pointer to the overlay info structure to fill
+- *
+- * Fills an overlay info structure with the overlay information
+- * from a device node. This device node must have a target property
+- * which contains a phandle of the overlay target node, and an
+- * __overlay__ child node which has the overlay contents.
+- * Both ovinfo->target & ovinfo->overlay have their references taken.
+- *
+- * Returns 0 on success, or a negative error value.
+- */
+-static int of_fill_overlay_info(struct overlay_changeset *ovcset,
+-		struct device_node *info_node, struct fragment *fragment)
+-{
+-	fragment->overlay = of_get_child_by_name(info_node, "__overlay__");
+-	if (!fragment->overlay)
+-		goto err_fail;
+-
+-	fragment->target = find_target_node(info_node);
+-	if (!fragment->target)
+-		goto err_fail;
+-
+-	return 0;
+-
+-err_fail:
+-	of_node_put(fragment->target);
+-	of_node_put(fragment->overlay);
+-
+-	memset(fragment, 0, sizeof(*fragment));
+-	return -EINVAL;
+-}
+-
+ /**
+  * init_overlay_changeset() - initialize overlay changeset from overlay tree
+  * @ovcs	Overlay changeset to build
+@@ -438,32 +402,61 @@ static int of_fill_overlay_info(struct overlay_changeset *ovcset,
+  * nodes and the __symbols__ node.  Any other top level node will be ignored.
+  *
+  * Returns 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error
+- * detected in @tree, or -ENODEV if no valid nodes found.
++ * detected in @tree, or -ENOSPC if idr_alloc() error.
+  */
+ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		struct device_node *tree)
+ {
+-	struct device_node *node;
++	struct device_node *node, *overlay_node;
+ 	struct fragment *fragment;
+ 	struct fragment *fragments;
+ 	int cnt, ret;
+ 
++	INIT_LIST_HEAD(&ovcs->ovcs_list);
++
++	of_changeset_init(&ovcs->cset);
++
++	ovcs->id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL);
++	if (ovcs->id <= 0)
++		return ovcs->id;
++
+ 	cnt = 0;
+-	for_each_child_of_node(tree, node)
+-		cnt++;
+ 
+-	if (of_get_child_by_name(tree, "__symbols__"))
++	/* fragment nodes */
++	for_each_child_of_node(tree, node) {
++		overlay_node = of_get_child_by_name(node, "__overlay__");
++		if (overlay_node) {
++			cnt++;
++			of_node_put(overlay_node);
++		}
++	}
++
++	node = of_get_child_by_name(tree, "__symbols__");
++	if (node) {
+ 		cnt++;
++		of_node_put(node);
++	}
+ 
+ 	fragments = kcalloc(cnt, sizeof(*fragments), GFP_KERNEL);
+-	if (!fragments)
+-		return -ENOMEM;
++	if (!fragments) {
++		ret = -ENOMEM;
++		goto err_free_idr;
++	}
+ 
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node) {
+-		ret = of_fill_overlay_info(ovcs, node, &fragments[cnt]);
+-		if (!ret)
+-			cnt++;
++		fragment = &fragments[cnt];
++		fragment->overlay = of_get_child_by_name(node, "__overlay__");
++		if (fragment->overlay) {
++			fragment->target = find_target_node(node);
++			if (!fragment->target) {
++				of_node_put(fragment->overlay);
++				ret = -EINVAL;
++				goto err_free_fragments;
++			} else {
++				cnt++;
++			}
++		}
+ 	}
+ 
+ 	node = of_get_child_by_name(tree, "__symbols__");
+@@ -475,44 +468,51 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 
+ 		if (!fragment->target) {
+ 			pr_err("no symbols in root of device tree.\n");
+-			return -EINVAL;
++			ret = -EINVAL;
++			goto err_free_fragments;
+ 		}
+ 
+ 		cnt++;
+ 	}
+ 
+ 	if (!cnt) {
+-		kfree(fragments);
+-		return -ENODEV;
++		ret = -EINVAL;
++		goto err_free_fragments;
+ 	}
+ 
+ 	ovcs->count = cnt;
+ 	ovcs->fragments = fragments;
+ 
+ 	return 0;
++
++
++err_free_fragments:
++	kfree(fragments);
++err_free_idr:
++	idr_remove(&ovcs_idr, ovcs->id);
++
++	return ret;
+ }
+ 
+-/**
+- * free_overlay_fragments() - Free a fragments array
+- * @ovcs	Overlay to free the overlay info from
+- *
+- * Frees the memory of an ovcs->fragments[] array.
+- */
+-static void free_overlay_fragments(struct overlay_changeset *ovcs)
++static void free_overlay_changeset(struct overlay_changeset *ovcs)
+ {
+ 	int i;
+ 
+-	/* do it in reverse */
+-	for (i = ovcs->count - 1; i >= 0; i--) {
++	if (!ovcs->cset.entries.next)
++		return;
++	of_changeset_destroy(&ovcs->cset);
++
++	if (ovcs->id)
++		idr_remove(&ovcs_idr, ovcs->id);
++
++	for (i = 0; i < ovcs->count; i++) {
+ 		of_node_put(ovcs->fragments[i].target);
+ 		of_node_put(ovcs->fragments[i].overlay);
+ 	}
+-
+ 	kfree(ovcs->fragments);
+-}
+ 
+-static LIST_HEAD(ovcs_list);
+-static DEFINE_IDR(ovcs_idr);
++	kfree(ovcs);
++}
+ 
+ /**
+  * of_overlay_apply() - Create and apply an overlay changeset
+@@ -526,47 +526,34 @@ static DEFINE_IDR(ovcs_idr);
+ int of_overlay_apply(struct device_node *tree)
+ {
+ 	struct overlay_changeset *ovcs;
+-	int id, ret;
++	int ret;
+ 
+ 	ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
+ 	if (!ovcs)
+ 		return -ENOMEM;
+-	ovcs->id = -1;
+-
+-	INIT_LIST_HEAD(&ovcs->ovcs_list);
+-
+-	of_changeset_init(&ovcs->cset);
+ 
+ 	mutex_lock(&of_mutex);
+ 
+-	id = idr_alloc(&ovcs_idr, ovcs, 0, 0, GFP_KERNEL);
+-	if (id < 0) {
+-		ret = id;
+-		goto err_destroy_trans;
+-	}
+-	ovcs->id = id;
+-
+ 	ret = init_overlay_changeset(ovcs, tree);
+ 	if (ret) {
+-		pr_err("init_overlay_changeset() failed for tree@%pOF\n",
+-		       tree);
+-		goto err_free_idr;
++		pr_err("init_overlay_changeset() failed, ret = %d\n", ret);
++		goto err_free_overlay_changeset;
+ 	}
+ 
+ 	ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY);
+ 	if (ret < 0) {
+ 		pr_err("%s: Pre-apply notifier failed (ret=%d)\n",
+ 		       __func__, ret);
+-		goto err_free_overlay_fragments;
++		goto err_free_overlay_changeset;
+ 	}
+ 
+ 	ret = build_changeset(ovcs);
+ 	if (ret)
+-		goto err_free_overlay_fragments;
++		goto err_free_overlay_changeset;
+ 
+ 	ret = __of_changeset_apply(&ovcs->cset);
+ 	if (ret)
+-		goto err_free_overlay_fragments;
++		goto err_free_overlay_changeset;
+ 
+ 	list_add_tail(&ovcs->ovcs_list, &ovcs_list);
+ 
+@@ -574,15 +561,11 @@ int of_overlay_apply(struct device_node *tree)
+ 
+ 	mutex_unlock(&of_mutex);
+ 
+-	return id;
++	return ovcs->id;
++
++err_free_overlay_changeset:
++	free_overlay_changeset(ovcs);
+ 
+-err_free_overlay_fragments:
+-	free_overlay_fragments(ovcs);
+-err_free_idr:
+-	idr_remove(&ovcs_idr, ovcs->id);
+-err_destroy_trans:
+-	of_changeset_destroy(&ovcs->cset);
+-	kfree(ovcs);
+ 	mutex_unlock(&of_mutex);
+ 
+ 	return ret;
+@@ -693,13 +676,14 @@ int of_overlay_remove(int ovcs_id)
+ 	}
+ 
+ 	overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE);
++
+ 	list_del(&ovcs->ovcs_list);
++
+ 	__of_changeset_revert(&ovcs->cset);
++
+ 	overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
+-	free_overlay_fragments(ovcs);
+-	idr_remove(&ovcs_idr, ovcs_id);
+-	of_changeset_destroy(&ovcs->cset);
+-	kfree(ovcs);
++
++	free_overlay_changeset(ovcs);
+ 
+ out:
+ 	mutex_unlock(&of_mutex);
+@@ -718,20 +702,15 @@ EXPORT_SYMBOL_GPL(of_overlay_remove);
+ int of_overlay_remove_all(void)
+ {
+ 	struct overlay_changeset *ovcs, *ovcs_n;
+-
+-	mutex_lock(&of_mutex);
++	int ret;
+ 
+ 	/* the tail of list is guaranteed to be safe to remove */
+ 	list_for_each_entry_safe_reverse(ovcs, ovcs_n, &ovcs_list, ovcs_list) {
+-		list_del(&ovcs->ovcs_list);
+-		__of_changeset_revert(&ovcs->cset);
+-		free_overlay_fragments(ovcs);
+-		idr_remove(&ovcs_idr, ovcs->id);
+-		kfree(ovcs);
++		ret = of_overlay_remove(ovcs->id);
++		if (ret)
++			return ret;
+ 	}
+ 
+-	mutex_unlock(&of_mutex);
+-
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_remove_all);
+-- 
+2.19.0
+
diff --git a/patches/0910-of-overlay-detect-cases-where-device-tree-may-become.patch b/patches/0910-of-overlay-detect-cases-where-device-tree-may-become.patch
new file mode 100644
index 00000000000000..5f1b9871c9d62d
--- /dev/null
+++ b/patches/0910-of-overlay-detect-cases-where-device-tree-may-become.patch
@@ -0,0 +1,940 @@
+From 80ab2e974826121e978435e1f799b8f766e49a29 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:26 -0700
+Subject: [PATCH 0910/1795] of: overlay: detect cases where device tree may
+ become corrupt
+
+When an attempt to apply an overlay changeset fails, an effort
+is made to revert any partial application of the changeset.
+When an attempt to remove an overlay changeset fails, an effort
+is made to re-apply any partial reversion of the changeset.
+
+The existing code does not check for failure to recover a failed
+overlay changeset application or overlay changeset revert.
+
+Add the missing checks and flag the devicetree as corrupt if the
+state of the devicetree can not be determined.
+
+Improve and expand the returned errors to more fully reflect the
+result of the effort to undo the partial effects of a failed attempt
+to apply or remove an overlay changeset.
+
+If the device tree might be corrupt, do not allow further attempts
+to apply or remove an overlay changeset.
+
+When creating an overlay changeset from an overlay device tree,
+add some additional warnings if the state of the overlay device
+tree is not as expected.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 24789c5ce5a373dd55640f9cd79117fcc3ccc46d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c |   5 +-
+ drivers/of/dynamic.c                         | 135 ++++++++--
+ drivers/of/of_private.h                      |   8 +-
+ drivers/of/overlay.c                         | 253 ++++++++++++++++---
+ drivers/of/unittest.c                        |  57 +++--
+ include/linux/of.h                           |  10 +-
+ 6 files changed, 372 insertions(+), 96 deletions(-)
+
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+index 5f5b7ba35f1d..7a7be0515bfd 100644
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
++++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+@@ -204,7 +204,7 @@ static void __init tilcdc_convert_slave_node(void)
+ 	/* For all memory needed for the overlay tree. This memory can
+ 	   be freed after the overlay has been applied. */
+ 	struct kfree_table kft;
+-	int ret;
++	int ovcs_id, ret;
+ 
+ 	if (kfree_table_init(&kft))
+ 		return;
+@@ -247,7 +247,8 @@ static void __init tilcdc_convert_slave_node(void)
+ 
+ 	tilcdc_node_disable(slave);
+ 
+-	ret = of_overlay_apply(overlay);
++	ovcs_id = 0;
++	ret = of_overlay_apply(overlay, &ovcs_id);
+ 	if (ret)
+ 		pr_err("%s: Applying overlay changeset failed: %d\n",
+ 			__func__, ret);
+diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c
+index 124510d56421..c1026efd6f9e 100644
+--- a/drivers/of/dynamic.c
++++ b/drivers/of/dynamic.c
+@@ -508,11 +508,12 @@ static void __of_changeset_entry_invert(struct of_changeset_entry *ce,
+ 	}
+ }
+ 
+-static void __of_changeset_entry_notify(struct of_changeset_entry *ce, bool revert)
++static int __of_changeset_entry_notify(struct of_changeset_entry *ce,
++		bool revert)
+ {
+ 	struct of_reconfig_data rd;
+ 	struct of_changeset_entry ce_inverted;
+-	int ret;
++	int ret = 0;
+ 
+ 	if (revert) {
+ 		__of_changeset_entry_invert(ce, &ce_inverted);
+@@ -534,11 +535,12 @@ static void __of_changeset_entry_notify(struct of_changeset_entry *ce, bool reve
+ 	default:
+ 		pr_err("invalid devicetree changeset action: %i\n",
+ 			(int)ce->action);
+-		return;
++		ret = -EINVAL;
+ 	}
+ 
+ 	if (ret)
+ 		pr_err("changeset notifier error @%pOF\n", ce->np);
++	return ret;
+ }
+ 
+ static int __of_changeset_entry_apply(struct of_changeset_entry *ce)
+@@ -672,32 +674,82 @@ void of_changeset_destroy(struct of_changeset *ocs)
+ }
+ EXPORT_SYMBOL_GPL(of_changeset_destroy);
+ 
+-int __of_changeset_apply(struct of_changeset *ocs)
++/*
++ * Apply the changeset entries in @ocs.
++ * If apply fails, an attempt is made to revert the entries that were
++ * successfully applied.
++ *
++ * If multiple revert errors occur then only the final revert error is reported.
++ *
++ * Returns 0 on success, a negative error value in case of an error.
++ * If a revert error occurs, it is returned in *ret_revert.
++ */
++int __of_changeset_apply_entries(struct of_changeset *ocs, int *ret_revert)
+ {
+ 	struct of_changeset_entry *ce;
+-	int ret;
++	int ret, ret_tmp;
+ 
+-	/* perform the rest of the work */
+ 	pr_debug("changeset: applying...\n");
+ 	list_for_each_entry(ce, &ocs->entries, node) {
+ 		ret = __of_changeset_entry_apply(ce);
+ 		if (ret) {
+ 			pr_err("Error applying changeset (%d)\n", ret);
+-			list_for_each_entry_continue_reverse(ce, &ocs->entries, node)
+-				__of_changeset_entry_revert(ce);
++			list_for_each_entry_continue_reverse(ce, &ocs->entries,
++							     node) {
++				ret_tmp = __of_changeset_entry_revert(ce);
++				if (ret_tmp)
++					*ret_revert = ret_tmp;
++			}
+ 			return ret;
+ 		}
+ 	}
+-	pr_debug("changeset: applied, emitting notifiers.\n");
++
++	return 0;
++}
++
++/*
++ * Returns 0 on success, a negative error value in case of an error.
++ *
++ * If multiple changset entry notification errors occur then only the
++ * final notification error is reported.
++ */
++int __of_changeset_apply_notify(struct of_changeset *ocs)
++{
++	struct of_changeset_entry *ce;
++	int ret = 0, ret_tmp;
++
++	pr_debug("changeset: emitting notifiers.\n");
+ 
+ 	/* drop the global lock while emitting notifiers */
+ 	mutex_unlock(&of_mutex);
+-	list_for_each_entry(ce, &ocs->entries, node)
+-		__of_changeset_entry_notify(ce, 0);
++	list_for_each_entry(ce, &ocs->entries, node) {
++		ret_tmp = __of_changeset_entry_notify(ce, 0);
++		if (ret_tmp)
++			ret = ret_tmp;
++	}
+ 	mutex_lock(&of_mutex);
+ 	pr_debug("changeset: notifiers sent.\n");
+ 
+-	return 0;
++	return ret;
++}
++
++/*
++ * Returns 0 on success, a negative error value in case of an error.
++ *
++ * If a changeset entry apply fails, an attempt is made to revert any
++ * previous entries in the changeset.  If any of the reverts fails,
++ * that failure is not reported.  Thus the state of the device tree
++ * is unknown if an apply error occurs.
++ */
++static int __of_changeset_apply(struct of_changeset *ocs)
++{
++	int ret, ret_revert = 0;
++
++	ret = __of_changeset_apply_entries(ocs, &ret_revert);
++	if (!ret)
++		ret = __of_changeset_apply_notify(ocs);
++
++	return ret;
+ }
+ 
+ /**
+@@ -724,31 +776,74 @@ int of_changeset_apply(struct of_changeset *ocs)
+ }
+ EXPORT_SYMBOL_GPL(of_changeset_apply);
+ 
+-int __of_changeset_revert(struct of_changeset *ocs)
++/*
++ * Revert the changeset entries in @ocs.
++ * If revert fails, an attempt is made to re-apply the entries that were
++ * successfully removed.
++ *
++ * If multiple re-apply errors occur then only the final apply error is
++ * reported.
++ *
++ * Returns 0 on success, a negative error value in case of an error.
++ * If an apply error occurs, it is returned in *ret_apply.
++ */
++int __of_changeset_revert_entries(struct of_changeset *ocs, int *ret_apply)
+ {
+ 	struct of_changeset_entry *ce;
+-	int ret;
++	int ret, ret_tmp;
+ 
+ 	pr_debug("changeset: reverting...\n");
+ 	list_for_each_entry_reverse(ce, &ocs->entries, node) {
+ 		ret = __of_changeset_entry_revert(ce);
+ 		if (ret) {
+ 			pr_err("Error reverting changeset (%d)\n", ret);
+-			list_for_each_entry_continue(ce, &ocs->entries, node)
+-				__of_changeset_entry_apply(ce);
++			list_for_each_entry_continue(ce, &ocs->entries, node) {
++				ret_tmp = __of_changeset_entry_apply(ce);
++				if (ret_tmp)
++					*ret_apply = ret_tmp;
++			}
+ 			return ret;
+ 		}
+ 	}
+-	pr_debug("changeset: reverted, emitting notifiers.\n");
++
++	return 0;
++}
++
++/*
++ * If multiple changset entry notification errors occur then only the
++ * final notification error is reported.
++ */
++int __of_changeset_revert_notify(struct of_changeset *ocs)
++{
++	struct of_changeset_entry *ce;
++	int ret = 0, ret_tmp;
++
++	pr_debug("changeset: emitting notifiers.\n");
+ 
+ 	/* drop the global lock while emitting notifiers */
+ 	mutex_unlock(&of_mutex);
+-	list_for_each_entry_reverse(ce, &ocs->entries, node)
+-		__of_changeset_entry_notify(ce, 1);
++	list_for_each_entry_reverse(ce, &ocs->entries, node) {
++		ret_tmp = __of_changeset_entry_notify(ce, 1);
++		if (ret_tmp)
++			ret = ret_tmp;
++	}
+ 	mutex_lock(&of_mutex);
+ 	pr_debug("changeset: notifiers sent.\n");
+ 
+-	return 0;
++	return ret;
++}
++
++static int __of_changeset_revert(struct of_changeset *ocs)
++{
++	int ret, ret_reply;
++
++	ret_reply = 0;
++	ret = __of_changeset_revert_entries(ocs, &ret_reply);
++
++	if (!ret)
++		ret = __of_changeset_revert_notify(ocs);
++
++	return ret;
+ }
+ 
+ /**
+diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
+index 3ae12ffbf547..b66e8a812147 100644
+--- a/drivers/of/of_private.h
++++ b/drivers/of/of_private.h
+@@ -45,8 +45,12 @@ static inline struct device_node *kobj_to_device_node(struct kobject *kobj)
+ extern int of_property_notify(int action, struct device_node *np,
+ 			      struct property *prop, struct property *old_prop);
+ extern void of_node_release(struct kobject *kobj);
+-extern int __of_changeset_apply(struct of_changeset *ocs);
+-extern int __of_changeset_revert(struct of_changeset *ocs);
++extern int __of_changeset_apply_entries(struct of_changeset *ocs,
++					int *ret_revert);
++extern int __of_changeset_apply_notify(struct of_changeset *ocs);
++extern int __of_changeset_revert_entries(struct of_changeset *ocs,
++					 int *ret_apply);
++extern int __of_changeset_revert_notify(struct of_changeset *ocs);
+ #else /* CONFIG_OF_DYNAMIC */
+ static inline int of_property_notify(int action, struct device_node *np,
+ 				     struct property *prop, struct property *old_prop)
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 905916e17eec..78c50fd57750 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -50,6 +50,22 @@ struct overlay_changeset {
+ 	struct of_changeset cset;
+ };
+ 
++/* flags are sticky - once set, do not reset */
++static int devicetree_state_flags;
++#define DTSF_APPLY_FAIL		0x01
++#define DTSF_REVERT_FAIL	0x02
++
++/*
++ * If a changeset apply or revert encounters an error, an attempt will
++ * be made to undo partial changes, but may fail.  If the undo fails
++ * we do not know the state of the devicetree.
++ */
++static int devicetree_corrupt(void)
++{
++	return devicetree_state_flags &
++		(DTSF_APPLY_FAIL | DTSF_REVERT_FAIL);
++}
++
+ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		struct device_node *target_node,
+ 		const struct device_node *overlay_node,
+@@ -72,6 +88,13 @@ int of_overlay_notifier_unregister(struct notifier_block *nb)
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_notifier_unregister);
+ 
++static char *of_overlay_action_name[] = {
++	"pre-apply",
++	"post-apply",
++	"pre-remove",
++	"post-remove",
++};
++
+ static int overlay_notify(struct overlay_changeset *ovcs,
+ 		enum of_overlay_notify_action action)
+ {
+@@ -86,8 +109,14 @@ static int overlay_notify(struct overlay_changeset *ovcs,
+ 
+ 		ret = blocking_notifier_call_chain(&overlay_notify_chain,
+ 						   action, &nd);
+-		if (ret)
+-			return notifier_to_errno(ret);
++		if (ret == NOTIFY_STOP)
++			return 0;
++		if (ret) {
++			ret = notifier_to_errno(ret);
++			pr_err("overlay changeset %s notifier error %d, target: %pOF\n",
++			       of_overlay_action_name[action], ret, nd.target);
++			return ret;
++		}
+ 	}
+ 
+ 	return 0;
+@@ -240,6 +269,14 @@ static int add_changeset_property(struct overlay_changeset *ovcs,
+  * build_changeset_next_level().
+  *
+  * NOTE: Multiple mods of created nodes not supported.
++ *       If more than one fragment contains a node that does not already exist
++ *       in the live tree, then for each fragment of_changeset_attach_node()
++ *       will add a changeset entry to add the node.  When the changeset is
++ *       applied, __of_attach_node() will attach the node twice (once for
++ *       each fragment).  At this point the device tree will be corrupted.
++ *
++ *       TODO: add integrity check to ensure that multiple fragments do not
++ *             create the same node.
+  *
+  * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
+  * invalid @overlay.
+@@ -312,8 +349,8 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		ret = add_changeset_property(ovcs, target_node, prop,
+ 					     is_symbols_node);
+ 		if (ret) {
+-			pr_err("Failed to apply prop @%pOF/%s\n",
+-			       target_node, prop->name);
++			pr_debug("Failed to apply prop @%pOF/%s, err=%d\n",
++				 target_node, prop->name, ret);
+ 			return ret;
+ 		}
+ 	}
+@@ -324,8 +361,8 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 	for_each_child_of_node(overlay_node, child) {
+ 		ret = add_changeset_node(ovcs, target_node, child);
+ 		if (ret) {
+-			pr_err("Failed to apply node @%pOF/%s\n",
+-			       target_node, child->name);
++			pr_debug("Failed to apply node @%pOF/%s, err=%d\n",
++				 target_node, child->name, ret);
+ 			of_node_put(child);
+ 			return ret;
+ 		}
+@@ -357,7 +394,7 @@ static int build_changeset(struct overlay_changeset *ovcs)
+ 					       fragment->overlay,
+ 					       fragment->is_symbols_node);
+ 		if (ret) {
+-			pr_err("apply failed '%pOF'\n", fragment->target);
++			pr_debug("apply failed '%pOF'\n", fragment->target);
+ 			return ret;
+ 		}
+ 	}
+@@ -412,6 +449,19 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 	struct fragment *fragments;
+ 	int cnt, ret;
+ 
++	/*
++	 * Warn for some issues.  Can not return -EINVAL for these until
++	 * of_unittest_apply_overlay() is fixed to pass these checks.
++	 */
++	if (!of_node_check_flag(tree, OF_DYNAMIC))
++		pr_debug("%s() tree is not dynamic\n", __func__);
++
++	if (!of_node_check_flag(tree, OF_DETACHED))
++		pr_debug("%s() tree is not detached\n", __func__);
++
++	if (!of_node_is_root(tree))
++		pr_debug("%s() tree is not root\n", __func__);
++
+ 	INIT_LIST_HEAD(&ovcs->ovcs_list);
+ 
+ 	of_changeset_init(&ovcs->cset);
+@@ -485,12 +535,13 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 
+ 	return 0;
+ 
+-
+ err_free_fragments:
+ 	kfree(fragments);
+ err_free_idr:
+ 	idr_remove(&ovcs_idr, ovcs->id);
+ 
++	pr_err("%s() failed, ret = %d\n", __func__, ret);
++
+ 	return ret;
+ }
+ 
+@@ -517,33 +568,71 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+ /**
+  * of_overlay_apply() - Create and apply an overlay changeset
+  * @tree:	Expanded overlay device tree
++ * @ovcs_id:	Pointer to overlay changeset id
++ *
++ * Creates and applies an overlay changeset.
+  *
+- * Creates and applies an overlay changeset.  If successful, the overlay
+- * changeset is added to the overlay changeset list.
++ * If an error occurs in a pre-apply notifier, then no changes are made
++ * to the device tree.
+  *
+- * Returns the id of the created overlay changeset, or a negative error number
++
++ * A non-zero return value will not have created the changeset if error is from:
++ *   - parameter checks
++ *   - building the changeset
++ *   - overlay changset pre-apply notifier
++ *
++ * If an error is returned by an overlay changeset pre-apply notifier
++ * then no further overlay changeset pre-apply notifier will be called.
++ *
++ * A non-zero return value will have created the changeset if error is from:
++ *   - overlay changeset entry notifier
++ *   - overlay changset post-apply notifier
++ *
++ * If an error is returned by an overlay changeset post-apply notifier
++ * then no further overlay changeset post-apply notifier will be called.
++ *
++ * If more than one notifier returns an error, then the last notifier
++ * error to occur is returned.
++ *
++ * If an error occurred while applying the overlay changeset, then an
++ * attempt is made to revert any changes that were made to the
++ * device tree.  If there were any errors during the revert attempt
++ * then the state of the device tree can not be determined, and any
++ * following attempt to apply or remove an overlay changeset will be
++ * refused.
++ *
++ * Returns 0 on success, or a negative error number.  Overlay changeset
++ * id is returned to *ovcs_id.
+  */
+-int of_overlay_apply(struct device_node *tree)
++
++int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ {
+ 	struct overlay_changeset *ovcs;
+-	int ret;
++	int ret = 0, ret_revert, ret_tmp;
++
++	*ovcs_id = 0;
++
++	if (devicetree_corrupt()) {
++		pr_err("devicetree state suspect, refuse to apply overlay\n");
++		ret = -EBUSY;
++		goto out;
++	}
+ 
+ 	ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
+-	if (!ovcs)
+-		return -ENOMEM;
++	if (!ovcs) {
++		ret = -ENOMEM;
++		goto out;
++	}
+ 
+ 	mutex_lock(&of_mutex);
+ 
+ 	ret = init_overlay_changeset(ovcs, tree);
+-	if (ret) {
+-		pr_err("init_overlay_changeset() failed, ret = %d\n", ret);
++	if (ret)
+ 		goto err_free_overlay_changeset;
+-	}
+ 
+ 	ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY);
+-	if (ret < 0) {
+-		pr_err("%s: Pre-apply notifier failed (ret=%d)\n",
+-		       __func__, ret);
++	if (ret) {
++		pr_err("overlay changeset pre-apply notify error %d\n", ret);
+ 		goto err_free_overlay_changeset;
+ 	}
+ 
+@@ -551,23 +640,46 @@ int of_overlay_apply(struct device_node *tree)
+ 	if (ret)
+ 		goto err_free_overlay_changeset;
+ 
+-	ret = __of_changeset_apply(&ovcs->cset);
+-	if (ret)
++	ret_revert = 0;
++	ret = __of_changeset_apply_entries(&ovcs->cset, &ret_revert);
++	if (ret) {
++		if (ret_revert) {
++			pr_debug("overlay changeset revert error %d\n",
++				 ret_revert);
++			devicetree_state_flags |= DTSF_APPLY_FAIL;
++		}
+ 		goto err_free_overlay_changeset;
++	} else {
++		ret = __of_changeset_apply_notify(&ovcs->cset);
++		if (ret)
++			pr_err("overlay changeset entry notify error %d\n",
++			       ret);
++		/* fall through */
++	}
+ 
+ 	list_add_tail(&ovcs->ovcs_list, &ovcs_list);
+-
+-	overlay_notify(ovcs, OF_OVERLAY_POST_APPLY);
++	*ovcs_id = ovcs->id;
++
++	ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_APPLY);
++	if (ret_tmp) {
++		pr_err("overlay changeset post-apply notify error %d\n",
++		       ret_tmp);
++		if (!ret)
++			ret = ret_tmp;
++	}
+ 
+ 	mutex_unlock(&of_mutex);
+ 
+-	return ovcs->id;
++	goto out;
+ 
+ err_free_overlay_changeset:
+ 	free_overlay_changeset(ovcs);
+ 
+ 	mutex_unlock(&of_mutex);
+ 
++out:
++	pr_debug("%s() err=%d\n", __func__, ret);
++
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_apply);
+@@ -649,45 +761,106 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+ 
+ /**
+  * of_overlay_remove() - Revert and free an overlay changeset
+- * @ovcs_id:	Overlay changeset id number
++ * @ovcs_id:	Pointer to overlay changeset id
+  *
+- * Removes an overlay if it is permissible.  ovcs_id was previously returned
++ * Removes an overlay if it is permissible.  @ovcs_id was previously returned
+  * by of_overlay_apply().
+  *
+- * Returns 0 on success, or a negative error number
++ * If an error occurred while attempting to revert the overlay changeset,
++ * then an attempt is made to re-apply any changeset entry that was
++ * reverted.  If an error occurs on re-apply then the state of the device
++ * tree can not be determined, and any following attempt to apply or remove
++ * an overlay changeset will be refused.
++ *
++ * A non-zero return value will not revert the changeset if error is from:
++ *   - parameter checks
++ *   - overlay changset pre-remove notifier
++ *   - overlay changeset entry revert
++ *
++ * If an error is returned by an overlay changeset pre-remove notifier
++ * then no further overlay changeset pre-remove notifier will be called.
++ *
++ * If more than one notifier returns an error, then the last notifier
++ * error to occur is returned.
++ *
++ * A non-zero return value will revert the changeset if error is from:
++ *   - overlay changeset entry notifier
++ *   - overlay changset post-remove notifier
++ *
++ * If an error is returned by an overlay changeset post-remove notifier
++ * then no further overlay changeset post-remove notifier will be called.
++ *
++ * Returns 0 on success, or a negative error number.  *ovcs_id is set to
++ * zero after reverting the changeset, even if a subsequent error occurs.
+  */
+-int of_overlay_remove(int ovcs_id)
++int of_overlay_remove(int *ovcs_id)
+ {
+ 	struct overlay_changeset *ovcs;
+-	int ret = 0;
++	int ret, ret_apply, ret_tmp;
++
++	ret = 0;
++
++	if (devicetree_corrupt()) {
++		pr_err("suspect devicetree state, refuse to remove overlay\n");
++		ret = -EBUSY;
++		goto out;
++	}
+ 
+ 	mutex_lock(&of_mutex);
+ 
+-	ovcs = idr_find(&ovcs_idr, ovcs_id);
++	ovcs = idr_find(&ovcs_idr, *ovcs_id);
+ 	if (!ovcs) {
+ 		ret = -ENODEV;
+-		pr_err("remove: Could not find overlay #%d\n", ovcs_id);
+-		goto out;
++		pr_err("remove: Could not find overlay #%d\n", *ovcs_id);
++		goto out_unlock;
+ 	}
+ 
+ 	if (!overlay_removal_is_ok(ovcs)) {
+ 		ret = -EBUSY;
+-		goto out;
++		goto out_unlock;
+ 	}
+ 
+-	overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE);
++	ret = overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE);
++	if (ret) {
++		pr_err("overlay changeset pre-remove notify error %d\n", ret);
++		goto out_unlock;
++	}
+ 
+ 	list_del(&ovcs->ovcs_list);
+ 
+-	__of_changeset_revert(&ovcs->cset);
++	ret_apply = 0;
++	ret = __of_changeset_revert_entries(&ovcs->cset, &ret_apply);
++	if (ret) {
++		if (ret_apply)
++			devicetree_state_flags |= DTSF_REVERT_FAIL;
++		goto out_unlock;
++	} else {
++		ret = __of_changeset_revert_notify(&ovcs->cset);
++		if (ret) {
++			pr_err("overlay changeset entry notify error %d\n",
++			       ret);
++			/* fall through - changeset was reverted */
++		}
++	}
+ 
+-	overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
++	*ovcs_id = 0;
++
++	ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
++	if (ret_tmp) {
++		pr_err("overlay changeset post-remove notify error %d\n",
++		       ret_tmp);
++		if (!ret)
++			ret = ret_tmp;
++	}
+ 
+ 	free_overlay_changeset(ovcs);
+ 
+-out:
++out_unlock:
+ 	mutex_unlock(&of_mutex);
+ 
++out:
++	pr_debug("%s() err=%d\n", __func__, ret);
++
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_remove);
+@@ -706,7 +879,7 @@ int of_overlay_remove_all(void)
+ 
+ 	/* the tail of list is guaranteed to be safe to remove */
+ 	list_for_each_entry_safe_reverse(ovcs, ovcs_n, &ovcs_list, ovcs_list) {
+-		ret = of_overlay_remove(ovcs->id);
++		ret = of_overlay_remove(&ovcs->id);
+ 		if (ret)
+ 			return ret;
+ 	}
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index 2a557bfd0a2c..c958cc66e8ea 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -1218,7 +1218,7 @@ static void of_unittest_untrack_overlay(int id)
+ 
+ static void of_unittest_destroy_tracked_overlays(void)
+ {
+-	int id, ret, defers;
++	int id, ret, defers, ovcs_id;
+ 
+ 	if (overlay_first_id < 0)
+ 		return;
+@@ -1231,7 +1231,8 @@ static void of_unittest_destroy_tracked_overlays(void)
+ 			if (!(overlay_id_bits[BIT_WORD(id)] & BIT_MASK(id)))
+ 				continue;
+ 
+-			ret = of_overlay_remove(id + overlay_first_id);
++			ovcs_id = id + overlay_first_id;
++			ret = of_overlay_remove(&ovcs_id);
+ 			if (ret == -ENODEV) {
+ 				pr_warn("%s: no overlay to destroy for #%d\n",
+ 					__func__, id + overlay_first_id);
+@@ -1253,7 +1254,7 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ 		int *overlay_id)
+ {
+ 	struct device_node *np = NULL;
+-	int ret, id = -1;
++	int ret;
+ 
+ 	np = of_find_node_by_path(overlay_path(overlay_nr));
+ 	if (np == NULL) {
+@@ -1263,23 +1264,20 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ 		goto out;
+ 	}
+ 
+-	ret = of_overlay_apply(np);
++	*overlay_id = 0;
++	ret = of_overlay_apply(np, overlay_id);
+ 	if (ret < 0) {
+ 		unittest(0, "could not create overlay from \"%s\"\n",
+ 				overlay_path(overlay_nr));
+ 		goto out;
+ 	}
+-	id = ret;
+-	of_unittest_track_overlay(id);
++	of_unittest_track_overlay(*overlay_id);
+ 
+ 	ret = 0;
+ 
+ out:
+ 	of_node_put(np);
+ 
+-	if (overlay_id)
+-		*overlay_id = id;
+-
+ 	return ret;
+ }
+ 
+@@ -1287,7 +1285,7 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr,
+ 		int before, int after, enum overlay_type ovtype)
+ {
+-	int ret;
++	int ret, ovcs_id;
+ 
+ 	/* unittest device must not be in before state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != before) {
+@@ -1298,7 +1296,8 @@ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr,
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = of_unittest_apply_overlay(overlay_nr, unittest_nr, NULL);
++	ovcs_id = 0;
++	ret = of_unittest_apply_overlay(overlay_nr, unittest_nr, &ovcs_id);
+ 	if (ret != 0) {
+ 		/* of_unittest_apply_overlay already called unittest() */
+ 		return ret;
+@@ -1321,7 +1320,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 		int unittest_nr, int before, int after,
+ 		enum overlay_type ovtype)
+ {
+-	int ret, ov_id;
++	int ret, ovcs_id;
+ 
+ 	/* unittest device must be in before state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != before) {
+@@ -1333,7 +1332,8 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 	}
+ 
+ 	/* apply the overlay */
+-	ret = of_unittest_apply_overlay(overlay_nr, unittest_nr, &ov_id);
++	ovcs_id = 0;
++	ret = of_unittest_apply_overlay(overlay_nr, unittest_nr, &ovcs_id);
+ 	if (ret != 0) {
+ 		/* of_unittest_apply_overlay already called unittest() */
+ 		return ret;
+@@ -1348,7 +1348,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = of_overlay_remove(ov_id);
++	ret = of_overlay_remove(&ovcs_id);
+ 	if (ret != 0) {
+ 		unittest(0, "overlay @\"%s\" failed to be destroyed @\"%s\"\n",
+ 				overlay_path(overlay_nr),
+@@ -1450,7 +1450,7 @@ static void of_unittest_overlay_5(void)
+ static void of_unittest_overlay_6(void)
+ {
+ 	struct device_node *np;
+-	int ret, i, ov_id[2];
++	int ret, i, ov_id[2], ovcs_id;
+ 	int overlay_nr = 6, unittest_nr = 6;
+ 	int before = 0, after = 1;
+ 
+@@ -1477,13 +1477,14 @@ static void of_unittest_overlay_6(void)
+ 			return;
+ 		}
+ 
+-		ret = of_overlay_apply(np);
++		ovcs_id = 0;
++		ret = of_overlay_apply(np, &ovcs_id);
+ 		if (ret < 0)  {
+ 			unittest(0, "could not create overlay from \"%s\"\n",
+ 					overlay_path(overlay_nr + i));
+ 			return;
+ 		}
+-		ov_id[i] = ret;
++		ov_id[i] = ovcs_id;
+ 		of_unittest_track_overlay(ov_id[i]);
+ 	}
+ 
+@@ -1501,7 +1502,8 @@ static void of_unittest_overlay_6(void)
+ 	}
+ 
+ 	for (i = 1; i >= 0; i--) {
+-		ret = of_overlay_remove(ov_id[i]);
++		ovcs_id = ov_id[i];
++		ret = of_overlay_remove(&ovcs_id);
+ 		if (ret != 0) {
+ 			unittest(0, "overlay @\"%s\" failed destroy @\"%s\"\n",
+ 					overlay_path(overlay_nr + i),
+@@ -1532,7 +1534,7 @@ static void of_unittest_overlay_6(void)
+ static void of_unittest_overlay_8(void)
+ {
+ 	struct device_node *np;
+-	int ret, i, ov_id[2];
++	int ret, i, ov_id[2], ovcs_id;
+ 	int overlay_nr = 8, unittest_nr = 8;
+ 
+ 	/* we don't care about device state in this test */
+@@ -1547,18 +1549,20 @@ static void of_unittest_overlay_8(void)
+ 			return;
+ 		}
+ 
+-		ret = of_overlay_apply(np);
++		ovcs_id = 0;
++		ret = of_overlay_apply(np, &ovcs_id);
+ 		if (ret < 0)  {
+ 			unittest(0, "could not create overlay from \"%s\"\n",
+ 					overlay_path(overlay_nr + i));
+ 			return;
+ 		}
+-		ov_id[i] = ret;
++		ov_id[i] = ovcs_id;
+ 		of_unittest_track_overlay(ov_id[i]);
+ 	}
+ 
+ 	/* now try to remove first overlay (it should fail) */
+-	ret = of_overlay_remove(ov_id[0]);
++	ovcs_id = ov_id[0];
++	ret = of_overlay_remove(&ovcs_id);
+ 	if (ret == 0) {
+ 		unittest(0, "overlay @\"%s\" was destroyed @\"%s\"\n",
+ 				overlay_path(overlay_nr + 0),
+@@ -1569,7 +1573,8 @@ static void of_unittest_overlay_8(void)
+ 
+ 	/* removing them in order should work */
+ 	for (i = 1; i >= 0; i--) {
+-		ret = of_overlay_remove(ov_id[i]);
++		ovcs_id = ov_id[i];
++		ret = of_overlay_remove(&ovcs_id);
+ 		if (ret != 0) {
+ 			unittest(0, "overlay @\"%s\" not destroyed @\"%s\"\n",
+ 					overlay_path(overlay_nr + i),
+@@ -2150,13 +2155,11 @@ static int __init overlay_data_add(int onum)
+ 		goto out_free_np_overlay;
+ 	}
+ 
+-	ret = of_overlay_apply(info->np_overlay);
++	info->overlay_id = 0;
++	ret = of_overlay_apply(info->np_overlay, &info->overlay_id);
+ 	if (ret < 0) {
+ 		pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum);
+ 		goto out_free_np_overlay;
+-	} else {
+-		info->overlay_id = ret;
+-		ret = 0;
+ 	}
+ 
+ 	pr_debug("__dtb_overlay_begin applied, overlay id %d\n", ret);
+diff --git a/include/linux/of.h b/include/linux/of.h
+index 211be870600e..e9eeefa3eb6f 100644
+--- a/include/linux/of.h
++++ b/include/linux/of.h
+@@ -1302,7 +1302,7 @@ static inline bool of_device_is_system_power_controller(const struct device_node
+  */
+ 
+ enum of_overlay_notify_action {
+-	OF_OVERLAY_PRE_APPLY,
++	OF_OVERLAY_PRE_APPLY = 0,
+ 	OF_OVERLAY_POST_APPLY,
+ 	OF_OVERLAY_PRE_REMOVE,
+ 	OF_OVERLAY_POST_REMOVE,
+@@ -1316,8 +1316,8 @@ struct of_overlay_notify_data {
+ #ifdef CONFIG_OF_OVERLAY
+ 
+ /* ID based overlays; the API for external users */
+-int of_overlay_apply(struct device_node *tree);
+-int of_overlay_remove(int id);
++int of_overlay_apply(struct device_node *tree, int *ovcs_id);
++int of_overlay_remove(int *ovcs_id);
+ int of_overlay_remove_all(void);
+ 
+ int of_overlay_notifier_register(struct notifier_block *nb);
+@@ -1325,12 +1325,12 @@ int of_overlay_notifier_unregister(struct notifier_block *nb);
+ 
+ #else
+ 
+-static inline int of_overlay_apply(struct device_node *tree)
++static inline int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ {
+ 	return -ENOTSUPP;
+ }
+ 
+-static inline int of_overlay_remove(int id)
++static inline int of_overlay_remove(int *ovcs_id)
+ {
+ 	return -ENOTSUPP;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0911-of-overlay-expand-check-of-whether-overlay-changeset.patch b/patches/0911-of-overlay-expand-check-of-whether-overlay-changeset.patch
new file mode 100644
index 00000000000000..a7fb13143e56ce
--- /dev/null
+++ b/patches/0911-of-overlay-expand-check-of-whether-overlay-changeset.patch
@@ -0,0 +1,80 @@
+From 58b093f19525003537def5f9a677f5e2dcaf157e Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:27 -0700
+Subject: [PATCH 0911/1795] of: overlay: expand check of whether overlay
+ changeset can be removed
+
+The test of whether it is safe to remove an overlay changeset
+looked at whether any node in the overlay changeset was in a
+subtree rooted at any more recently applied overlay changeset
+node.
+
+The test failed to determine whether any node in the overlay
+changeset was the root of a subtree that contained a more
+recently applied overlay changeset node.  Add this additional
+check to the test.
+
+The test is still lacking any check for any phandle dependencies.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 87f242c119c403e8b948c8b95eca4ab6212fd1a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 78c50fd57750..4cdee169a5ab 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -707,13 +707,13 @@ static int find_node(struct device_node *tree, struct device_node *np)
+ }
+ 
+ /*
+- * Is @remove_ce_np a child of or the same as any
++ * Is @remove_ce_node a child of, a parent of, or the same as any
+  * node in an overlay changeset more topmost than @remove_ovcs?
+  *
+  * Returns 1 if found, else 0
+  */
+-static int node_in_later_cs(struct overlay_changeset *remove_ovcs,
+-		struct device_node *remove_ce_np)
++static int node_overlaps_later_cs(struct overlay_changeset *remove_ovcs,
++		struct device_node *remove_ce_node)
+ {
+ 	struct overlay_changeset *ovcs;
+ 	struct of_changeset_entry *ce;
+@@ -723,10 +723,16 @@ static int node_in_later_cs(struct overlay_changeset *remove_ovcs,
+ 			break;
+ 
+ 		list_for_each_entry(ce, &ovcs->cset.entries, node) {
+-			if (find_node(ce->np, remove_ce_np)) {
+-				pr_err("%s: #%d clashes #%d @%pOF\n",
++			if (find_node(ce->np, remove_ce_node)) {
++				pr_err("%s: #%d overlaps with #%d @%pOF\n",
+ 					__func__, remove_ovcs->id, ovcs->id,
+-					remove_ce_np);
++					remove_ce_node);
++				return 1;
++			}
++			if (find_node(remove_ce_node, ce->np)) {
++				pr_err("%s: #%d overlaps with #%d @%pOF\n",
++					__func__, remove_ovcs->id, ovcs->id,
++					remove_ce_node);
+ 				return 1;
+ 			}
+ 		}
+@@ -750,7 +756,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+ 	struct of_changeset_entry *remove_ce;
+ 
+ 	list_for_each_entry(remove_ce, &remove_ovcs->cset.entries, node) {
+-		if (node_in_later_cs(remove_ovcs, remove_ce->np)) {
++		if (node_overlaps_later_cs(remove_ovcs, remove_ce->np)) {
+ 			pr_err("overlay #%d is not topmost\n", remove_ovcs->id);
+ 			return 0;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/0912-of-overlay-loosen-overly-strict-phandle-clash-check.patch b/patches/0912-of-overlay-loosen-overly-strict-phandle-clash-check.patch
new file mode 100644
index 00000000000000..2cacd8ff98bc1f
--- /dev/null
+++ b/patches/0912-of-overlay-loosen-overly-strict-phandle-clash-check.patch
@@ -0,0 +1,47 @@
+From 502ec093a22609685ba892a8e1e76319f2d97940 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:28 -0700
+Subject: [PATCH 0912/1795] of: overlay: loosen overly strict phandle clash
+ check
+
+When an overlay contains a node that already exists in
+the live device tree, the overlay node is not allowed
+to change the phandle of the existing node.
+
+The existing check refused to allow an overlay node to
+set the node phandle even when the existing node did
+not have a phandle.  Relax the check to allow an
+overlay node to set the phandle value if the existing
+node does not have a phandle.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 6d0f5470dbdeb7f9b1e20fc9409bf07fab1b5ac5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 4cdee169a5ab..791753321ed2 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -311,10 +311,10 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+ 		return build_changeset_next_level(ovcs, tchild, node, 0);
+ 	}
+ 
+-	if (node->phandle)
+-		return -EINVAL;
+-
+-	ret = build_changeset_next_level(ovcs, tchild, node, 0);
++	if (node->phandle && tchild->phandle)
++		ret = -EINVAL;
++	else
++		ret = build_changeset_next_level(ovcs, tchild, node, 0);
+ 	of_node_put(tchild);
+ 
+ 	return ret;
+-- 
+2.19.0
+
diff --git a/patches/0913-of-overlay-avoid-race-condition-between-applying-mul.patch b/patches/0913-of-overlay-avoid-race-condition-between-applying-mul.patch
new file mode 100644
index 00000000000000..20d07203e2370d
--- /dev/null
+++ b/patches/0913-of-overlay-avoid-race-condition-between-applying-mul.patch
@@ -0,0 +1,262 @@
+From c08bae56497ffa8f525b97eb4d7fef48579f7d1f Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:29 -0700
+Subject: [PATCH 0913/1795] of: overlay: avoid race condition between applying
+ multiple overlays
+
+The process of applying an overlay consists of:
+  - unflatten an overlay FDT (flattened device tree) into an
+    EDT (expanded device tree)
+  - fixup the phandle values in the overlay EDT to fit in a
+    range above the phandle values in the live device tree
+  - create the overlay changeset to reflect the contents of
+    the overlay EDT
+  - apply the overlay changeset, to modify the live device tree,
+    potentially changing the maximum phandle value in the live
+    device tree
+
+There is currently no protection against two overlay applies
+concurrently determining what range of phandle values are in use
+in the live device tree, and subsequently changing that range.
+Add a mutex to prevent multiple overlay applies from occurring
+simultaneously.
+
+Move of_resolve_phandles() into of_overlay_apply() so that it does not
+have to be duplicated by each caller of of_overlay_apply().
+
+The test in of_resolve_phandles() that the overlay tree is detached is
+temporarily disabled so that old style overlay unittests do not fail.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit f948d6d8b792bb90041edc12eac35faf83030994)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/of/of_private.h
+---
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c |  6 ----
+ drivers/of/of_private.h                      | 12 ++++++++
+ drivers/of/overlay.c                         | 32 ++++++++++++++++++++
+ drivers/of/resolver.c                        |  7 +++++
+ drivers/of/unittest.c                        | 22 ++++++++++----
+ include/linux/of.h                           |  3 --
+ 6 files changed, 67 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+index 7a7be0515bfd..54025af534d4 100644
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
++++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+@@ -145,7 +145,6 @@ static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
+ 		__dtb_tilcdc_slave_compat_begin;
+ 	static void *overlay_data;
+ 	struct device_node *overlay;
+-	int ret;
+ 
+ 	if (!size) {
+ 		pr_warn("%s: No overlay data\n", __func__);
+@@ -164,11 +163,6 @@ static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
+ 	}
+ 
+ 	of_node_set_flag(overlay, OF_DETACHED);
+-	ret = of_resolve_phandles(overlay);
+-	if (ret) {
+-		pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret);
+-		return NULL;
+-	}
+ 
+ 	return overlay;
+ }
+diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
+index b66e8a812147..03772bdbd94b 100644
+--- a/drivers/of/of_private.h
++++ b/drivers/of/of_private.h
+@@ -59,6 +59,18 @@ static inline int of_property_notify(int action, struct device_node *np,
+ }
+ #endif /* CONFIG_OF_DYNAMIC */
+ 
++#if defined(CONFIG_OF_RESOLVE)
++int of_resolve_phandles(struct device_node *tree);
++#endif
++
++#if defined(CONFIG_OF_OVERLAY)
++void of_overlay_mutex_lock(void);
++void of_overlay_mutex_unlock(void);
++#else
++static inline void of_overlay_mutex_lock(void) {};
++static inline void of_overlay_mutex_unlock(void) {};
++#endif
++
+ #if defined(CONFIG_OF_UNITTEST) && defined(CONFIG_OF_OVERLAY)
+ extern void __init unittest_unflatten_overlay_base(void);
+ #else
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 791753321ed2..d164f86e5541 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -71,6 +71,28 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		const struct device_node *overlay_node,
+ 		bool is_symbols_node);
+ 
++/*
++ * of_resolve_phandles() finds the largest phandle in the live tree.
++ * of_overlay_apply() may add a larger phandle to the live tree.
++ * Do not allow race between two overlays being applied simultaneously:
++ *    mutex_lock(&of_overlay_phandle_mutex)
++ *    of_resolve_phandles()
++ *    of_overlay_apply()
++ *    mutex_unlock(&of_overlay_phandle_mutex)
++ */
++static DEFINE_MUTEX(of_overlay_phandle_mutex);
++
++void of_overlay_mutex_lock(void)
++{
++	mutex_lock(&of_overlay_phandle_mutex);
++}
++
++void of_overlay_mutex_unlock(void)
++{
++	mutex_unlock(&of_overlay_phandle_mutex);
++}
++
++
+ static LIST_HEAD(ovcs_list);
+ static DEFINE_IDR(ovcs_idr);
+ 
+@@ -624,6 +646,12 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 		goto out;
+ 	}
+ 
++	of_overlay_mutex_lock();
++
++	ret = of_resolve_phandles(tree);
++	if (ret)
++		goto err_overlay_unlock;
++
+ 	mutex_lock(&of_mutex);
+ 
+ 	ret = init_overlay_changeset(ovcs, tree);
+@@ -669,9 +697,13 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 	}
+ 
+ 	mutex_unlock(&of_mutex);
++	of_overlay_mutex_unlock();
+ 
+ 	goto out;
+ 
++err_overlay_unlock:
++	of_overlay_mutex_unlock();
++
+ err_free_overlay_changeset:
+ 	free_overlay_changeset(ovcs);
+ 
+diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
+index 3bf4b6489fd0..f69fd3911160 100644
+--- a/drivers/of/resolver.c
++++ b/drivers/of/resolver.c
+@@ -280,11 +280,18 @@ int of_resolve_phandles(struct device_node *overlay)
+ 		err = -EINVAL;
+ 		goto out;
+ 	}
++
++#if 0
++	Temporarily disable check so that old style overlay unittests
++	do not fail when of_resolve_phandles() is moved into
++	of_overlay_apply().
++
+ 	if (!of_node_check_flag(overlay, OF_DETACHED)) {
+ 		pr_err("overlay not detached\n");
+ 		err = -EINVAL;
+ 		goto out;
+ 	}
++#endif
+ 
+ 	phandle_delta = live_tree_max_phandle() + 1;
+ 	adjust_overlay_phandles(overlay, phandle_delta);
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index c958cc66e8ea..842097fe4064 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -994,9 +994,17 @@ static int __init unittest_data_add(void)
+ 		pr_warn("%s: No tree to attach; not running tests\n", __func__);
+ 		return -ENODATA;
+ 	}
++
++	/*
++	 * This lock normally encloses of_overlay_apply() as well as
++	 * of_resolve_phandles().
++	 */
++	of_overlay_mutex_lock();
++
+ 	rc = of_resolve_phandles(unittest_data_node);
+ 	if (rc) {
+ 		pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
++		of_overlay_mutex_unlock();
+ 		return -EINVAL;
+ 	}
+ 
+@@ -1006,6 +1014,7 @@ static int __init unittest_data_add(void)
+ 			__of_attach_node_sysfs(np);
+ 		of_aliases = of_find_node_by_path("/aliases");
+ 		of_chosen = of_find_node_by_path("/chosen");
++		of_overlay_mutex_unlock();
+ 		return 0;
+ 	}
+ 
+@@ -1018,6 +1027,9 @@ static int __init unittest_data_add(void)
+ 		attach_node_and_children(np);
+ 		np = next;
+ 	}
++
++	of_overlay_mutex_unlock();
++
+ 	return 0;
+ }
+ 
+@@ -2149,16 +2161,11 @@ static int __init overlay_data_add(int onum)
+ 		goto out_free_data;
+ 	}
+ 
+-	ret = of_resolve_phandles(info->np_overlay);
+-	if (ret) {
+-		pr_err("resolve ot phandles (ret=%d), %d\n", ret, onum);
+-		goto out_free_np_overlay;
+-	}
+-
+ 	info->overlay_id = 0;
+ 	ret = of_overlay_apply(info->np_overlay, &info->overlay_id);
+ 	if (ret < 0) {
+ 		pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum);
++		of_overlay_mutex_unlock();
+ 		goto out_free_np_overlay;
+ 	}
+ 
+@@ -2208,7 +2215,10 @@ static __init void of_unittest_overlay_high_level(void)
+ 	 * Could not fixup phandles in unittest_unflatten_overlay_base()
+ 	 * because kmalloc() was not yet available.
+ 	 */
++	of_overlay_mutex_lock();
+ 	of_resolve_phandles(overlay_base_root);
++	of_overlay_mutex_unlock();
++
+ 
+ 	/*
+ 	 * do not allow overlay_base to duplicate any node already in
+diff --git a/include/linux/of.h b/include/linux/of.h
+index e9eeefa3eb6f..e273cc03a89d 100644
+--- a/include/linux/of.h
++++ b/include/linux/of.h
+@@ -1283,9 +1283,6 @@ static inline int of_reconfig_get_state_change(unsigned long action,
+ }
+ #endif /* CONFIG_OF_DYNAMIC */
+ 
+-/* CONFIG_OF_RESOLVE api */
+-extern int of_resolve_phandles(struct device_node *tree);
+-
+ /**
+  * of_device_is_system_power_controller - Tells if system-power-controller is found for device_node
+  * @np: Pointer to the given device_node
+-- 
+2.19.0
+
diff --git a/patches/0914-of-overlay-simplify-applying-symbols-from-an-overlay.patch b/patches/0914-of-overlay-simplify-applying-symbols-from-an-overlay.patch
new file mode 100644
index 00000000000000..7ef81c0704ea1c
--- /dev/null
+++ b/patches/0914-of-overlay-simplify-applying-symbols-from-an-overlay.patch
@@ -0,0 +1,235 @@
+From db0284c817f20c38b8a39cd8552529333a1af858 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:30 -0700
+Subject: [PATCH 0914/1795] of: overlay: simplify applying symbols from an
+ overlay
+
+The code to apply symbols from an overlay to the live device tree
+was implemented with the intent to be minimally intrusive on the
+existing code.  After recent restructuring of the overlay apply
+code, it is easier to disintangle the code that applies the
+symbols, and to make the overlay changeset creation code more
+straight forward and understandable.
+
+Remove the extra complexity, and make the code more obvious.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 3912b7917ab78d75b32bec8d297ac3c46b1b2a44)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 91 +++++++++++++++++++++++++++++++-------------
+ 1 file changed, 65 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index d164f86e5541..602218e07ec3 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -32,21 +32,22 @@
+ struct fragment {
+ 	struct device_node *target;
+ 	struct device_node *overlay;
+-	bool is_symbols_node;
+ };
+ 
+ /**
+  * struct overlay_changeset
+- * @ovcs_list:	list on which we are located
+- * @count:	count of @fragments structures
+- * @fragments:	info about fragment nodes in overlay expanded device tree
+- * @cset:	changeset to apply fragments to live device tree
++ * @ovcs_list:		list on which we are located
++ * @count:		count of fragment structures
++ * @fragments:		fragment nodes in the overlay expanded device tree
++ * @symbols_fragment:	last element of @fragments[] is the  __symbols__ node
++ * @cset:		changeset to apply fragments to live device tree
+  */
+ struct overlay_changeset {
+ 	int id;
+ 	struct list_head ovcs_list;
+ 	int count;
+ 	struct fragment *fragments;
++	bool symbols_fragment;
+ 	struct of_changeset cset;
+ };
+ 
+@@ -68,8 +69,7 @@ static int devicetree_corrupt(void)
+ 
+ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		struct device_node *target_node,
+-		const struct device_node *overlay_node,
+-		bool is_symbols_node);
++		const struct device_node *overlay_node);
+ 
+ /*
+  * of_resolve_phandles() finds the largest phandle in the live tree.
+@@ -221,7 +221,7 @@ static struct property *dup_and_fixup_symbol_prop(
+  * @ovcs:		overlay changeset
+  * @target_node:	where to place @overlay_prop in live tree
+  * @overlay_prop:	property to add or update, from overlay tree
+- * is_symbols_node:	1 if @target_node is "/__symbols__"
++ * @is_symbols_prop:	1 if @overlay_prop is from node "/__symbols__"
+  *
+  * If @overlay_prop does not already exist in @target_node, add changeset entry
+  * to add @overlay_prop in @target_node, else add changeset entry to update
+@@ -237,7 +237,7 @@ static struct property *dup_and_fixup_symbol_prop(
+ static int add_changeset_property(struct overlay_changeset *ovcs,
+ 		struct device_node *target_node,
+ 		struct property *overlay_prop,
+-		bool is_symbols_node)
++		bool is_symbols_prop)
+ {
+ 	struct property *new_prop = NULL, *prop;
+ 	int ret = 0;
+@@ -249,7 +249,7 @@ static int add_changeset_property(struct overlay_changeset *ovcs,
+ 	    !of_prop_cmp(overlay_prop->name, "linux,phandle"))
+ 		return 0;
+ 
+-	if (is_symbols_node) {
++	if (is_symbols_prop) {
+ 		if (prop)
+ 			return -EINVAL;
+ 		new_prop = dup_and_fixup_symbol_prop(ovcs, overlay_prop);
+@@ -330,13 +330,13 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+ 		if (ret)
+ 			return ret;
+ 
+-		return build_changeset_next_level(ovcs, tchild, node, 0);
++		return build_changeset_next_level(ovcs, tchild, node);
+ 	}
+ 
+ 	if (node->phandle && tchild->phandle)
+ 		ret = -EINVAL;
+ 	else
+-		ret = build_changeset_next_level(ovcs, tchild, node, 0);
++		ret = build_changeset_next_level(ovcs, tchild, node);
+ 	of_node_put(tchild);
+ 
+ 	return ret;
+@@ -347,7 +347,6 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+  * @ovcs:		overlay changeset
+  * @target_node:	where to place @overlay_node in live tree
+  * @overlay_node:	node from within an overlay device tree fragment
+- * @is_symbols_node:	@overlay_node is node "/__symbols__"
+  *
+  * Add the properties (if any) and nodes (if any) from @overlay_node to the
+  * @ovcs->cset changeset.  If an added node has child nodes, they will
+@@ -360,16 +359,14 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+  */
+ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		struct device_node *target_node,
+-		const struct device_node *overlay_node,
+-		bool is_symbols_node)
++		const struct device_node *overlay_node)
+ {
+ 	struct device_node *child;
+ 	struct property *prop;
+ 	int ret;
+ 
+ 	for_each_property_of_node(overlay_node, prop) {
+-		ret = add_changeset_property(ovcs, target_node, prop,
+-					     is_symbols_node);
++		ret = add_changeset_property(ovcs, target_node, prop, 0);
+ 		if (ret) {
+ 			pr_debug("Failed to apply prop @%pOF/%s, err=%d\n",
+ 				 target_node, prop->name, ret);
+@@ -377,9 +374,6 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 		}
+ 	}
+ 
+-	if (is_symbols_node)
+-		return 0;
+-
+ 	for_each_child_of_node(overlay_node, child) {
+ 		ret = add_changeset_node(ovcs, target_node, child);
+ 		if (ret) {
+@@ -393,6 +387,28 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+ 	return 0;
+ }
+ 
++/*
++ * Add the properties from __overlay__ node to the @ovcs->cset changeset.
++ */
++static int build_changeset_symbols_node(struct overlay_changeset *ovcs,
++		struct device_node *target_node,
++		const struct device_node *overlay_symbols_node)
++{
++	struct property *prop;
++	int ret;
++
++	for_each_property_of_node(overlay_symbols_node, prop) {
++		ret = add_changeset_property(ovcs, target_node, prop, 1);
++		if (ret) {
++			pr_debug("Failed to apply prop @%pOF/%s, err=%d\n",
++				 target_node, prop->name, ret);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
+ /**
+  * build_changeset() - populate overlay changeset in @ovcs from @ovcs->fragments
+  * @ovcs:	Overlay changeset
+@@ -407,14 +423,33 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
+  */
+ static int build_changeset(struct overlay_changeset *ovcs)
+ {
+-	int i, ret;
++	struct fragment *fragment;
++	int fragments_count, i, ret;
+ 
+-	for (i = 0; i < ovcs->count; i++) {
+-		struct fragment *fragment = &ovcs->fragments[i];
++	/*
++	 * if there is a symbols fragment in ovcs->fragments[i] it is
++	 * the final element in the array
++	 */
++	if (ovcs->symbols_fragment)
++		fragments_count = ovcs->count - 1;
++	else
++		fragments_count = ovcs->count;
++
++	for (i = 0; i < fragments_count; i++) {
++		fragment = &ovcs->fragments[i];
+ 
+ 		ret = build_changeset_next_level(ovcs, fragment->target,
+-					       fragment->overlay,
+-					       fragment->is_symbols_node);
++						 fragment->overlay);
++		if (ret) {
++			pr_debug("apply failed '%pOF'\n", fragment->target);
++			return ret;
++		}
++	}
++
++	if (ovcs->symbols_fragment) {
++		fragment = &ovcs->fragments[ovcs->count - 1];
++		ret = build_changeset_symbols_node(ovcs, fragment->target,
++						   fragment->overlay);
+ 		if (ret) {
+ 			pr_debug("apply failed '%pOF'\n", fragment->target);
+ 			return ret;
+@@ -531,12 +566,16 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		}
+ 	}
+ 
++	/*
++	 * if there is a symbols fragment in ovcs->fragments[i] it is
++	 * the final element in the array
++	 */
+ 	node = of_get_child_by_name(tree, "__symbols__");
+ 	if (node) {
++		ovcs->symbols_fragment = 1;
+ 		fragment = &fragments[cnt];
+ 		fragment->overlay = node;
+ 		fragment->target = of_find_node_by_path("/__symbols__");
+-		fragment->is_symbols_node = 1;
+ 
+ 		if (!fragment->target) {
+ 			pr_err("no symbols in root of device tree.\n");
+-- 
+2.19.0
+
diff --git a/patches/0915-of-overlay-remove-a-dependency-on-device-node-full_n.patch b/patches/0915-of-overlay-remove-a-dependency-on-device-node-full_n.patch
new file mode 100644
index 00000000000000..645d43aa07cb5c
--- /dev/null
+++ b/patches/0915-of-overlay-remove-a-dependency-on-device-node-full_n.patch
@@ -0,0 +1,213 @@
+From 4d1641c4c95510c5420dad4c71c13e04134aeb37 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:31 -0700
+Subject: [PATCH 0915/1795] of: overlay: remove a dependency on device node
+ full_name
+
+The "%pOF" printf format was recently added to print the
+full name of a device tree node, with the intent of changing
+the node full_name field to contain only the node name instead
+of the full path of the node.
+
+dup_and_fixup_symbol_prop() duplicates a property from the
+"/__symbols__" node of an overlay device tree.  The value
+of each duplicated property must be fixed up to include
+the full path of a node in the live device tree.  The
+current code uses the node's full_name for that purpose.
+Update the code to use the "%pOF" printf format to
+determine the node's full path.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit e0a58f3e08d4b7fa8e2a4075c522f1a98c9e4cab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/base.c       |  2 +-
+ drivers/of/of_private.h |  2 +
+ drivers/of/overlay.c    | 90 +++++++++++++++++++++++++----------------
+ 3 files changed, 59 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/of/base.c b/drivers/of/base.c
+index 63897531cd75..0a3f518f2ca2 100644
+--- a/drivers/of/base.c
++++ b/drivers/of/base.c
+@@ -760,7 +760,7 @@ struct device_node *of_get_child_by_name(const struct device_node *node,
+ }
+ EXPORT_SYMBOL(of_get_child_by_name);
+ 
+-static struct device_node *__of_find_node_by_path(struct device_node *parent,
++struct device_node *__of_find_node_by_path(struct device_node *parent,
+ 						const char *path)
+ {
+ 	struct device_node *child;
+diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
+index 03772bdbd94b..267edb1b50df 100644
+--- a/drivers/of/of_private.h
++++ b/drivers/of/of_private.h
+@@ -93,6 +93,8 @@ extern void *__unflatten_device_tree(const void *blob,
+ struct property *__of_prop_dup(const struct property *prop, gfp_t allocflags);
+ __printf(2, 3) struct device_node *__of_node_dup(const struct device_node *np, const char *fmt, ...);
+ 
++struct device_node *__of_find_node_by_path(struct device_node *parent,
++						const char *path);
+ struct device_node *__of_find_node_by_full_path(struct device_node *node,
+ 						const char *path);
+ 
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 602218e07ec3..0e9aefc1ff15 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -37,6 +37,7 @@ struct fragment {
+ /**
+  * struct overlay_changeset
+  * @ovcs_list:		list on which we are located
++ * @overlay_tree:	expanded device tree that contains the fragment nodes
+  * @count:		count of fragment structures
+  * @fragments:		fragment nodes in the overlay expanded device tree
+  * @symbols_fragment:	last element of @fragments[] is the  __symbols__ node
+@@ -45,6 +46,7 @@ struct fragment {
+ struct overlay_changeset {
+ 	int id;
+ 	struct list_head ovcs_list;
++	struct device_node *overlay_tree;
+ 	int count;
+ 	struct fragment *fragments;
+ 	bool symbols_fragment;
+@@ -145,12 +147,13 @@ static int overlay_notify(struct overlay_changeset *ovcs,
+ }
+ 
+ /*
+- * The properties in the "/__symbols__" node are "symbols".
++ * The values of properties in the "/__symbols__" node are paths in
++ * the ovcs->overlay_tree.  When duplicating the properties, the paths
++ * need to be adjusted to be the correct path for the live device tree.
+  *
+- * The value of properties in the "/__symbols__" node is the path of a
+- * node in the subtree of a fragment node's "__overlay__" node, for
+- * example "/fragment@0/__overlay__/symbol_path_tail".  Symbol_path_tail
+- * can be a single node or it may be a multi-node path.
++ * The paths refer to a node in the subtree of a fragment node's "__overlay__"
++ * node, for example "/fragment@0/__overlay__/symbol_path_tail",
++ * where symbol_path_tail can be a single node or it may be a multi-node path.
+  *
+  * The duplicated property value will be modified by replacing the
+  * "/fragment_name/__overlay/" portion of the value  with the target
+@@ -160,59 +163,76 @@ static struct property *dup_and_fixup_symbol_prop(
+ 		struct overlay_changeset *ovcs, const struct property *prop)
+ {
+ 	struct fragment *fragment;
+-	struct property *new;
+-	const char *overlay_name;
+-	char *symbol_path_tail;
+-	char *symbol_path;
++	struct property *new_prop;
++	struct device_node *fragment_node;
++	struct device_node *overlay_node;
++	const char *path;
++	const char *path_tail;
+ 	const char *target_path;
+ 	int k;
+-	int symbol_path_tail_len;
+ 	int overlay_name_len;
++	int path_len;
++	int path_tail_len;
+ 	int target_path_len;
+ 
+ 	if (!prop->value)
+ 		return NULL;
+-	symbol_path = prop->value;
++	if (strnlen(prop->value, prop->length) >= prop->length)
++		return NULL;
++	path = prop->value;
++	path_len = strlen(path);
+ 
+-	new = kzalloc(sizeof(*new), GFP_KERNEL);
+-	if (!new)
++	if (path_len < 1)
+ 		return NULL;
++	fragment_node = __of_find_node_by_path(ovcs->overlay_tree, path + 1);
++	overlay_node = __of_find_node_by_path(fragment_node, "__overlay__/");
++	of_node_put(fragment_node);
++	of_node_put(overlay_node);
+ 
+ 	for (k = 0; k < ovcs->count; k++) {
+ 		fragment = &ovcs->fragments[k];
+-		overlay_name = fragment->overlay->full_name;
+-		overlay_name_len = strlen(overlay_name);
+-		if (!strncasecmp(symbol_path, overlay_name, overlay_name_len))
++		if (fragment->overlay == overlay_node)
+ 			break;
+ 	}
+-
+ 	if (k >= ovcs->count)
+-		goto err_free;
++		return NULL;
++
++	overlay_name_len = snprintf(NULL, 0, "%pOF", fragment->overlay);
+ 
+-	target_path = fragment->target->full_name;
++	if (overlay_name_len > path_len)
++		return NULL;
++	path_tail = path + overlay_name_len;
++	path_tail_len = strlen(path_tail);
++
++	target_path = kasprintf(GFP_KERNEL, "%pOF", fragment->target);
++	if (!target_path)
++		return NULL;
+ 	target_path_len = strlen(target_path);
+ 
+-	symbol_path_tail = symbol_path + overlay_name_len;
+-	symbol_path_tail_len = strlen(symbol_path_tail);
++	new_prop = kzalloc(sizeof(*new_prop), GFP_KERNEL);
++	if (!new_prop)
++		goto err_free_target_path;
+ 
+-	new->name = kstrdup(prop->name, GFP_KERNEL);
+-	new->length = target_path_len + symbol_path_tail_len + 1;
+-	new->value = kzalloc(new->length, GFP_KERNEL);
++	new_prop->name = kstrdup(prop->name, GFP_KERNEL);
++	new_prop->length = target_path_len + path_tail_len + 1;
++	new_prop->value = kzalloc(new_prop->length, GFP_KERNEL);
++	if (!new_prop->name || !new_prop->value)
++		goto err_free_new_prop;
+ 
+-	if (!new->name || !new->value)
+-		goto err_free;
++	strcpy(new_prop->value, target_path);
++	strcpy(new_prop->value + target_path_len, path_tail);
+ 
+-	strcpy(new->value, target_path);
+-	strcpy(new->value + target_path_len, symbol_path_tail);
++	of_property_set_flag(new_prop, OF_DYNAMIC);
+ 
+-	of_property_set_flag(new, OF_DYNAMIC);
++	return new_prop;
+ 
+-	return new;
++err_free_new_prop:
++	kfree(new_prop->name);
++	kfree(new_prop->value);
++	kfree(new_prop);
++err_free_target_path:
++	kfree(target_path);
+ 
+- err_free:
+-	kfree(new->name);
+-	kfree(new->value);
+-	kfree(new);
+ 	return NULL;
+ }
+ 
+@@ -519,6 +539,8 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 	if (!of_node_is_root(tree))
+ 		pr_debug("%s() tree is not root\n", __func__);
+ 
++	ovcs->overlay_tree = tree;
++
+ 	INIT_LIST_HEAD(&ovcs->ovcs_list);
+ 
+ 	of_changeset_init(&ovcs->cset);
+-- 
+2.19.0
+
diff --git a/patches/0916-of-overlay-remove-unneeded-check-for-NULL-kbasename.patch b/patches/0916-of-overlay-remove-unneeded-check-for-NULL-kbasename.patch
new file mode 100644
index 00000000000000..be6ad3bc444b7e
--- /dev/null
+++ b/patches/0916-of-overlay-remove-unneeded-check-for-NULL-kbasename.patch
@@ -0,0 +1,35 @@
+From e60fb90755808ec28a90c15c29b4e919b63b3cb1 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Tue, 17 Oct 2017 16:36:32 -0700
+Subject: [PATCH 0916/1795] of: overlay: remove unneeded check for NULL
+ kbasename()
+
+kbasename() will not return NULL if passed a valid string.  If
+the parameter passed to kbasename() in this case is already NULL
+then the devicetree has been corrupted.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 34ca5d76f250d4ba98c4cdc069ab79b395f9ecac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 0e9aefc1ff15..c99842bb4b09 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -331,8 +331,6 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
+ 	int ret = 0;
+ 
+ 	node_kbasename = kbasename(node->full_name);
+-	if (!node_kbasename)
+-		return -ENOMEM;
+ 
+ 	for_each_child_of_node(target_node, tchild)
+ 		if (!of_node_cmp(node_kbasename, kbasename(tchild->full_name)))
+-- 
+2.19.0
+
diff --git a/patches/0917-of-overlay-pr_err-from-return-NOTIFY_OK-to-overlay-a.patch b/patches/0917-of-overlay-pr_err-from-return-NOTIFY_OK-to-overlay-a.patch
new file mode 100644
index 00000000000000..66e7d7ac14b13b
--- /dev/null
+++ b/patches/0917-of-overlay-pr_err-from-return-NOTIFY_OK-to-overlay-a.patch
@@ -0,0 +1,36 @@
+From 190db19a328adf06476d0f0baf6422aefd7cef6e Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Thu, 19 Oct 2017 14:18:27 -0700
+Subject: [PATCH 0917/1795] of: overlay: pr_err from return NOTIFY_OK to
+ overlay apply/remove
+
+A device tree overlay notifier can return NOTIFY_OK, NOTIFY_STOP,
+or an embedded errno.  overlay_notify() incorrectly reports an
+error for NOTIFY_OK.
+
+Reported-by: atull@kernel.org
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit a1d19bd4cf1febf0d5ff60243826a248bd20f1a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index c99842bb4b09..f5fce0fea40b 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -133,7 +133,7 @@ static int overlay_notify(struct overlay_changeset *ovcs,
+ 
+ 		ret = blocking_notifier_call_chain(&overlay_notify_chain,
+ 						   action, &nd);
+-		if (ret == NOTIFY_STOP)
++		if (ret == NOTIFY_OK || ret == NOTIFY_STOP)
+ 			return 0;
+ 		if (ret) {
+ 			ret = notifier_to_errno(ret);
+-- 
+2.19.0
+
diff --git a/patches/0918-of-overlay-make-pr_err-string-unique.patch b/patches/0918-of-overlay-make-pr_err-string-unique.patch
new file mode 100644
index 00000000000000..afa6c3a5da71a4
--- /dev/null
+++ b/patches/0918-of-overlay-make-pr_err-string-unique.patch
@@ -0,0 +1,35 @@
+From c637ece0a15c506cc84c52b01fbb30823d8281fe Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Thu, 19 Oct 2017 14:38:11 -0700
+Subject: [PATCH 0918/1795] of: overlay: make pr_err() string unique
+
+The same error string occurs in drivers/of/resolver.c.  Change
+the error here to more precisely describe this case, and avoid
+the possible confusion of looking in the wrong source location
+to understand the cause of an error.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 4ee7c0d9649d472d31969b9cbb8151161db6a807)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index f5fce0fea40b..c150abb9049d 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -598,7 +598,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		fragment->target = of_find_node_by_path("/__symbols__");
+ 
+ 		if (!fragment->target) {
+-			pr_err("no symbols in root of device tree.\n");
++			pr_err("symbols in overlay, but not in live tree\n");
+ 			ret = -EINVAL;
+ 			goto err_free_fragments;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/0919-of-Spelling-s-changset-changeset.patch b/patches/0919-of-Spelling-s-changset-changeset.patch
new file mode 100644
index 00000000000000..a5c9e44c2319d2
--- /dev/null
+++ b/patches/0919-of-Spelling-s-changset-changeset.patch
@@ -0,0 +1,79 @@
+From 7420c0e2af50de8c8dba86a037615401d597a46e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 28 Nov 2017 09:25:23 +0100
+Subject: [PATCH 0919/1795] of: Spelling s/changset/changeset/
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit e9d92e40ac9dea5a9a185fc11227f492f0b74fc7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/dynamic.c | 4 ++--
+ drivers/of/overlay.c | 8 ++++----
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c
+index c1026efd6f9e..5b1e8e53568a 100644
+--- a/drivers/of/dynamic.c
++++ b/drivers/of/dynamic.c
+@@ -710,7 +710,7 @@ int __of_changeset_apply_entries(struct of_changeset *ocs, int *ret_revert)
+ /*
+  * Returns 0 on success, a negative error value in case of an error.
+  *
+- * If multiple changset entry notification errors occur then only the
++ * If multiple changeset entry notification errors occur then only the
+  * final notification error is reported.
+  */
+ int __of_changeset_apply_notify(struct of_changeset *ocs)
+@@ -810,7 +810,7 @@ int __of_changeset_revert_entries(struct of_changeset *ocs, int *ret_apply)
+ }
+ 
+ /*
+- * If multiple changset entry notification errors occur then only the
++ * If multiple changeset entry notification errors occur then only the
+  * final notification error is reported.
+  */
+ int __of_changeset_revert_notify(struct of_changeset *ocs)
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index c150abb9049d..3036f1776efc 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -660,14 +660,14 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+  * A non-zero return value will not have created the changeset if error is from:
+  *   - parameter checks
+  *   - building the changeset
+- *   - overlay changset pre-apply notifier
++ *   - overlay changeset pre-apply notifier
+  *
+  * If an error is returned by an overlay changeset pre-apply notifier
+  * then no further overlay changeset pre-apply notifier will be called.
+  *
+  * A non-zero return value will have created the changeset if error is from:
+  *   - overlay changeset entry notifier
+- *   - overlay changset post-apply notifier
++ *   - overlay changeset post-apply notifier
+  *
+  * If an error is returned by an overlay changeset post-apply notifier
+  * then no further overlay changeset post-apply notifier will be called.
+@@ -871,7 +871,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+  *
+  * A non-zero return value will not revert the changeset if error is from:
+  *   - parameter checks
+- *   - overlay changset pre-remove notifier
++ *   - overlay changeset pre-remove notifier
+  *   - overlay changeset entry revert
+  *
+  * If an error is returned by an overlay changeset pre-remove notifier
+@@ -882,7 +882,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+  *
+  * A non-zero return value will revert the changeset if error is from:
+  *   - overlay changeset entry notifier
+- *   - overlay changset post-remove notifier
++ *   - overlay changeset post-remove notifier
+  *
+  * If an error is returned by an overlay changeset post-remove notifier
+  * then no further overlay changeset post-remove notifier will be called.
+-- 
+2.19.0
+
diff --git a/patches/0920-of-overlay-Remove-else-after-goto.patch b/patches/0920-of-overlay-Remove-else-after-goto.patch
new file mode 100644
index 00000000000000..eb875bfb7a86b7
--- /dev/null
+++ b/patches/0920-of-overlay-Remove-else-after-goto.patch
@@ -0,0 +1,80 @@
+From 2274da00ff22dc538035376b44ee88f2d7db0d4b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 28 Nov 2017 09:26:33 +0100
+Subject: [PATCH 0920/1795] of: overlay: Remove else after goto
+
+If an "if" branch is terminated by a "goto", there's no need to have an
+"else" statement and an indented block of code.
+
+Remove the "else" statement to simplify the code flow for the casual
+reviewer.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 6de67de326041c3a450a117b2733cbedd3aab097)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 3036f1776efc..2b852a39581e 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -580,9 +580,9 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 				of_node_put(fragment->overlay);
+ 				ret = -EINVAL;
+ 				goto err_free_fragments;
+-			} else {
+-				cnt++;
+ 			}
++
++			cnt++;
+ 		}
+ 	}
+ 
+@@ -736,14 +736,13 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 			devicetree_state_flags |= DTSF_APPLY_FAIL;
+ 		}
+ 		goto err_free_overlay_changeset;
+-	} else {
+-		ret = __of_changeset_apply_notify(&ovcs->cset);
+-		if (ret)
+-			pr_err("overlay changeset entry notify error %d\n",
+-			       ret);
+-		/* fall through */
+ 	}
+ 
++	ret = __of_changeset_apply_notify(&ovcs->cset);
++	if (ret)
++		pr_err("overlay changeset entry notify error %d\n", ret);
++	/* notify failure is not fatal, continue */
++
+ 	list_add_tail(&ovcs->ovcs_list, &ovcs_list);
+ 	*ovcs_id = ovcs->id;
+ 
+@@ -931,15 +930,13 @@ int of_overlay_remove(int *ovcs_id)
+ 		if (ret_apply)
+ 			devicetree_state_flags |= DTSF_REVERT_FAIL;
+ 		goto out_unlock;
+-	} else {
+-		ret = __of_changeset_revert_notify(&ovcs->cset);
+-		if (ret) {
+-			pr_err("overlay changeset entry notify error %d\n",
+-			       ret);
+-			/* fall through - changeset was reverted */
+-		}
+ 	}
+ 
++	ret = __of_changeset_revert_notify(&ovcs->cset);
++	if (ret)
++		pr_err("overlay changeset entry notify error %d\n", ret);
++	/* notify failure is not fatal, continue */
++
+ 	*ovcs_id = 0;
+ 
+ 	ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
+-- 
+2.19.0
+
diff --git a/patches/0921-of-overlay-Fix-memory-leak-in-of_overlay_apply-error.patch b/patches/0921-of-overlay-Fix-memory-leak-in-of_overlay_apply-error.patch
new file mode 100644
index 00000000000000..5f7d5b77049d7a
--- /dev/null
+++ b/patches/0921-of-overlay-Fix-memory-leak-in-of_overlay_apply-error.patch
@@ -0,0 +1,92 @@
+From b61bc86ecd5a6cf42217439bb8af7ae67926a40f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 5 Dec 2017 16:27:02 +0100
+Subject: [PATCH 0921/1795] of: overlay: Fix memory leak in of_overlay_apply()
+ error path
+
+If of_resolve_phandles() fails, free_overlay_changeset() is called in
+the error path.  However, that function returns early if the list hasn't
+been initialized yet, before freeing the object.
+
+Explicitly calling kfree() instead would solve that issue. However, that
+complicates matter, by having to consider which of two different methods
+to use to dispose of the same object.
+
+Hence make free_overlay_changeset() consider initialization state of the
+different parts of the object, making it always safe to call (once!) to
+dispose of a (partially) initialized overlay_changeset:
+  - Only destroy the changeset if the list was initialized,
+  - Make init_overlay_changeset() store the ID in ovcs->id on success,
+    to avoid calling idr_remove() with an error value or an already
+    released ID.
+
+Reported-by: Colin King <colin.king@canonical.com>
+Fixes: f948d6d8b792bb90 ("of: overlay: avoid race condition between applying multiple overlays")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 1352f09b4cc4f9dce386620b118401738bbf0d5f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 2b852a39581e..bb3f123ed259 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -522,7 +522,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 	struct device_node *node, *overlay_node;
+ 	struct fragment *fragment;
+ 	struct fragment *fragments;
+-	int cnt, ret;
++	int cnt, id, ret;
+ 
+ 	/*
+ 	 * Warn for some issues.  Can not return -EINVAL for these until
+@@ -543,9 +543,9 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 
+ 	of_changeset_init(&ovcs->cset);
+ 
+-	ovcs->id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL);
+-	if (ovcs->id <= 0)
+-		return ovcs->id;
++	id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL);
++	if (id <= 0)
++		return id;
+ 
+ 	cnt = 0;
+ 
+@@ -611,6 +611,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		goto err_free_fragments;
+ 	}
+ 
++	ovcs->id = id;
+ 	ovcs->count = cnt;
+ 	ovcs->fragments = fragments;
+ 
+@@ -619,7 +620,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ err_free_fragments:
+ 	kfree(fragments);
+ err_free_idr:
+-	idr_remove(&ovcs_idr, ovcs->id);
++	idr_remove(&ovcs_idr, id);
+ 
+ 	pr_err("%s() failed, ret = %d\n", __func__, ret);
+ 
+@@ -630,9 +631,8 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+ {
+ 	int i;
+ 
+-	if (!ovcs->cset.entries.next)
+-		return;
+-	of_changeset_destroy(&ovcs->cset);
++	if (ovcs->cset.entries.next)
++		of_changeset_destroy(&ovcs->cset);
+ 
+ 	if (ovcs->id)
+ 		idr_remove(&ovcs_idr, ovcs->id);
+-- 
+2.19.0
+
diff --git a/patches/0922-of-overlay-Fix-un-locking-in-of_overlay_apply.patch b/patches/0922-of-overlay-Fix-un-locking-in-of_overlay_apply.patch
new file mode 100644
index 00000000000000..452b942d18f0ff
--- /dev/null
+++ b/patches/0922-of-overlay-Fix-un-locking-in-of_overlay_apply.patch
@@ -0,0 +1,79 @@
+From e914535cc137a9f4547d97e51a6a5cc755d9c676 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 5 Dec 2017 16:27:03 +0100
+Subject: [PATCH 0922/1795] of: overlay: Fix (un)locking in of_overlay_apply()
+
+The special overlay mutex is taken first, hence it should be released
+last in the error path.
+
+of_resolve_phandles() must be called with of_mutex held.  Without it, a
+node and new phandle could be added via of_attach_node(), making the max
+phandle wrong.
+
+free_overlay_changeset() must be called with of_mutex held, if any
+non-trivial cleanup is to be done.
+
+Hence move "mutex_lock(&of_mutex)" up, as suggested by Frank, and merge
+the two tail statements of the success and error paths, now they became
+identical.
+
+Note that while the two mutexes are adjacent, we still need both:
+__of_changeset_apply_notify(), which is called by __of_changeset_apply()
+unlocks of_mutex, then does notifications then locks of_mutex.  So the
+mutex get released in the middle of of_overlay_apply()
+
+Fixes: f948d6d8b792bb90 ("of: overlay: avoid race condition between applying multiple overlays")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Frank Rowand <frank.rowand@sony.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 5e4748175fe942c86cbab840e2fa41a92b4d6cf6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index bb3f123ed259..fcce5cdbe229 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -706,12 +706,11 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 	}
+ 
+ 	of_overlay_mutex_lock();
++	mutex_lock(&of_mutex);
+ 
+ 	ret = of_resolve_phandles(tree);
+ 	if (ret)
+-		goto err_overlay_unlock;
+-
+-	mutex_lock(&of_mutex);
++		goto err_free_overlay_changeset;
+ 
+ 	ret = init_overlay_changeset(ovcs, tree);
+ 	if (ret)
+@@ -754,18 +753,14 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 			ret = ret_tmp;
+ 	}
+ 
+-	mutex_unlock(&of_mutex);
+-	of_overlay_mutex_unlock();
+-
+-	goto out;
+-
+-err_overlay_unlock:
+-	of_overlay_mutex_unlock();
++	goto out_unlock;
+ 
+ err_free_overlay_changeset:
+ 	free_overlay_changeset(ovcs);
+ 
++out_unlock:
+ 	mutex_unlock(&of_mutex);
++	of_overlay_mutex_unlock();
+ 
+ out:
+ 	pr_debug("%s() err=%d\n", __func__, ret);
+-- 
+2.19.0
+
diff --git a/patches/0923-of-overlay-Fix-out-of-bounds-write-in-init_overlay_c.patch b/patches/0923-of-overlay-Fix-out-of-bounds-write-in-init_overlay_c.patch
new file mode 100644
index 00000000000000..d8d695e0b59a75
--- /dev/null
+++ b/patches/0923-of-overlay-Fix-out-of-bounds-write-in-init_overlay_c.patch
@@ -0,0 +1,50 @@
+From e8b167d256e67d6b1f40ca905887c7e26d55ce67 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 8 Dec 2017 14:13:02 +0100
+Subject: [PATCH 0923/1795] of: overlay: Fix out-of-bounds write in
+ init_overlay_changeset()
+
+If an overlay has no "__symbols__" node, but it has nodes without
+"__overlay__" subnodes at the end (e.g. a "__fixups__" node), after
+filling in all fragments for nodes with "__overlay__" subnodes,
+"fragment = &fragments[cnt]" will point beyond the end of the allocated
+array.
+
+Hence writing to "fragment->overlay" will overwrite unallocated memory,
+which may lead to a crash later.
+
+Fix this by deferring both the assignment to "fragment" and the
+offending write afterwards until we know for sure the node has an
+"__overlay__" subnode, and thus a valid entry in "fragments[]".
+
+Fixes: 61b4de4e0b384f4a ("of: overlay: minor restructuring")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 35e691eddca565f475ba69ff84ca0c9db3b3257b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index fcce5cdbe229..83bb2edfc65c 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -572,9 +572,10 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node) {
+-		fragment = &fragments[cnt];
+-		fragment->overlay = of_get_child_by_name(node, "__overlay__");
+-		if (fragment->overlay) {
++		overlay_node = of_get_child_by_name(node, "__overlay__");
++		if (overlay_node) {
++			fragment = &fragments[cnt];
++			fragment->overlay = overlay_node;
+ 			fragment->target = find_target_node(node);
+ 			if (!fragment->target) {
+ 				of_node_put(fragment->overlay);
+-- 
+2.19.0
+
diff --git a/patches/0924-of-overlay-Make-node-skipping-in-init_overlay_change.patch b/patches/0924-of-overlay-Make-node-skipping-in-init_overlay_change.patch
new file mode 100644
index 00000000000000..8999d5339e77eb
--- /dev/null
+++ b/patches/0924-of-overlay-Make-node-skipping-in-init_overlay_change.patch
@@ -0,0 +1,56 @@
+From 9b690f636d3e1941b37415aec836bf35c1216ce3 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 8 Dec 2017 14:13:03 +0100
+Subject: [PATCH 0924/1795] of: overlay: Make node skipping in
+ init_overlay_changeset() clearer
+
+Make it more clear that nodes without "__overlay__" subnodes are
+skipped, by reverting the logic and using continue.
+This also reduces indentation level.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 589b754df3f37ca0a1f96fccde7f91c59266f38a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 83bb2edfc65c..3981b7da4fa9 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -573,18 +573,19 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 	cnt = 0;
+ 	for_each_child_of_node(tree, node) {
+ 		overlay_node = of_get_child_by_name(node, "__overlay__");
+-		if (overlay_node) {
+-			fragment = &fragments[cnt];
+-			fragment->overlay = overlay_node;
+-			fragment->target = find_target_node(node);
+-			if (!fragment->target) {
+-				of_node_put(fragment->overlay);
+-				ret = -EINVAL;
+-				goto err_free_fragments;
+-			}
++		if (!overlay_node)
++			continue;
+ 
+-			cnt++;
++		fragment = &fragments[cnt];
++		fragment->overlay = overlay_node;
++		fragment->target = find_target_node(node);
++		if (!fragment->target) {
++			of_node_put(fragment->overlay);
++			ret = -EINVAL;
++			goto err_free_fragments;
+ 		}
++
++		cnt++;
+ 	}
+ 
+ 	/*
+-- 
+2.19.0
+
diff --git a/patches/0925-ASoC-rsnd-indicate-IRQ-error-status-for-debug.patch b/patches/0925-ASoC-rsnd-indicate-IRQ-error-status-for-debug.patch
new file mode 100644
index 00000000000000..3ad58a36e5042d
--- /dev/null
+++ b/patches/0925-ASoC-rsnd-indicate-IRQ-error-status-for-debug.patch
@@ -0,0 +1,139 @@
+From 1c0d545fd8308c1ba27e0f99d9ef4131b8319f1b Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 13 Feb 2018 02:08:53 +0000
+Subject: [PATCH 0925/1795] ASoC: rsnd: indicate IRQ error status for debug
+
+SSI/SRC have under/over flow error handling, and its status is useful
+for debuging. But sometimes it might be too much message,
+and it might blocks necessity other information.
+
+To avoid such situation, basically this patch indicates interrupt
+status debug message if DEBUG was defined, but it will be suppressed
+if RSND_DEBUG_NO_IRQ_STATUS was defined.
+
+Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 2b62786951ca38cc9fd0bd9273de0aae1b45134d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/rsnd.h | 10 ++++++++++
+ sound/soc/sh/rcar/src.c  | 22 ++++++++++++++++++++--
+ sound/soc/sh/rcar/ssi.c  | 16 +++++++++++++++-
+ 3 files changed, 45 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index ad6523595b0a..5241ea7cf153 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -788,4 +788,14 @@ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type);
+ #define rsnd_mod_confirm_dvc(mdvc)
+ #endif
+ 
++/*
++ * If you don't need interrupt status debug message,
++ * define RSND_DEBUG_NO_IRQ_STATUS as 1 on top of src.c/ssi.c
++ *
++ * #define RSND_DEBUG_NO_IRQ_STATUS 1
++ */
++#define rsnd_dbg_irq_status(dev, param...)		\
++	if (!IS_BUILTIN(RSND_DEBUG_NO_IRQ_STATUS))	\
++		dev_dbg(dev, param)
++
+ #endif
+diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c
+index 510b68a483b4..a727e71587b6 100644
+--- a/sound/soc/sh/rcar/src.c
++++ b/sound/soc/sh/rcar/src.c
+@@ -8,6 +8,15 @@
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
++
++/*
++ * you can enable below define if you don't need
++ * SSI interrupt status debug message when debugging
++ * see rsnd_dbg_irq_status()
++ *
++ * #define RSND_DEBUG_NO_IRQ_STATUS 1
++ */
++
+ #include "rsnd.h"
+ 
+ #define SRC_NAME "src"
+@@ -325,7 +334,10 @@ static void rsnd_src_status_clear(struct rsnd_mod *mod)
+ 
+ static bool rsnd_src_error_occurred(struct rsnd_mod *mod)
+ {
++	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
++	struct device *dev = rsnd_priv_to_dev(priv);
+ 	u32 val0, val1;
++	u32 status0, status1;
+ 	bool ret = false;
+ 
+ 	val0 = val1 = OUF_SRC(rsnd_mod_id(mod));
+@@ -338,9 +350,15 @@ static bool rsnd_src_error_occurred(struct rsnd_mod *mod)
+ 	if (rsnd_src_sync_is_enabled(mod))
+ 		val0 = val0 & 0xffff;
+ 
+-	if ((rsnd_mod_read(mod, SCU_SYS_STATUS0) & val0) ||
+-	    (rsnd_mod_read(mod, SCU_SYS_STATUS1) & val1))
++	status0 = rsnd_mod_read(mod, SCU_SYS_STATUS0);
++	status1 = rsnd_mod_read(mod, SCU_SYS_STATUS1);
++	if ((status0 & val0) || (status1 & val1)) {
++		rsnd_dbg_irq_status(dev, "%s[%d] err status : 0x%08x, 0x%08x\n",
++			rsnd_mod_name(mod), rsnd_mod_id(mod),
++			status0, status1);
++
+ 		ret = true;
++	}
+ 
+ 	return ret;
+ }
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index 97a9db892a8f..333b802681ad 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -11,6 +11,15 @@
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
++
++/*
++ * you can enable below define if you don't need
++ * SSI interrupt status debug message when debugging
++ * see rsnd_dbg_irq_status()
++ *
++ * #define RSND_DEBUG_NO_IRQ_STATUS 1
++ */
++
+ #include <sound/simple_card_utils.h>
+ #include <linux/delay.h>
+ #include "rsnd.h"
+@@ -603,6 +612,7 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
+ 				 struct rsnd_dai_stream *io)
+ {
+ 	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
++	struct device *dev = rsnd_priv_to_dev(priv);
+ 	int is_dma = rsnd_ssi_is_dma_mode(mod);
+ 	u32 status;
+ 	bool elapsed = false;
+@@ -621,8 +631,12 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
+ 		elapsed = rsnd_ssi_pio_interrupt(mod, io);
+ 
+ 	/* DMA only */
+-	if (is_dma && (status & (UIRQ | OIRQ)))
++	if (is_dma && (status & (UIRQ | OIRQ))) {
++		rsnd_dbg_irq_status(dev, "%s[%d] err status : 0x%08x\n",
++			rsnd_mod_name(mod), rsnd_mod_id(mod), status);
++
+ 		stop = true;
++	}
+ 
+ 	rsnd_ssi_status_clear(mod);
+ rsnd_ssi_interrupt_out:
+-- 
+2.19.0
+
diff --git a/patches/0926-ASoC-rsnd-suppress-rsnd_dai_call-debug-message.patch b/patches/0926-ASoC-rsnd-suppress-rsnd_dai_call-debug-message.patch
new file mode 100644
index 00000000000000..2e6f7ae4352576
--- /dev/null
+++ b/patches/0926-ASoC-rsnd-suppress-rsnd_dai_call-debug-message.patch
@@ -0,0 +1,72 @@
+From c8d089b979b6fa508f18bc786d1346fbc080ceb3 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 13 Feb 2018 02:09:14 +0000
+Subject: [PATCH 0926/1795] ASoC: rsnd: suppress rsnd_dai_call() debug message
+
+rsnd_dai_call() is using dev_dbg(), but its message is sometimes
+blocks nessesary other messages. If RSND_DEBUG_NO_DAI_CALL was
+defined it will be suppressed by this patch.
+
+Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 1f6e920faae065fa8e6985b99ec86899bc3308de)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 11 ++++++++++-
+ sound/soc/sh/rcar/rsnd.h | 10 ++++++++++
+ 2 files changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 64d5ecb86528..5aafc37f5119 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -93,6 +93,15 @@
+  *  [mod]->fn() -> [mod]->fn() -> [mod]->fn()...
+  *
+  */
++
++/*
++ * you can enable below define if you don't need
++ * DAI status debug message when debugging
++ * see rsnd_dbg_dai_call()
++ *
++ * #define RSND_DEBUG_NO_DAI_CALL 1
++ */
++
+ #include <linux/pm_runtime.h>
+ #include "rsnd.h"
+ 
+@@ -468,7 +477,7 @@ static int rsnd_status_update(u32 *status,
+ 						__rsnd_mod_shift_##fn,	\
+ 						__rsnd_mod_add_##fn,	\
+ 						__rsnd_mod_call_##fn);	\
+-		dev_dbg(dev, "%s[%d]\t0x%08x %s\n",			\
++		rsnd_dbg_dai_call(dev, "%s[%d]\t0x%08x %s\n",		\
+ 			rsnd_mod_name(mod), rsnd_mod_id(mod), *status,	\
+ 			(func_call && (mod)->ops->fn) ? #fn : "");	\
+ 		if (func_call && (mod)->ops->fn)			\
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 5241ea7cf153..172c8d612890 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -798,4 +798,14 @@ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type);
+ 	if (!IS_BUILTIN(RSND_DEBUG_NO_IRQ_STATUS))	\
+ 		dev_dbg(dev, param)
+ 
++/*
++ * If you don't need rsnd_dai_call debug message,
++ * define RSND_DEBUG_NO_DAI_CALL as 1 on top of core.c
++ *
++ * #define RSND_DEBUG_NO_DAI_CALL 1
++ */
++#define rsnd_dbg_dai_call(dev, param...)		\
++	if (!IS_BUILTIN(RSND_DEBUG_NO_DAI_CALL))	\
++		dev_dbg(dev, param)
++
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/0927-ASoC-rsnd-Document-R-Car-M3-W-support.patch b/patches/0927-ASoC-rsnd-Document-R-Car-M3-W-support.patch
new file mode 100644
index 00000000000000..78364d5eca0429
--- /dev/null
+++ b/patches/0927-ASoC-rsnd-Document-R-Car-M3-W-support.patch
@@ -0,0 +1,35 @@
+From 3183ab5ef1d11ff4ad1a43740067344fe92d6dce Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 16 Mar 2018 14:59:45 +0100
+Subject: [PATCH 0927/1795] ASoC: rsnd: Document R-Car M3-W support
+
+Document support for the sound modules in the Renesas M3-W (r8a7796)
+SoC.
+
+No driver update is needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit da263026c013412110da464537e1c5532f0714ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+index 5bed9a595772..b86d790f630f 100644
+--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
++++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+@@ -351,6 +351,7 @@ Required properties:
+ 				    - "renesas,rcar_sound-r8a7793" (R-Car M2-N)
+ 				    - "renesas,rcar_sound-r8a7794" (R-Car E2)
+ 				    - "renesas,rcar_sound-r8a7795" (R-Car H3)
++				    - "renesas,rcar_sound-r8a7796" (R-Car M3-W)
+ - reg				: Should contain the register physical address.
+ 				  required register is
+ 				   SRU/ADG/SSI      if generation1
+-- 
+2.19.0
+
diff --git a/patches/0928-ASoC-rsnd-set-pm_ops-in-hibernate-compatible-way.patch b/patches/0928-ASoC-rsnd-set-pm_ops-in-hibernate-compatible-way.patch
new file mode 100644
index 00000000000000..3432098d7e405a
--- /dev/null
+++ b/patches/0928-ASoC-rsnd-set-pm_ops-in-hibernate-compatible-way.patch
@@ -0,0 +1,36 @@
+From 8443b0f7f992d52fb59550280d96cfd73212b9a9 Mon Sep 17 00:00:00 2001
+From: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
+Date: Tue, 20 Mar 2018 11:41:15 +0300
+Subject: [PATCH 0928/1795] ASoC: rsnd: set pm_ops in hibernate-compatible way
+
+Use SET_SYSTEM_SLEEP_PM_OPS() macro instead of direct assignment to
+.suspend and .resume fields.
+
+This makes driver working after restore from hibernation.
+
+Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit f8a9a29c4fe9dd0dd2206cc4368efec95dc9defb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 5aafc37f5119..96526c91a94b 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1569,8 +1569,7 @@ static int rsnd_resume(struct device *dev)
+ }
+ 
+ static const struct dev_pm_ops rsnd_pm_ops = {
+-	.suspend		= rsnd_suspend,
+-	.resume			= rsnd_resume,
++	SET_SYSTEM_SLEEP_PM_OPS(rsnd_suspend, rsnd_resume)
+ };
+ 
+ static struct platform_driver rsnd_driver = {
+-- 
+2.19.0
+
diff --git a/patches/0929-ASoC-rsnd-mark-PM-functions-__maybe_unused.patch b/patches/0929-ASoC-rsnd-mark-PM-functions-__maybe_unused.patch
new file mode 100644
index 00000000000000..ec530d53cc07ae
--- /dev/null
+++ b/patches/0929-ASoC-rsnd-mark-PM-functions-__maybe_unused.patch
@@ -0,0 +1,51 @@
+From 3d692ada74fe17ce2a416d77cb24ea5924b5e439 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 28 Mar 2018 16:53:10 +0200
+Subject: [PATCH 0929/1795] ASoC: rsnd: mark PM functions __maybe_unused
+
+The suspend/resume callbacks are now optional, leading to a warning
+when they are unused:
+
+sound/soc/sh/rcar/core.c:1548:12: error: 'rsnd_resume' defined but not used [-Werror=unused-function]
+ static int rsnd_resume(struct device *dev)
+            ^~~~~~~~~~~
+sound/soc/sh/rcar/core.c:1539:12: error: 'rsnd_suspend' defined but not used [-Werror=unused-function]
+ static int rsnd_suspend(struct device *dev)
+
+This marks the as __maybe_unused to avoid the warning.
+
+Fixes: f8a9a29c4fe9 ("ASoC: rsnd: set pm_ops in hibernate-compatible way")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 6f5427039c33e149b711c0f973fcac7f6875b768)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 96526c91a94b..be92c11a22bb 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1550,7 +1550,7 @@ static int rsnd_remove(struct platform_device *pdev)
+ 	return ret;
+ }
+ 
+-static int rsnd_suspend(struct device *dev)
++static int __maybe_unused rsnd_suspend(struct device *dev)
+ {
+ 	struct rsnd_priv *priv = dev_get_drvdata(dev);
+ 
+@@ -1559,7 +1559,7 @@ static int rsnd_suspend(struct device *dev)
+ 	return 0;
+ }
+ 
+-static int rsnd_resume(struct device *dev)
++static int __maybe_unused rsnd_resume(struct device *dev)
+ {
+ 	struct rsnd_priv *priv = dev_get_drvdata(dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/0930-drm-bridge-synopsys-dw-hdmi-fix-dw_hdmi_setup_rx_sen.patch b/patches/0930-drm-bridge-synopsys-dw-hdmi-fix-dw_hdmi_setup_rx_sen.patch
new file mode 100644
index 00000000000000..dd8b6b5e24825b
--- /dev/null
+++ b/patches/0930-drm-bridge-synopsys-dw-hdmi-fix-dw_hdmi_setup_rx_sen.patch
@@ -0,0 +1,120 @@
+From 88b31315de3888609506ebb057007737e3ca540a Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 30 May 2018 11:43:58 +0200
+Subject: [PATCH 0930/1795] drm/bridge/synopsys: dw-hdmi: fix
+ dw_hdmi_setup_rx_sense
+
+The dw_hdmi_setup_rx_sense exported function should not use struct device
+to recover the dw-hdmi context using drvdata, but take struct dw_hdmi
+directly like other exported functions.
+
+This caused a regression using Meson DRM on S905X since v4.17-rc1 :
+
+Internal error: Oops: 96000007 [#1] PREEMPT SMP
+[...]
+CPU: 0 PID: 124 Comm: irq/32-dw_hdmi_ Not tainted 4.17.0-rc7 #2
+Hardware name: Libre Technology CC (DT)
+[...]
+pc : osq_lock+0x54/0x188
+lr : __mutex_lock.isra.0+0x74/0x530
+[...]
+Process irq/32-dw_hdmi_ (pid: 124, stack limit = 0x00000000adf418cb)
+Call trace:
+  osq_lock+0x54/0x188
+  __mutex_lock_slowpath+0x10/0x18
+  mutex_lock+0x30/0x38
+  __dw_hdmi_setup_rx_sense+0x28/0x98
+  dw_hdmi_setup_rx_sense+0x10/0x18
+  dw_hdmi_top_thread_irq+0x2c/0x50
+  irq_thread_fn+0x28/0x68
+  irq_thread+0x10c/0x1a0
+  kthread+0x128/0x130
+  ret_from_fork+0x10/0x18
+ Code: 34000964 d00050a2 51000484 9135c042 (f864d844)
+ ---[ end trace 945641e1fbbc07da ]---
+ note: irq/32-dw_hdmi_[124] exited with preempt_count 1
+ genirq: exiting task "irq/32-dw_hdmi_" (124) is an active IRQ thread (irq 32)
+
+Fixes: eea034af90c6 ("drm/bridge/synopsys: dw-hdmi: don't clobber drvdata")
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Tested-by: Koen Kooi <koen@dominion.thruhere.net>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/1527673438-20643-1-git-send-email-narmstrong@baylibre.com
+(cherry picked from commit c32048d9e93a5ab925d745396c63e7b912147f0a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 15 ++++-----------
+ drivers/gpu/drm/meson/meson_dw_hdmi.c     |  2 +-
+ include/drm/bridge/dw_hdmi.h              |  2 +-
+ 3 files changed, 6 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index f7d89a9dc4a1..75d1b500ddd3 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2082,7 +2082,7 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
+ 	return ret;
+ }
+ 
+-void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
++void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
+ {
+ 	mutex_lock(&hdmi->mutex);
+ 
+@@ -2108,13 +2108,6 @@ void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
+ 	}
+ 	mutex_unlock(&hdmi->mutex);
+ }
+-
+-void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense)
+-{
+-	struct dw_hdmi *hdmi = dev_get_drvdata(dev);
+-
+-	__dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense);
+-}
+ EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
+ 
+ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+@@ -2150,9 +2143,9 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 	 */
+ 	if (intr_stat &
+ 	    (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
+-		__dw_hdmi_setup_rx_sense(hdmi,
+-					 phy_stat & HDMI_PHY_HPD,
+-					 phy_stat & HDMI_PHY_RX_SENSE);
++		dw_hdmi_setup_rx_sense(hdmi,
++				       phy_stat & HDMI_PHY_HPD,
++				       phy_stat & HDMI_PHY_RX_SENSE);
+ 
+ 		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
+ 			cec_notifier_set_phys_addr(hdmi->cec_notifier,
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index bc18e3fc7a68..54b1395837f0 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -527,7 +527,7 @@ static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
+ 		if (stat & HDMITX_TOP_INTR_HPD_RISE)
+ 			hpd_connected = true;
+ 
+-		dw_hdmi_setup_rx_sense(dw_hdmi->dev, hpd_connected,
++		dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
+ 				       hpd_connected);
+ 
+ 		drm_helper_hpd_irq_event(dw_hdmi->encoder.dev);
+diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
+index dd2a8cf7d20b..ccb5aa8468e0 100644
+--- a/include/drm/bridge/dw_hdmi.h
++++ b/include/drm/bridge/dw_hdmi.h
+@@ -151,7 +151,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
+ 			     struct drm_encoder *encoder,
+ 			     const struct dw_hdmi_plat_data *plat_data);
+ 
+-void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense);
++void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
+ 
+ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
+ void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
+-- 
+2.19.0
+
diff --git a/patches/0931-drm-tilcdc-Remove-redundant-OF_DETACHED-flag-setting.patch b/patches/0931-drm-tilcdc-Remove-redundant-OF_DETACHED-flag-setting.patch
new file mode 100644
index 00000000000000..8141dbe7a02aab
--- /dev/null
+++ b/patches/0931-drm-tilcdc-Remove-redundant-OF_DETACHED-flag-setting.patch
@@ -0,0 +1,44 @@
+From 63fb8d91ec17c901aceccae7a8e4ae9a64838263 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <stephen.boyd@linaro.org>
+Date: Fri, 13 Oct 2017 00:47:55 -0700
+Subject: [PATCH 0931/1795] drm/tilcdc: Remove redundant OF_DETACHED flag
+ setting
+
+of_fdt_unflatten_tree() already sets the flag on this node to
+OF_DETACHED, because of_fdt_unflatten_tree() calls
+__unflatten_device_tree() with the detached bool set to true.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: Frank Rowand <frowand.list@gmail.com>
+Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
+Signed-off-by: Jyri Sarha <jsarha@ti.com>
+(cherry picked from commit 44cd3939c111b78a9fc6e3136fb0f9b6f475f68a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+---
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+index 54025af534d4..71a4bb953273 100644
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
++++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+@@ -162,7 +162,11 @@ static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
+ 		return NULL;
+ 	}
+ 
+-	of_node_set_flag(overlay, OF_DETACHED);
++	ret = of_resolve_phandles(overlay);
++	if (ret) {
++		pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret);
++		return NULL;
++	}
+ 
+ 	return overlay;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0932-drm-tilcdc-Remove-obsolete-ti-tilcdc-slave-dts-bindi.patch b/patches/0932-drm-tilcdc-Remove-obsolete-ti-tilcdc-slave-dts-bindi.patch
new file mode 100644
index 00000000000000..df46f4367e5281
--- /dev/null
+++ b/patches/0932-drm-tilcdc-Remove-obsolete-ti-tilcdc-slave-dts-bindi.patch
@@ -0,0 +1,454 @@
+From fa68296bef3a5f65919df72cfda225ad99bd31b0 Mon Sep 17 00:00:00 2001
+From: Jyri Sarha <jsarha@ti.com>
+Date: Fri, 3 Nov 2017 12:54:01 +0200
+Subject: [PATCH 0932/1795] drm/tilcdc: Remove obsolete "ti,tilcdc,slave" dts
+ binding support
+
+This patch removes DRM_TILCDC_SLAVE_COMPAT option for supporting the
+obsolete "ti,tilcdc,slave" device tree binding. The new of_graph based
+binding - that is widely used in other drm driver too - has been
+supported since Linux v4.2. Maintaining the the backwards dts
+conversion code in the DRM_TILCDC_SLAVE_COMPAT has become a nuisance
+for the device/of development so the we decided to drop it after Linux
+v4.14, the 2017 LTS.
+
+Signed-off-by: Jyri Sarha <jsarha@ti.com>
+Acked-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 739acd85ffdb725a8ef206737875f4b2c1dad02a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+---
+ drivers/gpu/drm/tilcdc/Kconfig                |  11 -
+ drivers/gpu/drm/tilcdc/Makefile               |   3 -
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c  | 270 ------------------
+ .../gpu/drm/tilcdc/tilcdc_slave_compat.dts    |  72 -----
+ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h  |  25 --
+ 5 files changed, 381 deletions(-)
+ delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+ delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
+ delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
+
+diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
+index 28fed7e206d0..81ac82455ce4 100644
+--- a/drivers/gpu/drm/tilcdc/Kconfig
++++ b/drivers/gpu/drm/tilcdc/Kconfig
+@@ -12,14 +12,3 @@ config DRM_TILCDC
+ 	  controller, for example AM33xx in beagle-bone, DA8xx, or
+ 	  OMAP-L1xx.  This driver replaces the FB_DA8XX fbdev driver.
+ 
+-config DRM_TILCDC_SLAVE_COMPAT
+-	bool "Support device tree blobs using TI LCDC Slave binding"
+-	depends on DRM_TILCDC
+-	default y
+-	select OF_RESOLVE
+-	select OF_OVERLAY
+-	help
+-	  Choose this option if you need a kernel that is compatible
+-	  with device tree blobs using the obsolete "ti,tilcdc,slave"
+-	  binding. If you find "ti,tilcdc,slave"-string from your DTB,
+-	  you probably need this. Otherwise you do not.
+diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile
+index b9e1108e5b4e..87f9480e43b0 100644
+--- a/drivers/gpu/drm/tilcdc/Makefile
++++ b/drivers/gpu/drm/tilcdc/Makefile
+@@ -3,9 +3,6 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
+ 	ccflags-y += -Werror
+ endif
+ 
+-obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \
+-					 tilcdc_slave_compat.dtb.o
+-
+ tilcdc-y := \
+ 	tilcdc_plane.o \
+ 	tilcdc_crtc.o \
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+deleted file mode 100644
+index 71a4bb953273..000000000000
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
++++ /dev/null
+@@ -1,270 +0,0 @@
+-/*
+- * Copyright (C) 2015 Texas Instruments
+- * Author: Jyri Sarha <jsarha@ti.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- */
+-
+-/*
+- * To support the old "ti,tilcdc,slave" binding the binding has to be
+- * transformed to the new external encoder binding.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/of.h>
+-#include <linux/of_graph.h>
+-#include <linux/of_fdt.h>
+-#include <linux/slab.h>
+-#include <linux/list.h>
+-
+-#include "tilcdc_slave_compat.h"
+-
+-struct kfree_table {
+-	int total;
+-	int num;
+-	void **table;
+-};
+-
+-static int __init kfree_table_init(struct kfree_table *kft)
+-{
+-	kft->total = 32;
+-	kft->num = 0;
+-	kft->table = kmalloc(kft->total * sizeof(*kft->table),
+-			     GFP_KERNEL);
+-	if (!kft->table)
+-		return -ENOMEM;
+-
+-	return 0;
+-}
+-
+-static int __init kfree_table_add(struct kfree_table *kft, void *p)
+-{
+-	if (kft->num == kft->total) {
+-		void **old = kft->table;
+-
+-		kft->total *= 2;
+-		kft->table = krealloc(old, kft->total * sizeof(*kft->table),
+-				      GFP_KERNEL);
+-		if (!kft->table) {
+-			kft->table = old;
+-			kfree(p);
+-			return -ENOMEM;
+-		}
+-	}
+-	kft->table[kft->num++] = p;
+-	return 0;
+-}
+-
+-static void __init kfree_table_free(struct kfree_table *kft)
+-{
+-	int i;
+-
+-	for (i = 0; i < kft->num; i++)
+-		kfree(kft->table[i]);
+-
+-	kfree(kft->table);
+-}
+-
+-static
+-struct property * __init tilcdc_prop_dup(const struct property *prop,
+-					 struct kfree_table *kft)
+-{
+-	struct property *nprop;
+-
+-	nprop = kzalloc(sizeof(*nprop), GFP_KERNEL);
+-	if (!nprop || kfree_table_add(kft, nprop))
+-		return NULL;
+-
+-	nprop->name = kstrdup(prop->name, GFP_KERNEL);
+-	if (!nprop->name || kfree_table_add(kft, nprop->name))
+-		return NULL;
+-
+-	nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL);
+-	if (!nprop->value || kfree_table_add(kft, nprop->value))
+-		return NULL;
+-
+-	nprop->length = prop->length;
+-
+-	return nprop;
+-}
+-
+-static void __init tilcdc_copy_props(struct device_node *from,
+-				     struct device_node *to,
+-				     const char * const props[],
+-				     struct kfree_table *kft)
+-{
+-	struct property *prop;
+-	int i;
+-
+-	for (i = 0; props[i]; i++) {
+-		prop = of_find_property(from, props[i], NULL);
+-		if (!prop)
+-			continue;
+-
+-		prop = tilcdc_prop_dup(prop, kft);
+-		if (!prop)
+-			continue;
+-
+-		prop->next = to->properties;
+-		to->properties = prop;
+-	}
+-}
+-
+-static int __init tilcdc_prop_str_update(struct property *prop,
+-					  const char *str,
+-					  struct kfree_table *kft)
+-{
+-	prop->value = kstrdup(str, GFP_KERNEL);
+-	if (kfree_table_add(kft, prop->value) || !prop->value)
+-		return -ENOMEM;
+-	prop->length = strlen(str)+1;
+-	return 0;
+-}
+-
+-static void __init tilcdc_node_disable(struct device_node *node)
+-{
+-	struct property *prop;
+-
+-	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+-	if (!prop)
+-		return;
+-
+-	prop->name = "status";
+-	prop->value = "disabled";
+-	prop->length = strlen((char *)prop->value)+1;
+-
+-	of_update_property(node, prop);
+-}
+-
+-static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
+-{
+-	const int size = __dtb_tilcdc_slave_compat_end -
+-		__dtb_tilcdc_slave_compat_begin;
+-	static void *overlay_data;
+-	struct device_node *overlay;
+-
+-	if (!size) {
+-		pr_warn("%s: No overlay data\n", __func__);
+-		return NULL;
+-	}
+-
+-	overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin,
+-			       size, GFP_KERNEL);
+-	if (!overlay_data || kfree_table_add(kft, overlay_data))
+-		return NULL;
+-
+-	of_fdt_unflatten_tree(overlay_data, NULL, &overlay);
+-	if (!overlay) {
+-		pr_warn("%s: Unfattening overlay tree failed\n", __func__);
+-		return NULL;
+-	}
+-
+-	ret = of_resolve_phandles(overlay);
+-	if (ret) {
+-		pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret);
+-		return NULL;
+-	}
+-
+-	return overlay;
+-}
+-
+-static const struct of_device_id tilcdc_slave_of_match[] __initconst = {
+-	{ .compatible = "ti,tilcdc,slave", },
+-	{},
+-};
+-
+-static const struct of_device_id tilcdc_of_match[] __initconst = {
+-	{ .compatible = "ti,am33xx-tilcdc", },
+-	{},
+-};
+-
+-static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = {
+-	{ .compatible = "nxp,tda998x", },
+-	{},
+-};
+-
+-static const char * const tilcdc_slave_props[] __initconst = {
+-	"pinctrl-names",
+-	"pinctrl-0",
+-	"pinctrl-1",
+-	NULL
+-};
+-
+-static void __init tilcdc_convert_slave_node(void)
+-{
+-	struct device_node *slave = NULL, *lcdc = NULL;
+-	struct device_node *i2c = NULL, *fragment = NULL;
+-	struct device_node *overlay, *encoder;
+-	struct property *prop;
+-	/* For all memory needed for the overlay tree. This memory can
+-	   be freed after the overlay has been applied. */
+-	struct kfree_table kft;
+-	int ovcs_id, ret;
+-
+-	if (kfree_table_init(&kft))
+-		return;
+-
+-	lcdc = of_find_matching_node(NULL, tilcdc_of_match);
+-	slave = of_find_matching_node(NULL, tilcdc_slave_of_match);
+-
+-	if (!slave || !of_device_is_available(lcdc))
+-		goto out;
+-
+-	i2c = of_parse_phandle(slave, "i2c", 0);
+-	if (!i2c) {
+-		pr_err("%s: Can't find i2c node trough phandle\n", __func__);
+-		goto out;
+-	}
+-
+-	overlay = tilcdc_get_overlay(&kft);
+-	if (!overlay)
+-		goto out;
+-
+-	encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match);
+-	if (!encoder) {
+-		pr_err("%s: Failed to find tda998x node\n", __func__);
+-		goto out;
+-	}
+-
+-	tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft);
+-
+-	for_each_child_of_node(overlay, fragment) {
+-		prop = of_find_property(fragment, "target-path", NULL);
+-		if (!prop)
+-			continue;
+-		if (!strncmp("i2c", (char *)prop->value, prop->length))
+-			if (tilcdc_prop_str_update(prop, i2c->full_name, &kft))
+-				goto out;
+-		if (!strncmp("lcdc", (char *)prop->value, prop->length))
+-			if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft))
+-				goto out;
+-	}
+-
+-	tilcdc_node_disable(slave);
+-
+-	ovcs_id = 0;
+-	ret = of_overlay_apply(overlay, &ovcs_id);
+-	if (ret)
+-		pr_err("%s: Applying overlay changeset failed: %d\n",
+-			__func__, ret);
+-	else
+-		pr_info("%s: ti,tilcdc,slave node successfully converted\n",
+-			__func__);
+-out:
+-	kfree_table_free(&kft);
+-	of_node_put(i2c);
+-	of_node_put(slave);
+-	of_node_put(lcdc);
+-	of_node_put(fragment);
+-}
+-
+-static int __init tilcdc_slave_compat_init(void)
+-{
+-	tilcdc_convert_slave_node();
+-	return 0;
+-}
+-
+-subsys_initcall(tilcdc_slave_compat_init);
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
+deleted file mode 100644
+index 693f8b0aea2d..000000000000
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
++++ /dev/null
+@@ -1,72 +0,0 @@
+-/*
+- * DTS overlay for converting ti,tilcdc,slave binding to new binding.
+- *
+- * Copyright (C) 2015 Texas Instruments Inc.
+- * Author: Jyri Sarha <jsarha@ti.com>
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+- */
+-
+-/*
+- * target-path property values are simple tags that are replaced with
+- * correct values in tildcdc_slave_compat.c. Some properties are also
+- * copied over from the ti,tilcdc,slave node.
+- */
+-
+-/dts-v1/;
+-/ {
+-	fragment@0 {
+-		target-path = "i2c";
+-		__overlay__ {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			tda19988 {
+-				compatible = "nxp,tda998x";
+-				reg = <0x70>;
+-				status = "okay";
+-
+-				port {
+-					hdmi_0: endpoint@0 {
+-						remote-endpoint = <&lcd_0>;
+-					};
+-				};
+-			};
+-		};
+-	};
+-
+-	fragment@1 {
+-		target-path = "lcdc";
+-		__overlay__ {
+-			port {
+-				lcd_0: endpoint@0 {
+-					remote-endpoint = <&hdmi_0>;
+-				};
+-			};
+-		};
+-	};
+-
+-	__local_fixups__ {
+-		fragment@0 {
+-			__overlay__ {
+-				tda19988 {
+-					port {
+-						endpoint@0 {
+-							remote-endpoint	= <0>;
+-						};
+-					};
+-				};
+-			};
+-		};
+-		fragment@1 {
+-			__overlay__ {
+-				port {
+-					endpoint@0 {
+-						remote-endpoint	= <0>;
+-					};
+-				};
+-			};
+-		};
+-	};
+-};
+diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
+deleted file mode 100644
+index 403d35d87d0b..000000000000
+--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
++++ /dev/null
+@@ -1,25 +0,0 @@
+-/*
+- * Copyright (C) 2015 Texas Instruments
+- * Author: Jyri Sarha <jsarha@ti.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+- */
+-/* This header declares the symbols defined in tilcdc_slave_compat.dts */
+-
+-#ifndef __TILCDC_SLAVE_COMPAT_H__
+-#define __TILCDC_SLAVE_COMPAT_H__
+-
+-extern uint8_t __dtb_tilcdc_slave_compat_begin[];
+-extern uint8_t __dtb_tilcdc_slave_compat_end[];
+-
+-#endif /* __TILCDC_SLAVE_COMPAT_H__ */
+-- 
+2.19.0
+
diff --git a/patches/0933-of-unittest-refactor-Makefile.patch b/patches/0933-of-unittest-refactor-Makefile.patch
new file mode 100644
index 00000000000000..728a1503de7c3c
--- /dev/null
+++ b/patches/0933-of-unittest-refactor-Makefile.patch
@@ -0,0 +1,59 @@
+From c0ee7d8abea05b07a0f3217d003bc6f406d1c080 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Fri, 5 Jan 2018 20:55:30 +0900
+Subject: [PATCH 0933/1795] of: unittest: refactor Makefile
+
+Some cleanups:
+ - use obj-$(CONFIG_OF_OVERLAY) instead of ifdef ... endif
+ - compute targets from obj-y
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit bd6dc70b62bb99d257a3ef39840fd89bf98bc0dd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/unittest-data/Makefile | 19 +++++--------------
+ 1 file changed, 5 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/of/unittest-data/Makefile b/drivers/of/unittest-data/Makefile
+index 3031fc2f18f6..8a723c37a33d 100644
+--- a/drivers/of/unittest-data/Makefile
++++ b/drivers/of/unittest-data/Makefile
+@@ -1,19 +1,12 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y += testcases.dtb.o
+ 
+-targets += testcases.dtb testcases.dtb.S
++obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \
++			    overlay_bad_phandle.dtb.o \
++			    overlay_bad_symbol.dtb.o \
++			    overlay_base.dtb.o
+ 
+-ifdef CONFIG_OF_OVERLAY
+-
+-obj-y += overlay.dtb.o
+-obj-y += overlay_bad_phandle.dtb.o
+-obj-y += overlay_bad_symbol.dtb.o
+-obj-y += overlay_base.dtb.o
+-
+-targets += overlay.dtb overlay.dtb.S
+-targets += overlay_bad_phandle.dtb overlay_bad_phandle.dtb.S
+-targets += overlay_bad_symbol.dtb overlay_bad_symbol.dtb.S
+-targets += overlay_base.dtb overlay_base.dtb.S
++targets += $(foreach suffix, dtb dtb.S, $(patsubst %.dtb.o,%.$(suffix),$(obj-y)))
+ 
+ # enable creation of __symbols__ node
+ DTC_FLAGS_overlay := -@
+@@ -21,8 +14,6 @@ DTC_FLAGS_overlay_bad_phandle := -@
+ DTC_FLAGS_overlay_bad_symbol := -@
+ DTC_FLAGS_overlay_base := -@
+ 
+-endif
+-
+ .PRECIOUS: \
+ 	$(obj)/%.dtb.S \
+ 	$(obj)/%.dtb
+-- 
+2.19.0
+
diff --git a/patches/0934-of-fdt-use-memblock_virt_alloc-for-early-alloc.patch b/patches/0934-of-fdt-use-memblock_virt_alloc-for-early-alloc.patch
new file mode 100644
index 00000000000000..c6dcd9d6ecdafe
--- /dev/null
+++ b/patches/0934-of-fdt-use-memblock_virt_alloc-for-early-alloc.patch
@@ -0,0 +1,133 @@
+From 2df3f70135941bda49c7355d4ae43e34c8fa73ab Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Fri, 5 Jan 2018 15:32:33 -0600
+Subject: [PATCH 0934/1795] of/fdt: use memblock_virt_alloc for early alloc
+
+memblock_virt_alloc() works for both memblock and bootmem, so use it and
+make early_init_dt_alloc_memory_arch a static function. The arches using
+bootmem define early_init_dt_alloc_memory_arch as either:
+
+__alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS))
+
+or:
+
+alloc_bootmem_align(size, align)
+
+Both of these evaluate to the same thing as does memblock_virt_alloc for
+bootmem. So we can disable the arch specific functions by making
+early_init_dt_alloc_memory_arch static and they can be removed in
+subsequent commits.
+
+Cc: Frank Rowand <frowand.list@gmail.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 0fa1c579349fdd90173381712ad78aa99c09d38b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/fdt.c       | 16 ++++------------
+ drivers/of/unittest.c  | 11 ++++++++---
+ include/linux/of_fdt.h |  1 -
+ 3 files changed, 12 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
+index 6337c394bfe3..13df2aeb9ac7 100644
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -14,6 +14,7 @@
+ #include <linux/crc32.h>
+ #include <linux/kernel.h>
+ #include <linux/initrd.h>
++#include <linux/bootmem.h>
+ #include <linux/memblock.h>
+ #include <linux/mutex.h>
+ #include <linux/of.h>
+@@ -1217,14 +1218,6 @@ int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base,
+ 	return memblock_reserve(base, size);
+ }
+ 
+-/*
+- * called from unflatten_device_tree() to bootstrap devicetree itself
+- * Architectures can override this definition if memblock isn't used
+- */
+-void * __init __weak early_init_dt_alloc_memory_arch(u64 size, u64 align)
+-{
+-	return __va(memblock_alloc(size, align));
+-}
+ #else
+ void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
+ {
+@@ -1243,13 +1236,12 @@ int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base,
+ 		  &base, &size, nomap ? " (nomap)" : "");
+ 	return -ENOSYS;
+ }
++#endif
+ 
+-void * __init __weak early_init_dt_alloc_memory_arch(u64 size, u64 align)
++static void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+ {
+-	WARN_ON(1);
+-	return NULL;
++	return memblock_virt_alloc(size, align);
+ }
+-#endif
+ 
+ bool __init early_init_dt_verify(void *params)
+ {
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index 842097fe4064..f71a222a6654 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -5,6 +5,7 @@
+ 
+ #define pr_fmt(fmt) "### dt-test ### " fmt
+ 
++#include <linux/bootmem.h>
+ #include <linux/clk.h>
+ #include <linux/err.h>
+ #include <linux/errno.h>
+@@ -2053,6 +2054,11 @@ static struct overlay_info overlays[] = {
+ 
+ static struct device_node *overlay_base_root;
+ 
++static void * __init dt_alloc_memory(u64 size, u64 align)
++{
++	return memblock_virt_alloc(size, align);
++}
++
+ /*
+  * Create base device tree for the overlay unittest.
+  *
+@@ -2092,8 +2098,7 @@ void __init unittest_unflatten_overlay_base(void)
+ 		return;
+ 	}
+ 
+-	info->data = early_init_dt_alloc_memory_arch(size,
+-					     roundup_pow_of_two(FDT_V17_SIZE));
++	info->data = dt_alloc_memory(size, roundup_pow_of_two(FDT_V17_SIZE));
+ 	if (!info->data) {
+ 		pr_err("alloc for dtb 'overlay_base' failed");
+ 		return;
+@@ -2102,7 +2107,7 @@ void __init unittest_unflatten_overlay_base(void)
+ 	memcpy(info->data, info->dtb_begin, size);
+ 
+ 	__unflatten_device_tree(info->data, NULL, &info->np_overlay,
+-				early_init_dt_alloc_memory_arch, true);
++				dt_alloc_memory, true);
+ 	overlay_base_root = info->np_overlay;
+ }
+ 
+diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h
+index 013c5418aeec..f3d34619bd26 100644
+--- a/include/linux/of_fdt.h
++++ b/include/linux/of_fdt.h
+@@ -77,7 +77,6 @@ extern void early_init_dt_add_memory_arch(u64 base, u64 size);
+ extern int early_init_dt_mark_hotplug_memory_arch(u64 base, u64 size);
+ extern int early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size,
+ 					     bool no_map);
+-extern void * early_init_dt_alloc_memory_arch(u64 size, u64 align);
+ extern u64 dt_mem_next_cell(int s, const __be32 **cellp);
+ 
+ /* Early flat tree scan hooks */
+-- 
+2.19.0
+
diff --git a/patches/0935-of-fdt-Fix-ifdef-dependency-of-early-flattree-declar.patch b/patches/0935-of-fdt-Fix-ifdef-dependency-of-early-flattree-declar.patch
new file mode 100644
index 00000000000000..c745978c22f32c
--- /dev/null
+++ b/patches/0935-of-fdt-Fix-ifdef-dependency-of-early-flattree-declar.patch
@@ -0,0 +1,62 @@
+From c1ac3852d55e4434fd68fbe1b28a6c181114e532 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 4 Jan 2018 10:08:36 +0100
+Subject: [PATCH 0935/1795] of/fdt: Fix #ifdef dependency of early flattree
+ declarations
+
+If OF_FLATTREE=y, but OF_EARLY_FLATTREE=n:
+
+    drivers/tty/serial/earlycon.o: In function `param_setup_earlycon':
+    earlycon.c:(.init.text+0x3a4): undefined reference to `early_init_dt_scan_chosen_stdout'
+
+Fix this by moving the early flattree forward declarations and dummy
+implementations inside an #ifdef CONFIG_OF_EARLY_FLATTREE block.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit f347c36701339d55de15e01a3d392c0c3cd289f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/of_fdt.h | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h
+index f3d34619bd26..02c05028d0ba 100644
+--- a/include/linux/of_fdt.h
++++ b/include/linux/of_fdt.h
+@@ -47,6 +47,12 @@ extern void *initial_boot_params;
+ extern char __dtb_start[];
+ extern char __dtb_end[];
+ 
++/* Other Prototypes */
++extern u64 of_flat_dt_translate_address(unsigned long node);
++extern void of_fdt_limit_memory(int limit);
++#endif /* CONFIG_OF_FLATTREE */
++
++#ifdef CONFIG_OF_EARLY_FLATTREE
+ /* For scanning the flat device-tree at boot time */
+ extern int of_scan_flat_dt(int (*it)(unsigned long node, const char *uname,
+ 				     int depth, void *data),
+@@ -96,16 +102,14 @@ extern void unflatten_device_tree(void);
+ extern void unflatten_and_copy_device_tree(void);
+ extern void early_init_devtree(void *);
+ extern void early_get_first_memblock_info(void *, phys_addr_t *);
+-extern u64 of_flat_dt_translate_address(unsigned long node);
+-extern void of_fdt_limit_memory(int limit);
+-#else /* CONFIG_OF_FLATTREE */
++#else /* CONFIG_OF_EARLY_FLATTREE */
+ static inline int early_init_dt_scan_chosen_stdout(void) { return -ENODEV; }
+ static inline void early_init_fdt_scan_reserved_mem(void) {}
+ static inline void early_init_fdt_reserve_self(void) {}
+ static inline const char *of_flat_dt_get_machine_name(void) { return NULL; }
+ static inline void unflatten_device_tree(void) {}
+ static inline void unflatten_and_copy_device_tree(void) {}
+-#endif /* CONFIG_OF_FLATTREE */
++#endif /* CONFIG_OF_EARLY_FLATTREE */
+ 
+ #endif /* __ASSEMBLY__ */
+ #endif /* _LINUX_OF_FDT_H */
+-- 
+2.19.0
+
diff --git a/patches/0936-of-change-overlay-apply-input-data-from-unflattened-.patch b/patches/0936-of-change-overlay-apply-input-data-from-unflattened-.patch
new file mode 100644
index 00000000000000..9faff175b84a79
--- /dev/null
+++ b/patches/0936-of-change-overlay-apply-input-data-from-unflattened-.patch
@@ -0,0 +1,1674 @@
+From 146dedc90bbc6e7b9e4f171264f6572caa17b2e7 Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Mon, 12 Feb 2018 00:19:42 -0800
+Subject: [PATCH 0936/1795] of: change overlay apply input data from
+ unflattened to FDT
+
+Move duplicating and unflattening of an overlay flattened devicetree
+(FDT) into the overlay application code.  To accomplish this,
+of_overlay_apply() is replaced by of_overlay_fdt_apply().
+
+The copy of the FDT (aka "duplicate FDT") now belongs to devicetree
+code, which is thus responsible for freeing the duplicate FDT.  The
+caller of of_overlay_fdt_apply() remains responsible for freeing the
+original FDT.
+
+The unflattened devicetree now belongs to devicetree code, which is
+thus responsible for freeing the unflattened devicetree.
+
+These ownership changes prevent early freeing of the duplicated FDT
+or the unflattened devicetree, which could result in use after free
+errors.
+
+of_overlay_fdt_apply() is a private function for the anticipated
+overlay loader.
+
+Update unittest.c to use of_overlay_fdt_apply() instead of
+of_overlay_apply().
+
+Move overlay fragments from artificial locations in
+drivers/of/unittest-data/tests-overlay.dtsi into one devicetree
+source file per overlay.  This led to changes in
+drivers/of/unitest-data/Makefile and drivers/of/unitest.c.
+
+  - Add overlay directives to the overlay devicetree source files so
+    that dtc will compile them as true overlays into one FDT data
+    chunk per overlay.
+
+  - Set CFLAGS for drivers/of/unittest-data/testcases.dts so that
+    symbols will be generated for overlay resolution of overlays
+    that are no longer artificially contained in testcases.dts
+
+  - Unflatten and apply each unittest overlay FDT using
+    of_overlay_fdt_apply().
+
+  - Enable the of_resolve_phandles() check for whether the unflattened
+    overlay is detached.  This check was previously disabled because the
+    overlays from tests-overlay.dtsi were not unflattened into detached
+    trees.
+
+  - Other changes to unittest.c infrastructure to manage multiple test
+    FDTs built into the kernel image (access by name instead of
+    arbitrary number).
+
+  - of_unittest_overlay_high_level(): previously unused code to add
+    properties from the overlay_base devicetree to the live tree
+    was triggered by the restructuring of tests-overlay.dtsi and thus
+    testcases.dts.  This exposed two bugs: (1) the need to dup a
+    property before adding it, and (2) property 'name' is
+    auto-generated in the unflatten code and thus will be a duplicate
+    in the __symbols__ node - do not treat this duplicate as an error.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+(cherry picked from commit 39a751a4cb7e4798f0ce1169ec92de4a1aae39e3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/of/unittest.c
+	drivers/of/unittest-data/Makefile
+---
+ drivers/of/Kconfig                          |   1 +
+ drivers/of/overlay.c                        | 112 +++++++-
+ drivers/of/resolver.c                       |   6 -
+ drivers/of/unittest-data/Makefile           |  24 +-
+ drivers/of/unittest-data/overlay_0.dts      |  14 +
+ drivers/of/unittest-data/overlay_1.dts      |  14 +
+ drivers/of/unittest-data/overlay_10.dts     |  34 +++
+ drivers/of/unittest-data/overlay_11.dts     |  34 +++
+ drivers/of/unittest-data/overlay_12.dts     |  14 +
+ drivers/of/unittest-data/overlay_13.dts     |  14 +
+ drivers/of/unittest-data/overlay_15.dts     |  35 +++
+ drivers/of/unittest-data/overlay_2.dts      |  14 +
+ drivers/of/unittest-data/overlay_3.dts      |  14 +
+ drivers/of/unittest-data/overlay_4.dts      |  23 ++
+ drivers/of/unittest-data/overlay_5.dts      |  14 +
+ drivers/of/unittest-data/overlay_6.dts      |  15 +
+ drivers/of/unittest-data/overlay_7.dts      |  15 +
+ drivers/of/unittest-data/overlay_8.dts      |  15 +
+ drivers/of/unittest-data/overlay_9.dts      |  15 +
+ drivers/of/unittest-data/tests-overlay.dtsi | 213 --------------
+ drivers/of/unittest.c                       | 301 ++++++++++----------
+ include/linux/of.h                          |   6 +-
+ 22 files changed, 559 insertions(+), 388 deletions(-)
+ create mode 100644 drivers/of/unittest-data/overlay_0.dts
+ create mode 100644 drivers/of/unittest-data/overlay_1.dts
+ create mode 100644 drivers/of/unittest-data/overlay_10.dts
+ create mode 100644 drivers/of/unittest-data/overlay_11.dts
+ create mode 100644 drivers/of/unittest-data/overlay_12.dts
+ create mode 100644 drivers/of/unittest-data/overlay_13.dts
+ create mode 100644 drivers/of/unittest-data/overlay_15.dts
+ create mode 100644 drivers/of/unittest-data/overlay_2.dts
+ create mode 100644 drivers/of/unittest-data/overlay_3.dts
+ create mode 100644 drivers/of/unittest-data/overlay_4.dts
+ create mode 100644 drivers/of/unittest-data/overlay_5.dts
+ create mode 100644 drivers/of/unittest-data/overlay_6.dts
+ create mode 100644 drivers/of/unittest-data/overlay_7.dts
+ create mode 100644 drivers/of/unittest-data/overlay_8.dts
+ create mode 100644 drivers/of/unittest-data/overlay_9.dts
+
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index ba7b034b2b91..c60c485d04b7 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -102,6 +102,7 @@ config OF_RESOLVE
+ config OF_OVERLAY
+ 	bool "Device Tree overlays"
+ 	select OF_DYNAMIC
++	select OF_FLATTREE
+ 	select OF_RESOLVE
+ 	help
+ 	  Overlays are a method to dynamically modify part of the kernel's
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 3981b7da4fa9..585a5de1e329 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -15,10 +15,12 @@
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/of_fdt.h>
+ #include <linux/string.h>
+ #include <linux/ctype.h>
+ #include <linux/errno.h>
+ #include <linux/slab.h>
++#include <linux/libfdt.h>
+ #include <linux/err.h>
+ #include <linux/idr.h>
+ 
+@@ -36,7 +38,9 @@ struct fragment {
+ 
+ /**
+  * struct overlay_changeset
++ * @id:			changeset identifier
+  * @ovcs_list:		list on which we are located
++ * @fdt:		FDT that was unflattened to create @overlay_tree
+  * @overlay_tree:	expanded device tree that contains the fragment nodes
+  * @count:		count of fragment structures
+  * @fragments:		fragment nodes in the overlay expanded device tree
+@@ -46,6 +50,7 @@ struct fragment {
+ struct overlay_changeset {
+ 	int id;
+ 	struct list_head ovcs_list;
++	const void *fdt;
+ 	struct device_node *overlay_tree;
+ 	int count;
+ 	struct fragment *fragments;
+@@ -506,7 +511,8 @@ static struct device_node *find_target_node(struct device_node *info_node)
+ 
+ /**
+  * init_overlay_changeset() - initialize overlay changeset from overlay tree
+- * @ovcs	Overlay changeset to build
++ * @ovcs:	Overlay changeset to build
++ * @fdt:	the FDT that was unflattened to create @tree
+  * @tree:	Contains all the overlay fragments and overlay fixup nodes
+  *
+  * Initialize @ovcs.  Populate @ovcs->fragments with node information from
+@@ -517,7 +523,7 @@ static struct device_node *find_target_node(struct device_node *info_node)
+  * detected in @tree, or -ENOSPC if idr_alloc() error.
+  */
+ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+-		struct device_node *tree)
++		const void *fdt, struct device_node *tree)
+ {
+ 	struct device_node *node, *overlay_node;
+ 	struct fragment *fragment;
+@@ -538,6 +544,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 		pr_debug("%s() tree is not root\n", __func__);
+ 
+ 	ovcs->overlay_tree = tree;
++	ovcs->fdt = fdt;
+ 
+ 	INIT_LIST_HEAD(&ovcs->ovcs_list);
+ 
+@@ -609,6 +616,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
+ 	}
+ 
+ 	if (!cnt) {
++		pr_err("no fragments or symbols in overlay\n");
+ 		ret = -EINVAL;
+ 		goto err_free_fragments;
+ 	}
+@@ -645,11 +653,24 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+ 	}
+ 	kfree(ovcs->fragments);
+ 
++	/*
++	 * TODO
++	 *
++	 * would like to: kfree(ovcs->overlay_tree);
++	 * but can not since drivers may have pointers into this data
++	 *
++	 * would like to: kfree(ovcs->fdt);
++	 * but can not since drivers may have pointers into this data
++	 */
++
+ 	kfree(ovcs);
+ }
+ 
+-/**
++/*
++ * internal documentation
++ *
+  * of_overlay_apply() - Create and apply an overlay changeset
++ * @fdt:	the FDT that was unflattened to create @tree
+  * @tree:	Expanded overlay device tree
+  * @ovcs_id:	Pointer to overlay changeset id
+  *
+@@ -688,21 +709,29 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+  * id is returned to *ovcs_id.
+  */
+ 
+-int of_overlay_apply(struct device_node *tree, int *ovcs_id)
++static int of_overlay_apply(const void *fdt, struct device_node *tree,
++		int *ovcs_id)
+ {
+ 	struct overlay_changeset *ovcs;
+ 	int ret = 0, ret_revert, ret_tmp;
+ 
+-	*ovcs_id = 0;
++	/*
++	 * As of this point, fdt and tree belong to the overlay changeset.
++	 * overlay changeset code is responsible for freeing them.
++	 */
+ 
+ 	if (devicetree_corrupt()) {
+ 		pr_err("devicetree state suspect, refuse to apply overlay\n");
++		kfree(fdt);
++		kfree(tree);
+ 		ret = -EBUSY;
+ 		goto out;
+ 	}
+ 
+ 	ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
+ 	if (!ovcs) {
++		kfree(fdt);
++		kfree(tree);
+ 		ret = -ENOMEM;
+ 		goto out;
+ 	}
+@@ -712,12 +741,17 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 
+ 	ret = of_resolve_phandles(tree);
+ 	if (ret)
+-		goto err_free_overlay_changeset;
++		goto err_free_tree;
+ 
+-	ret = init_overlay_changeset(ovcs, tree);
++	ret = init_overlay_changeset(ovcs, fdt, tree);
+ 	if (ret)
+-		goto err_free_overlay_changeset;
++		goto err_free_tree;
+ 
++	/*
++	 * after overlay_notify(), ovcs->overlay_tree related pointers may have
++	 * leaked to drivers, so can not kfree() tree, aka ovcs->overlay_tree;
++	 * and can not free fdt, aka ovcs->fdt
++	 */
+ 	ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY);
+ 	if (ret) {
+ 		pr_err("overlay changeset pre-apply notify error %d\n", ret);
+@@ -757,6 +791,10 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 
+ 	goto out_unlock;
+ 
++err_free_tree:
++	kfree(fdt);
++	kfree(tree);
++
+ err_free_overlay_changeset:
+ 	free_overlay_changeset(ovcs);
+ 
+@@ -769,7 +807,63 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id)
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL_GPL(of_overlay_apply);
++
++int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size,
++			 int *ovcs_id)
++{
++	const void *new_fdt;
++	int ret;
++	u32 size;
++	struct device_node *overlay_root;
++
++	*ovcs_id = 0;
++	ret = 0;
++
++	if (overlay_fdt_size < sizeof(struct fdt_header) ||
++	    fdt_check_header(overlay_fdt)) {
++		pr_err("Invalid overlay_fdt header\n");
++		return -EINVAL;
++	}
++
++	size = fdt_totalsize(overlay_fdt);
++	if (overlay_fdt_size < size)
++		return -EINVAL;
++
++	/*
++	 * Must create permanent copy of FDT because of_fdt_unflatten_tree()
++	 * will create pointers to the passed in FDT in the unflattened tree.
++	 */
++	new_fdt = kmemdup(overlay_fdt, size, GFP_KERNEL);
++	if (!new_fdt)
++		return -ENOMEM;
++
++	of_fdt_unflatten_tree(new_fdt, NULL, &overlay_root);
++	if (!overlay_root) {
++		pr_err("unable to unflatten overlay_fdt\n");
++		ret = -EINVAL;
++		goto out_free_new_fdt;
++	}
++
++	ret = of_overlay_apply(new_fdt, overlay_root, ovcs_id);
++	if (ret < 0) {
++		/*
++		 * new_fdt and overlay_root now belong to the overlay
++		 * changeset.
++		 * overlay changeset code is responsible for freeing them.
++		 */
++		goto out;
++	}
++
++	return 0;
++
++
++out_free_new_fdt:
++	kfree(new_fdt);
++
++out:
++	return ret;
++}
++EXPORT_SYMBOL_GPL(of_overlay_fdt_apply);
+ 
+ /*
+  * Find @np in @tree.
+diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
+index f69fd3911160..5a05c08a8a88 100644
+--- a/drivers/of/resolver.c
++++ b/drivers/of/resolver.c
+@@ -281,17 +281,11 @@ int of_resolve_phandles(struct device_node *overlay)
+ 		goto out;
+ 	}
+ 
+-#if 0
+-	Temporarily disable check so that old style overlay unittests
+-	do not fail when of_resolve_phandles() is moved into
+-	of_overlay_apply().
+-
+ 	if (!of_node_check_flag(overlay, OF_DETACHED)) {
+ 		pr_err("overlay not detached\n");
+ 		err = -EINVAL;
+ 		goto out;
+ 	}
+-#endif
+ 
+ 	phandle_delta = live_tree_max_phandle() + 1;
+ 	adjust_overlay_phandles(overlay, phandle_delta);
+diff --git a/drivers/of/unittest-data/Makefile b/drivers/of/unittest-data/Makefile
+index 8a723c37a33d..d091609f4bef 100644
+--- a/drivers/of/unittest-data/Makefile
++++ b/drivers/of/unittest-data/Makefile
+@@ -2,6 +2,21 @@
+ obj-y += testcases.dtb.o
+ 
+ obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \
++			    overlay_0.dtb.o \
++			    overlay_1.dtb.o \
++			    overlay_2.dtb.o \
++			    overlay_3.dtb.o \
++			    overlay_4.dtb.o \
++			    overlay_5.dtb.o \
++			    overlay_6.dtb.o \
++			    overlay_7.dtb.o \
++			    overlay_8.dtb.o \
++			    overlay_9.dtb.o \
++			    overlay_10.dtb.o \
++			    overlay_11.dtb.o \
++			    overlay_12.dtb.o \
++			    overlay_13.dtb.o \
++			    overlay_15.dtb.o \
+ 			    overlay_bad_phandle.dtb.o \
+ 			    overlay_bad_symbol.dtb.o \
+ 			    overlay_base.dtb.o
+@@ -9,10 +24,11 @@ obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \
+ targets += $(foreach suffix, dtb dtb.S, $(patsubst %.dtb.o,%.$(suffix),$(obj-y)))
+ 
+ # enable creation of __symbols__ node
+-DTC_FLAGS_overlay := -@
+-DTC_FLAGS_overlay_bad_phandle := -@
+-DTC_FLAGS_overlay_bad_symbol := -@
+-DTC_FLAGS_overlay_base := -@
++DTC_FLAGS_overlay += -@
++DTC_FLAGS_overlay_bad_phandle += -@
++DTC_FLAGS_overlay_bad_symbol += -@
++DTC_FLAGS_overlay_base += -@
++DTC_FLAGS_testcases += -@
+ 
+ .PRECIOUS: \
+ 	$(obj)/%.dtb.S \
+diff --git a/drivers/of/unittest-data/overlay_0.dts b/drivers/of/unittest-data/overlay_0.dts
+new file mode 100644
+index 000000000000..ac0f9e0fe65f
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_0.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_0 - enable using absolute target path */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest0";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_1.dts b/drivers/of/unittest-data/overlay_1.dts
+new file mode 100644
+index 000000000000..e92a626e2948
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_1.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_1 - disable using absolute target path */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest1";
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_10.dts b/drivers/of/unittest-data/overlay_10.dts
+new file mode 100644
+index 000000000000..445925a10cd3
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_10.dts
+@@ -0,0 +1,34 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_10 */
++	/* overlays 8, 9, 10, 11 application and removal in bad sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus";
++		__overlay__ {
++
++			/* suppress DTC warning */
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			test-unittest10 {
++				compatible = "unittest";
++				status = "okay";
++				reg = <10>;
++
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				test-unittest101 {
++					compatible = "unittest";
++					status = "okay";
++					reg = <1>;
++				};
++
++			};
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_11.dts b/drivers/of/unittest-data/overlay_11.dts
+new file mode 100644
+index 000000000000..c1d14f34359e
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_11.dts
+@@ -0,0 +1,34 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_11 */
++	/* overlays 8, 9, 10, 11 application and removal in bad sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus";
++		__overlay__ {
++
++			/* suppress DTC warning */
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			test-unittest11 {
++				compatible = "unittest";
++				status = "okay";
++				reg = <11>;
++
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				test-unittest111 {
++					compatible = "unittest";
++					status = "okay";
++					reg = <1>;
++				};
++
++			};
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_12.dts b/drivers/of/unittest-data/overlay_12.dts
+new file mode 100644
+index 000000000000..ca3441e2cbec
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_12.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_12 - enable using absolute target path (i2c) */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_13.dts b/drivers/of/unittest-data/overlay_13.dts
+new file mode 100644
+index 000000000000..3c30dec63894
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_13.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_13 - disable using absolute target path (i2c) */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13";
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_15.dts b/drivers/of/unittest-data/overlay_15.dts
+new file mode 100644
+index 000000000000..44e44c62b739
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_15.dts
+@@ -0,0 +1,35 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_15 - mux overlay */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus";
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			test-unittest15 {
++				reg = <11>;
++				compatible = "unittest-i2c-mux";
++				status = "okay";
++
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				i2c@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					test-mux-dev {
++						reg = <32>;
++						compatible = "unittest-i2c-dev";
++						status = "okay";
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_2.dts b/drivers/of/unittest-data/overlay_2.dts
+new file mode 100644
+index 000000000000..cf1e4245b7ce
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_2.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_2 -  enable using label */
++
++	fragment@0 {
++		target = <&unittest2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_3.dts b/drivers/of/unittest-data/overlay_3.dts
+new file mode 100644
+index 000000000000..158dc44fc20a
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_3.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_3 - disable using label */
++
++	fragment@0 {
++		target = <&unittest3>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_4.dts b/drivers/of/unittest-data/overlay_4.dts
+new file mode 100644
+index 000000000000..b4a2e6c6b016
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_4.dts
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_4 - test insertion of a full node */
++
++	fragment@0 {
++		target = <&unittestbus>;
++		__overlay__ {
++
++			/* suppress DTC warning */
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			test-unittest4 {
++				compatible = "unittest";
++				status = "okay";
++				reg = <4>;
++			};
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_5.dts b/drivers/of/unittest-data/overlay_5.dts
+new file mode 100644
+index 000000000000..02ad25c1f19c
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_5.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_5 - test overlay apply revert */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest5";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_6.dts b/drivers/of/unittest-data/overlay_6.dts
+new file mode 100644
+index 000000000000..a14e965f5497
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_6.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_6 */
++	/* overlays 6, 7 application and removal in sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest6";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_7.dts b/drivers/of/unittest-data/overlay_7.dts
+new file mode 100644
+index 000000000000..4bd7e423209c
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_7.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_7 */
++	/* overlays 6, 7 application and removal in sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest7";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_8.dts b/drivers/of/unittest-data/overlay_8.dts
+new file mode 100644
+index 000000000000..5b21c53945a9
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_8.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_8 */
++	/* overlays 8, 9, 10, 11 application and removal in bad sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest8";
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/overlay_9.dts b/drivers/of/unittest-data/overlay_9.dts
+new file mode 100644
+index 000000000000..20ff055a5349
+--- /dev/null
++++ b/drivers/of/unittest-data/overlay_9.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++/plugin/;
++
++/ {
++	/* overlay_9 */
++	/* overlays 8, 9, 10, 11 application and removal in bad sequence */
++
++	fragment@0 {
++		target-path = "/testcase-data/overlay-node/test-bus/test-unittest8";
++		__overlay__ {
++			property-foo = "bar";
++		};
++	};
++};
+diff --git a/drivers/of/unittest-data/tests-overlay.dtsi b/drivers/of/unittest-data/tests-overlay.dtsi
+index 7b8001ab9f3a..fa2fb43bccac 100644
+--- a/drivers/of/unittest-data/tests-overlay.dtsi
++++ b/drivers/of/unittest-data/tests-overlay.dtsi
+@@ -113,218 +113,5 @@
+ 				};
+ 			};
+ 		};
+-
+-		/* test enable using absolute target path */
+-		overlay0 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest0";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-
+-		/* test disable using absolute target path */
+-		overlay1 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest1";
+-				__overlay__ {
+-					status = "disabled";
+-				};
+-			};
+-		};
+-
+-		/* test enable using label */
+-		overlay2 {
+-			fragment@0 {
+-				target = <&unittest2>;
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-
+-		/* test disable using label */
+-		overlay3 {
+-			fragment@0 {
+-				target = <&unittest3>;
+-				__overlay__ {
+-					status = "disabled";
+-				};
+-			};
+-		};
+-
+-		/* test insertion of a full node */
+-		overlay4 {
+-			fragment@0 {
+-				target = <&unittestbus>;
+-				__overlay__ {
+-
+-					/* suppress DTC warning */
+-					#address-cells = <1>;
+-					#size-cells = <0>;
+-
+-					test-unittest4 {
+-						compatible = "unittest";
+-						status = "okay";
+-						reg = <4>;
+-					};
+-				};
+-			};
+-		};
+-
+-		/* test overlay apply revert */
+-		overlay5 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest5";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-
+-		/* test overlays application and removal in sequence */
+-		overlay6 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest6";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-		overlay7 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest7";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-
+-		/* test overlays application and removal in bad sequence */
+-		overlay8 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest8";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-		overlay9 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/test-unittest8";
+-				__overlay__ {
+-					property-foo = "bar";
+-				};
+-			};
+-		};
+-
+-		overlay10 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus";
+-				__overlay__ {
+-
+-					/* suppress DTC warning */
+-					#address-cells = <1>;
+-					#size-cells = <0>;
+-
+-					test-unittest10 {
+-						compatible = "unittest";
+-						status = "okay";
+-						reg = <10>;
+-
+-						#address-cells = <1>;
+-						#size-cells = <0>;
+-
+-						test-unittest101 {
+-							compatible = "unittest";
+-							status = "okay";
+-							reg = <1>;
+-						};
+-
+-					};
+-				};
+-			};
+-		};
+-
+-		overlay11 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus";
+-				__overlay__ {
+-
+-					/* suppress DTC warning */
+-					#address-cells = <1>;
+-					#size-cells = <0>;
+-
+-					test-unittest11 {
+-						compatible = "unittest";
+-						status = "okay";
+-						reg = <11>;
+-
+-						#address-cells = <1>;
+-						#size-cells = <0>;
+-
+-						test-unittest111 {
+-							compatible = "unittest";
+-							status = "okay";
+-							reg = <1>;
+-						};
+-
+-					};
+-				};
+-			};
+-		};
+-
+-		/* test enable using absolute target path (i2c) */
+-		overlay12 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12";
+-				__overlay__ {
+-					status = "okay";
+-				};
+-			};
+-		};
+-
+-		/* test disable using absolute target path (i2c) */
+-		overlay13 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13";
+-				__overlay__ {
+-					status = "disabled";
+-				};
+-			};
+-		};
+-
+-		/* test mux overlay */
+-		overlay15 {
+-			fragment@0 {
+-				target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus";
+-				__overlay__ {
+-					#address-cells = <1>;
+-					#size-cells = <0>;
+-					test-unittest15 {
+-						reg = <11>;
+-						compatible = "unittest-i2c-mux";
+-						status = "okay";
+-
+-						#address-cells = <1>;
+-						#size-cells = <0>;
+-
+-						i2c@0 {
+-							#address-cells = <1>;
+-							#size-cells = <0>;
+-							reg = <0>;
+-
+-							test-mux-dev {
+-								reg = <32>;
+-								compatible = "unittest-i2c-dev";
+-								status = "okay";
+-							};
+-						};
+-					};
+-				};
+-			};
+-		};
+-
+ 	};
+ };
+diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
+index f71a222a6654..896b81a6d3ca 100644
+--- a/drivers/of/unittest.c
++++ b/drivers/of/unittest.c
+@@ -45,6 +45,8 @@ static struct unittest_results {
+ 	failed; \
+ })
+ 
++static int __init overlay_data_apply(const char *overlay_name, int *overlay_id);
++
+ static void __init of_unittest_find_node_by_name(void)
+ {
+ 	struct device_node *np;
+@@ -997,8 +999,7 @@ static int __init unittest_data_add(void)
+ 	}
+ 
+ 	/*
+-	 * This lock normally encloses of_overlay_apply() as well as
+-	 * of_resolve_phandles().
++	 * This lock normally encloses of_resolve_phandles()
+ 	 */
+ 	of_overlay_mutex_lock();
+ 
+@@ -1191,12 +1192,12 @@ static int of_unittest_device_exists(int unittest_nr, enum overlay_type ovtype)
+ 	return 0;
+ }
+ 
+-static const char *overlay_path(int nr)
++static const char *overlay_name_from_nr(int nr)
+ {
+ 	static char buf[256];
+ 
+ 	snprintf(buf, sizeof(buf) - 1,
+-		"/testcase-data/overlay%d", nr);
++		"overlay_%d", nr);
+ 	buf[sizeof(buf) - 1] = '\0';
+ 
+ 	return buf;
+@@ -1263,25 +1264,19 @@ static void of_unittest_destroy_tracked_overlays(void)
+ 	} while (defers > 0);
+ }
+ 
+-static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
++static int __init of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ 		int *overlay_id)
+ {
+ 	struct device_node *np = NULL;
++	const char *overlay_name;
+ 	int ret;
+ 
+-	np = of_find_node_by_path(overlay_path(overlay_nr));
+-	if (np == NULL) {
+-		unittest(0, "could not find overlay node @\"%s\"\n",
+-				overlay_path(overlay_nr));
+-		ret = -EINVAL;
+-		goto out;
+-	}
++	overlay_name = overlay_name_from_nr(overlay_nr);
+ 
+-	*overlay_id = 0;
+-	ret = of_overlay_apply(np, overlay_id);
+-	if (ret < 0) {
+-		unittest(0, "could not create overlay from \"%s\"\n",
+-				overlay_path(overlay_nr));
++	ret = overlay_data_apply(overlay_name, overlay_id);
++	if (!ret) {
++		unittest(0, "could not apply overlay \"%s\"\n",
++				overlay_name);
+ 		goto out;
+ 	}
+ 	of_unittest_track_overlay(*overlay_id);
+@@ -1295,15 +1290,16 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr,
+ }
+ 
+ /* apply an overlay while checking before and after states */
+-static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr,
+-		int before, int after, enum overlay_type ovtype)
++static int __init of_unittest_apply_overlay_check(int overlay_nr,
++		int unittest_nr, int before, int after,
++		enum overlay_type ovtype)
+ {
+ 	int ret, ovcs_id;
+ 
+ 	/* unittest device must not be in before state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != before) {
+-		unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s with device @\"%s\" %s\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype),
+ 				!before ? "enabled" : "disabled");
+ 		return -EINVAL;
+@@ -1318,8 +1314,8 @@ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr,
+ 
+ 	/* unittest device must be to set to after state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != after) {
+-		unittest(0, "overlay @\"%s\" failed to create @\"%s\" %s\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s failed to create @\"%s\" %s\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype),
+ 				!after ? "enabled" : "disabled");
+ 		return -EINVAL;
+@@ -1329,7 +1325,7 @@ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr,
+ }
+ 
+ /* apply an overlay and then revert it while checking before, after states */
+-static int of_unittest_apply_revert_overlay_check(int overlay_nr,
++static int __init of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 		int unittest_nr, int before, int after,
+ 		enum overlay_type ovtype)
+ {
+@@ -1337,8 +1333,8 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 
+ 	/* unittest device must be in before state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != before) {
+-		unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s with device @\"%s\" %s\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype),
+ 				!before ? "enabled" : "disabled");
+ 		return -EINVAL;
+@@ -1354,8 +1350,8 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 
+ 	/* unittest device must be in after state */
+ 	if (of_unittest_device_exists(unittest_nr, ovtype) != after) {
+-		unittest(0, "overlay @\"%s\" failed to create @\"%s\" %s\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s failed to create @\"%s\" %s\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype),
+ 				!after ? "enabled" : "disabled");
+ 		return -EINVAL;
+@@ -1363,16 +1359,16 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ 
+ 	ret = of_overlay_remove(&ovcs_id);
+ 	if (ret != 0) {
+-		unittest(0, "overlay @\"%s\" failed to be destroyed @\"%s\"\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s failed to be destroyed @\"%s\"\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype));
+ 		return ret;
+ 	}
+ 
+ 	/* unittest device must be again in before state */
+ 	if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) {
+-		unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n",
+-				overlay_path(overlay_nr),
++		unittest(0, "%s with device @\"%s\" %s\n",
++				overlay_name_from_nr(overlay_nr),
+ 				unittest_path(unittest_nr, ovtype),
+ 				!before ? "enabled" : "disabled");
+ 		return -EINVAL;
+@@ -1382,7 +1378,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr,
+ }
+ 
+ /* test activation of device */
+-static void of_unittest_overlay_0(void)
++static void __init of_unittest_overlay_0(void)
+ {
+ 	int ret;
+ 
+@@ -1395,7 +1391,7 @@ static void of_unittest_overlay_0(void)
+ }
+ 
+ /* test deactivation of device */
+-static void of_unittest_overlay_1(void)
++static void __init of_unittest_overlay_1(void)
+ {
+ 	int ret;
+ 
+@@ -1408,7 +1404,7 @@ static void of_unittest_overlay_1(void)
+ }
+ 
+ /* test activation of device */
+-static void of_unittest_overlay_2(void)
++static void __init of_unittest_overlay_2(void)
+ {
+ 	int ret;
+ 
+@@ -1421,7 +1417,7 @@ static void of_unittest_overlay_2(void)
+ }
+ 
+ /* test deactivation of device */
+-static void of_unittest_overlay_3(void)
++static void __init of_unittest_overlay_3(void)
+ {
+ 	int ret;
+ 
+@@ -1434,7 +1430,7 @@ static void of_unittest_overlay_3(void)
+ }
+ 
+ /* test activation of a full device node */
+-static void of_unittest_overlay_4(void)
++static void __init of_unittest_overlay_4(void)
+ {
+ 	int ret;
+ 
+@@ -1447,7 +1443,7 @@ static void of_unittest_overlay_4(void)
+ }
+ 
+ /* test overlay apply/revert sequence */
+-static void of_unittest_overlay_5(void)
++static void __init of_unittest_overlay_5(void)
+ {
+ 	int ret;
+ 
+@@ -1460,19 +1456,19 @@ static void of_unittest_overlay_5(void)
+ }
+ 
+ /* test overlay application in sequence */
+-static void of_unittest_overlay_6(void)
++static void __init of_unittest_overlay_6(void)
+ {
+-	struct device_node *np;
+ 	int ret, i, ov_id[2], ovcs_id;
+ 	int overlay_nr = 6, unittest_nr = 6;
+ 	int before = 0, after = 1;
++	const char *overlay_name;
+ 
+ 	/* unittest device must be in before state */
+ 	for (i = 0; i < 2; i++) {
+ 		if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY)
+ 				!= before) {
+-			unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n",
+-					overlay_path(overlay_nr + i),
++			unittest(0, "%s with device @\"%s\" %s\n",
++					overlay_name_from_nr(overlay_nr + i),
+ 					unittest_path(unittest_nr + i,
+ 						PDEV_OVERLAY),
+ 					!before ? "enabled" : "disabled");
+@@ -1483,18 +1479,12 @@ static void of_unittest_overlay_6(void)
+ 	/* apply the overlays */
+ 	for (i = 0; i < 2; i++) {
+ 
+-		np = of_find_node_by_path(overlay_path(overlay_nr + i));
+-		if (np == NULL) {
+-			unittest(0, "could not find overlay node @\"%s\"\n",
+-					overlay_path(overlay_nr + i));
+-			return;
+-		}
++		overlay_name = overlay_name_from_nr(overlay_nr + i);
+ 
+-		ovcs_id = 0;
+-		ret = of_overlay_apply(np, &ovcs_id);
+-		if (ret < 0)  {
+-			unittest(0, "could not create overlay from \"%s\"\n",
+-					overlay_path(overlay_nr + i));
++		ret = overlay_data_apply(overlay_name, &ovcs_id);
++		if (!ret)  {
++			unittest(0, "could not apply overlay \"%s\"\n",
++					overlay_name);
+ 			return;
+ 		}
+ 		ov_id[i] = ovcs_id;
+@@ -1506,7 +1496,7 @@ static void of_unittest_overlay_6(void)
+ 		if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY)
+ 				!= after) {
+ 			unittest(0, "overlay @\"%s\" failed @\"%s\" %s\n",
+-					overlay_path(overlay_nr + i),
++					overlay_name_from_nr(overlay_nr + i),
+ 					unittest_path(unittest_nr + i,
+ 						PDEV_OVERLAY),
+ 					!after ? "enabled" : "disabled");
+@@ -1518,8 +1508,8 @@ static void of_unittest_overlay_6(void)
+ 		ovcs_id = ov_id[i];
+ 		ret = of_overlay_remove(&ovcs_id);
+ 		if (ret != 0) {
+-			unittest(0, "overlay @\"%s\" failed destroy @\"%s\"\n",
+-					overlay_path(overlay_nr + i),
++			unittest(0, "%s failed destroy @\"%s\"\n",
++					overlay_name_from_nr(overlay_nr + i),
+ 					unittest_path(unittest_nr + i,
+ 						PDEV_OVERLAY));
+ 			return;
+@@ -1531,8 +1521,8 @@ static void of_unittest_overlay_6(void)
+ 		/* unittest device must be again in before state */
+ 		if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY)
+ 				!= before) {
+-			unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n",
+-					overlay_path(overlay_nr + i),
++			unittest(0, "%s with device @\"%s\" %s\n",
++					overlay_name_from_nr(overlay_nr + i),
+ 					unittest_path(unittest_nr + i,
+ 						PDEV_OVERLAY),
+ 					!before ? "enabled" : "disabled");
+@@ -1544,29 +1534,23 @@ static void of_unittest_overlay_6(void)
+ }
+ 
+ /* test overlay application in sequence */
+-static void of_unittest_overlay_8(void)
++static void __init of_unittest_overlay_8(void)
+ {
+-	struct device_node *np;
+ 	int ret, i, ov_id[2], ovcs_id;
+ 	int overlay_nr = 8, unittest_nr = 8;
++	const char *overlay_name;
+ 
+ 	/* we don't care about device state in this test */
+ 
+ 	/* apply the overlays */
+ 	for (i = 0; i < 2; i++) {
+ 
+-		np = of_find_node_by_path(overlay_path(overlay_nr + i));
+-		if (np == NULL) {
+-			unittest(0, "could not find overlay node @\"%s\"\n",
+-					overlay_path(overlay_nr + i));
+-			return;
+-		}
++		overlay_name = overlay_name_from_nr(overlay_nr + i);
+ 
+-		ovcs_id = 0;
+-		ret = of_overlay_apply(np, &ovcs_id);
++		ret = overlay_data_apply(overlay_name, &ovcs_id);
+ 		if (ret < 0)  {
+-			unittest(0, "could not create overlay from \"%s\"\n",
+-					overlay_path(overlay_nr + i));
++			unittest(0, "could not apply overlay \"%s\"\n",
++					overlay_name);
+ 			return;
+ 		}
+ 		ov_id[i] = ovcs_id;
+@@ -1577,8 +1561,8 @@ static void of_unittest_overlay_8(void)
+ 	ovcs_id = ov_id[0];
+ 	ret = of_overlay_remove(&ovcs_id);
+ 	if (ret == 0) {
+-		unittest(0, "overlay @\"%s\" was destroyed @\"%s\"\n",
+-				overlay_path(overlay_nr + 0),
++		unittest(0, "%s was destroyed @\"%s\"\n",
++				overlay_name_from_nr(overlay_nr + 0),
+ 				unittest_path(unittest_nr,
+ 					PDEV_OVERLAY));
+ 		return;
+@@ -1589,8 +1573,8 @@ static void of_unittest_overlay_8(void)
+ 		ovcs_id = ov_id[i];
+ 		ret = of_overlay_remove(&ovcs_id);
+ 		if (ret != 0) {
+-			unittest(0, "overlay @\"%s\" not destroyed @\"%s\"\n",
+-					overlay_path(overlay_nr + i),
++			unittest(0, "%s not destroyed @\"%s\"\n",
++					overlay_name_from_nr(overlay_nr + i),
+ 					unittest_path(unittest_nr,
+ 						PDEV_OVERLAY));
+ 			return;
+@@ -1602,7 +1586,7 @@ static void of_unittest_overlay_8(void)
+ }
+ 
+ /* test insertion of a bus with parent devices */
+-static void of_unittest_overlay_10(void)
++static void __init of_unittest_overlay_10(void)
+ {
+ 	int ret;
+ 	char *child_path;
+@@ -1625,7 +1609,7 @@ static void of_unittest_overlay_10(void)
+ }
+ 
+ /* test insertion of a bus with parent devices (and revert) */
+-static void of_unittest_overlay_11(void)
++static void __init of_unittest_overlay_11(void)
+ {
+ 	int ret;
+ 
+@@ -1891,7 +1875,7 @@ static void of_unittest_overlay_i2c_cleanup(void)
+ 	i2c_del_driver(&unittest_i2c_dev_driver);
+ }
+ 
+-static void of_unittest_overlay_i2c_12(void)
++static void __init of_unittest_overlay_i2c_12(void)
+ {
+ 	int ret;
+ 
+@@ -1904,7 +1888,7 @@ static void of_unittest_overlay_i2c_12(void)
+ }
+ 
+ /* test deactivation of device */
+-static void of_unittest_overlay_i2c_13(void)
++static void __init of_unittest_overlay_i2c_13(void)
+ {
+ 	int ret;
+ 
+@@ -1921,7 +1905,7 @@ static void of_unittest_overlay_i2c_14(void)
+ {
+ }
+ 
+-static void of_unittest_overlay_i2c_15(void)
++static void __init of_unittest_overlay_i2c_15(void)
+ {
+ 	int ret;
+ 
+@@ -2023,23 +2007,38 @@ static inline void __init of_unittest_overlay(void) { }
+ 	extern uint8_t __dtb_##name##_begin[]; \
+ 	extern uint8_t __dtb_##name##_end[]
+ 
+-#define OVERLAY_INFO(name, expected) \
+-{	.dtb_begin	 = __dtb_##name##_begin, \
+-	.dtb_end	 = __dtb_##name##_end, \
+-	.expected_result = expected, \
++#define OVERLAY_INFO(overlay_name, expected)             \
++{	.dtb_begin       = __dtb_##overlay_name##_begin, \
++	.dtb_end         = __dtb_##overlay_name##_end,   \
++	.expected_result = expected,                     \
++	.name            = #overlay_name,                \
+ }
+ 
+ struct overlay_info {
+-	uint8_t		   *dtb_begin;
+-	uint8_t		   *dtb_end;
+-	void		   *data;
+-	struct device_node *np_overlay;
+-	int		   expected_result;
+-	int		   overlay_id;
++	uint8_t		*dtb_begin;
++	uint8_t		*dtb_end;
++	int		expected_result;
++	int		overlay_id;
++	char		*name;
+ };
+ 
+ OVERLAY_INFO_EXTERN(overlay_base);
+ OVERLAY_INFO_EXTERN(overlay);
++OVERLAY_INFO_EXTERN(overlay_0);
++OVERLAY_INFO_EXTERN(overlay_1);
++OVERLAY_INFO_EXTERN(overlay_2);
++OVERLAY_INFO_EXTERN(overlay_3);
++OVERLAY_INFO_EXTERN(overlay_4);
++OVERLAY_INFO_EXTERN(overlay_5);
++OVERLAY_INFO_EXTERN(overlay_6);
++OVERLAY_INFO_EXTERN(overlay_7);
++OVERLAY_INFO_EXTERN(overlay_8);
++OVERLAY_INFO_EXTERN(overlay_9);
++OVERLAY_INFO_EXTERN(overlay_10);
++OVERLAY_INFO_EXTERN(overlay_11);
++OVERLAY_INFO_EXTERN(overlay_12);
++OVERLAY_INFO_EXTERN(overlay_13);
++OVERLAY_INFO_EXTERN(overlay_15);
+ OVERLAY_INFO_EXTERN(overlay_bad_phandle);
+ OVERLAY_INFO_EXTERN(overlay_bad_symbol);
+ 
+@@ -2047,6 +2046,21 @@ OVERLAY_INFO_EXTERN(overlay_bad_symbol);
+ static struct overlay_info overlays[] = {
+ 	OVERLAY_INFO(overlay_base, -9999),
+ 	OVERLAY_INFO(overlay, 0),
++	OVERLAY_INFO(overlay_0, 0),
++	OVERLAY_INFO(overlay_1, 0),
++	OVERLAY_INFO(overlay_2, 0),
++	OVERLAY_INFO(overlay_3, 0),
++	OVERLAY_INFO(overlay_4, 0),
++	OVERLAY_INFO(overlay_5, 0),
++	OVERLAY_INFO(overlay_6, 0),
++	OVERLAY_INFO(overlay_7, 0),
++	OVERLAY_INFO(overlay_8, 0),
++	OVERLAY_INFO(overlay_9, 0),
++	OVERLAY_INFO(overlay_10, 0),
++	OVERLAY_INFO(overlay_11, 0),
++	OVERLAY_INFO(overlay_12, 0),
++	OVERLAY_INFO(overlay_13, 0),
++	OVERLAY_INFO(overlay_15, 0),
+ 	OVERLAY_INFO(overlay_bad_phandle, -EINVAL),
+ 	OVERLAY_INFO(overlay_bad_symbol, -EINVAL),
+ 	{}
+@@ -2077,6 +2091,7 @@ void __init unittest_unflatten_overlay_base(void)
+ {
+ 	struct overlay_info *info;
+ 	u32 data_size;
++	void *new_fdt;
+ 	u32 size;
+ 
+ 	info = &overlays[0];
+@@ -2098,17 +2113,16 @@ void __init unittest_unflatten_overlay_base(void)
+ 		return;
+ 	}
+ 
+-	info->data = dt_alloc_memory(size, roundup_pow_of_two(FDT_V17_SIZE));
+-	if (!info->data) {
++	new_fdt = dt_alloc_memory(size, roundup_pow_of_two(FDT_V17_SIZE));
++	if (!new_fdt) {
+ 		pr_err("alloc for dtb 'overlay_base' failed");
+ 		return;
+ 	}
+ 
+-	memcpy(info->data, info->dtb_begin, size);
++	memcpy(new_fdt, info->dtb_begin, size);
+ 
+-	__unflatten_device_tree(info->data, NULL, &info->np_overlay,
++	__unflatten_device_tree(new_fdt, NULL, &overlay_base_root,
+ 				dt_alloc_memory, true);
+-	overlay_base_root = info->np_overlay;
+ }
+ 
+ /*
+@@ -2122,74 +2136,44 @@ void __init unittest_unflatten_overlay_base(void)
+  *
+  * Return 0 on unexpected error.
+  */
+-static int __init overlay_data_add(int onum)
++static int __init overlay_data_apply(const char *overlay_name, int *overlay_id)
+ {
+ 	struct overlay_info *info;
++	int found = 0;
+ 	int k;
+ 	int ret;
+ 	u32 size;
+-	u32 size_from_header;
+ 
+-	for (k = 0, info = overlays; info; info++, k++) {
+-		if (k == onum)
++	for (k = 0, info = overlays; info && info->name; info++, k++) {
++		if (!strcmp(overlay_name, info->name)) {
++			found = 1;
+ 			break;
++		}
+ 	}
+-	if (onum > k)
++	if (!found) {
++		pr_err("no overlay data for %s\n", overlay_name);
+ 		return 0;
++	}
+ 
+ 	size = info->dtb_end - info->dtb_begin;
+ 	if (!size) {
+-		pr_err("no overlay to attach, %d\n", onum);
+-		ret = 0;
+-	}
+-
+-	size_from_header = fdt_totalsize(info->dtb_begin);
+-	if (size_from_header != size) {
+-		pr_err("overlay header totalsize != actual size, %d", onum);
+-		return 0;
+-	}
+-
+-	/*
+-	 * Must create permanent copy of FDT because of_fdt_unflatten_tree()
+-	 * will create pointers to the passed in FDT in the EDT.
+-	 */
+-	info->data = kmemdup(info->dtb_begin, size, GFP_KERNEL);
+-	if (!info->data) {
+-		pr_err("unable to allocate memory for data, %d\n", onum);
+-		return 0;
+-	}
+-
+-	of_fdt_unflatten_tree(info->data, NULL, &info->np_overlay);
+-	if (!info->np_overlay) {
+-		pr_err("unable to unflatten overlay, %d\n", onum);
++		pr_err("no overlay data for %s\n", overlay_name);
+ 		ret = 0;
+-		goto out_free_data;
+ 	}
+ 
+-	info->overlay_id = 0;
+-	ret = of_overlay_apply(info->np_overlay, &info->overlay_id);
+-	if (ret < 0) {
+-		pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum);
+-		of_overlay_mutex_unlock();
+-		goto out_free_np_overlay;
+-	}
+-
+-	pr_debug("__dtb_overlay_begin applied, overlay id %d\n", ret);
+-
+-	goto out;
+-
+-out_free_np_overlay:
+-	/*
+-	 * info->np_overlay is the unflattened device tree
+-	 * It has not been spliced into the live tree.
+-	 */
+-
+-	/* todo: function to free unflattened device tree */
++	ret = of_overlay_fdt_apply(info->dtb_begin, size, &info->overlay_id);
++	if (overlay_id)
++		*overlay_id = info->overlay_id;
++	if (ret < 0)
++		goto out;
+ 
+-out_free_data:
+-	kfree(info->data);
++	pr_debug("%s applied\n", overlay_name);
+ 
+ out:
++	if (ret != info->expected_result)
++		pr_err("of_overlay_fdt_apply() expected %d, ret=%d, %s\n",
++		       info->expected_result, ret, overlay_name);
++
+ 	return (ret == info->expected_result);
+ }
+ 
+@@ -2291,18 +2275,29 @@ static __init void of_unittest_overlay_high_level(void)
+ 		__of_attach_node_sysfs(np);
+ 
+ 	if (of_symbols) {
++		struct property *new_prop;
+ 		for_each_property_of_node(overlay_base_symbols, prop) {
+-			ret = __of_add_property(of_symbols, prop);
++
++			new_prop = __of_prop_dup(prop, GFP_KERNEL);
++			if (!new_prop) {
++				unittest(0, "__of_prop_dup() of '%s' from overlay_base node __symbols__",
++					 prop->name);
++				goto err_unlock;
++			}
++			ret = __of_add_property(of_symbols, new_prop);
+ 			if (ret) {
+-				unittest(0,
+-					 "duplicate property '%s' in overlay_base node __symbols__",
++				if (!strcmp(new_prop->name, "name")) {
++					/* auto-generated by unflatten */
++					ret = 0;
++					continue;
++				}
++				unittest(0, "duplicate property '%s' in overlay_base node __symbols__",
+ 					 prop->name);
+ 				goto err_unlock;
+ 			}
+-			ret = __of_add_property_sysfs(of_symbols, prop);
++			ret = __of_add_property_sysfs(of_symbols, new_prop);
+ 			if (ret) {
+-				unittest(0,
+-					 "unable to add property '%s' in overlay_base node __symbols__ to sysfs",
++				unittest(0, "unable to add property '%s' in overlay_base node __symbols__ to sysfs",
+ 					 prop->name);
+ 				goto err_unlock;
+ 			}
+@@ -2314,13 +2309,13 @@ static __init void of_unittest_overlay_high_level(void)
+ 
+ 	/* now do the normal overlay usage test */
+ 
+-	unittest(overlay_data_add(1),
++	unittest(overlay_data_apply("overlay", NULL),
+ 		 "Adding overlay 'overlay' failed\n");
+ 
+-	unittest(overlay_data_add(2),
++	unittest(overlay_data_apply("overlay_bad_phandle", NULL),
+ 		 "Adding overlay 'overlay_bad_phandle' failed\n");
+ 
+-	unittest(overlay_data_add(3),
++	unittest(overlay_data_apply("overlay_bad_symbol", NULL),
+ 		 "Adding overlay 'overlay_bad_symbol' failed\n");
+ 
+ 	return;
+diff --git a/include/linux/of.h b/include/linux/of.h
+index e273cc03a89d..8fda85e54dbd 100644
+--- a/include/linux/of.h
++++ b/include/linux/of.h
+@@ -1312,8 +1312,8 @@ struct of_overlay_notify_data {
+ 
+ #ifdef CONFIG_OF_OVERLAY
+ 
+-/* ID based overlays; the API for external users */
+-int of_overlay_apply(struct device_node *tree, int *ovcs_id);
++int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size,
++			 int *ovcs_id);
+ int of_overlay_remove(int *ovcs_id);
+ int of_overlay_remove_all(void);
+ 
+@@ -1322,7 +1322,7 @@ int of_overlay_notifier_unregister(struct notifier_block *nb);
+ 
+ #else
+ 
+-static inline int of_overlay_apply(struct device_node *tree, int *ovcs_id)
++static inline int of_overlay_fdt_apply(void *overlay_fdt, int *ovcs_id)
+ {
+ 	return -ENOTSUPP;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0937-of-improve-reporting-invalid-overlay-target-path.patch b/patches/0937-of-improve-reporting-invalid-overlay-target-path.patch
new file mode 100644
index 00000000000000..7f5600a9fcf6e1
--- /dev/null
+++ b/patches/0937-of-improve-reporting-invalid-overlay-target-path.patch
@@ -0,0 +1,62 @@
+From 2930d26b5209fbab5b81989d7b084847af89cb4f Mon Sep 17 00:00:00 2001
+From: Frank Rowand <frank.rowand@sony.com>
+Date: Mon, 12 Feb 2018 00:25:04 -0800
+Subject: [PATCH 0937/1795] of: improve reporting invalid overlay target path
+
+Errors while developing the patch to create of_overlay_fdt_apply()
+exposed inadequate error messages to debug problems when overlay
+devicetree fragment nodes contain an invalid target path.  Improve
+the messages in find_target_node() to remedy this.
+
+Signed-off-by: Frank Rowand <frank.rowand@sony.com>
+(cherry picked from commit e547c0031697a0cb5ff7f4a66754fb3e082754ff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 22 ++++++++++++++++------
+ 1 file changed, 16 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 585a5de1e329..5c64752d473b 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -491,20 +491,30 @@ static int build_changeset(struct overlay_changeset *ovcs)
+  */
+ static struct device_node *find_target_node(struct device_node *info_node)
+ {
++	struct device_node *node;
+ 	const char *path;
+ 	u32 val;
+ 	int ret;
+ 
+ 	ret = of_property_read_u32(info_node, "target", &val);
+-	if (!ret)
+-		return of_find_node_by_phandle(val);
++	if (!ret) {
++		node = of_find_node_by_phandle(val);
++		if (!node)
++			pr_err("find target, node: %pOF, phandle 0x%x not found\n",
++			       info_node, val);
++		return node;
++	}
+ 
+ 	ret = of_property_read_string(info_node, "target-path", &path);
+-	if (!ret)
+-		return of_find_node_by_path(path);
++	if (!ret) {
++		node =  of_find_node_by_path(path);
++		if (!node)
++			pr_err("find target, node: %pOF, path '%s' not found\n",
++			       info_node, path);
++		return node;
++	}
+ 
+-	pr_err("Failed to find target for node %p (%s)\n",
+-		info_node, info_node->name);
++	pr_err("find target, node: %pOF, no target property\n", info_node);
+ 
+ 	return NULL;
+ }
+-- 
+2.19.0
+
diff --git a/patches/0938-of-overlay-Fix-forgotten-reference-to-of_overlay_app.patch b/patches/0938-of-overlay-Fix-forgotten-reference-to-of_overlay_app.patch
new file mode 100644
index 00000000000000..4945318c1ec870
--- /dev/null
+++ b/patches/0938-of-overlay-Fix-forgotten-reference-to-of_overlay_app.patch
@@ -0,0 +1,36 @@
+From 02dfb1d9db68f6563358616e135d521347d1fe1d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 9 Mar 2018 11:44:47 +0100
+Subject: [PATCH 0938/1795] of: overlay: Fix forgotten reference to
+ of_overlay_apply()
+
+While technically the ovcs_id is still returned by of_overlay_apply(),
+this is an internal function.  All public callers of of_overlay_remove()
+pass an ovcs_id returned by the public function of_overlay_fdt_apply().
+
+Fixes: 39a751a4cb7e4798 ("of: change overlay apply input data from unflattened to FDT")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit a514266ba675b28ff223ecd1fc431810ec828337)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/of/overlay.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index 5c64752d473b..ecf895bf2434 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -961,7 +961,7 @@ static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
+  * @ovcs_id:	Pointer to overlay changeset id
+  *
+  * Removes an overlay if it is permissible.  @ovcs_id was previously returned
+- * by of_overlay_apply().
++ * by of_overlay_fdt_apply().
+  *
+  * If an error occurred while attempting to revert the overlay changeset,
+  * then an attempt is made to re-apply any changeset entry that was
+-- 
+2.19.0
+
diff --git a/patches/0939-of-overlay-Stop-leaking-resources-on-overlay-removal.patch b/patches/0939-of-overlay-Stop-leaking-resources-on-overlay-removal.patch
new file mode 100644
index 00000000000000..4b4605db8c09a8
--- /dev/null
+++ b/patches/0939-of-overlay-Stop-leaking-resources-on-overlay-removal.patch
@@ -0,0 +1,105 @@
+From 46d486e57fb221866ff40b10e87e0707821aca81 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Thu, 26 Apr 2018 13:00:30 +0200
+Subject: [PATCH 0939/1795] of: overlay: Stop leaking resources on overlay
+ removal
+
+Only the overlay notifier callbacks have a chance to potentially get
+hold of references to those two resources, but they are not supposed to
+store them beyond OF_OVERLAY_POST_REMOVE.
+
+Document the overlay notifier API, its constraint regarding pointer
+lifetime, and then remove intentional leaks of ovcs->overlay_tree and
+ovcs->fdt from free_overlay_changeset.
+
+See also https://lkml.org/lkml/2018/4/23/1063 and following.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Reviewed-by: Frank Rowand <frowand.list@gmail.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 83ef4777f5ff3689e6e52d3913a13d79aa25f1b5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/overlay-notes.txt |  8 ++++++
+ drivers/of/overlay.c                       | 30 +++++++++++++++-------
+ 2 files changed, 29 insertions(+), 9 deletions(-)
+
+diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt
+index c4aa0adf13ec..9e2d3e25b33a 100644
+--- a/Documentation/devicetree/overlay-notes.txt
++++ b/Documentation/devicetree/overlay-notes.txt
+@@ -98,6 +98,14 @@ Finally, if you need to remove all overlays in one-go, just call
+ of_overlay_remove_all() which will remove every single one in the correct
+ order.
+ 
++In addition, there is the option to register notifiers that get called on
++overlay operations. See of_overlay_notifier_register/unregister and
++enum of_overlay_notify_action for details.
++
++Note that a notifier callback is not supposed to store pointers to a device
++tree node or its content beyond OF_OVERLAY_POST_REMOVE corresponding to the
++respective node it received.
++
+ Overlay DTS Format
+ ------------------
+ 
+diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
+index ecf895bf2434..68c281d8ca66 100644
+--- a/drivers/of/overlay.c
++++ b/drivers/of/overlay.c
+@@ -105,12 +105,28 @@ static DEFINE_IDR(ovcs_idr);
+ 
+ static BLOCKING_NOTIFIER_HEAD(overlay_notify_chain);
+ 
++/**
++ * of_overlay_notifier_register() - Register notifier for overlay operations
++ * @nb:		Notifier block to register
++ *
++ * Register for notification on overlay operations on device tree nodes. The
++ * reported actions definied by @of_reconfig_change. The notifier callback
++ * furthermore receives a pointer to the affected device tree node.
++ *
++ * Note that a notifier callback is not supposed to store pointers to a device
++ * tree node or its content beyond @OF_OVERLAY_POST_REMOVE corresponding to the
++ * respective node it received.
++ */
+ int of_overlay_notifier_register(struct notifier_block *nb)
+ {
+ 	return blocking_notifier_chain_register(&overlay_notify_chain, nb);
+ }
+ EXPORT_SYMBOL_GPL(of_overlay_notifier_register);
+ 
++/**
++ * of_overlay_notifier_register() - Unregister notifier for overlay operations
++ * @nb:		Notifier block to unregister
++ */
+ int of_overlay_notifier_unregister(struct notifier_block *nb)
+ {
+ 	return blocking_notifier_chain_unregister(&overlay_notify_chain, nb);
+@@ -662,17 +678,13 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
+ 		of_node_put(ovcs->fragments[i].overlay);
+ 	}
+ 	kfree(ovcs->fragments);
+-
+ 	/*
+-	 * TODO
+-	 *
+-	 * would like to: kfree(ovcs->overlay_tree);
+-	 * but can not since drivers may have pointers into this data
+-	 *
+-	 * would like to: kfree(ovcs->fdt);
+-	 * but can not since drivers may have pointers into this data
++	 * There should be no live pointers into ovcs->overlay_tree and
++	 * ovcs->fdt due to the policy that overlay notifiers are not allowed
++	 * to retain pointers into the overlay devicetree.
+ 	 */
+-
++	kfree(ovcs->overlay_tree);
++	kfree(ovcs->fdt);
+ 	kfree(ovcs);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/0940-treewide-setup_timer-timer_setup.patch b/patches/0940-treewide-setup_timer-timer_setup.patch
new file mode 100644
index 00000000000000..98af201ba06222
--- /dev/null
+++ b/patches/0940-treewide-setup_timer-timer_setup.patch
@@ -0,0 +1,777 @@
+From 2a8a53468474ce2182007ca4cb701b8280755abd Mon Sep 17 00:00:00 2001
+From: Kees Cook <keescook@chromium.org>
+Date: Mon, 16 Oct 2017 14:43:17 -0700
+Subject: [PATCH 0940/1795] treewide: setup_timer() -> timer_setup()
+
+This converts all remaining cases of the old setup_timer() API into using
+timer_setup(), where the callback argument is the structure already
+holding the struct timer_list. These should have no behavioral changes,
+since they just change which pointer is passed into the callback with
+the same available pointers after conversion. It handles the following
+examples, in addition to some other variations.
+
+Casting from unsigned long:
+
+    void my_callback(unsigned long data)
+    {
+        struct something *ptr = (struct something *)data;
+    ...
+    }
+    ...
+    setup_timer(&ptr->my_timer, my_callback, ptr);
+
+and forced object casts:
+
+    void my_callback(struct something *ptr)
+    {
+    ...
+    }
+    ...
+    setup_timer(&ptr->my_timer, my_callback, (unsigned long)ptr);
+
+become:
+
+    void my_callback(struct timer_list *t)
+    {
+        struct something *ptr = from_timer(ptr, t, my_timer);
+    ...
+    }
+    ...
+    timer_setup(&ptr->my_timer, my_callback, 0);
+
+Direct function assignments:
+
+    void my_callback(unsigned long data)
+    {
+        struct something *ptr = (struct something *)data;
+    ...
+    }
+    ...
+    ptr->my_timer.function = my_callback;
+
+have a temporary cast added, along with converting the args:
+
+    void my_callback(struct timer_list *t)
+    {
+        struct something *ptr = from_timer(ptr, t, my_timer);
+    ...
+    }
+    ...
+    ptr->my_timer.function = (TIMER_FUNC_TYPE)my_callback;
+
+And finally, callbacks without a data assignment:
+
+    void my_callback(unsigned long data)
+    {
+    ...
+    }
+    ...
+    setup_timer(&ptr->my_timer, my_callback, 0);
+
+have their argument renamed to verify they're unused during conversion:
+
+    void my_callback(struct timer_list *unused)
+    {
+    ...
+    }
+    ...
+    timer_setup(&ptr->my_timer, my_callback, 0);
+
+The conversion is done with the following Coccinelle script:
+
+spatch --very-quiet --all-includes --include-headers \
+	-I ./arch/x86/include -I ./arch/x86/include/generated \
+	-I ./include -I ./arch/x86/include/uapi \
+	-I ./arch/x86/include/generated/uapi -I ./include/uapi \
+	-I ./include/generated/uapi --include ./include/linux/kconfig.h \
+	--dir . \
+	--cocci-file ~/src/data/timer_setup.cocci
+
+@fix_address_of@
+expression e;
+@@
+
+ setup_timer(
+-&(e)
++&e
+ , ...)
+
+// Update any raw setup_timer() usages that have a NULL callback, but
+// would otherwise match change_timer_function_usage, since the latter
+// will update all function assignments done in the face of a NULL
+// function initialization in setup_timer().
+@change_timer_function_usage_NULL@
+expression _E;
+identifier _timer;
+type _cast_data;
+@@
+
+(
+-setup_timer(&_E->_timer, NULL, _E);
++timer_setup(&_E->_timer, NULL, 0);
+|
+-setup_timer(&_E->_timer, NULL, (_cast_data)_E);
++timer_setup(&_E->_timer, NULL, 0);
+|
+-setup_timer(&_E._timer, NULL, &_E);
++timer_setup(&_E._timer, NULL, 0);
+|
+-setup_timer(&_E._timer, NULL, (_cast_data)&_E);
++timer_setup(&_E._timer, NULL, 0);
+)
+
+@change_timer_function_usage@
+expression _E;
+identifier _timer;
+struct timer_list _stl;
+identifier _callback;
+type _cast_func, _cast_data;
+@@
+
+(
+-setup_timer(&_E->_timer, _callback, _E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, &_callback, _E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, _callback, (_cast_data)_E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, &_callback, (_cast_data)_E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, (_cast_func)_callback, _E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, (_cast_func)&_callback, _E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, (_cast_func)_callback, (_cast_data)_E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, (_cast_func)&_callback, (_cast_data)_E);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E._timer, _callback, (_cast_data)_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, _callback, (_cast_data)&_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, &_callback, (_cast_data)_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, &_callback, (_cast_data)&_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, (_cast_func)_callback, (_cast_data)_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, (_cast_func)_callback, (_cast_data)&_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, (_cast_func)&_callback, (_cast_data)_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, (_cast_func)&_callback, (_cast_data)&_E);
++timer_setup(&_E._timer, _callback, 0);
+|
+ _E->_timer@_stl.function = _callback;
+|
+ _E->_timer@_stl.function = &_callback;
+|
+ _E->_timer@_stl.function = (_cast_func)_callback;
+|
+ _E->_timer@_stl.function = (_cast_func)&_callback;
+|
+ _E._timer@_stl.function = _callback;
+|
+ _E._timer@_stl.function = &_callback;
+|
+ _E._timer@_stl.function = (_cast_func)_callback;
+|
+ _E._timer@_stl.function = (_cast_func)&_callback;
+)
+
+// callback(unsigned long arg)
+@change_callback_handle_cast
+ depends on change_timer_function_usage@
+identifier change_timer_function_usage._callback;
+identifier change_timer_function_usage._timer;
+type _origtype;
+identifier _origarg;
+type _handletype;
+identifier _handle;
+@@
+
+ void _callback(
+-_origtype _origarg
++struct timer_list *t
+ )
+ {
+(
+	... when != _origarg
+	_handletype *_handle =
+-(_handletype *)_origarg;
++from_timer(_handle, t, _timer);
+	... when != _origarg
+|
+	... when != _origarg
+	_handletype *_handle =
+-(void *)_origarg;
++from_timer(_handle, t, _timer);
+	... when != _origarg
+|
+	... when != _origarg
+	_handletype *_handle;
+	... when != _handle
+	_handle =
+-(_handletype *)_origarg;
++from_timer(_handle, t, _timer);
+	... when != _origarg
+|
+	... when != _origarg
+	_handletype *_handle;
+	... when != _handle
+	_handle =
+-(void *)_origarg;
++from_timer(_handle, t, _timer);
+	... when != _origarg
+)
+ }
+
+// callback(unsigned long arg) without existing variable
+@change_callback_handle_cast_no_arg
+ depends on change_timer_function_usage &&
+                     !change_callback_handle_cast@
+identifier change_timer_function_usage._callback;
+identifier change_timer_function_usage._timer;
+type _origtype;
+identifier _origarg;
+type _handletype;
+@@
+
+ void _callback(
+-_origtype _origarg
++struct timer_list *t
+ )
+ {
++	_handletype *_origarg = from_timer(_origarg, t, _timer);
++
+	... when != _origarg
+-	(_handletype *)_origarg
++	_origarg
+	... when != _origarg
+ }
+
+// Avoid already converted callbacks.
+@match_callback_converted
+ depends on change_timer_function_usage &&
+            !change_callback_handle_cast &&
+	    !change_callback_handle_cast_no_arg@
+identifier change_timer_function_usage._callback;
+identifier t;
+@@
+
+ void _callback(struct timer_list *t)
+ { ... }
+
+// callback(struct something *handle)
+@change_callback_handle_arg
+ depends on change_timer_function_usage &&
+	    !match_callback_converted &&
+            !change_callback_handle_cast &&
+            !change_callback_handle_cast_no_arg@
+identifier change_timer_function_usage._callback;
+identifier change_timer_function_usage._timer;
+type _handletype;
+identifier _handle;
+@@
+
+ void _callback(
+-_handletype *_handle
++struct timer_list *t
+ )
+ {
++	_handletype *_handle = from_timer(_handle, t, _timer);
+	...
+ }
+
+// If change_callback_handle_arg ran on an empty function, remove
+// the added handler.
+@unchange_callback_handle_arg
+ depends on change_timer_function_usage &&
+	    change_callback_handle_arg@
+identifier change_timer_function_usage._callback;
+identifier change_timer_function_usage._timer;
+type _handletype;
+identifier _handle;
+identifier t;
+@@
+
+ void _callback(struct timer_list *t)
+ {
+-	_handletype *_handle = from_timer(_handle, t, _timer);
+ }
+
+// We only want to refactor the setup_timer() data argument if we've found
+// the matching callback. This undoes changes in change_timer_function_usage.
+@unchange_timer_function_usage
+ depends on change_timer_function_usage &&
+            !change_callback_handle_cast &&
+            !change_callback_handle_cast_no_arg &&
+	    !change_callback_handle_arg@
+expression change_timer_function_usage._E;
+identifier change_timer_function_usage._timer;
+identifier change_timer_function_usage._callback;
+type change_timer_function_usage._cast_data;
+@@
+
+(
+-timer_setup(&_E->_timer, _callback, 0);
++setup_timer(&_E->_timer, _callback, (_cast_data)_E);
+|
+-timer_setup(&_E._timer, _callback, 0);
++setup_timer(&_E._timer, _callback, (_cast_data)&_E);
+)
+
+// If we fixed a callback from a .function assignment, fix the
+// assignment cast now.
+@change_timer_function_assignment
+ depends on change_timer_function_usage &&
+            (change_callback_handle_cast ||
+             change_callback_handle_cast_no_arg ||
+             change_callback_handle_arg)@
+expression change_timer_function_usage._E;
+identifier change_timer_function_usage._timer;
+identifier change_timer_function_usage._callback;
+type _cast_func;
+typedef TIMER_FUNC_TYPE;
+@@
+
+(
+ _E->_timer.function =
+-_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E->_timer.function =
+-&_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E->_timer.function =
+-(_cast_func)_callback;
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E->_timer.function =
+-(_cast_func)&_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E._timer.function =
+-_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E._timer.function =
+-&_callback;
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E._timer.function =
+-(_cast_func)_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+|
+ _E._timer.function =
+-(_cast_func)&_callback
++(TIMER_FUNC_TYPE)_callback
+ ;
+)
+
+// Sometimes timer functions are called directly. Replace matched args.
+@change_timer_function_calls
+ depends on change_timer_function_usage &&
+            (change_callback_handle_cast ||
+             change_callback_handle_cast_no_arg ||
+             change_callback_handle_arg)@
+expression _E;
+identifier change_timer_function_usage._timer;
+identifier change_timer_function_usage._callback;
+type _cast_data;
+@@
+
+ _callback(
+(
+-(_cast_data)_E
++&_E->_timer
+|
+-(_cast_data)&_E
++&_E._timer
+|
+-_E
++&_E->_timer
+)
+ )
+
+// If a timer has been configured without a data argument, it can be
+// converted without regard to the callback argument, since it is unused.
+@match_timer_function_unused_data@
+expression _E;
+identifier _timer;
+identifier _callback;
+@@
+
+(
+-setup_timer(&_E->_timer, _callback, 0);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, _callback, 0L);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E->_timer, _callback, 0UL);
++timer_setup(&_E->_timer, _callback, 0);
+|
+-setup_timer(&_E._timer, _callback, 0);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, _callback, 0L);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_E._timer, _callback, 0UL);
++timer_setup(&_E._timer, _callback, 0);
+|
+-setup_timer(&_timer, _callback, 0);
++timer_setup(&_timer, _callback, 0);
+|
+-setup_timer(&_timer, _callback, 0L);
++timer_setup(&_timer, _callback, 0);
+|
+-setup_timer(&_timer, _callback, 0UL);
++timer_setup(&_timer, _callback, 0);
+|
+-setup_timer(_timer, _callback, 0);
++timer_setup(_timer, _callback, 0);
+|
+-setup_timer(_timer, _callback, 0L);
++timer_setup(_timer, _callback, 0);
+|
+-setup_timer(_timer, _callback, 0UL);
++timer_setup(_timer, _callback, 0);
+)
+
+@change_callback_unused_data
+ depends on match_timer_function_unused_data@
+identifier match_timer_function_unused_data._callback;
+type _origtype;
+identifier _origarg;
+@@
+
+ void _callback(
+-_origtype _origarg
++struct timer_list *unused
+ )
+ {
+	... when != _origarg
+ }
+
+Signed-off-by: Kees Cook <keescook@chromium.org>
+(cherry picked from commit e99e88a9d2b067465adaa9c111ada99a041bef9a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	arch/alpha/kernel/srmcons.c
+	arch/arm/mach-iop32x/n2100.c
+	arch/arm/mach-orion5x/db88f5281-setup.c
+	arch/blackfin/kernel/nmi.c
+	arch/mips/lasat/picvue_proc.c
+	arch/powerpc/kernel/tau_6xx.c
+	arch/powerpc/oprofile/op_model_cell.c
+	arch/powerpc/platforms/cell/spufs/sched.c
+	arch/powerpc/platforms/powermac/low_i2c.c
+	arch/s390/kernel/time.c
+	arch/sh/drivers/heartbeat.c
+	arch/sh/drivers/pci/common.c
+	arch/sh/drivers/push-switch.c
+	block/blk-stat.c
+	block/blk-throttle.c
+	drivers/atm/ambassador.c
+	drivers/atm/firestream.c
+	drivers/atm/horizon.c
+	drivers/atm/idt77252.c
+	drivers/atm/lanai.c
+	drivers/atm/nicstar.c
+	drivers/block/DAC960.c
+	drivers/block/DAC960.h
+	drivers/block/rsxx/dma.c
+	drivers/block/skd_main.c
+	drivers/block/sunvdc.c
+	drivers/block/umem.c
+	drivers/block/xsysace.c
+	drivers/char/ipmi/bt-bmc.c
+	drivers/char/ipmi/ipmi_msghandler.c
+	drivers/char/ipmi/ipmi_si_intf.c
+	drivers/char/ipmi/ipmi_ssif.c
+	drivers/char/tpm/tpm-dev-common.c
+	drivers/gpu/drm/drm_vblank.c
+	drivers/gpu/drm/exynos/exynos_drm_vidi.c
+	drivers/gpu/drm/i2c/tda998x_drv.c
+	drivers/gpu/drm/msm/adreno/a5xx_preempt.c
+	drivers/gpu/drm/msm/msm_gpu.c
+	drivers/gpu/drm/omapdrm/dss/dsi.c
+	drivers/gpu/drm/rockchip/rockchip_drm_psr.c
+	drivers/gpu/drm/vgem/vgem_fence.c
+	drivers/gpu/drm/via/via_dmablit.c
+	drivers/hid/hid-appleir.c
+	drivers/hid/hid-prodikeys.c
+	drivers/hid/hid-wiimote-core.c
+	drivers/iio/common/ssp_sensors/ssp_dev.c
+	drivers/infiniband/hw/mlx5/mr.c
+	drivers/input/gameport/gameport.c
+	drivers/input/joystick/db9.c
+	drivers/input/joystick/gamecon.c
+	drivers/input/joystick/turbografx.c
+	drivers/iommu/iova.c
+	drivers/isdn/capi/capidrv.c
+	drivers/isdn/divert/isdn_divert.c
+	drivers/isdn/hardware/eicon/divasi.c
+	drivers/isdn/hardware/mISDN/hfcmulti.c
+	drivers/isdn/hardware/mISDN/hfcpci.c
+	drivers/isdn/hardware/mISDN/mISDNisar.c
+	drivers/isdn/i4l/isdn_common.c
+	drivers/isdn/i4l/isdn_net.c
+	drivers/isdn/i4l/isdn_ppp.c
+	drivers/isdn/i4l/isdn_tty.c
+	drivers/media/platform/s5p-mfc/s5p_mfc.c
+	drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
+	drivers/media/platform/vim2m.c
+	drivers/media/usb/au0828/au0828-dvb.c
+	drivers/media/usb/au0828/au0828-video.c
+	drivers/memstick/core/ms_block.c
+	drivers/mfd/rtsx_usb.c
+	drivers/mmc/core/host.c
+	drivers/mtd/sm_ftl.c
+	drivers/net/caif/caif_hsi.c
+	drivers/net/dsa/mv88e6xxx/phy.c
+	drivers/net/eql.c
+	drivers/net/ethernet/adi/bfin_mac.c
+	drivers/net/ethernet/agere/et131x.c
+	drivers/net/ethernet/amazon/ena/ena_netdev.c
+	drivers/net/ethernet/aquantia/atlantic/aq_nic.c
+	drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+	drivers/net/ethernet/atheros/atl1e/atl1e_main.c
+	drivers/net/ethernet/atheros/atlx/atl1.c
+	drivers/net/ethernet/atheros/atlx/atl2.c
+	drivers/net/ethernet/broadcom/b44.c
+	drivers/net/ethernet/broadcom/bnx2.c
+	drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+	drivers/net/ethernet/broadcom/bnxt/bnxt.c
+	drivers/net/ethernet/broadcom/tg3.c
+	drivers/net/ethernet/cisco/enic/enic_main.c
+	drivers/net/ethernet/marvell/mv643xx_eth.c
+	drivers/net/ethernet/marvell/pxa168_eth.c
+	drivers/net/ethernet/marvell/skge.c
+	drivers/net/ethernet/marvell/sky2.c
+	drivers/net/ethernet/myricom/myri10ge/myri10ge.c
+	drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+	drivers/net/ethernet/pasemi/pasemi_mac.c
+	drivers/net/ethernet/qlogic/qla3xxx.c
+	drivers/net/ethernet/rocker/rocker_ofdpa.c
+	drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+	drivers/net/ethernet/synopsys/dwc-xlgmac-net.c
+	drivers/net/ethernet/ti/cpsw_ale.c
+	drivers/net/ethernet/ti/netcp_ethss.c
+	drivers/net/ethernet/toshiba/spider_net.c
+	drivers/net/slip/slip.c
+	drivers/net/tun.c
+	drivers/net/wan/hdlc_ppp.c
+	drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c
+	drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
+	drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+	drivers/net/wireless/intel/iwlwifi/dvm/main.c
+	drivers/net/wireless/intel/iwlwifi/pcie/tx.c
+	drivers/net/wireless/intersil/hostap/hostap_ap.c
+	drivers/net/wireless/intersil/hostap/hostap_hw.c
+	drivers/net/wireless/intersil/orinoco/orinoco_usb.c
+	drivers/net/wireless/quantenna/qtnfmac/core.c
+	drivers/net/wireless/ti/wlcore/main.c
+	drivers/net/xen-netfront.c
+	drivers/nfc/pn533/pn533.c
+	drivers/nfc/st-nci/ndlc.c
+	drivers/ntb/test/ntb_pingpong.c
+	drivers/platform/x86/sony-laptop.c
+	drivers/pps/clients/pps-ktimer.c
+	drivers/rtc/rtc-dev.c
+	drivers/s390/block/dasd.c
+	drivers/s390/net/fsm.c
+	drivers/scsi/arcmsr/arcmsr_hba.c
+	drivers/scsi/arm/fas216.c
+	drivers/scsi/bfa/bfad.c
+	drivers/scsi/bfa/bfad_drv.h
+	drivers/scsi/bnx2fc/bnx2fc_tgt.c
+	drivers/scsi/esas2r/esas2r_main.c
+	drivers/scsi/fcoe/fcoe_ctlr.c
+	drivers/scsi/fnic/fnic_main.c
+	drivers/scsi/ncr53c8xx.c
+	drivers/staging/greybus/operation.c
+	drivers/staging/lustre/lnet/lnet/net_fault.c
+	drivers/staging/lustre/lustre/ptlrpc/service.c
+	drivers/staging/media/imx/imx-ic-prpencvf.c
+	drivers/staging/media/imx/imx-media-csi.c
+	drivers/staging/most/hdm-usb/hdm_usb.c
+	drivers/staging/rtl8192u/ieee80211/ieee80211_softmac.c
+	drivers/staging/rtl8712/recv_linux.c
+	drivers/staging/rtl8712/rtl8712_led.c
+	drivers/staging/unisys/visorbus/visorbus_main.c
+	drivers/staging/unisys/visornic/visornic_main.c
+	drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
+	drivers/target/target_core_user.c
+	drivers/tty/ipwireless/hardware.c
+	drivers/tty/n_gsm.c
+	drivers/tty/n_r3964.c
+	drivers/tty/serial/crisv10.c
+	drivers/tty/serial/fsl_lpuart.c
+	drivers/tty/serial/ifx6x60.c
+	drivers/tty/serial/imx.c
+	drivers/tty/serial/kgdb_nmi.c
+	drivers/tty/serial/max3100.c
+	drivers/tty/serial/mux.c
+	drivers/tty/serial/pnx8xxx_uart.c
+	drivers/tty/serial/sa1100.c
+	drivers/tty/serial/sh-sci.c
+	drivers/tty/serial/sn_console.c
+	drivers/tty/synclink.c
+	drivers/tty/synclink_gt.c
+	drivers/tty/synclinkmp.c
+	drivers/usb/core/hcd.c
+	drivers/usb/dwc2/hcd.c
+	drivers/usb/dwc2/hcd_queue.c
+	drivers/usb/gadget/udc/at91_udc.c
+	drivers/usb/gadget/udc/dummy_hcd.c
+	drivers/usb/gadget/udc/m66592-udc.c
+	drivers/usb/gadget/udc/omap_udc.c
+	drivers/usb/gadget/udc/pxa25x_udc.c
+	drivers/usb/gadget/udc/r8a66597-udc.c
+	drivers/usb/host/ohci-hcd.c
+	drivers/usb/host/oxu210hp-hcd.c
+	drivers/usb/host/r8a66597-hcd.c
+	drivers/usb/host/sl811-hcd.c
+	drivers/usb/host/uhci-hcd.c
+	drivers/usb/host/uhci-q.c
+	drivers/usb/host/xhci.c
+	drivers/usb/serial/mos7840.c
+	drivers/usb/storage/realtek_cr.c
+	drivers/uwb/drp.c
+	drivers/uwb/neh.c
+	drivers/uwb/rsv.c
+	drivers/uwb/uwb-internal.h
+	drivers/watchdog/at91sam9_wdt.c
+	drivers/watchdog/bcm47xx_wdt.c
+	drivers/watchdog/bcm63xx_wdt.c
+	drivers/watchdog/cpu5wdt.c
+	drivers/watchdog/mpc8xxx_wdt.c
+	drivers/watchdog/mtx-1_wdt.c
+	drivers/watchdog/nuc900_wdt.c
+	drivers/watchdog/pcwd.c
+	drivers/watchdog/pika_wdt.c
+	drivers/watchdog/rdc321x_wdt.c
+	drivers/watchdog/shwdt.c
+	fs/ocfs2/cluster/tcp.c
+	kernel/padata.c
+	kernel/time/clocksource.c
+	net/802/garp.c
+	net/802/mrp.c
+	net/appletalk/aarp.c
+	net/appletalk/ddp.c
+	net/batman-adv/tp_meter.c
+	net/bluetooth/hidp/core.c
+	net/bluetooth/rfcomm/core.c
+	net/bluetooth/sco.c
+	net/core/drop_monitor.c
+	net/core/gen_estimator.c
+	net/core/neighbour.c
+	net/decnet/dn_route.c
+	net/decnet/dn_timer.c
+	net/ipv4/igmp.c
+	net/ipv4/ipmr.c
+	net/ipv6/addrconf.c
+	net/ipv6/ip6mr.c
+	net/ipv6/mcast.c
+	net/ncsi/ncsi-manage.c
+	net/netfilter/nf_conntrack_expect.c
+	net/netfilter/nfnetlink_log.c
+	net/netfilter/xt_IDLETIMER.c
+	net/netfilter/xt_LED.c
+	net/nfc/nci/core.c
+	net/rxrpc/call_object.c
+	net/wireless/lib80211.c
+	net/x25/x25_link.c
+	net/xfrm/xfrm_state.c
+---
+ drivers/tty/serial/sh-sci.c | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 86b928e71dd9..a8a6ae8c3c57 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -1060,9 +1060,9 @@ static int scif_rtrg_enabled(struct uart_port *port)
+ 			(SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
+ }
+ 
+-static void rx_fifo_timer_fn(unsigned long arg)
++static void rx_fifo_timer_fn(struct timer_list *t)
+ {
+-	struct sci_port *s = (struct sci_port *)arg;
++	struct sci_port *s = from_timer(s, t, rx_fifo_timer);
+ 	struct uart_port *port = &s->port;
+ 
+ 	dev_dbg(port->dev, "Rx timed out\n");
+@@ -1140,8 +1140,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev,
+ 		sci->rx_fifo_timeout = r;
+ 		scif_set_rtrg(port, 1);
+ 		if (r > 0)
+-			setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
+-				    (unsigned long)sci);
++			timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
+ 	}
+ 
+ 	return count;
+@@ -1394,9 +1393,9 @@ static void work_fn_tx(struct work_struct *work)
+ 	dma_async_issue_pending(chan);
+ }
+ 
+-static void rx_timer_fn(unsigned long arg)
++static void rx_timer_fn(struct timer_list *t)
+ {
+-	struct sci_port *s = (struct sci_port *)arg;
++	struct sci_port *s = from_timer(s, t, rx_timer);
+ 	struct dma_chan *chan = s->chan_rx;
+ 	struct uart_port *port = &s->port;
+ 	struct dma_tx_state state;
+@@ -1574,7 +1573,7 @@ static void sci_request_dma(struct uart_port *port)
+ 			dma += s->buf_len_rx;
+ 		}
+ 
+-		setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
++		timer_setup(&s->rx_timer, rx_timer_fn, 0);
+ 
+ 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
+ 			sci_submit_rx(s);
+@@ -2240,8 +2239,7 @@ static void sci_reset(struct uart_port *port)
+ 	if (s->rx_trigger > 1) {
+ 		if (s->rx_fifo_timeout) {
+ 			scif_set_rtrg(port, 1);
+-			setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
+-				    (unsigned long)s);
++			timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
+ 		} else {
+ 			if (port->type == PORT_SCIFA ||
+ 			    port->type == PORT_SCIFB)
+-- 
+2.19.0
+
diff --git a/patches/0941-DT-serial-renesas-sci-serial-document-R8A77980-bindi.patch b/patches/0941-DT-serial-renesas-sci-serial-document-R8A77980-bindi.patch
new file mode 100644
index 00000000000000..69c4275949f0c4
--- /dev/null
+++ b/patches/0941-DT-serial-renesas-sci-serial-document-R8A77980-bindi.patch
@@ -0,0 +1,37 @@
+From 7011bd8b8f83f9c1e4dd2109dee0196a62217fdf Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 1 Feb 2018 22:36:20 +0300
+Subject: [PATCH 0941/1795] DT: serial: renesas,sci-serial: document R8A77980
+ bindings
+
+R-Car V3H (R8A77980) SoC has the R-Car gen3 compatible SCIF and HSCIF ports,
+so document the SoC specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 890fb16b4cdbc625b9213487c547793a775ad991)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+index 88f947c47adc..0cc5417904dd 100644
+--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
++++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+@@ -45,6 +45,8 @@ Required properties:
+     - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART.
+     - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
+     - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
++    - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
++    - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART.
+     - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
+     - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
+     - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
+-- 
+2.19.0
+
diff --git a/patches/0942-serial-sh-sci-use-hrtimer-for-receive-timeout.patch b/patches/0942-serial-sh-sci-use-hrtimer-for-receive-timeout.patch
new file mode 100644
index 00000000000000..4179e202487b91
--- /dev/null
+++ b/patches/0942-serial-sh-sci-use-hrtimer-for-receive-timeout.patch
@@ -0,0 +1,173 @@
+From 22ddac8033d8ad605f5cd5017a719ba101607d74 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Thu, 15 Feb 2018 13:02:41 +0100
+Subject: [PATCH 0942/1795] serial: sh-sci: use hrtimer for receive timeout
+
+High latencies of classic timers cause performance issues for high-
+speed serial transmissions. This patch transforms rx_timer into an
+hrtimer to reduce the minimum latency.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit b96408b47480f9947eee933fcce35ed4ae74cc9a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 47 +++++++++++++++++++++++--------------
+ 1 file changed, 30 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index a8a6ae8c3c57..2051a5309851 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -33,6 +33,7 @@
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/ioport.h>
++#include <linux/ktime.h>
+ #include <linux/major.h>
+ #include <linux/module.h>
+ #include <linux/mm.h>
+@@ -143,8 +144,8 @@ struct sci_port {
+ 	void				*rx_buf[2];
+ 	size_t				buf_len_rx;
+ 	struct work_struct		work_tx;
+-	struct timer_list		rx_timer;
+-	unsigned int			rx_timeout;
++	struct hrtimer			rx_timer;
++	unsigned int			rx_timeout;	/* microseconds */
+ #endif
+ 	unsigned int			rx_frame;
+ 	int				rx_trigger;
+@@ -1231,6 +1232,15 @@ static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
+ 	}
+ }
+ 
++static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
++{
++	long sec = usec / 1000000;
++	long nsec = (usec % 1000000) * 1000;
++	ktime_t t = ktime_set(sec, nsec);
++
++	hrtimer_start(hrt, t, HRTIMER_MODE_REL);
++}
++
+ static void sci_dma_rx_complete(void *arg)
+ {
+ 	struct sci_port *s = arg;
+@@ -1249,7 +1259,7 @@ static void sci_dma_rx_complete(void *arg)
+ 	if (active >= 0)
+ 		count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
+ 
+-	mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
++	start_hrtimer_us(&s->rx_timer, s->rx_timeout);
+ 
+ 	if (count)
+ 		tty_flip_buffer_push(&port->state->port);
+@@ -1393,9 +1403,9 @@ static void work_fn_tx(struct work_struct *work)
+ 	dma_async_issue_pending(chan);
+ }
+ 
+-static void rx_timer_fn(struct timer_list *t)
++static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
+ {
+-	struct sci_port *s = from_timer(s, t, rx_timer);
++	struct sci_port *s = container_of(t, struct sci_port, rx_timer);
+ 	struct dma_chan *chan = s->chan_rx;
+ 	struct uart_port *port = &s->port;
+ 	struct dma_tx_state state;
+@@ -1412,7 +1422,7 @@ static void rx_timer_fn(struct timer_list *t)
+ 	active = sci_dma_rx_find_active(s);
+ 	if (active < 0) {
+ 		spin_unlock_irqrestore(&port->lock, flags);
+-		return;
++		return HRTIMER_NORESTART;
+ 	}
+ 
+ 	status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
+@@ -1422,7 +1432,7 @@ static void rx_timer_fn(struct timer_list *t)
+ 			s->active_rx, active);
+ 
+ 		/* Let packet complete handler take care of the packet */
+-		return;
++		return HRTIMER_NORESTART;
+ 	}
+ 
+ 	dmaengine_pause(chan);
+@@ -1437,7 +1447,7 @@ static void rx_timer_fn(struct timer_list *t)
+ 	if (status == DMA_COMPLETE) {
+ 		spin_unlock_irqrestore(&port->lock, flags);
+ 		dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
+-		return;
++		return HRTIMER_NORESTART;
+ 	}
+ 
+ 	/* Handle incomplete DMA receive */
+@@ -1462,6 +1472,8 @@ static void rx_timer_fn(struct timer_list *t)
+ 	serial_port_out(port, SCSCR, scr | SCSCR_RIE);
+ 
+ 	spin_unlock_irqrestore(&port->lock, flags);
++
++	return HRTIMER_NORESTART;
+ }
+ 
+ static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
+@@ -1573,7 +1585,8 @@ static void sci_request_dma(struct uart_port *port)
+ 			dma += s->buf_len_rx;
+ 		}
+ 
+-		timer_setup(&s->rx_timer, rx_timer_fn, 0);
++		hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
++		s->rx_timer.function = rx_timer_fn;
+ 
+ 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
+ 			sci_submit_rx(s);
+@@ -1632,9 +1645,9 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
+ 		/* Clear current interrupt */
+ 		serial_port_out(port, SCxSR,
+ 				ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
+-		dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
++		dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
+ 			jiffies, s->rx_timeout);
+-		mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
++		start_hrtimer_us(&s->rx_timer, s->rx_timeout);
+ 
+ 		return IRQ_HANDLED;
+ 	}
+@@ -1645,7 +1658,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
+ 			scif_set_rtrg(port, s->rx_trigger);
+ 
+ 		mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
+-			  s->rx_frame * s->rx_fifo_timeout, 1000));
++			  s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
+ 	}
+ 
+ 	/* I think sci_receive_chars has to be called irrespective
+@@ -2081,7 +2094,7 @@ static void sci_shutdown(struct uart_port *port)
+ 	if (s->chan_rx) {
+ 		dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
+ 			port->line);
+-		del_timer_sync(&s->rx_timer);
++		hrtimer_cancel(&s->rx_timer);
+ 	}
+ #endif
+ 
+@@ -2482,11 +2495,11 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	if (termios->c_cflag & PARENB)
+ 		bits++;
+ 
+-	s->rx_frame = (100 * bits * HZ) / (baud / 10);
++	s->rx_frame = (10000 * bits) / (baud / 100);
+ #ifdef CONFIG_SERIAL_SH_SCI_DMA
+-	s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
+-	if (s->rx_timeout < msecs_to_jiffies(20))
+-		s->rx_timeout = msecs_to_jiffies(20);
++	s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
++	if (s->rx_timeout < 20)
++		s->rx_timeout = 20;
+ #endif
+ 
+ 	if ((termios->c_cflag & CREAD) != 0)
+-- 
+2.19.0
+
diff --git a/patches/0943-serial-sh-sci-Document-r8a77470-bindings.patch b/patches/0943-serial-sh-sci-Document-r8a77470-bindings.patch
new file mode 100644
index 00000000000000..c8d5aca712e0c7
--- /dev/null
+++ b/patches/0943-serial-sh-sci-Document-r8a77470-bindings.patch
@@ -0,0 +1,37 @@
+From 606562792182a4c4261947f14f89222493b33199 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Mon, 9 Apr 2018 13:20:00 +0100
+Subject: [PATCH 0943/1795] serial: sh-sci: Document r8a77470 bindings
+
+RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF
+ports, so document the SoC specific bindings.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ef9604b622ce3b77e0ec6b566a016ddd64c5deb0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+index 0cc5417904dd..106808b55b6d 100644
+--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
++++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+@@ -17,6 +17,8 @@ Required properties:
+     - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART.
+     - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART.
+     - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART.
++    - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART.
++    - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART.
+     - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
+     - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
+     - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
+-- 
+2.19.0
+
diff --git a/patches/0944-dt-bindings-arm-document-R8A77980-SoC-bindings.patch b/patches/0944-dt-bindings-arm-document-R8A77980-SoC-bindings.patch
new file mode 100644
index 00000000000000..58217c8b5df144
--- /dev/null
+++ b/patches/0944-dt-bindings-arm-document-R8A77980-SoC-bindings.patch
@@ -0,0 +1,34 @@
+From 50326bd970a3ab5d16db3dd7d7b1ee1e0d176a64 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 31 Jan 2018 22:56:47 +0300
+Subject: [PATCH 0944/1795] dt-bindings: arm: document R8A77980 SoC bindings
+
+Document the R-Car V3H (R8A77980) SoC device tree bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f15092f8482b63b91d7ca7f4bd7090da7f9f2f24)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 5c3af7ef0761..3ccad353acfa 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -41,6 +41,8 @@ SoCs:
+     compatible = "renesas,r8a7796"
+   - R-Car V3M (R8A77970)
+     compatible = "renesas,r8a77970"
++  - R-Car V3H (R8A77980)
++    compatible = "renesas,r8a77980"
+   - R-Car D3 (R8A77995)
+     compatible = "renesas,r8a77995"
+ 
+-- 
+2.19.0
+
diff --git a/patches/0945-arm64-defconfig-enable-R8A77980-SoC.patch b/patches/0945-arm64-defconfig-enable-R8A77980-SoC.patch
new file mode 100644
index 00000000000000..b51242485e0a16
--- /dev/null
+++ b/patches/0945-arm64-defconfig-enable-R8A77980-SoC.patch
@@ -0,0 +1,31 @@
+From 8fa98edacad016bee788b9be498285c0e70cd45c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 6 Feb 2018 14:20:45 +0100
+Subject: [PATCH 0945/1795] arm64: defconfig: enable R8A77980 SoC
+
+Enable the Renesas R-Car V3H (R8A77980) SoC in the ARM64 defconfig.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 9ab5977d472b3c63f99c23c2c4ec3a9820c50faf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 5a08e51c7ad0..20caba01c315 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -52,6 +52,7 @@ CONFIG_ARCH_RENESAS=y
+ CONFIG_ARCH_R8A7795=y
+ CONFIG_ARCH_R8A7796=y
+ CONFIG_ARCH_R8A77970=y
++CONFIG_ARCH_R8A77980=y
+ CONFIG_ARCH_R8A77995=y
+ CONFIG_ARCH_STRATIX10=y
+ CONFIG_ARCH_TEGRA=y
+-- 
+2.19.0
+
diff --git a/patches/0946-arm64-dts-renesas-r8a7795-move-scif-node-into-alphab.patch b/patches/0946-arm64-dts-renesas-r8a7795-move-scif-node-into-alphab.patch
new file mode 100644
index 00000000000000..b802efbc009909
--- /dev/null
+++ b/patches/0946-arm64-dts-renesas-r8a7795-move-scif-node-into-alphab.patch
@@ -0,0 +1,57 @@
+From 2c94910957efafeda5725eb3062a85c628670f93 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 3 Jan 2018 13:41:03 +0100
+Subject: [PATCH 0946/1795] arm64: dts: renesas: r8a7795: move scif node into
+ alphabetical order
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Move scif node so that sub-nodes of the root node are in
+alphabetical order.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 1c6c924a49e0cd8f908409fb2a68570d9a4b2998)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index d12df6f2ff09..24e9209ea54e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -165,13 +165,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* External SCIF clock - to be overridden by boards that provide it */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External PCIe clock - can be overridden by the board */
+ 	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+@@ -208,6 +201,13 @@
+ 		method = "smc";
+ 	};
+ 
++	/* External SCIF clock - to be overridden by boards that provide it */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	soc: soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+-- 
+2.19.0
+
diff --git a/patches/0947-arm64-dts-renesas-r8a7795-Add-OPPs-table-for-cpu-dev.patch b/patches/0947-arm64-dts-renesas-r8a7795-Add-OPPs-table-for-cpu-dev.patch
new file mode 100644
index 00000000000000..54f1bd7418f472
--- /dev/null
+++ b/patches/0947-arm64-dts-renesas-r8a7795-Add-OPPs-table-for-cpu-dev.patch
@@ -0,0 +1,157 @@
+From 7c1155dd38e19759becb7e26ed77554ebc4d1b15 Mon Sep 17 00:00:00 2001
+From: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Date: Wed, 3 Jan 2018 13:41:04 +0100
+Subject: [PATCH 0947/1795] arm64: dts: renesas: r8a7795: Add OPPs table for
+ cpu devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Define OOP tables for all CPUs.
+This allows CPUFreq to function.
+
+Based in part on work by Hien Dang.
+
+Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit dd149e851ace00a7832846e46ddefc6b181522c2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 61 ++++++++++++++++++++++++
+ 1 file changed, 61 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 24e9209ea54e..1485e6a8e112 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -41,6 +41,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a57_1: cpu@1 {
+@@ -50,6 +52,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a57_2: cpu@2 {
+@@ -59,6 +63,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a57_3: cpu@3 {
+@@ -68,6 +74,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a53_0: cpu@100 {
+@@ -77,6 +85,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_1: cpu@101 {
+@@ -86,6 +96,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_2: cpu@102 {
+@@ -95,6 +107,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_3: cpu@103 {
+@@ -104,6 +118,8 @@
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		L2_CA57: cache-controller-0 {
+@@ -165,6 +181,51 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	cluster0_opp: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1500000000 {
++			opp-hz = /bits/ 64 <1500000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++			opp-suspend;
++		};
++		opp-1600000000 {
++			opp-hz = /bits/ 64 <1600000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1700000000 {
++			opp-hz = /bits/ 64 <1700000000>;
++			opp-microvolt = <960000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++	};
++
++	cluster1_opp: opp_table1 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++	};
++
+ 	/* External PCIe clock - can be overridden by the board */
+ 	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0948-arm64-dts-renesas-r8a7796-Add-OPPs-table-for-cpu-dev.patch b/patches/0948-arm64-dts-renesas-r8a7796-Add-OPPs-table-for-cpu-dev.patch
new file mode 100644
index 00000000000000..fc6d16b31ae639
--- /dev/null
+++ b/patches/0948-arm64-dts-renesas-r8a7796-Add-OPPs-table-for-cpu-dev.patch
@@ -0,0 +1,144 @@
+From 6adaf101a67eb30b32ab5490514197651d49f2f2 Mon Sep 17 00:00:00 2001
+From: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Date: Wed, 3 Jan 2018 13:41:05 +0100
+Subject: [PATCH 0948/1795] arm64: dts: renesas: r8a7796: Add OPPs table for
+ cpu devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Define OOP tables for all CPUs.
+This allows CPUFreq to function.
+
+Based in part on work by Hien Dang.
+
+Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit da7e3113344fda50b10f1ad2c633abaaaf25d21b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index c5192d513d7d..e06bde6e2853 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -71,6 +71,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a57_1: cpu@1 {
+@@ -80,6 +82,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
++			operating-points-v2 = <&cluster0_opp>;
+ 		};
+ 
+ 		a53_0: cpu@100 {
+@@ -89,6 +93,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_1: cpu@101 {
+@@ -98,6 +104,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_2: cpu@102 {
+@@ -107,6 +115,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		a53_3: cpu@103 {
+@@ -116,6 +126,8 @@
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
++			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
++			operating-points-v2 = <&cluster1_opp>;
+ 		};
+ 
+ 		L2_CA57: cache-controller-0 {
+@@ -147,6 +159,56 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	cluster0_opp: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1500000000 {
++			opp-hz = /bits/ 64 <1500000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1600000000 {
++			opp-hz = /bits/ 64 <1600000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1700000000 {
++			opp-hz = /bits/ 64 <1700000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <960000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++	};
++
++	cluster1_opp: opp_table1 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++	};
++
+ 	/* External PCIe clock - can be overridden by the board */
+ 	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/0949-arm64-dts-renesas-r8a7796-add-thermal-cooling-manage.patch b/patches/0949-arm64-dts-renesas-r8a7796-add-thermal-cooling-manage.patch
new file mode 100644
index 00000000000000..51cc4c5931799d
--- /dev/null
+++ b/patches/0949-arm64-dts-renesas-r8a7796-add-thermal-cooling-manage.patch
@@ -0,0 +1,120 @@
+From b62cf1e27659c6ecaa094e2538f348332008c9f7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 4 Jan 2018 17:03:20 +0100
+Subject: [PATCH 0949/1795] arm64: dts: renesas: r8a7796: add thermal cooling
+ management
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add nodes and properties for thermal cooling management support.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Eduardo Valentin <edubezval@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 479e5d70a9cee635d0feda260eed3719fb565ca8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 38 ++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index e06bde6e2853..ef10fb548681 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -73,6 +73,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a57_1: cpu@1 {
+@@ -84,6 +85,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a53_0: cpu@100 {
+@@ -2060,12 +2062,24 @@
+ 			thermal-sensors = <&tsc 0>;
+ 
+ 			trips {
++				sensor1_passive: sensor1-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor1_crit: sensor1-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor1_passive>;
++					cooling-device = <&a57_0 5 5>;
++				};
++			};
+ 		};
+ 
+ 		sensor_thermal2: sensor-thermal2 {
+@@ -2074,12 +2088,24 @@
+ 			thermal-sensors = <&tsc 1>;
+ 
+ 			trips {
++				sensor2_passive: sensor2-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor2_crit: sensor2-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor2_passive>;
++					cooling-device = <&a57_0 5 5>;
++				};
++			};
+ 		};
+ 
+ 		sensor_thermal3: sensor-thermal3 {
+@@ -2088,12 +2114,24 @@
+ 			thermal-sensors = <&tsc 2>;
+ 
+ 			trips {
++				sensor3_passive: sensor3-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor3_crit: sensor3-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor3_passive>;
++					cooling-device = <&a57_0 5 5>;
++				};
++			};
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0950-arm64-dts-renesas-r8a7795-add-thermal-cooling-manage.patch b/patches/0950-arm64-dts-renesas-r8a7795-add-thermal-cooling-manage.patch
new file mode 100644
index 00000000000000..e719007ef0cf4b
--- /dev/null
+++ b/patches/0950-arm64-dts-renesas-r8a7795-add-thermal-cooling-manage.patch
@@ -0,0 +1,136 @@
+From ce62f35a087d27aa01d8d1bd8c933f067c880520 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 4 Jan 2018 17:03:19 +0100
+Subject: [PATCH 0950/1795] arm64: dts: renesas: r8a7795: add thermal cooling
+ management
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add nodes and properties for thermal cooling management support.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Eduardo Valentin <edubezval@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0c38c54ef9bc2a1062900adb01833e0b824f8462)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40 ++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 1485e6a8e112..19b7de57704c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -43,6 +43,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a57_1: cpu@1 {
+@@ -54,6 +55,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a57_2: cpu@2 {
+@@ -65,6 +67,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a57_3: cpu@3 {
+@@ -76,6 +79,7 @@
+ 			enable-method = "psci";
+ 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ 			operating-points-v2 = <&cluster0_opp>;
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		a53_0: cpu@100 {
+@@ -2418,12 +2422,24 @@
+ 			thermal-sensors = <&tsc 0>;
+ 
+ 			trips {
++				sensor1_passive: sensor1-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor1_crit: sensor1-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor1_passive>;
++					cooling-device = <&a57_0 4 4>;
++				};
++			};
+ 		};
+ 
+ 		sensor_thermal2: sensor-thermal2 {
+@@ -2432,12 +2448,24 @@
+ 			thermal-sensors = <&tsc 1>;
+ 
+ 			trips {
++				sensor2_passive: sensor2-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor2_crit: sensor2-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor2_passive>;
++					cooling-device = <&a57_0 4 4>;
++				};
++			};
+ 		};
+ 
+ 		sensor_thermal3: sensor-thermal3 {
+@@ -2446,12 +2474,24 @@
+ 			thermal-sensors = <&tsc 2>;
+ 
+ 			trips {
++				sensor3_passive: sensor3-passive {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
+ 				sensor3_crit: sensor3-crit {
+ 					temperature = <120000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
++
++			cooling-maps {
++				map0 {
++					trip = <&sensor3_passive>;
++					cooling-device = <&a57_0 4 4>;
++				};
++			};
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/0951-arm64-dts-renesas-salvator-common-add-GPIO-extender.patch b/patches/0951-arm64-dts-renesas-salvator-common-add-GPIO-extender.patch
new file mode 100644
index 00000000000000..8d1d20b0cdc093
--- /dev/null
+++ b/patches/0951-arm64-dts-renesas-salvator-common-add-GPIO-extender.patch
@@ -0,0 +1,38 @@
+From 4e7731077bae3777afb2606be6eda25681ad8da0 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Fri, 22 Dec 2017 21:11:46 +0100
+Subject: [PATCH 0951/1795] arm64: dts: renesas: salvator-common: add GPIO
+ extender
+
+We need to configure its GPIOs later.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ece30287af4e08e681f27c3d58853b68cdde658b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 97b1c1cfa222..acb62c73839f 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -336,6 +336,13 @@
+ &i2c4 {
+ 	status = "okay";
+ 
++	pca9654: gpio@20 {
++		compatible = "onnn,pca9654";
++		reg = <0x20>;
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++
+ 	csa_vdd: adc@7c {
+ 		compatible = "maxim,max9611";
+ 		reg = <0x7c>;
+-- 
+2.19.0
+
diff --git a/patches/0952-arm64-dts-renesas-r8a77970-move-node-which-has-no-re.patch b/patches/0952-arm64-dts-renesas-r8a77970-move-node-which-has-no-re.patch
new file mode 100644
index 00000000000000..aabc534b805a99
--- /dev/null
+++ b/patches/0952-arm64-dts-renesas-r8a77970-move-node-which-has-no-re.patch
@@ -0,0 +1,65 @@
+From 1e045d0b2537be0d545e1554fb64a200e521d00c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 13:25:49 +0100
+Subject: [PATCH 0952/1795] arm64: dts: renesas: r8a77970: move node which has
+ no reg property out of bus
+
+Move timer node from soc node to root node.  The node that have been moved
+do not have any register properties and thus shouldn't be placed on the
+bus.
+
+This problem is flagged by the compiler as follows:
+$ make W=1
+...
+  DTC     arch/arm64/boot/dts/renesas/r8a77970-eagle.dtb
+arch/arm64/boot/dts/renesas/r8a77970-eagle.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+  DTC     arch/arm64/boot/dts/renesas/r8a77970-v3msk.dtb
+arch/arm64/boot/dts/renesas/r8a77970-v3msk.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7569d1ee01c75b8581521bc67e595a575a7eafce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index c35a117fc447..566a7f704830 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -92,18 +92,6 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv8-timer";
+-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+-						  IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+-						  IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		rwdt: watchdog@e6020000 {
+ 			compatible = "renesas,r8a77970-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -442,4 +430,12 @@
+ 			#size-cells = <0>;
+ 		};
+ 	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0953-arm64-dts-renesas-r8a77995-move-nodes-which-have-no-.patch b/patches/0953-arm64-dts-renesas-r8a77995-move-nodes-which-have-no-.patch
new file mode 100644
index 00000000000000..1b6a13c752f5e9
--- /dev/null
+++ b/patches/0953-arm64-dts-renesas-r8a77995-move-nodes-which-have-no-.patch
@@ -0,0 +1,87 @@
+From 5a58ffc7897e293b395b305c823cdbbf64ce8507 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 13:24:42 +0100
+Subject: [PATCH 0953/1795] arm64: dts: renesas: r8a77995: move nodes which
+ have no reg property out of bus
+
+Move pmu_a53 and timer nodes from soc node to root node.  The nodes that
+have been moved do not have any register properties and thus shouldn't be
+placed on the bus.
+
+This problem is flagged by the compiler as follows:
+$ make W=1
+...
+arch/arm64/boot/dts/renesas/r8a77995-draak.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
+arch/arm64/boot/dts/renesas/r8a77995-draak.dtb: Warning (simple_bus_reg): Node /soc/pmu_a53 missing or empty reg/ranges property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f320eead5dad37f296201bbcc00a88188a63a7da)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++-------------
+ 1 file changed, 13 insertions(+), 17 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index cff42cd1a6c8..23f763beab46 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -58,6 +58,11 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu_a53 {
++		compatible = "arm,cortex-a53-pmu";
++		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+@@ -88,18 +93,6 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
+-		timer {
+-			compatible = "arm,armv8-timer";
+-			interrupts = <GIC_PPI 13
+-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 14
+-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 11
+-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				     <GIC_PPI 10
+-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+-		};
+-
+ 		rwdt: watchdog@e6020000 {
+ 			compatible = "renesas,r8a77995-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -110,11 +103,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		pmu_a53 {
+-			compatible = "arm,cortex-a53-pmu";
+-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+-		};
+-
+ 		ipmmu_vi0: mmu@febd0000 {
+ 			compatible = "renesas,ipmmu-r8a77995";
+ 			reg = <0 0xfebd0000 0 0x1000>;
+@@ -637,4 +625,12 @@
+ 			status = "disabled";
+ 		};
+ 	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/0954-arm64-dts-renesas-r8a7795-update-register-size-for-t.patch b/patches/0954-arm64-dts-renesas-r8a7795-update-register-size-for-t.patch
new file mode 100644
index 00000000000000..9a74f3a8367e90
--- /dev/null
+++ b/patches/0954-arm64-dts-renesas-r8a7795-update-register-size-for-t.patch
@@ -0,0 +1,49 @@
+From a5129cae8a0a37f1f7b25eba8745dea8ad532be9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 5 Jan 2018 16:54:46 +0100
+Subject: [PATCH 0954/1795] arm64: dts: renesas: r8a7795: update register size
+ for thermal
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To be able to read fused calibration values from hardware the size of
+the register resource of TSC1 needs to be incremented to cover one more
+register which holds the information if the calibration values have been
+fused or not.
+
+Instead of increasing TSC1 size to the value from the datasheet update
+all TSC's size to the smallest granularity of the address decoder
+circuitry
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cd8325dc194d6fa0707c9d5b427ca1fed6893b53)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 19b7de57704c..ce85704976f0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2385,9 +2385,9 @@
+ 
+ 		tsc: thermal@e6198000 {
+ 			compatible = "renesas,r8a7795-thermal";
+-			reg = <0 0xe6198000 0 0x68>,
+-			      <0 0xe61a0000 0 0x5c>,
+-			      <0 0xe61a8000 0 0x5c>;
++			reg = <0 0xe6198000 0 0x100>,
++			      <0 0xe61a0000 0 0x100>,
++			      <0 0xe61a8000 0 0x100>;
+ 			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0955-arm64-dts-renesas-r8a7796-update-register-size-for-t.patch b/patches/0955-arm64-dts-renesas-r8a7796-update-register-size-for-t.patch
new file mode 100644
index 00000000000000..b88ad775cc4b24
--- /dev/null
+++ b/patches/0955-arm64-dts-renesas-r8a7796-update-register-size-for-t.patch
@@ -0,0 +1,49 @@
+From fd269024408ba35a03bddab44d6faa2bf10ceacf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 5 Jan 2018 16:54:47 +0100
+Subject: [PATCH 0955/1795] arm64: dts: renesas: r8a7796: update register size
+ for thermal
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To be able to read fused calibration values from hardware the size of
+the register resource of TSC1 needs to be incremented to cover one more
+register which holds the information if the calibration values have been
+fused or not.
+
+Instead of increasing TSC1 size to the value from the datasheet update
+all TSC's size to the smallest granularity of the address decoder
+circuitry.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a052d934a4e03a81e1f6cf1c63ac693b04e9a441)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index ef10fb548681..f8e9313f9405 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1625,9 +1625,9 @@
+ 
+ 		tsc: thermal@e6198000 {
+ 			compatible = "renesas,r8a7796-thermal";
+-			reg = <0 0xe6198000 0 0x68>,
+-			      <0 0xe61a0000 0 0x5c>,
+-			      <0 0xe61a8000 0 0x5c>;
++			reg = <0 0xe6198000 0 0x100>,
++			      <0 0xe61a0000 0 0x100>,
++			      <0 0xe61a8000 0 0x100>;
+ 			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/0956-arm64-dts-renesas-r8a77995-add-I2C-support.patch b/patches/0956-arm64-dts-renesas-r8a77995-add-I2C-support.patch
new file mode 100644
index 00000000000000..dda889420b45f4
--- /dev/null
+++ b/patches/0956-arm64-dts-renesas-r8a77995-add-I2C-support.patch
@@ -0,0 +1,99 @@
+From ad9850214602c079ebae4808e52789e0794bb516 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 29 Jan 2018 16:45:44 +0100
+Subject: [PATCH 0956/1795] arm64: dts: renesas: r8a77995: add I2C support
+
+Defines R-Car D3 I2C controllers 0-3.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ffcd060fd51682d2695da7334aa607a807e3838e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 67 +++++++++++++++++++++++
+ 1 file changed, 67 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 23f763beab46..22e633c87d4c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -536,6 +536,73 @@
+ 			status = "disabled";
+ 		};
+ 
++		i2c0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6500000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6510000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e66d0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d0000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
+ 		pwm0: pwm@e6e30000 {
+ 			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e30000 0 0x8>;
+-- 
+2.19.0
+
diff --git a/patches/0957-arm64-dts-renesas-draak-enable-I2C-controller-0-and-.patch b/patches/0957-arm64-dts-renesas-draak-enable-I2C-controller-0-and-.patch
new file mode 100644
index 00000000000000..c33504f40052d8
--- /dev/null
+++ b/patches/0957-arm64-dts-renesas-draak-enable-I2C-controller-0-and-.patch
@@ -0,0 +1,57 @@
+From 2849c004e986d1dc7455eb2de5d9ba98281987af Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 29 Jan 2018 16:45:45 +0100
+Subject: [PATCH 0957/1795] arm64: dts: renesas: draak: enable I2C controller 0
+ and EEPROM
+
+Enables EEPROM on I2C0 on the Draak board.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 86e7a972adec5093e24e888ae3a949ee185dc533)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 09de73b11db8..6ff9d3eb7540 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -46,6 +46,11 @@
+ 		};
+ 	};
+ 
++	i2c0_pins: i2c0 {
++		groups = "i2c0";
++		function = "i2c0";
++	};
++
+ 	pwm0_pins: pwm0 {
+ 		groups = "pwm0_c";
+ 		function = "pwm0";
+@@ -67,6 +72,18 @@
+ 	};
+ };
+ 
++&i2c0 {
++	pinctrl-0 = <&i2c0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	eeprom@50 {
++		compatible = "rohm,br24t01", "atmel,24c01";
++		reg = <0x50>;
++		pagesize = <8>;
++	};
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0958-arm64-dts-renesas-draak-enable-I2C-controller-1.patch b/patches/0958-arm64-dts-renesas-draak-enable-I2C-controller-1.patch
new file mode 100644
index 00000000000000..12530cdd445bba
--- /dev/null
+++ b/patches/0958-arm64-dts-renesas-draak-enable-I2C-controller-1.patch
@@ -0,0 +1,50 @@
+From 2b6e03e83435f958e8dc78b2bba4c066e4a8f266 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 29 Jan 2018 16:45:46 +0100
+Subject: [PATCH 0958/1795] arm64: dts: renesas: draak: enable I2C controller 1
+
+No devices to add, I2C1 has an external connector only.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 41337aa1556a38a0b6861447ba7861c3a34bc204)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 6ff9d3eb7540..af07da240be0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -51,6 +51,11 @@
+ 		function = "i2c0";
+ 	};
+ 
++	i2c1_pins: i2c1 {
++		groups = "i2c1";
++		function = "i2c1";
++	};
++
+ 	pwm0_pins: pwm0 {
+ 		groups = "pwm0_c";
+ 		function = "pwm0";
+@@ -84,6 +89,12 @@
+ 	};
+ };
+ 
++&i2c1 {
++	pinctrl-0 = <&i2c1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0959-arm64-dts-renesas-initial-R8A77980-SoC-device-tree.patch b/patches/0959-arm64-dts-renesas-initial-R8A77980-SoC-device-tree.patch
new file mode 100644
index 00000000000000..6a2c052dfdb3bd
--- /dev/null
+++ b/patches/0959-arm64-dts-renesas-initial-R8A77980-SoC-device-tree.patch
@@ -0,0 +1,154 @@
+From 4e4a4fdba06a82aac2fa63b7b2eedc7c7b60cc20 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:33:39 +0300
+Subject: [PATCH 0959/1795] arm64: dts: renesas: initial R8A77980 SoC device
+ tree
+
+The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer,
+CPG, RST, and SYSC.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f3a54d6c17f5ec826ff81e4f9f35a11e63211c53)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 122 ++++++++++++++++++++++
+ 1 file changed, 122 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77980.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+new file mode 100644
+index 000000000000..6a92bbf55013
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -0,0 +1,122 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the r8a77980 SoC
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/ {
++	compatible = "renesas,r8a77980";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		a53_0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53", "arm,armv8";
++			reg = <0>;
++			clocks = <&cpg CPG_CORE 0>;
++			power-domains = <&sysc 5>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++		};
++
++		L2_CA53: cache-controller {
++			compatible = "cache";
++			power-domains = <&sysc 21>;
++			cache-unified;
++			cache-level = <2>;
++		};
++	};
++
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	extalr_clk: extalr {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77980-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77980-rst";
++			reg = <0 0xe6160000 0 0x200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77980-sysc";
++			reg = <0 0xe6180000 0 0x440>;
++			#power-domain-cells = <1>;
++		};
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
++				      IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
++		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
++				       IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
++				       IRQ_TYPE_LEVEL_LOW)>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/0960-arm64-dts-renesas-r8a77980-add-SYS-DMAC-support.patch b/patches/0960-arm64-dts-renesas-r8a77980-add-SYS-DMAC-support.patch
new file mode 100644
index 00000000000000..186d5f664b8c07
--- /dev/null
+++ b/patches/0960-arm64-dts-renesas-r8a77980-add-SYS-DMAC-support.patch
@@ -0,0 +1,102 @@
+From dc4e9b6c1ef239aa02df43483110c089331421c1 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:36:16 +0300
+Subject: [PATCH 0960/1795] arm64: dts: renesas: r8a77980: add SYS-DMAC support
+
+Describe SYS-DMAC1/2 in the R8A77980 device tree.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 00d3375f918d503326bc4e4550b023d1a71e8d29)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 68 +++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 6a92bbf55013..e5c7cf391334 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -85,6 +85,74 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		dmac1: dma-controller@e7300000 {
++			compatible = "renesas,dmac-r8a77980",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++		};
++
++		dmac2: dma-controller@e7310000 {
++			compatible = "renesas,dmac-r8a77980",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 217>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 217>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++		};
++
+ 		gic: interrupt-controller@f1010000 {
+ 			compatible = "arm,gic-400";
+ 			#interrupt-cells = <3>;
+-- 
+2.19.0
+
diff --git a/patches/0961-arm64-dts-renesas-r8a77970-Remove-non-existing-STBE-.patch b/patches/0961-arm64-dts-renesas-r8a77970-Remove-non-existing-STBE-.patch
new file mode 100644
index 00000000000000..13b5ac67ee9610
--- /dev/null
+++ b/patches/0961-arm64-dts-renesas-r8a77970-Remove-non-existing-STBE-.patch
@@ -0,0 +1,36 @@
+From 2c4843ba7b1a5162644375e2dafc0e5bc2a264f6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 6 Feb 2018 14:05:53 +0100
+Subject: [PATCH 0961/1795] arm64: dts: renesas: r8a77970: Remove non-existing
+ STBE region
+
+R-Car V3M does not have the Stream Buffer for EtherAVB-IF (STBE).
+
+Note that the RAVB driver does not use this region.
+
+Fixes: bea2ab136eaacec2 ("arm64: dts: renesas: r8a77970: add EtherAVB support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d0d2ad1ff6e379a8ca6c8e814433e54637fb1516)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 566a7f704830..fc397ccd06b6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -388,7 +388,7 @@
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77970",
+ 				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			reg = <0 0xe6800000 0 0x800>;
+ 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0962-arm64-dts-renesas-r8a77995-Remove-non-existing-STBE-.patch b/patches/0962-arm64-dts-renesas-r8a77995-Remove-non-existing-STBE-.patch
new file mode 100644
index 00000000000000..d672053d418103
--- /dev/null
+++ b/patches/0962-arm64-dts-renesas-r8a77995-Remove-non-existing-STBE-.patch
@@ -0,0 +1,36 @@
+From ba38cbe344fe6ab45820689cb0c378305619b4b1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 6 Feb 2018 14:05:54 +0100
+Subject: [PATCH 0962/1795] arm64: dts: renesas: r8a77995: Remove non-existing
+ STBE region
+
+R-Car D3 does not have the Stream Buffer for EtherAVB-IF (STBE).
+
+Note that the RAVB driver does not use this region.
+
+Fixes: f9ba0c4cfe6169b7 ("arm64: dts: renesas: r8a77995: Add EthernetAVB device node")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fa3d4c67dfe920515a3d840de983a2b3e77d3b94)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 22e633c87d4c..cd3c6a30fc47 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -476,7 +476,7 @@
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77995",
+ 				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			reg = <0 0xe6800000 0 0x800>;
+ 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-- 
+2.19.0
+
diff --git a/patches/0963-arm64-defconfig-enable-MESON-EFUSE.patch b/patches/0963-arm64-defconfig-enable-MESON-EFUSE.patch
new file mode 100644
index 00000000000000..13825c48a730da
--- /dev/null
+++ b/patches/0963-arm64-defconfig-enable-MESON-EFUSE.patch
@@ -0,0 +1,31 @@
+From 20738e99b85450f429842e47763c50b3fdd3fd5f Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Wed, 3 Jan 2018 16:54:52 +0100
+Subject: [PATCH 0963/1795] arm64: defconfig: enable MESON EFUSE
+
+Enable nvmem meson efuse driver as a module
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Kevin Hilman <khilman@baylibre.com>
+(cherry picked from commit 266c157de3b21b6da3e015085dda48cfa9f0f76d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 20caba01c315..b2a025b46937 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -565,6 +565,7 @@ CONFIG_PHY_XGENE=y
+ CONFIG_PHY_TEGRA_XUSB=y
+ CONFIG_QCOM_L2_PMU=y
+ CONFIG_QCOM_L3_PMU=y
++CONFIG_MESON_EFUSE=m
+ CONFIG_UNIPHIER_EFUSE=y
+ CONFIG_TEE=y
+ CONFIG_OPTEE=y
+-- 
+2.19.0
+
diff --git a/patches/0964-arm64-dts-renesas-r8a77970-add-PFC-support.patch b/patches/0964-arm64-dts-renesas-r8a77970-add-PFC-support.patch
new file mode 100644
index 00000000000000..c7f70f5a13d66c
--- /dev/null
+++ b/patches/0964-arm64-dts-renesas-r8a77970-add-PFC-support.patch
@@ -0,0 +1,36 @@
+From fbde49412bdfad46e9c8d55377f7b10c6ffe9048 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 10 Nov 2017 23:02:19 +0300
+Subject: [PATCH 0964/1795] arm64: dts: renesas: r8a77970: add PFC support
+
+Define the generic R8A77970 part of the PFC device node.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 15981bab23cc1caf7070fa10ac39efa5d928dee9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index fc397ccd06b6..8eccfec83c9c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -166,6 +166,11 @@
+ 			#iommu-cells = <1>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77970";
++			reg = <0 0xe6060000 0 0x504>;
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0965-arm64-dts-renesas-eagle-add-SCIF0-pins.patch b/patches/0965-arm64-dts-renesas-eagle-add-SCIF0-pins.patch
new file mode 100644
index 00000000000000..56e3d16f4709f8
--- /dev/null
+++ b/patches/0965-arm64-dts-renesas-eagle-add-SCIF0-pins.patch
@@ -0,0 +1,47 @@
+From 56a0d635d8a54b16779f8697289f1947a1e81fb5 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 10 Nov 2017 23:02:20 +0300
+Subject: [PATCH 0965/1795] arm64: dts: renesas: eagle: add SCIF0 pins
+
+Add the (previously omitted) SCIF0 pin data to the Eagle board's
+device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 31bded67ad215be592deda0c9ee8acdfe2067243)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index 8fe5c193e049..f174103d2206 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -52,11 +52,21 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&pfc {
++	scif0_pins: scif0 {
++		groups = "scif0_data";
++		function = "scif0";
++	};
++};
++
+ &rwdt {
+ 	timeout-sec = <60>;
+ 	status = "okay";
+ };
+ 
+ &scif0 {
++	pinctrl-0 = <&scif0_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0966-arm64-dts-renesas-r8a77970-add-GPIO-support.patch b/patches/0966-arm64-dts-renesas-r8a77970-add-GPIO-support.patch
new file mode 100644
index 00000000000000..175851ecadb74a
--- /dev/null
+++ b/patches/0966-arm64-dts-renesas-r8a77970-add-GPIO-support.patch
@@ -0,0 +1,125 @@
+From d2fbae20cbfc41650857b06cf5fd14846e98052a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 13 Feb 2018 14:22:52 +0300
+Subject: [PATCH 0966/1795] arm64: dts: renesas: r8a77970: add GPIO support
+
+Describe all 6 GPIO controllers in the R8A77970 device tree.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9618b2cbcf22fa3c206cac3984288413ef4d7194)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 90 +++++++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 8eccfec83c9c..31eeca1531f6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -171,6 +171,96 @@
+ 			reg = <0 0xe6060000 0 0x504>;
+ 		};
+ 
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 22>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
++
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 28>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
++
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 17>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
++
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 17>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
++
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 6>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
++
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a77970",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 15>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+-- 
+2.19.0
+
diff --git a/patches/0967-arm64-dts-renesas-eagle-specify-EtherAVB-PHY-IRQ.patch b/patches/0967-arm64-dts-renesas-eagle-specify-EtherAVB-PHY-IRQ.patch
new file mode 100644
index 00000000000000..118bade943e30a
--- /dev/null
+++ b/patches/0967-arm64-dts-renesas-eagle-specify-EtherAVB-PHY-IRQ.patch
@@ -0,0 +1,35 @@
+From e1bfbfa518d5fa5e6ddf46dab23621c1d8dcb94d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 13 Feb 2018 14:24:14 +0300
+Subject: [PATCH 0967/1795] arm64: dts: renesas: eagle: specify EtherAVB PHY
+ IRQ
+
+Specify  EtherAVB PHY IRQ  in the Eagle board's device tree, now that we
+have the GPIO support (previously phylib had to resort to polling).
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 51671b265b2915846826da407a4ab7d4ba52f404)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index f174103d2206..cb4bd40584cf 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -41,6 +41,8 @@
+ 	phy0: ethernet-phy@0 {
+ 		rxc-skew-ps = <1500>;
+ 		reg = <0>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ 	};
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/0968-arm64-dts-renesas-r8a77995-add-FCPV-nodes.patch b/patches/0968-arm64-dts-renesas-r8a77995-add-FCPV-nodes.patch
new file mode 100644
index 00000000000000..f78561f17d0fcd
--- /dev/null
+++ b/patches/0968-arm64-dts-renesas-r8a77995-add-FCPV-nodes.patch
@@ -0,0 +1,59 @@
+From ebac6e5f969925b3e5bf3747822def26ad8b96ef Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 14 Feb 2018 09:55:04 +0000
+Subject: [PATCH 0968/1795] arm64: dts: renesas: r8a77995: add FCPV nodes
+
+The FCPVB handles the interface between the VSPB and memory, while the
+FCPVD handles the interface between the VSPD and memory.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d7ef367be983185f336ac6e310ac9e469f53cd4a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 27 +++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index cd3c6a30fc47..196a917afea6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -691,6 +691,33 @@
+ 			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
++
++		fcpvb0: fcp@fe96f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfe96f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 607>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 607>;
++			iommus = <&ipmmu_vp0 5>;
++		};
++
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
++		};
++
++		fcpvd1: fcp@fea2f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea2f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 602>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 602>;
++			iommus = <&ipmmu_vi0 9>;
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/0969-arm64-dts-renesas-r8a77995-add-VSP-instances.patch b/patches/0969-arm64-dts-renesas-r8a77995-add-VSP-instances.patch
new file mode 100644
index 00000000000000..dac4fc41d8709b
--- /dev/null
+++ b/patches/0969-arm64-dts-renesas-r8a77995-add-VSP-instances.patch
@@ -0,0 +1,79 @@
+From ac3d86ac8ff26fa8fd28d1581e4ea86b645682b4 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 14 Feb 2018 09:55:05 +0000
+Subject: [PATCH 0969/1795] arm64: dts: renesas: r8a77995: add VSP instances
+
+The r8a77995 has a VSPBS to support image processing such as blending of
+two input images, and has two VSPDs to handle display pipelines with a
+DU.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+[simon: updated base address of vsp node to fea28000]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 295952a183d3d10d4f532c623c51c30e25d6a421)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 +++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 196a917afea6..621cf30e521d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -692,6 +692,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		vspbs: vsp@fe960000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe960000 0 0x8000>;
++			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 627>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 627>;
++			renesas,fcp = <&fcpvb0>;
++		};
++
+ 		fcpvb0: fcp@fe96f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe96f000 0 0x200>;
+@@ -701,6 +711,16 @@
+ 			iommus = <&ipmmu_vp0 5>;
+ 		};
+ 
++		vspd0: vsp@fea20000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea20000 0 0x8000>;
++			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 623>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 623>;
++			renesas,fcp = <&fcpvd0>;
++		};
++
+ 		fcpvd0: fcp@fea27000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfea27000 0 0x200>;
+@@ -710,6 +730,16 @@
+ 			iommus = <&ipmmu_vi0 8>;
+ 		};
+ 
++		vspd1: vsp@fea28000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea28000 0 0x8000>;
++			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 622>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 622>;
++			renesas,fcp = <&fcpvd1>;
++		};
++
+ 		fcpvd1: fcp@fea2f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfea2f000 0 0x200>;
+-- 
+2.19.0
+
diff --git a/patches/0970-arm64-dts-renesas-draak-enable-SDHI2.patch b/patches/0970-arm64-dts-renesas-draak-enable-SDHI2.patch
new file mode 100644
index 00000000000000..ea8be69583f4fc
--- /dev/null
+++ b/patches/0970-arm64-dts-renesas-draak-enable-SDHI2.patch
@@ -0,0 +1,89 @@
+From 230e66eec5fc0dc7983c859235ab1946bd9bf87c Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 29 Nov 2017 17:06:46 +0100
+Subject: [PATCH 0970/1795] arm64: dts: renesas: draak: enable SDHI2
+
+The single SDHI controller is connected to eMMC.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9d9505a2f4eb6aa29639c90b8ad596e62314faec)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77995-draak.dts | 44 +++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index af07da240be0..7ea6709d706d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -32,6 +32,24 @@
+ 		/* first 128MB is reserved for secure area. */
+ 		reg = <0x0 0x48000000 0x0 0x18000000>;
+ 	};
++
++	reg_1p8v: regulator0 {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_3p3v: regulator1 {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
+ };
+ 
+ &extal_clk {
+@@ -71,6 +89,18 @@
+ 		function = "scif2";
+ 	};
+ 
++	sdhi2_pins: sd2 {
++		groups = "mmc_data8", "mmc_ctrl";
++		function = "mmc";
++		power-source = <1800>;
++	};
++
++	sdhi2_pins_uhs: sd2_uhs {
++		groups = "mmc_data8", "mmc_ctrl";
++		function = "mmc";
++		power-source = <1800>;
++	};
++
+ 	usb0_pins: usb0 {
+ 		groups = "usb0";
+ 		function = "usb0";
+@@ -125,6 +155,20 @@
+ 	status = "okay";
+ };
+ 
++&sdhi2 {
++	/* used for on-board eMMC */
++	pinctrl-0 = <&sdhi2_pins>;
++	pinctrl-1 = <&sdhi2_pins_uhs>;
++	pinctrl-names = "default", "state_uhs";
++
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	bus-width = <8>;
++	mmc-hs200-1_8v;
++	non-removable;
++	status = "okay";
++};
++
+ &usb2_phy0 {
+ 	pinctrl-0 = <&usb0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/0971-arm64-dts-renesas-r8a77995-add-DU-support.patch b/patches/0971-arm64-dts-renesas-r8a77995-add-DU-support.patch
new file mode 100644
index 00000000000000..97919ef404b8a7
--- /dev/null
+++ b/patches/0971-arm64-dts-renesas-r8a77995-add-DU-support.patch
@@ -0,0 +1,66 @@
+From a0a4f20b7cfc37f70f83c3570a44a3da145200d3 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 15 Feb 2018 08:38:19 +0000
+Subject: [PATCH 0971/1795] arm64: dts: renesas: r8a77995: add DU support
+
+Define the generic r8a77995 part of the DU device node.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 18f1a773e3f9e6d1eb5549d98bae6f2959edecf2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 35 +++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 621cf30e521d..bcf737a20636 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -748,6 +748,41 @@
+ 			resets = <&cpg 602>;
+ 			iommus = <&ipmmu_vi0 9>;
+ 		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a77995";
++			reg = <0 0xfeb00000 0 0x80000>;
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			vsps = <&vspd0 0 &vspd1 0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					du_out_lvds1: endpoint {
++					};
++				};
++			};
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/0972-arm64-dts-renesas-r8a7795-es1-Fix-register-mappings-.patch b/patches/0972-arm64-dts-renesas-r8a7795-es1-Fix-register-mappings-.patch
new file mode 100644
index 00000000000000..5f1e2d9cc37c85
--- /dev/null
+++ b/patches/0972-arm64-dts-renesas-r8a7795-es1-Fix-register-mappings-.patch
@@ -0,0 +1,35 @@
+From 94babe2e3d4a678def6c70320a2644b54cc2d134 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 14 Feb 2018 09:55:06 +0000
+Subject: [PATCH 0972/1795] arm64: dts: renesas: r8a7795-es1: Fix register
+ mappings on VSPs
+
+The VSPD includes a CLUT on RPF2. Ensure that the register space is
+mapped correctly to support this.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d9366032b63bb544fd7d2fd290a922e8484a52c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 26769a11a190..f1d5e90503d5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -80,7 +80,7 @@
+ 
+ 	vspd3: vsp@fea38000 {
+ 		compatible = "renesas,vsp2";
+-		reg = <0 0xfea38000 0 0x4000>;
++		reg = <0 0xfea38000 0 0x8000>;
+ 		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 620>;
+ 		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/0973-arm64-dts-renesas-r8a7795-Fix-register-mappings-on-V.patch b/patches/0973-arm64-dts-renesas-r8a7795-Fix-register-mappings-on-V.patch
new file mode 100644
index 00000000000000..aa5d53afcdedb6
--- /dev/null
+++ b/patches/0973-arm64-dts-renesas-r8a7795-Fix-register-mappings-on-V.patch
@@ -0,0 +1,53 @@
+From cc3e8b7f8fbede22cb315bf114c4257a03bdb19d Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 14 Feb 2018 09:55:07 +0000
+Subject: [PATCH 0973/1795] arm64: dts: renesas: r8a7795: Fix register mappings
+ on VSPs
+
+The VSPD includes a CLUT on RPF2. Ensure that the register space is
+mapped correctly to support this.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c5dcfe6552f418df8db03e92e645339cdf746e34)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index ce85704976f0..9dc2b43e59f5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2208,7 +2208,7 @@
+ 
+ 		vspd0: vsp@fea20000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea20000 0 0x4000>;
++			reg = <0 0xfea20000 0 0x8000>;
+ 			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 623>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+@@ -2228,7 +2228,7 @@
+ 
+ 		vspd1: vsp@fea28000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea28000 0 0x4000>;
++			reg = <0 0xfea28000 0 0x8000>;
+ 			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 622>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+@@ -2248,7 +2248,7 @@
+ 
+ 		vspd2: vsp@fea30000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea30000 0 0x4000>;
++			reg = <0 0xfea30000 0 0x8000>;
+ 			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 621>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/0974-arm64-dts-renesas-r8a7796-Fix-register-mappings-on-V.patch b/patches/0974-arm64-dts-renesas-r8a7796-Fix-register-mappings-on-V.patch
new file mode 100644
index 00000000000000..95c7f19ea1e0c5
--- /dev/null
+++ b/patches/0974-arm64-dts-renesas-r8a7796-Fix-register-mappings-on-V.patch
@@ -0,0 +1,53 @@
+From 552531775aa70c27c1a74453c2f954e654bc3ed4 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 14 Feb 2018 09:55:08 +0000
+Subject: [PATCH 0974/1795] arm64: dts: renesas: r8a7796: Fix register mappings
+ on VSPs
+
+The VSPD includes a CLUT on RPF2. Ensure that the register space is
+mapped correctly to support this.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4361e56b751bbebf6a8660cd41429d8a3eb5e278)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index f8e9313f9405..157bd28014ed 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1903,7 +1903,7 @@
+ 
+ 		vspd0: vsp@fea20000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea20000 0 0x4000>;
++			reg = <0 0xfea20000 0 0x8000>;
+ 			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 623>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+@@ -1923,7 +1923,7 @@
+ 
+ 		vspd1: vsp@fea28000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea28000 0 0x4000>;
++			reg = <0 0xfea28000 0 0x8000>;
+ 			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 622>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+@@ -1943,7 +1943,7 @@
+ 
+ 		vspd2: vsp@fea30000 {
+ 			compatible = "renesas,vsp2";
+-			reg = <0 0xfea30000 0 0x4000>;
++			reg = <0 0xfea30000 0 0x8000>;
+ 			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 621>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/0975-arm64-dts-renesas-draak-Enable-DU.patch b/patches/0975-arm64-dts-renesas-draak-Enable-DU.patch
new file mode 100644
index 00000000000000..691c835b5376d3
--- /dev/null
+++ b/patches/0975-arm64-dts-renesas-draak-Enable-DU.patch
@@ -0,0 +1,96 @@
+From bbb28ef6c585bddfefc5e31704288008d288f55b Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 16 Feb 2018 12:32:35 +0000
+Subject: [PATCH 0975/1795] arm64: dts: renesas: draak: Enable DU
+
+Enable the DU, providing only the VGA output for now.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cfdec2af68acb32c805aaa454f151f8681e07673)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77995-draak.dts | 51 +++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 7ea6709d706d..34c7f58417ba 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -27,6 +27,38 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	vga {
++		compatible = "vga-connector";
++
++		port {
++			vga_in: endpoint {
++				remote-endpoint = <&adv7123_out>;
++			};
++		};
++	};
++
++	vga-encoder {
++		compatible = "adi,adv7123";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7123_in: endpoint {
++					remote-endpoint = <&du_out_rgb>;
++				};
++			};
++			port@1 {
++				reg = <1>;
++				adv7123_out: endpoint {
++					remote-endpoint = <&vga_in>;
++				};
++			};
++		};
++	};
++
+ 	memory@48000000 {
+ 		device_type = "memory";
+ 		/* first 128MB is reserved for secure area. */
+@@ -64,6 +96,11 @@
+ 		};
+ 	};
+ 
++	du_pins: du {
++		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
++		function = "du";
++	};
++
+ 	i2c0_pins: i2c0 {
+ 		groups = "i2c0";
+ 		function = "i2c0";
+@@ -125,6 +162,20 @@
+ 	status = "okay";
+ };
+ 
++&du {
++	pinctrl-0 = <&du_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	ports {
++		port@0 {
++			endpoint {
++				remote-endpoint = <&adv7123_in>;
++			};
++		};
++	};
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/0976-dt-bindings-arm-document-Condor-board-bindings.patch b/patches/0976-dt-bindings-arm-document-Condor-board-bindings.patch
new file mode 100644
index 00000000000000..2fc038da7131ac
--- /dev/null
+++ b/patches/0976-dt-bindings-arm-document-Condor-board-bindings.patch
@@ -0,0 +1,37 @@
+From 2758cdd7db1f0867760a73edbe9380cc6f7ac000 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:45:08 +0300
+Subject: [PATCH 0976/1795] dt-bindings: arm: document Condor board bindings
+
+Document the Condor device tree bindings, listing it as a supported board.
+
+This allows to use checkpatch.pl to validate .dts files referring to the
+Condor board.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8dc09f400a08108984c0bacc4af5cb395a3c5c22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 3ccad353acfa..41d3920aaa5e 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -59,6 +59,8 @@ Boards:
+     compatible = "renesas,blanche", "renesas,r8a7792"
+   - BOCK-W
+     compatible = "renesas,bockw", "renesas,r8a7778"
++  - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
++    compatible = "renesas,condor", "renesas,r8a77980"
+   - Draak (RTP0RC77995SEB0010S)
+     compatible = "renesas,draak", "renesas,r8a77995"
+   - Eagle (RTP0RC77970SEB0010S)
+-- 
+2.19.0
+
diff --git a/patches/0977-dt-bindings-arm-Document-Renesas-H2-based-Stout-DT-b.patch b/patches/0977-dt-bindings-arm-Document-Renesas-H2-based-Stout-DT-b.patch
new file mode 100644
index 00000000000000..bd33cb10cd39e6
--- /dev/null
+++ b/patches/0977-dt-bindings-arm-Document-Renesas-H2-based-Stout-DT-b.patch
@@ -0,0 +1,38 @@
+From 4b6cb43cee37d3c015528208cae5e4e2522305f1 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 15 Feb 2018 11:02:28 +0100
+Subject: [PATCH 0977/1795] dt-bindings: arm: Document Renesas H2-based Stout
+ DT bindings
+
+Document the Renesas H2 Stout (ADAS Starterkit) device tree bindings,
+listing it as a supported board.
+
+This allows to use checkpatch.pl to validate .dts files referring to
+the Stout board.
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 584fc22ceeda11d5ac40b1659d4708314d3d2675)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 41d3920aaa5e..98916b3864c2 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -116,6 +116,8 @@ Boards:
+     compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
+   - SK-RZG1M (YR8A77430S000BE)
+     compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
++  - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
++    compatible = "renesas,stout", "renesas,r8a7790"
+   - V3MSK
+     compatible = "renesas,v3msk", "renesas,r8a77970"
+   - Wheat
+-- 
+2.19.0
+
diff --git a/patches/0978-dt-bindings-arm-Document-R-Car-M3-N-SoC-DT-bindings.patch b/patches/0978-dt-bindings-arm-Document-R-Car-M3-N-SoC-DT-bindings.patch
new file mode 100644
index 00000000000000..1de2aba8f3f6c8
--- /dev/null
+++ b/patches/0978-dt-bindings-arm-Document-R-Car-M3-N-SoC-DT-bindings.patch
@@ -0,0 +1,36 @@
+From 2c5877452c0a30699e227a6fa7a8c1fa12678585 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 13 Feb 2018 10:45:48 +0100
+Subject: [PATCH 0978/1795] dt-bindings: arm: Document R-Car M3-N SoC DT
+ bindings
+
+Add device tree bindings documentation for Renesas R-Car M3-N (r8a77965)
+SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c0b11cc56c11df42616d9df45da7a140a2162d08)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 98916b3864c2..63edc11e83ef 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -39,6 +39,8 @@ SoCs:
+     compatible = "renesas,r8a7795"
+   - R-Car M3-W (R8A77960)
+     compatible = "renesas,r8a7796"
++  - R-Car M3-N (R8A77965)
++    compatible = "renesas,r8a77965"
+   - R-Car V3M (R8A77970)
+     compatible = "renesas,r8a77970"
+   - R-Car V3H (R8A77980)
+-- 
+2.19.0
+
diff --git a/patches/0979-arm64-defconfig-Enable-PWM-and-USB-for-R-Car.patch b/patches/0979-arm64-defconfig-Enable-PWM-and-USB-for-R-Car.patch
new file mode 100644
index 00000000000000..2d55a8cb669e33
--- /dev/null
+++ b/patches/0979-arm64-defconfig-Enable-PWM-and-USB-for-R-Car.patch
@@ -0,0 +1,54 @@
+From 2c8a943435bf631d41b08e69888d6d1e84569bc6 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 21 Feb 2018 14:57:16 +0900
+Subject: [PATCH 0979/1795] arm64: defconfig: Enable PWM and USB for R-Car
+
+Enables PWM controller, USB-DMAC that is used by HS-USB, USB 3.0
+peripheral controller and USB 3.0 PHY for R-Car SoCs.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5cb300ce806bfe3273bb94d373d43ca35c33ffdf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index b2a025b46937..1f92fb3e59ae 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -447,6 +447,7 @@ CONFIG_NOP_USB_XCEIV=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_RENESAS_USBHS_UDC=m
++CONFIG_USB_RENESAS_USB3=m
+ CONFIG_USB_ULPI_BUS=y
+ CONFIG_MMC=y
+ CONFIG_MMC_BLOCK_MINORS=32
+@@ -503,6 +504,7 @@ CONFIG_QCOM_BAM_DMA=y
+ CONFIG_QCOM_HIDMA_MGMT=y
+ CONFIG_QCOM_HIDMA=y
+ CONFIG_RCAR_DMAC=y
++CONFIG_RENESAS_USB_DMAC=m
+ CONFIG_VFIO=y
+ CONFIG_VFIO_PCI=y
+ CONFIG_VIRTIO_PCI=y
+@@ -550,10 +552,12 @@ CONFIG_PWM=y
+ CONFIG_PWM_BCM2835=m
+ CONFIG_PWM_CROS_EC=m
+ CONFIG_PWM_MESON=m
++CONFIG_PWM_RCAR=m
+ CONFIG_PWM_ROCKCHIP=y
+ CONFIG_PWM_SAMSUNG=y
+ CONFIG_PWM_TEGRA=m
+ CONFIG_PHY_RCAR_GEN3_USB2=y
++CONFIG_PHY_RCAR_GEN3_USB3=m
+ CONFIG_PHY_HI6220_USB=y
+ CONFIG_PHY_QCOM_USB_HS=y
+ CONFIG_PHY_SUN4I_USB=y
+-- 
+2.19.0
+
diff --git a/patches/0980-arm64-dts-renesas-r8a77980-add-H-SCIF-support.patch b/patches/0980-arm64-dts-renesas-r8a77980-add-H-SCIF-support.patch
new file mode 100644
index 00000000000000..f03865c9df28c0
--- /dev/null
+++ b/patches/0980-arm64-dts-renesas-r8a77980-add-H-SCIF-support.patch
@@ -0,0 +1,192 @@
+From dc1a0f258a8d0fb18500483169f757f7cb23ee87 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 21:30:23 +0300
+Subject: [PATCH 0980/1795] arm64: dts: renesas: r8a77980: add [H]SCIF support
+
+Describe [H]SCIF ports in the R8A77980 device tree.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3601d98ceab56e3d04c9c5e029903bee0337cb94)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 151 ++++++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index e5c7cf391334..eaa546f0a91f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -56,6 +56,13 @@
+ 		method = "smc";
+ 	};
+ 
++	/* External SCIF clock - to be overridden by boards that provide it */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -85,6 +92,150 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		hscif0: serial@e6540000 {
++			compatible = "renesas,hscif-r8a77980",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6540000 0 0x60>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 520>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
++			       <&dmac2 0x31>, <&dmac2 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 520>;
++			status = "disabled";
++		};
++
++		hscif1: serial@e6550000 {
++			compatible = "renesas,hscif-r8a77980",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6550000 0 0x60>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 519>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
++			       <&dmac2 0x33>, <&dmac2 0x32>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 519>;
++			status = "disabled";
++		};
++
++		hscif2: serial@e6560000 {
++			compatible = "renesas,hscif-r8a77980",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6560000 0 0x60>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 518>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
++			       <&dmac2 0x35>, <&dmac2 0x34>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 518>;
++			status = "disabled";
++		};
++
++		hscif3: serial@e66a0000 {
++			compatible = "renesas,hscif-r8a77980",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe66a0000 0 0x60>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 517>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
++			       <&dmac2 0x37>, <&dmac2 0x36>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 517>;
++			status = "disabled";
++		};
++
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a77980",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e60000 0 0x40>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a77980",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e68000 0 0x40>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
++
++		scif3: serial@e6c50000 {
++			compatible = "renesas,scif-r8a77980",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6c50000 0 0x40>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
++			       <&dmac2 0x57>, <&dmac2 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
++
++		scif4: serial@e6c40000 {
++			compatible = "renesas,scif-r8a77980",
++				     "renesas,rcar-gen3-scif",
++				     "renesas,scif";
++			reg = <0 0xe6c40000 0 0x40>;
++			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>,
++				 <&cpg CPG_CORE 19>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
++			       <&dmac2 0x59>, <&dmac2 0x58>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
++
+ 		dmac1: dma-controller@e7300000 {
+ 			compatible = "renesas,dmac-r8a77980",
+ 				     "renesas,rcar-dmac";
+-- 
+2.19.0
+
diff --git a/patches/0981-arm64-dts-renesas-r8a77980-add-EtherAVB-support.patch b/patches/0981-arm64-dts-renesas-r8a77980-add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..fcfbd480a05198
--- /dev/null
+++ b/patches/0981-arm64-dts-renesas-r8a77980-add-EtherAVB-support.patch
@@ -0,0 +1,78 @@
+From 6fdd87cc548ccb839af0e20d2d24e444c49cd37c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 21:32:54 +0300
+Subject: [PATCH 0981/1795] arm64: dts: renesas: r8a77980: add EtherAVB support
+
+Define the generic R8A77980 part of the EtherAVB device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bf6f90832f81710ee944dce05ecbef04d1943664)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 44 +++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index eaa546f0a91f..03845fd74996 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -164,6 +164,50 @@
+ 			status = "disabled";
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77980",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 		scif0: serial@e6e60000 {
+ 			compatible = "renesas,scif-r8a77980",
+ 				     "renesas,rcar-gen3-scif",
+-- 
+2.19.0
+
diff --git a/patches/0982-arm64-dts-renesas-initial-Condor-board-device-tree.patch b/patches/0982-arm64-dts-renesas-initial-Condor-board-device-tree.patch
new file mode 100644
index 00000000000000..58010e304346be
--- /dev/null
+++ b/patches/0982-arm64-dts-renesas-initial-Condor-board-device-tree.patch
@@ -0,0 +1,93 @@
+From 28f911e26de68b661dcc86613ae36a823bacbbc7 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 21:35:22 +0300
+Subject: [PATCH 0982/1795] arm64: dts: renesas: initial Condor board device
+ tree
+
+Add the initial device  tree for  the R8A77980 SoC based Condor board.
+The board has 1 debug serial port (SCIF0); include support for it, so
+that the serial console can work.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: correct memory size to 0x78000000 (2GiB)]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit b9edbce9155c718a1eeed535e88f88d4b6ef7783)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../boot/dts/renesas/r8a77980-condor.dts      | 45 +++++++++++++++++++
+ 2 files changed, 46 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index c8da452fbc9c..65f375f3d7cd 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
++dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+ always		:= $(dtb-y)
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+new file mode 100644
+index 000000000000..daf2957d3504
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -0,0 +1,45 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the Condor board
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++
++/dts-v1/;
++#include "r8a77980.dtsi"
++
++/ {
++	model = "Renesas Condor board based on r8a77980";
++	compatible = "renesas,condor", "renesas,r8a77980";
++
++	aliases {
++		serial0 = &scif0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0 0x48000000 0 0x78000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <16666666>;
++};
++
++&extalr_clk {
++	clock-frequency = <32768>;
++};
++
++&scif0 {
++	status = "okay";
++};
++
++&scif_clk {
++	clock-frequency = <14745600>;
++};
+-- 
+2.19.0
+
diff --git a/patches/0983-arm64-dts-renesas-condor-add-EtherAVB-support.patch b/patches/0983-arm64-dts-renesas-condor-add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..8305c0cdd2a665
--- /dev/null
+++ b/patches/0983-arm64-dts-renesas-condor-add-EtherAVB-support.patch
@@ -0,0 +1,53 @@
+From 841266a0caf412783341e5f37070dbfa15a072e3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 21:38:31 +0300
+Subject: [PATCH 0983/1795] arm64: dts: renesas: condor: add EtherAVB support
+
+Define the Condor board dependent part of the EtherAVB device node.
+
+Based  on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8091788f3d3856a0b6eabebf4e34cfecb38cfe96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+index daf2957d3504..06cf6845765a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -15,6 +15,7 @@
+ 
+ 	aliases {
+ 		serial0 = &scif0;
++		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+@@ -28,6 +29,18 @@
+ 	};
+ };
+ 
++&avb {
++	phy-mode = "rgmii-id";
++	phy-handle = <&phy0>;
++	renesas,no-ether-link;
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/0984-arm64-defconfig-enable-R8A77965-SoC.patch b/patches/0984-arm64-defconfig-enable-R8A77965-SoC.patch
new file mode 100644
index 00000000000000..e6652746e36faf
--- /dev/null
+++ b/patches/0984-arm64-defconfig-enable-R8A77965-SoC.patch
@@ -0,0 +1,31 @@
+From 5b28ed3fa198a5893b797186156e7062f73bbfb4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 23 Feb 2018 09:51:15 +0100
+Subject: [PATCH 0984/1795] arm64: defconfig: enable R8A77965 SoC
+
+Enable the Renesas R-Car M3-N (R8A77965) SoC in the ARM64 defconfig.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f3768b0bc2e924477b6ca20c2293e8d51d948431)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 1f92fb3e59ae..809a05f184fe 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y
+ CONFIG_ARCH_RENESAS=y
+ CONFIG_ARCH_R8A7795=y
+ CONFIG_ARCH_R8A7796=y
++CONFIG_ARCH_R8A77965=y
+ CONFIG_ARCH_R8A77970=y
+ CONFIG_ARCH_R8A77980=y
+ CONFIG_ARCH_R8A77995=y
+-- 
+2.19.0
+
diff --git a/patches/0985-dt-bindings-arm-Document-SoC-compatible-value-for-Ar.patch b/patches/0985-dt-bindings-arm-Document-SoC-compatible-value-for-Ar.patch
new file mode 100644
index 00000000000000..1737fc2b0f5e71
--- /dev/null
+++ b/patches/0985-dt-bindings-arm-Document-SoC-compatible-value-for-Ar.patch
@@ -0,0 +1,36 @@
+From 97b24b9a9568c186b63db7290574600a16736f2a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 19:03:42 +0100
+Subject: [PATCH 0985/1795] dt-bindings: arm: Document SoC compatible value for
+ Armadillo-800 EVA
+
+The compatible property of the root node in a DTS for Atmark Techno
+Armadillo-800 EVA should include the compatible value for the R-Mobile
+A1 SoC, too.
+
+Fixes: d2c2a0776899ba2d ("ARM: shmobile: Add platform device tree bindings documentation")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4a4b0f176b848e5050d75cacbdcf9aa86bef7848)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 63edc11e83ef..a99359e63b0a 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -56,7 +56,7 @@ Boards:
+   - APE6-EVM
+     compatible = "renesas,ape6evm", "renesas,r8a73a4"
+   - Atmark Techno Armadillo-800 EVA
+-    compatible = "renesas,armadillo800eva"
++    compatible = "renesas,armadillo800eva", "renesas,r8a7740"
+   - Blanche (RTP0RC7792SEB00010S)
+     compatible = "renesas,blanche", "renesas,r8a7792"
+   - BOCK-W
+-- 
+2.19.0
+
diff --git a/patches/0986-dt-bindings-arm-Document-Renesas-V3MSK-and-Wheat-boa.patch b/patches/0986-dt-bindings-arm-Document-Renesas-V3MSK-and-Wheat-boa.patch
new file mode 100644
index 00000000000000..2acc57558f5066
--- /dev/null
+++ b/patches/0986-dt-bindings-arm-Document-Renesas-V3MSK-and-Wheat-boa.patch
@@ -0,0 +1,39 @@
+From 3bcc88824de7948cc8203f127adf6bfee28261cf Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 19:03:43 +0100
+Subject: [PATCH 0986/1795] dt-bindings: arm: Document Renesas V3MSK and Wheat
+ board part numbers
+
+The DT binding documentation for the Renesas V3MSK and Wheat boards
+lacked board part numbers.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: corrected Wheat part number]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 04db44132bc544e12f8c7693db35a080edded6ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index a99359e63b0a..66edc1406bb8 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -120,9 +120,9 @@ Boards:
+     compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
+   - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+     compatible = "renesas,stout", "renesas,r8a7790"
+-  - V3MSK
++  - V3MSK (Y-ASK-RCAR-V3M-WS10)
+     compatible = "renesas,v3msk", "renesas,r8a77970"
+-  - Wheat
++  - Wheat (RTP0RC7792ASKB0000JE)
+     compatible = "renesas,wheat", "renesas,r8a7792"
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/0987-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch b/patches/0987-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
new file mode 100644
index 00000000000000..6a5f6d11972b7e
--- /dev/null
+++ b/patches/0987-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
@@ -0,0 +1,37 @@
+From 64151d899d5ed6a05d64bf49f1c68b88a71783c1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 19:03:45 +0100
+Subject: [PATCH 0987/1795] dt-bindings: arm: Document Renesas R-Car M3-N-based
+ Salvator-XS board
+
+The Renesas Salvator-XS development board can be equipped with an R-Car
+H3, M3-W, or M3-N SiP, which are pin-compatible.
+
+Document board part number and compatible values for the version with
+R-Car M3-N.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b604e4a008fe3e5956c5a07139a8168cbe22f46a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 66edc1406bb8..02c77e58301b 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -112,6 +112,8 @@ Boards:
+     compatible = "renesas,salvator-xs", "renesas,r8a7795"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
+     compatible = "renesas,salvator-xs", "renesas,r8a7796"
++  - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
++    compatible = "renesas,salvator-xs", "renesas,r8a77965"
+   - SILK (RTP0RC7794LCB00011S)
+     compatible = "renesas,silk", "renesas,r8a7794"
+   - SK-RZG1E (YR8A77450S000BE)
+-- 
+2.19.0
+
diff --git a/patches/0988-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch b/patches/0988-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
new file mode 100644
index 00000000000000..272959f9dd52e8
--- /dev/null
+++ b/patches/0988-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
@@ -0,0 +1,40 @@
+From 2a079199c7b67b4d57d4f927659a095c8f27e111 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 19:03:44 +0100
+Subject: [PATCH 0988/1795] dt-bindings: arm: Document Renesas R-Car M3-N-based
+ Salvator-X board
+
+The Renesas Salvator-X development board can be equipped with an R-Car
+H3, M3-W, or M3-N SiP, which are pin-compatible.
+
+Document board part number and compatible values for the version with
+R-Car M3-N.
+
+The board part number was extracted from a big patch by Takeshi Kihara
+in the BSP.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 09bea76aad76058d7d1dae8f5804751a017967c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 02c77e58301b..d3d1df97834f 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -108,6 +108,8 @@ Boards:
+     compatible = "renesas,salvator-x", "renesas,r8a7795"
+   - Salvator-X (RTP0RC7796SIPB0011S)
+     compatible = "renesas,salvator-x", "renesas,r8a7796"
++  - Salvator-X (RTP0RC7796SIPB0011S (M3N))
++    compatible = "renesas,salvator-x", "renesas,r8a77965"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+     compatible = "renesas,salvator-xs", "renesas,r8a7795"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
+-- 
+2.19.0
+
diff --git a/patches/0989-arm64-defconfig-enable-IOSCHED_DEADLINE.patch b/patches/0989-arm64-defconfig-enable-IOSCHED_DEADLINE.patch
new file mode 100644
index 00000000000000..bf9e0be8513c1f
--- /dev/null
+++ b/patches/0989-arm64-defconfig-enable-IOSCHED_DEADLINE.patch
@@ -0,0 +1,36 @@
+From 0364c8c0cbfd267fe8267fcf36521910893e273d Mon Sep 17 00:00:00 2001
+From: John Garry <john.garry@huawei.com>
+Date: Tue, 30 Jan 2018 21:22:57 +0800
+Subject: [PATCH 0989/1795] arm64: defconfig: enable IOSCHED_DEADLINE
+
+For certain workloads the deadline IO scheduler offers
+particular advantages over other schedulers and has shown
+to perform better, so enable it.
+
+The default IO scheduler is unaffected by this change, and
+currently is CFQ.
+
+Signed-off-by: John Garry <john.garry@huawei.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+(cherry picked from commit 5fc990703e8663b00741f6f86990d33093510302)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 809a05f184fe..3f6606291cf5 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -31,7 +31,6 @@ CONFIG_PROFILING=y
+ CONFIG_JUMP_LABEL=y
+ CONFIG_MODULES=y
+ CONFIG_MODULE_UNLOAD=y
+-# CONFIG_IOSCHED_DEADLINE is not set
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_ARCH_ALPINE=y
+ CONFIG_ARCH_BCM2835=y
+-- 
+2.19.0
+
diff --git a/patches/0990-arm64-defconfig-add-newly-added-accelerated-crypto-m.patch b/patches/0990-arm64-defconfig-add-newly-added-accelerated-crypto-m.patch
new file mode 100644
index 00000000000000..41894ff23251dd
--- /dev/null
+++ b/patches/0990-arm64-defconfig-add-newly-added-accelerated-crypto-m.patch
@@ -0,0 +1,33 @@
+From b66f3261daa6eaf5e1a2a737bbebe28256ea8f00 Mon Sep 17 00:00:00 2001
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Date: Wed, 14 Feb 2018 09:26:36 +0000
+Subject: [PATCH 0990/1795] arm64: defconfig: add newly added accelerated
+ crypto modules
+
+New crypto drivers have been introduced in v4.16 that implement the
+SHA-512, SHA3 and SM3 secure hash algorithms using ARMv8.2 optional
+instructions. Add these drivers to arm64's defconfig as modules.
+
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit b1bdf5084e88acdab7f9f8084e308f7cd8eed3a0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 3f6606291cf5..2c2e7631832d 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -637,3 +637,6 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+ CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
+ CONFIG_CRYPTO_CHACHA20_NEON=m
+ CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
+-- 
+2.19.0
+
diff --git a/patches/0991-arm64-defconfig-add-support-for-Socionext-SynQuacer-.patch b/patches/0991-arm64-defconfig-add-support-for-Socionext-SynQuacer-.patch
new file mode 100644
index 00000000000000..c41e4b8ce2ec58
--- /dev/null
+++ b/patches/0991-arm64-defconfig-add-support-for-Socionext-SynQuacer-.patch
@@ -0,0 +1,58 @@
+From a4c3c5fe22504a621bde7a809149290b3009448f Mon Sep 17 00:00:00 2001
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Date: Wed, 14 Feb 2018 09:26:37 +0000
+Subject: [PATCH 0991/1795] arm64: defconfig: add support for Socionext
+ SynQuacer based platforms
+
+Enable support in arm64's defconfig for Socionext SynQuacer based
+platforms, by enabling the arch Kconfig symbol, and enabling builtin
+support for the ethernet, GPIO and SDHCI controllers
+
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 30314c33a52fa675bd3404772fd2aa03fe7b39f2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 2c2e7631832d..5de829bb9b70 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -57,6 +57,7 @@ CONFIG_ARCH_R8A77995=y
+ CONFIG_ARCH_STRATIX10=y
+ CONFIG_ARCH_TEGRA=y
+ CONFIG_ARCH_SPRD=y
++CONFIG_ARCH_SYNQUACER=y
+ CONFIG_ARCH_THUNDER=y
+ CONFIG_ARCH_THUNDER2=y
+ CONFIG_ARCH_UNIPHIER=y
+@@ -210,6 +211,7 @@ CONFIG_QCOM_EMAC=m
+ CONFIG_RAVB=y
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
++CONFIG_SNI_NETSEC=y
+ CONFIG_STMMAC_ETH=m
+ CONFIG_MDIO_BUS_MUX_MMIOREG=y
+ CONFIG_AT803X_PHY=m
+@@ -306,6 +308,7 @@ CONFIG_PINCTRL_MSM8996=y
+ CONFIG_PINCTRL_QDF2XXX=y
+ CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+ CONFIG_GPIO_DWAPB=y
++CONFIG_GPIO_MB86S7X=y
+ CONFIG_GPIO_PL061=y
+ CONFIG_GPIO_RCAR=y
+ CONFIG_GPIO_UNIPHIER=y
+@@ -454,6 +457,7 @@ CONFIG_MMC_BLOCK_MINORS=32
+ CONFIG_MMC_ARMMMCI=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ACPI=y
++CONFIG_MMC_SDHCI_F_SDH30=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+ CONFIG_MMC_SDHCI_OF_ARASAN=y
+ CONFIG_MMC_SDHCI_OF_ESDHC=y
+-- 
+2.19.0
+
diff --git a/patches/0992-arm64-defconfig-Enable-NVIDIA-Tegra194-support.patch b/patches/0992-arm64-defconfig-Enable-NVIDIA-Tegra194-support.patch
new file mode 100644
index 00000000000000..89a804fb7e0c17
--- /dev/null
+++ b/patches/0992-arm64-defconfig-Enable-NVIDIA-Tegra194-support.patch
@@ -0,0 +1,31 @@
+From 71055468be1d31fb73f0da324cb9ec49e5f34926 Mon Sep 17 00:00:00 2001
+From: Mikko Perttunen <mperttunen@nvidia.com>
+Date: Tue, 20 Feb 2018 13:58:07 +0200
+Subject: [PATCH 0992/1795] arm64: defconfig: Enable NVIDIA Tegra194 support
+
+Enable NVIDIA Tegra194 support in the default 64-bit ARM configuration.
+
+Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+(cherry picked from commit 7f6487500326d323ea6e09464069a14a83e612f2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 5de829bb9b70..271f911d0e32 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -548,6 +548,7 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y
+ CONFIG_ARCH_TEGRA_132_SOC=y
+ CONFIG_ARCH_TEGRA_210_SOC=y
+ CONFIG_ARCH_TEGRA_186_SOC=y
++CONFIG_ARCH_TEGRA_194_SOC=y
+ CONFIG_EXTCON_USB_GPIO=y
+ CONFIG_IIO=y
+ CONFIG_EXYNOS_ADC=y
+-- 
+2.19.0
+
diff --git a/patches/0993-arm64-defconfig-Enable-the-APCS-IPC-driver-on-Qualco.patch b/patches/0993-arm64-defconfig-Enable-the-APCS-IPC-driver-on-Qualco.patch
new file mode 100644
index 00000000000000..e57b7e943e8710
--- /dev/null
+++ b/patches/0993-arm64-defconfig-Enable-the-APCS-IPC-driver-on-Qualco.patch
@@ -0,0 +1,36 @@
+From 1ad7821699e142595b6b4687d7119564a15df396 Mon Sep 17 00:00:00 2001
+From: Amit Kucheria <amit.kucheria@linaro.org>
+Date: Mon, 12 Feb 2018 16:33:32 +0530
+Subject: [PATCH 0993/1795] arm64: defconfig: Enable the APCS IPC driver on
+ Qualcomm platforms
+
+The APCS block is present on several Qualcomm SoCs e.g. 8916, 8996.  On the
+8916 it is needed to enable the clock controller that in turn enables
+cpufreq on the platform while on the 8996 it is needed for communication
+with RPM.
+
+Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit b01aadecd5eb14a1e383d7cda8271b2f0e94a935)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 271f911d0e32..ceafe8529a19 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -534,6 +534,7 @@ CONFIG_ARM_MHU=y
+ CONFIG_PLATFORM_MHU=y
+ CONFIG_BCM2835_MBOX=y
+ CONFIG_HI6220_MBOX=y
++CONFIG_QCOM_APCS_IPC=y
+ CONFIG_ROCKCHIP_IOMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
+-- 
+2.19.0
+
diff --git a/patches/0994-arm64-defconfig-enable-thermal-sensor-on-QCOM-platfo.patch b/patches/0994-arm64-defconfig-enable-thermal-sensor-on-QCOM-platfo.patch
new file mode 100644
index 00000000000000..819b4036c05732
--- /dev/null
+++ b/patches/0994-arm64-defconfig-enable-thermal-sensor-on-QCOM-platfo.patch
@@ -0,0 +1,44 @@
+From c9e239d072d4528b50bd27d72daf164402a29f86 Mon Sep 17 00:00:00 2001
+From: Amit Kucheria <amit.kucheria@linaro.org>
+Date: Tue, 6 Mar 2018 18:35:02 +0530
+Subject: [PATCH 0994/1795] arm64: defconfig: enable thermal sensor on QCOM
+ platforms
+
+Enable the driver for the TSENS IP that is present across several QCOM
+SoCs.
+
+Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit 52fe48c2b9bbeec6402a119f6b6be2050f5b999c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	arch/arm64/configs/defconfig
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index ceafe8529a19..54fb4bfb96d0 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -333,6 +333,7 @@ CONFIG_THERMAL_EMULATION=y
+ CONFIG_BRCMSTB_THERMAL=m
+ CONFIG_EXYNOS_THERMAL=y
+ CONFIG_RCAR_GEN3_THERMAL=y
++CONFIG_QCOM_TSENS=y
+ CONFIG_ROCKCHIP_THERMAL=m
+ CONFIG_WATCHDOG=y
+ CONFIG_S3C2410_WATCHDOG=y
+@@ -575,6 +576,7 @@ CONFIG_PHY_XGENE=y
+ CONFIG_PHY_TEGRA_XUSB=y
+ CONFIG_QCOM_L2_PMU=y
+ CONFIG_QCOM_L3_PMU=y
++CONFIG_QCOM_QFPROM=y
+ CONFIG_MESON_EFUSE=m
+ CONFIG_UNIPHIER_EFUSE=y
+ CONFIG_TEE=y
+-- 
+2.19.0
+
diff --git a/patches/0995-arm64-defconfig-enable-more-cpufreq-governors.patch b/patches/0995-arm64-defconfig-enable-more-cpufreq-governors.patch
new file mode 100644
index 00000000000000..c40bd77f3d907e
--- /dev/null
+++ b/patches/0995-arm64-defconfig-enable-more-cpufreq-governors.patch
@@ -0,0 +1,39 @@
+From 1a5706b2793bc7e3cd182cb3ea0450cd69963302 Mon Sep 17 00:00:00 2001
+From: Amit Kucheria <amit.kucheria@linaro.org>
+Date: Tue, 6 Mar 2018 18:35:03 +0530
+Subject: [PATCH 0995/1795] arm64: defconfig: enable more cpufreq governors
+
+Enable the various CPUFREQ governors and statistics to ease development.
+Don't change the default governor - performance governor.
+
+Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+(cherry picked from commit c1da37a3177366d565d16e03b89cf81d817c4689)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 54fb4bfb96d0..df40349ba9c5 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -101,6 +101,14 @@ CONFIG_HIBERNATION=y
+ CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+ CONFIG_ARM_CPUIDLE=y
+ CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ATTR_SET=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=m
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+ CONFIG_CPUFREQ_DT=y
+ CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+ CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+-- 
+2.19.0
+
diff --git a/patches/0996-arm64-defconfig-Enable-CONFIG_ARM_TEGRA186_CPUFREQ.patch b/patches/0996-arm64-defconfig-Enable-CONFIG_ARM_TEGRA186_CPUFREQ.patch
new file mode 100644
index 00000000000000..ddd8d9665091f0
--- /dev/null
+++ b/patches/0996-arm64-defconfig-Enable-CONFIG_ARM_TEGRA186_CPUFREQ.patch
@@ -0,0 +1,32 @@
+From c4c44275914a6a1645381c960a01f73d3e6ad0e4 Mon Sep 17 00:00:00 2001
+From: Mikko Perttunen <mperttunen@nvidia.com>
+Date: Thu, 16 Nov 2017 13:46:51 +0200
+Subject: [PATCH 0996/1795] arm64: defconfig: Enable
+ CONFIG_ARM_TEGRA186_CPUFREQ
+
+Enable Tegra186 CPU frequency scaling support by default.
+
+Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+(cherry picked from commit 317ccc727b06b6459fe0dd32b95b5e8c898402f6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index df40349ba9c5..f7cd5fe5787b 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -113,6 +113,7 @@ CONFIG_CPUFREQ_DT=y
+ CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+ CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+ CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_TEGRA186_CPUFREQ=y
+ CONFIG_ACPI_CPPC_CPUFREQ=m
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+-- 
+2.19.0
+
diff --git a/patches/0997-arm64-defconfig-Enable-CONFIG_TEGRA_BPMP_THERMAL.patch b/patches/0997-arm64-defconfig-Enable-CONFIG_TEGRA_BPMP_THERMAL.patch
new file mode 100644
index 00000000000000..e34093d1bd05a2
--- /dev/null
+++ b/patches/0997-arm64-defconfig-Enable-CONFIG_TEGRA_BPMP_THERMAL.patch
@@ -0,0 +1,31 @@
+From f7ae438ed9dd0a5e1b9308d44ed534bfd070a15c Mon Sep 17 00:00:00 2001
+From: Mikko Perttunen <mperttunen@nvidia.com>
+Date: Thu, 16 Nov 2017 13:46:52 +0200
+Subject: [PATCH 0997/1795] arm64: defconfig: Enable CONFIG_TEGRA_BPMP_THERMAL
+
+Enable Tegra BPMP thermal sensor support by default, built as a module.
+
+Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+(cherry picked from commit 07d2206ed73973916602d2b141629e04e9843c58)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index f7cd5fe5787b..81ddc9491ec8 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -344,6 +344,7 @@ CONFIG_EXYNOS_THERMAL=y
+ CONFIG_RCAR_GEN3_THERMAL=y
+ CONFIG_QCOM_TSENS=y
+ CONFIG_ROCKCHIP_THERMAL=m
++CONFIG_TEGRA_BPMP_THERMAL=m
+ CONFIG_WATCHDOG=y
+ CONFIG_S3C2410_WATCHDOG=y
+ CONFIG_MESON_GXBB_WATCHDOG=m
+-- 
+2.19.0
+
diff --git a/patches/0998-arm64-dts-renesas-r8a7796-Update-OPPs-to-support-CA5.patch b/patches/0998-arm64-dts-renesas-r8a7796-Update-OPPs-to-support-CA5.patch
new file mode 100644
index 00000000000000..50d6a148375f54
--- /dev/null
+++ b/patches/0998-arm64-dts-renesas-r8a7796-Update-OPPs-to-support-CA5.patch
@@ -0,0 +1,55 @@
+From ec5b5ca206badc97132d43e3886cf56a3794c33e Mon Sep 17 00:00:00 2001
+From: Dien Pham <dien.pham.ry@renesas.com>
+Date: Mon, 29 Jan 2018 19:21:20 +0100
+Subject: [PATCH 0998/1795] arm64: dts: renesas: r8a7796: Update OPPs to
+ support CA53 dfs
+
+Describe frequencies, other than the default for CA53 cores.  This is a
+pre-requisite for using providing alternative frequencies for use with
+CPUFreq with these cores.
+
+Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fbdad84cc759abc469e476ee2518d77280e80cd0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 157bd28014ed..076a9c9346ae 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -204,11 +204,27 @@
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
++		opp-800000000 {
++			opp-hz = /bits/ 64 <800000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
+ 		opp-1200000000 {
+ 			opp-hz = /bits/ 64 <1200000000>;
+ 			opp-microvolt = <820000>;
+ 			clock-latency-ns = <300000>;
+ 		};
++		opp-1300000000 {
++			opp-hz = /bits/ 64 <1300000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
+ 	};
+ 
+ 	/* External PCIe clock - can be overridden by the board */
+-- 
+2.19.0
+
diff --git a/patches/0999-arm64-dts-renesas-r8a7795-Update-OPPs-to-support-CA5.patch b/patches/0999-arm64-dts-renesas-r8a7795-Update-OPPs-to-support-CA5.patch
new file mode 100644
index 00000000000000..c8013789dbc599
--- /dev/null
+++ b/patches/0999-arm64-dts-renesas-r8a7795-Update-OPPs-to-support-CA5.patch
@@ -0,0 +1,44 @@
+From 706eda42aa6fd5888f098df957f1adf59199c422 Mon Sep 17 00:00:00 2001
+From: Dien Pham <dien.pham.ry@renesas.com>
+Date: Mon, 29 Jan 2018 19:21:21 +0100
+Subject: [PATCH 0999/1795] arm64: dts: renesas: r8a7795: Update OPPs to
+ support CA53 dfs
+
+Describe frequencies, other than the default for CA53 cores.  This is a
+pre-requisite for using providing alternative frequencies for use with
+CPUFreq with these cores.
+
+Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 85618efe149082b50f846834356b3bc23c4d1141)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 9dc2b43e59f5..6d53e1cb7b29 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -223,6 +223,16 @@
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
++		opp-800000000 {
++			opp-hz = /bits/ 64 <800000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
+ 		opp-1200000000 {
+ 			opp-hz = /bits/ 64 <1200000000>;
+ 			opp-microvolt = <820000>;
+-- 
+2.19.0
+
diff --git a/patches/1000-arm64-dts-renesas-initial-R8A77965-SoC-device-tree.patch b/patches/1000-arm64-dts-renesas-initial-R8A77965-SoC-device-tree.patch
new file mode 100644
index 00000000000000..d40d4a3e9a8b23
--- /dev/null
+++ b/patches/1000-arm64-dts-renesas-initial-R8A77965-SoC-device-tree.patch
@@ -0,0 +1,522 @@
+From 2dca68f86f3a9cd73a7bfe36e8c3b7142fe45804 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:10 +0100
+Subject: [PATCH 1000/1795] arm64: dts: renesas: initial R8A77965 SoC device
+ tree
+
+Basic support for the Gen 3 R-Car M3-N SoC.
+
+Based on original work from:
+Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Magnus Damm <damm+renesas@opensource.se>
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit df863d6f95f57dbb4f7c2f5ec2f230809551b17f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 490 ++++++++++++++++++++++
+ 1 file changed, 490 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77965.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+new file mode 100644
+index 000000000000..6b6ec653f543
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -0,0 +1,490 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the r8a77965 SoC
++ *
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ *
++ * Based on r8a7796.dtsi
++ * Copyright (C) 2016 Renesas Electronics Corp.
++ */
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++#define CPG_AUDIO_CLK_I		10
++
++/ {
++	compatible = "renesas,r8a77965";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		a57_0: cpu@0 {
++			compatible = "arm,cortex-a57", "arm,armv8";
++			reg = <0x0>;
++			device_type = "cpu";
++			power-domains = <&sysc 0>;
++			next-level-cache = <&L2_CA57>;
++			enable-method = "psci";
++		};
++
++		a57_1: cpu@1 {
++			compatible = "arm,cortex-a57","arm,armv8";
++			reg = <0x1>;
++			device_type = "cpu";
++			power-domains = <&sysc 1>;
++			next-level-cache = <&L2_CA57>;
++			enable-method = "psci";
++		};
++
++		L2_CA57: cache-controller-0 {
++			compatible = "cache";
++			reg = <0>;
++			power-domains = <&sysc 12>;
++			cache-unified;
++			cache-level = <2>;
++		};
++	};
++
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	extalr_clk: extalr {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock - to be overridden by boards that provide it */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External USB clocks - can be overridden by the board */
++	usb3s0_clk: usb3s0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>,
++				     <&a57_1>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
++		};
++
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77965";
++			reg = <0 0xe6060000 0 0x50c>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77965-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77965-rst";
++			reg = <0 0xe6160000 0 0x0200>;
++		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77965-sysc";
++			reg = <0 0xe6180000 0 0x0400>;
++			#power-domain-cells = <1>;
++		};
++
++		gpio0: gpio@e6050000 {
++			/* placeholder */
++		};
++
++		gpio1: gpio@e6051000 {
++			/* placeholder */
++		};
++
++		gpio2: gpio@e6052000 {
++			/* placeholder */
++		};
++
++		gpio3: gpio@e6053000 {
++			/* placeholder */
++		};
++
++		gpio4: gpio@e6054000 {
++			/* placeholder */
++		};
++
++		gpio5: gpio@e6055000 {
++			/* placeholder */
++		};
++
++		gpio6: gpio@e6055400 {
++			/* placeholder */
++		};
++
++		gpio7: gpio@e6055800 {
++			/* placeholder */
++		};
++
++		intc_ex: interrupt-controller@e61c0000 {
++			/* placeholder */
++		};
++
++		dmac0: dma-controller@e6700000 {
++			/* placeholder */
++		};
++
++		dmac1: dma-controller@e7300000 {
++			/* placeholder */
++		};
++
++		dmac2: dma-controller@e7310000 {
++			/* placeholder */
++		};
++
++		scif0: serial@e6e60000 {
++			/* placeholder */
++		};
++
++		scif1: serial@e6e68000 {
++			/* placeholder */
++		};
++
++		scif2: serial@e6e88000 {
++			/* placeholder */
++		};
++
++		scif3: serial@e6c50000 {
++			/* placeholder */
++		};
++
++		scif4: serial@e6c40000 {
++			/* placeholder */
++		};
++
++		scif5: serial@e6f30000 {
++			/* placeholder */
++		};
++
++		avb: ethernet@e6800000 {
++			/* placeholder */
++		};
++
++		csi20: csi2@fea80000 {
++			/* placeholder */
++		};
++
++		csi40: csi2@feaa0000 {
++			/* placeholder */
++		};
++
++		vin0: video@e6ef0000 {
++			/* placeholder */
++		};
++
++		vin1: video@e6ef1000 {
++			/* placeholder */
++		};
++
++		vin2: video@e6ef2000 {
++			/* placeholder */
++		};
++
++		vin3: video@e6ef3000 {
++			/* placeholder */
++		};
++
++		vin4: video@e6ef4000 {
++			/* placeholder */
++		};
++
++		vin5: video@e6ef5000 {
++			/* placeholder */
++		};
++
++		vin6: video@e6ef6000 {
++			/* placeholder */
++		};
++
++		vin7: video@e6ef7000 {
++			/* placeholder */
++		};
++
++		ohci0: usb@ee080000 {
++			/* placeholder */
++		};
++
++		ehci0: usb@ee080100 {
++			/* placeholder */
++		};
++
++		usb2_phy0: usb-phy@ee080200 {
++			/* placeholder */
++		};
++
++		ohci1: usb@ee0a0000 {
++			/* placeholder */
++		};
++
++		ehci1: usb@ee0a0100 {
++			/* placeholder */
++		};
++
++		i2c0: i2c@e6500000 {
++			/* placeholder */
++		};
++
++		i2c1: i2c@e6508000 {
++			/* placeholder */
++		};
++
++		i2c2: i2c@e6510000 {
++			/* placeholder */
++		};
++
++		i2c3: i2c@e66d0000 {
++			/* placeholder */
++		};
++
++		i2c4: i2c@e66d8000 {
++			/* placeholder */
++		};
++
++		i2c5: i2c@e66e0000 {
++			/* placeholder */
++		};
++
++		i2c6: i2c@e66e8000 {
++			/* placeholder */
++		};
++
++		i2c_dvfs: i2c@e60b0000 {
++			/* placeholder */
++		};
++
++		pwm0: pwm@e6e30000 {
++			/* placeholder */
++		};
++
++		pwm1: pwm@e6e31000 {
++			/* placeholder */
++		};
++
++		pwm2: pwm@e6e32000 {
++			/* placeholder */
++		};
++
++		pwm3: pwm@e6e33000 {
++			/* placeholder */
++		};
++
++		pwm4: pwm@e6e34000 {
++			/* placeholder */
++		};
++
++		pwm5: pwm@e6e35000 {
++			/* placeholder */
++		};
++
++		pwm6: pwm@e6e36000 {
++			/* placeholder */
++		};
++
++		du: display@feb00000 {
++			/* placeholder */
++
++			ports {
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_hdmi0: endpoint {
++					};
++				};
++				port@2 {
++					reg = <2>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
++
++		hsusb: usb@e6590000 {
++			/* placeholder */
++		};
++
++		pciec0: pcie@fe000000 {
++			/* placeholder */
++		};
++
++		pciec1: pcie@ee800000 {
++			/* placeholder */
++		};
++
++		rcar_sound: sound@ec500000 {
++			/* placeholder */
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++				};
++				dvc1: dvc-1 {
++				};
++			};
++
++			rcar_sound,src {
++				src0: src-0 {
++				};
++				src1: src-1 {
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++				};
++				ssi1: ssi-1 {
++				};
++			};
++		};
++
++		usb2_phy1: usb-phy@ee0a0200 {
++			/* placeholder */
++		};
++
++		sdhi0: sd@ee100000 {
++			/* placeholder */
++		};
++
++		sdhi1: sd@ee120000 {
++			/* placeholder */
++		};
++
++		sdhi2: sd@ee140000 {
++			/* placeholder */
++		};
++
++		sdhi3: sd@ee160000 {
++			/* placeholder */
++		};
++
++		usb3_phy0: usb-phy@e65ee000 {
++			/* placeholder */
++		};
++
++		usb3_peri0: usb@ee020000 {
++			/* placeholder */
++		};
++
++		xhci0: usb@ee000000 {
++			/* placeholder */
++		};
++
++		wdt0: watchdog@e6020000 {
++			/* placeholder */
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1001-arm64-dts-renesas-Add-R-Car-Salvator-x-M3-N-support.patch b/patches/1001-arm64-dts-renesas-Add-R-Car-Salvator-x-M3-N-support.patch
new file mode 100644
index 00000000000000..3ba47b1823fae5
--- /dev/null
+++ b/patches/1001-arm64-dts-renesas-Add-R-Car-Salvator-x-M3-N-support.patch
@@ -0,0 +1,66 @@
+From c9bdc46270d9103a11a3344aaa51ce2a688586b3 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:11 +0100
+Subject: [PATCH 1001/1795] arm64: dts: renesas: Add R-Car Salvator-x M3-N
+ support
+
+Add basic support for R-Car Salvator-X M3-N (R8A77965) board.
+
+Based on original work from:
+Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Magnus Damm <damm+renesas@opensource.se>
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5a2cd7e84945bc9acfcada18cb5f66cda9c1529e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../boot/dts/renesas/r8a77965-salvator-x.dts  | 21 +++++++++++++++++++
+ 2 files changed, 22 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 65f375f3d7cd..9dcc26e32891 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
++dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+new file mode 100644
+index 000000000000..75d890d91df9
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the Salvator-X board with R-Car M3-N
++ *
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ */
++
++/dts-v1/;
++#include "r8a77965.dtsi"
++#include "salvator-x.dtsi"
++
++/ {
++	model = "Renesas Salvator-X board based on r8a77965";
++	compatible = "renesas,salvator-x", "renesas,r8a77965";
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x78000000>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1002-arm64-dts-renesas-r8a77965-Add-dmac-device-nods.patch b/patches/1002-arm64-dts-renesas-r8a77965-Add-dmac-device-nods.patch
new file mode 100644
index 00000000000000..d0989a2b8d13b8
--- /dev/null
+++ b/patches/1002-arm64-dts-renesas-r8a77965-Add-dmac-device-nods.patch
@@ -0,0 +1,133 @@
+From 0e480e5dc2f501d31e72016fef84ce084778e165 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:13 +0100
+Subject: [PATCH 1002/1795] arm64: dts: renesas: r8a77965: Add dmac device nods
+
+Add dmac[0-2] device nodes for R-Car M3-N (r8a77965) SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 838c1121ca592bd39e33d5687af3eea9fc9d0700)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 96 ++++++++++++++++++++++-
+ 1 file changed, 93 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 6b6ec653f543..b83dafc5745e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -233,15 +233,105 @@
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+-			/* placeholder */
++			compatible = "renesas,dmac-r8a77965",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x10000>;
++			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
+ 		};
+ 
+ 		dmac1: dma-controller@e7300000 {
+-			/* placeholder */
++			compatible = "renesas,dmac-r8a77965",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
+ 		};
+ 
+ 		dmac2: dma-controller@e7310000 {
+-			/* placeholder */
++			compatible = "renesas,dmac-r8a77965",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 217>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 217>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
+ 		};
+ 
+ 		scif0: serial@e6e60000 {
+-- 
+2.19.0
+
diff --git a/patches/1003-arm64-dts-renesas-r8a77965-Add-SCIF-device-nodes.patch b/patches/1003-arm64-dts-renesas-r8a77965-Add-SCIF-device-nodes.patch
new file mode 100644
index 00000000000000..6b113b94d7dba7
--- /dev/null
+++ b/patches/1003-arm64-dts-renesas-r8a77965-Add-SCIF-device-nodes.patch
@@ -0,0 +1,132 @@
+From 110c8f50122ab477c4838f0c063d7917f3672d78 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:16 +0100
+Subject: [PATCH 1003/1795] arm64: dts: renesas: r8a77965: Add SCIF device
+ nodes
+
+Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0ea5b2fd38db56aad29e4b6a2028fccde438a110)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 85 +++++++++++++++++++++--
+ 1 file changed, 79 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index b83dafc5745e..3cb1a332314e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -335,27 +335,100 @@
+ 		};
+ 
+ 		scif0: serial@e6e60000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 207>;
++			status = "disabled";
+ 		};
+ 
+ 		scif1: serial@e6e68000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 206>;
++			status = "disabled";
+ 		};
+ 
+ 		scif2: serial@e6e88000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e88000 0 64>;
++			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 310>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 310>;
++			status = "disabled";
+ 		};
+ 
+ 		scif3: serial@e6c50000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 204>;
++			status = "disabled";
+ 		};
+ 
+ 		scif4: serial@e6c40000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 203>;
++			status = "disabled";
+ 		};
+ 
+ 		scif5: serial@e6f30000 {
+-			/* placeholder */
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6f30000 0 64>;
++			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
++			       <&dmac2 0x5b>, <&dmac2 0x5a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 202>;
++			status = "disabled";
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+-- 
+2.19.0
+
diff --git a/patches/1004-arm64-dts-renesas-r8a77965-Add-GPIO-nodes.patch b/patches/1004-arm64-dts-renesas-r8a77965-Add-GPIO-nodes.patch
new file mode 100644
index 00000000000000..00b0ce26959a73
--- /dev/null
+++ b/patches/1004-arm64-dts-renesas-r8a77965-Add-GPIO-nodes.patch
@@ -0,0 +1,156 @@
+From 38fd05382c5270f037f04f87cb96c63364681296 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:18 +0100
+Subject: [PATCH 1004/1795] arm64: dts: renesas: r8a77965: Add GPIO nodes
+
+Add GPIO nodes to r8a77965 SoC device tree file.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e34ca96b81a241523f79a244b5551135cf069852)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 104 ++++++++++++++++++++--
+ 1 file changed, 96 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 3cb1a332314e..55f05f79f7f7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -197,35 +197,123 @@
+ 		};
+ 
+ 		gpio0: gpio@e6050000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 16>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 912>;
+ 		};
+ 
+ 		gpio1: gpio@e6051000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 29>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 911>;
+ 		};
+ 
+ 		gpio2: gpio@e6052000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 15>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 910>;
+ 		};
+ 
+ 		gpio3: gpio@e6053000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 16>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 909>;
+ 		};
+ 
+ 		gpio4: gpio@e6054000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 18>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 908>;
+ 		};
+ 
+ 		gpio5: gpio@e6055000 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 907>;
+ 		};
+ 
+ 		gpio6: gpio@e6055400 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 906>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 906>;
+ 		};
+ 
+ 		gpio7: gpio@e6055800 {
+-			/* placeholder */
++			compatible = "renesas,gpio-r8a77965",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055800 0 0x50>;
++			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 224 4>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 905>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 905>;
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
+-- 
+2.19.0
+
diff --git a/patches/1005-arm64-dts-renesas-r8a77965-Add-reg-properties.patch b/patches/1005-arm64-dts-renesas-r8a77965-Add-reg-properties.patch
new file mode 100644
index 00000000000000..3b5d09debb97a6
--- /dev/null
+++ b/patches/1005-arm64-dts-renesas-r8a77965-Add-reg-properties.patch
@@ -0,0 +1,276 @@
+From 3ff50c0e62ed8653620e1290de087ec305280f37 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:53 +0100
+Subject: [PATCH 1005/1795] arm64: dts: renesas: r8a77965: Add "reg" properties
+
+Add "reg" properties to place-holder nodes with unit address defined for
+R-Car M3-N SoC.
+
+This silences the following DTC compiler warning:
+Warning (unit_address_vs_reg): Node /soc/... has a unit name,
+but no reg property
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9e1b00a2ef43049617e1d3e99e258e7b2d9f98ea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 51 +++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 55f05f79f7f7..4286453ba92d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -317,6 +317,7 @@
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
++			reg = <0 0xe61c0000 0 0x200>;
+ 			/* placeholder */
+ 		};
+ 
+@@ -520,130 +521,163 @@
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		csi20: csi2@fea80000 {
++			reg = <0 0xfea80000 0 0x10000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		csi40: csi2@feaa0000 {
++			reg = <0 0xfeaa0000 0 0x10000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin0: video@e6ef0000 {
++			reg = <0 0xe6ef0000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin1: video@e6ef1000 {
++			reg = <0 0xe6ef1000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin2: video@e6ef2000 {
++			reg = <0 0xe6ef2000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin3: video@e6ef3000 {
++			reg = <0 0xe6ef3000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin4: video@e6ef4000 {
++			reg = <0 0xe6ef4000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin5: video@e6ef5000 {
++			reg = <0 0xe6ef5000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin6: video@e6ef6000 {
++			reg = <0 0xe6ef6000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		vin7: video@e6ef7000 {
++			reg = <0 0xe6ef7000 0 0x1000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		ohci0: usb@ee080000 {
++			reg = <0 0xee080000 0 0x100>;
+ 			/* placeholder */
+ 		};
+ 
+ 		ehci0: usb@ee080100 {
++			reg = <0 0xee080100 0 0x100>;
+ 			/* placeholder */
+ 		};
+ 
+ 		usb2_phy0: usb-phy@ee080200 {
++			reg = <0 0xee080200 0 0x700>;
+ 			/* placeholder */
+ 		};
+ 
+ 		ohci1: usb@ee0a0000 {
++			reg = <0 0xee0a0000 0 0x100>;
+ 			/* placeholder */
+ 		};
+ 
+ 		ehci1: usb@ee0a0100 {
++			reg = <0 0xee0a0100 0 0x100>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c0: i2c@e6500000 {
++			reg = <0 0xe6500000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c1: i2c@e6508000 {
++			reg = <0 0xe6508000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c2: i2c@e6510000 {
++			reg = <0 0xe6510000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c3: i2c@e66d0000 {
++			reg = <0 0xe66d0000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c4: i2c@e66d8000 {
++			reg = <0 0xe66d8000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c5: i2c@e66e0000 {
++			reg = <0 0xe66e0000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c6: i2c@e66e8000 {
++			reg = <0 0xe66e8000 0 0x40>;
+ 			/* placeholder */
+ 		};
+ 
+ 		i2c_dvfs: i2c@e60b0000 {
++			reg = <0 0xe60b0000 0 0x425>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm0: pwm@e6e30000 {
++			reg = <0 0xe6e30000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm1: pwm@e6e31000 {
++			reg = <0 0xe6e31000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm2: pwm@e6e32000 {
++			reg = <0 0xe6e32000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm3: pwm@e6e33000 {
++			reg = <0 0xe6e33000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm4: pwm@e6e34000 {
++			reg = <0 0xe6e34000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm5: pwm@e6e35000 {
++			reg = <0 0xe6e35000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pwm6: pwm@e6e36000 {
++			reg = <0 0xe6e36000 0 8>;
+ 			/* placeholder */
+ 		};
+ 
+ 		du: display@feb00000 {
++			reg = <0 0xfeb00000 0 0x80000>,
++			      <0 0xfeb90000 0 0x14>;
+ 			/* placeholder */
+ 
+ 			ports {
+@@ -666,18 +700,26 @@
+ 		};
+ 
+ 		hsusb: usb@e6590000 {
++			reg = <0 0xe6590000 0 0x100>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pciec0: pcie@fe000000 {
++			reg = <0 0xfe000000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		pciec1: pcie@ee800000 {
++			reg = <0 0xee800000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		rcar_sound: sound@ec500000 {
++			reg =	<0 0xec500000 0 0x1000>, /* SCU */
++				<0 0xec5a0000 0 0x100>,  /* ADG */
++				<0 0xec540000 0 0x1000>, /* SSIU */
++				<0 0xec541000 0 0x280>,  /* SSI */
++				<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 			/* placeholder */
+ 
+ 			rcar_sound,dvc {
+@@ -703,38 +745,47 @@
+ 		};
+ 
+ 		usb2_phy1: usb-phy@ee0a0200 {
++			reg = <0 0xee0a0200 0 0x700>;
+ 			/* placeholder */
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
++			reg = <0 0xee100000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		sdhi1: sd@ee120000 {
++			reg = <0 0xee120000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		sdhi2: sd@ee140000 {
++			reg = <0 0xee140000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		sdhi3: sd@ee160000 {
++			reg = <0 0xee160000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+ 		usb3_phy0: usb-phy@e65ee000 {
++			reg = <0 0xe65ee000 0 0x90>;
+ 			/* placeholder */
+ 		};
+ 
+ 		usb3_peri0: usb@ee020000 {
++			reg = <0 0xee020000 0 0x400>;
+ 			/* placeholder */
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
++			reg = <0 0xee000000 0 0xc00>;
+ 			/* placeholder */
+ 		};
+ 
+ 		wdt0: watchdog@e6020000 {
++			reg = <0 0xe6020000 0 0x0c>;
+ 			/* placeholder */
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1006-arm64-dts-renesas-r8a77965-Add-address-cells-and-siz.patch b/patches/1006-arm64-dts-renesas-r8a77965-Add-address-cells-and-siz.patch
new file mode 100644
index 00000000000000..09a8678f04fe27
--- /dev/null
+++ b/patches/1006-arm64-dts-renesas-r8a77965-Add-address-cells-and-siz.patch
@@ -0,0 +1,106 @@
+From 9aa44a99af606e942fdcb57e67659a4497954127 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:54 +0100
+Subject: [PATCH 1006/1795] arm64: dts: renesas: r8a77965: Add #address-cells
+ and #size-cells
+
+Add "#address-cells" and "#size-cells" properties to all place-holder nodes
+that have children nodes defined by salvator-x[s].dtsi device tree.
+
+This silences the following DTC compiler warnings:
+Warning (reg_format): "reg" property in /soc/.. has invalid length (4 bytes)
+(#address-cells == 2, #size-cells == 1)
+Warning (avoid_default_addr_size): Relying on default #address-cells
+value for /soc/...
+Warning (avoid_default_addr_size): Relying on default #size-cells value
+for /soc/...
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ba8b5ad0afdda734001176f59d23a4ab31e61e7a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 25 +++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 4286453ba92d..61efb2d22257 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -521,6 +521,9 @@
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
+ 			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ 			/* placeholder */
+ 		};
+@@ -528,11 +531,21 @@
+ 		csi20: csi2@fea80000 {
+ 			reg = <0 0xfea80000 0 0x10000>;
+ 			/* placeholder */
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
+ 		};
+ 
+ 		csi40: csi2@feaa0000 {
+ 			reg = <0 0xfeaa0000 0 0x10000>;
+ 			/* placeholder */
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
+ 		};
+ 
+ 		vin0: video@e6ef0000 {
+@@ -611,6 +624,9 @@
+ 		};
+ 
+ 		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
+ 			reg = <0 0xe6510000 0 0x40>;
+ 			/* placeholder */
+ 		};
+@@ -621,6 +637,9 @@
+ 		};
+ 
+ 		i2c4: i2c@e66d8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
+ 			reg = <0 0xe66d8000 0 0x40>;
+ 			/* placeholder */
+ 		};
+@@ -636,6 +655,9 @@
+ 		};
+ 
+ 		i2c_dvfs: i2c@e60b0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
+ 			reg = <0 0xe60b0000 0 0x425>;
+ 			/* placeholder */
+ 		};
+@@ -681,6 +703,9 @@
+ 			/* placeholder */
+ 
+ 			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
+ 				port@0 {
+ 					reg = <0>;
+ 					du_out_rgb: endpoint {
+-- 
+2.19.0
+
diff --git a/patches/1007-arm64-dts-renesas-r8a77965-Remove-stale-reg-property.patch b/patches/1007-arm64-dts-renesas-r8a77965-Remove-stale-reg-property.patch
new file mode 100644
index 00000000000000..8ce98437f07928
--- /dev/null
+++ b/patches/1007-arm64-dts-renesas-r8a77965-Remove-stale-reg-property.patch
@@ -0,0 +1,38 @@
+From 829952393ba4cbdfef263b8c54a9bf7418d3f8f9 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:55 +0100
+Subject: [PATCH 1007/1795] arm64: dts: renesas: r8a77965: Remove stale reg
+ property
+
+Remove "reg" property from cache-controller-0 device node as it does not
+have any unit address.
+
+This silences the following DTC compiler warning:
+Warning (unit_address_vs_reg): Node /cpus/cache-controller-0 has a reg
+or ranges property, but no unit name
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 217a7d465b120f3227df592a12bbee9bac165613)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 61efb2d22257..0536b94a5ec0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -47,7 +47,6 @@
+ 
+ 		L2_CA57: cache-controller-0 {
+ 			compatible = "cache";
+-			reg = <0>;
+ 			power-domains = <&sysc 12>;
+ 			cache-unified;
+ 			cache-level = <2>;
+-- 
+2.19.0
+
diff --git a/patches/1008-arm64-dts-renesas-r8a77965-Add-phy-cells-property.patch b/patches/1008-arm64-dts-renesas-r8a77965-Add-phy-cells-property.patch
new file mode 100644
index 00000000000000..406ae096166129
--- /dev/null
+++ b/patches/1008-arm64-dts-renesas-r8a77965-Add-phy-cells-property.patch
@@ -0,0 +1,38 @@
+From 6c5ad66f23811e24e7a58270b5bacb7ddd1cf0c9 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:56 +0100
+Subject: [PATCH 1008/1795] arm64: dts: renesas: r8a77965: Add #phy-cells
+ property
+
+Add "#phy-cells" property to "usb-phy@e65ee000" device node.
+
+This silences the following DTC compiler warning:
+Warning (phys_property): Missing property '#phy-cells' in node
+/soc/usb-phy@e65ee000 or bad phandle (referred from
+/soc/usb@ee020000:phys[0])
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8a93a581457af7475aa8e874402d6ec1e4ee665c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 0536b94a5ec0..1a219674201f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -795,6 +795,7 @@
+ 
+ 		usb3_phy0: usb-phy@e65ee000 {
+ 			reg = <0 0xe65ee000 0 0x90>;
++			#phy-cells = <0>;
+ 			/* placeholder */
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1009-arm64-dts-renesas-r8a77965-Add-pwm-cells-property.patch b/patches/1009-arm64-dts-renesas-r8a77965-Add-pwm-cells-property.patch
new file mode 100644
index 00000000000000..d18dab42d47385
--- /dev/null
+++ b/patches/1009-arm64-dts-renesas-r8a77965-Add-pwm-cells-property.patch
@@ -0,0 +1,37 @@
+From 97ce5d5389d524185d89af31b7363018e45a0f19 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:57 +0100
+Subject: [PATCH 1009/1795] arm64: dts: renesas: r8a77965: Add #pwm-cells
+ property
+
+Add "#pwm-cells" property to "pwm@e6e31000" device node.
+
+This silences the following DTC compiler warning:
+Warning (pwms_property): Missing property '#pwm-cells' in node
+/soc/pwm@e6e31000 or bad phandle (referred from /backlight:pwms[0])
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eccdd3f13a6a166d70c7094d09ef365411882a59)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 1a219674201f..5dff176590d5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -668,6 +668,7 @@
+ 
+ 		pwm1: pwm@e6e31000 {
+ 			reg = <0 0xe6e31000 0 8>;
++			#pwm-cells = <2>;
+ 			/* placeholder */
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1010-arm64-dts-renesas-r8a77965-Add-interrupt-cells-prope.patch b/patches/1010-arm64-dts-renesas-r8a77965-Add-interrupt-cells-prope.patch
new file mode 100644
index 00000000000000..77f0c0f77b2834
--- /dev/null
+++ b/patches/1010-arm64-dts-renesas-r8a77965-Add-interrupt-cells-prope.patch
@@ -0,0 +1,41 @@
+From fd60ba8a7561d27b4674667000d4e9b2143c3a96 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:58 +0100
+Subject: [PATCH 1010/1795] arm64: dts: renesas: r8a77965: Add #interrupt-cells
+ property
+
+Add "#interrupt-cells" property and "interrupt-controller" label to
+"interrupt-controller@e61c0000" device node.
+
+This silences the following DTC compiler warnings:
+Warning (interrupts_property): Missing interrupt-controller or
+interrupt-map property in /soc/interrupt-controller@e61c0000
+Warning (interrupts_property): Missing #interrupt-cells in
+interrupt-parent /soc/interrupt-controller@e61c000
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f5af77016bcd80bfe850ca41da51d65bd31f8051)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 5dff176590d5..0118956cc6e0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -316,6 +316,8 @@
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
++			#interrupt-cells = <2>;
++			interrupt-controller;
+ 			reg = <0 0xe61c0000 0 0x200>;
+ 			/* placeholder */
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/1011-arm64-dts-renesas-r8a77965-Move-usb2_phy1-up.patch b/patches/1011-arm64-dts-renesas-r8a77965-Move-usb2_phy1-up.patch
new file mode 100644
index 00000000000000..792076ef26bed8
--- /dev/null
+++ b/patches/1011-arm64-dts-renesas-r8a77965-Move-usb2_phy1-up.patch
@@ -0,0 +1,47 @@
+From ba14492afb857ae8b9a964c562c333ce659dd75b Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 23 Feb 2018 14:40:59 +0100
+Subject: [PATCH 1011/1795] arm64: dts: renesas: r8a77965: Move usb2_phy1 up
+
+Move "usb2_ph1" place-holder device node next to "usb2_phy0" one.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fe6746059b165ab42e8aa0a2c7b7bf307baad660)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 0118956cc6e0..8c9648a24ee0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -604,6 +604,11 @@
+ 			/* placeholder */
+ 		};
+ 
++		usb2_phy1: usb-phy@ee0a0200 {
++			reg = <0 0xee0a0200 0 0x700>;
++			/* placeholder */
++		};
++
+ 		ohci1: usb@ee0a0000 {
+ 			reg = <0 0xee0a0000 0 0x100>;
+ 			/* placeholder */
+@@ -771,11 +776,6 @@
+ 			};
+ 		};
+ 
+-		usb2_phy1: usb-phy@ee0a0200 {
+-			reg = <0 0xee0a0200 0 0x700>;
+-			/* placeholder */
+-		};
+-
+ 		sdhi0: sd@ee100000 {
+ 			reg = <0 0xee100000 0 0x2000>;
+ 			/* placeholder */
+-- 
+2.19.0
+
diff --git a/patches/1012-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch b/patches/1012-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
new file mode 100644
index 00000000000000..3953b70ca94594
--- /dev/null
+++ b/patches/1012-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
@@ -0,0 +1,69 @@
+From cc97b697751211df77f79ad95aba392e6160399e Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 19 Feb 2018 19:20:55 +0100
+Subject: [PATCH 1012/1795] arm64: dts: renesas: Add support for Salvator-XS
+ with R-Car M3-N
+
+Add initial support for the Renesas Salvator-XS (Salvator-X 2nd version)
+development board equipped with an R-Car M3-N SiP.
+
+Most features are enabled through the shared salvator-xs.dtsi board
+description.  The memory configuration is specific to the M3-N SiP.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[geert: Switch to SPDX-License-Identifier, update patch description]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 19591a9b416669419110c8da3f4096d219b810ac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  2 +-
+ .../boot/dts/renesas/r8a77965-salvator-xs.dts | 21 +++++++++++++++++++
+ 2 files changed, 22 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 9dcc26e32891..554e31ac8bc3 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -7,7 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+-dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
++dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+new file mode 100644
+index 000000000000..8a45fc43348d
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the Salvator-X 2nd version board
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ */
++
++/dts-v1/;
++#include "r8a77965.dtsi"
++#include "salvator-xs.dtsi"
++
++/ {
++	model = "Renesas Salvator-X 2nd version board based on r8a77965";
++	compatible = "renesas,salvator-xs", "renesas,r8a77965";
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x78000000>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1013-arm64-dts-renesas-r8a77965-Add-IIC-DVFS-device-node.patch b/patches/1013-arm64-dts-renesas-r8a77965-Add-IIC-DVFS-device-node.patch
new file mode 100644
index 00000000000000..13363bfec226a6
--- /dev/null
+++ b/patches/1013-arm64-dts-renesas-r8a77965-Add-IIC-DVFS-device-node.patch
@@ -0,0 +1,56 @@
+From 478ebaed6632e0497d13e5e20aa70f179248d039 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 16:42:22 +0100
+Subject: [PATCH 1013/1795] arm64: dts: renesas: r8a77965: Add IIC-DVFS device
+ node
+
+Populate the device node for the IIC Bus Interface for DVFS (IIC for
+DVFS) on R-Car M3-N, and add an alias to fix its bus number.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8952792267fb3e14c8498e6ea9284e0da3f91a1f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 8c9648a24ee0..c1ecc1b8385f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -18,6 +18,10 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	aliases {
++		i2c7 = &i2c_dvfs;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -663,9 +667,17 @@
+ 		i2c_dvfs: i2c@e60b0000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-
++			compatible = "renesas,iic-r8a77965",
++				     "renesas,rcar-gen3-iic",
++				     "renesas,rmobile-iic";
+ 			reg = <0 0xe60b0000 0 0x425>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 926>;
++			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
++			dma-names = "tx", "rx";
++			status = "disabled";
+ 		};
+ 
+ 		pwm0: pwm@e6e30000 {
+-- 
+2.19.0
+
diff --git a/patches/1014-arm64-dts-renesas-r8a77965-Add-INTC-EX-device-node.patch b/patches/1014-arm64-dts-renesas-r8a77965-Add-INTC-EX-device-node.patch
new file mode 100644
index 00000000000000..5576e95d491524
--- /dev/null
+++ b/patches/1014-arm64-dts-renesas-r8a77965-Add-INTC-EX-device-node.patch
@@ -0,0 +1,47 @@
+From 0c06dbcbb48572fb9861c6caabaedea611f94351 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 26 Feb 2018 16:42:23 +0100
+Subject: [PATCH 1014/1795] arm64: dts: renesas: r8a77965: Add INTC-EX device
+ node
+
+Populate the device node for the Interrupt Controller for External
+Devices (INTC-EX) on R-Car M3-N, which serves external IRQ pins
+IRQ[0-5].
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ba03b432f56e29a8ee639d9e9787da283b2ed09c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index c1ecc1b8385f..b9aa0e7eaabf 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -320,10 +320,19 @@
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
++			compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			reg = <0 0xe61c0000 0 0x200>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 407>;
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+-- 
+2.19.0
+
diff --git a/patches/1015-arm64-dts-renesas-salvator-common-Override-EtherAVB-.patch b/patches/1015-arm64-dts-renesas-salvator-common-Override-EtherAVB-.patch
new file mode 100644
index 00000000000000..b80f32e5318330
--- /dev/null
+++ b/patches/1015-arm64-dts-renesas-salvator-common-Override-EtherAVB-.patch
@@ -0,0 +1,38 @@
+From 064ad43ce34dcd2dbabd8265f07d96769bf6eb68 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:45 +0100
+Subject: [PATCH 1015/1795] arm64: dts: renesas: salvator-common: Override
+ EtherAVB phy-mode
+
+As the PHY interface installed on the Salvator-X[S] board, provides TX
+channel delay, make the "phy-mode" property a board-specific one, meant
+to override the one specified in the SoC DTSI.
+
+Follow up patches will reset the r8a7795/96/965 SoC DTSI to use "rgmii"
+mode and let the board files override that.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3438ff82ddbaa430ccfcc11fe877691a7e326ae0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index acb62c73839f..326ee6b59aaa 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -248,6 +248,7 @@
+ 	pinctrl-0 = <&avb_pins>;
+ 	pinctrl-names = "default";
+ 	phy-handle = <&phy0>;
++	phy-mode = "rgmii-txid";
+ 	status = "okay";
+ 
+ 	phy0: ethernet-phy@0 {
+-- 
+2.19.0
+
diff --git a/patches/1016-arm64-dts-renesas-ulcb-Override-EtherAVB-phy-mode.patch b/patches/1016-arm64-dts-renesas-ulcb-Override-EtherAVB-phy-mode.patch
new file mode 100644
index 00000000000000..ec828645320f11
--- /dev/null
+++ b/patches/1016-arm64-dts-renesas-ulcb-Override-EtherAVB-phy-mode.patch
@@ -0,0 +1,37 @@
+From 612aa4b37ee638b5b39b67cecf75f924642387fd Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:46 +0100
+Subject: [PATCH 1016/1795] arm64: dts: renesas: ulcb: Override EtherAVB
+ phy-mode
+
+As the PHY interface installed on the ULCB board provides TX
+channel delay, make the "phy-mode" property a board-specific one, meant
+to override the one specified in the SoC DTSI.
+
+Follow up patches will reset the r8a7795/96 SoC DTSI to use "rgmii" mode\
+and let the board files override that.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b3635b18bba8fc6bd57b7747d97fc46afcf551b8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index 3e7a6b94e9f8..6f814845f8b6 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -146,6 +146,7 @@
+ 	pinctrl-0 = <&avb_pins>;
+ 	pinctrl-names = "default";
+ 	phy-handle = <&phy0>;
++	phy-mode = "rgmii-txid";
+ 	status = "okay";
+ 
+ 	phy0: ethernet-phy@0 {
+-- 
+2.19.0
+
diff --git a/patches/1017-arm64-dts-renesas-draak-Override-EtherAVB-phy-mode.patch b/patches/1017-arm64-dts-renesas-draak-Override-EtherAVB-phy-mode.patch
new file mode 100644
index 00000000000000..cdafc4ed15b277
--- /dev/null
+++ b/patches/1017-arm64-dts-renesas-draak-Override-EtherAVB-phy-mode.patch
@@ -0,0 +1,37 @@
+From 655e990e68b3d3eb87704816e56329240c5820eb Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:47 +0100
+Subject: [PATCH 1017/1795] arm64: dts: renesas: draak: Override EtherAVB
+ phy-mode
+
+As the PHY interface installed on the Draak board, provides TX
+channel delay, make the "phy-mode" property a board-specific one, meant
+to override the one specified in the SoC DTSI.
+
+Follow up patches will reset the r8a77995 SoC DTSI to use "rgmii" mode
+and let the board file override that.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9c63dcd4df91687a8378d0af1c25429c5ef23a82)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index 34c7f58417ba..d03f19414028 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -189,6 +189,7 @@
+ 	pinctrl-names = "default";
+ 	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
++	phy-mode = "rgmii-txid";
+ 	status = "okay";
+ 
+ 	phy0: ethernet-phy@0 {
+-- 
+2.19.0
+
diff --git a/patches/1018-arm64-dts-renesas-eagle-Override-EtherAVB-phy-mode.patch b/patches/1018-arm64-dts-renesas-eagle-Override-EtherAVB-phy-mode.patch
new file mode 100644
index 00000000000000..fe99247e01b881
--- /dev/null
+++ b/patches/1018-arm64-dts-renesas-eagle-Override-EtherAVB-phy-mode.patch
@@ -0,0 +1,37 @@
+From 3d13c327583be9a3566c231d8fe1ea54fdb48255 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:48 +0100
+Subject: [PATCH 1018/1795] arm64: dts: renesas: eagle: Override EtherAVB
+ phy-mode
+
+As the PHY interface installed on the Eagle board provides TX and RX
+channels delays, make the "phy-mode" property a board-specific one,
+meant to override the one specified in the SoC DTSI.
+
+Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii" mode
+and let the board file override that.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e5daa084cc9f6019a905785f0dfd1ffb146a519a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index cb4bd40584cf..fd3448deb714 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -36,6 +36,7 @@
+ &avb {
+ 	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
++	phy-mode = "rgmii-id";
+ 	status = "okay";
+ 
+ 	phy0: ethernet-phy@0 {
+-- 
+2.19.0
+
diff --git a/patches/1019-arm64-dts-renesas-v3msk-Override-EtherAVB-phy-mode.patch b/patches/1019-arm64-dts-renesas-v3msk-Override-EtherAVB-phy-mode.patch
new file mode 100644
index 00000000000000..4797953466969f
--- /dev/null
+++ b/patches/1019-arm64-dts-renesas-v3msk-Override-EtherAVB-phy-mode.patch
@@ -0,0 +1,37 @@
+From 6507b234b22cdc564b4f5b8ab901850a22692b04 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:49 +0100
+Subject: [PATCH 1019/1795] arm64: dts: renesas: v3msk: Override EtherAVB
+ phy-mode
+
+As the PHY interface installed on the V3MSK board provides TX and RX
+channels delays, make the "phy-mode" property a board-specific one,
+meant to override the one specified in the SoC DTSI.
+
+Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii"
+mode and let the board file override that.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9dcd1f26b9914864e0218712a666b23cf7e589c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+index 8624ca87d6b2..bb554eec57c8 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -34,6 +34,7 @@
+ &avb {
+ 	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
++	phy-mode = "rgmii-id";
+ 	status = "okay";
+ 
+ 	phy0: ethernet-phy@0 {
+-- 
+2.19.0
+
diff --git a/patches/1020-arm64-dts-renesas-r8a7796-Set-EtherAVB-phy-mode-to-r.patch b/patches/1020-arm64-dts-renesas-r8a7796-Set-EtherAVB-phy-mode-to-r.patch
new file mode 100644
index 00000000000000..1bf00a0128777c
--- /dev/null
+++ b/patches/1020-arm64-dts-renesas-r8a7796-Set-EtherAVB-phy-mode-to-r.patch
@@ -0,0 +1,36 @@
+From 6d02dbc8a6d66dcca45a3a2db87eac3cf4b2c1a8 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:50 +0100
+Subject: [PATCH 1020/1795] arm64: dts: renesas: r8a7796: Set EtherAVB phy mode
+ to "rgmii"
+
+Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
+files override it if the installed PHY layer provides delays for the
+RX/TX channels.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f2402dfd57ea00753dd29159a576e1dd93fdedc2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 076a9c9346ae..556eb8e45499 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -974,7 +974,7 @@
+ 			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+-			phy-mode = "rgmii-txid";
++			phy-mode = "rgmii";
+ 			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/1021-arm64-dts-renesas-r8a7795-Set-EtherAVB-phy-mode-to-r.patch b/patches/1021-arm64-dts-renesas-r8a7795-Set-EtherAVB-phy-mode-to-r.patch
new file mode 100644
index 00000000000000..027fffacb0214f
--- /dev/null
+++ b/patches/1021-arm64-dts-renesas-r8a7795-Set-EtherAVB-phy-mode-to-r.patch
@@ -0,0 +1,36 @@
+From 77caa181ae2b2a840cbf38a8e38e69e6b44887c8 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:51 +0100
+Subject: [PATCH 1021/1795] arm64: dts: renesas: r8a7795: Set EtherAVB phy mode
+ to "rgmii"
+
+Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
+files override it if the installed PHY layer provides delays for the
+RX/TX channels.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fd685e2eba1decc5cfd17e1005144400d53831f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 6d53e1cb7b29..09953cda3a55 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -873,7 +873,7 @@
+ 			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+-			phy-mode = "rgmii-txid";
++			phy-mode = "rgmii";
+ 			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/1022-arm64-dts-renesas-r8a77995-Set-EtherAVB-phy-mode-to-.patch b/patches/1022-arm64-dts-renesas-r8a77995-Set-EtherAVB-phy-mode-to-.patch
new file mode 100644
index 00000000000000..b267b02e4bb297
--- /dev/null
+++ b/patches/1022-arm64-dts-renesas-r8a77995-Set-EtherAVB-phy-mode-to-.patch
@@ -0,0 +1,36 @@
+From d76539f988a50d2bcaacc47a76ccf0726585d668 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:52 +0100
+Subject: [PATCH 1022/1795] arm64: dts: renesas: r8a77995: Set EtherAVB phy
+ mode to "rgmii"
+
+Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
+files override it if the installed PHY layer provides delays for the
+RX/TX channels.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e9131e54d1a834b085766d6318a28b03942fa455)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index bcf737a20636..82aed7ee984c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -512,7 +512,7 @@
+ 			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+-			phy-mode = "rgmii-txid";
++			phy-mode = "rgmii";
+ 			iommus = <&ipmmu_ds0 16>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/1023-arm64-dts-renesas-r8a77970-Set-EtherAVB-phy-mode-to-.patch b/patches/1023-arm64-dts-renesas-r8a77970-Set-EtherAVB-phy-mode-to-.patch
new file mode 100644
index 00000000000000..e82ae966749e2b
--- /dev/null
+++ b/patches/1023-arm64-dts-renesas-r8a77970-Set-EtherAVB-phy-mode-to-.patch
@@ -0,0 +1,35 @@
+From 658ec1dc8b3e371c294b39283559d2639bd7ab33 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:53 +0100
+Subject: [PATCH 1023/1795] arm64: dts: renesas: r8a77970: Set EtherAVB phy
+ mode to "rgmii"
+
+Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
+files override it if the installed PHY layer provides delays for the
+RX/TX channels.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 95c969d12ea19062077448a0081dc657232edd1d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 31eeca1531f6..13ff4305416e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -519,7 +519,7 @@
+ 			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+-			phy-mode = "rgmii-id";
++			phy-mode = "rgmii";
+ 			iommus = <&ipmmu_rt 3>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/1024-arm64-dts-renesas-r8a77965-Add-EtherAVB-device-node.patch b/patches/1024-arm64-dts-renesas-r8a77965-Add-EtherAVB-device-node.patch
new file mode 100644
index 00000000000000..8cd4ebca60c688
--- /dev/null
+++ b/patches/1024-arm64-dts-renesas-r8a77965-Add-EtherAVB-device-node.patch
@@ -0,0 +1,78 @@
+From fab4bddf93cd3fc36e8ba9335681529444196948 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 11:22:54 +0100
+Subject: [PATCH 1024/1795] arm64: dts: renesas: r8a77965: Add EtherAVB device
+ node
+
+Populate the ethernet@e6800000 device node to enable Ethernet interface
+for R-Car M3-N (R8A77965) SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 862a61d0e4705409271639fca8776020b6cff4a8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 43 +++++++++++++++++++++--
+ 1 file changed, 40 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index b9aa0e7eaabf..f0871fcdd984 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -535,11 +535,48 @@
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77965",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+-			/* placeholder */
++			status = "disabled";
+ 		};
+ 
+ 		csi20: csi2@fea80000 {
+-- 
+2.19.0
+
diff --git a/patches/1025-arm64-dts-renesas-r8a77965-salvator-xs-Add-SoC-name-.patch b/patches/1025-arm64-dts-renesas-r8a77965-salvator-xs-Add-SoC-name-.patch
new file mode 100644
index 00000000000000..b49a9d8bfd6b45
--- /dev/null
+++ b/patches/1025-arm64-dts-renesas-r8a77965-salvator-xs-Add-SoC-name-.patch
@@ -0,0 +1,33 @@
+From daf409955ac5f60072114b99e30e8fad4075b704 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 13:02:21 +0100
+Subject: [PATCH 1025/1795] arm64: dts: renesas: r8a77965-salvator-xs: Add SoC
+ name to file header
+
+Document clearly which SoC this DTS applies to, to distinguish from
+Salvator-XS boards equipped with other SoCs.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 972952d39fc1e2274c273ec9f1a47bcce30a5722)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+index 8a45fc43348d..a83a00deed9e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+- * Device Tree Source for the Salvator-X 2nd version board
++ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
+  *
+  * Copyright (C) 2017 Renesas Electronics Corp.
+  */
+-- 
+2.19.0
+
diff --git a/patches/1026-arm64-dts-renesas-r8a77970-add-I2C-support.patch b/patches/1026-arm64-dts-renesas-r8a77970-add-I2C-support.patch
new file mode 100644
index 00000000000000..4af1ebed773341
--- /dev/null
+++ b/patches/1026-arm64-dts-renesas-r8a77970-add-I2C-support.patch
@@ -0,0 +1,135 @@
+From 8551fcb2cc5c1fe551e059631499c389984883c8 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 3 Mar 2018 22:06:21 +0300
+Subject: [PATCH 1026/1795] arm64: dts: renesas: r8a77970: add I2C support
+
+Define the generic R8A77970 parts of the I2C[0-4] device node.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cbfa278e20913a9b8380278149fa7e4068ea82e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 93 +++++++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 13ff4305416e..e44281cc1047 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -19,6 +19,14 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -338,6 +346,91 @@
+ 			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
+ 		};
+ 
++		i2c0: i2c@e6500000 {
++			compatible = "renesas,i2c-r8a77970",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6500000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6508000 {
++			compatible = "renesas,i2c-r8a77970",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6510000 {
++			compatible = "renesas,i2c-r8a77970",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6510000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e66d0000 {
++			compatible = "renesas,i2c-r8a77970",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d0000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			dmas = <&dmac1 0x97>, <&dmac1 0x96>,
++			       <&dmac2 0x97>, <&dmac2 0x96>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c4: i2c@e66d8000 {
++			compatible = "renesas,i2c-r8a77970",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d8000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			dmas = <&dmac1 0x99>, <&dmac1 0x98>,
++			       <&dmac2 0x99>, <&dmac2 0x98>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		hscif0: serial@e6540000 {
+ 			compatible = "renesas,hscif-r8a77970",
+ 				     "renesas,rcar-gen3-hscif",
+-- 
+2.19.0
+
diff --git a/patches/1027-arm64-dts-renesas-eagle-add-I2C0-support.patch b/patches/1027-arm64-dts-renesas-eagle-add-I2C0-support.patch
new file mode 100644
index 00000000000000..183b2910f5e0f7
--- /dev/null
+++ b/patches/1027-arm64-dts-renesas-eagle-add-I2C0-support.patch
@@ -0,0 +1,59 @@
+From 9013416f126d82fc8e6a23c4bac1479c92834b44 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 3 Mar 2018 22:07:16 +0300
+Subject: [PATCH 1027/1795] arm64: dts: renesas: eagle: add I2C0 support
+
+Define the Eagle board dependent part of the I2C0 device node.
+
+The I2C0 bus is populated by ON Semiconductor PCA9653 I/O expander and
+Analog Devices ADV7511W HDMI transmitter (but we're only describing the
+former chip now).
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7859eb31e4d457496ace72965f2fbb50e836ef12)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index fd3448deb714..3c5f598c9766 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -55,7 +55,27 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&i2c0 {
++	pinctrl-0 = <&i2c0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	io_expander: gpio@20 {
++		compatible = "onnn,pca9654";
++		reg = <0x20>;
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++};
++
+ &pfc {
++	i2c0_pins: i2c0 {
++		groups = "i2c0";
++		function = "i2c0";
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data";
+ 		function = "scif0";
+-- 
+2.19.0
+
diff --git a/patches/1028-arm64-dts-renesas-r8a77970-sort-subnodes-of-root-nod.patch b/patches/1028-arm64-dts-renesas-r8a77970-sort-subnodes-of-root-nod.patch
new file mode 100644
index 00000000000000..310d9526d8ca31
--- /dev/null
+++ b/patches/1028-arm64-dts-renesas-r8a77970-sort-subnodes-of-root-nod.patch
@@ -0,0 +1,49 @@
+From c467a33f35998e113d72c0b20c899de94b4a8da7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 5 Mar 2018 18:24:55 +0100
+Subject: [PATCH 1028/1795] arm64: dts: renesas: r8a77970: sort subnodes of
+ root node alphabetically
+
+Sort root sub-nodes alphabetically for allow for easier maintenance of
+this file.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c7a99343cc30704c1d173de9bbe06adaa5e96101)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index e44281cc1047..c6db8ea43906 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -27,11 +27,6 @@
+ 		i2c4 = &i2c4;
+ 	};
+ 
+-	psci {
+-		compatible = "arm,psci-1.0", "arm,psci-0.2";
+-		method = "smc";
+-	};
+-
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -68,6 +63,11 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
+ 	/* External SCIF clock - to be overridden by boards that provide it */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1029-arm64-dts-renesas-r8a7795-Add-IPMMU-PV1-device-node.patch b/patches/1029-arm64-dts-renesas-r8a7795-Add-IPMMU-PV1-device-node.patch
new file mode 100644
index 00000000000000..75c7f79864f533
--- /dev/null
+++ b/patches/1029-arm64-dts-renesas-r8a7795-Add-IPMMU-PV1-device-node.patch
@@ -0,0 +1,62 @@
+From 84e1d1d1416e9519128f6b3957f943c368d14b2d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 6 Mar 2018 10:34:30 +0100
+Subject: [PATCH 1029/1795] arm64: dts: renesas: r8a7795: Add IPMMU-PV1 device
+ node
+
+Add r8a7795 IPMMU-PV1 and keep it disabled by default.
+
+This device is not present in r8a7795 ES1.x and
+is removed from the DT of those SoCs.
+
+This corrects an omission in
+3b7e7848f0e8 ("arm64: dts: renesas: r8a7795: Add IPMMU device nodes")
+
+This does not have any runtime effect.
+
+Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+(cherry picked from commit 9dd660eb1c201304b5d79012695fc6bca57f99a0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 +
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi     | 9 +++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index f1d5e90503d5..f9acd125d687 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -23,6 +23,7 @@
+ 
+ 	/delete-node/ mmu@febe0000;
+ 	/delete-node/ mmu@fe980000;
++	/delete-node/ mmu@fd950000;
+ 	/delete-node/ mmu@fd960000;
+ 	/delete-node/ mmu@fd970000;
+ 
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 09953cda3a55..0648fe451d09 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -545,6 +545,15 @@
+ 			status = "disabled";
+ 		};
+ 
++		ipmmu_pv1: mmu@fd950000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd950000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		ipmmu_pv2: mmu@fd960000 {
+ 			compatible = "renesas,ipmmu-r8a7795";
+ 			reg = <0 0xfd960000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/1030-arm64-dts-renesas-r8a7795-Add-missing-SYS-DMAC2-dmas.patch b/patches/1030-arm64-dts-renesas-r8a7795-Add-missing-SYS-DMAC2-dmas.patch
new file mode 100644
index 00000000000000..675e1408786cd3
--- /dev/null
+++ b/patches/1030-arm64-dts-renesas-r8a7795-Add-missing-SYS-DMAC2-dmas.patch
@@ -0,0 +1,154 @@
+From ce81914959677de3f1ec901d8144a0620824d8a4 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 15:24:14 +0100
+Subject: [PATCH 1030/1795] arm64: dts: renesas: r8a7795: Add missing SYS-DMAC2
+ dmas
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On R-Car H3, on-chip peripheral modules that can make use of DMA are
+wired to either SYS-DMAC0 only, or to both SYS-DMAC1 and SYS-DMAC2.
+
+Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2],
+SCIF[0125], and I2C[0-2].  These were initially left out because early
+firmware versions prohibited using SYS-DMAC2.  This restriction has been
+lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25, 2016).
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit eb21089c32054ecd6957d294a7125bbf100ff328)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 50 ++++++++++++++----------
+ 1 file changed, 30 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 0648fe451d09..1d5e3ac0231c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1076,8 +1076,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x31>, <&dmac1 0x30>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
++			       <&dmac2 0x31>, <&dmac2 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 520>;
+ 			status = "disabled";
+@@ -1093,8 +1094,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x33>, <&dmac1 0x32>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
++			       <&dmac2 0x33>, <&dmac2 0x32>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 519>;
+ 			status = "disabled";
+@@ -1110,8 +1112,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x35>, <&dmac1 0x34>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
++			       <&dmac2 0x35>, <&dmac2 0x34>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 518>;
+ 			status = "disabled";
+@@ -1222,8 +1225,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x51>, <&dmac1 0x50>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 207>;
+ 			status = "disabled";
+@@ -1238,8 +1242,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x53>, <&dmac1 0x52>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 206>;
+ 			status = "disabled";
+@@ -1254,8 +1259,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x13>, <&dmac1 0x12>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
++			       <&dmac2 0x13>, <&dmac2 0x12>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 310>;
+ 			status = "disabled";
+@@ -1302,8 +1308,9 @@
+ 				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
++			       <&dmac2 0x5b>, <&dmac2 0x5a>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 202>;
+ 			status = "disabled";
+@@ -1335,8 +1342,9 @@
+ 			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 931>;
+-			dmas = <&dmac1 0x91>, <&dmac1 0x90>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+@@ -1351,8 +1359,9 @@
+ 			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 930>;
+-			dmas = <&dmac1 0x93>, <&dmac1 0x92>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+@@ -1367,8 +1376,9 @@
+ 			clocks = <&cpg CPG_MOD 929>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 929>;
+-			dmas = <&dmac1 0x95>, <&dmac1 0x94>;
+-			dma-names = "tx", "rx";
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/1031-arm64-defconfig-Enable-the-Tegra-SMMU-by-default.patch b/patches/1031-arm64-defconfig-Enable-the-Tegra-SMMU-by-default.patch
new file mode 100644
index 00000000000000..36661ec146cf55
--- /dev/null
+++ b/patches/1031-arm64-defconfig-Enable-the-Tegra-SMMU-by-default.patch
@@ -0,0 +1,40 @@
+From 8eb062fddf2e97851c7336101d74ca5e878210b5 Mon Sep 17 00:00:00 2001
+From: Thierry Reding <treding@nvidia.com>
+Date: Wed, 14 Mar 2018 12:10:14 +0100
+Subject: [PATCH 1031/1795] arm64: defconfig: Enable the Tegra SMMU by default
+
+Display and graphics can't work together without an SMMU, so it is
+effectively always getting enabled anyway.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+(cherry picked from commit dc7073b0234ee6f48a8e609cd2def777de1e2d26)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 81ddc9491ec8..151db66f5347 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -547,6 +547,7 @@ CONFIG_BCM2835_MBOX=y
+ CONFIG_HI6220_MBOX=y
+ CONFIG_QCOM_APCS_IPC=y
+ CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_TEGRA_IOMMU_SMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
+ CONFIG_QCOM_IOMMU=y
+@@ -562,6 +563,8 @@ CONFIG_ARCH_TEGRA_210_SOC=y
+ CONFIG_ARCH_TEGRA_186_SOC=y
+ CONFIG_ARCH_TEGRA_194_SOC=y
+ CONFIG_EXTCON_USB_GPIO=y
++CONFIG_MEMORY=y
++CONFIG_TEGRA_MC=y
+ CONFIG_IIO=y
+ CONFIG_EXYNOS_ADC=y
+ CONFIG_ROCKCHIP_SARADC=m
+-- 
+2.19.0
+
diff --git a/patches/1032-arm64-dts-renesas-v3msk-add-SCIF0-pins.patch b/patches/1032-arm64-dts-renesas-v3msk-add-SCIF0-pins.patch
new file mode 100644
index 00000000000000..6d8924180666f7
--- /dev/null
+++ b/patches/1032-arm64-dts-renesas-v3msk-add-SCIF0-pins.patch
@@ -0,0 +1,42 @@
+From 6c7c9f1213ddc6485db14a949686f83c68d003db Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 13 Mar 2018 22:26:01 +0300
+Subject: [PATCH 1032/1795] arm64: dts: renesas: v3msk: add SCIF0 pins
+
+Add the (previously omitted) SCIF0 pin data to the V3M Starter Kit board's
+device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ca565be2b526a731d02a2fbff96fb0572567ea55)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+index bb554eec57c8..a8ceeac77992 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -51,6 +51,16 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&pfc {
++	scif0_pins: scif0 {
++		groups = "scif0_data";
++		function = "scif0";
++	};
++};
++
+ &scif0 {
++	pinctrl-0 = <&scif0_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/1033-arm64-defconfig-enable-stmmac-ethernet-to-defconfig.patch b/patches/1033-arm64-defconfig-enable-stmmac-ethernet-to-defconfig.patch
new file mode 100644
index 00000000000000..7dc1c307209a0b
--- /dev/null
+++ b/patches/1033-arm64-defconfig-enable-stmmac-ethernet-to-defconfig.patch
@@ -0,0 +1,48 @@
+From 5f0fb1bac641567e70b4b1d333bd0b2afdc286e9 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Fri, 23 Feb 2018 17:24:59 -0600
+Subject: [PATCH 1033/1795] arm64: defconfig: enable stmmac ethernet to
+ defconfig
+
+This patch enables the CONFIG_STMMAC_ETH to the default arm64 defconfig:
+
+-CONFIG_STMMAC_ETH=m
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_IPQ806X=m
++CONFIG_DWMAC_MESON=m
++CONFIG_DWMAC_ROCKCHIP=m
++CONFIG_DWMAC_SUNXI=m
++CONFIG_DWMAC_SUN8I=m
+
+The STMMAC ethernet controller is on the Stratix10 platform, and thus needs
+driver to be in the kernel image for NFS to work.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 83d6e27e6856edf30845df8708b3b1e226ba5c7f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 151db66f5347..fe21d494e145 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -221,7 +221,12 @@ CONFIG_RAVB=y
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
+ CONFIG_SNI_NETSEC=y
+-CONFIG_STMMAC_ETH=m
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_IPQ806X=m
++CONFIG_DWMAC_MESON=m
++CONFIG_DWMAC_ROCKCHIP=m
++CONFIG_DWMAC_SUNXI=m
++CONFIG_DWMAC_SUN8I=m
+ CONFIG_MDIO_BUS_MUX_MMIOREG=y
+ CONFIG_AT803X_PHY=m
+ CONFIG_MARVELL_PHY=m
+-- 
+2.19.0
+
diff --git a/patches/1034-arm64-defconfig-add-CONFIG_UNIPHIER_THERMAL-and-CONF.patch b/patches/1034-arm64-defconfig-add-CONFIG_UNIPHIER_THERMAL-and-CONF.patch
new file mode 100644
index 00000000000000..eae04800995e51
--- /dev/null
+++ b/patches/1034-arm64-defconfig-add-CONFIG_UNIPHIER_THERMAL-and-CONF.patch
@@ -0,0 +1,41 @@
+From ea0bfcc879925db6d735e3aaad13bd5025793525 Mon Sep 17 00:00:00 2001
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Date: Tue, 27 Mar 2018 21:23:27 +0900
+Subject: [PATCH 1034/1795] arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and
+ CONFIG_SNI_AVE
+
+Enable the thermal monitor driver and the AVE ethernet driver
+implemented on UniPhier SoCs.
+
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit d28db34a561ade68d30acc3d66d3cd8d9f26bcc9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index fe21d494e145..3b93432ee64f 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -220,6 +220,7 @@ CONFIG_QCOM_EMAC=m
+ CONFIG_RAVB=y
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
++CONFIG_SNI_AVE=y
+ CONFIG_SNI_NETSEC=y
+ CONFIG_STMMAC_ETH=y
+ CONFIG_DWMAC_IPQ806X=m
+@@ -350,6 +351,7 @@ CONFIG_RCAR_GEN3_THERMAL=y
+ CONFIG_QCOM_TSENS=y
+ CONFIG_ROCKCHIP_THERMAL=m
+ CONFIG_TEGRA_BPMP_THERMAL=m
++CONFIG_UNIPHIER_THERMAL=y
+ CONFIG_WATCHDOG=y
+ CONFIG_S3C2410_WATCHDOG=y
+ CONFIG_MESON_GXBB_WATCHDOG=m
+-- 
+2.19.0
+
diff --git a/patches/1035-arm64-add-Renesas-R8A77965-support.patch b/patches/1035-arm64-add-Renesas-R8A77965-support.patch
new file mode 100644
index 00000000000000..ca493b53cd17a8
--- /dev/null
+++ b/patches/1035-arm64-add-Renesas-R8A77965-support.patch
@@ -0,0 +1,37 @@
+From 9d83dd40d634319348f6dea01c64b0a40e0abafe Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:09 +0100
+Subject: [PATCH 1035/1795] arm64: add Renesas R8A77965 support
+
+Add configuration option for the R-Car M3-N (R8A77965) SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fd60ea3171c7429a37c5b47a9893f96c704f990d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/Kconfig.platforms | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index b4da79327fe0..b9f42b6040bd 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -185,6 +185,12 @@ config ARCH_R8A7796
+ 	help
+ 	  This enables support for the Renesas R-Car M3-W SoC.
+ 
++config ARCH_R8A77965
++	bool "Renesas R-Car M3-N SoC Platform"
++	depends on ARCH_RENESAS
++	help
++	  This enables support for the Renesas R-Car M3-N SoC.
++
+ config ARCH_R8A77970
+ 	bool "Renesas R-Car V3M SoC Platform"
+ 	depends on ARCH_RENESAS
+-- 
+2.19.0
+
diff --git a/patches/1036-arm64-add-Renesas-R8A77980-support.patch b/patches/1036-arm64-add-Renesas-R8A77980-support.patch
new file mode 100644
index 00000000000000..bea083b857301f
--- /dev/null
+++ b/patches/1036-arm64-add-Renesas-R8A77980-support.patch
@@ -0,0 +1,40 @@
+From e9dafcd4dc57fda7f1ab370de43365e5e954b939 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 31 Jan 2018 22:59:03 +0300
+Subject: [PATCH 1036/1795] arm64: add Renesas R8A77980 support
+
+Add a configuration option for the R-Car V3H (R8A77980) SoC.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b85e1f77d9e285e61f8aa5a3a7e2bc46431d07ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/Kconfig.platforms | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index b9f42b6040bd..3a96d394aea4 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -197,6 +197,12 @@ config ARCH_R8A77970
+ 	help
+ 	  This enables support for the Renesas R-Car V3M SoC.
+ 
++config ARCH_R8A77980
++	bool "Renesas R-Car V3H SoC Platform"
++	depends on ARCH_RENESAS
++	help
++	  This enables support for the Renesas R-Car V3H SoC.
++
+ config ARCH_R8A77995
+ 	bool "Renesas R-Car D3 SoC Platform"
+ 	depends on ARCH_RENESAS
+-- 
+2.19.0
+
diff --git a/patches/1037-drm-rcar-du-dw-hdmi-Fix-compilation.patch b/patches/1037-drm-rcar-du-dw-hdmi-Fix-compilation.patch
new file mode 100644
index 00000000000000..e1f59c9d72dd86
--- /dev/null
+++ b/patches/1037-drm-rcar-du-dw-hdmi-Fix-compilation.patch
@@ -0,0 +1,45 @@
+From b691bd93ca9c89e861e3c53da1074a6d1d48cb59 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@bootlin.com>
+Date: Fri, 16 Feb 2018 16:44:12 +0100
+Subject: [PATCH 1037/1795] drm/rcar-du: dw-hdmi: Fix compilation
+
+Commit eea034af90c6 ("drm/bridge/synopsys: dw-hdmi: don't clobber drvdata")
+broke the build with one build error and one warning. Fix both.
+
+Cc: Archit Taneja <architt@codeaurora.org>
+Cc: Jernej Skrabec <jernej.skrabec@siol.net>
+Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Fixes: eea034af90c6 ("drm/bridge/synopsys: dw-hdmi: don't clobber drvdata")
+Reported-by: kbuild test robot <fengguang.wu@intel.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180216154412.22876-1-maxime.ripard@bootlin.com
+(cherry picked from commit cd0e93d865538decfd0f917c112d3fc57aac90fe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
+index 3bebc6821e9c..76210ae25094 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
++++ b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
+@@ -75,11 +75,13 @@ static int rcar_dw_hdmi_probe(struct platform_device *pdev)
+ 		return PTR_ERR(hdmi);
+ 
+ 	platform_set_drvdata(pdev, hdmi);
++
++	return 0;
+ }
+ 
+ static int rcar_dw_hdmi_remove(struct platform_device *pdev)
+ {
+-	struct dw_hdmi *hdmi = platform_get_drvdata(dev);
++	struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
+ 
+ 	dw_hdmi_remove(hdmi);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1038-drm-rcar-du-Use-drm_mode_get_hv_timing-to-populate-p.patch b/patches/1038-drm-rcar-du-Use-drm_mode_get_hv_timing-to-populate-p.patch
new file mode 100644
index 00000000000000..fc4b8b3de8248c
--- /dev/null
+++ b/patches/1038-drm-rcar-du-Use-drm_mode_get_hv_timing-to-populate-p.patch
@@ -0,0 +1,59 @@
+From e6df66b684c544b6ae2099becf831d88f845e250 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 23 Jan 2018 19:08:53 +0200
+Subject: [PATCH 1038/1795] drm/rcar-du: Use drm_mode_get_hv_timing() to
+ populate plane clip rectangle
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use drm_mode_get_hv_timing() to fill out the plane clip rectangle.
+
+No functional changes as the code already uses crtc_state->mode
+to populate the clip, which is also what drm_mode_get_hv_timing()
+uses.
+
+Once everyone agrees on this we can move the clip handling into
+drm_atomic_helper_check_plane_state().
+
+Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180123170857.13818-1-ville.syrjala@linux.intel.com
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit b46a24bcc2b4c4e8b3cbd8c804ecd987a1354d03)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_plane.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+index 4a3d16cf3ed6..5687a94d4cb1 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+@@ -572,7 +572,7 @@ int __rcar_du_plane_atomic_check(struct drm_plane *plane,
+ {
+ 	struct drm_device *dev = plane->dev;
+ 	struct drm_crtc_state *crtc_state;
+-	struct drm_rect clip;
++	struct drm_rect clip = {};
+ 	int ret;
+ 
+ 	if (!state->crtc) {
+@@ -589,10 +589,9 @@ int __rcar_du_plane_atomic_check(struct drm_plane *plane,
+ 	if (IS_ERR(crtc_state))
+ 		return PTR_ERR(crtc_state);
+ 
+-	clip.x1 = 0;
+-	clip.y1 = 0;
+-	clip.x2 = crtc_state->mode.hdisplay;
+-	clip.y2 = crtc_state->mode.vdisplay;
++	if (crtc_state->enable)
++		drm_mode_get_hv_timing(&crtc_state->mode,
++				       &clip.x2, &clip.y2);
+ 
+ 	ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
+ 						  DRM_PLANE_HELPER_NO_SCALING,
+-- 
+2.19.0
+
diff --git a/patches/1039-drm-rcar-du-Remove-zpos-field-from-rcar_du_vsp_plane.patch b/patches/1039-drm-rcar-du-Remove-zpos-field-from-rcar_du_vsp_plane.patch
new file mode 100644
index 00000000000000..7155412a8f7700
--- /dev/null
+++ b/patches/1039-drm-rcar-du-Remove-zpos-field-from-rcar_du_vsp_plane.patch
@@ -0,0 +1,44 @@
+From 8c70b2f0a15c4c9c00dfec7bdbabdad47af036a8 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 17 Jan 2018 19:40:03 +0200
+Subject: [PATCH 1039/1795] drm: rcar-du: Remove zpos field from
+ rcar_du_vsp_plane_state structure
+
+Since commit 2fc4d838aaf2 ("drm: rcar: use generic code for managing
+zpos plane property") the rcar-du driver stores the plane zpos in the
+drm_plane_state structure. The commit however forgot to remove the zpos
+field from the rcar_du_vsp_plane_state structure. Remove it.
+
+Fixes: 2fc4d838aaf2 ("drm: rcar: use generic code for managing zpos plane property")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit 94255fd39ae88cc8f6bd84a5492f85112d14e1a9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+index f876c512163c..4c5d7bbce6aa 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+@@ -45,7 +45,6 @@ static inline struct rcar_du_vsp_plane *to_rcar_vsp_plane(struct drm_plane *p)
+  * @format: information about the pixel format used by the plane
+  * @sg_tables: scatter-gather tables for the frame buffer memory
+  * @alpha: value of the plane alpha property
+- * @zpos: value of the plane zpos property
+  */
+ struct rcar_du_vsp_plane_state {
+ 	struct drm_plane_state state;
+@@ -54,7 +53,6 @@ struct rcar_du_vsp_plane_state {
+ 	struct sg_table sg_tables[3];
+ 
+ 	unsigned int alpha;
+-	unsigned int zpos;
+ };
+ 
+ static inline struct rcar_du_vsp_plane_state *
+-- 
+2.19.0
+
diff --git a/patches/1040-drm-rcar-du-Use-1000-to-avoid-misunderstanding-in-rc.patch b/patches/1040-drm-rcar-du-Use-1000-to-avoid-misunderstanding-in-rc.patch
new file mode 100644
index 00000000000000..ced5fe419d4b05
--- /dev/null
+++ b/patches/1040-drm-rcar-du-Use-1000-to-avoid-misunderstanding-in-rc.patch
@@ -0,0 +1,35 @@
+From 4016fa562af102826c562b893bc2bdb058c8ab2f Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 18 Dec 2017 00:35:18 +0000
+Subject: [PATCH 1040/1795] drm: rcar-du: Use 1000 to avoid misunderstanding in
+ rcar_du_dpll_divider()
+
+It is difficult to understand its scale if number has many 0s.
+This patch uses "* 1000" to avoid it in rcar_du_dpll_divider().
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit b45c138502ad8dc84f50694430da293678c6d9cc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index 5685d5af6998..6820461f5ed1 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -132,7 +132,7 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
+ 
+ 				output = input * (n + 1) / (m + 1)
+ 				       / (fdpll + 1);
+-				if (output >= 400000000)
++				if (output >= 400 * 1000 * 1000)
+ 					continue;
+ 
+ 				diff = abs((long)output - (long)target);
+-- 
+2.19.0
+
diff --git a/patches/1041-drm-rcar-du-Calculate-DPLLCR-to-be-more-small-jitter.patch b/patches/1041-drm-rcar-du-Calculate-DPLLCR-to-be-more-small-jitter.patch
new file mode 100644
index 00000000000000..0a530953a4e761
--- /dev/null
+++ b/patches/1041-drm-rcar-du-Calculate-DPLLCR-to-be-more-small-jitter.patch
@@ -0,0 +1,119 @@
+From bd9acdf656599e20c581685c7f0874c2a709a8c0 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 18 Dec 2017 00:35:56 +0000
+Subject: [PATCH 1041/1795] drm: rcar-du: Calculate DPLLCR to be more small
+ jitter
+
+In general, PLL has VCO (= Voltage controlled oscillator),
+one of the very important electronic feature called as "jitter"
+is related to this VCO.
+In academic generalism, VCO should be maximum to be more small jitter.
+In high frequency clock, jitter will be large impact.
+Thus, selecting Hi VCO is general theory.
+
+   fin                                 fvco        fout      fclkout
+in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
+             +-> |  |                             |
+             |                                    |
+             +-----------------[1/N]<-------------+
+
+	fclkout = fvco / P / FDPLL -- (1)
+
+In PD, it will loop until fin/M = fvco/P/N
+
+	fvco = fin * P *  N / M -- (2)
+
+(1) + (2) indicates
+
+	fclkout = fin * N / M / FDPLL
+
+In this device, N = (n + 1), M = (m + 1), P = 2, FDPLL = (fdpll + 1).
+
+	fclkout = fin * (n + 1) / (m + 1) / (fdpll + 1)
+
+This is the datasheet formula.
+One note here is that it should be 2kHz < fvco < 4096MHz
+To be smaller jitter, fvco should be maximum,
+in other words, N as large as possible, M as small as possible driver
+should select. Here, basically M=1.
+This patch do it.
+
+Reported-by: HIROSHI INOSE <hiroshi.inose.rb@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+[Small clarifications in comments, renamed finnm to fout]
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+(cherry picked from commit 0bc69592abc870f45d82e72c40e44a913d5b90c0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 49 +++++++++++++++++++++++---
+ 1 file changed, 45 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index 6820461f5ed1..c4420538ec85 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -125,13 +125,54 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
+ 	unsigned int m;
+ 	unsigned int n;
+ 
+-	for (n = 39; n < 120; n++) {
+-		for (m = 0; m < 4; m++) {
++	/*
++	 *   fin                                 fvco        fout       fclkout
++	 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
++	 *              +-> |  |                             |
++	 *              |                                    |
++	 *              +---------------- [1/N] <------------+
++	 *
++	 *	fclkout = fvco / P / FDPLL -- (1)
++	 *
++	 * fin/M = fvco/P/N
++	 *
++	 *	fvco = fin * P *  N / M -- (2)
++	 *
++	 * (1) + (2) indicates
++	 *
++	 *	fclkout = fin * N / M / FDPLL
++	 *
++	 * NOTES
++	 *	N	: (n + 1)
++	 *	M	: (m + 1)
++	 *	FDPLL	: (fdpll + 1)
++	 *	P	: 2
++	 *	2kHz < fvco < 4096MHz
++	 *
++	 * To minimize the jitter,
++	 * N : as large as possible
++	 * M : as small as possible
++	 */
++	for (m = 0; m < 4; m++) {
++		for (n = 119; n > 38; n--) {
++			/*
++			 * This code only runs on 64-bit architectures, the
++			 * unsigned long type can thus be used for 64-bit
++			 * computation. It will still compile without any
++			 * warning on 32-bit architectures.
++			 *
++			 * To optimize calculations, use fout instead of fvco
++			 * to verify the VCO frequency constraint.
++			 */
++			unsigned long fout = input * (n + 1) / (m + 1);
++
++			if (fout < 1000 || fout > 2048 * 1000 * 1000U)
++				continue;
++
+ 			for (fdpll = 1; fdpll < 32; fdpll++) {
+ 				unsigned long output;
+ 
+-				output = input * (n + 1) / (m + 1)
+-				       / (fdpll + 1);
++				output = fout / (fdpll + 1);
+ 				if (output >= 400 * 1000 * 1000)
+ 					continue;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1042-drm-rcar-du-Enable-VSP-compositor-by-default-on-Gen3.patch b/patches/1042-drm-rcar-du-Enable-VSP-compositor-by-default-on-Gen3.patch
new file mode 100644
index 00000000000000..41e22ba5f4d67e
--- /dev/null
+++ b/patches/1042-drm-rcar-du-Enable-VSP-compositor-by-default-on-Gen3.patch
@@ -0,0 +1,36 @@
+From 0b212a44af1da1abf1200ee2326fa7dbc82ea619 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 12 Jan 2018 05:15:57 +0200
+Subject: [PATCH 1042/1795] drm: rcar-du: Enable VSP compositor by default on
+ Gen3
+
+On Gen3 hardware the VSP compositor is required for display. Enable it
+by default in the kernel configuration. The option is kept
+user-configurable for testing purpose on Gen2 platforms.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+(cherry picked from commit 9ff3e797e4d6faf4cbe94f10572cfc8b3ea30109)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
+index 8a50dab19e5c..5d0b4b7119af 100644
+--- a/drivers/gpu/drm/rcar-du/Kconfig
++++ b/drivers/gpu/drm/rcar-du/Kconfig
+@@ -26,7 +26,8 @@ config DRM_RCAR_LVDS
+ 	  Enable support for the R-Car Display Unit embedded LVDS encoders.
+ 
+ config DRM_RCAR_VSP
+-	bool "R-Car DU VSP Compositor Support"
++	bool "R-Car DU VSP Compositor Support" if ARM
++	default y if ARM64
+ 	depends on DRM_RCAR_DU
+ 	depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+ 	help
+-- 
+2.19.0
+
diff --git a/patches/1043-drm-rcar-du-lvds-Fix-LVDCR1-for-R-Car-gen3.patch b/patches/1043-drm-rcar-du-lvds-Fix-LVDCR1-for-R-Car-gen3.patch
new file mode 100644
index 00000000000000..d0a8d96ebf21ee
--- /dev/null
+++ b/patches/1043-drm-rcar-du-lvds-Fix-LVDCR1-for-R-Car-gen3.patch
@@ -0,0 +1,72 @@
+From 540ac6f29fa623ad75a733fccf3aaf70d03c438c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 21 Dec 2017 23:23:30 +0300
+Subject: [PATCH 1043/1795] drm: rcar-du: lvds: Fix LVDCR1 for R-Car gen3
+
+The LVDCR1 register for the R-Car gen3 SoCs was documented as having the
+layout different from the gen2 SoCs in  the early R-Car gen3 manuals but
+since v0.52 the LVDCR1 layout is described as being the same as on the gen2
+SoCs; the old CHn control values are said to be prohibited now (and there
+seems to be no valid output signal when they are used).
+
+Fixes: 6bc2e15cf21c ("drm: rcar-du: lvds: Add R-Car Gen3 support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 3e5907a17fe4aa42d32015482132475e2b39ad50)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 10 ++++------
+ drivers/gpu/drm/rcar-du/rcar_lvds_regs.h  |  6 ++----
+ 2 files changed, 6 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+index 6a4b8c98a719..b61daf2ddc97 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+@@ -67,9 +67,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
+ 
+ 	/* Turn all the channels on. */
+ 	rcar_lvds_write(lvds, LVDCR1,
+-			LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
+-			LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
+-			LVDCR1_CLKSTBY_GEN2);
++			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
++			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
+ 
+ 	/* Enable LVDS operation and turn bias circuitry on. */
+ 	lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
+@@ -113,9 +112,8 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
+ 
+ 	/* Turn all the channels on. */
+ 	rcar_lvds_write(lvds, LVDCR1,
+-			LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
+-			LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
+-			LVDCR1_CLKSTBY_GEN3);
++			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
++			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
+ 
+ 	/*
+ 	 * Turn the PLL on, set it to LVDS normal mode, wait for the startup
+diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
+index d7d294ba2dbe..2896835ca7e9 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
++++ b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
+@@ -26,10 +26,8 @@
+ 
+ #define LVDCR1				0x0004
+ #define LVDCR1_CKSEL			(1 << 15)		/* Gen2 only */
+-#define LVDCR1_CHSTBY_GEN2(n)		(3 << (2 + (n) * 2))	/* Gen2 only */
+-#define LVDCR1_CHSTBY_GEN3(n)		(1 << (2 + (n) * 2))	/* Gen3 only */
+-#define LVDCR1_CLKSTBY_GEN2		(3 << 0)		/* Gen2 only */
+-#define LVDCR1_CLKSTBY_GEN3		(1 << 0)		/* Gen3 only */
++#define LVDCR1_CHSTBY(n)		(3 << (2 + (n) * 2))
++#define LVDCR1_CLKSTBY			(3 << 0)
+ 
+ #define LVDPLLCR			0x0008
+ #define LVDPLLCR_CEEN			(1 << 14)
+-- 
+2.19.0
+
diff --git a/patches/1044-drm-rcar-du-lvds-Fix-LVDS-clock-frequency-range.patch b/patches/1044-drm-rcar-du-lvds-Fix-LVDS-clock-frequency-range.patch
new file mode 100644
index 00000000000000..c3e5754666c775
--- /dev/null
+++ b/patches/1044-drm-rcar-du-lvds-Fix-LVDS-clock-frequency-range.patch
@@ -0,0 +1,45 @@
+From 87c4d63a18056dd57e8b4d3aac0d6d25f0b8a7f0 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 12 Jan 2018 16:17:36 +0200
+Subject: [PATCH 1044/1795] drm: rcar-du: lvds: Fix LVDS clock frequency range
+
+According to the latest versions of both the Gen2 and Gen3 datasheets,
+the operating range for the LVDS clock is 31 MHz to 148.5 MHz on all
+SoCs. Update the driver accordingly.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+(cherry picked from commit 02f0aaaaf03049ac69473015c54bdd46eaebf1e3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 10 ++--------
+ 1 file changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+index b61daf2ddc97..01ef0f728e94 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+@@ -205,17 +205,11 @@ int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
+ void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
+ 				  struct drm_display_mode *mode)
+ {
+-	struct rcar_du_device *rcdu = lvds->dev;
+-
+ 	/*
+ 	 * The internal LVDS encoder has a restricted clock frequency operating
+-	 * range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
+-	 * the clock accordingly.
++	 * range (31MHz to 148.5MHz). Clamp the clock accordingly.
+ 	 */
+-	if (rcdu->info->gen < 3)
+-		mode->clock = clamp(mode->clock, 30000, 150000);
+-	else
+-		mode->clock = clamp(mode->clock, 25175, 148500);
++	mode->clock = clamp(mode->clock, 31000, 148500);
+ }
+ 
+ void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
+-- 
+2.19.0
+
diff --git a/patches/1045-drm-rcar-du-lvds-Refactor-LVDS-startup.patch b/patches/1045-drm-rcar-du-lvds-Refactor-LVDS-startup.patch
new file mode 100644
index 00000000000000..0851342ee87655
--- /dev/null
+++ b/patches/1045-drm-rcar-du-lvds-Refactor-LVDS-startup.patch
@@ -0,0 +1,197 @@
+From 0e40a59f5de2cabe9d43fdd676104c22999ec0ac Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 19 Jan 2018 21:29:19 +0300
+Subject: [PATCH 1045/1795] drm: rcar-du: lvds: Refactor LVDS startup
+
+After the recent corrections to the R-Car gen2/3 LVDS startup code, already
+similar enough at their ends rcar_lvds_enable_gen{2|3}() started asking for
+a merge and it's becoming actually necessary with the addition of the R-Car
+V3M (R8A77970) support -- this gen3 SoC has gen2-like LVDPLLCR layout.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+[Set the LVDS mode and input before turning channels on]
+[Rebased, coding style changes]
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+(cherry picked from commit 871dfe7b48bdc56877826d6cf669e9eef0cf671b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 132 +++++++++-------------
+ 1 file changed, 51 insertions(+), 81 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+index 01ef0f728e94..4defa8123eb2 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+@@ -39,102 +39,37 @@ static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
+ 	iowrite32(data, lvds->mmio + reg);
+ }
+ 
+-static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
+-				       struct rcar_du_crtc *rcrtc)
++static u32 rcar_lvds_lvdpllcr_gen2(unsigned int freq)
+ {
+-	const struct drm_display_mode *mode = &rcrtc->crtc.mode;
+-	unsigned int freq = mode->clock;
+-	u32 lvdcr0;
+-	u32 pllcr;
+-
+-	/* PLL clock configuration */
+ 	if (freq < 39000)
+-		pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
+ 	else if (freq < 61000)
+-		pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
+ 	else if (freq < 121000)
+-		pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
+ 	else
+-		pllcr = LVDPLLCR_PLLDLYCNT_150M;
+-
+-	rcar_lvds_write(lvds, LVDPLLCR, pllcr);
+-
+-	/* Select the input and set the LVDS mode. */
+-	lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
+-	if (rcrtc->index == 2)
+-		lvdcr0 |= LVDCR0_DUSEL;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	/* Turn all the channels on. */
+-	rcar_lvds_write(lvds, LVDCR1,
+-			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
+-			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
+-
+-	/* Enable LVDS operation and turn bias circuitry on. */
+-	lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	/*
+-	 * Turn the PLL on, wait for the startup delay, and turn the output
+-	 * on.
+-	 */
+-	lvdcr0 |= LVDCR0_PLLON;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	usleep_range(100, 150);
+-
+-	lvdcr0 |= LVDCR0_LVRES;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++		return LVDPLLCR_PLLDLYCNT_150M;
+ }
+ 
+-static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
+-				       struct rcar_du_crtc *rcrtc)
++static u32 rcar_lvds_lvdpllcr_gen3(unsigned int freq)
+ {
+-	const struct drm_display_mode *mode = &rcrtc->crtc.mode;
+-	unsigned int freq = mode->clock;
+-	u32 lvdcr0;
+-	u32 pllcr;
+-
+-	/* Set the PLL clock configuration and LVDS mode. */
+ 	if (freq < 42000)
+-		pllcr = LVDPLLCR_PLLDIVCNT_42M;
++		return LVDPLLCR_PLLDIVCNT_42M;
+ 	else if (freq < 85000)
+-		pllcr = LVDPLLCR_PLLDIVCNT_85M;
++		return LVDPLLCR_PLLDIVCNT_85M;
+ 	else if (freq < 128000)
+-		pllcr = LVDPLLCR_PLLDIVCNT_128M;
++		return LVDPLLCR_PLLDIVCNT_128M;
+ 	else
+-		pllcr = LVDPLLCR_PLLDIVCNT_148M;
+-
+-	rcar_lvds_write(lvds, LVDPLLCR, pllcr);
+-
+-	lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	/* Turn all the channels on. */
+-	rcar_lvds_write(lvds, LVDCR1,
+-			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
+-			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
+-
+-	/*
+-	 * Turn the PLL on, set it to LVDS normal mode, wait for the startup
+-	 * delay and turn the output on.
+-	 */
+-	lvdcr0 |= LVDCR0_PLLON;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	lvdcr0 |= LVDCR0_PWD;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	usleep_range(100, 150);
+-
+-	lvdcr0 |= LVDCR0_LVRES;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++		return LVDPLLCR_PLLDIVCNT_148M;
+ }
+ 
+ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
+ 				 struct rcar_du_crtc *rcrtc)
+ {
++	const struct drm_display_mode *mode = &rcrtc->crtc.mode;
++	u32 lvdpllcr;
+ 	u32 lvdhcr;
++	u32 lvdcr0;
+ 	int ret;
+ 
+ 	if (lvds->enabled)
+@@ -165,11 +100,46 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
+ 
+ 	rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
+ 
+-	/* Perform generation-specific initialization. */
++	/* PLL clock configuration. */
+ 	if (lvds->dev->info->gen < 3)
+-		rcar_du_lvdsenc_start_gen2(lvds, rcrtc);
++		lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
+ 	else
+-		rcar_du_lvdsenc_start_gen3(lvds, rcrtc);
++		lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
++	rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
++
++	/* Set the LVDS mode and select the input. */
++	lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
++	if (rcrtc->index == 2)
++		lvdcr0 |= LVDCR0_DUSEL;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++
++	/* Turn all the channels on. */
++	rcar_lvds_write(lvds, LVDCR1,
++			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
++			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
++
++	if (lvds->dev->info->gen < 3) {
++		/* Enable LVDS operation and turn the bias circuitry on. */
++		lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
++		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++	}
++
++	/* Turn the PLL on. */
++	lvdcr0 |= LVDCR0_PLLON;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++
++	if (lvds->dev->info->gen > 2) {
++		/* Set LVDS normal mode. */
++		lvdcr0 |= LVDCR0_PWD;
++		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++	}
++
++	/* Wait for the startup delay. */
++	usleep_range(100, 150);
++
++	/* Turn the output on. */
++	lvdcr0 |= LVDCR0_LVRES;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+ 
+ 	lvds->enabled = true;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1046-dt-bindings-display-renesas-Add-R-Car-LVDS-encoder-D.patch b/patches/1046-dt-bindings-display-renesas-Add-R-Car-LVDS-encoder-D.patch
new file mode 100644
index 00000000000000..3477caad89b04a
--- /dev/null
+++ b/patches/1046-dt-bindings-display-renesas-Add-R-Car-LVDS-encoder-D.patch
@@ -0,0 +1,101 @@
+From feab5f9a7b534240d378418bde66336ace1c8037 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 10 Jan 2018 16:05:46 +0200
+Subject: [PATCH 1046/1795] dt-bindings: display: renesas: Add R-Car LVDS
+ encoder DT bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Renesas R-Car Gen2 and Gen3 SoCs have internal LVDS encoders. Add
+corresponding device tree bindings.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 871b456040e79e651730d832c4e19728b75ef6ce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/display/bridge/renesas,lvds.txt  | 56 +++++++++++++++++++
+ MAINTAINERS                                   |  1 +
+ 2 files changed, 57 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+new file mode 100644
+index 000000000000..af45ba9d8f90
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+@@ -0,0 +1,56 @@
++Renesas R-Car LVDS Encoder
++==========================
++
++These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
++Gen2, R-Car Gen3 and RZ/G SoCs.
++
++Required properties:
++
++- compatible : Shall contain one of
++  - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
++  - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
++  - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
++  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
++  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
++  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
++
++- reg: Base address and length for the memory-mapped registers
++- clocks: A phandle + clock-specifier pair for the functional clock
++- resets: A phandle + reset specifier for the module reset
++
++Required nodes:
++
++The LVDS encoder has two video ports. Their connections are modelled using the
++OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
++
++- Video port 0 corresponds to the parallel RGB input
++- Video port 1 corresponds to the LVDS output
++
++Each port shall have a single endpoint.
++
++
++Example:
++
++	lvds0: lvds@feb90000 {
++		compatible = "renesas,r8a7790-lvds";
++		reg = <0 0xfeb90000 0 0x1c>;
++		clocks = <&cpg CPG_MOD 726>;
++		resets = <&cpg 726>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				lvds0_in: endpoint {
++					remote-endpoint = <&du_out_lvds0>;
++				};
++			};
++			port@1 {
++				reg = <1>;
++				lvds0_out: endpoint {
++				};
++			};
++		};
++	};
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 546beb6b0176..8fec63f3fcbc 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -4617,6 +4617,7 @@ F:	drivers/gpu/drm/rcar-du/
+ F:	drivers/gpu/drm/shmobile/
+ F:	include/linux/platform_data/shmob_drm.h
+ F:	Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
++F:	Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+ F:	Documentation/devicetree/bindings/display/renesas,du.txt
+ 
+ DRM DRIVERS FOR ROCKCHIP
+-- 
+2.19.0
+
diff --git a/patches/1047-dt-bindings-display-renesas-Deprecate-LVDS-support-i.patch b/patches/1047-dt-bindings-display-renesas-Deprecate-LVDS-support-i.patch
new file mode 100644
index 00000000000000..aca3a1a23f926c
--- /dev/null
+++ b/patches/1047-dt-bindings-display-renesas-Deprecate-LVDS-support-i.patch
@@ -0,0 +1,88 @@
+From 54393ba5725836edc61f31b37a25d421a0080521 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 10 Jan 2018 16:05:46 +0200
+Subject: [PATCH 1047/1795] dt-bindings: display: renesas: Deprecate LVDS
+ support in the DU bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The internal LVDS encoders now have their own DT bindings, representing
+them as part of the DU is deprecated.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 6d2ca85279becdff6c12c3c25598f0aed472998e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/display/renesas,du.txt           | 31 +++++++------------
+ 1 file changed, 11 insertions(+), 20 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index cd48aba3bc8c..e79cf9b0ad38 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -14,12 +14,7 @@ Required Properties:
+     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
+     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ 
+-  - reg: A list of base address and length of each memory resource, one for
+-    each entry in the reg-names property.
+-  - reg-names: Name of the memory resources. The DU requires one memory
+-    resource for the DU core (named "du") and one memory resource for each
+-    LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
+-    index).
++  - reg: the memory-mapped I/O registers base address and length
+ 
+   - interrupt-parent: phandle of the parent interrupt controller.
+   - interrupts: Interrupt specifiers for the DU interrupts.
+@@ -29,14 +24,13 @@ Required Properties:
+   - clock-names: Name of the clocks. This property is model-dependent.
+     - R8A7779 uses a single functional clock. The clock doesn't need to be
+       named.
+-    - All other DU instances use one functional clock per channel and one
+-      clock per LVDS encoder (if available). The functional clocks must be
+-      named "du.x" with "x" being the channel numerical index. The LVDS clocks
+-      must be named "lvds.x" with "x" being the LVDS encoder numerical index.
+-    - In addition to the functional and encoder clocks, all DU versions also
+-      support externally supplied pixel clocks. Those clocks are optional.
+-      When supplied they must be named "dclkin.x" with "x" being the input
+-      clock numerical index.
++    - All other DU instances use one functional clock per channel The
++      functional clocks must be named "du.x" with "x" being the channel
++      numerical index.
++    - In addition to the functional clocks, all DU versions also support
++      externally supplied pixel clocks. Those clocks are optional. When
++      supplied they must be named "dclkin.x" with "x" being the input clock
++      numerical index.
+ 
+   - vsps: A list of phandle and channel index tuples to the VSPs that handle
+     the memory interfaces for the DU channels. The phandle identifies the VSP
+@@ -69,9 +63,7 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
+ 
+ 	du: display@feb00000 {
+ 		compatible = "renesas,du-r8a7795";
+-		reg = <0 0xfeb00000 0 0x80000>,
+-		      <0 0xfeb90000 0 0x14>;
+-		reg-names = "du", "lvds.0";
++		reg = <0 0xfeb00000 0 0x80000>;
+ 		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+@@ -79,9 +71,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
+ 		clocks = <&cpg CPG_MOD 724>,
+ 			 <&cpg CPG_MOD 723>,
+ 			 <&cpg CPG_MOD 722>,
+-			 <&cpg CPG_MOD 721>,
+-			 <&cpg CPG_MOD 727>;
+-		clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
++			 <&cpg CPG_MOD 721>;
++		clock-names = "du.0", "du.1", "du.2", "du.3";
+ 		vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
+ 
+ 		ports {
+-- 
+2.19.0
+
diff --git a/patches/1048-drm-rcar-du-Fix-legacy-DT-to-create-LVDS-encoder-nod.patch b/patches/1048-drm-rcar-du-Fix-legacy-DT-to-create-LVDS-encoder-nod.patch
new file mode 100644
index 00000000000000..d028fd90b0f3c3
--- /dev/null
+++ b/patches/1048-drm-rcar-du-Fix-legacy-DT-to-create-LVDS-encoder-nod.patch
@@ -0,0 +1,735 @@
+From 51c90e70206ba1917dd9ffbdd699fb54f9f863be Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 10 Jan 2018 02:40:27 +0200
+Subject: [PATCH 1048/1795] drm: rcar-du: Fix legacy DT to create LVDS encoder
+ nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The internal LVDS encoders now have their own DT bindings. Before
+switching the driver infrastructure to those new bindings, implement
+backward-compatibility through live DT patching.
+
+Patching is disabled and will be enabled along with support for the new
+DT bindings in the DU driver.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Frank Rowand <frank.rowand@sony.com>
+(cherry picked from commit 81c0e3dd82927064a2f56a31a0974a0d110fcdb0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/Kconfig               |   2 +
+ drivers/gpu/drm/rcar-du/Makefile              |   7 +-
+ drivers/gpu/drm/rcar-du/rcar_du_of.c          | 322 ++++++++++++++++++
+ drivers/gpu/drm/rcar-du/rcar_du_of.h          |  20 ++
+ .../drm/rcar-du/rcar_du_of_lvds_r8a7790.dts   |  76 +++++
+ .../drm/rcar-du/rcar_du_of_lvds_r8a7791.dts   |  50 +++
+ .../drm/rcar-du/rcar_du_of_lvds_r8a7793.dts   |  50 +++
+ .../drm/rcar-du/rcar_du_of_lvds_r8a7795.dts   |  50 +++
+ .../drm/rcar-du/rcar_du_of_lvds_r8a7796.dts   |  50 +++
+ 9 files changed, 626 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of.c
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of.h
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts
+
+diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
+index 5d0b4b7119af..3f83352a7313 100644
+--- a/drivers/gpu/drm/rcar-du/Kconfig
++++ b/drivers/gpu/drm/rcar-du/Kconfig
+@@ -22,6 +22,8 @@ config DRM_RCAR_LVDS
+ 	bool "R-Car DU LVDS Encoder Support"
+ 	depends on DRM_RCAR_DU
+ 	select DRM_PANEL
++	select OF_FLATTREE
++	select OF_OVERLAY
+ 	help
+ 	  Enable support for the R-Car Display Unit embedded LVDS encoders.
+ 
+diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
+index 0cf5c11030e8..86b337b4be5d 100644
+--- a/drivers/gpu/drm/rcar-du/Makefile
++++ b/drivers/gpu/drm/rcar-du/Makefile
+@@ -8,7 +8,12 @@ rcar-du-drm-y := rcar_du_crtc.o \
+ 		 rcar_du_plane.o
+ 
+ rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS)	+= rcar_du_lvdsenc.o
+-
++rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS)	+= rcar_du_of.o \
++					   rcar_du_of_lvds_r8a7790.dtb.o \
++					   rcar_du_of_lvds_r8a7791.dtb.o \
++					   rcar_du_of_lvds_r8a7793.dtb.o \
++					   rcar_du_of_lvds_r8a7795.dtb.o \
++					   rcar_du_of_lvds_r8a7796.dtb.o
+ rcar-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
+ 
+ obj-$(CONFIG_DRM_RCAR_DU)		+= rcar-du-drm.o
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of.c b/drivers/gpu/drm/rcar-du/rcar_du_of.c
+new file mode 100644
+index 000000000000..68a0b82cb17e
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of.c
+@@ -0,0 +1,322 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of.c - Legacy DT bindings compatibility
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ *
++ * Based on work from Jyri Sarha <jsarha@ti.com>
++ * Copyright (C) 2015 Texas Instruments
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_fdt.h>
++#include <linux/of_graph.h>
++#include <linux/slab.h>
++
++#include "rcar_du_crtc.h"
++#include "rcar_du_drv.h"
++
++/* -----------------------------------------------------------------------------
++ * Generic Overlay Handling
++ */
++
++struct rcar_du_of_overlay {
++	const char *compatible;
++	void *begin;
++	void *end;
++};
++
++#define RCAR_DU_OF_DTB(type, soc)					\
++	extern char __dtb_rcar_du_of_##type##_##soc##_begin[];		\
++	extern char __dtb_rcar_du_of_##type##_##soc##_end[]
++
++#define RCAR_DU_OF_OVERLAY(type, soc)					\
++	{								\
++		.compatible = "renesas,du-" #soc,			\
++		.begin = __dtb_rcar_du_of_##type##_##soc##_begin,	\
++		.end = __dtb_rcar_du_of_##type##_##soc##_end,		\
++	}
++
++static int __init rcar_du_of_apply_overlay(const struct rcar_du_of_overlay *dtbs,
++					   const char *compatible)
++{
++	const struct rcar_du_of_overlay *dtb = NULL;
++	unsigned int i;
++	int ovcs_id;
++
++	for (i = 0; dtbs[i].compatible; ++i) {
++		if (!strcmp(dtbs[i].compatible, compatible)) {
++			dtb = &dtbs[i];
++			break;
++		}
++	}
++
++	if (!dtb)
++		return -ENODEV;
++
++	ovcs_id = 0;
++	return of_overlay_fdt_apply(dtb->begin, dtb->end - dtb->begin,
++				    &ovcs_id);
++}
++
++static int __init rcar_du_of_add_property(struct of_changeset *ocs,
++					  struct device_node *np,
++					  const char *name, const void *value,
++					  int length)
++{
++	struct property *prop;
++	int ret = -ENOMEM;
++
++	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
++	if (!prop)
++		return -ENOMEM;
++
++	prop->name = kstrdup(name, GFP_KERNEL);
++	if (!prop->name)
++		goto out_err;
++
++	prop->value = kmemdup(value, length, GFP_KERNEL);
++	if (!prop->value)
++		goto out_err;
++
++	of_property_set_flag(prop, OF_DYNAMIC);
++
++	prop->length = length;
++
++	ret = of_changeset_add_property(ocs, np, prop);
++	if (!ret)
++		return 0;
++
++out_err:
++	kfree(prop->value);
++	kfree(prop->name);
++	kfree(prop);
++	return ret;
++}
++
++/* -----------------------------------------------------------------------------
++ * LVDS Overlays
++ */
++
++RCAR_DU_OF_DTB(lvds, r8a7790);
++RCAR_DU_OF_DTB(lvds, r8a7791);
++RCAR_DU_OF_DTB(lvds, r8a7793);
++RCAR_DU_OF_DTB(lvds, r8a7795);
++RCAR_DU_OF_DTB(lvds, r8a7796);
++
++static const struct rcar_du_of_overlay rcar_du_lvds_overlays[] __initconst = {
++	RCAR_DU_OF_OVERLAY(lvds, r8a7790),
++	RCAR_DU_OF_OVERLAY(lvds, r8a7791),
++	RCAR_DU_OF_OVERLAY(lvds, r8a7793),
++	RCAR_DU_OF_OVERLAY(lvds, r8a7795),
++	RCAR_DU_OF_OVERLAY(lvds, r8a7796),
++	{ /* Sentinel */ },
++};
++
++static struct of_changeset rcar_du_lvds_changeset;
++
++static void __init rcar_du_of_lvds_patch_one(struct device_node *lvds,
++					     const struct of_phandle_args *clk,
++					     struct device_node *local,
++					     struct device_node *remote)
++{
++	unsigned int psize;
++	unsigned int i;
++	__be32 value[4];
++	int ret;
++
++	/*
++	 * Set the LVDS clocks property. This can't be performed by the overlay
++	 * as the structure of the clock specifier has changed over time, and we
++	 * don't know at compile time which binding version the system we will
++	 * run on uses.
++	 */
++	if (clk->args_count >= ARRAY_SIZE(value) - 1)
++		return;
++
++	of_changeset_init(&rcar_du_lvds_changeset);
++
++	value[0] = cpu_to_be32(clk->np->phandle);
++	for (i = 0; i < clk->args_count; ++i)
++		value[i + 1] = cpu_to_be32(clk->args[i]);
++
++	psize = (clk->args_count + 1) * 4;
++	ret = rcar_du_of_add_property(&rcar_du_lvds_changeset, lvds,
++				      "clocks", value, psize);
++	if (ret < 0)
++		goto done;
++
++	/*
++	 * Insert the node in the OF graph: patch the LVDS ports remote-endpoint
++	 * properties to point to the endpoints of the sibling nodes in the
++	 * graph. This can't be performed by the overlay: on the input side the
++	 * overlay would contain a phandle for the DU LVDS output port that
++	 * would clash with the system DT, and on the output side the connection
++	 * is board-specific.
++	 */
++	value[0] = cpu_to_be32(local->phandle);
++	value[1] = cpu_to_be32(remote->phandle);
++
++	for (i = 0; i < 2; ++i) {
++		struct device_node *endpoint;
++
++		endpoint = of_graph_get_endpoint_by_regs(lvds, i, 0);
++		if (!endpoint) {
++			ret = -EINVAL;
++			goto done;
++		}
++
++		ret = rcar_du_of_add_property(&rcar_du_lvds_changeset,
++					      endpoint, "remote-endpoint",
++					      &value[i], sizeof(value[i]));
++		of_node_put(endpoint);
++		if (ret < 0)
++			goto done;
++	}
++
++	ret = of_changeset_apply(&rcar_du_lvds_changeset);
++
++done:
++	if (ret < 0)
++		of_changeset_destroy(&rcar_du_lvds_changeset);
++}
++
++struct lvds_of_data {
++	struct resource res;
++	struct of_phandle_args clkspec;
++	struct device_node *local;
++	struct device_node *remote;
++};
++
++static void __init rcar_du_of_lvds_patch(const struct of_device_id *of_ids)
++{
++	const struct rcar_du_device_info *info;
++	const struct of_device_id *match;
++	struct lvds_of_data lvds_data[2] = { };
++	struct device_node *lvds_node;
++	struct device_node *soc_node;
++	struct device_node *du_node;
++	char compatible[22];
++	const char *soc_name;
++	unsigned int i;
++	int ret;
++
++	/* Get the DU node and exit if not present or disabled. */
++	du_node = of_find_matching_node_and_match(NULL, of_ids, &match);
++	if (!du_node || !of_device_is_available(du_node)) {
++		of_node_put(du_node);
++		return;
++	}
++
++	info = match->data;
++	soc_node = of_get_parent(du_node);
++
++	if (WARN_ON(info->num_lvds > ARRAY_SIZE(lvds_data)))
++		goto done;
++
++	/*
++	 * Skip if the LVDS nodes already exists.
++	 *
++	 * The nodes are searched based on the compatible string, which we
++	 * construct from the SoC name found in the DU compatible string. As a
++	 * match has been found we know the compatible string matches the
++	 * expected format and can thus skip some of the string manipulation
++	 * normal safety checks.
++	 */
++	soc_name = strchr(match->compatible, '-') + 1;
++	sprintf(compatible, "renesas,%s-lvds", soc_name);
++	lvds_node = of_find_compatible_node(NULL, NULL, compatible);
++	if (lvds_node) {
++		of_node_put(lvds_node);
++		return;
++	}
++
++	/*
++	 * Parse the DU node and store the register specifier, the clock
++	 * specifier and the local and remote endpoint of the LVDS link for
++	 * later use.
++	 */
++	for (i = 0; i < info->num_lvds; ++i) {
++		struct lvds_of_data *lvds = &lvds_data[i];
++		unsigned int port;
++		char name[7];
++		int index;
++
++		sprintf(name, "lvds.%u", i);
++		index = of_property_match_string(du_node, "clock-names", name);
++		if (index < 0)
++			continue;
++
++		ret = of_parse_phandle_with_args(du_node, "clocks",
++						 "#clock-cells", index,
++						 &lvds->clkspec);
++		if (ret < 0)
++			continue;
++
++		port = info->routes[RCAR_DU_OUTPUT_LVDS0 + i].port;
++
++		lvds->local = of_graph_get_endpoint_by_regs(du_node, port, 0);
++		if (!lvds->local)
++			continue;
++
++		lvds->remote = of_graph_get_remote_endpoint(lvds->local);
++		if (!lvds->remote)
++			continue;
++
++		index = of_property_match_string(du_node, "reg-names", name);
++		if (index < 0)
++			continue;
++
++		of_address_to_resource(du_node, index, &lvds->res);
++	}
++
++	/* Parse and apply the overlay. This will resolve phandles. */
++	ret = rcar_du_of_apply_overlay(rcar_du_lvds_overlays,
++				       match->compatible);
++	if (ret < 0)
++		goto done;
++
++	/* Patch the newly created LVDS encoder nodes. */
++	for_each_child_of_node(soc_node, lvds_node) {
++		struct resource res;
++
++		if (!of_device_is_compatible(lvds_node, compatible))
++			continue;
++
++		/* Locate the lvds_data entry based on the resource start. */
++		ret = of_address_to_resource(lvds_node, 0, &res);
++		if (ret < 0)
++			continue;
++
++		for (i = 0; i < ARRAY_SIZE(lvds_data); ++i) {
++			if (lvds_data[i].res.start == res.start)
++				break;
++		}
++
++		if (i == ARRAY_SIZE(lvds_data))
++			continue;
++
++		/* Patch the LVDS encoder. */
++		rcar_du_of_lvds_patch_one(lvds_node, &lvds_data[i].clkspec,
++					  lvds_data[i].local,
++					  lvds_data[i].remote);
++	}
++
++done:
++	for (i = 0; i < info->num_lvds; ++i) {
++		of_node_put(lvds_data[i].clkspec.np);
++		of_node_put(lvds_data[i].local);
++		of_node_put(lvds_data[i].remote);
++	}
++
++	of_node_put(soc_node);
++	of_node_put(du_node);
++}
++
++void __init rcar_du_of_init(const struct of_device_id *of_ids)
++{
++	rcar_du_of_lvds_patch(of_ids);
++}
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of.h b/drivers/gpu/drm/rcar-du/rcar_du_of.h
+new file mode 100644
+index 000000000000..c2e65a727e91
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of.h
+@@ -0,0 +1,20 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * rcar_du_of.h - Legacy DT bindings compatibility
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++#ifndef __RCAR_DU_OF_H__
++#define __RCAR_DU_OF_H__
++
++#include <linux/init.h>
++
++struct of_device_id;
++
++#ifdef CONFIG_DRM_RCAR_LVDS
++void __init rcar_du_of_init(const struct of_device_id *of_ids);
++#else
++static inline void rcar_du_of_init(const struct of_device_id *of_ids) { }
++#endif /* CONFIG_DRM_RCAR_LVDS */
++
++#endif /* __RCAR_DU_OF_H__ */
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts
+new file mode 100644
+index 000000000000..579753e04f3b
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of_lvds_r8a7790.dts - Legacy LVDS DT bindings conversion for R8A7790
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++
++/dts-v1/;
++/plugin/;
++/ {
++	fragment@0 {
++		target-path = "/";
++		__overlay__ {
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			lvds@feb90000 {
++				compatible = "renesas,r8a7790-lvds";
++				reg = <0 0xfeb90000 0 0x1c>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds0_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds0_out: endpoint {
++						};
++					};
++				};
++			};
++
++			lvds@feb94000 {
++				compatible = "renesas,r8a7790-lvds";
++				reg = <0 0xfeb94000 0 0x1c>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds1_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds1_out: endpoint {
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/display@feb00000/ports";
++		__overlay__ {
++			port@1 {
++				endpoint {
++					remote-endpoint = <&lvds0_input>;
++				};
++			};
++			port@2 {
++				endpoint {
++					remote-endpoint = <&lvds1_input>;
++				};
++			};
++		};
++	};
++};
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts
+new file mode 100644
+index 000000000000..cb9da1f3942b
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of_lvds_r8a7791.dts - Legacy LVDS DT bindings conversion for R8A7791
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++
++/dts-v1/;
++/plugin/;
++/ {
++	fragment@0 {
++		target-path = "/";
++		__overlay__ {
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			lvds@feb90000 {
++				compatible = "renesas,r8a7791-lvds";
++				reg = <0 0xfeb90000 0 0x1c>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds0_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds0_out: endpoint {
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/display@feb00000/ports";
++		__overlay__ {
++			port@1 {
++				endpoint {
++					remote-endpoint = <&lvds0_input>;
++				};
++			};
++		};
++	};
++};
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts
+new file mode 100644
+index 000000000000..e7b8804dc3c1
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of_lvds_r8a7793.dts - Legacy LVDS DT bindings conversion for R8A7793
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++
++/dts-v1/;
++/plugin/;
++/ {
++	fragment@0 {
++		target-path = "/";
++		__overlay__ {
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			lvds@feb90000 {
++				compatible = "renesas,r8a7793-lvds";
++				reg = <0 0xfeb90000 0 0x1c>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds0_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds0_out: endpoint {
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/display@feb00000/ports";
++		__overlay__ {
++			port@1 {
++				endpoint {
++					remote-endpoint = <&lvds0_input>;
++				};
++			};
++		};
++	};
++};
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts
+new file mode 100644
+index 000000000000..a1327443e6fa
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of_lvds_r8a7795.dts - Legacy LVDS DT bindings conversion for R8A7795
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++
++/dts-v1/;
++/plugin/;
++/ {
++	fragment@0 {
++		target-path = "/soc";
++		__overlay__ {
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			lvds@feb90000 {
++				compatible = "renesas,r8a7795-lvds";
++				reg = <0 0xfeb90000 0 0x14>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds0_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds0_out: endpoint {
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/soc/display@feb00000/ports";
++		__overlay__ {
++			port@3 {
++				endpoint {
++					remote-endpoint = <&lvds0_input>;
++				};
++			};
++		};
++	};
++};
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts
+new file mode 100644
+index 000000000000..b23d6466c415
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_du_of_lvds_r8a7796.dts - Legacy LVDS DT bindings conversion for R8A7796
++ *
++ * Copyright (C) 2018 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
++ */
++
++/dts-v1/;
++/plugin/;
++/ {
++	fragment@0 {
++		target-path = "/soc";
++		__overlay__ {
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			lvds@feb90000 {
++				compatible = "renesas,r8a7796-lvds";
++				reg = <0 0xfeb90000 0 0x14>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						lvds0_input: endpoint {
++						};
++					};
++					port@1 {
++						reg = <1>;
++						lvds0_out: endpoint {
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/soc/display@feb00000/ports";
++		__overlay__ {
++			port@3 {
++				endpoint {
++					remote-endpoint = <&lvds0_input>;
++				};
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1049-drm-rcar-du-Convert-LVDS-encoder-code-to-bridge-driv.patch b/patches/1049-drm-rcar-du-Convert-LVDS-encoder-code-to-bridge-driv.patch
new file mode 100644
index 00000000000000..5e059781405ad3
--- /dev/null
+++ b/patches/1049-drm-rcar-du-Convert-LVDS-encoder-code-to-bridge-driv.patch
@@ -0,0 +1,1450 @@
+From 05e8f0e3a47c0b6f7d148831e77cb7ac5b181640 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 10 Jan 2018 05:47:42 +0200
+Subject: [PATCH 1049/1795] drm: rcar-du: Convert LVDS encoder code to bridge
+ driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The LVDS encoders used to be described in DT as part of the DU. They now
+have their own DT node, linked to the DU using the OF graph bindings.
+This allows moving internal LVDS encoder support to a separate driver
+modelled as a DRM bridge. Backward compatibility is retained as legacy
+DT is patched live to move to the new bindings.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit c6a27fa41fabb35fcf0273c32a86f1424fa7de91)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/Kconfig           |   4 +-
+ drivers/gpu/drm/rcar-du/Makefile          |   3 +-
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c     |  21 +-
+ drivers/gpu/drm/rcar-du/rcar_du_drv.h     |   5 -
+ drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 175 +-------
+ drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  12 -
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c     |  14 +-
+ drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c |  93 ----
+ drivers/gpu/drm/rcar-du/rcar_du_lvdscon.h |  24 -
+ drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 238 ----------
+ drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h |  64 ---
+ drivers/gpu/drm/rcar-du/rcar_lvds.c       | 524 ++++++++++++++++++++++
+ 12 files changed, 561 insertions(+), 616 deletions(-)
+ delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+ delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_lvdscon.h
+ delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+ delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
+ create mode 100644 drivers/gpu/drm/rcar-du/rcar_lvds.c
+
+diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
+index 3f83352a7313..edde8d4b87a3 100644
+--- a/drivers/gpu/drm/rcar-du/Kconfig
++++ b/drivers/gpu/drm/rcar-du/Kconfig
+@@ -19,8 +19,8 @@ config DRM_RCAR_DW_HDMI
+ 	  Enable support for R-Car Gen3 internal HDMI encoder.
+ 
+ config DRM_RCAR_LVDS
+-	bool "R-Car DU LVDS Encoder Support"
+-	depends on DRM_RCAR_DU
++	tristate "R-Car DU LVDS Encoder Support"
++	depends on DRM && DRM_BRIDGE && OF
+ 	select DRM_PANEL
+ 	select OF_FLATTREE
+ 	select OF_OVERLAY
+diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
+index 86b337b4be5d..3e58ed93d5b1 100644
+--- a/drivers/gpu/drm/rcar-du/Makefile
++++ b/drivers/gpu/drm/rcar-du/Makefile
+@@ -4,10 +4,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
+ 		 rcar_du_encoder.o \
+ 		 rcar_du_group.o \
+ 		 rcar_du_kms.o \
+-		 rcar_du_lvdscon.o \
+ 		 rcar_du_plane.o
+ 
+-rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS)	+= rcar_du_lvdsenc.o
+ rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS)	+= rcar_du_of.o \
+ 					   rcar_du_of_lvds_r8a7790.dtb.o \
+ 					   rcar_du_of_lvds_r8a7791.dtb.o \
+@@ -18,3 +16,4 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
+ 
+ obj-$(CONFIG_DRM_RCAR_DU)		+= rcar-du-drm.o
+ obj-$(CONFIG_DRM_RCAR_DW_HDMI)		+= rcar_dw_hdmi.o
++obj-$(CONFIG_DRM_RCAR_LVDS)		+= rcar_lvds.o
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index 6e02c762a557..06a3fbdd728a 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -29,6 +29,7 @@
+ 
+ #include "rcar_du_drv.h"
+ #include "rcar_du_kms.h"
++#include "rcar_du_of.h"
+ #include "rcar_du_regs.h"
+ 
+ /* -----------------------------------------------------------------------------
+@@ -74,7 +75,6 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
+ 			.port = 1,
+ 		},
+ 	},
+-	.num_lvds = 0,
+ };
+ 
+ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
+@@ -95,14 +95,13 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
+ 			.port = 1,
+ 		},
+ 	},
+-	.num_lvds = 0,
+ };
+ 
+ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.quirks = RCAR_DU_QUIRK_ALIGN_128B | RCAR_DU_QUIRK_LVDS_LANES,
++	.quirks = RCAR_DU_QUIRK_ALIGN_128B,
+ 	.num_crtcs = 3,
+ 	.routes = {
+ 		/*
+@@ -164,7 +163,6 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
+ 			.port = 1,
+ 		},
+ 	},
+-	.num_lvds = 0,
+ };
+ 
+ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
+@@ -186,7 +184,6 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
+ 			.port = 1,
+ 		},
+ 	},
+-	.num_lvds = 0,
+ };
+ 
+ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
+@@ -434,7 +431,19 @@ static struct platform_driver rcar_du_platform_driver = {
+ 	},
+ };
+ 
+-module_platform_driver(rcar_du_platform_driver);
++static int __init rcar_du_init(void)
++{
++	rcar_du_of_init(rcar_du_of_table);
++
++	return platform_driver_register(&rcar_du_platform_driver);
++}
++module_init(rcar_du_init);
++
++static void __exit rcar_du_exit(void)
++{
++	platform_driver_unregister(&rcar_du_platform_driver);
++}
++module_exit(rcar_du_exit);
+ 
+ MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
+ MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+index f400fde65a0c..5c7ec15818c7 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+@@ -26,14 +26,12 @@ struct device;
+ struct drm_device;
+ struct drm_fbdev_cma;
+ struct rcar_du_device;
+-struct rcar_du_lvdsenc;
+ 
+ #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK	(1 << 0)	/* Per-CRTC IRQ and clock */
+ #define RCAR_DU_FEATURE_EXT_CTRL_REGS	(1 << 1)	/* Has extended control registers */
+ #define RCAR_DU_FEATURE_VSP1_SOURCE	(1 << 2)	/* Has inputs from VSP1 */
+ 
+ #define RCAR_DU_QUIRK_ALIGN_128B	(1 << 0)	/* Align pitches to 128 bytes */
+-#define RCAR_DU_QUIRK_LVDS_LANES	(1 << 1)	/* LVDS lanes 1 and 3 inverted */
+ 
+ /*
+  * struct rcar_du_output_routing - Output routing specification
+@@ -70,7 +68,6 @@ struct rcar_du_device_info {
+ 
+ #define RCAR_DU_MAX_CRTCS		4
+ #define RCAR_DU_MAX_GROUPS		DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
+-#define RCAR_DU_MAX_LVDS		2
+ #define RCAR_DU_MAX_VSPS		4
+ 
+ struct rcar_du_device {
+@@ -96,8 +93,6 @@ struct rcar_du_device {
+ 
+ 	unsigned int dpad0_source;
+ 	unsigned int vspd1_sink;
+-
+-	struct rcar_du_lvdsenc *lvds[RCAR_DU_MAX_LVDS];
+ };
+ 
+ static inline bool rcar_du_has(struct rcar_du_device *rcdu,
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+index ba8d2804c1d1..f9c933d3bae6 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+@@ -21,134 +21,22 @@
+ #include "rcar_du_drv.h"
+ #include "rcar_du_encoder.h"
+ #include "rcar_du_kms.h"
+-#include "rcar_du_lvdscon.h"
+-#include "rcar_du_lvdsenc.h"
+ 
+ /* -----------------------------------------------------------------------------
+  * Encoder
+  */
+ 
+-static void rcar_du_encoder_disable(struct drm_encoder *encoder)
+-{
+-	struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
+-
+-	if (renc->connector && renc->connector->panel) {
+-		drm_panel_disable(renc->connector->panel);
+-		drm_panel_unprepare(renc->connector->panel);
+-	}
+-
+-	if (renc->lvds)
+-		rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, false);
+-}
+-
+-static void rcar_du_encoder_enable(struct drm_encoder *encoder)
+-{
+-	struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
+-
+-	if (renc->lvds)
+-		rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, true);
+-
+-	if (renc->connector && renc->connector->panel) {
+-		drm_panel_prepare(renc->connector->panel);
+-		drm_panel_enable(renc->connector->panel);
+-	}
+-}
+-
+-static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder,
+-					struct drm_crtc_state *crtc_state,
+-					struct drm_connector_state *conn_state)
+-{
+-	struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
+-	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+-	const struct drm_display_mode *mode = &crtc_state->mode;
+-	struct drm_connector *connector = conn_state->connector;
+-	struct drm_device *dev = encoder->dev;
+-
+-	/*
+-	 * Only panel-related encoder types require validation here, everything
+-	 * else is handled by the bridge drivers.
+-	 */
+-	if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
+-		const struct drm_display_mode *panel_mode;
+-
+-		if (list_empty(&connector->modes)) {
+-			dev_dbg(dev->dev, "encoder: empty modes list\n");
+-			return -EINVAL;
+-		}
+-
+-		panel_mode = list_first_entry(&connector->modes,
+-					      struct drm_display_mode, head);
+-
+-		/* We're not allowed to modify the resolution. */
+-		if (mode->hdisplay != panel_mode->hdisplay ||
+-		    mode->vdisplay != panel_mode->vdisplay)
+-			return -EINVAL;
+-
+-		/*
+-		 * The flat panel mode is fixed, just copy it to the adjusted
+-		 * mode.
+-		 */
+-		drm_mode_copy(adjusted_mode, panel_mode);
+-	}
+-
+-	if (renc->lvds)
+-		rcar_du_lvdsenc_atomic_check(renc->lvds, adjusted_mode);
+-
+-	return 0;
+-}
+-
+ static void rcar_du_encoder_mode_set(struct drm_encoder *encoder,
+ 				     struct drm_crtc_state *crtc_state,
+ 				     struct drm_connector_state *conn_state)
+ {
+ 	struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
+-	struct drm_display_info *info = &conn_state->connector->display_info;
+-	enum rcar_lvds_mode mode;
+ 
+ 	rcar_du_crtc_route_output(crtc_state->crtc, renc->output);
+-
+-	if (!renc->lvds) {
+-		/*
+-		 * The DU driver creates connectors only for the outputs of the
+-		 * internal LVDS encoders.
+-		 */
+-		renc->connector = NULL;
+-		return;
+-	}
+-
+-	renc->connector = to_rcar_connector(conn_state->connector);
+-
+-	if (!info->num_bus_formats || !info->bus_formats) {
+-		dev_err(encoder->dev->dev, "no LVDS bus format reported\n");
+-		return;
+-	}
+-
+-	switch (info->bus_formats[0]) {
+-	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+-	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+-		mode = RCAR_LVDS_MODE_JEIDA;
+-		break;
+-	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+-		mode = RCAR_LVDS_MODE_VESA;
+-		break;
+-	default:
+-		dev_err(encoder->dev->dev,
+-			"unsupported LVDS bus format 0x%04x\n",
+-			info->bus_formats[0]);
+-		return;
+-	}
+-
+-	if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
+-		mode |= RCAR_LVDS_MODE_MIRROR;
+-
+-	rcar_du_lvdsenc_set_mode(renc->lvds, mode);
+ }
+ 
+ static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
+ 	.atomic_mode_set = rcar_du_encoder_mode_set,
+-	.disable = rcar_du_encoder_disable,
+-	.enable = rcar_du_encoder_enable,
+-	.atomic_check = rcar_du_encoder_atomic_check,
+ };
+ 
+ static const struct drm_encoder_funcs encoder_funcs = {
+@@ -172,33 +60,14 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
+ 	renc->output = output;
+ 	encoder = rcar_encoder_to_drm_encoder(renc);
+ 
+-	switch (output) {
+-	case RCAR_DU_OUTPUT_LVDS0:
+-		renc->lvds = rcdu->lvds[0];
+-		break;
++	dev_dbg(rcdu->dev, "initializing encoder %pOF for output %u\n",
++		enc_node, output);
+ 
+-	case RCAR_DU_OUTPUT_LVDS1:
+-		renc->lvds = rcdu->lvds[1];
+-		break;
+-
+-	default:
+-		break;
+-	}
+-
+-	if (enc_node) {
+-		dev_dbg(rcdu->dev, "initializing encoder %pOF for output %u\n",
+-			enc_node, output);
+-
+-		/* Locate the DRM bridge from the encoder DT node. */
+-		bridge = of_drm_find_bridge(enc_node);
+-		if (!bridge) {
+-			ret = -EPROBE_DEFER;
+-			goto done;
+-		}
+-	} else {
+-		dev_dbg(rcdu->dev,
+-			"initializing internal encoder for output %u\n",
+-			output);
++	/* Locate the DRM bridge from the encoder DT node. */
++	bridge = of_drm_find_bridge(enc_node);
++	if (!bridge) {
++		ret = -EPROBE_DEFER;
++		goto done;
+ 	}
+ 
+ 	ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs,
+@@ -208,28 +77,14 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
+ 
+ 	drm_encoder_helper_add(encoder, &encoder_helper_funcs);
+ 
+-	if (bridge) {
+-		/*
+-		 * Attach the bridge to the encoder. The bridge will create the
+-		 * connector.
+-		 */
+-		ret = drm_bridge_attach(encoder, bridge, NULL);
+-		if (ret) {
+-			drm_encoder_cleanup(encoder);
+-			return ret;
+-		}
+-	} else {
+-		/* There's no bridge, create the connector manually. */
+-		switch (output) {
+-		case RCAR_DU_OUTPUT_LVDS0:
+-		case RCAR_DU_OUTPUT_LVDS1:
+-			ret = rcar_du_lvds_connector_init(rcdu, renc, con_node);
+-			break;
+-
+-		default:
+-			ret = -EINVAL;
+-			break;
+-		}
++	/*
++	 * Attach the bridge to the encoder. The bridge will create the
++	 * connector.
++	 */
++	ret = drm_bridge_attach(encoder, bridge, NULL);
++	if (ret) {
++		drm_encoder_cleanup(encoder);
++		return ret;
+ 	}
+ 
+ done:
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
+index 5422fa4df272..2d2abcacd169 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
+@@ -19,13 +19,10 @@
+ 
+ struct drm_panel;
+ struct rcar_du_device;
+-struct rcar_du_lvdsenc;
+ 
+ struct rcar_du_encoder {
+ 	struct drm_encoder base;
+ 	enum rcar_du_output output;
+-	struct rcar_du_connector *connector;
+-	struct rcar_du_lvdsenc *lvds;
+ };
+ 
+ #define to_rcar_encoder(e) \
+@@ -33,15 +30,6 @@ struct rcar_du_encoder {
+ 
+ #define rcar_encoder_to_drm_encoder(e)	(&(e)->base)
+ 
+-struct rcar_du_connector {
+-	struct drm_connector connector;
+-	struct rcar_du_encoder *encoder;
+-	struct drm_panel *panel;
+-};
+-
+-#define to_rcar_connector(c) \
+-	container_of(c, struct rcar_du_connector, connector)
+-
+ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
+ 			 enum rcar_du_output output,
+ 			 struct device_node *enc_node,
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index 566d1a948c8f..0329b354bfa0 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -27,7 +27,6 @@
+ #include "rcar_du_drv.h"
+ #include "rcar_du_encoder.h"
+ #include "rcar_du_kms.h"
+-#include "rcar_du_lvdsenc.h"
+ #include "rcar_du_regs.h"
+ #include "rcar_du_vsp.h"
+ 
+@@ -341,11 +340,10 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
+ 	of_node_put(entity_ep_node);
+ 
+ 	if (!encoder) {
+-		/*
+-		 * If no encoder has been found the entity must be the
+-		 * connector.
+-		 */
+-		connector = entity;
++		dev_warn(rcdu->dev,
++			 "no encoder found for endpoint %pOF, skipping\n",
++			 ep->local_node);
++		return -ENODEV;
+ 	}
+ 
+ 	ret = rcar_du_encoder_init(rcdu, output, encoder, connector);
+@@ -595,10 +593,6 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	}
+ 
+ 	/* Initialize the encoders. */
+-	ret = rcar_du_lvdsenc_init(rcdu);
+-	if (ret < 0)
+-		return ret;
+-
+ 	ret = rcar_du_encoders_init(rcdu);
+ 	if (ret < 0)
+ 		return ret;
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+deleted file mode 100644
+index e96f2df0c305..000000000000
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
++++ /dev/null
+@@ -1,93 +0,0 @@
+-/*
+- * rcar_du_lvdscon.c  --  R-Car Display Unit LVDS Connector
+- *
+- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+- *
+- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#include <drm/drmP.h>
+-#include <drm/drm_atomic_helper.h>
+-#include <drm/drm_crtc.h>
+-#include <drm/drm_crtc_helper.h>
+-#include <drm/drm_panel.h>
+-
+-#include <video/display_timing.h>
+-#include <video/of_display_timing.h>
+-#include <video/videomode.h>
+-
+-#include "rcar_du_drv.h"
+-#include "rcar_du_encoder.h"
+-#include "rcar_du_kms.h"
+-#include "rcar_du_lvdscon.h"
+-
+-static int rcar_du_lvds_connector_get_modes(struct drm_connector *connector)
+-{
+-	struct rcar_du_connector *rcon = to_rcar_connector(connector);
+-
+-	return drm_panel_get_modes(rcon->panel);
+-}
+-
+-static const struct drm_connector_helper_funcs connector_helper_funcs = {
+-	.get_modes = rcar_du_lvds_connector_get_modes,
+-};
+-
+-static void rcar_du_lvds_connector_destroy(struct drm_connector *connector)
+-{
+-	struct rcar_du_connector *rcon = to_rcar_connector(connector);
+-
+-	drm_panel_detach(rcon->panel);
+-	drm_connector_cleanup(connector);
+-}
+-
+-static const struct drm_connector_funcs connector_funcs = {
+-	.reset = drm_atomic_helper_connector_reset,
+-	.fill_modes = drm_helper_probe_single_connector_modes,
+-	.destroy = rcar_du_lvds_connector_destroy,
+-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+-};
+-
+-int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
+-				struct rcar_du_encoder *renc,
+-				const struct device_node *np)
+-{
+-	struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc);
+-	struct rcar_du_connector *rcon;
+-	struct drm_connector *connector;
+-	int ret;
+-
+-	rcon = devm_kzalloc(rcdu->dev, sizeof(*rcon), GFP_KERNEL);
+-	if (rcon == NULL)
+-		return -ENOMEM;
+-
+-	connector = &rcon->connector;
+-
+-	rcon->panel = of_drm_find_panel(np);
+-	if (!rcon->panel)
+-		return -EPROBE_DEFER;
+-
+-	ret = drm_connector_init(rcdu->ddev, connector, &connector_funcs,
+-				 DRM_MODE_CONNECTOR_LVDS);
+-	if (ret < 0)
+-		return ret;
+-
+-	drm_connector_helper_add(connector, &connector_helper_funcs);
+-
+-	ret = drm_mode_connector_attach_encoder(connector, encoder);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = drm_panel_attach(rcon->panel, connector);
+-	if (ret < 0)
+-		return ret;
+-
+-	rcon->encoder = renc;
+-
+-	return 0;
+-}
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.h b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.h
+deleted file mode 100644
+index 639071dd235c..000000000000
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.h
++++ /dev/null
+@@ -1,24 +0,0 @@
+-/*
+- * rcar_du_lvdscon.h  --  R-Car Display Unit LVDS Connector
+- *
+- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+- *
+- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef __RCAR_DU_LVDSCON_H__
+-#define __RCAR_DU_LVDSCON_H__
+-
+-struct rcar_du_device;
+-struct rcar_du_encoder;
+-
+-int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
+-				struct rcar_du_encoder *renc,
+-				const struct device_node *np);
+-
+-#endif /* __RCAR_DU_LVDSCON_H__ */
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+deleted file mode 100644
+index 4defa8123eb2..000000000000
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
++++ /dev/null
+@@ -1,238 +0,0 @@
+-/*
+- * rcar_du_lvdsenc.c  --  R-Car Display Unit LVDS Encoder
+- *
+- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+- *
+- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <linux/io.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-
+-#include "rcar_du_drv.h"
+-#include "rcar_du_encoder.h"
+-#include "rcar_du_lvdsenc.h"
+-#include "rcar_lvds_regs.h"
+-
+-struct rcar_du_lvdsenc {
+-	struct rcar_du_device *dev;
+-
+-	unsigned int index;
+-	void __iomem *mmio;
+-	struct clk *clock;
+-	bool enabled;
+-
+-	enum rcar_lvds_input input;
+-	enum rcar_lvds_mode mode;
+-};
+-
+-static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
+-{
+-	iowrite32(data, lvds->mmio + reg);
+-}
+-
+-static u32 rcar_lvds_lvdpllcr_gen2(unsigned int freq)
+-{
+-	if (freq < 39000)
+-		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
+-	else if (freq < 61000)
+-		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
+-	else if (freq < 121000)
+-		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
+-	else
+-		return LVDPLLCR_PLLDLYCNT_150M;
+-}
+-
+-static u32 rcar_lvds_lvdpllcr_gen3(unsigned int freq)
+-{
+-	if (freq < 42000)
+-		return LVDPLLCR_PLLDIVCNT_42M;
+-	else if (freq < 85000)
+-		return LVDPLLCR_PLLDIVCNT_85M;
+-	else if (freq < 128000)
+-		return LVDPLLCR_PLLDIVCNT_128M;
+-	else
+-		return LVDPLLCR_PLLDIVCNT_148M;
+-}
+-
+-static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
+-				 struct rcar_du_crtc *rcrtc)
+-{
+-	const struct drm_display_mode *mode = &rcrtc->crtc.mode;
+-	u32 lvdpllcr;
+-	u32 lvdhcr;
+-	u32 lvdcr0;
+-	int ret;
+-
+-	if (lvds->enabled)
+-		return 0;
+-
+-	ret = clk_prepare_enable(lvds->clock);
+-	if (ret < 0)
+-		return ret;
+-
+-	/*
+-	 * Hardcode the channels and control signals routing for now.
+-	 *
+-	 * HSYNC -> CTRL0
+-	 * VSYNC -> CTRL1
+-	 * DISP  -> CTRL2
+-	 * 0     -> CTRL3
+-	 */
+-	rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
+-			LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
+-			LVDCTRCR_CTR0SEL_HSYNC);
+-
+-	if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES))
+-		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
+-		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
+-	else
+-		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
+-		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
+-
+-	rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
+-
+-	/* PLL clock configuration. */
+-	if (lvds->dev->info->gen < 3)
+-		lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
+-	else
+-		lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
+-	rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
+-
+-	/* Set the LVDS mode and select the input. */
+-	lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
+-	if (rcrtc->index == 2)
+-		lvdcr0 |= LVDCR0_DUSEL;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	/* Turn all the channels on. */
+-	rcar_lvds_write(lvds, LVDCR1,
+-			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
+-			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
+-
+-	if (lvds->dev->info->gen < 3) {
+-		/* Enable LVDS operation and turn the bias circuitry on. */
+-		lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
+-		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-	}
+-
+-	/* Turn the PLL on. */
+-	lvdcr0 |= LVDCR0_PLLON;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	if (lvds->dev->info->gen > 2) {
+-		/* Set LVDS normal mode. */
+-		lvdcr0 |= LVDCR0_PWD;
+-		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-	}
+-
+-	/* Wait for the startup delay. */
+-	usleep_range(100, 150);
+-
+-	/* Turn the output on. */
+-	lvdcr0 |= LVDCR0_LVRES;
+-	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+-
+-	lvds->enabled = true;
+-
+-	return 0;
+-}
+-
+-static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
+-{
+-	if (!lvds->enabled)
+-		return;
+-
+-	rcar_lvds_write(lvds, LVDCR0, 0);
+-	rcar_lvds_write(lvds, LVDCR1, 0);
+-
+-	clk_disable_unprepare(lvds->clock);
+-
+-	lvds->enabled = false;
+-}
+-
+-int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
+-			   bool enable)
+-{
+-	if (!enable) {
+-		rcar_du_lvdsenc_stop(lvds);
+-		return 0;
+-	} else if (crtc) {
+-		struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+-		return rcar_du_lvdsenc_start(lvds, rcrtc);
+-	} else
+-		return -EINVAL;
+-}
+-
+-void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
+-				  struct drm_display_mode *mode)
+-{
+-	/*
+-	 * The internal LVDS encoder has a restricted clock frequency operating
+-	 * range (31MHz to 148.5MHz). Clamp the clock accordingly.
+-	 */
+-	mode->clock = clamp(mode->clock, 31000, 148500);
+-}
+-
+-void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
+-			      enum rcar_lvds_mode mode)
+-{
+-	lvds->mode = mode;
+-}
+-
+-static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
+-					 struct platform_device *pdev)
+-{
+-	struct resource *mem;
+-	char name[7];
+-
+-	sprintf(name, "lvds.%u", lvds->index);
+-
+-	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+-	lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
+-	if (IS_ERR(lvds->mmio))
+-		return PTR_ERR(lvds->mmio);
+-
+-	lvds->clock = devm_clk_get(&pdev->dev, name);
+-	if (IS_ERR(lvds->clock)) {
+-		dev_err(&pdev->dev, "failed to get clock for %s\n", name);
+-		return PTR_ERR(lvds->clock);
+-	}
+-
+-	return 0;
+-}
+-
+-int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
+-{
+-	struct platform_device *pdev = to_platform_device(rcdu->dev);
+-	struct rcar_du_lvdsenc *lvds;
+-	unsigned int i;
+-	int ret;
+-
+-	for (i = 0; i < rcdu->info->num_lvds; ++i) {
+-		lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
+-		if (lvds == NULL)
+-			return -ENOMEM;
+-
+-		lvds->dev = rcdu;
+-		lvds->index = i;
+-		lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
+-		lvds->enabled = false;
+-
+-		ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
+-		if (ret < 0)
+-			return ret;
+-
+-		rcdu->lvds[i] = lvds;
+-	}
+-
+-	return 0;
+-}
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
+deleted file mode 100644
+index 7218ac89333e..000000000000
+--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
++++ /dev/null
+@@ -1,64 +0,0 @@
+-/*
+- * rcar_du_lvdsenc.h  --  R-Car Display Unit LVDS Encoder
+- *
+- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+- *
+- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef __RCAR_DU_LVDSENC_H__
+-#define __RCAR_DU_LVDSENC_H__
+-
+-#include <linux/io.h>
+-#include <linux/module.h>
+-
+-struct rcar_drm_crtc;
+-struct rcar_du_lvdsenc;
+-
+-enum rcar_lvds_input {
+-	RCAR_LVDS_INPUT_DU0,
+-	RCAR_LVDS_INPUT_DU1,
+-	RCAR_LVDS_INPUT_DU2,
+-};
+-
+-/* Keep in sync with the LVDCR0.LVMD hardware register values. */
+-enum rcar_lvds_mode {
+-	RCAR_LVDS_MODE_JEIDA = 0,
+-	RCAR_LVDS_MODE_MIRROR = 1,
+-	RCAR_LVDS_MODE_VESA = 4,
+-};
+-
+-#if IS_ENABLED(CONFIG_DRM_RCAR_LVDS)
+-int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu);
+-void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
+-			      enum rcar_lvds_mode mode);
+-int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
+-			   struct drm_crtc *crtc, bool enable);
+-void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
+-				  struct drm_display_mode *mode);
+-#else
+-static inline int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
+-{
+-	return 0;
+-}
+-static inline void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
+-					    enum rcar_lvds_mode mode)
+-{
+-}
+-static inline int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
+-					 struct drm_crtc *crtc, bool enable)
+-{
+-	return 0;
+-}
+-static inline void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
+-						struct drm_display_mode *mode)
+-{
+-}
+-#endif
+-
+-#endif /* __RCAR_DU_LVDSENC_H__ */
+diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+new file mode 100644
+index 000000000000..1247e26a0559
+--- /dev/null
++++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+@@ -0,0 +1,524 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rcar_lvds.c  --  R-Car LVDS Encoder
++ *
++ * Copyright (C) 2013-2018 Renesas Electronics Corporation
++ *
++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_graph.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_bridge.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_panel.h>
++
++#include "rcar_lvds_regs.h"
++
++/* Keep in sync with the LVDCR0.LVMD hardware register values. */
++enum rcar_lvds_mode {
++	RCAR_LVDS_MODE_JEIDA = 0,
++	RCAR_LVDS_MODE_MIRROR = 1,
++	RCAR_LVDS_MODE_VESA = 4,
++};
++
++#define RCAR_LVDS_QUIRK_LANES	(1 << 0)	/* LVDS lanes 1 and 3 inverted */
++
++struct rcar_lvds_device_info {
++	unsigned int gen;
++	unsigned int quirks;
++};
++
++struct rcar_lvds {
++	struct device *dev;
++	const struct rcar_lvds_device_info *info;
++
++	struct drm_bridge bridge;
++
++	struct drm_bridge *next_bridge;
++	struct drm_connector connector;
++	struct drm_panel *panel;
++
++	void __iomem *mmio;
++	struct clk *clock;
++	bool enabled;
++
++	struct drm_display_mode display_mode;
++	enum rcar_lvds_mode mode;
++};
++
++#define bridge_to_rcar_lvds(bridge) \
++	container_of(bridge, struct rcar_lvds, bridge)
++
++#define connector_to_rcar_lvds(connector) \
++	container_of(connector, struct rcar_lvds, connector)
++
++static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
++{
++	iowrite32(data, lvds->mmio + reg);
++}
++
++/* -----------------------------------------------------------------------------
++ * Connector & Panel
++ */
++
++static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
++{
++	struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
++
++	return drm_panel_get_modes(lvds->panel);
++}
++
++static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
++					    struct drm_connector_state *state)
++{
++	struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
++	const struct drm_display_mode *panel_mode;
++	struct drm_crtc_state *crtc_state;
++
++	if (list_empty(&connector->modes)) {
++		dev_dbg(lvds->dev, "connector: empty modes list\n");
++		return -EINVAL;
++	}
++
++	panel_mode = list_first_entry(&connector->modes,
++				      struct drm_display_mode, head);
++
++	/* We're not allowed to modify the resolution. */
++	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
++	if (IS_ERR(crtc_state))
++		return PTR_ERR(crtc_state);
++
++	if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
++	    crtc_state->mode.vdisplay != panel_mode->vdisplay)
++		return -EINVAL;
++
++	/* The flat panel mode is fixed, just copy it to the adjusted mode. */
++	drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
++
++	return 0;
++}
++
++static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
++	.get_modes = rcar_lvds_connector_get_modes,
++	.atomic_check = rcar_lvds_connector_atomic_check,
++};
++
++static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
++	.reset = drm_atomic_helper_connector_reset,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.destroy = drm_connector_cleanup,
++	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
++};
++
++/* -----------------------------------------------------------------------------
++ * Bridge
++ */
++
++static u32 rcar_lvds_lvdpllcr_gen2(unsigned int freq)
++{
++	if (freq < 39000)
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
++	else if (freq < 61000)
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
++	else if (freq < 121000)
++		return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
++	else
++		return LVDPLLCR_PLLDLYCNT_150M;
++}
++
++static u32 rcar_lvds_lvdpllcr_gen3(unsigned int freq)
++{
++	if (freq < 42000)
++		return LVDPLLCR_PLLDIVCNT_42M;
++	else if (freq < 85000)
++		return LVDPLLCR_PLLDIVCNT_85M;
++	else if (freq < 128000)
++		return LVDPLLCR_PLLDIVCNT_128M;
++	else
++		return LVDPLLCR_PLLDIVCNT_148M;
++}
++
++static void rcar_lvds_enable(struct drm_bridge *bridge)
++{
++	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
++	const struct drm_display_mode *mode = &lvds->display_mode;
++	/*
++	 * FIXME: We should really retrieve the CRTC through the state, but how
++	 * do we get a state pointer?
++	 */
++	struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
++	u32 lvdpllcr;
++	u32 lvdhcr;
++	u32 lvdcr0;
++	int ret;
++
++	WARN_ON(lvds->enabled);
++
++	ret = clk_prepare_enable(lvds->clock);
++	if (ret < 0)
++		return;
++
++	/*
++	 * Hardcode the channels and control signals routing for now.
++	 *
++	 * HSYNC -> CTRL0
++	 * VSYNC -> CTRL1
++	 * DISP  -> CTRL2
++	 * 0     -> CTRL3
++	 */
++	rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
++			LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
++			LVDCTRCR_CTR0SEL_HSYNC);
++
++	if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
++		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
++		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
++	else
++		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
++		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
++
++	rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
++
++	/* PLL clock configuration. */
++	if (lvds->info->gen < 3)
++		lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
++	else
++		lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
++	rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
++
++	/* Set the LVDS mode and select the input. */
++	lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
++	if (drm_crtc_index(crtc) == 2)
++		lvdcr0 |= LVDCR0_DUSEL;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++
++	/* Turn all the channels on. */
++	rcar_lvds_write(lvds, LVDCR1,
++			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
++			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
++
++	if (lvds->info->gen < 3) {
++		/* Enable LVDS operation and turn the bias circuitry on. */
++		lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
++		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++	}
++
++	/* Turn the PLL on. */
++	lvdcr0 |= LVDCR0_PLLON;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++
++	if (lvds->info->gen > 2) {
++		/* Set LVDS normal mode. */
++		lvdcr0 |= LVDCR0_PWD;
++		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++	}
++
++	/* Wait for the startup delay. */
++	usleep_range(100, 150);
++
++	/* Turn the output on. */
++	lvdcr0 |= LVDCR0_LVRES;
++	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++
++	if (lvds->panel) {
++		drm_panel_prepare(lvds->panel);
++		drm_panel_enable(lvds->panel);
++	}
++
++	lvds->enabled = true;
++}
++
++static void rcar_lvds_disable(struct drm_bridge *bridge)
++{
++	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
++
++	WARN_ON(!lvds->enabled);
++
++	if (lvds->panel) {
++		drm_panel_disable(lvds->panel);
++		drm_panel_unprepare(lvds->panel);
++	}
++
++	rcar_lvds_write(lvds, LVDCR0, 0);
++	rcar_lvds_write(lvds, LVDCR1, 0);
++
++	clk_disable_unprepare(lvds->clock);
++
++	lvds->enabled = false;
++}
++
++static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
++				 const struct drm_display_mode *mode,
++				 struct drm_display_mode *adjusted_mode)
++{
++	/*
++	 * The internal LVDS encoder has a restricted clock frequency operating
++	 * range (31MHz to 148.5MHz). Clamp the clock accordingly.
++	 */
++	adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
++
++	return true;
++}
++
++static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
++{
++	struct drm_display_info *info = &lvds->connector.display_info;
++	enum rcar_lvds_mode mode;
++
++	/*
++	 * There is no API yet to retrieve LVDS mode from a bridge, only panels
++	 * are supported.
++	 */
++	if (!lvds->panel)
++		return;
++
++	if (!info->num_bus_formats || !info->bus_formats) {
++		dev_err(lvds->dev, "no LVDS bus format reported\n");
++		return;
++	}
++
++	switch (info->bus_formats[0]) {
++	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
++	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
++		mode = RCAR_LVDS_MODE_JEIDA;
++		break;
++	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
++		mode = RCAR_LVDS_MODE_VESA;
++		break;
++	default:
++		dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
++			info->bus_formats[0]);
++		return;
++	}
++
++	if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
++		mode |= RCAR_LVDS_MODE_MIRROR;
++
++	lvds->mode = mode;
++}
++
++static void rcar_lvds_mode_set(struct drm_bridge *bridge,
++			       struct drm_display_mode *mode,
++			       struct drm_display_mode *adjusted_mode)
++{
++	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
++
++	WARN_ON(lvds->enabled);
++
++	lvds->display_mode = *adjusted_mode;
++
++	rcar_lvds_get_lvds_mode(lvds);
++}
++
++static int rcar_lvds_attach(struct drm_bridge *bridge)
++{
++	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
++	struct drm_connector *connector = &lvds->connector;
++	struct drm_encoder *encoder = bridge->encoder;
++	int ret;
++
++	/* If we have a next bridge just attach it. */
++	if (lvds->next_bridge)
++		return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
++					 bridge);
++
++	/* Otherwise we have a panel, create a connector. */
++	ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
++				 DRM_MODE_CONNECTOR_LVDS);
++	if (ret < 0)
++		return ret;
++
++	drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
++
++	ret = drm_mode_connector_attach_encoder(connector, encoder);
++	if (ret < 0)
++		return ret;
++
++	return drm_panel_attach(lvds->panel, connector);
++}
++
++static void rcar_lvds_detach(struct drm_bridge *bridge)
++{
++	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
++
++	if (lvds->panel)
++		drm_panel_detach(lvds->panel);
++}
++
++static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
++	.attach = rcar_lvds_attach,
++	.detach = rcar_lvds_detach,
++	.enable = rcar_lvds_enable,
++	.disable = rcar_lvds_disable,
++	.mode_fixup = rcar_lvds_mode_fixup,
++	.mode_set = rcar_lvds_mode_set,
++};
++
++/* -----------------------------------------------------------------------------
++ * Probe & Remove
++ */
++
++static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
++{
++	struct device_node *local_output = NULL;
++	struct device_node *remote_input = NULL;
++	struct device_node *remote = NULL;
++	struct device_node *node;
++	bool is_bridge = false;
++	int ret = 0;
++
++	local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
++	if (!local_output) {
++		dev_dbg(lvds->dev, "unconnected port@1\n");
++		return -ENODEV;
++	}
++
++	/*
++	 * Locate the connected entity and infer its type from the number of
++	 * endpoints.
++	 */
++	remote = of_graph_get_remote_port_parent(local_output);
++	if (!remote) {
++		dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
++		ret = -ENODEV;
++		goto done;
++	}
++
++	if (!of_device_is_available(remote)) {
++		dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
++			remote);
++		ret = -ENODEV;
++		goto done;
++	}
++
++	remote_input = of_graph_get_remote_endpoint(local_output);
++
++	for_each_endpoint_of_node(remote, node) {
++		if (node != remote_input) {
++			/*
++			 * We've found one endpoint other than the input, this
++			 * must be a bridge.
++			 */
++			is_bridge = true;
++			of_node_put(node);
++			break;
++		}
++	}
++
++	if (is_bridge) {
++		lvds->next_bridge = of_drm_find_bridge(remote);
++		if (!lvds->next_bridge)
++			ret = -EPROBE_DEFER;
++	} else {
++		lvds->panel = of_drm_find_panel(remote);
++		if (!lvds->panel)
++			ret = -EPROBE_DEFER;
++	}
++
++done:
++	of_node_put(local_output);
++	of_node_put(remote_input);
++	of_node_put(remote);
++
++	return ret;
++}
++
++static int rcar_lvds_probe(struct platform_device *pdev)
++{
++	struct rcar_lvds *lvds;
++	struct resource *mem;
++	int ret;
++
++	lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
++	if (lvds == NULL)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, lvds);
++
++	lvds->dev = &pdev->dev;
++	lvds->info = of_device_get_match_data(&pdev->dev);
++	lvds->enabled = false;
++
++	ret = rcar_lvds_parse_dt(lvds);
++	if (ret < 0)
++		return ret;
++
++	lvds->bridge.driver_private = lvds;
++	lvds->bridge.funcs = &rcar_lvds_bridge_ops;
++	lvds->bridge.of_node = pdev->dev.of_node;
++
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
++	if (IS_ERR(lvds->mmio))
++		return PTR_ERR(lvds->mmio);
++
++	lvds->clock = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(lvds->clock)) {
++		dev_err(&pdev->dev, "failed to get clock\n");
++		return PTR_ERR(lvds->clock);
++	}
++
++	drm_bridge_add(&lvds->bridge);
++
++	return 0;
++}
++
++static int rcar_lvds_remove(struct platform_device *pdev)
++{
++	struct rcar_lvds *lvds = platform_get_drvdata(pdev);
++
++	drm_bridge_remove(&lvds->bridge);
++
++	return 0;
++}
++
++static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
++	.gen = 2,
++};
++
++static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
++	.gen = 2,
++	.quirks = RCAR_LVDS_QUIRK_LANES,
++};
++
++static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
++	.gen = 3,
++};
++
++static const struct of_device_id rcar_lvds_of_table[] = {
++	{ .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
++	{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
++	{ .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
++	{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
++	{ .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
++	{ .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
++
++static struct platform_driver rcar_lvds_platform_driver = {
++	.probe		= rcar_lvds_probe,
++	.remove		= rcar_lvds_remove,
++	.driver		= {
++		.name	= "rcar-lvds",
++		.of_match_table = rcar_lvds_of_table,
++	},
++};
++
++module_platform_driver(rcar_lvds_platform_driver);
++
++MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
++MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.19.0
+
diff --git a/patches/1050-dt-bindings-display-renesas-du-Document-R8A77970-bin.patch b/patches/1050-dt-bindings-display-renesas-du-Document-R8A77970-bin.patch
new file mode 100644
index 00000000000000..3a7c0d6c6d2fb4
--- /dev/null
+++ b/patches/1050-dt-bindings-display-renesas-du-Document-R8A77970-bin.patch
@@ -0,0 +1,42 @@
+From 3090ff81e8932dbb0d819c5d6e1edb90d649ac39 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 19 Jan 2018 00:05:58 +0300
+Subject: [PATCH 1050/1795] dt-bindings: display: renesas: du: Document
+ R8A77970 bindings
+
+Document the R-Car V3M (R8A77970) SoC in the R-Car DU bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 88fb4a0e07d1fd3e3198b892fd89292091f6bd35)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index e79cf9b0ad38..6067ab3c150b 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -13,6 +13,7 @@ Required Properties:
+     - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
+     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
+     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
++    - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
+ 
+   - reg: the memory-mapped I/O registers base address and length
+ 
+@@ -57,6 +58,7 @@ corresponding to each DU output.
+  R8A7794 (R-Car E2)   DPAD 0         DPAD 1         -              -
+  R8A7795 (R-Car H3)   DPAD 0         HDMI 0         HDMI 1         LVDS 0
+  R8A7796 (R-Car M3-W) DPAD 0         HDMI 0         LVDS 0         -
++ R8A77970 (R-Car V3M) DPAD 0         LVDS 0         -              -
+ 
+ 
+ Example: R8A7795 (R-Car H3) ES2.0 DU
+-- 
+2.19.0
+
diff --git a/patches/1051-dt-bindings-display-renesas-lvds-Document-R8A77970-b.patch b/patches/1051-dt-bindings-display-renesas-lvds-Document-R8A77970-b.patch
new file mode 100644
index 00000000000000..36c9c306a1b292
--- /dev/null
+++ b/patches/1051-dt-bindings-display-renesas-lvds-Document-R8A77970-b.patch
@@ -0,0 +1,34 @@
+From e1a2ebf46010c5879be461e8f878c3cf56498b59 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 19 Jan 2018 21:29:20 +0300
+Subject: [PATCH 1051/1795] dt-bindings: display: renesas: lvds: Document
+ R8A77970 bindings
+
+Document the R-Car V3M (R8A77970) SoC in the R-Car LVDS bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 15c12c17c573098a4829e3a8f466ec0b275de561)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/display/bridge/renesas,lvds.txt          | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+index af45ba9d8f90..2b48a4348c15 100644
+--- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
++++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+@@ -13,6 +13,7 @@ Required properties:
+   - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
+   - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
+   - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
++  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
+ 
+ - reg: Base address and length for the memory-mapped registers
+ - clocks: A phandle + clock-specifier pair for the functional clock
+-- 
+2.19.0
+
diff --git a/patches/1052-drm-rcar-du-Add-R8A77970-support.patch b/patches/1052-drm-rcar-du-Add-R8A77970-support.patch
new file mode 100644
index 00000000000000..9d582e85cbe920
--- /dev/null
+++ b/patches/1052-drm-rcar-du-Add-R8A77970-support.patch
@@ -0,0 +1,59 @@
+From ab68528323b711ad870747bea8524c7c84a5049d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 19 Jan 2018 00:05:59 +0300
+Subject: [PATCH 1052/1795] drm: rcar-du: Add R8A77970 support
+
+Add support for the R-Car V3M (R8A77970) SoC to the R-Car DU driver.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit fe9ac01324a40e2aaf5782a1fb7038247a89c585)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index 06a3fbdd728a..3917d839c04c 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -246,6 +246,26 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+ 	.dpll_ch =  BIT(1),
+ };
+ 
++static const struct rcar_du_device_info rcar_du_r8a77970_info = {
++	.gen = 3,
++	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
++		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
++		  | RCAR_DU_FEATURE_VSP1_SOURCE,
++	.num_crtcs = 1,
++	.routes = {
++		/* R8A77970 has one RGB output and one LVDS output. */
++		[RCAR_DU_OUTPUT_DPAD0] = {
++			.possible_crtcs = BIT(0),
++			.port = 0,
++		},
++		[RCAR_DU_OUTPUT_LVDS0] = {
++			.possible_crtcs = BIT(0),
++			.port = 1,
++		},
++	},
++	.num_lvds = 1,
++};
++
+ static const struct of_device_id rcar_du_of_table[] = {
+ 	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
+ 	{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
+@@ -257,6 +277,7 @@ static const struct of_device_id rcar_du_of_table[] = {
+ 	{ .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
+ 	{ .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
+ 	{ .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
++	{ .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
+ 	{ }
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1053-drm-rcar-du-lvds-Add-R8A77970-support.patch b/patches/1053-drm-rcar-du-lvds-Add-R8A77970-support.patch
new file mode 100644
index 00000000000000..02ac70f5336147
--- /dev/null
+++ b/patches/1053-drm-rcar-du-lvds-Add-R8A77970-support.patch
@@ -0,0 +1,91 @@
+From 67fabac84378233416b0de6db8bf5f9c08f33360 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 1 Mar 2018 21:10:16 +0300
+Subject: [PATCH 1053/1795] drm: rcar-du: lvds: Add R8A77970 support
+
+Add support for the R-Car V3M (R8A77970) SoC to the LVDS encoder driver.
+Note that there are some differences with the other R-Car gen3 SoCs, e.g.
+LVDPLLCR has the same layout as in the R-Car gen2 SoCs.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit b6eb7102ad6dc7ae35c23b517809f5ae5aa5ccdd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_lvds.c | 20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+index 1247e26a0559..3d2d3bbd1342 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
++++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+@@ -32,6 +32,9 @@ enum rcar_lvds_mode {
+ };
+ 
+ #define RCAR_LVDS_QUIRK_LANES	(1 << 0)	/* LVDS lanes 1 and 3 inverted */
++#define RCAR_LVDS_QUIRK_GEN2_PLLCR (1 << 1)	/* LVDPLLCR has gen2 layout */
++#define RCAR_LVDS_QUIRK_GEN3_LVEN (1 << 2)	/* LVEN bit needs to be set */
++						/* on R8A77970/R8A7799x */
+ 
+ struct rcar_lvds_device_info {
+ 	unsigned int gen;
+@@ -191,7 +194,7 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
+ 	rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
+ 
+ 	/* PLL clock configuration. */
+-	if (lvds->info->gen < 3)
++	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN2_PLLCR)
+ 		lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
+ 	else
+ 		lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
+@@ -224,6 +227,12 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
+ 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+ 	}
+ 
++	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
++		/* Turn on the LVDS PHY. */
++		lvdcr0 |= LVDCR0_LVEN;
++		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
++	}
++
+ 	/* Wait for the startup delay. */
+ 	usleep_range(100, 150);
+ 
+@@ -485,17 +494,23 @@ static int rcar_lvds_remove(struct platform_device *pdev)
+ 
+ static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
+ 	.gen = 2,
++	.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR,
+ };
+ 
+ static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
+ 	.gen = 2,
+-	.quirks = RCAR_LVDS_QUIRK_LANES,
++	.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_LANES,
+ };
+ 
+ static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
+ 	.gen = 3,
+ };
+ 
++static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
++	.gen = 3,
++	.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN,
++};
++
+ static const struct of_device_id rcar_lvds_of_table[] = {
+ 	{ .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
+ 	{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
+@@ -503,6 +518,7 @@ static const struct of_device_id rcar_lvds_of_table[] = {
+ 	{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
+ 	{ .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
+ 	{ .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
++	{ .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
+ 	{ }
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1054-dt-bindings-display-renesas-du-Document-r8a77995-bin.patch b/patches/1054-dt-bindings-display-renesas-du-Document-r8a77995-bin.patch
new file mode 100644
index 00000000000000..4c1663ea3aeb88
--- /dev/null
+++ b/patches/1054-dt-bindings-display-renesas-du-Document-r8a77995-bin.patch
@@ -0,0 +1,41 @@
+From 400c813f05f377cfd696d68e7e745ba5a98da586 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 15 Feb 2018 08:38:17 +0000
+Subject: [PATCH 1054/1795] dt-bindings: display: renesas: du: Document
+ r8a77995 bindings
+
+Document the D3 (r8a77995) SoC in the R-Car DU bindings.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit b378b3561dee6413ee9fdd70a08e17ebe9afc073)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index 6067ab3c150b..c9cd17f99702 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -14,6 +14,7 @@ Required Properties:
+     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
+     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+     - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
++    - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
+ 
+   - reg: the memory-mapped I/O registers base address and length
+ 
+@@ -59,6 +60,7 @@ corresponding to each DU output.
+  R8A7795 (R-Car H3)   DPAD 0         HDMI 0         HDMI 1         LVDS 0
+  R8A7796 (R-Car M3-W) DPAD 0         HDMI 0         LVDS 0         -
+  R8A77970 (R-Car V3M) DPAD 0         LVDS 0         -              -
++ R8A77995 (R-Car D3)  DPAD 0         LVDS 0         LVDS 1         -
+ 
+ 
+ Example: R8A7795 (R-Car H3) ES2.0 DU
+-- 
+2.19.0
+
diff --git a/patches/1055-dt-bindings-display-renesas-lvds-Document-r8a77995-b.patch b/patches/1055-dt-bindings-display-renesas-lvds-Document-r8a77995-b.patch
new file mode 100644
index 00000000000000..88ed3bd346b686
--- /dev/null
+++ b/patches/1055-dt-bindings-display-renesas-lvds-Document-r8a77995-b.patch
@@ -0,0 +1,36 @@
+From 001c5cdea67337d2348222ea23862e353674e78c Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 15 Feb 2018 08:38:18 +0000
+Subject: [PATCH 1055/1795] dt-bindings: display: renesas: lvds: Document
+ r8a77995 bindings
+
+The D3 (r8a77995) supports two LVDS channels. Extend the binding to
+support them.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+[Fixed compatible string]
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+(cherry picked from commit 77f59f895da2fe5526073181c74c3fb85a7c80d1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/display/bridge/renesas,lvds.txt          | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+index 2b48a4348c15..4f0ab3ed3b6f 100644
+--- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
++++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
+@@ -14,6 +14,7 @@ Required properties:
+   - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
+   - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
+   - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
++  - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
+ 
+ - reg: Base address and length for the memory-mapped registers
+ - clocks: A phandle + clock-specifier pair for the functional clock
+-- 
+2.19.0
+
diff --git a/patches/1056-drm-rcar-du-lvds-Fix-crash-in-.atomic_check-when-dis.patch b/patches/1056-drm-rcar-du-lvds-Fix-crash-in-.atomic_check-when-dis.patch
new file mode 100644
index 00000000000000..42a4e5d6126751
--- /dev/null
+++ b/patches/1056-drm-rcar-du-lvds-Fix-crash-in-.atomic_check-when-dis.patch
@@ -0,0 +1,43 @@
+From 0b2f5ec90c76e79b098dfc367a8a96b2bb54e54f Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 22:40:21 +0300
+Subject: [PATCH 1056/1795] drm: rcar-du: lvds: Fix crash in .atomic_check when
+ disabling connector
+
+The connector .atomic_check() handler can be called with a NULL crtc
+pointer in the connector state when the connector gets disabled
+explicitly (through performing a legacy mode set or setting the
+connector's CRTC_ID property to 0). This causes a crash as the crtc
+pointer is dereferenced without any check.
+
+Fix it by returning from the .atomic_check() handler when then crtc
+pointer is NULL, as there is no check to be performed when the connector
+gets disabled.
+
+Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+(cherry picked from commit 643ca198aacc671f32ef7c0c2783f0b539070a36)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_lvds.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+index 3d2d3bbd1342..155ad840f3c5 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
++++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
+@@ -88,6 +88,9 @@ static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
+ 	const struct drm_display_mode *panel_mode;
+ 	struct drm_crtc_state *crtc_state;
+ 
++	if (!state->crtc)
++		return 0;
++
+ 	if (list_empty(&connector->modes)) {
+ 		dev_dbg(lvds->dev, "connector: empty modes list\n");
+ 		return -EINVAL;
+-- 
+2.19.0
+
diff --git a/patches/1057-soc-renesas-rcar-sysc-Mark-rcar_sysc_matches-__initc.patch b/patches/1057-soc-renesas-rcar-sysc-Mark-rcar_sysc_matches-__initc.patch
new file mode 100644
index 00000000000000..6aee01f5ef51bf
--- /dev/null
+++ b/patches/1057-soc-renesas-rcar-sysc-Mark-rcar_sysc_matches-__initc.patch
@@ -0,0 +1,37 @@
+From e833b31a5b0589bca0f9ace797c3e286949ed9b6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 19 Dec 2017 16:54:44 +0100
+Subject: [PATCH 1057/1795] soc: renesas: rcar-sysc: Mark rcar_sysc_matches[]
+ __initconst
+
+rcar_sysc_matches[] is used only by rcar_sysc_pd_init(), which is
+__init.  Hence mark rcar_sysc_matches[] __initconst.
+
+This frees another 1764 bytes (arm32/shmobile_defconfig) or 1000 bytes
+(arm64/renesas_defconfig) of memory after kernel init.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 707aa45d2612778e2f3b6c5e1950ed9fa48974aa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/rcar-sysc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 52c25a5e2646..636872bc2416 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -254,7 +254,7 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+ 	pm_genpd_init(genpd, gov, false);
+ }
+ 
+-static const struct of_device_id rcar_sysc_matches[] = {
++static const struct of_device_id rcar_sysc_matches[] __initconst = {
+ #ifdef CONFIG_SYSC_R8A7743
+ 	{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/1058-soc-renesas-r8a77970-sysc-fix-power-area-parents.patch b/patches/1058-soc-renesas-r8a77970-sysc-fix-power-area-parents.patch
new file mode 100644
index 00000000000000..5a58ae9749a455
--- /dev/null
+++ b/patches/1058-soc-renesas-r8a77970-sysc-fix-power-area-parents.patch
@@ -0,0 +1,49 @@
+From 1c48d9728a4186f485aad96285071fdd5820f605 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 23:09:48 +0300
+Subject: [PATCH 1058/1795] soc: renesas: r8a77970-sysc: fix power area parents
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+According to the figure 9.2(b) of the R-Car Series, 3rd Generation User’s
+Manual: Hardware Rev. 0.80 the A2IRn and A2SCn power areas in R8A77970 have
+the A3IR area as a parent, thus the SYSC driver has those parents wrong...
+
+Fixes: bab9b2a74fe9 ("soc: renesas: rcar-sysc: add R8A77970 support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 40d5c8e94751f4a4fa4e0e27e3805e201a4e79c0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/r8a77970-sysc.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c
+index 8c614164718e..caf894f193ed 100644
+--- a/drivers/soc/renesas/r8a77970-sysc.c
++++ b/drivers/soc/renesas/r8a77970-sysc.c
+@@ -25,12 +25,12 @@ static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
+ 	  PD_CPU_NOCR },
+ 	{ "cr7",	0x240, 0, R8A77970_PD_CR7,	R8A77970_PD_ALWAYS_ON },
+ 	{ "a3ir",	0x180, 0, R8A77970_PD_A3IR,	R8A77970_PD_ALWAYS_ON },
+-	{ "a2ir0",	0x400, 0, R8A77970_PD_A2IR0,	R8A77970_PD_ALWAYS_ON },
+-	{ "a2ir1",	0x400, 1, R8A77970_PD_A2IR1,	R8A77970_PD_A2IR0 },
+-	{ "a2ir2",	0x400, 2, R8A77970_PD_A2IR2,	R8A77970_PD_A2IR0 },
+-	{ "a2ir3",	0x400, 3, R8A77970_PD_A2IR3,	R8A77970_PD_A2IR0 },
+-	{ "a2sc0",	0x400, 4, R8A77970_PD_A2SC0,	R8A77970_PD_ALWAYS_ON },
+-	{ "a2sc1",	0x400, 5, R8A77970_PD_A2SC1,	R8A77970_PD_A2SC0 },
++	{ "a2ir0",	0x400, 0, R8A77970_PD_A2IR0,	R8A77970_PD_A3IR },
++	{ "a2ir1",	0x400, 1, R8A77970_PD_A2IR1,	R8A77970_PD_A3IR },
++	{ "a2ir2",	0x400, 2, R8A77970_PD_A2IR2,	R8A77970_PD_A3IR },
++	{ "a2ir3",	0x400, 3, R8A77970_PD_A2IR3,	R8A77970_PD_A3IR },
++	{ "a2sc0",	0x400, 4, R8A77970_PD_A2SC0,	R8A77970_PD_A3IR },
++	{ "a2sc1",	0x400, 5, R8A77970_PD_A2SC1,	R8A77970_PD_A3IR },
+ };
+ 
+ const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
+-- 
+2.19.0
+
diff --git a/patches/1059-dt-bindings-power-add-R8A77980-SYSC-power-domain-def.patch b/patches/1059-dt-bindings-power-add-R8A77980-SYSC-power-domain-def.patch
new file mode 100644
index 00000000000000..ab3e9201940844
--- /dev/null
+++ b/patches/1059-dt-bindings-power-add-R8A77980-SYSC-power-domain-def.patch
@@ -0,0 +1,75 @@
+From addd1782ed636d550b233928dfc3ee5731fbe1f8 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 21:29:16 +0300
+Subject: [PATCH 1059/1795] dt-bindings: power: add R8A77980 SYSC power domain
+ definitions
+
+Add macros usable by the device tree sources to reference R8A77980 SYSC
+power domains by index.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7755b40d07a8dba723aadcb9a1d2828331f3f1b3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/power/r8a77980-sysc.h | 43 +++++++++++++++++++++++
+ 1 file changed, 43 insertions(+)
+ create mode 100644 include/dt-bindings/power/r8a77980-sysc.h
+
+diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
+new file mode 100644
+index 000000000000..2c90c1237725
+--- /dev/null
++++ b/include/dt-bindings/power/r8a77980-sysc.h
+@@ -0,0 +1,43 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A77980_PD_A2SC2		0
++#define R8A77980_PD_A2SC3		1
++#define R8A77980_PD_A2SC4		2
++#define R8A77980_PD_A2PD0		3
++#define R8A77980_PD_A2PD1		4
++#define R8A77980_PD_CA53_CPU0		5
++#define R8A77980_PD_CA53_CPU1		6
++#define R8A77980_PD_CA53_CPU2		7
++#define R8A77980_PD_CA53_CPU3		8
++#define R8A77980_PD_A2CN		10
++#define R8A77980_PD_A3VIP		11
++#define R8A77980_PD_A2IR5		12
++#define R8A77980_PD_CR7			13
++#define R8A77980_PD_A2IR4		15
++#define R8A77980_PD_CA53_SCU		21
++#define R8A77980_PD_A2IR0		23
++#define R8A77980_PD_A3IR		24
++#define R8A77980_PD_A3VIP1		25
++#define R8A77980_PD_A3VIP2		26
++#define R8A77980_PD_A2IR1		27
++#define R8A77980_PD_A2IR2		28
++#define R8A77980_PD_A2IR3		29
++#define R8A77980_PD_A2SC0		30
++#define R8A77980_PD_A2SC1		31
++
++/* Always-on power area */
++#define R8A77980_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1060-soc-renesas-rcar-sysc-add-R8A77980-support.patch b/patches/1060-soc-renesas-rcar-sysc-add-R8A77980-support.patch
new file mode 100644
index 00000000000000..08295061798d9b
--- /dev/null
+++ b/patches/1060-soc-renesas-rcar-sysc-add-R8A77980-support.patch
@@ -0,0 +1,161 @@
+From d668bc6472ccb2045ef0b4ea8f282c7381562ce5 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 21:28:02 +0300
+Subject: [PATCH 1060/1795] soc: renesas: rcar-sysc: add R8A77980 support
+
+Add support for R-Car V3H (R8A77980) SoC power areas to the R-Car SYSC
+driver.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 41d6d8bd8ae94ca9ee53720cd530168aca557db7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/power/renesas,rcar-sysc.txt      |  1 +
+ drivers/soc/renesas/Kconfig                   |  5 ++
+ drivers/soc/renesas/Makefile                  |  1 +
+ drivers/soc/renesas/r8a77980-sysc.c           | 52 +++++++++++++++++++
+ drivers/soc/renesas/rcar-sysc.c               |  3 ++
+ drivers/soc/renesas/rcar-sysc.h               |  1 +
+ 6 files changed, 63 insertions(+)
+ create mode 100644 drivers/soc/renesas/r8a77980-sysc.c
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+index 8690f10426a3..6284a9550b3c 100644
+--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
++++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+@@ -18,6 +18,7 @@ Required properties:
+       - "renesas,r8a7795-sysc" (R-Car H3)
+       - "renesas,r8a7796-sysc" (R-Car M3-W)
+       - "renesas,r8a77970-sysc" (R-Car V3M)
++      - "renesas,r8a77980-sysc" (R-Car V3H)
+       - "renesas,r8a77995-sysc" (R-Car D3)
+   - reg: Address start and address range for the device.
+   - #power-domain-cells: Must be 1.
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 741b7cd8f311..0aefa5f7b44a 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -15,6 +15,7 @@ config SOC_RENESAS
+ 	select SYSC_R8A7795 if ARCH_R8A7795
+ 	select SYSC_R8A7796 if ARCH_R8A7796
+ 	select SYSC_R8A77970 if ARCH_R8A77970
++	select SYSC_R8A77980 if ARCH_R8A77980
+ 	select SYSC_R8A77995 if ARCH_R8A77995
+ 
+ if SOC_RENESAS
+@@ -60,6 +61,10 @@ config SYSC_R8A77970
+ 	bool "R-Car V3M System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+ 
++config SYSC_R8A77980
++	bool "R-Car V3H System Controller support" if COMPILE_TEST
++	select SYSC_RCAR
++
+ config SYSC_R8A77995
+ 	bool "R-Car D3 System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index 845d62a08ce1..d3b7bb3284c0 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_SYSC_R8A7794)	+= r8a7794-sysc.o
+ obj-$(CONFIG_SYSC_R8A7795)	+= r8a7795-sysc.o
+ obj-$(CONFIG_SYSC_R8A7796)	+= r8a7796-sysc.o
+ obj-$(CONFIG_SYSC_R8A77970)	+= r8a77970-sysc.o
++obj-$(CONFIG_SYSC_R8A77980)	+= r8a77980-sysc.o
+ obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
+ 
+ # Family
+diff --git a/drivers/soc/renesas/r8a77980-sysc.c b/drivers/soc/renesas/r8a77980-sysc.c
+new file mode 100644
+index 000000000000..9265fb525ef3
+--- /dev/null
++++ b/drivers/soc/renesas/r8a77980-sysc.c
+@@ -0,0 +1,52 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Renesas R-Car V3H System Controller
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a77980-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a77980_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
++	{ "ca53-scu",	0x140, 0, R8A77980_PD_CA53_SCU,	R8A77980_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca53-cpu0",	0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu1",	0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu2",	0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu3",	0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "cr7",	0x240, 0, R8A77980_PD_CR7,	R8A77980_PD_ALWAYS_ON },
++	{ "a3ir",	0x180, 0, R8A77980_PD_A3IR,	R8A77980_PD_ALWAYS_ON },
++	{ "a2ir0",	0x400, 0, R8A77980_PD_A2IR0,	R8A77980_PD_A3IR },
++	{ "a2ir1",	0x400, 1, R8A77980_PD_A2IR1,	R8A77980_PD_A3IR },
++	{ "a2ir2",	0x400, 2, R8A77980_PD_A2IR2,	R8A77980_PD_A3IR },
++	{ "a2ir3",	0x400, 3, R8A77980_PD_A2IR3,	R8A77980_PD_A3IR },
++	{ "a2ir4",	0x400, 4, R8A77980_PD_A2IR4,	R8A77980_PD_A3IR },
++	{ "a2ir5",	0x400, 5, R8A77980_PD_A2IR5,	R8A77980_PD_A3IR },
++	{ "a2sc0",	0x400, 6, R8A77980_PD_A2SC0,	R8A77980_PD_A3IR },
++	{ "a2sc1",	0x400, 7, R8A77980_PD_A2SC1,	R8A77980_PD_A3IR },
++	{ "a2sc2",	0x400, 8, R8A77980_PD_A2SC2,	R8A77980_PD_A3IR },
++	{ "a2sc3",	0x400, 9, R8A77980_PD_A2SC3,	R8A77980_PD_A3IR },
++	{ "a2sc4",	0x400, 10, R8A77980_PD_A2SC4,	R8A77980_PD_A3IR },
++	{ "a2pd0",	0x400, 11, R8A77980_PD_A2PD0,	R8A77980_PD_A3IR },
++	{ "a2pd1",	0x400, 12, R8A77980_PD_A2PD1,	R8A77980_PD_A3IR },
++	{ "a2cn",	0x400, 13, R8A77980_PD_A2CN,	R8A77980_PD_A3IR },
++	{ "a3vip",	0x2c0, 0, R8A77980_PD_A3VIP,	R8A77980_PD_ALWAYS_ON },
++	{ "a3vip1",	0x300, 0, R8A77980_PD_A3VIP1,	R8A77980_PD_A3VIP },
++	{ "a3vip2",	0x280, 0, R8A77980_PD_A3VIP2,	R8A77980_PD_A3VIP },
++};
++
++const struct rcar_sysc_info r8a77980_sysc_info __initconst = {
++	.areas = r8a77980_areas,
++	.num_areas = ARRAY_SIZE(r8a77980_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 636872bc2416..72b0f4a9ad4e 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -287,6 +287,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
+ #ifdef CONFIG_SYSC_R8A77970
+ 	{ .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
+ #endif
++#ifdef CONFIG_SYSC_R8A77980
++	{ .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
++#endif
+ #ifdef CONFIG_SYSC_R8A77995
+ 	{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
+ #endif
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index 9d9daf9eb91b..974b18619c08 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -59,6 +59,7 @@ extern const struct rcar_sysc_info r8a7794_sysc_info;
+ extern const struct rcar_sysc_info r8a7795_sysc_info;
+ extern const struct rcar_sysc_info r8a7796_sysc_info;
+ extern const struct rcar_sysc_info r8a77970_sysc_info;
++extern const struct rcar_sysc_info r8a77980_sysc_info;
+ extern const struct rcar_sysc_info r8a77995_sysc_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/1061-soc-renesas-rcar-sysc-Add-R-Car-M3-N-support.patch b/patches/1061-soc-renesas-rcar-sysc-Add-R-Car-M3-N-support.patch
new file mode 100644
index 00000000000000..6e333a7abeaf72
--- /dev/null
+++ b/patches/1061-soc-renesas-rcar-sysc-Add-R-Car-M3-N-support.patch
@@ -0,0 +1,180 @@
+From 8e0b5336646c478d0149806d5ad080ee2d505541 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:06 +0100
+Subject: [PATCH 1061/1795] soc: renesas: rcar-sysc: Add R-Car M3-N support
+
+Add support for R-Car M3-N (R8A77965) power areas.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a527709b78b3c9979fb47ddd4c3d3fd96182b504)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/power/renesas,rcar-sysc.txt      |  1 +
+ drivers/soc/renesas/Kconfig                   |  5 +++
+ drivers/soc/renesas/Makefile                  |  1 +
+ drivers/soc/renesas/r8a77965-sysc.c           | 37 +++++++++++++++++++
+ drivers/soc/renesas/rcar-sysc.c               |  3 ++
+ drivers/soc/renesas/rcar-sysc.h               |  1 +
+ include/dt-bindings/power/r8a77965-sysc.h     | 30 +++++++++++++++
+ 7 files changed, 78 insertions(+)
+ create mode 100644 drivers/soc/renesas/r8a77965-sysc.c
+ create mode 100644 include/dt-bindings/power/r8a77965-sysc.h
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+index 6284a9550b3c..ab399e559257 100644
+--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
++++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+@@ -17,6 +17,7 @@ Required properties:
+       - "renesas,r8a7794-sysc" (R-Car E2)
+       - "renesas,r8a7795-sysc" (R-Car H3)
+       - "renesas,r8a7796-sysc" (R-Car M3-W)
++      - "renesas,r8a77965-sysc" (R-Car M3-N)
+       - "renesas,r8a77970-sysc" (R-Car V3M)
+       - "renesas,r8a77980-sysc" (R-Car V3H)
+       - "renesas,r8a77995-sysc" (R-Car D3)
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 0aefa5f7b44a..3bbe6114a420 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -14,6 +14,7 @@ config SOC_RENESAS
+ 	select SYSC_R8A7794 if ARCH_R8A7794
+ 	select SYSC_R8A7795 if ARCH_R8A7795
+ 	select SYSC_R8A7796 if ARCH_R8A7796
++	select SYSC_R8A77965 if ARCH_R8A77965
+ 	select SYSC_R8A77970 if ARCH_R8A77970
+ 	select SYSC_R8A77980 if ARCH_R8A77980
+ 	select SYSC_R8A77995 if ARCH_R8A77995
+@@ -57,6 +58,10 @@ config SYSC_R8A7796
+ 	bool "R-Car M3-W System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+ 
++config SYSC_R8A77965
++	bool "R-Car M3-N System Controller support" if COMPILE_TEST
++	select SYSC_RCAR
++
+ config SYSC_R8A77970
+ 	bool "R-Car V3M System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index d3b7bb3284c0..ccb5ec57a262 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSC_R8A7792)	+= r8a7792-sysc.o
+ obj-$(CONFIG_SYSC_R8A7794)	+= r8a7794-sysc.o
+ obj-$(CONFIG_SYSC_R8A7795)	+= r8a7795-sysc.o
+ obj-$(CONFIG_SYSC_R8A7796)	+= r8a7796-sysc.o
++obj-$(CONFIG_SYSC_R8A77965)	+= r8a77965-sysc.o
+ obj-$(CONFIG_SYSC_R8A77970)	+= r8a77970-sysc.o
+ obj-$(CONFIG_SYSC_R8A77980)	+= r8a77980-sysc.o
+ obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
+diff --git a/drivers/soc/renesas/r8a77965-sysc.c b/drivers/soc/renesas/r8a77965-sysc.c
+new file mode 100644
+index 000000000000..d7f7928e3c07
+--- /dev/null
++++ b/drivers/soc/renesas/r8a77965-sysc.c
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Renesas R-Car M3-N System Controller
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ *
++ * Based on Renesas R-Car M3-W System Controller
++ * Copyright (C) 2016 Glider bvba
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a77965-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a77965_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
++	{ "ca57-scu",	0x1c0, 0, R8A77965_PD_CA57_SCU,	R8A77965_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca57-cpu0",	 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU,
++	  PD_CPU_NOCR },
++	{ "ca57-cpu1",	 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU,
++	  PD_CPU_NOCR },
++	{ "cr7",	0x240, 0, R8A77965_PD_CR7,	R8A77965_PD_ALWAYS_ON },
++	{ "a3vc",	0x380, 0, R8A77965_PD_A3VC,	R8A77965_PD_ALWAYS_ON },
++	{ "a3vp",	0x340, 0, R8A77965_PD_A3VP,	R8A77965_PD_ALWAYS_ON },
++	{ "a2vc1",	0x3c0, 1, R8A77965_PD_A2VC1,	R8A77965_PD_A3VC },
++	{ "3dg-a",	0x100, 0, R8A77965_PD_3DG_A,	R8A77965_PD_ALWAYS_ON },
++	{ "3dg-b",	0x100, 1, R8A77965_PD_3DG_B,	R8A77965_PD_3DG_A },
++	{ "a3ir",	0x180, 0, R8A77965_PD_A3IR,	R8A77965_PD_ALWAYS_ON },
++};
++
++const struct rcar_sysc_info r8a77965_sysc_info __initconst = {
++	.areas = r8a77965_areas,
++	.num_areas = ARRAY_SIZE(r8a77965_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 72b0f4a9ad4e..faf20e719361 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
+ #ifdef CONFIG_SYSC_R8A7796
+ 	{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
+ #endif
++#ifdef CONFIG_SYSC_R8A77965
++	{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
++#endif
+ #ifdef CONFIG_SYSC_R8A77970
+ 	{ .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
+ #endif
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index 974b18619c08..dcdc9ec8eba7 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info;
+ extern const struct rcar_sysc_info r8a7794_sysc_info;
+ extern const struct rcar_sysc_info r8a7795_sysc_info;
+ extern const struct rcar_sysc_info r8a7796_sysc_info;
++extern const struct rcar_sysc_info r8a77965_sysc_info;
+ extern const struct rcar_sysc_info r8a77970_sysc_info;
+ extern const struct rcar_sysc_info r8a77980_sysc_info;
+ extern const struct rcar_sysc_info r8a77995_sysc_info;
+diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
+new file mode 100644
+index 000000000000..05a4b5917314
+--- /dev/null
++++ b/include/dt-bindings/power/r8a77965-sysc.h
+@@ -0,0 +1,30 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ * Copyright (C) 2016 Glider bvba
++ */
++
++#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A77965_PD_CA57_CPU0		 0
++#define R8A77965_PD_CA57_CPU1		 1
++#define R8A77965_PD_A3VP		 9
++#define R8A77965_PD_CA57_SCU		12
++#define R8A77965_PD_CR7			13
++#define R8A77965_PD_A3VC		14
++#define R8A77965_PD_3DG_A		17
++#define R8A77965_PD_3DG_B		18
++#define R8A77965_PD_A3IR		24
++#define R8A77965_PD_A2VC1		26
++
++/* Always-on power area */
++#define R8A77965_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1062-ARM-dts-r8a7790-Reduce-size-of-thermal-registers.patch b/patches/1062-ARM-dts-r8a7790-Reduce-size-of-thermal-registers.patch
new file mode 100644
index 00000000000000..d1e2c45086fd62
--- /dev/null
+++ b/patches/1062-ARM-dts-r8a7790-Reduce-size-of-thermal-registers.patch
@@ -0,0 +1,37 @@
+From 9792e8c684a286d9af4f48069f5e48e0135cbc83 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 13:14:43 +0100
+Subject: [PATCH 1062/1795] ARM: dts: r8a7790: Reduce size of thermal registers
+
+Reduce size of thermal registers in DT for r8a7790 (R-Car H2) SoC.
+
+According to the "User's Manual: Hardware" v2.00 the registers at base
+0xe61f0000 extend to an offset of 0x10, rather than 0x14 which is the case
+on the r8a73a4 (R-Mobile APE6).
+
+This should not have any runtime affect as mapping granularity is PAGE_SIZE.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 61ad2b1ab4b1ce4e495854c4faa75ca95e5e8ecd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index ed9a68538a55..13926fc7abfa 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -294,7 +294,7 @@
+ 		compatible =	"renesas,thermal-r8a7790",
+ 				"renesas,rcar-gen2-thermal",
+ 				"renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
++		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/1063-ARM-dts-r8a7791-Reduce-size-of-thermal-registers.patch b/patches/1063-ARM-dts-r8a7791-Reduce-size-of-thermal-registers.patch
new file mode 100644
index 00000000000000..bc100548632cb5
--- /dev/null
+++ b/patches/1063-ARM-dts-r8a7791-Reduce-size-of-thermal-registers.patch
@@ -0,0 +1,37 @@
+From 8339e0c29647ae0d5d85849ced8249ec2752adbd Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 13:14:44 +0100
+Subject: [PATCH 1063/1795] ARM: dts: r8a7791: Reduce size of thermal registers
+
+Reduce size of thermal registers in DT for r8a7791 (R-Car M3-W) SoC.
+
+According to the "User's Manual: Hardware" v2.00 the registers at base
+0xe61f0000 extend to an offset of 0x10, rather than 0x14 which is the case
+on the r8a73a4 (R-Mobile APE6).
+
+This should not have any runtime affect as mapping granularity is PAGE_SIZE.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3f599906744ecc2ece7ed0418a5822348000c0e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 008a260f86a5..8266a9b7cafd 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -240,7 +240,7 @@
+ 		compatible =	"renesas,thermal-r8a7791",
+ 				"renesas,rcar-gen2-thermal",
+ 				"renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
++		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/1064-ARM-dts-r8a7793-Reduce-size-of-thermal-registers.patch b/patches/1064-ARM-dts-r8a7793-Reduce-size-of-thermal-registers.patch
new file mode 100644
index 00000000000000..2833ad49d2cc8c
--- /dev/null
+++ b/patches/1064-ARM-dts-r8a7793-Reduce-size-of-thermal-registers.patch
@@ -0,0 +1,37 @@
+From 31936dc57a33dfb6b6d975b816ef2599ee22d4d1 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 20 Dec 2017 13:14:45 +0100
+Subject: [PATCH 1064/1795] ARM: dts: r8a7793: Reduce size of thermal registers
+
+Reduce size of thermal registers in DT for r8a7793 (R-Car M3-N) SoC.
+
+According to the "User's Manual: Hardware" v2.00 the registers at base
+0xe61f0000 extend to an offset of 0x10, rather than 0x14 which is the case
+on the r8a73a4 (R-Mobile APE6).
+
+This should not have any runtime affect as mapping granularity is PAGE_SIZE.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1cfe2186c708c8f954097086e3da0cffd1e75f4e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 039b22517526..e95f4fb44dc4 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -231,7 +231,7 @@
+ 		compatible =	"renesas,thermal-r8a7793",
+ 				"renesas,rcar-gen2-thermal",
+ 				"renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
++		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+ 		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-- 
+2.19.0
+
diff --git a/patches/1065-ARM-dts-lager-Add-CEC-clock-for-HDMI-transmitter.patch b/patches/1065-ARM-dts-lager-Add-CEC-clock-for-HDMI-transmitter.patch
new file mode 100644
index 00000000000000..6bd4139098ec8d
--- /dev/null
+++ b/patches/1065-ARM-dts-lager-Add-CEC-clock-for-HDMI-transmitter.patch
@@ -0,0 +1,51 @@
+From a97744a964d3ec81f2ec3aee64bbd35b8ab844a3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 9 Jan 2018 17:49:04 +0100
+Subject: [PATCH 1065/1795] ARM: dts: lager: Add CEC clock for HDMI transmitter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The adv7511 on the Lager board has a 12 MHz fixed clock
+for the CEC block. Specify this in the dts to enable CEC support.
+
+Based on a similar patch for Koelsch by Hans Verkuil.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c5aa87977626e778e1ee3bd03b14a300d9338a3a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index f2ea632381e7..7892b113ecaa 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -669,11 +669,19 @@
+ 		};
+ 	};
+ 
++	cec_clock: cec-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <12000000>;
++	};
++
+ 	hdmi@39 {
+ 		compatible = "adi,adv7511w";
+ 		reg = <0x39>;
+ 		interrupt-parent = <&gpio1>;
+ 		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&cec_clock>;
++		clock-names = "cec";
+ 
+ 		adi,input-depth = <8>;
+ 		adi,input-colorspace = "rgb";
+-- 
+2.19.0
+
diff --git a/patches/1066-ARM-dts-iwg20m-Enable-cmt0.patch b/patches/1066-ARM-dts-iwg20m-Enable-cmt0.patch
new file mode 100644
index 00000000000000..0de519b68d8771
--- /dev/null
+++ b/patches/1066-ARM-dts-iwg20m-Enable-cmt0.patch
@@ -0,0 +1,35 @@
+From 422cf697f0c4327695e9ea9b3575d8ce1042e354 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 11 Jan 2018 20:59:38 +0000
+Subject: [PATCH 1066/1795] ARM: dts: iwg20m: Enable cmt0
+
+This patch enables cmt0 support from within the iwg20m SoM dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cbeb319b9f220982acc2f533ffee5042a6763c39)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+index 75a8ca571846..1d3e9503c5bd 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
++++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+@@ -34,6 +34,10 @@
+ 	};
+ };
+ 
++&cmt0 {
++	status = "okay";
++};
++
+ &extal_clk {
+ 	clock-frequency = <20000000>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1067-ARM-dts-iwg22m-Enable-cmt0.patch b/patches/1067-ARM-dts-iwg22m-Enable-cmt0.patch
new file mode 100644
index 00000000000000..b1f727f009026f
--- /dev/null
+++ b/patches/1067-ARM-dts-iwg22m-Enable-cmt0.patch
@@ -0,0 +1,35 @@
+From f2bd9c340b88d0073255ec4e24d613b23cdfcd97 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Thu, 11 Jan 2018 20:59:39 +0000
+Subject: [PATCH 1067/1795] ARM: dts: iwg22m: Enable cmt0
+
+This patch enables cmt0 support from within the iwg22m SoM dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7d1671828696650db6123ab1d7a592a0bbf42ff2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index ed9a8cf3fe36..8d0a392b6811 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -29,6 +29,10 @@
+ 	};
+ };
+ 
++&cmt0 {
++	status = "okay";
++};
++
+ &extal_clk {
+ 	clock-frequency = <20000000>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1068-ARM-dts-r8a7790-consistently-use-single-space-after.patch b/patches/1068-ARM-dts-r8a7790-consistently-use-single-space-after.patch
new file mode 100644
index 00000000000000..ebf91625f838b1
--- /dev/null
+++ b/patches/1068-ARM-dts-r8a7790-consistently-use-single-space-after.patch
@@ -0,0 +1,137 @@
+From 2c900c0d001f26a2ce59ecc2ac717a7e7ad280ef Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:02 +0100
+Subject: [PATCH 1068/1795] ARM: dts: r8a7790: consistently use single space
+ after =
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Consistently use a single space after a =.
+
+This patch removes instances where a tab or multiple spaces are used
+instead.  It also avoids running over 80 columns in width in one of the
+lines where whitespace is updated.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 41b3568dc4f11e555aecf37fff5a08f398f97a03)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 75 +++++++++++++++++-----------------
+ 1 file changed, 38 insertions(+), 37 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 13926fc7abfa..b4306f7c1bbb 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -291,9 +291,9 @@
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+-		compatible =	"renesas,thermal-r8a7790",
+-				"renesas,rcar-gen2-thermal",
+-				"renesas,rcar-thermal";
++		compatible = "renesas,thermal-r8a7790",
++			     "renesas,rcar-gen2-thermal",
++			     "renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+@@ -423,20 +423,20 @@
+ 	audma0: dma-controller@ec700000 {
+ 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ 		reg = <0 0xec700000 0 0x10000>;
+-		interrupts =	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "error",
+ 				"ch0", "ch1", "ch2", "ch3",
+ 				"ch4", "ch5", "ch6", "ch7",
+@@ -453,20 +453,20 @@
+ 	audma1: dma-controller@ec720000 {
+ 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+ 		reg = <0 0xec720000 0 0x10000>;
+-		interrupts =	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "error",
+ 				"ch0", "ch1", "ch2", "ch3",
+ 				"ch4", "ch5", "ch6", "ch7",
+@@ -1437,12 +1437,13 @@
+ 		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+ 		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+ 		 */
+-		compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
+-		reg =	<0 0xec500000 0 0x1000>, /* SCU */
+-			<0 0xec5a0000 0 0x100>,  /* ADG */
+-			<0 0xec540000 0 0x1000>, /* SSIU */
+-			<0 0xec541000 0 0x280>,  /* SSI */
+-			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++		compatible = "renesas,rcar_sound-r8a7790",
++			     "renesas,rcar_sound-gen2";
++		reg = <0 0xec500000 0 0x1000>, /* SCU */
++		      <0 0xec5a0000 0 0x100>,  /* ADG */
++		      <0 0xec540000 0 0x1000>, /* SSIU */
++		      <0 0xec541000 0 0x280>,  /* SSI */
++		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+ 		clocks = <&cpg CPG_MOD 1005>,
+-- 
+2.19.0
+
diff --git a/patches/1069-ARM-dts-r8a7790-add-soc-node.patch b/patches/1069-ARM-dts-r8a7790-add-soc-node.patch
new file mode 100644
index 00000000000000..cb6e05db15682d
--- /dev/null
+++ b/patches/1069-ARM-dts-r8a7790-add-soc-node.patch
@@ -0,0 +1,2936 @@
+From 7631ff4ee3886bfaa1092d69a3713a5f26b2b30f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:03 +0100
+Subject: [PATCH 1069/1795] ARM: dts: r8a7790: add soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add soc node to represent the bus and move all nodes with a base address
+into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and
+R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car
+Gen2 SoCs to this scheme.
+
+The ordering is derived from simply moving each node with an address up to
+before any nodes without a base address that occur before the soc node.  To
+improve maintainability follow-up patches will sort subnodes of both the
+new soc node and the root node.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4bdb7aa7dcd0cbf49298dc73adf27639bf792161)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 2794 ++++++++++++++++----------------
+ 1 file changed, 1432 insertions(+), 1362 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index b4306f7c1bbb..1f4b3a4ed287 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -17,7 +17,6 @@
+ 
+ / {
+ 	compatible = "renesas,r8a7790";
+-	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+@@ -159,981 +158,1524 @@
+ 		};
+ 	};
+ 
+-	thermal-zones {
+-		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
+ 
+-			thermal-sensors = <&thermal>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
+ 
+-			trips {
+-				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
+-				};
+-			};
+-			cooling-maps {
+-			};
++		apmu@e6151000 {
++			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ 		};
+-	};
+ 
+-	apmu@e6151000 {
+-		compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+-		reg = <0 0xe6151000 0 0x188>;
+-		cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+-	};
++		apmu@e6152000 {
++			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
++		};
+ 
+-	apmu@e6152000 {
+-		compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+-		reg = <0 0xe6152000 0 0x188>;
+-		cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+-	};
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
+ 
+-	gic: interrupt-controller@f1001000 {
+-		compatible = "arm,gic-400";
+-		#interrupt-cells = <3>;
+-		#address-cells = <0>;
+-		interrupt-controller;
+-		reg = <0 0xf1001000 0 0x1000>,
+-			<0 0xf1002000 0 0x2000>,
+-			<0 0xf1004000 0 0x2000>,
+-			<0 0xf1006000 0 0x2000>;
+-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&cpg CPG_MOD 408>;
+-		clock-names = "clk";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 408>;
+-	};
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
+ 
+-	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6050000 0 0x50>;
+-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 0 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 912>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 912>;
+-	};
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 30>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
+ 
+-	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6051000 0 0x50>;
+-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 32 30>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 911>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 911>;
+-	};
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 30>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
+ 
+-	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6052000 0 0x50>;
+-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 64 30>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 910>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 910>;
+-	};
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
+ 
+-	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6053000 0 0x50>;
+-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 96 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 909>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 909>;
+-	};
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
+ 
+-	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6054000 0 0x50>;
+-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 128 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 908>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 908>;
+-	};
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7790",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
+ 
+-	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055000 0 0x50>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 160 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 907>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 907>;
+-	};
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7790",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
++		};
+ 
+-	thermal: thermal@e61f0000 {
+-		compatible = "renesas,thermal-r8a7790",
+-			     "renesas,rcar-gen2-thermal",
+-			     "renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+-		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 522>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 522>;
+-		#thermal-sensor-cells = <0>;
+-	};
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7790-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
+ 
+-	timer {
+-		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7790-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
++		};
+ 
+-	cmt0: timer@ffca0000 {
+-		compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
+-		reg = <0 0xffca0000 0 0x1004>;
+-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 124>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 124>;
+-
+-		status = "disabled";
+-	};
++		irqc0: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a7790", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
+ 
+-	cmt1: timer@e6130000 {
+-		compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
+-		reg = <0 0xe6130000 0 0x1004>;
+-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 329>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 329>;
+-
+-		status = "disabled";
+-	};
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	irqc0: interrupt-controller@e61c0000 {
+-		compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		reg = <0 0xe61c0000 0 0x200>;
+-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 407>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 407>;
+-	};
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	dmac0: dma-controller@e6700000 {
+-		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+-		reg = <0 0xe6700000 0 0x20000>;
+-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 219>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 219>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	dmac1: dma-controller@e6720000 {
+-		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+-		reg = <0 0xe6720000 0 0x20000>;
+-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 218>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 218>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	audma0: dma-controller@ec700000 {
+-		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+-		reg = <0 0xec700000 0 0x10000>;
+-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 502>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 502>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7790-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
+ 
+-	audma1: dma-controller@ec720000 {
+-		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+-		reg = <0 0xec720000 0 0x10000>;
+-		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 501>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 501>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7790-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
+ 
+-	usb_dmac0: dma-controller@e65a0000 {
+-		compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+-		reg = <0 0xe65a0000 0 0x100>;
+-		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "ch0", "ch1";
+-		clocks = <&cpg CPG_MOD 330>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 330>;
+-		#dma-cells = <1>;
+-		dma-channels = <2>;
+-	};
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7790",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
++		};
+ 
+-	usb_dmac1: dma-controller@e65b0000 {
+-		compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+-		reg = <0 0xe65b0000 0 0x100>;
+-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "ch0", "ch1";
+-		clocks = <&cpg CPG_MOD 331>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 331>;
+-		#dma-cells = <1>;
+-		dma-channels = <2>;
+-	};
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7790",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c0: i2c@e6508000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6508000 0 0x40>;
+-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 931>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 931>;
+-		i2c-scl-internal-delay-ns = <110>;
+-		status = "disabled";
+-	};
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7790",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c1: i2c@e6518000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6518000 0 0x40>;
+-		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 930>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 930>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7790",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
++		};
+ 
+-	i2c2: i2c@e6530000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6530000 0 0x40>;
+-		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 929>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 929>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		iic0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7790",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
+ 
+-	i2c3: i2c@e6540000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6540000 0 0x40>;
+-		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 928>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 928>;
+-		i2c-scl-internal-delay-ns = <110>;
+-		status = "disabled";
+-	};
++		iic1: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7790",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
+ 
+-	iic0: i2c@e6500000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6500000 0 0x425>;
+-		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 318>;
+-		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-		       <&dmac1 0x61>, <&dmac1 0x62>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 318>;
+-		status = "disabled";
+-	};
++		iic2: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7790",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6520000 0 0x425>;
++			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 300>;
++			dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
++			       <&dmac1 0x69>, <&dmac1 0x6a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 300>;
++			status = "disabled";
++		};
+ 
+-	iic1: i2c@e6510000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6510000 0 0x425>;
+-		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 323>;
+-		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-		       <&dmac1 0x65>, <&dmac1 0x66>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 323>;
+-		status = "disabled";
+-	};
++		iic3: i2c@e60b0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7790",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
++			       <&dmac1 0x77>, <&dmac1 0x78>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 926>;
++			status = "disabled";
++		};
+ 
+-	iic2: i2c@e6520000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6520000 0 0x425>;
+-		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 300>;
+-		dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+-		       <&dmac1 0x69>, <&dmac1 0x6a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 300>;
+-		status = "disabled";
+-	};
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7790",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
+ 
+-	iic3: i2c@e60b0000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe60b0000 0 0x425>;
+-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 926>;
+-		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+-		       <&dmac1 0x77>, <&dmac1 0x78>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 926>;
+-		status = "disabled";
+-	};
++		mmcif1: mmc@ee220000 {
++			compatible = "renesas,mmcif-r8a7790",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee220000 0 0x80>;
++			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 305>;
++			dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
++			       <&dmac1 0xe1>, <&dmac1 0xe2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 305>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
+ 
+-	mmcif0: mmc@ee200000 {
+-		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+-		reg = <0 0xee200000 0 0x80>;
+-		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 315>;
+-		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 315>;
+-		reg-io-width = <4>;
+-		status = "disabled";
+-		max-frequency = <97500000>;
+-	};
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7790";
++			reg = <0 0xe6060000 0 0x250>;
++		};
+ 
+-	mmcif1: mmc@ee220000 {
+-		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+-		reg = <0 0xee220000 0 0x80>;
+-		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 305>;
+-		dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+-		       <&dmac1 0xe1>, <&dmac1 0xe2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 305>;
+-		reg-io-width = <4>;
+-		status = "disabled";
+-		max-frequency = <97500000>;
+-	};
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
+ 
+-	pfc: pin-controller@e6060000 {
+-		compatible = "renesas,pfc-r8a7790";
+-		reg = <0 0xe6060000 0 0x250>;
+-	};
++		sdhi1: sd@ee120000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee120000 0 0x328>;
++			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 313>;
++			dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
++			       <&dmac1 0xc9>, <&dmac1 0xca>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 313>;
++			status = "disabled";
++		};
+ 
+-	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7790",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee100000 0 0x328>;
+-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 314>;
+-		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-		       <&dmac1 0xcd>, <&dmac1 0xce>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <195000000>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 314>;
+-		status = "disabled";
+-	};
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
+ 
+-	sdhi1: sd@ee120000 {
+-		compatible = "renesas,sdhi-r8a7790",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee120000 0 0x328>;
+-		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 313>;
+-		dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+-		       <&dmac1 0xc9>, <&dmac1 0xca>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <195000000>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 313>;
+-		status = "disabled";
+-	};
++		sdhi3: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
+ 
+-	sdhi2: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7790",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee140000 0 0x100>;
+-		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 312>;
+-		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 312>;
+-		status = "disabled";
+-	};
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7790",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
++			       <&dmac1 0x21>, <&dmac1 0x22>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
+ 
+-	sdhi3: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7790",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee160000 0 0x100>;
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 311>;
+-		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 311>;
+-		status = "disabled";
+-	};
++		scifa1: serial@e6c50000 {
++			compatible = "renesas,scifa-r8a7790",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
++			       <&dmac1 0x25>, <&dmac1 0x26>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
+ 
+-	scifa0: serial@e6c40000 {
+-		compatible = "renesas,scifa-r8a7790",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c40000 0 64>;
+-		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 204>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+-		       <&dmac1 0x21>, <&dmac1 0x22>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 204>;
+-		status = "disabled";
+-	};
++		scifa2: serial@e6c60000 {
++			compatible = "renesas,scifa-r8a7790",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c60000 0 64>;
++			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
++			       <&dmac1 0x27>, <&dmac1 0x28>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 202>;
++			status = "disabled";
++		};
+ 
+-	scifa1: serial@e6c50000 {
+-		compatible = "renesas,scifa-r8a7790",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c50000 0 64>;
+-		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 203>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+-		       <&dmac1 0x25>, <&dmac1 0x26>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 203>;
+-		status = "disabled";
+-	};
++		scifb0: serial@e6c20000 {
++			compatible = "renesas,scifb-r8a7790",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c20000 0 0x100>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
++			       <&dmac1 0x3d>, <&dmac1 0x3e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
+ 
+-	scifa2: serial@e6c60000 {
+-		compatible = "renesas,scifa-r8a7790",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c60000 0 64>;
+-		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 202>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+-		       <&dmac1 0x27>, <&dmac1 0x28>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 202>;
+-		status = "disabled";
+-	};
++		scifb1: serial@e6c30000 {
++			compatible = "renesas,scifb-r8a7790",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c30000 0 0x100>;
++			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
++			       <&dmac1 0x19>, <&dmac1 0x1a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
+ 
+-	scifb0: serial@e6c20000 {
+-		compatible = "renesas,scifb-r8a7790",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c20000 0 0x100>;
+-		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 206>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+-		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 206>;
+-		status = "disabled";
+-	};
++		scifb2: serial@e6ce0000 {
++			compatible = "renesas,scifb-r8a7790",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6ce0000 0 0x100>;
++			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 216>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
++			       <&dmac1 0x1d>, <&dmac1 0x1e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 216>;
++			status = "disabled";
++		};
+ 
+-	scifb1: serial@e6c30000 {
+-		compatible = "renesas,scifb-r8a7790",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c30000 0 0x100>;
+-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 207>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+-		       <&dmac1 0x19>, <&dmac1 0x1a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 207>;
+-		status = "disabled";
+-	};
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7790",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>,
++				 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 721>;
++			status = "disabled";
++		};
+ 
+-	scifb2: serial@e6ce0000 {
+-		compatible = "renesas,scifb-r8a7790",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6ce0000 0 0x100>;
+-		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 216>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+-		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 216>;
+-		status = "disabled";
+-	};
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7790",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 720>,
++				 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 720>;
++			status = "disabled";
++		};
+ 
+-	scif0: serial@e6e60000 {
+-		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e60000 0 64>;
+-		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+-		       <&dmac1 0x29>, <&dmac1 0x2a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 721>;
+-		status = "disabled";
+-	};
++		scif2: serial@e6e56000 {
++			compatible = "renesas,scif-r8a7790",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e56000 0 64>;
++			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 310>,
++				 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 310>;
++			status = "disabled";
++		};
+ 
+-	scif1: serial@e6e68000 {
+-		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e68000 0 64>;
+-		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+-		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 720>;
+-		status = "disabled";
+-	};
++		hscif0: serial@e62c0000 {
++			compatible = "renesas,hscif-r8a7790",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c0000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 717>,
++				 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 717>;
++			status = "disabled";
++		};
+ 
+-	scif2: serial@e6e56000 {
+-		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e56000 0 64>;
+-		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+-		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 310>;
+-		status = "disabled";
+-	};
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7790",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>,
++				 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++		};
+ 
+-	hscif0: serial@e62c0000 {
+-		compatible = "renesas,hscif-r8a7790",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c0000 0 96>;
+-		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-		       <&dmac1 0x39>, <&dmac1 0x3a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 717>;
+-		status = "disabled";
+-	};
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
+ 
+-	hscif1: serial@e62c8000 {
+-		compatible = "renesas,hscif-r8a7790",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c8000 0 96>;
+-		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 716>;
+-		status = "disabled";
+-	};
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
+ 
+-	icram0:	sram@e63a0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63a0000 0 0x12000>;
+-	};
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
+ 
+-	icram1:	sram@e63c0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63c0000 0 0x1000>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		ranges = <0 0 0xe63c0000 0x1000>;
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7790",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-		smp-sram@0 {
+-			compatible = "renesas,smp-sram";
+-			reg = <0 0x10>;
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7790",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7790",
+-			     "renesas,rcar-gen2-ether";
+-		reg = <0 0xee700000 0 0x400>;
+-		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 813>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 813>;
+-		phy-mode = "rmii";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		sata0: sata@ee300000 {
++			compatible = "renesas,sata-r8a7790",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee300000 0 0x2000>;
++			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 815>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 815>;
++			status = "disabled";
++		};
+ 
+-	avb: ethernet@e6800000 {
+-		compatible = "renesas,etheravb-r8a7790",
+-			     "renesas,etheravb-rcar-gen2";
+-		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 812>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 812>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		sata1: sata@ee500000 {
++			compatible = "renesas,sata-r8a7790",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee500000 0 0x2000>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 814>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 814>;
++			status = "disabled";
++		};
+ 
+-	sata0: sata@ee300000 {
+-		compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+-		reg = <0 0xee300000 0 0x2000>;
+-		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 815>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 815>;
+-		status = "disabled";
+-	};
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7790",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
+ 
+-	sata1: sata@ee500000 {
+-		compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+-		reg = <0 0xee500000 0 0x2000>;
+-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 814>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 814>;
+-		status = "disabled";
+-	};
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7790",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
+ 
+-	hsusb: usb@e6590000 {
+-		compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
+-		reg = <0 0xe6590000 0 0x100>;
+-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-		dma-names = "ch0", "ch1", "ch2", "ch3";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		renesas,buswait = <4>;
+-		phys = <&usb0 1>;
+-		phy-names = "usb";
+-		status = "disabled";
+-	};
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
++		};
+ 
+-	usbphy: usb-phy@e6590100 {
+-		compatible = "renesas,usb-phy-r8a7790",
+-			     "renesas,rcar-gen2-usb-phy";
+-		reg = <0 0xe6590100 0 0x100>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		clock-names = "usbhs";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		status = "disabled";
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7790",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
+ 
+-		usb0: usb-channel@0 {
+-			reg = <0>;
+-			#phy-cells = <1>;
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7790",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
+ 		};
+-		usb2: usb-channel@2 {
+-			reg = <2>;
+-			#phy-cells = <1>;
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7790",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	vin0: video@e6ef0000 {
+-		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef0000 0 0x1000>;
+-		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 811>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 811>;
+-		status = "disabled";
+-	};
++		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a7790",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef3000 0 0x1000>;
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
++			status = "disabled";
++		};
+ 
+-	vin1: video@e6ef1000 {
+-		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef1000 0 0x1000>;
+-		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 810>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 810>;
+-		status = "disabled";
+-	};
++		vsp@fe920000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe920000 0 0x8000>;
++			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 130>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 130>;
++		};
+ 
+-	vin2: video@e6ef2000 {
+-		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef2000 0 0x1000>;
+-		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 809>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 809>;
+-		status = "disabled";
+-	};
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
+ 
+-	vin3: video@e6ef3000 {
+-		compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef3000 0 0x1000>;
+-		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 808>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 808>;
+-		status = "disabled";
+-	};
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
+ 
+-	vsp@fe920000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe920000 0 0x8000>;
+-		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 130>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 130>;
+-	};
++		vsp@fe938000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe938000 0 0x8000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 127>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
++		};
+ 
+-	vsp@fe928000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe928000 0 0x8000>;
+-		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 131>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 131>;
+-	};
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7790";
++			reg = <0 0xfeb00000 0 0x70000>,
++			      <0 0xfeb90000 0 0x1c>,
++			      <0 0xfeb94000 0 0x1c>;
++			reg-names = "du", "lvds.0", "lvds.1";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
++				 <&cpg CPG_MOD 725>;
++			clock-names = "du.0", "du.1", "du.2", "lvds.0",
++				      "lvds.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++				port@2 {
++					reg = <2>;
++					du_out_lvds1: endpoint {
++					};
++				};
++			};
++		};
+ 
+-	vsp@fe930000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe930000 0 0x8000>;
+-		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 128>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 128>;
+-	};
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7790",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
+ 
+-	vsp@fe938000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe938000 0 0x8000>;
+-		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 127>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 127>;
+-	};
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7790",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
+ 
+-	du: display@feb00000 {
+-		compatible = "renesas,du-r8a7790";
+-		reg = <0 0xfeb00000 0 0x70000>,
+-		      <0 0xfeb90000 0 0x1c>,
+-		      <0 0xfeb94000 0 0x1c>;
+-		reg-names = "du", "lvds.0", "lvds.1";
+-		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+-			 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+-			 <&cpg CPG_MOD 725>;
+-		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+-		status = "disabled";
+-
+-		ports {
++		jpu: jpeg-codec@fe980000 {
++			compatible = "renesas,jpu-r8a7790",
++				     "renesas,rcar-gen2-jpu";
++			reg = <0 0xfe980000 0 0x10300>;
++			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 106>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 106>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7790-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7790-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7790-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
++		};
++
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7790", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-			port@0 {
+-				reg = <0>;
+-				du_out_rgb: endpoint {
++		msiof0: spi@e6e20000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e20000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 0>;
++			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
++			       <&dmac1 0x51>, <&dmac1 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof1: spi@e6e10000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e10000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
++			       <&dmac1 0x55>, <&dmac1 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 208>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof2: spi@e6e00000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 205>;
++			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
++			       <&dmac1 0x41>, <&dmac1 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 205>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof3: spi@e6c90000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6c90000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 215>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x46>,
++			       <&dmac1 0x45>, <&dmac1 0x46>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 215>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		xhci: usb@ee000000 {
++			compatible = "renesas,xhci-r8a7790",
++				     "renesas,rcar-gen2-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			phys = <&usb2 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7790",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pci1: pci@ee0b0000 {
++			compatible = "renesas,pci-r8a7790",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0b0000 0 0xc00>,
++			      <0 0xee0a0000 0 0x1100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pci2: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7790",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			status = "disabled";
++
++			bus-range = <2 2>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x20800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x21000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pciec: pcie@fe000000 {
++			compatible = "renesas,pcie-r8a7790",
++				     "renesas,pcie-rcar-gen2";
++			reg = <0 0xfe000000 0 0x80000>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			bus-range = <0x00 0xff>;
++			device_type = "pci";
++			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
++				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
++				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
++				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
++			/* Map all possible DDR as inbound ranges */
++			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
++				      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
++			clock-names = "pcie", "pcie_bus";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 319>;
++			status = "disabled";
++		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7790",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++				 <&cpg CPG_CORE R8A7790_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0",
++				      "src.9", "src.8", "src.7", "src.6",
++				      "src.5", "src.4", "src.3", "src.2",
++				      "src.1", "src.0",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>,
++				 <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
++
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma1 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma1 0xbe>;
++					dma-names = "tx";
+ 				};
+ 			};
+-			port@1 {
+-				reg = <1>;
+-				du_out_lvds0: endpoint {
++
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
++
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
++
++			rcar_sound,src {
++				src0: src-0 {
++					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x85>, <&audma1 0x9a>;
++					dma-names = "rx", "tx";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma1 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma1 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma1 0xb4>;
++					dma-names = "rx", "tx";
++				};
++				src7: src-7 {
++					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x93>, <&audma1 0xb6>;
++					dma-names = "rx", "tx";
++				};
++				src8: src-8 {
++					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x95>, <&audma1 0xb8>;
++					dma-names = "rx", "tx";
++				};
++				src9: src-9 {
++					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x97>, <&audma1 0xba>;
++					dma-names = "rx", "tx";
+ 				};
+ 			};
+-			port@2 {
+-				reg = <2>;
+-				du_out_lvds1: endpoint {
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>,
++					       <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>,
++					       <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>,
++					       <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>,
++					       <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>,
++					       <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
++					       <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
++					       <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>,
++					       <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>,
++					       <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>,
++					       <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
+ 				};
+ 			};
+ 		};
+-	};
+ 
+-	can0: can@e6e80000 {
+-		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e80000 0 0x1000>;
+-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 916>;
+-		status = "disabled";
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xffc80000 0 0x1000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 	};
+ 
+-	can1: can@e6e88000 {
+-		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e88000 0 0x1000>;
+-		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 915>;
+-		status = "disabled";
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive	= <0>;
++			polling-delay		= <0>;
++
++			thermal-sensors = <&thermal>;
++
++			trips {
++				cpu-crit {
++					temperature	= <95000>;
++					hysteresis	= <0>;
++					type		= "critical";
++				};
++			};
++			cooling-maps {
++			};
++		};
+ 	};
+ 
+-	jpu: jpeg-codec@fe980000 {
+-		compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
+-		reg = <0 0xfe980000 0 0x10300>;
+-		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 106>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 106>;
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+ 	/* External root clock */
+@@ -1194,476 +1736,4 @@
+ 		/* This value must be overridden by the board. */
+ 		clock-frequency = <0>;
+ 	};
+-
+-	cpg: clock-controller@e6150000 {
+-		compatible = "renesas,r8a7790-cpg-mssr";
+-		reg = <0 0xe6150000 0 0x1000>;
+-		clocks = <&extal_clk>, <&usb_extal_clk>;
+-		clock-names = "extal", "usb_extal";
+-		#clock-cells = <2>;
+-		#power-domain-cells = <0>;
+-		#reset-cells = <1>;
+-	};
+-
+-	prr: chipid@ff000044 {
+-		compatible = "renesas,prr";
+-		reg = <0 0xff000044 0 4>;
+-	};
+-
+-	rst: reset-controller@e6160000 {
+-		compatible = "renesas,r8a7790-rst";
+-		reg = <0 0xe6160000 0 0x0100>;
+-	};
+-
+-	sysc: system-controller@e6180000 {
+-		compatible = "renesas,r8a7790-sysc";
+-		reg = <0 0xe6180000 0 0x0200>;
+-		#power-domain-cells = <1>;
+-	};
+-
+-	qspi: spi@e6b10000 {
+-		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+-		reg = <0 0xe6b10000 0 0x2c>;
+-		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 917>;
+-		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-		       <&dmac1 0x17>, <&dmac1 0x18>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 917>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof0: spi@e6e20000 {
+-		compatible = "renesas,msiof-r8a7790",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e20000 0 0x0064>;
+-		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 0>;
+-		dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+-		       <&dmac1 0x51>, <&dmac1 0x52>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 0>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof1: spi@e6e10000 {
+-		compatible = "renesas,msiof-r8a7790",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e10000 0 0x0064>;
+-		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 208>;
+-		dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+-		       <&dmac1 0x55>, <&dmac1 0x56>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 208>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof2: spi@e6e00000 {
+-		compatible = "renesas,msiof-r8a7790",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e00000 0 0x0064>;
+-		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 205>;
+-		dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+-		       <&dmac1 0x41>, <&dmac1 0x42>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 205>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof3: spi@e6c90000 {
+-		compatible = "renesas,msiof-r8a7790",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6c90000 0 0x0064>;
+-		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 215>;
+-		dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+-		       <&dmac1 0x45>, <&dmac1 0x46>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 215>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	xhci: usb@ee000000 {
+-		compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
+-		reg = <0 0xee000000 0 0xc00>;
+-		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 328>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 328>;
+-		phys = <&usb2 1>;
+-		phy-names = "usb";
+-		status = "disabled";
+-	};
+-
+-	pci0: pci@ee090000 {
+-		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee090000 0 0xc00>,
+-		      <0 0xee080000 0 0x1100>;
+-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <0 0>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x800 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
+-		};
+-
+-		usb@2,0 {
+-			reg = <0x1000 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
+-		};
+-	};
+-
+-	pci1: pci@ee0b0000 {
+-		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee0b0000 0 0xc00>,
+-		      <0 0xee0a0000 0 0x1100>;
+-		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <1 1>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-	};
+-
+-	pci2: pci@ee0d0000 {
+-		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		reg = <0 0xee0d0000 0 0xc00>,
+-		      <0 0xee0c0000 0 0x1100>;
+-		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-		status = "disabled";
+-
+-		bus-range = <2 2>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x20800 0 0 0 0>;
+-			phys = <&usb2 0>;
+-			phy-names = "usb";
+-		};
+-
+-		usb@2,0 {
+-			reg = <0x21000 0 0 0 0>;
+-			phys = <&usb2 0>;
+-			phy-names = "usb";
+-		};
+-	};
+-
+-	pciec: pcie@fe000000 {
+-		compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
+-		reg = <0 0xfe000000 0 0x80000>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		bus-range = <0x00 0xff>;
+-		device_type = "pci";
+-		ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+-			  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+-			  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+-			  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+-		/* Map all possible DDR as inbound ranges */
+-		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+-			      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+-		#interrupt-cells = <1>;
+-		interrupt-map-mask = <0 0 0 0>;
+-		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+-		clock-names = "pcie", "pcie_bus";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 319>;
+-		status = "disabled";
+-	};
+-
+-	rcar_sound: sound@ec500000 {
+-		/*
+-		 * #sound-dai-cells is required
+-		 *
+-		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+-		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+-		 */
+-		compatible = "renesas,rcar_sound-r8a7790",
+-			     "renesas,rcar_sound-gen2";
+-		reg = <0 0xec500000 0 0x1000>, /* SCU */
+-		      <0 0xec5a0000 0 0x100>,  /* ADG */
+-		      <0 0xec540000 0 0x1000>, /* SSIU */
+-		      <0 0xec541000 0 0x280>,  /* SSI */
+-		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+-		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+-
+-		clocks = <&cpg CPG_MOD 1005>,
+-			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+-			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+-			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+-			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+-			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+-			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+-			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+-			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+-			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+-			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+-			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+-			 <&cpg CPG_CORE R8A7790_CLK_M2>;
+-		clock-names = "ssi-all",
+-				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-				"src.9", "src.8", "src.7", "src.6", "src.5",
+-				"src.4", "src.3", "src.2", "src.1", "src.0",
+-				"ctu.0", "ctu.1",
+-				"mix.0", "mix.1",
+-				"dvc.0", "dvc.1",
+-				"clk_a", "clk_b", "clk_c", "clk_i";
+-		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-		resets = <&cpg 1005>,
+-			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+-			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+-			 <&cpg 1014>, <&cpg 1015>;
+-		reset-names = "ssi-all",
+-			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+-
+-		status = "disabled";
+-
+-		rcar_sound,dvc {
+-			dvc0: dvc-0 {
+-				dmas = <&audma1 0xbc>;
+-				dma-names = "tx";
+-			};
+-			dvc1: dvc-1 {
+-				dmas = <&audma1 0xbe>;
+-				dma-names = "tx";
+-			};
+-		};
+-
+-		rcar_sound,mix {
+-			mix0: mix-0 { };
+-			mix1: mix-1 { };
+-		};
+-
+-		rcar_sound,ctu {
+-			ctu00: ctu-0 { };
+-			ctu01: ctu-1 { };
+-			ctu02: ctu-2 { };
+-			ctu03: ctu-3 { };
+-			ctu10: ctu-4 { };
+-			ctu11: ctu-5 { };
+-			ctu12: ctu-6 { };
+-			ctu13: ctu-7 { };
+-		};
+-
+-		rcar_sound,src {
+-			src0: src-0 {
+-				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x85>, <&audma1 0x9a>;
+-				dma-names = "rx", "tx";
+-			};
+-			src1: src-1 {
+-				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x87>, <&audma1 0x9c>;
+-				dma-names = "rx", "tx";
+-			};
+-			src2: src-2 {
+-				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x89>, <&audma1 0x9e>;
+-				dma-names = "rx", "tx";
+-			};
+-			src3: src-3 {
+-				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src4: src-4 {
+-				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src5: src-5 {
+-				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+-				dma-names = "rx", "tx";
+-			};
+-			src6: src-6 {
+-				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x91>, <&audma1 0xb4>;
+-				dma-names = "rx", "tx";
+-			};
+-			src7: src-7 {
+-				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x93>, <&audma1 0xb6>;
+-				dma-names = "rx", "tx";
+-			};
+-			src8: src-8 {
+-				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x95>, <&audma1 0xb8>;
+-				dma-names = "rx", "tx";
+-			};
+-			src9: src-9 {
+-				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x97>, <&audma1 0xba>;
+-				dma-names = "rx", "tx";
+-			};
+-		};
+-
+-		rcar_sound,ssi {
+-			ssi0: ssi-0 {
+-				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi1: ssi-1 {
+-				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi2: ssi-2 {
+-				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi3: ssi-3 {
+-				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi4: ssi-4 {
+-				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi5: ssi-5 {
+-				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi6: ssi-6 {
+-				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi7: ssi-7 {
+-				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi8: ssi-8 {
+-				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi9: ssi-9 {
+-				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-		};
+-	};
+-
+-	ipmmu_sy0: mmu@e6280000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6280000 0 0x1000>;
+-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_sy1: mmu@e6290000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6290000 0 0x1000>;
+-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_ds: mmu@e6740000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6740000 0 0x1000>;
+-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mp: mmu@ec680000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xec680000 0 0x1000>;
+-		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mx: mmu@fe951000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xfe951000 0 0x1000>;
+-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_rt: mmu@ffc80000 {
+-		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+-		reg = <0 0xffc80000 0 0x1000>;
+-		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1070-ARM-dts-r8a7790-sort-subnodes-of-soc-node.patch b/patches/1070-ARM-dts-r8a7790-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..859832c57d41c5
--- /dev/null
+++ b/patches/1070-ARM-dts-r8a7790-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,1781 @@
+From 27401ab18f0f6e963c87ced50afb1a5793f478af Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:04 +0100
+Subject: [PATCH 1070/1795] ARM: dts: r8a7790: sort subnodes of soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the addresss on the bus with instances of the same
+IP block grouped together.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5923abc19cd76b63652401f2851b863b8f5deffa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 1592 ++++++++++++++++----------------
+ 1 file changed, 796 insertions(+), 796 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 1f4b3a4ed287..54c5a2d7ea89 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -166,32 +166,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6151000 {
+-			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+-			reg = <0 0xe6151000 0 0x188>;
+-			cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+-		};
+-
+-		apmu@e6152000 {
+-			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+-			reg = <0 0xe6152000 0 0x188>;
+-			cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+-			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7790",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -282,50 +256,42 @@
+ 			resets = <&cpg 907>;
+ 		};
+ 
+-		thermal: thermal@e61f0000 {
+-			compatible = "renesas,thermal-r8a7790",
+-				     "renesas,rcar-gen2-thermal",
+-				     "renesas,rcar-thermal";
+-			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 522>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 522>;
+-			#thermal-sensor-cells = <0>;
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7790";
++			reg = <0 0xe6060000 0 0x250>;
+ 		};
+ 
+-		cmt0: timer@ffca0000 {
+-			compatible = "renesas,r8a7790-cmt0",
+-				     "renesas,rcar-gen2-cmt0";
+-			reg = <0 0xffca0000 0 0x1004>;
+-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 124>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 124>;
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7790-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
+ 
+-			status = "disabled";
++		apmu@e6151000 {
++			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ 		};
+ 
+-		cmt1: timer@e6130000 {
+-			compatible = "renesas,r8a7790-cmt1",
+-				     "renesas,rcar-gen2-cmt1";
+-			reg = <0 0xe6130000 0 0x1004>;
+-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 329>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
++		apmu@e6152000 {
++			compatible = "renesas,r8a7790-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
++		};
+ 
+-			status = "disabled";
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7790-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7790-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
+ 		};
+ 
+ 		irqc0: interrupt-controller@e61c0000 {
+@@ -342,160 +308,91 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		dmac0: dma-controller@e6700000 {
+-			compatible = "renesas,dmac-r8a7790",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6700000 0 0x20000>;
+-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 219>;
+-			clock-names = "fck";
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7790",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 219>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
+ 		};
+ 
+-		dmac1: dma-controller@e6720000 {
+-			compatible = "renesas,dmac-r8a7790",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6720000 0 0x20000>;
+-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7790",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		audma1: dma-controller@ec720000 {
+-			compatible = "renesas,dmac-r8a7790",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec720000 0 0x10000>;
+-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 501>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 501>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		usb_dmac0: dma-controller@e65a0000 {
+-			compatible = "renesas,r8a7790-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65a0000 0 0x100>;
+-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 330>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 330>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		usb_dmac1: dma-controller@e65b0000 {
+-			compatible = "renesas,r8a7790-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65b0000 0 0x100>;
+-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 331>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 331>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7790",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xffc80000 0 0x1000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
+ 		};
+ 
+ 		i2c0: i2c@e6508000 {
+@@ -622,107 +519,172 @@
+ 			status = "disabled";
+ 		};
+ 
+-		mmcif0: mmc@ee200000 {
+-			compatible = "renesas,mmcif-r8a7790",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee200000 0 0x80>;
+-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 315>;
+-			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-			       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7790",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 315>;
+-			reg-io-width = <4>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
+ 			status = "disabled";
+-			max-frequency = <97500000>;
+ 		};
+ 
+-		mmcif1: mmc@ee220000 {
+-			compatible = "renesas,mmcif-r8a7790",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee220000 0 0x80>;
+-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 305>;
+-			dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+-			       <&dmac1 0xe1>, <&dmac1 0xe2>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7790",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 305>;
+-			reg-io-width = <4>;
++			resets = <&cpg 704>;
+ 			status = "disabled";
+-			max-frequency = <97500000>;
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7790";
+-			reg = <0 0xe6060000 0 0x250>;
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7790-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
+ 		};
+ 
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7790",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7790-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
+-			status = "disabled";
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
+ 		};
+ 
+-		sdhi1: sd@ee120000 {
+-			compatible = "renesas,sdhi-r8a7790",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee120000 0 0x328>;
+-			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 313>;
+-			dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+-			       <&dmac1 0xc9>, <&dmac1 0xca>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 313>;
+-			status = "disabled";
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7790",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee140000 0 0x100>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
+-			status = "disabled";
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		sdhi3: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7790",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee160000 0 0x100>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7790",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifa0: serial@e6c40000 {
+-			compatible = "renesas,scifa-r8a7790",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c40000 0 64>;
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7790", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7790",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
+ 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 204>;
+ 			clock-names = "fck";
+@@ -892,110 +854,94 @@
+ 			status = "disabled";
+ 		};
+ 
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
+-		};
+-
+-		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7790",
+-				     "renesas,rcar-gen2-ether";
+-			reg = <0 0xee700000 0 0x400>;
+-			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 813>;
++		msiof0: spi@e6e20000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e20000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 0>;
++			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
++			       <&dmac1 0x51>, <&dmac1 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 813>;
+-			phy-mode = "rmii";
++			resets = <&cpg 0>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7790",
+-				     "renesas,etheravb-rcar-gen2";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 812>;
++		msiof1: spi@e6e10000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e10000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
++			       <&dmac1 0x55>, <&dmac1 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
++			resets = <&cpg 208>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		sata0: sata@ee300000 {
+-			compatible = "renesas,sata-r8a7790",
+-				     "renesas,rcar-gen2-sata";
+-			reg = <0 0xee300000 0 0x2000>;
+-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 815>;
++		msiof2: spi@e6e00000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 205>;
++			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
++			       <&dmac1 0x41>, <&dmac1 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 815>;
++			resets = <&cpg 205>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		sata1: sata@ee500000 {
+-			compatible = "renesas,sata-r8a7790",
+-				     "renesas,rcar-gen2-sata";
+-			reg = <0 0xee500000 0 0x2000>;
+-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 814>;
++		msiof3: spi@e6c90000 {
++			compatible = "renesas,msiof-r8a7790",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6c90000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 215>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x46>,
++			       <&dmac1 0x45>, <&dmac1 0x46>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 814>;
++			resets = <&cpg 215>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7790",
+-				     "renesas,rcar-gen2-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7790",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			renesas,buswait = <4>;
+-			phys = <&usb0 1>;
+-			phy-names = "usb";
++			resets = <&cpg 916>;
+ 			status = "disabled";
+ 		};
+ 
+-		usbphy: usb-phy@e6590100 {
+-			compatible = "renesas,usb-phy-r8a7790",
+-				     "renesas,rcar-gen2-usb-phy";
+-			reg = <0 0xe6590100 0 0x100>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			clock-names = "usbhs";
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7790",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
++			resets = <&cpg 915>;
+ 			status = "disabled";
+-
+-			usb0: usb-channel@0 {
+-				reg = <0>;
+-				#phy-cells = <1>;
+-			};
+-			usb2: usb-channel@2 {
+-				reg = <2>;
+-				#phy-cells = <1>;
+-			};
+ 		};
+ 
+ 		vin0: video@e6ef0000 {
+@@ -1042,220 +988,267 @@
+ 			status = "disabled";
+ 		};
+ 
+-		vsp@fe920000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe920000 0 0x8000>;
+-			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 130>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 130>;
+-		};
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7790",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+-		vsp@fe928000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe928000 0 0x8000>;
+-			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 131>;
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++				 <&cpg CPG_CORE R8A7790_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0",
++				      "src.9", "src.8", "src.7", "src.6",
++				      "src.5", "src.4", "src.3", "src.2",
++				      "src.1", "src.0",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 131>;
+-		};
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>,
++				 <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
+ 
+-		vsp@fe930000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe930000 0 0x8000>;
+-			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 128>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 128>;
+-		};
++			status = "disabled";
+ 
+-		vsp@fe938000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe938000 0 0x8000>;
+-			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 127>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 127>;
+-		};
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma1 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma1 0xbe>;
++					dma-names = "tx";
++				};
++			};
+ 
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7790";
+-			reg = <0 0xfeb00000 0 0x70000>,
+-			      <0 0xfeb90000 0 0x1c>,
+-			      <0 0xfeb94000 0 0x1c>;
+-			reg-names = "du", "lvds.0", "lvds.1";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+-				 <&cpg CPG_MOD 725>;
+-			clock-names = "du.0", "du.1", "du.2", "lvds.0",
+-				      "lvds.1";
+-			status = "disabled";
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
+ 
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
+ 
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb: endpoint {
+-					};
++			rcar_sound,src {
++				src0: src-0 {
++					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x85>, <&audma1 0x9a>;
++					dma-names = "rx", "tx";
+ 				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_lvds0: endpoint {
+-					};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma1 0x9c>;
++					dma-names = "rx", "tx";
+ 				};
+-				port@2 {
+-					reg = <2>;
+-					du_out_lvds1: endpoint {
+-					};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma1 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma1 0xb4>;
++					dma-names = "rx", "tx";
++				};
++				src7: src-7 {
++					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x93>, <&audma1 0xb6>;
++					dma-names = "rx", "tx";
++				};
++				src8: src-8 {
++					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x95>, <&audma1 0xb8>;
++					dma-names = "rx", "tx";
++				};
++				src9: src-9 {
++					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x97>, <&audma1 0xba>;
++					dma-names = "rx", "tx";
+ 				};
+ 			};
+-		};
+-
+-		can0: can@e6e80000 {
+-			compatible = "renesas,can-r8a7790",
+-				     "renesas,rcar-gen2-can";
+-			reg = <0 0xe6e80000 0 0x1000>;
+-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 916>,
+-				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 916>;
+-			status = "disabled";
+-		};
+-
+-		can1: can@e6e88000 {
+-			compatible = "renesas,can-r8a7790",
+-				     "renesas,rcar-gen2-can";
+-			reg = <0 0xe6e88000 0 0x1000>;
+-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 915>,
+-				 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
+-			status = "disabled";
+-		};
+-
+-		jpu: jpeg-codec@fe980000 {
+-			compatible = "renesas,jpu-r8a7790",
+-				     "renesas,rcar-gen2-jpu";
+-			reg = <0 0xfe980000 0 0x10300>;
+-			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 106>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 106>;
+-		};
+-
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7790-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
+-		};
+-
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
+-		};
+-
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7790-rst";
+-			reg = <0 0xe6160000 0 0x0100>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7790-sysc";
+-			reg = <0 0xe6180000 0 0x0200>;
+-			#power-domain-cells = <1>;
+-		};
+-
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 917>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+ 
+-		msiof0: spi@e6e20000 {
+-			compatible = "renesas,msiof-r8a7790",
+-				     "renesas,rcar-gen2-msiof";
+-			reg = <0 0xe6e20000 0 0x0064>;
+-			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 0>;
+-			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+-			       <&dmac1 0x51>, <&dmac1 0x52>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 0>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		msiof1: spi@e6e10000 {
+-			compatible = "renesas,msiof-r8a7790",
+-				     "renesas,rcar-gen2-msiof";
+-			reg = <0 0xe6e10000 0 0x0064>;
+-			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 208>;
+-			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+-			       <&dmac1 0x55>, <&dmac1 0x56>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 208>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>,
++					       <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>,
++					       <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>,
++					       <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>,
++					       <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>,
++					       <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
++					       <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
++					       <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>,
++					       <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>,
++					       <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>,
++					       <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++			};
+ 		};
+ 
+-		msiof2: spi@e6e00000 {
+-			compatible = "renesas,msiof-r8a7790",
+-				     "renesas,rcar-gen2-msiof";
+-			reg = <0 0xe6e00000 0 0x0064>;
+-			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 205>;
+-			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+-			       <&dmac1 0x41>, <&dmac1 0x42>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 205>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
+ 		};
+-
+-		msiof3: spi@e6c90000 {
+-			compatible = "renesas,msiof-r8a7790",
+-				     "renesas,rcar-gen2-msiof";
+-			reg = <0 0xe6c90000 0 0x0064>;
+-			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 215>;
+-			dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+-			       <&dmac1 0x45>, <&dmac1 0x46>;
+-			dma-names = "tx", "rx", "tx", "rx";
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7790",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 215>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
+ 		};
+ 
+ 		xhci: usb@ee000000 {
+@@ -1364,6 +1357,148 @@
+ 			};
+ 		};
+ 
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee120000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee120000 0 0x328>;
++			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 313>;
++			dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
++			       <&dmac1 0xc9>, <&dmac1 0xca>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 313>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi3: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7790",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7790",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
++
++		mmcif1: mmc@ee220000 {
++			compatible = "renesas,mmcif-r8a7790",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee220000 0 0x80>;
++			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 305>;
++			dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
++			       <&dmac1 0xe1>, <&dmac1 0xe2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 305>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
++
++		sata0: sata@ee300000 {
++			compatible = "renesas,sata-r8a7790",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee300000 0 0x2000>;
++			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 815>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 815>;
++			status = "disabled";
++		};
++
++		sata1: sata@ee500000 {
++			compatible = "renesas,sata-r8a7790",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee500000 0 0x2000>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 814>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 814>;
++			status = "disabled";
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7790",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
+ 		pciec: pcie@fe000000 {
+ 			compatible = "renesas,pcie-r8a7790",
+ 				     "renesas,pcie-rcar-gen2";
+@@ -1392,261 +1527,126 @@
+ 			status = "disabled";
+ 		};
+ 
+-		rcar_sound: sound@ec500000 {
+-			/*
+-			 * #sound-dai-cells is required
+-			 *
+-			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+-			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+-			 */
+-			compatible = "renesas,rcar_sound-r8a7790",
+-				     "renesas,rcar_sound-gen2";
+-			reg = <0 0xec500000 0 0x1000>, /* SCU */
+-			      <0 0xec5a0000 0 0x100>,  /* ADG */
+-			      <0 0xec540000 0 0x1000>, /* SSIU */
+-			      <0 0xec541000 0 0x280>,  /* SSI */
+-			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+-			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++		vsp@fe920000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe920000 0 0x8000>;
++			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 130>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 130>;
++		};
+ 
+-			clocks = <&cpg CPG_MOD 1005>,
+-				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+-				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+-				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+-				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+-				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+-				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+-				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+-				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+-				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+-				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+-				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+-				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+-				 <&cpg CPG_CORE R8A7790_CLK_M2>;
+-			clock-names = "ssi-all",
+-				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+-				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+-				      "ssi.1", "ssi.0",
+-				      "src.9", "src.8", "src.7", "src.6",
+-				      "src.5", "src.4", "src.3", "src.2",
+-				      "src.1", "src.0",
+-				      "ctu.0", "ctu.1",
+-				      "mix.0", "mix.1",
+-				      "dvc.0", "dvc.1",
+-				      "clk_a", "clk_b", "clk_c", "clk_i";
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
++
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
++
++		vsp@fe938000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe938000 0 0x8000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 127>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
++		};
++
++		jpu: jpeg-codec@fe980000 {
++			compatible = "renesas,jpu-r8a7790",
++				     "renesas,rcar-gen2-jpu";
++			reg = <0 0xfe980000 0 0x10300>;
++			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 106>;
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 1005>,
+-				 <&cpg 1006>, <&cpg 1007>,
+-				 <&cpg 1008>, <&cpg 1009>,
+-				 <&cpg 1010>, <&cpg 1011>,
+-				 <&cpg 1012>, <&cpg 1013>,
+-				 <&cpg 1014>, <&cpg 1015>;
+-			reset-names = "ssi-all",
+-				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+-				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+-				      "ssi.1", "ssi.0";
++			resets = <&cpg 106>;
++		};
+ 
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7790";
++			reg = <0 0xfeb00000 0 0x70000>,
++			      <0 0xfeb90000 0 0x1c>,
++			      <0 0xfeb94000 0 0x1c>;
++			reg-names = "du", "lvds.0", "lvds.1";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
++				 <&cpg CPG_MOD 725>;
++			clock-names = "du.0", "du.1", "du.2", "lvds.0",
++				      "lvds.1";
+ 			status = "disabled";
+ 
+-			rcar_sound,dvc {
+-				dvc0: dvc-0 {
+-					dmas = <&audma1 0xbc>;
+-					dma-names = "tx";
+-				};
+-				dvc1: dvc-1 {
+-					dmas = <&audma1 0xbe>;
+-					dma-names = "tx";
+-				};
+-			};
+-
+-			rcar_sound,mix {
+-				mix0: mix-0 { };
+-				mix1: mix-1 { };
+-			};
+-
+-			rcar_sound,ctu {
+-				ctu00: ctu-0 { };
+-				ctu01: ctu-1 { };
+-				ctu02: ctu-2 { };
+-				ctu03: ctu-3 { };
+-				ctu10: ctu-4 { };
+-				ctu11: ctu-5 { };
+-				ctu12: ctu-6 { };
+-				ctu13: ctu-7 { };
+-			};
+-
+-			rcar_sound,src {
+-				src0: src-0 {
+-					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x85>, <&audma1 0x9a>;
+-					dma-names = "rx", "tx";
+-				};
+-				src1: src-1 {
+-					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x87>, <&audma1 0x9c>;
+-					dma-names = "rx", "tx";
+-				};
+-				src2: src-2 {
+-					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x89>, <&audma1 0x9e>;
+-					dma-names = "rx", "tx";
+-				};
+-				src3: src-3 {
+-					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+-					dma-names = "rx", "tx";
+-				};
+-				src4: src-4 {
+-					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+-					dma-names = "rx", "tx";
+-				};
+-				src5: src-5 {
+-					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+-					dma-names = "rx", "tx";
+-				};
+-				src6: src-6 {
+-					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x91>, <&audma1 0xb4>;
+-					dma-names = "rx", "tx";
+-				};
+-				src7: src-7 {
+-					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x93>, <&audma1 0xb6>;
+-					dma-names = "rx", "tx";
+-				};
+-				src8: src-8 {
+-					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x95>, <&audma1 0xb8>;
+-					dma-names = "rx", "tx";
+-				};
+-				src9: src-9 {
+-					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x97>, <&audma1 0xba>;
+-					dma-names = "rx", "tx";
+-				};
+-			};
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
+ 
+-			rcar_sound,ssi {
+-				ssi0: ssi-0 {
+-					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x01>, <&audma1 0x02>,
+-					       <&audma0 0x15>, <&audma1 0x16>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi1: ssi-1 {
+-					 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x03>, <&audma1 0x04>,
+-					       <&audma0 0x49>, <&audma1 0x4a>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi2: ssi-2 {
+-					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x05>, <&audma1 0x06>,
+-					       <&audma0 0x63>, <&audma1 0x64>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi3: ssi-3 {
+-					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x07>, <&audma1 0x08>,
+-					       <&audma0 0x6f>, <&audma1 0x70>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi4: ssi-4 {
+-					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x09>, <&audma1 0x0a>,
+-					       <&audma0 0x71>, <&audma1 0x72>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi5: ssi-5 {
+-					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+-					       <&audma0 0x73>, <&audma1 0x74>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi6: ssi-6 {
+-					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+-					       <&audma0 0x75>, <&audma1 0x76>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi7: ssi-7 {
+-					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0f>, <&audma1 0x10>,
+-					       <&audma0 0x79>, <&audma1 0x7a>;
+-					dma-names = "rx", "tx", "rxu", "txu";
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
+ 				};
+-				ssi8: ssi-8 {
+-					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x11>, <&audma1 0x12>,
+-					       <&audma0 0x7b>, <&audma1 0x7c>;
+-					dma-names = "rx", "tx", "rxu", "txu";
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
+ 				};
+-				ssi9: ssi-9 {
+-					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x13>, <&audma1 0x14>,
+-					       <&audma0 0x7d>, <&audma1 0x7e>;
+-					dma-names = "rx", "tx", "rxu", "txu";
++				port@2 {
++					reg = <2>;
++					du_out_lvds1: endpoint {
++					};
+ 				};
+ 			};
+ 		};
+ 
+-		ipmmu_sy0: mmu@e6280000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6280000 0 0x1000>;
+-			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_sy1: mmu@e6290000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6290000 0 0x1000>;
+-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
+ 		};
+ 
+-		ipmmu_ds: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7790-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
+ 
+-		ipmmu_mp: mmu@ec680000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xec680000 0 0x1000>;
+-			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_mx: mmu@fe951000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xfe951000 0 0x1000>;
+-			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7790-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
+ 
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a7790",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1071-ARM-dts-r8a7790-sort-subnodes-of-root-node.patch b/patches/1071-ARM-dts-r8a7790-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..89daee2a3ceb47
--- /dev/null
+++ b/patches/1071-ARM-dts-r8a7790-sort-subnodes-of-root-node.patch
@@ -0,0 +1,158 @@
+From 5a18f84cb57b88718dfb51ad779546593cd2b27b Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:05 +0100
+Subject: [PATCH 1071/1795] ARM: dts: r8a7790: sort subnodes of root node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort subnodes of root node to aid maintenance.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 003d2d68b2a6fbf242506d4d579f3b5506224c88)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 104 ++++++++++++++++-----------------
+ 1 file changed, 52 insertions(+), 52 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 54c5a2d7ea89..3bbcc0b93f1c 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -40,6 +40,35 @@
+ 		vin3 = &vin3;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -158,6 +187,29 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1678,62 +1730,10 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External PCIe clock - can be overridden by the board */
+-	pcie_bus_clk: pcie_bus {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1072-ARM-dts-r8a7791-consistently-use-single-space-after.patch b/patches/1072-ARM-dts-r8a7791-consistently-use-single-space-after.patch
new file mode 100644
index 00000000000000..c9a36dcfedd145
--- /dev/null
+++ b/patches/1072-ARM-dts-r8a7791-consistently-use-single-space-after.patch
@@ -0,0 +1,137 @@
+From dd22e3053b635cdefc06b2c3c6ebae8f2b8a4b6c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:06 +0100
+Subject: [PATCH 1072/1795] ARM: dts: r8a7791: consistently use single space
+ after =
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Consistently use a single space after a =.
+
+This patch removes instances where a tab or multiple spaces are used
+instead.  It also avoids running over 80 columns in width in one of the
+lines where whitespace is updated.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5025c78b3b69914d4da8e75cf2390329cf04ca95)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 75 +++++++++++++++++-----------------
+ 1 file changed, 38 insertions(+), 37 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 8266a9b7cafd..38a9b8cb736d 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -237,9 +237,9 @@
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+-		compatible =	"renesas,thermal-r8a7791",
+-				"renesas,rcar-gen2-thermal",
+-				"renesas,rcar-thermal";
++		compatible = "renesas,thermal-r8a7791",
++			     "renesas,rcar-gen2-thermal",
++			     "renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+@@ -375,20 +375,20 @@
+ 	audma0: dma-controller@ec700000 {
+ 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ 		reg = <0 0xec700000 0 0x10000>;
+-		interrupts =	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "error",
+ 				"ch0", "ch1", "ch2", "ch3",
+ 				"ch4", "ch5", "ch6", "ch7",
+@@ -405,20 +405,20 @@
+ 	audma1: dma-controller@ec720000 {
+ 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+ 		reg = <0 0xec720000 0 0x10000>;
+-		interrupts =	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "error",
+ 				"ch0", "ch1", "ch2", "ch3",
+ 				"ch4", "ch5", "ch6", "ch7",
+@@ -1487,12 +1487,13 @@
+ 		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+ 		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+ 		 */
+-		compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
+-		reg =	<0 0xec500000 0 0x1000>, /* SCU */
+-			<0 0xec5a0000 0 0x100>,  /* ADG */
+-			<0 0xec540000 0 0x1000>, /* SSIU */
+-			<0 0xec541000 0 0x280>,  /* SSI */
+-			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++		compatible = "renesas,rcar_sound-r8a7791",
++			     "renesas,rcar_sound-gen2";
++		reg = <0 0xec500000 0 0x1000>, /* SCU */
++		      <0 0xec5a0000 0 0x100>,  /* ADG */
++		      <0 0xec540000 0 0x1000>, /* SSIU */
++		      <0 0xec541000 0 0x280>,  /* SSI */
++		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+ 		clocks = <&cpg CPG_MOD 1005>,
+-- 
+2.19.0
+
diff --git a/patches/1073-ARM-dts-r8a7791-add-soc-node.patch b/patches/1073-ARM-dts-r8a7791-add-soc-node.patch
new file mode 100644
index 00000000000000..f6c42859aab23e
--- /dev/null
+++ b/patches/1073-ARM-dts-r8a7791-add-soc-node.patch
@@ -0,0 +1,3045 @@
+From a3cf5807523cf746388166c408ba842e0f60e1e7 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:07 +0100
+Subject: [PATCH 1073/1795] ARM: dts: r8a7791: add soc node
+
+Add soc node to represent the bus and move all nodes with a base address
+into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and
+R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car
+Gen2 SoCs to this scheme.
+
+The ordering is derived from simply moving each node with an address up to
+before any nodes without a base address that occur before the soc node.  To
+improve maintainability follow-up patches will sort subnodes of both the
+new soc node and the root node.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit bb21803ea44076525a97e8a247acfa442b2bf115)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 2909 ++++++++++++++++----------------
+ 1 file changed, 1489 insertions(+), 1420 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 38a9b8cb736d..de2af2199731 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -17,7 +17,6 @@
+ 
+ / {
+ 	compatible = "renesas,r8a7791";
+-	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+@@ -102,1066 +101,1579 @@
+ 		};
+ 	};
+ 
+-	apmu@e6152000 {
+-		compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+-		reg = <0 0xe6152000 0 0x188>;
+-		cpus = <&cpu0 &cpu1>;
+-	};
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
+ 
+-	gic: interrupt-controller@f1001000 {
+-		compatible = "arm,gic-400";
+-		#interrupt-cells = <3>;
+-		#address-cells = <0>;
+-		interrupt-controller;
+-		reg = <0 0xf1001000 0 0x1000>,
+-			<0 0xf1002000 0 0x2000>,
+-			<0 0xf1004000 0 0x2000>,
+-			<0 0xf1006000 0 0x2000>;
+-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&cpg CPG_MOD 408>;
+-		clock-names = "clk";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 408>;
+-	};
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
+ 
+-	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6050000 0 0x50>;
+-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 0 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 912>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 912>;
+-	};
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
+ 
+-	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6051000 0 0x50>;
+-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 32 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 911>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 911>;
+-	};
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
+ 
+-	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6052000 0 0x50>;
+-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 64 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 910>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 910>;
+-	};
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
+ 
+-	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6053000 0 0x50>;
+-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 96 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 909>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 909>;
+-	};
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
+ 
+-	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6054000 0 0x50>;
+-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 128 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 908>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 908>;
+-	};
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
+ 
+-	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055000 0 0x50>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 160 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 907>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 907>;
+-	};
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 905>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 905>;
++		};
+ 
+-	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055400 0 0x50>;
+-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 192 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 905>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 905>;
+-	};
++		gpio7: gpio@e6055800 {
++			compatible = "renesas,gpio-r8a7791",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055800 0 0x50>;
++			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 224 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 904>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 904>;
++		};
+ 
+-	gpio7: gpio@e6055800 {
+-		compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055800 0 0x50>;
+-		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 224 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 904>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 904>;
+-	};
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7791";
++			reg = <0 0xe6060000 0 0x250>;
++		};
+ 
+-	thermal: thermal@e61f0000 {
+-		compatible = "renesas,thermal-r8a7791",
+-			     "renesas,rcar-gen2-thermal",
+-			     "renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+-		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 522>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 522>;
+-		#thermal-sensor-cells = <0>;
+-	};
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7791-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
+ 
+-	timer {
+-		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
++		apmu@e6152000 {
++			compatible = "renesas,r8a7791-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
+ 
+-	cmt0: timer@ffca0000 {
+-		compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
+-		reg = <0 0xffca0000 0 0x1004>;
+-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 124>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 124>;
+-
+-		status = "disabled";
+-	};
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7791-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
+ 
+-	cmt1: timer@e6130000 {
+-		compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
+-		reg = <0 0xe6130000 0 0x1004>;
+-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 329>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 329>;
+-
+-		status = "disabled";
+-	};
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7791-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
++		};
+ 
+-	irqc0: interrupt-controller@e61c0000 {
+-		compatible = "renesas,irqc-r8a7791", "renesas,irqc";
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		reg = <0 0xe61c0000 0 0x200>;
+-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 407>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 407>;
+-	};
++		irqc0: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a7791", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
+ 
+-	dmac0: dma-controller@e6700000 {
+-		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+-		reg = <0 0xe6700000 0 0x20000>;
+-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 219>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 219>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7791",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
++		};
+ 
+-	dmac1: dma-controller@e6720000 {
+-		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+-		reg = <0 0xe6720000 0 0x20000>;
+-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 218>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 218>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	audma0: dma-controller@ec700000 {
+-		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+-		reg = <0 0xec700000 0 0x10000>;
+-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 502>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 502>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	audma1: dma-controller@ec720000 {
+-		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
+-		reg = <0 0xec720000 0 0x10000>;
+-		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 501>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 501>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	usb_dmac0: dma-controller@e65a0000 {
+-		compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
+-		reg = <0 0xe65a0000 0 0x100>;
+-		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "ch0", "ch1";
+-		clocks = <&cpg CPG_MOD 330>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 330>;
+-		#dma-cells = <1>;
+-		dma-channels = <2>;
+-	};
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	usb_dmac1: dma-controller@e65b0000 {
+-		compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
+-		reg = <0 0xe65b0000 0 0x100>;
+-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "ch0", "ch1";
+-		clocks = <&cpg CPG_MOD 331>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 331>;
+-		#dma-cells = <1>;
+-		dma-channels = <2>;
+-	};
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	/* The memory map in the User's Manual maps the cores to bus numbers */
+-	i2c0: i2c@e6508000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6508000 0 0x40>;
+-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 931>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 931>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xffc80000 0 0x1000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	i2c1: i2c@e6518000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6518000 0 0x40>;
+-		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 930>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 930>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7791",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-	i2c2: i2c@e6530000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6530000 0 0x40>;
+-		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 929>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 929>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
+ 
+-	i2c3: i2c@e6540000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6540000 0 0x40>;
+-		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 928>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 928>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
+ 
+-	i2c4: i2c@e6520000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6520000 0 0x40>;
+-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 927>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 927>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
+ 
+-	i2c5: i2c@e6528000 {
+-		/* doesn't need pinmux */
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6528000 0 0x40>;
+-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 925>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 925>;
+-		i2c-scl-internal-delay-ns = <110>;
+-		status = "disabled";
+-	};
++		/* The memory map in the User's Manual maps the cores to
++		 * bus numbers
++		 */
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c6: i2c@e60b0000 {
+-		/* doesn't need pinmux */
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe60b0000 0 0x425>;
+-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 926>;
+-		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+-		       <&dmac1 0x77>, <&dmac1 0x78>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 926>;
+-		status = "disabled";
+-	};
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c7: i2c@e6500000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6500000 0 0x425>;
+-		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 318>;
+-		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-		       <&dmac1 0x61>, <&dmac1 0x62>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 318>;
+-		status = "disabled";
+-	};
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c8: i2c@e6510000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6510000 0 0x425>;
+-		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 323>;
+-		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-		       <&dmac1 0x65>, <&dmac1 0x66>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 323>;
+-		status = "disabled";
+-	};
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	pfc: pin-controller@e6060000 {
+-		compatible = "renesas,pfc-r8a7791";
+-		reg = <0 0xe6060000 0 0x250>;
+-	};
++		i2c4: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	mmcif0: mmc@ee200000 {
+-		compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
+-		reg = <0 0xee200000 0 0x80>;
+-		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 315>;
+-		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 315>;
+-		reg-io-width = <4>;
+-		status = "disabled";
+-		max-frequency = <97500000>;
+-	};
++		i2c5: i2c@e6528000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7791",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
++		};
+ 
+-	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7791",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee100000 0 0x328>;
+-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 314>;
+-		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-		       <&dmac1 0xcd>, <&dmac1 0xce>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <195000000>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 314>;
+-		status = "disabled";
+-	};
++		i2c6: i2c@e60b0000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7791",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
++			       <&dmac1 0x77>, <&dmac1 0x78>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 926>;
++			status = "disabled";
++		};
+ 
+-	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7791",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee140000 0 0x100>;
+-		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 312>;
+-		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 312>;
+-		status = "disabled";
+-	};
++		i2c7: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7791",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
+ 
+-	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7791",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee160000 0 0x100>;
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 311>;
+-		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 311>;
+-		status = "disabled";
+-	};
++		i2c8: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7791",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
+ 
+-	scifa0: serial@e6c40000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c40000 0 64>;
+-		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 204>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+-		       <&dmac1 0x21>, <&dmac1 0x22>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 204>;
+-		status = "disabled";
+-	};
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7791",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
+ 
+-	scifa1: serial@e6c50000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c50000 0 64>;
+-		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 203>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+-		       <&dmac1 0x25>, <&dmac1 0x26>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 203>;
+-		status = "disabled";
+-	};
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7791",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
+ 
+-	scifa2: serial@e6c60000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c60000 0 64>;
+-		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 202>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+-		       <&dmac1 0x27>, <&dmac1 0x28>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 202>;
+-		status = "disabled";
+-	};
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
++		};
+ 
+-	scifa3: serial@e6c70000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c70000 0 64>;
+-		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1106>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+-		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 1106>;
+-		status = "disabled";
+-	};
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7791-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
+ 
+-	scifa4: serial@e6c78000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c78000 0 64>;
+-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1107>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+-		       <&dmac1 0x1f>, <&dmac1 0x20>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 1107>;
+-		status = "disabled";
+-	};
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7791-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
+ 
+-	scifa5: serial@e6c80000 {
+-		compatible = "renesas,scifa-r8a7791",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c80000 0 64>;
+-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1108>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+-		       <&dmac1 0x23>, <&dmac1 0x24>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 1108>;
+-		status = "disabled";
+-	};
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7791",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	scifb0: serial@e6c20000 {
+-		compatible = "renesas,scifb-r8a7791",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c20000 0 0x100>;
+-		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 206>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+-		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 206>;
+-		status = "disabled";
+-	};
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7791",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	scifb1: serial@e6c30000 {
+-		compatible = "renesas,scifb-r8a7791",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c30000 0 0x100>;
+-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 207>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+-		       <&dmac1 0x19>, <&dmac1 0x1a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 207>;
+-		status = "disabled";
+-	};
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7791",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	scifb2: serial@e6ce0000 {
+-		compatible = "renesas,scifb-r8a7791",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6ce0000 0 0x100>;
+-		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 216>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+-		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 216>;
+-		status = "disabled";
+-	};
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7791", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	scif0: serial@e6e60000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e60000 0 64>;
+-		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+-		       <&dmac1 0x29>, <&dmac1 0x2a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 721>;
+-		status = "disabled";
+-	};
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
++			       <&dmac1 0x21>, <&dmac1 0x22>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
+ 
+-	scif1: serial@e6e68000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e68000 0 64>;
+-		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+-		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 720>;
+-		status = "disabled";
+-	};
++		scifa1: serial@e6c50000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
++			       <&dmac1 0x25>, <&dmac1 0x26>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
+ 
+-	adc: adc@e6e54000 {
+-		compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+-		reg = <0 0xe6e54000 0 64>;
+-		clocks = <&cpg CPG_MOD 901>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 901>;
+-		status = "disabled";
+-	};
++		scifa2: serial@e6c60000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c60000 0 64>;
++			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
++			       <&dmac1 0x27>, <&dmac1 0x28>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 202>;
++			status = "disabled";
++		};
+ 
+-	scif2: serial@e6e58000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e58000 0 64>;
+-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+-		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 719>;
+-		status = "disabled";
+-	};
++		scifa3: serial@e6c70000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c70000 0 64>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1106>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
++			       <&dmac1 0x1b>, <&dmac1 0x1c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 1106>;
++			status = "disabled";
++		};
+ 
+-	scif3: serial@e6ea8000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ea8000 0 64>;
+-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+-		       <&dmac1 0x2f>, <&dmac1 0x30>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 718>;
+-		status = "disabled";
+-	};
++		scifa4: serial@e6c78000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c78000 0 64>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1107>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
++			       <&dmac1 0x1f>, <&dmac1 0x20>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 1107>;
++			status = "disabled";
++		};
+ 
+-	scif4: serial@e6ee0000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee0000 0 64>;
+-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+-		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 715>;
+-		status = "disabled";
+-	};
++		scifa5: serial@e6c80000 {
++			compatible = "renesas,scifa-r8a7791",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c80000 0 64>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1108>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
++			       <&dmac1 0x23>, <&dmac1 0x24>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 1108>;
++			status = "disabled";
++		};
+ 
+-	scif5: serial@e6ee8000 {
+-		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee8000 0 64>;
+-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+-		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 714>;
+-		status = "disabled";
+-	};
++		scifb0: serial@e6c20000 {
++			compatible = "renesas,scifb-r8a7791",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c20000 0 0x100>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
++			       <&dmac1 0x3d>, <&dmac1 0x3e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
+ 
+-	hscif0: serial@e62c0000 {
+-		compatible = "renesas,hscif-r8a7791",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c0000 0 96>;
+-		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-		       <&dmac1 0x39>, <&dmac1 0x3a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 717>;
+-		status = "disabled";
+-	};
++		scifb1: serial@e6c30000 {
++			compatible = "renesas,scifb-r8a7791",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c30000 0 0x100>;
++			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
++			       <&dmac1 0x19>, <&dmac1 0x1a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
+ 
+-	hscif1: serial@e62c8000 {
+-		compatible = "renesas,hscif-r8a7791",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c8000 0 96>;
+-		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 716>;
+-		status = "disabled";
+-	};
++		scifb2: serial@e6ce0000 {
++			compatible = "renesas,scifb-r8a7791",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6ce0000 0 0x100>;
++			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 216>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
++			       <&dmac1 0x1d>, <&dmac1 0x1e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 216>;
++			status = "disabled";
++		};
+ 
+-	hscif2: serial@e62d0000 {
+-		compatible = "renesas,hscif-r8a7791",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62d0000 0 96>;
+-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+-		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 713>;
+-		status = "disabled";
+-	};
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 721>;
++			status = "disabled";
++		};
+ 
+-	icram0:	sram@e63a0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63a0000 0 0x12000>;
+-	};
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 720>;
++			status = "disabled";
++		};
+ 
+-	icram1:	sram@e63c0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63c0000 0 0x1000>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		ranges = <0 0 0xe63c0000 0x1000>;
++		scif2: serial@e6e58000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e58000 0 64>;
++			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 719>;
++			status = "disabled";
++		};
+ 
+-		smp-sram@0 {
+-			compatible = "renesas,smp-sram";
+-			reg = <0 0x10>;
++		scif3: serial@e6ea8000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ea8000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
++			       <&dmac1 0x2f>, <&dmac1 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 718>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7791",
+-			     "renesas,rcar-gen2-ether";
+-		reg = <0 0xee700000 0 0x400>;
+-		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 813>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 813>;
+-		phy-mode = "rmii";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		scif4: serial@e6ee0000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee0000 0 64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
++			       <&dmac1 0xfb>, <&dmac1 0xfc>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 715>;
++			status = "disabled";
++		};
+ 
+-	avb: ethernet@e6800000 {
+-		compatible = "renesas,etheravb-r8a7791",
+-			     "renesas,etheravb-rcar-gen2";
+-		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 812>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 812>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		scif5: serial@e6ee8000 {
++			compatible = "renesas,scif-r8a7791",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee8000 0 64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
++			       <&dmac1 0xfd>, <&dmac1 0xfe>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
++		};
+ 
+-	sata0: sata@ee300000 {
+-		compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+-		reg = <0 0xee300000 0 0x2000>;
+-		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 815>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 815>;
+-		status = "disabled";
+-	};
++		hscif0: serial@e62c0000 {
++			compatible = "renesas,hscif-r8a7791",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c0000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 717>;
++			status = "disabled";
++		};
+ 
+-	sata1: sata@ee500000 {
+-		compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+-		reg = <0 0xee500000 0 0x2000>;
+-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 814>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 814>;
+-		status = "disabled";
+-	};
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7791",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++		};
+ 
+-	hsusb: usb@e6590000 {
+-		compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
+-		reg = <0 0xe6590000 0 0x100>;
+-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-		       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-		dma-names = "ch0", "ch1", "ch2", "ch3";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		renesas,buswait = <4>;
+-		phys = <&usb0 1>;
+-		phy-names = "usb";
+-		status = "disabled";
+-	};
++		hscif2: serial@e62d0000 {
++			compatible = "renesas,hscif-r8a7791",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62d0000 0 96>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
++			       <&dmac1 0x3b>, <&dmac1 0x3c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 713>;
++			status = "disabled";
++		};
+ 
+-	usbphy: usb-phy@e6590100 {
+-		compatible = "renesas,usb-phy-r8a7791",
+-			     "renesas,rcar-gen2-usb-phy";
+-		reg = <0 0xe6590100 0 0x100>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		clock-names = "usbhs";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		status = "disabled";
++		msiof0: spi@e6e20000 {
++			compatible = "renesas,msiof-r8a7791",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e20000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 000>;
++			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
++			       <&dmac1 0x51>, <&dmac1 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-		usb0: usb-channel@0 {
+-			reg = <0>;
+-			#phy-cells = <1>;
++		msiof1: spi@e6e10000 {
++			compatible = "renesas,msiof-r8a7791",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e10000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
++			       <&dmac1 0x55>, <&dmac1 0x56>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 208>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+-		usb2: usb-channel@2 {
+-			reg = <2>;
+-			#phy-cells = <1>;
++
++		msiof2: spi@e6e00000 {
++			compatible = "renesas,msiof-r8a7791",
++				     "renesas,rcar-gen2-msiof";
++			reg = <0 0xe6e00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 205>;
++			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
++			       <&dmac1 0x41>, <&dmac1 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 205>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	vin0: video@e6ef0000 {
+-		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef0000 0 0x1000>;
+-		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 811>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 811>;
+-		status = "disabled";
+-	};
++		adc: adc@e6e54000 {
++			compatible = "renesas,r8a7791-gyroadc",
++				     "renesas,rcar-gyroadc";
++			reg = <0 0xe6e54000 0 64>;
++			clocks = <&cpg CPG_MOD 901>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 901>;
++			status = "disabled";
++		};
+ 
+-	vin1: video@e6ef1000 {
+-		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef1000 0 0x1000>;
+-		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 810>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 810>;
+-		status = "disabled";
+-	};
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7791",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
+ 
+-	vin2: video@e6ef2000 {
+-		compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef2000 0 0x1000>;
+-		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 809>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 809>;
+-		status = "disabled";
+-	};
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7791",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
+ 
+-	vsp@fe928000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe928000 0 0x8000>;
+-		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 131>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 131>;
+-	};
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7791",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
+ 
+-	vsp@fe930000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe930000 0 0x8000>;
+-		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 128>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 128>;
+-	};
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7791",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
++		};
+ 
+-	vsp@fe938000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe938000 0 0x8000>;
+-		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 127>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 127>;
+-	};
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7791",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			status = "disabled";
++		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7791",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++				 <&cpg CPG_CORE R8A7791_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0", "src.9", "src.8",
++				      "src.7", "src.6", "src.5", "src.4",
++				      "src.3", "src.2", "src.1", "src.0",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>,
++				 <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
++
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma1 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma1 0xbe>;
++					dma-names = "tx";
++				};
++			};
++
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
++
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
++
++			rcar_sound,src {
++				src0: src-0 {
++					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x85>, <&audma1 0x9a>;
++					dma-names = "rx", "tx";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma1 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma1 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma1 0xb4>;
++					dma-names = "rx", "tx";
++				};
++				src7: src-7 {
++					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x93>, <&audma1 0xb6>;
++					dma-names = "rx", "tx";
++				};
++				src8: src-8 {
++					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x95>, <&audma1 0xb8>;
++					dma-names = "rx", "tx";
++				};
++				src9: src-9 {
++					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x97>, <&audma1 0xba>;
++					dma-names = "rx", "tx";
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>,
++					       <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>,
++					       <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>,
++					       <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>,
++					       <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>,
++					       <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
++					       <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
++					       <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>,
++					       <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>,
++					       <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>,
++					       <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++			};
++		};
++
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7791",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7791",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	du: display@feb00000 {
+-		compatible = "renesas,du-r8a7791";
+-		reg = <0 0xfeb00000 0 0x40000>,
+-		      <0 0xfeb90000 0 0x1c>;
+-		reg-names = "du", "lvds.0";
+-		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 724>,
+-			 <&cpg CPG_MOD 723>,
+-			 <&cpg CPG_MOD 726>;
+-		clock-names = "du.0", "du.1", "lvds.0";
+-		status = "disabled";
+-
+-		ports {
++		xhci: usb@ee000000 {
++			compatible = "renesas,xhci-r8a7791",
++				     "renesas,rcar-gen2-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			phys = <&usb2 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7791",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7791",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7791",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7791",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7791",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7791",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
++
++		sata0: sata@ee300000 {
++			compatible = "renesas,sata-r8a7791",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee300000 0 0x2000>;
++			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 815>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 815>;
++			status = "disabled";
++		};
++
++		sata1: sata@ee500000 {
++			compatible = "renesas,sata-r8a7791",
++				     "renesas,rcar-gen2-sata";
++			reg = <0 0xee500000 0 0x2000>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 814>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 814>;
++			status = "disabled";
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7791",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-			port@0 {
+-				reg = <0>;
+-				du_out_rgb: endpoint {
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
++		pciec: pcie@fe000000 {
++			compatible = "renesas,pcie-r8a7791",
++				     "renesas,pcie-rcar-gen2";
++			reg = <0 0xfe000000 0 0x80000>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			bus-range = <0x00 0xff>;
++			device_type = "pci";
++			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
++				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
++				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
++				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
++			/* Map all possible DDR as inbound ranges */
++			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
++				      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
++			clock-names = "pcie", "pcie_bus";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 319>;
++			status = "disabled";
++		};
++
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
++
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
++
++		vsp@fe938000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe938000 0 0x8000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 127>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
++		};
++
++		jpu: jpeg-codec@fe980000 {
++			compatible = "renesas,jpu-r8a7791",
++				     "renesas,rcar-gen2-jpu";
++			reg = <0 0xfe980000 0 0x10300>;
++			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 106>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 106>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7791";
++			reg = <0 0xfeb00000 0 0x40000>,
++			      <0 0xfeb90000 0 0x1c>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 726>;
++			clock-names = "du.0", "du.1", "lvds.0";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
+ 				};
+-			};
+-			port@1 {
+-				reg = <1>;
+-				du_out_lvds0: endpoint {
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
+ 				};
+ 			};
+ 		};
+-	};
+ 
+-	can0: can@e6e80000 {
+-		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e80000 0 0x1000>;
+-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 916>;
+-		status = "disabled";
+-	};
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7791-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
+ 
+-	can1: can@e6e88000 {
+-		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e88000 0 0x1000>;
+-		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 915>;
+-		status = "disabled";
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7791-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
++		};
+ 	};
+ 
+-	jpu: jpeg-codec@fe980000 {
+-		compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
+-		reg = <0 0xfe980000 0 0x10300>;
+-		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 106>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 106>;
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+ 	/* External root clock */
+@@ -1222,447 +1734,4 @@
+ 		/* This value must be overridden by the board. */
+ 		clock-frequency = <0>;
+ 	};
+-
+-	cpg: clock-controller@e6150000 {
+-		compatible = "renesas,r8a7791-cpg-mssr";
+-		reg = <0 0xe6150000 0 0x1000>;
+-		clocks = <&extal_clk>, <&usb_extal_clk>;
+-		clock-names = "extal", "usb_extal";
+-		#clock-cells = <2>;
+-		#power-domain-cells = <0>;
+-		#reset-cells = <1>;
+-	};
+-
+-	rst: reset-controller@e6160000 {
+-		compatible = "renesas,r8a7791-rst";
+-		reg = <0 0xe6160000 0 0x0100>;
+-	};
+-
+-	prr: chipid@ff000044 {
+-		compatible = "renesas,prr";
+-		reg = <0 0xff000044 0 4>;
+-	};
+-
+-	sysc: system-controller@e6180000 {
+-		compatible = "renesas,r8a7791-sysc";
+-		reg = <0 0xe6180000 0 0x0200>;
+-		#power-domain-cells = <1>;
+-	};
+-
+-	qspi: spi@e6b10000 {
+-		compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+-		reg = <0 0xe6b10000 0 0x2c>;
+-		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 917>;
+-		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-		       <&dmac1 0x17>, <&dmac1 0x18>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 917>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof0: spi@e6e20000 {
+-		compatible = "renesas,msiof-r8a7791",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e20000 0 0x0064>;
+-		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 000>;
+-		dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+-		       <&dmac1 0x51>, <&dmac1 0x52>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 0>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof1: spi@e6e10000 {
+-		compatible = "renesas,msiof-r8a7791",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e10000 0 0x0064>;
+-		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 208>;
+-		dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+-		       <&dmac1 0x55>, <&dmac1 0x56>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 208>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	msiof2: spi@e6e00000 {
+-		compatible = "renesas,msiof-r8a7791",
+-			     "renesas,rcar-gen2-msiof";
+-		reg = <0 0xe6e00000 0 0x0064>;
+-		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 205>;
+-		dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+-		       <&dmac1 0x41>, <&dmac1 0x42>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 205>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	xhci: usb@ee000000 {
+-		compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
+-		reg = <0 0xee000000 0 0xc00>;
+-		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 328>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 328>;
+-		phys = <&usb2 1>;
+-		phy-names = "usb";
+-		status = "disabled";
+-	};
+-
+-	pci0: pci@ee090000 {
+-		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee090000 0 0xc00>,
+-		      <0 0xee080000 0 0x1100>;
+-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <0 0>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x800 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
+-		};
+-
+-		usb@2,0 {
+-			reg = <0x1000 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
+-		};
+-	};
+-
+-	pci1: pci@ee0d0000 {
+-		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee0d0000 0 0xc00>,
+-		      <0 0xee0c0000 0 0x1100>;
+-		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <1 1>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x10800 0 0 0 0>;
+-			phys = <&usb2 0>;
+-			phy-names = "usb";
+-		};
+-
+-		usb@2,0 {
+-			reg = <0x11000 0 0 0 0>;
+-			phys = <&usb2 0>;
+-			phy-names = "usb";
+-		};
+-	};
+-
+-	pciec: pcie@fe000000 {
+-		compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
+-		reg = <0 0xfe000000 0 0x80000>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		bus-range = <0x00 0xff>;
+-		device_type = "pci";
+-		ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+-			  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+-			  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+-			  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+-		/* Map all possible DDR as inbound ranges */
+-		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+-			      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+-		#interrupt-cells = <1>;
+-		interrupt-map-mask = <0 0 0 0>;
+-		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+-		clock-names = "pcie", "pcie_bus";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 319>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_sy0: mmu@e6280000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6280000 0 0x1000>;
+-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_sy1: mmu@e6290000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6290000 0 0x1000>;
+-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_ds: mmu@e6740000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6740000 0 0x1000>;
+-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mp: mmu@ec680000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xec680000 0 0x1000>;
+-		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mx: mmu@fe951000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xfe951000 0 0x1000>;
+-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_rt: mmu@ffc80000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xffc80000 0 0x1000>;
+-		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_gp: mmu@e62a0000 {
+-		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe62a0000 0 0x1000>;
+-		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	rcar_sound: sound@ec500000 {
+-		/*
+-		 * #sound-dai-cells is required
+-		 *
+-		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+-		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+-		 */
+-		compatible = "renesas,rcar_sound-r8a7791",
+-			     "renesas,rcar_sound-gen2";
+-		reg = <0 0xec500000 0 0x1000>, /* SCU */
+-		      <0 0xec5a0000 0 0x100>,  /* ADG */
+-		      <0 0xec540000 0 0x1000>, /* SSIU */
+-		      <0 0xec541000 0 0x280>,  /* SSI */
+-		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+-		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+-
+-		clocks = <&cpg CPG_MOD 1005>,
+-			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+-			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+-			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+-			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+-			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+-			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+-			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+-			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+-			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+-			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+-			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+-			 <&cpg CPG_CORE R8A7791_CLK_M2>;
+-		clock-names = "ssi-all",
+-				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-				"src.9", "src.8", "src.7", "src.6", "src.5",
+-				"src.4", "src.3", "src.2", "src.1", "src.0",
+-				"ctu.0", "ctu.1",
+-				"mix.0", "mix.1",
+-				"dvc.0", "dvc.1",
+-				"clk_a", "clk_b", "clk_c", "clk_i";
+-		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+-		resets = <&cpg 1005>,
+-			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+-			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+-			 <&cpg 1014>, <&cpg 1015>;
+-		reset-names = "ssi-all",
+-			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+-
+-		status = "disabled";
+-
+-		rcar_sound,dvc {
+-			dvc0: dvc-0 {
+-				dmas = <&audma1 0xbc>;
+-				dma-names = "tx";
+-			};
+-			dvc1: dvc-1 {
+-				dmas = <&audma1 0xbe>;
+-				dma-names = "tx";
+-			};
+-		};
+-
+-		rcar_sound,mix {
+-			mix0: mix-0 { };
+-			mix1: mix-1 { };
+-		};
+-
+-		rcar_sound,ctu {
+-			ctu00: ctu-0 { };
+-			ctu01: ctu-1 { };
+-			ctu02: ctu-2 { };
+-			ctu03: ctu-3 { };
+-			ctu10: ctu-4 { };
+-			ctu11: ctu-5 { };
+-			ctu12: ctu-6 { };
+-			ctu13: ctu-7 { };
+-		};
+-
+-		rcar_sound,src {
+-			src0: src-0 {
+-				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x85>, <&audma1 0x9a>;
+-				dma-names = "rx", "tx";
+-			};
+-			src1: src-1 {
+-				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x87>, <&audma1 0x9c>;
+-				dma-names = "rx", "tx";
+-			};
+-			src2: src-2 {
+-				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x89>, <&audma1 0x9e>;
+-				dma-names = "rx", "tx";
+-			};
+-			src3: src-3 {
+-				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src4: src-4 {
+-				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src5: src-5 {
+-				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+-				dma-names = "rx", "tx";
+-			};
+-			src6: src-6 {
+-				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x91>, <&audma1 0xb4>;
+-				dma-names = "rx", "tx";
+-			};
+-			src7: src-7 {
+-				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x93>, <&audma1 0xb6>;
+-				dma-names = "rx", "tx";
+-			};
+-			src8: src-8 {
+-				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x95>, <&audma1 0xb8>;
+-				dma-names = "rx", "tx";
+-			};
+-			src9: src-9 {
+-				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x97>, <&audma1 0xba>;
+-				dma-names = "rx", "tx";
+-			};
+-		};
+-
+-		rcar_sound,ssi {
+-			ssi0: ssi-0 {
+-				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi1: ssi-1 {
+-				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi2: ssi-2 {
+-				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi3: ssi-3 {
+-				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi4: ssi-4 {
+-				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi5: ssi-5 {
+-				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi6: ssi-6 {
+-				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi7: ssi-7 {
+-				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi8: ssi-8 {
+-				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi9: ssi-9 {
+-				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-		};
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1074-ARM-dts-r8a7791-sort-subnodes-of-root-node.patch b/patches/1074-ARM-dts-r8a7791-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..6dd62522ff0573
--- /dev/null
+++ b/patches/1074-ARM-dts-r8a7791-sort-subnodes-of-root-node.patch
@@ -0,0 +1,197 @@
+From 282483a609f9fd79315462e94dbca25663409765 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:08 +0100
+Subject: [PATCH 1074/1795] ARM: dts: r8a7791: sort subnodes of root node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort subnodes of root node to aid maintenance.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 21b05c52abe355e205eb133f2fe3dbc2520edeed)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 134 ++++++++++++++++-----------------
+ 1 file changed, 67 insertions(+), 67 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index de2af2199731..dc659351472f 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -39,6 +39,35 @@
+ 		vin2 = &vin2;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -82,23 +111,27 @@
+ 		};
+ 	};
+ 
+-	thermal-zones {
+-		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
+ 
+-			thermal-sensors = <&thermal>;
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
+ 
+-			trips {
+-				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
+-				};
+-			};
+-			cooling-maps {
+-			};
+-		};
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
+ 	};
+ 
+ 	soc {
+@@ -1668,6 +1701,25 @@
+ 		};
+ 	};
+ 
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive	= <0>;
++			polling-delay		= <0>;
++
++			thermal-sensors = <&thermal>;
++
++			trips {
++				cpu-crit {
++					temperature	= <95000>;
++					hysteresis	= <0>;
++					type		= "critical";
++				};
++			};
++			cooling-maps {
++			};
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -1676,62 +1728,10 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External PCIe clock - can be overridden by the board */
+-	pcie_bus_clk: pcie_bus {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1075-ARM-dts-r8a7792-sort-subnodes-of-soc-node.patch b/patches/1075-ARM-dts-r8a7792-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..bbaf5acc6157ca
--- /dev/null
+++ b/patches/1075-ARM-dts-r8a7792-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,578 @@
+From 6d407508dad9e7910c84e30be55755a297117c78 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:09 +0100
+Subject: [PATCH 1075/1795] ARM: dts: r8a7792: sort subnodes of soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3758e51b4b1e9cfd98be29b32b374582a00873c3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 498 ++++++++++++++++-----------------
+ 1 file changed, 249 insertions(+), 249 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 3be15a158bad..268987ff0201 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -101,63 +101,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6152000 {
+-			compatible = "renesas,r8a7792-apmu", "renesas,apmu";
+-			reg = <0 0xe6152000 0 0x188>;
+-			cpus = <&cpu0 &cpu1>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>,
+-			      <0 0xf1002000 0 0x2000>,
+-			      <0 0xf1004000 0 0x2000>,
+-			      <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+-				      IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+-		irqc: interrupt-controller@e61c0000 {
+-			compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			reg = <0 0xe61c0000 0 0x200>;
+-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 407>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 407>;
+-		};
+-
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7792-rst";
+-			reg = <0 0xe6160000 0 0x0100>;
+-		};
+-
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7792-sysc";
+-			reg = <0 0xe6180000 0 0x0200>;
+-			#power-domain-cells = <1>;
+-		};
+-
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7792";
+-			reg = <0 0xe6060000 0 0x144>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7792",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -338,6 +281,155 @@
+ 			resets = <&cpg 913>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7792";
++			reg = <0 0xe6060000 0 0x144>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7792-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>;
++			clock-names = "extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		apmu@e6152000 {
++			compatible = "renesas,r8a7792-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7792-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7792-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
++		};
++
++		irqc: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a7792", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
++
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
++
++		/* I2C doesn't need pinmux */
++		i2c0: i2c@e6508000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6518000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6530000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e6540000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c4: i2c@e6520000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c5: i2c@e6528000 {
++			compatible = "renesas,i2c-r8a7792",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <110>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		dmac0: dma-controller@e6700000 {
+ 			compatible = "renesas,dmac-r8a7792",
+ 				     "renesas,rcar-dmac";
+@@ -404,6 +496,35 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7792",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7792", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		scif0: serial@e6e60000 {
+ 			compatible = "renesas,scif-r8a7792",
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+@@ -500,162 +621,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
+-		};
+-
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7792",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			clocks = <&cpg CPG_MOD 314>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
+-			status = "disabled";
+-		};
+-
+-		jpu: jpeg-codec@fe980000 {
+-			compatible = "renesas,jpu-r8a7792",
+-				     "renesas,rcar-gen2-jpu";
+-			reg = <0 0xfe980000 0 0x10300>;
+-			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 106>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 106>;
+-		};
+-
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7792",
+-				     "renesas,etheravb-rcar-gen2";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		/* I2C doesn't need pinmux */
+-		i2c0: i2c@e6508000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c1: i2c@e6518000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6518000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c2: i2c@e6530000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6530000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c3: i2c@e6540000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6540000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c4: i2c@e6520000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6520000 0 0x40>;
+-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 927>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 927>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c5: i2c@e6528000 {
+-			compatible = "renesas,i2c-r8a7792",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6528000 0 0x40>;
+-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 925>;
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 925>;
+-			i2c-scl-internal-delay-ns = <110>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+-			resets = <&cpg 917>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+ 		msiof0: spi@e6e20000 {
+ 			compatible = "renesas,msiof-r8a7792",
+ 				     "renesas,rcar-gen2-msiof";
+@@ -688,34 +653,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7792";
+-			reg = <0 0xfeb00000 0 0x40000>;
+-			reg-names = "du";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>,
+-				 <&cpg CPG_MOD 723>;
+-			clock-names = "du.0", "du.1";
+-			status = "disabled";
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb0: endpoint {
+-					};
+-				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_rgb1: endpoint {
+-					};
+-				};
+-			};
+-		};
+-
+ 		can0: can@e6e80000 {
+ 			compatible = "renesas,can-r8a7792",
+ 				     "renesas,rcar-gen2-can";
+@@ -808,6 +745,36 @@
+ 			status = "disabled";
+ 		};
+ 
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7792",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			clocks = <&cpg CPG_MOD 314>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>,
++			      <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>,
++			      <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
++				      IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
+ 		vsp@fe928000 {
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe928000 0 0x8000>;
+@@ -835,14 +802,47 @@
+ 			resets = <&cpg 127>;
+ 		};
+ 
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7792-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>;
+-			clock-names = "extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
++		jpu: jpeg-codec@fe980000 {
++			compatible = "renesas,jpu-r8a7792",
++				     "renesas,rcar-gen2-jpu";
++			reg = <0 0xfe980000 0 0x10300>;
++			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 106>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 106>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7792";
++			reg = <0 0xfeb00000 0 0x40000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb0: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_rgb1: endpoint {
++					};
++				};
++			};
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1076-ARM-dts-r8a7793-consistently-use-single-space-after.patch b/patches/1076-ARM-dts-r8a7793-consistently-use-single-space-after.patch
new file mode 100644
index 00000000000000..07c7fcc021e14e
--- /dev/null
+++ b/patches/1076-ARM-dts-r8a7793-consistently-use-single-space-after.patch
@@ -0,0 +1,67 @@
+From 37bcde232686de3f0b58c97d4675ae5a06ca324e Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:10 +0100
+Subject: [PATCH 1076/1795] ARM: dts: r8a7793: consistently use single space
+ after =
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Consistently use a single space after a =.
+
+This patch removes instances where a tab is used instead.  It also avoids
+running over 80 columns in width in one of the lines where whitespace is
+updated.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 93a4a46fa1a6b2cf51cfbdd2e46572e5d4dad57d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index e95f4fb44dc4..ea4bc06c8e8a 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -228,9 +228,9 @@
+ 	};
+ 
+ 	thermal: thermal@e61f0000 {
+-		compatible =	"renesas,thermal-r8a7793",
+-				"renesas,rcar-gen2-thermal",
+-				"renesas,rcar-thermal";
++		compatible = "renesas,thermal-r8a7793",
++			     "renesas,rcar-gen2-thermal",
++			     "renesas,rcar-thermal";
+ 		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&cpg CPG_MOD 522>;
+@@ -1174,12 +1174,13 @@
+ 		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+ 		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+ 		 */
+-		compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
+-		reg =	<0 0xec500000 0 0x1000>, /* SCU */
+-			<0 0xec5a0000 0 0x100>,  /* ADG */
+-			<0 0xec540000 0 0x1000>, /* SSIU */
+-			<0 0xec541000 0 0x280>,  /* SSI */
+-			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++		compatible = "renesas,rcar_sound-r8a7793",
++			     "renesas,rcar_sound-gen2";
++		reg = <0 0xec500000 0 0x1000>, /* SCU */
++		      <0 0xec5a0000 0 0x100>,  /* ADG */
++		      <0 0xec540000 0 0x1000>, /* SSIU */
++		      <0 0xec541000 0 0x280>,  /* SSI */
++		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+ 		clocks = <&cpg CPG_MOD 1005>,
+-- 
+2.19.0
+
diff --git a/patches/1077-ARM-dts-r8a7793-add-soc-node.patch b/patches/1077-ARM-dts-r8a7793-add-soc-node.patch
new file mode 100644
index 00000000000000..3988d12c0e3811
--- /dev/null
+++ b/patches/1077-ARM-dts-r8a7793-add-soc-node.patch
@@ -0,0 +1,2455 @@
+From e591dd2735cc9c033df4641c117d8bd8499c99c2 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:11 +0100
+Subject: [PATCH 1077/1795] ARM: dts: r8a7793: add soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add soc node to represent the bus and move all nodes with a base address
+into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and
+R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car
+Gen2 SoCs to this scheme.
+
+The ordering is derived from simply moving each node with an address up to
+before any nodes without a base address that occur before the soc node.  To
+improve maintainability follow-up patches will sort subnodes of both the
+new soc node and the root node.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit bff8f8c2feb7898e5dcdf451678041a1477cc9a2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 2325 ++++++++++++++++----------------
+ 1 file changed, 1193 insertions(+), 1132 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index ea4bc06c8e8a..d18a65c647bb 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -15,7 +15,6 @@
+ 
+ / {
+ 	compatible = "renesas,r8a7793";
+-	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+@@ -74,958 +73,1273 @@
+ 		};
+ 	};
+ 
+-	apmu@e6152000 {
+-		compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+-		reg = <0 0xe6152000 0 0x188>;
+-		cpus = <&cpu0 &cpu1>;
+-	};
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
+ 
+-	thermal-zones {
+-		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
+ 
+-			thermal-sensors = <&thermal>;
++		apmu@e6152000 {
++			compatible = "renesas,r8a7793-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
+ 
+-			trips {
+-				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
+-				};
+-			};
+-			cooling-maps {
+-			};
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>,
++				<0 0xf1002000 0 0x2000>,
++				<0 0xf1004000 0 0x2000>,
++				<0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
+ 		};
+-	};
+ 
+-	gic: interrupt-controller@f1001000 {
+-		compatible = "arm,gic-400";
+-		#interrupt-cells = <3>;
+-		#address-cells = <0>;
+-		interrupt-controller;
+-		reg = <0 0xf1001000 0 0x1000>,
+-			<0 0xf1002000 0 0x2000>,
+-			<0 0xf1004000 0 0x2000>,
+-			<0 0xf1006000 0 0x2000>;
+-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&cpg CPG_MOD 408>;
+-		clock-names = "clk";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 408>;
+-	};
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
+ 
+-	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6050000 0 0x50>;
+-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 0 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 912>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 912>;
+-	};
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
+ 
+-	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6051000 0 0x50>;
+-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 32 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 911>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 911>;
+-	};
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
+ 
+-	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6052000 0 0x50>;
+-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 64 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 910>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 910>;
+-	};
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
+ 
+-	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6053000 0 0x50>;
+-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 96 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 909>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 909>;
+-	};
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
+ 
+-	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6054000 0 0x50>;
+-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 128 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 908>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 908>;
+-	};
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
+ 
+-	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055000 0 0x50>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 160 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 907>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 907>;
+-	};
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 905>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 905>;
++		};
+ 
+-	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055400 0 0x50>;
+-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 192 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 905>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 905>;
+-	};
++		gpio7: gpio@e6055800 {
++			compatible = "renesas,gpio-r8a7793",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055800 0 0x50>;
++			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 224 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 904>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 904>;
++		};
+ 
+-	gpio7: gpio@e6055800 {
+-		compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055800 0 0x50>;
+-		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 224 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 904>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 904>;
+-	};
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7793",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
++		};
+ 
+-	thermal: thermal@e61f0000 {
+-		compatible = "renesas,thermal-r8a7793",
+-			     "renesas,rcar-gen2-thermal",
+-			     "renesas,rcar-thermal";
+-		reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+-		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 522>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 522>;
+-		#thermal-sensor-cells = <0>;
+-	};
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7793-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
+ 
+-	timer {
+-		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7793-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
++		};
+ 
+-	cmt0: timer@ffca0000 {
+-		compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
+-		reg = <0 0xffca0000 0 0x1004>;
+-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 124>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 124>;
+-
+-		status = "disabled";
+-	};
++		irqc0: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a7793", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
+ 
+-	cmt1: timer@e6130000 {
+-		compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
+-		reg = <0 0xe6130000 0 0x1004>;
+-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 329>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 329>;
+-
+-		status = "disabled";
+-	};
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	irqc0: interrupt-controller@e61c0000 {
+-		compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		reg = <0 0xe61c0000 0 0x200>;
+-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 407>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 407>;
+-	};
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	dmac0: dma-controller@e6700000 {
+-		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+-		reg = <0 0xe6700000 0 0x20000>;
+-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 219>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 219>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	dmac1: dma-controller@e6720000 {
+-		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+-		reg = <0 0xe6720000 0 0x20000>;
+-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 218>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 218>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	audma0: dma-controller@ec700000 {
+-		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+-		reg = <0 0xec700000 0 0x10000>;
+-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 502>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 502>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		/* The memory map in the User's Manual maps the cores to
++		 * bus numbers
++		 */
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	audma1: dma-controller@ec720000 {
+-		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+-		reg = <0 0xec720000 0 0x10000>;
+-		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12";
+-		clocks = <&cpg CPG_MOD 501>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 501>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	/* The memory map in the User's Manual maps the cores to bus numbers */
+-	i2c0: i2c@e6508000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6508000 0 0x40>;
+-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 931>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 931>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c1: i2c@e6518000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6518000 0 0x40>;
+-		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 930>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 930>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c2: i2c@e6530000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6530000 0 0x40>;
+-		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 929>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 929>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c4: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c3: i2c@e6540000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6540000 0 0x40>;
+-		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 928>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 928>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c5: i2c@e6528000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7793",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
++		};
+ 
+-	i2c4: i2c@e6520000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6520000 0 0x40>;
+-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 927>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 927>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c6: i2c@e60b0000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7793",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
++			       <&dmac1 0x77>, <&dmac1 0x78>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 926>;
++			status = "disabled";
++		};
+ 
+-	i2c5: i2c@e6528000 {
+-		/* doesn't need pinmux */
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6528000 0 0x40>;
+-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 925>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 925>;
+-		i2c-scl-internal-delay-ns = <110>;
+-		status = "disabled";
+-	};
++		i2c7: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7793",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
+ 
+-	i2c6: i2c@e60b0000 {
+-		/* doesn't need pinmux */
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe60b0000 0 0x425>;
+-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 926>;
+-		dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+-		       <&dmac1 0x77>, <&dmac1 0x78>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 926>;
+-		status = "disabled";
+-	};
++		i2c8: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7793",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
+ 
+-	i2c7: i2c@e6500000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6500000 0 0x425>;
+-		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 318>;
+-		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-		       <&dmac1 0x61>, <&dmac1 0x62>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 318>;
+-		status = "disabled";
+-	};
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7793";
++			reg = <0 0xe6060000 0 0x250>;
++		};
+ 
+-	i2c8: i2c@e6510000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6510000 0 0x425>;
+-		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 323>;
+-		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-		       <&dmac1 0x65>, <&dmac1 0x66>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 323>;
+-		status = "disabled";
+-	};
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
+ 
+-	pfc: pin-controller@e6060000 {
+-		compatible = "renesas,pfc-r8a7793";
+-		reg = <0 0xe6060000 0 0x250>;
+-	};
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
+ 
+-	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7793",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee100000 0 0x328>;
+-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 314>;
+-		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-		       <&dmac1 0xcd>, <&dmac1 0xce>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <195000000>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 314>;
+-		status = "disabled";
+-	};
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
+ 
+-	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7793",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee140000 0 0x100>;
+-		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 312>;
+-		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 312>;
+-		status = "disabled";
+-	};
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7793",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
+ 
+-	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7793",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee160000 0 0x100>;
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 311>;
+-		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 311>;
+-		status = "disabled";
+-	};
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
++			       <&dmac1 0x21>, <&dmac1 0x22>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
+ 
+-	mmcif0: mmc@ee200000 {
+-		compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+-		reg = <0 0xee200000 0 0x80>;
+-		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 315>;
+-		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 315>;
+-		reg-io-width = <4>;
+-		status = "disabled";
+-		max-frequency = <97500000>;
+-	};
++		scifa1: serial@e6c50000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
++			       <&dmac1 0x25>, <&dmac1 0x26>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
+ 
+-	scifa0: serial@e6c40000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c40000 0 64>;
+-		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 204>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+-		       <&dmac1 0x21>, <&dmac1 0x22>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 204>;
+-		status = "disabled";
+-	};
++		scifa2: serial@e6c60000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c60000 0 64>;
++			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
++			       <&dmac1 0x27>, <&dmac1 0x28>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 202>;
++			status = "disabled";
++		};
+ 
+-	scifa1: serial@e6c50000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c50000 0 64>;
+-		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 203>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+-		       <&dmac1 0x25>, <&dmac1 0x26>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 203>;
+-		status = "disabled";
+-	};
++		scifa3: serial@e6c70000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c70000 0 64>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1106>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
++			       <&dmac1 0x1b>, <&dmac1 0x1c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 1106>;
++			status = "disabled";
++		};
+ 
+-	scifa2: serial@e6c60000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c60000 0 64>;
+-		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 202>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+-		       <&dmac1 0x27>, <&dmac1 0x28>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 202>;
+-		status = "disabled";
+-	};
++		scifa4: serial@e6c78000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c78000 0 64>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1107>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
++			       <&dmac1 0x1f>, <&dmac1 0x20>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 1107>;
++			status = "disabled";
++		};
+ 
+-	scifa3: serial@e6c70000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c70000 0 64>;
+-		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1106>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+-		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 1106>;
+-		status = "disabled";
+-	};
++		scifa5: serial@e6c80000 {
++			compatible = "renesas,scifa-r8a7793",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c80000 0 64>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1108>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
++			       <&dmac1 0x23>, <&dmac1 0x24>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 1108>;
++			status = "disabled";
++		};
+ 
+-	scifa4: serial@e6c78000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c78000 0 64>;
+-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1107>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+-		       <&dmac1 0x1f>, <&dmac1 0x20>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 1107>;
+-		status = "disabled";
+-	};
++		scifb0: serial@e6c20000 {
++			compatible = "renesas,scifb-r8a7793",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c20000 0 0x100>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
++			       <&dmac1 0x3d>, <&dmac1 0x3e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
+ 
+-	scifa5: serial@e6c80000 {
+-		compatible = "renesas,scifa-r8a7793",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c80000 0 64>;
+-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1108>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+-		       <&dmac1 0x23>, <&dmac1 0x24>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 1108>;
+-		status = "disabled";
+-	};
++		scifb1: serial@e6c30000 {
++			compatible = "renesas,scifb-r8a7793",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c30000 0 0x100>;
++			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
++			       <&dmac1 0x19>, <&dmac1 0x1a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
+ 
+-	scifb0: serial@e6c20000 {
+-		compatible = "renesas,scifb-r8a7793",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c20000 0 0x100>;
+-		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 206>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+-		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 206>;
+-		status = "disabled";
+-	};
++		scifb2: serial@e6ce0000 {
++			compatible = "renesas,scifb-r8a7793",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6ce0000 0 0x100>;
++			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 216>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
++			       <&dmac1 0x1d>, <&dmac1 0x1e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 216>;
++			status = "disabled";
++		};
+ 
+-	scifb1: serial@e6c30000 {
+-		compatible = "renesas,scifb-r8a7793",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c30000 0 0x100>;
+-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 207>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+-		       <&dmac1 0x19>, <&dmac1 0x1a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 207>;
+-		status = "disabled";
+-	};
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 721>;
++			status = "disabled";
++		};
+ 
+-	scifb2: serial@e6ce0000 {
+-		compatible = "renesas,scifb-r8a7793",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6ce0000 0 0x100>;
+-		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 216>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+-		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 216>;
+-		status = "disabled";
+-	};
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 720>;
++			status = "disabled";
++		};
+ 
+-	scif0: serial@e6e60000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e60000 0 64>;
+-		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+-		       <&dmac1 0x29>, <&dmac1 0x2a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 721>;
+-		status = "disabled";
+-	};
++		scif2: serial@e6e58000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e58000 0 64>;
++			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 719>;
++			status = "disabled";
++		};
+ 
+-	scif1: serial@e6e68000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e68000 0 64>;
+-		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+-		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 720>;
+-		status = "disabled";
+-	};
++		scif3: serial@e6ea8000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ea8000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
++			       <&dmac1 0x2f>, <&dmac1 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 718>;
++			status = "disabled";
++		};
+ 
+-	scif2: serial@e6e58000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e58000 0 64>;
+-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+-		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 719>;
+-		status = "disabled";
+-	};
++		scif4: serial@e6ee0000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee0000 0 64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
++			       <&dmac1 0xfb>, <&dmac1 0xfc>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 715>;
++			status = "disabled";
++		};
+ 
+-	scif3: serial@e6ea8000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ea8000 0 64>;
+-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+-		       <&dmac1 0x2f>, <&dmac1 0x30>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 718>;
+-		status = "disabled";
+-	};
++		scif5: serial@e6ee8000 {
++			compatible = "renesas,scif-r8a7793",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee8000 0 64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
++			       <&dmac1 0xfd>, <&dmac1 0xfe>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
++		};
+ 
+-	scif4: serial@e6ee0000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee0000 0 64>;
+-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+-		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 715>;
+-		status = "disabled";
+-	};
++		hscif0: serial@e62c0000 {
++			compatible = "renesas,hscif-r8a7793",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c0000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 717>;
++			status = "disabled";
++		};
+ 
+-	scif5: serial@e6ee8000 {
+-		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee8000 0 64>;
+-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+-		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 714>;
+-		status = "disabled";
+-	};
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7793",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++		};
+ 
+-	hscif0: serial@e62c0000 {
+-		compatible = "renesas,hscif-r8a7793",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c0000 0 96>;
+-		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-		       <&dmac1 0x39>, <&dmac1 0x3a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 717>;
+-		status = "disabled";
+-	};
++		hscif2: serial@e62d0000 {
++			compatible = "renesas,hscif-r8a7793",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62d0000 0 96>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
++			       <&dmac1 0x3b>, <&dmac1 0x3c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 713>;
++			status = "disabled";
++		};
+ 
+-	hscif1: serial@e62c8000 {
+-		compatible = "renesas,hscif-r8a7793",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c8000 0 96>;
+-		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 716>;
+-		status = "disabled";
+-	};
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
+ 
+-	hscif2: serial@e62d0000 {
+-		compatible = "renesas,hscif-r8a7793",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62d0000 0 96>;
+-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+-		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 713>;
+-		status = "disabled";
+-	};
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
+ 
+-	icram0:	sram@e63a0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63a0000 0 0x12000>;
+-	};
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
+ 
+-	icram1:	sram@e63c0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63c0000 0 0x1000>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		ranges = <0 0 0xe63c0000 0x1000>;
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7793",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-		smp-sram@0 {
+-			compatible = "renesas,smp-sram";
+-			reg = <0 0x10>;
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7793",
+-			     "renesas,rcar-gen2-ether";
+-		reg = <0 0xee700000 0 0x400>;
+-		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 813>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 813>;
+-		phy-mode = "rmii";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
++		};
+ 
+-	vin0: video@e6ef0000 {
+-		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef0000 0 0x1000>;
+-		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 811>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 811>;
+-		status = "disabled";
+-	};
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			status = "disabled";
++		};
+ 
+-	vin1: video@e6ef1000 {
+-		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef1000 0 0x1000>;
+-		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 810>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 810>;
+-		status = "disabled";
+-	};
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7793", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	vin2: video@e6ef2000 {
+-		compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef2000 0 0x1000>;
+-		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 809>;
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 809>;
+-		status = "disabled";
+-	};
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7793";
++			reg = <0 0xfeb00000 0 0x40000>,
++			      <0 0xfeb90000 0 0x1c>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 726>;
++			clock-names = "du.0", "du.1", "lvds.0";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
+ 
+-	qspi: spi@e6b10000 {
+-		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+-		reg = <0 0xe6b10000 0 0x2c>;
+-		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 917>;
+-		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-		       <&dmac1 0x17>, <&dmac1 0x18>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 917>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7793",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
+ 
+-	du: display@feb00000 {
+-		compatible = "renesas,du-r8a7793";
+-		reg = <0 0xfeb00000 0 0x40000>,
+-		      <0 0xfeb90000 0 0x1c>;
+-		reg-names = "du", "lvds.0";
+-		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 724>,
+-			 <&cpg CPG_MOD 723>,
+-			 <&cpg CPG_MOD 726>;
+-		clock-names = "du.0", "du.1", "lvds.0";
+-		status = "disabled";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7793",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7793-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7793-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
++		};
++
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
+ 
+-			port@0 {
+-				reg = <0>;
+-				du_out_rgb: endpoint {
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xffc80000 0 0x1000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7793",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
++				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
++				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
++				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
++				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
++				 <&cpg CPG_CORE R8A7793_CLK_M2>;
++			clock-names = "ssi-all",
++					"ssi.9", "ssi.8", "ssi.7", "ssi.6",
++					"ssi.5", "ssi.4", "ssi.3", "ssi.2",
++					"ssi.1", "ssi.0",
++					"src.9", "src.8", "src.7", "src.6",
++					"src.5", "src.4", "src.3", "src.2",
++					"src.1", "src.0",
++					"dvc.0", "dvc.1",
++					"clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>,
++				 <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
++
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma1 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma1 0xbe>;
++					dma-names = "tx";
+ 				};
+ 			};
+-			port@1 {
+-				reg = <1>;
+-				du_out_lvds0: endpoint {
++
++			rcar_sound,src {
++				src0: src-0 {
++					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x85>, <&audma1 0x9a>;
++					dma-names = "rx", "tx";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma1 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma1 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma1 0xb4>;
++					dma-names = "rx", "tx";
++				};
++				src7: src-7 {
++					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x93>, <&audma1 0xb6>;
++					dma-names = "rx", "tx";
++				};
++				src8: src-8 {
++					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x95>, <&audma1 0xb8>;
++					dma-names = "rx", "tx";
++				};
++				src9: src-9 {
++					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x97>, <&audma1 0xba>;
++					dma-names = "rx", "tx";
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>,
++					       <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>,
++					       <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>,
++					       <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>,
++					       <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>,
++					       <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
++					       <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
++					       <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>,
++					       <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>,
++					       <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>,
++					       <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
+ 				};
+ 			};
+ 		};
++
++		/* Special CPG clocks */
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7793-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
+ 	};
+ 
+-	can0: can@e6e80000 {
+-		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e80000 0 0x1000>;
+-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 916>;
+-		status = "disabled";
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive	= <0>;
++			polling-delay		= <0>;
++
++			thermal-sensors = <&thermal>;
++
++			trips {
++				cpu-crit {
++					temperature	= <95000>;
++					hysteresis	= <0>;
++					type		= "critical";
++				};
++			};
++			cooling-maps {
++			};
++		};
+ 	};
+ 
+-	can1: can@e6e88000 {
+-		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e88000 0 0x1000>;
+-		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 915>;
+-		status = "disabled";
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+ 	/* External root clock */
+@@ -1079,257 +1393,4 @@
+ 		/* This value must be overridden by the board. */
+ 		clock-frequency = <0>;
+ 	};
+-
+-	/* Special CPG clocks */
+-	cpg: clock-controller@e6150000 {
+-		compatible = "renesas,r8a7793-cpg-mssr";
+-		reg = <0 0xe6150000 0 0x1000>;
+-		clocks = <&extal_clk>, <&usb_extal_clk>;
+-		clock-names = "extal", "usb_extal";
+-		#clock-cells = <2>;
+-		#power-domain-cells = <0>;
+-		#reset-cells = <1>;
+-	};
+-
+-	rst: reset-controller@e6160000 {
+-		compatible = "renesas,r8a7793-rst";
+-		reg = <0 0xe6160000 0 0x0100>;
+-	};
+-
+-	prr: chipid@ff000044 {
+-		compatible = "renesas,prr";
+-		reg = <0 0xff000044 0 4>;
+-	};
+-
+-	sysc: system-controller@e6180000 {
+-		compatible = "renesas,r8a7793-sysc";
+-		reg = <0 0xe6180000 0 0x0200>;
+-		#power-domain-cells = <1>;
+-	};
+-
+-	ipmmu_sy0: mmu@e6280000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6280000 0 0x1000>;
+-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_sy1: mmu@e6290000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6290000 0 0x1000>;
+-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_ds: mmu@e6740000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6740000 0 0x1000>;
+-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mp: mmu@ec680000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xec680000 0 0x1000>;
+-		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mx: mmu@fe951000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xfe951000 0 0x1000>;
+-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_rt: mmu@ffc80000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xffc80000 0 0x1000>;
+-		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_gp: mmu@e62a0000 {
+-		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe62a0000 0 0x1000>;
+-		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	rcar_sound: sound@ec500000 {
+-		/*
+-		 * #sound-dai-cells is required
+-		 *
+-		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+-		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+-		 */
+-		compatible = "renesas,rcar_sound-r8a7793",
+-			     "renesas,rcar_sound-gen2";
+-		reg = <0 0xec500000 0 0x1000>, /* SCU */
+-		      <0 0xec5a0000 0 0x100>,  /* ADG */
+-		      <0 0xec540000 0 0x1000>, /* SSIU */
+-		      <0 0xec541000 0 0x280>,  /* SSI */
+-		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+-		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+-
+-		clocks = <&cpg CPG_MOD 1005>,
+-			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+-			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+-			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+-			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+-			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+-			 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+-			 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+-			 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+-			 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+-			 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+-			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+-			 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+-			 <&cpg CPG_CORE R8A7793_CLK_M2>;
+-		clock-names = "ssi-all",
+-				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-				"src.9", "src.8", "src.7", "src.6", "src.5",
+-				"src.4", "src.3", "src.2", "src.1", "src.0",
+-				"dvc.0", "dvc.1",
+-				"clk_a", "clk_b", "clk_c", "clk_i";
+-		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-		resets = <&cpg 1005>,
+-			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+-			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+-			 <&cpg 1014>, <&cpg 1015>;
+-		reset-names = "ssi-all",
+-			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+-
+-		status = "disabled";
+-
+-		rcar_sound,dvc {
+-			dvc0: dvc-0 {
+-				dmas = <&audma1 0xbc>;
+-				dma-names = "tx";
+-			};
+-			dvc1: dvc-1 {
+-				dmas = <&audma1 0xbe>;
+-				dma-names = "tx";
+-			};
+-		};
+-
+-		rcar_sound,src {
+-			src0: src-0 {
+-				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x85>, <&audma1 0x9a>;
+-				dma-names = "rx", "tx";
+-			};
+-			src1: src-1 {
+-				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x87>, <&audma1 0x9c>;
+-				dma-names = "rx", "tx";
+-			};
+-			src2: src-2 {
+-				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x89>, <&audma1 0x9e>;
+-				dma-names = "rx", "tx";
+-			};
+-			src3: src-3 {
+-				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src4: src-4 {
+-				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src5: src-5 {
+-				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+-				dma-names = "rx", "tx";
+-			};
+-			src6: src-6 {
+-				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x91>, <&audma1 0xb4>;
+-				dma-names = "rx", "tx";
+-			};
+-			src7: src-7 {
+-				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x93>, <&audma1 0xb6>;
+-				dma-names = "rx", "tx";
+-			};
+-			src8: src-8 {
+-				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x95>, <&audma1 0xb8>;
+-				dma-names = "rx", "tx";
+-			};
+-			src9: src-9 {
+-				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x97>, <&audma1 0xba>;
+-				dma-names = "rx", "tx";
+-			};
+-		};
+-
+-		rcar_sound,ssi {
+-			ssi0: ssi-0 {
+-				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi1: ssi-1 {
+-				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi2: ssi-2 {
+-				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi3: ssi-3 {
+-				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi4: ssi-4 {
+-				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi5: ssi-5 {
+-				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi6: ssi-6 {
+-				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi7: ssi-7 {
+-				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi8: ssi-8 {
+-				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi9: ssi-9 {
+-				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-		};
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1078-ARM-dts-r8a7793-sort-subnodes-of-soc-node.patch b/patches/1078-ARM-dts-r8a7793-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..1734eac24d02eb
--- /dev/null
+++ b/patches/1078-ARM-dts-r8a7793-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,987 @@
+From 9ffc209882306b843cade9dcfd03f5b50fef110d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:12 +0100
+Subject: [PATCH 1078/1795] ARM: dts: r8a7793: sort subnodes of soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 40ed6d16cf06fd8b1320c74cb6669356caf8daa9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 872 ++++++++++++++++-----------------
+ 1 file changed, 436 insertions(+), 436 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index d18a65c647bb..f2b58a28cee9 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -81,28 +81,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6152000 {
+-			compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+-			reg = <0 0xe6152000 0 0x188>;
+-			cpus = <&cpu0 &cpu1>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>,
+-				<0 0xf1002000 0 0x2000>,
+-				<0 0xf1004000 0 0x2000>,
+-				<0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7793",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -223,50 +201,37 @@
+ 			resets = <&cpg 904>;
+ 		};
+ 
+-		thermal: thermal@e61f0000 {
+-			compatible = "renesas,thermal-r8a7793",
+-				     "renesas,rcar-gen2-thermal",
+-				     "renesas,rcar-thermal";
+-			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 522>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 522>;
+-			#thermal-sensor-cells = <0>;
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7793";
++			reg = <0 0xe6060000 0 0x250>;
+ 		};
+ 
+-		cmt0: timer@ffca0000 {
+-			compatible = "renesas,r8a7793-cmt0",
+-				     "renesas,rcar-gen2-cmt0";
+-			reg = <0 0xffca0000 0 0x1004>;
+-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 124>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 124>;
++		/* Special CPG clocks */
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7793-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
+ 
+-			status = "disabled";
++		apmu@e6152000 {
++			compatible = "renesas,r8a7793-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
+ 		};
+ 
+-		cmt1: timer@e6130000 {
+-			compatible = "renesas,r8a7793-cmt1",
+-				     "renesas,rcar-gen2-cmt1";
+-			reg = <0 0xe6130000 0 0x1004>;
+-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 329>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7793-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
+ 
+-			status = "disabled";
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7793-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
+ 		};
+ 
+ 		irqc0: interrupt-controller@e61c0000 {
+@@ -289,132 +254,101 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		dmac0: dma-controller@e6700000 {
+-			compatible = "renesas,dmac-r8a7793",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6700000 0 0x20000>;
+-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 219>;
+-			clock-names = "fck";
++		thermal: thermal@e61f0000 {
++			compatible = "renesas,thermal-r8a7793",
++				     "renesas,rcar-gen2-thermal",
++				     "renesas,rcar-thermal";
++			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 219>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <0>;
+ 		};
+ 
+-		dmac1: dma-controller@e6720000 {
+-			compatible = "renesas,dmac-r8a7793",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6720000 0 0x20000>;
+-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7793",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		audma1: dma-controller@ec720000 {
+-			compatible = "renesas,dmac-r8a7793",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec720000 0 0x10000>;
+-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12";
+-			clocks = <&cpg CPG_MOD 501>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 501>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xffc80000 0 0x1000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7793",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
+ 		};
+ 
+ 		/* The memory map in the User's Manual maps the cores to
+@@ -557,70 +491,86 @@
+ 			status = "disabled";
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7793";
+-			reg = <0 0xe6060000 0 0x250>;
+-		};
+-
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7793",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
+-			status = "disabled";
+-		};
+-
+-		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7793",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee140000 0 0x100>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
+-			status = "disabled";
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7793",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee160000 0 0x100>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
+-			status = "disabled";
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		mmcif0: mmc@ee200000 {
+-			compatible = "renesas,mmcif-r8a7793",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee200000 0 0x80>;
+-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 315>;
+-			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7793", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 315>;
+-			reg-io-width = <4>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+-			max-frequency = <97500000>;
+ 		};
+ 
+ 		scifa0: serial@e6c40000 {
+@@ -902,117 +852,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
+-		};
+-
+-		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7793",
+-				     "renesas,rcar-gen2-ether";
+-			reg = <0 0xee700000 0 0x400>;
+-			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 813>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 813>;
+-			phy-mode = "rmii";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		vin0: video@e6ef0000 {
+-			compatible = "renesas,vin-r8a7793",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef0000 0 0x1000>;
+-			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 811>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 811>;
+-			status = "disabled";
+-		};
+-
+-		vin1: video@e6ef1000 {
+-			compatible = "renesas,vin-r8a7793",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef1000 0 0x1000>;
+-			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 810>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 810>;
+-			status = "disabled";
+-		};
+-
+-		vin2: video@e6ef2000 {
+-			compatible = "renesas,vin-r8a7793",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef2000 0 0x1000>;
+-			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 809>;
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 809>;
+-			status = "disabled";
+-		};
+-
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+-			resets = <&cpg 917>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7793";
+-			reg = <0 0xfeb00000 0 0x40000>,
+-			      <0 0xfeb90000 0 0x1c>;
+-			reg-names = "du", "lvds.0";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>,
+-				 <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 726>;
+-			clock-names = "du.0", "du.1", "lvds.0";
+-			status = "disabled";
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb: endpoint {
+-					};
+-				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_lvds0: endpoint {
+-					};
+-				};
+-			};
+-		};
+-
+ 		can0: can@e6e80000 {
+ 			compatible = "renesas,can-r8a7793",
+ 				     "renesas,rcar-gen2-can";
+@@ -1039,86 +878,36 @@
+ 			status = "disabled";
+ 		};
+ 
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7793-rst";
+-			reg = <0 0xe6160000 0 0x0100>;
+-		};
+-
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7793-sysc";
+-			reg = <0 0xe6180000 0 0x0200>;
+-			#power-domain-cells = <1>;
+-		};
+-
+-		ipmmu_sy0: mmu@e6280000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6280000 0 0x1000>;
+-			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_sy1: mmu@e6290000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6290000 0 0x1000>;
+-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_ds: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_mp: mmu@ec680000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xec680000 0 0x1000>;
+-			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_mx: mmu@fe951000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xfe951000 0 0x1000>;
+-			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_gp: mmu@e62a0000 {
+-			compatible = "renesas,ipmmu-r8a7793",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe62a0000 0 0x1000>;
+-			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7793",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1153,14 +942,14 @@
+ 				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ 				 <&cpg CPG_CORE R8A7793_CLK_M2>;
+ 			clock-names = "ssi-all",
+-					"ssi.9", "ssi.8", "ssi.7", "ssi.6",
+-					"ssi.5", "ssi.4", "ssi.3", "ssi.2",
+-					"ssi.1", "ssi.0",
+-					"src.9", "src.8", "src.7", "src.6",
+-					"src.5", "src.4", "src.3", "src.2",
+-					"src.1", "src.0",
+-					"dvc.0", "dvc.1",
+-					"clk_a", "clk_b", "clk_c", "clk_i";
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0",
++				      "src.9", "src.8", "src.7", "src.6",
++				      "src.5", "src.4", "src.3", "src.2",
++				      "src.1", "src.0",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 			resets = <&cpg 1005>,
+ 				 <&cpg 1006>, <&cpg 1007>,
+@@ -1303,15 +1092,226 @@
+ 			};
+ 		};
+ 
+-		/* Special CPG clocks */
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7793-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7793",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7793",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7793",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++			max-frequency = <97500000>;
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7793",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>,
++				<0 0xf1002000 0 0x2000>,
++				<0 0xf1004000 0 0x2000>,
++				<0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7793";
++			reg = <0 0xfeb00000 0 0x40000>,
++			      <0 0xfeb90000 0 0x1c>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 726>;
++			clock-names = "du.0", "du.1", "lvds.0";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7793-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7793-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1079-ARM-dts-r8a7793-sort-subnodes-of-root-node.patch b/patches/1079-ARM-dts-r8a7793-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..f306593a40da0c
--- /dev/null
+++ b/patches/1079-ARM-dts-r8a7793-sort-subnodes-of-root-node.patch
@@ -0,0 +1,146 @@
+From 2bb54d402d4af67ec643f1a072f0306c77c2b8f4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:13 +0100
+Subject: [PATCH 1079/1795] ARM: dts: r8a7793: sort subnodes of root node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ac24c5e52285154cca1c34488348e62f5288d6dc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 90 +++++++++++++++++-----------------
+ 1 file changed, 45 insertions(+), 45 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index f2b58a28cee9..aa7d7792fb13 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -31,6 +31,35 @@
+ 		spi0 = &qspi;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -73,6 +102,22 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1342,55 +1387,10 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1080-ARM-dts-r8a7794-consistently-use-single-space-after.patch b/patches/1080-ARM-dts-r8a7794-consistently-use-single-space-after.patch
new file mode 100644
index 00000000000000..b7f69bc479b511
--- /dev/null
+++ b/patches/1080-ARM-dts-r8a7794-consistently-use-single-space-after.patch
@@ -0,0 +1,84 @@
+From b7110b285c1cfb80315244dfedd646340c32faed Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:14 +0100
+Subject: [PATCH 1080/1795] ARM: dts: r8a7794: consistently use single space
+ after =
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Consistently use a single space after a =.
+
+This patch removes instances where a tab is used instead.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b190cce35ff90e392f89a3d45e0814cdbfd7434c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 38 +++++++++++++++++-----------------
+ 1 file changed, 19 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 106b4e1649ff..79263377ded3 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -319,20 +319,20 @@
+ 	audma0: dma-controller@ec700000 {
+ 		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+ 		reg = <0 0xec700000 0 0x10000>;
+-		interrupts =	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "error",
+ 				  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+ 				  "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+@@ -1186,11 +1186,11 @@
+ 		 */
+ 		compatible = "renesas,rcar_sound-r8a7794",
+ 			     "renesas,rcar_sound-gen2";
+-		reg =	<0 0xec500000 0 0x1000>, /* SCU */
+-			<0 0xec5a0000 0 0x100>,  /* ADG */
+-			<0 0xec540000 0 0x1000>, /* SSIU */
+-			<0 0xec541000 0 0x280>,  /* SSI */
+-			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
++		reg = <0 0xec500000 0 0x1000>, /* SCU */
++		      <0 0xec5a0000 0 0x100>,  /* ADG */
++		      <0 0xec540000 0 0x1000>, /* SSIU */
++		      <0 0xec541000 0 0x280>,  /* SSI */
++		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
+ 		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ 
+ 		clocks = <&cpg CPG_MOD 1005>,
+-- 
+2.19.0
+
diff --git a/patches/1081-ARM-dts-r8a7794-add-soc-node.patch b/patches/1081-ARM-dts-r8a7794-add-soc-node.patch
new file mode 100644
index 00000000000000..f76e8463f3bba2
--- /dev/null
+++ b/patches/1081-ARM-dts-r8a7794-add-soc-node.patch
@@ -0,0 +1,2496 @@
+From 362675a44828d2826a255085dad174bc16502a42 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:15 +0100
+Subject: [PATCH 1081/1795] ARM: dts: r8a7794: add soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add soc node to represent the bus and move all nodes with a base address
+into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and
+R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car
+Gen2 SoCs to this scheme.
+
+The ordering is derived from simply moving each node with an address up to
+before any nodes without a base address that occur before the soc node.  To
+improve maintainability follow-up patches will sort subnodes of both the
+new soc node and the root node.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0f2901d74a99e2e6c0aea2ef9b1820c7d0ed88e1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 2358 ++++++++++++++++----------------
+ 1 file changed, 1205 insertions(+), 1153 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 79263377ded3..0d65069b1a89 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -16,7 +16,6 @@
+ 
+ / {
+ 	compatible = "renesas,r8a7794";
+-	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+@@ -67,985 +66,1293 @@
+ 		};
+ 	};
+ 
+-	apmu@e6151000 {
+-		compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+-		reg = <0 0xe6151000 0 0x188>;
+-		cpus = <&cpu0 &cpu1>;
+-	};
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
+ 
+-	gic: interrupt-controller@f1001000 {
+-		compatible = "arm,gic-400";
+-		#interrupt-cells = <3>;
+-		#address-cells = <0>;
+-		interrupt-controller;
+-		reg = <0 0xf1001000 0 0x1000>,
+-			<0 0xf1002000 0 0x2000>,
+-			<0 0xf1004000 0 0x2000>,
+-			<0 0xf1006000 0 0x2000>;
+-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-		clocks = <&cpg CPG_MOD 408>;
+-		clock-names = "clk";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 408>;
+-	};
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
+ 
+-	gpio0: gpio@e6050000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6050000 0 0x50>;
+-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 0 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 912>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 912>;
+-	};
++		apmu@e6151000 {
++			compatible = "renesas,r8a7794-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
+ 
+-	gpio1: gpio@e6051000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6051000 0 0x50>;
+-		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 32 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 911>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 911>;
+-	};
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>,
++			      <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>,
++			      <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
+ 
+-	gpio2: gpio@e6052000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6052000 0 0x50>;
+-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 64 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 910>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 910>;
+-	};
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
++		};
+ 
+-	gpio3: gpio@e6053000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6053000 0 0x50>;
+-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 96 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 909>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 909>;
+-	};
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
++		};
+ 
+-	gpio4: gpio@e6054000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6054000 0 0x50>;
+-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 128 32>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 908>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 908>;
+-	};
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
++		};
+ 
+-	gpio5: gpio@e6055000 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055000 0 0x50>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 160 28>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 907>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 907>;
+-	};
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
++		};
+ 
+-	gpio6: gpio@e6055400 {
+-		compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+-		reg = <0 0xe6055400 0 0x50>;
+-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+-		#gpio-cells = <2>;
+-		gpio-controller;
+-		gpio-ranges = <&pfc 0 192 26>;
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		clocks = <&cpg CPG_MOD 905>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 905>;
+-	};
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
++		};
+ 
+-	cmt0: timer@ffca0000 {
+-		compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
+-		reg = <0 0xffca0000 0 0x1004>;
+-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 124>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 124>;
+-
+-		status = "disabled";
+-	};
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 28>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
++		};
+ 
+-	cmt1: timer@e6130000 {
+-		compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
+-		reg = <0 0xe6130000 0 0x1004>;
+-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 329>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 329>;
+-
+-		status = "disabled";
+-	};
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a7794",
++				     "renesas,rcar-gen2-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 905>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 905>;
++		};
+ 
+-	timer {
+-		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7794-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
+ 
+-	irqc0: interrupt-controller@e61c0000 {
+-		compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+-		#interrupt-cells = <2>;
+-		interrupt-controller;
+-		reg = <0 0xe61c0000 0 0x200>;
+-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 407>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 407>;
+-	};
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7794-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
++		};
+ 
+-	pfc: pin-controller@e6060000 {
+-		compatible = "renesas,pfc-r8a7794";
+-		reg = <0 0xe6060000 0 0x11c>;
+-	};
++		irqc0: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a7794", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 407>;
++		};
+ 
+-	dmac0: dma-controller@e6700000 {
+-		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+-		reg = <0 0xe6700000 0 0x20000>;
+-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 219>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 219>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7794";
++			reg = <0 0xe6060000 0 0x11c>;
++		};
+ 
+-	dmac1: dma-controller@e6720000 {
+-		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+-		reg = <0 0xe6720000 0 0x20000>;
+-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				"ch0", "ch1", "ch2", "ch3",
+-				"ch4", "ch5", "ch6", "ch7",
+-				"ch8", "ch9", "ch10", "ch11",
+-				"ch12", "ch13", "ch14";
+-		clocks = <&cpg CPG_MOD 218>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 218>;
+-		#dma-cells = <1>;
+-		dma-channels = <15>;
+-	};
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	audma0: dma-controller@ec700000 {
+-		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+-		reg = <0 0xec700000 0 0x10000>;
+-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error",
+-				  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+-				  "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+-				  "ch12";
+-		clocks = <&cpg CPG_MOD 502>;
+-		clock-names = "fck";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 502>;
+-		#dma-cells = <1>;
+-		dma-channels = <13>;
+-	};
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
+ 
+-	scifa0: serial@e6c40000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c40000 0 64>;
+-		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 204>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+-		       <&dmac1 0x21>, <&dmac1 0x22>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 204>;
+-		status = "disabled";
+-	};
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3", "ch4",
++					  "ch5", "ch6", "ch7", "ch8", "ch9",
++					  "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
+ 
+-	scifa1: serial@e6c50000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c50000 0 64>;
+-		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 203>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+-		       <&dmac1 0x25>, <&dmac1 0x26>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 203>;
+-		status = "disabled";
+-	};
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
++			       <&dmac1 0x21>, <&dmac1 0x22>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 204>;
++			status = "disabled";
++		};
+ 
+-	scifa2: serial@e6c60000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c60000 0 64>;
+-		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 202>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+-		       <&dmac1 0x27>, <&dmac1 0x28>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 202>;
+-		status = "disabled";
+-	};
++		scifa1: serial@e6c50000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
++			       <&dmac1 0x25>, <&dmac1 0x26>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 203>;
++			status = "disabled";
++		};
+ 
+-	scifa3: serial@e6c70000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c70000 0 64>;
+-		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1106>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+-		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 1106>;
+-		status = "disabled";
+-	};
++		scifa2: serial@e6c60000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c60000 0 64>;
++			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
++			       <&dmac1 0x27>, <&dmac1 0x28>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 202>;
++			status = "disabled";
++		};
+ 
+-	scifa4: serial@e6c78000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c78000 0 64>;
+-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1107>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+-		       <&dmac1 0x1f>, <&dmac1 0x20>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 1107>;
+-		status = "disabled";
+-	};
++		scifa3: serial@e6c70000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c70000 0 64>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1106>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
++			       <&dmac1 0x1b>, <&dmac1 0x1c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 1106>;
++			status = "disabled";
++		};
+ 
+-	scifa5: serial@e6c80000 {
+-		compatible = "renesas,scifa-r8a7794",
+-			     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-		reg = <0 0xe6c80000 0 64>;
+-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 1108>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+-		       <&dmac1 0x23>, <&dmac1 0x24>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 1108>;
+-		status = "disabled";
+-	};
++		scifa4: serial@e6c78000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c78000 0 64>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1107>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
++			       <&dmac1 0x1f>, <&dmac1 0x20>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 1107>;
++			status = "disabled";
++		};
+ 
+-	scifb0: serial@e6c20000 {
+-		compatible = "renesas,scifb-r8a7794",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c20000 0 0x100>;
+-		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 206>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+-		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 206>;
+-		status = "disabled";
+-	};
++		scifa5: serial@e6c80000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c80000 0 64>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1108>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
++			       <&dmac1 0x23>, <&dmac1 0x24>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 1108>;
++			status = "disabled";
++		};
+ 
+-	scifb1: serial@e6c30000 {
+-		compatible = "renesas,scifb-r8a7794",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6c30000 0 0x100>;
+-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 207>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+-		       <&dmac1 0x19>, <&dmac1 0x1a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 207>;
+-		status = "disabled";
+-	};
++		scifb0: serial@e6c20000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c20000 0 0x100>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
++			       <&dmac1 0x3d>, <&dmac1 0x3e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
+ 
+-	scifb2: serial@e6ce0000 {
+-		compatible = "renesas,scifb-r8a7794",
+-			     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-		reg = <0 0xe6ce0000 0 0x100>;
+-		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 216>;
+-		clock-names = "fck";
+-		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+-		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 216>;
+-		status = "disabled";
+-	};
++		scifb1: serial@e6c30000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c30000 0 0x100>;
++			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
++			       <&dmac1 0x19>, <&dmac1 0x1a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
+ 
+-	scif0: serial@e6e60000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e60000 0 64>;
+-		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+-		       <&dmac1 0x29>, <&dmac1 0x2a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 721>;
+-		status = "disabled";
+-	};
++		scifb2: serial@e6ce0000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6ce0000 0 0x100>;
++			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 216>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
++			       <&dmac1 0x1d>, <&dmac1 0x1e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 216>;
++			status = "disabled";
++		};
+ 
+-	scif1: serial@e6e68000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e68000 0 64>;
+-		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+-		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 720>;
+-		status = "disabled";
+-	};
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 721>;
++			status = "disabled";
++		};
+ 
+-	scif2: serial@e6e58000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6e58000 0 64>;
+-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+-		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 719>;
+-		status = "disabled";
+-	};
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 720>;
++			status = "disabled";
++		};
+ 
+-	scif3: serial@e6ea8000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ea8000 0 64>;
+-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+-		       <&dmac1 0x2f>, <&dmac1 0x30>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 718>;
+-		status = "disabled";
+-	};
++		scif2: serial@e6e58000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e58000 0 64>;
++			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 719>;
++			status = "disabled";
++		};
+ 
+-	scif4: serial@e6ee0000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee0000 0 64>;
+-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+-		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 715>;
+-		status = "disabled";
+-	};
++		scif3: serial@e6ea8000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ea8000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
++			       <&dmac1 0x2f>, <&dmac1 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 718>;
++			status = "disabled";
++		};
+ 
+-	scif5: serial@e6ee8000 {
+-		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+-			     "renesas,scif";
+-		reg = <0 0xe6ee8000 0 64>;
+-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+-		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 714>;
+-		status = "disabled";
+-	};
++		scif4: serial@e6ee0000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee0000 0 64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
++			       <&dmac1 0xfb>, <&dmac1 0xfc>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 715>;
++			status = "disabled";
++		};
+ 
+-	hscif0: serial@e62c0000 {
+-		compatible = "renesas,hscif-r8a7794",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c0000 0 96>;
+-		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-		       <&dmac1 0x39>, <&dmac1 0x3a>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 717>;
+-		status = "disabled";
+-	};
++		scif5: serial@e6ee8000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee8000 0 64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
++			       <&dmac1 0xfd>, <&dmac1 0xfe>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
++		};
+ 
+-	hscif1: serial@e62c8000 {
+-		compatible = "renesas,hscif-r8a7794",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62c8000 0 96>;
+-		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 716>;
+-		status = "disabled";
+-	};
++		hscif0: serial@e62c0000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c0000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 717>,
++				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 717>;
++			status = "disabled";
++		};
+ 
+-	hscif2: serial@e62d0000 {
+-		compatible = "renesas,hscif-r8a7794",
+-			     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-		reg = <0 0xe62d0000 0 96>;
+-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-			 <&scif_clk>;
+-		clock-names = "fck", "brg_int", "scif_clk";
+-		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+-		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 713>;
+-		status = "disabled";
+-	};
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>,
++				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++		};
+ 
+-	icram0:	sram@e63a0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63a0000 0 0x12000>;
+-	};
++		hscif2: serial@e62d0000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62d0000 0 96>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
++			       <&dmac1 0x3b>, <&dmac1 0x3c>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 713>;
++			status = "disabled";
++		};
+ 
+-	icram1:	sram@e63c0000 {
+-		compatible = "mmio-sram";
+-		reg = <0 0xe63c0000 0 0x1000>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		ranges = <0 0 0xe63c0000 0x1000>;
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
+ 
+-		smp-sram@0 {
+-			compatible = "renesas,smp-sram";
+-			reg = <0 0x10>;
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
+ 		};
+-	};
+ 
+-	ether: ethernet@ee700000 {
+-		compatible = "renesas,ether-r8a7794",
+-			     "renesas,rcar-gen2-ether";
+-		reg = <0 0xee700000 0 0x400>;
+-		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 813>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 813>;
+-		phy-mode = "rmii";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7794",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	avb: ethernet@e6800000 {
+-		compatible = "renesas,etheravb-r8a7794",
+-			     "renesas,etheravb-rcar-gen2";
+-		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 812>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 812>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7794",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	/* The memory map in the User's Manual maps the cores to bus numbers */
+-	i2c0: i2c@e6508000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6508000 0 0x40>;
+-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 931>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 931>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		/* The memory map in the User's Manual maps the cores to
++		 * bus numbers
++		 */
++		i2c0: i2c@e6508000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c1: i2c@e6518000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6518000 0 0x40>;
+-		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 930>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 930>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c1: i2c@e6518000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c2: i2c@e6530000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6530000 0 0x40>;
+-		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 929>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 929>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c2: i2c@e6530000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c3: i2c@e6540000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6540000 0 0x40>;
+-		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 928>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 928>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c3: i2c@e6540000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c4: i2c@e6520000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6520000 0 0x40>;
+-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 927>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 927>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c4: i2c@e6520000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c5: i2c@e6528000 {
+-		compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+-		reg = <0 0xe6528000 0 0x40>;
+-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 925>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 925>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c-scl-internal-delay-ns = <6>;
+-		status = "disabled";
+-	};
++		i2c5: i2c@e6528000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
+ 
+-	i2c6: i2c@e6500000 {
+-		compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6500000 0 0x425>;
+-		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 318>;
+-		dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-		       <&dmac1 0x61>, <&dmac1 0x62>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 318>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		i2c6: i2c@e6500000 {
++			compatible = "renesas,iic-r8a7794",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	i2c7: i2c@e6510000 {
+-		compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+-			     "renesas,rmobile-iic";
+-		reg = <0 0xe6510000 0 0x425>;
+-		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 323>;
+-		dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-		       <&dmac1 0x65>, <&dmac1 0x66>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 323>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		i2c7: i2c@e6510000 {
++			compatible = "renesas,iic-r8a7794",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	mmcif0: mmc@ee200000 {
+-		compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
+-		reg = <0 0xee200000 0 0x80>;
+-		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 315>;
+-		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-		       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 315>;
+-		reg-io-width = <4>;
+-		status = "disabled";
+-	};
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7794",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++		};
+ 
+-	sdhi0: sd@ee100000 {
+-		compatible = "renesas,sdhi-r8a7794",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee100000 0 0x328>;
+-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 314>;
+-		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-		       <&dmac1 0xcd>, <&dmac1 0xce>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <195000000>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 314>;
+-		status = "disabled";
+-	};
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
+ 
+-	sdhi1: sd@ee140000 {
+-		compatible = "renesas,sdhi-r8a7794",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee140000 0 0x100>;
+-		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 312>;
+-		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-		       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 312>;
+-		status = "disabled";
+-	};
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
+ 
+-	sdhi2: sd@ee160000 {
+-		compatible = "renesas,sdhi-r8a7794",
+-			     "renesas,rcar-gen2-sdhi";
+-		reg = <0 0xee160000 0 0x100>;
+-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 311>;
+-		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-		       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		max-frequency = <97500000>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 311>;
+-		status = "disabled";
+-	};
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
+ 
+-	qspi: spi@e6b10000 {
+-		compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+-		reg = <0 0xe6b10000 0 0x2c>;
+-		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 917>;
+-		dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-		       <&dmac1 0x17>, <&dmac1 0x18>;
+-		dma-names = "tx", "rx", "tx", "rx";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 917>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7794", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	vin0: video@e6ef0000 {
+-		compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef0000 0 0x1000>;
+-		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 811>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 811>;
+-		status = "disabled";
+-	};
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7794",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
+ 
+-	vin1: video@e6ef1000 {
+-		compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+-		reg = <0 0xe6ef1000 0 0x1000>;
+-		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 810>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 810>;
+-		status = "disabled";
+-	};
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7794",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			status = "disabled";
++		};
+ 
+-	pci0: pci@ee090000 {
+-		compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee090000 0 0xc00>,
+-		      <0 0xee080000 0 0x1100>;
+-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <0 0>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x800 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7794",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
+ 		};
+ 
+-		usb@2,0 {
+-			reg = <0x1000 0 0 0 0>;
+-			phys = <&usb0 0>;
+-			phy-names = "usb";
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7794",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
+ 		};
+-	};
+ 
+-	pci1: pci@ee0d0000 {
+-		compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+-		device_type = "pci";
+-		reg = <0 0xee0d0000 0 0xc00>,
+-		      <0 0xee0c0000 0 0x1100>;
+-		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 703>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 703>;
+-		status = "disabled";
+-
+-		bus-range = <1 1>;
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-		#interrupt-cells = <1>;
+-		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-		interrupt-map-mask = <0xff00 0 0 0x7>;
+-		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		usb@1,0 {
+-			reg = <0x10800 0 0 0 0>;
+-			phys = <&usb2 0>;
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7794",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
+ 			phy-names = "usb";
++			status = "disabled";
+ 		};
+ 
+-		usb@2,0 {
+-			reg = <0x11000 0 0 0 0>;
+-			phys = <&usb2 0>;
+-			phy-names = "usb";
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7794",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
+ 		};
+-	};
+ 
+-	hsusb: usb@e6590000 {
+-		compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
+-		reg = <0 0xe6590000 0 0x100>;
+-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		renesas,buswait = <4>;
+-		phys = <&usb0 1>;
+-		phy-names = "usb";
+-		status = "disabled";
+-	};
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
+ 
+-	usbphy: usb-phy@e6590100 {
+-		compatible = "renesas,usb-phy-r8a7794",
+-			     "renesas,rcar-gen2-usb-phy";
+-		reg = <0 0xe6590100 0 0x100>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		clocks = <&cpg CPG_MOD 704>;
+-		clock-names = "usbhs";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 704>;
+-		status = "disabled";
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
+ 
+-		usb0: usb-channel@0 {
+-			reg = <0>;
+-			#phy-cells = <1>;
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7794";
++			reg = <0 0xfeb00000 0 0x40000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb0: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_rgb1: endpoint {
++					};
++				};
++			};
+ 		};
+-		usb2: usb-channel@2 {
+-			reg = <2>;
+-			#phy-cells = <1>;
++
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7794",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
+ 		};
+-	};
+ 
+-	vsp@fe928000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe928000 0 0x8000>;
+-		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 131>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 131>;
+-	};
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7794",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
+ 
+-	vsp@fe930000 {
+-		compatible = "renesas,vsp1";
+-		reg = <0 0xfe930000 0 0x8000>;
+-		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 128>;
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 128>;
+-	};
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7794-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
+ 
+-	du: display@feb00000 {
+-		compatible = "renesas,du-r8a7794";
+-		reg = <0 0xfeb00000 0 0x40000>;
+-		reg-names = "du";
+-		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+-		clock-names = "du.0", "du.1";
+-		status = "disabled";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7794-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
+ 
+-			port@0 {
+-				reg = <0>;
+-				du_out_rgb0: endpoint {
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7794-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
++		};
++
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		rcar_sound: sound@ec500000 {
++			/*
++			 * #sound-dai-cells is required
++			 *
++			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
++			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
++			 */
++			compatible = "renesas,rcar_sound-r8a7794",
++				     "renesas,rcar_sound-gen2";
++			reg = <0 0xec500000 0 0x1000>, /* SCU */
++			      <0 0xec5a0000 0 0x100>,  /* ADG */
++			      <0 0xec540000 0 0x1000>, /* SSIU */
++			      <0 0xec541000 0 0x280>,  /* SSI */
++			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
++			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
++
++			clocks = <&cpg CPG_MOD 1005>,
++				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
++				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
++				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
++				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
++				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
++				 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
++				 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
++				 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
++				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
++				 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
++				 <&cpg CPG_CORE R8A7794_CLK_M2>;
++			clock-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0",
++				      "src.6", "src.5", "src.4", "src.3",
++				      "src.2", "src.1",
++				      "ctu.0", "ctu.1",
++				      "mix.0", "mix.1",
++				      "dvc.0", "dvc.1",
++				      "clk_a", "clk_b", "clk_c", "clk_i";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 1005>,
++				 <&cpg 1006>, <&cpg 1007>,
++				 <&cpg 1008>, <&cpg 1009>,
++				 <&cpg 1010>, <&cpg 1011>,
++				 <&cpg 1012>, <&cpg 1013>,
++				 <&cpg 1014>, <&cpg 1015>;
++			reset-names = "ssi-all",
++				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
++				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
++				      "ssi.1", "ssi.0";
++
++			status = "disabled";
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++					dmas = <&audma0 0xbc>;
++					dma-names = "tx";
++				};
++				dvc1: dvc-1 {
++					dmas = <&audma0 0xbe>;
++					dma-names = "tx";
+ 				};
+ 			};
+-			port@1 {
+-				reg = <1>;
+-				du_out_rgb1: endpoint {
++
++			rcar_sound,mix {
++				mix0: mix-0 { };
++				mix1: mix-1 { };
++			};
++
++			rcar_sound,ctu {
++				ctu00: ctu-0 { };
++				ctu01: ctu-1 { };
++				ctu02: ctu-2 { };
++				ctu03: ctu-3 { };
++				ctu10: ctu-4 { };
++				ctu11: ctu-5 { };
++				ctu12: ctu-6 { };
++				ctu13: ctu-7 { };
++			};
++
++			rcar_sound,src {
++				src-0 {
++					status = "disabled";
++				};
++				src1: src-1 {
++					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x87>, <&audma0 0x9c>;
++					dma-names = "rx", "tx";
++				};
++				src2: src-2 {
++					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x89>, <&audma0 0x9e>;
++					dma-names = "rx", "tx";
++				};
++				src3: src-3 {
++					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
++					dma-names = "rx", "tx";
++				};
++				src4: src-4 {
++					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
++					dma-names = "rx", "tx";
++				};
++				src5: src-5 {
++					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
++					dma-names = "rx", "tx";
++				};
++				src6: src-6 {
++					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x91>, <&audma0 0xb4>;
++					dma-names = "rx", "tx";
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma0 0x02>,
++					       <&audma0 0x15>, <&audma0 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma0 0x04>,
++					       <&audma0 0x49>, <&audma0 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma0 0x06>,
++					       <&audma0 0x63>, <&audma0 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma0 0x08>,
++					       <&audma0 0x6f>, <&audma0 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma0 0x0a>,
++					       <&audma0 0x71>, <&audma0 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
++					       <&audma0 0x73>, <&audma0 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
++					       <&audma0 0x75>, <&audma0 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma0 0x10>,
++					       <&audma0 0x79>, <&audma0 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma0 0x12>,
++					       <&audma0 0x7b>, <&audma0 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma0 0x14>,
++					       <&audma0 0x7d>, <&audma0 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
+ 				};
+ 			};
+ 		};
+ 	};
+ 
+-	can0: can@e6e80000 {
+-		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e80000 0 0x1000>;
+-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 916>;
+-		status = "disabled";
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-	can1: can@e6e88000 {
+-		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+-		reg = <0 0xe6e88000 0 0x1000>;
+-		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+-			 <&can_clk>;
+-		clock-names = "clkp1", "clkp2", "can_clk";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 915>;
+-		status = "disabled";
+-	};
+ 
+ 	/* External root clock */
+ 	extal_clk: extal {
+@@ -1098,259 +1405,4 @@
+ 		#clock-cells = <0>;
+ 		clock-frequency = <0>;
+ 	};
+-
+-	cpg: clock-controller@e6150000 {
+-		compatible = "renesas,r8a7794-cpg-mssr";
+-		reg = <0 0xe6150000 0 0x1000>;
+-		clocks = <&extal_clk>, <&usb_extal_clk>;
+-		clock-names = "extal", "usb_extal";
+-		#clock-cells = <2>;
+-		#power-domain-cells = <0>;
+-		#reset-cells = <1>;
+-	};
+-
+-	rst: reset-controller@e6160000 {
+-		compatible = "renesas,r8a7794-rst";
+-		reg = <0 0xe6160000 0 0x0100>;
+-	};
+-
+-	prr: chipid@ff000044 {
+-		compatible = "renesas,prr";
+-		reg = <0 0xff000044 0 4>;
+-	};
+-
+-	sysc: system-controller@e6180000 {
+-		compatible = "renesas,r8a7794-sysc";
+-		reg = <0 0xe6180000 0 0x0200>;
+-		#power-domain-cells = <1>;
+-	};
+-
+-	ipmmu_sy0: mmu@e6280000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6280000 0 0x1000>;
+-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_sy1: mmu@e6290000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6290000 0 0x1000>;
+-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_ds: mmu@e6740000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe6740000 0 0x1000>;
+-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mp: mmu@ec680000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xec680000 0 0x1000>;
+-		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_mx: mmu@fe951000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xfe951000 0 0x1000>;
+-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	ipmmu_gp: mmu@e62a0000 {
+-		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+-		reg = <0 0xe62a0000 0 0x1000>;
+-		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+-		#iommu-cells = <1>;
+-		status = "disabled";
+-	};
+-
+-	rcar_sound: sound@ec500000 {
+-		/*
+-		 * #sound-dai-cells is required
+-		 *
+-		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+-		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+-		 */
+-		compatible = "renesas,rcar_sound-r8a7794",
+-			     "renesas,rcar_sound-gen2";
+-		reg = <0 0xec500000 0 0x1000>, /* SCU */
+-		      <0 0xec5a0000 0 0x100>,  /* ADG */
+-		      <0 0xec540000 0 0x1000>, /* SSIU */
+-		      <0 0xec541000 0 0x280>,  /* SSI */
+-		      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
+-		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+-
+-		clocks = <&cpg CPG_MOD 1005>,
+-			 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+-			 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+-			 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+-			 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+-			 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+-			 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+-			 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+-			 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+-			 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+-			 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+-			 <&cpg CPG_CORE R8A7794_CLK_M2>;
+-		clock-names = "ssi-all",
+-			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+-			      "src.6", "src.5", "src.4", "src.3", "src.2",
+-			      "src.1",
+-			      "ctu.0", "ctu.1",
+-			      "mix.0", "mix.1",
+-			      "dvc.0", "dvc.1",
+-			      "clk_a", "clk_b", "clk_c", "clk_i";
+-		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-		resets = <&cpg 1005>,
+-			 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+-			 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+-			 <&cpg 1014>, <&cpg 1015>;
+-		reset-names = "ssi-all",
+-			      "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+-			      "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+-
+-		status = "disabled";
+-
+-		rcar_sound,dvc {
+-			dvc0: dvc-0 {
+-				dmas = <&audma0 0xbc>;
+-				dma-names = "tx";
+-			};
+-			dvc1: dvc-1 {
+-				dmas = <&audma0 0xbe>;
+-				dma-names = "tx";
+-			};
+-		};
+-
+-		rcar_sound,mix {
+-			mix0: mix-0 { };
+-			mix1: mix-1 { };
+-		};
+-
+-		rcar_sound,ctu {
+-			ctu00: ctu-0 { };
+-			ctu01: ctu-1 { };
+-			ctu02: ctu-2 { };
+-			ctu03: ctu-3 { };
+-			ctu10: ctu-4 { };
+-			ctu11: ctu-5 { };
+-			ctu12: ctu-6 { };
+-			ctu13: ctu-7 { };
+-		};
+-
+-		rcar_sound,src {
+-			src-0 {
+-				status = "disabled";
+-			};
+-			src1: src-1 {
+-				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x87>, <&audma0 0x9c>;
+-				dma-names = "rx", "tx";
+-			};
+-			src2: src-2 {
+-				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x89>, <&audma0 0x9e>;
+-				dma-names = "rx", "tx";
+-			};
+-			src3: src-3 {
+-				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src4: src-4 {
+-				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+-				dma-names = "rx", "tx";
+-			};
+-			src5: src-5 {
+-				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+-				dma-names = "rx", "tx";
+-			};
+-			src6: src-6 {
+-				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x91>, <&audma0 0xb4>;
+-				dma-names = "rx", "tx";
+-			};
+-		};
+-
+-		rcar_sound,ssi {
+-			ssi0: ssi-0 {
+-				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x01>, <&audma0 0x02>,
+-				       <&audma0 0x15>, <&audma0 0x16>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi1: ssi-1 {
+-				interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x03>, <&audma0 0x04>,
+-				       <&audma0 0x49>, <&audma0 0x4a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi2: ssi-2 {
+-				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x05>, <&audma0 0x06>,
+-				       <&audma0 0x63>, <&audma0 0x64>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi3: ssi-3 {
+-				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x07>, <&audma0 0x08>,
+-				       <&audma0 0x6f>, <&audma0 0x70>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi4: ssi-4 {
+-				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x09>, <&audma0 0x0a>,
+-				       <&audma0 0x71>, <&audma0 0x72>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi5: ssi-5 {
+-				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+-				       <&audma0 0x73>, <&audma0 0x74>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi6: ssi-6 {
+-				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+-				       <&audma0 0x75>, <&audma0 0x76>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi7: ssi-7 {
+-				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x0f>, <&audma0 0x10>,
+-				       <&audma0 0x79>, <&audma0 0x7a>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi8: ssi-8 {
+-				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x11>, <&audma0 0x12>,
+-				       <&audma0 0x7b>, <&audma0 0x7c>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-			ssi9: ssi-9 {
+-				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-				dmas = <&audma0 0x13>, <&audma0 0x14>,
+-				       <&audma0 0x7d>, <&audma0 0x7e>;
+-				dma-names = "rx", "tx", "rxu", "txu";
+-			};
+-		};
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1082-ARM-dts-r8a7794-sort-subnodes-of-soc-node.patch b/patches/1082-ARM-dts-r8a7794-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..4f3b163a46d7da
--- /dev/null
+++ b/patches/1082-ARM-dts-r8a7794-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,1759 @@
+From 4798978ea6cc7ebebc78e7a5d64b64b3ffc57ec5 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:16 +0100
+Subject: [PATCH 1082/1795] ARM: dts: r8a7794: sort subnodes of soc node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f217f7bbb0fe5b446d5ad44ae6792e35eab4362e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 1525 ++++++++++++++++----------------
+ 1 file changed, 762 insertions(+), 763 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 0d65069b1a89..9e5f886f53c5 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -74,28 +74,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6151000 {
+-			compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+-			reg = <0 0xe6151000 0 0x188>;
+-			cpus = <&cpu0 &cpu1>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>,
+-			      <0 0xf1002000 0 0x2000>,
+-			      <0 0xf1004000 0 0x2000>,
+-			      <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7794",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -201,38 +179,36 @@
+ 			resets = <&cpg 905>;
+ 		};
+ 
+-		cmt0: timer@ffca0000 {
+-			compatible = "renesas,r8a7794-cmt0",
+-				     "renesas,rcar-gen2-cmt0";
+-			reg = <0 0xffca0000 0 0x1004>;
+-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 124>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 124>;
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7794";
++			reg = <0 0xe6060000 0 0x11c>;
++		};
+ 
+-			status = "disabled";
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7794-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
+ 		};
+ 
+-		cmt1: timer@e6130000 {
+-			compatible = "renesas,r8a7794-cmt1",
+-				     "renesas,rcar-gen2-cmt1";
+-			reg = <0 0xe6130000 0 0x1004>;
+-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 329>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
++		apmu@e6151000 {
++			compatible = "renesas,r8a7794-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
+ 
+-			status = "disabled";
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7794-rst";
++			reg = <0 0xe6160000 0 0x0100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7794-sysc";
++			reg = <0 0xe6180000 0 0x0200>;
++			#power-domain-cells = <1>;
+ 		};
+ 
+ 		irqc0: interrupt-controller@e61c0000 {
+@@ -255,419 +231,303 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7794";
+-			reg = <0 0xe6060000 0 0x11c>;
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		dmac0: dma-controller@e6700000 {
+-			compatible = "renesas,dmac-r8a7794",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6700000 0 0x20000>;
+-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 219>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 219>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		dmac1: dma-controller@e6720000 {
+-			compatible = "renesas,dmac-r8a7794",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6720000 0 0x20000>;
+-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7794",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3", "ch4",
+-					  "ch5", "ch6", "ch7", "ch8", "ch9",
+-					  "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		scifa0: serial@e6c40000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c40000 0 64>;
+-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 204>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+-			       <&dmac1 0x21>, <&dmac1 0x22>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 204>;
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifa1: serial@e6c50000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c50000 0 64>;
+-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 203>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+-			       <&dmac1 0x25>, <&dmac1 0x26>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 203>;
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7794",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifa2: serial@e6c60000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c60000 0 64>;
+-			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 202>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+-			       <&dmac1 0x27>, <&dmac1 0x28>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 202>;
+-			status = "disabled";
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
+ 		};
+ 
+-		scifa3: serial@e6c70000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c70000 0 64>;
+-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 1106>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+-			       <&dmac1 0x1b>, <&dmac1 0x1c>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 1106>;
+-			status = "disabled";
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
+ 		};
+ 
+-		scifa4: serial@e6c78000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c78000 0 64>;
+-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 1107>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+-			       <&dmac1 0x1f>, <&dmac1 0x20>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		/* The memory map in the User's Manual maps the cores to
++		 * bus numbers
++		 */
++		i2c0: i2c@e6508000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 1107>;
++			resets = <&cpg 931>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifa5: serial@e6c80000 {
+-			compatible = "renesas,scifa-r8a7794",
+-				     "renesas,rcar-gen2-scifa", "renesas,scifa";
+-			reg = <0 0xe6c80000 0 64>;
+-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 1108>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+-			       <&dmac1 0x23>, <&dmac1 0x24>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		i2c1: i2c@e6518000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 1108>;
++			resets = <&cpg 930>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifb0: serial@e6c20000 {
+-			compatible = "renesas,scifb-r8a7794",
+-				     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-			reg = <0 0xe6c20000 0 0x100>;
+-			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 206>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+-			       <&dmac1 0x3d>, <&dmac1 0x3e>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		i2c2: i2c@e6530000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 206>;
++			resets = <&cpg 929>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifb1: serial@e6c30000 {
+-			compatible = "renesas,scifb-r8a7794",
+-				     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-			reg = <0 0xe6c30000 0 0x100>;
+-			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 207>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+-			       <&dmac1 0x19>, <&dmac1 0x1a>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		i2c3: i2c@e6540000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 207>;
++			resets = <&cpg 928>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scifb2: serial@e6ce0000 {
+-			compatible = "renesas,scifb-r8a7794",
+-				     "renesas,rcar-gen2-scifb", "renesas,scifb";
+-			reg = <0 0xe6ce0000 0 0x100>;
+-			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 216>;
+-			clock-names = "fck";
+-			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+-			       <&dmac1 0x1d>, <&dmac1 0x1e>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		i2c4: i2c@e6520000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 216>;
++			resets = <&cpg 927>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif0: serial@e6e60000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif",
+-				     "renesas,scif";
+-			reg = <0 0xe6e60000 0 64>;
+-			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+-			       <&dmac1 0x29>, <&dmac1 0x2a>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		i2c5: i2c@e6528000 {
++			compatible = "renesas,i2c-r8a7794",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 721>;
++			resets = <&cpg 925>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif1: serial@e6e68000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif",
+-				     "renesas,scif";
+-			reg = <0 0xe6e68000 0 64>;
+-			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+-			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++		i2c6: i2c@e6500000 {
++			compatible = "renesas,iic-r8a7794",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 720>;
++			resets = <&cpg 318>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif2: serial@e6e58000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif", "renesas,scif";
+-			reg = <0 0xe6e58000 0 64>;
+-			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+-			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++		i2c7: i2c@e6510000 {
++			compatible = "renesas,iic-r8a7794",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 719>;
++			resets = <&cpg 323>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif3: serial@e6ea8000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif", "renesas,scif";
+-			reg = <0 0xe6ea8000 0 64>;
+-			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+-			       <&dmac1 0x2f>, <&dmac1 0x30>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7794",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 718>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
+ 			status = "disabled";
+ 		};
+ 
+-		scif4: serial@e6ee0000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif", "renesas,scif";
+-			reg = <0 0xe6ee0000 0 64>;
+-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+-			       <&dmac1 0xfb>, <&dmac1 0xfc>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7794",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 715>;
++			resets = <&cpg 704>;
+ 			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
+ 		};
+ 
+-		scif5: serial@e6ee8000 {
+-			compatible = "renesas,scif-r8a7794",
+-				     "renesas,rcar-gen2-scif", "renesas,scif";
+-			reg = <0 0xe6ee8000 0 64>;
+-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+-			       <&dmac1 0xfd>, <&dmac1 0xfe>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 714>;
+-			status = "disabled";
+-		};
+-
+-		hscif0: serial@e62c0000 {
+-			compatible = "renesas,hscif-r8a7794",
+-				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-			reg = <0 0xe62c0000 0 96>;
+-			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 717>,
+-				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-			       <&dmac1 0x39>, <&dmac1 0x3a>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 717>;
+-			status = "disabled";
+-		};
+-
+-		hscif1: serial@e62c8000 {
+-			compatible = "renesas,hscif-r8a7794",
+-				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-			reg = <0 0xe62c8000 0 96>;
+-			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 716>,
+-				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-			       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 716>;
+-			status = "disabled";
+-		};
+-
+-		hscif2: serial@e62d0000 {
+-			compatible = "renesas,hscif-r8a7794",
+-				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-			reg = <0 0xe62d0000 0 96>;
+-			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+-			       <&dmac1 0x3b>, <&dmac1 0x3c>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 713>;
+-			status = "disabled";
+-		};
+-
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7794",
+-				     "renesas,rcar-gen2-ether";
+-			reg = <0 0xee700000 0 0x400>;
+-			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 813>;
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 813>;
+-			phy-mode = "rmii";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+@@ -683,374 +543,301 @@
+ 			status = "disabled";
+ 		};
+ 
+-		/* The memory map in the User's Manual maps the cores to
+-		 * bus numbers
+-		 */
+-		i2c0: i2c@e6508000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7794", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
++			resets = <&cpg 917>;
++			num-cs = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c1: i2c@e6518000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6518000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
++		scifa0: serial@e6c40000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
++			       <&dmac1 0x21>, <&dmac1 0x22>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 204>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c2: i2c@e6530000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6530000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
++		scifa1: serial@e6c50000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
++			       <&dmac1 0x25>, <&dmac1 0x26>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c3: i2c@e6540000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6540000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
++		scifa2: serial@e6c60000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c60000 0 64>;
++			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
++			       <&dmac1 0x27>, <&dmac1 0x28>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 202>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c4: i2c@e6520000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6520000 0 0x40>;
+-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 927>;
++		scifa3: serial@e6c70000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c70000 0 64>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1106>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
++			       <&dmac1 0x1b>, <&dmac1 0x1c>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 927>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 1106>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c5: i2c@e6528000 {
+-			compatible = "renesas,i2c-r8a7794",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6528000 0 0x40>;
+-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 925>;
++		scifa4: serial@e6c78000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c78000 0 64>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1107>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
++			       <&dmac1 0x1f>, <&dmac1 0x20>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 925>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 1107>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c6: i2c@e6500000 {
+-			compatible = "renesas,iic-r8a7794",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6500000 0 0x425>;
+-			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 318>;
+-			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-			       <&dmac1 0x61>, <&dmac1 0x62>;
++		scifa5: serial@e6c80000 {
++			compatible = "renesas,scifa-r8a7794",
++				     "renesas,rcar-gen2-scifa", "renesas,scifa";
++			reg = <0 0xe6c80000 0 64>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 1108>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
++			       <&dmac1 0x23>, <&dmac1 0x24>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 318>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 1108>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c7: i2c@e6510000 {
+-			compatible = "renesas,iic-r8a7794",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6510000 0 0x425>;
+-			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 323>;
+-			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-			       <&dmac1 0x65>, <&dmac1 0x66>;
++		scifb0: serial@e6c20000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c20000 0 0x100>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
++			       <&dmac1 0x3d>, <&dmac1 0x3e>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 323>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 206>;
+ 			status = "disabled";
+ 		};
+ 
+-		mmcif0: mmc@ee200000 {
+-			compatible = "renesas,mmcif-r8a7794",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee200000 0 0x80>;
+-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 315>;
+-			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++		scifb1: serial@e6c30000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6c30000 0 0x100>;
++			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
++			       <&dmac1 0x19>, <&dmac1 0x1a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 315>;
+-			reg-io-width = <4>;
++			resets = <&cpg 207>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7794",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
++		scifb2: serial@e6ce0000 {
++			compatible = "renesas,scifb-r8a7794",
++				     "renesas,rcar-gen2-scifb", "renesas,scifb";
++			reg = <0 0xe6ce0000 0 0x100>;
++			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 216>;
++			clock-names = "fck";
++			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
++			       <&dmac1 0x1d>, <&dmac1 0x1e>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
++			resets = <&cpg 216>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7794",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee140000 0 0x100>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
++			resets = <&cpg 721>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7794",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee160000 0 0x100>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif",
++				     "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
++			resets = <&cpg 720>;
+ 			status = "disabled";
+ 		};
+ 
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
++		scif2: serial@e6e58000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e58000 0 64>;
++			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 917>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 719>;
+ 			status = "disabled";
+ 		};
+ 
+-		vin0: video@e6ef0000 {
+-			compatible = "renesas,vin-r8a7794",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef0000 0 0x1000>;
+-			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 811>;
++		scif3: serial@e6ea8000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ea8000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
++			       <&dmac1 0x2f>, <&dmac1 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 811>;
++			resets = <&cpg 718>;
+ 			status = "disabled";
+ 		};
+ 
+-		vin1: video@e6ef1000 {
+-			compatible = "renesas,vin-r8a7794",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef1000 0 0x1000>;
+-			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 810>;
++		scif4: serial@e6ee0000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee0000 0 64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
++			       <&dmac1 0xfb>, <&dmac1 0xfc>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 810>;
++			resets = <&cpg 715>;
+ 			status = "disabled";
+ 		};
+ 
+-		pci0: pci@ee090000 {
+-			compatible = "renesas,pci-r8a7794",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee090000 0 0xc00>,
+-			      <0 0xee080000 0 0x1100>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
++		scif5: serial@e6ee8000 {
++			compatible = "renesas,scif-r8a7794",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee8000 0 64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
++			       <&dmac1 0xfd>, <&dmac1 0xfe>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
++			resets = <&cpg 714>;
+ 			status = "disabled";
+-
+-			bus-range = <0 0>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x800 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x1000 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+ 		};
+ 
+-		pci1: pci@ee0d0000 {
+-			compatible = "renesas,pci-r8a7794",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee0d0000 0 0xc00>,
+-			      <0 0xee0c0000 0 0x1100>;
+-			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			status = "disabled";
+-
+-			bus-range = <1 1>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x10800 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x11000 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-		};
+-
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7794",
+-				     "renesas,rcar-gen2-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
++		hscif0: serial@e62c0000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c0000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 717>,
++				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			renesas,buswait = <4>;
+-			phys = <&usb0 1>;
+-			phy-names = "usb";
++			resets = <&cpg 717>;
+ 			status = "disabled";
+ 		};
+ 
+-		usbphy: usb-phy@e6590100 {
+-			compatible = "renesas,usb-phy-r8a7794",
+-				     "renesas,rcar-gen2-usb-phy";
+-			reg = <0 0xe6590100 0 0x100>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			clock-names = "usbhs";
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>,
++				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
++			resets = <&cpg 716>;
+ 			status = "disabled";
+-
+-			usb0: usb-channel@0 {
+-				reg = <0>;
+-				#phy-cells = <1>;
+-			};
+-			usb2: usb-channel@2 {
+-				reg = <2>;
+-				#phy-cells = <1>;
+-			};
+-		};
+-
+-		vsp@fe928000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe928000 0 0x8000>;
+-			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 131>;
+-			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 131>;
+ 		};
+ 
+-		vsp@fe930000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe930000 0 0x8000>;
+-			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 128>;
++		hscif2: serial@e62d0000 {
++			compatible = "renesas,hscif-r8a7794",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62d0000 0 96>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
++			       <&dmac1 0x3b>, <&dmac1 0x3c>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+-			resets = <&cpg 128>;
+-		};
+-
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7794";
+-			reg = <0 0xfeb00000 0 0x40000>;
+-			reg-names = "du";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+-			clock-names = "du.0", "du.1";
++			resets = <&cpg 713>;
+ 			status = "disabled";
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb0: endpoint {
+-					};
+-				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_rgb1: endpoint {
+-					};
+-				};
+-			};
+ 		};
+ 
+ 		can0: can@e6e80000 {
+@@ -1079,87 +866,25 @@
+ 			status = "disabled";
+ 		};
+ 
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7794-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
+-		};
+-
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7794-rst";
+-			reg = <0 0xe6160000 0 0x0100>;
+-		};
+-
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7794-sysc";
+-			reg = <0 0xe6180000 0 0x0200>;
+-			#power-domain-cells = <1>;
+-		};
+-
+-		ipmmu_sy0: mmu@e6280000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6280000 0 0x1000>;
+-			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_sy1: mmu@e6290000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6290000 0 0x1000>;
+-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_ds: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_mp: mmu@ec680000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xec680000 0 0x1000>;
+-			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_mx: mmu@fe951000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xfe951000 0 0x1000>;
+-			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7794",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_gp: mmu@e62a0000 {
+-			compatible = "renesas,ipmmu-r8a7794",
+-				     "renesas,ipmmu-vmsa";
+-			reg = <0 0xe62a0000 0 0x1000>;
+-			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7794",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1343,6 +1068,281 @@
+ 				};
+ 			};
+ 		};
++
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7794",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3", "ch4",
++					  "ch5", "ch6", "ch7", "ch8", "ch9",
++					  "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7794",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7794",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7794",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7794",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			status = "disabled";
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7794",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>,
++			      <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>,
++			      <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
++
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7794";
++			reg = <0 0xfeb00000 0 0x40000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb0: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_rgb1: endpoint {
++					};
++				};
++			};
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7794-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7794-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++
++			status = "disabled";
++		};
+ 	};
+ 
+ 	timer {
+@@ -1353,7 +1353,6 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-
+ 	/* External root clock */
+ 	extal_clk: extal {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1083-ARM-dts-r8a7794-sort-subnodes-of-root-node.patch b/patches/1083-ARM-dts-r8a7794-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..98a92274987007
--- /dev/null
+++ b/patches/1083-ARM-dts-r8a7794-sort-subnodes-of-root-node.patch
@@ -0,0 +1,148 @@
+From fcb8ac9184664c21d8f70d2322b5bee3f334d927 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 17 Jan 2018 17:17:17 +0100
+Subject: [PATCH 1083/1795] ARM: dts: r8a7794: sort subnodes of root node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together.
+
+Also re-align comment of audio_clka to match other R-Car SoCs.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 807eeaf95e2647277f89284d91d1785c2280c2c6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 90 +++++++++++++++++-----------------
+ 1 file changed, 45 insertions(+), 45 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 9e5f886f53c5..d588efa6aeaa 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -33,6 +33,35 @@
+ 		vin1 = &vin1;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clka: audio_clka {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkb: audio_clkb {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++	audio_clkc: audio_clkc {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -66,6 +95,22 @@
+ 		};
+ 	};
+ 
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1353,55 +1398,10 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+-	/* External root clock */
+-	extal_clk: extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+ 	/* External USB clock - can be overridden by the board */
+ 	usb_extal_clk: usb_extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <48000000>;
+ 	};
+-
+-	/* External CAN clock */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External SCIF clock */
+-	scif_clk: scif {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		/* This value must be overridden by the board. */
+-		clock-frequency = <0>;
+-	};
+-
+-	/*
+-	 * The external audio clocks are configured  as 0 Hz fixed
+-	 * frequency clocks by default.  Boards that provide audio
+-	 * clocks should override them.
+-	 */
+-	audio_clka: audio_clka {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clkb: audio_clkb {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-	audio_clkc: audio_clkc {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1084-ARM-dts-r8a7790-consistently-use-single-space-before.patch b/patches/1084-ARM-dts-r8a7790-consistently-use-single-space-before.patch
new file mode 100644
index 00000000000000..e42efd61c42622
--- /dev/null
+++ b/patches/1084-ARM-dts-r8a7790-consistently-use-single-space-before.patch
@@ -0,0 +1,50 @@
+From 6a50df1564827376fb6e4a3e687a11b496db5d39 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 26 Jan 2018 10:36:33 +0100
+Subject: [PATCH 1084/1795] ARM: dts: r8a7790: consistently use single space
+ before =
+
+Consistently use a single space before a =.
+
+This patch fixes instances where a tab is used instead.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5a63226206ce2313badee0b6ffec47f7a305c8ae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 3bbcc0b93f1c..e4367cecad18 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1705,16 +1705,16 @@
+ 
+ 	thermal-zones {
+ 		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
+ 
+ 			thermal-sensors = <&thermal>;
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
++					temperature = <95000>;
++					hysteresis = <0>;
++					type = "critical";
+ 				};
+ 			};
+ 			cooling-maps {
+-- 
+2.19.0
+
diff --git a/patches/1085-ARM-dts-r8a7791-consistently-use-single-space-before.patch b/patches/1085-ARM-dts-r8a7791-consistently-use-single-space-before.patch
new file mode 100644
index 00000000000000..a7d12b37c33ccd
--- /dev/null
+++ b/patches/1085-ARM-dts-r8a7791-consistently-use-single-space-before.patch
@@ -0,0 +1,50 @@
+From b8fb495c61e032f3b394c79b36bd29b840add43a Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 26 Jan 2018 10:36:34 +0100
+Subject: [PATCH 1085/1795] ARM: dts: r8a7791: consistently use single space
+ before =
+
+Consistently use a single space before a =.
+
+This patch fixes instances where a tab is used instead.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c57c1b7ce8c6743ca745a577e7ac6b81a59a2479)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index dc659351472f..f11dab71b03a 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -1703,16 +1703,16 @@
+ 
+ 	thermal-zones {
+ 		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
+ 
+ 			thermal-sensors = <&thermal>;
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
++					temperature = <95000>;
++					hysteresis = <0>;
++					type = "critical";
+ 				};
+ 			};
+ 			cooling-maps {
+-- 
+2.19.0
+
diff --git a/patches/1086-ARM-dts-r8a7793-consistently-use-single-space-before.patch b/patches/1086-ARM-dts-r8a7793-consistently-use-single-space-before.patch
new file mode 100644
index 00000000000000..4d54975c063ca4
--- /dev/null
+++ b/patches/1086-ARM-dts-r8a7793-consistently-use-single-space-before.patch
@@ -0,0 +1,50 @@
+From 531aec31c8cc79189cb652ee215cbf86532d27b5 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 26 Jan 2018 10:36:35 +0100
+Subject: [PATCH 1086/1795] ARM: dts: r8a7793: consistently use single space
+ before =
+
+Consistently use a single space before a =.
+
+This patch fixes instances where a tab is used instead.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 77b1e3d230e5e42bbde3f11923b34382832a8415)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index aa7d7792fb13..f9c5a557107d 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -1362,16 +1362,16 @@
+ 
+ 	thermal-zones {
+ 		cpu_thermal: cpu-thermal {
+-			polling-delay-passive	= <0>;
+-			polling-delay		= <0>;
++			polling-delay-passive = <0>;
++			polling-delay = <0>;
+ 
+ 			thermal-sensors = <&thermal>;
+ 
+ 			trips {
+ 				cpu-crit {
+-					temperature	= <95000>;
+-					hysteresis	= <0>;
+-					type		= "critical";
++					temperature = <95000>;
++					hysteresis = <0>;
++					type = "critical";
+ 				};
+ 			};
+ 			cooling-maps {
+-- 
+2.19.0
+
diff --git a/patches/1087-ARM-dts-r8a7743-sort-subnodes-of-soc-node.patch b/patches/1087-ARM-dts-r8a7743-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..11898be4db5d66
--- /dev/null
+++ b/patches/1087-ARM-dts-r8a7743-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,1475 @@
+From 6363dab92e6d6b8eb977659ea0334826f74bc7f4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 26 Jan 2018 10:40:51 +0100
+Subject: [PATCH 1087/1795] ARM: dts: r8a7743: sort subnodes of soc node
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together and sorted alphabetically.
+
+Minor whitespace and line-wrapping changes are also made
+to match the formatting of R-Car Gen2 SoCs.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 8eccafe92d100d836dfee541c3337b42d818533c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 1327 ++++++++++++++++----------------
+ 1 file changed, 662 insertions(+), 665 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 0b74c6c7d21d..1933aaccb874 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -141,29 +141,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6152000 {
+-			compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+-			reg = <0 0xe6152000 0 0x188>;
+-			cpus = <&cpu0 &cpu1>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>,
+-			      <0 0xf1002000 0 0x2000>,
+-			      <0 0xf1004000 0 0x2000>,
+-			      <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+-						 IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7743",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -284,6 +261,48 @@
+ 			resets = <&cpg 904>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7743";
++			reg = <0 0xe6060000 0 0x250>;
++		};
++
++		tpu: pwm@e60f0000 {
++			compatible = "renesas,tpu-r8a7743", "renesas,tpu";
++			reg = <0 0xe60f0000 0 0x148>;
++			clocks = <&cpg CPG_MOD 304>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 304>;
++			#pwm-cells = <3>;
++			status = "disabled";
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7743-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		apmu@e6152000 {
++			compatible = "renesas,r8a7743-apmu", "renesas,apmu";
++			reg = <0 0xe6152000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7743-rst";
++			reg = <0 0xe6160000 0 0x100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7743-sysc";
++			reg = <0 0xe6180000 0 0x200>;
++			#power-domain-cells = <1>;
++		};
++
+ 		irqc: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -316,195 +335,206 @@
+ 			#thermal-sensor-cells = <0>;
+ 		};
+ 
+-		cmt0: timer@ffca0000 {
+-			compatible = "renesas,r8a7743-cmt0",
+-				     "renesas,rcar-gen2-cmt0";
+-			reg = <0 0xffca0000 0 0x1004>;
+-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 124>;
+-			clock-names = "fck";
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
++
++		icram2:	sram@e6300000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe6300000 0 0x40000>;
++		};
++
++		/* The memory map in the User's Manual maps the cores to
++		 * bus numbers
++		 */
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 124>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		cmt1: timer@e6130000 {
+-			compatible = "renesas,r8a7743-cmt1",
+-				     "renesas,rcar-gen2-cmt1";
+-			reg = <0 0xe6130000 0 0x1004>;
+-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 329>;
+-			clock-names = "fck";
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7743-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7743-rst";
+-			reg = <0 0xe6160000 0 0x100>;
++		i2c4: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7743-sysc";
+-			reg = <0 0xe6180000 0 0x200>;
+-			#power-domain-cells = <1>;
++		i2c5: i2c@e6528000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7743",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7743";
+-			reg = <0 0xe6060000 0 0x250>;
++		iic0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
+ 		};
+ 
+-		dmac0: dma-controller@e6700000 {
+-			compatible = "renesas,dmac-r8a7743",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6700000 0 0x20000>;
+-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 219>;
+-			clock-names = "fck";
++		iic1: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 219>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++			resets = <&cpg 323>;
++			status = "disabled";
+ 		};
+ 
+-		dmac1: dma-controller@e6720000 {
+-			compatible = "renesas,dmac-r8a7743",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe6720000 0 0x20000>;
+-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
++		iic3: i2c@e60b0000 {
++			/* doesn't need pinmux */
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7743",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
++			       <&dmac1 0x77>, <&dmac1 0x78>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
++			resets = <&cpg 926>;
++			status = "disabled";
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7743",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7743",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
+ 		};
+ 
+-		audma1: dma-controller@ec720000 {
+-			compatible = "renesas,dmac-r8a7743",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec720000 0 0x10000>;
+-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 501>;
+-			clock-names = "fck";
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7743",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 501>;
+-			#dma-cells = <1>;
+-			dma-channels = <13>;
++			resets = <&cpg 704>;
++			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
+ 		};
+ 
+ 		usb_dmac0: dma-controller@e65a0000 {
+@@ -535,143 +565,98 @@
+ 			dma-channels = <2>;
+ 		};
+ 
+-		/* The memory map in the User's Manual maps the cores to bus
+-		 *  numbers
+-		 */
+-		i2c0: i2c@e6508000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		i2c1: i2c@e6518000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6518000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
+ 		};
+ 
+-		i2c2: i2c@e6530000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6530000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7743",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c3: i2c@e6540000 {
++			resets = <&cpg 812>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6540000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c4: i2c@e6520000 {
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7743", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			num-cs = <1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6520000 0 0x40>;
+-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 927>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 927>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c5: i2c@e6528000 {
+-			/* doesn't need pinmux */
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7743",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6528000 0 0x40>;
+-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 925>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 925>;
+-			i2c-scl-internal-delay-ns = <110>;
+-			status = "disabled";
+-		};
+-
+-		iic0: i2c@e6500000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7743",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6500000 0 0x425>;
+-			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 318>;
+-			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-			       <&dmac1 0x61>, <&dmac1 0x62>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 318>;
+-			status = "disabled";
+-		};
+-
+-		iic1: i2c@e6510000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7743",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6510000 0 0x425>;
+-			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 323>;
+-			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-			       <&dmac1 0x65>, <&dmac1 0x66>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 323>;
+-			status = "disabled";
+-		};
+-
+-		iic3: i2c@e60b0000 {
+-			/* doesn't need pinmux */
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7743",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe60b0000 0 0x425>;
+-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 926>;
+-			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+-			       <&dmac1 0x77>, <&dmac1 0x78>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 926>;
++			resets = <&cpg 917>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -954,88 +939,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		icram2:	sram@e6300000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe6300000 0 0x40000>;
+-		};
+-
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
+-		};
+-
+-		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7743",
+-				     "renesas,rcar-gen2-ether";
+-			reg = <0 0xee700000 0 0x400>;
+-			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 813>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 813>;
+-			phy-mode = "rmii";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7743",
+-				     "renesas,etheravb-rcar-gen2";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		mmcif0: mmc@ee200000 {
+-			compatible = "renesas,mmcif-r8a7743",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee200000 0 0x80>;
+-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 315>;
+-			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-			       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 315>;
+-			reg-io-width = <4>;
+-			max-frequency = <97500000>;
+-			status = "disabled";
+-		};
+-
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7743", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			resets = <&cpg 917>;
+-			status = "disabled";
+-		};
+-
+ 		msiof0: spi@e6e20000 {
+ 			compatible = "renesas,msiof-r8a7743",
+ 				     "renesas,rcar-gen2-msiof";
+@@ -1084,26 +987,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		/*
+-		 * pci1 and xhci share the same phy, therefore only one of them
+-		 * can be active at any one time. If both of them are enabled,
+-		 * a race condition will determine who'll control the phy.
+-		 * A firmware file is needed by the xhci driver in order for
+-		 * USB 3.0 to work properly.
+-		 */
+-		xhci: usb@ee000000 {
+-			compatible = "renesas,xhci-r8a7743",
+-				     "renesas,rcar-gen2-xhci";
+-			reg = <0 0xee000000 0 0xc00>;
+-			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 328>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 328>;
+-			phys = <&usb2 1>;
+-			phy-names = "usb";
+-			status = "disabled";
+-		};
+-
+ 		pwm0: pwm@e6e30000 {
+ 			compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e30000 0 0x8>;
+@@ -1174,119 +1057,53 @@
+ 			status = "disabled";
+ 		};
+ 
+-		tpu: pwm@e60f0000 {
+-			compatible = "renesas,tpu-r8a7743", "renesas,tpu";
+-			reg = <0 0xe60f0000 0 0x148>;
+-			clocks = <&cpg CPG_MOD 304>;
++		can0: can@e6e80000 {
++			compatible = "renesas,can-r8a7743",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e80000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 304>;
+-			#pwm-cells = <3>;
++			resets = <&cpg 916>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7743",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
++		can1: can@e6e88000 {
++			compatible = "renesas,can-r8a7743",
++				     "renesas,rcar-gen2-can";
++			reg = <0 0xe6e88000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
++				 <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
++			resets = <&cpg 915>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7743",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee140000 0 0x100>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7743",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
++			resets = <&cpg 811>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7743",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee160000 0 0x100>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7743",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
+ 			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
+-			status = "disabled";
+-		};
+-
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7743",
+-				     "renesas,rcar-gen2-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			renesas,buswait = <4>;
+-			phys = <&usb0 1>;
+-			phy-names = "usb";
+-			status = "disabled";
+-		};
+-
+-		usbphy: usb-phy@e6590100 {
+-			compatible = "renesas,usb-phy-r8a7743",
+-				     "renesas,rcar-gen2-usb-phy";
+-			reg = <0 0xe6590100 0 0x100>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			clock-names = "usbhs";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			status = "disabled";
+-
+-			usb0: usb-channel@0 {
+-				reg = <0>;
+-				#phy-cells = <1>;
+-			};
+-			usb2: usb-channel@2 {
+-				reg = <2>;
+-				#phy-cells = <1>;
+-			};
+-		};
+-
+-		vin0: video@e6ef0000 {
+-			compatible = "renesas,vin-r8a7743",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef0000 0 0x1000>;
+-			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 811>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 811>;
+-			status = "disabled";
+-		};
+-
+-		vin1: video@e6ef1000 {
+-			compatible = "renesas,vin-r8a7743",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef1000 0 0x1000>;
+-			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 810>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 810>;
++			resets = <&cpg 810>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1301,162 +1118,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7743";
+-			reg = <0 0xfeb00000 0 0x40000>,
+-			      <0 0xfeb90000 0 0x1c>;
+-			reg-names = "du", "lvds.0";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>,
+-				 <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 726>;
+-			clock-names = "du.0", "du.1", "lvds.0";
+-			status = "disabled";
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb: endpoint {
+-					};
+-				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_lvds0: endpoint {
+-					};
+-				};
+-			};
+-		};
+-
+-		can0: can@e6e80000 {
+-			compatible = "renesas,can-r8a7743",
+-				     "renesas,rcar-gen2-can";
+-			reg = <0 0xe6e80000 0 0x1000>;
+-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 916>,
+-				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+-				 <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 916>;
+-			status = "disabled";
+-		};
+-
+-		can1: can@e6e88000 {
+-			compatible = "renesas,can-r8a7743",
+-				     "renesas,rcar-gen2-can";
+-			reg = <0 0xe6e88000 0 0x1000>;
+-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 915>,
+-				 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+-				 <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
+-			status = "disabled";
+-		};
+-
+-		pci0: pci@ee090000 {
+-			compatible = "renesas,pci-r8a7743",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee090000 0 0xc00>,
+-			      <0 0xee080000 0 0x1100>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			status = "disabled";
+-
+-			bus-range = <0 0>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x800 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x1000 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+-		};
+-
+-		pci1: pci@ee0d0000 {
+-			compatible = "renesas,pci-r8a7743",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee0d0000 0 0xc00>,
+-			      <0 0xee0c0000 0 0x1100>;
+-			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			status = "disabled";
+-
+-			bus-range = <1 1>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x10800 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x11000 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-		};
+-
+-		pciec: pcie@fe000000 {
+-			compatible = "renesas,pcie-r8a7743",
+-				     "renesas,pcie-rcar-gen2";
+-			reg = <0 0xfe000000 0 0x80000>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			bus-range = <0x00 0xff>;
+-			device_type = "pci";
+-			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+-				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+-				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+-				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+-			/* Map all possible DDR as inbound ranges */
+-			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+-				      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 0>;
+-			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+-			clock-names = "pcie", "pcie_bus";
+-			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+-			resets = <&cpg 319>;
+-			status = "disabled";
+-		};
+-
+ 		rcar_sound: sound@ec500000 {
+ 			/*
+ 			 * #sound-dai-cells is required
+@@ -1641,6 +1302,342 @@
+ 				};
+ 			};
+ 		};
++
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7743",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		/*
++		 * pci1 and xhci share the same phy, therefore only one of them
++		 * can be active at any one time. If both of them are enabled,
++		 * a race condition will determine who'll control the phy.
++		 * A firmware file is needed by the xhci driver in order for
++		 * USB 3.0 to work properly.
++		 */
++		xhci: usb@ee000000 {
++			compatible = "renesas,xhci-r8a7743",
++				     "renesas,rcar-gen2-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			phys = <&usb2 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7743",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7743",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7743",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7743",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			max-frequency = <97500000>;
++			status = "disabled";
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7743",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
++		pciec: pcie@fe000000 {
++			compatible = "renesas,pcie-r8a7743",
++				     "renesas,pcie-rcar-gen2";
++			reg = <0 0xfe000000 0 0x80000>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			bus-range = <0x00 0xff>;
++			device_type = "pci";
++			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
++				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
++				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
++				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
++			/* Map all possible DDR as inbound ranges */
++			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
++				      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
++			clock-names = "pcie", "pcie_bus";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 319>;
++			status = "disabled";
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7743";
++			reg = <0 0xfeb00000 0 0x40000>,
++			      <0 0xfeb90000 0 0x1c>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 726>;
++			clock-names = "du.0", "du.1", "lvds.0";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7743-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7743-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+2.19.0
+
diff --git a/patches/1088-ARM-dts-r8a7745-sort-subnodes-of-soc-node.patch b/patches/1088-ARM-dts-r8a7745-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..8d2925955bcdd0
--- /dev/null
+++ b/patches/1088-ARM-dts-r8a7745-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,1271 @@
+From 6aa74de3943de0ab438799051ea336b2a8d33a2a Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 26 Jan 2018 10:40:52 +0100
+Subject: [PATCH 1088/1795] ARM: dts: r8a7745: sort subnodes of soc node
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together and sorted alphabetically.
+
+Minor whitespace and line-wrapping changes are also made
+to match the formatting of R-Car Gen2 SoCs.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 28c07001db756d5542a80be4441c0d2be0f114c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 1138 ++++++++++++++++----------------
+ 1 file changed, 567 insertions(+), 571 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index ae918e9cce21..9c8d72c83bdc 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -121,29 +121,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		apmu@e6151000 {
+-			compatible = "renesas,r8a7745-apmu", "renesas,apmu";
+-			reg = <0 0xe6151000 0 0x188>;
+-			cpus = <&cpu0 &cpu1>;
+-		};
+-
+-		gic: interrupt-controller@f1001000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1001000 0 0x1000>,
+-			      <0 0xf1002000 0 0x2000>,
+-			      <0 0xf1004000 0 0x2000>,
+-			      <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+-						 IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7745",
+ 				     "renesas,rcar-gen2-gpio";
+@@ -249,6 +226,48 @@
+ 			resets = <&cpg 905>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7745";
++			reg = <0 0xe6060000 0 0x11c>;
++		};
++
++		tpu: pwm@e60f0000 {
++			compatible = "renesas,tpu-r8a7745", "renesas,tpu";
++			reg = <0 0xe60f0000 0 0x148>;
++			clocks = <&cpg CPG_MOD 304>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 304>;
++			#pwm-cells = <3>;
++			status = "disabled";
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7745-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		apmu@e6151000 {
++			compatible = "renesas,r8a7745-apmu", "renesas,apmu";
++			reg = <0 0xe6151000 0 0x188>;
++			cpus = <&cpu0 &cpu1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7745-rst";
++			reg = <0 0xe6160000 0 0x100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7745-sysc";
++			reg = <0 0xe6180000 0 0x200>;
++			#power-domain-cells = <1>;
++		};
++
+ 		irqc: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -269,67 +288,211 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		cmt0: timer@ffca0000 {
+-			compatible = "renesas,r8a7745-cmt0",
+-				     "renesas,rcar-gen2-cmt0";
+-			reg = <0 0xffca0000 0 0x1004>;
+-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 124>;
+-			clock-names = "fck";
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x10>;
++			};
++		};
++
++		icram2:	sram@e6300000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe6300000 0 0x40000>;
++		};
++		i2c0: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 124>;
++			resets = <&cpg 931>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		cmt1: timer@e6130000 {
+-			compatible = "renesas,r8a7745-cmt1",
+-				     "renesas,rcar-gen2-cmt1";
+-			reg = <0 0xe6130000 0 0x1004>;
+-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 329>;
+-			clock-names = "fck";
++		i2c1: i2c@e6518000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6518000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
++			resets = <&cpg 930>;
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a7745-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&usb_extal_clk>;
+-			clock-names = "extal", "usb_extal";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
++		i2c2: i2c@e6530000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6530000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		prr: chipid@ff000044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xff000044 0 4>;
++		i2c3: i2c@e6540000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6540000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a7745-rst";
+-			reg = <0 0xe6160000 0 0x100>;
++		i2c4: i2c@e6520000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6520000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a7745-sysc";
+-			reg = <0 0xe6180000 0 0x200>;
+-			#power-domain-cells = <1>;
++		i2c5: i2c@e6528000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7745",
++				     "renesas,rcar-gen2-i2c";
++			reg = <0 0xe6528000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 925>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 925>;
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7745";
+-			reg = <0 0xe6060000 0 0x11c>;
++		iic0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7745",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6500000 0 0x425>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 318>;
++			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
++			       <&dmac1 0x61>, <&dmac1 0x62>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 318>;
++			status = "disabled";
++		};
++
++		iic1: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7745",
++				     "renesas,rcar-gen2-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe6510000 0 0x425>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 323>;
++			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
++			       <&dmac1 0x65>, <&dmac1 0x66>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 323>;
++			status = "disabled";
++		};
++
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7745",
++				     "renesas,rcar-gen2-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			renesas,buswait = <4>;
++			phys = <&usb0 1>;
++			phy-names = "usb";
++			status = "disabled";
++		};
++
++		usbphy: usb-phy@e6590100 {
++			compatible = "renesas,usb-phy-r8a7745",
++				     "renesas,rcar-gen2-usb-phy";
++			reg = <0 0xe6590100 0 0x100>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&cpg CPG_MOD 704>;
++			clock-names = "usbhs";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 704>;
++			status = "disabled";
++
++			usb0: usb-channel@0 {
++				reg = <0>;
++				#phy-cells = <1>;
++			};
++			usb2: usb-channel@2 {
++				reg = <2>;
++				#phy-cells = <1>;
++			};
++		};
++
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7745-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7745-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+@@ -353,10 +516,10 @@
+ 				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ 				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
+ 			clocks = <&cpg CPG_MOD 219>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+@@ -385,76 +548,46 @@
+ 				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ 				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ 				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <15>;
+-		};
+-
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7745",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "error",
+ 					  "ch0", "ch1", "ch2", "ch3",
+ 					  "ch4", "ch5", "ch6", "ch7",
+ 					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12";
+-			clocks = <&cpg CPG_MOD 502>;
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
++			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+-			dma-channels = <13>;
++			dma-channels = <15>;
+ 		};
+ 
+-		usb_dmac0: dma-controller@e65a0000 {
+-			compatible = "renesas,r8a7745-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65a0000 0 0x100>;
+-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 330>;
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7745",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 330>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+-		usb_dmac1: dma-controller@e65b0000 {
+-			compatible = "renesas,r8a7745-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65b0000 0 0x100>;
+-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 331>;
++		qspi: spi@e6b10000 {
++			compatible = "renesas,qspi-r8a7745", "renesas,qspi";
++			reg = <0 0xe6b10000 0 0x2c>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 917>;
++			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
++			       <&dmac1 0x17>, <&dmac1 0x18>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 331>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			resets = <&cpg 917>;
++			status = "disabled";
+ 		};
+ 
+ 		scifa0: serial@e6c40000 {
+@@ -695,294 +828,45 @@
+ 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 717>,
+ 				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+-			       <&dmac1 0x39>, <&dmac1 0x3a>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 717>;
+-			status = "disabled";
+-		};
+-
+-		hscif1: serial@e62c8000 {
+-			compatible = "renesas,hscif-r8a7745",
+-				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-			reg = <0 0xe62c8000 0 0x60>;
+-			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 716>,
+-				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+-			       <&dmac1 0x4d>, <&dmac1 0x4e>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 716>;
+-			status = "disabled";
+-		};
+-
+-		hscif2: serial@e62d0000 {
+-			compatible = "renesas,hscif-r8a7745",
+-				     "renesas,rcar-gen2-hscif", "renesas,hscif";
+-			reg = <0 0xe62d0000 0 0x60>;
+-			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 713>,
+-				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+-			       <&dmac1 0x3b>, <&dmac1 0x3c>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 713>;
+-			status = "disabled";
+-		};
+-
+-		icram2:	sram@e6300000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe6300000 0 0x40000>;
+-		};
+-
+-		icram0:	sram@e63a0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63a0000 0 0x12000>;
+-		};
+-
+-		icram1:	sram@e63c0000 {
+-			compatible = "mmio-sram";
+-			reg = <0 0xe63c0000 0 0x1000>;
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0 0 0xe63c0000 0x1000>;
+-
+-			smp-sram@0 {
+-				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
+-			};
+-		};
+-
+-		ether: ethernet@ee700000 {
+-			compatible = "renesas,ether-r8a7745",
+-				     "renesas,rcar-gen2-ether";
+-			reg = <0 0xee700000 0 0x400>;
+-			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 813>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 813>;
+-			phy-mode = "rmii";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7745",
+-				     "renesas,etheravb-rcar-gen2";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+-			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		i2c0: i2c@e6508000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c1: i2c@e6518000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6518000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c2: i2c@e6530000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6530000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c3: i2c@e6540000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6540000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c4: i2c@e6520000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6520000 0 0x40>;
+-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 927>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 927>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c5: i2c@e6528000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7745",
+-				     "renesas,rcar-gen2-i2c";
+-			reg = <0 0xe6528000 0 0x40>;
+-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 925>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 925>;
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		iic0: i2c@e6500000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7745",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6500000 0 0x425>;
+-			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 318>;
+-			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+-			       <&dmac1 0x61>, <&dmac1 0x62>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 318>;
+-			status = "disabled";
+-		};
+-
+-		iic1: i2c@e6510000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7745",
+-				     "renesas,rcar-gen2-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe6510000 0 0x425>;
+-			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 323>;
+-			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+-			       <&dmac1 0x65>, <&dmac1 0x66>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 323>;
+-			status = "disabled";
+-		};
+-
+-		mmcif0: mmc@ee200000 {
+-			compatible = "renesas,mmcif-r8a7745",
+-				     "renesas,sh-mmcif";
+-			reg = <0 0xee200000 0 0x80>;
+-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 315>;
+-			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+-			       <&dmac1 0xd1>, <&dmac1 0xd2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 315>;
+-			reg-io-width = <4>;
+-			max-frequency = <97500000>;
+-			status = "disabled";
+-		};
+-
+-		qspi: spi@e6b10000 {
+-			compatible = "renesas,qspi-r8a7745", "renesas,qspi";
+-			reg = <0 0xe6b10000 0 0x2c>;
+-			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 917>;
+-			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+-			       <&dmac1 0x17>, <&dmac1 0x18>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
++			       <&dmac1 0x39>, <&dmac1 0x3a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			num-cs = <1>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			resets = <&cpg 917>;
++			resets = <&cpg 717>;
+ 			status = "disabled";
+ 		};
+ 
+-		vin0: video@e6ef0000 {
+-			compatible = "renesas,vin-r8a7745",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef0000 0 0x1000>;
+-			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 811>;
++		hscif1: serial@e62c8000 {
++			compatible = "renesas,hscif-r8a7745",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62c8000 0 0x60>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>,
++				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
++			       <&dmac1 0x4d>, <&dmac1 0x4e>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 811>;
++			resets = <&cpg 716>;
+ 			status = "disabled";
+ 		};
+ 
+-		vin1: video@e6ef1000 {
+-			compatible = "renesas,vin-r8a7745",
+-				     "renesas,rcar-gen2-vin";
+-			reg = <0 0xe6ef1000 0 0x1000>;
+-			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 810>;
++		hscif2: serial@e62d0000 {
++			compatible = "renesas,hscif-r8a7745",
++				     "renesas,rcar-gen2-hscif", "renesas,hscif";
++			reg = <0 0xe62d0000 0 0x60>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 713>,
++				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
++			       <&dmac1 0x3b>, <&dmac1 0x3c>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 810>;
+-			status = "disabled";
+-		};
+-
+-		du: display@feb00000 {
+-			compatible = "renesas,du-r8a7745";
+-			reg = <0 0xfeb00000 0 0x40000>;
+-			reg-names = "du";
+-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+-			clock-names = "du.0", "du.1";
++			resets = <&cpg 713>;
+ 			status = "disabled";
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				port@0 {
+-					reg = <0>;
+-					du_out_rgb0: endpoint {
+-					};
+-				};
+-				port@1 {
+-					reg = <1>;
+-					du_out_rgb1: endpoint {
+-					};
+-				};
+-			};
+ 		};
+ 
+ 		msiof0: spi@e6e20000 {
+@@ -1103,170 +987,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		tpu: pwm@e60f0000 {
+-			compatible = "renesas,tpu-r8a7745", "renesas,tpu";
+-			reg = <0 0xe60f0000 0 0x148>;
+-			clocks = <&cpg CPG_MOD 304>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 304>;
+-			#pwm-cells = <3>;
+-			status = "disabled";
+-		};
+-
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7745",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee100000 0 0x328>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+-			       <&dmac1 0xcd>, <&dmac1 0xce>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <195000000>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
+-			status = "disabled";
+-		};
+-
+-		sdhi1: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7745",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee140000 0 0x100>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+-			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
+-			status = "disabled";
+-		};
+-
+-		sdhi2: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7745",
+-				     "renesas,rcar-gen2-sdhi";
+-			reg = <0 0xee160000 0 0x100>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+-			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			max-frequency = <97500000>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
+-			status = "disabled";
+-		};
+-
+-		pci0: pci@ee090000 {
+-			compatible = "renesas,pci-r8a7745",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee090000 0 0xc00>,
+-			      <0 0xee080000 0 0x1100>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			status = "disabled";
+-
+-			bus-range = <0 0>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x800 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x1000 0 0 0 0>;
+-				phys = <&usb0 0>;
+-				phy-names = "usb";
+-			};
+-		};
+-
+-		pci1: pci@ee0d0000 {
+-			compatible = "renesas,pci-r8a7745",
+-				     "renesas,pci-rcar-gen2";
+-			device_type = "pci";
+-			reg = <0 0xee0d0000 0 0xc00>,
+-			      <0 0xee0c0000 0 0x1100>;
+-			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			status = "disabled";
+-
+-			bus-range = <1 1>;
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			#interrupt-cells = <1>;
+-			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+-			interrupt-map-mask = <0xff00 0 0 0x7>;
+-			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+-					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			usb@1,0 {
+-				reg = <0x10800 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-
+-			usb@2,0 {
+-				reg = <0x11000 0 0 0 0>;
+-				phys = <&usb2 0>;
+-				phy-names = "usb";
+-			};
+-		};
+-
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7745",
+-				     "renesas,rcar-gen2-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			renesas,buswait = <4>;
+-			phys = <&usb0 1>;
+-			phy-names = "usb";
+-			status = "disabled";
+-		};
+-
+-		usbphy: usb-phy@e6590100 {
+-			compatible = "renesas,usb-phy-r8a7745",
+-				     "renesas,rcar-gen2-usb-phy";
+-			reg = <0 0xe6590100 0 0x100>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			clock-names = "usbhs";
+-			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
+-			status = "disabled";
+-
+-			usb0: usb-channel@0 {
+-				reg = <0>;
+-				#phy-cells = <1>;
+-			};
+-			usb2: usb-channel@2 {
+-				reg = <2>;
+-				#phy-cells = <1>;
+-			};
+-		};
+-
+ 		can0: can@e6e80000 {
+ 			compatible = "renesas,can-r8a7745",
+ 				     "renesas,rcar-gen2-can";
+@@ -1291,7 +1011,29 @@
+ 				 <&can_clk>;
+ 			clock-names = "clkp1", "clkp2", "can_clk";
+ 			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
++
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7745",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			status = "disabled";
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7745",
++				     "renesas,rcar-gen2-vin";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1474,6 +1216,260 @@
+ 				};
+ 			};
+ 		};
++
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7745",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <13>;
++		};
++
++		pci0: pci@ee090000 {
++			compatible = "renesas,pci-r8a7745",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee090000 0 0xc00>,
++			      <0 0xee080000 0 0x1100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x800 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x1000 0 0 0 0>;
++				phys = <&usb0 0>;
++				phy-names = "usb";
++			};
++		};
++
++		pci1: pci@ee0d0000 {
++			compatible = "renesas,pci-r8a7745",
++				     "renesas,pci-rcar-gen2";
++			device_type = "pci";
++			reg = <0 0xee0d0000 0 0xc00>,
++			      <0 0xee0c0000 0 0x1100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++
++			bus-range = <1 1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
++			interrupt-map-mask = <0xff00 0 0 0x7>;
++			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
++					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++
++			usb@1,0 {
++				reg = <0x10800 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++
++			usb@2,0 {
++				reg = <0x11000 0 0 0 0>;
++				phys = <&usb2 0>;
++				phy-names = "usb";
++			};
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee100000 0 0x328>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
++			       <&dmac1 0xcd>, <&dmac1 0xce>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <195000000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee140000 0 0x100>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
++			       <&dmac1 0xc1>, <&dmac1 0xc2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7745",
++				     "renesas,rcar-gen2-sdhi";
++			reg = <0 0xee160000 0 0x100>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
++			       <&dmac1 0xd3>, <&dmac1 0xd4>;
++			dma-names = "tx", "rx", "tx", "rx";
++			max-frequency = <97500000>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		mmcif0: mmc@ee200000 {
++			compatible = "renesas,mmcif-r8a7745",
++				     "renesas,sh-mmcif";
++			reg = <0 0xee200000 0 0x80>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 315>;
++			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
++			       <&dmac1 0xd1>, <&dmac1 0xd2>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 315>;
++			reg-io-width = <4>;
++			max-frequency = <97500000>;
++			status = "disabled";
++		};
++
++		ether: ethernet@ee700000 {
++			compatible = "renesas,ether-r8a7745",
++				     "renesas,rcar-gen2-ether";
++			reg = <0 0xee700000 0 0x400>;
++			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 813>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 813>;
++			phy-mode = "rmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7745";
++			reg = <0 0xfeb00000 0 0x40000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb0: endpoint {
++					};
++				};
++				port@1 {
++					reg = <1>;
++					du_out_rgb1: endpoint {
++					};
++				};
++			};
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,r8a7745-cmt0",
++				     "renesas,rcar-gen2-cmt0";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 124>;
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,r8a7745-cmt1",
++				     "renesas,rcar-gen2-cmt1";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 329>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1089-ARM-dts-r8a7743-Add-IPMMU-DT-nodes.patch b/patches/1089-ARM-dts-r8a7743-Add-IPMMU-DT-nodes.patch
new file mode 100644
index 00000000000000..aaca850a610959
--- /dev/null
+++ b/patches/1089-ARM-dts-r8a7743-Add-IPMMU-DT-nodes.patch
@@ -0,0 +1,90 @@
+From d971bfc94cac0ec04d631ff8be5b950ae7ab37bd Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 24 Jan 2018 15:42:01 +0000
+Subject: [PATCH 1089/1795] ARM: dts: r8a7743: Add IPMMU DT nodes
+
+Add the six IPMMU instances found in the r8a7743 to DT with a disabled
+status.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bbb44da0b5958e05cba96b36a354d5e9be46b1a8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 58 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 1933aaccb874..11a1263211eb 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -335,6 +335,64 @@
+ 			#thermal-sensor-cells = <0>;
+ 		};
+ 
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7743",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		icram0:	sram@e63a0000 {
+ 			compatible = "mmio-sram";
+ 			reg = <0 0xe63a0000 0 0x12000>;
+-- 
+2.19.0
+
diff --git a/patches/1090-ARM-dts-r8a7745-Add-IPMMU-DT-nodes.patch b/patches/1090-ARM-dts-r8a7745-Add-IPMMU-DT-nodes.patch
new file mode 100644
index 00000000000000..84592ef31e78cf
--- /dev/null
+++ b/patches/1090-ARM-dts-r8a7745-Add-IPMMU-DT-nodes.patch
@@ -0,0 +1,90 @@
+From fe036b54c38016e3b72a497f531d909c70d10e82 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 24 Jan 2018 15:42:02 +0000
+Subject: [PATCH 1090/1795] ARM: dts: r8a7745: Add IPMMU DT nodes
+
+Add the six IPMMU instances found in the r8a7745 to DT with a disabled
+status.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0dcba3de58354e35c91a31dafe597e81e7c22294)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 58 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 9c8d72c83bdc..413288b05515 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -288,6 +288,64 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		ipmmu_sy0: mmu@e6280000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6280000 0 0x1000>;
++			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_sy1: mmu@e6290000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6290000 0 0x1000>;
++			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe6740000 0 0x1000>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mp: mmu@ec680000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xec680000 0 0x1000>;
++			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mx: mmu@fe951000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xfe951000 0 0x1000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_gp: mmu@e62a0000 {
++			compatible = "renesas,ipmmu-r8a7745",
++				     "renesas,ipmmu-vmsa";
++			reg = <0 0xe62a0000 0 0x1000>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
+ 		icram0:	sram@e63a0000 {
+ 			compatible = "mmio-sram";
+ 			reg = <0 0xe63a0000 0 0x12000>;
+-- 
+2.19.0
+
diff --git a/patches/1091-ARM-dts-r8a7743-Add-VSP-support.patch b/patches/1091-ARM-dts-r8a7743-Add-VSP-support.patch
new file mode 100644
index 00000000000000..4eb1c39e1730ce
--- /dev/null
+++ b/patches/1091-ARM-dts-r8a7743-Add-VSP-support.patch
@@ -0,0 +1,58 @@
+From be12900deace74fb5f76e9f13cdb54355576556f Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 24 Jan 2018 16:11:51 +0000
+Subject: [PATCH 1091/1795] ARM: dts: r8a7743: Add VSP support
+
+Add VSP support to SoC DT.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0565605aa9887a3d6423fb08c0cbb0de3a22f838)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 11a1263211eb..1d9073ba0ce0 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -1630,6 +1630,33 @@
+ 			status = "disabled";
+ 		};
+ 
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
++
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
++
++		vsp@fe938000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe938000 0 0x8000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 127>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7743";
+ 			reg = <0 0xfeb00000 0 0x40000>,
+-- 
+2.19.0
+
diff --git a/patches/1092-ARM-dts-r8a7745-Add-VSP-support.patch b/patches/1092-ARM-dts-r8a7745-Add-VSP-support.patch
new file mode 100644
index 00000000000000..528edcec4c75ec
--- /dev/null
+++ b/patches/1092-ARM-dts-r8a7745-Add-VSP-support.patch
@@ -0,0 +1,49 @@
+From b16583fe1764931edc9827e0af8bbacc8615a4d5 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 24 Jan 2018 16:11:52 +0000
+Subject: [PATCH 1092/1795] ARM: dts: r8a7745: Add VSP support
+
+Add VSP support to SoC DT.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 76a2577d97f0b221245e56a17a70bb10a3a97419)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 413288b05515..dd49a8b48f3e 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -1465,6 +1465,24 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
++		vsp@fe928000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe928000 0 0x8000>;
++			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 131>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 131>;
++		};
++
++		vsp@fe930000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe930000 0 0x8000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 128>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 128>;
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7745";
+ 			reg = <0 0xfeb00000 0 0x40000>;
+-- 
+2.19.0
+
diff --git a/patches/1093-ARM-dts-lager-use-demuxer-for-IIC2-I2C2.patch b/patches/1093-ARM-dts-lager-use-demuxer-for-IIC2-I2C2.patch
new file mode 100644
index 00000000000000..0a8b53f8db1a86
--- /dev/null
+++ b/patches/1093-ARM-dts-lager-use-demuxer-for-IIC2-I2C2.patch
@@ -0,0 +1,283 @@
+From c820a27355fc8ad7154b206655a38724abacde19 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:50 +0100
+Subject: [PATCH 1093/1795] ARM: dts: lager: use demuxer for IIC2/I2C2
+
+Create a separate bus for HDMI related I2C slaves.
+
+Based on work by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, removed typo in comment, fixed aliases, switched to
+named GPIOS, sort SCL pins first]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 4e65e1b6721aafca073a308ae7f32e1cdddfdcd8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 213 ++++++++++++++++------------
+ 1 file changed, 124 insertions(+), 89 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index 7892b113ecaa..9f511d4fac10 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -51,8 +51,10 @@
+ 		serial0 = &scif0;
+ 		serial1 = &scifa1;
+ 		i2c8 = &gpioi2c1;
++		i2c9 = &gpioi2c2;
+ 		i2c10 = &i2cexio0;
+ 		i2c11 = &i2cexio1;
++		i2c12 = &i2chdmi;
+ 	};
+ 
+ 	chosen {
+@@ -272,8 +274,18 @@
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
++	gpioi2c2: i2c-9 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+@@ -308,6 +320,104 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 	};
++
++        /*
++         * IIC2 and I2C2 may be switched using pinmux.
++         * A fallback to GPIO is also provided.
++         */
++	i2chdmi: i2c-12 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ak4643: codec@12 {
++			compatible = "asahi-kasei,ak4643";
++			#sound-dai-cells = <0>;
++			reg = <0x12>;
++		};
++
++		composite-in@20 {
++			compatible = "adi,adv7180";
++			reg = <0x20>;
++			remote = <&vin1>;
++
++			port {
++				adv7180: endpoint {
++					bus-width = <8>;
++					remote-endpoint = <&vin1ep0>;
++				};
++			};
++		};
++
++		cec_clock: cec-clock {
++			compatible = "fixed-clock";
++			#clock-cells = <0>;
++			clock-frequency = <12000000>;
++		};
++
++		hdmi@39 {
++			compatible = "adi,adv7511w";
++			reg = <0x39>;
++			interrupt-parent = <&gpio1>;
++			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
++			clocks = <&cec_clock>;
++			clock-names = "cec";
++
++			adi,input-depth = <8>;
++			adi,input-colorspace = "rgb";
++			adi,input-clock = "1x";
++			adi,input-style = <1>;
++			adi,input-justification = "evenly";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7511_in: endpoint {
++						remote-endpoint = <&du_out_lvds0>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					adv7511_out: endpoint {
++						remote-endpoint = <&hdmi_con_out>;
++					};
++				};
++			};
++		};
++
++		hdmi-in@4c {
++			compatible = "adi,adv7612";
++			reg = <0x4c>;
++			interrupt-parent = <&gpio1>;
++			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
++			default-input = <0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7612_in: endpoint {
++						remote-endpoint = <&hdmi_con_in>;
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					adv7612_out: endpoint {
++						remote-endpoint = <&vin0ep2>;
++					};
++				};
++			};
++		};
++	};
+ };
+ 
+ &du {
+@@ -437,6 +547,11 @@
+ 		function = "iic1";
+ 	};
+ 
++	i2c2_pins: i2c2 {
++		groups = "i2c2";
++		function = "i2c2";
++	};
++
+ 	iic2_pins: iic2 {
+ 		groups = "iic2";
+ 		function = "iic2";
+@@ -643,98 +758,18 @@
+ 	pinctrl-names = "i2c-exio1";
+ };
+ 
+-&iic2	{
+-	status = "okay";
+-	pinctrl-0 = <&iic2_pins>;
+-	pinctrl-names = "default";
++&i2c2	{
++	pinctrl-0 = <&i2c2_pins>;
++	pinctrl-names = "i2c-hdmi";
+ 
+ 	clock-frequency = <100000>;
++};
+ 
+-	ak4643: codec@12 {
+-		compatible = "asahi-kasei,ak4643";
+-		#sound-dai-cells = <0>;
+-		reg = <0x12>;
+-	};
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180";
+-		reg = <0x20>;
+-		remote = <&vin1>;
+-
+-		port {
+-			adv7180: endpoint {
+-				bus-width = <8>;
+-				remote-endpoint = <&vin1ep0>;
+-			};
+-		};
+-	};
+-
+-	cec_clock: cec-clock {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <12000000>;
+-	};
+-
+-	hdmi@39 {
+-		compatible = "adi,adv7511w";
+-		reg = <0x39>;
+-		interrupt-parent = <&gpio1>;
+-		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+-		clocks = <&cec_clock>;
+-		clock-names = "cec";
+-
+-		adi,input-depth = <8>;
+-		adi,input-colorspace = "rgb";
+-		adi,input-clock = "1x";
+-		adi,input-style = <1>;
+-		adi,input-justification = "evenly";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7511_in: endpoint {
+-					remote-endpoint = <&du_out_lvds0>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-				adv7511_out: endpoint {
+-					remote-endpoint = <&hdmi_con_out>;
+-				};
+-			};
+-		};
+-	};
+-
+-	hdmi-in@4c {
+-		compatible = "adi,adv7612";
+-		reg = <0x4c>;
+-		interrupt-parent = <&gpio1>;
+-		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+-		default-input = <0>;
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7612_in: endpoint {
+-					remote-endpoint = <&hdmi_con_in>;
+-				};
+-			};
++&iic2	{
++	pinctrl-0 = <&iic2_pins>;
++	pinctrl-names = "i2c-hdmi";
+ 
+-			port@2 {
+-				reg = <2>;
+-				adv7612_out: endpoint {
+-					remote-endpoint = <&vin0ep2>;
+-				};
+-			};
+-		};
+-	};
++	clock-frequency = <100000>;
+ };
+ 
+ &iic3 {
+-- 
+2.19.0
+
diff --git a/patches/1094-ARM-dts-lager-use-demuxer-for-IIC3-I2C3.patch b/patches/1094-ARM-dts-lager-use-demuxer-for-IIC3-I2C3.patch
new file mode 100644
index 00000000000000..ec9babf5d55d9b
--- /dev/null
+++ b/patches/1094-ARM-dts-lager-use-demuxer-for-IIC3-I2C3.patch
@@ -0,0 +1,141 @@
+From 09da92c4a0d52601c8e0d6c58274b62a0e0d458b Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:51 +0100
+Subject: [PATCH 1094/1795] ARM: dts: lager: use demuxer for IIC3/I2C3
+
+Create a separate bus for da9063 PMIC and da9210 regulator
+related I2C slaves.
+
+Based on similar work for HDMI by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, corrected chip name in commit msg, updated aliases]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit e6081b21a19156c982f757cb1b6753cfb7e93ebc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 84 ++++++++++++++++++-----------
+ 1 file changed, 53 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index 9f511d4fac10..20c1b4f224b8 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -55,6 +55,7 @@
+ 		i2c10 = &i2cexio0;
+ 		i2c11 = &i2cexio1;
+ 		i2c12 = &i2chdmi;
++		i2c13 = &i2cpwr;
+ 	};
+ 
+ 	chosen {
+@@ -418,6 +419,46 @@
+ 			};
+ 		};
+ 	};
++
++	/*
++	 * IIC3 and I2C3 may be switched using pinmux.
++	 * IIC3/I2C3 does not appear to support fallback to GPIO.
++	 */
++	i2cpwr: i2c-13 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&iic3>, <&i2c3>;
++		i2c-bus-name = "i2c-pwr";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		pmic@58 {
++			compatible = "dlg,da9063";
++			reg = <0x58>;
++			interrupt-parent = <&irqc0>;
++			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++			interrupt-controller;
++
++			rtc {
++				compatible = "dlg,da9063-rtc";
++			};
++
++			wdt {
++				compatible = "dlg,da9063-watchdog";
++			};
++		};
++
++		vdd_dvfs: regulator@68 {
++			compatible = "dlg,da9210";
++			reg = <0x68>;
++			interrupt-parent = <&irqc0>;
++			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++
++			regulator-min-microvolt = <1000000>;
++			regulator-max-microvolt = <1000000>;
++			regulator-boot-on;
++			regulator-always-on;
++		};
++	};
+ };
+ 
+ &du {
+@@ -557,6 +598,11 @@
+ 		function = "iic2";
+ 	};
+ 
++	i2c3_pins: i2c3 {
++		groups = "i2c3";
++		function = "i2c3";
++	};
++
+ 	iic3_pins: iic3 {
+ 		groups = "iic3";
+ 		function = "iic3";
+@@ -772,38 +818,14 @@
+ 	clock-frequency = <100000>;
+ };
+ 
+-&iic3 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&iic3_pins>;
+-	status = "okay";
+-
+-	pmic@58 {
+-		compatible = "dlg,da9063";
+-		reg = <0x58>;
+-		interrupt-parent = <&irqc0>;
+-		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+-		interrupt-controller;
+-
+-		rtc {
+-			compatible = "dlg,da9063-rtc";
+-		};
+-
+-		wdt {
+-			compatible = "dlg,da9063-watchdog";
+-		};
+-	};
+-
+-	vdd_dvfs: regulator@68 {
+-		compatible = "dlg,da9210";
+-		reg = <0x68>;
+-		interrupt-parent = <&irqc0>;
+-		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++&i2c3	{
++	pinctrl-0 = <&i2c3_pins>;
++	pinctrl-names = "i2c-pwr";
++};
+ 
+-		regulator-min-microvolt = <1000000>;
+-		regulator-max-microvolt = <1000000>;
+-		regulator-boot-on;
+-		regulator-always-on;
+-	};
++&iic3	{
++	pinctrl-0 = <&iic3_pins>;
++	pinctrl-names = "i2c-pwr";
+ };
+ 
+ &pci0 {
+-- 
+2.19.0
+
diff --git a/patches/1095-ARM-dts-koelsch-use-demuxer-for-I2C2.patch b/patches/1095-ARM-dts-koelsch-use-demuxer-for-I2C2.patch
new file mode 100644
index 00000000000000..ee3ad4da9aea8e
--- /dev/null
+++ b/patches/1095-ARM-dts-koelsch-use-demuxer-for-I2C2.patch
@@ -0,0 +1,260 @@
+From b9e79fc0ffba66e6548c445932002af7df94c53f Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:52 +0100
+Subject: [PATCH 1095/1795] ARM: dts: koelsch: use demuxer for I2C2
+
+Create a separate bus for HDMI related I2C2 and provide fallback to GPIO.
+
+Based on work for the r8a7790/lager by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, fixed aliases, switched to named GPIOs, sorted by SCL
+pins]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 168a70999401e516fdf63dca742218bab04996a4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 200 ++++++++++++++------------
+ 1 file changed, 111 insertions(+), 89 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index a50924d12b6f..4b20db197de6 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -51,7 +51,9 @@
+ 		serial0 = &scif0;
+ 		serial1 = &scif1;
+ 		i2c9 = &gpioi2c1;
++		i2c10 = &gpioi2c2;
+ 		i2c12 = &i2cexio1;
++		i2c13 = &i2chdmi;
+ 	};
+ 
+ 	chosen {
+@@ -312,8 +314,18 @@
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
++	gpioi2c2: i2c-10 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
+@@ -328,6 +340,103 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 	};
++
++	/*
++	 * A fallback to GPIO is provided for I2C2.
++	 */
++	i2chdmi: i2c-13 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c2>, <&gpioi2c2>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ak4643: codec@12 {
++			compatible = "asahi-kasei,ak4643";
++			#sound-dai-cells = <0>;
++			reg = <0x12>;
++		};
++
++		composite-in@20 {
++			compatible = "adi,adv7180";
++			reg = <0x20>;
++			remote = <&vin1>;
++
++			port {
++				adv7180: endpoint {
++					bus-width = <8>;
++					remote-endpoint = <&vin1ep>;
++				};
++			};
++		};
++
++		hdmi@39 {
++			compatible = "adi,adv7511w";
++			reg = <0x39>;
++			interrupt-parent = <&gpio3>;
++			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
++			clocks = <&cec_clock>;
++			clock-names = "cec";
++
++			adi,input-depth = <8>;
++			adi,input-colorspace = "rgb";
++			adi,input-clock = "1x";
++			adi,input-style = <1>;
++			adi,input-justification = "evenly";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7511_in: endpoint {
++						remote-endpoint = <&du_out_rgb>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					adv7511_out: endpoint {
++						remote-endpoint = <&hdmi_con_out>;
++					};
++				};
++			};
++		};
++
++		hdmi-in@4c {
++			compatible = "adi,adv7612";
++			reg = <0x4c>;
++			interrupt-parent = <&gpio4>;
++			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++			default-input = <0>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7612_in: endpoint {
++						remote-endpoint = <&hdmi_con_in>;
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					adv7612_out: endpoint {
++						remote-endpoint = <&vin0ep2>;
++					};
++				};
++			};
++		};
++
++		eeprom@50 {
++			compatible = "renesas,r1ex24002", "atmel,24c02";
++			reg = <0x50>;
++			pagesize = <16>;
++		};
++	};
+ };
+ 
+ &du {
+@@ -621,96 +730,9 @@
+ 
+ &i2c2 {
+ 	pinctrl-0 = <&i2c2_pins>;
+-	pinctrl-names = "default";
++	pinctrl-names = "i2c-hdmi";
+ 
+-	status = "okay";
+ 	clock-frequency = <100000>;
+-
+-	ak4643: codec@12 {
+-		compatible = "asahi-kasei,ak4643";
+-		#sound-dai-cells = <0>;
+-		reg = <0x12>;
+-	};
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180";
+-		reg = <0x20>;
+-		remote = <&vin1>;
+-
+-		port {
+-			adv7180: endpoint {
+-				bus-width = <8>;
+-				remote-endpoint = <&vin1ep>;
+-			};
+-		};
+-	};
+-
+-	hdmi@39 {
+-		compatible = "adi,adv7511w";
+-		reg = <0x39>;
+-		interrupt-parent = <&gpio3>;
+-		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+-		clocks = <&cec_clock>;
+-		clock-names = "cec";
+-
+-		adi,input-depth = <8>;
+-		adi,input-colorspace = "rgb";
+-		adi,input-clock = "1x";
+-		adi,input-style = <1>;
+-		adi,input-justification = "evenly";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7511_in: endpoint {
+-					remote-endpoint = <&du_out_rgb>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-				adv7511_out: endpoint {
+-					remote-endpoint = <&hdmi_con_out>;
+-				};
+-			};
+-		};
+-	};
+-
+-	hdmi-in@4c {
+-		compatible = "adi,adv7612";
+-		reg = <0x4c>;
+-		interrupt-parent = <&gpio4>;
+-		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+-		default-input = <0>;
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7612_in: endpoint {
+-					remote-endpoint = <&hdmi_con_in>;
+-				};
+-			};
+-
+-			port@2 {
+-				reg = <2>;
+-				adv7612_out: endpoint {
+-					remote-endpoint = <&vin0ep2>;
+-				};
+-			};
+-		};
+-	};
+-
+-	eeprom@50 {
+-		compatible = "renesas,r1ex24002", "atmel,24c02";
+-		reg = <0x50>;
+-		pagesize = <16>;
+-	};
+ };
+ 
+ &i2c6 {
+-- 
+2.19.0
+
diff --git a/patches/1096-ARM-dts-koelsch-use-demuxer-for-I2C4.patch b/patches/1096-ARM-dts-koelsch-use-demuxer-for-I2C4.patch
new file mode 100644
index 00000000000000..22b2f0d1dd090e
--- /dev/null
+++ b/patches/1096-ARM-dts-koelsch-use-demuxer-for-I2C4.patch
@@ -0,0 +1,99 @@
+From ce36a16a5f3306e13e87d3de38387cd87a66ccd1 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:53 +0100
+Subject: [PATCH 1096/1795] ARM: dts: koelsch: use demuxer for I2C4
+
+Make it possible to fallback to GPIO for I2C4 on the EXIO-E connector.
+
+This is based on reference work for the I2C0 core of the lager/r8a7790
+by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, fixed aliases, switched to named GPIOS, fixed pinmux for I2C4]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit be93275c4dade2d089d495f38a09e62712ea4e39)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 34 +++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index 4b20db197de6..f40321a1c917 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -52,8 +52,10 @@
+ 		serial1 = &scif1;
+ 		i2c9 = &gpioi2c1;
+ 		i2c10 = &gpioi2c2;
++		i2c11 = &gpioi2c4;
+ 		i2c12 = &i2cexio1;
+ 		i2c13 = &i2chdmi;
++		i2c14 = &i2cexio4;
+ 	};
+ 
+ 	chosen {
+@@ -329,6 +331,16 @@
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
++	gpioi2c4: i2c-11 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
+ 	/*
+ 	 * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
+ 	 * A fallback to GPIO is provided.
+@@ -437,6 +449,18 @@
+ 			pagesize = <16>;
+ 		};
+ 	};
++
++	/*
++	 * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
++	 * A fallback to GPIO is provided.
++	 */
++	i2cexio4: i2c-14 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c4>, <&gpioi2c4>;
++		i2c-bus-name = "i2c-exio4";
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
+ };
+ 
+ &du {
+@@ -480,6 +504,11 @@
+ 		function = "i2c2";
+ 	};
+ 
++	i2c4_pins: i2c4 {
++		groups = "i2c4_c";
++		function = "i2c4";
++	};
++
+ 	du_pins: du {
+ 		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ 		function = "du";
+@@ -735,6 +764,11 @@
+ 	clock-frequency = <100000>;
+ };
+ 
++&i2c4 {
++	pinctrl-0 = <&i2c4_pins>;
++	pinctrl-names = "i2c-exio4";
++};
++
+ &i2c6 {
+ 	status = "okay";
+ 	clock-frequency = <100000>;
+-- 
+2.19.0
+
diff --git a/patches/1097-ARM-dts-porter-use-demuxer-for-I2C2.patch b/patches/1097-ARM-dts-porter-use-demuxer-for-I2C2.patch
new file mode 100644
index 00000000000000..53880b117c2437
--- /dev/null
+++ b/patches/1097-ARM-dts-porter-use-demuxer-for-I2C2.patch
@@ -0,0 +1,178 @@
+From 4f6612e24dfa37fc992d227056ae5130991e9ae2 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:54 +0100
+Subject: [PATCH 1097/1795] ARM: dts: porter: use demuxer for I2C2
+
+Create a separate bus for HDMI related I2C2 and provide fallback to GPIO.
+
+Based on work for the r8a7790/lager by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, fixed aliases, switched to named GPIOs]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 12937bffd64f5b9970589d0b946305d14cc45e6a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-porter.dts | 128 ++++++++++++++++-----------
+ 1 file changed, 75 insertions(+), 53 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
+index 9a02d03b23c2..c14e6fe9e4f6 100644
+--- a/arch/arm/boot/dts/r8a7791-porter.dts
++++ b/arch/arm/boot/dts/r8a7791-porter.dts
+@@ -29,6 +29,8 @@
+ 
+ 	aliases {
+ 		serial0 = &scif0;
++		i2c9 = &gpioi2c2;
++		i2c10 = &i2chdmi;
+ 	};
+ 
+ 	chosen {
+@@ -135,6 +137,78 @@
+ 			clocks = <&x14_clk>;
+ 		};
+ 	};
++
++	gpioi2c2: i2c-9 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
++	/*
++	 * A fallback to GPIO is provided for I2C2.
++	 */
++	i2chdmi: i2c-10 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c2>, <&gpioi2c2>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ak4642: codec@12 {
++			compatible = "asahi-kasei,ak4642";
++			#sound-dai-cells = <0>;
++			reg = <0x12>;
++		};
++
++		composite-in@20 {
++			compatible = "adi,adv7180";
++			reg = <0x20>;
++			remote = <&vin0>;
++
++			port {
++				adv7180: endpoint {
++					bus-width = <8>;
++					remote-endpoint = <&vin0ep>;
++				};
++			};
++		};
++
++		hdmi@39 {
++			compatible = "adi,adv7511w";
++			reg = <0x39>;
++			interrupt-parent = <&gpio3>;
++			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
++
++			adi,input-depth = <8>;
++			adi,input-colorspace = "rgb";
++			adi,input-clock = "1x";
++			adi,input-style = <1>;
++			adi,input-justification = "evenly";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7511_in: endpoint {
++						remote-endpoint = <&du_out_rgb>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					adv7511_out: endpoint {
++						remote-endpoint = <&hdmi_con>;
++					};
++				};
++			};
++		};
++	};
+ };
+ 
+ &extal_clk {
+@@ -296,61 +370,9 @@
+ 
+ &i2c2 {
+ 	pinctrl-0 = <&i2c2_pins>;
+-	pinctrl-names = "default";
++	pinctrl-names = "i2c-hdmi";
+ 
+-	status = "okay";
+ 	clock-frequency = <400000>;
+-
+-	ak4642: codec@12 {
+-		compatible = "asahi-kasei,ak4642";
+-		#sound-dai-cells = <0>;
+-		reg = <0x12>;
+-	};
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180";
+-		reg = <0x20>;
+-		remote = <&vin0>;
+-
+-		port {
+-			adv7180: endpoint {
+-				bus-width = <8>;
+-				remote-endpoint = <&vin0ep>;
+-			};
+-		};
+-	};
+-
+-	hdmi@39 {
+-		compatible = "adi,adv7511w";
+-		reg = <0x39>;
+-		interrupt-parent = <&gpio3>;
+-		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+-
+-		adi,input-depth = <8>;
+-		adi,input-colorspace = "rgb";
+-		adi,input-clock = "1x";
+-		adi,input-style = <1>;
+-		adi,input-justification = "evenly";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7511_in: endpoint {
+-					remote-endpoint = <&du_out_rgb>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-				adv7511_out: endpoint {
+-					remote-endpoint = <&hdmi_con>;
+-				};
+-			};
+-		};
+-	};
+ };
+ 
+ &sata0 {
+-- 
+2.19.0
+
diff --git a/patches/1098-ARM-dts-alt-use-demuxer-for-I2C1.patch b/patches/1098-ARM-dts-alt-use-demuxer-for-I2C1.patch
new file mode 100644
index 00000000000000..95b680c521e403
--- /dev/null
+++ b/patches/1098-ARM-dts-alt-use-demuxer-for-I2C1.patch
@@ -0,0 +1,113 @@
+From 75212b02e4951e7c0b960c5e0deec8507ef8b425 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:55 +0100
+Subject: [PATCH 1098/1795] ARM: dts: alt: use demuxer for I2C1
+
+Create a separate bus for HDMI related I2C1 and provide fallback to GPIO.
+
+Based on work for the r8a7790/lager by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, fixed aliases, switched to named GPIOs]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 61866d7fdc7007acfca2107f7d9fcb05ed0c6203)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 53 +++++++++++++++++++++----------
+ 1 file changed, 37 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index 60c6515c4996..26a883484ea8 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -18,7 +18,9 @@
+ 
+ 	aliases {
+ 		serial0 = &scif2;
++		i2c9 = &gpioi2c1;
+ 		i2c10 = &gpioi2c4;
++		i2c11 = &i2chdmi;
+ 		i2c12 = &i2cexio4;
+ 	};
+ 
+@@ -138,16 +140,49 @@
+ 		clock-frequency = <148500000>;
+ 	};
+ 
++	gpioi2c1: i2c-9 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++	};
++
+ 	gpioi2c4: i2c-10 {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 		compatible = "i2c-gpio";
+ 		status = "disabled";
+-		sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
++	/*
++	 * A fallback to GPIO is provided for I2C1.
++	 */
++	i2chdmi: i2c-11 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c1>, <&gpioi2c1>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		composite-in@20 {
++			compatible = "adi,adv7180";
++			reg = <0x20>;
++			remote = <&vin0>;
++
++			port {
++				adv7180: endpoint {
++					bus-width = <8>;
++					remote-endpoint = <&vin0ep>;
++				};
++			};
++		};
++	};
++
+ 	/*
+ 	 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
+ 	 * A fallback to GPIO is provided.
+@@ -324,23 +359,9 @@
+ 
+ &i2c1 {
+ 	pinctrl-0 = <&i2c1_pins>;
+-	pinctrl-names = "default";
++	pinctrl-names = "i2c-hdmi";
+ 
+-	status = "okay";
+ 	clock-frequency = <400000>;
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180";
+-		reg = <0x20>;
+-		remote = <&vin0>;
+-
+-		port {
+-			adv7180: endpoint {
+-				bus-width = <8>;
+-				remote-endpoint = <&vin0ep>;
+-			};
+-		};
+-	};
+ };
+ 
+ &i2c4 {
+-- 
+2.19.0
+
diff --git a/patches/1099-ARM-dts-silk-use-demuxer-for-I2C1.patch b/patches/1099-ARM-dts-silk-use-demuxer-for-I2C1.patch
new file mode 100644
index 00000000000000..a56836197d5b83
--- /dev/null
+++ b/patches/1099-ARM-dts-silk-use-demuxer-for-I2C1.patch
@@ -0,0 +1,178 @@
+From 0af6d53b28dc202ac1292aafe1dba1d4c98073ec Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:56 +0100
+Subject: [PATCH 1099/1795] ARM: dts: silk: use demuxer for I2C1
+
+Create a separate bus for HDMI related I2C1 and provide fallback to GPIO.
+
+Based on work for the r8a7790/lager by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, fixed aliases, switched to named GPIOs]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit d4c1ce2813942407cead7adb86d1dd9dfc46f74c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-silk.dts | 128 +++++++++++++++++------------
+ 1 file changed, 75 insertions(+), 53 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index edfad0e5ac53..f1afe2dda13a 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -31,6 +31,8 @@
+ 
+ 	aliases {
+ 		serial0 = &scif2;
++		i2c9 = &gpioi2c1;
++		i2c10 = &i2chdmi;
+ 	};
+ 
+ 	chosen {
+@@ -153,6 +155,78 @@
+ 			clocks = <&x9_clk>;
+ 		};
+ 	};
++
++	gpioi2c1: i2c-9 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
++	/*
++	 * A fallback to GPIO is provided for I2C1.
++	 */
++	i2chdmi: i2c-10 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c1>, <&gpioi2c1>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ak4643: codec@12 {
++			compatible = "asahi-kasei,ak4643";
++			#sound-dai-cells = <0>;
++			reg = <0x12>;
++		};
++
++		composite-in@20 {
++			compatible = "adi,adv7180";
++			reg = <0x20>;
++			remote = <&vin0>;
++
++			port {
++				adv7180: endpoint {
++					bus-width = <8>;
++					remote-endpoint = <&vin0ep>;
++				};
++			};
++		};
++
++		hdmi@39 {
++			compatible = "adi,adv7511w";
++			reg = <0x39>;
++			interrupt-parent = <&gpio5>;
++			interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
++
++			adi,input-depth = <8>;
++			adi,input-colorspace = "rgb";
++			adi,input-clock = "1x";
++			adi,input-style = <1>;
++			adi,input-justification = "evenly";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7511_in: endpoint {
++						remote-endpoint = <&du_out_rgb0>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					adv7511_out: endpoint {
++						remote-endpoint = <&hdmi_con>;
++					};
++				};
++			};
++		};
++	};
+ };
+ 
+ &extal_clk {
+@@ -268,61 +342,9 @@
+ 
+ &i2c1 {
+ 	pinctrl-0 = <&i2c1_pins>;
+-	pinctrl-names = "default";
++	pinctrl-names = "i2c-hdmi";
+ 
+-	status = "okay";
+ 	clock-frequency = <400000>;
+-
+-	ak4643: codec@12 {
+-		compatible = "asahi-kasei,ak4643";
+-		#sound-dai-cells = <0>;
+-		reg = <0x12>;
+-	};
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180";
+-		reg = <0x20>;
+-		remote = <&vin0>;
+-
+-		port {
+-			adv7180: endpoint {
+-				bus-width = <8>;
+-				remote-endpoint = <&vin0ep>;
+-			};
+-		};
+-	};
+-
+-	hdmi@39 {
+-		compatible = "adi,adv7511w";
+-		reg = <0x39>;
+-		interrupt-parent = <&gpio5>;
+-		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+-
+-		adi,input-depth = <8>;
+-		adi,input-colorspace = "rgb";
+-		adi,input-clock = "1x";
+-		adi,input-style = <1>;
+-		adi,input-justification = "evenly";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7511_in: endpoint {
+-					remote-endpoint = <&du_out_rgb0>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-				adv7511_out: endpoint {
+-					remote-endpoint = <&hdmi_con>;
+-				};
+-			};
+-		};
+-	};
+ };
+ 
+ &mmcif0 {
+-- 
+2.19.0
+
diff --git a/patches/1100-ARM-dts-gose-use-demuxer-for-I2C2.patch b/patches/1100-ARM-dts-gose-use-demuxer-for-I2C2.patch
new file mode 100644
index 00000000000000..2eff76b4e515de
--- /dev/null
+++ b/patches/1100-ARM-dts-gose-use-demuxer-for-I2C2.patch
@@ -0,0 +1,271 @@
+From f536523942c4ec5ae2486d4398af803cd3b5ee7d Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:57 +0100
+Subject: [PATCH 1100/1795] ARM: dts: gose: use demuxer for I2C2
+
+Create a separate bus for HDMI related I2C2 and provide fallback to GPIO.
+
+Based on work for the r8a7790/lager by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, corrected board name in subject, fixed aliases, switched
+to named GPIOs]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 786ef2eeb04cca41d6382556f1409f37f64c4a0c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts | 218 ++++++++++++++++-------------
+ 1 file changed, 121 insertions(+), 97 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 51b3ffac8efa..2b330ef71f4c 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -48,6 +48,8 @@
+ 	aliases {
+ 		serial0 = &scif0;
+ 		serial1 = &scif1;
++		i2c9 = &gpioi2c2;
++		i2c11 = &i2chdmi;
+ 	};
+ 
+ 	chosen {
+@@ -296,6 +298,124 @@
+ 		#clock-cells = <0>;
+ 		clock-frequency = <148500000>;
+ 	};
++
++	gpioi2c2: i2c-9 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
++	/*
++	 * A fallback to GPIO is provided for I2C2.
++	 */
++	i2chdmi: i2c-11 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c2>, <&gpioi2c2>;
++		i2c-bus-name = "i2c-hdmi";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ak4643: codec@12 {
++			compatible = "asahi-kasei,ak4643";
++			#sound-dai-cells = <0>;
++			reg = <0x12>;
++		};
++
++		composite-in@20 {
++			compatible = "adi,adv7180cp";
++			reg = <0x20>;
++			remote = <&vin1>;
++
++			port {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7180_in: endpoint {
++						remote-endpoint = <&composite_con_in>;
++					};
++				};
++
++				port@3 {
++					reg = <3>;
++					adv7180_out: endpoint {
++						bus-width = <8>;
++						remote-endpoint = <&vin1ep>;
++					};
++				};
++			};
++		};
++
++		hdmi@39 {
++			compatible = "adi,adv7511w";
++			reg = <0x39>;
++			interrupt-parent = <&gpio3>;
++			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
++
++			adi,input-depth = <8>;
++			adi,input-colorspace = "rgb";
++			adi,input-clock = "1x";
++			adi,input-style = <1>;
++			adi,input-justification = "evenly";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7511_in: endpoint {
++						remote-endpoint = <&du_out_rgb>;
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					adv7511_out: endpoint {
++						remote-endpoint = <&hdmi_con_out>;
++					};
++				};
++			};
++		};
++
++		hdmi-in@4c {
++			compatible = "adi,adv7612";
++			reg = <0x4c>;
++			interrupt-parent = <&gpio4>;
++			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++			default-input = <0>;
++
++			port {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					adv7612_in: endpoint {
++						remote-endpoint = <&hdmi_con_in>;
++					};
++				};
++
++				port@2 {
++					reg = <2>;
++					adv7612_out: endpoint {
++						remote-endpoint = <&vin0ep2>;
++					};
++				};
++			};
++		};
++
++		eeprom@50 {
++			compatible = "renesas,r1ex24002", "atmel,24c02";
++			reg = <0x50>;
++			pagesize = <16>;
++		};
++	};
+ };
+ 
+ &du {
+@@ -544,107 +664,11 @@
+ 
+ &i2c2 {
+ 	pinctrl-0 = <&i2c2_pins>;
+-	pinctrl-names = "default";
++	pinctrl-names = "i2c-hdmi";
+ 
+ 	status = "okay";
+ 	clock-frequency = <100000>;
+ 
+-	ak4643: codec@12 {
+-		compatible = "asahi-kasei,ak4643";
+-		#sound-dai-cells = <0>;
+-		reg = <0x12>;
+-	};
+-
+-	composite-in@20 {
+-		compatible = "adi,adv7180cp";
+-		reg = <0x20>;
+-		remote = <&vin1>;
+-
+-		port {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7180_in: endpoint {
+-					remote-endpoint = <&composite_con_in>;
+-				};
+-			};
+-
+-			port@3 {
+-				reg = <3>;
+-				adv7180_out: endpoint {
+-					bus-width = <8>;
+-					remote-endpoint = <&vin1ep>;
+-				};
+-			};
+-		};
+-	};
+-
+-	hdmi@39 {
+-		compatible = "adi,adv7511w";
+-		reg = <0x39>;
+-		interrupt-parent = <&gpio3>;
+-		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+-
+-		adi,input-depth = <8>;
+-		adi,input-colorspace = "rgb";
+-		adi,input-clock = "1x";
+-		adi,input-style = <1>;
+-		adi,input-justification = "evenly";
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7511_in: endpoint {
+-					remote-endpoint = <&du_out_rgb>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-				adv7511_out: endpoint {
+-					remote-endpoint = <&hdmi_con_out>;
+-				};
+-			};
+-		};
+-	};
+-
+-	hdmi-in@4c {
+-		compatible = "adi,adv7612";
+-		reg = <0x4c>;
+-		interrupt-parent = <&gpio4>;
+-		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+-		default-input = <0>;
+-
+-		port {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				adv7612_in: endpoint {
+-					remote-endpoint = <&hdmi_con_in>;
+-				};
+-			};
+-
+-			port@2 {
+-				reg = <2>;
+-				adv7612_out: endpoint {
+-					remote-endpoint = <&vin0ep2>;
+-				};
+-			};
+-		};
+-	};
+-
+-	eeprom@50 {
+-		compatible = "renesas,r1ex24002", "atmel,24c02";
+-		reg = <0x50>;
+-		pagesize = <16>;
+-	};
+ };
+ 
+ &i2c6 {
+-- 
+2.19.0
+
diff --git a/patches/1101-ARM-dts-gose-use-demuxer-for-I2C4.patch b/patches/1101-ARM-dts-gose-use-demuxer-for-I2C4.patch
new file mode 100644
index 00000000000000..4eb38209148599
--- /dev/null
+++ b/patches/1101-ARM-dts-gose-use-demuxer-for-I2C4.patch
@@ -0,0 +1,99 @@
+From 1da224436828252e2cfa059a2bde07b87ac013fd Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 6 Feb 2018 23:29:58 +0100
+Subject: [PATCH 1101/1795] ARM: dts: gose: use demuxer for I2C4
+
+Make it possible to fallback to GPIO for I2C4 on the EXIO-E connector.
+
+This is based on reference work for the I2C0 core of the lager/r8a7790
+by Wolfram Sang.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+[wsa: rebased, corrected board name in subject, fixed aliases, switched
+to named GPIOs, fixed pinmux for I2C4]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+(cherry picked from commit 931bc7ec2d43f85c0b05aacb31bd1bd187ed7f65)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts | 34 ++++++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 2b330ef71f4c..9ed6961f2d9a 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -49,7 +49,9 @@
+ 		serial0 = &scif0;
+ 		serial1 = &scif1;
+ 		i2c9 = &gpioi2c2;
++		i2c10 = &gpioi2c4;
+ 		i2c11 = &i2chdmi;
++		i2c12 = &i2cexio4;
+ 	};
+ 
+ 	chosen {
+@@ -309,6 +311,16 @@
+ 		i2c-gpio,delay-us = <5>;
+ 	};
+ 
++	gpioi2c4: i2c-10 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++		scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <5>;
++	};
++
+ 	/*
+ 	 * A fallback to GPIO is provided for I2C2.
+ 	 */
+@@ -416,6 +428,18 @@
+ 			pagesize = <16>;
+ 		};
+ 	};
++
++	/*
++	 * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
++	 * A fallback to GPIO is provided.
++	 */
++	i2cexio4: i2c-12 {
++		compatible = "i2c-demux-pinctrl";
++		i2c-parent = <&i2c4>, <&gpioi2c4>;
++		i2c-bus-name = "i2c-exio4";
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
+ };
+ 
+ &du {
+@@ -454,6 +478,11 @@
+ 		function = "i2c2";
+ 	};
+ 
++	i2c4_pins: i2c4 {
++		groups = "i2c4_c";
++		function = "i2c4";
++	};
++
+ 	du_pins: du {
+ 		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ 		function = "du";
+@@ -692,6 +721,11 @@
+ 	};
+ };
+ 
++&i2c4 {
++	pinctrl-0 = <&i2c4_pins>;
++	pinctrl-names = "i2c-exio4";
++};
++
+ &rcar_sound {
+ 	pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1102-ARM-shmobile-Enable-RZA1-pin-controller.patch b/patches/1102-ARM-shmobile-Enable-RZA1-pin-controller.patch
new file mode 100644
index 00000000000000..f87dec24f4e862
--- /dev/null
+++ b/patches/1102-ARM-shmobile-Enable-RZA1-pin-controller.patch
@@ -0,0 +1,32 @@
+From 4dedd2c7353af96b42975bbc98a4f2121e7ed7bf Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 9 Feb 2018 18:34:18 +0100
+Subject: [PATCH 1102/1795] ARM: shmobile: Enable RZA1 pin controller
+
+Enable PINCTRL_RZA1 option in shmobile_defconfig
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f90d738ef6718b35ac7267b05a2e027c90e19f4d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index 578434cfd1a0..79b2b7c12264 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -120,6 +120,7 @@ CONFIG_SPI=y
+ CONFIG_SPI_RSPI=y
+ CONFIG_SPI_SH_MSIOF=y
+ CONFIG_SPI_SH_HSPI=y
++CONFIG_PINCTRL_RZA1=y
+ CONFIG_GPIO_EM=y
+ CONFIG_GPIO_RCAR=y
+ CONFIG_GPIO_PCF857X=y
+-- 
+2.19.0
+
diff --git a/patches/1103-ARM-shmobile-stout-enable-R-Car-Gen2-regulator-quirk.patch b/patches/1103-ARM-shmobile-stout-enable-R-Car-Gen2-regulator-quirk.patch
new file mode 100644
index 00000000000000..6eaf4a58e5390f
--- /dev/null
+++ b/patches/1103-ARM-shmobile-stout-enable-R-Car-Gen2-regulator-quirk.patch
@@ -0,0 +1,86 @@
+From 00105e09b7538936f55effd0e3b29af14118d36e Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 15 Feb 2018 12:33:50 +0100
+Subject: [PATCH 1103/1795] ARM: shmobile: stout: enable R-Car Gen2 regulator
+ quirk
+
+Regulator setup is suboptimal on H2 Stout too. The Stout newly has
+two DA9210 regulators, so the quirk is extended to handle another
+DA9210 at i2c address 0x70.
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ff938cd14d67a7040258759b46e3d5b4548f4c2c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../mach-shmobile/regulator-quirk-rcar-gen2.c | 23 +++++++++++++------
+ 1 file changed, 16 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+index 44438f344dc8..27fb3a5ec73e 100644
+--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+@@ -1,9 +1,9 @@
+ /*
+  * R-Car Generation 2 da9063/da9210 regulator quirk
+  *
+- * The r8a7790/lager and r8a7791/koelsch development boards have da9063 and
+- * da9210 regulators.  Both regulators have their interrupt request lines tied
+- * to the same interrupt pin (IRQ2) on the SoC.
++ * Certain Gen2 development boards have an da9063 and one or more da9210
++ * regulators. All of these regulators have their interrupt request lines
++ * tied to the same interrupt pin (IRQ2) on the SoC.
+  *
+  * After cold boot or da9063-induced restart, both the da9063 and da9210 seem
+  * to assert their interrupt request lines.  Hence as soon as one driver
+@@ -50,7 +50,7 @@ static void __iomem *irqc;
+ static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
+ static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
+ 
+-static struct i2c_msg da9xxx_msgs[2] = {
++static struct i2c_msg da9xxx_msgs[3] = {
+ 	{
+ 		.addr = 0x58,
+ 		.len = ARRAY_SIZE(da9063_irq_clr),
+@@ -59,6 +59,10 @@ static struct i2c_msg da9xxx_msgs[2] = {
+ 		.addr = 0x68,
+ 		.len = ARRAY_SIZE(da9210_irq_clr),
+ 		.buf = da9210_irq_clr,
++	}, {
++		.addr = 0x70,
++		.len = ARRAY_SIZE(da9210_irq_clr),
++		.buf = da9210_irq_clr,
+ 	},
+ };
+ 
+@@ -85,11 +89,15 @@ static int regulator_quirk_notify(struct notifier_block *nb,
+ 	dev_dbg(dev, "Detected %s\n", client->name);
+ 
+ 	if ((client->addr == 0x58 && !strcmp(client->name, "da9063")) ||
+-	    (client->addr == 0x68 && !strcmp(client->name, "da9210"))) {
+-		int ret;
++	    (client->addr == 0x68 && !strcmp(client->name, "da9210")) ||
++	    (client->addr == 0x70 && !strcmp(client->name, "da9210"))) {
++		int ret, len;
++
++		/* There are two DA9210 on Stout, one on the other boards. */
++		len = of_machine_is_compatible("renesas,stout") ? 3 : 2;
+ 
+ 		dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
+-		ret = i2c_transfer(client->adapter, da9xxx_msgs, ARRAY_SIZE(da9xxx_msgs));
++		ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
+ 		if (ret != ARRAY_SIZE(da9xxx_msgs))
+ 			dev_err(&client->dev, "i2c error %d\n", ret);
+ 	}
+@@ -118,6 +126,7 @@ static int __init rcar_gen2_regulator_quirk(void)
+ 
+ 	if (!of_machine_is_compatible("renesas,koelsch") &&
+ 	    !of_machine_is_compatible("renesas,lager") &&
++	    !of_machine_is_compatible("renesas,stout") &&
+ 	    !of_machine_is_compatible("renesas,gose"))
+ 		return -ENODEV;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1104-ARM-shmobile-rcar-gen2-Fix-error-check-in-regulator-.patch b/patches/1104-ARM-shmobile-rcar-gen2-Fix-error-check-in-regulator-.patch
new file mode 100644
index 00000000000000..7a7a1837f303cf
--- /dev/null
+++ b/patches/1104-ARM-shmobile-rcar-gen2-Fix-error-check-in-regulator-.patch
@@ -0,0 +1,41 @@
+From 1210c0f7d5dbaa72899e8448899c10900d1bfdff Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 28 Feb 2018 10:13:00 +0100
+Subject: [PATCH 1104/1795] ARM: shmobile: rcar-gen2: Fix error check in
+ regulator quirk
+
+On systems with two regulators, a bogus error message is printed on
+success:
+
+    i2c 6-0058: i2c error 2
+
+While adding support for Stout, the number of messages to send was
+made variable, but the corresponding return value check of
+i2c_transfer() wasn't updated.
+
+Fixes: ff938cd14d67a704 ("ARM: shmobile: stout: enable R-Car Gen2 regulator quirk")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 60fc75bdf5b1b8ed3e0a372b7b35f27726ff542b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+index 27fb3a5ec73e..93f628acfd94 100644
+--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+@@ -98,7 +98,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
+ 
+ 		dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
+ 		ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
+-		if (ret != ARRAY_SIZE(da9xxx_msgs))
++		if (ret != len)
+ 			dev_err(&client->dev, "i2c error %d\n", ret);
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/1105-ARM-shmobile-defconfig-Refresh.patch b/patches/1105-ARM-shmobile-defconfig-Refresh.patch
new file mode 100644
index 00000000000000..069b449d0f709d
--- /dev/null
+++ b/patches/1105-ARM-shmobile-defconfig-Refresh.patch
@@ -0,0 +1,46 @@
+From b464f8f7554be9c1d66b1cb9f4df77a4bf01429d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 13:27:45 +0100
+Subject: [PATCH 1105/1795] ARM: shmobile: defconfig: Refresh
+
+- CONFIG_AEABI is enabled since commit 494609701e06a004 ("ARM: always
+    enable AEABI for ARMv6+"),
+  - CONFIG_SERIAL_SH_SCI_CONSOLE is enabled since commit
+    c5bb576d5e21e91a ("tty: serial: sh-sci: Hide serial console config
+    question"),
+  - CONFIG_SERIAL_SH_SCI_DMA is enabled since commit be7e251d20e6c800
+    ("tty: serial: sh-sci: Hide DMA config question").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c7b6b600a23473748d5e82e814c6ebbbcf37b006)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index 79b2b7c12264..e3658ec04e83 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -34,7 +34,6 @@ CONFIG_SMP=y
+ CONFIG_SCHED_MC=y
+ CONFIG_HAVE_ARM_ARCH_TIMER=y
+ CONFIG_NR_CPUS=8
+-CONFIG_AEABI=y
+ CONFIG_HIGHMEM=y
+ CONFIG_CMA=y
+ CONFIG_ZBOOT_ROM_TEXT=0x0
+@@ -105,8 +104,6 @@ CONFIG_SERIAL_8250_CONSOLE=y
+ CONFIG_SERIAL_8250_EM=y
+ CONFIG_SERIAL_SH_SCI=y
+ CONFIG_SERIAL_SH_SCI_NR_UARTS=20
+-CONFIG_SERIAL_SH_SCI_CONSOLE=y
+-CONFIG_SERIAL_SH_SCI_DMA=y
+ CONFIG_I2C_CHARDEV=y
+ CONFIG_I2C_MUX=y
+ CONFIG_I2C_DEMUX_PINCTRL=y
+-- 
+2.19.0
+
diff --git a/patches/1106-ARM-shmobile-defconfig-Disable-CONFIG_EMBEDDED.patch b/patches/1106-ARM-shmobile-defconfig-Disable-CONFIG_EMBEDDED.patch
new file mode 100644
index 00000000000000..8e659064dc3451
--- /dev/null
+++ b/patches/1106-ARM-shmobile-defconfig-Disable-CONFIG_EMBEDDED.patch
@@ -0,0 +1,69 @@
+From 915bd08069dc5ed3edb0a2e969d1b36d92c7bf2f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 2 Mar 2018 13:27:46 +0100
+Subject: [PATCH 1106/1795] ARM: shmobile: defconfig: Disable CONFIG_EMBEDDED
+
+CONFIG_EXPERT exposes too many config options that do not matter for
+development.  E.g. it prohibits using the default values for the various
+SH_SCI options.  However, CONFIG_EMBEDDED selects CONFIG_EXPERT, so it
+cannot be disabled.
+
+Hence disable CONFIG_EMBEDDED, and compensate for the loss of
+CONFIG_DEBUG_KERNEL by enabling the latter.
+
+Actual impact, all harmless:
+  - CONFIG_NAMESPACES=y (plus a few related CONFIG_*_NS options),
+  - CONFIG_SYSCTL_SYSCALL=n,
+  - CONFIG_SERIAL_SH_SCI_NR_UARTS changed from 20 to 18,
+  - Some HID support became enabled,
+  - CONFIG_DEBUG_MEMORY_INIT=y,
+
+Refresh the result.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a20d1390c1daac4b8ae1e544e1e49dfd386125a8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index e3658ec04e83..a701601fbd76 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -5,8 +5,6 @@ CONFIG_IKCONFIG_PROC=y
+ CONFIG_CGROUPS=y
+ CONFIG_BLK_DEV_INITRD=y
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+-CONFIG_SYSCTL_SYSCALL=y
+-CONFIG_EMBEDDED=y
+ CONFIG_PERF_EVENTS=y
+ CONFIG_SLAB=y
+ CONFIG_ARCH_RENESAS=y
+@@ -103,7 +101,6 @@ CONFIG_SERIAL_8250=y
+ CONFIG_SERIAL_8250_CONSOLE=y
+ CONFIG_SERIAL_8250_EM=y
+ CONFIG_SERIAL_SH_SCI=y
+-CONFIG_SERIAL_SH_SCI_NR_UARTS=20
+ CONFIG_I2C_CHARDEV=y
+ CONFIG_I2C_MUX=y
+ CONFIG_I2C_DEMUX_PINCTRL=y
+@@ -164,7 +161,6 @@ CONFIG_FB_SH_MOBILE_MERAM=y
+ # CONFIG_BACKLIGHT_GENERIC is not set
+ CONFIG_BACKLIGHT_PWM=y
+ CONFIG_BACKLIGHT_AS3711=y
+-CONFIG_FRAMEBUFFER_CONSOLE=y
+ CONFIG_SOUND=y
+ CONFIG_SND=y
+ CONFIG_SND_SOC=y
+@@ -225,4 +221,5 @@ CONFIG_NLS_ISO8859_1=y
+ CONFIG_PRINTK_TIME=y
+ # CONFIG_ENABLE_WARN_DEPRECATED is not set
+ # CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
+ # CONFIG_ARM_UNWIND is not set
+-- 
+2.19.0
+
diff --git a/patches/1107-ARM-shmobile-Add-watchdog-support.patch b/patches/1107-ARM-shmobile-Add-watchdog-support.patch
new file mode 100644
index 00000000000000..652a515aedf09f
--- /dev/null
+++ b/patches/1107-ARM-shmobile-Add-watchdog-support.patch
@@ -0,0 +1,132 @@
+From df58867687de3f5468e7d6664bc2860b68342d82 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Wed, 28 Feb 2018 17:40:22 +0000
+Subject: [PATCH 1107/1795] ARM: shmobile: Add watchdog support
+
+On R-Car Gen2 and RZ/G1 platforms, we use the SBAR registers to make non
+boot CPUs run a routine designed to bring up SMP and deal with hot plug.
+The value contained in the SBAR registers is not initialized by a WDT
+triggered reset, which means that after a WDT triggered reset we jump
+to the SMP bring up routine, preventing the system from executing the
+bootrom code.
+
+The purpose of this patch is to jump to the bootrom code in case of a
+WDT triggered reset, and keep the SMP functionality untouched.
+In order to tell if the code had been called due to the WDT overflowing
+we are testing WOVF from register RWTCSRA.
+
+The new function shmobile_boot_vector_gen2 isn't replacing
+shmobile_boot_vector for backward compatibility reasons. The kernel
+will install the best option (either shmobile_boot_vector or
+shmobile_boot_vector_gen2) to ICRAM1 after parsing the device tree,
+according to the amount of memory available.
+
+Since shmobile_boot_vector has become bigger, "reg" property of nodes
+compatible with "renesas,smp-sram" now need to be set to a value
+greater or equal to "<0 0x60>".
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: dropped #ifdef from common.h]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 58adf1ba0d227754d9bc763c667f10efe0053ce5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/common.h  |  4 +++
+ arch/arm/mach-shmobile/headsmp.S | 55 ++++++++++++++++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+
+diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
+index a8fa4f7e1f60..43c1ac696274 100644
+--- a/arch/arm/mach-shmobile/common.h
++++ b/arch/arm/mach-shmobile/common.h
+@@ -7,6 +7,10 @@ extern void shmobile_init_delay(void);
+ extern void shmobile_boot_vector(void);
+ extern unsigned long shmobile_boot_fn;
+ extern unsigned long shmobile_boot_size;
++extern void shmobile_boot_vector_gen2(void);
++extern unsigned long shmobile_boot_fn_gen2;
++extern unsigned long shmobile_boot_cpu_gen2;
++extern unsigned long shmobile_boot_size_gen2;
+ extern void shmobile_smp_boot(void);
+ extern void shmobile_smp_sleep(void);
+ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
+diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
+index 32e0bf6e3ccb..cef8e8c555f8 100644
+--- a/arch/arm/mach-shmobile/headsmp.S
++++ b/arch/arm/mach-shmobile/headsmp.S
+@@ -16,6 +16,11 @@
+ #include <asm/assembler.h>
+ #include <asm/memory.h>
+ 
++#define SCTLR_MMU	0x01
++#define BOOTROM_ADDRESS	0xE6340000
++#define RWTCSRA_ADDRESS 0xE6020004
++#define RWTCSRA_WOVF	0x10
++
+ /*
+  * Reset vector for secondary CPUs.
+  * This will be mapped at address 0 by SBAR register.
+@@ -37,6 +42,56 @@ shmobile_boot_fn:
+ shmobile_boot_size:
+ 	.long	. - shmobile_boot_vector
+ 
++#ifdef CONFIG_ARCH_RCAR_GEN2
++/*
++ * Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs.
++ * This will be mapped at address 0 by SBAR register.
++ */
++ENTRY(shmobile_boot_vector_gen2)
++	mrc	p15, 0, r0, c0, c0, 5		@ r0 = MPIDR
++	ldr	r1, shmobile_boot_cpu_gen2
++	cmp	r0, r1
++	bne	shmobile_smp_continue_gen2
++
++	mrc	p15, 0, r1, c1, c0, 0		@ r1 = SCTLR
++	and	r0, r1, #SCTLR_MMU
++	cmp	r0, #SCTLR_MMU
++	beq	shmobile_smp_continue_gen2
++
++	ldr	r0, rwtcsra
++	mov	r1, #0
++	ldrb	r1, [r0]
++	and	r0, r1, #RWTCSRA_WOVF
++	cmp	r0, #RWTCSRA_WOVF
++	bne	shmobile_smp_continue_gen2
++
++	ldr	r0, bootrom
++	bx	r0
++
++shmobile_smp_continue_gen2:
++	ldr     r1, shmobile_boot_fn_gen2
++	bx	r1
++
++ENDPROC(shmobile_boot_vector_gen2)
++
++	.align	4
++rwtcsra:
++	.word	RWTCSRA_ADDRESS
++bootrom:
++	.word	BOOTROM_ADDRESS
++	.globl	shmobile_boot_cpu_gen2
++shmobile_boot_cpu_gen2:
++	.word	0x00000000
++
++	.align	2
++	.globl	shmobile_boot_fn_gen2
++shmobile_boot_fn_gen2:
++	.space	4
++	.globl	shmobile_boot_size_gen2
++shmobile_boot_size_gen2:
++	.long	. - shmobile_boot_vector_gen2
++#endif /* CONFIG_ARCH_RCAR_GEN2 */
++
+ /*
+  * Per-CPU SMP boot function/argument selection code based on MPIDR
+  */
+-- 
+2.19.0
+
diff --git a/patches/1108-ARM-shmobile-rcar-gen2-Add-watchdog-support.patch b/patches/1108-ARM-shmobile-rcar-gen2-Add-watchdog-support.patch
new file mode 100644
index 00000000000000..c4ad0b2ac72164
--- /dev/null
+++ b/patches/1108-ARM-shmobile-rcar-gen2-Add-watchdog-support.patch
@@ -0,0 +1,75 @@
+From debaca4ae89d77c384a0dd9d87485a8c8bd087ef Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:19 +0000
+Subject: [PATCH 1108/1795] ARM: shmobile: rcar-gen2: Add watchdog support
+
+This patch adds watchdog support by installing shmobile_boot_vector_gen2
+to ICRAM1 when enough memory is available, in which case we also keep a
+copy of MPIDR to complete the reset vector logic.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 01d675f159e0f0792947fb823cf2425da4d747ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/platsmp-apmu.c |  1 +
+ arch/arm/mach-shmobile/pm-rcar-gen2.c | 15 ++++++++++++---
+ 2 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
+index 4422b615a6ee..ba732effc90b 100644
+--- a/arch/arm/mach-shmobile/platsmp-apmu.c
++++ b/arch/arm/mach-shmobile/platsmp-apmu.c
+@@ -191,6 +191,7 @@ static void __init shmobile_smp_apmu_setup_boot(void)
+ {
+ 	/* install boot code shared by all CPUs */
+ 	shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
++	shmobile_boot_fn_gen2 = shmobile_boot_fn;
+ }
+ 
+ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
+index e5f215c8b218..5a798b406af0 100644
+--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
+@@ -17,6 +17,7 @@
+ #include <linux/smp.h>
+ #include <linux/soc/renesas/rcar-sysc.h>
+ #include <asm/io.h>
++#include <asm/cputype.h>
+ #include "common.h"
+ #include "rcar-gen2.h"
+ 
+@@ -37,7 +38,6 @@
+ #define CA7RESCNT_CODE	0x5a5a0000
+ #define CA7RESCNT_CPUS	0xf		/* CPU0-3 */
+ 
+-
+ /* On-chip RAM */
+ #define ICRAM1		0xe63c0000	/* Inter Connect RAM1 (4 KiB) */
+ 
+@@ -119,8 +119,17 @@ void __init rcar_gen2_pm_init(void)
+ 	p = ioremap(res.start, resource_size(&res));
+ 	if (!p)
+ 		return;
+-
+-	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
++	/*
++	 * install the reset vector, use the largest version if we have enough
++	 * memory available
++	 */
++	if (resource_size(&res) >= shmobile_boot_size_gen2) {
++		shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
++		memcpy_toio(p, shmobile_boot_vector_gen2,
++			    shmobile_boot_size_gen2);
++	} else {
++		memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
++	}
+ 	iounmap(p);
+ 
+ 	/* setup reset vectors */
+-- 
+2.19.0
+
diff --git a/patches/1109-ARM-dts-kzm9d-Fix-debounce-interval-property-misspel.patch b/patches/1109-ARM-dts-kzm9d-Fix-debounce-interval-property-misspel.patch
new file mode 100644
index 00000000000000..371b699c5e4cee
--- /dev/null
+++ b/patches/1109-ARM-dts-kzm9d-Fix-debounce-interval-property-misspel.patch
@@ -0,0 +1,57 @@
+From fcf795286d904fe01ae2c5125f84d6ccae5c0560 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 13 Feb 2018 15:15:29 +0100
+Subject: [PATCH 1109/1795] ARM: dts: kzm9d: Fix "debounce-interval" property
+ misspelling
+
+"debounce_interval" was never supported.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b1798f2a97dacade8c6db97074b0f36327c77bcc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/emev2-kzm9d.dts | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
+index 60d0a732833a..c238407133bf 100644
+--- a/arch/arm/boot/dts/emev2-kzm9d.dts
++++ b/arch/arm/boot/dts/emev2-kzm9d.dts
+@@ -38,28 +38,28 @@
+ 		#size-cells = <0>;
+ 
+ 		one {
+-			debounce_interval = <50>;
++			debounce-interval = <50>;
+ 			wakeup-source;
+ 			label = "DSW2-1";
+ 			linux,code = <KEY_1>;
+ 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ 		};
+ 		two {
+-			debounce_interval = <50>;
++			debounce-interval = <50>;
+ 			wakeup-source;
+ 			label = "DSW2-2";
+ 			linux,code = <KEY_2>;
+ 			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ 		};
+ 		three {
+-			debounce_interval = <50>;
++			debounce-interval = <50>;
+ 			wakeup-source;
+ 			label = "DSW2-3";
+ 			linux,code = <KEY_3>;
+ 			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ 		};
+ 		four {
+-			debounce_interval = <50>;
++			debounce-interval = <50>;
+ 			wakeup-source;
+ 			label = "DSW2-4";
+ 			linux,code = <KEY_4>;
+-- 
+2.19.0
+
diff --git a/patches/1110-ARM-dts-lager-Move-cec_clock-to-root-node.patch b/patches/1110-ARM-dts-lager-Move-cec_clock-to-root-node.patch
new file mode 100644
index 00000000000000..7ebfbe18f7ef13
--- /dev/null
+++ b/patches/1110-ARM-dts-lager-Move-cec_clock-to-root-node.patch
@@ -0,0 +1,57 @@
+From ca7953e2c8b8dd3bf13e70a092b8848b1daaa03e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 13 Feb 2018 14:40:45 +0100
+Subject: [PATCH 1110/1795] ARM: dts: lager: Move cec_clock to root node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+cec-clock is a fixed clock generator that is not controlled by i2c-12
+and thus should not be a child of the i2c-12 bus node. Rather, it should
+be a child of the root node of the DT.
+
+Fixes: c5aa87977626e778 ("ARM: dts: lager: Add CEC clock for HDMI transmitter")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fe61513f1611def2535962954be4bb4fc2cb182c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index 20c1b4f224b8..063fdb65dc60 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -247,6 +247,12 @@
+ 		};
+ 	};
+ 
++	cec_clock: cec-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <12000000>;
++	};
++
+ 	hdmi-out {
+ 		compatible = "hdmi-connector";
+ 		type = "a";
+@@ -352,12 +358,6 @@
+ 			};
+ 		};
+ 
+-		cec_clock: cec-clock {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <12000000>;
+-		};
+-
+ 		hdmi@39 {
+ 			compatible = "adi,adv7511w";
+ 			reg = <0x39>;
+-- 
+2.19.0
+
diff --git a/patches/1111-ARM-dts-stout-Initial-r8a7790-Stout-board-support.patch b/patches/1111-ARM-dts-stout-Initial-r8a7790-Stout-board-support.patch
new file mode 100644
index 00000000000000..da2c1c7d96a9d1
--- /dev/null
+++ b/patches/1111-ARM-dts-stout-Initial-r8a7790-Stout-board-support.patch
@@ -0,0 +1,414 @@
+From 3b5689648c170d0d8185bd8b3cfcfec4c42c4a7c Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 15 Feb 2018 19:49:19 +0100
+Subject: [PATCH 1111/1795] ARM: dts: stout: Initial r8a7790 Stout board
+ support
+
+Stout base board support making use of 1 GiB of memory,
+the Renesas H2 r8a7790 SoC with the SCIFA0 serial port
+and CA15 with ARM architected timer.
+
+Furthermore, this device tree contains entries for:
+  - 4x LEDs
+  - SDHI SD/MMC controller
+  - Display unit with HDMI output
+  - SH fast ethernet controller
+  - QSPI controller with S25FL512S attached to it
+  - I2C controller with DA9210 and DA 9063 PMICs
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 92bcfdb334ca7fc4c029927d25a89adcf34d0529)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/Makefile          |   1 +
+ arch/arm/boot/dts/r8a7790-stout.dts | 363 ++++++++++++++++++++++++++++
+ 2 files changed, 364 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a7790-stout.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 58fae9c03b82..e820cd2fe07f 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -733,6 +733,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
+ 	r8a7778-bockw.dtb \
+ 	r8a7779-marzen.dtb \
+ 	r8a7790-lager.dtb \
++	r8a7790-stout.dtb \
+ 	r8a7791-koelsch.dtb \
+ 	r8a7791-porter.dtb \
+ 	r8a7792-blanche.dtb \
+diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
+new file mode 100644
+index 000000000000..a13a92c26645
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a7790-stout.dts
+@@ -0,0 +1,363 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the Stout board
++ *
++ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
++ */
++
++/dts-v1/;
++#include "r8a7790.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Stout";
++	compatible = "renesas,stout", "renesas,r8a7790";
++
++	aliases {
++		serial0 = &scifa0;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0 0x40000000 0 0x40000000>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		led1 {
++			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++		};
++		led2 {
++			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
++		};
++		led3 {
++			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
++		};
++		led5 {
++			gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	fixedregulator3v3: regulator-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_sdhi0: regulator-vcc-sdhi0 {
++		compatible = "regulator-fixed";
++
++		regulator-name = "SDHI0 Vcc";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
++	hdmi-out {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_out: endpoint {
++				remote-endpoint = <&adv7511_out>;
++			};
++		};
++	};
++
++	osc1_clk: osc1-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <148500000>;
++	};
++
++	osc4_clk: osc4-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <12000000>;
++	};
++};
++
++&du {
++	pinctrl-0 = <&du_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
++		 <&osc1_clk>;
++	clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
++
++	ports {
++		port@0 {
++			endpoint {
++				remote-endpoint = <&adv7511_in>;
++			};
++		};
++		port@1 {
++			lvds_connector0: endpoint {
++			};
++		};
++		port@2 {
++			lvds_connector1: endpoint {
++			};
++		};
++	};
++};
++
++&extal_clk {
++	clock-frequency = <20000000>;
++};
++
++&pfc {
++
++	pinctrl-0 = <&scif_clk_pins>;
++	pinctrl-names = "default";
++
++	du_pins: du {
++		groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
++		function = "du";
++	};
++
++	scifa0_pins: scifa0 {
++		groups = "scifa0_data_b";
++		function = "scifa0";
++	};
++
++	scif_clk_pins: scif_clk {
++		groups = "scif_clk";
++		function = "scif_clk";
++	};
++
++	ether_pins: ether {
++		groups = "eth_link", "eth_mdio", "eth_rmii";
++		function = "eth";
++	};
++
++	phy1_pins: phy1 {
++		groups = "intc_irq1";
++		function = "intc";
++	};
++
++	sdhi0_pins: sd0 {
++		groups = "sdhi0_data4", "sdhi0_ctrl";
++		function = "sdhi0";
++		power-source = <3300>;
++	};
++
++	qspi_pins: qspi {
++		groups = "qspi_ctrl", "qspi_data4";
++		function = "qspi";
++	};
++
++	iic2_pins: iic2 {
++		groups = "iic2_b";
++		function = "iic2";
++	};
++
++	iic3_pins: iic3 {
++		groups = "iic3";
++		function = "iic3";
++	};
++
++	usb0_pins: usb0 {
++		groups = "usb0";
++		function = "usb0";
++	};
++};
++
++&ether {
++	pinctrl-0 = <&ether_pins &phy1_pins>;
++	pinctrl-names = "default";
++
++	phy-handle = <&phy1>;
++	renesas,ether-link-active-low;
++	status = "okay";
++
++	phy1: ethernet-phy@1 {
++		reg = <1>;
++		interrupt-parent = <&irqc0>;
++		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
++		micrel,led-mode = <1>;
++	};
++};
++
++&cmt0 {
++	status = "okay";
++};
++
++&qspi {
++	pinctrl-0 = <&qspi_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++
++	flash: flash@0 {
++		compatible = "spansion,s25fl512s", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <30000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++		spi-cpha;
++		spi-cpol;
++		m25p,fast-read;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "loader";
++				reg = <0x00000000 0x00080000>;
++				read-only;
++			};
++			partition@80000 {
++				label = "uboot";
++				reg = <0x00080000 0x00040000>;
++				read-only;
++			};
++			partition@c0000 {
++				label = "uboot-env";
++				reg = <0x000c0000 0x00040000>;
++				read-only;
++			};
++			partition@100000 {
++				label = "flash";
++				reg = <0x00100000 0x03f00000>;
++			};
++		};
++	};
++};
++
++&scifa0 {
++	pinctrl-0 = <&scifa0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&scif_clk {
++	clock-frequency = <14745600>;
++};
++
++&sdhi0 {
++	pinctrl-0 = <&sdhi0_pins>;
++	pinctrl-names = "default";
++
++	vmmc-supply = <&vcc_sdhi0>;
++	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
++	status = "okay";
++};
++
++&cpu0 {
++	cpu0-supply = <&vdd_dvfs>;
++};
++
++&iic2	{
++	status = "okay";
++	pinctrl-0 = <&iic2_pins>;
++	pinctrl-names = "default";
++
++	clock-frequency = <100000>;
++
++	hdmi@39 {
++		compatible = "adi,adv7511w";
++		reg = <0x39>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&osc4_clk>;
++		clock-names = "cec";
++
++		adi,input-depth = <8>;
++		adi,input-colorspace = "rgb";
++		adi,input-clock = "1x";
++		adi,input-style = <1>;
++		adi,input-justification = "evenly";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7511_in: endpoint {
++					remote-endpoint = <&du_out_rgb>;
++				};
++			};
++
++			port@1 {
++				reg = <1>;
++				adv7511_out: endpoint {
++					remote-endpoint = <&hdmi_con_out>;
++				};
++			};
++		};
++	};
++};
++
++&iic3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&iic3_pins>;
++	status = "okay";
++
++	pmic@58 {
++		compatible = "dlg,da9063";
++		reg = <0x58>;
++		interrupt-parent = <&irqc0>;
++		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++
++		rtc {
++			compatible = "dlg,da9063-rtc";
++		};
++
++		wdt {
++			compatible = "dlg,da9063-watchdog";
++		};
++	};
++
++	vdd_dvfs: regulator@68 {
++		compatible = "dlg,da9210";
++		reg = <0x68>;
++		interrupt-parent = <&irqc0>;
++		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1000000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vdd: regulator@70 {
++		compatible = "dlg,da9210";
++		reg = <0x70>;
++		interrupt-parent = <&irqc0>;
++		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
++
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1000000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&pci0 {
++	status = "okay";
++	pinctrl-0 = <&usb0_pins>;
++	pinctrl-names = "default";
++};
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1112-ARM-dts-marzen-Add-SDHI0-VCCQ-Regulator.patch b/patches/1112-ARM-dts-marzen-Add-SDHI0-VCCQ-Regulator.patch
new file mode 100644
index 00000000000000..6e096f8a95674d
--- /dev/null
+++ b/patches/1112-ARM-dts-marzen-Add-SDHI0-VCCQ-Regulator.patch
@@ -0,0 +1,55 @@
+From f49485d6ea1373146f832f0480f73620d5c343d6 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 19 Feb 2018 21:37:58 +0900
+Subject: [PATCH 1112/1795] ARM: dts: marzen: Add SDHI0 VCCQ Regulator
+
+Add support for the on-board voltage regulator hooked up to GPIO3_20
+on r8a7779 Marzen. The board schematics describes the regulator as U4
+TPS2110A. Input wise, U4 has D0 fixed to ground, D1 tied to GPIO3_20
+while IN1 is fixed to 3.3V and IN2 is fixed to 1.8V. OUT goes to the
+pull-ups for the data pins of SDHI0.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 56bac953b15087dbced6951248ca05a6f0888831)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7779-marzen.dts | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
+index 9412a86f9b30..4b9006bac3cb 100644
+--- a/arch/arm/boot/dts/r8a7779-marzen.dts
++++ b/arch/arm/boot/dts/r8a7779-marzen.dts
+@@ -42,6 +42,19 @@
+ 		regulator-always-on;
+ 	};
+ 
++	vccq_sdhi0: regulator-vccq-sdhi0 {
++		compatible = "regulator-gpio";
++
++		regulator-name = "SDHI0 VccQ";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++
++		gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
++		gpios-states = <1>;
++		states = <3300000 1
++			  1800000 0>;
++	};
++
+ 	ethernet@18000000 {
+ 		compatible = "smsc,lan9220", "smsc,lan9115";
+ 		reg = <0x18000000 0x100>;
+@@ -243,6 +256,7 @@
+ 	pinctrl-names = "default";
+ 
+ 	vmmc-supply = <&fixedregulator3v3>;
++	vqmmc-supply = <&vccq_sdhi0>;
+ 	bus-width = <4>;
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/1113-ARM-dts-silk-Add-r1ex24002-EEPROM-to-DT.patch b/patches/1113-ARM-dts-silk-Add-r1ex24002-EEPROM-to-DT.patch
new file mode 100644
index 00000000000000..b52b8ebb5a7bab
--- /dev/null
+++ b/patches/1113-ARM-dts-silk-Add-r1ex24002-EEPROM-to-DT.patch
@@ -0,0 +1,38 @@
+From 469d1c51fd1c17ec6c9a67484ea4594dd98a291f Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 19 Feb 2018 20:49:42 +0900
+Subject: [PATCH 1113/1795] ARM: dts: silk: Add r1ex24002 EEPROM to DT
+
+Extend the Silk board support to include U14 which is an I2C based EEPROM
+hooked up to the I2C1 bus.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7f8f74cd8d28f0b14b004c6c1640df439e5c2108)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-silk.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index f1afe2dda13a..befd0fb880cc 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -226,6 +226,12 @@
+ 				};
+ 			};
+ 		};
++
++		eeprom@50 {
++			compatible = "renesas,r1ex24002", "atmel,24c02";
++			reg = <0x50>;
++			pagesize = <16>;
++		};
+ 	};
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1114-ARM-dts-silk-Add-GPIO-keys-to-DT.patch b/patches/1114-ARM-dts-silk-Add-GPIO-keys-to-DT.patch
new file mode 100644
index 00000000000000..b73244f9b16041
--- /dev/null
+++ b/patches/1114-ARM-dts-silk-Add-GPIO-keys-to-DT.patch
@@ -0,0 +1,94 @@
+From 278b0c3f8c9afb24bb6f2c7086f04acd0a23928c Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Mon, 19 Feb 2018 20:49:51 +0900
+Subject: [PATCH 1114/1795] ARM: dts: silk: Add GPIO keys to DT
+
+Extend the Silk board support to include SW3, SW4, SW6 and SW12. They
+are all connected via GPIO lines and handled by the gpio-keys driver.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a24a5821a684a62ae2c53a214eaf2ad4f4f0dbcf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-silk.dts | 55 ++++++++++++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index befd0fb880cc..351cb3b3d966 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -24,6 +24,7 @@
+ /dts-v1/;
+ #include "r8a7794.dtsi"
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
+ 
+ / {
+ 	model = "SILK";
+@@ -45,6 +46,60 @@
+ 		reg = <0 0x40000000 0 0x40000000>;
+ 	};
+ 
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key-3 {
++			gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_3>;
++			label = "SW3";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-4 {
++			gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_4>;
++			label = "SW4";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-6 {
++			gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_6>;
++			label = "SW6";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-a {
++			gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_A>;
++			label = "SW12-1";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-b {
++			gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_B>;
++			label = "SW12-2";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-c {
++			gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_C>;
++			label = "SW12-3";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++		key-d {
++			gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_D>;
++			label = "SW12-4";
++			wakeup-source;
++			debounce-interval = <20>;
++		};
++	};
++
+ 	d3_3v: regulator-d3-3v {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "D3.3V";
+-- 
+2.19.0
+
diff --git a/patches/1115-ARM-dts-r8a7790-Convert-to-new-LVDS-DT-bindings.patch b/patches/1115-ARM-dts-r8a7790-Convert-to-new-LVDS-DT-bindings.patch
new file mode 100644
index 00000000000000..06fc5d99c680a3
--- /dev/null
+++ b/patches/1115-ARM-dts-r8a7790-Convert-to-new-LVDS-DT-bindings.patch
@@ -0,0 +1,172 @@
+From 8c47c858527d824cc155eae89613deb054c54d73 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 20 Apr 2018 14:57:52 +0300
+Subject: [PATCH 1115/1795] ARM: dts: r8a7790: Convert to new LVDS DT bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The internal LVDS encoder now has DT bindings separate from the DU. Port
+the device tree over to the new model.
+
+Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
+Fixes: 4bdb7aa7dcd0 ("ARM: dts: r8a7790: add soc node")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 15a1ff30d8f9bd83273d8712973b88663ad16265)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 22 +++++++---
+ arch/arm/boot/dts/r8a7790.dtsi      | 65 +++++++++++++++++++++++++----
+ 2 files changed, 74 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index 063fdb65dc60..f07f9018c3e7 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -379,7 +379,7 @@
+ 				port@0 {
+ 					reg = <0>;
+ 					adv7511_in: endpoint {
+-						remote-endpoint = <&du_out_lvds0>;
++						remote-endpoint = <&lvds0_out>;
+ 					};
+ 				};
+ 
+@@ -467,10 +467,8 @@
+ 	status = "okay";
+ 
+ 	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
+-		 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+ 		 <&x13_clk>, <&x2_clk>;
+-	clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+-		      "dclkin.0", "dclkin.1";
++	clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
+ 
+ 	ports {
+ 		port@0 {
+@@ -478,12 +476,26 @@
+ 				remote-endpoint = <&adv7123_in>;
+ 			};
+ 		};
++	};
++};
++
++&lvds0 {
++	status = "okay";
++
++	ports {
+ 		port@1 {
+ 			endpoint {
+ 				remote-endpoint = <&adv7511_in>;
+ 			};
+ 		};
+-		port@2 {
++	};
++};
++
++&lvds1 {
++	status = "okay";
++
++	ports {
++		port@1 {
+ 			lvds_connector: endpoint {
+ 			};
+ 		};
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index e4367cecad18..05a0fc23ac88 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1627,18 +1627,13 @@
+ 
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7790";
+-			reg = <0 0xfeb00000 0 0x70000>,
+-			      <0 0xfeb90000 0 0x1c>,
+-			      <0 0xfeb94000 0 0x1c>;
+-			reg-names = "du", "lvds.0", "lvds.1";
++			reg = <0 0xfeb00000 0 0x70000>;
+ 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+-				 <&cpg CPG_MOD 725>;
+-			clock-names = "du.0", "du.1", "du.2", "lvds.0",
+-				      "lvds.1";
++				 <&cpg CPG_MOD 722>;
++			clock-names = "du.0", "du.1", "du.2";
+ 			status = "disabled";
+ 
+ 			ports {
+@@ -1653,11 +1648,65 @@
+ 				port@1 {
+ 					reg = <1>;
+ 					du_out_lvds0: endpoint {
++						remote-endpoint = <&lvds0_in>;
+ 					};
+ 				};
+ 				port@2 {
+ 					reg = <2>;
+ 					du_out_lvds1: endpoint {
++						remote-endpoint = <&lvds1_in>;
++					};
++				};
++			};
++		};
++
++		lvds0: lvds@feb90000 {
++			compatible = "renesas,r8a7790-lvds";
++			reg = <0 0xfeb90000 0 0x1c>;
++			clocks = <&cpg CPG_MOD 726>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 726>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					lvds0_in: endpoint {
++						remote-endpoint = <&du_out_lvds0>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					lvds0_out: endpoint {
++					};
++				};
++			};
++		};
++
++		lvds1: lvds@feb94000 {
++			compatible = "renesas,r8a7790-lvds";
++			reg = <0 0xfeb94000 0 0x1c>;
++			clocks = <&cpg CPG_MOD 725>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 725>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					lvds1_in: endpoint {
++						remote-endpoint = <&du_out_lvds1>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					lvds1_out: endpoint {
+ 					};
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1116-ARM-dts-r8a7791-Convert-to-new-LVDS-DT-bindings.patch b/patches/1116-ARM-dts-r8a7791-Convert-to-new-LVDS-DT-bindings.patch
new file mode 100644
index 00000000000000..4cf35dbf01d47d
--- /dev/null
+++ b/patches/1116-ARM-dts-r8a7791-Convert-to-new-LVDS-DT-bindings.patch
@@ -0,0 +1,151 @@
+From f3ec6db6be9d4054f41e4fd05959772f4b8601dc Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 20 Apr 2018 14:57:53 +0300
+Subject: [PATCH 1116/1795] ARM: dts: r8a7791: Convert to new LVDS DT bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The internal LVDS encoder now has DT bindings separate from the DU. Port
+the device tree over to the new model.
+
+Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
+Fixes: bb21803ea440 ("ARM: dts: r8a7791: add soc node")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e5c3f4707f3956a2f34b8c16daad07a16873c498)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 12 ++++++---
+ arch/arm/boot/dts/r8a7791-porter.dts  | 16 +++++++++---
+ arch/arm/boot/dts/r8a7791.dtsi        | 36 ++++++++++++++++++++++-----
+ 3 files changed, 52 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index f40321a1c917..9d7213a0b8b8 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -468,10 +468,9 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ 		 <&x13_clk>, <&x2_clk>;
+-	clock-names = "du.0", "du.1", "lvds.0",
+-		      "dclkin.0", "dclkin.1";
++	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 
+ 	ports {
+ 		port@0 {
+@@ -479,6 +478,13 @@
+ 				remote-endpoint = <&adv7511_in>;
+ 			};
+ 		};
++	};
++};
++
++&lvds0 {
++	status = "okay";
++
++	ports {
+ 		port@1 {
+ 			lvds_connector: endpoint {
+ 			};
+diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
+index c14e6fe9e4f6..ae9ed9ff53ef 100644
+--- a/arch/arm/boot/dts/r8a7791-porter.dts
++++ b/arch/arm/boot/dts/r8a7791-porter.dts
+@@ -441,10 +441,9 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ 		 <&x3_clk>, <&x16_clk>;
+-	clock-names = "du.0", "du.1", "lvds.0",
+-		      "dclkin.0", "dclkin.1";
++	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 
+ 	ports {
+ 		port@0 {
+@@ -455,6 +454,17 @@
+ 	};
+ };
+ 
++&lvds0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			lvds_connector: endpoint {
++			};
++		};
++	};
++};
++
+ &rcar_sound {
+ 	pinctrl-0 = <&ssi_pins &audio_clk_pins>;
+ 	pinctrl-names = "default";
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index f11dab71b03a..506b20885413 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -1633,15 +1633,12 @@
+ 
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7791";
+-			reg = <0 0xfeb00000 0 0x40000>,
+-			      <0 0xfeb90000 0 0x1c>;
+-			reg-names = "du", "lvds.0";
++			reg = <0 0xfeb00000 0 0x40000>;
+ 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 724>,
+-				 <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 726>;
+-			clock-names = "du.0", "du.1", "lvds.0";
++				 <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
+ 			status = "disabled";
+ 
+ 			ports {
+@@ -1656,6 +1653,33 @@
+ 				port@1 {
+ 					reg = <1>;
+ 					du_out_lvds0: endpoint {
++						remote-endpoint = <&lvds0_in>;
++					};
++				};
++			};
++		};
++
++		lvds0: lvds@feb90000 {
++			compatible = "renesas,r8a7791-lvds";
++			reg = <0 0xfeb90000 0 0x1c>;
++			clocks = <&cpg CPG_MOD 726>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 726>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					lvds0_in: endpoint {
++						remote-endpoint = <&du_out_lvds0>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					lvds0_out: endpoint {
+ 					};
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1117-ARM-dts-r8a7793-Convert-to-new-LVDS-DT-bindings.patch b/patches/1117-ARM-dts-r8a7793-Convert-to-new-LVDS-DT-bindings.patch
new file mode 100644
index 00000000000000..3504da3baf6c1d
--- /dev/null
+++ b/patches/1117-ARM-dts-r8a7793-Convert-to-new-LVDS-DT-bindings.patch
@@ -0,0 +1,114 @@
+From 1d62c82cc30700c2f4be64ff02c09149b9bed36c Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 20 Apr 2018 14:57:54 +0300
+Subject: [PATCH 1117/1795] ARM: dts: r8a7793: Convert to new LVDS DT bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The internal LVDS encoder now has DT bindings separate from the DU. Port
+the device tree over to the new model.
+
+Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
+Fixes: bff8f8c2feb7 ("ARM: dts: r8a7793: add soc node")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit edb0c3affe5214a21d71ffb82ca92ed068e828df)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts | 10 +++++---
+ arch/arm/boot/dts/r8a7793.dtsi     | 37 +++++++++++++++++++++++++-----
+ 2 files changed, 38 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 9ed6961f2d9a..96e117d8b2cc 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -447,10 +447,9 @@
+ 	pinctrl-names = "default";
+ 	status = "okay";
+ 
+-	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
++	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ 		 <&x13_clk>, <&x2_clk>;
+-	clock-names = "du.0", "du.1", "lvds.0",
+-		      "dclkin.0", "dclkin.1";
++	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+ 
+ 	ports {
+ 		port@0 {
+@@ -458,6 +457,11 @@
+ 				remote-endpoint = <&adv7511_in>;
+ 			};
+ 		};
++	};
++};
++
++&lvds0 {
++	ports {
+ 		port@1 {
+ 			lvds_connector: endpoint {
+ 			};
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index f9c5a557107d..4f526030dc7c 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -1292,15 +1292,12 @@
+ 
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7793";
+-			reg = <0 0xfeb00000 0 0x40000>,
+-			      <0 0xfeb90000 0 0x1c>;
+-			reg-names = "du", "lvds.0";
++			reg = <0 0xfeb00000 0 0x40000>;
+ 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 724>,
+-				 <&cpg CPG_MOD 723>,
+-				 <&cpg CPG_MOD 726>;
+-			clock-names = "du.0", "du.1", "lvds.0";
++				 <&cpg CPG_MOD 723>;
++			clock-names = "du.0", "du.1";
+ 			status = "disabled";
+ 
+ 			ports {
+@@ -1315,6 +1312,34 @@
+ 				port@1 {
+ 					reg = <1>;
+ 					du_out_lvds0: endpoint {
++						remote-endpoint = <&lvds0_in>;
++					};
++				};
++			};
++		};
++
++		lvds0: lvds@feb90000 {
++			compatible = "renesas,r8a7793-lvds";
++			reg = <0 0xfeb90000 0 0x1c>;
++			clocks = <&cpg CPG_MOD 726>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 726>;
++
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					lvds0_in: endpoint {
++						remote-endpoint = <&du_out_lvds0>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					lvds0_out: endpoint {
+ 					};
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1118-media-v4l2-common-create-v4l2_g-s_parm_cap-helpers.patch b/patches/1118-media-v4l2-common-create-v4l2_g-s_parm_cap-helpers.patch
new file mode 100644
index 00000000000000..7f394da3b4e2da
--- /dev/null
+++ b/patches/1118-media-v4l2-common-create-v4l2_g-s_parm_cap-helpers.patch
@@ -0,0 +1,114 @@
+From ae170d7d6beebd28e80f5d4b7941e922c22a6fd1 Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hans.verkuil@cisco.com>
+Date: Mon, 22 Jan 2018 03:58:36 -0500
+Subject: [PATCH 1118/1795] media: v4l2-common: create v4l2_g/s_parm_cap
+ helpers
+
+Create helpers to handle VIDIOC_G/S_PARM by querying the
+g/s_frame_interval v4l2_subdev ops.
+
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 672de9a79cd34c864f5eca7de5264b2645212605)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/v4l2-core/v4l2-common.c | 48 +++++++++++++++++++++++++++
+ include/media/v4l2-common.h           | 26 +++++++++++++++
+ 2 files changed, 74 insertions(+)
+
+diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
+index a5ea1f517291..b9597202b872 100644
+--- a/drivers/media/v4l2-core/v4l2-common.c
++++ b/drivers/media/v4l2-core/v4l2-common.c
+@@ -405,3 +405,51 @@ void v4l2_get_timestamp(struct timeval *tv)
+ 	tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
+ }
+ EXPORT_SYMBOL_GPL(v4l2_get_timestamp);
++
++int v4l2_g_parm_cap(struct video_device *vdev,
++		    struct v4l2_subdev *sd, struct v4l2_streamparm *a)
++{
++	struct v4l2_subdev_frame_interval ival = { 0 };
++	int ret;
++
++	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++	    a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		return -EINVAL;
++
++	if (vdev->device_caps & V4L2_CAP_READWRITE)
++		a->parm.capture.readbuffers = 2;
++	if (v4l2_subdev_has_op(sd, video, g_frame_interval))
++		a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++	ret = v4l2_subdev_call(sd, video, g_frame_interval, &ival);
++	if (!ret)
++		a->parm.capture.timeperframe = ival.interval;
++	return ret;
++}
++EXPORT_SYMBOL_GPL(v4l2_g_parm_cap);
++
++int v4l2_s_parm_cap(struct video_device *vdev,
++		    struct v4l2_subdev *sd, struct v4l2_streamparm *a)
++{
++	struct v4l2_subdev_frame_interval ival = {
++		.interval = a->parm.capture.timeperframe
++	};
++	int ret;
++
++	if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++	    a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		return -EINVAL;
++
++	memset(&a->parm, 0, sizeof(a->parm));
++	if (vdev->device_caps & V4L2_CAP_READWRITE)
++		a->parm.capture.readbuffers = 2;
++	else
++		a->parm.capture.readbuffers = 0;
++
++	if (v4l2_subdev_has_op(sd, video, g_frame_interval))
++		a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++	ret = v4l2_subdev_call(sd, video, s_frame_interval, &ival);
++	if (!ret)
++		a->parm.capture.timeperframe = ival.interval;
++	return ret;
++}
++EXPORT_SYMBOL_GPL(v4l2_s_parm_cap);
+diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
+index aac8b7b6e691..f6c4f7fdb89a 100644
+--- a/include/media/v4l2-common.h
++++ b/include/media/v4l2-common.h
+@@ -264,4 +264,30 @@ const struct v4l2_frmsize_discrete *v4l2_find_nearest_format(
+ 
+ void v4l2_get_timestamp(struct timeval *tv);
+ 
++/**
++ * v4l2_g_parm_cap - helper routine for vidioc_g_parm to fill this in by
++ *      calling the g_frame_interval op of the given subdev. It only works
++ *      for V4L2_BUF_TYPE_VIDEO_CAPTURE(_MPLANE), hence the _cap in the
++ *      function name.
++ *
++ * @vdev: the struct video_device pointer. Used to determine the device caps.
++ * @sd: the sub-device pointer.
++ * @a: the VIDIOC_G_PARM argument.
++ */
++int v4l2_g_parm_cap(struct video_device *vdev,
++		    struct v4l2_subdev *sd, struct v4l2_streamparm *a);
++
++/**
++ * v4l2_s_parm_cap - helper routine for vidioc_s_parm to fill this in by
++ *      calling the s_frame_interval op of the given subdev. It only works
++ *      for V4L2_BUF_TYPE_VIDEO_CAPTURE(_MPLANE), hence the _cap in the
++ *      function name.
++ *
++ * @vdev: the struct video_device pointer. Used to determine the device caps.
++ * @sd: the sub-device pointer.
++ * @a: the VIDIOC_S_PARM argument.
++ */
++int v4l2_s_parm_cap(struct video_device *vdev,
++		    struct v4l2_subdev *sd, struct v4l2_streamparm *a);
++
+ #endif /* V4L2_COMMON_H_ */
+-- 
+2.19.0
+
diff --git a/patches/1119-media-dt-bindings-media-Add-Renesas-CEU-bindings.patch b/patches/1119-media-dt-bindings-media-Add-Renesas-CEU-bindings.patch
new file mode 100644
index 00000000000000..a10373c21ddffe
--- /dev/null
+++ b/patches/1119-media-dt-bindings-media-Add-Renesas-CEU-bindings.patch
@@ -0,0 +1,110 @@
+From 1dba93e222b013f63e96e7bd18e90e599137a728 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Wed, 21 Feb 2018 12:47:55 -0500
+Subject: [PATCH 1119/1795] media: dt-bindings: media: Add Renesas CEU bindings
+
+Add bindings documentation for Renesas Capture Engine Unit (CEU).
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a444e5184f329738691b06ed31addaa0edb6aa01)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/media/renesas,ceu.txt | 81 +++++++++++++++++++
+ 1 file changed, 81 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/renesas,ceu.txt
+
+diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt
+new file mode 100644
+index 000000000000..3fc66dfb192c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/renesas,ceu.txt
+@@ -0,0 +1,81 @@
++Renesas Capture Engine Unit (CEU)
++----------------------------------------------
++
++The Capture Engine Unit is the image capture interface found in the Renesas
++SH Mobile and RZ SoCs.
++
++The interface supports a single parallel input with data bus width of 8 or 16
++bits.
++
++Required properties:
++- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
++  and RZ/A1M SoCs.
++- reg: Registers address base and size.
++- interrupts: The interrupt specifier.
++
++The CEU supports a single parallel input and should contain a single 'port'
++subnode with a single 'endpoint'. Connection to input devices are modeled
++according to the video interfaces OF bindings specified in:
++Documentation/devicetree/bindings/media/video-interfaces.txt
++
++Optional endpoint properties applicable to parallel input bus described in
++the above mentioned "video-interfaces.txt" file are supported.
++
++- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
++  If property is not present, default is active high.
++- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
++  If property is not present, default is active high.
++
++Example:
++
++The example describes the connection between the Capture Engine Unit and an
++OV7670 image sensor connected to i2c1 interface.
++
++ceu: ceu@e8210000 {
++	reg = <0xe8210000 0x209c>;
++	compatible = "renesas,r7s72100-ceu";
++	interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&vio_pins>;
++
++	status = "okay";
++
++	port {
++		ceu_in: endpoint {
++			remote-endpoint = <&ov7670_out>;
++
++			hsync-active = <1>;
++			vsync-active = <0>;
++		};
++	};
++};
++
++i2c1: i2c@fcfee400 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins>;
++
++	status = "okay";
++
++	clock-frequency = <100000>;
++
++	ov7670: camera@21 {
++		compatible = "ovti,ov7670";
++		reg = <0x21>;
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&vio_pins>;
++
++		reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>;
++		powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>;
++
++		port {
++			ov7670_out: endpoint {
++				remote-endpoint = <&ceu_in>;
++
++				hsync-active = <1>;
++				vsync-active = <0>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1120-media-include-media-Add-Renesas-CEU-driver-interface.patch b/patches/1120-media-include-media-Add-Renesas-CEU-driver-interface.patch
new file mode 100644
index 00000000000000..a0d1770477d4da
--- /dev/null
+++ b/patches/1120-media-include-media-Add-Renesas-CEU-driver-interface.patch
@@ -0,0 +1,58 @@
+From 14b84eff9f9104f045d51a53564eab95f2ba9aa7 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Wed, 21 Feb 2018 12:47:56 -0500
+Subject: [PATCH 1120/1795] media: include: media: Add Renesas CEU driver
+ interface
+
+Add renesas-ceu header file.
+
+Do not remove the existing sh_mobile_ceu.h one as long as the original
+driver does not go away.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 20b5605240a8a650185c623065eadc1d04017a86)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/media/drv-intf/renesas-ceu.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+ create mode 100644 include/media/drv-intf/renesas-ceu.h
+
+diff --git a/include/media/drv-intf/renesas-ceu.h b/include/media/drv-intf/renesas-ceu.h
+new file mode 100644
+index 000000000000..52841d1b4763
+--- /dev/null
++++ b/include/media/drv-intf/renesas-ceu.h
+@@ -0,0 +1,26 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * renesas-ceu.h - Renesas CEU driver interface
++ *
++ * Copyright 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ */
++
++#ifndef __MEDIA_DRV_INTF_RENESAS_CEU_H__
++#define __MEDIA_DRV_INTF_RENESAS_CEU_H__
++
++#define CEU_MAX_SUBDEVS		2
++
++struct ceu_async_subdev {
++	unsigned long flags;
++	unsigned char bus_width;
++	unsigned char bus_shift;
++	unsigned int i2c_adapter_id;
++	unsigned int i2c_address;
++};
++
++struct ceu_platform_data {
++	unsigned int num_subdevs;
++	struct ceu_async_subdev subdevs[CEU_MAX_SUBDEVS];
++};
++
++#endif /* ___MEDIA_DRV_INTF_RENESAS_CEU_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1121-media-platform-Add-Renesas-CEU-driver.patch b/patches/1121-media-platform-Add-Renesas-CEU-driver.patch
new file mode 100644
index 00000000000000..25585aa39a801e
--- /dev/null
+++ b/patches/1121-media-platform-Add-Renesas-CEU-driver.patch
@@ -0,0 +1,1753 @@
+From 6b424230ba0e473fee5b3db6d35e98343885efca Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 22 Feb 2018 05:37:19 -0500
+Subject: [PATCH 1121/1795] media: platform: Add Renesas CEU driver
+
+Add driver for Renesas Capture Engine Unit (CEU).
+
+The CEU interface supports capturing 'data' (YUV422) and 'images'
+(NV[12|21|16|61]).
+
+This driver aims to replace the soc_camera-based sh_mobile_ceu one.
+
+Tested with ov7670 camera sensor, providing YUYV_2X8 data on Renesas RZ
+platform GR-Peach.
+
+Tested with ov7725 camera sensor on SH4 platform Migo-R.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+[hans.verkuil@cisco.com: added two 'fall-through' comments]
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 32e5a70dc8f4e9813c61e5465d72d2e9830ba0ff)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/media/platform/Makefile
+---
+ drivers/media/platform/Kconfig       |    9 +
+ drivers/media/platform/Makefile      |    1 +
+ drivers/media/platform/renesas-ceu.c | 1677 ++++++++++++++++++++++++++
+ 3 files changed, 1687 insertions(+)
+ create mode 100644 drivers/media/platform/renesas-ceu.c
+
+diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
+index 3c4f7fa7b9d8..401caea9fa2b 100644
+--- a/drivers/media/platform/Kconfig
++++ b/drivers/media/platform/Kconfig
+@@ -144,6 +144,15 @@ config VIDEO_STM32_DCMI
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called stm32-dcmi.
+ 
++config VIDEO_RENESAS_CEU
++	tristate "Renesas Capture Engine Unit (CEU) driver"
++	depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
++	depends on ARCH_SHMOBILE || ARCH_R7S72100 || COMPILE_TEST
++	select VIDEOBUF2_DMA_CONTIG
++	select V4L2_FWNODE
++	---help---
++	  This is a v4l2 driver for the Renesas CEU Interface
++
+ source "drivers/media/platform/soc_camera/Kconfig"
+ source "drivers/media/platform/exynos4-is/Kconfig"
+ source "drivers/media/platform/am437x/Kconfig"
+diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
+index 327f80a6f82c..76149a11fb76 100644
+--- a/drivers/media/platform/Makefile
++++ b/drivers/media/platform/Makefile
+@@ -58,6 +58,7 @@ obj-$(CONFIG_VIDEO_SH_VOU)		+= sh_vou.o
+ obj-$(CONFIG_SOC_CAMERA)		+= soc_camera/
+ 
+ obj-$(CONFIG_VIDEO_RCAR_DRIF)		+= rcar_drif.o
++obj-$(CONFIG_VIDEO_RENESAS_CEU)		+= renesas-ceu.o
+ obj-$(CONFIG_VIDEO_RENESAS_FCP) 	+= rcar-fcp.o
+ obj-$(CONFIG_VIDEO_RENESAS_FDP1)	+= rcar_fdp1.o
+ obj-$(CONFIG_VIDEO_RENESAS_JPU) 	+= rcar_jpu.o
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+new file mode 100644
+index 000000000000..15148479a061
+--- /dev/null
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -0,0 +1,1677 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface
++ * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ *
++ * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
++ * Copyright (C) 2008 Magnus Damm
++ *
++ * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
++ * Copyright (C) 2006, Sascha Hauer, Pengutronix
++ * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
++ */
++
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_graph.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <linux/time.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-async.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-mediabus.h>
++#include <media/videobuf2-dma-contig.h>
++
++#include <media/drv-intf/renesas-ceu.h>
++
++#define DRIVER_NAME	"renesas-ceu"
++
++/* CEU registers offsets and masks. */
++#define CEU_CAPSR	0x00 /* Capture start register			*/
++#define CEU_CAPCR	0x04 /* Capture control register		*/
++#define CEU_CAMCR	0x08 /* Capture interface control register	*/
++#define CEU_CAMOR	0x10 /* Capture interface offset register	*/
++#define CEU_CAPWR	0x14 /* Capture interface width register	*/
++#define CEU_CAIFR	0x18 /* Capture interface input format register */
++#define CEU_CRCNTR	0x28 /* CEU register control register		*/
++#define CEU_CRCMPR	0x2c /* CEU register forcible control register	*/
++#define CEU_CFLCR	0x30 /* Capture filter control register		*/
++#define CEU_CFSZR	0x34 /* Capture filter size clip register	*/
++#define CEU_CDWDR	0x38 /* Capture destination width register	*/
++#define CEU_CDAYR	0x3c /* Capture data address Y register		*/
++#define CEU_CDACR	0x40 /* Capture data address C register		*/
++#define CEU_CFWCR	0x5c /* Firewall operation control register	*/
++#define CEU_CDOCR	0x64 /* Capture data output control register	*/
++#define CEU_CEIER	0x70 /* Capture event interrupt enable register	*/
++#define CEU_CETCR	0x74 /* Capture event flag clear register	*/
++#define CEU_CSTSR	0x7c /* Capture status register			*/
++#define CEU_CSRTR	0x80 /* Capture software reset register		*/
++
++/* Data synchronous fetch mode. */
++#define CEU_CAMCR_JPEG			BIT(4)
++
++/* Input components ordering: CEU_CAMCR.DTARY field. */
++#define CEU_CAMCR_DTARY_8_UYVY		(0x00 << 8)
++#define CEU_CAMCR_DTARY_8_VYUY		(0x01 << 8)
++#define CEU_CAMCR_DTARY_8_YUYV		(0x02 << 8)
++#define CEU_CAMCR_DTARY_8_YVYU		(0x03 << 8)
++/* TODO: input components ordering for 16 bits input. */
++
++/* Bus transfer MTU. */
++#define CEU_CAPCR_BUS_WIDTH256		(0x3 << 20)
++
++/* Bus width configuration. */
++#define CEU_CAMCR_DTIF_16BITS		BIT(12)
++
++/* No downsampling to planar YUV420 in image fetch mode. */
++#define CEU_CDOCR_NO_DOWSAMPLE		BIT(4)
++
++/* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */
++#define CEU_CDOCR_SWAP_ENDIANNESS	(7)
++
++/* Capture reset and enable bits. */
++#define CEU_CAPSR_CPKIL			BIT(16)
++#define CEU_CAPSR_CE			BIT(0)
++
++/* CEU operating flag bit. */
++#define CEU_CAPCR_CTNCP			BIT(16)
++#define CEU_CSTRST_CPTON		BIT(1)
++
++/* Platform specific IRQ source flags. */
++#define CEU_CETCR_ALL_IRQS_RZ		0x397f313
++#define CEU_CETCR_ALL_IRQS_SH4		0x3d7f313
++
++/* Prohibited register access interrupt bit. */
++#define CEU_CETCR_IGRW			BIT(4)
++/* One-frame capture end interrupt. */
++#define CEU_CEIER_CPE			BIT(0)
++/* VBP error. */
++#define CEU_CEIER_VBP			BIT(20)
++#define CEU_CEIER_MASK			(CEU_CEIER_CPE | CEU_CEIER_VBP)
++
++#define CEU_MAX_WIDTH	2560
++#define CEU_MAX_HEIGHT	1920
++#define CEU_MAX_BPL	8188
++#define CEU_W_MAX(w)	((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH)
++#define CEU_H_MAX(h)	((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT)
++
++/*
++ * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce
++ *
++ * @mbus_code: bus format code
++ * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr)
++ * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components
++ *		    (Y, Cr, Cb)
++ * @swapped: does Cr appear before Cb?
++ * @bps: number of bits sent over bus for each sample
++ * @bpp: number of bits per pixels unit
++ */
++struct ceu_mbus_fmt {
++	u32	mbus_code;
++	u32	fmt_order;
++	u32	fmt_order_swap;
++	bool	swapped;
++	u8	bps;
++	u8	bpp;
++};
++
++/*
++ * ceu_buffer - Link vb2 buffer to the list of available buffers.
++ */
++struct ceu_buffer {
++	struct vb2_v4l2_buffer vb;
++	struct list_head queue;
++};
++
++static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf)
++{
++	return container_of(vbuf, struct ceu_buffer, vb);
++}
++
++/*
++ * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice.
++ */
++struct ceu_subdev {
++	struct v4l2_subdev *v4l2_sd;
++	struct v4l2_async_subdev asd;
++
++	/* per-subdevice mbus configuration options */
++	unsigned int mbus_flags;
++	struct ceu_mbus_fmt mbus_fmt;
++};
++
++static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd)
++{
++	return container_of(asd, struct ceu_subdev, asd);
++}
++
++/*
++ * ceu_device - CEU device instance
++ */
++struct ceu_device {
++	struct device		*dev;
++	struct video_device	vdev;
++	struct v4l2_device	v4l2_dev;
++
++	/* subdevices descriptors */
++	struct ceu_subdev	*subdevs;
++	/* the subdevice currently in use */
++	struct ceu_subdev	*sd;
++	unsigned int		sd_index;
++	unsigned int		num_sd;
++
++	/* platform specific mask with all IRQ sources flagged */
++	u32			irq_mask;
++
++	/* currently configured field and pixel format */
++	enum v4l2_field	field;
++	struct v4l2_pix_format_mplane v4l2_pix;
++
++	/* async subdev notification helpers */
++	struct v4l2_async_notifier notifier;
++	/* pointers to "struct ceu_subdevice -> asd" */
++	struct v4l2_async_subdev **asds;
++
++	/* vb2 queue, capture buffer list and active buffer pointer */
++	struct vb2_queue	vb2_vq;
++	struct list_head	capture;
++	struct vb2_v4l2_buffer	*active;
++	unsigned int		sequence;
++
++	/* mlock - lock access to interface reset and vb2 queue */
++	struct mutex	mlock;
++
++	/* lock - lock access to capture buffer queue and active buffer */
++	spinlock_t	lock;
++
++	/* base - CEU memory base address */
++	void __iomem	*base;
++};
++
++static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev)
++{
++	return container_of(v4l2_dev, struct ceu_device, v4l2_dev);
++}
++
++/* --- CEU memory output formats --- */
++
++/*
++ * ceu_fmt - describe a memory output format supported by CEU interface.
++ *
++ * @fourcc: memory layout fourcc format code
++ * @bpp: number of bits for each pixel stored in memory
++ */
++struct ceu_fmt {
++	u32	fourcc;
++	u32	bpp;
++};
++
++/*
++ * ceu_format_list - List of supported memory output formats
++ *
++ * If sensor provides any YUYV bus format, all the following planar memory
++ * formats are available thanks to CEU re-ordering and sub-sampling
++ * capabilities.
++ */
++static const struct ceu_fmt ceu_fmt_list[] = {
++	{
++		.fourcc	= V4L2_PIX_FMT_NV16,
++		.bpp	= 16,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV61,
++		.bpp	= 16,
++	},
++	{
++		.fourcc	= V4L2_PIX_FMT_NV12,
++		.bpp	= 12,
++	},
++	{
++		.fourcc	= V4L2_PIX_FMT_NV21,
++		.bpp	= 12,
++	},
++	{
++		.fourcc	= V4L2_PIX_FMT_YUYV,
++		.bpp	= 16,
++	},
++};
++
++static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc)
++{
++	const struct ceu_fmt *fmt = &ceu_fmt_list[0];
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++)
++		if (fmt->fourcc == fourcc)
++			return fmt;
++
++	return NULL;
++}
++
++static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix)
++{
++	switch (pix->pixelformat) {
++	case V4L2_PIX_FMT_YUYV:
++		return false;
++	case V4L2_PIX_FMT_NV16:
++	case V4L2_PIX_FMT_NV61:
++	case V4L2_PIX_FMT_NV12:
++	case V4L2_PIX_FMT_NV21:
++		return true;
++	default:
++		return false;
++	}
++}
++
++/* --- CEU HW operations --- */
++
++static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data)
++{
++	iowrite32(data, priv->base + reg_offs);
++}
++
++static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs)
++{
++	return ioread32(priv->base + reg_offs);
++}
++
++/*
++ * ceu_soft_reset() - Software reset the CEU interface.
++ * @ceu_device: CEU device.
++ *
++ * Returns 0 for success, -EIO for error.
++ */
++static int ceu_soft_reset(struct ceu_device *ceudev)
++{
++	unsigned int i;
++
++	ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL);
++
++	for (i = 0; i < 100; i++) {
++		if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON))
++			break;
++		udelay(1);
++	}
++
++	if (i == 100) {
++		dev_err(ceudev->dev, "soft reset time out\n");
++		return -EIO;
++	}
++
++	for (i = 0; i < 100; i++) {
++		if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL))
++			return 0;
++		udelay(1);
++	}
++
++	/* If we get here, CEU has not reset properly. */
++	return -EIO;
++}
++
++/* --- CEU Capture Operations --- */
++
++/*
++ * ceu_hw_config() - Configure CEU interface registers.
++ */
++static int ceu_hw_config(struct ceu_device *ceudev)
++{
++	u32 camcr, cdocr, cfzsr, cdwdr, capwr;
++	struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
++	unsigned int mbus_flags = ceu_sd->mbus_flags;
++
++	/* Start configuring CEU registers */
++	ceu_write(ceudev, CEU_CAIFR, 0);
++	ceu_write(ceudev, CEU_CFWCR, 0);
++	ceu_write(ceudev, CEU_CRCNTR, 0);
++	ceu_write(ceudev, CEU_CRCMPR, 0);
++
++	/* Set the frame capture period for both image capture and data sync. */
++	capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;
++
++	/*
++	 * Swap input data endianness by default.
++	 * In data fetch mode bytes are received in chunks of 8 bytes.
++	 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)
++	 * The data is however by default written to memory in reverse order:
++	 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)
++	 *
++	 * Use CEU_CDOCR[2:0] to swap data ordering.
++	 */
++	cdocr = CEU_CDOCR_SWAP_ENDIANNESS;
++
++	/*
++	 * Configure CAMCR and CDOCR:
++	 * match input components ordering with memory output format and
++	 * handle downsampling to YUV420.
++	 *
++	 * If the memory output planar format is 'swapped' (Cr before Cb) and
++	 * input format is not, use the swapped version of CAMCR.DTARY.
++	 *
++	 * If the memory output planar format is not 'swapped' (Cb before Cr)
++	 * and input format is, use the swapped version of CAMCR.DTARY.
++	 *
++	 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).
++	 * If output is planar YUV422 set CDOCR[4] = 1
++	 *
++	 * No downsample for data fetch sync mode.
++	 */
++	switch (pix->pixelformat) {
++	/* Data fetch sync mode */
++	case V4L2_PIX_FMT_YUYV:
++		/* TODO: handle YUYV permutations through DTARY bits. */
++		camcr	= CEU_CAMCR_JPEG;
++		cdocr	|= CEU_CDOCR_NO_DOWSAMPLE;
++		cfzsr	= (pix->height << 16) | pix->width;
++		cdwdr	= pix->plane_fmt[0].bytesperline;
++		break;
++
++	/* Non-swapped planar image capture mode. */
++	case V4L2_PIX_FMT_NV16:
++		cdocr	|= CEU_CDOCR_NO_DOWSAMPLE;
++		/* fall-through */
++	case V4L2_PIX_FMT_NV12:
++		if (mbus_fmt->swapped)
++			camcr = mbus_fmt->fmt_order_swap;
++		else
++			camcr = mbus_fmt->fmt_order;
++
++		cfzsr	= (pix->height << 16) | pix->width;
++		cdwdr	= pix->width;
++		break;
++
++	/* Swapped planar image capture mode. */
++	case V4L2_PIX_FMT_NV61:
++		cdocr	|= CEU_CDOCR_NO_DOWSAMPLE;
++		/* fall-through */
++	case V4L2_PIX_FMT_NV21:
++		if (mbus_fmt->swapped)
++			camcr = mbus_fmt->fmt_order;
++		else
++			camcr = mbus_fmt->fmt_order_swap;
++
++		cfzsr	= (pix->height << 16) | pix->width;
++		cdwdr	= pix->width;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;
++	camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;
++
++	/* TODO: handle 16 bit bus width with DTIF bit in CAMCR */
++	ceu_write(ceudev, CEU_CAMCR, camcr);
++	ceu_write(ceudev, CEU_CDOCR, cdocr);
++	ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);
++
++	/*
++	 * TODO: make CAMOR offsets configurable.
++	 * CAMOR wants to know the number of blanks between a VS/HS signal
++	 * and valid data. This value should actually come from the sensor...
++	 */
++	ceu_write(ceudev, CEU_CAMOR, 0);
++
++	/* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */
++	ceu_write(ceudev, CEU_CAPWR, capwr);
++	ceu_write(ceudev, CEU_CFSZR, cfzsr);
++	ceu_write(ceudev, CEU_CDWDR, cdwdr);
++
++	return 0;
++}
++
++/*
++ * ceu_capture() - Trigger start of a capture sequence.
++ *
++ * Program the CEU DMA registers with addresses where to transfer image data.
++ */
++static int ceu_capture(struct ceu_device *ceudev)
++{
++	struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
++	dma_addr_t phys_addr_top;
++
++	phys_addr_top =
++		vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0);
++	ceu_write(ceudev, CEU_CDAYR, phys_addr_top);
++
++	/* Ignore CbCr plane for non multi-planar image formats. */
++	if (ceu_fmt_mplane(pix)) {
++		phys_addr_top =
++			vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf,
++						      1);
++		ceu_write(ceudev, CEU_CDACR, phys_addr_top);
++	}
++
++	/*
++	 * Trigger new capture start: once for each frame, as we work in
++	 * one-frame capture mode.
++	 */
++	ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE);
++
++	return 0;
++}
++
++static irqreturn_t ceu_irq(int irq, void *data)
++{
++	struct ceu_device *ceudev = data;
++	struct vb2_v4l2_buffer *vbuf;
++	struct ceu_buffer *buf;
++	u32 status;
++
++	/* Clean interrupt status. */
++	status = ceu_read(ceudev, CEU_CETCR);
++	ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
++
++	/* Unexpected interrupt. */
++	if (!(status & CEU_CEIER_MASK))
++		return IRQ_NONE;
++
++	spin_lock(&ceudev->lock);
++
++	/* Stale interrupt from a released buffer, ignore it. */
++	vbuf = ceudev->active;
++	if (!vbuf) {
++		spin_unlock(&ceudev->lock);
++		return IRQ_HANDLED;
++	}
++
++	/*
++	 * When a VBP interrupt occurs, no capture end interrupt will occur
++	 * and the image of that frame is not captured correctly.
++	 */
++	if (status & CEU_CEIER_VBP) {
++		dev_err(ceudev->dev, "VBP interrupt: abort capture\n");
++		goto error_irq_out;
++	}
++
++	/* Prepare to return the 'previous' buffer. */
++	vbuf->vb2_buf.timestamp = ktime_get_ns();
++	vbuf->sequence = ceudev->sequence++;
++	vbuf->field = ceudev->field;
++
++	/* Prepare a new 'active' buffer and trigger a new capture. */
++	if (!list_empty(&ceudev->capture)) {
++		buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
++				       queue);
++		list_del(&buf->queue);
++		ceudev->active = &buf->vb;
++
++		ceu_capture(ceudev);
++	}
++
++	/* Return the 'previous' buffer. */
++	vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
++
++	spin_unlock(&ceudev->lock);
++
++	return IRQ_HANDLED;
++
++error_irq_out:
++	/* Return the 'previous' buffer and all queued ones. */
++	vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR);
++
++	list_for_each_entry(buf, &ceudev->capture, queue)
++		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
++
++	spin_unlock(&ceudev->lock);
++
++	return IRQ_HANDLED;
++}
++
++/* --- CEU Videobuf2 operations --- */
++
++static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane,
++				   unsigned int bpl, unsigned int szimage)
++{
++	memset(plane, 0, sizeof(*plane));
++
++	plane->sizeimage = szimage;
++	if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL)
++		plane->bytesperline = bpl;
++}
++
++/*
++ * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format'
++ *			    information according to the currently configured
++ *			    pixel format.
++ * @ceu_device: CEU device.
++ * @ceu_fmt: Active image format.
++ * @pix: Pixel format information (store line width and image sizes)
++ */
++static void ceu_calc_plane_sizes(struct ceu_device *ceudev,
++				 const struct ceu_fmt *ceu_fmt,
++				 struct v4l2_pix_format_mplane *pix)
++{
++	unsigned int bpl, szimage;
++
++	switch (pix->pixelformat) {
++	case V4L2_PIX_FMT_YUYV:
++		pix->num_planes	= 1;
++		bpl		= pix->width * ceu_fmt->bpp / 8;
++		szimage		= pix->height * bpl;
++		ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
++		break;
++
++	case V4L2_PIX_FMT_NV12:
++	case V4L2_PIX_FMT_NV21:
++		pix->num_planes	= 2;
++		bpl		= pix->width;
++		szimage		= pix->height * pix->width;
++		ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
++		ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2);
++		break;
++
++	case V4L2_PIX_FMT_NV16:
++	case V4L2_PIX_FMT_NV61:
++	default:
++		pix->num_planes	= 2;
++		bpl		= pix->width;
++		szimage		= pix->height * pix->width;
++		ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
++		ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage);
++		break;
++	}
++}
++
++/*
++ * ceu_vb2_setup() - is called to check whether the driver can accept the
++ *		     requested number of buffers and to fill in plane sizes
++ *		     for the current frame format, if required.
++ */
++static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count,
++			 unsigned int *num_planes, unsigned int sizes[],
++			 struct device *alloc_devs[])
++{
++	struct ceu_device *ceudev = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
++	unsigned int i;
++
++	/* num_planes is set: just check plane sizes. */
++	if (*num_planes) {
++		for (i = 0; i < pix->num_planes; i++)
++			if (sizes[i] < pix->plane_fmt[i].sizeimage)
++				return -EINVAL;
++
++		return 0;
++	}
++
++	/* num_planes not set: called from REQBUFS, just set plane sizes. */
++	*num_planes = pix->num_planes;
++	for (i = 0; i < pix->num_planes; i++)
++		sizes[i] = pix->plane_fmt[i].sizeimage;
++
++	return 0;
++}
++
++static void ceu_vb2_queue(struct vb2_buffer *vb)
++{
++	struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++	struct ceu_buffer *buf = vb2_to_ceu(vbuf);
++	unsigned long irqflags;
++
++	spin_lock_irqsave(&ceudev->lock, irqflags);
++	list_add_tail(&buf->queue, &ceudev->capture);
++	spin_unlock_irqrestore(&ceudev->lock, irqflags);
++}
++
++static int ceu_vb2_prepare(struct vb2_buffer *vb)
++{
++	struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
++	struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
++	unsigned int i;
++
++	for (i = 0; i < pix->num_planes; i++) {
++		if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
++			dev_err(ceudev->dev,
++				"Plane size too small (%lu < %u)\n",
++				vb2_plane_size(vb, i),
++				pix->plane_fmt[i].sizeimage);
++			return -EINVAL;
++		}
++
++		vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
++	}
++
++	return 0;
++}
++
++static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++	struct ceu_device *ceudev = vb2_get_drv_priv(vq);
++	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
++	struct ceu_buffer *buf;
++	unsigned long irqflags;
++	int ret;
++
++	/* Program the CEU interface according to the CEU image format. */
++	ret = ceu_hw_config(ceudev);
++	if (ret)
++		goto error_return_bufs;
++
++	ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1);
++	if (ret && ret != -ENOIOCTLCMD) {
++		dev_dbg(ceudev->dev,
++			"Subdevice failed to start streaming: %d\n", ret);
++		goto error_return_bufs;
++	}
++
++	spin_lock_irqsave(&ceudev->lock, irqflags);
++	ceudev->sequence = 0;
++
++	/* Grab the first available buffer and trigger the first capture. */
++	buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
++			       queue);
++	if (!buf) {
++		spin_unlock_irqrestore(&ceudev->lock, irqflags);
++		dev_dbg(ceudev->dev,
++			"No buffer available for capture.\n");
++		goto error_stop_sensor;
++	}
++
++	list_del(&buf->queue);
++	ceudev->active = &buf->vb;
++
++	/* Clean and program interrupts for first capture. */
++	ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
++	ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
++
++	ceu_capture(ceudev);
++
++	spin_unlock_irqrestore(&ceudev->lock, irqflags);
++
++	return 0;
++
++error_stop_sensor:
++	v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
++
++error_return_bufs:
++	spin_lock_irqsave(&ceudev->lock, irqflags);
++	list_for_each_entry(buf, &ceudev->capture, queue)
++		vb2_buffer_done(&ceudev->active->vb2_buf,
++				VB2_BUF_STATE_QUEUED);
++	ceudev->active = NULL;
++	spin_unlock_irqrestore(&ceudev->lock, irqflags);
++
++	return ret;
++}
++
++static void ceu_stop_streaming(struct vb2_queue *vq)
++{
++	struct ceu_device *ceudev = vb2_get_drv_priv(vq);
++	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
++	struct ceu_buffer *buf;
++	unsigned long irqflags;
++
++	/* Clean and disable interrupt sources. */
++	ceu_write(ceudev, CEU_CETCR,
++		  ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask);
++	ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
++
++	v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
++
++	spin_lock_irqsave(&ceudev->lock, irqflags);
++	if (ceudev->active) {
++		vb2_buffer_done(&ceudev->active->vb2_buf,
++				VB2_BUF_STATE_ERROR);
++		ceudev->active = NULL;
++	}
++
++	/* Release all queued buffers. */
++	list_for_each_entry(buf, &ceudev->capture, queue)
++		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
++	INIT_LIST_HEAD(&ceudev->capture);
++
++	spin_unlock_irqrestore(&ceudev->lock, irqflags);
++
++	ceu_soft_reset(ceudev);
++}
++
++static const struct vb2_ops ceu_vb2_ops = {
++	.queue_setup		= ceu_vb2_setup,
++	.buf_queue		= ceu_vb2_queue,
++	.buf_prepare		= ceu_vb2_prepare,
++	.wait_prepare		= vb2_ops_wait_prepare,
++	.wait_finish		= vb2_ops_wait_finish,
++	.start_streaming	= ceu_start_streaming,
++	.stop_streaming		= ceu_stop_streaming,
++};
++
++/* --- CEU image formats handling --- */
++
++/*
++ * ceu_try_fmt() - test format on CEU and sensor
++ * @ceudev: The CEU device.
++ * @v4l2_fmt: format to test.
++ *
++ * Returns 0 for success, < 0 for errors.
++ */
++static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
++{
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
++	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
++	struct v4l2_subdev_pad_config pad_cfg;
++	const struct ceu_fmt *ceu_fmt;
++	int ret;
++
++	struct v4l2_subdev_format sd_format = {
++		.which = V4L2_SUBDEV_FORMAT_TRY,
++	};
++
++	switch (pix->pixelformat) {
++	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_NV16:
++	case V4L2_PIX_FMT_NV61:
++	case V4L2_PIX_FMT_NV12:
++	case V4L2_PIX_FMT_NV21:
++		break;
++
++	default:
++		pix->pixelformat = V4L2_PIX_FMT_NV16;
++		break;
++	}
++
++	ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat);
++
++	/* CFSZR requires height and width to be 4-pixel aligned. */
++	v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
++			      &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
++
++	/*
++	 * Set format on sensor sub device: bus format used to produce memory
++	 * format is selected at initialization time.
++	 */
++	v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
++	ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_cfg, &sd_format);
++	if (ret)
++		return ret;
++
++	/* Apply size returned by sensor as the CEU can't scale. */
++	v4l2_fill_pix_format_mplane(pix, &sd_format.format);
++
++	/* Calculate per-plane sizes based on image format. */
++	ceu_calc_plane_sizes(ceudev, ceu_fmt, pix);
++
++	return 0;
++}
++
++/*
++ * ceu_set_fmt() - Apply the supplied format to both sensor and CEU
++ */
++static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
++{
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
++	int ret;
++
++	struct v4l2_subdev_format format = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++
++	ret = ceu_try_fmt(ceudev, v4l2_fmt);
++	if (ret)
++		return ret;
++
++	v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp);
++	ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format);
++	if (ret)
++		return ret;
++
++	ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp;
++	ceudev->field = V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++/*
++ * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA
++ *			   sizes.
++ */
++static int ceu_set_default_fmt(struct ceu_device *ceudev)
++{
++	int ret;
++
++	struct v4l2_format v4l2_fmt = {
++		.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
++		.fmt.pix_mp = {
++			.width		= VGA_WIDTH,
++			.height		= VGA_HEIGHT,
++			.field		= V4L2_FIELD_NONE,
++			.pixelformat	= V4L2_PIX_FMT_NV16,
++			.num_planes	= 2,
++			.plane_fmt	= {
++				[0]	= {
++					.sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
++					.bytesperline = VGA_WIDTH * 2,
++				},
++				[1]	= {
++					.sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
++					.bytesperline = VGA_WIDTH * 2,
++				},
++			},
++		},
++	};
++
++	ret = ceu_try_fmt(ceudev, &v4l2_fmt);
++	if (ret)
++		return ret;
++
++	ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp;
++	ceudev->field = V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++/*
++ * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize
++ *			 CEU media bus format used to produce memory formats.
++ *
++ * Find out if sensor can produce a permutation of 8-bits YUYV bus format.
++ * From a single 8-bits YUYV bus format the CEU can produce several memory
++ * output formats:
++ * - NV[12|21|16|61] through image fetch mode;
++ * - YUYV422 if sensor provides YUYV422
++ *
++ * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY
++ * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode
++ */
++static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
++{
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
++	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
++	bool yuyv_bus_fmt = false;
++
++	struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.index = 0,
++	};
++
++	/* Find out if sensor can produce any permutation of 8-bits YUYV422. */
++	while (!yuyv_bus_fmt &&
++	       !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code,
++				 NULL, &sd_mbus_fmt)) {
++		switch (sd_mbus_fmt.code) {
++		case MEDIA_BUS_FMT_YUYV8_2X8:
++		case MEDIA_BUS_FMT_YVYU8_2X8:
++		case MEDIA_BUS_FMT_UYVY8_2X8:
++		case MEDIA_BUS_FMT_VYUY8_2X8:
++			yuyv_bus_fmt = true;
++			break;
++		default:
++			/*
++			 * Only support 8-bits YUYV bus formats at the moment;
++			 *
++			 * TODO: add support for binary formats (data sync
++			 * fetch mode).
++			 */
++			break;
++		}
++
++		sd_mbus_fmt.index++;
++	}
++
++	if (!yuyv_bus_fmt)
++		return -ENXIO;
++
++	/*
++	 * Save the first encountered YUYV format as "mbus_fmt" and use it
++	 * to output all planar YUV422 and YUV420 (NV*) formats to memory as
++	 * well as for data synch fetch mode (YUYV - YVYU etc. ).
++	 */
++	mbus_fmt->mbus_code	= sd_mbus_fmt.code;
++	mbus_fmt->bps		= 8;
++
++	/* Annotate the selected bus format components ordering. */
++	switch (sd_mbus_fmt.code) {
++	case MEDIA_BUS_FMT_YUYV8_2X8:
++		mbus_fmt->fmt_order		= CEU_CAMCR_DTARY_8_YUYV;
++		mbus_fmt->fmt_order_swap	= CEU_CAMCR_DTARY_8_YVYU;
++		mbus_fmt->swapped		= false;
++		mbus_fmt->bpp			= 16;
++		break;
++
++	case MEDIA_BUS_FMT_YVYU8_2X8:
++		mbus_fmt->fmt_order		= CEU_CAMCR_DTARY_8_YVYU;
++		mbus_fmt->fmt_order_swap	= CEU_CAMCR_DTARY_8_YUYV;
++		mbus_fmt->swapped		= true;
++		mbus_fmt->bpp			= 16;
++		break;
++
++	case MEDIA_BUS_FMT_UYVY8_2X8:
++		mbus_fmt->fmt_order		= CEU_CAMCR_DTARY_8_UYVY;
++		mbus_fmt->fmt_order_swap	= CEU_CAMCR_DTARY_8_VYUY;
++		mbus_fmt->swapped		= false;
++		mbus_fmt->bpp			= 16;
++		break;
++
++	case MEDIA_BUS_FMT_VYUY8_2X8:
++		mbus_fmt->fmt_order		= CEU_CAMCR_DTARY_8_VYUY;
++		mbus_fmt->fmt_order_swap	= CEU_CAMCR_DTARY_8_UYVY;
++		mbus_fmt->swapped		= true;
++		mbus_fmt->bpp			= 16;
++		break;
++	}
++
++	return 0;
++}
++
++/* --- Runtime PM Handlers --- */
++
++/*
++ * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
++ */
++static int ceu_runtime_resume(struct device *dev)
++{
++	struct ceu_device *ceudev = dev_get_drvdata(dev);
++	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
++
++	v4l2_subdev_call(v4l2_sd, core, s_power, 1);
++
++	ceu_soft_reset(ceudev);
++
++	return 0;
++}
++
++/*
++ * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
++ *			   Turn sensor power off.
++ */
++static int ceu_runtime_suspend(struct device *dev)
++{
++	struct ceu_device *ceudev = dev_get_drvdata(dev);
++	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
++
++	v4l2_subdev_call(v4l2_sd, core, s_power, 0);
++
++	ceu_write(ceudev, CEU_CEIER, 0);
++	ceu_soft_reset(ceudev);
++
++	return 0;
++}
++
++/* --- File Operations --- */
++
++static int ceu_open(struct file *file)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++	int ret;
++
++	ret = v4l2_fh_open(file);
++	if (ret)
++		return ret;
++
++	mutex_lock(&ceudev->mlock);
++	/* Causes soft-reset and sensor power on on first open */
++	pm_runtime_get_sync(ceudev->dev);
++	mutex_unlock(&ceudev->mlock);
++
++	return 0;
++}
++
++static int ceu_release(struct file *file)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	vb2_fop_release(file);
++
++	mutex_lock(&ceudev->mlock);
++	/* Causes soft-reset and sensor power down on last close */
++	pm_runtime_put(ceudev->dev);
++	mutex_unlock(&ceudev->mlock);
++
++	return 0;
++}
++
++static const struct v4l2_file_operations ceu_fops = {
++	.owner			= THIS_MODULE,
++	.open			= ceu_open,
++	.release		= ceu_release,
++	.unlocked_ioctl		= video_ioctl2,
++	.mmap			= vb2_fop_mmap,
++	.poll			= vb2_fop_poll,
++};
++
++/* --- Video Device IOCTLs --- */
++
++static int ceu_querycap(struct file *file, void *priv,
++			struct v4l2_capability *cap)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	strlcpy(cap->card, "Renesas CEU", sizeof(cap->card));
++	strlcpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
++	snprintf(cap->bus_info, sizeof(cap->bus_info),
++		 "platform:renesas-ceu-%s", dev_name(ceudev->dev));
++
++	return 0;
++}
++
++static int ceu_enum_fmt_vid_cap(struct file *file, void *priv,
++				struct v4l2_fmtdesc *f)
++{
++	const struct ceu_fmt *fmt;
++
++	if (f->index >= ARRAY_SIZE(ceu_fmt_list))
++		return -EINVAL;
++
++	fmt = &ceu_fmt_list[f->index];
++	f->pixelformat = fmt->fourcc;
++
++	return 0;
++}
++
++static int ceu_try_fmt_vid_cap(struct file *file, void *priv,
++			       struct v4l2_format *f)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	return ceu_try_fmt(ceudev, f);
++}
++
++static int ceu_s_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	if (vb2_is_streaming(&ceudev->vb2_vq))
++		return -EBUSY;
++
++	return ceu_set_fmt(ceudev, f);
++}
++
++static int ceu_g_fmt_vid_cap(struct file *file, void *priv,
++			     struct v4l2_format *f)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	f->fmt.pix_mp = ceudev->v4l2_pix;
++
++	return 0;
++}
++
++static int ceu_enum_input(struct file *file, void *priv,
++			  struct v4l2_input *inp)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++	struct ceu_subdev *ceusd;
++
++	if (inp->index >= ceudev->num_sd)
++		return -EINVAL;
++
++	ceusd = &ceudev->subdevs[inp->index];
++
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->std = 0;
++	snprintf(inp->name, sizeof(inp->name), "Camera%u: %s",
++		 inp->index, ceusd->v4l2_sd->name);
++
++	return 0;
++}
++
++static int ceu_g_input(struct file *file, void *priv, unsigned int *i)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	*i = ceudev->sd_index;
++
++	return 0;
++}
++
++static int ceu_s_input(struct file *file, void *priv, unsigned int i)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++	struct ceu_subdev *ceu_sd_old;
++	int ret;
++
++	if (i >= ceudev->num_sd)
++		return -EINVAL;
++
++	if (vb2_is_streaming(&ceudev->vb2_vq))
++		return -EBUSY;
++
++	if (i == ceudev->sd_index)
++		return 0;
++
++	ceu_sd_old = ceudev->sd;
++	ceudev->sd = &ceudev->subdevs[i];
++
++	/*
++	 * Make sure we can generate output image formats and apply
++	 * default one.
++	 */
++	ret = ceu_init_mbus_fmt(ceudev);
++	if (ret) {
++		ceudev->sd = ceu_sd_old;
++		return -EINVAL;
++	}
++
++	ret = ceu_set_default_fmt(ceudev);
++	if (ret) {
++		ceudev->sd = ceu_sd_old;
++		return -EINVAL;
++	}
++
++	/* Now that we're sure we can use the sensor, power off the old one. */
++	v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0);
++	v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1);
++
++	ceudev->sd_index = i;
++
++	return 0;
++}
++
++static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
++}
++
++static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++
++	return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
++}
++
++static int ceu_enum_framesizes(struct file *file, void *fh,
++			       struct v4l2_frmsizeenum *fsize)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	const struct ceu_fmt *ceu_fmt;
++	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
++	int ret;
++
++	struct v4l2_subdev_frame_size_enum fse = {
++		.code	= ceu_sd->mbus_fmt.mbus_code,
++		.index	= fsize->index,
++		.which	= V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++
++	/* Just check if user supplied pixel format is supported. */
++	ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format);
++	if (!ceu_fmt)
++		return -EINVAL;
++
++	ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size,
++			       NULL, &fse);
++	if (ret)
++		return ret;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++	fsize->discrete.width = CEU_W_MAX(fse.max_width);
++	fsize->discrete.height = CEU_H_MAX(fse.max_height);
++
++	return 0;
++}
++
++static int ceu_enum_frameintervals(struct file *file, void *fh,
++				   struct v4l2_frmivalenum *fival)
++{
++	struct ceu_device *ceudev = video_drvdata(file);
++	struct ceu_subdev *ceu_sd = ceudev->sd;
++	const struct ceu_fmt *ceu_fmt;
++	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
++	int ret;
++
++	struct v4l2_subdev_frame_interval_enum fie = {
++		.code	= ceu_sd->mbus_fmt.mbus_code,
++		.index = fival->index,
++		.width = fival->width,
++		.height = fival->height,
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++
++	/* Just check if user supplied pixel format is supported. */
++	ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format);
++	if (!ceu_fmt)
++		return -EINVAL;
++
++	ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL,
++			       &fie);
++	if (ret)
++		return ret;
++
++	fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++	fival->discrete = fie.interval;
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops ceu_ioctl_ops = {
++	.vidioc_querycap		= ceu_querycap,
++
++	.vidioc_enum_fmt_vid_cap_mplane	= ceu_enum_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap_mplane	= ceu_try_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap_mplane	= ceu_s_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap_mplane	= ceu_g_fmt_vid_cap,
++
++	.vidioc_enum_input		= ceu_enum_input,
++	.vidioc_g_input			= ceu_g_input,
++	.vidioc_s_input			= ceu_s_input,
++
++	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
++	.vidioc_querybuf		= vb2_ioctl_querybuf,
++	.vidioc_qbuf			= vb2_ioctl_qbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
++	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
++	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
++	.vidioc_streamon		= vb2_ioctl_streamon,
++	.vidioc_streamoff		= vb2_ioctl_streamoff,
++
++	.vidioc_g_parm			= ceu_g_parm,
++	.vidioc_s_parm			= ceu_s_parm,
++	.vidioc_enum_framesizes		= ceu_enum_framesizes,
++	.vidioc_enum_frameintervals	= ceu_enum_frameintervals,
++
++	.vidioc_log_status              = v4l2_ctrl_log_status,
++	.vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
++	.vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
++};
++
++/*
++ * ceu_vdev_release() - release CEU video device memory when last reference
++ *			to this driver is closed
++ */
++static void ceu_vdev_release(struct video_device *vdev)
++{
++	struct ceu_device *ceudev = video_get_drvdata(vdev);
++
++	kfree(ceudev);
++}
++
++static int ceu_notify_bound(struct v4l2_async_notifier *notifier,
++			    struct v4l2_subdev *v4l2_sd,
++			    struct v4l2_async_subdev *asd)
++{
++	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
++	struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
++	struct ceu_subdev *ceu_sd = to_ceu_subdev(asd);
++
++	ceu_sd->v4l2_sd = v4l2_sd;
++	ceudev->num_sd++;
++
++	return 0;
++}
++
++static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
++{
++	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
++	struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
++	struct video_device *vdev = &ceudev->vdev;
++	struct vb2_queue *q = &ceudev->vb2_vq;
++	struct v4l2_subdev *v4l2_sd;
++	int ret;
++
++	/* Initialize vb2 queue. */
++	q->type			= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	q->io_modes		= VB2_MMAP | VB2_DMABUF;
++	q->drv_priv		= ceudev;
++	q->ops			= &ceu_vb2_ops;
++	q->mem_ops		= &vb2_dma_contig_memops;
++	q->buf_struct_size	= sizeof(struct ceu_buffer);
++	q->timestamp_flags	= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	q->min_buffers_needed	= 2;
++	q->lock			= &ceudev->mlock;
++	q->dev			= ceudev->v4l2_dev.dev;
++
++	ret = vb2_queue_init(q);
++	if (ret)
++		return ret;
++
++	/*
++	 * Make sure at least one sensor is primary and use it to initialize
++	 * ceu formats.
++	 */
++	if (!ceudev->sd) {
++		ceudev->sd = &ceudev->subdevs[0];
++		ceudev->sd_index = 0;
++	}
++
++	v4l2_sd = ceudev->sd->v4l2_sd;
++
++	ret = ceu_init_mbus_fmt(ceudev);
++	if (ret)
++		return ret;
++
++	ret = ceu_set_default_fmt(ceudev);
++	if (ret)
++		return ret;
++
++	/* Register the video device. */
++	strncpy(vdev->name, DRIVER_NAME, strlen(DRIVER_NAME));
++	vdev->v4l2_dev		= v4l2_dev;
++	vdev->lock		= &ceudev->mlock;
++	vdev->queue		= &ceudev->vb2_vq;
++	vdev->ctrl_handler	= v4l2_sd->ctrl_handler;
++	vdev->fops		= &ceu_fops;
++	vdev->ioctl_ops		= &ceu_ioctl_ops;
++	vdev->release		= ceu_vdev_release;
++	vdev->device_caps	= V4L2_CAP_VIDEO_CAPTURE_MPLANE |
++				  V4L2_CAP_STREAMING;
++	video_set_drvdata(vdev, ceudev);
++
++	ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
++	if (ret < 0) {
++		v4l2_err(vdev->v4l2_dev,
++			 "video_register_device failed: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static const struct v4l2_async_notifier_operations ceu_notify_ops = {
++	.bound		= ceu_notify_bound,
++	.complete	= ceu_notify_complete,
++};
++
++/*
++ * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in
++ *			      ceu device. Both DT and platform data parsing use
++ *			      this routine.
++ *
++ * Returns 0 for success, -ENOMEM for failure.
++ */
++static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd)
++{
++	/* Reserve memory for 'n_sd' ceu_subdev descriptors. */
++	ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd,
++				       sizeof(*ceudev->subdevs), GFP_KERNEL);
++	if (!ceudev->subdevs)
++		return -ENOMEM;
++
++	/*
++	 * Reserve memory for 'n_sd' pointers to async_subdevices.
++	 * ceudev->asds members will point to &ceu_subdev.asd
++	 */
++	ceudev->asds = devm_kcalloc(ceudev->dev, n_sd,
++				    sizeof(*ceudev->asds), GFP_KERNEL);
++	if (!ceudev->asds)
++		return -ENOMEM;
++
++	ceudev->sd = NULL;
++	ceudev->sd_index = 0;
++	ceudev->num_sd = 0;
++
++	return 0;
++}
++
++/*
++ * ceu_parse_platform_data() - Initialize async_subdevices using platform
++ *			       device provided data.
++ */
++static int ceu_parse_platform_data(struct ceu_device *ceudev,
++				   const struct ceu_platform_data *pdata)
++{
++	const struct ceu_async_subdev *async_sd;
++	struct ceu_subdev *ceu_sd;
++	unsigned int i;
++	int ret;
++
++	if (pdata->num_subdevs == 0)
++		return -ENODEV;
++
++	ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < pdata->num_subdevs; i++) {
++		/* Setup the ceu subdevice and the async subdevice. */
++		async_sd = &pdata->subdevs[i];
++		ceu_sd = &ceudev->subdevs[i];
++
++		INIT_LIST_HEAD(&ceu_sd->asd.list);
++
++		ceu_sd->mbus_flags	= async_sd->flags;
++		ceu_sd->asd.match_type	= V4L2_ASYNC_MATCH_I2C;
++		ceu_sd->asd.match.i2c.adapter_id = async_sd->i2c_adapter_id;
++		ceu_sd->asd.match.i2c.address = async_sd->i2c_address;
++
++		ceudev->asds[i] = &ceu_sd->asd;
++	}
++
++	return pdata->num_subdevs;
++}
++
++/*
++ * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph.
++ */
++static int ceu_parse_dt(struct ceu_device *ceudev)
++{
++	struct device_node *of = ceudev->dev->of_node;
++	struct v4l2_fwnode_endpoint fw_ep;
++	struct ceu_subdev *ceu_sd;
++	struct device_node *ep;
++	unsigned int i;
++	int num_ep;
++	int ret;
++
++	num_ep = of_graph_get_endpoint_count(of);
++	if (!num_ep)
++		return -ENODEV;
++
++	ret = ceu_init_async_subdevs(ceudev, num_ep);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < num_ep; i++) {
++		ep = of_graph_get_endpoint_by_regs(of, 0, i);
++		if (!ep) {
++			dev_err(ceudev->dev,
++				"No subdevice connected on endpoint %u.\n", i);
++			ret = -ENODEV;
++			goto error_put_node;
++		}
++
++		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
++		if (ret) {
++			dev_err(ceudev->dev,
++				"Unable to parse endpoint #%u.\n", i);
++			goto error_put_node;
++		}
++
++		if (fw_ep.bus_type != V4L2_MBUS_PARALLEL) {
++			dev_err(ceudev->dev,
++				"Only parallel input supported.\n");
++			ret = -EINVAL;
++			goto error_put_node;
++		}
++
++		/* Setup the ceu subdevice and the async subdevice. */
++		ceu_sd = &ceudev->subdevs[i];
++		INIT_LIST_HEAD(&ceu_sd->asd.list);
++
++		ceu_sd->mbus_flags = fw_ep.bus.parallel.flags;
++		ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
++		ceu_sd->asd.match.fwnode.fwnode =
++			fwnode_graph_get_remote_port_parent(
++					of_fwnode_handle(ep));
++
++		ceudev->asds[i] = &ceu_sd->asd;
++		of_node_put(ep);
++	}
++
++	return num_ep;
++
++error_put_node:
++	of_node_put(ep);
++	return ret;
++}
++
++/*
++ * struct ceu_data - Platform specific CEU data
++ * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs
++ *	      between SH4 and RZ platforms.
++ */
++struct ceu_data {
++	u32 irq_mask;
++};
++
++static const struct ceu_data ceu_data_rz = {
++	.irq_mask = CEU_CETCR_ALL_IRQS_RZ,
++};
++
++static const struct ceu_data ceu_data_sh4 = {
++	.irq_mask = CEU_CETCR_ALL_IRQS_SH4,
++};
++
++#if IS_ENABLED(CONFIG_OF)
++static const struct of_device_id ceu_of_match[] = {
++	{ .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ceu_of_match);
++#endif
++
++static int ceu_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	const struct ceu_data *ceu_data;
++	struct ceu_device *ceudev;
++	struct resource *res;
++	unsigned int irq;
++	int num_subdevs;
++	int ret;
++
++	ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL);
++	if (!ceudev)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, ceudev);
++	ceudev->dev = dev;
++
++	INIT_LIST_HEAD(&ceudev->capture);
++	spin_lock_init(&ceudev->lock);
++	mutex_init(&ceudev->mlock);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	ceudev->base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(ceudev->base)) {
++		ret = PTR_ERR(ceudev->base);
++		goto error_free_ceudev;
++	}
++
++	ret = platform_get_irq(pdev, 0);
++	if (ret < 0) {
++		dev_err(dev, "Failed to get irq: %d\n", ret);
++		goto error_free_ceudev;
++	}
++	irq = ret;
++
++	ret = devm_request_irq(dev, irq, ceu_irq,
++			       0, dev_name(dev), ceudev);
++	if (ret) {
++		dev_err(&pdev->dev, "Unable to request CEU interrupt.\n");
++		goto error_free_ceudev;
++	}
++
++	pm_runtime_enable(dev);
++
++	ret = v4l2_device_register(dev, &ceudev->v4l2_dev);
++	if (ret)
++		goto error_pm_disable;
++
++	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
++		ceu_data = of_match_device(ceu_of_match, dev)->data;
++		num_subdevs = ceu_parse_dt(ceudev);
++	} else if (dev->platform_data) {
++		/* Assume SH4 if booting with platform data. */
++		ceu_data = &ceu_data_sh4;
++		num_subdevs = ceu_parse_platform_data(ceudev,
++						      dev->platform_data);
++	} else {
++		num_subdevs = -EINVAL;
++	}
++
++	if (num_subdevs < 0) {
++		ret = num_subdevs;
++		goto error_v4l2_unregister;
++	}
++	ceudev->irq_mask = ceu_data->irq_mask;
++
++	ceudev->notifier.v4l2_dev	= &ceudev->v4l2_dev;
++	ceudev->notifier.subdevs	= ceudev->asds;
++	ceudev->notifier.num_subdevs	= num_subdevs;
++	ceudev->notifier.ops		= &ceu_notify_ops;
++	ret = v4l2_async_notifier_register(&ceudev->v4l2_dev,
++					   &ceudev->notifier);
++	if (ret)
++		goto error_v4l2_unregister;
++
++	dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev));
++
++	return 0;
++
++error_v4l2_unregister:
++	v4l2_device_unregister(&ceudev->v4l2_dev);
++error_pm_disable:
++	pm_runtime_disable(dev);
++error_free_ceudev:
++	kfree(ceudev);
++
++	return ret;
++}
++
++static int ceu_remove(struct platform_device *pdev)
++{
++	struct ceu_device *ceudev = platform_get_drvdata(pdev);
++
++	pm_runtime_disable(ceudev->dev);
++
++	v4l2_async_notifier_unregister(&ceudev->notifier);
++
++	v4l2_device_unregister(&ceudev->v4l2_dev);
++
++	video_unregister_device(&ceudev->vdev);
++
++	return 0;
++}
++
++static const struct dev_pm_ops ceu_pm_ops = {
++	SET_RUNTIME_PM_OPS(ceu_runtime_suspend,
++			   ceu_runtime_resume,
++			   NULL)
++};
++
++static struct platform_driver ceu_driver = {
++	.driver		= {
++		.name	= DRIVER_NAME,
++		.pm	= &ceu_pm_ops,
++		.of_match_table = of_match_ptr(ceu_of_match),
++	},
++	.probe		= ceu_probe,
++	.remove		= ceu_remove,
++};
++
++module_platform_driver(ceu_driver);
++
++MODULE_DESCRIPTION("Renesas CEU camera driver");
++MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.19.0
+
diff --git a/patches/1122-media-platform-renesas-ceu-Fix-CSTRST_CPON-mask.patch b/patches/1122-media-platform-renesas-ceu-Fix-CSTRST_CPON-mask.patch
new file mode 100644
index 00000000000000..0c8ca757ba66db
--- /dev/null
+++ b/patches/1122-media-platform-renesas-ceu-Fix-CSTRST_CPON-mask.patch
@@ -0,0 +1,34 @@
+From dfb776ec6d2e81301f1b571eec440c77e74d3d37 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 27 Feb 2018 12:32:52 -0500
+Subject: [PATCH 1122/1795] media: platform: renesas-ceu: Fix CSTRST_CPON mask
+
+The CSTRST_CPON mask was wrongly assigned to BIT(1) instead of BIT(0).
+Fix that by changing the mask opportunely.
+
+Reported-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 309131594016651ab44753ea447a36987e8f4c23)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/renesas-ceu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+index 15148479a061..4242b4b3c1b3 100644
+--- a/drivers/media/platform/renesas-ceu.c
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -95,7 +95,7 @@
+ 
+ /* CEU operating flag bit. */
+ #define CEU_CAPCR_CTNCP			BIT(16)
+-#define CEU_CSTRST_CPTON		BIT(1)
++#define CEU_CSTRST_CPTON		BIT(0)
+ 
+ /* Platform specific IRQ source flags. */
+ #define CEU_CETCR_ALL_IRQS_RZ		0x397f313
+-- 
+2.19.0
+
diff --git a/patches/1123-media-renesas-ceu-mark-PM-functions-as-__maybe_unuse.patch b/patches/1123-media-renesas-ceu-mark-PM-functions-as-__maybe_unuse.patch
new file mode 100644
index 00000000000000..abca2037ea05af
--- /dev/null
+++ b/patches/1123-media-renesas-ceu-mark-PM-functions-as-__maybe_unuse.patch
@@ -0,0 +1,55 @@
+From 25939d0e27f0102e18869df90ba6706f470207c7 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 28 Feb 2018 18:19:37 -0500
+Subject: [PATCH 1123/1795] media: renesas-ceu: mark PM functions as
+ __maybe_unused
+
+The PM runtime operations are unused when CONFIG_PM is disabled,
+leading to a harmless warning:
+
+drivers/media/platform/renesas-ceu.c:1003:12: error: 'ceu_runtime_suspend' defined but not used [-Werror=unused-function]
+ static int ceu_runtime_suspend(struct device *dev)
+            ^~~~~~~~~~~~~~~~~~~
+drivers/media/platform/renesas-ceu.c:987:12: error: 'ceu_runtime_resume' defined but not used [-Werror=unused-function]
+ static int ceu_runtime_resume(struct device *dev)
+            ^~~~~~~~~~~~~~~~~~
+
+This adds a __maybe_unused annotation to shut up the warning.
+
+Fixes: 32e5a70dc8f4 ("media: platform: Add Renesas CEU driver")
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 997ef6b2627c54f5404c2f444e52c7140d1b6d01)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/renesas-ceu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+index 4242b4b3c1b3..49592030f2f1 100644
+--- a/drivers/media/platform/renesas-ceu.c
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -984,7 +984,7 @@ static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
+ /*
+  * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
+  */
+-static int ceu_runtime_resume(struct device *dev)
++static int __maybe_unused ceu_runtime_resume(struct device *dev)
+ {
+ 	struct ceu_device *ceudev = dev_get_drvdata(dev);
+ 	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
+@@ -1000,7 +1000,7 @@ static int ceu_runtime_resume(struct device *dev)
+  * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
+  *			   Turn sensor power off.
+  */
+-static int ceu_runtime_suspend(struct device *dev)
++static int __maybe_unused ceu_runtime_suspend(struct device *dev)
+ {
+ 	struct ceu_device *ceudev = dev_get_drvdata(dev);
+ 	struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
+-- 
+2.19.0
+
diff --git a/patches/1124-gpio-pca953x-add-compatibility-for-pcal6524-and-pcal.patch b/patches/1124-gpio-pca953x-add-compatibility-for-pcal6524-and-pcal.patch
new file mode 100644
index 00000000000000..89d1f3c3bfa0f6
--- /dev/null
+++ b/patches/1124-gpio-pca953x-add-compatibility-for-pcal6524-and-pcal.patch
@@ -0,0 +1,62 @@
+From e183634a771dc4675e16feeabf97538564be0a27 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 10 Mar 2018 12:00:01 +0100
+Subject: [PATCH 1124/1795] gpio: pca953x: add compatibility for pcal6524 and
+ pcal9555a
+
+The Pyra-Handheld originally used the tca6424 but recently we have
+replaced it by the pin and package compatible pcal6524. So let's
+add this to the bindings and the driver.
+
+And while we are at it, the pcal9555a does not have a compatible entry
+either but is already supported by the device id table.
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 3a711e0dd4e68f6b202db3f9e2c0086a8780da25)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 2 ++
+ drivers/gpio/gpio-pca953x.c                             | 4 ++++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+index 0d0158728f89..d2a937682836 100644
+--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+@@ -16,6 +16,8 @@ Required properties:
+ 	nxp,pca9574
+ 	nxp,pca9575
+ 	nxp,pca9698
++	nxp,pcal6524
++	nxp,pcal9555a
+ 	maxim,max7310
+ 	maxim,max7312
+ 	maxim,max7313
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index c4795167119b..c8bfd4acb40d 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -70,6 +70,7 @@ static const struct i2c_device_id pca953x_id[] = {
+ 	{ "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
+ 	{ "pca9698", 40 | PCA953X_TYPE, },
+ 
++	{ "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
+ 	{ "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
+ 
+ 	{ "max7310", 8  | PCA953X_TYPE, },
+@@ -935,6 +936,9 @@ static const struct of_device_id pca953x_dt_ids[] = {
+ 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+ 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ 
++	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_INT), },
++	{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_INT), },
++
+ 	{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
+ 	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+ 	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
+-- 
+2.19.0
+
diff --git a/patches/1125-irqchip-renesas-irqc-Use-wakeup_path-i.s.o.-explicit.patch b/patches/1125-irqchip-renesas-irqc-Use-wakeup_path-i.s.o.-explicit.patch
new file mode 100644
index 00000000000000..9c477981f6282f
--- /dev/null
+++ b/patches/1125-irqchip-renesas-irqc-Use-wakeup_path-i.s.o.-explicit.patch
@@ -0,0 +1,112 @@
+From ca4410f99af07b0fa1948eb95e954e666f51e660 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Feb 2018 14:55:12 +0100
+Subject: [PATCH 1125/1795] irqchip/renesas-irqc: Use wakeup_path i.s.o.
+ explicit clock handling
+
+Since commit 6f46aedb9c85873b ("irqchip: renesas-irqc: Add wake-up
+support"), when an IRQ is used for wakeup, the INTC
+block's module clock is manually kept running during system suspend, to
+make sure the device stays active.
+
+However, this explicit clock handling is merely a workaround for a
+failure to properly communicate wakeup information to the device core.
+
+Instead, set the device's power.wakeup_path field, to indicate this
+device is part of the wakeup path.  Depending on the PM Domain's
+active_wakeup configuration, the genpd core code will keep the device
+enabled (and the clock running) during system suspend when needed.
+This allows for the removal of all explicit clock handling code from the
+driver.
+
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit 734e036a9e1052da0b4b22bc320f6b30964e346d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-renesas-irqc.c | 30 ++++++++++++++++--------------
+ 1 file changed, 16 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
+index 52304b139aa4..a4f11124024d 100644
+--- a/drivers/irqchip/irq-renesas-irqc.c
++++ b/drivers/irqchip/irq-renesas-irqc.c
+@@ -17,7 +17,6 @@
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+-#include <linux/clk.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/spinlock.h>
+@@ -64,7 +63,7 @@ struct irqc_priv {
+ 	struct platform_device *pdev;
+ 	struct irq_chip_generic *gc;
+ 	struct irq_domain *irq_domain;
+-	struct clk *clk;
++	atomic_t wakeup_path;
+ };
+ 
+ static struct irqc_priv *irq_data_to_priv(struct irq_data *data)
+@@ -111,14 +110,10 @@ static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
+ 	int hw_irq = irqd_to_hwirq(d);
+ 
+ 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
+-
+-	if (!p->clk)
+-		return 0;
+-
+ 	if (on)
+-		clk_enable(p->clk);
++		atomic_inc(&p->wakeup_path);
+ 	else
+-		clk_disable(p->clk);
++		atomic_dec(&p->wakeup_path);
+ 
+ 	return 0;
+ }
+@@ -159,12 +154,6 @@ static int irqc_probe(struct platform_device *pdev)
+ 	p->pdev = pdev;
+ 	platform_set_drvdata(pdev, p);
+ 
+-	p->clk = devm_clk_get(&pdev->dev, NULL);
+-	if (IS_ERR(p->clk)) {
+-		dev_warn(&pdev->dev, "unable to get clock\n");
+-		p->clk = NULL;
+-	}
+-
+ 	pm_runtime_enable(&pdev->dev);
+ 	pm_runtime_get_sync(&pdev->dev);
+ 
+@@ -276,6 +265,18 @@ static int irqc_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static int __maybe_unused irqc_suspend(struct device *dev)
++{
++	struct irqc_priv *p = dev_get_drvdata(dev);
++
++	if (atomic_read(&p->wakeup_path))
++		device_set_wakeup_path(dev);
++
++	return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);
++
+ static const struct of_device_id irqc_dt_ids[] = {
+ 	{ .compatible = "renesas,irqc", },
+ 	{},
+@@ -288,6 +289,7 @@ static struct platform_driver irqc_device_driver = {
+ 	.driver		= {
+ 		.name	= "renesas_irqc",
+ 		.of_match_table	= irqc_dt_ids,
++		.pm	= &irqc_pm_ops,
+ 	}
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1126-irqchip-renesas-intc-irqpin-Use-wakeup_path-i.s.o.-e.patch b/patches/1126-irqchip-renesas-intc-irqpin-Use-wakeup_path-i.s.o.-e.patch
new file mode 100644
index 00000000000000..a818a3f714a195
--- /dev/null
+++ b/patches/1126-irqchip-renesas-intc-irqpin-Use-wakeup_path-i.s.o.-e.patch
@@ -0,0 +1,139 @@
+From 6ab225da2e5e2dba647dbf1d01ce308458d85bb7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Feb 2018 14:55:11 +0100
+Subject: [PATCH 1126/1795] irqchip/renesas-intc-irqpin: Use wakeup_path i.s.o.
+ explicit clock handling
+
+Since commit 705bc96c2c15313c ("irqchip: renesas-intc-irqpin: Add
+minimal runtime PM support"), when an IRQ is used for wakeup, the INTC
+block's module clock (if exists) is manually kept running during system
+suspend, to make sure the device stays active.
+
+However, this explicit clock handling is merely a workaround for a
+failure to properly communicate wakeup information to the device core.
+
+Instead, set the device's power.wakeup_path field, to indicate this
+device is part of the wakeup path.  Depending on the PM Domain's
+active_wakeup configuration, the genpd core code will keep the device
+enabled (and the clock running) during system suspend when needed.
+This allows for the removal of all explicit clock handling code from the
+driver.
+
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+(cherry picked from commit 66bf8252cf0d79ba693183d6b858885a19825d10)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/irqchip/irq-renesas-intc-irqpin.c | 40 +++++++++--------------
+ 1 file changed, 16 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
+index 06f29cf5018a..11704418e181 100644
+--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
++++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
+@@ -17,7 +17,6 @@
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+-#include <linux/clk.h>
+ #include <linux/init.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+@@ -78,16 +77,14 @@ struct intc_irqpin_priv {
+ 	struct platform_device *pdev;
+ 	struct irq_chip irq_chip;
+ 	struct irq_domain *irq_domain;
+-	struct clk *clk;
++	atomic_t wakeup_path;
+ 	unsigned shared_irqs:1;
+-	unsigned needs_clk:1;
+ 	u8 shared_irq_mask;
+ };
+ 
+ struct intc_irqpin_config {
+ 	unsigned int irlm_bit;
+ 	unsigned needs_irlm:1;
+-	unsigned needs_clk:1;
+ };
+ 
+ static unsigned long intc_irqpin_read32(void __iomem *iomem)
+@@ -287,14 +284,10 @@ static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
+ 	int hw_irq = irqd_to_hwirq(d);
+ 
+ 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
+-
+-	if (!p->clk)
+-		return 0;
+-
+ 	if (on)
+-		clk_enable(p->clk);
++		atomic_inc(&p->wakeup_path);
+ 	else
+-		clk_disable(p->clk);
++		atomic_dec(&p->wakeup_path);
+ 
+ 	return 0;
+ }
+@@ -365,12 +358,10 @@ static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
+ static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
+ 	.irlm_bit = 23, /* ICR0.IRLM0 */
+ 	.needs_irlm = 1,
+-	.needs_clk = 0,
+ };
+ 
+ static const struct intc_irqpin_config intc_irqpin_rmobile = {
+ 	.needs_irlm = 0,
+-	.needs_clk = 1,
+ };
+ 
+ static const struct of_device_id intc_irqpin_dt_ids[] = {
+@@ -422,18 +413,6 @@ static int intc_irqpin_probe(struct platform_device *pdev)
+ 	platform_set_drvdata(pdev, p);
+ 
+ 	config = of_device_get_match_data(dev);
+-	if (config)
+-		p->needs_clk = config->needs_clk;
+-
+-	p->clk = devm_clk_get(dev, NULL);
+-	if (IS_ERR(p->clk)) {
+-		if (p->needs_clk) {
+-			dev_err(dev, "unable to get clock\n");
+-			ret = PTR_ERR(p->clk);
+-			goto err0;
+-		}
+-		p->clk = NULL;
+-	}
+ 
+ 	pm_runtime_enable(dev);
+ 	pm_runtime_get_sync(dev);
+@@ -602,12 +581,25 @@ static int intc_irqpin_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static int __maybe_unused intc_irqpin_suspend(struct device *dev)
++{
++	struct intc_irqpin_priv *p = dev_get_drvdata(dev);
++
++	if (atomic_read(&p->wakeup_path))
++		device_set_wakeup_path(dev);
++
++	return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
++
+ static struct platform_driver intc_irqpin_device_driver = {
+ 	.probe		= intc_irqpin_probe,
+ 	.remove		= intc_irqpin_remove,
+ 	.driver		= {
+ 		.name	= "renesas_intc_irqpin",
+ 		.of_match_table = intc_irqpin_dt_ids,
++		.pm	= &intc_irqpin_pm_ops,
+ 	}
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1127-gpio-gpio-rcar-Support-S2RAM.patch b/patches/1127-gpio-gpio-rcar-Support-S2RAM.patch
new file mode 100644
index 00000000000000..aef86af62a46e9
--- /dev/null
+++ b/patches/1127-gpio-gpio-rcar-Support-S2RAM.patch
@@ -0,0 +1,123 @@
+From d1366b19af1d50879f0d34c3633f012e209b3938 Mon Sep 17 00:00:00 2001
+From: Hien Dang <hien.dang.eb@renesas.com>
+Date: Mon, 5 Feb 2018 04:15:02 +0900
+Subject: [PATCH 1127/1795] gpio: gpio-rcar: Support S2RAM
+
+This patch adds an implementation that saves and restores the state of
+GPIO configuration on suspend and resume.
+
+Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[Modify structure of the bank info to simplify a saving registers]
+[Remove DEV_PM_OPS macro]
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 51750fb167a054684a18c20e0e78f7f65b12c985)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/gpio/gpio-rcar.c
+---
+ drivers/gpio/gpio-rcar.c | 60 ++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 58 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index 4a0dc495efcd..21d55d361e8a 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -30,6 +30,16 @@
+ #include <linux/spinlock.h>
+ #include <linux/slab.h>
+ 
++struct gpio_rcar_bank_info {
++	u32 iointsel;
++	u32 inoutsel;
++	u32 outdt;
++	u32 posneg;
++	u32 edglevel;
++	u32 bothedge;
++	u32 intmsk;
++};
++
+ struct gpio_rcar_priv {
+ 	void __iomem *base;
+ 	spinlock_t lock;
+@@ -39,6 +49,7 @@ struct gpio_rcar_priv {
+ 	unsigned int irq_parent;
+ 	atomic_t wakeup_path;
+ 	bool has_both_edge_trigger;
++	struct gpio_rcar_bank_info bank_info;
+ };
+ 
+ #define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
+@@ -512,17 +523,62 @@ static int gpio_rcar_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
+-static int __maybe_unused gpio_rcar_suspend(struct device *dev)
++#ifdef CONFIG_PM_SLEEP
++static int gpio_rcar_suspend(struct device *dev)
+ {
+ 	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+ 
++	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
++	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
++	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
++	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
++	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
++	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
++	if (p->has_both_edge_trigger)
++		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
++
+ 	if (atomic_read(&p->wakeup_path))
+ 		device_set_wakeup_path(dev);
+ 
+ 	return 0;
+ }
+ 
+-static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, NULL);
++static int gpio_rcar_resume(struct device *dev)
++{
++	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
++	unsigned int offset;
++	u32 mask;
++
++	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
++		mask = BIT(offset);
++		/* I/O pin */
++		if (!(p->bank_info.iointsel & mask)) {
++			if (p->bank_info.inoutsel & mask)
++				gpio_rcar_direction_output(
++					&p->gpio_chip, offset,
++					!!(p->bank_info.outdt & mask));
++			else
++				gpio_rcar_direction_input(&p->gpio_chip,
++							  offset);
++		} else {
++			/* Interrupt pin */
++			gpio_rcar_config_interrupt_input_mode(
++				p,
++				offset,
++				!(p->bank_info.posneg & mask),
++				!(p->bank_info.edglevel & mask),
++				!!(p->bank_info.bothedge & mask));
++
++			if (p->bank_info.intmsk & mask)
++				gpio_rcar_write(p, MSKCLR, mask);
++		}
++	}
++
++	return 0;
++}
++#endif /* CONFIG_PM_SLEEP*/
++
++static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
+ 
+ static struct platform_driver gpio_rcar_device_driver = {
+ 	.probe		= gpio_rcar_probe,
+-- 
+2.19.0
+
diff --git a/patches/1128-clk-renesas-Stop-enabling-legacy-DT-clock-support-by.patch b/patches/1128-clk-renesas-Stop-enabling-legacy-DT-clock-support-by.patch
new file mode 100644
index 00000000000000..a9a7a555d99d9b
--- /dev/null
+++ b/patches/1128-clk-renesas-Stop-enabling-legacy-DT-clock-support-by.patch
@@ -0,0 +1,40 @@
+From a66e6ef242dc8c0873e1405ca919f3f562dd7efe Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 25 Apr 2017 14:04:35 +0200
+Subject: [PATCH 1128/1795] clk: renesas: Stop enabling legacy DT clock support
+ by default
+
+Since v4.15-rc1, the DTS files for all R-Car Gen2 SoCs have been
+converted to the new CPG/MSSR bindings.  Hence it is now safe to no
+longer enable legacy DT clock support by default.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f1a2879c1c57eb40747db3ff1b7b80cb9041e11b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index 43b5a89c4b28..84b40b95ca0e 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -24,12 +24,13 @@ if CLK_RENESAS
+ config CLK_RENESAS_LEGACY
+ 	bool "Legacy DT clock support"
+ 	depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
+-	default y
+ 	help
+ 	  Enable backward compatibility with old device trees describing a
+ 	  hierarchical representation of the various CPG and MSTP clocks.
+ 
+ 	  Say Y if you want your kernel to work with old DTBs.
++	  It is safe to say N if you use the DTS that is supplied with the
++	  current kernel source tree.
+ 
+ # SoC
+ config CLK_EMEV2
+-- 
+2.19.0
+
diff --git a/patches/1129-clk-renesas-rcar-gen3-Add-Z-clock-divider-support.patch b/patches/1129-clk-renesas-rcar-gen3-Add-Z-clock-divider-support.patch
new file mode 100644
index 00000000000000..649d962413474c
--- /dev/null
+++ b/patches/1129-clk-renesas-rcar-gen3-Add-Z-clock-divider-support.patch
@@ -0,0 +1,192 @@
+From fdee0f6b86fa5735f8b82bee7b546659dc28d7f4 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:49 +0100
+Subject: [PATCH 1129/1795] clk: renesas: rcar-gen3: Add Z clock divider
+ support
+
+This patch adds Z clock divider support for R-Car Gen3 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3391891fa9c82fd14bcddec2f422299b57ce8091)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen3-cpg.c | 133 ++++++++++++++++++++++++++++
+ drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
+ 2 files changed, 134 insertions(+)
+
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index 0904886f5501..b85918fa62c6 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -13,6 +13,7 @@
+  */
+ 
+ #include <linux/bug.h>
++#include <linux/bitfield.h>
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+@@ -61,6 +62,134 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
+ 	raw_notifier_chain_register(notifiers, &csn->nb);
+ }
+ 
++/*
++ * Z Clock
++ *
++ * Traits of this clock:
++ * prepare - clk_prepare only ensures that parents are prepared
++ * enable - clk_enable only ensures that parents are enabled
++ * rate - rate is adjustable.  clk->rate = (parent->rate * mult / 32 ) / 2
++ * parent - fixed parent.  No clk_set_parent support
++ */
++#define CPG_FRQCRB			0x00000004
++#define CPG_FRQCRB_KICK			BIT(31)
++#define CPG_FRQCRC			0x000000e0
++#define CPG_FRQCRC_ZFC_MASK		GENMASK(12, 8)
++
++struct cpg_z_clk {
++	struct clk_hw hw;
++	void __iomem *reg;
++	void __iomem *kick_reg;
++};
++
++#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
++
++static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
++					   unsigned long parent_rate)
++{
++	struct cpg_z_clk *zclk = to_z_clk(hw);
++	unsigned int mult;
++
++	mult = 32 - FIELD_GET(CPG_FRQCRC_ZFC_MASK, clk_readl(zclk->reg));
++
++	/* Factor of 2 is for fixed divider */
++	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
++}
++
++static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
++				 unsigned long *parent_rate)
++{
++	/* Factor of 2 is for fixed divider */
++	unsigned long prate = *parent_rate / 2;
++	unsigned int mult;
++
++	mult = div_u64(rate * 32ULL, prate);
++	mult = clamp(mult, 1U, 32U);
++
++	return (u64)prate * mult / 32;
++}
++
++static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
++			      unsigned long parent_rate)
++{
++	struct cpg_z_clk *zclk = to_z_clk(hw);
++	unsigned int mult;
++	unsigned int i;
++	u32 val, kick;
++
++	/* Factor of 2 is for fixed divider */
++	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
++	mult = clamp(mult, 1U, 32U);
++
++	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
++		return -EBUSY;
++
++	val = clk_readl(zclk->reg) & ~CPG_FRQCRC_ZFC_MASK;
++	val |= FIELD_PREP(CPG_FRQCRC_ZFC_MASK, 32 - mult);
++	clk_writel(val, zclk->reg);
++
++	/*
++	 * Set KICK bit in FRQCRB to update hardware setting and wait for
++	 * clock change completion.
++	 */
++	kick = clk_readl(zclk->kick_reg);
++	kick |= CPG_FRQCRB_KICK;
++	clk_writel(kick, zclk->kick_reg);
++
++	/*
++	 * Note: There is no HW information about the worst case latency.
++	 *
++	 * Using experimental measurements, it seems that no more than
++	 * ~10 iterations are needed, independently of the CPU rate.
++	 * Since this value might be dependent of external xtal rate, pll1
++	 * rate or even the other emulation clocks rate, use 1000 as a
++	 * "super" safe value.
++	 */
++	for (i = 1000; i; i--) {
++		if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
++			return 0;
++
++		cpu_relax();
++	}
++
++	return -ETIMEDOUT;
++}
++
++static const struct clk_ops cpg_z_clk_ops = {
++	.recalc_rate = cpg_z_clk_recalc_rate,
++	.round_rate = cpg_z_clk_round_rate,
++	.set_rate = cpg_z_clk_set_rate,
++};
++
++static struct clk * __init cpg_z_clk_register(const char *name,
++					      const char *parent_name,
++					      void __iomem *reg)
++{
++	struct clk_init_data init;
++	struct cpg_z_clk *zclk;
++	struct clk *clk;
++
++	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
++	if (!zclk)
++		return ERR_PTR(-ENOMEM);
++
++	init.name = name;
++	init.ops = &cpg_z_clk_ops;
++	init.flags = 0;
++	init.parent_names = &parent_name;
++	init.num_parents = 1;
++
++	zclk->reg = reg + CPG_FRQCRC;
++	zclk->kick_reg = reg + CPG_FRQCRB;
++	zclk->hw.init = &init;
++
++	clk = clk_register(NULL, &zclk->hw);
++	if (IS_ERR(clk))
++		kfree(zclk);
++
++	return clk;
++}
++
+ /*
+  * SDn Clock
+  */
+@@ -420,6 +549,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 		mult = 1;
+ 		break;
+ 
++	case CLK_TYPE_GEN3_Z:
++		return cpg_z_clk_register(core->name, __clk_get_name(parent),
++					  base);
++
+ 	default:
+ 		return ERR_PTR(-EINVAL);
+ 	}
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
+index 2e4284399f53..c73d4d6fdc85 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.h
++++ b/drivers/clk/renesas/rcar-gen3-cpg.h
+@@ -21,6 +21,7 @@ enum rcar_gen3_clk_types {
+ 	CLK_TYPE_GEN3_SD,
+ 	CLK_TYPE_GEN3_R,
+ 	CLK_TYPE_GEN3_PE,
++	CLK_TYPE_GEN3_Z,
+ };
+ 
+ #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
+-- 
+2.19.0
+
diff --git a/patches/1130-clk-renesas-rcar-gen3-Add-Z2-clock-divider-support.patch b/patches/1130-clk-renesas-rcar-gen3-Add-Z2-clock-divider-support.patch
new file mode 100644
index 00000000000000..35ac8f0646b8d2
--- /dev/null
+++ b/patches/1130-clk-renesas-rcar-gen3-Add-Z2-clock-divider-support.patch
@@ -0,0 +1,115 @@
+From ede4c18d52a6c364f5b283ace8b066470c7e4d2e Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:50 +0100
+Subject: [PATCH 1130/1795] clk: renesas: rcar-gen3: Add Z2 clock divider
+ support
+
+This patch adds Z2 clock divider support for R-Car Gen3 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 41ceeb5fef7719474a17a5a6052cae5b6c9e37c0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen3-cpg.c | 22 ++++++++++++++++------
+ drivers/clk/renesas/rcar-gen3-cpg.h |  1 +
+ 2 files changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index b85918fa62c6..0c8fe10d57fe 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -63,7 +63,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
+ }
+ 
+ /*
+- * Z Clock
++ * Z Clock & Z2 Clock
+  *
+  * Traits of this clock:
+  * prepare - clk_prepare only ensures that parents are prepared
+@@ -75,11 +75,13 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
+ #define CPG_FRQCRB_KICK			BIT(31)
+ #define CPG_FRQCRC			0x000000e0
+ #define CPG_FRQCRC_ZFC_MASK		GENMASK(12, 8)
++#define CPG_FRQCRC_Z2FC_MASK		GENMASK(4, 0)
+ 
+ struct cpg_z_clk {
+ 	struct clk_hw hw;
+ 	void __iomem *reg;
+ 	void __iomem *kick_reg;
++	unsigned long mask;
+ };
+ 
+ #define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
+@@ -89,8 +91,10 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+ {
+ 	struct cpg_z_clk *zclk = to_z_clk(hw);
+ 	unsigned int mult;
++	u32 val;
+ 
+-	mult = 32 - FIELD_GET(CPG_FRQCRC_ZFC_MASK, clk_readl(zclk->reg));
++	val = clk_readl(zclk->reg) & zclk->mask;
++	mult = 32 - (val >> __ffs(zclk->mask));
+ 
+ 	/* Factor of 2 is for fixed divider */
+ 	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
+@@ -124,8 +128,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+ 		return -EBUSY;
+ 
+-	val = clk_readl(zclk->reg) & ~CPG_FRQCRC_ZFC_MASK;
+-	val |= FIELD_PREP(CPG_FRQCRC_ZFC_MASK, 32 - mult);
++	val = clk_readl(zclk->reg) & ~zclk->mask;
++	val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
+ 	clk_writel(val, zclk->reg);
+ 
+ 	/*
+@@ -163,7 +167,8 @@ static const struct clk_ops cpg_z_clk_ops = {
+ 
+ static struct clk * __init cpg_z_clk_register(const char *name,
+ 					      const char *parent_name,
+-					      void __iomem *reg)
++					      void __iomem *reg,
++					      unsigned long mask)
+ {
+ 	struct clk_init_data init;
+ 	struct cpg_z_clk *zclk;
+@@ -182,6 +187,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
+ 	zclk->reg = reg + CPG_FRQCRC;
+ 	zclk->kick_reg = reg + CPG_FRQCRB;
+ 	zclk->hw.init = &init;
++	zclk->mask = mask;
+ 
+ 	clk = clk_register(NULL, &zclk->hw);
+ 	if (IS_ERR(clk))
+@@ -551,7 +557,11 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 
+ 	case CLK_TYPE_GEN3_Z:
+ 		return cpg_z_clk_register(core->name, __clk_get_name(parent),
+-					  base);
++					  base, CPG_FRQCRC_ZFC_MASK);
++
++	case CLK_TYPE_GEN3_Z2:
++		return cpg_z_clk_register(core->name, __clk_get_name(parent),
++					  base, CPG_FRQCRC_Z2FC_MASK);
+ 
+ 	default:
+ 		return ERR_PTR(-EINVAL);
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
+index c73d4d6fdc85..ea4f8fc3c4c9 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.h
++++ b/drivers/clk/renesas/rcar-gen3-cpg.h
+@@ -22,6 +22,7 @@ enum rcar_gen3_clk_types {
+ 	CLK_TYPE_GEN3_R,
+ 	CLK_TYPE_GEN3_PE,
+ 	CLK_TYPE_GEN3_Z,
++	CLK_TYPE_GEN3_Z2,
+ };
+ 
+ #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
+-- 
+2.19.0
+
diff --git a/patches/1131-clk-renesas-r8a7795-Add-Z-clock.patch b/patches/1131-clk-renesas-r8a7795-Add-Z-clock.patch
new file mode 100644
index 00000000000000..3e4f8375c61e82
--- /dev/null
+++ b/patches/1131-clk-renesas-r8a7795-Add-Z-clock.patch
@@ -0,0 +1,32 @@
+From b3ea3a3711b6e0ee86c6b6e499228b6951018274 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:51 +0100
+Subject: [PATCH 1131/1795] clk: renesas: r8a7795: Add Z clock
+
+This patch adds Z clock for R8A7795 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 4003508b4f233104a17150463604dc9c36833815)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+index b1d9f48eae9e..995a4c4fb01e 100644
+--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+@@ -74,6 +74,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
+ 	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
+ 
+ 	/* Core Clock Outputs */
++	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
+ 	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+ 	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ 	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+-- 
+2.19.0
+
diff --git a/patches/1132-clk-renesas-r8a7795-Add-Z2-clock.patch b/patches/1132-clk-renesas-r8a7795-Add-Z2-clock.patch
new file mode 100644
index 00000000000000..ac1f02383e23df
--- /dev/null
+++ b/patches/1132-clk-renesas-r8a7795-Add-Z2-clock.patch
@@ -0,0 +1,32 @@
+From 0feb9f39069b2b6afd4258df090fe94755c4034f Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:52 +0100
+Subject: [PATCH 1132/1795] clk: renesas: r8a7795: Add Z2 clock
+
+This patch adds Z2 clock for r8a7795 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 1eadca3557f77afbb64100e077f48ac338d731dc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+index 995a4c4fb01e..775b0ceaa337 100644
+--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+@@ -75,6 +75,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
+ 
+ 	/* Core Clock Outputs */
+ 	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
++	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+ 	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+ 	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ 	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+-- 
+2.19.0
+
diff --git a/patches/1133-clk-renesas-r8a7796-Add-Z-clock.patch b/patches/1133-clk-renesas-r8a7796-Add-Z-clock.patch
new file mode 100644
index 00000000000000..6216c12fc4efce
--- /dev/null
+++ b/patches/1133-clk-renesas-r8a7796-Add-Z-clock.patch
@@ -0,0 +1,32 @@
+From df91df183e022449ff4991fbe45da2fa7ff32157 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:53 +0100
+Subject: [PATCH 1133/1795] clk: renesas: r8a7796: Add Z clock
+
+This patch adds Z clock for R8A7796 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 72f2a6b31544da1978ab9fb032d0e17ded4af4a7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+index 41e29734126b..799a9e574e79 100644
+--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+@@ -74,6 +74,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
+ 	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
+ 
+ 	/* Core Clock Outputs */
++	DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
+ 	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+ 	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ 	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+-- 
+2.19.0
+
diff --git a/patches/1134-clk-renesas-r8a7796-Add-Z2-clock.patch b/patches/1134-clk-renesas-r8a7796-Add-Z2-clock.patch
new file mode 100644
index 00000000000000..d81e5852ca59e1
--- /dev/null
+++ b/patches/1134-clk-renesas-r8a7796-Add-Z2-clock.patch
@@ -0,0 +1,32 @@
+From 70cc598c507aae840b1f72035ce99003d7ed0f18 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 29 Jan 2018 19:01:54 +0100
+Subject: [PATCH 1134/1795] clk: renesas: r8a7796: Add Z2 clock
+
+This patch adds Z2 clock for R8A7796 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c50378efa9aa16acfe16d7313d29a874c2c86e5e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+index 799a9e574e79..dfb267a92f2a 100644
+--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
+@@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
+ 
+ 	/* Core Clock Outputs */
+ 	DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
++	DEF_BASE("z2",          R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+ 	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+ 	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ 	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+-- 
+2.19.0
+
diff --git a/patches/1135-clk-renesas-r8a7743-Add-rwdt-clock.patch b/patches/1135-clk-renesas-r8a7743-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..302f1e8ffa84c9
--- /dev/null
+++ b/patches/1135-clk-renesas-r8a7743-Add-rwdt-clock.patch
@@ -0,0 +1,42 @@
+From ab5f7fda473a7f1d7f579bfd58d8a909b814cf45 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:24 +0000
+Subject: [PATCH 1135/1795] clk: renesas: r8a7743: Add rwdt clock
+
+Add "rwdt" clock to r8a7743_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 039738bf986a516a01e96a4874c172dfe7e66892)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
+index 6dc0b3082aa6..d3c8b1e2969f 100644
+--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
+@@ -117,6 +117,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
+ 	DEF_MOD("cmt1",			 329,	R8A7743_CLK_R),
+ 	DEF_MOD("usbhs-dmac0",		 330,	R8A7743_CLK_HP),
+ 	DEF_MOD("usbhs-dmac1",		 331,	R8A7743_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A7743_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7743_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7743_CLK_ZS),
+ 	DEF_MOD("audio-dmac1",		 501,	R8A7743_CLK_HP),
+@@ -195,6 +196,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1136-clk-renesas-r8a7745-Add-rwdt-clock.patch b/patches/1136-clk-renesas-r8a7745-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..261b893d73880c
--- /dev/null
+++ b/patches/1136-clk-renesas-r8a7745-Add-rwdt-clock.patch
@@ -0,0 +1,42 @@
+From 27a8fc6c55f5e25343d83ae168d24b47110412fd Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:25 +0000
+Subject: [PATCH 1136/1795] clk: renesas: r8a7745: Add rwdt clock
+
+Add "rwdt" clock to r8a7745_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit e0c0a2c4a2bc7c2959d19600ccd03eec4b27c4be)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+index 2859504cc866..87f5a3619e4f 100644
+--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+@@ -114,6 +114,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
+ 	DEF_MOD("cmt1",			 329,	R8A7745_CLK_R),
+ 	DEF_MOD("usbhs-dmac0",		 330,	R8A7745_CLK_HP),
+ 	DEF_MOD("usbhs-dmac1",		 331,	R8A7745_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A7745_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7745_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7745_CLK_ZS),
+ 	DEF_MOD("audio-dmac0",		 502,	R8A7745_CLK_HP),
+@@ -180,6 +181,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1137-clk-renesas-r8a7790-Add-rwdt-clock.patch b/patches/1137-clk-renesas-r8a7790-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..69f4e0eaf17a27
--- /dev/null
+++ b/patches/1137-clk-renesas-r8a7790-Add-rwdt-clock.patch
@@ -0,0 +1,42 @@
+From 6db4652adcaffed76fe0bc16d7e0aac297707e55 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:26 +0000
+Subject: [PATCH 1137/1795] clk: renesas: r8a7790: Add rwdt clock
+
+Add "rwdt" clock to r8a7790_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 30c288bbf55c1356fd939b158a17c8e8612bdc11)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7790-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
+index 46bb55bb223d..f936cb74b681 100644
+--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
+@@ -140,6 +140,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+ 	DEF_MOD("cmt1",			 329,	R8A7790_CLK_R),
+ 	DEF_MOD("usbhs-dmac0",		 330,	R8A7790_CLK_HP),
+ 	DEF_MOD("usbhs-dmac1",		 331,	R8A7790_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A7790_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7790_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7790_CLK_ZS),
+ 	DEF_MOD("audio-dmac1",		 501,	R8A7790_CLK_HP),
+@@ -211,6 +212,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1138-clk-renesas-r8a7791-r8a7793-Add-rwdt-clock.patch b/patches/1138-clk-renesas-r8a7791-r8a7793-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..393b4db4ea3aed
--- /dev/null
+++ b/patches/1138-clk-renesas-r8a7791-r8a7793-Add-rwdt-clock.patch
@@ -0,0 +1,42 @@
+From ca55097cf038eabf1ee7a076f8f692e1108eacc4 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:27 +0000
+Subject: [PATCH 1138/1795] clk: renesas: r8a7791/r8a7793: Add rwdt clock
+
+Add "rwdt" clock to r8a7791_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5ada6bee8c966bf7bdc23512d1571adaeea22f0b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
+index c0b51f9bb278..820b220b09cc 100644
+--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
+@@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
+ 	DEF_MOD("cmt1",			 329,	R8A7791_CLK_R),
+ 	DEF_MOD("usbhs-dmac0",		 330,	R8A7791_CLK_HP),
+ 	DEF_MOD("usbhs-dmac1",		 331,	R8A7791_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A7791_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7791_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7791_CLK_ZS),
+ 	DEF_MOD("audio-dmac1",		 501,	R8A7791_CLK_HP),
+@@ -209,6 +210,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1139-clk-renesas-r8a7794-Add-rwdt-clock.patch b/patches/1139-clk-renesas-r8a7794-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..0db0041b4889c2
--- /dev/null
+++ b/patches/1139-clk-renesas-r8a7794-Add-rwdt-clock.patch
@@ -0,0 +1,42 @@
+From ddf731b3b5ed43bdbd3c3f525c8232d2e7d21f7c Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:28 +0000
+Subject: [PATCH 1139/1795] clk: renesas: r8a7794: Add rwdt clock
+
+Add "rwdt" clock to r8a7794_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c43d8630fe1a6bb09e005d38793346d989aa4dad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
+index ec091a42da54..2a40bbeaeeaf 100644
+--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
+@@ -121,6 +121,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+ 	DEF_MOD("cmt1",			 329,	R8A7794_CLK_R),
+ 	DEF_MOD("usbhs-dmac0",		 330,	R8A7794_CLK_HP),
+ 	DEF_MOD("usbhs-dmac1",		 331,	R8A7794_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A7794_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7794_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7794_CLK_ZS),
+ 	DEF_MOD("audio-dmac0",		 502,	R8A7794_CLK_HP),
+@@ -190,6 +191,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1140-clk-renesas-r8a7792-Add-rwdt-clock.patch b/patches/1140-clk-renesas-r8a7792-Add-rwdt-clock.patch
new file mode 100644
index 00000000000000..3e91790f16b178
--- /dev/null
+++ b/patches/1140-clk-renesas-r8a7792-Add-rwdt-clock.patch
@@ -0,0 +1,40 @@
+From f499a78a3e987f79ed466b1921b7370448fdbd18 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 7 Feb 2018 16:43:23 +0100
+Subject: [PATCH 1140/1795] clk: renesas: r8a7792: Add rwdt clock
+
+Add "rwdt" clock to r8a7792_mod_clks. Also, since we may need to access
+the watchdog registers at any time, declare the clock as critical.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 20254c7cea447d2ffba17046e3e80da667d742d3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
+index 7f85bbf20bf7..609a54080496 100644
+--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
+@@ -98,6 +98,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+ 	DEF_MOD("tpu0",			 304,	R8A7792_CLK_CP),
+ 	DEF_MOD("sdhi0",		 314,	R8A7792_CLK_SD),
+ 	DEF_MOD("cmt1",			 329,	R8A7792_CLK_R),
++	DEF_MOD("rwdt",			 402,	R8A7792_CLK_R),
+ 	DEF_MOD("irqc",			 407,	R8A7792_CLK_CP),
+ 	DEF_MOD("intc-sys",		 408,	R8A7792_CLK_ZS),
+ 	DEF_MOD("audio-dmac0",		 502,	R8A7792_CLK_HP),
+@@ -154,6 +155,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+ };
+ 
+ static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
+ 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1141-dt-bindings-clock-add-R8A77980-CPG-core-clock-defini.patch b/patches/1141-dt-bindings-clock-add-R8A77980-CPG-core-clock-defini.patch
new file mode 100644
index 00000000000000..66c11c033f0b43
--- /dev/null
+++ b/patches/1141-dt-bindings-clock-add-R8A77980-CPG-core-clock-defini.patch
@@ -0,0 +1,87 @@
+From 4670e54f86ff8a9d96780c543b2a23ce96d93740 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 15 Feb 2018 14:56:53 +0300
+Subject: [PATCH 1141/1795] dt-bindings: clock: add R8A77980 CPG core clock
+ definitions
+
+Add macros usable by the device tree sources to reference the R8A77980
+CPG core clocks by index. The data come from the table 8.2e of the R-Car
+Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
+however I had to add the Z2 clock which is somehow present only on the
+figure 8.1e...
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 35b3c462dae1b451772992d4e43bfef814499b49)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 +++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+ create mode 100644 include/dt-bindings/clock/r8a77980-cpg-mssr.h
+
+diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
+new file mode 100644
+index 000000000000..a4c0d76c392e
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
+@@ -0,0 +1,51 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a77980 CPG Core Clocks */
++#define R8A77980_CLK_Z2			0
++#define R8A77980_CLK_ZR			1
++#define R8A77980_CLK_ZTR		2
++#define R8A77980_CLK_ZTRD2		3
++#define R8A77980_CLK_ZT			4
++#define R8A77980_CLK_ZX			5
++#define R8A77980_CLK_S0D1		6
++#define R8A77980_CLK_S0D2		7
++#define R8A77980_CLK_S0D3		8
++#define R8A77980_CLK_S0D4		9
++#define R8A77980_CLK_S0D6		10
++#define R8A77980_CLK_S0D12		11
++#define R8A77980_CLK_S0D24		12
++#define R8A77980_CLK_S1D1		13
++#define R8A77980_CLK_S1D2		14
++#define R8A77980_CLK_S1D4		15
++#define R8A77980_CLK_S2D1		16
++#define R8A77980_CLK_S2D2		17
++#define R8A77980_CLK_S2D4		18
++#define R8A77980_CLK_S3D1		19
++#define R8A77980_CLK_S3D2		20
++#define R8A77980_CLK_S3D4		21
++#define R8A77980_CLK_LB			22
++#define R8A77980_CLK_CL			23
++#define R8A77980_CLK_ZB3		24
++#define R8A77980_CLK_ZB3D2		25
++#define R8A77980_CLK_ZB3D4		26
++#define R8A77980_CLK_SD0H		27
++#define R8A77980_CLK_SD0		28
++#define R8A77980_CLK_RPC		29
++#define R8A77980_CLK_RPCD2		30
++#define R8A77980_CLK_MSO		31
++#define R8A77980_CLK_CANFD		32
++#define R8A77980_CLK_CSI0		33
++#define R8A77980_CLK_CP			34
++#define R8A77980_CLK_CPEX		35
++#define R8A77980_CLK_R			36
++#define R8A77980_CLK_OSC		37
++
++#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1142-clk-renesas-cpg-mssr-add-R8A77980-support.patch b/patches/1142-clk-renesas-cpg-mssr-add-R8A77980-support.patch
new file mode 100644
index 00000000000000..788421ac20a4bb
--- /dev/null
+++ b/patches/1142-clk-renesas-cpg-mssr-add-R8A77980-support.patch
@@ -0,0 +1,352 @@
+From 288c7cf2779b285da81c4d2c591486a7b11133c3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 15 Feb 2018 14:58:45 +0300
+Subject: [PATCH 1142/1795] clk: renesas: cpg-mssr: add R8A77980 support
+
+Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
+Software Reset support,  using the CPG/MSSR driver core and the common
+R-Car Gen3 code.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ce15783c510a9905545e7708345454c38b725dd8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/renesas,cpg-mssr.txt       |   5 +-
+ drivers/clk/renesas/Kconfig                   |   5 +
+ drivers/clk/renesas/Makefile                  |   1 +
+ drivers/clk/renesas/r8a77980-cpg-mssr.c       | 227 ++++++++++++++++++
+ drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
+ 6 files changed, 243 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/renesas/r8a77980-cpg-mssr.c
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+index f1890d0777a6..bc4ea0868dbc 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+@@ -23,6 +23,7 @@ Required Properties:
+       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
+       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+       - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
++      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+       - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
+ 
+   - reg: Base address and length of the memory resource used by the CPG/MSSR
+@@ -32,8 +33,8 @@ Required Properties:
+     clock-names
+   - clock-names: List of external parent clock names. Valid names are:
+       - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+-		 r8a7795, r8a7796, r8a77970, r8a77995)
+-      - "extalr" (r8a7795, r8a7796, r8a77970)
++		 r8a7795, r8a7796, r8a77970, r8a77980, r8a77995)
++      - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980)
+       - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+ 
+   - #clock-cells: Must be 2
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index 84b40b95ca0e..43bab4f9c4e2 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -16,6 +16,7 @@ config CLK_RENESAS
+ 	select CLK_R8A7795 if ARCH_R8A7795
+ 	select CLK_R8A7796 if ARCH_R8A7796
+ 	select CLK_R8A77970 if ARCH_R8A77970
++	select CLK_R8A77980 if ARCH_R8A77980
+ 	select CLK_R8A77995 if ARCH_R8A77995
+ 	select CLK_SH73A0 if ARCH_SH73A0
+ 
+@@ -101,6 +102,10 @@ config CLK_R8A77970
+ 	bool "R-Car V3M clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+ 
++config CLK_R8A77980
++	bool "R-Car V3H clock support" if COMPILE_TEST
++	select CLK_RCAR_GEN3_CPG
++
+ config CLK_R8A77995
+ 	bool "R-Car D3 clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index 34c4e0b37afa..e20fa195d107 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_R8A7794)		+= r8a7794-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7795)		+= r8a7795-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o
++obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
+ obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
+ 
+diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
+new file mode 100644
+index 000000000000..7aaae73a321a
+--- /dev/null
++++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
+@@ -0,0 +1,227 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * Based on r8a7795-cpg-mssr.c
++ *
++ * Copyright (C) 2015 Glider bvba
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++#include <linux/sys_soc.h>
++
++#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen3-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++	CLK_EXTALR,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL1,
++	CLK_PLL2,
++	CLK_PLL3,
++	CLK_PLL1_DIV2,
++	CLK_PLL1_DIV4,
++	CLK_S0,
++	CLK_S1,
++	CLK_S2,
++	CLK_S3,
++	CLK_SDSRC,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",  CLK_EXTAL),
++	DEF_INPUT("extalr", CLK_EXTALR),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
++	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
++	DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
++	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
++
++	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,	   CLK_PLL1,       2, 1),
++	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,	   CLK_PLL1_DIV2,  2, 1),
++	DEF_FIXED(".s0",	CLK_S0,		   CLK_PLL1_DIV2,  2, 1),
++	DEF_FIXED(".s1",	CLK_S1,		   CLK_PLL1_DIV2,  3, 1),
++	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED(".sdsrc",	CLK_SDSRC,	   CLK_PLL1_DIV2,  2, 1),
++
++	/* Core Clock Outputs */
++	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED("ztrd2",	R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
++	DEF_FIXED("zt",		R8A77980_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED("zx",		R8A77980_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
++	DEF_FIXED("s0d1",	R8A77980_CLK_S0D1,  CLK_S0,         1, 1),
++	DEF_FIXED("s0d2",	R8A77980_CLK_S0D2,  CLK_S0,         2, 1),
++	DEF_FIXED("s0d3",	R8A77980_CLK_S0D3,  CLK_S0,         3, 1),
++	DEF_FIXED("s0d4",	R8A77980_CLK_S0D4,  CLK_S0,         4, 1),
++	DEF_FIXED("s0d6",	R8A77980_CLK_S0D6,  CLK_S0,         6, 1),
++	DEF_FIXED("s0d12",	R8A77980_CLK_S0D12, CLK_S0,        12, 1),
++	DEF_FIXED("s0d24",	R8A77980_CLK_S0D24, CLK_S0,        24, 1),
++	DEF_FIXED("s1d1",	R8A77980_CLK_S1D1,  CLK_S1,         1, 1),
++	DEF_FIXED("s1d2",	R8A77980_CLK_S1D2,  CLK_S1,         2, 1),
++	DEF_FIXED("s1d4",	R8A77980_CLK_S1D4,  CLK_S1,         4, 1),
++	DEF_FIXED("s2d1",	R8A77980_CLK_S2D1,  CLK_S2,         1, 1),
++	DEF_FIXED("s2d2",	R8A77980_CLK_S2D2,  CLK_S2,         2, 1),
++	DEF_FIXED("s2d4",	R8A77980_CLK_S2D4,  CLK_S2,         4, 1),
++	DEF_FIXED("s3d1",	R8A77980_CLK_S3D1,  CLK_S3,         1, 1),
++	DEF_FIXED("s3d2",	R8A77980_CLK_S3D2,  CLK_S3,         2, 1),
++	DEF_FIXED("s3d4",	R8A77980_CLK_S3D4,  CLK_S3,         4, 1),
++
++	DEF_GEN3_SD("sd0",	R8A77980_CLK_SD0,   CLK_SDSRC,	  0x0074),
++
++	DEF_FIXED("cl",		R8A77980_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
++	DEF_FIXED("cp",		R8A77980_CLK_CP,    CLK_EXTAL,	    2, 1),
++	DEF_FIXED("cpex",	R8A77980_CLK_CPEX,  CLK_EXTAL,	    2, 1),
++
++	DEF_DIV6P1("canfd",	R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
++	DEF_DIV6P1("csi0",	R8A77980_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
++	DEF_DIV6P1("mso",	R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
++};
++
++static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
++	DEF_MOD("tmu4",			 121,	R8A77980_CLK_S0D6),
++	DEF_MOD("tmu3",			 122,	R8A77980_CLK_S0D6),
++	DEF_MOD("tmu2",			 123,	R8A77980_CLK_S0D6),
++	DEF_MOD("tmu1",			 124,	R8A77980_CLK_S0D6),
++	DEF_MOD("tmu0",			 125,	R8A77980_CLK_CP),
++	DEF_MOD("scif4",		 203,	R8A77980_CLK_S3D4),
++	DEF_MOD("scif3",		 204,	R8A77980_CLK_S3D4),
++	DEF_MOD("scif1",		 206,	R8A77980_CLK_S3D4),
++	DEF_MOD("scif0",		 207,	R8A77980_CLK_S3D4),
++	DEF_MOD("msiof3",		 208,	R8A77980_CLK_MSO),
++	DEF_MOD("msiof2",		 209,	R8A77980_CLK_MSO),
++	DEF_MOD("msiof1",		 210,	R8A77980_CLK_MSO),
++	DEF_MOD("msiof0",		 211,	R8A77980_CLK_MSO),
++	DEF_MOD("sys-dmac2",		 217,	R8A77980_CLK_S0D3),
++	DEF_MOD("sys-dmac1",		 218,	R8A77980_CLK_S0D3),
++	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),
++	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),
++	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S3D1),
++	DEF_MOD("intc-ex",		 407,	R8A77980_CLK_CP),
++	DEF_MOD("intc-ap",		 408,	R8A77980_CLK_S0D3),
++	DEF_MOD("hscif3",		 517,	R8A77980_CLK_S3D1),
++	DEF_MOD("hscif2",		 518,	R8A77980_CLK_S3D1),
++	DEF_MOD("hscif1",		 519,	R8A77980_CLK_S3D1),
++	DEF_MOD("hscif0",		 520,	R8A77980_CLK_S3D1),
++	DEF_MOD("imp4",			 521,	R8A77980_CLK_S1D1),
++	DEF_MOD("thermal",		 522,	R8A77980_CLK_CP),
++	DEF_MOD("pwm",			 523,	R8A77980_CLK_S0D12),
++	DEF_MOD("impdma1",		 526,	R8A77980_CLK_S1D1),
++	DEF_MOD("impdma0",		 527,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp-ocv4",		 528,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp-ocv3",		 529,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp-ocv2",		 531,	R8A77980_CLK_S1D1),
++	DEF_MOD("fcpvd0",		 603,	R8A77980_CLK_S3D1),
++	DEF_MOD("vspd0",		 623,	R8A77980_CLK_S3D1),
++	DEF_MOD("csi41",		 715,	R8A77980_CLK_CSI0),
++	DEF_MOD("csi40",		 716,	R8A77980_CLK_CSI0),
++	DEF_MOD("du0",			 724,	R8A77980_CLK_S2D1),
++	DEF_MOD("lvds",			 727,	R8A77980_CLK_S2D1),
++	DEF_MOD("etheravb",		 812,	R8A77980_CLK_S3D2),
++	DEF_MOD("gether",		 813,	R8A77980_CLK_S3D2),
++	DEF_MOD("imp3",			 824,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp2",			 825,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp1",			 826,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp0",			 827,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp-ocv1",		 828,	R8A77980_CLK_S1D1),
++	DEF_MOD("imp-ocv0",		 829,	R8A77980_CLK_S1D1),
++	DEF_MOD("impram",		 830,	R8A77980_CLK_S1D1),
++	DEF_MOD("impcnn",		 831,	R8A77980_CLK_S1D1),
++	DEF_MOD("gpio5",		 907,	R8A77980_CLK_CP),
++	DEF_MOD("gpio4",		 908,	R8A77980_CLK_CP),
++	DEF_MOD("gpio3",		 909,	R8A77980_CLK_CP),
++	DEF_MOD("gpio2",		 910,	R8A77980_CLK_CP),
++	DEF_MOD("gpio1",		 911,	R8A77980_CLK_CP),
++	DEF_MOD("gpio0",		 912,	R8A77980_CLK_CP),
++	DEF_MOD("can-fd",		 914,	R8A77980_CLK_S3D2),
++	DEF_MOD("i2c4",			 927,	R8A77980_CLK_S0D6),
++	DEF_MOD("i2c3",			 928,	R8A77980_CLK_S0D6),
++	DEF_MOD("i2c2",			 929,	R8A77980_CLK_S3D2),
++	DEF_MOD("i2c1",			 930,	R8A77980_CLK_S3D2),
++	DEF_MOD("i2c0",			 931,	R8A77980_CLK_S3D2),
++};
++
++static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
++};
++
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ *   MD		EXTAL		PLL2	PLL1	PLL3
++ * 14 13	(MHz)
++ * --------------------------------------------------
++ * 0  0		16.66 x 1	x240	x192	x192
++ * 0  1		20    x 1	x200	x160	x160
++ * 1  0		27    x 1	x148	x118	x118
++ * 1  1		33.33 / 2	x240	x192	x192
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
++					 (((md) & BIT(13)) >> 13))
++
++static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
++	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
++	{ 1,		192,	1,	192,	1,	},
++	{ 1,		160,	1,	160,	1,	},
++	{ 1,		118,	1,	118,	1,	},
++	{ 2,		192,	1,	192,	1,	},
++};
++
++static int __init r8a77980_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++
++	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
++}
++
++const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks = r8a77980_core_clks,
++	.num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
++	.last_dt_core_clk = LAST_DT_CORE_CLK,
++	.num_total_core_clks = MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks = r8a77980_mod_clks,
++	.num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
++	.num_hw_mod_clks = 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks = r8a77980_crit_mod_clks,
++	.num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
++
++	/* Callbacks */
++	.init = r8a77980_cpg_mssr_init,
++	.cpg_clk_register = rcar_gen3_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 2c9988fef656..da5c3dacbab4 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -700,6 +700,12 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a77970_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_ARCH_R8A77980
++	{
++		.compatible = "renesas,r8a77980-cpg-mssr",
++		.data = &r8a77980_cpg_mssr_info,
++	},
++#endif
+ #ifdef CONFIG_CLK_R8A77995
+ 	{
+ 		.compatible = "renesas,r8a77995-cpg-mssr",
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index 0745b0930308..143293e3d193 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/1143-clk-renesas-cpg-mssr-Add-support-for-R-Car-M3-N.patch b/patches/1143-clk-renesas-cpg-mssr-Add-support-for-R-Car-M3-N.patch
new file mode 100644
index 00000000000000..58d3e1c30b13f5
--- /dev/null
+++ b/patches/1143-clk-renesas-cpg-mssr-Add-support-for-R-Car-M3-N.patch
@@ -0,0 +1,526 @@
+From 4e7693ad99dd17ca595d54bea2ae0d944df927ac Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 20 Feb 2018 16:12:03 +0100
+Subject: [PATCH 1143/1795] clk: renesas: cpg-mssr: Add support for R-Car M3-N
+
+Initial support for R-Car M3-N (r8a77965), including core and module
+clocks.
+
+Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual:
+Hardware (Rev. 0.80, Oct 31, 2017)".
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7ce36da900c0a2ff4777d9ba51c4f1cb74205463)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/renesas,cpg-mssr.txt       |   5 +-
+ drivers/clk/renesas/Kconfig                   |   5 +
+ drivers/clk/renesas/Makefile                  |   1 +
+ drivers/clk/renesas/r8a77965-cpg-mssr.c       | 334 ++++++++++++++++++
+ drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
+ include/dt-bindings/clock/r8a77965-cpg-mssr.h |  62 ++++
+ 7 files changed, 412 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c
+ create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+index bc4ea0868dbc..773a5226342f 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+@@ -22,6 +22,7 @@ Required Properties:
+       - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
+       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
+       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
++      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
+       - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+       - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+       - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
+@@ -33,8 +34,8 @@ Required Properties:
+     clock-names
+   - clock-names: List of external parent clock names. Valid names are:
+       - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+-		 r8a7795, r8a7796, r8a77970, r8a77980, r8a77995)
+-      - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980)
++		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
++      - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
+       - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+ 
+   - #clock-cells: Must be 2
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index 43bab4f9c4e2..ef76c861ec84 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -15,6 +15,7 @@ config CLK_RENESAS
+ 	select CLK_R8A7794 if ARCH_R8A7794
+ 	select CLK_R8A7795 if ARCH_R8A7795
+ 	select CLK_R8A7796 if ARCH_R8A7796
++	select CLK_R8A77965 if ARCH_R8A77965
+ 	select CLK_R8A77970 if ARCH_R8A77970
+ 	select CLK_R8A77980 if ARCH_R8A77980
+ 	select CLK_R8A77995 if ARCH_R8A77995
+@@ -98,6 +99,10 @@ config CLK_R8A7796
+ 	bool "R-Car M3-W clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+ 
++config CLK_R8A77965
++	bool "R-Car M3-N clock support" if COMPILE_TEST
++	select CLK_RCAR_GEN3_CPG
++
+ config CLK_R8A77970
+ 	bool "R-Car V3M clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index e20fa195d107..6c0f19636e3e 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792)		+= r8a7792-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7794)		+= r8a7794-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7795)		+= r8a7795-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o
++obj-$(CONFIG_CLK_R8A77965)		+= r8a77965-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
+diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+new file mode 100644
+index 000000000000..41e506ab557d
+--- /dev/null
++++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+@@ -0,0 +1,334 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ *
++ * Based on r8a7795-cpg-mssr.c
++ *
++ * Copyright (C) 2015 Glider bvba
++ * Copyright (C) 2015 Renesas Electronics Corp.
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++
++#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen3-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++	CLK_EXTALR,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL0,
++	CLK_PLL1,
++	CLK_PLL3,
++	CLK_PLL4,
++	CLK_PLL1_DIV2,
++	CLK_PLL1_DIV4,
++	CLK_S0,
++	CLK_S1,
++	CLK_S2,
++	CLK_S3,
++	CLK_SDSRC,
++	CLK_SSPSRC,
++	CLK_RINT,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",      CLK_EXTAL),
++	DEF_INPUT("extalr",     CLK_EXTALR),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
++	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
++	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
++	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
++	DEF_BASE(".pll4",	CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
++
++	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,		CLK_PLL1,	2, 1),
++	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,		CLK_PLL1_DIV2,	2, 1),
++	DEF_FIXED(".s0",	CLK_S0,			CLK_PLL1_DIV2,	2, 1),
++	DEF_FIXED(".s1",	CLK_S1,			CLK_PLL1_DIV2,	3, 1),
++	DEF_FIXED(".s2",	CLK_S2,			CLK_PLL1_DIV2,	4, 1),
++	DEF_FIXED(".s3",	CLK_S3,			CLK_PLL1_DIV2,	6, 1),
++	DEF_FIXED(".sdsrc",	CLK_SDSRC,		CLK_PLL1_DIV2,	2, 1),
++
++	/* Core Clock Outputs */
++	DEF_BASE("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z, CLK_PLL0),
++	DEF_FIXED("ztr",	R8A77965_CLK_ZTR,	CLK_PLL1_DIV2,	6, 1),
++	DEF_FIXED("ztrd2",	R8A77965_CLK_ZTRD2,	CLK_PLL1_DIV2,	12, 1),
++	DEF_FIXED("zt",		R8A77965_CLK_ZT,	CLK_PLL1_DIV2,	4, 1),
++	DEF_FIXED("zx",		R8A77965_CLK_ZX,	CLK_PLL1_DIV2,	2, 1),
++	DEF_FIXED("s0d1",	R8A77965_CLK_S0D1,	CLK_S0,		1, 1),
++	DEF_FIXED("s0d2",	R8A77965_CLK_S0D2,	CLK_S0,		2, 1),
++	DEF_FIXED("s0d3",	R8A77965_CLK_S0D3,	CLK_S0,		3, 1),
++	DEF_FIXED("s0d4",	R8A77965_CLK_S0D4,	CLK_S0,		4, 1),
++	DEF_FIXED("s0d6",	R8A77965_CLK_S0D6,	CLK_S0,		6, 1),
++	DEF_FIXED("s0d8",	R8A77965_CLK_S0D8,	CLK_S0,		8, 1),
++	DEF_FIXED("s0d12",	R8A77965_CLK_S0D12,	CLK_S0,		12, 1),
++	DEF_FIXED("s1d1",	R8A77965_CLK_S1D1,	CLK_S1,		1, 1),
++	DEF_FIXED("s1d2",	R8A77965_CLK_S1D2,	CLK_S1,		2, 1),
++	DEF_FIXED("s1d4",	R8A77965_CLK_S1D4,	CLK_S1,		4, 1),
++	DEF_FIXED("s2d1",	R8A77965_CLK_S2D1,	CLK_S2,		1, 1),
++	DEF_FIXED("s2d2",	R8A77965_CLK_S2D2,	CLK_S2,		2, 1),
++	DEF_FIXED("s2d4",	R8A77965_CLK_S2D4,	CLK_S2,		4, 1),
++	DEF_FIXED("s3d1",	R8A77965_CLK_S3D1,	CLK_S3,		1, 1),
++	DEF_FIXED("s3d2",	R8A77965_CLK_S3D2,	CLK_S3,		2, 1),
++	DEF_FIXED("s3d4",	R8A77965_CLK_S3D4,	CLK_S3,		4, 1),
++
++	DEF_GEN3_SD("sd0",	R8A77965_CLK_SD0,	CLK_SDSRC,	0x074),
++	DEF_GEN3_SD("sd1",	R8A77965_CLK_SD1,	CLK_SDSRC,	0x078),
++	DEF_GEN3_SD("sd2",	R8A77965_CLK_SD2,	CLK_SDSRC,	0x268),
++	DEF_GEN3_SD("sd3",	R8A77965_CLK_SD3,	CLK_SDSRC,	0x26c),
++
++	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2,	48, 1),
++	DEF_FIXED("cp",		R8A77965_CLK_CP,	CLK_EXTAL,	2, 1),
++
++	DEF_DIV6P1("canfd",	R8A77965_CLK_CANFD,	CLK_PLL1_DIV4,	0x244),
++	DEF_DIV6P1("csi0",	R8A77965_CLK_CSI0,	CLK_PLL1_DIV4,	0x00c),
++	DEF_DIV6P1("mso",	R8A77965_CLK_MSO,	CLK_PLL1_DIV4,	0x014),
++	DEF_DIV6P1("hdmi",	R8A77965_CLK_HDMI,	CLK_PLL1_DIV4,	0x250),
++
++	DEF_DIV6_RO("osc",	R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
++	DEF_DIV6_RO("r_int",	CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
++
++	DEF_BASE("r",		R8A77965_CLK_R,	CLK_TYPE_GEN3_R, CLK_RINT),
++};
++
++static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
++	DEF_MOD("scif5",		202,	R8A77965_CLK_S3D4),
++	DEF_MOD("scif4",		203,	R8A77965_CLK_S3D4),
++	DEF_MOD("scif3",		204,	R8A77965_CLK_S3D4),
++	DEF_MOD("scif1",		206,	R8A77965_CLK_S3D4),
++	DEF_MOD("scif0",		207,	R8A77965_CLK_S3D4),
++	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S0D3),
++	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S0D3),
++	DEF_MOD("sys-dmac0",		219,	R8A77965_CLK_S0D3),
++
++	DEF_MOD("cmt3",			300,	R8A77965_CLK_R),
++	DEF_MOD("cmt2",			301,	R8A77965_CLK_R),
++	DEF_MOD("cmt1",			302,	R8A77965_CLK_R),
++	DEF_MOD("cmt0",			303,	R8A77965_CLK_R),
++	DEF_MOD("scif2",		310,	R8A77965_CLK_S3D4),
++	DEF_MOD("sdif3",		311,	R8A77965_CLK_SD3),
++	DEF_MOD("sdif2",		312,	R8A77965_CLK_SD2),
++	DEF_MOD("sdif1",		313,	R8A77965_CLK_SD1),
++	DEF_MOD("sdif0",		314,	R8A77965_CLK_SD0),
++	DEF_MOD("pcie1",		318,	R8A77965_CLK_S3D1),
++	DEF_MOD("pcie0",		319,	R8A77965_CLK_S3D1),
++	DEF_MOD("usb3-if0",		328,	R8A77965_CLK_S3D1),
++	DEF_MOD("usb-dmac0",		330,	R8A77965_CLK_S3D1),
++	DEF_MOD("usb-dmac1",		331,	R8A77965_CLK_S3D1),
++
++	DEF_MOD("rwdt",			402,	R8A77965_CLK_R),
++	DEF_MOD("intc-ex",		407,	R8A77965_CLK_CP),
++	DEF_MOD("intc-ap",		408,	R8A77965_CLK_S0D3),
++
++	DEF_MOD("audmac1",		501,	R8A77965_CLK_S0D3),
++	DEF_MOD("audmac0",		502,	R8A77965_CLK_S0D3),
++	DEF_MOD("drif7",		508,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif6",		509,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif5",		510,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif4",		511,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif3",		512,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif2",		513,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif1",		514,	R8A77965_CLK_S3D2),
++	DEF_MOD("drif0",		515,	R8A77965_CLK_S3D2),
++	DEF_MOD("hscif4",		516,	R8A77965_CLK_S3D1),
++	DEF_MOD("hscif3",		517,	R8A77965_CLK_S3D1),
++	DEF_MOD("hscif2",		518,	R8A77965_CLK_S3D1),
++	DEF_MOD("hscif1",		519,	R8A77965_CLK_S3D1),
++	DEF_MOD("hscif0",		520,	R8A77965_CLK_S3D1),
++	DEF_MOD("thermal",		522,	R8A77965_CLK_CP),
++	DEF_MOD("pwm",			523,	R8A77965_CLK_S0D12),
++
++	DEF_MOD("fcpvd1",		602,	R8A77965_CLK_S0D2),
++	DEF_MOD("fcpvd0",		603,	R8A77965_CLK_S0D2),
++	DEF_MOD("fcpvb0",		607,	R8A77965_CLK_S0D1),
++	DEF_MOD("fcpvi0",		611,	R8A77965_CLK_S0D1),
++	DEF_MOD("fcpf0",		615,	R8A77965_CLK_S0D1),
++	DEF_MOD("fcpcs",		619,	R8A77965_CLK_S0D2),
++	DEF_MOD("vspd1",		622,	R8A77965_CLK_S0D2),
++	DEF_MOD("vspd0",		623,	R8A77965_CLK_S0D2),
++	DEF_MOD("vspb",			626,	R8A77965_CLK_S0D1),
++	DEF_MOD("vspi0",		631,	R8A77965_CLK_S0D1),
++
++	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D4),
++	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D4),
++	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D4),
++	DEF_MOD("csi20",		714,	R8A77965_CLK_CSI0),
++	DEF_MOD("csi40",		716,	R8A77965_CLK_CSI0),
++	DEF_MOD("du2",			722,	R8A77965_CLK_S2D1),
++	DEF_MOD("du1",			723,	R8A77965_CLK_S2D1),
++	DEF_MOD("du0",			724,	R8A77965_CLK_S2D1),
++	DEF_MOD("lvds",			727,	R8A77965_CLK_S2D1),
++	DEF_MOD("hdmi0",		729,	R8A77965_CLK_HDMI),
++
++	DEF_MOD("vin7",			804,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin6",			805,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin5",			806,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin4",			807,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin3",			808,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin2",			809,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin1",			810,	R8A77965_CLK_S0D2),
++	DEF_MOD("vin0",			811,	R8A77965_CLK_S0D2),
++	DEF_MOD("etheravb",		812,	R8A77965_CLK_S0D6),
++	DEF_MOD("imr1",			822,	R8A77965_CLK_S0D2),
++	DEF_MOD("imr0",			823,	R8A77965_CLK_S0D2),
++
++	DEF_MOD("gpio7",		905,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio6",		906,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio5",		907,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio4",		908,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio3",		909,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio2",		910,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio1",		911,	R8A77965_CLK_S3D4),
++	DEF_MOD("gpio0",		912,	R8A77965_CLK_S3D4),
++	DEF_MOD("can-fd",		914,	R8A77965_CLK_S3D2),
++	DEF_MOD("can-if1",		915,	R8A77965_CLK_S3D4),
++	DEF_MOD("can-if0",		916,	R8A77965_CLK_S3D4),
++	DEF_MOD("i2c6",			918,	R8A77965_CLK_S0D6),
++	DEF_MOD("i2c5",			919,	R8A77965_CLK_S0D6),
++	DEF_MOD("i2c-dvfs",		926,	R8A77965_CLK_CP),
++	DEF_MOD("i2c4",			927,	R8A77965_CLK_S0D6),
++	DEF_MOD("i2c3",			928,	R8A77965_CLK_S0D6),
++	DEF_MOD("i2c2",			929,	R8A77965_CLK_S3D2),
++	DEF_MOD("i2c1",			930,	R8A77965_CLK_S3D2),
++	DEF_MOD("i2c0",			931,	R8A77965_CLK_S3D2),
++
++	DEF_MOD("ssi-all",		1005,	R8A77965_CLK_S3D4),
++	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
++	DEF_MOD("scu-all",		1017,	R8A77965_CLK_S3D4),
++	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
++};
++
++static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
++};
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ *   MD		EXTAL		PLL0	PLL1	PLL3	PLL4
++ * 14 13 19 17	(MHz)
++ *-----------------------------------------------------------
++ * 0  0  0  0	16.66 x 1	x180	x192	x192	x144
++ * 0  0  0  1	16.66 x 1	x180	x192	x128	x144
++ * 0  0  1  0	Prohibited setting
++ * 0  0  1  1	16.66 x 1	x180	x192	x192	x144
++ * 0  1  0  0	20    x 1	x150	x160	x160	x120
++ * 0  1  0  1	20    x 1	x150	x160	x106	x120
++ * 0  1  1  0	Prohibited setting
++ * 0  1  1  1	20    x 1	x150	x160	x160	x120
++ * 1  0  0  0	25    x 1	x120	x128	x128	x96
++ * 1  0  0  1	25    x 1	x120	x128	x84	x96
++ * 1  0  1  0	Prohibited setting
++ * 1  0  1  1	25    x 1	x120	x128	x128	x96
++ * 1  1  0  0	33.33 / 2	x180	x192	x192	x144
++ * 1  1  0  1	33.33 / 2	x180	x192	x128	x144
++ * 1  1  1  0	Prohibited setting
++ * 1  1  1  1	33.33 / 2	x180	x192	x192	x144
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
++					 (((md) & BIT(13)) >> 11) | \
++					 (((md) & BIT(19)) >> 18) | \
++					 (((md) & BIT(17)) >> 17))
++
++static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
++	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
++	{ 1,		192,	1,	192,	1,	},
++	{ 1,		192,	1,	128,	1,	},
++	{ 0, /* Prohibited setting */			},
++	{ 1,		192,	1,	192,	1,	},
++	{ 1,		160,	1,	160,	1,	},
++	{ 1,		160,	1,	106,	1,	},
++	{ 0, /* Prohibited setting */			},
++	{ 1,		160,	1,	160,	1,	},
++	{ 1,		128,	1,	128,	1,	},
++	{ 1,		128,	1,	84,	1,	},
++	{ 0, /* Prohibited setting */			},
++	{ 1,		128,	1,	128,	1,	},
++	{ 2,		192,	1,	192,	1,	},
++	{ 2,		192,	1,	128,	1,	},
++	{ 0, /* Prohibited setting */			},
++	{ 2,		192,	1,	192,	1,	},
++};
++
++static int __init r8a77965_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++	if (!cpg_pll_config->extal_div) {
++		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
++		return -EINVAL;
++	}
++
++	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
++};
++
++const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks		= r8a77965_core_clks,
++	.num_core_clks		= ARRAY_SIZE(r8a77965_core_clks),
++	.last_dt_core_clk	= LAST_DT_CORE_CLK,
++	.num_total_core_clks	= MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks		= r8a77965_mod_clks,
++	.num_mod_clks		= ARRAY_SIZE(r8a77965_mod_clks),
++	.num_hw_mod_clks	= 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks		= r8a77965_crit_mod_clks,
++	.num_crit_mod_clks	= ARRAY_SIZE(r8a77965_crit_mod_clks),
++
++	/* Callbacks */
++	.init			= r8a77965_cpg_mssr_init,
++	.cpg_clk_register	= rcar_gen3_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index da5c3dacbab4..4f314c77bf48 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -694,6 +694,12 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a7796_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_CLK_R8A77965
++	{
++		.compatible = "renesas,r8a77965-cpg-mssr",
++		.data = &r8a77965_cpg_mssr_info,
++	},
++#endif
+ #ifdef CONFIG_CLK_R8A77970
+ 	{
+ 		.compatible = "renesas,r8a77970-cpg-mssr",
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index 143293e3d193..97ccb093c10f 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -139,6 +139,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
+new file mode 100644
+index 000000000000..6d3b5a9a6084
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
+@@ -0,0 +1,62 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a77965 CPG Core Clocks */
++#define R8A77965_CLK_Z			0
++#define R8A77965_CLK_ZR			1
++#define R8A77965_CLK_ZG			2
++#define R8A77965_CLK_ZTR		3
++#define R8A77965_CLK_ZTRD2		4
++#define R8A77965_CLK_ZT			5
++#define R8A77965_CLK_ZX			6
++#define R8A77965_CLK_S0D1		7
++#define R8A77965_CLK_S0D2		8
++#define R8A77965_CLK_S0D3		9
++#define R8A77965_CLK_S0D4		10
++#define R8A77965_CLK_S0D6		11
++#define R8A77965_CLK_S0D8		12
++#define R8A77965_CLK_S0D12		13
++#define R8A77965_CLK_S1D1		14
++#define R8A77965_CLK_S1D2		15
++#define R8A77965_CLK_S1D4		16
++#define R8A77965_CLK_S2D1		17
++#define R8A77965_CLK_S2D2		18
++#define R8A77965_CLK_S2D4		19
++#define R8A77965_CLK_S3D1		20
++#define R8A77965_CLK_S3D2		21
++#define R8A77965_CLK_S3D4		22
++#define R8A77965_CLK_LB			23
++#define R8A77965_CLK_CL			24
++#define R8A77965_CLK_ZB3		25
++#define R8A77965_CLK_ZB3D2		26
++#define R8A77965_CLK_CR			27
++#define R8A77965_CLK_CRD2		28
++#define R8A77965_CLK_SD0H		29
++#define R8A77965_CLK_SD0		30
++#define R8A77965_CLK_SD1H		31
++#define R8A77965_CLK_SD1		32
++#define R8A77965_CLK_SD2H		33
++#define R8A77965_CLK_SD2		34
++#define R8A77965_CLK_SD3H		35
++#define R8A77965_CLK_SD3		36
++#define R8A77965_CLK_SSP2		37
++#define R8A77965_CLK_SSP1		38
++#define R8A77965_CLK_SSPRS		39
++#define R8A77965_CLK_RPC		40
++#define R8A77965_CLK_RPCD2		41
++#define R8A77965_CLK_MSO		42
++#define R8A77965_CLK_CANFD		43
++#define R8A77965_CLK_HDMI		44
++#define R8A77965_CLK_CSI0		45
++#define R8A77965_CLK_CP			46
++#define R8A77965_CLK_CPEX		47
++#define R8A77965_CLK_R			48
++#define R8A77965_CLK_OSC		49
++
++#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1144-clk-renesas-r8a77965-Replace-DU2-clock.patch b/patches/1144-clk-renesas-r8a77965-Replace-DU2-clock.patch
new file mode 100644
index 00000000000000..284d612cb63822
--- /dev/null
+++ b/patches/1144-clk-renesas-r8a77965-Replace-DU2-clock.patch
@@ -0,0 +1,35 @@
+From d645564c36862c0e6f98228c22e88bc7b82d9916 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Tue, 13 Mar 2018 16:18:20 +0100
+Subject: [PATCH 1144/1795] clk: renesas: r8a77965: Replace DU2 clock
+
+R-Car M3-N does not have the DU2 unit but it has DU3 instead.
+Fix the module clock definition to reflect that.
+
+Fixes: 7ce36da900c0a2ff ("clk: renesas: cpg-mssr: Add support for R-Car M3-N")
+Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 1e04204eff99b520737315af882f7fb61a9443be)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+index 41e506ab557d..b1acfb60351c 100644
+--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+@@ -173,7 +173,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ 	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D4),
+ 	DEF_MOD("csi20",		714,	R8A77965_CLK_CSI0),
+ 	DEF_MOD("csi40",		716,	R8A77965_CLK_CSI0),
+-	DEF_MOD("du2",			722,	R8A77965_CLK_S2D1),
++	DEF_MOD("du3",			721,	R8A77965_CLK_S2D1),
+ 	DEF_MOD("du1",			723,	R8A77965_CLK_S2D1),
+ 	DEF_MOD("du0",			724,	R8A77965_CLK_S2D1),
+ 	DEF_MOD("lvds",			727,	R8A77965_CLK_S2D1),
+-- 
+2.19.0
+
diff --git a/patches/1145-clk-renesas-div6-Always-use-readl-writel.patch b/patches/1145-clk-renesas-div6-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..0333fdffbb97a5
--- /dev/null
+++ b/patches/1145-clk-renesas-div6-Always-use-readl-writel.patch
@@ -0,0 +1,105 @@
+From ab25203ce44f8cd92412dd798cfb334a66eeb505 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:43:12 +0100
+Subject: [PATCH 1145/1795] clk: renesas: div6: Always use readl()/writel()
+
+On arm32/arm64, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c733c7d9374191cac6668ce6ea074909d036d8f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-div6.c | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
+index 151336d2ba59..9febbf42c3df 100644
+--- a/drivers/clk/renesas/clk-div6.c
++++ b/drivers/clk/renesas/clk-div6.c
+@@ -53,9 +53,9 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
+ 	struct div6_clock *clock = to_div6_clock(hw);
+ 	u32 val;
+ 
+-	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
++	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
+ 	    | CPG_DIV6_DIV(clock->div - 1);
+-	clk_writel(val, clock->reg);
++	writel(val, clock->reg);
+ 
+ 	return 0;
+ }
+@@ -65,7 +65,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
+ 	struct div6_clock *clock = to_div6_clock(hw);
+ 	u32 val;
+ 
+-	val = clk_readl(clock->reg);
++	val = readl(clock->reg);
+ 	val |= CPG_DIV6_CKSTP;
+ 	/*
+ 	 * DIV6 clocks require the divisor field to be non-zero when stopping
+@@ -75,14 +75,14 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
+ 	 */
+ 	if (!(val & CPG_DIV6_DIV_MASK))
+ 		val |= CPG_DIV6_DIV_MASK;
+-	clk_writel(val, clock->reg);
++	writel(val, clock->reg);
+ }
+ 
+ static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
+ {
+ 	struct div6_clock *clock = to_div6_clock(hw);
+ 
+-	return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
++	return !(readl(clock->reg) & CPG_DIV6_CKSTP);
+ }
+ 
+ static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
+@@ -122,10 +122,10 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
+ 
+ 	clock->div = div;
+ 
+-	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
++	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
+ 	/* Only program the new divisor if the clock isn't stopped. */
+ 	if (!(val & CPG_DIV6_CKSTP))
+-		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
++		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
+ 
+ 	return 0;
+ }
+@@ -139,7 +139,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
+ 	if (clock->src_width == 0)
+ 		return 0;
+ 
+-	hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
++	hw_index = (readl(clock->reg) >> clock->src_shift) &
+ 		   (BIT(clock->src_width) - 1);
+ 	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ 		if (clock->parents[i] == hw_index)
+@@ -163,8 +163,8 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
+ 	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
+ 	hw_index = clock->parents[index];
+ 
+-	clk_writel((clk_readl(clock->reg) & mask) |
+-		(hw_index << clock->src_shift), clock->reg);
++	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
++	       clock->reg);
+ 
+ 	return 0;
+ }
+@@ -241,7 +241,7 @@ struct clk * __init cpg_div6_register(const char *name,
+ 	 * Read the divisor. Disabling the clock overwrites the divisor, so we
+ 	 * need to cache its value for the enable operation.
+ 	 */
+-	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
++	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
+ 
+ 	switch (num_parents) {
+ 	case 1:
+-- 
+2.19.0
+
diff --git a/patches/1146-clk-renesas-mstp-Always-use-readl-writel.patch b/patches/1146-clk-renesas-mstp-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..b1da4c4effd199
--- /dev/null
+++ b/patches/1146-clk-renesas-mstp-Always-use-readl-writel.patch
@@ -0,0 +1,41 @@
+From b9a36e0459de83c5c3d790f7c6e9605f4fa92244 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:43:37 +0100
+Subject: [PATCH 1146/1795] clk: renesas: mstp: Always use readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8027519840653520c256cb5e7768b60af3bc895e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-mstp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
+index 858c24d4da8f..e82adcb16a52 100644
+--- a/drivers/clk/renesas/clk-mstp.c
++++ b/drivers/clk/renesas/clk-mstp.c
+@@ -64,13 +64,13 @@ struct mstp_clock {
+ static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
+ 				u32 __iomem *reg)
+ {
+-	return group->width_8bit ? readb(reg) : clk_readl(reg);
++	return group->width_8bit ? readb(reg) : readl(reg);
+ }
+ 
+ static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
+ 				  u32 __iomem *reg)
+ {
+-	group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
++	group->width_8bit ? writeb(val, reg) : writel(val, reg);
+ }
+ 
+ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
+-- 
+2.19.0
+
diff --git a/patches/1147-clk-renesas-r8a73a4-Always-use-readl-writel.patch b/patches/1147-clk-renesas-r8a73a4-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..ec820ec41c609f
--- /dev/null
+++ b/patches/1147-clk-renesas-r8a73a4-Always-use-readl-writel.patch
@@ -0,0 +1,70 @@
+From 6fc1a00cad9bba2e6f8a15bb9025d95b174f04b4 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:43:47 +0100
+Subject: [PATCH 1147/1795] clk: renesas: r8a73a4: Always use readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b86b493eb29120b82ba919e2653c863c0b3804d6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-r8a73a4.c | 11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c
+index 28d204bb659e..7b903ce4c901 100644
+--- a/drivers/clk/renesas/clk-r8a73a4.c
++++ b/drivers/clk/renesas/clk-r8a73a4.c
+@@ -71,7 +71,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
+ 
+ 
+ 	if (!strcmp(name, "main")) {
+-		u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR);
++		u32 ckscr = readl(cpg->reg + CPG_CKSCR);
+ 
+ 		switch ((ckscr >> 28) & 3) {
+ 		case 0:	/* extal1 */
+@@ -95,14 +95,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
+ 		 * clock implementation and we currently have no need to change
+ 		 * the multiplier value.
+ 		 */
+-		u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
++		u32 value = readl(cpg->reg + CPG_PLL0CR);
+ 
+ 		parent_name = "main";
+ 		mult = ((value >> 24) & 0x7f) + 1;
+ 		if (value & BIT(20))
+ 			div = 2;
+ 	} else if (!strcmp(name, "pll1")) {
+-		u32 value = clk_readl(cpg->reg + CPG_PLL1CR);
++		u32 value = readl(cpg->reg + CPG_PLL1CR);
+ 
+ 		parent_name = "main";
+ 		/* XXX: enable bit? */
+@@ -125,7 +125,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
+ 		default:
+ 			return ERR_PTR(-EINVAL);
+ 		}
+-		value = clk_readl(cpg->reg + cr);
++		value = readl(cpg->reg + cr);
+ 		switch ((value >> 5) & 7) {
+ 		case 0:
+ 			parent_name = "main";
+@@ -161,8 +161,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
+ 			shift = 0;
+ 		}
+ 		div *= 32;
+-		mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift)
+-		       & 0x1f);
++		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
+ 	} else {
+ 		struct div4_clk *c;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1148-clk-renesas-r8a7740-Always-use-readl-writel.patch b/patches/1148-clk-renesas-r8a7740-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..1c2f365f2cdb21
--- /dev/null
+++ b/patches/1148-clk-renesas-r8a7740-Always-use-readl-writel.patch
@@ -0,0 +1,50 @@
+From 0fb25b82a4cd86f1423e8665ec3413dbaace3a7d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:43:57 +0100
+Subject: [PATCH 1148/1795] clk: renesas: r8a7740: Always use readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f32b0696eabd7a9dc6efd6a97448742d5f2a7db0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-r8a7740.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
+index 2f7ce6696b6c..d074f8e982d0 100644
+--- a/drivers/clk/renesas/clk-r8a7740.c
++++ b/drivers/clk/renesas/clk-r8a7740.c
+@@ -98,20 +98,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
+ 		 * clock implementation and we currently have no need to change
+ 		 * the multiplier value.
+ 		 */
+-		u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
++		u32 value = readl(cpg->reg + CPG_FRQCRC);
+ 		parent_name = "system";
+ 		mult = ((value >> 24) & 0x7f) + 1;
+ 	} else if (!strcmp(name, "pllc1")) {
+-		u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
++		u32 value = readl(cpg->reg + CPG_FRQCRA);
+ 		parent_name = "system";
+ 		mult = ((value >> 24) & 0x7f) + 1;
+ 		div = 2;
+ 	} else if (!strcmp(name, "pllc2")) {
+-		u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
++		u32 value = readl(cpg->reg + CPG_PLLC2CR);
+ 		parent_name = "system";
+ 		mult = ((value >> 24) & 0x3f) + 1;
+ 	} else if (!strcmp(name, "usb24s")) {
+-		u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
++		u32 value = readl(cpg->reg + CPG_USBCKCR);
+ 		if (value & BIT(7))
+ 			/* extal2 */
+ 			parent_name = of_clk_get_parent_name(np, 1);
+-- 
+2.19.0
+
diff --git a/patches/1149-clk-renesas-rcar-gen2-Always-use-readl-writel.patch b/patches/1149-clk-renesas-rcar-gen2-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..0dfe3e101e1cfb
--- /dev/null
+++ b/patches/1149-clk-renesas-rcar-gen2-Always-use-readl-writel.patch
@@ -0,0 +1,81 @@
+From 4c49f8700944401ce4fe810a2f168f5fc51e8aa2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:44:09 +0100
+Subject: [PATCH 1149/1795] clk: renesas: rcar-gen2: Always use
+ readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6c669e504a62641fd7189df13ef57d182373e36f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-rcar-gen2.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
+index d14cbe1ca29a..ee32a022e6da 100644
+--- a/drivers/clk/renesas/clk-rcar-gen2.c
++++ b/drivers/clk/renesas/clk-rcar-gen2.c
+@@ -62,8 +62,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+ 	unsigned int mult;
+ 	unsigned int val;
+ 
+-	val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
+-	    >> CPG_FRQCRC_ZFC_SHIFT;
++	val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
+ 	mult = 32 - val;
+ 
+ 	return div_u64((u64)parent_rate * mult, 32);
+@@ -95,21 +94,21 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	mult = div_u64((u64)rate * 32, parent_rate);
+ 	mult = clamp(mult, 1U, 32U);
+ 
+-	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
++	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+ 		return -EBUSY;
+ 
+-	val = clk_readl(zclk->reg);
++	val = readl(zclk->reg);
+ 	val &= ~CPG_FRQCRC_ZFC_MASK;
+ 	val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
+-	clk_writel(val, zclk->reg);
++	writel(val, zclk->reg);
+ 
+ 	/*
+ 	 * Set KICK bit in FRQCRB to update hardware setting and wait for
+ 	 * clock change completion.
+ 	 */
+-	kick = clk_readl(zclk->kick_reg);
++	kick = readl(zclk->kick_reg);
+ 	kick |= CPG_FRQCRB_KICK;
+-	clk_writel(kick, zclk->kick_reg);
++	writel(kick, zclk->kick_reg);
+ 
+ 	/*
+ 	 * Note: There is no HW information about the worst case latency.
+@@ -121,7 +120,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	 * "super" safe value.
+ 	 */
+ 	for (i = 1000; i; i--) {
+-		if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
++		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+ 			return 0;
+ 
+ 		cpu_relax();
+@@ -332,7 +331,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
+ 			mult = config->pll0_mult;
+ 			div = 3;
+ 		} else {
+-			u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
++			u32 value = readl(cpg->reg + CPG_PLL0CR);
+ 			mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
+ 		}
+ 		parent_name = "main";
+-- 
+2.19.0
+
diff --git a/patches/1150-clk-renesas-rza1-Always-use-readl-writel.patch b/patches/1150-clk-renesas-rza1-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..100830f1fb698a
--- /dev/null
+++ b/patches/1150-clk-renesas-rza1-Always-use-readl-writel.patch
@@ -0,0 +1,37 @@
+From ec43f2148ad8c4d624da7558d6e32dfdf37d714f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:44:19 +0100
+Subject: [PATCH 1150/1795] clk: renesas: rza1: Always use readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fcf371b3517771589819ffefe2aa16b31f0b0a63)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-rz.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
+index 127c58135c8f..67dd712aa723 100644
+--- a/drivers/clk/renesas/clk-rz.c
++++ b/drivers/clk/renesas/clk-rz.c
+@@ -75,9 +75,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
+ 	 * let them run at fixed current speed and implement the details later.
+ 	 */
+ 	if (strcmp(name, "i") == 0)
+-		val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
++		val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
+ 	else if (strcmp(name, "g") == 0)
+-		val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
++		val = readl(cpg->reg + CPG_FRQCR2) & 3;
+ 	else
+ 		return ERR_PTR(-EINVAL);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1151-clk-renesas-sh73a0-Always-use-readl-writel.patch b/patches/1151-clk-renesas-sh73a0-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..aea84c5dd056f6
--- /dev/null
+++ b/patches/1151-clk-renesas-sh73a0-Always-use-readl-writel.patch
@@ -0,0 +1,62 @@
+From 72bcdca587ebafc584aa786668e161b255f21d52 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:44:30 +0100
+Subject: [PATCH 1151/1795] clk: renesas: sh73a0: Always use readl()/writel()
+
+On arm32, there is no reason to use the (soon deprecated)
+clk_readl()/clk_writel().  Hence use the generic readl()/writel()
+instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f046d6a6bf2a1f0db5e2f61b5236efb1b6bebfde)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/clk-sh73a0.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
+index 3892346c4fcc..bab33610eb6c 100644
+--- a/drivers/clk/renesas/clk-sh73a0.c
++++ b/drivers/clk/renesas/clk-sh73a0.c
+@@ -85,7 +85,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
+ 
+ 	if (!strcmp(name, "main")) {
+ 		/* extal1, extal1_div2, extal2, extal2_div2 */
+-		u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
++		u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
+ 
+ 		parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
+ 		div = (parent_idx & 1) + 1;
+@@ -110,11 +110,11 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
+ 		default:
+ 			return ERR_PTR(-EINVAL);
+ 		}
+-		if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
+-			mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
++		if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
++			mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
+ 			/* handle CFG bit for PLL1 and PLL2 */
+ 			if (enable_bit == 1 || enable_bit == 2)
+-				if (clk_readl(enable_reg) & BIT(20))
++				if (readl(enable_reg) & BIT(20))
+ 					mult *= 2;
+ 		}
+ 	} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
+@@ -193,9 +193,9 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
+ 		return;
+ 
+ 	/* Set SDHI clocks to a known state */
+-	clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
+-	clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
+-	clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
++	writel(0x108, cpg->reg + CPG_SD0CKCR);
++	writel(0x108, cpg->reg + CPG_SD1CKCR);
++	writel(0x108, cpg->reg + CPG_SD2CKCR);
+ 
+ 	for (i = 0; i < num_clks; ++i) {
+ 		const char *name;
+-- 
+2.19.0
+
diff --git a/patches/1152-clk-renesas-rcar-gen3-Always-use-readl-writel.patch b/patches/1152-clk-renesas-rcar-gen3-Always-use-readl-writel.patch
new file mode 100644
index 00000000000000..59e0d29c8c122e
--- /dev/null
+++ b/patches/1152-clk-renesas-rcar-gen3-Always-use-readl-writel.patch
@@ -0,0 +1,73 @@
+From 1b712309410d4999d140db087c38188f497fabd8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 15 Mar 2018 10:44:37 +0100
+Subject: [PATCH 1152/1795] clk: renesas: rcar-gen3: Always use
+ readl()/writel()
+
+The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
+clk_readl()/clk_writel() and readl()/writel() to access the clock
+registers. Settle on the generic readl()/writel().
+
+Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
+readl()/writel()").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2b935d524d851830b68dd8c58d3098d775d6047a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen3-cpg.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index 0c8fe10d57fe..628b63b85d3f 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -93,7 +93,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+ 	unsigned int mult;
+ 	u32 val;
+ 
+-	val = clk_readl(zclk->reg) & zclk->mask;
++	val = readl(zclk->reg) & zclk->mask;
+ 	mult = 32 - (val >> __ffs(zclk->mask));
+ 
+ 	/* Factor of 2 is for fixed divider */
+@@ -125,20 +125,20 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
+ 	mult = clamp(mult, 1U, 32U);
+ 
+-	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
++	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+ 		return -EBUSY;
+ 
+-	val = clk_readl(zclk->reg) & ~zclk->mask;
++	val = readl(zclk->reg) & ~zclk->mask;
+ 	val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
+-	clk_writel(val, zclk->reg);
++	writel(val, zclk->reg);
+ 
+ 	/*
+ 	 * Set KICK bit in FRQCRB to update hardware setting and wait for
+ 	 * clock change completion.
+ 	 */
+-	kick = clk_readl(zclk->kick_reg);
++	kick = readl(zclk->kick_reg);
+ 	kick |= CPG_FRQCRB_KICK;
+-	clk_writel(kick, zclk->kick_reg);
++	writel(kick, zclk->kick_reg);
+ 
+ 	/*
+ 	 * Note: There is no HW information about the worst case latency.
+@@ -150,7 +150,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ 	 * "super" safe value.
+ 	 */
+ 	for (i = 1000; i; i--) {
+-		if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
++		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+ 			return 0;
+ 
+ 		cpu_relax();
+-- 
+2.19.0
+
diff --git a/patches/1153-clk-renesas-cpg-mssr-Adjust-r8a77980-ifdef.patch b/patches/1153-clk-renesas-cpg-mssr-Adjust-r8a77980-ifdef.patch
new file mode 100644
index 00000000000000..062e5b254f7019
--- /dev/null
+++ b/patches/1153-clk-renesas-cpg-mssr-Adjust-r8a77980-ifdef.patch
@@ -0,0 +1,34 @@
+From fcd5d3e7ba5454f86d2b5eb89cdcfce772459b3d Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 20 Mar 2018 16:40:16 +0900
+Subject: [PATCH 1153/1795] clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
+
+Adjust the R8A77980-specific #ifdefs to use CLK instead of ARCH
+to follow same style as other SoCs.
+
+Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support")
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 472f5f391819b4b22ec040f227aea26f515b6ae2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/renesas-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 4f314c77bf48..69a7c756658b 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -706,7 +706,7 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a77970_cpg_mssr_info,
+ 	},
+ #endif
+-#ifdef CONFIG_ARCH_R8A77980
++#ifdef CONFIG_CLK_R8A77980
+ 	{
+ 		.compatible = "renesas,r8a77980-cpg-mssr",
+ 		.data = &r8a77980_cpg_mssr_info,
+-- 
+2.19.0
+
diff --git a/patches/1154-drivers-base-Unified-device-connection-lookup.patch b/patches/1154-drivers-base-Unified-device-connection-lookup.patch
new file mode 100644
index 00000000000000..43059c3650547d
--- /dev/null
+++ b/patches/1154-drivers-base-Unified-device-connection-lookup.patch
@@ -0,0 +1,273 @@
+From 31716fd2785d75b97580bdcd328322c27833f84f Mon Sep 17 00:00:00 2001
+From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Date: Tue, 20 Mar 2018 15:57:02 +0300
+Subject: [PATCH 1154/1795] drivers: base: Unified device connection lookup
+
+Several frameworks - clk, gpio, phy, pmw, etc. - maintain
+lookup tables for describing connections and provide custom
+API for handling them. This introduces a single generic
+lookup table and API for the connections.
+
+The motivation for this commit is centralizing the
+connection lookup, but the goal is to ultimately extract the
+connection descriptions also from firmware by using the
+fwnode_graph_* functions and other mechanisms that are
+available.
+
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit f2d9b66d84f3ff5ea3aff111e6a403e04fa8bf37)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../driver-api/device_connection.rst          |  43 ++++++
+ drivers/base/Makefile                         |   3 +-
+ drivers/base/devcon.c                         | 136 ++++++++++++++++++
+ include/linux/device.h                        |  22 +++
+ 4 files changed, 203 insertions(+), 1 deletion(-)
+ create mode 100644 Documentation/driver-api/device_connection.rst
+ create mode 100644 drivers/base/devcon.c
+
+diff --git a/Documentation/driver-api/device_connection.rst b/Documentation/driver-api/device_connection.rst
+new file mode 100644
+index 000000000000..affbc5566ab0
+--- /dev/null
++++ b/Documentation/driver-api/device_connection.rst
+@@ -0,0 +1,43 @@
++==================
++Device connections
++==================
++
++Introduction
++------------
++
++Devices often have connections to other devices that are outside of the direct
++child/parent relationship. A serial or network communication controller, which
++could be a PCI device, may need to be able to get a reference to its PHY
++component, which could be attached for example to the I2C bus. Some device
++drivers need to be able to control the clocks or the GPIOs for their devices,
++and so on.
++
++Device connections are generic descriptions of any type of connection between
++two separate devices.
++
++Device connections alone do not create a dependency between the two devices.
++They are only descriptions which are not tied to either of the devices directly.
++A dependency between the two devices exists only if one of the two endpoint
++devices requests a reference to the other. The descriptions themselves can be
++defined in firmware (not yet supported) or they can be built-in.
++
++Usage
++-----
++
++Device connections should exist before device ``->probe`` callback is called for
++either endpoint device in the description. If the connections are defined in
++firmware, this is not a problem. It should be considered if the connection
++descriptions are "built-in", and need to be added separately.
++
++The connection description consists of the names of the two devices with the
++connection, i.e. the endpoints, and unique identifier for the connection which
++is needed if there are multiple connections between the two devices.
++
++After a description exists, the devices in it can request reference to the other
++endpoint device, or they can request the description itself.
++
++API
++---
++
++.. kernel-doc:: drivers/base/devcon.c
++   : functions: device_connection_find_match device_connection_find device_connection_add device_connection_remove
+diff --git a/drivers/base/Makefile b/drivers/base/Makefile
+index e32a52490051..12a7f64d35a9 100644
+--- a/drivers/base/Makefile
++++ b/drivers/base/Makefile
+@@ -5,7 +5,8 @@ obj-y			:= component.o core.o bus.o dd.o syscore.o \
+ 			   driver.o class.o platform.o \
+ 			   cpu.o firmware.o init.o map.o devres.o \
+ 			   attribute_container.o transport_class.o \
+-			   topology.o container.o property.o cacheinfo.o
++			   topology.o container.o property.o cacheinfo.o \
++			   devcon.o
+ obj-$(CONFIG_DEVTMPFS)	+= devtmpfs.o
+ obj-$(CONFIG_DMA_CMA) += dma-contiguous.o
+ obj-y			+= power/
+diff --git a/drivers/base/devcon.c b/drivers/base/devcon.c
+new file mode 100644
+index 000000000000..d427e806cd73
+--- /dev/null
++++ b/drivers/base/devcon.c
+@@ -0,0 +1,136 @@
++// SPDX-License-Identifier: GPL-2.0
++/**
++ * Device connections
++ *
++ * Copyright (C) 2018 Intel Corporation
++ * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
++ */
++
++#include <linux/device.h>
++
++static DEFINE_MUTEX(devcon_lock);
++static LIST_HEAD(devcon_list);
++
++/**
++ * device_connection_find_match - Find physical connection to a device
++ * @dev: Device with the connection
++ * @con_id: Identifier for the connection
++ * @data: Data for the match function
++ * @match: Function to check and convert the connection description
++ *
++ * Find a connection with unique identifier @con_id between @dev and another
++ * device. @match will be used to convert the connection description to data the
++ * caller is expecting to be returned.
++ */
++void *device_connection_find_match(struct device *dev, const char *con_id,
++			       void *data,
++			       void *(*match)(struct device_connection *con,
++					      int ep, void *data))
++{
++	const char *devname = dev_name(dev);
++	struct device_connection *con;
++	void *ret = NULL;
++	int ep;
++
++	if (!match)
++		return NULL;
++
++	mutex_lock(&devcon_lock);
++
++	list_for_each_entry(con, &devcon_list, list) {
++		ep = match_string(con->endpoint, 2, devname);
++		if (ep < 0)
++			continue;
++
++		if (con_id && strcmp(con->id, con_id))
++			continue;
++
++		ret = match(con, !ep, data);
++		if (ret)
++			break;
++	}
++
++	mutex_unlock(&devcon_lock);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(device_connection_find_match);
++
++extern struct bus_type platform_bus_type;
++extern struct bus_type pci_bus_type;
++extern struct bus_type i2c_bus_type;
++extern struct bus_type spi_bus_type;
++
++static struct bus_type *generic_match_buses[] = {
++	&platform_bus_type,
++#ifdef CONFIG_PCI
++	&pci_bus_type,
++#endif
++#ifdef CONFIG_I2C
++	&i2c_bus_type,
++#endif
++#ifdef CONFIG_SPI_MASTER
++	&spi_bus_type,
++#endif
++	NULL,
++};
++
++/* This tries to find the device from the most common bus types by name. */
++static void *generic_match(struct device_connection *con, int ep, void *data)
++{
++	struct bus_type *bus;
++	struct device *dev;
++
++	for (bus = generic_match_buses[0]; bus; bus++) {
++		dev = bus_find_device_by_name(bus, NULL, con->endpoint[ep]);
++		if (dev)
++			return dev;
++	}
++
++	/*
++	 * We only get called if a connection was found, tell the caller to
++	 * wait for the other device to show up.
++	 */
++	return ERR_PTR(-EPROBE_DEFER);
++}
++
++/**
++ * device_connection_find - Find two devices connected together
++ * @dev: Device with the connection
++ * @con_id: Identifier for the connection
++ *
++ * Find a connection with unique identifier @con_id between @dev and
++ * another device. On success returns handle to the device that is connected
++ * to @dev, with the reference count for the found device incremented. Returns
++ * NULL if no matching connection was found, or ERR_PTR(-EPROBE_DEFER) when a
++ * connection was found but the other device has not been enumerated yet.
++ */
++struct device *device_connection_find(struct device *dev, const char *con_id)
++{
++	return device_connection_find_match(dev, con_id, NULL, generic_match);
++}
++EXPORT_SYMBOL_GPL(device_connection_find);
++
++/**
++ * device_connection_add - Register a connection description
++ * @con: The connection description to be registered
++ */
++void device_connection_add(struct device_connection *con)
++{
++	mutex_lock(&devcon_lock);
++	list_add_tail(&con->list, &devcon_list);
++	mutex_unlock(&devcon_lock);
++}
++EXPORT_SYMBOL_GPL(device_connection_add);
++
++/**
++ * device_connections_remove - Unregister connection description
++ * @con: The connection description to be unregistered
++ */
++void device_connection_remove(struct device_connection *con)
++{
++	mutex_lock(&devcon_lock);
++	list_del(&con->list);
++	mutex_unlock(&devcon_lock);
++}
++EXPORT_SYMBOL_GPL(device_connection_remove);
+diff --git a/include/linux/device.h b/include/linux/device.h
+index 66fe271c2544..f23208176c84 100644
+--- a/include/linux/device.h
++++ b/include/linux/device.h
+@@ -728,6 +728,28 @@ struct device_dma_parameters {
+ 	unsigned long segment_boundary_mask;
+ };
+ 
++/**
++ * struct device_connection - Device Connection Descriptor
++ * @endpoint: The names of the two devices connected together
++ * @id: Unique identifier for the connection
++ * @list: List head, private, for internal use only
++ */
++struct device_connection {
++	const char		*endpoint[2];
++	const char		*id;
++	struct list_head	list;
++};
++
++void *device_connection_find_match(struct device *dev, const char *con_id,
++				void *data,
++				void *(*match)(struct device_connection *con,
++					       int ep, void *data));
++
++struct device *device_connection_find(struct device *dev, const char *con_id);
++
++void device_connection_add(struct device_connection *con);
++void device_connection_remove(struct device_connection *con);
++
+ /**
+  * enum device_link_state - Device link states.
+  * @DL_STATE_NONE: The presence of the drivers is not being tracked.
+-- 
+2.19.0
+
diff --git a/patches/1155-usb-common-Small-class-for-USB-role-switches.patch b/patches/1155-usb-common-Small-class-for-USB-role-switches.patch
new file mode 100644
index 00000000000000..ae40b59a64ddee
--- /dev/null
+++ b/patches/1155-usb-common-Small-class-for-USB-role-switches.patch
@@ -0,0 +1,462 @@
+From df16a173f3ee1e799d7ab41d870f0c87c2568218 Mon Sep 17 00:00:00 2001
+From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Date: Tue, 20 Mar 2018 15:57:04 +0300
+Subject: [PATCH 1155/1795] usb: common: Small class for USB role switches
+
+USB role switch is a device that can be used to choose the
+data role for USB connector. With dual-role capable USB
+controllers, the controller itself will be the switch, but
+on some platforms the USB host and device controllers are
+separate IPs and there is a mux between them and the
+connector. On those platforms the mux driver will need to
+register the switch.
+
+With USB Type-C connectors, the host-to-device relationship
+is negotiated over the Configuration Channel (CC). That
+means the USB Type-C drivers need to be in control of the
+role switch. The class provides a simple API for the USB
+Type-C drivers for the control.
+
+For other types of USB connectors (mainly microAB) the class
+provides user space control via sysfs attribute file that
+can be used to request role swapping from the switch.
+
+Reviewed-by: Hans de Goede <hdegoede@redhat.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fde0aa6c175a4d8aa19e82b86ae0f9278bc8563b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-class-usb_role          |  21 ++
+ drivers/usb/Kconfig                           |   3 +
+ drivers/usb/common/Makefile                   |   1 +
+ drivers/usb/common/roles.c                    | 305 ++++++++++++++++++
+ include/linux/usb/role.h                      |  53 +++
+ 5 files changed, 383 insertions(+)
+ create mode 100644 Documentation/ABI/testing/sysfs-class-usb_role
+ create mode 100644 drivers/usb/common/roles.c
+ create mode 100644 include/linux/usb/role.h
+
+diff --git a/Documentation/ABI/testing/sysfs-class-usb_role b/Documentation/ABI/testing/sysfs-class-usb_role
+new file mode 100644
+index 000000000000..3b810a425a52
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-class-usb_role
+@@ -0,0 +1,21 @@
++What:		/sys/class/usb_role/
++Date:		Jan 2018
++Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
++Description:
++		Place in sysfs for USB Role Switches. USB Role Switch is a
++		device that can select the data role (host or device) for USB
++		port.
++
++What:		/sys/class/usb_role/<switch>/role
++Date:		Jan 2018
++Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
++Description:
++		The current role of the switch. This attribute can be used for
++		requesting role swapping with non-USB Type-C ports. With USB
++		Type-C ports, the ABI defined for USB Type-C connector class
++		must be used.
++
++		Valid values:
++		- none
++		- host
++		- device
+diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
+index 72eb3e41e3b6..d7ac6151d5b1 100644
+--- a/drivers/usb/Kconfig
++++ b/drivers/usb/Kconfig
+@@ -204,4 +204,7 @@ config USB_ULPI_BUS
+ 	  To compile this driver as a module, choose M here: the module will
+ 	  be called ulpi.
+ 
++config USB_ROLE_SWITCH
++	tristate
++
+ endif # USB_SUPPORT
+diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
+index 0a7c45e85481..fb4d5ef4165c 100644
+--- a/drivers/usb/common/Makefile
++++ b/drivers/usb/common/Makefile
+@@ -9,3 +9,4 @@ usb-common-$(CONFIG_USB_LED_TRIG) += led.o
+ 
+ obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+ obj-$(CONFIG_USB_ULPI_BUS)	+= ulpi.o
++obj-$(CONFIG_USB_ROLE_SWITCH)	+= roles.o
+diff --git a/drivers/usb/common/roles.c b/drivers/usb/common/roles.c
+new file mode 100644
+index 000000000000..15cc76e22123
+--- /dev/null
++++ b/drivers/usb/common/roles.c
+@@ -0,0 +1,305 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * USB Role Switch Support
++ *
++ * Copyright (C) 2018 Intel Corporation
++ * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
++ *         Hans de Goede <hdegoede@redhat.com>
++ */
++
++#include <linux/usb/role.h>
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++
++static struct class *role_class;
++
++struct usb_role_switch {
++	struct device dev;
++	struct mutex lock; /* device lock*/
++	enum usb_role role;
++
++	/* From descriptor */
++	struct device *usb2_port;
++	struct device *usb3_port;
++	struct device *udc;
++	usb_role_switch_set_t set;
++	usb_role_switch_get_t get;
++	bool allow_userspace_control;
++};
++
++#define to_role_switch(d)	container_of(d, struct usb_role_switch, dev)
++
++/**
++ * usb_role_switch_set_role - Set USB role for a switch
++ * @sw: USB role switch
++ * @role: USB role to be switched to
++ *
++ * Set USB role @role for @sw.
++ */
++int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role)
++{
++	int ret;
++
++	if (IS_ERR_OR_NULL(sw))
++		return 0;
++
++	mutex_lock(&sw->lock);
++
++	ret = sw->set(sw->dev.parent, role);
++	if (!ret)
++		sw->role = role;
++
++	mutex_unlock(&sw->lock);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_set_role);
++
++/**
++ * usb_role_switch_get_role - Get the USB role for a switch
++ * @sw: USB role switch
++ *
++ * Depending on the role-switch-driver this function returns either a cached
++ * value of the last set role, or reads back the actual value from the hardware.
++ */
++enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw)
++{
++	enum usb_role role;
++
++	if (IS_ERR_OR_NULL(sw))
++		return USB_ROLE_NONE;
++
++	mutex_lock(&sw->lock);
++
++	if (sw->get)
++		role = sw->get(sw->dev.parent);
++	else
++		role = sw->role;
++
++	mutex_unlock(&sw->lock);
++
++	return role;
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_get_role);
++
++static int __switch_match(struct device *dev, const void *name)
++{
++	return !strcmp((const char *)name, dev_name(dev));
++}
++
++static void *usb_role_switch_match(struct device_connection *con, int ep,
++				   void *data)
++{
++	struct device *dev;
++
++	dev = class_find_device(role_class, NULL, con->endpoint[ep],
++				__switch_match);
++
++	return dev ? to_role_switch(dev) : ERR_PTR(-EPROBE_DEFER);
++}
++
++/**
++ * usb_role_switch_get - Find USB role switch linked with the caller
++ * @dev: The caller device
++ *
++ * Finds and returns role switch linked with @dev. The reference count for the
++ * found switch is incremented.
++ */
++struct usb_role_switch *usb_role_switch_get(struct device *dev)
++{
++	return device_connection_find_match(dev, "usb-role-switch", NULL,
++					    usb_role_switch_match);
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_get);
++
++/**
++ * usb_role_switch_put - Release handle to a switch
++ * @sw: USB Role Switch
++ *
++ * Decrement reference count for @sw.
++ */
++void usb_role_switch_put(struct usb_role_switch *sw)
++{
++	if (!IS_ERR_OR_NULL(sw))
++		put_device(&sw->dev);
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_put);
++
++static umode_t
++usb_role_switch_is_visible(struct kobject *kobj, struct attribute *attr, int n)
++{
++	struct device *dev = container_of(kobj, typeof(*dev), kobj);
++	struct usb_role_switch *sw = to_role_switch(dev);
++
++	if (sw->allow_userspace_control)
++		return attr->mode;
++
++	return 0;
++}
++
++static const char * const usb_roles[] = {
++	[USB_ROLE_NONE]		= "none",
++	[USB_ROLE_HOST]		= "host",
++	[USB_ROLE_DEVICE]	= "device",
++};
++
++static ssize_t
++role_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct usb_role_switch *sw = to_role_switch(dev);
++	enum usb_role role = usb_role_switch_get_role(sw);
++
++	return sprintf(buf, "%s\n", usb_roles[role]);
++}
++
++static ssize_t role_store(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t size)
++{
++	struct usb_role_switch *sw = to_role_switch(dev);
++	int ret;
++
++	ret = sysfs_match_string(usb_roles, buf);
++	if (ret < 0) {
++		bool res;
++
++		/* Extra check if the user wants to disable the switch */
++		ret = kstrtobool(buf, &res);
++		if (ret || res)
++			return -EINVAL;
++	}
++
++	ret = usb_role_switch_set_role(sw, ret);
++	if (ret)
++		return ret;
++
++	return size;
++}
++static DEVICE_ATTR_RW(role);
++
++static struct attribute *usb_role_switch_attrs[] = {
++	&dev_attr_role.attr,
++	NULL,
++};
++
++static const struct attribute_group usb_role_switch_group = {
++	.is_visible = usb_role_switch_is_visible,
++	.attrs = usb_role_switch_attrs,
++};
++
++static const struct attribute_group *usb_role_switch_groups[] = {
++	&usb_role_switch_group,
++	NULL,
++};
++
++static int
++usb_role_switch_uevent(struct device *dev, struct kobj_uevent_env *env)
++{
++	int ret;
++
++	ret = add_uevent_var(env, "USB_ROLE_SWITCH=%s", dev_name(dev));
++	if (ret)
++		dev_err(dev, "failed to add uevent USB_ROLE_SWITCH\n");
++
++	return ret;
++}
++
++static void usb_role_switch_release(struct device *dev)
++{
++	struct usb_role_switch *sw = to_role_switch(dev);
++
++	kfree(sw);
++}
++
++static const struct device_type usb_role_dev_type = {
++	.name = "usb_role_switch",
++	.groups = usb_role_switch_groups,
++	.uevent = usb_role_switch_uevent,
++	.release = usb_role_switch_release,
++};
++
++/**
++ * usb_role_switch_register - Register USB Role Switch
++ * @parent: Parent device for the switch
++ * @desc: Description of the switch
++ *
++ * USB Role Switch is a device capable or choosing the role for USB connector.
++ * On platforms where the USB controller is dual-role capable, the controller
++ * driver will need to register the switch. On platforms where the USB host and
++ * USB device controllers behind the connector are separate, there will be a
++ * mux, and the driver for that mux will need to register the switch.
++ *
++ * Returns handle to a new role switch or ERR_PTR. The content of @desc is
++ * copied.
++ */
++struct usb_role_switch *
++usb_role_switch_register(struct device *parent,
++			 const struct usb_role_switch_desc *desc)
++{
++	struct usb_role_switch *sw;
++	int ret;
++
++	if (!desc || !desc->set)
++		return ERR_PTR(-EINVAL);
++
++	sw = kzalloc(sizeof(*sw), GFP_KERNEL);
++	if (!sw)
++		return ERR_PTR(-ENOMEM);
++
++	mutex_init(&sw->lock);
++
++	sw->allow_userspace_control = desc->allow_userspace_control;
++	sw->usb2_port = desc->usb2_port;
++	sw->usb3_port = desc->usb3_port;
++	sw->udc = desc->udc;
++	sw->set = desc->set;
++	sw->get = desc->get;
++
++	sw->dev.parent = parent;
++	sw->dev.class = role_class;
++	sw->dev.type = &usb_role_dev_type;
++	dev_set_name(&sw->dev, "%s-role-switch", dev_name(parent));
++
++	ret = device_register(&sw->dev);
++	if (ret) {
++		put_device(&sw->dev);
++		return ERR_PTR(ret);
++	}
++
++	/* TODO: Symlinks for the host port and the device controller. */
++
++	return sw;
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_register);
++
++/**
++ * usb_role_switch_unregister - Unregsiter USB Role Switch
++ * @sw: USB Role Switch
++ *
++ * Unregister switch that was registered with usb_role_switch_register().
++ */
++void usb_role_switch_unregister(struct usb_role_switch *sw)
++{
++	if (!IS_ERR_OR_NULL(sw))
++		device_unregister(&sw->dev);
++}
++EXPORT_SYMBOL_GPL(usb_role_switch_unregister);
++
++static int __init usb_roles_init(void)
++{
++	role_class = class_create(THIS_MODULE, "usb_role");
++	return PTR_ERR_OR_ZERO(role_class);
++}
++subsys_initcall(usb_roles_init);
++
++static void __exit usb_roles_exit(void)
++{
++	class_destroy(role_class);
++}
++module_exit(usb_roles_exit);
++
++MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
++MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("USB Role Class");
+diff --git a/include/linux/usb/role.h b/include/linux/usb/role.h
+new file mode 100644
+index 000000000000..edc51be4a77c
+--- /dev/null
++++ b/include/linux/usb/role.h
+@@ -0,0 +1,53 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#ifndef __LINUX_USB_ROLE_H
++#define __LINUX_USB_ROLE_H
++
++#include <linux/device.h>
++
++struct usb_role_switch;
++
++enum usb_role {
++	USB_ROLE_NONE,
++	USB_ROLE_HOST,
++	USB_ROLE_DEVICE,
++};
++
++typedef int (*usb_role_switch_set_t)(struct device *dev, enum usb_role role);
++typedef enum usb_role (*usb_role_switch_get_t)(struct device *dev);
++
++/**
++ * struct usb_role_switch_desc - USB Role Switch Descriptor
++ * @usb2_port: Optional reference to the host controller port device (USB2)
++ * @usb3_port: Optional reference to the host controller port device (USB3)
++ * @udc: Optional reference to the peripheral controller device
++ * @set: Callback for setting the role
++ * @get: Callback for getting the role (optional)
++ * @allow_userspace_control: If true userspace may change the role through sysfs
++ *
++ * @usb2_port and @usb3_port will point to the USB host port and @udc to the USB
++ * device controller behind the USB connector with the role switch. If
++ * @usb2_port, @usb3_port and @udc are included in the description, the
++ * reference count for them should be incremented by the caller of
++ * usb_role_switch_register() before registering the switch.
++ */
++struct usb_role_switch_desc {
++	struct device *usb2_port;
++	struct device *usb3_port;
++	struct device *udc;
++	usb_role_switch_set_t set;
++	usb_role_switch_get_t get;
++	bool allow_userspace_control;
++};
++
++int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role);
++enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw);
++struct usb_role_switch *usb_role_switch_get(struct device *dev);
++void usb_role_switch_put(struct usb_role_switch *sw);
++
++struct usb_role_switch *
++usb_role_switch_register(struct device *parent,
++			 const struct usb_role_switch_desc *desc);
++void usb_role_switch_unregister(struct usb_role_switch *sw);
++
++#endif /* __LINUX_USB_ROLE_H */
+-- 
+2.19.0
+
diff --git a/patches/1156-dt-bindings-i2c-document-R8A77995-bindings.patch b/patches/1156-dt-bindings-i2c-document-R8A77995-bindings.patch
new file mode 100644
index 00000000000000..971c22c0bf7b25
--- /dev/null
+++ b/patches/1156-dt-bindings-i2c-document-R8A77995-bindings.patch
@@ -0,0 +1,34 @@
+From 87eb936f5ca581609bd2753ad47d3e8c10f9debf Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Mon, 29 Jan 2018 16:45:47 +0100
+Subject: [PATCH 1156/1795] dt-bindings: i2c: document R8A77995 bindings
+
+R-Car D3 (R8A77995) SoC has a R-Car Gen3-compatible I2C controller.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit d0adf769df210248f60d33e62b1d4d14df271c02)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+index a777477e4547..e91dbafe71e5 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+@@ -14,6 +14,7 @@ Required properties:
+ 	"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
+ 	"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ 	"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
++	"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
+ 	"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+ 	"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ 				device.
+-- 
+2.19.0
+
diff --git a/patches/1157-dt-bindings-i2c-document-R8A77965-bindings.patch b/patches/1157-dt-bindings-i2c-document-R8A77965-bindings.patch
new file mode 100644
index 00000000000000..25b060c0535d8f
--- /dev/null
+++ b/patches/1157-dt-bindings-i2c-document-R8A77965-bindings.patch
@@ -0,0 +1,32 @@
+From 5c12e625ac6a48b2b1447465368b5993473790d9 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 20 Mar 2018 22:53:20 +0100
+Subject: [PATCH 1157/1795] dt-bindings: i2c: document R8A77965 bindings
+
+R-Car M3-N (R8A77965) SoC has a R-Car Gen3-compatible I2C controller.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 9d952aa2c8a46ba577b77619cc53e3df95507095)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+index e91dbafe71e5..4a7811ecd954 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+@@ -13,6 +13,7 @@ Required properties:
+ 	"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
+ 	"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
+ 	"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
++	"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
+ 	"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+ 	"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
+ 	"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+-- 
+2.19.0
+
diff --git a/patches/1158-i2c-rcar-fix-mask-value-of-prohibited-bit.patch b/patches/1158-i2c-rcar-fix-mask-value-of-prohibited-bit.patch
new file mode 100644
index 00000000000000..fc4cea72182393
--- /dev/null
+++ b/patches/1158-i2c-rcar-fix-mask-value-of-prohibited-bit.patch
@@ -0,0 +1,38 @@
+From 5e24dddfdae5b1002cc90a03282298e611e44295 Mon Sep 17 00:00:00 2001
+From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
+Date: Tue, 20 Mar 2018 22:04:14 +0100
+Subject: [PATCH 1158/1795] i2c: rcar: fix mask value of prohibited bit
+
+According to documentation, Bit 7 of ICMSR is unused and 0 should be
+written to it. Fix the mask accordingly.
+
+Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
+[wsa: edited commit message]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+
+(cherry picked from commit a1de3253a8840bf373e7c6330f21b7807c6c0536)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 4159ebcec2bb..c6915b835396 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -102,8 +102,8 @@
+ #define RCAR_IRQ_RECV	(MNR | MAL | MST | MAT | MDR)
+ #define RCAR_IRQ_STOP	(MST)
+ 
+-#define RCAR_IRQ_ACK_SEND	(~(MAT | MDE) & 0xFF)
+-#define RCAR_IRQ_ACK_RECV	(~(MAT | MDR) & 0xFF)
++#define RCAR_IRQ_ACK_SEND	(~(MAT | MDE) & 0x7F)
++#define RCAR_IRQ_ACK_RECV	(~(MAT | MDR) & 0x7F)
+ 
+ #define ID_LAST_MSG	(1 << 0)
+ #define ID_FIRST_MSG	(1 << 1)
+-- 
+2.19.0
+
diff --git a/patches/1159-drm-adv7511-Add-support-for-i2c_new_secondary_device.patch b/patches/1159-drm-adv7511-Add-support-for-i2c_new_secondary_device.patch
new file mode 100644
index 00000000000000..309a57eb7ae864
--- /dev/null
+++ b/patches/1159-drm-adv7511-Add-support-for-i2c_new_secondary_device.patch
@@ -0,0 +1,150 @@
+From f7e8637999845d0df988b59bbafd853d9fe48deb Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Tue, 13 Feb 2018 17:48:57 +0000
+Subject: [PATCH 1159/1795] drm: adv7511: Add support for
+ i2c_new_secondary_device
+
+The ADV7511 has four 256-byte maps that can be accessed via the main I2C
+ports. Each map has it own I2C address and acts as a standard slave
+device on the I2C bus.
+
+Allow a device tree node to override the default addresses so that
+address conflicts with other devices on the same bus may be resolved at
+the board description level.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/1518544137-2742-6-git-send-email-kbingham@kernel.org
+(cherry picked from commit 680532c50bca0f591ea90f4e820c5c1ce48adbfd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511.h     |  6 +++
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 42 +++++++++++++-------
+ 2 files changed, 33 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+index d034b2cb5eee..73d8ccb97742 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
+@@ -93,6 +93,11 @@
+ #define ADV7511_REG_CHIP_ID_HIGH		0xf5
+ #define ADV7511_REG_CHIP_ID_LOW			0xf6
+ 
++/* Hardware defined default addresses for I2C register maps */
++#define ADV7511_CEC_I2C_ADDR_DEFAULT		0x3c
++#define ADV7511_EDID_I2C_ADDR_DEFAULT		0x3f
++#define ADV7511_PACKET_I2C_ADDR_DEFAULT		0x38
++
+ #define ADV7511_CSC_ENABLE			BIT(7)
+ #define ADV7511_CSC_UPDATE_MODE			BIT(5)
+ 
+@@ -321,6 +326,7 @@ enum adv7511_type {
+ struct adv7511 {
+ 	struct i2c_client *i2c_main;
+ 	struct i2c_client *i2c_edid;
++	struct i2c_client *i2c_packet;
+ 	struct i2c_client *i2c_cec;
+ 
+ 	struct regmap *regmap;
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 95066350a2b0..afdd206c1a55 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -598,7 +598,7 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
+ 	/* Reading the EDID only works if the device is powered */
+ 	if (!adv7511->powered) {
+ 		unsigned int edid_i2c_addr =
+-					(adv7511->i2c_main->addr << 1) + 4;
++					(adv7511->i2c_edid->addr << 1);
+ 
+ 		__adv7511_power_on(adv7511);
+ 
+@@ -981,10 +981,10 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv)
+ {
+ 	int ret;
+ 
+-	adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
+-				     adv->i2c_main->addr - 1);
++	adv->i2c_cec = i2c_new_secondary_device(adv->i2c_main, "cec",
++						ADV7511_CEC_I2C_ADDR_DEFAULT);
+ 	if (!adv->i2c_cec)
+-		return -ENOMEM;
++		return -EINVAL;
+ 	i2c_set_clientdata(adv->i2c_cec, adv);
+ 
+ 	adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
+@@ -1094,8 +1094,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	struct adv7511_link_config link_config;
+ 	struct adv7511 *adv7511;
+ 	struct device *dev = &i2c->dev;
+-	unsigned int main_i2c_addr = i2c->addr << 1;
+-	unsigned int edid_i2c_addr = main_i2c_addr + 4;
+ 	unsigned int val;
+ 	int ret;
+ 
+@@ -1165,23 +1163,34 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	if (ret)
+ 		goto uninit_regulators;
+ 
+-	regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr);
+-	regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
+-		     main_i2c_addr - 0xa);
+-	regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR,
+-		     main_i2c_addr - 2);
+-
+ 	adv7511_packet_disable(adv7511, 0xffff);
+ 
+-	adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1);
++	adv7511->i2c_edid = i2c_new_secondary_device(i2c, "edid",
++					ADV7511_EDID_I2C_ADDR_DEFAULT);
+ 	if (!adv7511->i2c_edid) {
+-		ret = -ENOMEM;
++		ret = -EINVAL;
+ 		goto uninit_regulators;
+ 	}
+ 
++	regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
++		     adv7511->i2c_edid->addr << 1);
++
++	adv7511->i2c_packet = i2c_new_secondary_device(i2c, "packet",
++					ADV7511_PACKET_I2C_ADDR_DEFAULT);
++	if (!adv7511->i2c_packet) {
++		ret = -EINVAL;
++		goto err_i2c_unregister_edid;
++	}
++
++	regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
++		     adv7511->i2c_packet->addr << 1);
++
+ 	ret = adv7511_init_cec_regmap(adv7511);
+ 	if (ret)
+-		goto err_i2c_unregister_edid;
++		goto err_i2c_unregister_packet;
++
++	regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR,
++		     adv7511->i2c_cec->addr << 1);
+ 
+ 	INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
+ 
+@@ -1219,6 +1228,8 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	i2c_unregister_device(adv7511->i2c_cec);
+ 	if (adv7511->cec_clk)
+ 		clk_disable_unprepare(adv7511->cec_clk);
++err_i2c_unregister_packet:
++	i2c_unregister_device(adv7511->i2c_packet);
+ err_i2c_unregister_edid:
+ 	i2c_unregister_device(adv7511->i2c_edid);
+ uninit_regulators:
+@@ -1245,6 +1256,7 @@ static int adv7511_remove(struct i2c_client *i2c)
+ 
+ 	cec_unregister_adapter(adv7511->cec_adap);
+ 
++	i2c_unregister_device(adv7511->i2c_packet);
+ 	i2c_unregister_device(adv7511->i2c_edid);
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/1160-drm-bridge-adv7511-fix-mode_valid-s-return-type.patch b/patches/1160-drm-bridge-adv7511-fix-mode_valid-s-return-type.patch
new file mode 100644
index 00000000000000..4f8d6a14e48c82
--- /dev/null
+++ b/patches/1160-drm-bridge-adv7511-fix-mode_valid-s-return-type.patch
@@ -0,0 +1,37 @@
+From b52ef49c2b5fbb85633bbad706d224527ad452db Mon Sep 17 00:00:00 2001
+From: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
+Date: Tue, 24 Apr 2018 15:14:47 +0200
+Subject: [PATCH 1160/1795] drm/bridge: adv7511: fix mode_valid's return type
+
+The method struct drm_connector_helper_funcs::mode_valid is defined
+as returning an 'enum drm_mode_status' but the driver implementation
+for this method uses an 'int' for it.
+
+Fix this by using 'enum drm_mode_status' in the driver too.
+
+Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180424131450.1910-1-luc.vanoostenryck@gmail.com
+(cherry picked from commit 0e19b023414e9f8f75e9b5aafda585ca490a70bb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index afdd206c1a55..94e3ea413c33 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -666,7 +666,7 @@ adv7511_detect(struct adv7511 *adv7511, struct drm_connector *connector)
+ 	return status;
+ }
+ 
+-static int adv7511_mode_valid(struct adv7511 *adv7511,
++static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
+ 			      struct drm_display_mode *mode)
+ {
+ 	if (mode->clock > 165000)
+-- 
+2.19.0
+
diff --git a/patches/1161-drm-bridge-adv7511-fix-spelling-of-driver-name-in-Kc.patch b/patches/1161-drm-bridge-adv7511-fix-spelling-of-driver-name-in-Kc.patch
new file mode 100644
index 00000000000000..17b82b482c2399
--- /dev/null
+++ b/patches/1161-drm-bridge-adv7511-fix-spelling-of-driver-name-in-Kc.patch
@@ -0,0 +1,33 @@
+From 31eb262910dd2ab79a6d485180e21b35f9a27044 Mon Sep 17 00:00:00 2001
+From: Peter Rosin <peda@axentia.se>
+Date: Thu, 26 Apr 2018 23:36:44 +0200
+Subject: [PATCH 1161/1795] drm/bridge: adv7511: fix spelling of driver name in
+ Kconfig
+
+Could perhaps prevent some confusion.
+
+Signed-off-by: Peter Rosin <peda@axentia.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180426213644.29318-1-peda@axentia.se
+(cherry picked from commit 7bd2d2ecedff26b3a87b026b98acc4b7110c9ee6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/Kconfig b/drivers/gpu/drm/bridge/adv7511/Kconfig
+index 592b9d2ec034..944e440c4fde 100644
+--- a/drivers/gpu/drm/bridge/adv7511/Kconfig
++++ b/drivers/gpu/drm/bridge/adv7511/Kconfig
+@@ -1,5 +1,5 @@
+ config DRM_I2C_ADV7511
+-	tristate "AV7511 encoder"
++	tristate "ADV7511 encoder"
+ 	depends on OF
+ 	select DRM_KMS_HELPER
+ 	select REGMAP_I2C
+-- 
+2.19.0
+
diff --git a/patches/1162-gpu-drm-bridge-adv7511-Replace-mdelay-with-usleep_ra.patch b/patches/1162-gpu-drm-bridge-adv7511-Replace-mdelay-with-usleep_ra.patch
new file mode 100644
index 00000000000000..44be771dbea859
--- /dev/null
+++ b/patches/1162-gpu-drm-bridge-adv7511-Replace-mdelay-with-usleep_ra.patch
@@ -0,0 +1,44 @@
+From 9ffb5117fb20fae0757a48026a7890038e9f6a29 Mon Sep 17 00:00:00 2001
+From: Jia-Ju Bai <baijiaju1990@gmail.com>
+Date: Wed, 11 Apr 2018 16:33:42 +0800
+Subject: [PATCH 1162/1795] gpu: drm: bridge: adv7511: Replace mdelay with
+ usleep_range in adv7511_probe
+
+adv7511_probe() is never called in atomic context.
+This function is only set as ".probe" in struct i2c_driver.
+
+Despite never getting called from atomic context, adv7511_probe()
+calls mdelay() to busily wait.
+This is not necessary and can be replaced with usleep_range() to
+avoid busy waiting.
+
+This is found by a static analysis tool named DCNS written by myself.
+And I also manually check it.
+
+Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Archit Taneja <architt@codeaurora.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/1523435622-4329-1-git-send-email-baijiaju1990@gmail.com
+(cherry picked from commit 5f27314141757794378abb2907fb7116947d644b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+index 94e3ea413c33..dd3ff2f2cdce 100644
+--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+@@ -1139,7 +1139,7 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ 	}
+ 
+ 	if (adv7511->gpio_pd) {
+-		mdelay(5);
++		usleep_range(5000, 6000);
+ 		gpiod_set_value_cansleep(adv7511->gpio_pd, 0);
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/1163-media-adv7511-fix-clearing-of-the-CEC-receive-buffer.patch b/patches/1163-media-adv7511-fix-clearing-of-the-CEC-receive-buffer.patch
new file mode 100644
index 00000000000000..d1cf08d9a5a9e8
--- /dev/null
+++ b/patches/1163-media-adv7511-fix-clearing-of-the-CEC-receive-buffer.patch
@@ -0,0 +1,87 @@
+From 88e8b5a13c84d941fd76fdc5ee1af13a420d4dfc Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hverkuil@xs4all.nl>
+Date: Tue, 15 May 2018 04:50:05 -0400
+Subject: [PATCH 1163/1795] media: adv7511: fix clearing of the CEC receive
+ buffer
+
+The CEC receive buffer was not always cleared correctly. The
+datasheet was a bit confusing since sometimes it mentioned that the
+bit in CEC register 0x4a had to be toggled, and sometimes it suggested
+it was a 'Clear-on-write' bit. But it really needs to be toggled.
+
+The patch also enables/disables the CEC irqs after the other irq are
+enabled/disabled instead of doing it before. It may not matter, but it
+feels more logical to do it in that order, and the implementation that
+we (Cisco) have used until now and that is known to be reliable also
+did it in that order.
+
+Signed-off-by: Hans Verkuil <hansverk@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 3c785e48786f9f7ef19a69433ba4c6ce83c949fa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/i2c/adv7511.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c
+index 2817bafc67bf..5ff25efd0f08 100644
+--- a/drivers/media/i2c/adv7511.c
++++ b/drivers/media/i2c/adv7511.c
+@@ -744,8 +744,8 @@ static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
+ 		/* power up cec section */
+ 		adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01);
+ 		/* legacy mode and clear all rx buffers */
++		adv7511_cec_write(sd, 0x4a, 0x00);
+ 		adv7511_cec_write(sd, 0x4a, 0x07);
+-		adv7511_cec_write(sd, 0x4a, 0);
+ 		adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */
+ 		/* enabled irqs: */
+ 		/* tx: ready */
+@@ -929,9 +929,6 @@ static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
+ 	else if (adv7511_have_hotplug(sd))
+ 		irqs |= MASK_ADV7511_EDID_RDY_INT;
+ 
+-	adv7511_wr_and_or(sd, 0x95, 0xc0,
+-			  (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
+-
+ 	/*
+ 	 * This i2c write can fail (approx. 1 in 1000 writes). But it
+ 	 * is essential that this register is correct, so retry it
+@@ -945,9 +942,11 @@ static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
+ 		irqs_rd = adv7511_rd(sd, 0x94);
+ 	} while (retries-- && irqs_rd != irqs);
+ 
+-	if (irqs_rd == irqs)
+-		return;
+-	v4l2_err(sd, "Could not set interrupts: hw failure?\n");
++	if (irqs_rd != irqs)
++		v4l2_err(sd, "Could not set interrupts: hw failure?\n");
++
++	adv7511_wr_and_or(sd, 0x95, 0xc0,
++			  (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
+ }
+ 
+ /* Interrupt handler */
+@@ -994,8 +993,8 @@ static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
+ 			for (i = 0; i < msg.len; i++)
+ 				msg.msg[i] = adv7511_cec_read(sd, i + 0x15);
+ 
+-			adv7511_cec_write(sd, 0x4a, 1); /* toggle to re-enable rx 1 */
+-			adv7511_cec_write(sd, 0x4a, 0);
++			adv7511_cec_write(sd, 0x4a, 0); /* toggle to re-enable rx 1 */
++			adv7511_cec_write(sd, 0x4a, 1);
+ 			cec_received_msg(state->cec_adap, &msg);
+ 		}
+ 	}
+@@ -1790,6 +1789,7 @@ static void adv7511_init_setup(struct v4l2_subdev *sd)
+ 
+ 	/* legacy mode */
+ 	adv7511_cec_write(sd, 0x4a, 0x00);
++	adv7511_cec_write(sd, 0x4a, 0x07);
+ 
+ 	if (cec_clk % 750000 != 0)
+ 		v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n",
+-- 
+2.19.0
+
diff --git a/patches/1164-media-adv7511-fix-incorrect-clear-of-CEC-receive-int.patch b/patches/1164-media-adv7511-fix-incorrect-clear-of-CEC-receive-int.patch
new file mode 100644
index 00000000000000..21b8c063b186d5
--- /dev/null
+++ b/patches/1164-media-adv7511-fix-incorrect-clear-of-CEC-receive-int.patch
@@ -0,0 +1,41 @@
+From be2a5ca84cd25584096191fb8ea57cda38a4a79a Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hans.verkuil@cisco.com>
+Date: Tue, 22 May 2018 07:33:14 -0400
+Subject: [PATCH 1164/1795] media: adv7511: fix incorrect clear of CEC receive
+ interrupt
+
+If a CEC message was received and the RX interrupt was set, but
+not yet processed, and a new transmit was issues, then the
+transmit code would inadvertently clear the RX interrupt and
+after that no new messages would ever be received.
+
+Instead it should only clear TX interrupts since register 0x97
+is a clear-on-write register.
+
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 00f6f92dbbeb3b98d38b26449be0df46b2e6d6a4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/i2c/adv7511.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c
+index 5ff25efd0f08..0dda236a3153 100644
+--- a/drivers/media/i2c/adv7511.c
++++ b/drivers/media/i2c/adv7511.c
+@@ -843,8 +843,8 @@ static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+ 	 */
+ 	adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
+ 
+-	/* blocking, clear cec tx irq status */
+-	adv7511_wr_and_or(sd, 0x97, 0xc7, 0x38);
++	/* clear cec tx irq status */
++	adv7511_wr(sd, 0x97, 0x38);
+ 
+ 	/* write data */
+ 	for (i = 0; i < len; i++)
+-- 
+2.19.0
+
diff --git a/patches/1165-dt-bindings-display-renesas-Add-R-Car-M3-N-HDMI-TX-D.patch b/patches/1165-dt-bindings-display-renesas-Add-R-Car-M3-N-HDMI-TX-D.patch
new file mode 100644
index 00000000000000..e4b9a03811e2cd
--- /dev/null
+++ b/patches/1165-dt-bindings-display-renesas-Add-R-Car-M3-N-HDMI-TX-D.patch
@@ -0,0 +1,37 @@
+From 889bc1fa8e2e1f1b13c9ce1cc38849ef9f14e6e5 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:21:50 +0100
+Subject: [PATCH 1165/1795] dt-bindings: display: renesas: Add R-Car M3-N HDMI
+ TX DT bindings
+
+The M3-N HDMI TX controller is compatible with the M3-W and H3. No
+extension to the DT bindings are needed.
+
+Add an SoC-specific compatible string in case differences between the IP
+versions are found later and require model-specific handling.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 425f33bdcd4f492546354cbe4daafe420c450a83)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/display/bridge/renesas,dw-hdmi.txt       | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+index 3a72a103a18a..a41d280c3f9f 100644
+--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
++++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+@@ -14,6 +14,7 @@ Required properties:
+ - compatible : Shall contain one or more of
+   - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
+   - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
++  - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
+   - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
+ 
+     When compatible with generic versions, nodes must list the SoC-specific
+-- 
+2.19.0
+
diff --git a/patches/1166-ASoC-sh-Drop-SUPERH-platform-dependency.patch b/patches/1166-ASoC-sh-Drop-SUPERH-platform-dependency.patch
new file mode 100644
index 00000000000000..019e3281cb9758
--- /dev/null
+++ b/patches/1166-ASoC-sh-Drop-SUPERH-platform-dependency.patch
@@ -0,0 +1,34 @@
+From f0f9c4509d3a8dfc490178d167c93b95c6492f0c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 20 Apr 2018 16:22:14 +0200
+Subject: [PATCH 1166/1795] ASoC: sh: Drop SUPERH platform dependency
+
+The SIU sound peripheral is used only on SuperH SH-Mobile platforms.
+As both SUPERH and ARCH_SHMOBILE are set for these platforms, the SUPERH
+dependency can be dropped.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 4070d91754039e88f7b64e462f3d0d8cdb4be041)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
+index 1aa5cd77ca24..365f46321147 100644
+--- a/sound/soc/sh/Kconfig
++++ b/sound/soc/sh/Kconfig
+@@ -28,7 +28,7 @@ config SND_SOC_SH4_FSI
+ 
+ config SND_SOC_SH4_SIU
+ 	tristate
+-	depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
++	depends on ARCH_SHMOBILE && HAVE_CLK
+ 	select DMA_ENGINE
+ 	select DMADEVICES
+ 	select SH_DMAE
+-- 
+2.19.0
+
diff --git a/patches/1167-ASoC-sh-Update-menu-title-and-platform-dependency.patch b/patches/1167-ASoC-sh-Update-menu-title-and-platform-dependency.patch
new file mode 100644
index 00000000000000..85c0ef7b5f30e9
--- /dev/null
+++ b/patches/1167-ASoC-sh-Update-menu-title-and-platform-dependency.patch
@@ -0,0 +1,41 @@
+From e8f71f0e70e2342ac2260c5259974e6fe0f2502f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 20 Apr 2018 15:28:32 +0200
+Subject: [PATCH 1167/1795] ASoC: sh: Update menu title and platform dependency
+
+Change the menu title to refer to "Renesas SoCs" instead of "SuperH", as
+both SuperH and ARM SoCs are supported.
+
+Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
+is ARCH_RENESAS a more appropriate platform dependency for Renesas ARM
+SoCs than the legacy ARCH_SHMOBILE, hence use the former.
+Renesas SuperH SH-Mobile SoCs are still covered by the SUPERH
+dependency.
+
+This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
+future.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 6ec2d0c27cd788a92021e9b16f92d31890b11b14)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
+index 365f46321147..0ae0800bf3a8 100644
+--- a/sound/soc/sh/Kconfig
++++ b/sound/soc/sh/Kconfig
+@@ -1,5 +1,5 @@
+-menu "SoC Audio support for SuperH"
+-	depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
++menu "SoC Audio support for Renesas SoCs"
++	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
+ 
+ config SND_SOC_PCM_SH7760
+ 	tristate "SoC Audio support for Renesas SH7760"
+-- 
+2.19.0
+
diff --git a/patches/1168-i2c-busses-remove-superfluous-ignoring-of-children-f.patch b/patches/1168-i2c-busses-remove-superfluous-ignoring-of-children-f.patch
new file mode 100644
index 00000000000000..4e64e4c52be340
--- /dev/null
+++ b/patches/1168-i2c-busses-remove-superfluous-ignoring-of-children-f.patch
@@ -0,0 +1,74 @@
+From 4fd69d7c2f4e7e7bbe311decfd2cf03775e0ad33 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sun, 29 Apr 2018 20:41:04 +0200
+Subject: [PATCH 1168/1795] i2c: busses: remove superfluous ignoring of
+ children for RPM
+
+These days, the I2C core ensures that the embedded adapter device
+ignores the PM states of its children already. Because the adapter
+device is an opaque logical device, there is no need for drivers to
+repeat that again.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 77bade677c3c5616dfadfd21f0220fcddbfa4cbe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-hix5hd2.c   |  1 -
+ drivers/i2c/busses/i2c-nomadik.c   |  2 --
+ drivers/i2c/busses/i2c-sh_mobile.c | 11 -----------
+ 3 files changed, 14 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c
+index bb68957d3da5..1504c3c1a1c0 100644
+--- a/drivers/i2c/busses/i2c-hix5hd2.c
++++ b/drivers/i2c/busses/i2c-hix5hd2.c
+@@ -471,7 +471,6 @@ static int hix5hd2_i2c_probe(struct platform_device *pdev)
+ 		goto err_clk;
+ 	}
+ 
+-	pm_suspend_ignore_children(&pdev->dev, true);
+ 	pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
+ 	pm_runtime_use_autosuspend(priv->dev);
+ 	pm_runtime_set_active(priv->dev);
+diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
+index 49c7c0c91486..0ed5a41804dc 100644
+--- a/drivers/i2c/busses/i2c-nomadik.c
++++ b/drivers/i2c/busses/i2c-nomadik.c
+@@ -1012,8 +1012,6 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
+ 		goto err_no_mem;
+ 	}
+ 
+-	pm_suspend_ignore_children(&adev->dev, true);
+-
+ 	dev->clk = devm_clk_get(&adev->dev, NULL);
+ 	if (IS_ERR(dev->clk)) {
+ 		dev_err(&adev->dev, "could not get i2c clock\n");
+diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
+index d856bc211715..5fda4188a9e5 100644
+--- a/drivers/i2c/busses/i2c-sh_mobile.c
++++ b/drivers/i2c/busses/i2c-sh_mobile.c
+@@ -899,17 +899,6 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
+ 	if (resource_size(res) > 0x17)
+ 		pd->flags |= IIC_FLAG_HAS_ICIC67;
+ 
+-	/* Enable Runtime PM for this device.
+-	 *
+-	 * Also tell the Runtime PM core to ignore children
+-	 * for this device since it is valid for us to suspend
+-	 * this I2C master driver even though the slave devices
+-	 * on the I2C bus may not be suspended.
+-	 *
+-	 * The state of the I2C hardware bus is unaffected by
+-	 * the Runtime PM state.
+-	 */
+-	pm_suspend_ignore_children(&dev->dev, true);
+ 	pm_runtime_enable(&dev->dev);
+ 	pm_runtime_get_sync(&dev->dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1169-dt-bindings-net-ravb-Add-support-for-r8a77990-SoC.patch b/patches/1169-dt-bindings-net-ravb-Add-support-for-r8a77990-SoC.patch
new file mode 100644
index 00000000000000..2941a8b59cf977
--- /dev/null
+++ b/patches/1169-dt-bindings-net-ravb-Add-support-for-r8a77990-SoC.patch
@@ -0,0 +1,35 @@
+From cbc9a7113eef9fbff780e329c901b0a2647d39bc Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 12:18:56 +0900
+Subject: [PATCH 1169/1795] dt-bindings: net: ravb: Add support for r8a77990
+ SoC
+
+Add documentation for r8a77990 compatible string to renesas ravb device
+tree bindings documentation.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 7824b54dd72ddd1f1d26aa48604b7ea17cfaebc3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+index 890526dbfc26..fac897d54423 100644
+--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
++++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
+@@ -21,6 +21,7 @@ Required properties:
+       - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
+       - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
+       - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
++      - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
+       - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
+       - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ 		R-Car Gen3 devices.
+-- 
+2.19.0
+
diff --git a/patches/1170-dmaengine-rcar-dmac-Document-R-Car-D3-bindings.patch b/patches/1170-dmaengine-rcar-dmac-Document-R-Car-D3-bindings.patch
new file mode 100644
index 00000000000000..83f0db738c778c
--- /dev/null
+++ b/patches/1170-dmaengine-rcar-dmac-Document-R-Car-D3-bindings.patch
@@ -0,0 +1,37 @@
+From 9fae9ad8274ef062c6ba7092169ac58575f26929 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Tue, 24 Apr 2018 10:51:06 +0200
+Subject: [PATCH 1170/1795] dmaengine: rcar-dmac: Document R-Car D3 bindings
+
+R8A77995's SYS-DMAC is R-Car Gen3-compatible.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+[simon: rebased]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+
+(cherry picked from commit 9f17b101f938f56c79ac645ea506de106b964ca9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+index 61315eaa7660..b1ba639554c0 100644
+--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
++++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+@@ -29,6 +29,7 @@ Required Properties:
+ 		- "renesas,dmac-r8a77965" (R-Car M3-N)
+ 		- "renesas,dmac-r8a77970" (R-Car V3M)
+ 		- "renesas,dmac-r8a77980" (R-Car V3H)
++		- "renesas,dmac-r8a77995" (R-Car D3)
+ 
+ - reg: base address and length of the registers block for the DMAC
+ 
+-- 
+2.19.0
+
diff --git a/patches/1171-media-v4l-vsp1-Don-t-start-stop-media-pipeline-for-D.patch b/patches/1171-media-v4l-vsp1-Don-t-start-stop-media-pipeline-for-D.patch
new file mode 100644
index 00000000000000..557f7a50882246
--- /dev/null
+++ b/patches/1171-media-v4l-vsp1-Don-t-start-stop-media-pipeline-for-D.patch
@@ -0,0 +1,77 @@
+From 66d251f819f966bca9f283ed06e8efae7f57413f Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 12:12:36 -0500
+Subject: [PATCH 1171/1795] media: v4l: vsp1: Don't start/stop media pipeline
+ for DRM
+
+The DRM support code manages a pipeline of VSP entities, each backed by
+a media entity. When starting or stopping the pipeline, it starts and
+stops the media pipeline through the media API in order to store the
+pipeline pointer in every entity.
+
+The driver doesn't use the pipe pointer in media entities, neither does
+it rely on the other effects of the media_pipeline_start() and
+media_pipeline_stop() functions. Furthermore, as the media links for the
+DRM pipeline are never set up correctly, and as the pipeline can be
+modified dynamically when enabling or disabling planes, the current
+implementation is not correct. Remove the incorrect and unneeded code.
+
+While at it remove the outdated comment that states that entities are
+not started when the LIF is setup, as they now are.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 9fd099b1832cab8748ac85f451be8d79ab132d59)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 18 +-----------------
+ 1 file changed, 1 insertion(+), 17 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index b8fee1834253..a1f2ba044092 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -109,8 +109,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		if (ret == -ETIMEDOUT)
+ 			dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
+ 
+-		media_pipeline_stop(&pipe->output->entity.subdev.entity);
+-
+ 		for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
+ 			struct vsp1_rwpf *rpf = pipe->inputs[i];
+ 
+@@ -223,13 +221,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		return -EPIPE;
+ 	}
+ 
+-	/*
+-	 * Mark the pipeline as streaming and enable the VSP1. This will store
+-	 * the pipeline pointer in all entities, which the s_stream handlers
+-	 * will need. We don't start the entities themselves right at this point
+-	 * as there's no plane configured yet, so we can't start processing
+-	 * buffers.
+-	 */
++	/* Enable the VSP1. */
+ 	ret = vsp1_device_get(vsp1);
+ 	if (ret < 0)
+ 		return ret;
+@@ -241,14 +233,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	drm_pipe->du_complete = cfg->callback;
+ 	drm_pipe->du_private = cfg->callback_data;
+ 
+-	ret = media_pipeline_start(&pipe->output->entity.subdev.entity,
+-					  &pipe->pipe);
+-	if (ret < 0) {
+-		dev_dbg(vsp1->dev, "%s: pipeline start failed\n", __func__);
+-		vsp1_device_put(vsp1);
+-		return ret;
+-	}
+-
+ 	/* Disable the display interrupts. */
+ 	vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
+ 	vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
+-- 
+2.19.0
+
diff --git a/patches/1172-media-v4l-vsp1-Remove-unused-field-from-vsp1_drm_pip.patch b/patches/1172-media-v4l-vsp1-Remove-unused-field-from-vsp1_drm_pip.patch
new file mode 100644
index 00000000000000..477726a59f7557
--- /dev/null
+++ b/patches/1172-media-v4l-vsp1-Remove-unused-field-from-vsp1_drm_pip.patch
@@ -0,0 +1,55 @@
+From 222c3fa0d9415170b76b9fef7e74cfd44882cbb9 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 23 Feb 2018 15:21:40 -0500
+Subject: [PATCH 1172/1795] media: v4l: vsp1: Remove unused field from
+ vsp1_drm_pipeline structure
+
+The vsp1_drm_pipeline enabled field is set but never used. Remove it.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 7a7810878ef35aec905c859e346a7a141e82bafa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 4 ----
+ drivers/media/platform/vsp1/vsp1_drm.h | 2 --
+ 2 files changed, 6 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index a1f2ba044092..a267f12f0cc8 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -273,10 +273,6 @@ EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
+  */
+ void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
+ {
+-	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
+-	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
+-
+-	drm_pipe->enabled = drm_pipe->pipe.num_inputs != 0;
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index 1cd9db785bf7..9aa19325cbe9 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -20,13 +20,11 @@
+ /**
+  * vsp1_drm_pipeline - State for the API exposed to the DRM driver
+  * @pipe: the VSP1 pipeline used for display
+- * @enabled: pipeline state at the beginning of an update
+  * @du_complete: frame completion callback for the DU driver (optional)
+  * @du_private: data to be passed to the du_complete callback
+  */
+ struct vsp1_drm_pipeline {
+ 	struct vsp1_pipeline pipe;
+-	bool enabled;
+ 
+ 	/* Frame synchronisation */
+ 	void (*du_complete)(void *, bool);
+-- 
+2.19.0
+
diff --git a/patches/1173-media-v4l-vsp1-Store-pipeline-pointer-in-vsp1_entity.patch b/patches/1173-media-v4l-vsp1-Store-pipeline-pointer-in-vsp1_entity.patch
new file mode 100644
index 00000000000000..44374292b2a99a
--- /dev/null
+++ b/patches/1173-media-v4l-vsp1-Store-pipeline-pointer-in-vsp1_entity.patch
@@ -0,0 +1,343 @@
+From a485dd38d2ac8c9aaa3efe9a6c991e084a7209d8 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 17:22:43 -0500
+Subject: [PATCH 1173/1795] media: v4l: vsp1: Store pipeline pointer in
+ vsp1_entity
+
+Various types of objects subclassing vsp1_entity currently store a
+pointer to the pipeline. Move the pointer to vsp1_entity to simplify the
+code and avoid storing the pipeline in more entity subclasses later.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 1ccbb32cb8b4b0445d4281a37752e54e0fcade4c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c    | 20 +++++++++-----
+ drivers/media/platform/vsp1/vsp1_drv.c    |  2 +-
+ drivers/media/platform/vsp1/vsp1_entity.h |  2 ++
+ drivers/media/platform/vsp1/vsp1_histo.c  |  2 +-
+ drivers/media/platform/vsp1/vsp1_histo.h  |  3 ---
+ drivers/media/platform/vsp1/vsp1_pipe.c   | 33 +++++++----------------
+ drivers/media/platform/vsp1/vsp1_rwpf.h   |  2 --
+ drivers/media/platform/vsp1/vsp1_video.c  | 17 +++++-------
+ 8 files changed, 34 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index a267f12f0cc8..a7ad85ab0b08 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -120,6 +120,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 			 * inputs.
+ 			 */
+ 			WARN_ON(list_empty(&rpf->entity.list_pipe));
++			rpf->entity.pipe = NULL;
+ 			list_del_init(&rpf->entity.list_pipe);
+ 			pipe->inputs[i] = NULL;
+ 
+@@ -536,8 +537,10 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 			continue;
+ 		}
+ 
+-		if (list_empty(&rpf->entity.list_pipe))
++		if (list_empty(&rpf->entity.list_pipe)) {
++			rpf->entity.pipe = pipe;
+ 			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
++		}
+ 
+ 		bru->inputs[i].rpf = rpf;
+ 		rpf->bru_input = i;
+@@ -562,6 +565,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 			vsp1_dl_list_write(dl, entity->route->reg,
+ 					   VI6_DPR_NODE_UNUSED);
+ 
++			entity->pipe = NULL;
+ 			list_del_init(&entity->list_pipe);
+ 
+ 			continue;
+@@ -625,24 +629,28 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
+ 
+ 		vsp1_pipeline_init(pipe);
+ 
++		pipe->frame_end = vsp1_du_pipeline_frame_end;
++
+ 		/*
+ 		 * The DRM pipeline is static, add entities manually. The first
+ 		 * pipeline uses the BRU and the second pipeline the BRS.
+ 		 */
+ 		pipe->bru = i == 0 ? &vsp1->bru->entity : &vsp1->brs->entity;
+-		pipe->lif = &vsp1->lif[i]->entity;
+ 		pipe->output = vsp1->wpf[i];
+-		pipe->output->pipe = pipe;
+-		pipe->frame_end = vsp1_du_pipeline_frame_end;
++		pipe->lif = &vsp1->lif[i]->entity;
+ 
++		pipe->bru->pipe = pipe;
+ 		pipe->bru->sink = &pipe->output->entity;
+ 		pipe->bru->sink_pad = 0;
++		list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
++
++		pipe->output->entity.pipe = pipe;
+ 		pipe->output->entity.sink = pipe->lif;
+ 		pipe->output->entity.sink_pad = 0;
++		list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
+ 
+-		list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
++		pipe->lif->pipe = pipe;
+ 		list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
+-		list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
+ 	}
+ 
+ 	/* Disable all RPFs initially. */
+diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c
+index eed9516e25e1..58a7993f2306 100644
+--- a/drivers/media/platform/vsp1/vsp1_drv.c
++++ b/drivers/media/platform/vsp1/vsp1_drv.c
+@@ -63,7 +63,7 @@ static irqreturn_t vsp1_irq_handler(int irq, void *data)
+ 		vsp1_write(vsp1, VI6_WPF_IRQ_STA(i), ~status & mask);
+ 
+ 		if (status & VI6_WFP_IRQ_STA_DFE) {
+-			vsp1_pipeline_frame_end(wpf->pipe);
++			vsp1_pipeline_frame_end(wpf->entity.pipe);
+ 			ret = IRQ_HANDLED;
+ 		}
+ 	}
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index 408602ebeb97..c26523c56c05 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -106,6 +106,8 @@ struct vsp1_entity {
+ 	unsigned int index;
+ 	const struct vsp1_route *route;
+ 
++	struct vsp1_pipeline *pipe;
++
+ 	struct list_head list_dev;
+ 	struct list_head list_pipe;
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_histo.c b/drivers/media/platform/vsp1/vsp1_histo.c
+index afab77cf4fa5..8638ebc514b4 100644
+--- a/drivers/media/platform/vsp1/vsp1_histo.c
++++ b/drivers/media/platform/vsp1/vsp1_histo.c
+@@ -61,7 +61,7 @@ void vsp1_histogram_buffer_complete(struct vsp1_histogram *histo,
+ 				    struct vsp1_histogram_buffer *buf,
+ 				    size_t size)
+ {
+-	struct vsp1_pipeline *pipe = histo->pipe;
++	struct vsp1_pipeline *pipe = histo->entity.pipe;
+ 	unsigned long flags;
+ 
+ 	/*
+diff --git a/drivers/media/platform/vsp1/vsp1_histo.h b/drivers/media/platform/vsp1/vsp1_histo.h
+index af2874f6031d..e774adbf251f 100644
+--- a/drivers/media/platform/vsp1/vsp1_histo.h
++++ b/drivers/media/platform/vsp1/vsp1_histo.h
+@@ -25,7 +25,6 @@
+ #include "vsp1_entity.h"
+ 
+ struct vsp1_device;
+-struct vsp1_pipeline;
+ 
+ #define HISTO_PAD_SINK				0
+ #define HISTO_PAD_SOURCE			1
+@@ -37,8 +36,6 @@ struct vsp1_histogram_buffer {
+ };
+ 
+ struct vsp1_histogram {
+-	struct vsp1_pipeline *pipe;
+-
+ 	struct vsp1_entity entity;
+ 	struct video_device video;
+ 	struct media_pad pad;
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index 44944ac86d9b..99ccbac3256a 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -185,6 +185,7 @@ const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
+ 
+ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
+ {
++	struct vsp1_entity *entity;
+ 	unsigned int i;
+ 
+ 	if (pipe->bru) {
+@@ -194,29 +195,13 @@ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
+ 			bru->inputs[i].rpf = NULL;
+ 	}
+ 
+-	for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
+-		if (pipe->inputs[i]) {
+-			pipe->inputs[i]->pipe = NULL;
+-			pipe->inputs[i] = NULL;
+-		}
+-	}
+-
+-	if (pipe->output) {
+-		pipe->output->pipe = NULL;
+-		pipe->output = NULL;
+-	}
++	for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i)
++		pipe->inputs[i] = NULL;
+ 
+-	if (pipe->hgo) {
+-		struct vsp1_hgo *hgo = to_hgo(&pipe->hgo->subdev);
++	pipe->output = NULL;
+ 
+-		hgo->histo.pipe = NULL;
+-	}
+-
+-	if (pipe->hgt) {
+-		struct vsp1_hgt *hgt = to_hgt(&pipe->hgt->subdev);
+-
+-		hgt->histo.pipe = NULL;
+-	}
++	list_for_each_entry(entity, &pipe->entities, list_pipe)
++		entity->pipe = NULL;
+ 
+ 	INIT_LIST_HEAD(&pipe->entities);
+ 	pipe->state = VSP1_PIPELINE_STOPPED;
+@@ -423,7 +408,7 @@ void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
+ 		if (wpf == NULL)
+ 			continue;
+ 
+-		pipe = wpf->pipe;
++		pipe = wpf->entity.pipe;
+ 		if (pipe == NULL)
+ 			continue;
+ 
+@@ -440,7 +425,7 @@ void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
+ 		if (wpf == NULL)
+ 			continue;
+ 
+-		pipe = wpf->pipe;
++		pipe = wpf->entity.pipe;
+ 		if (pipe == NULL)
+ 			continue;
+ 
+@@ -465,7 +450,7 @@ void vsp1_pipelines_resume(struct vsp1_device *vsp1)
+ 		if (wpf == NULL)
+ 			continue;
+ 
+-		pipe = wpf->pipe;
++		pipe = wpf->entity.pipe;
+ 		if (pipe == NULL)
+ 			continue;
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h
+index 58215a7ab631..c94ac89abfa7 100644
+--- a/drivers/media/platform/vsp1/vsp1_rwpf.h
++++ b/drivers/media/platform/vsp1/vsp1_rwpf.h
+@@ -27,7 +27,6 @@
+ 
+ struct v4l2_ctrl;
+ struct vsp1_dl_manager;
+-struct vsp1_pipeline;
+ struct vsp1_rwpf;
+ struct vsp1_video;
+ 
+@@ -39,7 +38,6 @@ struct vsp1_rwpf {
+ 	struct vsp1_entity entity;
+ 	struct v4l2_ctrl_handler ctrls;
+ 
+-	struct vsp1_pipeline *pipe;
+ 	struct vsp1_video *video;
+ 
+ 	unsigned int max_width;
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index 93f69b3ac911..e88be9cd2a0f 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -324,7 +324,7 @@ static int vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe)
+ static struct vsp1_vb2_buffer *
+ vsp1_video_complete_buffer(struct vsp1_video *video)
+ {
+-	struct vsp1_pipeline *pipe = video->rwpf->pipe;
++	struct vsp1_pipeline *pipe = video->rwpf->entity.pipe;
+ 	struct vsp1_vb2_buffer *next = NULL;
+ 	struct vsp1_vb2_buffer *done;
+ 	unsigned long flags;
+@@ -598,20 +598,19 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe,
+ 		subdev = media_entity_to_v4l2_subdev(entity);
+ 		e = to_vsp1_entity(subdev);
+ 		list_add_tail(&e->list_pipe, &pipe->entities);
++		e->pipe = pipe;
+ 
+ 		switch (e->type) {
+ 		case VSP1_ENTITY_RPF:
+ 			rwpf = to_rwpf(subdev);
+ 			pipe->inputs[rwpf->entity.index] = rwpf;
+ 			rwpf->video->pipe_index = ++pipe->num_inputs;
+-			rwpf->pipe = pipe;
+ 			break;
+ 
+ 		case VSP1_ENTITY_WPF:
+ 			rwpf = to_rwpf(subdev);
+ 			pipe->output = rwpf;
+ 			rwpf->video->pipe_index = 0;
+-			rwpf->pipe = pipe;
+ 			break;
+ 
+ 		case VSP1_ENTITY_LIF:
+@@ -625,12 +624,10 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe,
+ 
+ 		case VSP1_ENTITY_HGO:
+ 			pipe->hgo = e;
+-			to_hgo(subdev)->histo.pipe = pipe;
+ 			break;
+ 
+ 		case VSP1_ENTITY_HGT:
+ 			pipe->hgt = e;
+-			to_hgt(subdev)->histo.pipe = pipe;
+ 			break;
+ 
+ 		default:
+@@ -682,7 +679,7 @@ static struct vsp1_pipeline *vsp1_video_pipeline_get(struct vsp1_video *video)
+ 	 * Otherwise allocate a new pipeline and initialize it, it will be freed
+ 	 * when the last reference is released.
+ 	 */
+-	if (!video->rwpf->pipe) {
++	if (!video->rwpf->entity.pipe) {
+ 		pipe = kzalloc(sizeof(*pipe), GFP_KERNEL);
+ 		if (!pipe)
+ 			return ERR_PTR(-ENOMEM);
+@@ -694,7 +691,7 @@ static struct vsp1_pipeline *vsp1_video_pipeline_get(struct vsp1_video *video)
+ 			return ERR_PTR(ret);
+ 		}
+ 	} else {
+-		pipe = video->rwpf->pipe;
++		pipe = video->rwpf->entity.pipe;
+ 		kref_get(&pipe->kref);
+ 	}
+ 
+@@ -777,7 +774,7 @@ static void vsp1_video_buffer_queue(struct vb2_buffer *vb)
+ {
+ 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ 	struct vsp1_video *video = vb2_get_drv_priv(vb->vb2_queue);
+-	struct vsp1_pipeline *pipe = video->rwpf->pipe;
++	struct vsp1_pipeline *pipe = video->rwpf->entity.pipe;
+ 	struct vsp1_vb2_buffer *buf = to_vsp1_vb2_buffer(vbuf);
+ 	unsigned long flags;
+ 	bool empty;
+@@ -877,7 +874,7 @@ static void vsp1_video_cleanup_pipeline(struct vsp1_pipeline *pipe)
+ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
+ {
+ 	struct vsp1_video *video = vb2_get_drv_priv(vq);
+-	struct vsp1_pipeline *pipe = video->rwpf->pipe;
++	struct vsp1_pipeline *pipe = video->rwpf->entity.pipe;
+ 	bool start_pipeline = false;
+ 	unsigned long flags;
+ 	int ret;
+@@ -919,7 +916,7 @@ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
+ static void vsp1_video_stop_streaming(struct vb2_queue *vq)
+ {
+ 	struct vsp1_video *video = vb2_get_drv_priv(vq);
+-	struct vsp1_pipeline *pipe = video->rwpf->pipe;
++	struct vsp1_pipeline *pipe = video->rwpf->entity.pipe;
+ 	unsigned long flags;
+ 	int ret;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1174-media-v4l-vsp1-Use-vsp1_entity.pipe-to-check-if-enti.patch b/patches/1174-media-v4l-vsp1-Use-vsp1_entity.pipe-to-check-if-enti.patch
new file mode 100644
index 00000000000000..ecbfe6aa534649
--- /dev/null
+++ b/patches/1174-media-v4l-vsp1-Use-vsp1_entity.pipe-to-check-if-enti.patch
@@ -0,0 +1,59 @@
+From 6c442a3b398e2de97621b2f2d71a05d60cffe015 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 17:27:47 -0500
+Subject: [PATCH 1174/1795] media: v4l: vsp1: Use vsp1_entity.pipe to check if
+ entity belongs to a pipeline
+
+The DRM pipeline handling code uses the entity's pipe list head to check
+whether the entity is already included in a pipeline. This method is a
+bit fragile in the sense that it uses list_empty() on a list_head that
+is a list member. Replace it by a simpler check for the entity pipe
+pointer.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit d4fedb0b91bc4ea585c029a6e8e0ee3dd4aad741)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index a7ad85ab0b08..e210917fdc3f 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -119,9 +119,9 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 			 * Remove the RPF from the pipe and the list of BRU
+ 			 * inputs.
+ 			 */
+-			WARN_ON(list_empty(&rpf->entity.list_pipe));
++			WARN_ON(!rpf->entity.pipe);
+ 			rpf->entity.pipe = NULL;
+-			list_del_init(&rpf->entity.list_pipe);
++			list_del(&rpf->entity.list_pipe);
+ 			pipe->inputs[i] = NULL;
+ 
+ 			bru->inputs[rpf->bru_input].rpf = NULL;
+@@ -537,7 +537,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 			continue;
+ 		}
+ 
+-		if (list_empty(&rpf->entity.list_pipe)) {
++		if (!rpf->entity.pipe) {
+ 			rpf->entity.pipe = pipe;
+ 			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
+ 		}
+@@ -566,7 +566,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 					   VI6_DPR_NODE_UNUSED);
+ 
+ 			entity->pipe = NULL;
+-			list_del_init(&entity->list_pipe);
++			list_del(&entity->list_pipe);
+ 
+ 			continue;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/1175-media-v4l-vsp1-Share-duplicated-DRM-pipeline-configu.patch b/patches/1175-media-v4l-vsp1-Share-duplicated-DRM-pipeline-configu.patch
new file mode 100644
index 00000000000000..77f28206b752ee
--- /dev/null
+++ b/patches/1175-media-v4l-vsp1-Share-duplicated-DRM-pipeline-configu.patch
@@ -0,0 +1,159 @@
+From ab4809ce971d23c3557553ee957b0625de0c42f9 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 23 Feb 2018 15:35:00 -0500
+Subject: [PATCH 1175/1795] media: v4l: vsp1: Share duplicated DRM pipeline
+ configuration code
+
+Move the duplicated DRM pipeline configuration code to a function and
+call it from vsp1_du_setup_lif() and vsp1_du_atomic_flush().
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit c8c310c99e2d79e3381b33ac4300d6777ddaaa7e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 95 ++++++++++++--------------
+ 1 file changed, 43 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index e210917fdc3f..9a043a915c0b 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -42,6 +42,47 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 		drm_pipe->du_complete(drm_pipe->du_private, completed);
+ }
+ 
++/* -----------------------------------------------------------------------------
++ * Pipeline Configuration
++ */
++
++/* Configure all entities in the pipeline. */
++static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
++{
++	struct vsp1_entity *entity;
++	struct vsp1_entity *next;
++	struct vsp1_dl_list *dl;
++
++	dl = vsp1_dl_list_get(pipe->output->dlm);
++
++	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
++		/* Disconnect unused RPFs from the pipeline. */
++		if (entity->type == VSP1_ENTITY_RPF &&
++		    !pipe->inputs[entity->index]) {
++			vsp1_dl_list_write(dl, entity->route->reg,
++					   VI6_DPR_NODE_UNUSED);
++
++			entity->pipe = NULL;
++			list_del(&entity->list_pipe);
++
++			continue;
++		}
++
++		vsp1_entity_route_setup(entity, pipe, dl);
++
++		if (entity->ops->configure) {
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_INIT);
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_RUNTIME);
++			entity->ops->configure(entity, pipe, dl,
++					       VSP1_ENTITY_PARAMS_PARTITION);
++		}
++	}
++
++	vsp1_dl_list_commit(dl);
++}
++
+ /* -----------------------------------------------------------------------------
+  * DU Driver API
+  */
+@@ -85,9 +126,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_drm_pipeline *drm_pipe;
+ 	struct vsp1_pipeline *pipe;
+ 	struct vsp1_bru *bru;
+-	struct vsp1_entity *entity;
+-	struct vsp1_entity *next;
+-	struct vsp1_dl_list *dl;
+ 	struct v4l2_subdev_format format;
+ 	unsigned long flags;
+ 	unsigned int i;
+@@ -239,22 +277,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
+ 
+ 	/* Configure all entities in the pipeline. */
+-	dl = vsp1_dl_list_get(pipe->output->dlm);
+-
+-	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
+-		vsp1_entity_route_setup(entity, pipe, dl);
+-
+-		if (entity->ops->configure) {
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_INIT);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_RUNTIME);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_PARTITION);
+-		}
+-	}
+-
+-	vsp1_dl_list_commit(dl);
++	vsp1_du_pipeline_configure(pipe);
+ 
+ 	/* Start the pipeline. */
+ 	spin_lock_irqsave(&pipe->irqlock, flags);
+@@ -490,15 +513,9 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 	struct vsp1_pipeline *pipe = &drm_pipe->pipe;
+ 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
+ 	struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
+-	struct vsp1_entity *entity;
+-	struct vsp1_entity *next;
+-	struct vsp1_dl_list *dl;
+ 	unsigned int i;
+ 	int ret;
+ 
+-	/* Prepare the display list. */
+-	dl = vsp1_dl_list_get(pipe->output->dlm);
+-
+ 	/* Count the number of enabled inputs and sort them by Z-order. */
+ 	pipe->num_inputs = 0;
+ 
+@@ -557,33 +574,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 				__func__, rpf->entity.index);
+ 	}
+ 
+-	/* Configure all entities in the pipeline. */
+-	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
+-		/* Disconnect unused RPFs from the pipeline. */
+-		if (entity->type == VSP1_ENTITY_RPF &&
+-		    !pipe->inputs[entity->index]) {
+-			vsp1_dl_list_write(dl, entity->route->reg,
+-					   VI6_DPR_NODE_UNUSED);
+-
+-			entity->pipe = NULL;
+-			list_del(&entity->list_pipe);
+-
+-			continue;
+-		}
+-
+-		vsp1_entity_route_setup(entity, pipe, dl);
+-
+-		if (entity->ops->configure) {
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_INIT);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_RUNTIME);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_PARTITION);
+-		}
+-	}
+-
+-	vsp1_dl_list_commit(dl);
++	vsp1_du_pipeline_configure(pipe);
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1176-media-v4l-vsp1-Move-DRM-atomic-commit-pipeline-setup.patch b/patches/1176-media-v4l-vsp1-Move-DRM-atomic-commit-pipeline-setup.patch
new file mode 100644
index 00000000000000..ac06daa516a3f9
--- /dev/null
+++ b/patches/1176-media-v4l-vsp1-Move-DRM-atomic-commit-pipeline-setup.patch
@@ -0,0 +1,396 @@
+From fffbcd644e98d1a93a31c11cdba2927b7d0ea890 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 23 Feb 2018 15:35:00 -0500
+Subject: [PATCH 1176/1795] media: v4l: vsp1: Move DRM atomic commit pipeline
+ setup to separate function
+
+The DRM pipeline setup code used at atomic commit time is similar to the
+setup code used when enabling the pipeline. Move it to a separate
+function in order to share it.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 02b902fcf64a9b2c0ed1cf74528344afca619f2c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 347 +++++++++++++------------
+ 1 file changed, 180 insertions(+), 167 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 9a043a915c0b..d99278f45bd8 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -46,6 +46,185 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+  * Pipeline Configuration
+  */
+ 
++/* Setup one RPF and the connected BRU sink pad. */
++static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
++				      struct vsp1_pipeline *pipe,
++				      struct vsp1_rwpf *rpf,
++				      unsigned int bru_input)
++{
++	struct v4l2_subdev_selection sel;
++	struct v4l2_subdev_format format;
++	const struct v4l2_rect *crop;
++	int ret;
++
++	/*
++	 * Configure the format on the RPF sink pad and propagate it up to the
++	 * BRU sink pad.
++	 */
++	crop = &vsp1->drm->inputs[rpf->entity.index].crop;
++
++	memset(&format, 0, sizeof(format));
++	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	format.pad = RWPF_PAD_SINK;
++	format.format.width = crop->width + crop->left;
++	format.format.height = crop->height + crop->top;
++	format.format.code = rpf->fmtinfo->mbus;
++	format.format.field = V4L2_FIELD_NONE;
++
++	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev,
++		"%s: set format %ux%u (%x) on RPF%u sink\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, rpf->entity.index);
++
++	memset(&sel, 0, sizeof(sel));
++	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	sel.pad = RWPF_PAD_SINK;
++	sel.target = V4L2_SEL_TGT_CROP;
++	sel.r = *crop;
++
++	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
++			       &sel);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev,
++		"%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
++		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
++		rpf->entity.index);
++
++	/*
++	 * RPF source, hardcode the format to ARGB8888 to turn on format
++	 * conversion if needed.
++	 */
++	format.pad = RWPF_PAD_SOURCE;
++
++	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev,
++		"%s: got format %ux%u (%x) on RPF%u source\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, rpf->entity.index);
++
++	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
++
++	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	/* BRU sink, propagate the format from the RPF source. */
++	format.pad = bru_input;
++
++	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, BRU_NAME(pipe->bru), format.pad);
++
++	sel.pad = bru_input;
++	sel.target = V4L2_SEL_TGT_COMPOSE;
++	sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
++
++	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_selection, NULL,
++			       &sel);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
++		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
++		BRU_NAME(pipe->bru), sel.pad);
++
++	return 0;
++}
++
++static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
++{
++	return vsp1->drm->inputs[rpf->entity.index].zpos;
++}
++
++/* Setup the input side of the pipeline (RPFs and BRU sink pads). */
++static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
++					 struct vsp1_pipeline *pipe)
++{
++	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
++	struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
++	unsigned int i;
++	int ret;
++
++	/* Count the number of enabled inputs and sort them by Z-order. */
++	pipe->num_inputs = 0;
++
++	for (i = 0; i < vsp1->info->rpf_count; ++i) {
++		struct vsp1_rwpf *rpf = vsp1->rpf[i];
++		unsigned int j;
++
++		/*
++		 * Make sure we don't accept more inputs than the hardware can
++		 * handle. This is a temporary fix to avoid display stall, we
++		 * need to instead allocate the BRU or BRS to display pipelines
++		 * dynamically based on the number of planes they each use.
++		 */
++		if (pipe->num_inputs >= pipe->bru->source_pad)
++			pipe->inputs[i] = NULL;
++
++		if (!pipe->inputs[i])
++			continue;
++
++		/* Insert the RPF in the sorted RPFs array. */
++		for (j = pipe->num_inputs++; j > 0; --j) {
++			if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
++				break;
++			inputs[j] = inputs[j-1];
++		}
++
++		inputs[j] = rpf;
++	}
++
++	/* Setup the RPF input pipeline for every enabled input. */
++	for (i = 0; i < pipe->bru->source_pad; ++i) {
++		struct vsp1_rwpf *rpf = inputs[i];
++
++		if (!rpf) {
++			bru->inputs[i].rpf = NULL;
++			continue;
++		}
++
++		if (!rpf->entity.pipe) {
++			rpf->entity.pipe = pipe;
++			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
++		}
++
++		bru->inputs[i].rpf = rpf;
++		rpf->bru_input = i;
++		rpf->entity.sink = pipe->bru;
++		rpf->entity.sink_pad = i;
++
++		dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
++			__func__, rpf->entity.index, BRU_NAME(pipe->bru), i);
++
++		ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, i);
++		if (ret < 0) {
++			dev_err(vsp1->dev,
++				"%s: failed to setup RPF.%u\n",
++				__func__, rpf->entity.index);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
+ /* Configure all entities in the pipeline. */
+ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ {
+@@ -396,111 +575,6 @@ int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
+ 
+-static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1,
+-				  struct vsp1_pipeline *pipe,
+-				  struct vsp1_rwpf *rpf, unsigned int bru_input)
+-{
+-	struct v4l2_subdev_selection sel;
+-	struct v4l2_subdev_format format;
+-	const struct v4l2_rect *crop;
+-	int ret;
+-
+-	/*
+-	 * Configure the format on the RPF sink pad and propagate it up to the
+-	 * BRU sink pad.
+-	 */
+-	crop = &vsp1->drm->inputs[rpf->entity.index].crop;
+-
+-	memset(&format, 0, sizeof(format));
+-	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+-	format.pad = RWPF_PAD_SINK;
+-	format.format.width = crop->width + crop->left;
+-	format.format.height = crop->height + crop->top;
+-	format.format.code = rpf->fmtinfo->mbus;
+-	format.format.field = V4L2_FIELD_NONE;
+-
+-	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev,
+-		"%s: set format %ux%u (%x) on RPF%u sink\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, rpf->entity.index);
+-
+-	memset(&sel, 0, sizeof(sel));
+-	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+-	sel.pad = RWPF_PAD_SINK;
+-	sel.target = V4L2_SEL_TGT_CROP;
+-	sel.r = *crop;
+-
+-	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
+-			       &sel);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev,
+-		"%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
+-		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
+-		rpf->entity.index);
+-
+-	/*
+-	 * RPF source, hardcode the format to ARGB8888 to turn on format
+-	 * conversion if needed.
+-	 */
+-	format.pad = RWPF_PAD_SOURCE;
+-
+-	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev,
+-		"%s: got format %ux%u (%x) on RPF%u source\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, rpf->entity.index);
+-
+-	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
+-
+-	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* BRU sink, propagate the format from the RPF source. */
+-	format.pad = bru_input;
+-
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, BRU_NAME(pipe->bru), format.pad);
+-
+-	sel.pad = bru_input;
+-	sel.target = V4L2_SEL_TGT_COMPOSE;
+-	sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
+-
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_selection, NULL,
+-			       &sel);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
+-		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
+-		BRU_NAME(pipe->bru), sel.pad);
+-
+-	return 0;
+-}
+-
+-static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
+-{
+-	return vsp1->drm->inputs[rpf->entity.index].zpos;
+-}
+-
+ /**
+  * vsp1_du_atomic_flush - Commit an atomic update
+  * @dev: the VSP device
+@@ -511,69 +585,8 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
+ 	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
+ 	struct vsp1_pipeline *pipe = &drm_pipe->pipe;
+-	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
+-	struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
+-	unsigned int i;
+-	int ret;
+-
+-	/* Count the number of enabled inputs and sort them by Z-order. */
+-	pipe->num_inputs = 0;
+-
+-	for (i = 0; i < vsp1->info->rpf_count; ++i) {
+-		struct vsp1_rwpf *rpf = vsp1->rpf[i];
+-		unsigned int j;
+-
+-		/*
+-		 * Make sure we don't accept more inputs than the hardware can
+-		 * handle. This is a temporary fix to avoid display stall, we
+-		 * need to instead allocate the BRU or BRS to display pipelines
+-		 * dynamically based on the number of planes they each use.
+-		 */
+-		if (pipe->num_inputs >= pipe->bru->source_pad)
+-			pipe->inputs[i] = NULL;
+-
+-		if (!pipe->inputs[i])
+-			continue;
+-
+-		/* Insert the RPF in the sorted RPFs array. */
+-		for (j = pipe->num_inputs++; j > 0; --j) {
+-			if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
+-				break;
+-			inputs[j] = inputs[j-1];
+-		}
+-
+-		inputs[j] = rpf;
+-	}
+-
+-	/* Setup the RPF input pipeline for every enabled input. */
+-	for (i = 0; i < pipe->bru->source_pad; ++i) {
+-		struct vsp1_rwpf *rpf = inputs[i];
+-
+-		if (!rpf) {
+-			bru->inputs[i].rpf = NULL;
+-			continue;
+-		}
+-
+-		if (!rpf->entity.pipe) {
+-			rpf->entity.pipe = pipe;
+-			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
+-		}
+-
+-		bru->inputs[i].rpf = rpf;
+-		rpf->bru_input = i;
+-		rpf->entity.sink = pipe->bru;
+-		rpf->entity.sink_pad = i;
+-
+-		dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
+-			__func__, rpf->entity.index, BRU_NAME(pipe->bru), i);
+-
+-		ret = vsp1_du_setup_rpf_pipe(vsp1, pipe, rpf, i);
+-		if (ret < 0)
+-			dev_err(vsp1->dev,
+-				"%s: failed to setup RPF.%u\n",
+-				__func__, rpf->entity.index);
+-	}
+ 
++	vsp1_du_pipeline_setup_inputs(vsp1, pipe);
+ 	vsp1_du_pipeline_configure(pipe);
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
+-- 
+2.19.0
+
diff --git a/patches/1177-media-v4l-vsp1-Setup-BRU-at-atomic-commit-time.patch b/patches/1177-media-v4l-vsp1-Setup-BRU-at-atomic-commit-time.patch
new file mode 100644
index 00000000000000..f13767a6acdb0e
--- /dev/null
+++ b/patches/1177-media-v4l-vsp1-Setup-BRU-at-atomic-commit-time.patch
@@ -0,0 +1,132 @@
+From 03978e6355279b720bebc1acecd0d4b0b861be71 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 14:26:21 -0500
+Subject: [PATCH 1177/1795] media: v4l: vsp1: Setup BRU at atomic commit time
+
+To implement fully dynamic plane assignment to pipelines, we need to
+reassign the BRU and BRS to the DRM pipelines in the atomic commit
+handler. In preparation for this setup factor out the BRU source pad
+code and call it both at LIF setup and atomic commit time.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 7ff667cfe3ae32929856847c2ad085dd2b43c71d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 56 +++++++++++++++++++++++++-
+ drivers/media/platform/vsp1/vsp1_drm.h |  5 +++
+ 2 files changed, 60 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index d99278f45bd8..879eb0eda02f 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -148,12 +148,51 @@ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 	return 0;
+ }
+ 
++/* Setup the BRU source pad. */
++static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
++				      struct vsp1_pipeline *pipe)
++{
++	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
++	struct v4l2_subdev_format format = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++	int ret;
++
++	/*
++	 * Configure the format on the BRU source and verify that it matches the
++	 * requested format. We don't set the media bus code as it is configured
++	 * on the BRU sink pad 0 and propagated inside the entity, not on the
++	 * source pad.
++	 */
++	format.pad = pipe->bru->source_pad;
++	format.format.width = drm_pipe->width;
++	format.format.height = drm_pipe->height;
++	format.format.field = V4L2_FIELD_NONE;
++
++	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, BRU_NAME(pipe->bru), pipe->bru->source_pad);
++
++	if (format.format.width != drm_pipe->width ||
++	    format.format.height != drm_pipe->height) {
++		dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
++		return -EPIPE;
++	}
++
++	return 0;
++}
++
+ static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
+ {
+ 	return vsp1->drm->inputs[rpf->entity.index].zpos;
+ }
+ 
+-/* Setup the input side of the pipeline (RPFs and BRU sink pads). */
++/* Setup the input side of the pipeline (RPFs and BRU). */
+ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 					 struct vsp1_pipeline *pipe)
+ {
+@@ -191,6 +230,18 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 		inputs[j] = rpf;
+ 	}
+ 
++	/*
++	 * Setup the BRU. This must be done before setting up the RPF input
++	 * pipelines as the BRU sink compose rectangles depend on the BRU source
++	 * format.
++	 */
++	ret = vsp1_du_pipeline_setup_bru(vsp1, pipe);
++	if (ret < 0) {
++		dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
++			BRU_NAME(pipe->bru));
++		return ret;
++	}
++
+ 	/* Setup the RPF input pipeline for every enabled input. */
+ 	for (i = 0; i < pipe->bru->source_pad; ++i) {
+ 		struct vsp1_rwpf *rpf = inputs[i];
+@@ -355,6 +406,9 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		return 0;
+ 	}
+ 
++	drm_pipe->width = cfg->width;
++	drm_pipe->height = cfg->height;
++
+ 	dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
+ 		__func__, pipe_index, cfg->width, cfg->height);
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index 9aa19325cbe9..c8dd75ba01f6 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -20,12 +20,17 @@
+ /**
+  * vsp1_drm_pipeline - State for the API exposed to the DRM driver
+  * @pipe: the VSP1 pipeline used for display
++ * @width: output display width
++ * @height: output display height
+  * @du_complete: frame completion callback for the DU driver (optional)
+  * @du_private: data to be passed to the du_complete callback
+  */
+ struct vsp1_drm_pipeline {
+ 	struct vsp1_pipeline pipe;
+ 
++	unsigned int width;
++	unsigned int height;
++
+ 	/* Frame synchronisation */
+ 	void (*du_complete)(void *, bool);
+ 	void *du_private;
+-- 
+2.19.0
+
diff --git a/patches/1178-media-v4l-vsp1-Replace-manual-DRM-pipeline-input-set.patch b/patches/1178-media-v4l-vsp1-Replace-manual-DRM-pipeline-input-set.patch
new file mode 100644
index 00000000000000..0212401b028e27
--- /dev/null
+++ b/patches/1178-media-v4l-vsp1-Replace-manual-DRM-pipeline-input-set.patch
@@ -0,0 +1,88 @@
+From b2732473ecdbdb5043e56a2d9479dbac01947d91 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 14:26:21 -0500
+Subject: [PATCH 1178/1795] media: v4l: vsp1: Replace manual DRM pipeline input
+ setup in vsp1_du_setup_lif
+
+The vsp1_du_setup_lif() function sets up the DRM pipeline input
+manually. This duplicates the code from the
+vsp1_du_pipeline_setup_inputs() function. Replace the manual
+implementation by a call to the function.
+
+As the pipeline has no enabled input in vsp1_du_setup_lif(), the
+vsp1_du_pipeline_setup_inputs() function will not setup any RPF, and
+will thus not setup formats on the BRU sink pads. This isn't a problem
+as all inputs are disabled, and the BRU sink pads will be reconfigured
+from the atomic commit handler when inputs will be enabled.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit b76b3ce55f48d9f2ef8279a92c422962faf749b6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 40 ++++----------------------
+ 1 file changed, 6 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 879eb0eda02f..4a628bbf7e47 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -412,47 +412,19 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
+ 		__func__, pipe_index, cfg->width, cfg->height);
+ 
+-	/*
+-	 * Configure the format at the BRU sinks and propagate it through the
+-	 * pipeline.
+-	 */
++	/* Setup formats through the pipeline. */
++	ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
++	if (ret < 0)
++		return ret;
++
+ 	memset(&format, 0, sizeof(format));
+ 	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+-
+-	for (i = 0; i < pipe->bru->source_pad; ++i) {
+-		format.pad = i;
+-
+-		format.format.width = cfg->width;
+-		format.format.height = cfg->height;
+-		format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
+-		format.format.field = V4L2_FIELD_NONE;
+-
+-		ret = v4l2_subdev_call(&pipe->bru->subdev, pad,
+-				       set_fmt, NULL, &format);
+-		if (ret < 0)
+-			return ret;
+-
+-		dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+-			__func__, format.format.width, format.format.height,
+-			format.format.code, BRU_NAME(pipe->bru), i);
+-	}
+-
+-	format.pad = pipe->bru->source_pad;
++	format.pad = RWPF_PAD_SINK;
+ 	format.format.width = cfg->width;
+ 	format.format.height = cfg->height;
+ 	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
+ 	format.format.field = V4L2_FIELD_NONE;
+ 
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, BRU_NAME(pipe->bru), i);
+-
+-	format.pad = RWPF_PAD_SINK;
+ 	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
+ 			       &format);
+ 	if (ret < 0)
+-- 
+2.19.0
+
diff --git a/patches/1179-media-v4l-vsp1-Move-DRM-pipeline-output-setup-code-t.patch b/patches/1179-media-v4l-vsp1-Move-DRM-pipeline-output-setup-code-t.patch
new file mode 100644
index 00000000000000..cdf4c42dc1dc1f
--- /dev/null
+++ b/patches/1179-media-v4l-vsp1-Move-DRM-pipeline-output-setup-code-t.patch
@@ -0,0 +1,157 @@
+From 9aa13669ba9e40fb7fc14ddf587c3e2720dca093 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 14:26:21 -0500
+Subject: [PATCH 1179/1795] media: v4l: vsp1: Move DRM pipeline output setup
+ code to a function
+
+In order to make the vsp1_du_setup_lif() easier to read, and for
+symmetry with the DRM pipeline input setup, move the pipeline output
+setup code to a separate function.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 5a4d566a5b9b04321df6b6d8637cf0a9285d22cd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 106 ++++++++++++++-----------
+ 1 file changed, 60 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 4a628bbf7e47..a7cccc9b05ef 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -276,6 +276,65 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 	return 0;
+ }
+ 
++/* Setup the output side of the pipeline (WPF and LIF). */
++static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
++					 struct vsp1_pipeline *pipe)
++{
++	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
++	struct v4l2_subdev_format format = { 0, };
++	int ret;
++
++	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	format.pad = RWPF_PAD_SINK;
++	format.format.width = drm_pipe->width;
++	format.format.height = drm_pipe->height;
++	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
++	format.format.field = V4L2_FIELD_NONE;
++
++	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, pipe->output->entity.index);
++
++	format.pad = RWPF_PAD_SOURCE;
++	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, pipe->output->entity.index);
++
++	format.pad = LIF_PAD_SINK;
++	ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
++			       &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code, pipe->lif->index);
++
++	/*
++	 * Verify that the format at the output of the pipeline matches the
++	 * requested frame size and media bus code.
++	 */
++	if (format.format.width != drm_pipe->width ||
++	    format.format.height != drm_pipe->height ||
++	    format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
++		dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
++			pipe->lif->index);
++		return -EPIPE;
++	}
++
++	return 0;
++}
++
+ /* Configure all entities in the pipeline. */
+ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ {
+@@ -356,7 +415,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_drm_pipeline *drm_pipe;
+ 	struct vsp1_pipeline *pipe;
+ 	struct vsp1_bru *bru;
+-	struct v4l2_subdev_format format;
+ 	unsigned long flags;
+ 	unsigned int i;
+ 	int ret;
+@@ -417,54 +475,10 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	memset(&format, 0, sizeof(format));
+-	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+-	format.pad = RWPF_PAD_SINK;
+-	format.format.width = cfg->width;
+-	format.format.height = cfg->height;
+-	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
+-	format.format.field = V4L2_FIELD_NONE;
+-
+-	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, pipe->output->entity.index);
+-
+-	format.pad = RWPF_PAD_SOURCE;
+-	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
+-			       &format);
+-	if (ret < 0)
+-		return ret;
+-
+-	dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, pipe->output->entity.index);
+-
+-	format.pad = LIF_PAD_SINK;
+-	ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
+-			       &format);
++	ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
+-		__func__, format.format.width, format.format.height,
+-		format.format.code, pipe_index);
+-
+-	/*
+-	 * Verify that the format at the output of the pipeline matches the
+-	 * requested frame size and media bus code.
+-	 */
+-	if (format.format.width != cfg->width ||
+-	    format.format.height != cfg->height ||
+-	    format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
+-		dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
+-		return -EPIPE;
+-	}
+-
+ 	/* Enable the VSP1. */
+ 	ret = vsp1_device_get(vsp1);
+ 	if (ret < 0)
+-- 
+2.19.0
+
diff --git a/patches/1180-media-v4l-vsp1-Turn-frame-end-completion-status-into.patch b/patches/1180-media-v4l-vsp1-Turn-frame-end-completion-status-into.patch
new file mode 100644
index 00000000000000..51d4052b31798d
--- /dev/null
+++ b/patches/1180-media-v4l-vsp1-Turn-frame-end-completion-status-into.patch
@@ -0,0 +1,195 @@
+From 247cc6095bec7b931d9d797ffc28b2443ffe047a Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 4 Apr 2018 17:30:49 -0400
+Subject: [PATCH 1180/1795] media: v4l: vsp1: Turn frame end completion status
+ into a bitfield
+
+We will soon need to return more than a boolean completion status from
+the vsp1_dlm_irq_frame_end() IRQ handler. Turn the return value into a
+bitfield to prepare for that. No functional change is introduced here.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit bbc56faf3c04eddaca0d6f022bde31fbae23b6fe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c    | 22 +++++++++++++---------
+ drivers/media/platform/vsp1/vsp1_dl.h    |  4 +++-
+ drivers/media/platform/vsp1/vsp1_drm.c   |  5 +++--
+ drivers/media/platform/vsp1/vsp1_pipe.c  |  8 ++++----
+ drivers/media/platform/vsp1/vsp1_pipe.h  |  2 +-
+ drivers/media/platform/vsp1/vsp1_video.c |  4 ++--
+ 6 files changed, 26 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 0b86ed01e85d..662fa2a347c9 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -616,14 +616,18 @@ void vsp1_dl_list_commit(struct vsp1_dl_list *dl)
+  * vsp1_dlm_irq_frame_end - Display list handler for the frame end interrupt
+  * @dlm: the display list manager
+  *
+- * Return true if the previous display list has completed at frame end, or false
+- * if it has been delayed by one frame because the display list commit raced
+- * with the frame end interrupt. The function always returns true in header mode
+- * as display list processing is then not continuous and races never occur.
++ * Return a set of flags that indicates display list completion status.
++ *
++ * The VSP1_DL_FRAME_END_COMPLETED flag indicates that the previous display list
++ * has completed at frame end. If the flag is not returned display list
++ * completion has been delayed by one frame because the display list commit
++ * raced with the frame end interrupt. The function always returns with the flag
++ * set in header mode as display list processing is then not continuous and
++ * races never occur.
+  */
+-bool vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
++unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ {
+-	bool completed = false;
++	unsigned int flags = 0;
+ 
+ 	spin_lock(&dlm->lock);
+ 
+@@ -634,7 +638,7 @@ bool vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ 	if (dlm->singleshot) {
+ 		__vsp1_dl_list_put(dlm->active);
+ 		dlm->active = NULL;
+-		completed = true;
++		flags |= VSP1_DL_FRAME_END_COMPLETED;
+ 		goto done;
+ 	}
+ 
+@@ -655,7 +659,7 @@ bool vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ 		__vsp1_dl_list_put(dlm->active);
+ 		dlm->active = dlm->queued;
+ 		dlm->queued = NULL;
+-		completed = true;
++		flags |= VSP1_DL_FRAME_END_COMPLETED;
+ 	}
+ 
+ 	/*
+@@ -672,7 +676,7 @@ bool vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ done:
+ 	spin_unlock(&dlm->lock);
+ 
+-	return completed;
++	return flags;
+ }
+ 
+ /* Hardware Setup */
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index ee3508172f0a..cbc2fc53e10b 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -20,6 +20,8 @@ struct vsp1_dl_fragment;
+ struct vsp1_dl_list;
+ struct vsp1_dl_manager;
+ 
++#define VSP1_DL_FRAME_END_COMPLETED		BIT(0)
++
+ void vsp1_dlm_setup(struct vsp1_device *vsp1);
+ 
+ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+@@ -27,7 +29,7 @@ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 					unsigned int prealloc);
+ void vsp1_dlm_destroy(struct vsp1_dl_manager *dlm);
+ void vsp1_dlm_reset(struct vsp1_dl_manager *dlm);
+-bool vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
++unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
+ 
+ struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm);
+ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index a7cccc9b05ef..541473b1df67 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -34,12 +34,13 @@
+  */
+ 
+ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+-				       bool completed)
++				       unsigned int completion)
+ {
+ 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+ 
+ 	if (drm_pipe->du_complete)
+-		drm_pipe->du_complete(drm_pipe->du_private, completed);
++		drm_pipe->du_complete(drm_pipe->du_private,
++				      completion & VSP1_DL_FRAME_END_COMPLETED);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index 99ccbac3256a..1134f14ed4aa 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -315,17 +315,17 @@ bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
+ 
+ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
+ {
+-	bool completed;
++	unsigned int flags;
+ 
+ 	if (pipe == NULL)
+ 		return;
+ 
+ 	/*
+ 	 * If the DL commit raced with the frame end interrupt, the commit ends
+-	 * up being postponed by one frame. @completed represents whether the
++	 * up being postponed by one frame. The returned flags tell whether the
+ 	 * active frame was finished or postponed.
+ 	 */
+-	completed = vsp1_dlm_irq_frame_end(pipe->output->dlm);
++	flags = vsp1_dlm_irq_frame_end(pipe->output->dlm);
+ 
+ 	if (pipe->hgo)
+ 		vsp1_hgo_frame_end(pipe->hgo);
+@@ -338,7 +338,7 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
+ 	 * frame_end to account for vblank events.
+ 	 */
+ 	if (pipe->frame_end)
+-		pipe->frame_end(pipe, completed);
++		pipe->frame_end(pipe, flags);
+ 
+ 	pipe->sequence++;
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index dfff9b5685fe..412da67527c0 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -118,7 +118,7 @@ struct vsp1_pipeline {
+ 	enum vsp1_pipeline_state state;
+ 	wait_queue_head_t wq;
+ 
+-	void (*frame_end)(struct vsp1_pipeline *pipe, bool completed);
++	void (*frame_end)(struct vsp1_pipeline *pipe, unsigned int completion);
+ 
+ 	struct mutex lock;
+ 	struct kref kref;
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index e88be9cd2a0f..fd600d23ab23 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -444,7 +444,7 @@ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+ }
+ 
+ static void vsp1_video_pipeline_frame_end(struct vsp1_pipeline *pipe,
+-					  bool completed)
++					  unsigned int completion)
+ {
+ 	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
+ 	enum vsp1_pipeline_state state;
+@@ -452,7 +452,7 @@ static void vsp1_video_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 	unsigned int i;
+ 
+ 	/* M2M Pipelines should never call here with an incomplete frame. */
+-	WARN_ON_ONCE(!completed);
++	WARN_ON_ONCE(!(completion & VSP1_DL_FRAME_END_COMPLETED));
+ 
+ 	spin_lock_irqsave(&pipe->irqlock, flags);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1181-media-v4l-vsp1-Add-per-display-list-internal-complet.patch b/patches/1181-media-v4l-vsp1-Add-per-display-list-internal-complet.patch
new file mode 100644
index 00000000000000..5cbe9726540da0
--- /dev/null
+++ b/patches/1181-media-v4l-vsp1-Add-per-display-list-internal-complet.patch
@@ -0,0 +1,154 @@
+From d1db3eba931ce3b825725e090d7a2ce955582946 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 14:26:21 -0500
+Subject: [PATCH 1181/1795] media: v4l: vsp1: Add per-display list internal
+ completion notification support
+
+Display list completion is already reported to the frame end handler,
+but that mechanism is global to all display lists. In order to implement
+BRU and BRS reassignment in DRM pipelines we will need to commit a
+display list and wait for its completion internally, without reporting
+it to the DRM driver. Extend the display list API to support such an
+internal use of the display list.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit bc3c9c8802b8d87e46715f23f1b0d3588cd8c5c4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c    | 23 ++++++++++++++++++++++-
+ drivers/media/platform/vsp1/vsp1_dl.h    |  3 ++-
+ drivers/media/platform/vsp1/vsp1_drm.c   |  2 +-
+ drivers/media/platform/vsp1/vsp1_video.c |  2 +-
+ 4 files changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 662fa2a347c9..30ad491605ff 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -72,6 +72,7 @@ struct vsp1_dl_body {
+  * @fragments: list of extra display list bodies
+  * @has_chain: if true, indicates that there's a partition chain
+  * @chain: entry in the display list partition chain
++ * @internal: whether the display list is used for internal purpose
+  */
+ struct vsp1_dl_list {
+ 	struct list_head list;
+@@ -85,6 +86,8 @@ struct vsp1_dl_list {
+ 
+ 	bool has_chain;
+ 	struct list_head chain;
++
++	bool internal;
+ };
+ 
+ enum vsp1_dl_mode {
+@@ -550,8 +553,16 @@ static void vsp1_dl_list_commit_continuous(struct vsp1_dl_list *dl)
+ 	 * case we can't replace the queued list by the new one, as we could
+ 	 * race with the hardware. We thus mark the update as pending, it will
+ 	 * be queued up to the hardware by the frame end interrupt handler.
++	 *
++	 * If a display list is already pending we simply drop it as the new
++	 * display list is assumed to contain a more recent configuration. It is
++	 * an error if the already pending list has the internal flag set, as
++	 * there is then a process waiting for that list to complete. This
++	 * shouldn't happen as the waiting process should perform proper
++	 * locking, but warn just in case.
+ 	 */
+ 	if (vsp1_dl_list_hw_update_pending(dlm)) {
++		WARN_ON(dlm->pending && dlm->pending->internal);
+ 		__vsp1_dl_list_put(dlm->pending);
+ 		dlm->pending = dl;
+ 		return;
+@@ -581,7 +592,7 @@ static void vsp1_dl_list_commit_singleshot(struct vsp1_dl_list *dl)
+ 	dlm->active = dl;
+ }
+ 
+-void vsp1_dl_list_commit(struct vsp1_dl_list *dl)
++void vsp1_dl_list_commit(struct vsp1_dl_list *dl, bool internal)
+ {
+ 	struct vsp1_dl_manager *dlm = dl->dlm;
+ 	struct vsp1_dl_list *dl_child;
+@@ -598,6 +609,8 @@ void vsp1_dl_list_commit(struct vsp1_dl_list *dl)
+ 		}
+ 	}
+ 
++	dl->internal = internal;
++
+ 	spin_lock_irqsave(&dlm->lock, flags);
+ 
+ 	if (dlm->singleshot)
+@@ -624,6 +637,10 @@ void vsp1_dl_list_commit(struct vsp1_dl_list *dl)
+  * raced with the frame end interrupt. The function always returns with the flag
+  * set in header mode as display list processing is then not continuous and
+  * races never occur.
++ *
++ * The VSP1_DL_FRAME_END_INTERNAL flag indicates that the previous display list
++ * has completed and had been queued with the internal notification flag.
++ * Internal notification is only supported for continuous mode.
+  */
+ unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ {
+@@ -656,6 +673,10 @@ unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
+ 	 * frame end interrupt. The display list thus becomes active.
+ 	 */
+ 	if (dlm->queued) {
++		if (dlm->queued->internal)
++			flags |= VSP1_DL_FRAME_END_INTERNAL;
++		dlm->queued->internal = false;
++
+ 		__vsp1_dl_list_put(dlm->active);
+ 		dlm->active = dlm->queued;
+ 		dlm->queued = NULL;
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index cbc2fc53e10b..1a5bbd5ddb7b 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -21,6 +21,7 @@ struct vsp1_dl_list;
+ struct vsp1_dl_manager;
+ 
+ #define VSP1_DL_FRAME_END_COMPLETED		BIT(0)
++#define VSP1_DL_FRAME_END_INTERNAL		BIT(1)
+ 
+ void vsp1_dlm_setup(struct vsp1_device *vsp1);
+ 
+@@ -34,7 +35,7 @@ unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
+ struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm);
+ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data);
+-void vsp1_dl_list_commit(struct vsp1_dl_list *dl);
++void vsp1_dl_list_commit(struct vsp1_dl_list *dl, bool internal);
+ 
+ struct vsp1_dl_body *vsp1_dl_fragment_alloc(struct vsp1_device *vsp1,
+ 					    unsigned int num_entries);
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 541473b1df67..68b126044ea1 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -370,7 +370,7 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 		}
+ 	}
+ 
+-	vsp1_dl_list_commit(dl);
++	vsp1_dl_list_commit(dl, false);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index fd600d23ab23..c4b572712d76 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -437,7 +437,7 @@ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+ 	}
+ 
+ 	/* Complete, and commit the head display list. */
+-	vsp1_dl_list_commit(pipe->dl);
++	vsp1_dl_list_commit(pipe->dl, false);
+ 	pipe->dl = NULL;
+ 
+ 	vsp1_pipeline_run(pipe);
+-- 
+2.19.0
+
diff --git a/patches/1182-media-v4l-vsp1-Generalize-detection-of-entity-remova.patch b/patches/1182-media-v4l-vsp1-Generalize-detection-of-entity-remova.patch
new file mode 100644
index 00000000000000..cf5e8c55455b7b
--- /dev/null
+++ b/patches/1182-media-v4l-vsp1-Generalize-detection-of-entity-remova.patch
@@ -0,0 +1,65 @@
+From f8f61b831403086258d3fb880393e1769770d3f0 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Mon, 26 Feb 2018 04:22:40 -0500
+Subject: [PATCH 1182/1795] media: v4l: vsp1: Generalize detection of entity
+ removal from DRM pipeline
+
+When disabling a DRM plane, the corresponding RPF is only marked as
+removed from the pipeline in the atomic update handler, with the actual
+removal happening when configuring the pipeline at atomic commit time.
+This is required as the RPF has to be disabled in the hardware, which
+can't be done from the atomic update handler.
+
+The current implementation is RPF-specific. Make it independent of the
+entity type by using the entity's pipe pointer to mark removal from the
+pipeline. This will allow using the mechanism to remove BRU instances.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 1dd72ee923b7ed96abe15b2cb09aa5d85315871e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 68b126044ea1..a9c53892a9ea 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -346,13 +346,12 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 	dl = vsp1_dl_list_get(pipe->output->dlm);
+ 
+ 	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
+-		/* Disconnect unused RPFs from the pipeline. */
+-		if (entity->type == VSP1_ENTITY_RPF &&
+-		    !pipe->inputs[entity->index]) {
++		/* Disconnect unused entities from the pipeline. */
++		if (!entity->pipe) {
+ 			vsp1_dl_list_write(dl, entity->route->reg,
+ 					   VI6_DPR_NODE_UNUSED);
+ 
+-			entity->pipe = NULL;
++			entity->sink = NULL;
+ 			list_del(&entity->list_pipe);
+ 
+ 			continue;
+@@ -569,10 +568,11 @@ int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
+ 			rpf_index);
+ 
+ 		/*
+-		 * Remove the RPF from the pipe's inputs. The atomic flush
+-		 * handler will disable the input and remove the entity from the
+-		 * pipe's entities list.
++		 * Remove the RPF from the pipeline's inputs. Keep it in the
++		 * pipeline's entity list to let vsp1_du_pipeline_configure()
++		 * remove it from the hardware pipeline.
+ 		 */
++		rpf->entity.pipe = NULL;
+ 		drm_pipe->pipe.inputs[rpf_index] = NULL;
+ 		return 0;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1183-media-v4l-vsp1-Assign-BRU-and-BRS-to-pipelines-dynam.patch b/patches/1183-media-v4l-vsp1-Assign-BRU-and-BRS-to-pipelines-dynam.patch
new file mode 100644
index 00000000000000..dd011aec1dc298
--- /dev/null
+++ b/patches/1183-media-v4l-vsp1-Assign-BRU-and-BRS-to-pipelines-dynam.patch
@@ -0,0 +1,394 @@
+From 69ecdcac3dac404ec96faaafb799f3fe39a3ac23 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 22 Feb 2018 14:26:21 -0500
+Subject: [PATCH 1183/1795] media: v4l: vsp1: Assign BRU and BRS to pipelines
+ dynamically
+
+The VSPDL variant drives two DU channels through two LIF and two
+blenders, BRU and BRS. The DU channels thus share the five available
+VSPDL inputs and expose them as five KMS planes.
+
+The current implementation assigns the BRS to the second LIF and thus
+artificially limits the number of planes for the second display channel
+to two at most.
+
+Lift this artificial limitation by assigning the BRU and BRS to the
+display pipelines on demand based on the number of planes used by each
+pipeline. When a display pipeline needs more than two inputs and the BRU
+is already in use by the other pipeline, this requires reconfiguring the
+other pipeline to free the BRU before processing, which can result in
+frame drop on both pipelines.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit f81f9adc4ee1e94a38a9059f6291feea74f184e5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 161 +++++++++++++++++++++----
+ drivers/media/platform/vsp1/vsp1_drm.h |   9 ++
+ 2 files changed, 144 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index a9c53892a9ea..f82f83b6d4ff 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -37,10 +37,15 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 				       unsigned int completion)
+ {
+ 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
++	bool complete = completion == VSP1_DL_FRAME_END_COMPLETED;
+ 
+ 	if (drm_pipe->du_complete)
+-		drm_pipe->du_complete(drm_pipe->du_private,
+-				      completion & VSP1_DL_FRAME_END_COMPLETED);
++		drm_pipe->du_complete(drm_pipe->du_private, complete);
++
++	if (completion & VSP1_DL_FRAME_END_INTERNAL) {
++		drm_pipe->force_bru_release = false;
++		wake_up(&drm_pipe->wait_queue);
++	}
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -150,6 +155,10 @@ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ }
+ 
+ /* Setup the BRU source pad. */
++static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
++					 struct vsp1_pipeline *pipe);
++static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
++
+ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 				      struct vsp1_pipeline *pipe)
+ {
+@@ -157,8 +166,93 @@ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 	struct v4l2_subdev_format format = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ 	};
++	struct vsp1_entity *bru;
+ 	int ret;
+ 
++	/*
++	 * Pick a BRU:
++	 * - If we need more than two inputs, use the main BRU.
++	 * - Otherwise, if we are not forced to release our BRU, keep it.
++	 * - Else, use any free BRU (randomly starting with the main BRU).
++	 */
++	if (pipe->num_inputs > 2)
++		bru = &vsp1->bru->entity;
++	else if (pipe->bru && !drm_pipe->force_bru_release)
++		bru = pipe->bru;
++	else if (!vsp1->bru->entity.pipe)
++		bru = &vsp1->bru->entity;
++	else
++		bru = &vsp1->brs->entity;
++
++	/* Switch BRU if needed. */
++	if (bru != pipe->bru) {
++		struct vsp1_entity *released_bru = NULL;
++
++		/* Release our BRU if we have one. */
++		if (pipe->bru) {
++			/*
++			 * The BRU might be acquired by the other pipeline in
++			 * the next step. We must thus remove it from the list
++			 * of entities for this pipeline. The other pipeline's
++			 * hardware configuration will reconfigure the BRU
++			 * routing.
++			 *
++			 * However, if the other pipeline doesn't acquire our
++			 * BRU, we need to keep it in the list, otherwise the
++			 * hardware configuration step won't disconnect it from
++			 * the pipeline. To solve this, store the released BRU
++			 * pointer to add it back to the list of entities later
++			 * if it isn't acquired by the other pipeline.
++			 */
++			released_bru = pipe->bru;
++
++			list_del(&pipe->bru->list_pipe);
++			pipe->bru->sink = NULL;
++			pipe->bru->pipe = NULL;
++			pipe->bru = NULL;
++		}
++
++		/*
++		 * If the BRU we need is in use, force the owner pipeline to
++		 * switch to the other BRU and wait until the switch completes.
++		 */
++		if (bru->pipe) {
++			struct vsp1_drm_pipeline *owner_pipe;
++
++			owner_pipe = to_vsp1_drm_pipeline(bru->pipe);
++			owner_pipe->force_bru_release = true;
++
++			vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
++			vsp1_du_pipeline_configure(&owner_pipe->pipe);
++
++			ret = wait_event_timeout(owner_pipe->wait_queue,
++						 !owner_pipe->force_bru_release,
++						 msecs_to_jiffies(500));
++			if (ret == 0)
++				dev_warn(vsp1->dev,
++					 "DRM pipeline %u reconfiguration timeout\n",
++					 owner_pipe->pipe.lif->index);
++		}
++
++		/*
++		 * If the BRU we have released previously hasn't been acquired
++		 * by the other pipeline, add it back to the entities list (with
++		 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
++		 * disconnect it from the hardware pipeline.
++		 */
++		if (released_bru && !released_bru->pipe)
++			list_add_tail(&released_bru->list_pipe,
++				      &pipe->entities);
++
++		/* Add the BRU to the pipeline. */
++		pipe->bru = bru;
++		pipe->bru->pipe = pipe;
++		pipe->bru->sink = &pipe->output->entity;
++		pipe->bru->sink_pad = 0;
++
++		list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
++	}
++
+ 	/*
+ 	 * Configure the format on the BRU source and verify that it matches the
+ 	 * requested format. We don't set the media bus code as it is configured
+@@ -198,7 +292,7 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 					 struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
+-	struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
++	struct vsp1_bru *bru;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -209,15 +303,6 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 		struct vsp1_rwpf *rpf = vsp1->rpf[i];
+ 		unsigned int j;
+ 
+-		/*
+-		 * Make sure we don't accept more inputs than the hardware can
+-		 * handle. This is a temporary fix to avoid display stall, we
+-		 * need to instead allocate the BRU or BRS to display pipelines
+-		 * dynamically based on the number of planes they each use.
+-		 */
+-		if (pipe->num_inputs >= pipe->bru->source_pad)
+-			pipe->inputs[i] = NULL;
+-
+ 		if (!pipe->inputs[i])
+ 			continue;
+ 
+@@ -243,6 +328,8 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 		return ret;
+ 	}
+ 
++	bru = to_bru(&pipe->bru->subdev);
++
+ 	/* Setup the RPF input pipeline for every enabled input. */
+ 	for (i = 0; i < pipe->bru->source_pad; ++i) {
+ 		struct vsp1_rwpf *rpf = inputs[i];
+@@ -339,6 +426,7 @@ static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
+ /* Configure all entities in the pipeline. */
+ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ {
++	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+ 	struct vsp1_entity *entity;
+ 	struct vsp1_entity *next;
+ 	struct vsp1_dl_list *dl;
+@@ -369,7 +457,7 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 		}
+ 	}
+ 
+-	vsp1_dl_list_commit(dl, false);
++	vsp1_dl_list_commit(dl, drm_pipe->force_bru_release);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -414,7 +502,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
+ 	struct vsp1_drm_pipeline *drm_pipe;
+ 	struct vsp1_pipeline *pipe;
+-	struct vsp1_bru *bru;
+ 	unsigned long flags;
+ 	unsigned int i;
+ 	int ret;
+@@ -424,9 +511,14 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 
+ 	drm_pipe = &vsp1->drm->pipe[pipe_index];
+ 	pipe = &drm_pipe->pipe;
+-	bru = to_bru(&pipe->bru->subdev);
+ 
+ 	if (!cfg) {
++		struct vsp1_bru *bru;
++
++		mutex_lock(&vsp1->drm->lock);
++
++		bru = to_bru(&pipe->bru->subdev);
++
+ 		/*
+ 		 * NULL configuration means the CRTC is being disabled, stop
+ 		 * the pipeline and turn the light off.
+@@ -456,6 +548,12 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		drm_pipe->du_complete = NULL;
+ 		pipe->num_inputs = 0;
+ 
++		list_del(&pipe->bru->list_pipe);
++		pipe->bru->pipe = NULL;
++		pipe->bru = NULL;
++
++		mutex_unlock(&vsp1->drm->lock);
++
+ 		vsp1_dlm_reset(pipe->output->dlm);
+ 		vsp1_device_put(vsp1);
+ 
+@@ -470,19 +568,21 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
+ 		__func__, pipe_index, cfg->width, cfg->height);
+ 
++	mutex_lock(&vsp1->drm->lock);
++
+ 	/* Setup formats through the pipeline. */
+ 	ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
+ 	if (ret < 0)
+-		return ret;
++		goto unlock;
+ 
+ 	ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
+ 	if (ret < 0)
+-		return ret;
++		goto unlock;
+ 
+ 	/* Enable the VSP1. */
+ 	ret = vsp1_device_get(vsp1);
+ 	if (ret < 0)
+-		return ret;
++		goto unlock;
+ 
+ 	/*
+ 	 * Register a callback to allow us to notify the DRM driver of frame
+@@ -498,6 +598,12 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	/* Configure all entities in the pipeline. */
+ 	vsp1_du_pipeline_configure(pipe);
+ 
++unlock:
++	mutex_unlock(&vsp1->drm->lock);
++
++	if (ret < 0)
++		return ret;
++
+ 	/* Start the pipeline. */
+ 	spin_lock_irqsave(&pipe->irqlock, flags);
+ 	vsp1_pipeline_run(pipe);
+@@ -516,6 +622,9 @@ EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
+  */
+ void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
+ {
++	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
++
++	mutex_lock(&vsp1->drm->lock);
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
+ 
+@@ -629,6 +738,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
+ 
+ 	vsp1_du_pipeline_setup_inputs(vsp1, pipe);
+ 	vsp1_du_pipeline_configure(pipe);
++	mutex_unlock(&vsp1->drm->lock);
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
+ 
+@@ -667,28 +777,26 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
+ 	if (!vsp1->drm)
+ 		return -ENOMEM;
+ 
++	mutex_init(&vsp1->drm->lock);
++
+ 	/* Create one DRM pipeline per LIF. */
+ 	for (i = 0; i < vsp1->info->lif_count; ++i) {
+ 		struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
+ 		struct vsp1_pipeline *pipe = &drm_pipe->pipe;
+ 
++		init_waitqueue_head(&drm_pipe->wait_queue);
++
+ 		vsp1_pipeline_init(pipe);
+ 
+ 		pipe->frame_end = vsp1_du_pipeline_frame_end;
+ 
+ 		/*
+-		 * The DRM pipeline is static, add entities manually. The first
+-		 * pipeline uses the BRU and the second pipeline the BRS.
++		 * The output side of the DRM pipeline is static, add the
++		 * corresponding entities manually.
+ 		 */
+-		pipe->bru = i == 0 ? &vsp1->bru->entity : &vsp1->brs->entity;
+ 		pipe->output = vsp1->wpf[i];
+ 		pipe->lif = &vsp1->lif[i]->entity;
+ 
+-		pipe->bru->pipe = pipe;
+-		pipe->bru->sink = &pipe->output->entity;
+-		pipe->bru->sink_pad = 0;
+-		list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
+-
+ 		pipe->output->entity.pipe = pipe;
+ 		pipe->output->entity.sink = pipe->lif;
+ 		pipe->output->entity.sink_pad = 0;
+@@ -710,4 +818,5 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
+ 
+ void vsp1_drm_cleanup(struct vsp1_device *vsp1)
+ {
++	mutex_destroy(&vsp1->drm->lock);
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index c8dd75ba01f6..c84bc1c456c0 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -13,7 +13,9 @@
+ #ifndef __VSP1_DRM_H__
+ #define __VSP1_DRM_H__
+ 
++#include <linux/mutex.h>
+ #include <linux/videodev2.h>
++#include <linux/wait.h>
+ 
+ #include "vsp1_pipe.h"
+ 
+@@ -22,6 +24,8 @@
+  * @pipe: the VSP1 pipeline used for display
+  * @width: output display width
+  * @height: output display height
++ * @force_bru_release: when set, release the BRU during the next reconfiguration
++ * @wait_queue: wait queue to wait for BRU release completion
+  * @du_complete: frame completion callback for the DU driver (optional)
+  * @du_private: data to be passed to the du_complete callback
+  */
+@@ -31,6 +35,9 @@ struct vsp1_drm_pipeline {
+ 	unsigned int width;
+ 	unsigned int height;
+ 
++	bool force_bru_release;
++	wait_queue_head_t wait_queue;
++
+ 	/* Frame synchronisation */
+ 	void (*du_complete)(void *, bool);
+ 	void *du_private;
+@@ -39,11 +46,13 @@ struct vsp1_drm_pipeline {
+ /**
+  * vsp1_drm - State for the API exposed to the DRM driver
+  * @pipe: the VSP1 DRM pipeline used for display
++ * @lock: protects the BRU and BRS allocation
+  * @inputs: source crop rectangle, destination compose rectangle and z-order
+  *	position for every input (indexed by RPF index)
+  */
+ struct vsp1_drm {
+ 	struct vsp1_drm_pipeline pipe[VSP1_MAX_LIF];
++	struct mutex lock;
+ 
+ 	struct {
+ 		struct v4l2_rect crop;
+-- 
+2.19.0
+
diff --git a/patches/1184-media-v4l-vsp1-Add-BRx-dynamic-assignment-debugging-.patch b/patches/1184-media-v4l-vsp1-Add-BRx-dynamic-assignment-debugging-.patch
new file mode 100644
index 00000000000000..5e4f5b7811fd52
--- /dev/null
+++ b/patches/1184-media-v4l-vsp1-Add-BRx-dynamic-assignment-debugging-.patch
@@ -0,0 +1,70 @@
+From 1bf5f000b8c1aa485d0272dc54efb0d6b6efe7e5 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 23 Feb 2018 18:58:48 -0500
+Subject: [PATCH 1184/1795] media: v4l: vsp1: Add BRx dynamic assignment
+ debugging messages
+
+Dynamic assignment of the BRU and BRS to pipelines is prone to
+regressions, add messages to make debugging easier. Keep it as a
+separate commit to ease removal of those messages once the code will
+deem to be completely stable.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Acked-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit dc3eaba4ee3debc1baa4a0e148cc7521f45d773b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index f82f83b6d4ff..b43d6dc0d5f5 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -190,6 +190,10 @@ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 
+ 		/* Release our BRU if we have one. */
+ 		if (pipe->bru) {
++			dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
++				__func__, pipe->lif->index,
++				BRU_NAME(pipe->bru));
++
+ 			/*
+ 			 * The BRU might be acquired by the other pipeline in
+ 			 * the next step. We must thus remove it from the list
+@@ -219,6 +223,9 @@ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 		if (bru->pipe) {
+ 			struct vsp1_drm_pipeline *owner_pipe;
+ 
++			dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
++				__func__, pipe->lif->index, BRU_NAME(bru));
++
+ 			owner_pipe = to_vsp1_drm_pipeline(bru->pipe);
+ 			owner_pipe->force_bru_release = true;
+ 
+@@ -245,6 +252,9 @@ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 				      &pipe->entities);
+ 
+ 		/* Add the BRU to the pipeline. */
++		dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
++			__func__, pipe->lif->index, BRU_NAME(bru));
++
+ 		pipe->bru = bru;
+ 		pipe->bru->pipe = pipe;
+ 		pipe->bru->sink = &pipe->output->entity;
+@@ -548,6 +558,10 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		drm_pipe->du_complete = NULL;
+ 		pipe->num_inputs = 0;
+ 
++		dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
++			__func__, pipe->lif->index,
++			BRU_NAME(pipe->bru));
++
+ 		list_del(&pipe->bru->list_pipe);
+ 		pipe->bru->pipe = NULL;
+ 		pipe->bru = NULL;
+-- 
+2.19.0
+
diff --git a/patches/1185-media-v4l-vsp1-Rename-BRU-to-BRx.patch b/patches/1185-media-v4l-vsp1-Rename-BRU-to-BRx.patch
new file mode 100644
index 00000000000000..a5521f0f5b2872
--- /dev/null
+++ b/patches/1185-media-v4l-vsp1-Rename-BRU-to-BRx.patch
@@ -0,0 +1,1311 @@
+From c154488bc20e8f623db0c19f0a024bd079575bdc Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Mon, 26 Feb 2018 11:06:21 -0500
+Subject: [PATCH 1185/1795] media: v4l: vsp1: Rename BRU to BRx
+
+Some VSP instances have two blending units named BRU (Blend/ROP Unit)
+and BRS (Blend/ROP Sub unit). The BRS is a smaller version of the BRU
+with only two inputs, but otherwise offers similar features and offers
+the same register interface. The BRU and BRS can be used exchangeably in
+VSP pipelines (provided no more than two inputs are needed).
+
+Due to historical reasons, the VSP1 driver implements support for both
+the BRU and BRS through objects named vsp1_bru. The code uses the name
+BRU to refer to either the BRU or the BRS, except in a few places where
+noted explicitly. This creates confusion.
+
+In an effort to avoid confusion, rename the vsp1_bru object and the
+corresponding API to vsp1_brx, and use BRx to refer to blend unit
+instances regardless of their type. The names BRU and BRS are retained
+where reference to a particular blend unit type is needed, as well as in
+hardware registers to stay close to the datasheet.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Acked-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit cbb7fa49c7466b19e984f3c87d2a07f5b56a1764)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/Makefile          |   2 +-
+ drivers/media/platform/vsp1/vsp1.h            |   6 +-
+ .../platform/vsp1/{vsp1_bru.c => vsp1_brx.c}  | 202 +++++++++---------
+ .../platform/vsp1/{vsp1_bru.h => vsp1_brx.h}  |  18 +-
+ drivers/media/platform/vsp1/vsp1_drm.c        | 174 +++++++--------
+ drivers/media/platform/vsp1/vsp1_drm.h        |   6 +-
+ drivers/media/platform/vsp1/vsp1_drv.c        |   6 +-
+ drivers/media/platform/vsp1/vsp1_pipe.c       |  12 +-
+ drivers/media/platform/vsp1/vsp1_pipe.h       |   4 +-
+ drivers/media/platform/vsp1/vsp1_rpf.c        |  12 +-
+ drivers/media/platform/vsp1/vsp1_rwpf.h       |   2 +-
+ drivers/media/platform/vsp1/vsp1_video.c      |  16 +-
+ drivers/media/platform/vsp1/vsp1_wpf.c        |   8 +-
+ 13 files changed, 234 insertions(+), 234 deletions(-)
+ rename drivers/media/platform/vsp1/{vsp1_bru.c => vsp1_brx.c} (63%)
+ rename drivers/media/platform/vsp1/{vsp1_bru.h => vsp1_brx.h} (66%)
+
+diff --git a/drivers/media/platform/vsp1/Makefile b/drivers/media/platform/vsp1/Makefile
+index f5cd6f0491cb..596775f932c0 100644
+--- a/drivers/media/platform/vsp1/Makefile
++++ b/drivers/media/platform/vsp1/Makefile
+@@ -3,7 +3,7 @@ vsp1-y					:= vsp1_drv.o vsp1_entity.o vsp1_pipe.o
+ vsp1-y					+= vsp1_dl.o vsp1_drm.o vsp1_video.o
+ vsp1-y					+= vsp1_rpf.o vsp1_rwpf.o vsp1_wpf.o
+ vsp1-y					+= vsp1_clu.o vsp1_hsit.o vsp1_lut.o
+-vsp1-y					+= vsp1_bru.o vsp1_sru.o vsp1_uds.o
++vsp1-y					+= vsp1_brx.o vsp1_sru.o vsp1_uds.o
+ vsp1-y					+= vsp1_hgo.o vsp1_hgt.o vsp1_histo.o
+ vsp1-y					+= vsp1_lif.o
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h
+index 78ef838416b3..894cc725c2d4 100644
+--- a/drivers/media/platform/vsp1/vsp1.h
++++ b/drivers/media/platform/vsp1/vsp1.h
+@@ -30,7 +30,7 @@ struct rcar_fcp_device;
+ struct vsp1_drm;
+ struct vsp1_entity;
+ struct vsp1_platform_data;
+-struct vsp1_bru;
++struct vsp1_brx;
+ struct vsp1_clu;
+ struct vsp1_hgo;
+ struct vsp1_hgt;
+@@ -78,8 +78,8 @@ struct vsp1_device {
+ 	struct rcar_fcp_device *fcp;
+ 	struct device *bus_master;
+ 
+-	struct vsp1_bru *brs;
+-	struct vsp1_bru *bru;
++	struct vsp1_brx *brs;
++	struct vsp1_brx *bru;
+ 	struct vsp1_clu *clu;
+ 	struct vsp1_hgo *hgo;
+ 	struct vsp1_hgt *hgt;
+diff --git a/drivers/media/platform/vsp1/vsp1_bru.c b/drivers/media/platform/vsp1/vsp1_brx.c
+similarity index 63%
+rename from drivers/media/platform/vsp1/vsp1_bru.c
+rename to drivers/media/platform/vsp1/vsp1_brx.c
+index e8fd2ae3b3eb..b4af1d546022 100644
+--- a/drivers/media/platform/vsp1/vsp1_bru.c
++++ b/drivers/media/platform/vsp1/vsp1_brx.c
+@@ -1,5 +1,5 @@
+ /*
+- * vsp1_bru.c  --  R-Car VSP1 Blend ROP Unit
++ * vsp1_brx.c  --  R-Car VSP1 Blend ROP Unit (BRU and BRS)
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+@@ -17,45 +17,45 @@
+ #include <media/v4l2-subdev.h>
+ 
+ #include "vsp1.h"
+-#include "vsp1_bru.h"
++#include "vsp1_brx.h"
+ #include "vsp1_dl.h"
+ #include "vsp1_pipe.h"
+ #include "vsp1_rwpf.h"
+ #include "vsp1_video.h"
+ 
+-#define BRU_MIN_SIZE				1U
+-#define BRU_MAX_SIZE				8190U
++#define BRX_MIN_SIZE				1U
++#define BRX_MAX_SIZE				8190U
+ 
+ /* -----------------------------------------------------------------------------
+  * Device Access
+  */
+ 
+-static inline void vsp1_bru_write(struct vsp1_bru *bru, struct vsp1_dl_list *dl,
++static inline void vsp1_brx_write(struct vsp1_brx *brx, struct vsp1_dl_list *dl,
+ 				  u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, bru->base + reg, data);
++	vsp1_dl_list_write(dl, brx->base + reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+  * Controls
+  */
+ 
+-static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
++static int brx_s_ctrl(struct v4l2_ctrl *ctrl)
+ {
+-	struct vsp1_bru *bru =
+-		container_of(ctrl->handler, struct vsp1_bru, ctrls);
++	struct vsp1_brx *brx =
++		container_of(ctrl->handler, struct vsp1_brx, ctrls);
+ 
+ 	switch (ctrl->id) {
+ 	case V4L2_CID_BG_COLOR:
+-		bru->bgcolor = ctrl->val;
++		brx->bgcolor = ctrl->val;
+ 		break;
+ 	}
+ 
+ 	return 0;
+ }
+ 
+-static const struct v4l2_ctrl_ops bru_ctrl_ops = {
+-	.s_ctrl = bru_s_ctrl,
++static const struct v4l2_ctrl_ops brx_ctrl_ops = {
++	.s_ctrl = brx_s_ctrl,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -63,12 +63,12 @@ static const struct v4l2_ctrl_ops bru_ctrl_ops = {
+  */
+ 
+ /*
+- * The BRU can't perform format conversion, all sink and source formats must be
++ * The BRx can't perform format conversion, all sink and source formats must be
+  * identical. We pick the format on the first sink pad (pad 0) and propagate it
+  * to all other pads.
+  */
+ 
+-static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
++static int brx_enum_mbus_code(struct v4l2_subdev *subdev,
+ 			      struct v4l2_subdev_pad_config *cfg,
+ 			      struct v4l2_subdev_mbus_code_enum *code)
+ {
+@@ -81,7 +81,7 @@ static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
+ 					  ARRAY_SIZE(codes));
+ }
+ 
+-static int bru_enum_frame_size(struct v4l2_subdev *subdev,
++static int brx_enum_frame_size(struct v4l2_subdev *subdev,
+ 			       struct v4l2_subdev_pad_config *cfg,
+ 			       struct v4l2_subdev_frame_size_enum *fse)
+ {
+@@ -92,29 +92,29 @@ static int bru_enum_frame_size(struct v4l2_subdev *subdev,
+ 	    fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
+ 		return -EINVAL;
+ 
+-	fse->min_width = BRU_MIN_SIZE;
+-	fse->max_width = BRU_MAX_SIZE;
+-	fse->min_height = BRU_MIN_SIZE;
+-	fse->max_height = BRU_MAX_SIZE;
++	fse->min_width = BRX_MIN_SIZE;
++	fse->max_width = BRX_MAX_SIZE;
++	fse->min_height = BRX_MIN_SIZE;
++	fse->max_height = BRX_MAX_SIZE;
+ 
+ 	return 0;
+ }
+ 
+-static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
++static struct v4l2_rect *brx_get_compose(struct vsp1_brx *brx,
+ 					 struct v4l2_subdev_pad_config *cfg,
+ 					 unsigned int pad)
+ {
+-	return v4l2_subdev_get_try_compose(&bru->entity.subdev, cfg, pad);
++	return v4l2_subdev_get_try_compose(&brx->entity.subdev, cfg, pad);
+ }
+ 
+-static void bru_try_format(struct vsp1_bru *bru,
++static void brx_try_format(struct vsp1_brx *brx,
+ 			   struct v4l2_subdev_pad_config *config,
+ 			   unsigned int pad, struct v4l2_mbus_framefmt *fmt)
+ {
+ 	struct v4l2_mbus_framefmt *format;
+ 
+ 	switch (pad) {
+-	case BRU_PAD_SINK(0):
++	case BRX_PAD_SINK(0):
+ 		/* Default to YUV if the requested format is not supported. */
+ 		if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
+ 		    fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
+@@ -122,46 +122,46 @@ static void bru_try_format(struct vsp1_bru *bru,
+ 		break;
+ 
+ 	default:
+-		/* The BRU can't perform format conversion. */
+-		format = vsp1_entity_get_pad_format(&bru->entity, config,
+-						    BRU_PAD_SINK(0));
++		/* The BRx can't perform format conversion. */
++		format = vsp1_entity_get_pad_format(&brx->entity, config,
++						    BRX_PAD_SINK(0));
+ 		fmt->code = format->code;
+ 		break;
+ 	}
+ 
+-	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
+-	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
++	fmt->width = clamp(fmt->width, BRX_MIN_SIZE, BRX_MAX_SIZE);
++	fmt->height = clamp(fmt->height, BRX_MIN_SIZE, BRX_MAX_SIZE);
+ 	fmt->field = V4L2_FIELD_NONE;
+ 	fmt->colorspace = V4L2_COLORSPACE_SRGB;
+ }
+ 
+-static int bru_set_format(struct v4l2_subdev *subdev,
++static int brx_set_format(struct v4l2_subdev *subdev,
+ 			  struct v4l2_subdev_pad_config *cfg,
+ 			  struct v4l2_subdev_format *fmt)
+ {
+-	struct vsp1_bru *bru = to_bru(subdev);
++	struct vsp1_brx *brx = to_brx(subdev);
+ 	struct v4l2_subdev_pad_config *config;
+ 	struct v4l2_mbus_framefmt *format;
+ 	int ret = 0;
+ 
+-	mutex_lock(&bru->entity.lock);
++	mutex_lock(&brx->entity.lock);
+ 
+-	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
++	config = vsp1_entity_get_pad_config(&brx->entity, cfg, fmt->which);
+ 	if (!config) {
+ 		ret = -EINVAL;
+ 		goto done;
+ 	}
+ 
+-	bru_try_format(bru, config, fmt->pad, &fmt->format);
++	brx_try_format(brx, config, fmt->pad, &fmt->format);
+ 
+-	format = vsp1_entity_get_pad_format(&bru->entity, config, fmt->pad);
++	format = vsp1_entity_get_pad_format(&brx->entity, config, fmt->pad);
+ 	*format = fmt->format;
+ 
+ 	/* Reset the compose rectangle */
+-	if (fmt->pad != bru->entity.source_pad) {
++	if (fmt->pad != brx->entity.source_pad) {
+ 		struct v4l2_rect *compose;
+ 
+-		compose = bru_get_compose(bru, config, fmt->pad);
++		compose = brx_get_compose(brx, config, fmt->pad);
+ 		compose->left = 0;
+ 		compose->top = 0;
+ 		compose->width = format->width;
+@@ -169,48 +169,48 @@ static int bru_set_format(struct v4l2_subdev *subdev,
+ 	}
+ 
+ 	/* Propagate the format code to all pads */
+-	if (fmt->pad == BRU_PAD_SINK(0)) {
++	if (fmt->pad == BRX_PAD_SINK(0)) {
+ 		unsigned int i;
+ 
+-		for (i = 0; i <= bru->entity.source_pad; ++i) {
+-			format = vsp1_entity_get_pad_format(&bru->entity,
++		for (i = 0; i <= brx->entity.source_pad; ++i) {
++			format = vsp1_entity_get_pad_format(&brx->entity,
+ 							    config, i);
+ 			format->code = fmt->format.code;
+ 		}
+ 	}
+ 
+ done:
+-	mutex_unlock(&bru->entity.lock);
++	mutex_unlock(&brx->entity.lock);
+ 	return ret;
+ }
+ 
+-static int bru_get_selection(struct v4l2_subdev *subdev,
++static int brx_get_selection(struct v4l2_subdev *subdev,
+ 			     struct v4l2_subdev_pad_config *cfg,
+ 			     struct v4l2_subdev_selection *sel)
+ {
+-	struct vsp1_bru *bru = to_bru(subdev);
++	struct vsp1_brx *brx = to_brx(subdev);
+ 	struct v4l2_subdev_pad_config *config;
+ 
+-	if (sel->pad == bru->entity.source_pad)
++	if (sel->pad == brx->entity.source_pad)
+ 		return -EINVAL;
+ 
+ 	switch (sel->target) {
+ 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ 		sel->r.left = 0;
+ 		sel->r.top = 0;
+-		sel->r.width = BRU_MAX_SIZE;
+-		sel->r.height = BRU_MAX_SIZE;
++		sel->r.width = BRX_MAX_SIZE;
++		sel->r.height = BRX_MAX_SIZE;
+ 		return 0;
+ 
+ 	case V4L2_SEL_TGT_COMPOSE:
+-		config = vsp1_entity_get_pad_config(&bru->entity, cfg,
++		config = vsp1_entity_get_pad_config(&brx->entity, cfg,
+ 						    sel->which);
+ 		if (!config)
+ 			return -EINVAL;
+ 
+-		mutex_lock(&bru->entity.lock);
+-		sel->r = *bru_get_compose(bru, config, sel->pad);
+-		mutex_unlock(&bru->entity.lock);
++		mutex_lock(&brx->entity.lock);
++		sel->r = *brx_get_compose(brx, config, sel->pad);
++		mutex_unlock(&brx->entity.lock);
+ 		return 0;
+ 
+ 	default:
+@@ -218,25 +218,25 @@ static int bru_get_selection(struct v4l2_subdev *subdev,
+ 	}
+ }
+ 
+-static int bru_set_selection(struct v4l2_subdev *subdev,
++static int brx_set_selection(struct v4l2_subdev *subdev,
+ 			     struct v4l2_subdev_pad_config *cfg,
+ 			     struct v4l2_subdev_selection *sel)
+ {
+-	struct vsp1_bru *bru = to_bru(subdev);
++	struct vsp1_brx *brx = to_brx(subdev);
+ 	struct v4l2_subdev_pad_config *config;
+ 	struct v4l2_mbus_framefmt *format;
+ 	struct v4l2_rect *compose;
+ 	int ret = 0;
+ 
+-	if (sel->pad == bru->entity.source_pad)
++	if (sel->pad == brx->entity.source_pad)
+ 		return -EINVAL;
+ 
+ 	if (sel->target != V4L2_SEL_TGT_COMPOSE)
+ 		return -EINVAL;
+ 
+-	mutex_lock(&bru->entity.lock);
++	mutex_lock(&brx->entity.lock);
+ 
+-	config = vsp1_entity_get_pad_config(&bru->entity, cfg, sel->which);
++	config = vsp1_entity_get_pad_config(&brx->entity, cfg, sel->which);
+ 	if (!config) {
+ 		ret = -EINVAL;
+ 		goto done;
+@@ -246,8 +246,8 @@ static int bru_set_selection(struct v4l2_subdev *subdev,
+ 	 * The compose rectangle top left corner must be inside the output
+ 	 * frame.
+ 	 */
+-	format = vsp1_entity_get_pad_format(&bru->entity, config,
+-					    bru->entity.source_pad);
++	format = vsp1_entity_get_pad_format(&brx->entity, config,
++					    brx->entity.source_pad);
+ 	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
+ 	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
+ 
+@@ -255,42 +255,42 @@ static int bru_set_selection(struct v4l2_subdev *subdev,
+ 	 * Scaling isn't supported, the compose rectangle size must be identical
+ 	 * to the sink format size.
+ 	 */
+-	format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad);
++	format = vsp1_entity_get_pad_format(&brx->entity, config, sel->pad);
+ 	sel->r.width = format->width;
+ 	sel->r.height = format->height;
+ 
+-	compose = bru_get_compose(bru, config, sel->pad);
++	compose = brx_get_compose(brx, config, sel->pad);
+ 	*compose = sel->r;
+ 
+ done:
+-	mutex_unlock(&bru->entity.lock);
++	mutex_unlock(&brx->entity.lock);
+ 	return ret;
+ }
+ 
+-static const struct v4l2_subdev_pad_ops bru_pad_ops = {
++static const struct v4l2_subdev_pad_ops brx_pad_ops = {
+ 	.init_cfg = vsp1_entity_init_cfg,
+-	.enum_mbus_code = bru_enum_mbus_code,
+-	.enum_frame_size = bru_enum_frame_size,
++	.enum_mbus_code = brx_enum_mbus_code,
++	.enum_frame_size = brx_enum_frame_size,
+ 	.get_fmt = vsp1_subdev_get_pad_format,
+-	.set_fmt = bru_set_format,
+-	.get_selection = bru_get_selection,
+-	.set_selection = bru_set_selection,
++	.set_fmt = brx_set_format,
++	.get_selection = brx_get_selection,
++	.set_selection = brx_set_selection,
+ };
+ 
+-static const struct v4l2_subdev_ops bru_ops = {
+-	.pad    = &bru_pad_ops,
++static const struct v4l2_subdev_ops brx_ops = {
++	.pad    = &brx_pad_ops,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+  * VSP1 Entity Operations
+  */
+ 
+-static void bru_configure(struct vsp1_entity *entity,
++static void brx_configure(struct vsp1_entity *entity,
+ 			  struct vsp1_pipeline *pipe,
+ 			  struct vsp1_dl_list *dl,
+ 			  enum vsp1_entity_params params)
+ {
+-	struct vsp1_bru *bru = to_bru(&entity->subdev);
++	struct vsp1_brx *brx = to_brx(&entity->subdev);
+ 	struct v4l2_mbus_framefmt *format;
+ 	unsigned int flags;
+ 	unsigned int i;
+@@ -298,8 +298,8 @@ static void bru_configure(struct vsp1_entity *entity,
+ 	if (params != VSP1_ENTITY_PARAMS_INIT)
+ 		return;
+ 
+-	format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config,
+-					    bru->entity.source_pad);
++	format = vsp1_entity_get_pad_format(&brx->entity, brx->entity.config,
++					    brx->entity.source_pad);
+ 
+ 	/*
+ 	 * The hardware is extremely flexible but we have no userspace API to
+@@ -313,7 +313,7 @@ static void bru_configure(struct vsp1_entity *entity,
+ 	 * format at the pipeline output is premultiplied.
+ 	 */
+ 	flags = pipe->output ? pipe->output->format.flags : 0;
+-	vsp1_bru_write(bru, dl, VI6_BRU_INCTRL,
++	vsp1_brx_write(brx, dl, VI6_BRU_INCTRL,
+ 		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
+ 		       0 : VI6_BRU_INCTRL_NRM);
+ 
+@@ -321,12 +321,12 @@ static void bru_configure(struct vsp1_entity *entity,
+ 	 * Set the background position to cover the whole output image and
+ 	 * configure its color.
+ 	 */
+-	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_SIZE,
++	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_SIZE,
+ 		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
+ 		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
+-	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_LOC, 0);
++	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_LOC, 0);
+ 
+-	vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_COL, bru->bgcolor |
++	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_COL, brx->bgcolor |
+ 		       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
+ 
+ 	/*
+@@ -336,25 +336,25 @@ static void bru_configure(struct vsp1_entity *entity,
+ 	 * unit.
+ 	 */
+ 	if (entity->type == VSP1_ENTITY_BRU)
+-		vsp1_bru_write(bru, dl, VI6_BRU_ROP,
++		vsp1_brx_write(brx, dl, VI6_BRU_ROP,
+ 			       VI6_BRU_ROP_DSTSEL_BRUIN(1) |
+ 			       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
+ 			       VI6_BRU_ROP_AROP(VI6_ROP_NOP));
+ 
+-	for (i = 0; i < bru->entity.source_pad; ++i) {
++	for (i = 0; i < brx->entity.source_pad; ++i) {
+ 		bool premultiplied = false;
+ 		u32 ctrl = 0;
+ 
+ 		/*
+-		 * Configure all Blend/ROP units corresponding to an enabled BRU
++		 * Configure all Blend/ROP units corresponding to an enabled BRx
+ 		 * input for alpha blending. Blend/ROP units corresponding to
+-		 * disabled BRU inputs are used in ROP NOP mode to ignore the
++		 * disabled BRx inputs are used in ROP NOP mode to ignore the
+ 		 * SRC input.
+ 		 */
+-		if (bru->inputs[i].rpf) {
++		if (brx->inputs[i].rpf) {
+ 			ctrl |= VI6_BRU_CTRL_RBC;
+ 
+-			premultiplied = bru->inputs[i].rpf->format.flags
++			premultiplied = brx->inputs[i].rpf->format.flags
+ 				      & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
+ 		} else {
+ 			ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
+@@ -378,7 +378,7 @@ static void bru_configure(struct vsp1_entity *entity,
+ 		if (!(entity->type == VSP1_ENTITY_BRU && i == 1))
+ 			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
+ 
+-		vsp1_bru_write(bru, dl, VI6_BRU_CTRL(i), ctrl);
++		vsp1_brx_write(brx, dl, VI6_BRU_CTRL(i), ctrl);
+ 
+ 		/*
+ 		 * Harcode the blending formula to
+@@ -393,7 +393,7 @@ static void bru_configure(struct vsp1_entity *entity,
+ 		 *
+ 		 * otherwise.
+ 		 */
+-		vsp1_bru_write(bru, dl, VI6_BRU_BLD(i),
++		vsp1_brx_write(brx, dl, VI6_BRU_BLD(i),
+ 			       VI6_BRU_BLD_CCMDX_255_SRC_A |
+ 			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
+ 						VI6_BRU_BLD_CCMDY_SRC_A) |
+@@ -403,29 +403,29 @@ static void bru_configure(struct vsp1_entity *entity,
+ 	}
+ }
+ 
+-static const struct vsp1_entity_operations bru_entity_ops = {
+-	.configure = bru_configure,
++static const struct vsp1_entity_operations brx_entity_ops = {
++	.configure = brx_configure,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+  * Initialization and Cleanup
+  */
+ 
+-struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1,
++struct vsp1_brx *vsp1_brx_create(struct vsp1_device *vsp1,
+ 				 enum vsp1_entity_type type)
+ {
+-	struct vsp1_bru *bru;
++	struct vsp1_brx *brx;
+ 	unsigned int num_pads;
+ 	const char *name;
+ 	int ret;
+ 
+-	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
+-	if (bru == NULL)
++	brx = devm_kzalloc(vsp1->dev, sizeof(*brx), GFP_KERNEL);
++	if (brx == NULL)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	bru->base = type == VSP1_ENTITY_BRU ? VI6_BRU_BASE : VI6_BRS_BASE;
+-	bru->entity.ops = &bru_entity_ops;
+-	bru->entity.type = type;
++	brx->base = type == VSP1_ENTITY_BRU ? VI6_BRU_BASE : VI6_BRS_BASE;
++	brx->entity.ops = &brx_entity_ops;
++	brx->entity.type = type;
+ 
+ 	if (type == VSP1_ENTITY_BRU) {
+ 		num_pads = vsp1->info->num_bru_inputs + 1;
+@@ -435,26 +435,26 @@ struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1,
+ 		name = "brs";
+ 	}
+ 
+-	ret = vsp1_entity_init(vsp1, &bru->entity, name, num_pads, &bru_ops,
++	ret = vsp1_entity_init(vsp1, &brx->entity, name, num_pads, &brx_ops,
+ 			       MEDIA_ENT_F_PROC_VIDEO_COMPOSER);
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
+ 	/* Initialize the control handler. */
+-	v4l2_ctrl_handler_init(&bru->ctrls, 1);
+-	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
++	v4l2_ctrl_handler_init(&brx->ctrls, 1);
++	v4l2_ctrl_new_std(&brx->ctrls, &brx_ctrl_ops, V4L2_CID_BG_COLOR,
+ 			  0, 0xffffff, 1, 0);
+ 
+-	bru->bgcolor = 0;
++	brx->bgcolor = 0;
+ 
+-	bru->entity.subdev.ctrl_handler = &bru->ctrls;
++	brx->entity.subdev.ctrl_handler = &brx->ctrls;
+ 
+-	if (bru->ctrls.error) {
++	if (brx->ctrls.error) {
+ 		dev_err(vsp1->dev, "%s: failed to initialize controls\n", name);
+-		ret = bru->ctrls.error;
+-		vsp1_entity_destroy(&bru->entity);
++		ret = brx->ctrls.error;
++		vsp1_entity_destroy(&brx->entity);
+ 		return ERR_PTR(ret);
+ 	}
+ 
+-	return bru;
++	return brx;
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_bru.h b/drivers/media/platform/vsp1/vsp1_brx.h
+similarity index 66%
+rename from drivers/media/platform/vsp1/vsp1_bru.h
+rename to drivers/media/platform/vsp1/vsp1_brx.h
+index c98ed96d8de6..927aa4254c0f 100644
+--- a/drivers/media/platform/vsp1/vsp1_bru.h
++++ b/drivers/media/platform/vsp1/vsp1_brx.h
+@@ -1,5 +1,5 @@
+ /*
+- * vsp1_bru.h  --  R-Car VSP1 Blend ROP Unit
++ * vsp1_brx.h  --  R-Car VSP1 Blend ROP Unit (BRU and BRS)
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+@@ -10,8 +10,8 @@
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  */
+-#ifndef __VSP1_BRU_H__
+-#define __VSP1_BRU_H__
++#ifndef __VSP1_BRX_H__
++#define __VSP1_BRX_H__
+ 
+ #include <media/media-entity.h>
+ #include <media/v4l2-ctrls.h>
+@@ -22,9 +22,9 @@
+ struct vsp1_device;
+ struct vsp1_rwpf;
+ 
+-#define BRU_PAD_SINK(n)				(n)
++#define BRX_PAD_SINK(n)				(n)
+ 
+-struct vsp1_bru {
++struct vsp1_brx {
+ 	struct vsp1_entity entity;
+ 	unsigned int base;
+ 
+@@ -37,12 +37,12 @@ struct vsp1_bru {
+ 	u32 bgcolor;
+ };
+ 
+-static inline struct vsp1_bru *to_bru(struct v4l2_subdev *subdev)
++static inline struct vsp1_brx *to_brx(struct v4l2_subdev *subdev)
+ {
+-	return container_of(subdev, struct vsp1_bru, entity.subdev);
++	return container_of(subdev, struct vsp1_brx, entity.subdev);
+ }
+ 
+-struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1,
++struct vsp1_brx *vsp1_brx_create(struct vsp1_device *vsp1,
+ 				 enum vsp1_entity_type type);
+ 
+-#endif /* __VSP1_BRU_H__ */
++#endif /* __VSP1_BRX_H__ */
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index b43d6dc0d5f5..095dc48aa25a 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -20,14 +20,14 @@
+ #include <media/vsp1.h>
+ 
+ #include "vsp1.h"
+-#include "vsp1_bru.h"
++#include "vsp1_brx.h"
+ #include "vsp1_dl.h"
+ #include "vsp1_drm.h"
+ #include "vsp1_lif.h"
+ #include "vsp1_pipe.h"
+ #include "vsp1_rwpf.h"
+ 
+-#define BRU_NAME(e)	(e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
++#define BRX_NAME(e)	(e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
+ 
+ /* -----------------------------------------------------------------------------
+  * Interrupt Handling
+@@ -43,7 +43,7 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 		drm_pipe->du_complete(drm_pipe->du_private, complete);
+ 
+ 	if (completion & VSP1_DL_FRAME_END_INTERNAL) {
+-		drm_pipe->force_bru_release = false;
++		drm_pipe->force_brx_release = false;
+ 		wake_up(&drm_pipe->wait_queue);
+ 	}
+ }
+@@ -52,11 +52,11 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+  * Pipeline Configuration
+  */
+ 
+-/* Setup one RPF and the connected BRU sink pad. */
++/* Setup one RPF and the connected BRx sink pad. */
+ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 				      struct vsp1_pipeline *pipe,
+ 				      struct vsp1_rwpf *rpf,
+-				      unsigned int bru_input)
++				      unsigned int brx_input)
+ {
+ 	struct v4l2_subdev_selection sel;
+ 	struct v4l2_subdev_format format;
+@@ -65,7 +65,7 @@ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 
+ 	/*
+ 	 * Configure the format on the RPF sink pad and propagate it up to the
+-	 * BRU sink pad.
++	 * BRx sink pad.
+ 	 */
+ 	crop = &vsp1->drm->inputs[rpf->entity.index].crop;
+ 
+@@ -126,114 +126,114 @@ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	/* BRU sink, propagate the format from the RPF source. */
+-	format.pad = bru_input;
++	/* BRx sink, propagate the format from the RPF source. */
++	format.pad = brx_input;
+ 
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
++	ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
+ 			       &format);
+ 	if (ret < 0)
+ 		return ret;
+ 
+ 	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+ 		__func__, format.format.width, format.format.height,
+-		format.format.code, BRU_NAME(pipe->bru), format.pad);
++		format.format.code, BRX_NAME(pipe->brx), format.pad);
+ 
+-	sel.pad = bru_input;
++	sel.pad = brx_input;
+ 	sel.target = V4L2_SEL_TGT_COMPOSE;
+ 	sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
+ 
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_selection, NULL,
++	ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
+ 			       &sel);
+ 	if (ret < 0)
+ 		return ret;
+ 
+ 	dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
+ 		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
+-		BRU_NAME(pipe->bru), sel.pad);
++		BRX_NAME(pipe->brx), sel.pad);
+ 
+ 	return 0;
+ }
+ 
+-/* Setup the BRU source pad. */
++/* Setup the BRx source pad. */
+ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 					 struct vsp1_pipeline *pipe);
+ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
+ 
+-static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
++static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
+ 				      struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+ 	struct v4l2_subdev_format format = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ 	};
+-	struct vsp1_entity *bru;
++	struct vsp1_entity *brx;
+ 	int ret;
+ 
+ 	/*
+-	 * Pick a BRU:
+-	 * - If we need more than two inputs, use the main BRU.
+-	 * - Otherwise, if we are not forced to release our BRU, keep it.
+-	 * - Else, use any free BRU (randomly starting with the main BRU).
++	 * Pick a BRx:
++	 * - If we need more than two inputs, use the BRU.
++	 * - Otherwise, if we are not forced to release our BRx, keep it.
++	 * - Else, use any free BRx (randomly starting with the BRU).
+ 	 */
+ 	if (pipe->num_inputs > 2)
+-		bru = &vsp1->bru->entity;
+-	else if (pipe->bru && !drm_pipe->force_bru_release)
+-		bru = pipe->bru;
++		brx = &vsp1->bru->entity;
++	else if (pipe->brx && !drm_pipe->force_brx_release)
++		brx = pipe->brx;
+ 	else if (!vsp1->bru->entity.pipe)
+-		bru = &vsp1->bru->entity;
++		brx = &vsp1->bru->entity;
+ 	else
+-		bru = &vsp1->brs->entity;
++		brx = &vsp1->brs->entity;
+ 
+-	/* Switch BRU if needed. */
+-	if (bru != pipe->bru) {
+-		struct vsp1_entity *released_bru = NULL;
++	/* Switch BRx if needed. */
++	if (brx != pipe->brx) {
++		struct vsp1_entity *released_brx = NULL;
+ 
+-		/* Release our BRU if we have one. */
+-		if (pipe->bru) {
++		/* Release our BRx if we have one. */
++		if (pipe->brx) {
+ 			dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
+ 				__func__, pipe->lif->index,
+-				BRU_NAME(pipe->bru));
++				BRX_NAME(pipe->brx));
+ 
+ 			/*
+-			 * The BRU might be acquired by the other pipeline in
++			 * The BRx might be acquired by the other pipeline in
+ 			 * the next step. We must thus remove it from the list
+ 			 * of entities for this pipeline. The other pipeline's
+-			 * hardware configuration will reconfigure the BRU
++			 * hardware configuration will reconfigure the BRx
+ 			 * routing.
+ 			 *
+ 			 * However, if the other pipeline doesn't acquire our
+-			 * BRU, we need to keep it in the list, otherwise the
++			 * BRx, we need to keep it in the list, otherwise the
+ 			 * hardware configuration step won't disconnect it from
+-			 * the pipeline. To solve this, store the released BRU
++			 * the pipeline. To solve this, store the released BRx
+ 			 * pointer to add it back to the list of entities later
+ 			 * if it isn't acquired by the other pipeline.
+ 			 */
+-			released_bru = pipe->bru;
++			released_brx = pipe->brx;
+ 
+-			list_del(&pipe->bru->list_pipe);
+-			pipe->bru->sink = NULL;
+-			pipe->bru->pipe = NULL;
+-			pipe->bru = NULL;
++			list_del(&pipe->brx->list_pipe);
++			pipe->brx->sink = NULL;
++			pipe->brx->pipe = NULL;
++			pipe->brx = NULL;
+ 		}
+ 
+ 		/*
+-		 * If the BRU we need is in use, force the owner pipeline to
+-		 * switch to the other BRU and wait until the switch completes.
++		 * If the BRx we need is in use, force the owner pipeline to
++		 * switch to the other BRx and wait until the switch completes.
+ 		 */
+-		if (bru->pipe) {
++		if (brx->pipe) {
+ 			struct vsp1_drm_pipeline *owner_pipe;
+ 
+ 			dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
+-				__func__, pipe->lif->index, BRU_NAME(bru));
++				__func__, pipe->lif->index, BRX_NAME(brx));
+ 
+-			owner_pipe = to_vsp1_drm_pipeline(bru->pipe);
+-			owner_pipe->force_bru_release = true;
++			owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
++			owner_pipe->force_brx_release = true;
+ 
+ 			vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
+ 			vsp1_du_pipeline_configure(&owner_pipe->pipe);
+ 
+ 			ret = wait_event_timeout(owner_pipe->wait_queue,
+-						 !owner_pipe->force_bru_release,
++						 !owner_pipe->force_brx_release,
+ 						 msecs_to_jiffies(500));
+ 			if (ret == 0)
+ 				dev_warn(vsp1->dev,
+@@ -242,46 +242,46 @@ static int vsp1_du_pipeline_setup_bru(struct vsp1_device *vsp1,
+ 		}
+ 
+ 		/*
+-		 * If the BRU we have released previously hasn't been acquired
++		 * If the BRx we have released previously hasn't been acquired
+ 		 * by the other pipeline, add it back to the entities list (with
+ 		 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
+ 		 * disconnect it from the hardware pipeline.
+ 		 */
+-		if (released_bru && !released_bru->pipe)
+-			list_add_tail(&released_bru->list_pipe,
++		if (released_brx && !released_brx->pipe)
++			list_add_tail(&released_brx->list_pipe,
+ 				      &pipe->entities);
+ 
+-		/* Add the BRU to the pipeline. */
++		/* Add the BRx to the pipeline. */
+ 		dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
+-			__func__, pipe->lif->index, BRU_NAME(bru));
++			__func__, pipe->lif->index, BRX_NAME(brx));
+ 
+-		pipe->bru = bru;
+-		pipe->bru->pipe = pipe;
+-		pipe->bru->sink = &pipe->output->entity;
+-		pipe->bru->sink_pad = 0;
++		pipe->brx = brx;
++		pipe->brx->pipe = pipe;
++		pipe->brx->sink = &pipe->output->entity;
++		pipe->brx->sink_pad = 0;
+ 
+-		list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
++		list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
+ 	}
+ 
+ 	/*
+-	 * Configure the format on the BRU source and verify that it matches the
++	 * Configure the format on the BRx source and verify that it matches the
+ 	 * requested format. We don't set the media bus code as it is configured
+-	 * on the BRU sink pad 0 and propagated inside the entity, not on the
++	 * on the BRx sink pad 0 and propagated inside the entity, not on the
+ 	 * source pad.
+ 	 */
+-	format.pad = pipe->bru->source_pad;
++	format.pad = pipe->brx->source_pad;
+ 	format.format.width = drm_pipe->width;
+ 	format.format.height = drm_pipe->height;
+ 	format.format.field = V4L2_FIELD_NONE;
+ 
+-	ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
++	ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
+ 			       &format);
+ 	if (ret < 0)
+ 		return ret;
+ 
+ 	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
+ 		__func__, format.format.width, format.format.height,
+-		format.format.code, BRU_NAME(pipe->bru), pipe->bru->source_pad);
++		format.format.code, BRX_NAME(pipe->brx), pipe->brx->source_pad);
+ 
+ 	if (format.format.width != drm_pipe->width ||
+ 	    format.format.height != drm_pipe->height) {
+@@ -297,12 +297,12 @@ static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
+ 	return vsp1->drm->inputs[rpf->entity.index].zpos;
+ }
+ 
+-/* Setup the input side of the pipeline (RPFs and BRU). */
++/* Setup the input side of the pipeline (RPFs and BRx). */
+ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+-					 struct vsp1_pipeline *pipe)
++					struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
+-	struct vsp1_bru *bru;
++	struct vsp1_brx *brx;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -327,25 +327,25 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 	}
+ 
+ 	/*
+-	 * Setup the BRU. This must be done before setting up the RPF input
+-	 * pipelines as the BRU sink compose rectangles depend on the BRU source
++	 * Setup the BRx. This must be done before setting up the RPF input
++	 * pipelines as the BRx sink compose rectangles depend on the BRx source
+ 	 * format.
+ 	 */
+-	ret = vsp1_du_pipeline_setup_bru(vsp1, pipe);
++	ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
+ 	if (ret < 0) {
+ 		dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
+-			BRU_NAME(pipe->bru));
++			BRX_NAME(pipe->brx));
+ 		return ret;
+ 	}
+ 
+-	bru = to_bru(&pipe->bru->subdev);
++	brx = to_brx(&pipe->brx->subdev);
+ 
+ 	/* Setup the RPF input pipeline for every enabled input. */
+-	for (i = 0; i < pipe->bru->source_pad; ++i) {
++	for (i = 0; i < pipe->brx->source_pad; ++i) {
+ 		struct vsp1_rwpf *rpf = inputs[i];
+ 
+ 		if (!rpf) {
+-			bru->inputs[i].rpf = NULL;
++			brx->inputs[i].rpf = NULL;
+ 			continue;
+ 		}
+ 
+@@ -354,13 +354,13 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
+ 		}
+ 
+-		bru->inputs[i].rpf = rpf;
+-		rpf->bru_input = i;
+-		rpf->entity.sink = pipe->bru;
++		brx->inputs[i].rpf = rpf;
++		rpf->brx_input = i;
++		rpf->entity.sink = pipe->brx;
+ 		rpf->entity.sink_pad = i;
+ 
+ 		dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
+-			__func__, rpf->entity.index, BRU_NAME(pipe->bru), i);
++			__func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
+ 
+ 		ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, i);
+ 		if (ret < 0) {
+@@ -467,7 +467,7 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 		}
+ 	}
+ 
+-	vsp1_dl_list_commit(dl, drm_pipe->force_bru_release);
++	vsp1_dl_list_commit(dl, drm_pipe->force_brx_release);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -492,8 +492,8 @@ EXPORT_SYMBOL_GPL(vsp1_du_init);
+  * @cfg: the LIF configuration
+  *
+  * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
+- * and @cfg.height. This sets up formats on the blend unit (BRU or BRS) source
+- * pad, the WPF sink and source pads, and the LIF sink pad.
++ * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
++ * source pads, and the LIF sink pad.
+  *
+  * The @pipe_index argument selects which DRM pipeline to setup. The number of
+  * available pipelines depend on the VSP instance.
+@@ -523,11 +523,11 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 	pipe = &drm_pipe->pipe;
+ 
+ 	if (!cfg) {
+-		struct vsp1_bru *bru;
++		struct vsp1_brx *brx;
+ 
+ 		mutex_lock(&vsp1->drm->lock);
+ 
+-		bru = to_bru(&pipe->bru->subdev);
++		brx = to_brx(&pipe->brx->subdev);
+ 
+ 		/*
+ 		 * NULL configuration means the CRTC is being disabled, stop
+@@ -544,7 +544,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 				continue;
+ 
+ 			/*
+-			 * Remove the RPF from the pipe and the list of BRU
++			 * Remove the RPF from the pipe and the list of BRx
+ 			 * inputs.
+ 			 */
+ 			WARN_ON(!rpf->entity.pipe);
+@@ -552,7 +552,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 			list_del(&rpf->entity.list_pipe);
+ 			pipe->inputs[i] = NULL;
+ 
+-			bru->inputs[rpf->bru_input].rpf = NULL;
++			brx->inputs[rpf->brx_input].rpf = NULL;
+ 		}
+ 
+ 		drm_pipe->du_complete = NULL;
+@@ -560,11 +560,11 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 
+ 		dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
+ 			__func__, pipe->lif->index,
+-			BRU_NAME(pipe->bru));
++			BRX_NAME(pipe->brx));
+ 
+-		list_del(&pipe->bru->list_pipe);
+-		pipe->bru->pipe = NULL;
+-		pipe->bru = NULL;
++		list_del(&pipe->brx->list_pipe);
++		pipe->brx->pipe = NULL;
++		pipe->brx = NULL;
+ 
+ 		mutex_unlock(&vsp1->drm->lock);
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index c84bc1c456c0..d738cc57f0e3 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -24,8 +24,8 @@
+  * @pipe: the VSP1 pipeline used for display
+  * @width: output display width
+  * @height: output display height
+- * @force_bru_release: when set, release the BRU during the next reconfiguration
+- * @wait_queue: wait queue to wait for BRU release completion
++ * @force_brx_release: when set, release the BRx during the next reconfiguration
++ * @wait_queue: wait queue to wait for BRx release completion
+  * @du_complete: frame completion callback for the DU driver (optional)
+  * @du_private: data to be passed to the du_complete callback
+  */
+@@ -35,7 +35,7 @@ struct vsp1_drm_pipeline {
+ 	unsigned int width;
+ 	unsigned int height;
+ 
+-	bool force_bru_release;
++	bool force_brx_release;
+ 	wait_queue_head_t wait_queue;
+ 
+ 	/* Frame synchronisation */
+diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c
+index 58a7993f2306..f41cd70409db 100644
+--- a/drivers/media/platform/vsp1/vsp1_drv.c
++++ b/drivers/media/platform/vsp1/vsp1_drv.c
+@@ -26,7 +26,7 @@
+ #include <media/v4l2-subdev.h>
+ 
+ #include "vsp1.h"
+-#include "vsp1_bru.h"
++#include "vsp1_brx.h"
+ #include "vsp1_clu.h"
+ #include "vsp1_dl.h"
+ #include "vsp1_drm.h"
+@@ -269,7 +269,7 @@ static int vsp1_create_entities(struct vsp1_device *vsp1)
+ 
+ 	/* Instantiate all the entities. */
+ 	if (vsp1->info->features & VSP1_HAS_BRS) {
+-		vsp1->brs = vsp1_bru_create(vsp1, VSP1_ENTITY_BRS);
++		vsp1->brs = vsp1_brx_create(vsp1, VSP1_ENTITY_BRS);
+ 		if (IS_ERR(vsp1->brs)) {
+ 			ret = PTR_ERR(vsp1->brs);
+ 			goto done;
+@@ -279,7 +279,7 @@ static int vsp1_create_entities(struct vsp1_device *vsp1)
+ 	}
+ 
+ 	if (vsp1->info->features & VSP1_HAS_BRU) {
+-		vsp1->bru = vsp1_bru_create(vsp1, VSP1_ENTITY_BRU);
++		vsp1->bru = vsp1_brx_create(vsp1, VSP1_ENTITY_BRU);
+ 		if (IS_ERR(vsp1->bru)) {
+ 			ret = PTR_ERR(vsp1->bru);
+ 			goto done;
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index 1134f14ed4aa..3fc5ecfa35e8 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -20,7 +20,7 @@
+ #include <media/v4l2-subdev.h>
+ 
+ #include "vsp1.h"
+-#include "vsp1_bru.h"
++#include "vsp1_brx.h"
+ #include "vsp1_dl.h"
+ #include "vsp1_entity.h"
+ #include "vsp1_hgo.h"
+@@ -188,11 +188,11 @@ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
+ 	struct vsp1_entity *entity;
+ 	unsigned int i;
+ 
+-	if (pipe->bru) {
+-		struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
++	if (pipe->brx) {
++		struct vsp1_brx *brx = to_brx(&pipe->brx->subdev);
+ 
+-		for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
+-			bru->inputs[i].rpf = NULL;
++		for (i = 0; i < ARRAY_SIZE(brx->inputs); ++i)
++			brx->inputs[i].rpf = NULL;
+ 	}
+ 
+ 	for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i)
+@@ -207,7 +207,7 @@ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
+ 	pipe->state = VSP1_PIPELINE_STOPPED;
+ 	pipe->buffers_ready = 0;
+ 	pipe->num_inputs = 0;
+-	pipe->bru = NULL;
++	pipe->brx = NULL;
+ 	pipe->hgo = NULL;
+ 	pipe->hgt = NULL;
+ 	pipe->lif = NULL;
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index 412da67527c0..07ccd6b810c5 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -99,7 +99,7 @@ struct vsp1_partition {
+  * @num_inputs: number of RPFs
+  * @inputs: array of RPFs in the pipeline (indexed by RPF index)
+  * @output: WPF at the output of the pipeline
+- * @bru: BRU entity, if present
++ * @brx: BRx entity, if present
+  * @hgo: HGO entity, if present
+  * @hgt: HGT entity, if present
+  * @lif: LIF entity, if present
+@@ -129,7 +129,7 @@ struct vsp1_pipeline {
+ 	unsigned int num_inputs;
+ 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF];
+ 	struct vsp1_rwpf *output;
+-	struct vsp1_entity *bru;
++	struct vsp1_entity *brx;
+ 	struct vsp1_entity *hgo;
+ 	struct vsp1_entity *hgt;
+ 	struct vsp1_entity *lif;
+diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c
+index fe0633da5a5f..7e74c2015070 100644
+--- a/drivers/media/platform/vsp1/vsp1_rpf.c
++++ b/drivers/media/platform/vsp1/vsp1_rpf.c
+@@ -167,12 +167,12 @@ static void rpf_configure(struct vsp1_entity *entity,
+ 	vsp1_rpf_write(rpf, dl, VI6_RPF_DSWAP, fmtinfo->swap);
+ 
+ 	/* Output location */
+-	if (pipe->bru) {
++	if (pipe->brx) {
+ 		const struct v4l2_rect *compose;
+ 
+-		compose = vsp1_entity_get_pad_selection(pipe->bru,
+-							pipe->bru->config,
+-							rpf->bru_input,
++		compose = vsp1_entity_get_pad_selection(pipe->brx,
++							pipe->brx->config,
++							rpf->brx_input,
+ 							V4L2_SEL_TGT_COMPOSE);
+ 		left = compose->left;
+ 		top = compose->top;
+@@ -191,10 +191,10 @@ static void rpf_configure(struct vsp1_entity *entity,
+ 	 * alpha channel by a fixed global alpha value, and multiply the pixel
+ 	 * components to convert the input to premultiplied alpha.
+ 	 *
+-	 * As alpha premultiplication is available in the BRU for both Gen2 and
++	 * As alpha premultiplication is available in the BRx for both Gen2 and
+ 	 * Gen3 we handle it there and use the Gen3 alpha multiplier for global
+ 	 * alpha multiplication only. This however prevents conversion to
+-	 * premultiplied alpha if no BRU is present in the pipeline. If that use
++	 * premultiplied alpha if no BRx is present in the pipeline. If that use
+ 	 * case turns out to be useful we will revisit the implementation (for
+ 	 * Gen3 only).
+ 	 *
+diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h
+index c94ac89abfa7..915aeadb21dd 100644
+--- a/drivers/media/platform/vsp1/vsp1_rwpf.h
++++ b/drivers/media/platform/vsp1/vsp1_rwpf.h
+@@ -45,7 +45,7 @@ struct vsp1_rwpf {
+ 
+ 	struct v4l2_pix_format_mplane format;
+ 	const struct vsp1_format_info *fmtinfo;
+-	unsigned int bru_input;
++	unsigned int brx_input;
+ 
+ 	unsigned int alpha;
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index c4b572712d76..c41a4495a874 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -28,7 +28,7 @@
+ #include <media/videobuf2-dma-contig.h>
+ 
+ #include "vsp1.h"
+-#include "vsp1_bru.h"
++#include "vsp1_brx.h"
+ #include "vsp1_dl.h"
+ #include "vsp1_entity.h"
+ #include "vsp1_hgo.h"
+@@ -488,7 +488,7 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe,
+ 	struct media_entity_enum ent_enum;
+ 	struct vsp1_entity *entity;
+ 	struct media_pad *pad;
+-	struct vsp1_bru *bru = NULL;
++	struct vsp1_brx *brx = NULL;
+ 	int ret;
+ 
+ 	ret = media_entity_enum_init(&ent_enum, &input->entity.vsp1->media_dev);
+@@ -524,14 +524,14 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe,
+ 		if (entity->type == VSP1_ENTITY_BRU ||
+ 		    entity->type == VSP1_ENTITY_BRS) {
+ 			/* BRU and BRS can't be chained. */
+-			if (bru) {
++			if (brx) {
+ 				ret = -EPIPE;
+ 				goto out;
+ 			}
+ 
+-			bru = to_bru(&entity->subdev);
+-			bru->inputs[pad->index].rpf = input;
+-			input->bru_input = pad->index;
++			brx = to_brx(&entity->subdev);
++			brx->inputs[pad->index].rpf = input;
++			input->brx_input = pad->index;
+ 		}
+ 
+ 		/* We've reached the WPF, we're done. */
+@@ -553,7 +553,7 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe,
+ 			}
+ 
+ 			pipe->uds = entity;
+-			pipe->uds_input = bru ? &bru->entity : &input->entity;
++			pipe->uds_input = brx ? &brx->entity : &input->entity;
+ 		}
+ 
+ 		/* Follow the source link, ignoring any HGO or HGT. */
+@@ -619,7 +619,7 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe,
+ 
+ 		case VSP1_ENTITY_BRU:
+ 		case VSP1_ENTITY_BRS:
+-			pipe->bru = e;
++			pipe->brx = e;
+ 			break;
+ 
+ 		case VSP1_ENTITY_HGO:
+diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c
+index 8bd6b2f1af15..53858d100228 100644
+--- a/drivers/media/platform/vsp1/vsp1_wpf.c
++++ b/drivers/media/platform/vsp1/vsp1_wpf.c
+@@ -436,7 +436,7 @@ static void wpf_configure(struct vsp1_entity *entity,
+ 	vsp1_dl_list_write(dl, VI6_WPF_WRBCK_CTRL, 0);
+ 
+ 	/*
+-	 * Sources. If the pipeline has a single input and BRU is not used,
++	 * Sources. If the pipeline has a single input and BRx is not used,
+ 	 * configure it as the master layer. Otherwise configure all
+ 	 * inputs as sub-layers and select the virtual RPF as the master
+ 	 * layer.
+@@ -447,13 +447,13 @@ static void wpf_configure(struct vsp1_entity *entity,
+ 		if (!input)
+ 			continue;
+ 
+-		srcrpf |= (!pipe->bru && pipe->num_inputs == 1)
++		srcrpf |= (!pipe->brx && pipe->num_inputs == 1)
+ 			? VI6_WPF_SRCRPF_RPF_ACT_MST(input->entity.index)
+ 			: VI6_WPF_SRCRPF_RPF_ACT_SUB(input->entity.index);
+ 	}
+ 
+-	if (pipe->bru)
+-		srcrpf |= pipe->bru->type == VSP1_ENTITY_BRU
++	if (pipe->brx)
++		srcrpf |= pipe->brx->type == VSP1_ENTITY_BRU
+ 			? VI6_WPF_SRCRPF_VIRACT_MST
+ 			: VI6_WPF_SRCRPF_VIRACT2_MST;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1186-media-v4l-vsp1-Use-SPDX-license-headers.patch b/patches/1186-media-v4l-vsp1-Use-SPDX-license-headers.patch
new file mode 100644
index 00000000000000..b47e2dbfcb64d4
--- /dev/null
+++ b/patches/1186-media-v4l-vsp1-Use-SPDX-license-headers.patch
@@ -0,0 +1,806 @@
+From 1b1be0c7ae99afab140a012855d8155b450345e4 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sun, 22 Apr 2018 17:33:20 -0400
+Subject: [PATCH 1186/1795] media: v4l: vsp1: Use SPDX license headers
+
+Adopt the SPDX license identifier headers to ease license compliance
+management. All files in the driver are licensed under the GPLv2+ except
+for the vsp1_regs.h file which is licensed under the GPLv2. This is
+likely an oversight, but fixing this requires contacting the copyright
+owners and is out of scope for this patch.
+
+While at it fix the file descriptions to match file names where copy and
+paste error occurred.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 1c4b5f49191aa66ceb04c25d177240c42fa07025)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1.h        | 6 +-----
+ drivers/media/platform/vsp1/vsp1_brx.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_brx.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_clu.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_clu.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_dl.c     | 8 ++------
+ drivers/media/platform/vsp1/vsp1_dl.h     | 6 +-----
+ drivers/media/platform/vsp1/vsp1_drm.c    | 8 ++------
+ drivers/media/platform/vsp1/vsp1_drm.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_drv.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_entity.c | 6 +-----
+ drivers/media/platform/vsp1/vsp1_entity.h | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hgo.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hgo.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hgt.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hgt.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_histo.c  | 6 +-----
+ drivers/media/platform/vsp1/vsp1_histo.h  | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hsit.c   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_hsit.h   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_lif.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_lif.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_lut.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_lut.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_pipe.c   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_pipe.h   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_regs.h   | 5 +----
+ drivers/media/platform/vsp1/vsp1_rpf.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_rwpf.c   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_rwpf.h   | 6 +-----
+ drivers/media/platform/vsp1/vsp1_sru.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_sru.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_uds.c    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_uds.h    | 6 +-----
+ drivers/media/platform/vsp1/vsp1_video.c  | 6 +-----
+ drivers/media/platform/vsp1/vsp1_video.h  | 6 +-----
+ drivers/media/platform/vsp1/vsp1_wpf.c    | 6 +-----
+ 37 files changed, 39 insertions(+), 186 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h
+index 894cc725c2d4..9cf4e1c4b036 100644
+--- a/drivers/media/platform/vsp1/vsp1.h
++++ b/drivers/media/platform/vsp1/vsp1.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1.h  --  R-Car VSP1 Driver
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_H__
+ #define __VSP1_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_brx.c b/drivers/media/platform/vsp1/vsp1_brx.c
+index b4af1d546022..3beec18fd863 100644
+--- a/drivers/media/platform/vsp1/vsp1_brx.c
++++ b/drivers/media/platform/vsp1/vsp1_brx.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_brx.c  --  R-Car VSP1 Blend ROP Unit (BRU and BRS)
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_brx.h b/drivers/media/platform/vsp1/vsp1_brx.h
+index 927aa4254c0f..6abbb8c3343c 100644
+--- a/drivers/media/platform/vsp1/vsp1_brx.h
++++ b/drivers/media/platform/vsp1/vsp1_brx.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_brx.h  --  R-Car VSP1 Blend ROP Unit (BRU and BRS)
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_BRX_H__
+ #define __VSP1_BRX_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index f2fb26e5ab4e..9626b6308585 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_clu.c  --  R-Car VSP1 Cubic Look-Up Table
+  *
+  * Copyright (C) 2015-2016 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.h b/drivers/media/platform/vsp1/vsp1_clu.h
+index 036e0a2f1a42..c45e6e707592 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.h
++++ b/drivers/media/platform/vsp1/vsp1_clu.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_clu.h  --  R-Car VSP1 Cubic Look-Up Table
+  *
+  * Copyright (C) 2015 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_CLU_H__
+ #define __VSP1_CLU_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 30ad491605ff..801dea475740 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+- * vsp1_dl.h  --  R-Car VSP1 Display List
++ * vsp1_dl.c  --  R-Car VSP1 Display List
+  *
+  * Copyright (C) 2015 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index 1a5bbd5ddb7b..e6279b1abd19 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_dl.h  --  R-Car VSP1 Display List
+  *
+  * Copyright (C) 2015 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_DL_H__
+ #define __VSP1_DL_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 095dc48aa25a..2b29a83dceb9 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+- * vsp1_drm.c  --  R-Car VSP1 DRM API
++ * vsp1_drm.c  --  R-Car VSP1 DRM/KMS Interface
+  *
+  * Copyright (C) 2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index d738cc57f0e3..f4af1b2b12d6 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_drm.h  --  R-Car VSP1 DRM/KMS Interface
+  *
+  * Copyright (C) 2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_DRM_H__
+ #define __VSP1_DRM_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c
+index f41cd70409db..331a2e0af0d3 100644
+--- a/drivers/media/platform/vsp1/vsp1_drv.c
++++ b/drivers/media/platform/vsp1/vsp1_drv.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_drv.c  --  R-Car VSP1 Driver
+  *
+  * Copyright (C) 2013-2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/clk.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index 54de15095709..72354caf5746 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_entity.c  --  R-Car VSP1 Base Entity
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index c26523c56c05..fb20a1578f3b 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_entity.h  --  R-Car VSP1 Base Entity
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_ENTITY_H__
+ #define __VSP1_ENTITY_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_hgo.c b/drivers/media/platform/vsp1/vsp1_hgo.c
+index 50309c053b78..d514807ccdf4 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgo.c
++++ b/drivers/media/platform/vsp1/vsp1_hgo.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_hgo.c  --  R-Car VSP1 Histogram Generator 1D
+  *
+  * Copyright (C) 2016 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_hgo.h b/drivers/media/platform/vsp1/vsp1_hgo.h
+index c6c0b7a80e0c..6b0c8580e1bf 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgo.h
++++ b/drivers/media/platform/vsp1/vsp1_hgo.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_hgo.h  --  R-Car VSP1 Histogram Generator 1D
+  *
+  * Copyright (C) 2016 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_HGO_H__
+ #define __VSP1_HGO_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_hgt.c b/drivers/media/platform/vsp1/vsp1_hgt.c
+index b5ce305e3e6f..18dc89f47c45 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgt.c
++++ b/drivers/media/platform/vsp1/vsp1_hgt.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_hgt.c  --  R-Car VSP1 Histogram Generator 2D
+  *
+  * Copyright (C) 2016 Renesas Electronics Corporation
+  *
+  * Contact: Niklas Söderlund (niklas.soderlund@ragnatech.se)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_hgt.h b/drivers/media/platform/vsp1/vsp1_hgt.h
+index 83f2e130942a..38ec237bdd2d 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgt.h
++++ b/drivers/media/platform/vsp1/vsp1_hgt.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_hgt.h  --  R-Car VSP1 Histogram Generator 2D
+  *
+  * Copyright (C) 2016 Renesas Electronics Corporation
+  *
+  * Contact: Niklas Söderlund (niklas.soderlund@ragnatech.se)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_HGT_H__
+ #define __VSP1_HGT_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_histo.c b/drivers/media/platform/vsp1/vsp1_histo.c
+index 8638ebc514b4..029181c1fb61 100644
+--- a/drivers/media/platform/vsp1/vsp1_histo.c
++++ b/drivers/media/platform/vsp1/vsp1_histo.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_histo.c  --  R-Car VSP1 Histogram API
+  *
+@@ -5,11 +6,6 @@
+  * Copyright (C) 2016 Laurent Pinchart
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_histo.h b/drivers/media/platform/vsp1/vsp1_histo.h
+index e774adbf251f..06f029846244 100644
+--- a/drivers/media/platform/vsp1/vsp1_histo.h
++++ b/drivers/media/platform/vsp1/vsp1_histo.h
+@@ -1,3 +1,4 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_histo.h  --  R-Car VSP1 Histogram API
+  *
+@@ -5,11 +6,6 @@
+  * Copyright (C) 2016 Laurent Pinchart
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_HISTO_H__
+ #define __VSP1_HISTO_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_hsit.c b/drivers/media/platform/vsp1/vsp1_hsit.c
+index 764d405345ee..7ba3535f3c9b 100644
+--- a/drivers/media/platform/vsp1/vsp1_hsit.c
++++ b/drivers/media/platform/vsp1/vsp1_hsit.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_hsit.c  --  R-Car VSP1 Hue Saturation value (Inverse) Transform
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_hsit.h b/drivers/media/platform/vsp1/vsp1_hsit.h
+index 82f1c8426900..a658b1aa49e7 100644
+--- a/drivers/media/platform/vsp1/vsp1_hsit.h
++++ b/drivers/media/platform/vsp1/vsp1_hsit.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_hsit.h  --  R-Car VSP1 Hue Saturation value (Inverse) Transform
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_HSIT_H__
+ #define __VSP1_HSIT_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index 704920753998..b20b842f06ba 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_lif.c  --  R-Car VSP1 LCD Controller Interface
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.h b/drivers/media/platform/vsp1/vsp1_lif.h
+index 3417339379b1..71a4eda9c2b2 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.h
++++ b/drivers/media/platform/vsp1/vsp1_lif.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_lif.h  --  R-Car VSP1 LCD Controller Interface
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_LIF_H__
+ #define __VSP1_LIF_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index c67cc60db0db..7bdabb311c6c 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_lut.c  --  R-Car VSP1 Look-Up Table
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.h b/drivers/media/platform/vsp1/vsp1_lut.h
+index f8c4e8f0a79d..dce2fdc315f6 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.h
++++ b/drivers/media/platform/vsp1/vsp1_lut.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_lut.h  --  R-Car VSP1 Look-Up Table
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_LUT_H__
+ #define __VSP1_LUT_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index 3fc5ecfa35e8..6fde4c0b9844 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
+  *
+  * Copyright (C) 2013-2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/delay.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index 07ccd6b810c5..663d7fed7929 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_pipe.h  --  R-Car VSP1 Pipeline
+  *
+  * Copyright (C) 2013-2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_PIPE_H__
+ #define __VSP1_PIPE_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h
+index dae0c1901297..3201ad4b77d4 100644
+--- a/drivers/media/platform/vsp1/vsp1_regs.h
++++ b/drivers/media/platform/vsp1/vsp1_regs.h
+@@ -1,13 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * vsp1_regs.h  --  R-Car VSP1 Registers Definitions
+  *
+  * Copyright (C) 2013 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2
+- * as published by the Free Software Foundation.
+  */
+ 
+ #ifndef __VSP1_REGS_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c
+index 7e74c2015070..7005a4c6aa88 100644
+--- a/drivers/media/platform/vsp1/vsp1_rpf.c
++++ b/drivers/media/platform/vsp1/vsp1_rpf.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_rpf.c  --  R-Car VSP1 Read Pixel Formatter
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c
+index cfd8f1904fa6..049bdd958e56 100644
+--- a/drivers/media/platform/vsp1/vsp1_rwpf.c
++++ b/drivers/media/platform/vsp1/vsp1_rwpf.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_rwpf.c  --  R-Car VSP1 Read and Write Pixel Formatters
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <media/v4l2-subdev.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h
+index 915aeadb21dd..70742ecf766f 100644
+--- a/drivers/media/platform/vsp1/vsp1_rwpf.h
++++ b/drivers/media/platform/vsp1/vsp1_rwpf.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_rwpf.h  --  R-Car VSP1 Read and Write Pixel Formatters
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_RWPF_H__
+ #define __VSP1_RWPF_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_sru.c b/drivers/media/platform/vsp1/vsp1_sru.c
+index 51e5691187c3..44cb9b134a19 100644
+--- a/drivers/media/platform/vsp1/vsp1_sru.c
++++ b/drivers/media/platform/vsp1/vsp1_sru.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_sru.c  --  R-Car VSP1 Super Resolution Unit
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_sru.h b/drivers/media/platform/vsp1/vsp1_sru.h
+index 85e241457af2..ddb00eadd1ea 100644
+--- a/drivers/media/platform/vsp1/vsp1_sru.h
++++ b/drivers/media/platform/vsp1/vsp1_sru.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_sru.h  --  R-Car VSP1 Super Resolution Unit
+  *
+  * Copyright (C) 2013 Renesas Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_SRU_H__
+ #define __VSP1_SRU_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c
+index 72f72a9d2152..e5afd69df939 100644
+--- a/drivers/media/platform/vsp1/vsp1_uds.c
++++ b/drivers/media/platform/vsp1/vsp1_uds.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_uds.c  --  R-Car VSP1 Up and Down Scaler
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_uds.h b/drivers/media/platform/vsp1/vsp1_uds.h
+index 7bf3cdcffc65..2cd9f4b95442 100644
+--- a/drivers/media/platform/vsp1/vsp1_uds.h
++++ b/drivers/media/platform/vsp1/vsp1_uds.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_uds.h  --  R-Car VSP1 Up and Down Scaler
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_UDS_H__
+ #define __VSP1_UDS_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index c41a4495a874..ba89dd176a13 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_video.c  --  R-Car VSP1 Video Node
+  *
+  * Copyright (C) 2013-2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/list.h>
+diff --git a/drivers/media/platform/vsp1/vsp1_video.h b/drivers/media/platform/vsp1/vsp1_video.h
+index 50ea7f02205f..75a5a65c66fe 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.h
++++ b/drivers/media/platform/vsp1/vsp1_video.h
+@@ -1,14 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
+ /*
+  * vsp1_video.h  --  R-Car VSP1 Video Node
+  *
+  * Copyright (C) 2013-2015 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ #ifndef __VSP1_VIDEO_H__
+ #define __VSP1_VIDEO_H__
+diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c
+index 53858d100228..65ed2f849551 100644
+--- a/drivers/media/platform/vsp1/vsp1_wpf.c
++++ b/drivers/media/platform/vsp1/vsp1_wpf.c
+@@ -1,14 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * vsp1_wpf.c  --  R-Car VSP1 Write Pixel Formatter
+  *
+  * Copyright (C) 2013-2014 Renesas Electronics Corporation
+  *
+  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+  */
+ 
+ #include <linux/device.h>
+-- 
+2.19.0
+
diff --git a/patches/1187-media-v4l-vsp1-Share-the-CLU-LIF-and-LUT-set_fmt-pad.patch b/patches/1187-media-v4l-vsp1-Share-the-CLU-LIF-and-LUT-set_fmt-pad.patch
new file mode 100644
index 00000000000000..c5b3a2bbf1f454
--- /dev/null
+++ b/patches/1187-media-v4l-vsp1-Share-the-CLU-LIF-and-LUT-set_fmt-pad.patch
@@ -0,0 +1,390 @@
+From f7c46b5b1633979a3da1450601e58e6c452c62e9 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Mon, 27 Nov 2017 14:59:45 -0500
+Subject: [PATCH 1187/1795] media: v4l: vsp1: Share the CLU, LIF and LUT
+ set_fmt pad operation code
+
+The implementation of the set_fmt pad operation is identical in the
+three modules. Move it to a generic helper function.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit b4ccae1025f3c7dac3c35019369627622ec01e94)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_clu.c    | 65 ++++----------------
+ drivers/media/platform/vsp1/vsp1_entity.c | 75 +++++++++++++++++++++++
+ drivers/media/platform/vsp1/vsp1_entity.h |  6 ++
+ drivers/media/platform/vsp1/vsp1_lif.c    | 65 ++++----------------
+ drivers/media/platform/vsp1/vsp1_lut.c    | 65 ++++----------------
+ 5 files changed, 116 insertions(+), 160 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index 9626b6308585..96a448e1504c 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -114,18 +114,18 @@ static const struct v4l2_ctrl_config clu_mode_control = {
+  * V4L2 Subdevice Pad Operations
+  */
+ 
++static const unsigned int clu_codes[] = {
++	MEDIA_BUS_FMT_ARGB8888_1X32,
++	MEDIA_BUS_FMT_AHSV8888_1X32,
++	MEDIA_BUS_FMT_AYUV8_1X32,
++};
++
+ static int clu_enum_mbus_code(struct v4l2_subdev *subdev,
+ 			      struct v4l2_subdev_pad_config *cfg,
+ 			      struct v4l2_subdev_mbus_code_enum *code)
+ {
+-	static const unsigned int codes[] = {
+-		MEDIA_BUS_FMT_ARGB8888_1X32,
+-		MEDIA_BUS_FMT_AHSV8888_1X32,
+-		MEDIA_BUS_FMT_AYUV8_1X32,
+-	};
+-
+-	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, codes,
+-					  ARRAY_SIZE(codes));
++	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, clu_codes,
++					  ARRAY_SIZE(clu_codes));
+ }
+ 
+ static int clu_enum_frame_size(struct v4l2_subdev *subdev,
+@@ -141,51 +141,10 @@ static int clu_set_format(struct v4l2_subdev *subdev,
+ 			  struct v4l2_subdev_pad_config *cfg,
+ 			  struct v4l2_subdev_format *fmt)
+ {
+-	struct vsp1_clu *clu = to_clu(subdev);
+-	struct v4l2_subdev_pad_config *config;
+-	struct v4l2_mbus_framefmt *format;
+-	int ret = 0;
+-
+-	mutex_lock(&clu->entity.lock);
+-
+-	config = vsp1_entity_get_pad_config(&clu->entity, cfg, fmt->which);
+-	if (!config) {
+-		ret = -EINVAL;
+-		goto done;
+-	}
+-
+-	/* Default to YUV if the requested format is not supported. */
+-	if (fmt->format.code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
+-	    fmt->format.code != MEDIA_BUS_FMT_AHSV8888_1X32 &&
+-	    fmt->format.code != MEDIA_BUS_FMT_AYUV8_1X32)
+-		fmt->format.code = MEDIA_BUS_FMT_AYUV8_1X32;
+-
+-	format = vsp1_entity_get_pad_format(&clu->entity, config, fmt->pad);
+-
+-	if (fmt->pad == CLU_PAD_SOURCE) {
+-		/* The CLU output format can't be modified. */
+-		fmt->format = *format;
+-		goto done;
+-	}
+-
+-	format->code = fmt->format.code;
+-	format->width = clamp_t(unsigned int, fmt->format.width,
+-				CLU_MIN_SIZE, CLU_MAX_SIZE);
+-	format->height = clamp_t(unsigned int, fmt->format.height,
+-				 CLU_MIN_SIZE, CLU_MAX_SIZE);
+-	format->field = V4L2_FIELD_NONE;
+-	format->colorspace = V4L2_COLORSPACE_SRGB;
+-
+-	fmt->format = *format;
+-
+-	/* Propagate the format to the source pad. */
+-	format = vsp1_entity_get_pad_format(&clu->entity, config,
+-					    CLU_PAD_SOURCE);
+-	*format = fmt->format;
+-
+-done:
+-	mutex_unlock(&clu->entity.lock);
+-	return ret;
++	return vsp1_subdev_set_pad_format(subdev, cfg, fmt, clu_codes,
++					  ARRAY_SIZE(clu_codes),
++					  CLU_MIN_SIZE, CLU_MIN_SIZE,
++					  CLU_MAX_SIZE, CLU_MAX_SIZE);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index 72354caf5746..9195a0eca467 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -307,6 +307,81 @@ int vsp1_subdev_enum_frame_size(struct v4l2_subdev *subdev,
+ 	return ret;
+ }
+ 
++/*
++ * vsp1_subdev_set_pad_format - Subdev pad set_fmt handler
++ * @subdev: V4L2 subdevice
++ * @cfg: V4L2 subdev pad configuration
++ * @fmt: V4L2 subdev format
++ * @codes: Array of supported media bus codes
++ * @ncodes: Number of supported media bus codes
++ * @min_width: Minimum image width
++ * @min_height: Minimum image height
++ * @max_width: Maximum image width
++ * @max_height: Maximum image height
++ *
++ * This function implements the subdev set_fmt pad operation for entities that
++ * do not support scaling or cropping. It defaults to the first supplied media
++ * bus code if the requested code isn't supported, clamps the size to the
++ * supplied minimum and maximum, and propagates the sink pad format to the
++ * source pad.
++ */
++int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,
++			       struct v4l2_subdev_pad_config *cfg,
++			       struct v4l2_subdev_format *fmt,
++			       const unsigned int *codes, unsigned int ncodes,
++			       unsigned int min_width, unsigned int min_height,
++			       unsigned int max_width, unsigned int max_height)
++{
++	struct vsp1_entity *entity = to_vsp1_entity(subdev);
++	struct v4l2_subdev_pad_config *config;
++	struct v4l2_mbus_framefmt *format;
++	unsigned int i;
++	int ret = 0;
++
++	mutex_lock(&entity->lock);
++
++	config = vsp1_entity_get_pad_config(entity, cfg, fmt->which);
++	if (!config) {
++		ret = -EINVAL;
++		goto done;
++	}
++
++	format = vsp1_entity_get_pad_format(entity, config, fmt->pad);
++
++	if (fmt->pad == entity->source_pad) {
++		/* The output format can't be modified. */
++		fmt->format = *format;
++		goto done;
++	}
++
++	/*
++	 * Default to the first media bus code if the requested format is not
++	 * supported.
++	 */
++	for (i = 0; i < ncodes; ++i) {
++		if (fmt->format.code == codes[i])
++			break;
++	}
++
++	format->code = i < ncodes ? codes[i] : codes[0];
++	format->width = clamp_t(unsigned int, fmt->format.width,
++				min_width, max_width);
++	format->height = clamp_t(unsigned int, fmt->format.height,
++				 min_height, max_height);
++	format->field = V4L2_FIELD_NONE;
++	format->colorspace = V4L2_COLORSPACE_SRGB;
++
++	fmt->format = *format;
++
++	/* Propagate the format to the source pad. */
++	format = vsp1_entity_get_pad_format(entity, config, entity->source_pad);
++	*format = fmt->format;
++
++done:
++	mutex_unlock(&entity->lock);
++	return ret;
++}
++
+ /* -----------------------------------------------------------------------------
+  * Media Operations
+  */
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index fb20a1578f3b..0839a62cfa71 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -160,6 +160,12 @@ struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad);
+ int vsp1_subdev_get_pad_format(struct v4l2_subdev *subdev,
+ 			       struct v4l2_subdev_pad_config *cfg,
+ 			       struct v4l2_subdev_format *fmt);
++int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,
++			       struct v4l2_subdev_pad_config *cfg,
++			       struct v4l2_subdev_format *fmt,
++			       const unsigned int *codes, unsigned int ncodes,
++			       unsigned int min_width, unsigned int min_height,
++			       unsigned int max_width, unsigned int max_height);
+ int vsp1_subdev_enum_mbus_code(struct v4l2_subdev *subdev,
+ 			       struct v4l2_subdev_pad_config *cfg,
+ 			       struct v4l2_subdev_mbus_code_enum *code,
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index b20b842f06ba..fbdd5715f829 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -33,17 +33,17 @@ static inline void vsp1_lif_write(struct vsp1_lif *lif, struct vsp1_dl_list *dl,
+  * V4L2 Subdevice Operations
+  */
+ 
++static const unsigned int lif_codes[] = {
++	MEDIA_BUS_FMT_ARGB8888_1X32,
++	MEDIA_BUS_FMT_AYUV8_1X32,
++};
++
+ static int lif_enum_mbus_code(struct v4l2_subdev *subdev,
+ 			      struct v4l2_subdev_pad_config *cfg,
+ 			      struct v4l2_subdev_mbus_code_enum *code)
+ {
+-	static const unsigned int codes[] = {
+-		MEDIA_BUS_FMT_ARGB8888_1X32,
+-		MEDIA_BUS_FMT_AYUV8_1X32,
+-	};
+-
+-	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, codes,
+-					  ARRAY_SIZE(codes));
++	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, lif_codes,
++					  ARRAY_SIZE(lif_codes));
+ }
+ 
+ static int lif_enum_frame_size(struct v4l2_subdev *subdev,
+@@ -59,53 +59,10 @@ static int lif_set_format(struct v4l2_subdev *subdev,
+ 			  struct v4l2_subdev_pad_config *cfg,
+ 			  struct v4l2_subdev_format *fmt)
+ {
+-	struct vsp1_lif *lif = to_lif(subdev);
+-	struct v4l2_subdev_pad_config *config;
+-	struct v4l2_mbus_framefmt *format;
+-	int ret = 0;
+-
+-	mutex_lock(&lif->entity.lock);
+-
+-	config = vsp1_entity_get_pad_config(&lif->entity, cfg, fmt->which);
+-	if (!config) {
+-		ret = -EINVAL;
+-		goto done;
+-	}
+-
+-	/* Default to YUV if the requested format is not supported. */
+-	if (fmt->format.code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
+-	    fmt->format.code != MEDIA_BUS_FMT_AYUV8_1X32)
+-		fmt->format.code = MEDIA_BUS_FMT_AYUV8_1X32;
+-
+-	format = vsp1_entity_get_pad_format(&lif->entity, config, fmt->pad);
+-
+-	if (fmt->pad == LIF_PAD_SOURCE) {
+-		/*
+-		 * The LIF source format is always identical to its sink
+-		 * format.
+-		 */
+-		fmt->format = *format;
+-		goto done;
+-	}
+-
+-	format->code = fmt->format.code;
+-	format->width = clamp_t(unsigned int, fmt->format.width,
+-				LIF_MIN_SIZE, LIF_MAX_SIZE);
+-	format->height = clamp_t(unsigned int, fmt->format.height,
+-				 LIF_MIN_SIZE, LIF_MAX_SIZE);
+-	format->field = V4L2_FIELD_NONE;
+-	format->colorspace = V4L2_COLORSPACE_SRGB;
+-
+-	fmt->format = *format;
+-
+-	/* Propagate the format to the source pad. */
+-	format = vsp1_entity_get_pad_format(&lif->entity, config,
+-					    LIF_PAD_SOURCE);
+-	*format = fmt->format;
+-
+-done:
+-	mutex_unlock(&lif->entity.lock);
+-	return ret;
++	return vsp1_subdev_set_pad_format(subdev, cfg, fmt, lif_codes,
++					  ARRAY_SIZE(lif_codes),
++					  LIF_MIN_SIZE, LIF_MIN_SIZE,
++					  LIF_MAX_SIZE, LIF_MAX_SIZE);
+ }
+ 
+ static const struct v4l2_subdev_pad_ops lif_pad_ops = {
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index 7bdabb311c6c..f2e48a02ca7d 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -90,18 +90,18 @@ static const struct v4l2_ctrl_config lut_table_control = {
+  * V4L2 Subdevice Pad Operations
+  */
+ 
++static const unsigned int lut_codes[] = {
++	MEDIA_BUS_FMT_ARGB8888_1X32,
++	MEDIA_BUS_FMT_AHSV8888_1X32,
++	MEDIA_BUS_FMT_AYUV8_1X32,
++};
++
+ static int lut_enum_mbus_code(struct v4l2_subdev *subdev,
+ 			      struct v4l2_subdev_pad_config *cfg,
+ 			      struct v4l2_subdev_mbus_code_enum *code)
+ {
+-	static const unsigned int codes[] = {
+-		MEDIA_BUS_FMT_ARGB8888_1X32,
+-		MEDIA_BUS_FMT_AHSV8888_1X32,
+-		MEDIA_BUS_FMT_AYUV8_1X32,
+-	};
+-
+-	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, codes,
+-					  ARRAY_SIZE(codes));
++	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, lut_codes,
++					  ARRAY_SIZE(lut_codes));
+ }
+ 
+ static int lut_enum_frame_size(struct v4l2_subdev *subdev,
+@@ -117,51 +117,10 @@ static int lut_set_format(struct v4l2_subdev *subdev,
+ 			  struct v4l2_subdev_pad_config *cfg,
+ 			  struct v4l2_subdev_format *fmt)
+ {
+-	struct vsp1_lut *lut = to_lut(subdev);
+-	struct v4l2_subdev_pad_config *config;
+-	struct v4l2_mbus_framefmt *format;
+-	int ret = 0;
+-
+-	mutex_lock(&lut->entity.lock);
+-
+-	config = vsp1_entity_get_pad_config(&lut->entity, cfg, fmt->which);
+-	if (!config) {
+-		ret = -EINVAL;
+-		goto done;
+-	}
+-
+-	/* Default to YUV if the requested format is not supported. */
+-	if (fmt->format.code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
+-	    fmt->format.code != MEDIA_BUS_FMT_AHSV8888_1X32 &&
+-	    fmt->format.code != MEDIA_BUS_FMT_AYUV8_1X32)
+-		fmt->format.code = MEDIA_BUS_FMT_AYUV8_1X32;
+-
+-	format = vsp1_entity_get_pad_format(&lut->entity, config, fmt->pad);
+-
+-	if (fmt->pad == LUT_PAD_SOURCE) {
+-		/* The LUT output format can't be modified. */
+-		fmt->format = *format;
+-		goto done;
+-	}
+-
+-	format->code = fmt->format.code;
+-	format->width = clamp_t(unsigned int, fmt->format.width,
+-				LUT_MIN_SIZE, LUT_MAX_SIZE);
+-	format->height = clamp_t(unsigned int, fmt->format.height,
+-				 LUT_MIN_SIZE, LUT_MAX_SIZE);
+-	format->field = V4L2_FIELD_NONE;
+-	format->colorspace = V4L2_COLORSPACE_SRGB;
+-
+-	fmt->format = *format;
+-
+-	/* Propagate the format to the source pad. */
+-	format = vsp1_entity_get_pad_format(&lut->entity, config,
+-					    LUT_PAD_SOURCE);
+-	*format = fmt->format;
+-
+-done:
+-	mutex_unlock(&lut->entity.lock);
+-	return ret;
++	return vsp1_subdev_set_pad_format(subdev, cfg, fmt, lut_codes,
++					  ARRAY_SIZE(lut_codes),
++					  LUT_MIN_SIZE, LUT_MIN_SIZE,
++					  LUT_MAX_SIZE, LUT_MAX_SIZE);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+-- 
+2.19.0
+
diff --git a/patches/1188-media-v4l-vsp1-Reset-the-crop-and-compose-rectangles.patch b/patches/1188-media-v4l-vsp1-Reset-the-crop-and-compose-rectangles.patch
new file mode 100644
index 00000000000000..8027e273e8661d
--- /dev/null
+++ b/patches/1188-media-v4l-vsp1-Reset-the-crop-and-compose-rectangles.patch
@@ -0,0 +1,139 @@
+From e3ec5ce96b24f9b0ab2171a082d20bf745f93197 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Mon, 27 Nov 2017 19:27:32 -0500
+Subject: [PATCH 1188/1795] media: v4l: vsp1: Reset the crop and compose
+ rectangles in the set_fmt helper
+
+To make vsp1_subdev_set_pad_format() usable by entities that support
+selection rectangles, we need to reset the crop and compose rectangles
+when setting the format on the sink pad. Do so and replace the custom
+set_fmt implementation of the histogram code by a call to
+vsp1_subdev_set_pad_format().
+
+Resetting the crop and compose rectangles for entities that don't
+support crop and compose has no adverse effect as the rectangles are
+ignored anyway.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 3d7899c21fbba1706014fcbb2a499ea24e6f103c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_entity.c | 16 ++++++
+ drivers/media/platform/vsp1/vsp1_histo.c  | 59 ++---------------------
+ 2 files changed, 20 insertions(+), 55 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index 9195a0eca467..f10c61339d46 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -335,6 +335,7 @@ int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,
+ 	struct vsp1_entity *entity = to_vsp1_entity(subdev);
+ 	struct v4l2_subdev_pad_config *config;
+ 	struct v4l2_mbus_framefmt *format;
++	struct v4l2_rect *selection;
+ 	unsigned int i;
+ 	int ret = 0;
+ 
+@@ -377,6 +378,21 @@ int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,
+ 	format = vsp1_entity_get_pad_format(entity, config, entity->source_pad);
+ 	*format = fmt->format;
+ 
++	/* Reset the crop and compose rectangles */
++	selection = vsp1_entity_get_pad_selection(entity, config, fmt->pad,
++						  V4L2_SEL_TGT_CROP);
++	selection->left = 0;
++	selection->top = 0;
++	selection->width = format->width;
++	selection->height = format->height;
++
++	selection = vsp1_entity_get_pad_selection(entity, config, fmt->pad,
++						  V4L2_SEL_TGT_COMPOSE);
++	selection->left = 0;
++	selection->top = 0;
++	selection->width = format->width;
++	selection->height = format->height;
++
+ done:
+ 	mutex_unlock(&entity->lock);
+ 	return ret;
+diff --git a/drivers/media/platform/vsp1/vsp1_histo.c b/drivers/media/platform/vsp1/vsp1_histo.c
+index 029181c1fb61..5e15c8ff88d9 100644
+--- a/drivers/media/platform/vsp1/vsp1_histo.c
++++ b/drivers/media/platform/vsp1/vsp1_histo.c
+@@ -389,65 +389,14 @@ static int histo_set_format(struct v4l2_subdev *subdev,
+ 			    struct v4l2_subdev_format *fmt)
+ {
+ 	struct vsp1_histogram *histo = subdev_to_histo(subdev);
+-	struct v4l2_subdev_pad_config *config;
+-	struct v4l2_mbus_framefmt *format;
+-	struct v4l2_rect *selection;
+-	unsigned int i;
+-	int ret = 0;
+ 
+ 	if (fmt->pad != HISTO_PAD_SINK)
+ 		return histo_get_format(subdev, cfg, fmt);
+ 
+-	mutex_lock(&histo->entity.lock);
+-
+-	config = vsp1_entity_get_pad_config(&histo->entity, cfg, fmt->which);
+-	if (!config) {
+-		ret = -EINVAL;
+-		goto done;
+-	}
+-
+-	/*
+-	 * Default to the first format if the requested format is not
+-	 * supported.
+-	 */
+-	for (i = 0; i < histo->num_formats; ++i) {
+-		if (fmt->format.code == histo->formats[i])
+-			break;
+-	}
+-	if (i == histo->num_formats)
+-		fmt->format.code = histo->formats[0];
+-
+-	format = vsp1_entity_get_pad_format(&histo->entity, config, fmt->pad);
+-
+-	format->code = fmt->format.code;
+-	format->width = clamp_t(unsigned int, fmt->format.width,
+-				HISTO_MIN_SIZE, HISTO_MAX_SIZE);
+-	format->height = clamp_t(unsigned int, fmt->format.height,
+-				 HISTO_MIN_SIZE, HISTO_MAX_SIZE);
+-	format->field = V4L2_FIELD_NONE;
+-	format->colorspace = V4L2_COLORSPACE_SRGB;
+-
+-	fmt->format = *format;
+-
+-	/* Reset the crop and compose rectangles */
+-	selection = vsp1_entity_get_pad_selection(&histo->entity, config,
+-						  fmt->pad, V4L2_SEL_TGT_CROP);
+-	selection->left = 0;
+-	selection->top = 0;
+-	selection->width = format->width;
+-	selection->height = format->height;
+-
+-	selection = vsp1_entity_get_pad_selection(&histo->entity, config,
+-						  fmt->pad,
+-						  V4L2_SEL_TGT_COMPOSE);
+-	selection->left = 0;
+-	selection->top = 0;
+-	selection->width = format->width;
+-	selection->height = format->height;
+-
+-done:
+-	mutex_unlock(&histo->entity.lock);
+-	return ret;
++	return vsp1_subdev_set_pad_format(subdev, cfg, fmt,
++					  histo->formats, histo->num_formats,
++					  HISTO_MIN_SIZE, HISTO_MIN_SIZE,
++					  HISTO_MAX_SIZE, HISTO_MAX_SIZE);
+ }
+ 
+ static const struct v4l2_subdev_pad_ops histo_pad_ops = {
+-- 
+2.19.0
+
diff --git a/patches/1189-media-v4l-vsp1-Document-the-vsp1_du_atomic_config-st.patch b/patches/1189-media-v4l-vsp1-Document-the-vsp1_du_atomic_config-st.patch
new file mode 100644
index 00000000000000..521bf24feae696
--- /dev/null
+++ b/patches/1189-media-v4l-vsp1-Document-the-vsp1_du_atomic_config-st.patch
@@ -0,0 +1,43 @@
+From 8b0fc42ca5c1a488585e20010d00a3d0c1fc7441 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 30 Nov 2017 11:32:18 -0500
+Subject: [PATCH 1189/1795] media: v4l: vsp1: Document the
+ vsp1_du_atomic_config structure
+
+The structure is used in the API that the VSP1 driver exposes to the DU
+driver. Documenting it is thus important.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 0d93d5c915d5b8a7f74f6d3e59748c06adcf6e9f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/media/vsp1.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/include/media/vsp1.h b/include/media/vsp1.h
+index 68a8abe4fac5..ff7ef894465d 100644
+--- a/include/media/vsp1.h
++++ b/include/media/vsp1.h
+@@ -41,6 +41,16 @@ struct vsp1_du_lif_config {
+ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
+ 		      const struct vsp1_du_lif_config *cfg);
+ 
++/**
++ * struct vsp1_du_atomic_config - VSP atomic configuration parameters
++ * @pixelformat: plane pixel format (V4L2 4CC)
++ * @pitch: line pitch in bytes, for all planes
++ * @mem: DMA memory address for each plane of the frame buffer
++ * @src: source rectangle in the frame buffer (integer coordinates)
++ * @dst: destination rectangle on the display (integer coordinates)
++ * @alpha: alpha value (0: fully transparent, 255: fully opaque)
++ * @zpos: Z position of the plane (from 0 to number of planes minus 1)
++ */
+ struct vsp1_du_atomic_config {
+ 	u32 pixelformat;
+ 	unsigned int pitch;
+-- 
+2.19.0
+
diff --git a/patches/1190-media-v4l-vsp1-Extend-the-DU-API-to-support-CRC-comp.patch b/patches/1190-media-v4l-vsp1-Extend-the-DU-API-to-support-CRC-comp.patch
new file mode 100644
index 00000000000000..79249ebab31c0a
--- /dev/null
+++ b/patches/1190-media-v4l-vsp1-Extend-the-DU-API-to-support-CRC-comp.patch
@@ -0,0 +1,146 @@
+From f7bb567f938136f961da61f9477241e2e916bf1c Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 1 Dec 2017 06:47:19 -0500
+Subject: [PATCH 1190/1795] media: v4l: vsp1: Extend the DU API to support CRC
+ computation
+
+Add a parameter (in the form of a structure to ease future API
+extensions) to the VSP atomic flush handler to pass CRC source
+configuration, and pass the CRC value to the completion callback.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 6e274b43b5730f53029354fc10c0beabefed60e2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c  |  6 +++--
+ drivers/media/platform/vsp1/vsp1_drm.c |  6 +++--
+ drivers/media/platform/vsp1/vsp1_drm.h |  2 +-
+ include/media/vsp1.h                   | 35 ++++++++++++++++++++++++--
+ 4 files changed, 42 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index 2c260c33840b..bdcec201591f 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -31,7 +31,7 @@
+ #include "rcar_du_kms.h"
+ #include "rcar_du_vsp.h"
+ 
+-static void rcar_du_vsp_complete(void *private, bool completed)
++static void rcar_du_vsp_complete(void *private, bool completed, u32 crc)
+ {
+ 	struct rcar_du_crtc *crtc = private;
+ 
+@@ -102,7 +102,9 @@ void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
+ 
+ void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
+ {
+-	vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe);
++	struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
++
++	vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, &cfg);
+ }
+ 
+ /* Keep the two tables in sync. */
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 2b29a83dceb9..5fc31578f9b0 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -36,7 +36,7 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 	bool complete = completion == VSP1_DL_FRAME_END_COMPLETED;
+ 
+ 	if (drm_pipe->du_complete)
+-		drm_pipe->du_complete(drm_pipe->du_private, complete);
++		drm_pipe->du_complete(drm_pipe->du_private, complete, 0);
+ 
+ 	if (completion & VSP1_DL_FRAME_END_INTERNAL) {
+ 		drm_pipe->force_brx_release = false;
+@@ -739,8 +739,10 @@ EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
+  * vsp1_du_atomic_flush - Commit an atomic update
+  * @dev: the VSP device
+  * @pipe_index: the DRM pipeline index
++ * @cfg: atomic pipe configuration
+  */
+-void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
++void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
++			  const struct vsp1_du_atomic_pipe_config *cfg)
+ {
+ 	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
+ 	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index f4af1b2b12d6..e5b88b28806c 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -35,7 +35,7 @@ struct vsp1_drm_pipeline {
+ 	wait_queue_head_t wait_queue;
+ 
+ 	/* Frame synchronisation */
+-	void (*du_complete)(void *, bool);
++	void (*du_complete)(void *data, bool completed, u32 crc);
+ 	void *du_private;
+ };
+ 
+diff --git a/include/media/vsp1.h b/include/media/vsp1.h
+index ff7ef894465d..678c24de1ac6 100644
+--- a/include/media/vsp1.h
++++ b/include/media/vsp1.h
+@@ -34,7 +34,7 @@ struct vsp1_du_lif_config {
+ 	unsigned int width;
+ 	unsigned int height;
+ 
+-	void (*callback)(void *, bool);
++	void (*callback)(void *data, bool completed, u32 crc);
+ 	void *callback_data;
+ };
+ 
+@@ -61,11 +61,42 @@ struct vsp1_du_atomic_config {
+ 	unsigned int zpos;
+ };
+ 
++/**
++ * enum vsp1_du_crc_source - Source used for CRC calculation
++ * @VSP1_DU_CRC_NONE: CRC calculation disabled
++ * @VSP1_DU_CRC_PLANE: Perform CRC calculation on an input plane
++ * @VSP1_DU_CRC_OUTPUT: Perform CRC calculation on the composed output
++ */
++enum vsp1_du_crc_source {
++	VSP1_DU_CRC_NONE,
++	VSP1_DU_CRC_PLANE,
++	VSP1_DU_CRC_OUTPUT,
++};
++
++/**
++ * struct vsp1_du_crc_config - VSP CRC computation configuration parameters
++ * @source: source for CRC calculation
++ * @index: index of the CRC source plane (when source is set to plane)
++ */
++struct vsp1_du_crc_config {
++	enum vsp1_du_crc_source source;
++	unsigned int index;
++};
++
++/**
++ * struct vsp1_du_atomic_pipe_config - VSP atomic pipe configuration parameters
++ * @crc: CRC computation configuration
++ */
++struct vsp1_du_atomic_pipe_config {
++	struct vsp1_du_crc_config crc;
++};
++
+ void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index);
+ int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
+ 			  unsigned int rpf,
+ 			  const struct vsp1_du_atomic_config *cfg);
+-void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index);
++void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
++			  const struct vsp1_du_atomic_pipe_config *cfg);
+ int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt);
+ void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1191-media-v4l-vsp1-Add-support-for-the-DISCOM-entity.patch b/patches/1191-media-v4l-vsp1-Add-support-for-the-DISCOM-entity.patch
new file mode 100644
index 00000000000000..9f862d71feea0a
--- /dev/null
+++ b/patches/1191-media-v4l-vsp1-Add-support-for-the-DISCOM-entity.patch
@@ -0,0 +1,567 @@
+From b333a9c703462b1f665c5cc41aeab7c867c2054d Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Mon, 27 Nov 2017 15:45:42 -0500
+Subject: [PATCH 1191/1795] media: v4l: vsp1: Add support for the DISCOM entity
+
+The DISCOM calculates a CRC on a configurable window of the frame. It
+interfaces to the VSP through the UIF glue, hence the name used in the
+code.
+
+The module supports configuration of the CRC window through the crop
+rectangle on the sink pad of the corresponding entity. However, unlike
+the traditional V4L2 subdevice model, the crop rectangle does not
+influence the format on the source pad.
+
+Modeling the DISCOM as a sink-only entity would allow adhering to the
+V4L2 subdevice model at the expense of more complex code in the driver,
+as at the hardware level the UIF is handled as a sink+source entity. As
+the DISCOM is only present in R-Car Gen3 VSP-D and VSP-DL instances it
+is not exposed to userspace through V4L2 but controlled through the DU
+driver. We can thus change this model later if needed without fear of
+affecting userspace.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 33025a5c661a9cc9a48af5e00b7fd4ea0bd36008)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/Makefile      |   2 +-
+ drivers/media/platform/vsp1/vsp1.h        |   4 +
+ drivers/media/platform/vsp1/vsp1_drv.c    |  20 ++
+ drivers/media/platform/vsp1/vsp1_entity.c |   6 +
+ drivers/media/platform/vsp1/vsp1_entity.h |   1 +
+ drivers/media/platform/vsp1/vsp1_regs.h   |  41 ++++
+ drivers/media/platform/vsp1/vsp1_uif.c    | 271 ++++++++++++++++++++++
+ drivers/media/platform/vsp1/vsp1_uif.h    |  32 +++
+ 8 files changed, 376 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/media/platform/vsp1/vsp1_uif.c
+ create mode 100644 drivers/media/platform/vsp1/vsp1_uif.h
+
+diff --git a/drivers/media/platform/vsp1/Makefile b/drivers/media/platform/vsp1/Makefile
+index 596775f932c0..4bb4dcbef7b5 100644
+--- a/drivers/media/platform/vsp1/Makefile
++++ b/drivers/media/platform/vsp1/Makefile
+@@ -5,6 +5,6 @@ vsp1-y					+= vsp1_rpf.o vsp1_rwpf.o vsp1_wpf.o
+ vsp1-y					+= vsp1_clu.o vsp1_hsit.o vsp1_lut.o
+ vsp1-y					+= vsp1_brx.o vsp1_sru.o vsp1_uds.o
+ vsp1-y					+= vsp1_hgo.o vsp1_hgt.o vsp1_histo.o
+-vsp1-y					+= vsp1_lif.o
++vsp1-y					+= vsp1_lif.o vsp1_uif.o
+ 
+ obj-$(CONFIG_VIDEO_RENESAS_VSP1)	+= vsp1.o
+diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h
+index 9cf4e1c4b036..33f632331474 100644
+--- a/drivers/media/platform/vsp1/vsp1.h
++++ b/drivers/media/platform/vsp1/vsp1.h
+@@ -36,10 +36,12 @@ struct vsp1_lut;
+ struct vsp1_rwpf;
+ struct vsp1_sru;
+ struct vsp1_uds;
++struct vsp1_uif;
+ 
+ #define VSP1_MAX_LIF		2
+ #define VSP1_MAX_RPF		5
+ #define VSP1_MAX_UDS		3
++#define VSP1_MAX_UIF		2
+ #define VSP1_MAX_WPF		4
+ 
+ #define VSP1_HAS_LUT		(1 << 1)
+@@ -60,6 +62,7 @@ struct vsp1_device_info {
+ 	unsigned int lif_count;
+ 	unsigned int rpf_count;
+ 	unsigned int uds_count;
++	unsigned int uif_count;
+ 	unsigned int wpf_count;
+ 	unsigned int num_bru_inputs;
+ 	bool uapi;
+@@ -86,6 +89,7 @@ struct vsp1_device {
+ 	struct vsp1_rwpf *rpf[VSP1_MAX_RPF];
+ 	struct vsp1_sru *sru;
+ 	struct vsp1_uds *uds[VSP1_MAX_UDS];
++	struct vsp1_uif *uif[VSP1_MAX_UIF];
+ 	struct vsp1_rwpf *wpf[VSP1_MAX_WPF];
+ 
+ 	struct list_head entities;
+diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c
+index 331a2e0af0d3..d29f9c4baebe 100644
+--- a/drivers/media/platform/vsp1/vsp1_drv.c
++++ b/drivers/media/platform/vsp1/vsp1_drv.c
+@@ -35,6 +35,7 @@
+ #include "vsp1_rwpf.h"
+ #include "vsp1_sru.h"
+ #include "vsp1_uds.h"
++#include "vsp1_uif.h"
+ #include "vsp1_video.h"
+ 
+ /* -----------------------------------------------------------------------------
+@@ -409,6 +410,19 @@ static int vsp1_create_entities(struct vsp1_device *vsp1)
+ 		list_add_tail(&uds->entity.list_dev, &vsp1->entities);
+ 	}
+ 
++	for (i = 0; i < vsp1->info->uif_count; ++i) {
++		struct vsp1_uif *uif;
++
++		uif = vsp1_uif_create(vsp1, i);
++		if (IS_ERR(uif)) {
++			ret = PTR_ERR(uif);
++			goto done;
++		}
++
++		vsp1->uif[i] = uif;
++		list_add_tail(&uif->entity.list_dev, &vsp1->entities);
++	}
++
+ 	for (i = 0; i < vsp1->info->wpf_count; ++i) {
+ 		struct vsp1_rwpf *wpf;
+ 
+@@ -513,6 +527,9 @@ static int vsp1_device_init(struct vsp1_device *vsp1)
+ 	for (i = 0; i < vsp1->info->uds_count; ++i)
+ 		vsp1_write(vsp1, VI6_DPR_UDS_ROUTE(i), VI6_DPR_NODE_UNUSED);
+ 
++	for (i = 0; i < vsp1->info->uif_count; ++i)
++		vsp1_write(vsp1, VI6_DPR_UIF_ROUTE(i), VI6_DPR_NODE_UNUSED);
++
+ 	vsp1_write(vsp1, VI6_DPR_SRU_ROUTE, VI6_DPR_NODE_UNUSED);
+ 	vsp1_write(vsp1, VI6_DPR_LUT_ROUTE, VI6_DPR_NODE_UNUSED);
+ 	vsp1_write(vsp1, VI6_DPR_CLU_ROUTE, VI6_DPR_NODE_UNUSED);
+@@ -740,6 +757,7 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
+ 		.features = VSP1_HAS_BRU | VSP1_HAS_WPF_VFLIP,
+ 		.lif_count = 1,
+ 		.rpf_count = 5,
++		.uif_count = 1,
+ 		.wpf_count = 2,
+ 		.num_bru_inputs = 5,
+ 	}, {
+@@ -749,6 +767,7 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
+ 		.features = VSP1_HAS_BRS | VSP1_HAS_BRU,
+ 		.lif_count = 1,
+ 		.rpf_count = 5,
++		.uif_count = 1,
+ 		.wpf_count = 1,
+ 		.num_bru_inputs = 5,
+ 	}, {
+@@ -758,6 +777,7 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
+ 		.features = VSP1_HAS_BRS | VSP1_HAS_BRU,
+ 		.lif_count = 2,
+ 		.rpf_count = 5,
++		.uif_count = 2,
+ 		.wpf_count = 2,
+ 		.num_bru_inputs = 5,
+ 	},
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index f10c61339d46..c411643695e4 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -539,6 +539,10 @@ struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad)
+ 	{ VSP1_ENTITY_UDS, idx, VI6_DPR_UDS_ROUTE(idx),			\
+ 	  { VI6_DPR_NODE_UDS(idx) }, VI6_DPR_NODE_UDS(idx) }
+ 
++#define VSP1_ENTITY_ROUTE_UIF(idx)					\
++	{ VSP1_ENTITY_UIF, idx, VI6_DPR_UIF_ROUTE(idx),			\
++	  { VI6_DPR_NODE_UIF(idx) }, VI6_DPR_NODE_UIF(idx) }
++
+ #define VSP1_ENTITY_ROUTE_WPF(idx)					\
+ 	{ VSP1_ENTITY_WPF, idx, 0,					\
+ 	  { VI6_DPR_NODE_WPF(idx) }, VI6_DPR_NODE_WPF(idx) }
+@@ -567,6 +571,8 @@ static const struct vsp1_route vsp1_routes[] = {
+ 	VSP1_ENTITY_ROUTE_UDS(0),
+ 	VSP1_ENTITY_ROUTE_UDS(1),
+ 	VSP1_ENTITY_ROUTE_UDS(2),
++	VSP1_ENTITY_ROUTE_UIF(0),	/* Named UIF4 in the documentation */
++	VSP1_ENTITY_ROUTE_UIF(1),	/* Named UIF5 in the documentation */
+ 	VSP1_ENTITY_ROUTE_WPF(0),
+ 	VSP1_ENTITY_ROUTE_WPF(1),
+ 	VSP1_ENTITY_ROUTE_WPF(2),
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index 0839a62cfa71..94490d697dcf 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -33,6 +33,7 @@ enum vsp1_entity_type {
+ 	VSP1_ENTITY_RPF,
+ 	VSP1_ENTITY_SRU,
+ 	VSP1_ENTITY_UDS,
++	VSP1_ENTITY_UIF,
+ 	VSP1_ENTITY_WPF,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h
+index 3201ad4b77d4..0d249ff9f564 100644
+--- a/drivers/media/platform/vsp1/vsp1_regs.h
++++ b/drivers/media/platform/vsp1/vsp1_regs.h
+@@ -307,6 +307,44 @@
+ #define VI6_WPF_WRBCK_CTRL		0x1034
+ #define VI6_WPF_WRBCK_CTRL_WBMD		(1 << 0)
+ 
++/* -----------------------------------------------------------------------------
++ * UIF Control Registers
++ */
++
++#define VI6_UIF_OFFSET			0x100
++
++#define VI6_UIF_DISCOM_DOCMCR		0x1c00
++#define VI6_UIF_DISCOM_DOCMCR_CMPRU	(1 << 16)
++#define VI6_UIF_DISCOM_DOCMCR_CMPR	(1 << 0)
++
++#define VI6_UIF_DISCOM_DOCMSTR		0x1c04
++#define VI6_UIF_DISCOM_DOCMSTR_CMPPRE	(1 << 1)
++#define VI6_UIF_DISCOM_DOCMSTR_CMPST	(1 << 0)
++
++#define VI6_UIF_DISCOM_DOCMCLSTR	0x1c08
++#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE	(1 << 1)
++#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST	(1 << 0)
++
++#define VI6_UIF_DISCOM_DOCMIENR		0x1c0c
++#define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN	(1 << 1)
++#define VI6_UIF_DISCOM_DOCMIENR_CMPIEN		(1 << 0)
++
++#define VI6_UIF_DISCOM_DOCMMDR		0x1c10
++#define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n)	((n) << 16)
++
++#define VI6_UIF_DISCOM_DOCMPMR		0x1c14
++#define VI6_UIF_DISCOM_DOCMPMR_CMPDFF(n)	((n) << 17)
++#define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n)	((n) << 8)
++#define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF		(1 << 7)
++#define VI6_UIF_DISCOM_DOCMPMR_SEL(n)		((n) << 0)
++
++#define VI6_UIF_DISCOM_DOCMECRCR	0x1c18
++#define VI6_UIF_DISCOM_DOCMCCRCR	0x1c1c
++#define VI6_UIF_DISCOM_DOCMSPXR		0x1c20
++#define VI6_UIF_DISCOM_DOCMSPYR		0x1c24
++#define VI6_UIF_DISCOM_DOCMSZXR		0x1c28
++#define VI6_UIF_DISCOM_DOCMSZYR		0x1c2c
++
+ /* -----------------------------------------------------------------------------
+  * DPR Control Registers
+  */
+@@ -339,7 +377,10 @@
+ #define VI6_DPR_SMPPT_PT_MASK		(0x3f << 0)
+ #define VI6_DPR_SMPPT_PT_SHIFT		0
+ 
++#define VI6_DPR_UIF_ROUTE(n)		(0x2074 + (n) * 4)
++
+ #define VI6_DPR_NODE_RPF(n)		(n)
++#define VI6_DPR_NODE_UIF(n)		(12 + (n))
+ #define VI6_DPR_NODE_SRU		16
+ #define VI6_DPR_NODE_UDS(n)		(17 + (n))
+ #define VI6_DPR_NODE_LUT		22
+diff --git a/drivers/media/platform/vsp1/vsp1_uif.c b/drivers/media/platform/vsp1/vsp1_uif.c
+new file mode 100644
+index 000000000000..c219165b15b9
+--- /dev/null
++++ b/drivers/media/platform/vsp1/vsp1_uif.c
+@@ -0,0 +1,271 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * vsp1_uif.c  --  R-Car VSP1 User Logic Interface
++ *
++ * Copyright (C) 2017-2018 Laurent Pinchart
++ *
++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
++ */
++
++#include <linux/device.h>
++#include <linux/gfp.h>
++#include <linux/sys_soc.h>
++
++#include <media/media-entity.h>
++#include <media/v4l2-subdev.h>
++
++#include "vsp1.h"
++#include "vsp1_dl.h"
++#include "vsp1_entity.h"
++#include "vsp1_uif.h"
++
++#define UIF_MIN_SIZE				4U
++#define UIF_MAX_SIZE				8190U
++
++/* -----------------------------------------------------------------------------
++ * Device Access
++ */
++
++static inline u32 vsp1_uif_read(struct vsp1_uif *uif, u32 reg)
++{
++	return vsp1_read(uif->entity.vsp1,
++			 uif->entity.index * VI6_UIF_OFFSET + reg);
++}
++static inline void vsp1_uif_write(struct vsp1_uif *uif, struct vsp1_dl_list *dl,
++				  u32 reg, u32 data)
++{
++	vsp1_dl_list_write(dl, reg + uif->entity.index * VI6_UIF_OFFSET, data);
++}
++
++u32 vsp1_uif_get_crc(struct vsp1_uif *uif)
++{
++	return vsp1_uif_read(uif, VI6_UIF_DISCOM_DOCMCCRCR);
++}
++
++/* -----------------------------------------------------------------------------
++ * V4L2 Subdevice Pad Operations
++ */
++
++static const unsigned int uif_codes[] = {
++	MEDIA_BUS_FMT_ARGB8888_1X32,
++	MEDIA_BUS_FMT_AHSV8888_1X32,
++	MEDIA_BUS_FMT_AYUV8_1X32,
++};
++
++static int uif_enum_mbus_code(struct v4l2_subdev *subdev,
++			      struct v4l2_subdev_pad_config *cfg,
++			      struct v4l2_subdev_mbus_code_enum *code)
++{
++	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, uif_codes,
++					  ARRAY_SIZE(uif_codes));
++}
++
++static int uif_enum_frame_size(struct v4l2_subdev *subdev,
++			       struct v4l2_subdev_pad_config *cfg,
++			       struct v4l2_subdev_frame_size_enum *fse)
++{
++	return vsp1_subdev_enum_frame_size(subdev, cfg, fse, UIF_MIN_SIZE,
++					   UIF_MIN_SIZE, UIF_MAX_SIZE,
++					   UIF_MAX_SIZE);
++}
++
++static int uif_set_format(struct v4l2_subdev *subdev,
++			    struct v4l2_subdev_pad_config *cfg,
++			    struct v4l2_subdev_format *fmt)
++{
++	return vsp1_subdev_set_pad_format(subdev, cfg, fmt, uif_codes,
++					  ARRAY_SIZE(uif_codes),
++					  UIF_MIN_SIZE, UIF_MIN_SIZE,
++					  UIF_MAX_SIZE, UIF_MAX_SIZE);
++}
++
++static int uif_get_selection(struct v4l2_subdev *subdev,
++			     struct v4l2_subdev_pad_config *cfg,
++			     struct v4l2_subdev_selection *sel)
++{
++	struct vsp1_uif *uif = to_uif(subdev);
++	struct v4l2_subdev_pad_config *config;
++	struct v4l2_mbus_framefmt *format;
++	int ret = 0;
++
++	if (sel->pad != UIF_PAD_SINK)
++		return -EINVAL;
++
++	mutex_lock(&uif->entity.lock);
++
++	config = vsp1_entity_get_pad_config(&uif->entity, cfg, sel->which);
++	if (!config) {
++		ret = -EINVAL;
++		goto done;
++	}
++
++	switch (sel->target) {
++	case V4L2_SEL_TGT_CROP_BOUNDS:
++	case V4L2_SEL_TGT_CROP_DEFAULT:
++		format = vsp1_entity_get_pad_format(&uif->entity, config,
++						    UIF_PAD_SINK);
++		sel->r.left = 0;
++		sel->r.top = 0;
++		sel->r.width = format->width;
++		sel->r.height = format->height;
++		break;
++
++	case V4L2_SEL_TGT_CROP:
++		sel->r = *vsp1_entity_get_pad_selection(&uif->entity, config,
++							sel->pad, sel->target);
++		break;
++
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++done:
++	mutex_unlock(&uif->entity.lock);
++	return ret;
++}
++
++static int uif_set_selection(struct v4l2_subdev *subdev,
++			     struct v4l2_subdev_pad_config *cfg,
++			     struct v4l2_subdev_selection *sel)
++{
++	struct vsp1_uif *uif = to_uif(subdev);
++	struct v4l2_subdev_pad_config *config;
++	struct v4l2_mbus_framefmt *format;
++	struct v4l2_rect *selection;
++	int ret = 0;
++
++	if (sel->pad != UIF_PAD_SINK ||
++	    sel->target != V4L2_SEL_TGT_CROP)
++		return -EINVAL;
++
++	mutex_lock(&uif->entity.lock);
++
++	config = vsp1_entity_get_pad_config(&uif->entity, cfg, sel->which);
++	if (!config) {
++		ret = -EINVAL;
++		goto done;
++	}
++
++	/* The crop rectangle must be inside the input frame. */
++	format = vsp1_entity_get_pad_format(&uif->entity, config, UIF_PAD_SINK);
++
++	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
++	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
++	sel->r.width = clamp_t(unsigned int, sel->r.width, UIF_MIN_SIZE,
++			       format->width - sel->r.left);
++	sel->r.height = clamp_t(unsigned int, sel->r.height, UIF_MIN_SIZE,
++				format->height - sel->r.top);
++
++	/* Store the crop rectangle. */
++	selection = vsp1_entity_get_pad_selection(&uif->entity, config,
++						  sel->pad, V4L2_SEL_TGT_CROP);
++	*selection = sel->r;
++
++done:
++	mutex_unlock(&uif->entity.lock);
++	return ret;
++}
++
++/* -----------------------------------------------------------------------------
++ * V4L2 Subdevice Operations
++ */
++
++static const struct v4l2_subdev_pad_ops uif_pad_ops = {
++	.init_cfg = vsp1_entity_init_cfg,
++	.enum_mbus_code = uif_enum_mbus_code,
++	.enum_frame_size = uif_enum_frame_size,
++	.get_fmt = vsp1_subdev_get_pad_format,
++	.set_fmt = uif_set_format,
++	.get_selection = uif_get_selection,
++	.set_selection = uif_set_selection,
++};
++
++static const struct v4l2_subdev_ops uif_ops = {
++	.pad    = &uif_pad_ops,
++};
++
++/* -----------------------------------------------------------------------------
++ * VSP1 Entity Operations
++ */
++
++static void uif_configure(struct vsp1_entity *entity,
++			  struct vsp1_pipeline *pipe,
++			  struct vsp1_dl_list *dl,
++			  enum vsp1_entity_params params)
++{
++	struct vsp1_uif *uif = to_uif(&entity->subdev);
++	const struct v4l2_rect *crop;
++	unsigned int left;
++	unsigned int width;
++
++	/*
++	 * Per-partition configuration isn't needed as the DISCOM is used in
++	 * display pipelines only.
++	 */
++	if (params != VSP1_ENTITY_PARAMS_INIT)
++		return;
++
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMPMR,
++		       VI6_UIF_DISCOM_DOCMPMR_SEL(9));
++
++	crop = vsp1_entity_get_pad_selection(entity, entity->config,
++					     UIF_PAD_SINK, V4L2_SEL_TGT_CROP);
++
++	left = crop->left;
++	width = crop->width;
++
++	/* On M3-W the horizontal coordinates are twice the register value. */
++	if (uif->m3w_quirk) {
++		left /= 2;
++		width /= 2;
++	}
++
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSPXR, left);
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSPYR, crop->top);
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSZXR, width);
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSZYR, crop->height);
++
++	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMCR,
++		       VI6_UIF_DISCOM_DOCMCR_CMPR);
++}
++
++static const struct vsp1_entity_operations uif_entity_ops = {
++	.configure = uif_configure,
++};
++
++/* -----------------------------------------------------------------------------
++ * Initialization and Cleanup
++ */
++
++static const struct soc_device_attribute vsp1_r8a7796[] = {
++	{ .soc_id = "r8a7796" },
++	{ /* sentinel */ }
++};
++
++struct vsp1_uif *vsp1_uif_create(struct vsp1_device *vsp1, unsigned int index)
++{
++	struct vsp1_uif *uif;
++	char name[6];
++	int ret;
++
++	uif = devm_kzalloc(vsp1->dev, sizeof(*uif), GFP_KERNEL);
++	if (!uif)
++		return ERR_PTR(-ENOMEM);
++
++	if (soc_device_match(vsp1_r8a7796))
++		uif->m3w_quirk = true;
++
++	uif->entity.ops = &uif_entity_ops;
++	uif->entity.type = VSP1_ENTITY_UIF;
++	uif->entity.index = index;
++
++	/* The datasheet names the two UIF instances UIF4 and UIF5. */
++	sprintf(name, "uif.%u", index + 4);
++	ret = vsp1_entity_init(vsp1, &uif->entity, name, 2, &uif_ops,
++			       MEDIA_ENT_F_PROC_VIDEO_STATISTICS);
++	if (ret < 0)
++		return ERR_PTR(ret);
++
++	return uif;
++}
+diff --git a/drivers/media/platform/vsp1/vsp1_uif.h b/drivers/media/platform/vsp1/vsp1_uif.h
+new file mode 100644
+index 000000000000..c71ab5f6a6f8
+--- /dev/null
++++ b/drivers/media/platform/vsp1/vsp1_uif.h
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * vsp1_uif.h  --  R-Car VSP1 User Logic Interface
++ *
++ * Copyright (C) 2017-2018 Laurent Pinchart
++ *
++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
++ */
++#ifndef __VSP1_UIF_H__
++#define __VSP1_UIF_H__
++
++#include "vsp1_entity.h"
++
++struct vsp1_device;
++
++#define UIF_PAD_SINK				0
++#define UIF_PAD_SOURCE				1
++
++struct vsp1_uif {
++	struct vsp1_entity entity;
++	bool m3w_quirk;
++};
++
++static inline struct vsp1_uif *to_uif(struct v4l2_subdev *subdev)
++{
++	return container_of(subdev, struct vsp1_uif, entity.subdev);
++}
++
++struct vsp1_uif *vsp1_uif_create(struct vsp1_device *vsp1, unsigned int index);
++u32 vsp1_uif_get_crc(struct vsp1_uif *uif);
++
++#endif /* __VSP1_UIF_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1192-media-v4l-vsp1-Integrate-DISCOM-in-display-pipeline.patch b/patches/1192-media-v4l-vsp1-Integrate-DISCOM-in-display-pipeline.patch
new file mode 100644
index 00000000000000..12dc6c1009000b
--- /dev/null
+++ b/patches/1192-media-v4l-vsp1-Integrate-DISCOM-in-display-pipeline.patch
@@ -0,0 +1,249 @@
+From 713f8893488c48dc0db1491089e81d489f5892ca Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Thu, 30 Nov 2017 09:45:20 -0500
+Subject: [PATCH 1192/1795] media: v4l: vsp1: Integrate DISCOM in display
+ pipeline
+
+The DISCOM is used to compute CRCs on display frames. Integrate it in
+the display pipeline at the output of the blending unit to process
+output frames.
+
+Computing CRCs on input frames is possible by positioning the DISCOM at
+a different point in the pipeline. This use case isn't supported at the
+moment and could be implemented by extending the API between the VSP1
+and DU drivers if needed.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 5e824f989e6e8621b095e017b23ac888a827e019)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 115 ++++++++++++++++++++++++-
+ drivers/media/platform/vsp1/vsp1_drm.h |   7 ++
+ 2 files changed, 119 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 5fc31578f9b0..68e8830f27fa 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -22,6 +22,7 @@
+ #include "vsp1_lif.h"
+ #include "vsp1_pipe.h"
+ #include "vsp1_rwpf.h"
++#include "vsp1_uif.h"
+ 
+ #define BRX_NAME(e)	(e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
+ 
+@@ -35,8 +36,13 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+ 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+ 	bool complete = completion == VSP1_DL_FRAME_END_COMPLETED;
+ 
+-	if (drm_pipe->du_complete)
+-		drm_pipe->du_complete(drm_pipe->du_private, complete, 0);
++	if (drm_pipe->du_complete) {
++		struct vsp1_entity *uif = drm_pipe->uif;
++		u32 crc;
++
++		crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
++		drm_pipe->du_complete(drm_pipe->du_private, complete, crc);
++	}
+ 
+ 	if (completion & VSP1_DL_FRAME_END_INTERNAL) {
+ 		drm_pipe->force_brx_release = false;
+@@ -48,10 +54,66 @@ static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
+  * Pipeline Configuration
+  */
+ 
++/*
++ * Insert the UIF in the pipeline between the prev and next entities. If no UIF
++ * is available connect the two entities directly.
++ */
++static int vsp1_du_insert_uif(struct vsp1_device *vsp1,
++			      struct vsp1_pipeline *pipe,
++			      struct vsp1_entity *uif,
++			      struct vsp1_entity *prev, unsigned int prev_pad,
++			      struct vsp1_entity *next, unsigned int next_pad)
++{
++	struct v4l2_subdev_format format;
++	int ret;
++
++	if (!uif) {
++		/*
++		 * If there's no UIF to be inserted, connect the previous and
++		 * next entities directly.
++		 */
++		prev->sink = next;
++		prev->sink_pad = next_pad;
++		return 0;
++	}
++
++	prev->sink = uif;
++	prev->sink_pad = UIF_PAD_SINK;
++
++	memset(&format, 0, sizeof(format));
++	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	format.pad = prev_pad;
++
++	ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);
++	if (ret < 0)
++		return ret;
++
++	format.pad = UIF_PAD_SINK;
++
++	ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);
++	if (ret < 0)
++		return ret;
++
++	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",
++		__func__, format.format.width, format.format.height,
++		format.format.code);
++
++	/*
++	 * The UIF doesn't mangle the format between its sink and source pads,
++	 * so there is no need to retrieve the format on its source pad.
++	 */
++
++	uif->sink = next;
++	uif->sink_pad = next_pad;
++
++	return 0;
++}
++
+ /* Setup one RPF and the connected BRx sink pad. */
+ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 				      struct vsp1_pipeline *pipe,
+ 				      struct vsp1_rwpf *rpf,
++				      struct vsp1_entity *uif,
+ 				      unsigned int brx_input)
+ {
+ 	struct v4l2_subdev_selection sel;
+@@ -122,6 +184,12 @@ static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
+ 	if (ret < 0)
+ 		return ret;
+ 
++	/* Insert and configure the UIF if available. */
++	ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
++				 pipe->brx, brx_input);
++	if (ret < 0)
++		return ret;
++
+ 	/* BRx sink, propagate the format from the RPF source. */
+ 	format.pad = brx_input;
+ 
+@@ -297,7 +365,10 @@ static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
+ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 					struct vsp1_pipeline *pipe)
+ {
++	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
+ 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
++	struct vsp1_entity *uif;
++	bool use_uif = false;
+ 	struct vsp1_brx *brx;
+ 	unsigned int i;
+ 	int ret;
+@@ -358,7 +429,11 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 		dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
+ 			__func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
+ 
+-		ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, i);
++		uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&
++		      drm_pipe->crc.index == i ? drm_pipe->uif : NULL;
++		if (uif)
++			use_uif = true;
++		ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
+ 		if (ret < 0) {
+ 			dev_err(vsp1->dev,
+ 				"%s: failed to setup RPF.%u\n",
+@@ -367,6 +442,31 @@ static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
+ 		}
+ 	}
+ 
++	/* Insert and configure the UIF at the BRx output if available. */
++	uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;
++	if (uif)
++		use_uif = true;
++	ret = vsp1_du_insert_uif(vsp1, pipe, uif,
++				 pipe->brx, pipe->brx->source_pad,
++				 &pipe->output->entity, 0);
++	if (ret < 0)
++		dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",
++			__func__, BRX_NAME(pipe->brx));
++
++	/*
++	 * If the UIF is not in use schedule it for removal by setting its pipe
++	 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
++	 * hardware pipeline and from the pipeline's list of entities. Otherwise
++	 * make sure it is present in the pipeline's list of entities if it
++	 * wasn't already.
++	 */
++	if (!use_uif) {
++		drm_pipe->uif->pipe = NULL;
++	} else if (!drm_pipe->uif->pipe) {
++		drm_pipe->uif->pipe = pipe;
++		list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
++	}
++
+ 	return 0;
+ }
+ 
+@@ -748,6 +848,8 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
+ 	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
+ 	struct vsp1_pipeline *pipe = &drm_pipe->pipe;
+ 
++	drm_pipe->crc = cfg->crc;
++
+ 	vsp1_du_pipeline_setup_inputs(vsp1, pipe);
+ 	vsp1_du_pipeline_configure(pipe);
+ 	mutex_unlock(&vsp1->drm->lock);
+@@ -816,6 +918,13 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
+ 
+ 		pipe->lif->pipe = pipe;
+ 		list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
++
++		/*
++		 * CRC computation is initially disabled, don't add the UIF to
++		 * the pipeline.
++		 */
++		if (i < vsp1->info->uif_count)
++			drm_pipe->uif = &vsp1->uif[i]->entity;
+ 	}
+ 
+ 	/* Disable all RPFs initially. */
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h
+index e5b88b28806c..8dfd274a59e2 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.h
++++ b/drivers/media/platform/vsp1/vsp1_drm.h
+@@ -13,6 +13,8 @@
+ #include <linux/videodev2.h>
+ #include <linux/wait.h>
+ 
++#include <media/vsp1.h>
++
+ #include "vsp1_pipe.h"
+ 
+ /**
+@@ -22,6 +24,8 @@
+  * @height: output display height
+  * @force_brx_release: when set, release the BRx during the next reconfiguration
+  * @wait_queue: wait queue to wait for BRx release completion
++ * @uif: UIF entity if available for the pipeline
++ * @crc: CRC computation configuration
+  * @du_complete: frame completion callback for the DU driver (optional)
+  * @du_private: data to be passed to the du_complete callback
+  */
+@@ -34,6 +38,9 @@ struct vsp1_drm_pipeline {
+ 	bool force_brx_release;
+ 	wait_queue_head_t wait_queue;
+ 
++	struct vsp1_entity *uif;
++	struct vsp1_du_crc_config crc;
++
+ 	/* Frame synchronisation */
+ 	void (*du_complete)(void *data, bool completed, u32 crc);
+ 	void *du_private;
+-- 
+2.19.0
+
diff --git a/patches/1193-media-vsp1-Move-video-suspend-resume-handling-to-vid.patch b/patches/1193-media-vsp1-Move-video-suspend-resume-handling-to-vid.patch
new file mode 100644
index 00000000000000..67d00eac420c5d
--- /dev/null
+++ b/patches/1193-media-vsp1-Move-video-suspend-resume-handling-to-vid.patch
@@ -0,0 +1,247 @@
+From c410295997c08525082442e7d994deb8265b9d99 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:41:55 -0400
+Subject: [PATCH 1193/1795] media: vsp1: Move video suspend resume handling to
+ video object
+
+The suspend and resume handlers are only utilised by video pipelines,
+yet the functions currently reside in the vsp1_pipe object.
+
+This causes an issue with resume, as the functions incorrectly call
+vsp1_pipeline_run() directly instead of processing the video object
+through vsp1_video_pipeline_run().
+
+Move the functions to the video object, renaming accordingly and update
+the resume handler to call vsp1_video_pipeline_run() as appropriate.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit fce34e49e4a75b3bc6cada6ae5147e410b443399)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drv.c   |  4 +-
+ drivers/media/platform/vsp1/vsp1_pipe.c  | 70 ----------------------
+ drivers/media/platform/vsp1/vsp1_pipe.h  |  3 -
+ drivers/media/platform/vsp1/vsp1_video.c | 75 ++++++++++++++++++++++++
+ drivers/media/platform/vsp1/vsp1_video.h |  3 +
+ 5 files changed, 80 insertions(+), 75 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c
+index d29f9c4baebe..5d82f6ee56ea 100644
+--- a/drivers/media/platform/vsp1/vsp1_drv.c
++++ b/drivers/media/platform/vsp1/vsp1_drv.c
+@@ -589,7 +589,7 @@ static int __maybe_unused vsp1_pm_suspend(struct device *dev)
+ 	 * restarted explicitly by the DU.
+ 	 */
+ 	if (!vsp1->drm)
+-		vsp1_pipelines_suspend(vsp1);
++		vsp1_video_suspend(vsp1);
+ 
+ 	pm_runtime_force_suspend(vsp1->dev);
+ 
+@@ -607,7 +607,7 @@ static int __maybe_unused vsp1_pm_resume(struct device *dev)
+ 	 * restarted explicitly by the DU.
+ 	 */
+ 	if (!vsp1->drm)
+-		vsp1_pipelines_resume(vsp1);
++		vsp1_video_resume(vsp1);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index 6fde4c0b9844..da21f1a7cd75 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -386,73 +386,3 @@ void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
+ 	}
+ }
+ 
+-void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
+-{
+-	unsigned long flags;
+-	unsigned int i;
+-	int ret;
+-
+-	/*
+-	 * To avoid increasing the system suspend time needlessly, loop over the
+-	 * pipelines twice, first to set them all to the stopping state, and
+-	 * then to wait for the stop to complete.
+-	 */
+-	for (i = 0; i < vsp1->info->wpf_count; ++i) {
+-		struct vsp1_rwpf *wpf = vsp1->wpf[i];
+-		struct vsp1_pipeline *pipe;
+-
+-		if (wpf == NULL)
+-			continue;
+-
+-		pipe = wpf->entity.pipe;
+-		if (pipe == NULL)
+-			continue;
+-
+-		spin_lock_irqsave(&pipe->irqlock, flags);
+-		if (pipe->state == VSP1_PIPELINE_RUNNING)
+-			pipe->state = VSP1_PIPELINE_STOPPING;
+-		spin_unlock_irqrestore(&pipe->irqlock, flags);
+-	}
+-
+-	for (i = 0; i < vsp1->info->wpf_count; ++i) {
+-		struct vsp1_rwpf *wpf = vsp1->wpf[i];
+-		struct vsp1_pipeline *pipe;
+-
+-		if (wpf == NULL)
+-			continue;
+-
+-		pipe = wpf->entity.pipe;
+-		if (pipe == NULL)
+-			continue;
+-
+-		ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
+-					 msecs_to_jiffies(500));
+-		if (ret == 0)
+-			dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
+-				 wpf->entity.index);
+-	}
+-}
+-
+-void vsp1_pipelines_resume(struct vsp1_device *vsp1)
+-{
+-	unsigned long flags;
+-	unsigned int i;
+-
+-	/* Resume all running pipelines. */
+-	for (i = 0; i < vsp1->info->wpf_count; ++i) {
+-		struct vsp1_rwpf *wpf = vsp1->wpf[i];
+-		struct vsp1_pipeline *pipe;
+-
+-		if (wpf == NULL)
+-			continue;
+-
+-		pipe = wpf->entity.pipe;
+-		if (pipe == NULL)
+-			continue;
+-
+-		spin_lock_irqsave(&pipe->irqlock, flags);
+-		if (vsp1_pipeline_ready(pipe))
+-			vsp1_pipeline_run(pipe);
+-		spin_unlock_irqrestore(&pipe->irqlock, flags);
+-	}
+-}
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index 663d7fed7929..69858ba6cb31 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -164,9 +164,6 @@ void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
+ 				       unsigned int index,
+ 				       struct vsp1_partition_window *window);
+ 
+-void vsp1_pipelines_suspend(struct vsp1_device *vsp1);
+-void vsp1_pipelines_resume(struct vsp1_device *vsp1);
+-
+ const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
+ 						    u32 fourcc);
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index ba89dd176a13..5deb35210055 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -1170,6 +1170,81 @@ static const struct v4l2_file_operations vsp1_video_fops = {
+ 	.mmap = vb2_fop_mmap,
+ };
+ 
++/* -----------------------------------------------------------------------------
++ * Suspend and Resume
++ */
++
++void vsp1_video_suspend(struct vsp1_device *vsp1)
++{
++	unsigned long flags;
++	unsigned int i;
++	int ret;
++
++	/*
++	 * To avoid increasing the system suspend time needlessly, loop over the
++	 * pipelines twice, first to set them all to the stopping state, and
++	 * then to wait for the stop to complete.
++	 */
++	for (i = 0; i < vsp1->info->wpf_count; ++i) {
++		struct vsp1_rwpf *wpf = vsp1->wpf[i];
++		struct vsp1_pipeline *pipe;
++
++		if (wpf == NULL)
++			continue;
++
++		pipe = wpf->entity.pipe;
++		if (pipe == NULL)
++			continue;
++
++		spin_lock_irqsave(&pipe->irqlock, flags);
++		if (pipe->state == VSP1_PIPELINE_RUNNING)
++			pipe->state = VSP1_PIPELINE_STOPPING;
++		spin_unlock_irqrestore(&pipe->irqlock, flags);
++	}
++
++	for (i = 0; i < vsp1->info->wpf_count; ++i) {
++		struct vsp1_rwpf *wpf = vsp1->wpf[i];
++		struct vsp1_pipeline *pipe;
++
++		if (wpf == NULL)
++			continue;
++
++		pipe = wpf->entity.pipe;
++		if (pipe == NULL)
++			continue;
++
++		ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
++					 msecs_to_jiffies(500));
++		if (ret == 0)
++			dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
++				 wpf->entity.index);
++	}
++}
++
++void vsp1_video_resume(struct vsp1_device *vsp1)
++{
++	unsigned long flags;
++	unsigned int i;
++
++	/* Resume all running pipelines. */
++	for (i = 0; i < vsp1->info->wpf_count; ++i) {
++		struct vsp1_rwpf *wpf = vsp1->wpf[i];
++		struct vsp1_pipeline *pipe;
++
++		if (wpf == NULL)
++			continue;
++
++		pipe = wpf->entity.pipe;
++		if (pipe == NULL)
++			continue;
++
++		spin_lock_irqsave(&pipe->irqlock, flags);
++		if (vsp1_pipeline_ready(pipe))
++			vsp1_video_pipeline_run(pipe);
++		spin_unlock_irqrestore(&pipe->irqlock, flags);
++	}
++}
++
+ /* -----------------------------------------------------------------------------
+  * Initialization and Cleanup
+  */
+diff --git a/drivers/media/platform/vsp1/vsp1_video.h b/drivers/media/platform/vsp1/vsp1_video.h
+index 75a5a65c66fe..f3cf5e2fdf5a 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.h
++++ b/drivers/media/platform/vsp1/vsp1_video.h
+@@ -51,6 +51,9 @@ static inline struct vsp1_video *to_vsp1_video(struct video_device *vdev)
+ 	return container_of(vdev, struct vsp1_video, video);
+ }
+ 
++void vsp1_video_suspend(struct vsp1_device *vsp1);
++void vsp1_video_resume(struct vsp1_device *vsp1);
++
+ struct vsp1_video *vsp1_video_create(struct vsp1_device *vsp1,
+ 				     struct vsp1_rwpf *rwpf);
+ void vsp1_video_cleanup(struct vsp1_video *video);
+-- 
+2.19.0
+
diff --git a/patches/1194-media-vsp1-Reword-uses-of-fragment-as-body.patch b/patches/1194-media-vsp1-Reword-uses-of-fragment-as-body.patch
new file mode 100644
index 00000000000000..188c1b53aac520
--- /dev/null
+++ b/patches/1194-media-vsp1-Reword-uses-of-fragment-as-body.patch
@@ -0,0 +1,407 @@
+From 03a3f07b5adfbd176c90eecf307e779b7a55d09e Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:41:56 -0400
+Subject: [PATCH 1194/1795] media: vsp1: Reword uses of 'fragment' as 'body'
+
+Throughout the codebase, the term 'fragment' is used to represent a
+display list body. This term duplicates the 'body' which is already in
+use.
+
+The datasheet references these objects as a body, therefore replace all
+mentions of a fragment with a body, along with the corresponding
+pluralised terms.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 764dfee1a153eebf43bdb4eee94ef7e156ff5f5f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_clu.c |  10 +--
+ drivers/media/platform/vsp1/vsp1_dl.c  | 111 ++++++++++++-------------
+ drivers/media/platform/vsp1/vsp1_dl.h  |  13 ++-
+ drivers/media/platform/vsp1/vsp1_lut.c |   8 +-
+ 4 files changed, 70 insertions(+), 72 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index 96a448e1504c..ebfbb915dcdc 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -43,19 +43,19 @@ static int clu_set_table(struct vsp1_clu *clu, struct v4l2_ctrl *ctrl)
+ 	struct vsp1_dl_body *dlb;
+ 	unsigned int i;
+ 
+-	dlb = vsp1_dl_fragment_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
++	dlb = vsp1_dl_body_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
+ 	if (!dlb)
+ 		return -ENOMEM;
+ 
+-	vsp1_dl_fragment_write(dlb, VI6_CLU_ADDR, 0);
++	vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
+ 	for (i = 0; i < 17 * 17 * 17; ++i)
+-		vsp1_dl_fragment_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
++		vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
+ 
+ 	spin_lock_irq(&clu->lock);
+ 	swap(clu->clu, dlb);
+ 	spin_unlock_irq(&clu->lock);
+ 
+-	vsp1_dl_fragment_free(dlb);
++	vsp1_dl_body_free(dlb);
+ 	return 0;
+ }
+ 
+@@ -211,7 +211,7 @@ static void clu_configure(struct vsp1_entity *entity,
+ 		spin_unlock_irqrestore(&clu->lock, flags);
+ 
+ 		if (dlb)
+-			vsp1_dl_list_add_fragment(dl, dlb);
++			vsp1_dl_list_add_body(dl, dlb);
+ 		break;
+ 	}
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 801dea475740..083da4f05c20 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -65,7 +65,7 @@ struct vsp1_dl_body {
+  * @header: display list header, NULL for headerless lists
+  * @dma: DMA address for the header
+  * @body0: first display list body
+- * @fragments: list of extra display list bodies
++ * @bodies: list of extra display list bodies
+  * @has_chain: if true, indicates that there's a partition chain
+  * @chain: entry in the display list partition chain
+  * @internal: whether the display list is used for internal purpose
+@@ -78,7 +78,7 @@ struct vsp1_dl_list {
+ 	dma_addr_t dma;
+ 
+ 	struct vsp1_dl_body body0;
+-	struct list_head fragments;
++	struct list_head bodies;
+ 
+ 	bool has_chain;
+ 	struct list_head chain;
+@@ -97,13 +97,13 @@ enum vsp1_dl_mode {
+  * @mode: display list operation mode (header or headerless)
+  * @singleshot: execute the display list in single-shot mode
+  * @vsp1: the VSP1 device
+- * @lock: protects the free, active, queued, pending and gc_fragments lists
++ * @lock: protects the free, active, queued, pending and gc_bodies lists
+  * @free: array of all free display lists
+  * @active: list currently being processed (loaded) by hardware
+  * @queued: list queued to the hardware (written to the DL registers)
+  * @pending: list waiting to be queued to the hardware
+- * @gc_work: fragments garbage collector work struct
+- * @gc_fragments: array of display list fragments waiting to be freed
++ * @gc_work: bodies garbage collector work struct
++ * @gc_bodies: array of display list bodies waiting to be freed
+  */
+ struct vsp1_dl_manager {
+ 	unsigned int index;
+@@ -118,7 +118,7 @@ struct vsp1_dl_manager {
+ 	struct vsp1_dl_list *pending;
+ 
+ 	struct work_struct gc_work;
+-	struct list_head gc_fragments;
++	struct list_head gc_bodies;
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -156,18 +156,17 @@ static void vsp1_dl_body_cleanup(struct vsp1_dl_body *dlb)
+ }
+ 
+ /**
+- * vsp1_dl_fragment_alloc - Allocate a display list fragment
++ * vsp1_dl_body_alloc - Allocate a display list body
+  * @vsp1: The VSP1 device
+- * @num_entries: The maximum number of entries that the fragment can contain
++ * @num_entries: The maximum number of entries that the body can contain
+  *
+- * Allocate a display list fragment with enough memory to contain the requested
++ * Allocate a display list body with enough memory to contain the requested
+  * number of entries.
+  *
+- * Return a pointer to a fragment on success or NULL if memory can't be
+- * allocated.
++ * Return a pointer to a body on success or NULL if memory can't be allocated.
+  */
+-struct vsp1_dl_body *vsp1_dl_fragment_alloc(struct vsp1_device *vsp1,
+-					    unsigned int num_entries)
++struct vsp1_dl_body *vsp1_dl_body_alloc(struct vsp1_device *vsp1,
++					unsigned int num_entries)
+ {
+ 	struct vsp1_dl_body *dlb;
+ 	int ret;
+@@ -186,20 +185,20 @@ struct vsp1_dl_body *vsp1_dl_fragment_alloc(struct vsp1_device *vsp1,
+ }
+ 
+ /**
+- * vsp1_dl_fragment_free - Free a display list fragment
+- * @dlb: The fragment
++ * vsp1_dl_body_free - Free a display list body
++ * @dlb: The body
+  *
+- * Free the given display list fragment and the associated DMA memory.
++ * Free the given display list body and the associated DMA memory.
+  *
+- * Fragments must only be freed explicitly if they are not added to a display
++ * Bodies must only be freed explicitly if they are not added to a display
+  * list, as the display list will take ownership of them and free them
+- * otherwise. Manual free typically happens at cleanup time for fragments that
++ * otherwise. Manual free typically happens at cleanup time for bodies that
+  * have been allocated but not used.
+  *
+  * Passing a NULL pointer to this function is safe, in that case no operation
+  * will be performed.
+  */
+-void vsp1_dl_fragment_free(struct vsp1_dl_body *dlb)
++void vsp1_dl_body_free(struct vsp1_dl_body *dlb)
+ {
+ 	if (!dlb)
+ 		return;
+@@ -209,16 +208,16 @@ void vsp1_dl_fragment_free(struct vsp1_dl_body *dlb)
+ }
+ 
+ /**
+- * vsp1_dl_fragment_write - Write a register to a display list fragment
+- * @dlb: The fragment
++ * vsp1_dl_body_write - Write a register to a display list body
++ * @dlb: The body
+  * @reg: The register address
+  * @data: The register value
+  *
+- * Write the given register and value to the display list fragment. The maximum
+- * number of entries that can be written in a fragment is specified when the
+- * fragment is allocated by vsp1_dl_fragment_alloc().
++ * Write the given register and value to the display list body. The maximum
++ * number of entries that can be written in a body is specified when the body is
++ * allocated by vsp1_dl_body_alloc().
+  */
+-void vsp1_dl_fragment_write(struct vsp1_dl_body *dlb, u32 reg, u32 data)
++void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+ 	dlb->entries[dlb->num_entries].addr = reg;
+ 	dlb->entries[dlb->num_entries].data = data;
+@@ -239,7 +238,7 @@ static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm)
+ 	if (!dl)
+ 		return NULL;
+ 
+-	INIT_LIST_HEAD(&dl->fragments);
++	INIT_LIST_HEAD(&dl->bodies);
+ 	dl->dlm = dlm;
+ 
+ 	/*
+@@ -276,7 +275,7 @@ static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm)
+ static void vsp1_dl_list_free(struct vsp1_dl_list *dl)
+ {
+ 	vsp1_dl_body_cleanup(&dl->body0);
+-	list_splice_init(&dl->fragments, &dl->dlm->gc_fragments);
++	list_splice_init(&dl->bodies, &dl->dlm->gc_bodies);
+ 	kfree(dl);
+ }
+ 
+@@ -331,13 +330,13 @@ static void __vsp1_dl_list_put(struct vsp1_dl_list *dl)
+ 	dl->has_chain = false;
+ 
+ 	/*
+-	 * We can't free fragments here as DMA memory can only be freed in
+-	 * interruptible context. Move all fragments to the display list
+-	 * manager's list of fragments to be freed, they will be
+-	 * garbage-collected by the work queue.
++	 * We can't free bodies here as DMA memory can only be freed in
++	 * interruptible context. Move all bodies to the display list manager's
++	 * list of bodies to be freed, they will be garbage-collected by the
++	 * work queue.
+ 	 */
+-	if (!list_empty(&dl->fragments)) {
+-		list_splice_init(&dl->fragments, &dl->dlm->gc_fragments);
++	if (!list_empty(&dl->bodies)) {
++		list_splice_init(&dl->bodies, &dl->dlm->gc_bodies);
+ 		schedule_work(&dl->dlm->gc_work);
+ 	}
+ 
+@@ -378,33 +377,33 @@ void vsp1_dl_list_put(struct vsp1_dl_list *dl)
+  */
+ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
+ {
+-	vsp1_dl_fragment_write(&dl->body0, reg, data);
++	vsp1_dl_body_write(&dl->body0, reg, data);
+ }
+ 
+ /**
+- * vsp1_dl_list_add_fragment - Add a fragment to the display list
++ * vsp1_dl_list_add_body - Add a body to the display list
+  * @dl: The display list
+- * @dlb: The fragment
++ * @dlb: The body
+  *
+- * Add a display list body as a fragment to a display list. Registers contained
+- * in fragments are processed after registers contained in the main display
+- * list, in the order in which fragments are added.
++ * Add a display list body to a display list. Registers contained in bodies are
++ * processed after registers contained in the main display list, in the order in
++ * which bodies are added.
+  *
+- * Adding a fragment to a display list passes ownership of the fragment to the
+- * list. The caller must not touch the fragment after this call, and must not
+- * free it explicitly with vsp1_dl_fragment_free().
++ * Adding a body to a display list passes ownership of the body to the list. The
++ * caller must not touch the body after this call, and must not free it
++ * explicitly with vsp1_dl_body_free().
+  *
+- * Fragments are only usable for display lists in header mode. Attempt to
+- * add a fragment to a header-less display list will return an error.
++ * Additional bodies are only usable for display lists in header mode.
++ * Attempting to add a body to a header-less display list will return an error.
+  */
+-int vsp1_dl_list_add_fragment(struct vsp1_dl_list *dl,
+-			      struct vsp1_dl_body *dlb)
++int vsp1_dl_list_add_body(struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb)
+ {
+ 	/* Multi-body lists are only available in header mode. */
+ 	if (dl->dlm->mode != VSP1_DL_MODE_HEADER)
+ 		return -EINVAL;
+ 
+-	list_add_tail(&dlb->list, &dl->fragments);
++	list_add_tail(&dlb->list, &dl->bodies);
++
+ 	return 0;
+ }
+ 
+@@ -453,7 +452,7 @@ static void vsp1_dl_list_fill_header(struct vsp1_dl_list *dl, bool is_last)
+ 	hdr->num_bytes = dl->body0.num_entries
+ 		       * sizeof(*dl->header->lists);
+ 
+-	list_for_each_entry(dlb, &dl->fragments, list) {
++	list_for_each_entry(dlb, &dl->bodies, list) {
+ 		num_lists++;
+ 		hdr++;
+ 
+@@ -732,25 +731,25 @@ void vsp1_dlm_reset(struct vsp1_dl_manager *dlm)
+ }
+ 
+ /*
+- * Free all fragments awaiting to be garbage-collected.
++ * Free all bodies awaiting to be garbage-collected.
+  *
+  * This function must be called without the display list manager lock held.
+  */
+-static void vsp1_dlm_fragments_free(struct vsp1_dl_manager *dlm)
++static void vsp1_dlm_bodies_free(struct vsp1_dl_manager *dlm)
+ {
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&dlm->lock, flags);
+ 
+-	while (!list_empty(&dlm->gc_fragments)) {
++	while (!list_empty(&dlm->gc_bodies)) {
+ 		struct vsp1_dl_body *dlb;
+ 
+-		dlb = list_first_entry(&dlm->gc_fragments, struct vsp1_dl_body,
++		dlb = list_first_entry(&dlm->gc_bodies, struct vsp1_dl_body,
+ 				       list);
+ 		list_del(&dlb->list);
+ 
+ 		spin_unlock_irqrestore(&dlm->lock, flags);
+-		vsp1_dl_fragment_free(dlb);
++		vsp1_dl_body_free(dlb);
+ 		spin_lock_irqsave(&dlm->lock, flags);
+ 	}
+ 
+@@ -762,7 +761,7 @@ static void vsp1_dlm_garbage_collect(struct work_struct *work)
+ 	struct vsp1_dl_manager *dlm =
+ 		container_of(work, struct vsp1_dl_manager, gc_work);
+ 
+-	vsp1_dlm_fragments_free(dlm);
++	vsp1_dlm_bodies_free(dlm);
+ }
+ 
+ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+@@ -784,7 +783,7 @@ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 
+ 	spin_lock_init(&dlm->lock);
+ 	INIT_LIST_HEAD(&dlm->free);
+-	INIT_LIST_HEAD(&dlm->gc_fragments);
++	INIT_LIST_HEAD(&dlm->gc_bodies);
+ 	INIT_WORK(&dlm->gc_work, vsp1_dlm_garbage_collect);
+ 
+ 	for (i = 0; i < prealloc; ++i) {
+@@ -814,5 +813,5 @@ void vsp1_dlm_destroy(struct vsp1_dl_manager *dlm)
+ 		vsp1_dl_list_free(dl);
+ 	}
+ 
+-	vsp1_dlm_fragments_free(dlm);
++	vsp1_dlm_bodies_free(dlm);
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index e6279b1abd19..57565debe132 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -12,7 +12,7 @@
+ #include <linux/types.h>
+ 
+ struct vsp1_device;
+-struct vsp1_dl_fragment;
++struct vsp1_dl_body;
+ struct vsp1_dl_list;
+ struct vsp1_dl_manager;
+ 
+@@ -33,12 +33,11 @@ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data);
+ void vsp1_dl_list_commit(struct vsp1_dl_list *dl, bool internal);
+ 
+-struct vsp1_dl_body *vsp1_dl_fragment_alloc(struct vsp1_device *vsp1,
+-					    unsigned int num_entries);
+-void vsp1_dl_fragment_free(struct vsp1_dl_body *dlb);
+-void vsp1_dl_fragment_write(struct vsp1_dl_body *dlb, u32 reg, u32 data);
+-int vsp1_dl_list_add_fragment(struct vsp1_dl_list *dl,
+-			      struct vsp1_dl_body *dlb);
++struct vsp1_dl_body *vsp1_dl_body_alloc(struct vsp1_device *vsp1,
++					unsigned int num_entries);
++void vsp1_dl_body_free(struct vsp1_dl_body *dlb);
++void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data);
++int vsp1_dl_list_add_body(struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb);
+ int vsp1_dl_list_add_chain(struct vsp1_dl_list *head, struct vsp1_dl_list *dl);
+ 
+ #endif /* __VSP1_DL_H__ */
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index f2e48a02ca7d..acbaca0f47f0 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -40,19 +40,19 @@ static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl)
+ 	struct vsp1_dl_body *dlb;
+ 	unsigned int i;
+ 
+-	dlb = vsp1_dl_fragment_alloc(lut->entity.vsp1, 256);
++	dlb = vsp1_dl_body_alloc(lut->entity.vsp1, 256);
+ 	if (!dlb)
+ 		return -ENOMEM;
+ 
+ 	for (i = 0; i < 256; ++i)
+-		vsp1_dl_fragment_write(dlb, VI6_LUT_TABLE + 4 * i,
++		vsp1_dl_body_write(dlb, VI6_LUT_TABLE + 4 * i,
+ 				       ctrl->p_new.p_u32[i]);
+ 
+ 	spin_lock_irq(&lut->lock);
+ 	swap(lut->lut, dlb);
+ 	spin_unlock_irq(&lut->lock);
+ 
+-	vsp1_dl_fragment_free(dlb);
++	vsp1_dl_body_free(dlb);
+ 	return 0;
+ }
+ 
+@@ -167,7 +167,7 @@ static void lut_configure(struct vsp1_entity *entity,
+ 		spin_unlock_irqrestore(&lut->lock, flags);
+ 
+ 		if (dlb)
+-			vsp1_dl_list_add_fragment(dl, dlb);
++			vsp1_dl_list_add_body(dl, dlb);
+ 		break;
+ 	}
+ }
+-- 
+2.19.0
+
diff --git a/patches/1195-media-vsp1-Protect-bodies-against-overflow.patch b/patches/1195-media-vsp1-Protect-bodies-against-overflow.patch
new file mode 100644
index 00000000000000..d8790b811ffb8c
--- /dev/null
+++ b/patches/1195-media-vsp1-Protect-bodies-against-overflow.patch
@@ -0,0 +1,64 @@
+From d79026d5203db7d9205b7206307fe0499d00ce70 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:41:57 -0400
+Subject: [PATCH 1195/1795] media: vsp1: Protect bodies against overflow
+
+The body write function relies on the code never asking it to write more
+than the entries available in the list.
+
+Currently with each list body containing 256 entries, this is fine, but
+we can reduce this number greatly saving memory. In preparation of this
+add a level of protection to catch any buffer overflows.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 076673419741c1c769f59536c199234937df1762)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 083da4f05c20..51965c30dec2 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -46,6 +46,7 @@ struct vsp1_dl_entry {
+  * @dma: DMA address of the entries
+  * @size: size of the DMA memory in bytes
+  * @num_entries: number of stored entries
++ * @max_entries: number of entries available
+  */
+ struct vsp1_dl_body {
+ 	struct list_head list;
+@@ -56,6 +57,7 @@ struct vsp1_dl_body {
+ 	size_t size;
+ 
+ 	unsigned int num_entries;
++	unsigned int max_entries;
+ };
+ 
+ /**
+@@ -138,6 +140,7 @@ static int vsp1_dl_body_init(struct vsp1_device *vsp1,
+ 
+ 	dlb->vsp1 = vsp1;
+ 	dlb->size = size;
++	dlb->max_entries = num_entries;
+ 
+ 	dlb->entries = dma_alloc_wc(vsp1->bus_master, dlb->size, &dlb->dma,
+ 				    GFP_KERNEL);
+@@ -219,6 +222,10 @@ void vsp1_dl_body_free(struct vsp1_dl_body *dlb)
+  */
+ void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
++	if (WARN_ONCE(dlb->num_entries >= dlb->max_entries,
++		      "DLB size exceeded (max %u)", dlb->max_entries))
++		return;
++
+ 	dlb->entries[dlb->num_entries].addr = reg;
+ 	dlb->entries[dlb->num_entries].data = data;
+ 	dlb->num_entries++;
+-- 
+2.19.0
+
diff --git a/patches/1196-media-vsp1-Provide-a-body-pool.patch b/patches/1196-media-vsp1-Provide-a-body-pool.patch
new file mode 100644
index 00000000000000..437bbd23690638
--- /dev/null
+++ b/patches/1196-media-vsp1-Provide-a-body-pool.patch
@@ -0,0 +1,264 @@
+From 855b3e66d8b8bb99ee40683f9f6fc0ceade713db Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:41:58 -0400
+Subject: [PATCH 1196/1795] media: vsp1: Provide a body pool
+
+Each display list allocates a body to store register values in a dma
+accessible buffer from a dma_alloc_wc() allocation. Each of these
+results in an entry in the IOMMU TLB, and a large number of display list
+allocations adds pressure to this resource.
+
+Reduce TLB pressure on the IPMMUs by allocating multiple display list
+bodies in a single allocation, and providing these to the display list
+through a 'body pool'. A pool can be allocated by the display list
+manager or entities which require their own body allocations.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 5de0473982aab2c0f877565a26c1803eed8d61ac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c | 163 ++++++++++++++++++++++++++
+ drivers/media/platform/vsp1/vsp1_dl.h |   8 ++
+ 2 files changed, 171 insertions(+)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 51965c30dec2..41ace89a585b 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -41,6 +41,8 @@ struct vsp1_dl_entry {
+ /**
+  * struct vsp1_dl_body - Display list body
+  * @list: entry in the display list list of bodies
++ * @free: entry in the pool free body list
++ * @pool: pool to which this body belongs
+  * @vsp1: the VSP1 device
+  * @entries: array of entries
+  * @dma: DMA address of the entries
+@@ -50,6 +52,9 @@ struct vsp1_dl_entry {
+  */
+ struct vsp1_dl_body {
+ 	struct list_head list;
++	struct list_head free;
++
++	struct vsp1_dl_body_pool *pool;
+ 	struct vsp1_device *vsp1;
+ 
+ 	struct vsp1_dl_entry *entries;
+@@ -60,6 +65,30 @@ struct vsp1_dl_body {
+ 	unsigned int max_entries;
+ };
+ 
++/**
++ * struct vsp1_dl_body_pool - display list body pool
++ * @dma: DMA address of the entries
++ * @size: size of the full DMA memory pool in bytes
++ * @mem: CPU memory pointer for the pool
++ * @bodies: Array of DLB structures for the pool
++ * @free: List of free DLB entries
++ * @lock: Protects the free list
++ * @vsp1: the VSP1 device
++ */
++struct vsp1_dl_body_pool {
++	/* DMA allocation */
++	dma_addr_t dma;
++	size_t size;
++	void *mem;
++
++	/* Body management */
++	struct vsp1_dl_body *bodies;
++	struct list_head free;
++	spinlock_t lock;
++
++	struct vsp1_device *vsp1;
++};
++
+ /**
+  * struct vsp1_dl_list - Display list
+  * @list: entry in the display list manager lists
+@@ -104,6 +133,7 @@ enum vsp1_dl_mode {
+  * @active: list currently being processed (loaded) by hardware
+  * @queued: list queued to the hardware (written to the DL registers)
+  * @pending: list waiting to be queued to the hardware
++ * @pool: body pool for the display list bodies
+  * @gc_work: bodies garbage collector work struct
+  * @gc_bodies: array of display list bodies waiting to be freed
+  */
+@@ -119,6 +149,8 @@ struct vsp1_dl_manager {
+ 	struct vsp1_dl_list *queued;
+ 	struct vsp1_dl_list *pending;
+ 
++	struct vsp1_dl_body_pool *pool;
++
+ 	struct work_struct gc_work;
+ 	struct list_head gc_bodies;
+ };
+@@ -127,6 +159,137 @@ struct vsp1_dl_manager {
+  * Display List Body Management
+  */
+ 
++/**
++ * vsp1_dl_body_pool_create - Create a pool of bodies from a single allocation
++ * @vsp1: The VSP1 device
++ * @num_bodies: The number of bodies to allocate
++ * @num_entries: The maximum number of entries that a body can contain
++ * @extra_size: Extra allocation provided for the bodies
++ *
++ * Allocate a pool of display list bodies each with enough memory to contain the
++ * requested number of entries plus the @extra_size.
++ *
++ * Return a pointer to a pool on success or NULL if memory can't be allocated.
++ */
++struct vsp1_dl_body_pool *
++vsp1_dl_body_pool_create(struct vsp1_device *vsp1, unsigned int num_bodies,
++			 unsigned int num_entries, size_t extra_size)
++{
++	struct vsp1_dl_body_pool *pool;
++	size_t dlb_size;
++	unsigned int i;
++
++	pool = kzalloc(sizeof(*pool), GFP_KERNEL);
++	if (!pool)
++		return NULL;
++
++	pool->vsp1 = vsp1;
++
++	/*
++	 * TODO: 'extra_size' is only used by vsp1_dlm_create(), to allocate
++	 * extra memory for the display list header. We need only one header per
++	 * display list, not per display list body, thus this allocation is
++	 * extraneous and should be reworked in the future.
++	 */
++	dlb_size = num_entries * sizeof(struct vsp1_dl_entry) + extra_size;
++	pool->size = dlb_size * num_bodies;
++
++	pool->bodies = kcalloc(num_bodies, sizeof(*pool->bodies), GFP_KERNEL);
++	if (!pool->bodies) {
++		kfree(pool);
++		return NULL;
++	}
++
++	pool->mem = dma_alloc_wc(vsp1->bus_master, pool->size, &pool->dma,
++				 GFP_KERNEL);
++	if (!pool->mem) {
++		kfree(pool->bodies);
++		kfree(pool);
++		return NULL;
++	}
++
++	spin_lock_init(&pool->lock);
++	INIT_LIST_HEAD(&pool->free);
++
++	for (i = 0; i < num_bodies; ++i) {
++		struct vsp1_dl_body *dlb = &pool->bodies[i];
++
++		dlb->pool = pool;
++		dlb->max_entries = num_entries;
++
++		dlb->dma = pool->dma + i * dlb_size;
++		dlb->entries = pool->mem + i * dlb_size;
++
++		list_add_tail(&dlb->free, &pool->free);
++	}
++
++	return pool;
++}
++
++/**
++ * vsp1_dl_body_pool_destroy - Release a body pool
++ * @pool: The body pool
++ *
++ * Release all components of a pool allocation.
++ */
++void vsp1_dl_body_pool_destroy(struct vsp1_dl_body_pool *pool)
++{
++	if (!pool)
++		return;
++
++	if (pool->mem)
++		dma_free_wc(pool->vsp1->bus_master, pool->size, pool->mem,
++			    pool->dma);
++
++	kfree(pool->bodies);
++	kfree(pool);
++}
++
++/**
++ * vsp1_dl_body_get - Obtain a body from a pool
++ * @pool: The body pool
++ *
++ * Obtain a body from the pool without blocking.
++ *
++ * Returns a display list body or NULL if there are none available.
++ */
++struct vsp1_dl_body *vsp1_dl_body_get(struct vsp1_dl_body_pool *pool)
++{
++	struct vsp1_dl_body *dlb = NULL;
++	unsigned long flags;
++
++	spin_lock_irqsave(&pool->lock, flags);
++
++	if (!list_empty(&pool->free)) {
++		dlb = list_first_entry(&pool->free, struct vsp1_dl_body, free);
++		list_del(&dlb->free);
++	}
++
++	spin_unlock_irqrestore(&pool->lock, flags);
++
++	return dlb;
++}
++
++/**
++ * vsp1_dl_body_put - Return a body back to its pool
++ * @dlb: The display list body
++ *
++ * Return a body back to the pool, and reset the num_entries to clear the list.
++ */
++void vsp1_dl_body_put(struct vsp1_dl_body *dlb)
++{
++	unsigned long flags;
++
++	if (!dlb)
++		return;
++
++	dlb->num_entries = 0;
++
++	spin_lock_irqsave(&dlb->pool->lock, flags);
++	list_add_tail(&dlb->free, &dlb->pool->free);
++	spin_unlock_irqrestore(&dlb->pool->lock, flags);
++}
++
+ /*
+  * Initialize a display list body object and allocate DMA memory for the body
+  * data. The display list body object is expected to have been initialized to
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index 57565debe132..107eebcdbab6 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -13,6 +13,7 @@
+ 
+ struct vsp1_device;
+ struct vsp1_dl_body;
++struct vsp1_dl_body_pool;
+ struct vsp1_dl_list;
+ struct vsp1_dl_manager;
+ 
+@@ -33,6 +34,13 @@ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data);
+ void vsp1_dl_list_commit(struct vsp1_dl_list *dl, bool internal);
+ 
++struct vsp1_dl_body_pool *
++vsp1_dl_body_pool_create(struct vsp1_device *vsp1, unsigned int num_bodies,
++			 unsigned int num_entries, size_t extra_size);
++void vsp1_dl_body_pool_destroy(struct vsp1_dl_body_pool *pool);
++struct vsp1_dl_body *vsp1_dl_body_get(struct vsp1_dl_body_pool *pool);
++void vsp1_dl_body_put(struct vsp1_dl_body *dlb);
++
+ struct vsp1_dl_body *vsp1_dl_body_alloc(struct vsp1_device *vsp1,
+ 					unsigned int num_entries);
+ void vsp1_dl_body_free(struct vsp1_dl_body *dlb);
+-- 
+2.19.0
+
diff --git a/patches/1197-media-vsp1-Convert-display-lists-to-use-new-body-poo.patch b/patches/1197-media-vsp1-Convert-display-lists-to-use-new-body-poo.patch
new file mode 100644
index 00000000000000..be466fea81f774
--- /dev/null
+++ b/patches/1197-media-vsp1-Convert-display-lists-to-use-new-body-poo.patch
@@ -0,0 +1,574 @@
+From e30d8aaff990efd1a615cc0fd5a38265d904da61 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:41:59 -0400
+Subject: [PATCH 1197/1795] media: vsp1: Convert display lists to use new body
+ pool
+
+Adapt the dl->body0 object to use an object from the body pool. This
+greatly reduces the pressure on the TLB for IPMMU use cases, as all of
+the lists use a single allocation for the main body.
+
+The CLU and LUT objects pre-allocate a pool containing three bodies,
+allowing a userspace update before the hardware has committed a previous
+set of tables.
+
+Bodies are no longer 'freed' in interrupt context, but instead released
+back to their respective pools. This allows us to remove the garbage
+collector in the DLM.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 5d7936b8e27dffb528bfb9e155136f2772c288f0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_clu.c |  27 ++-
+ drivers/media/platform/vsp1/vsp1_clu.h |   1 +
+ drivers/media/platform/vsp1/vsp1_dl.c  | 221 ++++++-------------------
+ drivers/media/platform/vsp1/vsp1_dl.h  |   3 -
+ drivers/media/platform/vsp1/vsp1_lut.c |  27 ++-
+ drivers/media/platform/vsp1/vsp1_lut.h |   1 +
+ 6 files changed, 100 insertions(+), 180 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index ebfbb915dcdc..8efa12f5e53f 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -19,6 +19,8 @@
+ #define CLU_MIN_SIZE				4U
+ #define CLU_MAX_SIZE				8190U
+ 
++#define CLU_SIZE				(17 * 17 * 17)
++
+ /* -----------------------------------------------------------------------------
+  * Device Access
+  */
+@@ -43,19 +45,19 @@ static int clu_set_table(struct vsp1_clu *clu, struct v4l2_ctrl *ctrl)
+ 	struct vsp1_dl_body *dlb;
+ 	unsigned int i;
+ 
+-	dlb = vsp1_dl_body_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
++	dlb = vsp1_dl_body_get(clu->pool);
+ 	if (!dlb)
+ 		return -ENOMEM;
+ 
+ 	vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
+-	for (i = 0; i < 17 * 17 * 17; ++i)
++	for (i = 0; i < CLU_SIZE; ++i)
+ 		vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
+ 
+ 	spin_lock_irq(&clu->lock);
+ 	swap(clu->clu, dlb);
+ 	spin_unlock_irq(&clu->lock);
+ 
+-	vsp1_dl_body_free(dlb);
++	vsp1_dl_body_put(dlb);
+ 	return 0;
+ }
+ 
+@@ -216,8 +218,16 @@ static void clu_configure(struct vsp1_entity *entity,
+ 	}
+ }
+ 
++static void clu_destroy(struct vsp1_entity *entity)
++{
++	struct vsp1_clu *clu = to_clu(&entity->subdev);
++
++	vsp1_dl_body_pool_destroy(clu->pool);
++}
++
+ static const struct vsp1_entity_operations clu_entity_ops = {
+ 	.configure = clu_configure,
++	.destroy = clu_destroy,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -243,6 +253,17 @@ struct vsp1_clu *vsp1_clu_create(struct vsp1_device *vsp1)
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
++	/*
++	 * Pre-allocate a body pool, with 3 bodies allowing a userspace update
++	 * before the hardware has committed a previous set of tables, handling
++	 * both the queued and pending dl entries. One extra entry is added to
++	 * the CLU_SIZE to allow for the VI6_CLU_ADDR header.
++	 */
++	clu->pool = vsp1_dl_body_pool_create(clu->entity.vsp1, 3, CLU_SIZE + 1,
++					     0);
++	if (!clu->pool)
++		return ERR_PTR(-ENOMEM);
++
+ 	/* Initialize the control handler. */
+ 	v4l2_ctrl_handler_init(&clu->ctrls, 2);
+ 	v4l2_ctrl_new_custom(&clu->ctrls, &clu_table_control, NULL);
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.h b/drivers/media/platform/vsp1/vsp1_clu.h
+index c45e6e707592..cef2f44481ba 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.h
++++ b/drivers/media/platform/vsp1/vsp1_clu.h
+@@ -32,6 +32,7 @@ struct vsp1_clu {
+ 	spinlock_t lock;
+ 	unsigned int mode;
+ 	struct vsp1_dl_body *clu;
++	struct vsp1_dl_body_pool *pool;
+ };
+ 
+ static inline struct vsp1_clu *to_clu(struct v4l2_subdev *subdev)
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 41ace89a585b..617c46a03dec 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -108,7 +108,7 @@ struct vsp1_dl_list {
+ 	struct vsp1_dl_header *header;
+ 	dma_addr_t dma;
+ 
+-	struct vsp1_dl_body body0;
++	struct vsp1_dl_body *body0;
+ 	struct list_head bodies;
+ 
+ 	bool has_chain;
+@@ -128,14 +128,12 @@ enum vsp1_dl_mode {
+  * @mode: display list operation mode (header or headerless)
+  * @singleshot: execute the display list in single-shot mode
+  * @vsp1: the VSP1 device
+- * @lock: protects the free, active, queued, pending and gc_bodies lists
++ * @lock: protects the free, active, queued, and pending lists
+  * @free: array of all free display lists
+  * @active: list currently being processed (loaded) by hardware
+  * @queued: list queued to the hardware (written to the DL registers)
+  * @pending: list waiting to be queued to the hardware
+  * @pool: body pool for the display list bodies
+- * @gc_work: bodies garbage collector work struct
+- * @gc_bodies: array of display list bodies waiting to be freed
+  */
+ struct vsp1_dl_manager {
+ 	unsigned int index;
+@@ -150,9 +148,6 @@ struct vsp1_dl_manager {
+ 	struct vsp1_dl_list *pending;
+ 
+ 	struct vsp1_dl_body_pool *pool;
+-
+-	struct work_struct gc_work;
+-	struct list_head gc_bodies;
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -290,89 +285,6 @@ void vsp1_dl_body_put(struct vsp1_dl_body *dlb)
+ 	spin_unlock_irqrestore(&dlb->pool->lock, flags);
+ }
+ 
+-/*
+- * Initialize a display list body object and allocate DMA memory for the body
+- * data. The display list body object is expected to have been initialized to
+- * 0 when allocated.
+- */
+-static int vsp1_dl_body_init(struct vsp1_device *vsp1,
+-			     struct vsp1_dl_body *dlb, unsigned int num_entries,
+-			     size_t extra_size)
+-{
+-	size_t size = num_entries * sizeof(*dlb->entries) + extra_size;
+-
+-	dlb->vsp1 = vsp1;
+-	dlb->size = size;
+-	dlb->max_entries = num_entries;
+-
+-	dlb->entries = dma_alloc_wc(vsp1->bus_master, dlb->size, &dlb->dma,
+-				    GFP_KERNEL);
+-	if (!dlb->entries)
+-		return -ENOMEM;
+-
+-	return 0;
+-}
+-
+-/*
+- * Cleanup a display list body and free allocated DMA memory allocated.
+- */
+-static void vsp1_dl_body_cleanup(struct vsp1_dl_body *dlb)
+-{
+-	dma_free_wc(dlb->vsp1->bus_master, dlb->size, dlb->entries, dlb->dma);
+-}
+-
+-/**
+- * vsp1_dl_body_alloc - Allocate a display list body
+- * @vsp1: The VSP1 device
+- * @num_entries: The maximum number of entries that the body can contain
+- *
+- * Allocate a display list body with enough memory to contain the requested
+- * number of entries.
+- *
+- * Return a pointer to a body on success or NULL if memory can't be allocated.
+- */
+-struct vsp1_dl_body *vsp1_dl_body_alloc(struct vsp1_device *vsp1,
+-					unsigned int num_entries)
+-{
+-	struct vsp1_dl_body *dlb;
+-	int ret;
+-
+-	dlb = kzalloc(sizeof(*dlb), GFP_KERNEL);
+-	if (!dlb)
+-		return NULL;
+-
+-	ret = vsp1_dl_body_init(vsp1, dlb, num_entries, 0);
+-	if (ret < 0) {
+-		kfree(dlb);
+-		return NULL;
+-	}
+-
+-	return dlb;
+-}
+-
+-/**
+- * vsp1_dl_body_free - Free a display list body
+- * @dlb: The body
+- *
+- * Free the given display list body and the associated DMA memory.
+- *
+- * Bodies must only be freed explicitly if they are not added to a display
+- * list, as the display list will take ownership of them and free them
+- * otherwise. Manual free typically happens at cleanup time for bodies that
+- * have been allocated but not used.
+- *
+- * Passing a NULL pointer to this function is safe, in that case no operation
+- * will be performed.
+- */
+-void vsp1_dl_body_free(struct vsp1_dl_body *dlb)
+-{
+-	if (!dlb)
+-		return;
+-
+-	vsp1_dl_body_cleanup(dlb);
+-	kfree(dlb);
+-}
+-
+ /**
+  * vsp1_dl_body_write - Write a register to a display list body
+  * @dlb: The body
+@@ -401,8 +313,6 @@ void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm)
+ {
+ 	struct vsp1_dl_list *dl;
+-	size_t header_size;
+-	int ret;
+ 
+ 	dl = kzalloc(sizeof(*dl), GFP_KERNEL);
+ 	if (!dl)
+@@ -411,41 +321,39 @@ static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm)
+ 	INIT_LIST_HEAD(&dl->bodies);
+ 	dl->dlm = dlm;
+ 
+-	/*
+-	 * Initialize the display list body and allocate DMA memory for the body
+-	 * and the optional header. Both are allocated together to avoid memory
+-	 * fragmentation, with the header located right after the body in
+-	 * memory.
+-	 */
+-	header_size = dlm->mode == VSP1_DL_MODE_HEADER
+-		    ? ALIGN(sizeof(struct vsp1_dl_header), 8)
+-		    : 0;
+-
+-	ret = vsp1_dl_body_init(dlm->vsp1, &dl->body0, VSP1_DL_NUM_ENTRIES,
+-				header_size);
+-	if (ret < 0) {
+-		kfree(dl);
++	/* Get a default body for our list. */
++	dl->body0 = vsp1_dl_body_get(dlm->pool);
++	if (!dl->body0)
+ 		return NULL;
+-	}
+-
+ 	if (dlm->mode == VSP1_DL_MODE_HEADER) {
+-		size_t header_offset = VSP1_DL_NUM_ENTRIES
+-				     * sizeof(*dl->body0.entries);
++		size_t header_offset = dl->body0->max_entries
++				     * sizeof(*dl->body0->entries);
+ 
+-		dl->header = ((void *)dl->body0.entries) + header_offset;
+-		dl->dma = dl->body0.dma + header_offset;
++		dl->header = ((void *)dl->body0->entries) + header_offset;
++		dl->dma = dl->body0->dma + header_offset;
+ 
+ 		memset(dl->header, 0, sizeof(*dl->header));
+-		dl->header->lists[0].addr = dl->body0.dma;
++		dl->header->lists[0].addr = dl->body0->dma;
+ 	}
+ 
+ 	return dl;
+ }
+ 
++static void vsp1_dl_list_bodies_put(struct vsp1_dl_list *dl)
++{
++	struct vsp1_dl_body *dlb, *tmp;
++
++	list_for_each_entry_safe(dlb, tmp, &dl->bodies, list) {
++		list_del(&dlb->list);
++		vsp1_dl_body_put(dlb);
++	}
++}
++
+ static void vsp1_dl_list_free(struct vsp1_dl_list *dl)
+ {
+-	vsp1_dl_body_cleanup(&dl->body0);
+-	list_splice_init(&dl->bodies, &dl->dlm->gc_bodies);
++	vsp1_dl_body_put(dl->body0);
++	vsp1_dl_list_bodies_put(dl);
++
+ 	kfree(dl);
+ }
+ 
+@@ -499,18 +407,13 @@ static void __vsp1_dl_list_put(struct vsp1_dl_list *dl)
+ 
+ 	dl->has_chain = false;
+ 
++	vsp1_dl_list_bodies_put(dl);
++
+ 	/*
+-	 * We can't free bodies here as DMA memory can only be freed in
+-	 * interruptible context. Move all bodies to the display list manager's
+-	 * list of bodies to be freed, they will be garbage-collected by the
+-	 * work queue.
++	 * body0 is reused as as an optimisation as presently every display list
++	 * has at least one body, thus we reinitialise the entries list.
+ 	 */
+-	if (!list_empty(&dl->bodies)) {
+-		list_splice_init(&dl->bodies, &dl->dlm->gc_bodies);
+-		schedule_work(&dl->dlm->gc_work);
+-	}
+-
+-	dl->body0.num_entries = 0;
++	dl->body0->num_entries = 0;
+ 
+ 	list_add_tail(&dl->list, &dl->dlm->free);
+ }
+@@ -547,7 +450,7 @@ void vsp1_dl_list_put(struct vsp1_dl_list *dl)
+  */
+ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
+ {
+-	vsp1_dl_body_write(&dl->body0, reg, data);
++	vsp1_dl_body_write(dl->body0, reg, data);
+ }
+ 
+ /**
+@@ -560,8 +463,8 @@ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
+  * which bodies are added.
+  *
+  * Adding a body to a display list passes ownership of the body to the list. The
+- * caller must not touch the body after this call, and must not free it
+- * explicitly with vsp1_dl_body_free().
++ * caller must not touch the body after this call, and must not release it
++ * explicitly with vsp1_dl_body_put().
+  *
+  * Additional bodies are only usable for display lists in header mode.
+  * Attempting to add a body to a header-less display list will return an error.
+@@ -619,7 +522,7 @@ static void vsp1_dl_list_fill_header(struct vsp1_dl_list *dl, bool is_last)
+ 	 * list was allocated.
+ 	 */
+ 
+-	hdr->num_bytes = dl->body0.num_entries
++	hdr->num_bytes = dl->body0->num_entries
+ 		       * sizeof(*dl->header->lists);
+ 
+ 	list_for_each_entry(dlb, &dl->bodies, list) {
+@@ -693,9 +596,9 @@ static void vsp1_dl_list_hw_enqueue(struct vsp1_dl_list *dl)
+ 		 * bit will be cleared by the hardware when the display list
+ 		 * processing starts.
+ 		 */
+-		vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->body0.dma);
++		vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->body0->dma);
+ 		vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD |
+-			   (dl->body0.num_entries * sizeof(*dl->header->lists)));
++			(dl->body0->num_entries * sizeof(*dl->header->lists)));
+ 	} else {
+ 		/*
+ 		 * In header mode, program the display list header address. If
+@@ -900,45 +803,12 @@ void vsp1_dlm_reset(struct vsp1_dl_manager *dlm)
+ 	dlm->pending = NULL;
+ }
+ 
+-/*
+- * Free all bodies awaiting to be garbage-collected.
+- *
+- * This function must be called without the display list manager lock held.
+- */
+-static void vsp1_dlm_bodies_free(struct vsp1_dl_manager *dlm)
+-{
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&dlm->lock, flags);
+-
+-	while (!list_empty(&dlm->gc_bodies)) {
+-		struct vsp1_dl_body *dlb;
+-
+-		dlb = list_first_entry(&dlm->gc_bodies, struct vsp1_dl_body,
+-				       list);
+-		list_del(&dlb->list);
+-
+-		spin_unlock_irqrestore(&dlm->lock, flags);
+-		vsp1_dl_body_free(dlb);
+-		spin_lock_irqsave(&dlm->lock, flags);
+-	}
+-
+-	spin_unlock_irqrestore(&dlm->lock, flags);
+-}
+-
+-static void vsp1_dlm_garbage_collect(struct work_struct *work)
+-{
+-	struct vsp1_dl_manager *dlm =
+-		container_of(work, struct vsp1_dl_manager, gc_work);
+-
+-	vsp1_dlm_bodies_free(dlm);
+-}
+-
+ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 					unsigned int index,
+ 					unsigned int prealloc)
+ {
+ 	struct vsp1_dl_manager *dlm;
++	size_t header_size;
+ 	unsigned int i;
+ 
+ 	dlm = devm_kzalloc(vsp1->dev, sizeof(*dlm), GFP_KERNEL);
+@@ -953,8 +823,21 @@ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 
+ 	spin_lock_init(&dlm->lock);
+ 	INIT_LIST_HEAD(&dlm->free);
+-	INIT_LIST_HEAD(&dlm->gc_bodies);
+-	INIT_WORK(&dlm->gc_work, vsp1_dlm_garbage_collect);
++
++	/*
++	 * Initialize the display list body and allocate DMA memory for the body
++	 * and the optional header. Both are allocated together to avoid memory
++	 * fragmentation, with the header located right after the body in
++	 * memory.
++	 */
++	header_size = dlm->mode == VSP1_DL_MODE_HEADER
++		    ? ALIGN(sizeof(struct vsp1_dl_header), 8)
++		    : 0;
++
++	dlm->pool = vsp1_dl_body_pool_create(vsp1, prealloc,
++					     VSP1_DL_NUM_ENTRIES, header_size);
++	if (!dlm->pool)
++		return NULL;
+ 
+ 	for (i = 0; i < prealloc; ++i) {
+ 		struct vsp1_dl_list *dl;
+@@ -976,12 +859,10 @@ void vsp1_dlm_destroy(struct vsp1_dl_manager *dlm)
+ 	if (!dlm)
+ 		return;
+ 
+-	cancel_work_sync(&dlm->gc_work);
+-
+ 	list_for_each_entry_safe(dl, next, &dlm->free, list) {
+ 		list_del(&dl->list);
+ 		vsp1_dl_list_free(dl);
+ 	}
+ 
+-	vsp1_dlm_bodies_free(dlm);
++	vsp1_dl_body_pool_destroy(dlm->pool);
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index 107eebcdbab6..6a7d48e385d5 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -41,9 +41,6 @@ void vsp1_dl_body_pool_destroy(struct vsp1_dl_body_pool *pool);
+ struct vsp1_dl_body *vsp1_dl_body_get(struct vsp1_dl_body_pool *pool);
+ void vsp1_dl_body_put(struct vsp1_dl_body *dlb);
+ 
+-struct vsp1_dl_body *vsp1_dl_body_alloc(struct vsp1_device *vsp1,
+-					unsigned int num_entries);
+-void vsp1_dl_body_free(struct vsp1_dl_body *dlb);
+ void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data);
+ int vsp1_dl_list_add_body(struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb);
+ int vsp1_dl_list_add_chain(struct vsp1_dl_list *head, struct vsp1_dl_list *dl);
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index acbaca0f47f0..6b358617ce15 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -19,6 +19,8 @@
+ #define LUT_MIN_SIZE				4U
+ #define LUT_MAX_SIZE				8190U
+ 
++#define LUT_SIZE				256
++
+ /* -----------------------------------------------------------------------------
+  * Device Access
+  */
+@@ -40,11 +42,11 @@ static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl)
+ 	struct vsp1_dl_body *dlb;
+ 	unsigned int i;
+ 
+-	dlb = vsp1_dl_body_alloc(lut->entity.vsp1, 256);
++	dlb = vsp1_dl_body_get(lut->pool);
+ 	if (!dlb)
+ 		return -ENOMEM;
+ 
+-	for (i = 0; i < 256; ++i)
++	for (i = 0; i < LUT_SIZE; ++i)
+ 		vsp1_dl_body_write(dlb, VI6_LUT_TABLE + 4 * i,
+ 				       ctrl->p_new.p_u32[i]);
+ 
+@@ -52,7 +54,7 @@ static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl)
+ 	swap(lut->lut, dlb);
+ 	spin_unlock_irq(&lut->lock);
+ 
+-	vsp1_dl_body_free(dlb);
++	vsp1_dl_body_put(dlb);
+ 	return 0;
+ }
+ 
+@@ -83,7 +85,7 @@ static const struct v4l2_ctrl_config lut_table_control = {
+ 	.max = 0x00ffffff,
+ 	.step = 1,
+ 	.def = 0,
+-	.dims = { 256},
++	.dims = { LUT_SIZE },
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -172,8 +174,16 @@ static void lut_configure(struct vsp1_entity *entity,
+ 	}
+ }
+ 
++static void lut_destroy(struct vsp1_entity *entity)
++{
++	struct vsp1_lut *lut = to_lut(&entity->subdev);
++
++	vsp1_dl_body_pool_destroy(lut->pool);
++}
++
+ static const struct vsp1_entity_operations lut_entity_ops = {
+ 	.configure = lut_configure,
++	.destroy = lut_destroy,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -199,6 +209,15 @@ struct vsp1_lut *vsp1_lut_create(struct vsp1_device *vsp1)
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
++	/*
++	 * Pre-allocate a body pool, with 3 bodies allowing a userspace update
++	 * before the hardware has committed a previous set of tables, handling
++	 * both the queued and pending dl entries.
++	 */
++	lut->pool = vsp1_dl_body_pool_create(vsp1, 3, LUT_SIZE, 0);
++	if (!lut->pool)
++		return ERR_PTR(-ENOMEM);
++
+ 	/* Initialize the control handler. */
+ 	v4l2_ctrl_handler_init(&lut->ctrls, 1);
+ 	v4l2_ctrl_new_custom(&lut->ctrls, &lut_table_control, NULL);
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.h b/drivers/media/platform/vsp1/vsp1_lut.h
+index dce2fdc315f6..8cb0df1b7e27 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.h
++++ b/drivers/media/platform/vsp1/vsp1_lut.h
+@@ -29,6 +29,7 @@ struct vsp1_lut {
+ 
+ 	spinlock_t lock;
+ 	struct vsp1_dl_body *lut;
++	struct vsp1_dl_body_pool *pool;
+ };
+ 
+ static inline struct vsp1_lut *to_lut(struct v4l2_subdev *subdev)
+-- 
+2.19.0
+
diff --git a/patches/1198-media-vsp1-Use-reference-counting-for-bodies.patch b/patches/1198-media-vsp1-Use-reference-counting-for-bodies.patch
new file mode 100644
index 00000000000000..85d1095fb1b4fe
--- /dev/null
+++ b/patches/1198-media-vsp1-Use-reference-counting-for-bodies.patch
@@ -0,0 +1,126 @@
+From 3f922cd5be091b57d4e7b9758f1f55bf1d46090d Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:42:00 -0400
+Subject: [PATCH 1198/1795] media: vsp1: Use reference counting for bodies
+
+Extend the display list body with a reference count, allowing bodies to
+be kept as long as a reference is maintained. This provides the ability
+to keep a cached copy of bodies which will not change, so that they can
+be re-applied to multiple display lists.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 2d9445db0ee9d8695ab3dadb614829b70e43b61f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_clu.c |  7 ++++++-
+ drivers/media/platform/vsp1/vsp1_dl.c  | 16 ++++++++++++++--
+ drivers/media/platform/vsp1/vsp1_lut.c |  7 ++++++-
+ 3 files changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index 8efa12f5e53f..ea83f1b7d125 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -212,8 +212,13 @@ static void clu_configure(struct vsp1_entity *entity,
+ 		clu->clu = NULL;
+ 		spin_unlock_irqrestore(&clu->lock, flags);
+ 
+-		if (dlb)
++		if (dlb) {
+ 			vsp1_dl_list_add_body(dl, dlb);
++
++			/* Release our local reference. */
++			vsp1_dl_body_put(dlb);
++		}
++
+ 		break;
+ 	}
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 617c46a03dec..1407c90c6880 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -10,6 +10,7 @@
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/gfp.h>
++#include <linux/refcount.h>
+ #include <linux/slab.h>
+ #include <linux/workqueue.h>
+ 
+@@ -54,6 +55,8 @@ struct vsp1_dl_body {
+ 	struct list_head list;
+ 	struct list_head free;
+ 
++	refcount_t refcnt;
++
+ 	struct vsp1_dl_body_pool *pool;
+ 	struct vsp1_device *vsp1;
+ 
+@@ -258,6 +261,7 @@ struct vsp1_dl_body *vsp1_dl_body_get(struct vsp1_dl_body_pool *pool)
+ 	if (!list_empty(&pool->free)) {
+ 		dlb = list_first_entry(&pool->free, struct vsp1_dl_body, free);
+ 		list_del(&dlb->free);
++		refcount_set(&dlb->refcnt, 1);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&pool->lock, flags);
+@@ -278,6 +282,9 @@ void vsp1_dl_body_put(struct vsp1_dl_body *dlb)
+ 	if (!dlb)
+ 		return;
+ 
++	if (!refcount_dec_and_test(&dlb->refcnt))
++		return;
++
+ 	dlb->num_entries = 0;
+ 
+ 	spin_lock_irqsave(&dlb->pool->lock, flags);
+@@ -463,8 +470,11 @@ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
+  * which bodies are added.
+  *
+  * Adding a body to a display list passes ownership of the body to the list. The
+- * caller must not touch the body after this call, and must not release it
+- * explicitly with vsp1_dl_body_put().
++ * caller retains its reference to the fragment when adding it to the display
++ * list, but is not allowed to add new entries to the body.
++ *
++ * The reference must be explicitly released by a call to vsp1_dl_body_put()
++ * when the body isn't needed anymore.
+  *
+  * Additional bodies are only usable for display lists in header mode.
+  * Attempting to add a body to a header-less display list will return an error.
+@@ -475,6 +485,8 @@ int vsp1_dl_list_add_body(struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb)
+ 	if (dl->dlm->mode != VSP1_DL_MODE_HEADER)
+ 		return -EINVAL;
+ 
++	refcount_inc(&dlb->refcnt);
++
+ 	list_add_tail(&dlb->list, &dl->bodies);
+ 
+ 	return 0;
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index 6b358617ce15..b3ea90172439 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -168,8 +168,13 @@ static void lut_configure(struct vsp1_entity *entity,
+ 		lut->lut = NULL;
+ 		spin_unlock_irqrestore(&lut->lock, flags);
+ 
+-		if (dlb)
++		if (dlb) {
+ 			vsp1_dl_list_add_body(dl, dlb);
++
++			/* Release our local reference. */
++			vsp1_dl_body_put(dlb);
++		}
++
+ 		break;
+ 	}
+ }
+-- 
+2.19.0
+
diff --git a/patches/1199-media-vsp1-Refactor-display-list-configure-operation.patch b/patches/1199-media-vsp1-Refactor-display-list-configure-operation.patch
new file mode 100644
index 00000000000000..b8044202ca613a
--- /dev/null
+++ b/patches/1199-media-vsp1-Refactor-display-list-configure-operation.patch
@@ -0,0 +1,1293 @@
+From 47fd8baef33883c8ad6e783c8e16f1b89f345b42 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:42:01 -0400
+Subject: [PATCH 1199/1795] media: vsp1: Refactor display list configure
+ operations
+
+The entities provide a single .configure operation which configures the
+object into the target display list, based on the vsp1_entity_params
+selection.
+
+Split the configure function into three parts, '.configure_stream()',
+'.configure_frame()', and '.configure_partition()' to facilitate
+splitting the configuration of each parameter class into separate
+display list bodies.
+
+[laurent.pinchart+renesas@ideasonboard.com: Blank line reformatting, remote unneeded local variable initialization]
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 46ce3639a579c29dc3166a9a66522f72f11f560c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_brx.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_clu.c    |  78 +++---
+ drivers/media/platform/vsp1/vsp1_drm.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_entity.c |  24 ++
+ drivers/media/platform/vsp1/vsp1_entity.h |  39 +--
+ drivers/media/platform/vsp1/vsp1_hgo.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_hgt.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_hsit.c   |  12 +-
+ drivers/media/platform/vsp1/vsp1_lif.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_lut.c    |  47 ++--
+ drivers/media/platform/vsp1/vsp1_rpf.c    | 168 ++++++------
+ drivers/media/platform/vsp1/vsp1_sru.c    |  12 +-
+ drivers/media/platform/vsp1/vsp1_uds.c    |  56 ++--
+ drivers/media/platform/vsp1/vsp1_uif.c    |  16 +-
+ drivers/media/platform/vsp1/vsp1_video.c  |  28 +-
+ drivers/media/platform/vsp1/vsp1_wpf.c    | 302 ++++++++++++----------
+ 16 files changed, 422 insertions(+), 420 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_brx.c b/drivers/media/platform/vsp1/vsp1_brx.c
+index 3beec18fd863..011edac5ebc1 100644
+--- a/drivers/media/platform/vsp1/vsp1_brx.c
++++ b/drivers/media/platform/vsp1/vsp1_brx.c
+@@ -281,19 +281,15 @@ static const struct v4l2_subdev_ops brx_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void brx_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void brx_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_brx *brx = to_brx(&entity->subdev);
+ 	struct v4l2_mbus_framefmt *format;
+ 	unsigned int flags;
+ 	unsigned int i;
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	format = vsp1_entity_get_pad_format(&brx->entity, brx->entity.config,
+ 					    brx->entity.source_pad);
+ 
+@@ -400,7 +396,7 @@ static void brx_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations brx_entity_ops = {
+-	.configure = brx_configure,
++	.configure_stream = brx_configure_stream,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index ea83f1b7d125..34f17a82ac1f 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -169,57 +169,50 @@ static const struct v4l2_subdev_ops clu_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void clu_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void clu_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
++{
++	struct vsp1_clu *clu = to_clu(&entity->subdev);
++	struct v4l2_mbus_framefmt *format;
++
++	/*
++	 * The yuv_mode can't be changed during streaming. Cache it internally
++	 * for future runtime configuration calls.
++	 */
++	format = vsp1_entity_get_pad_format(&clu->entity,
++					    clu->entity.config,
++					    CLU_PAD_SINK);
++	clu->yuv_mode = format->code == MEDIA_BUS_FMT_AYUV8_1X32;
++}
++
++static void clu_configure_frame(struct vsp1_entity *entity,
++				struct vsp1_pipeline *pipe,
++				struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_clu *clu = to_clu(&entity->subdev);
+ 	struct vsp1_dl_body *dlb;
+ 	unsigned long flags;
+ 	u32 ctrl = VI6_CLU_CTRL_AAI | VI6_CLU_CTRL_MVS | VI6_CLU_CTRL_EN;
+ 
+-	switch (params) {
+-	case VSP1_ENTITY_PARAMS_INIT: {
+-		/*
+-		 * The format can't be changed during streaming, only verify it
+-		 * at setup time and store the information internally for future
+-		 * runtime configuration calls.
+-		 */
+-		struct v4l2_mbus_framefmt *format;
+-
+-		format = vsp1_entity_get_pad_format(&clu->entity,
+-						    clu->entity.config,
+-						    CLU_PAD_SINK);
+-		clu->yuv_mode = format->code == MEDIA_BUS_FMT_AYUV8_1X32;
+-		break;
+-	}
+-
+-	case VSP1_ENTITY_PARAMS_PARTITION:
+-		break;
++	/* 2D mode can only be used with the YCbCr pixel encoding. */
++	if (clu->mode == V4L2_CID_VSP1_CLU_MODE_2D && clu->yuv_mode)
++		ctrl |= VI6_CLU_CTRL_AX1I_2D | VI6_CLU_CTRL_AX2I_2D
++		     |  VI6_CLU_CTRL_OS0_2D | VI6_CLU_CTRL_OS1_2D
++		     |  VI6_CLU_CTRL_OS2_2D | VI6_CLU_CTRL_M2D;
+ 
+-	case VSP1_ENTITY_PARAMS_RUNTIME:
+-		/* 2D mode can only be used with the YCbCr pixel encoding. */
+-		if (clu->mode == V4L2_CID_VSP1_CLU_MODE_2D && clu->yuv_mode)
+-			ctrl |= VI6_CLU_CTRL_AX1I_2D | VI6_CLU_CTRL_AX2I_2D
+-			     |  VI6_CLU_CTRL_OS0_2D | VI6_CLU_CTRL_OS1_2D
+-			     |  VI6_CLU_CTRL_OS2_2D | VI6_CLU_CTRL_M2D;
++	vsp1_clu_write(clu, dl, VI6_CLU_CTRL, ctrl);
+ 
+-		vsp1_clu_write(clu, dl, VI6_CLU_CTRL, ctrl);
++	spin_lock_irqsave(&clu->lock, flags);
++	dlb = clu->clu;
++	clu->clu = NULL;
++	spin_unlock_irqrestore(&clu->lock, flags);
+ 
+-		spin_lock_irqsave(&clu->lock, flags);
+-		dlb = clu->clu;
+-		clu->clu = NULL;
+-		spin_unlock_irqrestore(&clu->lock, flags);
++	if (dlb) {
++		vsp1_dl_list_add_body(dl, dlb);
+ 
+-		if (dlb) {
+-			vsp1_dl_list_add_body(dl, dlb);
+-
+-			/* Release our local reference. */
+-			vsp1_dl_body_put(dlb);
+-		}
+-
+-		break;
++		/* Release our local reference. */
++		vsp1_dl_body_put(dlb);
+ 	}
+ }
+ 
+@@ -231,7 +224,8 @@ static void clu_destroy(struct vsp1_entity *entity)
+ }
+ 
+ static const struct vsp1_entity_operations clu_entity_ops = {
+-	.configure = clu_configure,
++	.configure_stream = clu_configure_stream,
++	.configure_frame = clu_configure_frame,
+ 	.destroy = clu_destroy,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 68e8830f27fa..32ab98f101c1 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -552,15 +552,9 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 		}
+ 
+ 		vsp1_entity_route_setup(entity, pipe, dl);
+-
+-		if (entity->ops->configure) {
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_INIT);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_RUNTIME);
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_PARTITION);
+-		}
++		vsp1_entity_configure_stream(entity, pipe, dl);
++		vsp1_entity_configure_frame(entity, pipe, dl);
++		vsp1_entity_configure_partition(entity, pipe, dl);
+ 	}
+ 
+ 	vsp1_dl_list_commit(dl, drm_pipe->force_brx_release);
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index c411643695e4..73f6611ec279 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -69,6 +69,30 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 	vsp1_dl_list_write(dl, source->route->reg, route);
+ }
+ 
++void vsp1_entity_configure_stream(struct vsp1_entity *entity,
++				  struct vsp1_pipeline *pipe,
++				  struct vsp1_dl_list *dl)
++{
++	if (entity->ops->configure_stream)
++		entity->ops->configure_stream(entity, pipe, dl);
++}
++
++void vsp1_entity_configure_frame(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
++{
++	if (entity->ops->configure_frame)
++		entity->ops->configure_frame(entity, pipe, dl);
++}
++
++void vsp1_entity_configure_partition(struct vsp1_entity *entity,
++				     struct vsp1_pipeline *pipe,
++				     struct vsp1_dl_list *dl)
++{
++	if (entity->ops->configure_partition)
++		entity->ops->configure_partition(entity, pipe, dl);
++}
++
+ /* -----------------------------------------------------------------------------
+  * V4L2 Subdevice Operations
+  */
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index 94490d697dcf..c29676671b1a 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -37,18 +37,6 @@ enum vsp1_entity_type {
+ 	VSP1_ENTITY_WPF,
+ };
+ 
+-/**
+- * enum vsp1_entity_params - Entity configuration parameters class
+- * @VSP1_ENTITY_PARAMS_INIT - Initial parameters
+- * @VSP1_ENTITY_PARAMS_PARTITION - Per-image partition parameters
+- * @VSP1_ENTITY_PARAMS_RUNTIME - Runtime-configurable parameters
+- */
+-enum vsp1_entity_params {
+-	VSP1_ENTITY_PARAMS_INIT,
+-	VSP1_ENTITY_PARAMS_PARTITION,
+-	VSP1_ENTITY_PARAMS_RUNTIME,
+-};
+-
+ #define VSP1_ENTITY_MAX_INPUTS		5	/* For the BRU */
+ 
+ /*
+@@ -77,8 +65,10 @@ struct vsp1_route {
+ /**
+  * struct vsp1_entity_operations - Entity operations
+  * @destroy:	Destroy the entity.
+- * @configure:	Setup the hardware based on the entity state (pipeline, formats,
+- *		selection rectangles, ...)
++ * @configure_stream:	Setup the hardware parameters for the stream which do
++ *			not vary between frames (pipeline, formats).
++ * @configure_frame:	Configure the runtime parameters for each frame.
++ * @configure_partition: Configure partition specific parameters.
+  * @max_width:	Return the max supported width of data that the entity can
+  *		process in a single operation.
+  * @partition:	Process the partition construction based on this entity's
+@@ -86,8 +76,13 @@ struct vsp1_route {
+  */
+ struct vsp1_entity_operations {
+ 	void (*destroy)(struct vsp1_entity *);
+-	void (*configure)(struct vsp1_entity *, struct vsp1_pipeline *,
+-			  struct vsp1_dl_list *, enum vsp1_entity_params);
++	void (*configure_stream)(struct vsp1_entity *, struct vsp1_pipeline *,
++				 struct vsp1_dl_list *);
++	void (*configure_frame)(struct vsp1_entity *, struct vsp1_pipeline *,
++					struct vsp1_dl_list *);
++	void (*configure_partition)(struct vsp1_entity *,
++				    struct vsp1_pipeline *,
++				    struct vsp1_dl_list *);
+ 	unsigned int (*max_width)(struct vsp1_entity *, struct vsp1_pipeline *);
+ 	void (*partition)(struct vsp1_entity *, struct vsp1_pipeline *,
+ 			  struct vsp1_partition *, unsigned int,
+@@ -156,6 +151,18 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 			     struct vsp1_pipeline *pipe,
+ 			     struct vsp1_dl_list *dl);
+ 
++void vsp1_entity_configure_stream(struct vsp1_entity *entity,
++				  struct vsp1_pipeline *pipe,
++				  struct vsp1_dl_list *dl);
++
++void vsp1_entity_configure_frame(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl);
++
++void vsp1_entity_configure_partition(struct vsp1_entity *entity,
++				     struct vsp1_pipeline *pipe,
++				     struct vsp1_dl_list *dl);
++
+ struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad);
+ 
+ int vsp1_subdev_get_pad_format(struct v4l2_subdev *subdev,
+diff --git a/drivers/media/platform/vsp1/vsp1_hgo.c b/drivers/media/platform/vsp1/vsp1_hgo.c
+index d514807ccdf4..8855ad15d132 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgo.c
++++ b/drivers/media/platform/vsp1/vsp1_hgo.c
+@@ -129,10 +129,9 @@ static const struct v4l2_ctrl_config hgo_num_bins_control = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void hgo_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void hgo_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
+ 	struct v4l2_rect *compose;
+@@ -140,9 +139,6 @@ static void hgo_configure(struct vsp1_entity *entity,
+ 	unsigned int hratio;
+ 	unsigned int vratio;
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	crop = vsp1_entity_get_pad_selection(entity, entity->config,
+ 					     HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);
+ 	compose = vsp1_entity_get_pad_selection(entity, entity->config,
+@@ -174,7 +170,7 @@ static void hgo_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations hgo_entity_ops = {
+-	.configure = hgo_configure,
++	.configure_stream = hgo_configure_stream,
+ 	.destroy = vsp1_histogram_destroy,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_hgt.c b/drivers/media/platform/vsp1/vsp1_hgt.c
+index 18dc89f47c45..a7ec2c9fdc5c 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgt.c
++++ b/drivers/media/platform/vsp1/vsp1_hgt.c
+@@ -125,10 +125,9 @@ static const struct v4l2_ctrl_config hgt_hue_areas = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void hgt_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void hgt_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_hgt *hgt = to_hgt(&entity->subdev);
+ 	struct v4l2_rect *compose;
+@@ -139,9 +138,6 @@ static void hgt_configure(struct vsp1_entity *entity,
+ 	u8 upper;
+ 	unsigned int i;
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	crop = vsp1_entity_get_pad_selection(entity, entity->config,
+ 					     HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);
+ 	compose = vsp1_entity_get_pad_selection(entity, entity->config,
+@@ -175,7 +171,7 @@ static void hgt_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations hgt_entity_ops = {
+-	.configure = hgt_configure,
++	.configure_stream = hgt_configure_stream,
+ 	.destroy = vsp1_histogram_destroy,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_hsit.c b/drivers/media/platform/vsp1/vsp1_hsit.c
+index 7ba3535f3c9b..798c1448e3dc 100644
+--- a/drivers/media/platform/vsp1/vsp1_hsit.c
++++ b/drivers/media/platform/vsp1/vsp1_hsit.c
+@@ -127,16 +127,12 @@ static const struct v4l2_subdev_ops hsit_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void hsit_configure(struct vsp1_entity *entity,
+-			   struct vsp1_pipeline *pipe,
+-			   struct vsp1_dl_list *dl,
+-			   enum vsp1_entity_params params)
++static void hsit_configure_stream(struct vsp1_entity *entity,
++				  struct vsp1_pipeline *pipe,
++				  struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_hsit *hsit = to_hsit(&entity->subdev);
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	if (hsit->inverse)
+ 		vsp1_hsit_write(hsit, dl, VI6_HSI_CTRL, VI6_HSI_CTRL_EN);
+ 	else
+@@ -144,7 +140,7 @@ static void hsit_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations hsit_entity_ops = {
+-	.configure = hsit_configure,
++	.configure_stream = hsit_configure_stream,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index fbdd5715f829..5a3f3e7b9bd3 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -81,10 +81,9 @@ static const struct v4l2_subdev_ops lif_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void lif_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void lif_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	const struct v4l2_mbus_framefmt *format;
+ 	struct vsp1_lif *lif = to_lif(&entity->subdev);
+@@ -92,9 +91,6 @@ static void lif_configure(struct vsp1_entity *entity,
+ 	unsigned int obth = 400;
+ 	unsigned int lbth = 200;
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	format = vsp1_entity_get_pad_format(&lif->entity, lif->entity.config,
+ 					    LIF_PAD_SOURCE);
+ 
+@@ -123,7 +119,7 @@ static void lif_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations lif_entity_ops = {
+-	.configure = lif_configure,
++	.configure_stream = lif_configure_stream,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index b3ea90172439..1b62f54dc302 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -145,37 +145,33 @@ static const struct v4l2_subdev_ops lut_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void lut_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void lut_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_lut *lut = to_lut(&entity->subdev);
+-	struct vsp1_dl_body *dlb;
+-	unsigned long flags;
+-
+-	switch (params) {
+-	case VSP1_ENTITY_PARAMS_INIT:
+-		vsp1_lut_write(lut, dl, VI6_LUT_CTRL, VI6_LUT_CTRL_EN);
+-		break;
+ 
+-	case VSP1_ENTITY_PARAMS_PARTITION:
+-		break;
++	vsp1_lut_write(lut, dl, VI6_LUT_CTRL, VI6_LUT_CTRL_EN);
++}
+ 
+-	case VSP1_ENTITY_PARAMS_RUNTIME:
+-		spin_lock_irqsave(&lut->lock, flags);
+-		dlb = lut->lut;
+-		lut->lut = NULL;
+-		spin_unlock_irqrestore(&lut->lock, flags);
++static void lut_configure_frame(struct vsp1_entity *entity,
++				struct vsp1_pipeline *pipe,
++				struct vsp1_dl_list *dl)
++{
++	struct vsp1_lut *lut = to_lut(&entity->subdev);
++	struct vsp1_dl_body *dlb;
++	unsigned long flags;
+ 
+-		if (dlb) {
+-			vsp1_dl_list_add_body(dl, dlb);
++	spin_lock_irqsave(&lut->lock, flags);
++	dlb = lut->lut;
++	lut->lut = NULL;
++	spin_unlock_irqrestore(&lut->lock, flags);
+ 
+-			/* Release our local reference. */
+-			vsp1_dl_body_put(dlb);
+-		}
++	if (dlb) {
++		vsp1_dl_list_add_body(dl, dlb);
+ 
+-		break;
++		/* Release our local reference. */
++		vsp1_dl_body_put(dlb);
+ 	}
+ }
+ 
+@@ -187,7 +183,8 @@ static void lut_destroy(struct vsp1_entity *entity)
+ }
+ 
+ static const struct vsp1_entity_operations lut_entity_ops = {
+-	.configure = lut_configure,
++	.configure_stream = lut_configure_stream,
++	.configure_frame = lut_configure_frame,
+ 	.destroy = lut_destroy,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c
+index 7005a4c6aa88..deb86cc235ef 100644
+--- a/drivers/media/platform/vsp1/vsp1_rpf.c
++++ b/drivers/media/platform/vsp1/vsp1_rpf.c
+@@ -42,10 +42,9 @@ static const struct v4l2_subdev_ops rpf_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void rpf_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void rpf_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
+ 	const struct vsp1_format_info *fmtinfo = rpf->fmtinfo;
+@@ -57,80 +56,6 @@ static void rpf_configure(struct vsp1_entity *entity,
+ 	u32 pstride;
+ 	u32 infmt;
+ 
+-	if (params == VSP1_ENTITY_PARAMS_RUNTIME) {
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_VRTCOL_SET,
+-			       rpf->alpha << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_MULT_ALPHA, rpf->mult_alpha |
+-			       (rpf->alpha << VI6_RPF_MULT_ALPHA_RATIO_SHIFT));
+-
+-		vsp1_pipeline_propagate_alpha(pipe, dl, rpf->alpha);
+-		return;
+-	}
+-
+-	if (params == VSP1_ENTITY_PARAMS_PARTITION) {
+-		struct vsp1_device *vsp1 = rpf->entity.vsp1;
+-		struct vsp1_rwpf_memory mem = rpf->mem;
+-		struct v4l2_rect crop;
+-
+-		/*
+-		 * Source size and crop offsets.
+-		 *
+-		 * The crop offsets correspond to the location of the crop
+-		 * rectangle top left corner in the plane buffer. Only two
+-		 * offsets are needed, as planes 2 and 3 always have identical
+-		 * strides.
+-		 */
+-		crop = *vsp1_rwpf_get_crop(rpf, rpf->entity.config);
+-
+-		/*
+-		 * Partition Algorithm Control
+-		 *
+-		 * The partition algorithm can split this frame into multiple
+-		 * slices. We must scale our partition window based on the pipe
+-		 * configuration to match the destination partition window.
+-		 * To achieve this, we adjust our crop to provide a 'sub-crop'
+-		 * matching the expected partition window. Only 'left' and
+-		 * 'width' need to be adjusted.
+-		 */
+-		if (pipe->partitions > 1) {
+-			crop.width = pipe->partition->rpf.width;
+-			crop.left += pipe->partition->rpf.left;
+-		}
+-
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_BSIZE,
+-			       (crop.width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) |
+-			       (crop.height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT));
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_ESIZE,
+-			       (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) |
+-			       (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT));
+-
+-		mem.addr[0] += crop.top * format->plane_fmt[0].bytesperline
+-			     + crop.left * fmtinfo->bpp[0] / 8;
+-
+-		if (format->num_planes > 1) {
+-			unsigned int offset;
+-
+-			offset = crop.top * format->plane_fmt[1].bytesperline
+-			       + crop.left / fmtinfo->hsub
+-			       * fmtinfo->bpp[1] / 8;
+-			mem.addr[1] += offset;
+-			mem.addr[2] += offset;
+-		}
+-
+-		/*
+-		 * On Gen3 hardware the SPUVS bit has no effect on 3-planar
+-		 * formats. Swap the U and V planes manually in that case.
+-		 */
+-		if (vsp1->info->gen == 3 && format->num_planes == 3 &&
+-		    fmtinfo->swap_uv)
+-			swap(mem.addr[1], mem.addr[2]);
+-
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]);
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]);
+-		vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]);
+-		return;
+-	}
+-
+ 	/* Stride */
+ 	pstride = format->plane_fmt[0].bytesperline
+ 		<< VI6_RPF_SRCM_PSTRIDE_Y_SHIFT;
+@@ -243,6 +168,89 @@ static void rpf_configure(struct vsp1_entity *entity,
+ 
+ }
+ 
++static void rpf_configure_frame(struct vsp1_entity *entity,
++				struct vsp1_pipeline *pipe,
++				struct vsp1_dl_list *dl)
++{
++	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
++
++	vsp1_rpf_write(rpf, dl, VI6_RPF_VRTCOL_SET,
++		       rpf->alpha << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
++	vsp1_rpf_write(rpf, dl, VI6_RPF_MULT_ALPHA, rpf->mult_alpha |
++		       (rpf->alpha << VI6_RPF_MULT_ALPHA_RATIO_SHIFT));
++
++	vsp1_pipeline_propagate_alpha(pipe, dl, rpf->alpha);
++}
++
++static void rpf_configure_partition(struct vsp1_entity *entity,
++				    struct vsp1_pipeline *pipe,
++				    struct vsp1_dl_list *dl)
++{
++	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
++	struct vsp1_rwpf_memory mem = rpf->mem;
++	struct vsp1_device *vsp1 = rpf->entity.vsp1;
++	const struct vsp1_format_info *fmtinfo = rpf->fmtinfo;
++	const struct v4l2_pix_format_mplane *format = &rpf->format;
++	struct v4l2_rect crop;
++
++	/*
++	 * Source size and crop offsets.
++	 *
++	 * The crop offsets correspond to the location of the crop
++	 * rectangle top left corner in the plane buffer. Only two
++	 * offsets are needed, as planes 2 and 3 always have identical
++	 * strides.
++	 */
++	crop = *vsp1_rwpf_get_crop(rpf, rpf->entity.config);
++
++	/*
++	 * Partition Algorithm Control
++	 *
++	 * The partition algorithm can split this frame into multiple
++	 * slices. We must scale our partition window based on the pipe
++	 * configuration to match the destination partition window.
++	 * To achieve this, we adjust our crop to provide a 'sub-crop'
++	 * matching the expected partition window. Only 'left' and
++	 * 'width' need to be adjusted.
++	 */
++	if (pipe->partitions > 1) {
++		crop.width = pipe->partition->rpf.width;
++		crop.left += pipe->partition->rpf.left;
++	}
++
++	vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_BSIZE,
++		       (crop.width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) |
++		       (crop.height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT));
++	vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_ESIZE,
++		       (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) |
++		       (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT));
++
++	mem.addr[0] += crop.top * format->plane_fmt[0].bytesperline
++		     + crop.left * fmtinfo->bpp[0] / 8;
++
++	if (format->num_planes > 1) {
++		unsigned int offset;
++
++		offset = crop.top * format->plane_fmt[1].bytesperline
++		       + crop.left / fmtinfo->hsub
++		       * fmtinfo->bpp[1] / 8;
++		mem.addr[1] += offset;
++		mem.addr[2] += offset;
++	}
++
++	/*
++	 * On Gen3 hardware the SPUVS bit has no effect on 3-planar
++	 * formats. Swap the U and V planes manually in that case.
++	 */
++	if (vsp1->info->gen == 3 && format->num_planes == 3 &&
++	    fmtinfo->swap_uv)
++		swap(mem.addr[1], mem.addr[2]);
++
++	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]);
++	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]);
++	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]);
++}
++
+ static void rpf_partition(struct vsp1_entity *entity,
+ 			  struct vsp1_pipeline *pipe,
+ 			  struct vsp1_partition *partition,
+@@ -253,7 +261,9 @@ static void rpf_partition(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations rpf_entity_ops = {
+-	.configure = rpf_configure,
++	.configure_stream = rpf_configure_stream,
++	.configure_frame = rpf_configure_frame,
++	.configure_partition = rpf_configure_partition,
+ 	.partition = rpf_partition,
+ };
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_sru.c b/drivers/media/platform/vsp1/vsp1_sru.c
+index 44cb9b134a19..d29f63dfc17e 100644
+--- a/drivers/media/platform/vsp1/vsp1_sru.c
++++ b/drivers/media/platform/vsp1/vsp1_sru.c
+@@ -267,10 +267,9 @@ static const struct v4l2_subdev_ops sru_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void sru_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void sru_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	const struct vsp1_sru_param *param;
+ 	struct vsp1_sru *sru = to_sru(&entity->subdev);
+@@ -278,9 +277,6 @@ static void sru_configure(struct vsp1_entity *entity,
+ 	struct v4l2_mbus_framefmt *output;
+ 	u32 ctrl0;
+ 
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	input = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
+ 					   SRU_PAD_SINK);
+ 	output = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
+@@ -347,7 +343,7 @@ static void sru_partition(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations sru_entity_ops = {
+-	.configure = sru_configure,
++	.configure_stream = sru_configure_stream,
+ 	.max_width = sru_max_width,
+ 	.partition = sru_partition,
+ };
+diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c
+index e5afd69df939..c81ce9e5bff3 100644
+--- a/drivers/media/platform/vsp1/vsp1_uds.c
++++ b/drivers/media/platform/vsp1/vsp1_uds.c
+@@ -255,10 +255,9 @@ static const struct v4l2_subdev_ops uds_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void uds_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void uds_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_uds *uds = to_uds(&entity->subdev);
+ 	const struct v4l2_mbus_framefmt *output;
+@@ -272,27 +271,6 @@ static void uds_configure(struct vsp1_entity *entity,
+ 	output = vsp1_entity_get_pad_format(&uds->entity, uds->entity.config,
+ 					    UDS_PAD_SOURCE);
+ 
+-	if (params == VSP1_ENTITY_PARAMS_PARTITION) {
+-		struct vsp1_partition *partition = pipe->partition;
+-
+-		/* Input size clipping */
+-		vsp1_uds_write(uds, dl, VI6_UDS_HSZCLIP, VI6_UDS_HSZCLIP_HCEN |
+-			       (0 << VI6_UDS_HSZCLIP_HCL_OFST_SHIFT) |
+-			       (partition->uds_sink.width
+-					<< VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT));
+-
+-		/* Output size clipping */
+-		vsp1_uds_write(uds, dl, VI6_UDS_CLIP_SIZE,
+-			       (partition->uds_source.width
+-					<< VI6_UDS_CLIP_SIZE_HSIZE_SHIFT) |
+-			       (output->height
+-					<< VI6_UDS_CLIP_SIZE_VSIZE_SHIFT));
+-		return;
+-	}
+-
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	hscale = uds_compute_ratio(input->width, output->width);
+ 	vscale = uds_compute_ratio(input->height, output->height);
+ 
+@@ -324,6 +302,31 @@ static void uds_configure(struct vsp1_entity *entity,
+ 		       (vscale << VI6_UDS_SCALE_VFRAC_SHIFT));
+ }
+ 
++static void uds_configure_partition(struct vsp1_entity *entity,
++				    struct vsp1_pipeline *pipe,
++				    struct vsp1_dl_list *dl)
++{
++	struct vsp1_uds *uds = to_uds(&entity->subdev);
++	struct vsp1_partition *partition = pipe->partition;
++	const struct v4l2_mbus_framefmt *output;
++
++	output = vsp1_entity_get_pad_format(&uds->entity, uds->entity.config,
++					    UDS_PAD_SOURCE);
++
++	/* Input size clipping */
++	vsp1_uds_write(uds, dl, VI6_UDS_HSZCLIP, VI6_UDS_HSZCLIP_HCEN |
++		       (0 << VI6_UDS_HSZCLIP_HCL_OFST_SHIFT) |
++		       (partition->uds_sink.width
++				<< VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT));
++
++	/* Output size clipping */
++	vsp1_uds_write(uds, dl, VI6_UDS_CLIP_SIZE,
++		       (partition->uds_source.width
++				<< VI6_UDS_CLIP_SIZE_HSIZE_SHIFT) |
++		       (output->height
++				<< VI6_UDS_CLIP_SIZE_VSIZE_SHIFT));
++}
++
+ static unsigned int uds_max_width(struct vsp1_entity *entity,
+ 				  struct vsp1_pipeline *pipe)
+ {
+@@ -380,7 +383,8 @@ static void uds_partition(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations uds_entity_ops = {
+-	.configure = uds_configure,
++	.configure_stream = uds_configure_stream,
++	.configure_partition = uds_configure_partition,
+ 	.max_width = uds_max_width,
+ 	.partition = uds_partition,
+ };
+diff --git a/drivers/media/platform/vsp1/vsp1_uif.c b/drivers/media/platform/vsp1/vsp1_uif.c
+index c219165b15b9..c526e484b326 100644
+--- a/drivers/media/platform/vsp1/vsp1_uif.c
++++ b/drivers/media/platform/vsp1/vsp1_uif.c
+@@ -189,23 +189,15 @@ static const struct v4l2_subdev_ops uif_ops = {
+  * VSP1 Entity Operations
+  */
+ 
+-static void uif_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void uif_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_uif *uif = to_uif(&entity->subdev);
+ 	const struct v4l2_rect *crop;
+ 	unsigned int left;
+ 	unsigned int width;
+ 
+-	/*
+-	 * Per-partition configuration isn't needed as the DISCOM is used in
+-	 * display pipelines only.
+-	 */
+-	if (params != VSP1_ENTITY_PARAMS_INIT)
+-		return;
+-
+ 	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMPMR,
+ 		       VI6_UIF_DISCOM_DOCMPMR_SEL(9));
+ 
+@@ -231,7 +223,7 @@ static void uif_configure(struct vsp1_entity *entity,
+ }
+ 
+ static const struct vsp1_entity_operations uif_entity_ops = {
+-	.configure = uif_configure,
++	.configure_stream = uif_configure_stream,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index 5deb35210055..c457d0626588 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -382,11 +382,8 @@ static void vsp1_video_pipeline_run_partition(struct vsp1_pipeline *pipe,
+ 
+ 	pipe->partition = &pipe->part_table[partition];
+ 
+-	list_for_each_entry(entity, &pipe->entities, list_pipe) {
+-		if (entity->ops->configure)
+-			entity->ops->configure(entity, pipe, dl,
+-					       VSP1_ENTITY_PARAMS_PARTITION);
+-	}
++	list_for_each_entry(entity, &pipe->entities, list_pipe)
++		vsp1_entity_configure_partition(entity, pipe, dl);
+ }
+ 
+ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+@@ -398,21 +395,13 @@ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+ 	if (!pipe->dl)
+ 		pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
+ 
+-	/*
+-	 * Start with the runtime parameters as the configure operation can
+-	 * compute/cache information needed when configuring partitions. This
+-	 * is the case with flipping in the WPF.
+-	 */
+-	list_for_each_entry(entity, &pipe->entities, list_pipe) {
+-		if (entity->ops->configure)
+-			entity->ops->configure(entity, pipe, pipe->dl,
+-					       VSP1_ENTITY_PARAMS_RUNTIME);
+-	}
++	list_for_each_entry(entity, &pipe->entities, list_pipe)
++		vsp1_entity_configure_frame(entity, pipe, pipe->dl);
+ 
+-	/* Run the first partition */
++	/* Run the first partition. */
+ 	vsp1_video_pipeline_run_partition(pipe, pipe->dl, 0);
+ 
+-	/* Process consecutive partitions as necessary */
++	/* Process consecutive partitions as necessary. */
+ 	for (partition = 1; partition < pipe->partitions; ++partition) {
+ 		struct vsp1_dl_list *dl;
+ 
+@@ -833,10 +822,7 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ 
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe) {
+ 		vsp1_entity_route_setup(entity, pipe, pipe->dl);
+-
+-		if (entity->ops->configure)
+-			entity->ops->configure(entity, pipe, pipe->dl,
+-					       VSP1_ENTITY_PARAMS_INIT);
++		vsp1_entity_configure_stream(entity, pipe, pipe->dl);
+ 	}
+ 
+ 	return 0;
+diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c
+index 65ed2f849551..8662c5d2fc64 100644
+--- a/drivers/media/platform/vsp1/vsp1_wpf.c
++++ b/drivers/media/platform/vsp1/vsp1_wpf.c
+@@ -232,10 +232,9 @@ static void vsp1_wpf_destroy(struct vsp1_entity *entity)
+ 	vsp1_dlm_destroy(wpf->dlm);
+ }
+ 
+-static void wpf_configure(struct vsp1_entity *entity,
+-			  struct vsp1_pipeline *pipe,
+-			  struct vsp1_dl_list *dl,
+-			  enum vsp1_entity_params params)
++static void wpf_configure_stream(struct vsp1_entity *entity,
++				 struct vsp1_pipeline *pipe,
++				 struct vsp1_dl_list *dl)
+ {
+ 	struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev);
+ 	struct vsp1_device *vsp1 = wpf->entity.vsp1;
+@@ -245,149 +244,12 @@ static void wpf_configure(struct vsp1_entity *entity,
+ 	u32 outfmt = 0;
+ 	u32 srcrpf = 0;
+ 
+-	if (params == VSP1_ENTITY_PARAMS_RUNTIME) {
+-		const unsigned int mask = BIT(WPF_CTRL_VFLIP)
+-					| BIT(WPF_CTRL_HFLIP);
+-		unsigned long flags;
+-
+-		spin_lock_irqsave(&wpf->flip.lock, flags);
+-		wpf->flip.active = (wpf->flip.active & ~mask)
+-				 | (wpf->flip.pending & mask);
+-		spin_unlock_irqrestore(&wpf->flip.lock, flags);
+-
+-		outfmt = (wpf->alpha << VI6_WPF_OUTFMT_PDV_SHIFT) | wpf->outfmt;
+-
+-		if (wpf->flip.active & BIT(WPF_CTRL_VFLIP))
+-			outfmt |= VI6_WPF_OUTFMT_FLP;
+-		if (wpf->flip.active & BIT(WPF_CTRL_HFLIP))
+-			outfmt |= VI6_WPF_OUTFMT_HFLP;
+-
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_OUTFMT, outfmt);
+-		return;
+-	}
+-
+ 	sink_format = vsp1_entity_get_pad_format(&wpf->entity,
+ 						 wpf->entity.config,
+ 						 RWPF_PAD_SINK);
+ 	source_format = vsp1_entity_get_pad_format(&wpf->entity,
+ 						   wpf->entity.config,
+ 						   RWPF_PAD_SOURCE);
+-
+-	if (params == VSP1_ENTITY_PARAMS_PARTITION) {
+-		const struct v4l2_pix_format_mplane *format = &wpf->format;
+-		const struct vsp1_format_info *fmtinfo = wpf->fmtinfo;
+-		struct vsp1_rwpf_memory mem = wpf->mem;
+-		unsigned int flip = wpf->flip.active;
+-		unsigned int width = sink_format->width;
+-		unsigned int height = sink_format->height;
+-		unsigned int offset;
+-
+-		/*
+-		 * Cropping. The partition algorithm can split the image into
+-		 * multiple slices.
+-		 */
+-		if (pipe->partitions > 1)
+-			width = pipe->partition->wpf.width;
+-
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_HSZCLIP, VI6_WPF_SZCLIP_EN |
+-			       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
+-			       (width << VI6_WPF_SZCLIP_SIZE_SHIFT));
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_VSZCLIP, VI6_WPF_SZCLIP_EN |
+-			       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
+-			       (height << VI6_WPF_SZCLIP_SIZE_SHIFT));
+-
+-		if (pipe->lif)
+-			return;
+-
+-		/*
+-		 * Update the memory offsets based on flipping configuration.
+-		 * The destination addresses point to the locations where the
+-		 * VSP starts writing to memory, which can be any corner of the
+-		 * image depending on the combination of flipping and rotation.
+-		 */
+-
+-		/*
+-		 * First take the partition left coordinate into account.
+-		 * Compute the offset to order the partitions correctly on the
+-		 * output based on whether flipping is enabled. Consider
+-		 * horizontal flipping when rotation is disabled but vertical
+-		 * flipping when rotation is enabled, as rotating the image
+-		 * switches the horizontal and vertical directions. The offset
+-		 * is applied horizontally or vertically accordingly.
+-		 */
+-		if (flip & BIT(WPF_CTRL_HFLIP) && !wpf->flip.rotate)
+-			offset = format->width - pipe->partition->wpf.left
+-				- pipe->partition->wpf.width;
+-		else if (flip & BIT(WPF_CTRL_VFLIP) && wpf->flip.rotate)
+-			offset = format->height - pipe->partition->wpf.left
+-				- pipe->partition->wpf.width;
+-		else
+-			offset = pipe->partition->wpf.left;
+-
+-		for (i = 0; i < format->num_planes; ++i) {
+-			unsigned int hsub = i > 0 ? fmtinfo->hsub : 1;
+-			unsigned int vsub = i > 0 ? fmtinfo->vsub : 1;
+-
+-			if (wpf->flip.rotate)
+-				mem.addr[i] += offset / vsub
+-					     * format->plane_fmt[i].bytesperline;
+-			else
+-				mem.addr[i] += offset / hsub
+-					     * fmtinfo->bpp[i] / 8;
+-		}
+-
+-		if (flip & BIT(WPF_CTRL_VFLIP)) {
+-			/*
+-			 * When rotating the output (after rotation) image
+-			 * height is equal to the partition width (before
+-			 * rotation). Otherwise it is equal to the output
+-			 * image height.
+-			 */
+-			if (wpf->flip.rotate)
+-				height = pipe->partition->wpf.width;
+-			else
+-				height = format->height;
+-
+-			mem.addr[0] += (height - 1)
+-				     * format->plane_fmt[0].bytesperline;
+-
+-			if (format->num_planes > 1) {
+-				offset = (height / fmtinfo->vsub - 1)
+-				       * format->plane_fmt[1].bytesperline;
+-				mem.addr[1] += offset;
+-				mem.addr[2] += offset;
+-			}
+-		}
+-
+-		if (wpf->flip.rotate && !(flip & BIT(WPF_CTRL_HFLIP))) {
+-			unsigned int hoffset = max(0, (int)format->width - 16);
+-
+-			/*
+-			 * Compute the output coordinate. The partition
+-			 * horizontal (left) offset becomes a vertical offset.
+-			 */
+-			for (i = 0; i < format->num_planes; ++i) {
+-				unsigned int hsub = i > 0 ? fmtinfo->hsub : 1;
+-
+-				mem.addr[i] += hoffset / hsub
+-					     * fmtinfo->bpp[i] / 8;
+-			}
+-		}
+-
+-		/*
+-		 * On Gen3 hardware the SPUVS bit has no effect on 3-planar
+-		 * formats. Swap the U and V planes manually in that case.
+-		 */
+-		if (vsp1->info->gen == 3 && format->num_planes == 3 &&
+-		    fmtinfo->swap_uv)
+-			swap(mem.addr[1], mem.addr[2]);
+-
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_Y, mem.addr[0]);
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C0, mem.addr[1]);
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C1, mem.addr[2]);
+-		return;
+-	}
+-
+ 	/* Format */
+ 	if (!pipe->lif) {
+ 		const struct v4l2_pix_format_mplane *format = &wpf->format;
+@@ -461,6 +323,160 @@ static void wpf_configure(struct vsp1_entity *entity,
+ 			   VI6_WFP_IRQ_ENB_DFEE);
+ }
+ 
++static void wpf_configure_frame(struct vsp1_entity *entity,
++				struct vsp1_pipeline *pipe,
++				struct vsp1_dl_list *dl)
++{
++	const unsigned int mask = BIT(WPF_CTRL_VFLIP)
++				| BIT(WPF_CTRL_HFLIP);
++	struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev);
++	unsigned long flags;
++	u32 outfmt;
++
++	spin_lock_irqsave(&wpf->flip.lock, flags);
++	wpf->flip.active = (wpf->flip.active & ~mask)
++			 | (wpf->flip.pending & mask);
++	spin_unlock_irqrestore(&wpf->flip.lock, flags);
++
++	outfmt = (wpf->alpha << VI6_WPF_OUTFMT_PDV_SHIFT) | wpf->outfmt;
++
++	if (wpf->flip.active & BIT(WPF_CTRL_VFLIP))
++		outfmt |= VI6_WPF_OUTFMT_FLP;
++	if (wpf->flip.active & BIT(WPF_CTRL_HFLIP))
++		outfmt |= VI6_WPF_OUTFMT_HFLP;
++
++	vsp1_wpf_write(wpf, dl, VI6_WPF_OUTFMT, outfmt);
++}
++
++static void wpf_configure_partition(struct vsp1_entity *entity,
++				    struct vsp1_pipeline *pipe,
++				    struct vsp1_dl_list *dl)
++{
++	struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev);
++	struct vsp1_device *vsp1 = wpf->entity.vsp1;
++	struct vsp1_rwpf_memory mem = wpf->mem;
++	const struct v4l2_mbus_framefmt *sink_format;
++	const struct v4l2_pix_format_mplane *format = &wpf->format;
++	const struct vsp1_format_info *fmtinfo = wpf->fmtinfo;
++	unsigned int width;
++	unsigned int height;
++	unsigned int offset;
++	unsigned int flip;
++	unsigned int i;
++
++	sink_format = vsp1_entity_get_pad_format(&wpf->entity,
++						 wpf->entity.config,
++						 RWPF_PAD_SINK);
++	width = sink_format->width;
++	height = sink_format->height;
++
++	/*
++	 * Cropping. The partition algorithm can split the image into
++	 * multiple slices.
++	 */
++	if (pipe->partitions > 1)
++		width = pipe->partition->wpf.width;
++
++	vsp1_wpf_write(wpf, dl, VI6_WPF_HSZCLIP, VI6_WPF_SZCLIP_EN |
++		       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
++		       (width << VI6_WPF_SZCLIP_SIZE_SHIFT));
++	vsp1_wpf_write(wpf, dl, VI6_WPF_VSZCLIP, VI6_WPF_SZCLIP_EN |
++		       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
++		       (height << VI6_WPF_SZCLIP_SIZE_SHIFT));
++
++	if (pipe->lif)
++		return;
++
++	/*
++	 * Update the memory offsets based on flipping configuration.
++	 * The destination addresses point to the locations where the
++	 * VSP starts writing to memory, which can be any corner of the
++	 * image depending on the combination of flipping and rotation.
++	 */
++
++	/*
++	 * First take the partition left coordinate into account.
++	 * Compute the offset to order the partitions correctly on the
++	 * output based on whether flipping is enabled. Consider
++	 * horizontal flipping when rotation is disabled but vertical
++	 * flipping when rotation is enabled, as rotating the image
++	 * switches the horizontal and vertical directions. The offset
++	 * is applied horizontally or vertically accordingly.
++	 */
++	flip = wpf->flip.active;
++
++	if (flip & BIT(WPF_CTRL_HFLIP) && !wpf->flip.rotate)
++		offset = format->width - pipe->partition->wpf.left
++			- pipe->partition->wpf.width;
++	else if (flip & BIT(WPF_CTRL_VFLIP) && wpf->flip.rotate)
++		offset = format->height - pipe->partition->wpf.left
++			- pipe->partition->wpf.width;
++	else
++		offset = pipe->partition->wpf.left;
++
++	for (i = 0; i < format->num_planes; ++i) {
++		unsigned int hsub = i > 0 ? fmtinfo->hsub : 1;
++		unsigned int vsub = i > 0 ? fmtinfo->vsub : 1;
++
++		if (wpf->flip.rotate)
++			mem.addr[i] += offset / vsub
++				     * format->plane_fmt[i].bytesperline;
++		else
++			mem.addr[i] += offset / hsub
++				     * fmtinfo->bpp[i] / 8;
++	}
++
++	if (flip & BIT(WPF_CTRL_VFLIP)) {
++		/*
++		 * When rotating the output (after rotation) image
++		 * height is equal to the partition width (before
++		 * rotation). Otherwise it is equal to the output
++		 * image height.
++		 */
++		if (wpf->flip.rotate)
++			height = pipe->partition->wpf.width;
++		else
++			height = format->height;
++
++		mem.addr[0] += (height - 1)
++			     * format->plane_fmt[0].bytesperline;
++
++		if (format->num_planes > 1) {
++			offset = (height / fmtinfo->vsub - 1)
++			       * format->plane_fmt[1].bytesperline;
++			mem.addr[1] += offset;
++			mem.addr[2] += offset;
++		}
++	}
++
++	if (wpf->flip.rotate && !(flip & BIT(WPF_CTRL_HFLIP))) {
++		unsigned int hoffset = max(0, (int)format->width - 16);
++
++		/*
++		 * Compute the output coordinate. The partition
++		 * horizontal (left) offset becomes a vertical offset.
++		 */
++		for (i = 0; i < format->num_planes; ++i) {
++			unsigned int hsub = i > 0 ? fmtinfo->hsub : 1;
++
++			mem.addr[i] += hoffset / hsub
++				     * fmtinfo->bpp[i] / 8;
++		}
++	}
++
++	/*
++	 * On Gen3 hardware the SPUVS bit has no effect on 3-planar
++	 * formats. Swap the U and V planes manually in that case.
++	 */
++	if (vsp1->info->gen == 3 && format->num_planes == 3 &&
++	    fmtinfo->swap_uv)
++		swap(mem.addr[1], mem.addr[2]);
++
++	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_Y, mem.addr[0]);
++	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C0, mem.addr[1]);
++	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C1, mem.addr[2]);
++}
++
+ static unsigned int wpf_max_width(struct vsp1_entity *entity,
+ 				  struct vsp1_pipeline *pipe)
+ {
+@@ -480,7 +496,9 @@ static void wpf_partition(struct vsp1_entity *entity,
+ 
+ static const struct vsp1_entity_operations wpf_entity_ops = {
+ 	.destroy = vsp1_wpf_destroy,
+-	.configure = wpf_configure,
++	.configure_stream = wpf_configure_stream,
++	.configure_frame = wpf_configure_frame,
++	.configure_partition = wpf_configure_partition,
+ 	.max_width = wpf_max_width,
+ 	.partition = wpf_partition,
+ };
+-- 
+2.19.0
+
diff --git a/patches/1200-media-vsp1-Adapt-entities-to-configure-into-a-body.patch b/patches/1200-media-vsp1-Adapt-entities-to-configure-into-a-body.patch
new file mode 100644
index 00000000000000..05a63646fbf797
--- /dev/null
+++ b/patches/1200-media-vsp1-Adapt-entities-to-configure-into-a-body.patch
@@ -0,0 +1,1204 @@
+From 521a2cd416c4ccf6d06bd6b5e22939648bae73e2 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:42:02 -0400
+Subject: [PATCH 1200/1795] media: vsp1: Adapt entities to configure into a
+ body
+
+Currently the entities store their configurations into a display list.
+Adapt this such that the code can be configured into a body directly,
+allowing greater flexibility and control of the content.
+
+All users of vsp1_dl_list_write() are removed in this process, thus it
+too is removed.
+
+A helper, vsp1_dl_list_get_body0() is provided to access the internal body0
+from the display list.
+
+[laurent.pinchart+renesas@ideasonboard.com: Don't remove blank line unnecessarily]
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 12832dd9dde9241a3fcb38ab6ca40d13780476f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_brx.c    | 22 ++++++------
+ drivers/media/platform/vsp1/vsp1_clu.c    | 23 ++++++------
+ drivers/media/platform/vsp1/vsp1_dl.c     | 12 +++----
+ drivers/media/platform/vsp1/vsp1_dl.h     |  2 +-
+ drivers/media/platform/vsp1/vsp1_drm.c    | 12 ++++---
+ drivers/media/platform/vsp1/vsp1_entity.c | 22 ++++++------
+ drivers/media/platform/vsp1/vsp1_entity.h | 18 ++++++----
+ drivers/media/platform/vsp1/vsp1_hgo.c    | 16 ++++-----
+ drivers/media/platform/vsp1/vsp1_hgt.c    | 18 +++++-----
+ drivers/media/platform/vsp1/vsp1_hsit.c   | 10 +++---
+ drivers/media/platform/vsp1/vsp1_lif.c    | 15 ++++----
+ drivers/media/platform/vsp1/vsp1_lut.c    | 23 ++++++------
+ drivers/media/platform/vsp1/vsp1_pipe.c   |  4 +--
+ drivers/media/platform/vsp1/vsp1_pipe.h   |  3 +-
+ drivers/media/platform/vsp1/vsp1_rpf.c    | 43 ++++++++++++-----------
+ drivers/media/platform/vsp1/vsp1_sru.c    | 14 ++++----
+ drivers/media/platform/vsp1/vsp1_uds.c    | 25 ++++++-------
+ drivers/media/platform/vsp1/vsp1_uds.h    |  2 +-
+ drivers/media/platform/vsp1/vsp1_uif.c    | 21 +++++------
+ drivers/media/platform/vsp1/vsp1_video.c  | 16 ++++++---
+ drivers/media/platform/vsp1/vsp1_wpf.c    | 42 +++++++++++-----------
+ 21 files changed, 194 insertions(+), 169 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_brx.c b/drivers/media/platform/vsp1/vsp1_brx.c
+index 011edac5ebc1..359917b5d842 100644
+--- a/drivers/media/platform/vsp1/vsp1_brx.c
++++ b/drivers/media/platform/vsp1/vsp1_brx.c
+@@ -26,10 +26,10 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_brx_write(struct vsp1_brx *brx, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_brx_write(struct vsp1_brx *brx,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, brx->base + reg, data);
++	vsp1_dl_body_write(dlb, brx->base + reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -283,7 +283,7 @@ static const struct v4l2_subdev_ops brx_ops = {
+ 
+ static void brx_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_brx *brx = to_brx(&entity->subdev);
+ 	struct v4l2_mbus_framefmt *format;
+@@ -305,7 +305,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
+ 	 * format at the pipeline output is premultiplied.
+ 	 */
+ 	flags = pipe->output ? pipe->output->format.flags : 0;
+-	vsp1_brx_write(brx, dl, VI6_BRU_INCTRL,
++	vsp1_brx_write(brx, dlb, VI6_BRU_INCTRL,
+ 		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
+ 		       0 : VI6_BRU_INCTRL_NRM);
+ 
+@@ -313,12 +313,12 @@ static void brx_configure_stream(struct vsp1_entity *entity,
+ 	 * Set the background position to cover the whole output image and
+ 	 * configure its color.
+ 	 */
+-	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_SIZE,
++	vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_SIZE,
+ 		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
+ 		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
+-	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_LOC, 0);
++	vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_LOC, 0);
+ 
+-	vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_COL, brx->bgcolor |
++	vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_COL, brx->bgcolor |
+ 		       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
+ 
+ 	/*
+@@ -328,7 +328,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
+ 	 * unit.
+ 	 */
+ 	if (entity->type == VSP1_ENTITY_BRU)
+-		vsp1_brx_write(brx, dl, VI6_BRU_ROP,
++		vsp1_brx_write(brx, dlb, VI6_BRU_ROP,
+ 			       VI6_BRU_ROP_DSTSEL_BRUIN(1) |
+ 			       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
+ 			       VI6_BRU_ROP_AROP(VI6_ROP_NOP));
+@@ -370,7 +370,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
+ 		if (!(entity->type == VSP1_ENTITY_BRU && i == 1))
+ 			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
+ 
+-		vsp1_brx_write(brx, dl, VI6_BRU_CTRL(i), ctrl);
++		vsp1_brx_write(brx, dlb, VI6_BRU_CTRL(i), ctrl);
+ 
+ 		/*
+ 		 * Harcode the blending formula to
+@@ -385,7 +385,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
+ 		 *
+ 		 * otherwise.
+ 		 */
+-		vsp1_brx_write(brx, dl, VI6_BRU_BLD(i),
++		vsp1_brx_write(brx, dlb, VI6_BRU_BLD(i),
+ 			       VI6_BRU_BLD_CCMDX_255_SRC_A |
+ 			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
+ 						VI6_BRU_BLD_CCMDY_SRC_A) |
+diff --git a/drivers/media/platform/vsp1/vsp1_clu.c b/drivers/media/platform/vsp1/vsp1_clu.c
+index 34f17a82ac1f..942fc14c19d1 100644
+--- a/drivers/media/platform/vsp1/vsp1_clu.c
++++ b/drivers/media/platform/vsp1/vsp1_clu.c
+@@ -25,10 +25,10 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_clu_write(struct vsp1_clu *clu, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_clu_write(struct vsp1_clu *clu,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -171,7 +171,7 @@ static const struct v4l2_subdev_ops clu_ops = {
+ 
+ static void clu_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_clu *clu = to_clu(&entity->subdev);
+ 	struct v4l2_mbus_framefmt *format;
+@@ -188,10 +188,11 @@ static void clu_configure_stream(struct vsp1_entity *entity,
+ 
+ static void clu_configure_frame(struct vsp1_entity *entity,
+ 				struct vsp1_pipeline *pipe,
+-				struct vsp1_dl_list *dl)
++				struct vsp1_dl_list *dl,
++				struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_clu *clu = to_clu(&entity->subdev);
+-	struct vsp1_dl_body *dlb;
++	struct vsp1_dl_body *clu_dlb;
+ 	unsigned long flags;
+ 	u32 ctrl = VI6_CLU_CTRL_AAI | VI6_CLU_CTRL_MVS | VI6_CLU_CTRL_EN;
+ 
+@@ -201,18 +202,18 @@ static void clu_configure_frame(struct vsp1_entity *entity,
+ 		     |  VI6_CLU_CTRL_OS0_2D | VI6_CLU_CTRL_OS1_2D
+ 		     |  VI6_CLU_CTRL_OS2_2D | VI6_CLU_CTRL_M2D;
+ 
+-	vsp1_clu_write(clu, dl, VI6_CLU_CTRL, ctrl);
++	vsp1_clu_write(clu, dlb, VI6_CLU_CTRL, ctrl);
+ 
+ 	spin_lock_irqsave(&clu->lock, flags);
+-	dlb = clu->clu;
++	clu_dlb = clu->clu;
+ 	clu->clu = NULL;
+ 	spin_unlock_irqrestore(&clu->lock, flags);
+ 
+-	if (dlb) {
+-		vsp1_dl_list_add_body(dl, dlb);
++	if (clu_dlb) {
++		vsp1_dl_list_add_body(dl, clu_dlb);
+ 
+ 		/* Release our local reference. */
+-		vsp1_dl_body_put(dlb);
++		vsp1_dl_body_put(clu_dlb);
+ 	}
+ }
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index 1407c90c6880..c7fa1cb088cd 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -447,17 +447,15 @@ void vsp1_dl_list_put(struct vsp1_dl_list *dl)
+ }
+ 
+ /**
+- * vsp1_dl_list_write - Write a register to the display list
++ * vsp1_dl_list_get_body0 - Obtain the default body for the display list
+  * @dl: The display list
+- * @reg: The register address
+- * @data: The register value
+  *
+- * Write the given register and value to the display list. Up to 256 registers
+- * can be written per display list.
++ * Obtain a pointer to the internal display list body allowing this to be passed
++ * directly to configure operations.
+  */
+-void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
++struct vsp1_dl_body *vsp1_dl_list_get_body0(struct vsp1_dl_list *dl)
+ {
+-	vsp1_dl_body_write(dl->body0, reg, data);
++	return dl->body0;
+ }
+ 
+ /**
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index 6a7d48e385d5..216bd23029dd 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -31,7 +31,7 @@ unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
+ 
+ struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm);
+ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+-void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data);
++struct vsp1_dl_body *vsp1_dl_list_get_body0(struct vsp1_dl_list *dl);
+ void vsp1_dl_list_commit(struct vsp1_dl_list *dl, bool internal);
+ 
+ struct vsp1_dl_body_pool *
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index 32ab98f101c1..edb35a5c57ea 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -536,13 +536,15 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 	struct vsp1_entity *entity;
+ 	struct vsp1_entity *next;
+ 	struct vsp1_dl_list *dl;
++	struct vsp1_dl_body *dlb;
+ 
+ 	dl = vsp1_dl_list_get(pipe->output->dlm);
++	dlb = vsp1_dl_list_get_body0(dl);
+ 
+ 	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
+ 		/* Disconnect unused entities from the pipeline. */
+ 		if (!entity->pipe) {
+-			vsp1_dl_list_write(dl, entity->route->reg,
++			vsp1_dl_body_write(dlb, entity->route->reg,
+ 					   VI6_DPR_NODE_UNUSED);
+ 
+ 			entity->sink = NULL;
+@@ -551,10 +553,10 @@ static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
+ 			continue;
+ 		}
+ 
+-		vsp1_entity_route_setup(entity, pipe, dl);
+-		vsp1_entity_configure_stream(entity, pipe, dl);
+-		vsp1_entity_configure_frame(entity, pipe, dl);
+-		vsp1_entity_configure_partition(entity, pipe, dl);
++		vsp1_entity_route_setup(entity, pipe, dlb);
++		vsp1_entity_configure_stream(entity, pipe, dlb);
++		vsp1_entity_configure_frame(entity, pipe, dl, dlb);
++		vsp1_entity_configure_partition(entity, pipe, dl, dlb);
+ 	}
+ 
+ 	vsp1_dl_list_commit(dl, drm_pipe->force_brx_release);
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c
+index 73f6611ec279..da276a85aa95 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.c
++++ b/drivers/media/platform/vsp1/vsp1_entity.c
+@@ -22,7 +22,7 @@
+ 
+ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 			     struct vsp1_pipeline *pipe,
+-			     struct vsp1_dl_list *dl)
++			     struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_entity *source;
+ 	u32 route;
+@@ -38,7 +38,7 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 		smppt = (pipe->output->entity.index << VI6_DPR_SMPPT_TGW_SHIFT)
+ 		      | (source->route->output << VI6_DPR_SMPPT_PT_SHIFT);
+ 
+-		vsp1_dl_list_write(dl, VI6_DPR_HGO_SMPPT, smppt);
++		vsp1_dl_body_write(dlb, VI6_DPR_HGO_SMPPT, smppt);
+ 		return;
+ 	} else if (entity->type == VSP1_ENTITY_HGT) {
+ 		u32 smppt;
+@@ -51,7 +51,7 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 		smppt = (pipe->output->entity.index << VI6_DPR_SMPPT_TGW_SHIFT)
+ 		      | (source->route->output << VI6_DPR_SMPPT_PT_SHIFT);
+ 
+-		vsp1_dl_list_write(dl, VI6_DPR_HGT_SMPPT, smppt);
++		vsp1_dl_body_write(dlb, VI6_DPR_HGT_SMPPT, smppt);
+ 		return;
+ 	}
+ 
+@@ -66,31 +66,33 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 	 */
+ 	if (source->type == VSP1_ENTITY_BRS)
+ 		route |= VI6_DPR_ROUTE_BRSSEL;
+-	vsp1_dl_list_write(dl, source->route->reg, route);
++	vsp1_dl_body_write(dlb, source->route->reg, route);
+ }
+ 
+ void vsp1_entity_configure_stream(struct vsp1_entity *entity,
+ 				  struct vsp1_pipeline *pipe,
+-				  struct vsp1_dl_list *dl)
++				  struct vsp1_dl_body *dlb)
+ {
+ 	if (entity->ops->configure_stream)
+-		entity->ops->configure_stream(entity, pipe, dl);
++		entity->ops->configure_stream(entity, pipe, dlb);
+ }
+ 
+ void vsp1_entity_configure_frame(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_list *dl,
++				 struct vsp1_dl_body *dlb)
+ {
+ 	if (entity->ops->configure_frame)
+-		entity->ops->configure_frame(entity, pipe, dl);
++		entity->ops->configure_frame(entity, pipe, dl, dlb);
+ }
+ 
+ void vsp1_entity_configure_partition(struct vsp1_entity *entity,
+ 				     struct vsp1_pipeline *pipe,
+-				     struct vsp1_dl_list *dl)
++				     struct vsp1_dl_list *dl,
++				     struct vsp1_dl_body *dlb)
+ {
+ 	if (entity->ops->configure_partition)
+-		entity->ops->configure_partition(entity, pipe, dl);
++		entity->ops->configure_partition(entity, pipe, dl, dlb);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h
+index c29676671b1a..97acb7795cf1 100644
+--- a/drivers/media/platform/vsp1/vsp1_entity.h
++++ b/drivers/media/platform/vsp1/vsp1_entity.h
+@@ -15,6 +15,7 @@
+ #include <media/v4l2-subdev.h>
+ 
+ struct vsp1_device;
++struct vsp1_dl_body;
+ struct vsp1_dl_list;
+ struct vsp1_pipeline;
+ struct vsp1_partition;
+@@ -77,12 +78,13 @@ struct vsp1_route {
+ struct vsp1_entity_operations {
+ 	void (*destroy)(struct vsp1_entity *);
+ 	void (*configure_stream)(struct vsp1_entity *, struct vsp1_pipeline *,
+-				 struct vsp1_dl_list *);
++				 struct vsp1_dl_body *);
+ 	void (*configure_frame)(struct vsp1_entity *, struct vsp1_pipeline *,
+-					struct vsp1_dl_list *);
++				struct vsp1_dl_list *, struct vsp1_dl_body *);
+ 	void (*configure_partition)(struct vsp1_entity *,
+ 				    struct vsp1_pipeline *,
+-				    struct vsp1_dl_list *);
++				    struct vsp1_dl_list *,
++				    struct vsp1_dl_body *);
+ 	unsigned int (*max_width)(struct vsp1_entity *, struct vsp1_pipeline *);
+ 	void (*partition)(struct vsp1_entity *, struct vsp1_pipeline *,
+ 			  struct vsp1_partition *, unsigned int,
+@@ -149,19 +151,21 @@ int vsp1_entity_init_cfg(struct v4l2_subdev *subdev,
+ 
+ void vsp1_entity_route_setup(struct vsp1_entity *entity,
+ 			     struct vsp1_pipeline *pipe,
+-			     struct vsp1_dl_list *dl);
++			     struct vsp1_dl_body *dlb);
+ 
+ void vsp1_entity_configure_stream(struct vsp1_entity *entity,
+ 				  struct vsp1_pipeline *pipe,
+-				  struct vsp1_dl_list *dl);
++				  struct vsp1_dl_body *dlb);
+ 
+ void vsp1_entity_configure_frame(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl);
++				 struct vsp1_dl_list *dl,
++				 struct vsp1_dl_body *dlb);
+ 
+ void vsp1_entity_configure_partition(struct vsp1_entity *entity,
+ 				     struct vsp1_pipeline *pipe,
+-				     struct vsp1_dl_list *dl);
++				     struct vsp1_dl_list *dl,
++				     struct vsp1_dl_body *dlb);
+ 
+ struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad);
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_hgo.c b/drivers/media/platform/vsp1/vsp1_hgo.c
+index 8855ad15d132..827373c25351 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgo.c
++++ b/drivers/media/platform/vsp1/vsp1_hgo.c
+@@ -28,10 +28,10 @@ static inline u32 vsp1_hgo_read(struct vsp1_hgo *hgo, u32 reg)
+ 	return vsp1_read(hgo->histo.entity.vsp1, reg);
+ }
+ 
+-static inline void vsp1_hgo_write(struct vsp1_hgo *hgo, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_hgo_write(struct vsp1_hgo *hgo,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -131,7 +131,7 @@ static const struct v4l2_ctrl_config hgo_num_bins_control = {
+ 
+ static void hgo_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
+ 	struct v4l2_rect *compose;
+@@ -145,12 +145,12 @@ static void hgo_configure_stream(struct vsp1_entity *entity,
+ 						HISTO_PAD_SINK,
+ 						V4L2_SEL_TGT_COMPOSE);
+ 
+-	vsp1_hgo_write(hgo, dl, VI6_HGO_REGRST, VI6_HGO_REGRST_RCLEA);
++	vsp1_hgo_write(hgo, dlb, VI6_HGO_REGRST, VI6_HGO_REGRST_RCLEA);
+ 
+-	vsp1_hgo_write(hgo, dl, VI6_HGO_OFFSET,
++	vsp1_hgo_write(hgo, dlb, VI6_HGO_OFFSET,
+ 		       (crop->left << VI6_HGO_OFFSET_HOFFSET_SHIFT) |
+ 		       (crop->top << VI6_HGO_OFFSET_VOFFSET_SHIFT));
+-	vsp1_hgo_write(hgo, dl, VI6_HGO_SIZE,
++	vsp1_hgo_write(hgo, dlb, VI6_HGO_SIZE,
+ 		       (crop->width << VI6_HGO_SIZE_HSIZE_SHIFT) |
+ 		       (crop->height << VI6_HGO_SIZE_VSIZE_SHIFT));
+ 
+@@ -162,7 +162,7 @@ static void hgo_configure_stream(struct vsp1_entity *entity,
+ 
+ 	hratio = crop->width * 2 / compose->width / 3;
+ 	vratio = crop->height * 2 / compose->height / 3;
+-	vsp1_hgo_write(hgo, dl, VI6_HGO_MODE,
++	vsp1_hgo_write(hgo, dlb, VI6_HGO_MODE,
+ 		       (hgo->num_bins == 256 ? VI6_HGO_MODE_STEP : 0) |
+ 		       (hgo->max_rgb ? VI6_HGO_MODE_MAXRGB : 0) |
+ 		       (hratio << VI6_HGO_MODE_HRATIO_SHIFT) |
+diff --git a/drivers/media/platform/vsp1/vsp1_hgt.c b/drivers/media/platform/vsp1/vsp1_hgt.c
+index a7ec2c9fdc5c..bb6ce6fdd5f4 100644
+--- a/drivers/media/platform/vsp1/vsp1_hgt.c
++++ b/drivers/media/platform/vsp1/vsp1_hgt.c
+@@ -28,10 +28,10 @@ static inline u32 vsp1_hgt_read(struct vsp1_hgt *hgt, u32 reg)
+ 	return vsp1_read(hgt->histo.entity.vsp1, reg);
+ }
+ 
+-static inline void vsp1_hgt_write(struct vsp1_hgt *hgt, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_hgt_write(struct vsp1_hgt *hgt,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -127,7 +127,7 @@ static const struct v4l2_ctrl_config hgt_hue_areas = {
+ 
+ static void hgt_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_hgt *hgt = to_hgt(&entity->subdev);
+ 	struct v4l2_rect *compose;
+@@ -144,12 +144,12 @@ static void hgt_configure_stream(struct vsp1_entity *entity,
+ 						HISTO_PAD_SINK,
+ 						V4L2_SEL_TGT_COMPOSE);
+ 
+-	vsp1_hgt_write(hgt, dl, VI6_HGT_REGRST, VI6_HGT_REGRST_RCLEA);
++	vsp1_hgt_write(hgt, dlb, VI6_HGT_REGRST, VI6_HGT_REGRST_RCLEA);
+ 
+-	vsp1_hgt_write(hgt, dl, VI6_HGT_OFFSET,
++	vsp1_hgt_write(hgt, dlb, VI6_HGT_OFFSET,
+ 		       (crop->left << VI6_HGT_OFFSET_HOFFSET_SHIFT) |
+ 		       (crop->top << VI6_HGT_OFFSET_VOFFSET_SHIFT));
+-	vsp1_hgt_write(hgt, dl, VI6_HGT_SIZE,
++	vsp1_hgt_write(hgt, dlb, VI6_HGT_SIZE,
+ 		       (crop->width << VI6_HGT_SIZE_HSIZE_SHIFT) |
+ 		       (crop->height << VI6_HGT_SIZE_VSIZE_SHIFT));
+ 
+@@ -157,7 +157,7 @@ static void hgt_configure_stream(struct vsp1_entity *entity,
+ 	for (i = 0; i < HGT_NUM_HUE_AREAS; ++i) {
+ 		lower = hgt->hue_areas[i*2 + 0];
+ 		upper = hgt->hue_areas[i*2 + 1];
+-		vsp1_hgt_write(hgt, dl, VI6_HGT_HUE_AREA(i),
++		vsp1_hgt_write(hgt, dlb, VI6_HGT_HUE_AREA(i),
+ 			       (lower << VI6_HGT_HUE_AREA_LOWER_SHIFT) |
+ 			       (upper << VI6_HGT_HUE_AREA_UPPER_SHIFT));
+ 	}
+@@ -165,7 +165,7 @@ static void hgt_configure_stream(struct vsp1_entity *entity,
+ 
+ 	hratio = crop->width * 2 / compose->width / 3;
+ 	vratio = crop->height * 2 / compose->height / 3;
+-	vsp1_hgt_write(hgt, dl, VI6_HGT_MODE,
++	vsp1_hgt_write(hgt, dlb, VI6_HGT_MODE,
+ 		       (hratio << VI6_HGT_MODE_HRATIO_SHIFT) |
+ 		       (vratio << VI6_HGT_MODE_VRATIO_SHIFT));
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_hsit.c b/drivers/media/platform/vsp1/vsp1_hsit.c
+index 798c1448e3dc..39ab2e0c7c18 100644
+--- a/drivers/media/platform/vsp1/vsp1_hsit.c
++++ b/drivers/media/platform/vsp1/vsp1_hsit.c
+@@ -24,9 +24,9 @@
+  */
+ 
+ static inline void vsp1_hsit_write(struct vsp1_hsit *hsit,
+-				   struct vsp1_dl_list *dl, u32 reg, u32 data)
++				   struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -129,14 +129,14 @@ static const struct v4l2_subdev_ops hsit_ops = {
+ 
+ static void hsit_configure_stream(struct vsp1_entity *entity,
+ 				  struct vsp1_pipeline *pipe,
+-				  struct vsp1_dl_list *dl)
++				  struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_hsit *hsit = to_hsit(&entity->subdev);
+ 
+ 	if (hsit->inverse)
+-		vsp1_hsit_write(hsit, dl, VI6_HSI_CTRL, VI6_HSI_CTRL_EN);
++		vsp1_hsit_write(hsit, dlb, VI6_HSI_CTRL, VI6_HSI_CTRL_EN);
+ 	else
+-		vsp1_hsit_write(hsit, dl, VI6_HST_CTRL, VI6_HST_CTRL_EN);
++		vsp1_hsit_write(hsit, dlb, VI6_HST_CTRL, VI6_HST_CTRL_EN);
+ }
+ 
+ static const struct vsp1_entity_operations hsit_entity_ops = {
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index 5a3f3e7b9bd3..0cb63244b21a 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -23,10 +23,11 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_lif_write(struct vsp1_lif *lif, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_lif_write(struct vsp1_lif *lif,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg + lif->entity.index * VI6_LIF_OFFSET, data);
++	vsp1_dl_body_write(dlb, reg + lif->entity.index * VI6_LIF_OFFSET,
++			       data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -83,7 +84,7 @@ static const struct v4l2_subdev_ops lif_ops = {
+ 
+ static void lif_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	const struct v4l2_mbus_framefmt *format;
+ 	struct vsp1_lif *lif = to_lif(&entity->subdev);
+@@ -96,11 +97,11 @@ static void lif_configure_stream(struct vsp1_entity *entity,
+ 
+ 	obth = min(obth, (format->width + 1) / 2 * format->height - 4);
+ 
+-	vsp1_lif_write(lif, dl, VI6_LIF_CSBTH,
++	vsp1_lif_write(lif, dlb, VI6_LIF_CSBTH,
+ 			(hbth << VI6_LIF_CSBTH_HBTH_SHIFT) |
+ 			(lbth << VI6_LIF_CSBTH_LBTH_SHIFT));
+ 
+-	vsp1_lif_write(lif, dl, VI6_LIF_CTRL,
++	vsp1_lif_write(lif, dlb, VI6_LIF_CTRL,
+ 			(obth << VI6_LIF_CTRL_OBTH_SHIFT) |
+ 			(format->code == 0 ? VI6_LIF_CTRL_CFMT : 0) |
+ 			VI6_LIF_CTRL_REQSEL | VI6_LIF_CTRL_LIF_EN);
+@@ -113,7 +114,7 @@ static void lif_configure_stream(struct vsp1_entity *entity,
+ 	 */
+ 	if ((entity->vsp1->version & VI6_IP_VERSION_MASK) ==
+ 	    (VI6_IP_VERSION_MODEL_VSPD_V3 | VI6_IP_VERSION_SOC_V3M))
+-		vsp1_lif_write(lif, dl, VI6_LIF_LBA,
++		vsp1_lif_write(lif, dlb, VI6_LIF_LBA,
+ 			       VI6_LIF_LBA_LBA0 |
+ 			       (1536 << VI6_LIF_LBA_LBA1_SHIFT));
+ }
+diff --git a/drivers/media/platform/vsp1/vsp1_lut.c b/drivers/media/platform/vsp1/vsp1_lut.c
+index 1b62f54dc302..64c48d9459b0 100644
+--- a/drivers/media/platform/vsp1/vsp1_lut.c
++++ b/drivers/media/platform/vsp1/vsp1_lut.c
+@@ -25,10 +25,10 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_lut_write(struct vsp1_lut *lut, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_lut_write(struct vsp1_lut *lut,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -147,31 +147,32 @@ static const struct v4l2_subdev_ops lut_ops = {
+ 
+ static void lut_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_lut *lut = to_lut(&entity->subdev);
+ 
+-	vsp1_lut_write(lut, dl, VI6_LUT_CTRL, VI6_LUT_CTRL_EN);
++	vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN);
+ }
+ 
+ static void lut_configure_frame(struct vsp1_entity *entity,
+ 				struct vsp1_pipeline *pipe,
+-				struct vsp1_dl_list *dl)
++				struct vsp1_dl_list *dl,
++				struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_lut *lut = to_lut(&entity->subdev);
+-	struct vsp1_dl_body *dlb;
++	struct vsp1_dl_body *lut_dlb;
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&lut->lock, flags);
+-	dlb = lut->lut;
++	lut_dlb = lut->lut;
+ 	lut->lut = NULL;
+ 	spin_unlock_irqrestore(&lut->lock, flags);
+ 
+-	if (dlb) {
+-		vsp1_dl_list_add_body(dl, dlb);
++	if (lut_dlb) {
++		vsp1_dl_list_add_body(dl, lut_dlb);
+ 
+ 		/* Release our local reference. */
+-		vsp1_dl_body_put(dlb);
++		vsp1_dl_body_put(lut_dlb);
+ 	}
+ }
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
+index da21f1a7cd75..54ff539ffea0 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.c
++++ b/drivers/media/platform/vsp1/vsp1_pipe.c
+@@ -348,7 +348,7 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
+  * from the input RPF alpha.
+  */
+ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
+-				   struct vsp1_dl_list *dl, unsigned int alpha)
++				   struct vsp1_dl_body *dlb, unsigned int alpha)
+ {
+ 	if (!pipe->uds)
+ 		return;
+@@ -361,7 +361,7 @@ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
+ 	    pipe->uds_input->type == VSP1_ENTITY_BRS)
+ 		alpha = 255;
+ 
+-	vsp1_uds_set_alpha(pipe->uds, dl, alpha);
++	vsp1_uds_set_alpha(pipe->uds, dlb, alpha);
+ }
+ 
+ /*
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index 69858ba6cb31..f1155d20fa2d 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -157,7 +157,8 @@ bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe);
+ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe);
+ 
+ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
+-				   struct vsp1_dl_list *dl, unsigned int alpha);
++				   struct vsp1_dl_body *dlb,
++				   unsigned int alpha);
+ 
+ void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
+ 				       struct vsp1_partition *partition,
+diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c
+index deb86cc235ef..69e5fe6e6b50 100644
+--- a/drivers/media/platform/vsp1/vsp1_rpf.c
++++ b/drivers/media/platform/vsp1/vsp1_rpf.c
+@@ -25,9 +25,10 @@
+  */
+ 
+ static inline void vsp1_rpf_write(struct vsp1_rwpf *rpf,
+-				  struct vsp1_dl_list *dl, u32 reg, u32 data)
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg + rpf->entity.index * VI6_RPF_OFFSET, data);
++	vsp1_dl_body_write(dlb, reg + rpf->entity.index * VI6_RPF_OFFSET,
++			       data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -44,7 +45,7 @@ static const struct v4l2_subdev_ops rpf_ops = {
+ 
+ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
+ 	const struct vsp1_format_info *fmtinfo = rpf->fmtinfo;
+@@ -63,7 +64,7 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 		pstride |= format->plane_fmt[1].bytesperline
+ 			<< VI6_RPF_SRCM_PSTRIDE_C_SHIFT;
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_PSTRIDE, pstride);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_PSTRIDE, pstride);
+ 
+ 	/* Format */
+ 	sink_format = vsp1_entity_get_pad_format(&rpf->entity,
+@@ -84,8 +85,8 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 	if (sink_format->code != source_format->code)
+ 		infmt |= VI6_RPF_INFMT_CSC;
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_INFMT, infmt);
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_DSWAP, fmtinfo->swap);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_INFMT, infmt);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_DSWAP, fmtinfo->swap);
+ 
+ 	/* Output location */
+ 	if (pipe->brx) {
+@@ -99,7 +100,7 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 		top = compose->top;
+ 	}
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_LOC,
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_LOC,
+ 		       (left << VI6_RPF_LOC_HCOORD_SHIFT) |
+ 		       (top << VI6_RPF_LOC_VCOORD_SHIFT));
+ 
+@@ -126,7 +127,7 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 	 *
+ 	 * In all cases, disable color keying.
+ 	 */
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT |
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT |
+ 		       (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED
+ 				       : VI6_RPF_ALPH_SEL_ASEL_FIXED));
+ 
+@@ -163,28 +164,30 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
+ 		rpf->mult_alpha = mult;
+ 	}
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_MSK_CTRL, 0);
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_CKEY_CTRL, 0);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_MSK_CTRL, 0);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_CKEY_CTRL, 0);
+ 
+ }
+ 
+ static void rpf_configure_frame(struct vsp1_entity *entity,
+ 				struct vsp1_pipeline *pipe,
+-				struct vsp1_dl_list *dl)
++				struct vsp1_dl_list *dl,
++				struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_VRTCOL_SET,
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_VRTCOL_SET,
+ 		       rpf->alpha << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_MULT_ALPHA, rpf->mult_alpha |
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_MULT_ALPHA, rpf->mult_alpha |
+ 		       (rpf->alpha << VI6_RPF_MULT_ALPHA_RATIO_SHIFT));
+ 
+-	vsp1_pipeline_propagate_alpha(pipe, dl, rpf->alpha);
++	vsp1_pipeline_propagate_alpha(pipe, dlb, rpf->alpha);
+ }
+ 
+ static void rpf_configure_partition(struct vsp1_entity *entity,
+ 				    struct vsp1_pipeline *pipe,
+-				    struct vsp1_dl_list *dl)
++				    struct vsp1_dl_list *dl,
++				    struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
+ 	struct vsp1_rwpf_memory mem = rpf->mem;
+@@ -218,10 +221,10 @@ static void rpf_configure_partition(struct vsp1_entity *entity,
+ 		crop.left += pipe->partition->rpf.left;
+ 	}
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_BSIZE,
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRC_BSIZE,
+ 		       (crop.width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) |
+ 		       (crop.height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT));
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRC_ESIZE,
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRC_ESIZE,
+ 		       (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) |
+ 		       (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT));
+ 
+@@ -246,9 +249,9 @@ static void rpf_configure_partition(struct vsp1_entity *entity,
+ 	    fmtinfo->swap_uv)
+ 		swap(mem.addr[1], mem.addr[2]);
+ 
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]);
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]);
+-	vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]);
++	vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]);
+ }
+ 
+ static void rpf_partition(struct vsp1_entity *entity,
+diff --git a/drivers/media/platform/vsp1/vsp1_sru.c b/drivers/media/platform/vsp1/vsp1_sru.c
+index d29f63dfc17e..04e4e05af6ae 100644
+--- a/drivers/media/platform/vsp1/vsp1_sru.c
++++ b/drivers/media/platform/vsp1/vsp1_sru.c
+@@ -24,10 +24,10 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_sru_write(struct vsp1_sru *sru, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_sru_write(struct vsp1_sru *sru,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg, data);
++	vsp1_dl_body_write(dlb, reg, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -269,7 +269,7 @@ static const struct v4l2_subdev_ops sru_ops = {
+ 
+ static void sru_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	const struct vsp1_sru_param *param;
+ 	struct vsp1_sru *sru = to_sru(&entity->subdev);
+@@ -295,9 +295,9 @@ static void sru_configure_stream(struct vsp1_entity *entity,
+ 
+ 	ctrl0 |= param->ctrl0;
+ 
+-	vsp1_sru_write(sru, dl, VI6_SRU_CTRL0, ctrl0);
+-	vsp1_sru_write(sru, dl, VI6_SRU_CTRL1, VI6_SRU_CTRL1_PARAM5);
+-	vsp1_sru_write(sru, dl, VI6_SRU_CTRL2, param->ctrl2);
++	vsp1_sru_write(sru, dlb, VI6_SRU_CTRL0, ctrl0);
++	vsp1_sru_write(sru, dlb, VI6_SRU_CTRL1, VI6_SRU_CTRL1_PARAM5);
++	vsp1_sru_write(sru, dlb, VI6_SRU_CTRL2, param->ctrl2);
+ }
+ 
+ static unsigned int sru_max_width(struct vsp1_entity *entity,
+diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c
+index c81ce9e5bff3..c20c84b54936 100644
+--- a/drivers/media/platform/vsp1/vsp1_uds.c
++++ b/drivers/media/platform/vsp1/vsp1_uds.c
+@@ -27,22 +27,22 @@
+  * Device Access
+  */
+ 
+-static inline void vsp1_uds_write(struct vsp1_uds *uds, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++static inline void vsp1_uds_write(struct vsp1_uds *uds,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg + uds->entity.index * VI6_UDS_OFFSET, data);
++	vsp1_dl_body_write(dlb, reg + uds->entity.index * VI6_UDS_OFFSET, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+  * Scaling Computation
+  */
+ 
+-void vsp1_uds_set_alpha(struct vsp1_entity *entity, struct vsp1_dl_list *dl,
++void vsp1_uds_set_alpha(struct vsp1_entity *entity, struct vsp1_dl_body *dlb,
+ 			unsigned int alpha)
+ {
+ 	struct vsp1_uds *uds = to_uds(&entity->subdev);
+ 
+-	vsp1_uds_write(uds, dl, VI6_UDS_ALPVAL,
++	vsp1_uds_write(uds, dlb, VI6_UDS_ALPVAL,
+ 		       alpha << VI6_UDS_ALPVAL_VAL0_SHIFT);
+ }
+ 
+@@ -257,7 +257,7 @@ static const struct v4l2_subdev_ops uds_ops = {
+ 
+ static void uds_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_uds *uds = to_uds(&entity->subdev);
+ 	const struct v4l2_mbus_framefmt *output;
+@@ -286,25 +286,26 @@ static void uds_configure_stream(struct vsp1_entity *entity,
+ 	else
+ 		multitap = true;
+ 
+-	vsp1_uds_write(uds, dl, VI6_UDS_CTRL,
++	vsp1_uds_write(uds, dlb, VI6_UDS_CTRL,
+ 		       (uds->scale_alpha ? VI6_UDS_CTRL_AON : 0) |
+ 		       (multitap ? VI6_UDS_CTRL_BC : 0));
+ 
+-	vsp1_uds_write(uds, dl, VI6_UDS_PASS_BWIDTH,
++	vsp1_uds_write(uds, dlb, VI6_UDS_PASS_BWIDTH,
+ 		       (uds_passband_width(hscale)
+ 				<< VI6_UDS_PASS_BWIDTH_H_SHIFT) |
+ 		       (uds_passband_width(vscale)
+ 				<< VI6_UDS_PASS_BWIDTH_V_SHIFT));
+ 
+ 	/* Set the scaling ratios. */
+-	vsp1_uds_write(uds, dl, VI6_UDS_SCALE,
++	vsp1_uds_write(uds, dlb, VI6_UDS_SCALE,
+ 		       (hscale << VI6_UDS_SCALE_HFRAC_SHIFT) |
+ 		       (vscale << VI6_UDS_SCALE_VFRAC_SHIFT));
+ }
+ 
+ static void uds_configure_partition(struct vsp1_entity *entity,
+ 				    struct vsp1_pipeline *pipe,
+-				    struct vsp1_dl_list *dl)
++				    struct vsp1_dl_list *dl,
++				    struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_uds *uds = to_uds(&entity->subdev);
+ 	struct vsp1_partition *partition = pipe->partition;
+@@ -314,13 +315,13 @@ static void uds_configure_partition(struct vsp1_entity *entity,
+ 					    UDS_PAD_SOURCE);
+ 
+ 	/* Input size clipping */
+-	vsp1_uds_write(uds, dl, VI6_UDS_HSZCLIP, VI6_UDS_HSZCLIP_HCEN |
++	vsp1_uds_write(uds, dlb, VI6_UDS_HSZCLIP, VI6_UDS_HSZCLIP_HCEN |
+ 		       (0 << VI6_UDS_HSZCLIP_HCL_OFST_SHIFT) |
+ 		       (partition->uds_sink.width
+ 				<< VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT));
+ 
+ 	/* Output size clipping */
+-	vsp1_uds_write(uds, dl, VI6_UDS_CLIP_SIZE,
++	vsp1_uds_write(uds, dlb, VI6_UDS_CLIP_SIZE,
+ 		       (partition->uds_source.width
+ 				<< VI6_UDS_CLIP_SIZE_HSIZE_SHIFT) |
+ 		       (output->height
+diff --git a/drivers/media/platform/vsp1/vsp1_uds.h b/drivers/media/platform/vsp1/vsp1_uds.h
+index 2cd9f4b95442..c34f95a666d2 100644
+--- a/drivers/media/platform/vsp1/vsp1_uds.h
++++ b/drivers/media/platform/vsp1/vsp1_uds.h
+@@ -31,7 +31,7 @@ static inline struct vsp1_uds *to_uds(struct v4l2_subdev *subdev)
+ 
+ struct vsp1_uds *vsp1_uds_create(struct vsp1_device *vsp1, unsigned int index);
+ 
+-void vsp1_uds_set_alpha(struct vsp1_entity *uds, struct vsp1_dl_list *dl,
++void vsp1_uds_set_alpha(struct vsp1_entity *uds, struct vsp1_dl_body *dlb,
+ 			unsigned int alpha);
+ 
+ #endif /* __VSP1_UDS_H__ */
+diff --git a/drivers/media/platform/vsp1/vsp1_uif.c b/drivers/media/platform/vsp1/vsp1_uif.c
+index c526e484b326..4b58d51df231 100644
+--- a/drivers/media/platform/vsp1/vsp1_uif.c
++++ b/drivers/media/platform/vsp1/vsp1_uif.c
+@@ -31,10 +31,11 @@ static inline u32 vsp1_uif_read(struct vsp1_uif *uif, u32 reg)
+ 	return vsp1_read(uif->entity.vsp1,
+ 			 uif->entity.index * VI6_UIF_OFFSET + reg);
+ }
+-static inline void vsp1_uif_write(struct vsp1_uif *uif, struct vsp1_dl_list *dl,
+-				  u32 reg, u32 data)
++
++static inline void vsp1_uif_write(struct vsp1_uif *uif,
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg + uif->entity.index * VI6_UIF_OFFSET, data);
++	vsp1_dl_body_write(dlb, reg + uif->entity.index * VI6_UIF_OFFSET, data);
+ }
+ 
+ u32 vsp1_uif_get_crc(struct vsp1_uif *uif)
+@@ -191,14 +192,14 @@ static const struct v4l2_subdev_ops uif_ops = {
+ 
+ static void uif_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_uif *uif = to_uif(&entity->subdev);
+ 	const struct v4l2_rect *crop;
+ 	unsigned int left;
+ 	unsigned int width;
+ 
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMPMR,
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMPMR,
+ 		       VI6_UIF_DISCOM_DOCMPMR_SEL(9));
+ 
+ 	crop = vsp1_entity_get_pad_selection(entity, entity->config,
+@@ -213,12 +214,12 @@ static void uif_configure_stream(struct vsp1_entity *entity,
+ 		width /= 2;
+ 	}
+ 
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSPXR, left);
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSPYR, crop->top);
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSZXR, width);
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMSZYR, crop->height);
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMSPXR, left);
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMSPYR, crop->top);
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMSZXR, width);
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMSZYR, crop->height);
+ 
+-	vsp1_uif_write(uif, dl, VI6_UIF_DISCOM_DOCMCR,
++	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMCR,
+ 		       VI6_UIF_DISCOM_DOCMCR_CMPR);
+ }
+ 
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index c457d0626588..c46291ff9e6b 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -378,25 +378,29 @@ static void vsp1_video_pipeline_run_partition(struct vsp1_pipeline *pipe,
+ 					      struct vsp1_dl_list *dl,
+ 					      unsigned int partition)
+ {
++	struct vsp1_dl_body *dlb = vsp1_dl_list_get_body0(dl);
+ 	struct vsp1_entity *entity;
+ 
+ 	pipe->partition = &pipe->part_table[partition];
+ 
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe)
+-		vsp1_entity_configure_partition(entity, pipe, dl);
++		vsp1_entity_configure_partition(entity, pipe, dl, dlb);
+ }
+ 
+ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
+ 	struct vsp1_entity *entity;
++	struct vsp1_dl_body *dlb;
+ 	unsigned int partition;
+ 
+ 	if (!pipe->dl)
+ 		pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
+ 
++	dlb = vsp1_dl_list_get_body0(pipe->dl);
++
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe)
+-		vsp1_entity_configure_frame(entity, pipe, pipe->dl);
++		vsp1_entity_configure_frame(entity, pipe, pipe->dl, dlb);
+ 
+ 	/* Run the first partition. */
+ 	vsp1_video_pipeline_run_partition(pipe, pipe->dl, 0);
+@@ -787,6 +791,7 @@ static void vsp1_video_buffer_queue(struct vb2_buffer *vb)
+ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_entity *entity;
++	struct vsp1_dl_body *dlb;
+ 	int ret;
+ 
+ 	/* Determine this pipelines sizes for image partitioning support. */
+@@ -799,6 +804,9 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ 	if (!pipe->dl)
+ 		return -ENOMEM;
+ 
++	/* Retrieve the default DLB from the list. */
++	dlb = vsp1_dl_list_get_body0(pipe->dl);
++
+ 	if (pipe->uds) {
+ 		struct vsp1_uds *uds = to_uds(&pipe->uds->subdev);
+ 
+@@ -821,8 +829,8 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ 	}
+ 
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe) {
+-		vsp1_entity_route_setup(entity, pipe, pipe->dl);
+-		vsp1_entity_configure_stream(entity, pipe, pipe->dl);
++		vsp1_entity_route_setup(entity, pipe, dlb);
++		vsp1_entity_configure_stream(entity, pipe, dlb);
+ 	}
+ 
+ 	return 0;
+diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c
+index 8662c5d2fc64..23c8f706b3f2 100644
+--- a/drivers/media/platform/vsp1/vsp1_wpf.c
++++ b/drivers/media/platform/vsp1/vsp1_wpf.c
+@@ -27,9 +27,9 @@
+  */
+ 
+ static inline void vsp1_wpf_write(struct vsp1_rwpf *wpf,
+-				  struct vsp1_dl_list *dl, u32 reg, u32 data)
++				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
+ {
+-	vsp1_dl_list_write(dl, reg + wpf->entity.index * VI6_WPF_OFFSET, data);
++	vsp1_dl_body_write(dlb, reg + wpf->entity.index * VI6_WPF_OFFSET, data);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -234,7 +234,7 @@ static void vsp1_wpf_destroy(struct vsp1_entity *entity)
+ 
+ static void wpf_configure_stream(struct vsp1_entity *entity,
+ 				 struct vsp1_pipeline *pipe,
+-				 struct vsp1_dl_list *dl)
++				 struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev);
+ 	struct vsp1_device *vsp1 = wpf->entity.vsp1;
+@@ -268,17 +268,17 @@ static void wpf_configure_stream(struct vsp1_entity *entity,
+ 			outfmt |= VI6_WPF_OUTFMT_SPUVS;
+ 
+ 		/* Destination stride and byte swapping. */
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_STRIDE_Y,
++		vsp1_wpf_write(wpf, dlb, VI6_WPF_DSTM_STRIDE_Y,
+ 			       format->plane_fmt[0].bytesperline);
+ 		if (format->num_planes > 1)
+-			vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_STRIDE_C,
++			vsp1_wpf_write(wpf, dlb, VI6_WPF_DSTM_STRIDE_C,
+ 				       format->plane_fmt[1].bytesperline);
+ 
+-		vsp1_wpf_write(wpf, dl, VI6_WPF_DSWAP, fmtinfo->swap);
++		vsp1_wpf_write(wpf, dlb, VI6_WPF_DSWAP, fmtinfo->swap);
+ 
+ 		if (vsp1->info->features & VSP1_HAS_WPF_HFLIP &&
+ 		    wpf->entity.index == 0)
+-			vsp1_wpf_write(wpf, dl, VI6_WPF_ROT_CTRL,
++			vsp1_wpf_write(wpf, dlb, VI6_WPF_ROT_CTRL,
+ 				       VI6_WPF_ROT_CTRL_LN16 |
+ 				       (256 << VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT));
+ 	}
+@@ -288,10 +288,10 @@ static void wpf_configure_stream(struct vsp1_entity *entity,
+ 
+ 	wpf->outfmt = outfmt;
+ 
+-	vsp1_dl_list_write(dl, VI6_DPR_WPF_FPORCH(wpf->entity.index),
++	vsp1_dl_body_write(dlb, VI6_DPR_WPF_FPORCH(wpf->entity.index),
+ 			   VI6_DPR_WPF_FPORCH_FP_WPFN);
+ 
+-	vsp1_dl_list_write(dl, VI6_WPF_WRBCK_CTRL, 0);
++	vsp1_dl_body_write(dlb, VI6_WPF_WRBCK_CTRL, 0);
+ 
+ 	/*
+ 	 * Sources. If the pipeline has a single input and BRx is not used,
+@@ -315,17 +315,18 @@ static void wpf_configure_stream(struct vsp1_entity *entity,
+ 			? VI6_WPF_SRCRPF_VIRACT_MST
+ 			: VI6_WPF_SRCRPF_VIRACT2_MST;
+ 
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_SRCRPF, srcrpf);
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_SRCRPF, srcrpf);
+ 
+ 	/* Enable interrupts */
+-	vsp1_dl_list_write(dl, VI6_WPF_IRQ_STA(wpf->entity.index), 0);
+-	vsp1_dl_list_write(dl, VI6_WPF_IRQ_ENB(wpf->entity.index),
++	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_STA(wpf->entity.index), 0);
++	vsp1_dl_body_write(dlb, VI6_WPF_IRQ_ENB(wpf->entity.index),
+ 			   VI6_WFP_IRQ_ENB_DFEE);
+ }
+ 
+ static void wpf_configure_frame(struct vsp1_entity *entity,
+ 				struct vsp1_pipeline *pipe,
+-				struct vsp1_dl_list *dl)
++				struct vsp1_dl_list *dl,
++				struct vsp1_dl_body *dlb)
+ {
+ 	const unsigned int mask = BIT(WPF_CTRL_VFLIP)
+ 				| BIT(WPF_CTRL_HFLIP);
+@@ -345,12 +346,13 @@ static void wpf_configure_frame(struct vsp1_entity *entity,
+ 	if (wpf->flip.active & BIT(WPF_CTRL_HFLIP))
+ 		outfmt |= VI6_WPF_OUTFMT_HFLP;
+ 
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_OUTFMT, outfmt);
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_OUTFMT, outfmt);
+ }
+ 
+ static void wpf_configure_partition(struct vsp1_entity *entity,
+ 				    struct vsp1_pipeline *pipe,
+-				    struct vsp1_dl_list *dl)
++				    struct vsp1_dl_list *dl,
++				    struct vsp1_dl_body *dlb)
+ {
+ 	struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev);
+ 	struct vsp1_device *vsp1 = wpf->entity.vsp1;
+@@ -377,10 +379,10 @@ static void wpf_configure_partition(struct vsp1_entity *entity,
+ 	if (pipe->partitions > 1)
+ 		width = pipe->partition->wpf.width;
+ 
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_HSZCLIP, VI6_WPF_SZCLIP_EN |
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_HSZCLIP, VI6_WPF_SZCLIP_EN |
+ 		       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
+ 		       (width << VI6_WPF_SZCLIP_SIZE_SHIFT));
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_VSZCLIP, VI6_WPF_SZCLIP_EN |
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_VSZCLIP, VI6_WPF_SZCLIP_EN |
+ 		       (0 << VI6_WPF_SZCLIP_OFST_SHIFT) |
+ 		       (height << VI6_WPF_SZCLIP_SIZE_SHIFT));
+ 
+@@ -472,9 +474,9 @@ static void wpf_configure_partition(struct vsp1_entity *entity,
+ 	    fmtinfo->swap_uv)
+ 		swap(mem.addr[1], mem.addr[2]);
+ 
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_Y, mem.addr[0]);
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C0, mem.addr[1]);
+-	vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C1, mem.addr[2]);
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_DSTM_ADDR_Y, mem.addr[0]);
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_DSTM_ADDR_C0, mem.addr[1]);
++	vsp1_wpf_write(wpf, dlb, VI6_WPF_DSTM_ADDR_C1, mem.addr[2]);
+ }
+ 
+ static unsigned int wpf_max_width(struct vsp1_entity *entity,
+-- 
+2.19.0
+
diff --git a/patches/1201-media-vsp1-Move-video-configuration-to-a-cached-dlb.patch b/patches/1201-media-vsp1-Move-video-configuration-to-a-cached-dlb.patch
new file mode 100644
index 00000000000000..c4231c3a3fe7c6
--- /dev/null
+++ b/patches/1201-media-vsp1-Move-video-configuration-to-a-cached-dlb.patch
@@ -0,0 +1,293 @@
+From f719c2ec9a79a9e54a3d7ffaf22d08857f27e219 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 18 May 2018 16:42:03 -0400
+Subject: [PATCH 1201/1795] media: vsp1: Move video configuration to a cached
+ dlb
+
+We are now able to configure a pipeline directly into a local display
+list body. Take advantage of this fact, and create a cacheable body to
+store the configuration of the pipeline in the pipeline object.
+
+vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
+Convert this function to use the cached pipe->stream_config body and
+obtain a local display list reference.
+
+Attach the pipe->stream_config body to the display list when needed
+before committing to hardware.
+
+Use a flag 'configured' to know when we should attach our stream_config
+to the next outgoing display list to reconfigure the hardware in the
+event of our first frame, or the first frame following a suspend/resume
+cycle.
+
+Our video DL usage now looks like the below output:
+
+dl->body0 contains our disposable runtime configuration. Max 41.
+dl_child->body0 is our partition specific configuration. Max 12.
+dl->bodies shows our constant configuration and LUTs.
+
+  These two are LUT/CLU:
+     * dl->bodies[x]->num_entries 256 / max 256
+     * dl->bodies[x]->num_entries 4914 / max 4914
+
+Which shows that our 'constant' configuration cache is currently
+utilised to a maximum of 64 entries.
+
+trace-cmd report | \
+
+  dl->body0->num_entries 13 / max 128
+  dl->body0->num_entries 14 / max 128
+  dl->body0->num_entries 16 / max 128
+  dl->body0->num_entries 20 / max 128
+  dl->body0->num_entries 27 / max 128
+  dl->body0->num_entries 34 / max 128
+  dl->body0->num_entries 41 / max 128
+  dl_child->body0->num_entries 10 / max 128
+  dl_child->body0->num_entries 12 / max 128
+  dl->bodies[x]->num_entries 15 / max 128
+  dl->bodies[x]->num_entries 16 / max 128
+  dl->bodies[x]->num_entries 17 / max 128
+  dl->bodies[x]->num_entries 18 / max 128
+  dl->bodies[x]->num_entries 20 / max 128
+  dl->bodies[x]->num_entries 21 / max 128
+  dl->bodies[x]->num_entries 256 / max 256
+  dl->bodies[x]->num_entries 31 / max 128
+  dl->bodies[x]->num_entries 32 / max 128
+  dl->bodies[x]->num_entries 39 / max 128
+  dl->bodies[x]->num_entries 40 / max 128
+  dl->bodies[x]->num_entries 47 / max 128
+  dl->bodies[x]->num_entries 48 / max 128
+  dl->bodies[x]->num_entries 4914 / max 4914
+  dl->bodies[x]->num_entries 55 / max 128
+  dl->bodies[x]->num_entries 56 / max 128
+  dl->bodies[x]->num_entries 63 / max 128
+  dl->bodies[x]->num_entries 64 / max 128
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit e646e17713eeb3b6484b6d7a24ce34854123fa39)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_dl.c    | 10 +++-
+ drivers/media/platform/vsp1/vsp1_dl.h    |  1 +
+ drivers/media/platform/vsp1/vsp1_pipe.h  |  6 ++-
+ drivers/media/platform/vsp1/vsp1_video.c | 69 +++++++++++++++---------
+ 4 files changed, 56 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c
+index c7fa1cb088cd..d9b9cdd8fbe2 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.c
++++ b/drivers/media/platform/vsp1/vsp1_dl.c
+@@ -813,6 +813,11 @@ void vsp1_dlm_reset(struct vsp1_dl_manager *dlm)
+ 	dlm->pending = NULL;
+ }
+ 
++struct vsp1_dl_body *vsp1_dlm_dl_body_get(struct vsp1_dl_manager *dlm)
++{
++	return vsp1_dl_body_get(dlm->pool);
++}
++
+ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 					unsigned int index,
+ 					unsigned int prealloc)
+@@ -838,13 +843,14 @@ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ 	 * Initialize the display list body and allocate DMA memory for the body
+ 	 * and the optional header. Both are allocated together to avoid memory
+ 	 * fragmentation, with the header located right after the body in
+-	 * memory.
++	 * memory. An extra body is allocated on top of the prealloc to account
++	 * for the cached body used by the vsp1_pipeline object.
+ 	 */
+ 	header_size = dlm->mode == VSP1_DL_MODE_HEADER
+ 		    ? ALIGN(sizeof(struct vsp1_dl_header), 8)
+ 		    : 0;
+ 
+-	dlm->pool = vsp1_dl_body_pool_create(vsp1, prealloc,
++	dlm->pool = vsp1_dl_body_pool_create(vsp1, prealloc + 1,
+ 					     VSP1_DL_NUM_ENTRIES, header_size);
+ 	if (!dlm->pool)
+ 		return NULL;
+diff --git a/drivers/media/platform/vsp1/vsp1_dl.h b/drivers/media/platform/vsp1/vsp1_dl.h
+index 216bd23029dd..7dba0469c92e 100644
+--- a/drivers/media/platform/vsp1/vsp1_dl.h
++++ b/drivers/media/platform/vsp1/vsp1_dl.h
+@@ -28,6 +28,7 @@ struct vsp1_dl_manager *vsp1_dlm_create(struct vsp1_device *vsp1,
+ void vsp1_dlm_destroy(struct vsp1_dl_manager *dlm);
+ void vsp1_dlm_reset(struct vsp1_dl_manager *dlm);
+ unsigned int vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
++struct vsp1_dl_body *vsp1_dlm_dl_body_get(struct vsp1_dl_manager *dlm);
+ 
+ struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm);
+ void vsp1_dl_list_put(struct vsp1_dl_list *dl);
+diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h
+index f1155d20fa2d..743d8f0db45c 100644
+--- a/drivers/media/platform/vsp1/vsp1_pipe.h
++++ b/drivers/media/platform/vsp1/vsp1_pipe.h
+@@ -102,7 +102,8 @@ struct vsp1_partition {
+  * @uds: UDS entity, if present
+  * @uds_input: entity at the input of the UDS, if the UDS is present
+  * @entities: list of entities in the pipeline
+- * @dl: display list associated with the pipeline
++ * @stream_config: cached stream configuration for video pipelines
++ * @configured: when false the @stream_config shall be written to the hardware
+  * @partitions: The number of partitions used to process one frame
+  * @partition: The current partition for configuration to process
+  * @part_table: The pre-calculated partitions used by the pipeline
+@@ -139,7 +140,8 @@ struct vsp1_pipeline {
+ 	 */
+ 	struct list_head entities;
+ 
+-	struct vsp1_dl_list *dl;
++	struct vsp1_dl_body *stream_config;
++	bool configured;
+ 
+ 	unsigned int partitions;
+ 	struct vsp1_partition *partition;
+diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
+index c46291ff9e6b..81d47a09d7bc 100644
+--- a/drivers/media/platform/vsp1/vsp1_video.c
++++ b/drivers/media/platform/vsp1/vsp1_video.c
+@@ -392,42 +392,51 @@ static void vsp1_video_pipeline_run(struct vsp1_pipeline *pipe)
+ 	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
+ 	struct vsp1_entity *entity;
+ 	struct vsp1_dl_body *dlb;
++	struct vsp1_dl_list *dl;
+ 	unsigned int partition;
+ 
+-	if (!pipe->dl)
+-		pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
++	dl = vsp1_dl_list_get(pipe->output->dlm);
+ 
+-	dlb = vsp1_dl_list_get_body0(pipe->dl);
++	/*
++	 * If the VSP hardware isn't configured yet (which occurs either when
++	 * processing the first frame or after a system suspend/resume), add the
++	 * cached stream configuration to the display list to perform a full
++	 * initialisation.
++	 */
++	if (!pipe->configured)
++		vsp1_dl_list_add_body(dl, pipe->stream_config);
++
++	dlb = vsp1_dl_list_get_body0(dl);
+ 
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe)
+-		vsp1_entity_configure_frame(entity, pipe, pipe->dl, dlb);
++		vsp1_entity_configure_frame(entity, pipe, dl, dlb);
+ 
+ 	/* Run the first partition. */
+-	vsp1_video_pipeline_run_partition(pipe, pipe->dl, 0);
++	vsp1_video_pipeline_run_partition(pipe, dl, 0);
+ 
+ 	/* Process consecutive partitions as necessary. */
+ 	for (partition = 1; partition < pipe->partitions; ++partition) {
+-		struct vsp1_dl_list *dl;
++		struct vsp1_dl_list *dl_next;
+ 
+-		dl = vsp1_dl_list_get(pipe->output->dlm);
++		dl_next = vsp1_dl_list_get(pipe->output->dlm);
+ 
+ 		/*
+ 		 * An incomplete chain will still function, but output only
+ 		 * the partitions that had a dl available. The frame end
+ 		 * interrupt will be marked on the last dl in the chain.
+ 		 */
+-		if (!dl) {
++		if (!dl_next) {
+ 			dev_err(vsp1->dev, "Failed to obtain a dl list. Frame will be incomplete\n");
+ 			break;
+ 		}
+ 
+-		vsp1_video_pipeline_run_partition(pipe, dl, partition);
+-		vsp1_dl_list_add_chain(pipe->dl, dl);
++		vsp1_video_pipeline_run_partition(pipe, dl_next, partition);
++		vsp1_dl_list_add_chain(dl, dl_next);
+ 	}
+ 
+ 	/* Complete, and commit the head display list. */
+-	vsp1_dl_list_commit(pipe->dl, false);
+-	pipe->dl = NULL;
++	vsp1_dl_list_commit(dl, false);
++	pipe->configured = true;
+ 
+ 	vsp1_pipeline_run(pipe);
+ }
+@@ -791,7 +800,6 @@ static void vsp1_video_buffer_queue(struct vb2_buffer *vb)
+ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ {
+ 	struct vsp1_entity *entity;
+-	struct vsp1_dl_body *dlb;
+ 	int ret;
+ 
+ 	/* Determine this pipelines sizes for image partitioning support. */
+@@ -799,14 +807,6 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	/* Prepare the display list. */
+-	pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
+-	if (!pipe->dl)
+-		return -ENOMEM;
+-
+-	/* Retrieve the default DLB from the list. */
+-	dlb = vsp1_dl_list_get_body0(pipe->dl);
+-
+ 	if (pipe->uds) {
+ 		struct vsp1_uds *uds = to_uds(&pipe->uds->subdev);
+ 
+@@ -828,9 +828,18 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe)
+ 		}
+ 	}
+ 
++	/*
++	 * Compute and cache the stream configuration into a body. The cached
++	 * body will be added to the display list by vsp1_video_pipeline_run()
++	 * whenever the pipeline needs to be fully reconfigured.
++	 */
++	pipe->stream_config = vsp1_dlm_dl_body_get(pipe->output->dlm);
++	if (!pipe->stream_config)
++		return -ENOMEM;
++
+ 	list_for_each_entry(entity, &pipe->entities, list_pipe) {
+-		vsp1_entity_route_setup(entity, pipe, dlb);
+-		vsp1_entity_configure_stream(entity, pipe, dlb);
++		vsp1_entity_route_setup(entity, pipe, pipe->stream_config);
++		vsp1_entity_configure_stream(entity, pipe, pipe->stream_config);
+ 	}
+ 
+ 	return 0;
+@@ -853,12 +862,14 @@ static void vsp1_video_cleanup_pipeline(struct vsp1_pipeline *pipe)
+ {
+ 	lockdep_assert_held(&pipe->lock);
+ 
++	/* Release any cached configuration from our output video. */
++	vsp1_dl_body_put(pipe->stream_config);
++	pipe->stream_config = NULL;
++	pipe->configured = false;
++
+ 	/* Release our partition table allocation */
+ 	kfree(pipe->part_table);
+ 	pipe->part_table = NULL;
+-
+-	vsp1_dl_list_put(pipe->dl);
+-	pipe->dl = NULL;
+ }
+ 
+ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count)
+@@ -1232,6 +1243,12 @@ void vsp1_video_resume(struct vsp1_device *vsp1)
+ 		if (pipe == NULL)
+ 			continue;
+ 
++		/*
++		 * The hardware may have been reset during a suspend and will
++		 * need a full reconfiguration.
++		 */
++		pipe->configured = false;
++
+ 		spin_lock_irqsave(&pipe->irqlock, flags);
+ 		if (vsp1_pipeline_ready(pipe))
+ 			vsp1_video_pipeline_run(pipe);
+-- 
+2.19.0
+
diff --git a/patches/1202-dt-bindings-thermal-rcar-gen3-thermal-update-registe.patch b/patches/1202-dt-bindings-thermal-rcar-gen3-thermal-update-registe.patch
new file mode 100644
index 00000000000000..8fd6a39475ca2c
--- /dev/null
+++ b/patches/1202-dt-bindings-thermal-rcar-gen3-thermal-update-registe.patch
@@ -0,0 +1,48 @@
+From 62434918b5f0a3ff463c2ed3b6ed84510da85bbf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 17 Apr 2018 22:49:58 +0200
+Subject: [PATCH 1202/1795] dt-bindings: thermal: rcar-gen3-thermal: update
+ register size in example
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The datasheet has been expanded with more registers and the DT files
+have been updated with the new size. This change updates the example so
+writing new DT files can use the enhanced driver which uses the new
+registers.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+[robh: s/have/has/, s/enchanted/enhanced/]
+Signed-off-by: Rob Herring <robh@kernel.org>
+
+(cherry picked from commit 2564fd43f6b24a3fc593c58a714461076943c276)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/thermal/rcar-gen3-thermal.txt       | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+index fdf5caa6229b..39e7d4e61a63 100644
+--- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
++++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+@@ -27,9 +27,9 @@ Example:
+ 
+ 	tsc: thermal@e6198000 {
+ 		compatible = "renesas,r8a7795-thermal";
+-		reg = <0 0xe6198000 0 0x68>,
+-		      <0 0xe61a0000 0 0x5c>,
+-		      <0 0xe61a8000 0 0x5c>;
++		reg = <0 0xe6198000 0 0x100>,
++		      <0 0xe61a0000 0 0x100>,
++		      <0 0xe61a8000 0 0x100>;
+ 		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.19.0
+
diff --git a/patches/1203-thermal-rcar_gen3_thermal-Update-calculation-formula.patch b/patches/1203-thermal-rcar_gen3_thermal-Update-calculation-formula.patch
new file mode 100644
index 00000000000000..ad3e1006f272ce
--- /dev/null
+++ b/patches/1203-thermal-rcar_gen3_thermal-Update-calculation-formula.patch
@@ -0,0 +1,66 @@
+From b77be6c3a09b7275d3c100b2c8cc3590ce4da494 Mon Sep 17 00:00:00 2001
+From: Hien Dang <hien.dang.eb@renesas.com>
+Date: Tue, 17 Apr 2018 22:57:46 +0200
+Subject: [PATCH 1203/1795] thermal: rcar_gen3_thermal: Update calculation
+ formula due to HW evaluation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Due to hardware evaluation result,
+Max temperature is changed from 96 to 116 degree Celsius.
+Also, calculation formula and pseudo FUSE values are changed accordingly.
+
+Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
+Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit fc66ddff3840232ed102250551d7b6031a49ff17)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_gen3_thermal.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index 561a0a332208..79c2cdb4105f 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -132,7 +132,7 @@ static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc,
+ #define RCAR3_THERMAL_GRAN 500 /* mili Celsius */
+ 
+ /* no idea where these constants come from */
+-#define TJ_1 96
++#define TJ_1 116
+ #define TJ_3 -41
+ 
+ static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
+@@ -146,7 +146,7 @@ static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
+ 	 * Division is not scaled in BSP and if scaled it might overflow
+ 	 * the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled
+ 	 */
+-	tj_2 = (FIXPT_INT((ptat[1] - ptat[2]) * 137)
++	tj_2 = (FIXPT_INT((ptat[1] - ptat[2]) * 157)
+ 		/ (ptat[0] - ptat[2])) - FIXPT_INT(41);
+ 
+ 	coef->a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]),
+@@ -354,11 +354,11 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
+ 
+ 	/* default values if FUSEs are missing */
+ 	/* TODO: Read values from hardware on supported platforms */
+-	int ptat[3] = { 2351, 1509, 435 };
++	int ptat[3] = { 2631, 1509, 435 };
+ 	int thcode[TSC_MAX_NUM][3] = {
+-		{ 3248, 2800, 2221 },
+-		{ 3245, 2795, 2216 },
+-		{ 3250, 2805, 2237 },
++		{ 3397, 2800, 2221 },
++		{ 3393, 2795, 2216 },
++		{ 3389, 2805, 2237 },
+ 	};
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+-- 
+2.19.0
+
diff --git a/patches/1204-thermal-rcar_gen3_thermal-update-max-temperature-cla.patch b/patches/1204-thermal-rcar_gen3_thermal-update-max-temperature-cla.patch
new file mode 100644
index 00000000000000..c11f8536db40da
--- /dev/null
+++ b/patches/1204-thermal-rcar_gen3_thermal-update-max-temperature-cla.patch
@@ -0,0 +1,41 @@
+From 9c318ca6186af149ae39a1b2f06f76dfbcf70c6c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 17 Apr 2018 22:57:47 +0200
+Subject: [PATCH 1204/1795] thermal: rcar_gen3_thermal: update max temperature
+ clamp
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Change the upper limit to clamp the high temperature value to 120C when
+setting trip points.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 270ba432003f4cdaf136f1dc736b9fe6dc9d5537)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_gen3_thermal.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index 79c2cdb4105f..3905ec8b2689 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -207,8 +207,8 @@ static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high)
+ {
+ 	struct rcar_gen3_thermal_tsc *tsc = devdata;
+ 
+-	low = clamp_val(low, -40000, 125000);
+-	high = clamp_val(high, -40000, 125000);
++	low = clamp_val(low, -40000, 120000);
++	high = clamp_val(high, -40000, 120000);
+ 
+ 	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1,
+ 				rcar_gen3_thermal_mcelsius_to_temp(tsc, low));
+-- 
+2.19.0
+
diff --git a/patches/1205-dt-bindings-thermal-rcar-gen3-thermal-add-r8a77965.patch b/patches/1205-dt-bindings-thermal-rcar-gen3-thermal-add-r8a77965.patch
new file mode 100644
index 00000000000000..83fcdad09e843f
--- /dev/null
+++ b/patches/1205-dt-bindings-thermal-rcar-gen3-thermal-add-r8a77965.patch
@@ -0,0 +1,48 @@
+From 239d068a5af3d4f2d7fc3320d902cad71e60e64f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 26 Apr 2018 21:42:01 +0200
+Subject: [PATCH 1205/1795] dt-bindings: thermal: rcar-gen3-thermal: add
+ r8a77965
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Based on previous work by Ryo Kataoka <ryo.kataoka.wt@renesas.com>.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 0706cb152daf56b8bc39965b108b0ff48f0c1c4a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/thermal/rcar-gen3-thermal.txt          | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+index 39e7d4e61a63..cfa154bb0fa7 100644
+--- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
++++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+@@ -9,6 +9,7 @@ Required properties:
+ 			  Examples with soctypes are:
+ 			    - "renesas,r8a7795-thermal" (R-Car H3)
+ 			    - "renesas,r8a7796-thermal" (R-Car M3-W)
++			    - "renesas,r8a77965-thermal" (R-Car M3-N)
+ - reg			: Address ranges of the thermal registers. Each sensor
+ 			  needs one address range. Sorting must be done in
+ 			  increasing order according to datasheet, i.e.
+@@ -18,7 +19,7 @@ Required properties:
+ 
+ Optional properties:
+ 
+-- interrupts           : interrupts routed to the TSC (3 for H3 and M3-W)
++- interrupts           : interrupts routed to the TSC (3 for H3, M3-W and M3-N)
+ - power-domain		: Must contain a reference to the power domain. This
+ 			  property is mandatory if the thermal sensor instance
+ 			  is part of a controllable power domain.
+-- 
+2.19.0
+
diff --git a/patches/1206-thermal-rcar_gen3_thermal-add-r8a77965-support.patch b/patches/1206-thermal-rcar_gen3_thermal-add-r8a77965-support.patch
new file mode 100644
index 00000000000000..2c6bd2a6c4f20a
--- /dev/null
+++ b/patches/1206-thermal-rcar_gen3_thermal-add-r8a77965-support.patch
@@ -0,0 +1,35 @@
+From 064d9d1137eb1f5d3b9825da81b9e285e33b2b12 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 26 Apr 2018 21:42:02 +0200
+Subject: [PATCH 1206/1795] thermal: rcar_gen3_thermal: add r8a77965 support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 2e7db3eceb41416ac9633ea58c28760b3c01cfcc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_gen3_thermal.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index 3905ec8b2689..766521eb7071 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -329,6 +329,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
+ static const struct of_device_id rcar_gen3_thermal_dt_ids[] = {
+ 	{ .compatible = "renesas,r8a7795-thermal", },
+ 	{ .compatible = "renesas,r8a7796-thermal", },
++	{ .compatible = "renesas,r8a77965-thermal", },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids);
+-- 
+2.19.0
+
diff --git a/patches/1207-soc-renesas-rcar-rst-Add-support-for-RZ-G1C.patch b/patches/1207-soc-renesas-rcar-rst-Add-support-for-RZ-G1C.patch
new file mode 100644
index 00000000000000..2aae50e6243864
--- /dev/null
+++ b/patches/1207-soc-renesas-rcar-rst-Add-support-for-RZ-G1C.patch
@@ -0,0 +1,44 @@
+From 7b2840b2069e973b95dbcd87ef03ab44ec2ce0d3 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 27 Mar 2018 15:37:14 +0100
+Subject: [PATCH 1207/1795] soc: renesas: rcar-rst: Add support for RZ/G1C
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a3a9033f1193842c6e0b518db196ade0f882cf78)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
+ drivers/soc/renesas/rcar-rst.c                          | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+index 294a0dae106a..7be61efc3c8a 100644
+--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
++++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+@@ -17,6 +17,7 @@ Required properties:
+ 		Examples with soctypes are:
+ 		  - "renesas,r8a7743-rst" (RZ/G1M)
+ 		  - "renesas,r8a7745-rst" (RZ/G1E)
++		  - "renesas,r8a77470-rst" (RZ/G1C)
+ 		  - "renesas,r8a7778-reset-wdt" (R-Car M1A)
+ 		  - "renesas,r8a7779-reset-wdt" (R-Car H1)
+ 		  - "renesas,r8a7790-rst" (R-Car H2)
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index 8e9cb7996ab0..66d7dbac2ded 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -44,6 +44,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	/* RZ/G is handled like R-Car Gen2 */
+ 	{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
++	{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
+ 	/* R-Car Gen1 */
+ 	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
+ 	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
+-- 
+2.19.0
+
diff --git a/patches/1208-soc-renesas-rcar-rst-Add-support-for-R-Car-E3.patch b/patches/1208-soc-renesas-rcar-rst-Add-support-for-R-Car-E3.patch
new file mode 100644
index 00000000000000..446d58f4955e4d
--- /dev/null
+++ b/patches/1208-soc-renesas-rcar-rst-Add-support-for-R-Car-E3.patch
@@ -0,0 +1,64 @@
+From dd5a25570b016135c2fcb56716d00010faa96237 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Wed, 11 Apr 2018 18:36:26 +0900
+Subject: [PATCH 1208/1795] soc: renesas: rcar-rst: Add support for R-Car E3
+
+Add support for R-Car E3 (R8A77990) to the R-Car RST driver.
+This driver is needed for the clock driver to work.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[shimoda: rebase]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit b0d77648e0cd910ff087853237502ff08dfdb352)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
+ drivers/soc/renesas/Kconfig                             | 3 ++-
+ drivers/soc/renesas/rcar-rst.c                          | 1 +
+ 3 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+index 7be61efc3c8a..67e83b02e10b 100644
+--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
++++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
+@@ -30,6 +30,7 @@ Required properties:
+ 		  - "renesas,r8a77965-rst" (R-Car M3-N)
+ 		  - "renesas,r8a77970-rst" (R-Car V3M)
+ 		  - "renesas,r8a77980-rst" (R-Car V3H)
++		  - "renesas,r8a77990-rst" (R-Car E3)
+ 		  - "renesas,r8a77995-rst" (R-Car D3)
+   - reg: Address start and address range for the device.
+ 
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index 3bbe6114a420..b747aa317647 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -4,7 +4,8 @@ config SOC_RENESAS
+ 	select SOC_BUS
+ 	select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
+ 			   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
+-			   ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77995
++			   ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \
++			   ARCH_R8A77995
+ 	select SYSC_R8A7743 if ARCH_R8A7743
+ 	select SYSC_R8A7745 if ARCH_R8A7745
+ 	select SYSC_R8A7779 if ARCH_R8A7779
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index 66d7dbac2ded..d9c1034e70e9 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -60,6 +60,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
+ 	{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
++	{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
+ 	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
+ 	{ /* sentinel */ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/1209-ASoC-rsnd-makes-rsnd_cmd_mod_get-static.patch b/patches/1209-ASoC-rsnd-makes-rsnd_cmd_mod_get-static.patch
new file mode 100644
index 00000000000000..db695a5c04b705
--- /dev/null
+++ b/patches/1209-ASoC-rsnd-makes-rsnd_cmd_mod_get-static.patch
@@ -0,0 +1,66 @@
+From 025c0716ecce1985e2f313f8d0c6ae4b3c19fd3f Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 6 Apr 2018 05:41:43 +0000
+Subject: [PATCH 1209/1795] ASoC: rsnd: makes rsnd_cmd_mod_get() static
+
+rsnd_cmd_mod_get() is used from cmd.c only.
+Let's makes it static function
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 9fff2d3980b8e319b270accb18bcf08ca80d836f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/cmd.c  | 15 +++++++--------
+ sound/soc/sh/rcar/rsnd.h |  1 -
+ 2 files changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/cmd.c b/sound/soc/sh/rcar/cmd.c
+index f1d4fb566892..4221937ae79b 100644
+--- a/sound/soc/sh/rcar/cmd.c
++++ b/sound/soc/sh/rcar/cmd.c
+@@ -125,6 +125,13 @@ static struct rsnd_mod_ops rsnd_cmd_ops = {
+ 	.stop	= rsnd_cmd_stop,
+ };
+ 
++static struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id)
++{
++	if (WARN_ON(id < 0 || id >= rsnd_cmd_nr(priv)))
++		id = 0;
++
++	return rsnd_mod_get((struct rsnd_cmd *)(priv->cmd) + id);
++}
+ int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id)
+ {
+ 	struct rsnd_priv *priv = rsnd_io_to_priv(io);
+@@ -133,14 +140,6 @@ int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id)
+ 	return rsnd_dai_connect(mod, io, mod->type);
+ }
+ 
+-struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id)
+-{
+-	if (WARN_ON(id < 0 || id >= rsnd_cmd_nr(priv)))
+-		id = 0;
+-
+-	return rsnd_mod_get((struct rsnd_cmd *)(priv->cmd) + id);
+-}
+-
+ int rsnd_cmd_probe(struct rsnd_priv *priv)
+ {
+ 	struct device *dev = rsnd_priv_to_dev(priv);
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index 172c8d612890..ab4d55548ed1 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -775,7 +775,6 @@ struct rsnd_mod *rsnd_dvc_mod_get(struct rsnd_priv *priv, int id);
+ int rsnd_cmd_probe(struct rsnd_priv *priv);
+ void rsnd_cmd_remove(struct rsnd_priv *priv);
+ int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id);
+-struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id);
+ 
+ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type);
+ #ifdef DEBUG
+-- 
+2.19.0
+
diff --git a/patches/1210-ASoC-rsnd-add-RSND_GEN3-for-R-Car-Gen3.patch b/patches/1210-ASoC-rsnd-add-RSND_GEN3-for-R-Car-Gen3.patch
new file mode 100644
index 00000000000000..4f20ee2132c1cc
--- /dev/null
+++ b/patches/1210-ASoC-rsnd-add-RSND_GEN3-for-R-Car-Gen3.patch
@@ -0,0 +1,98 @@
+From daa85cbe60f6a1b186e21200235f785e2ccce7f2 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 11 Apr 2018 02:10:29 +0000
+Subject: [PATCH 1210/1795] ASoC: rsnd: add RSND_GEN3 for R-Car Gen3
+
+rsnd driver is supporting Gen3. The difference between Gen1 and Gen2
+were very big, but, between Gen2 and Gen3 are not so much.
+Thus, it is assuming Gen2 and Gen3 have compatible, therefore,
+there is no RSND_GEN3 and rsnd_is_gen3() macro.
+But in the future, it will need Gen2 and Gen3 different operation,
+and for Gen4.
+This patch adds missing RSND_GEN3 and rsnd_is_gen3() macro.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit d188e140ad9723faccefa4ed5dc313cd467123c9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 2 +-
+ sound/soc/sh/rcar/dma.c  | 4 ++--
+ sound/soc/sh/rcar/gen.c  | 3 ++-
+ sound/soc/sh/rcar/rsnd.h | 2 ++
+ 4 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index be92c11a22bb..813dd673a7ae 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -111,7 +111,7 @@
+ static const struct of_device_id rsnd_of_match[] = {
+ 	{ .compatible = "renesas,rcar_sound-gen1", .data = (void *)RSND_GEN1 },
+ 	{ .compatible = "renesas,rcar_sound-gen2", .data = (void *)RSND_GEN2 },
+-	{ .compatible = "renesas,rcar_sound-gen3", .data = (void *)RSND_GEN2 }, /* gen2 compatible */
++	{ .compatible = "renesas,rcar_sound-gen3", .data = (void *)RSND_GEN3 },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rsnd_of_match);
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 41de23417c4a..32ac97be26f1 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -695,7 +695,7 @@ static int rsnd_dma_alloc(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
+ 
+ 	rsnd_dma_of_path(mod, io, is_play, &mod_from, &mod_to);
+ 
+-	/* for Gen2 */
++	/* for Gen2 or later */
+ 	if (mod_from && mod_to) {
+ 		ops	= &rsnd_dmapp_ops;
+ 		attach	= rsnd_dmapp_attach;
+@@ -773,7 +773,7 @@ int rsnd_dma_probe(struct rsnd_priv *priv)
+ 		return 0;
+ 
+ 	/*
+-	 * for Gen2
++	 * for Gen2 or later
+ 	 */
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audmapp");
+ 	dmac = devm_kzalloc(dev, sizeof(*dmac), GFP_KERNEL);
+diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c
+index f04c4100043a..25642e92dae0 100644
+--- a/sound/soc/sh/rcar/gen.c
++++ b/sound/soc/sh/rcar/gen.c
+@@ -414,7 +414,8 @@ int rsnd_gen_probe(struct rsnd_priv *priv)
+ 	ret = -ENODEV;
+ 	if (rsnd_is_gen1(priv))
+ 		ret = rsnd_gen1_probe(priv);
+-	else if (rsnd_is_gen2(priv))
++	else if (rsnd_is_gen2(priv) ||
++		 rsnd_is_gen3(priv))
+ 		ret = rsnd_gen2_probe(priv);
+ 
+ 	if (ret < 0)
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index ab4d55548ed1..b1896f1eb214 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -538,6 +538,7 @@ struct rsnd_priv {
+ #define RSND_GEN_MASK	(0xF << 0)
+ #define RSND_GEN1	(1 << 0)
+ #define RSND_GEN2	(2 << 0)
++#define RSND_GEN3	(3 << 0)
+ 
+ 	/*
+ 	 * below value will be filled on rsnd_gen_probe()
+@@ -609,6 +610,7 @@ struct rsnd_priv {
+ 
+ #define rsnd_is_gen1(priv)	(((priv)->flags & RSND_GEN_MASK) == RSND_GEN1)
+ #define rsnd_is_gen2(priv)	(((priv)->flags & RSND_GEN_MASK) == RSND_GEN2)
++#define rsnd_is_gen3(priv)	(((priv)->flags & RSND_GEN_MASK) == RSND_GEN3)
+ 
+ #define rsnd_flags_has(p, f) ((p)->flags & (f))
+ #define rsnd_flags_set(p, f) ((p)->flags |= (f))
+-- 
+2.19.0
+
diff --git a/patches/1211-ASoC-rsnd-don-t-assume-node-full-path-name-for-HDMI-.patch b/patches/1211-ASoC-rsnd-don-t-assume-node-full-path-name-for-HDMI-.patch
new file mode 100644
index 00000000000000..8d967044658226
--- /dev/null
+++ b/patches/1211-ASoC-rsnd-don-t-assume-node-full-path-name-for-HDMI-.patch
@@ -0,0 +1,69 @@
+From 14d0567b436105207b16dc8180edb0698bd34a35 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 11 Apr 2018 02:10:45 +0000
+Subject: [PATCH 1211/1795] ASoC: rsnd: don't assume node full path name for
+ HDMI probing
+
+Current ssi.c is assuming below 2 things to probing HDMI node.
+1) remote node is including "hdmi0" or "hdmi1" in node name
+2) remote_ep->full_name is including full path name
+
+But, these assumptions are broken by below
+1) Node names should not use numerical suffixes
+ commit 6b5ac2f1cb11 ("arm64: dts: renesas: r8a7795: Drop bogus HDMI
+                       node names suffixes")
+2) node full_name no longer include full path name
+ commit a7e4cfb0a7ca ("of/fdt: only store the device node basename
+                       in full_name")
+
+Because of these reasons, ssi.c can't probe HDMI on current kernel.
+This patch probes HDMI0/1 by using its address.
+Note is that we need to keep updating for this address for future
+generation chip.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 9ff7386656f5b7d9524ab7bdf69d508d14800d42)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index 333b802681ad..31ffe3f0e163 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -1004,19 +1004,26 @@ static void __rsnd_ssi_parse_hdmi_connection(struct rsnd_priv *priv,
+ 	struct device *dev = rsnd_priv_to_dev(priv);
+ 	struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
+ 	struct rsnd_ssi *ssi;
++	struct device_node *remote_node = of_graph_get_port_parent(remote_ep);
++
++	/* support Gen3 only */
++	if (!rsnd_is_gen3(priv))
++		return;
+ 
+ 	if (!mod)
+ 		return;
+ 
+ 	ssi  = rsnd_mod_to_ssi(mod);
+ 
+-	if (strstr(remote_ep->full_name, "hdmi0")) {
++	/* HDMI0 */
++	if (strstr(remote_node->full_name, "hdmi@fead0000")) {
+ 		rsnd_flags_set(ssi, RSND_SSI_HDMI0);
+ 		dev_dbg(dev, "%s[%d] connected to HDMI0\n",
+ 			 rsnd_mod_name(mod), rsnd_mod_id(mod));
+ 	}
+ 
+-	if (strstr(remote_ep->full_name, "hdmi1")) {
++	/* HDMI1 */
++	if (strstr(remote_node->full_name, "hdmi@feae0000")) {
+ 		rsnd_flags_set(ssi, RSND_SSI_HDMI1);
+ 		dev_dbg(dev, "%s[%d] connected to HDMI1\n",
+ 			rsnd_mod_name(mod), rsnd_mod_id(mod));
+-- 
+2.19.0
+
diff --git a/patches/1212-ASoC-rsnd-Enable-IPMMU-v2.patch b/patches/1212-ASoC-rsnd-Enable-IPMMU-v2.patch
new file mode 100644
index 00000000000000..9785760f056dbe
--- /dev/null
+++ b/patches/1212-ASoC-rsnd-Enable-IPMMU-v2.patch
@@ -0,0 +1,133 @@
+From 441ee8ae847f3e80b0b2fefc40cf44fe4a7ca77f Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 16 Apr 2018 05:14:01 +0000
+Subject: [PATCH 1212/1795] ASoC: rsnd: Enable IPMMU v2
+
+commit 4821d914fe747 ("ASoC: rsnd: use dma_sync_single_for_xxx() for
+IOMMU") (= v1) which have been already reverted had supported IPMMU
+support on rsnd driver.
+Because memory allocating timing and DMAEngine access timing were
+different, it used continuous memory and called dma map function by
+itself.
+
+OTOH, it is using DMA descriptor mode (= DMA cyclic mode), thus, there
+was timing conflict between DMA sync/unsync and DMA transfer starting,
+and it maked sound noise.
+
+This patch supports IPMMU with coherent memory, and, it uses Audio DMAC
+dev for allocating memory by snd_pcm_lib_preallocate_pages_for_all() to
+indicate memory area to IPMMU.
+One note is that Playback/Capture need each paired Audio DMAC dev.
+Because of this, we need to keep each paired Audio DMAC dev when probing,
+and use it when allocating each memory for IPMMU.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 5423d77253ac5bcb2d3de61cf0811c0f2a62c0af)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/core.c | 47 +++++++++++++++++++++++++++++++++++-----
+ sound/soc/sh/rcar/dma.c  |  7 ++++++
+ sound/soc/sh/rcar/rsnd.h |  1 +
+ 3 files changed, 50 insertions(+), 5 deletions(-)
+
+diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
+index 813dd673a7ae..2660d2566021 100644
+--- a/sound/soc/sh/rcar/core.c
++++ b/sound/soc/sh/rcar/core.c
+@@ -1352,6 +1352,37 @@ int rsnd_kctrl_new(struct rsnd_mod *mod,
+ #define PREALLOC_BUFFER		(32 * 1024)
+ #define PREALLOC_BUFFER_MAX	(32 * 1024)
+ 
++static int rsnd_preallocate_pages(struct snd_soc_pcm_runtime *rtd,
++				  struct rsnd_dai_stream *io,
++				  int stream)
++{
++	struct rsnd_priv *priv = rsnd_io_to_priv(io);
++	struct device *dev = rsnd_priv_to_dev(priv);
++	struct snd_pcm_substream *substream;
++	int err;
++
++	/*
++	 * use Audio-DMAC dev if we can use IPMMU
++	 * see
++	 *	rsnd_dmaen_attach()
++	 */
++	if (io->dmac_dev)
++		dev = io->dmac_dev;
++
++	for (substream = rtd->pcm->streams[stream].substream;
++	     substream;
++	     substream = substream->next) {
++		err = snd_pcm_lib_preallocate_pages(substream,
++					SNDRV_DMA_TYPE_DEV,
++					dev,
++					PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
++		if (err < 0)
++			return err;
++	}
++
++	return 0;
++}
++
+ static int rsnd_pcm_new(struct snd_soc_pcm_runtime *rtd)
+ {
+ 	struct snd_soc_dai *dai = rtd->cpu_dai;
+@@ -1366,11 +1397,17 @@ static int rsnd_pcm_new(struct snd_soc_pcm_runtime *rtd)
+ 	if (ret)
+ 		return ret;
+ 
+-	return snd_pcm_lib_preallocate_pages_for_all(
+-		rtd->pcm,
+-		SNDRV_DMA_TYPE_DEV,
+-		rtd->card->snd_card->dev,
+-		PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
++	ret = rsnd_preallocate_pages(rtd, &rdai->playback,
++				     SNDRV_PCM_STREAM_PLAYBACK);
++	if (ret)
++		return ret;
++
++	ret = rsnd_preallocate_pages(rtd, &rdai->capture,
++				     SNDRV_PCM_STREAM_CAPTURE);
++	if (ret)
++		return ret;
++
++	return 0;
+ }
+ 
+ static const struct snd_soc_platform_driver rsnd_soc_platform = {
+diff --git a/sound/soc/sh/rcar/dma.c b/sound/soc/sh/rcar/dma.c
+index 32ac97be26f1..ef82b94d038b 100644
+--- a/sound/soc/sh/rcar/dma.c
++++ b/sound/soc/sh/rcar/dma.c
+@@ -253,6 +253,13 @@ static int rsnd_dmaen_attach(struct rsnd_dai_stream *io,
+ 		return -EAGAIN;
+ 	}
+ 
++	/*
++	 * use it for IPMMU if needed
++	 * see
++	 *	rsnd_preallocate_pages()
++	 */
++	io->dmac_dev = chan->device->dev;
++
+ 	dma_release_channel(chan);
+ 
+ 	dmac->dmaen_num++;
+diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
+index b1896f1eb214..6d7280d2d9be 100644
+--- a/sound/soc/sh/rcar/rsnd.h
++++ b/sound/soc/sh/rcar/rsnd.h
+@@ -435,6 +435,7 @@ struct rsnd_dai_stream {
+ 	struct snd_pcm_substream *substream;
+ 	struct rsnd_mod *mod[RSND_MOD_MAX];
+ 	struct rsnd_dai *rdai;
++	struct device *dmac_dev; /* for IPMMU */
+ 	u32 parent_ssi_status;
+ };
+ #define rsnd_io_to_mod(io, i)	((i) < RSND_MOD_MAX ? (io)->mod[(i)] : NULL)
+-- 
+2.19.0
+
diff --git a/patches/1213-ASoC-rsnd-ssi-wait-maximum-5ms-for-status-check.patch b/patches/1213-ASoC-rsnd-ssi-wait-maximum-5ms-for-status-check.patch
new file mode 100644
index 00000000000000..840d71166defea
--- /dev/null
+++ b/patches/1213-ASoC-rsnd-ssi-wait-maximum-5ms-for-status-check.patch
@@ -0,0 +1,40 @@
+From 902382bb71d26a329d63635940555fa02073ad89 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 16 Apr 2018 00:38:13 +0000
+Subject: [PATCH 1213/1795] ASoC: rsnd: ssi: wait maximum 5ms for status check
+
+It is waiting udelay(50) x 1024 (= 50ms) for status check
+in worst case, but it is overkill.
+And we shouldn't use udelay() for 50us
+(linux/Documentation/timers/timers-howto.txt)
+
+Waiting maximum udelay(5) x 1024 (= 5ms) is very enough
+for status check.
+This patch fixes these issue.
+
+Reported-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 3fd391fb7c97ab6dfb9e44926a265566d1d1ab79)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ sound/soc/sh/rcar/ssi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c
+index 31ffe3f0e163..9538f76f8e20 100644
+--- a/sound/soc/sh/rcar/ssi.c
++++ b/sound/soc/sh/rcar/ssi.c
+@@ -171,7 +171,7 @@ static void rsnd_ssi_status_check(struct rsnd_mod *mod,
+ 		if (status & bit)
+ 			return;
+ 
+-		udelay(50);
++		udelay(5);
+ 	}
+ 
+ 	dev_warn(dev, "%s[%d] status check failed\n",
+-- 
+2.19.0
+
diff --git a/patches/1214-dt-bindings-thermal-rcar-thermal-add-R8A77995-suppor.patch b/patches/1214-dt-bindings-thermal-rcar-thermal-add-R8A77995-suppor.patch
new file mode 100644
index 00000000000000..02555dfad7cb05
--- /dev/null
+++ b/patches/1214-dt-bindings-thermal-rcar-thermal-add-R8A77995-suppor.patch
@@ -0,0 +1,54 @@
+From 57ef52599298e6d2cac24f7bb179e927f3fbac81 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Sun, 20 May 2018 18:26:18 +0900
+Subject: [PATCH 1214/1795] dt-bindings: thermal: rcar-thermal: add R8A77995
+ support
+
+Update rcar thermal dt-binding to  add R8A77995 info.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 31db453bd4bd2aaf5385fc2dbeab256cfc343fee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+index 349e635f2d87..67c563f1b4c4 100644
+--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
++++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+@@ -3,7 +3,8 @@
+ Required properties:
+ - compatible		: "renesas,thermal-<soctype>",
+ 			   "renesas,rcar-gen2-thermal" (with thermal-zone) or
+-			   "renesas,rcar-thermal" (without thermal-zone) as fallback.
++			   "renesas,rcar-thermal" (without thermal-zone) as
++                           fallback except R-Car D3.
+ 			  Examples with soctypes are:
+ 			    - "renesas,thermal-r8a73a4" (R-Mobile APE6)
+ 			    - "renesas,thermal-r8a7743" (RZ/G1M)
+@@ -12,13 +13,15 @@ Required properties:
+ 			    - "renesas,thermal-r8a7791" (R-Car M2-W)
+ 			    - "renesas,thermal-r8a7792" (R-Car V2H)
+ 			    - "renesas,thermal-r8a7793" (R-Car M2-N)
++			    - "renesas,thermal-r8a77995" (R-Car D3)
+ - reg			: Address range of the thermal registers.
+ 			  The 1st reg will be recognized as common register
+ 			  if it has "interrupts".
+ 
+ Option properties:
+ 
+-- interrupts		: use interrupt
++- interrupts		: If present should contain 3 interrupts for
++                          R-Car D3 or 1 interrupt otherwise.
+ 
+ Example (non interrupt support):
+ 
+-- 
+2.19.0
+
diff --git a/patches/1215-thermal-rcar_thermal-add-r8a77995-support.patch b/patches/1215-thermal-rcar_thermal-add-r8a77995-support.patch
new file mode 100644
index 00000000000000..1b5357f902fcfb
--- /dev/null
+++ b/patches/1215-thermal-rcar_thermal-add-r8a77995-support.patch
@@ -0,0 +1,273 @@
+From 3c591dfa8787941eaef26b81ae91e133dfe1335b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Sun, 20 May 2018 18:26:17 +0900
+Subject: [PATCH 1215/1795] thermal: rcar_thermal: add r8a77995 support
+
+Add support for R-Car D3 (r8a77995) thermal sensor.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 1969d9dc2079e4b551712e9f0c1c69403aee9769)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_thermal.c | 158 ++++++++++++++++++++++++++-------
+ 1 file changed, 126 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
+index 73e5fee6cf1d..45fb284d4c11 100644
+--- a/drivers/thermal/rcar_thermal.c
++++ b/drivers/thermal/rcar_thermal.c
+@@ -58,10 +58,47 @@ struct rcar_thermal_common {
+ 	spinlock_t lock;
+ };
+ 
++struct rcar_thermal_chip {
++	unsigned int use_of_thermal : 1;
++	unsigned int has_filonoff : 1;
++	unsigned int irq_per_ch : 1;
++	unsigned int needs_suspend_resume : 1;
++	unsigned int nirqs;
++};
++
++static const struct rcar_thermal_chip rcar_thermal = {
++	.use_of_thermal = 0,
++	.has_filonoff = 1,
++	.irq_per_ch = 0,
++	.needs_suspend_resume = 0,
++	.nirqs = 1,
++};
++
++static const struct rcar_thermal_chip rcar_gen2_thermal = {
++	.use_of_thermal = 1,
++	.has_filonoff = 1,
++	.irq_per_ch = 0,
++	.needs_suspend_resume = 0,
++	.nirqs = 1,
++};
++
++static const struct rcar_thermal_chip rcar_gen3_thermal = {
++	.use_of_thermal = 1,
++	.has_filonoff = 0,
++	.irq_per_ch = 1,
++	.needs_suspend_resume = 1,
++	/*
++	 * The Gen3 chip has 3 interrupts, but this driver uses only 2
++	 * interrupts to detect a temperature change, rise or fall.
++	 */
++	.nirqs = 2,
++};
++
+ struct rcar_thermal_priv {
+ 	void __iomem *base;
+ 	struct rcar_thermal_common *common;
+ 	struct thermal_zone_device *zone;
++	const struct rcar_thermal_chip *chip;
+ 	struct delayed_work work;
+ 	struct mutex lock;
+ 	struct list_head list;
+@@ -77,13 +114,20 @@ struct rcar_thermal_priv {
+ #define rcar_priv_to_dev(priv)		((priv)->common->dev)
+ #define rcar_has_irq_support(priv)	((priv)->common->base)
+ #define rcar_id_to_shift(priv)		((priv)->id * 8)
+-#define rcar_of_data(dev)		((unsigned long)of_device_get_match_data(dev))
+-#define rcar_use_of_thermal(dev)	(rcar_of_data(dev) == USE_OF_THERMAL)
+ 
+-#define USE_OF_THERMAL	1
+ static const struct of_device_id rcar_thermal_dt_ids[] = {
+-	{ .compatible = "renesas,rcar-thermal", },
+-	{ .compatible = "renesas,rcar-gen2-thermal", .data = (void *)USE_OF_THERMAL },
++	{
++		.compatible = "renesas,rcar-thermal",
++		.data = &rcar_thermal,
++	},
++	{
++		.compatible = "renesas,rcar-gen2-thermal",
++		 .data = &rcar_gen2_thermal,
++	},
++	{
++		.compatible = "renesas,thermal-r8a77995",
++		.data = &rcar_gen3_thermal,
++	},
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
+@@ -190,7 +234,8 @@ static int rcar_thermal_update_temp(struct rcar_thermal_priv *priv)
+ 	 * enable IRQ
+ 	 */
+ 	if (rcar_has_irq_support(priv)) {
+-		rcar_thermal_write(priv, FILONOFF, 0);
++		if (priv->chip->has_filonoff)
++			rcar_thermal_write(priv, FILONOFF, 0);
+ 
+ 		/* enable Rising/Falling edge interrupt */
+ 		rcar_thermal_write(priv, POSNEG,  0x1);
+@@ -420,7 +465,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
+ 
+ 	rcar_thermal_for_each_priv(priv, common) {
+ 		rcar_thermal_irq_disable(priv);
+-		if (rcar_use_of_thermal(dev))
++		if (priv->chip->use_of_thermal)
+ 			thermal_remove_hwmon_sysfs(priv->zone);
+ 		else
+ 			thermal_zone_device_unregister(priv->zone);
+@@ -438,6 +483,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 	struct rcar_thermal_priv *priv;
+ 	struct device *dev = &pdev->dev;
+ 	struct resource *res, *irq;
++	const struct rcar_thermal_chip *chip = of_device_get_match_data(dev);
+ 	int mres = 0;
+ 	int i;
+ 	int ret = -ENODEV;
+@@ -457,19 +503,35 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 	pm_runtime_enable(dev);
+ 	pm_runtime_get_sync(dev);
+ 
+-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+-	if (irq) {
+-		/*
+-		 * platform has IRQ support.
+-		 * Then, driver uses common registers
+-		 * rcar_has_irq_support() will be enabled
+-		 */
+-		res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
+-		common->base = devm_ioremap_resource(dev, res);
+-		if (IS_ERR(common->base))
+-			return PTR_ERR(common->base);
++	for (i = 0; i < chip->nirqs; i++) {
++		irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++		if (!irq)
++			continue;
++		if (!common->base) {
++			/*
++			 * platform has IRQ support.
++			 * Then, driver uses common registers
++			 * rcar_has_irq_support() will be enabled
++			 */
++			res = platform_get_resource(pdev, IORESOURCE_MEM,
++						    mres++);
++			common->base = devm_ioremap_resource(dev, res);
++			if (IS_ERR(common->base))
++				return PTR_ERR(common->base);
++
++			idle = 0; /* polling delay is not needed */
++		}
+ 
+-		idle = 0; /* polling delay is not needed */
++		ret = devm_request_irq(dev, irq->start, rcar_thermal_irq,
++				       IRQF_SHARED, dev_name(dev), common);
++		if (ret) {
++			dev_err(dev, "irq request failed\n ");
++			goto error_unregister;
++		}
++
++		/* update ENR bits */
++		if (chip->irq_per_ch)
++			enr_bits |= 1 << i;
+ 	}
+ 
+ 	for (i = 0;; i++) {
+@@ -491,6 +553,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 
+ 		priv->common = common;
+ 		priv->id = i;
++		priv->chip = chip;
+ 		mutex_init(&priv->lock);
+ 		INIT_LIST_HEAD(&priv->list);
+ 		INIT_DELAYED_WORK(&priv->work, rcar_thermal_work);
+@@ -498,7 +561,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 		if (ret < 0)
+ 			goto error_unregister;
+ 
+-		if (rcar_use_of_thermal(dev))
++		if (chip->use_of_thermal)
+ 			priv->zone = devm_thermal_zone_of_sensor_register(
+ 						dev, i, priv,
+ 						&rcar_thermal_zone_of_ops);
+@@ -515,7 +578,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 			goto error_unregister;
+ 		}
+ 
+-		if (rcar_use_of_thermal(dev)) {
++		if (chip->use_of_thermal) {
+ 			/*
+ 			 * thermal_zone doesn't enable hwmon as default,
+ 			 * but, enable it here to keep compatible
+@@ -531,20 +594,12 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 		list_move_tail(&priv->list, &common->head);
+ 
+ 		/* update ENR bits */
+-		enr_bits |= 3 << (i * 8);
++		if (!chip->irq_per_ch)
++			enr_bits |= 3 << (i * 8);
+ 	}
+ 
+-	/* enable temperature comparation */
+-	if (irq) {
+-		ret = devm_request_irq(dev, irq->start, rcar_thermal_irq, 0,
+-				       dev_name(dev), common);
+-		if (ret) {
+-			dev_err(dev, "irq request failed\n ");
+-			goto error_unregister;
+-		}
+-
++	if (enr_bits)
+ 		rcar_thermal_common_write(common, ENR, enr_bits);
+-	}
+ 
+ 	dev_info(dev, "%d sensor probed\n", i);
+ 
+@@ -556,9 +611,48 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 	return ret;
+ }
+ 
++#ifdef CONFIG_PM_SLEEP
++static int rcar_thermal_suspend(struct device *dev)
++{
++	struct rcar_thermal_common *common = dev_get_drvdata(dev);
++	struct rcar_thermal_priv *priv = list_first_entry(&common->head,
++							  typeof(*priv), list);
++
++	if (priv->chip->needs_suspend_resume) {
++		rcar_thermal_common_write(common, ENR, 0);
++		rcar_thermal_irq_disable(priv);
++		rcar_thermal_bset(priv, THSCR, CPCTL, 0);
++	}
++
++	return 0;
++}
++
++static int rcar_thermal_resume(struct device *dev)
++{
++	struct rcar_thermal_common *common = dev_get_drvdata(dev);
++	struct rcar_thermal_priv *priv = list_first_entry(&common->head,
++							  typeof(*priv), list);
++	int ret;
++
++	if (priv->chip->needs_suspend_resume) {
++		ret = rcar_thermal_update_temp(priv);
++		if (ret < 0)
++			return ret;
++		rcar_thermal_irq_enable(priv);
++		rcar_thermal_common_write(common, ENR, 0x03);
++	}
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(rcar_thermal_pm_ops, rcar_thermal_suspend,
++			 rcar_thermal_resume);
++
+ static struct platform_driver rcar_thermal_driver = {
+ 	.driver	= {
+ 		.name	= "rcar_thermal",
++		.pm = &rcar_thermal_pm_ops,
+ 		.of_match_table = rcar_thermal_dt_ids,
+ 	},
+ 	.probe		= rcar_thermal_probe,
+-- 
+2.19.0
+
diff --git a/patches/1216-dt-bindings-more-status-property-removal-from-exampl.patch b/patches/1216-dt-bindings-more-status-property-removal-from-exampl.patch
new file mode 100644
index 00000000000000..68c10e9500f653
--- /dev/null
+++ b/patches/1216-dt-bindings-more-status-property-removal-from-exampl.patch
@@ -0,0 +1,183 @@
+From 1bb5577512167ba8057954512b25e85cfc55bb43 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Tue, 17 Apr 2018 08:53:39 -0500
+Subject: [PATCH 1216/1795] dt-bindings: more status property removal from
+ examples
+
+Whack-a-mole some more occurrences of status in examples.
+
+Acked-by: Vinod Koul <vinod.koul@intel.com>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: James Hogan <jhogan@kernel.org>
+Cc: Ulf Hansson <ulf.hansson@linaro.org>
+Cc: David Woodhouse <dwmw2@infradead.org>
+Cc: Brian Norris <computersforpeace@gmail.com>
+Cc: Boris Brezillon <boris.brezillon@bootlin.com>
+Cc: Marek Vasut <marek.vasut@gmail.com>
+Cc: Richard Weinberger <richard@nod.at>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: Tanmay Inamdar <tinamdar@apm.com>
+Cc: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Rodolfo Giometti <giometti@enneenne.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 304a39b4bc94525b357083d44d766ff318f208e0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/dma/k3dma.txt       | 1 -
+ Documentation/devicetree/bindings/dma/ti-edma.txt     | 1 -
+ Documentation/devicetree/bindings/mips/lantiq/rcu.txt | 2 --
+ Documentation/devicetree/bindings/mmc/tmio_mmc.txt    | 4 ----
+ Documentation/devicetree/bindings/mtd/mtk-nand.txt    | 4 ----
+ Documentation/devicetree/bindings/pci/xgene-pci.txt   | 7 -------
+ Documentation/devicetree/bindings/pps/pps-gpio.txt    | 1 -
+ 7 files changed, 20 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt
+index 23f8d712c3ce..4945aeac4dc4 100644
+--- a/Documentation/devicetree/bindings/dma/k3dma.txt
++++ b/Documentation/devicetree/bindings/dma/k3dma.txt
+@@ -23,7 +23,6 @@ Controller:
+ 			dma-requests = <27>;
+ 			interrupts = <0 12 4>;
+ 			clocks = <&pclk>;
+-			status = "disable";
+ 		};
+ 
+ Client:
+diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
+index 41f0c1a07c56..9019389ce4a8 100644
+--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
++++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
+@@ -190,7 +190,6 @@ mmc0: mmc@23000000 {
+ 	power-domains = <&k2g_pds 0xb>;
+ 	clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+ 	clock-names = "fck", "mmchsdb_fck";
+-	status = "disabled";
+ };
+ 
+ ------------------------------------------------------------------------------
+diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
+index a086f1e1cdd7..7f0822b4beae 100644
+--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
++++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
+@@ -61,7 +61,6 @@ Example of the RCU bindings on a xRX200 SoC:
+ 		usb_phy0: usb2-phy@18 {
+ 			compatible = "lantiq,xrx200-usb2-phy";
+ 			reg = <0x18 4>, <0x38 4>;
+-			status = "disabled";
+ 
+ 			resets = <&reset1 4 4>, <&reset0 4 4>;
+ 			reset-names = "phy", "ctrl";
+@@ -71,7 +70,6 @@ Example of the RCU bindings on a xRX200 SoC:
+ 		usb_phy1: usb2-phy@34 {
+ 			compatible = "lantiq,xrx200-usb2-phy";
+ 			reg = <0x34 4>, <0x3C 4>;
+-			status = "disabled";
+ 
+ 			resets = <&reset1 5 4>, <&reset0 4 4>;
+ 			reset-names = "phy", "ctrl";
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index 2d5287eeed95..634bb66fc49c 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -67,7 +67,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 314>;
+-		status = "disabled";
+ 	};
+ 
+ 	sdhi1: sd@ee120000 {
+@@ -81,7 +80,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 		max-frequency = <195000000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 313>;
+-		status = "disabled";
+ 	};
+ 
+ 	sdhi2: sd@ee140000 {
+@@ -95,7 +93,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 312>;
+-		status = "disabled";
+ 	};
+ 
+ 	sdhi3: sd@ee160000 {
+@@ -109,5 +106,4 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
+ 		max-frequency = <97500000>;
+ 		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ 		resets = <&cpg 311>;
+-		status = "disabled";
+ 	};
+diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+index dbf9e054c11c..bd7a38b6ed1b 100644
+--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
++++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+@@ -18,7 +18,6 @@ Required NFI properties:
+ - interrupts:			Interrupts of NFI.
+ - clocks:			NFI required clocks.
+ - clock-names:			NFI clocks internal name.
+-- status:			Disabled default. Then set "okay" by platform.
+ - ecc-engine:			Required ECC Engine node.
+ - #address-cells:		NAND chip index, should be 1.
+ - #size-cells:			Should be 0.
+@@ -32,7 +31,6 @@ Example:
+ 		clocks = <&pericfg CLK_PERI_NFI>,
+ 			 <&pericfg CLK_PERI_NFI_PAD>;
+ 		clock-names = "nfi_clk", "pad_clk";
+-		status = "disabled";
+ 		ecc-engine = <&bch>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -147,7 +145,6 @@ Required BCH properties:
+ - interrupts:	Interrupts of ECC.
+ - clocks:	ECC required clocks.
+ - clock-names:	ECC clocks internal name.
+-- status:	Disabled default. Then set "okay" by platform.
+ 
+ Example:
+ 
+@@ -157,5 +154,4 @@ Example:
+ 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ 		clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ 		clock-names = "nfiecc_clk";
+-		status = "disabled";
+ 	};
+diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt
+index 6fd2decfa66c..92490330dc1c 100644
+--- a/Documentation/devicetree/bindings/pci/xgene-pci.txt
++++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt
+@@ -25,8 +25,6 @@ Optional properties:
+ 
+ Example:
+ 
+-SoC-specific DT Entry:
+-
+ 	pcie0: pcie@1f2b0000 {
+ 		status = "disabled";
+ 		device_type = "pci";
+@@ -50,8 +48,3 @@ SoC-specific DT Entry:
+ 		clocks = <&pcie0clk 0>;
+ 	};
+ 
+-
+-Board-specific DT Entry:
+-	&pcie0 {
+-		status = "ok";
+-	};
+diff --git a/Documentation/devicetree/bindings/pps/pps-gpio.txt b/Documentation/devicetree/bindings/pps/pps-gpio.txt
+index 0de23b793657..3683874832ae 100644
+--- a/Documentation/devicetree/bindings/pps/pps-gpio.txt
++++ b/Documentation/devicetree/bindings/pps/pps-gpio.txt
+@@ -20,5 +20,4 @@ Example:
+ 		assert-falling-edge;
+ 
+ 		compatible = "pps-gpio";
+-		status = "okay";
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1217-mmc-renesas_sdhi-use-helpers-to-access-struct-scatte.patch b/patches/1217-mmc-renesas_sdhi-use-helpers-to-access-struct-scatte.patch
new file mode 100644
index 00000000000000..c6d303f2c13087
--- /dev/null
+++ b/patches/1217-mmc-renesas_sdhi-use-helpers-to-access-struct-scatte.patch
@@ -0,0 +1,71 @@
+From c0e81a54e38198fc1e3fb912ca7048cbcac60453 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 18 Apr 2018 20:20:58 +0200
+Subject: [PATCH 1217/1795] mmc: renesas_sdhi: use helpers to access struct
+ scatterlist members
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Instead of directly accessing the members of struct scatterlist use the
+helpers mmc_get_dma_dir() and sg_dma_address() in
+renesas_sdhi_internal_dmac_start_dma(). Based on previous work by
+Masaharu Hayakawa.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+[rebased to mmc/next]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+
+(cherry picked from commit a028b435bf37fa091f701ee44e45cc152740fb8f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 07a642cd33af..21e50dac6ba1 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -157,7 +157,6 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ {
+ 	struct scatterlist *sg = host->sg_ptr;
+ 	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+-	enum dma_data_direction dir;
+ 	int ret;
+ 
+ 	/* This DMAC cannot handle if sg_len is not 1 */
+@@ -169,16 +168,15 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 
+ 	if (data->flags & MMC_DATA_READ) {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+-		dir = DMA_FROM_DEVICE;
+ 		if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
+ 		    test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
+ 			goto force_pio;
+ 	} else {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+-		dir = DMA_TO_DEVICE;
+ 	}
+ 
+-	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
++	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len,
++			 mmc_get_dma_dir(data));
+ 	if (ret == 0)
+ 		goto force_pio;
+ 
+@@ -188,7 +186,7 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
+ 					    dtran_mode);
+ 	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
+-					    sg->dma_address);
++					    sg_dma_address(sg));
+ 
+ 	return;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1218-mmc-renesas_sdhi-Fix-alignment-check-of-sg-buffer.patch b/patches/1218-mmc-renesas_sdhi-Fix-alignment-check-of-sg-buffer.patch
new file mode 100644
index 00000000000000..1b0e5e38834f04
--- /dev/null
+++ b/patches/1218-mmc-renesas_sdhi-Fix-alignment-check-of-sg-buffer.patch
@@ -0,0 +1,71 @@
+From 80493a36f5e3cbf00916af69fd2945492c97d33e Mon Sep 17 00:00:00 2001
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Date: Wed, 18 Apr 2018 20:20:59 +0200
+Subject: [PATCH 1218/1795] mmc: renesas_sdhi: Fix alignment check of sg buffer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sometimes sg->offset is not used for buffer addresses allocated by
+dma_map_sg(), so alignment checks should be done on the allocated buffer
+addresses. Delete the alignment check for sg->offset that is done before
+dma_map_sg(). Instead, it performs the alignment check for
+sg->dma_address after dma_map_sg().
+
+Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+[Niklas: broke this commit in two and tidied small style issue]
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+[rebased to mmc/next]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+
+(cherry picked from commit ae275b9d606f92227f43603919dc3576380efdc1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 21e50dac6ba1..2a4d65940a7c 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -157,14 +157,20 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ {
+ 	struct scatterlist *sg = host->sg_ptr;
+ 	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+-	int ret;
+ 
+ 	/* This DMAC cannot handle if sg_len is not 1 */
+ 	WARN_ON(host->sg_len > 1);
+ 
++	if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
++			mmc_get_dma_dir(data)))
++		goto force_pio;
++
+ 	/* This DMAC cannot handle if buffer is not 8-bytes alignment */
+-	if (!IS_ALIGNED(sg->offset, 8))
++	if (!IS_ALIGNED(sg_dma_address(sg), 8)) {
++		dma_unmap_sg(&host->pdev->dev, sg, host->sg_len,
++			     mmc_get_dma_dir(data));
+ 		goto force_pio;
++	}
+ 
+ 	if (data->flags & MMC_DATA_READ) {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+@@ -175,11 +181,6 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+ 	}
+ 
+-	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len,
+-			 mmc_get_dma_dir(data));
+-	if (ret == 0)
+-		goto force_pio;
+-
+ 	renesas_sdhi_internal_dmac_enable_dma(host, true);
+ 
+ 	/* set dma parameters */
+-- 
+2.19.0
+
diff --git a/patches/1219-mmc-renesas_sdhi_internal_dmac-use-more-generic-whit.patch b/patches/1219-mmc-renesas_sdhi_internal_dmac-use-more-generic-whit.patch
new file mode 100644
index 00000000000000..65d88c0d8b61e6
--- /dev/null
+++ b/patches/1219-mmc-renesas_sdhi_internal_dmac-use-more-generic-whit.patch
@@ -0,0 +1,47 @@
+From b7c40ebb9a5de780ab5ba8dc3e67d4a4b3516c88 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 18 Apr 2018 20:21:00 +0200
+Subject: [PATCH 1219/1795] mmc: renesas_sdhi_internal_dmac: use more generic
+ whitelisting
+
+Whitelisting every ES version does not scale. So, we whitelist whole
+SoCs independent of ES version. If we need specific handling for an ES
+version, we put it to the front, so it will be matched first.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 1abf9e52ea502afb44700098d1cf49a102bd259a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 2a4d65940a7c..b6774bae9beb 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -271,12 +271,15 @@ static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
+  * implementation as others may use a different implementation.
+  */
+ static const struct soc_device_attribute gen3_soc_whitelist[] = {
++	/* specific ones */
+ 	{ .soc_id = "r8a7795", .revision = "ES1.*",
+ 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
+-	{ .soc_id = "r8a7795", .revision = "ES2.0" },
+ 	{ .soc_id = "r8a7796", .revision = "ES1.0",
+ 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
+-	{ .soc_id = "r8a77995", .revision = "ES1.0" },
++	/* generic ones */
++	{ .soc_id = "r8a7795" },
++	{ .soc_id = "r8a7796" },
++	{ .soc_id = "r8a77995" },
+ 	{ /* sentinel */ }
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1220-mmc-renesas_sdhi_internal_dmac-remove-superfluous-WA.patch b/patches/1220-mmc-renesas_sdhi_internal_dmac-remove-superfluous-WA.patch
new file mode 100644
index 00000000000000..6152af5369b475
--- /dev/null
+++ b/patches/1220-mmc-renesas_sdhi_internal_dmac-remove-superfluous-WA.patch
@@ -0,0 +1,45 @@
+From 893b5843ba6298344789d6af977d956e021c0e34 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 18 Apr 2018 20:21:01 +0200
+Subject: [PATCH 1220/1795] mmc: renesas_sdhi_internal_dmac: remove superfluous
+ WARN
+
+The WARN can never trigger because we limited the max_seg number in
+renesas_sdhi_of_data already. Remove it and update the comment.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit ebca50dfae525341c48c2f69798667352318549e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index b6774bae9beb..7c2c8a7d020e 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -91,7 +91,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+ 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
+-	/* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
++	/* DMAC can handle 0xffffffff blk count but only 1 segment */
+ 	.max_blk_count	= 0xffffffff,
+ 	.max_segs	= 1,
+ };
+@@ -158,9 +158,6 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 	struct scatterlist *sg = host->sg_ptr;
+ 	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+ 
+-	/* This DMAC cannot handle if sg_len is not 1 */
+-	WARN_ON(host->sg_len > 1);
+-
+ 	if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
+ 			mmc_get_dma_dir(data)))
+ 		goto force_pio;
+-- 
+2.19.0
+
diff --git a/patches/1221-mmc-dt-tmio_mmc-document-R8A77980-bindings.patch b/patches/1221-mmc-dt-tmio_mmc-document-R8A77980-bindings.patch
new file mode 100644
index 00000000000000..422830d2f47ded
--- /dev/null
+++ b/patches/1221-mmc-dt-tmio_mmc-document-R8A77980-bindings.patch
@@ -0,0 +1,34 @@
+From 79219e61e16808926379def6aa5b4fa5df048137 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Mon, 16 Apr 2018 21:30:02 +0300
+Subject: [PATCH 1221/1795] mmc: dt: tmio_mmc: document R8A77980 bindings
+
+Document the R-Car V3H (R8A77980) SoC in the Renesas SDHI bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b638602eae7851918d2abed823ab3bed0c269e59)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index 634bb66fc49c..881d4448d9d1 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -26,6 +26,7 @@ Required properties:
+ 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
+ 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
+ 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
++		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
+ 		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
+ 		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
+ 		"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
+-- 
+2.19.0
+
diff --git a/patches/1222-mmc-renesas_sdhi_internal_dmac-add-R8A77980-to-white.patch b/patches/1222-mmc-renesas_sdhi_internal_dmac-add-R8A77980-to-white.patch
new file mode 100644
index 00000000000000..fb28ecf0288aea
--- /dev/null
+++ b/patches/1222-mmc-renesas_sdhi_internal_dmac-add-R8A77980-to-white.patch
@@ -0,0 +1,34 @@
+From cb74b7ff28fad55da84b5b27d377c1b203079a5f Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 19 Apr 2018 23:07:44 +0300
+Subject: [PATCH 1222/1795] mmc: renesas_sdhi_internal_dmac: add R8A77980 to
+ whitelist
+
+I've successfully tested eMMC on R8A77980/Condor. R8A77980 has a single
+SDHI core anyway, so can't be a subject of the known RX DMA errata...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit e419768f3242e0e91ee6c691b2e871ff6afd6995)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 7c2c8a7d020e..71cdb6df83cb 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -276,6 +276,7 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
+ 	/* generic ones */
+ 	{ .soc_id = "r8a7795" },
+ 	{ .soc_id = "r8a7796" },
++	{ .soc_id = "r8a77980" },
+ 	{ .soc_id = "r8a77995" },
+ 	{ /* sentinel */ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/1223-mmc-renesas_sdhi-Add-r8a77965-support.patch b/patches/1223-mmc-renesas_sdhi-Add-r8a77965-support.patch
new file mode 100644
index 00000000000000..edafb64581889c
--- /dev/null
+++ b/patches/1223-mmc-renesas_sdhi-Add-r8a77965-support.patch
@@ -0,0 +1,48 @@
+From fccc4dbdf3df1fda365140b5f8af9ea8145fc0e5 Mon Sep 17 00:00:00 2001
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Date: Wed, 9 May 2018 21:38:48 +0900
+Subject: [PATCH 1223/1795] mmc: renesas_sdhi: Add r8a77965 support
+
+This patch adds r8a77965 support in SDHI.
+
+Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit caeffcf1b26bac57676fbb15df81bff1b79123ea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c      | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+index 881d4448d9d1..839f469f4525 100644
+--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
++++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+@@ -26,6 +26,7 @@ Required properties:
+ 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
+ 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
+ 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
++		"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
+ 		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
+ 		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
+ 		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 71cdb6df83cb..c7bec7dd032a 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -276,6 +276,7 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
+ 	/* generic ones */
+ 	{ .soc_id = "r8a7795" },
+ 	{ .soc_id = "r8a7796" },
++	{ .soc_id = "r8a77965" },
+ 	{ .soc_id = "r8a77980" },
+ 	{ .soc_id = "r8a77995" },
+ 	{ /* sentinel */ }
+-- 
+2.19.0
+
diff --git a/patches/1224-mmc-renesas_sdhi-really-fix-WP-logic-regressions.patch b/patches/1224-mmc-renesas_sdhi-really-fix-WP-logic-regressions.patch
new file mode 100644
index 00000000000000..f9931b5f6d70f3
--- /dev/null
+++ b/patches/1224-mmc-renesas_sdhi-really-fix-WP-logic-regressions.patch
@@ -0,0 +1,105 @@
+From c49ee19ed7240ab9e6f2449e81b0141638cf3e7d Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Fri, 1 Jun 2018 13:00:37 +0200
+Subject: [PATCH 1224/1795] mmc: renesas_sdhi: really fix WP logic regressions
+
+This reverts commit e060d376cc61 ("mmc: renesas_sdhi: fix WP detection")
+and adds some code to really fix the regressions.
+
+It was missed so far that Renesas R-Car instantiations of SDHI chose to
+disable internal WP and used the existence of "wp-gpios" to en/disable
+WP at all.
+
+With the first refactoring by Yamada-san with commit 2ad1db059b9a ("mmc:
+renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT instead of TMIO own flag"),
+WP was always disabled even when GPIOs were present. With Wolfram's
+first fix which gets now reverted, GPIOs were honored. But when not
+available, the fallback was to internal WP and not to disabled WP. This
+caused wrong WP status on uSD card slots.
+
+Restore the old behaviour now. By default, WP is disabled. When a GPIO
+is found, the GPIO re-enables WP. We will think about possible better
+ways to handle this in the future.
+
+Tested on a previously regressing Renesas Lager board (H2) and a still
+working Renesas Salvator-X board (M3-W).
+
+Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Cc: stable@vger.kernel.org # v4.17+
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit ef5332c10d4f332a2ac79e9ad5452f4e89d1815a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_core.c          | 5 +++++
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
+ drivers/mmc/host/renesas_sdhi_sys_dmac.c      | 3 +++
+ 3 files changed, 9 insertions(+)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
+index 51e01f03fb99..45c015da2e75 100644
+--- a/drivers/mmc/host/renesas_sdhi_core.c
++++ b/drivers/mmc/host/renesas_sdhi_core.c
+@@ -28,6 +28,7 @@
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/mmc/host.h>
++#include <linux/mmc/slot-gpio.h>
+ #include <linux/mfd/tmio.h>
+ #include <linux/sh_dma.h>
+ #include <linux/delay.h>
+@@ -534,6 +535,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
+ 	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
+ 	host->dma_ops		= dma_ops;
+ 
++	/* For some SoC, we disable internal WP. GPIO may override this */
++	if (mmc_can_gpio_ro(host->mmc))
++		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
++
+ 	/* SDR speeds are only available on Gen2+ */
+ 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
+ 		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index c7bec7dd032a..e521f486b430 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -87,6 +87,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+index 848e50c1638a..4bb46c489d71 100644
+--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+@@ -42,6 +42,7 @@ static const struct renesas_sdhi_of_data of_rz_compatible = {
+ static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
+ 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ };
+ 
+ /* Definitions for sampling clocks */
+@@ -61,6 +62,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.dma_buswidth	= DMA_SLAVE_BUSWIDTH_4_BYTES,
+ 	.dma_rx_offset	= 0x2000,
+ 	.scc_offset	= 0x0300,
+@@ -81,6 +83,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+ 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+ 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ 			  MMC_CAP_CMD23,
++	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
+ 	.bus_shift	= 2,
+ 	.scc_offset	= 0x1000,
+ 	.taps		= rcar_gen3_scc_taps,
+-- 
+2.19.0
+
diff --git a/patches/1225-soc-renesas-Identify-RZ-G1C.patch b/patches/1225-soc-renesas-Identify-RZ-G1C.patch
new file mode 100644
index 00000000000000..3d36a413f8bc6e
--- /dev/null
+++ b/patches/1225-soc-renesas-Identify-RZ-G1C.patch
@@ -0,0 +1,47 @@
+From 40793f3ae7e82dfd4c87fff0d027e9758b857b59 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 27 Mar 2018 15:37:13 +0100
+Subject: [PATCH 1225/1795] soc: renesas: Identify RZ/G1C
+
+Add support for identifying the RZ/G1C (r8a77470) SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1daf13ba10378cad9ea4f5f26b83dd36c36dcdc0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index ea71c413c926..3912a71bd417 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -100,6 +100,11 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
+ 	.id	= 0x4c,
+ };
+ 
++static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
++	.family	= &fam_rzg,
++	.id	= 0x53,
++};
++
+ static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
+ 	.family	= &fam_rcar_gen1,
+ };
+@@ -192,6 +197,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
+ #ifdef CONFIG_ARCH_R8A7745
+ 	{ .compatible = "renesas,r8a7745",	.data = &soc_rz_g1e },
+ #endif
++#ifdef CONFIG_ARCH_R8A77470
++	{ .compatible = "renesas,r8a77470",	.data = &soc_rz_g1c },
++#endif
+ #ifdef CONFIG_ARCH_R8A7778
+ 	{ .compatible = "renesas,r8a7778",	.data = &soc_rcar_m1a },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/1226-soc-renesas-identify-R-Car-E3.patch b/patches/1226-soc-renesas-identify-R-Car-E3.patch
new file mode 100644
index 00000000000000..bb4afdbbcb19f6
--- /dev/null
+++ b/patches/1226-soc-renesas-identify-R-Car-E3.patch
@@ -0,0 +1,47 @@
+From b3e61ad30682bba6c421350b91e26574319027ca Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Wed, 11 Apr 2018 18:36:23 +0900
+Subject: [PATCH 1226/1795] soc: renesas: identify R-Car E3
+
+This patch adds support for identifying the R-Car E3 (R8A77990) SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 44842d4555e39d821171f3753d370c245396db32)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/renesas-soc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 3912a71bd417..d44d0e687ab8 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -164,6 +164,11 @@ static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
+ 	.id	= 0x56,
+ };
+ 
++static const struct renesas_soc soc_rcar_e3 __initconst __maybe_unused = {
++	.family	= &fam_rcar_gen3,
++	.id	= 0x57,
++};
++
+ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
+ 	.family	= &fam_rcar_gen3,
+ 	.id	= 0x58,
+@@ -236,6 +241,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
+ #ifdef CONFIG_ARCH_R8A77980
+ 	{ .compatible = "renesas,r8a77980",	.data = &soc_rcar_v3h },
+ #endif
++#ifdef CONFIG_ARCH_R8A77990
++	{ .compatible = "renesas,r8a77990",	.data = &soc_rcar_e3 },
++#endif
+ #ifdef CONFIG_ARCH_R8A77995
+ 	{ .compatible = "renesas,r8a77995",	.data = &soc_rcar_d3 },
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/1227-dt-bindings-timer-renesas-cmt-Document-r8a774-35-CMT.patch b/patches/1227-dt-bindings-timer-renesas-cmt-Document-r8a774-35-CMT.patch
new file mode 100644
index 00000000000000..82ed46f7c8bc8a
--- /dev/null
+++ b/patches/1227-dt-bindings-timer-renesas-cmt-Document-r8a774-35-CMT.patch
@@ -0,0 +1,58 @@
+From e6ea9ecf8ddc81e3828ec5b37578b32fe6ba3b25 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 18 Dec 2017 17:39:01 +0000
+Subject: [PATCH 1227/1795] dt-bindings: timer: renesas, cmt: Document
+ r8a774[35] CMT support
+
+Document SoC specific compatible strings for r8a7743 and r8a7745.
+No driver change is needed as the fallback strings will activate
+the right code.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 24d79d738b6fed977f44cae2ca277a49a7aa5f70)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/timer/renesas,cmt.txt      | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+index d740989eb569..b40add2d9bb4 100644
+--- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt
++++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+@@ -22,6 +22,10 @@ Required Properties:
+ 
+     - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
+     - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
++    - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
++    - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
++    - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
++    - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.
+     - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
+     - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
+     - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
+@@ -31,10 +35,12 @@ Required Properties:
+     - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
+     - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
+ 
+-    - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2.
+-    - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2.
+-		These are fallbacks for r8a73a4 and all the R-Car Gen2
+-		entries	listed above.
++    - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
++		and RZ/G1.
++    - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2
++		and RZ/G1.
++		These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries
++		listed above.
+ 
+   - reg: base address and length of the registers block for the timer module.
+   - interrupts: interrupt-specifier for the timer, one per channel.
+-- 
+2.19.0
+
diff --git a/patches/1228-dmaengine-shdmac-Change-platform-check-to-CONFIG_ARC.patch b/patches/1228-dmaengine-shdmac-Change-platform-check-to-CONFIG_ARC.patch
new file mode 100644
index 00000000000000..2a2124538bb9f9
--- /dev/null
+++ b/patches/1228-dmaengine-shdmac-Change-platform-check-to-CONFIG_ARC.patch
@@ -0,0 +1,129 @@
+From fb210387083980aa87f3560d4f286194724c64de Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 20 Apr 2018 15:28:28 +0200
+Subject: [PATCH 1228/1795] dmaengine: shdmac: Change platform check to
+ CONFIG_ARCH_RENESAS
+
+Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
+is CONFIG_ARCH_RENESAS a more appropriate platform check than the legacy
+CONFIG_ARCH_SHMOBILE, hence use the former.
+
+Renesas SuperH SH-Mobile SoCs are still covered by the CONFIG_CPU_SH4
+check, just like before support for Renesas ARM SoCs was added.
+
+Instead of blindly changing all the #ifdefs, switch the main code block
+in sh_dmae_probe() to IS_ENABLED(), as this allows to remove all the
+remaining #ifdefs.
+
+This will allow to drop ARCH_SHMOBILE on ARM in the near future.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 0ef9944d2e05bedc6e388fe215edd4c1bed192bc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/shdmac.c | 50 +++++++++++++++++------------------------
+ 1 file changed, 21 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
+index c94ffab0d25c..04a74e0a95b7 100644
+--- a/drivers/dma/sh/shdmac.c
++++ b/drivers/dma/sh/shdmac.c
+@@ -443,7 +443,6 @@ static bool sh_dmae_reset(struct sh_dmae_device *shdev)
+ 	return ret;
+ }
+ 
+-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
+ static irqreturn_t sh_dmae_err(int irq, void *data)
+ {
+ 	struct sh_dmae_device *shdev = data;
+@@ -454,7 +453,6 @@ static irqreturn_t sh_dmae_err(int irq, void *data)
+ 	sh_dmae_reset(shdev);
+ 	return IRQ_HANDLED;
+ }
+-#endif
+ 
+ static bool sh_dmae_desc_completed(struct shdma_chan *schan,
+ 				   struct shdma_desc *sdesc)
+@@ -686,11 +684,8 @@ static int sh_dmae_probe(struct platform_device *pdev)
+ 	const struct sh_dmae_pdata *pdata;
+ 	unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
+ 	int chan_irq[SH_DMAE_MAX_CHANNELS];
+-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
+ 	unsigned long irqflags = 0;
+-	int errirq;
+-#endif
+-	int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
++	int err, errirq, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
+ 	struct sh_dmae_device *shdev;
+ 	struct dma_device *dma_dev;
+ 	struct resource *chan, *dmars, *errirq_res, *chanirq_res;
+@@ -792,33 +787,32 @@ static int sh_dmae_probe(struct platform_device *pdev)
+ 	if (err)
+ 		goto rst_err;
+ 
+-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
+-	chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
++	if (IS_ENABLED(CONFIG_CPU_SH4) || IS_ENABLED(CONFIG_ARCH_RENESAS)) {
++		chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+ 
+-	if (!chanirq_res)
+-		chanirq_res = errirq_res;
+-	else
+-		irqres++;
++		if (!chanirq_res)
++			chanirq_res = errirq_res;
++		else
++			irqres++;
+ 
+-	if (chanirq_res == errirq_res ||
+-	    (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
+-		irqflags = IRQF_SHARED;
++		if (chanirq_res == errirq_res ||
++		    (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
++			irqflags = IRQF_SHARED;
+ 
+-	errirq = errirq_res->start;
++		errirq = errirq_res->start;
+ 
+-	err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
+-			       "DMAC Address Error", shdev);
+-	if (err) {
+-		dev_err(&pdev->dev,
+-			"DMA failed requesting irq #%d, error %d\n",
+-			errirq, err);
+-		goto eirq_err;
++		err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err,
++				       irqflags, "DMAC Address Error", shdev);
++		if (err) {
++			dev_err(&pdev->dev,
++				"DMA failed requesting irq #%d, error %d\n",
++				errirq, err);
++			goto eirq_err;
++		}
++	} else {
++		chanirq_res = errirq_res;
+ 	}
+ 
+-#else
+-	chanirq_res = errirq_res;
+-#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
+-
+ 	if (chanirq_res->start == chanirq_res->end &&
+ 	    !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
+ 		/* Special case - all multiplexed */
+@@ -884,9 +878,7 @@ static int sh_dmae_probe(struct platform_device *pdev)
+ chan_probe_err:
+ 	sh_dmae_chan_remove(shdev);
+ 
+-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
+ eirq_err:
+-#endif
+ rst_err:
+ 	spin_lock_irq(&sh_dmae_lock);
+ 	list_del_rcu(&shdev->node);
+-- 
+2.19.0
+
diff --git a/patches/1229-sh_eth-use-TSU-register-accessors-for-TSU_POST-n.patch b/patches/1229-sh_eth-use-TSU-register-accessors-for-TSU_POST-n.patch
new file mode 100644
index 00000000000000..6ef963f8db83bd
--- /dev/null
+++ b/patches/1229-sh_eth-use-TSU-register-accessors-for-TSU_POST-n.patch
@@ -0,0 +1,72 @@
+From 9b1340bb2192826f6072c13a43012c6bef3dec42 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 2 May 2018 22:54:48 +0300
+Subject: [PATCH 1229/1795] sh_eth: use TSU register accessors for TSU_POST<n>
+
+There's no particularly good reason TSU_POST<n> registers get accessed
+circumventing sh_eth_tsu_{read|write}() -- start using those, removing
+(badly named) sh_eth_tsu_get_post_reg_offset(),  while at it...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 77cb065fde0a179f252caabfad5466cf9c522572)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 20 ++++++--------------
+ 1 file changed, 6 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index d14914495a65..b71f726abb53 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2583,12 +2583,6 @@ static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
+ }
+ 
+ /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
+-static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
+-					    int entry)
+-{
+-	return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
+-}
+-
+ static u32 sh_eth_tsu_get_post_mask(int entry)
+ {
+ 	return 0x0f << (28 - ((entry % 8) * 4));
+@@ -2603,27 +2597,25 @@ static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
+ 					     int entry)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
++	int reg = TSU_POST1 + entry / 8;
+ 	u32 tmp;
+-	void *reg_offset;
+ 
+-	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
+-	tmp = ioread32(reg_offset);
+-	iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
++	tmp = sh_eth_tsu_read(mdp, reg);
++	sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
+ }
+ 
+ static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
+ 					      int entry)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
++	int reg = TSU_POST1 + entry / 8;
+ 	u32 post_mask, ref_mask, tmp;
+-	void *reg_offset;
+ 
+-	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
+ 	post_mask = sh_eth_tsu_get_post_mask(entry);
+ 	ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
+ 
+-	tmp = ioread32(reg_offset);
+-	iowrite32(tmp & ~post_mask, reg_offset);
++	tmp = sh_eth_tsu_read(mdp, reg);
++	sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
+ 
+ 	/* If other port enables, the function returns "true" */
+ 	return tmp & ref_mask;
+-- 
+2.19.0
+
diff --git a/patches/1230-sh_eth-WARN_ON-access-to-unimplemented-TSU-register.patch b/patches/1230-sh_eth-WARN_ON-access-to-unimplemented-TSU-register.patch
new file mode 100644
index 00000000000000..9f55b5d72cb179
--- /dev/null
+++ b/patches/1230-sh_eth-WARN_ON-access-to-unimplemented-TSU-register.patch
@@ -0,0 +1,54 @@
+From 9bc3eb94e1da2003c4ce82062810054be817e01a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 2 May 2018 22:55:52 +0300
+Subject: [PATCH 1230/1795] sh_eth: WARN_ON() access to unimplemented TSU
+ register
+
+Commit 3365711df024 ("sh_eth: WARN on access to a register not implemented
+in a particular chip") added  WARN_ON() to sh_eth_{read|write}() but not
+to sh_eth_tsu_{read|write}(). Now that we've routed almost all TSU register
+accesses  (except TSU_ADR{H|L}<n> -- which are special) thru the latter
+pair of accessors, it makes sense to check for the unimplemented TSU
+registers as well...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 627a0d20fa7b9e05ea4f42f47ea84d450dbbc96f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index b71f726abb53..f22f1af16d0e 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -442,12 +442,22 @@ static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
+ static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
+ 			     int enum_index)
+ {
+-	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
++	u16 offset = mdp->reg_offset[enum_index];
++
++	if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
++		return;
++
++	iowrite32(data, mdp->tsu_addr + offset);
+ }
+ 
+ static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
+ {
+-	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
++	u16 offset = mdp->reg_offset[enum_index];
++
++	if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
++		return ~0U;
++
++	return ioread32(mdp->tsu_addr + offset);
+ }
+ 
+ static void sh_eth_select_mii(struct net_device *ndev)
+-- 
+2.19.0
+
diff --git a/patches/1231-sh_eth-add-RGMII-support.patch b/patches/1231-sh_eth-add-RGMII-support.patch
new file mode 100644
index 00000000000000..41de659a5ab13b
--- /dev/null
+++ b/patches/1231-sh_eth-add-RGMII-support.patch
@@ -0,0 +1,38 @@
+From a682329c04bb5fa4b1a2f523bf800735a09e065b Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 18 May 2018 21:30:18 +0300
+Subject: [PATCH 1231/1795] sh_eth: add RGMII support
+
+The R-Car V3H (AKA R8A77980) GEther controller  adds support for the RGMII
+PHY interface mode as a new  value  for the RMII_MII register.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 230c184679d5517e9770275853cd3456d00d6599)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index f22f1af16d0e..c9060768ffcf 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -466,6 +466,9 @@ static void sh_eth_select_mii(struct net_device *ndev)
+ 	u32 value;
+ 
+ 	switch (mdp->phy_interface) {
++	case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
++		value = 0x3;
++		break;
+ 	case PHY_INTERFACE_MODE_GMII:
+ 		value = 0x2;
+ 		break;
+-- 
+2.19.0
+
diff --git a/patches/1232-sh_eth-add-EDMR.NBST-support.patch b/patches/1232-sh_eth-add-EDMR.NBST-support.patch
new file mode 100644
index 00000000000000..93d4ab24d0b10f
--- /dev/null
+++ b/patches/1232-sh_eth-add-EDMR.NBST-support.patch
@@ -0,0 +1,60 @@
+From 472236b8c7802c7df26ead68f38d2b1fa20c2197 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 18 May 2018 21:31:28 +0300
+Subject: [PATCH 1232/1795] sh_eth: add EDMR.NBST support
+
+The R-Car V3H (AKA R8A77980) GEther controller adds the DMA burst mode bit
+(NBST) in EDMR and the manual tells to always set it before doing any DMA.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 93f0fa75190fefee55408a1c0812fa54f576c61b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 4 ++++
+ drivers/net/ethernet/renesas/sh_eth.h | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index c9060768ffcf..19ebb6e9f91a 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1434,6 +1434,10 @@ static int sh_eth_dev_init(struct net_device *ndev)
+ 
+ 	sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
+ 
++	/* DMA transfer burst mode */
++	if (mdp->cd->nbst)
++		sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
++
+ 	if (mdp->cd->bculr)
+ 		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
+ 
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 1bf930d4a1e5..6dd24fc515ca 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -184,6 +184,7 @@ enum GECMR_BIT {
+ 
+ /* EDMR */
+ enum DMAC_M_BIT {
++	EDMR_NBST = 0x80,
+ 	EDMR_EL = 0x40, /* Litte endian */
+ 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
+ 	EDMR_SRST_GETHER = 0x03,
+@@ -505,6 +506,7 @@ struct sh_eth_cpu_data {
+ 	unsigned bculr:1;	/* EtherC have BCULR */
+ 	unsigned tsu:1;		/* EtherC have TSU */
+ 	unsigned hw_swap:1;	/* E-DMAC have DE bit in EDMR */
++	unsigned nbst:1;	/* E-DMAC has NBST bit in EDMR */
+ 	unsigned rpadir:1;	/* E-DMAC have RPADIR */
+ 	unsigned no_trimd:1;	/* E-DMAC DO NOT have TRIMD */
+ 	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
+-- 
+2.19.0
+
diff --git a/patches/1233-sh_eth-add-R8A77980-support.patch b/patches/1233-sh_eth-add-R8A77980-support.patch
new file mode 100644
index 00000000000000..1bbcfd3764d911
--- /dev/null
+++ b/patches/1233-sh_eth-add-R8A77980-support.patch
@@ -0,0 +1,100 @@
+From db5aa81b4408b6ea082af6f659adf8799782a631 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 18 May 2018 21:32:46 +0300
+Subject: [PATCH 1233/1795] sh_eth: add R8A77980 support
+
+Finally, add support for the DT probing of the R-Car V3H (AKA R8A77980) --
+it's the only R-Car gen3 SoC having the GEther controller -- others have
+only EtherAVB...
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 3eb9c2ad1db04913041b78e0b5e543527128b90b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/net/sh_eth.txt        |  1 +
+ drivers/net/ethernet/renesas/sh_eth.c         | 44 +++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt
+index 5172799a7f1a..82a4cf2c145d 100644
+--- a/Documentation/devicetree/bindings/net/sh_eth.txt
++++ b/Documentation/devicetree/bindings/net/sh_eth.txt
+@@ -14,6 +14,7 @@ Required properties:
+ 	      "renesas,ether-r8a7791"  if the device is a part of R8A7791 SoC.
+ 	      "renesas,ether-r8a7793"  if the device is a part of R8A7793 SoC.
+ 	      "renesas,ether-r8a7794"  if the device is a part of R8A7794 SoC.
++	      "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC.
+ 	      "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
+ 	      "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
+ 	      "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 19ebb6e9f91a..9ea1abd9f8c5 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -753,6 +753,49 @@ static struct sh_eth_cpu_data rcar_gen2_data = {
+ 	.rmiimode	= 1,
+ 	.magic		= 1,
+ };
++
++/* R8A77980 */
++static struct sh_eth_cpu_data r8a77980_data = {
++	.soft_reset	= sh_eth_soft_reset_gether,
++
++	.set_duplex	= sh_eth_set_duplex,
++	.set_rate	= sh_eth_set_rate_gether,
++
++	.register_type  = SH_ETH_REG_GIGABIT,
++
++	.edtrr_trns	= EDTRR_TRNS_GETHER,
++	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
++	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
++			  ECSIPR_MPDIP,
++	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
++			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
++			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
++			  EESIPR_RMAFIP | EESIPR_RRFIP |
++			  EESIPR_RTLFIP | EESIPR_RTSFIP |
++			  EESIPR_PREIP | EESIPR_CERFIP,
++
++	.tx_check       = EESR_FTC | EESR_CD | EESR_RTO,
++	.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
++			  EESR_RFE | EESR_RDE | EESR_RFRMER |
++			  EESR_TFE | EESR_TDE | EESR_ECI,
++	.fdr_value	= 0x0000070f,
++
++	.apr		= 1,
++	.mpr		= 1,
++	.tpauser	= 1,
++	.bculr		= 1,
++	.hw_swap	= 1,
++	.nbst		= 1,
++	.rpadir		= 1,
++	.rpadir_value   = 2 << 16,
++	.no_trimd	= 1,
++	.no_ade		= 1,
++	.xdfar_rw	= 1,
++	.hw_checksum	= 1,
++	.select_mii	= 1,
++	.magic		= 1,
++	.cexcr		= 1,
++};
+ #endif /* CONFIG_OF */
+ 
+ static void sh_eth_set_rate_sh7724(struct net_device *ndev)
+@@ -3112,6 +3155,7 @@ static const struct of_device_id sh_eth_match_table[] = {
+ 	{ .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
+ 	{ .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
++	{ .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
+ 	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
+ 	{ .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
+ 	{ .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
+-- 
+2.19.0
+
diff --git a/patches/1234-sh_eth-fix-typo-in-EESR.TRO-bit-name.patch b/patches/1234-sh_eth-fix-typo-in-EESR.TRO-bit-name.patch
new file mode 100644
index 00000000000000..832a69bfb70aaa
--- /dev/null
+++ b/patches/1234-sh_eth-fix-typo-in-EESR.TRO-bit-name.patch
@@ -0,0 +1,92 @@
+From cb5116ed282bdfe68ba78c2edab5f5798dc74049 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 20 May 2018 00:02:36 +0300
+Subject: [PATCH 1234/1795] sh_eth: fix typo in EESR.TRO bit name
+
+The  correct name of the EESR bit 8 is TRO (transmit retry over), not RTO.
+Note that EESIPR bit 8, TROIP remained correct...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 27164491cb82b611b5269e632e4af0664788794d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 10 +++++-----
+ drivers/net/ethernet/renesas/sh_eth.h |  4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 9ea1abd9f8c5..b69b2071247b 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -706,7 +706,7 @@ static struct sh_eth_cpu_data rcar_gen1_data = {
+ 			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+ 			  EESIPR_PREIP | EESIPR_CERFIP,
+ 
+-	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
++	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
+ 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+ 			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
+ 	.fdr_value	= 0x00000f0f,
+@@ -738,7 +738,7 @@ static struct sh_eth_cpu_data rcar_gen2_data = {
+ 			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+ 			  EESIPR_PREIP | EESIPR_CERFIP,
+ 
+-	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
++	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
+ 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+ 			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
+ 	.fdr_value	= 0x00000f0f,
+@@ -774,7 +774,7 @@ static struct sh_eth_cpu_data r8a77980_data = {
+ 			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+ 			  EESIPR_PREIP | EESIPR_CERFIP,
+ 
+-	.tx_check       = EESR_FTC | EESR_CD | EESR_RTO,
++	.tx_check       = EESR_FTC | EESR_CD | EESR_TRO,
+ 	.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
+ 			  EESR_RFE | EESR_RDE | EESR_RFRMER |
+ 			  EESR_TFE | EESR_TDE | EESR_ECI,
+@@ -831,7 +831,7 @@ static struct sh_eth_cpu_data sh7724_data = {
+ 			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+ 			  EESIPR_PREIP | EESIPR_CERFIP,
+ 
+-	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
++	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
+ 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+ 			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
+ 
+@@ -876,7 +876,7 @@ static struct sh_eth_cpu_data sh7757_data = {
+ 			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+ 			  EESIPR_PREIP | EESIPR_CERFIP,
+ 
+-	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
++	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
+ 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+ 			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
+ 
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 6dd24fc515ca..01671bd6654c 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -243,7 +243,7 @@ enum EESR_BIT {
+ 	EESR_CND	= 0x00000800,
+ 	EESR_DLC	= 0x00000400,
+ 	EESR_CD		= 0x00000200,
+-	EESR_RTO	= 0x00000100,
++	EESR_TRO	= 0x00000100,
+ 	EESR_RMAF	= 0x00000080,
+ 	EESR_CEEF	= 0x00000040,
+ 	EESR_CELF	= 0x00000020,
+@@ -263,7 +263,7 @@ enum EESR_BIT {
+ 				 EESR_CERF)  /* Recv frame CRC error */
+ 
+ #define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
+-				 EESR_RTO)
++				 EESR_TRO)
+ #define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
+ 				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
+ 				 EESR_TFE | EESR_TDE)
+-- 
+2.19.0
+
diff --git a/patches/1235-sh_eth-fix-comment-grammar-in-struct-sh_eth_cpu_data.patch b/patches/1235-sh_eth-fix-comment-grammar-in-struct-sh_eth_cpu_data.patch
new file mode 100644
index 00000000000000..563471eca43a8b
--- /dev/null
+++ b/patches/1235-sh_eth-fix-comment-grammar-in-struct-sh_eth_cpu_data.patch
@@ -0,0 +1,58 @@
+From 5de13614a5c6d8de2212e8a189485f4642636927 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 20 May 2018 00:03:42 +0300
+Subject: [PATCH 1235/1795] sh_eth: fix comment grammar in 'struct
+ sh_eth_cpu_data'
+
+All the verbs in the comments to the 'struct sh_eth_cpu_data' declaration
+should  be in a  3rd person singular, to match the nouns.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 9c59c9a8e94660d05790e47bd4a8c756254614b7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.h | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 01671bd6654c..5dee19b61aee 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -499,21 +499,21 @@ struct sh_eth_cpu_data {
+ 
+ 	/* hardware features */
+ 	unsigned long irq_flags; /* IRQ configuration flags */
+-	unsigned no_psr:1;	/* EtherC DO NOT have PSR */
+-	unsigned apr:1;		/* EtherC have APR */
+-	unsigned mpr:1;		/* EtherC have MPR */
+-	unsigned tpauser:1;	/* EtherC have TPAUSER */
+-	unsigned bculr:1;	/* EtherC have BCULR */
+-	unsigned tsu:1;		/* EtherC have TSU */
+-	unsigned hw_swap:1;	/* E-DMAC have DE bit in EDMR */
++	unsigned no_psr:1;	/* EtherC DOES NOT have PSR */
++	unsigned apr:1;		/* EtherC has APR */
++	unsigned mpr:1;		/* EtherC has MPR */
++	unsigned tpauser:1;	/* EtherC has TPAUSER */
++	unsigned bculr:1;	/* EtherC has BCULR */
++	unsigned tsu:1;		/* EtherC has TSU */
++	unsigned hw_swap:1;	/* E-DMAC has DE bit in EDMR */
+ 	unsigned nbst:1;	/* E-DMAC has NBST bit in EDMR */
+-	unsigned rpadir:1;	/* E-DMAC have RPADIR */
+-	unsigned no_trimd:1;	/* E-DMAC DO NOT have TRIMD */
+-	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
++	unsigned rpadir:1;	/* E-DMAC has RPADIR */
++	unsigned no_trimd:1;	/* E-DMAC DOES NOT have TRIMD */
++	unsigned no_ade:1;	/* E-DMAC DOES NOT have ADE bit in EESR */
+ 	unsigned no_xdfar:1;	/* E-DMAC DOES NOT have RDFAR/TDFAR */
+ 	unsigned xdfar_rw:1;	/* E-DMAC has writeable RDFAR/TDFAR */
+ 	unsigned hw_checksum:1;	/* E-DMAC has CSMR */
+-	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
++	unsigned select_mii:1;	/* EtherC has RMII_MII (MII select register) */
+ 	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
+ 	unsigned rtrate:1;	/* EtherC has RTRATE register */
+ 	unsigned magic:1;	/* EtherC has ECMR.MPDE and ECSR.MPD */
+-- 
+2.19.0
+
diff --git a/patches/1236-sh_eth-fix-typo-in-comment-to-BCULR-write.patch b/patches/1236-sh_eth-fix-typo-in-comment-to-BCULR-write.patch
new file mode 100644
index 00000000000000..a3994ee415f931
--- /dev/null
+++ b/patches/1236-sh_eth-fix-typo-in-comment-to-BCULR-write.patch
@@ -0,0 +1,37 @@
+From 00ce16d092da1852f1c1939c43051213d5b1f2ec Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 20 May 2018 00:05:02 +0300
+Subject: [PATCH 1236/1795] sh_eth: fix typo in comment to BCULR write
+
+Simon has noticed a typo in the comment accompaining the BCULR write --
+fix it and move the comment before the write (following the style of
+the other comments), while at it...
+
+Reported-by: Simon Horman <horms@verge.net.au>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 6b14787ab11d8fc2225132f0fe8275531fdefc72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index b69b2071247b..08b3e22f3469 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -1481,8 +1481,9 @@ static int sh_eth_dev_init(struct net_device *ndev)
+ 	if (mdp->cd->nbst)
+ 		sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
+ 
++	/* Burst cycle count upper-limit */
+ 	if (mdp->cd->bculr)
+-		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
++		sh_eth_write(ndev, 0x800, BCULR);
+ 
+ 	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1237-sh_eth-make-sh_eth_soft_swap-work-on-ARM.patch b/patches/1237-sh_eth-make-sh_eth_soft_swap-work-on-ARM.patch
new file mode 100644
index 00000000000000..5ede0fa2adb9c2
--- /dev/null
+++ b/patches/1237-sh_eth-make-sh_eth_soft_swap-work-on-ARM.patch
@@ -0,0 +1,42 @@
+From 5b8cfd0dc22a193aedcb56694e80f758bc125833 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 2 Jun 2018 22:37:42 +0300
+Subject: [PATCH 1237/1795] sh_eth: make sh_eth_soft_swap() work on ARM
+
+Browsing  thru the driver disassembly, I noticed that ARM gcc generated
+no  code  whatsoever for sh_eth_soft_swap() while building a little-endian
+kernel -- apparently __LITTLE_ENDIAN__ was not being #define'd, however
+it got implicitly #define'd when building with the SH gcc (I could only
+find the explicit #define __LITTLE_ENDIAN that was #include'd when building
+a little-endian kernel).  Luckily, the Ether controller  only doing big-
+endian DMA is encountered on the early SH771x SoCs only and all ARM SoCs
+implement EDMR.DE and thus set 'sh_eth_cpu_data::hw_swap'. But anyway, we
+need to fix the #ifdef inside sh_eth_soft_swap() to something that would
+work on all architectures...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 232b6743e4d12d8383aaf2d632d5ed4cc377419e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index 5dee19b61aee..d77de7651d8f 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -562,7 +562,7 @@ struct sh_eth_private {
+ 
+ static inline void sh_eth_soft_swap(char *src, int len)
+ {
+-#ifdef __LITTLE_ENDIAN__
++#ifdef __LITTLE_ENDIAN
+ 	u32 *p = (u32 *)src;
+ 	u32 *maxp;
+ 	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
+-- 
+2.19.0
+
diff --git a/patches/1238-sh_eth-uninline-sh_eth_soft_swap.patch b/patches/1238-sh_eth-uninline-sh_eth_soft_swap.patch
new file mode 100644
index 00000000000000..cd9e058f04cc56
--- /dev/null
+++ b/patches/1238-sh_eth-uninline-sh_eth_soft_swap.patch
@@ -0,0 +1,68 @@
+From cb52f25031af8d492279f0bd4e854a4235b4d6c2 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 2 Jun 2018 22:38:56 +0300
+Subject: [PATCH 1238/1795] sh_eth: uninline sh_eth_soft_swap()
+
+sh_eth_tsu_soft_swap() is called twice by the driver, remove *inline* and
+move  that function  from the header to the driver itself to let gcc decide
+whether to expand it inline or not...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit bb2fa4e847d779c0c3eba78c1abbe142134dcc3d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 11 +++++++++++
+ drivers/net/ethernet/renesas/sh_eth.h | 12 ------------
+ 2 files changed, 11 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 08b3e22f3469..f89b0f6a178b 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -460,6 +460,17 @@ static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
+ 	return ioread32(mdp->tsu_addr + offset);
+ }
+ 
++static void sh_eth_soft_swap(char *src, int len)
++{
++#ifdef __LITTLE_ENDIAN
++	u32 *p = (u32 *)src;
++	u32 *maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
++
++	for (; p < maxp; p++)
++		*p = swab32(*p);
++#endif
++}
++
+ static void sh_eth_select_mii(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
+index d77de7651d8f..726c55a82dd7 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.h
++++ b/drivers/net/ethernet/renesas/sh_eth.h
+@@ -560,18 +560,6 @@ struct sh_eth_private {
+ 	unsigned wol_enabled:1;
+ };
+ 
+-static inline void sh_eth_soft_swap(char *src, int len)
+-{
+-#ifdef __LITTLE_ENDIAN
+-	u32 *p = (u32 *)src;
+-	u32 *maxp;
+-	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
+-
+-	for (; p < maxp; p++)
+-		*p = swab32(*p);
+-#endif
+-}
+-
+ static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
+ 					  int enum_index)
+ {
+-- 
+2.19.0
+
diff --git a/patches/1239-sh_eth-use-DIV_ROUND_UP-in-sh_eth_soft_swap.patch b/patches/1239-sh_eth-use-DIV_ROUND_UP-in-sh_eth_soft_swap.patch
new file mode 100644
index 00000000000000..85b10e1f76af67
--- /dev/null
+++ b/patches/1239-sh_eth-use-DIV_ROUND_UP-in-sh_eth_soft_swap.patch
@@ -0,0 +1,34 @@
+From f8c299b9a1123e7c5dcece7e2d7239262e576731 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 2 Jun 2018 22:40:16 +0300
+Subject: [PATCH 1239/1795] sh_eth: use DIV_ROUND_UP() in sh_eth_soft_swap()
+
+When initializing 'maxp' in sh_eth_soft_swap(), the buffer length needs
+to be rounded  up -- that's just asking for DIV_ROUND_UP()!
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 1100149a23a5053de4709dc4ba14ab14bd826562)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index f89b0f6a178b..d83683961d87 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -464,7 +464,7 @@ static void sh_eth_soft_swap(char *src, int len)
+ {
+ #ifdef __LITTLE_ENDIAN
+ 	u32 *p = (u32 *)src;
+-	u32 *maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
++	u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
+ 
+ 	for (; p < maxp; p++)
+ 		*p = swab32(*p);
+-- 
+2.19.0
+
diff --git a/patches/1240-net-Remove-depends-on-HAS_DMA-in-case-of-platform-de.patch b/patches/1240-net-Remove-depends-on-HAS_DMA-in-case-of-platform-de.patch
new file mode 100644
index 00000000000000..de645a2c550b1c
--- /dev/null
+++ b/patches/1240-net-Remove-depends-on-HAS_DMA-in-case-of-platform-de.patch
@@ -0,0 +1,244 @@
+From bfd31a206bb6136caa5ba035bccd88bc75468603 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 22 Jun 2018 13:08:43 +0200
+Subject: [PATCH 1240/1795] net: Remove depends on HAS_DMA in case of platform
+ dependency
+
+Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
+symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
+In most cases this other symbol is an architecture or platform specific
+symbol, or PCI.
+
+Generic symbols and drivers without platform dependencies keep their
+dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
+cannot work anyway.
+
+This simplifies the dependencies, and allows to improve compile-testing.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Reviewed-by: Mark Brown <broonie@kernel.org>
+Acked-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit e020797b7def11c8feeb3ee5c1f48c12cb959def)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/amd/Kconfig                | 2 +-
+ drivers/net/ethernet/apm/xgene-v2/Kconfig       | 1 -
+ drivers/net/ethernet/apm/xgene/Kconfig          | 1 -
+ drivers/net/ethernet/arc/Kconfig                | 6 ++++--
+ drivers/net/ethernet/broadcom/Kconfig           | 2 --
+ drivers/net/ethernet/calxeda/Kconfig            | 2 +-
+ drivers/net/ethernet/hisilicon/Kconfig          | 2 +-
+ drivers/net/ethernet/marvell/Kconfig            | 8 +++-----
+ drivers/net/ethernet/mellanox/mlxsw/Kconfig     | 2 +-
+ drivers/net/ethernet/renesas/Kconfig            | 2 --
+ drivers/net/wireless/broadcom/brcm80211/Kconfig | 1 -
+ drivers/net/wireless/quantenna/qtnfmac/Kconfig  | 2 +-
+ 12 files changed, 12 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/net/ethernet/amd/Kconfig b/drivers/net/ethernet/amd/Kconfig
+index a8e8f4e9c1bb..9e5cf5583c87 100644
+--- a/drivers/net/ethernet/amd/Kconfig
++++ b/drivers/net/ethernet/amd/Kconfig
+@@ -173,7 +173,7 @@ config SUNLANCE
+ 
+ config AMD_XGBE
+ 	tristate "AMD 10GbE Ethernet driver"
+-	depends on ((OF_NET && OF_ADDRESS) || ACPI || PCI) && HAS_IOMEM && HAS_DMA
++	depends on ((OF_NET && OF_ADDRESS) || ACPI || PCI) && HAS_IOMEM
+ 	depends on X86 || ARM64 || COMPILE_TEST
+ 	select BITREVERSE
+ 	select CRC32
+diff --git a/drivers/net/ethernet/apm/xgene-v2/Kconfig b/drivers/net/ethernet/apm/xgene-v2/Kconfig
+index 1205861b6318..eedd3f3dd22e 100644
+--- a/drivers/net/ethernet/apm/xgene-v2/Kconfig
++++ b/drivers/net/ethernet/apm/xgene-v2/Kconfig
+@@ -1,6 +1,5 @@
+ config NET_XGENE_V2
+ 	tristate "APM X-Gene SoC Ethernet-v2 Driver"
+-	depends on HAS_DMA
+ 	depends on ARCH_XGENE || COMPILE_TEST
+ 	help
+ 	  This is the Ethernet driver for the on-chip ethernet interface
+diff --git a/drivers/net/ethernet/apm/xgene/Kconfig b/drivers/net/ethernet/apm/xgene/Kconfig
+index afccb033177b..e4e33c900b57 100644
+--- a/drivers/net/ethernet/apm/xgene/Kconfig
++++ b/drivers/net/ethernet/apm/xgene/Kconfig
+@@ -1,6 +1,5 @@
+ config NET_XGENE
+ 	tristate "APM X-Gene SoC Ethernet Driver"
+-	depends on HAS_DMA
+ 	depends on ARCH_XGENE || COMPILE_TEST
+ 	select PHYLIB
+ 	select MDIO_XGENE
+diff --git a/drivers/net/ethernet/arc/Kconfig b/drivers/net/ethernet/arc/Kconfig
+index e743ddf46343..5d0ab8e74b68 100644
+--- a/drivers/net/ethernet/arc/Kconfig
++++ b/drivers/net/ethernet/arc/Kconfig
+@@ -24,7 +24,8 @@ config ARC_EMAC_CORE
+ config ARC_EMAC
+ 	tristate "ARC EMAC support"
+ 	select ARC_EMAC_CORE
+-	depends on OF_IRQ && OF_NET && HAS_DMA && (ARC || COMPILE_TEST)
++	depends on OF_IRQ && OF_NET
++	depends on ARC || COMPILE_TEST
+ 	---help---
+ 	  On some legacy ARC (Synopsys) FPGA boards such as ARCAngel4/ML50x
+ 	  non-standard on-chip ethernet device ARC EMAC 10/100 is used.
+@@ -33,7 +34,8 @@ config ARC_EMAC
+ config EMAC_ROCKCHIP
+ 	tristate "Rockchip EMAC support"
+ 	select ARC_EMAC_CORE
+-	depends on OF_IRQ && OF_NET && REGULATOR && HAS_DMA && (ARCH_ROCKCHIP || COMPILE_TEST)
++	depends on OF_IRQ && OF_NET && REGULATOR
++	depends on ARCH_ROCKCHIP || COMPILE_TEST
+ 	---help---
+ 	  Support for Rockchip RK3036/RK3066/RK3188 EMAC ethernet controllers.
+ 	  This selects Rockchip SoC glue layer support for the
+diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig
+index 67134ece1107..5fb25d4f8591 100644
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -157,7 +157,6 @@ config BGMAC
+ config BGMAC_BCMA
+ 	tristate "Broadcom iProc GBit BCMA support"
+ 	depends on BCMA && BCMA_HOST_SOC
+-	depends on HAS_DMA
+ 	depends on BCM47XX || ARCH_BCM_5301X || COMPILE_TEST
+ 	select BGMAC
+ 	select PHYLIB
+@@ -170,7 +169,6 @@ config BGMAC_BCMA
+ 
+ config BGMAC_PLATFORM
+ 	tristate "Broadcom iProc GBit platform support"
+-	depends on HAS_DMA
+ 	depends on ARCH_BCM_IPROC || COMPILE_TEST
+ 	depends on OF
+ 	select BGMAC
+diff --git a/drivers/net/ethernet/calxeda/Kconfig b/drivers/net/ethernet/calxeda/Kconfig
+index 07d2201530d2..9fdd496b90ff 100644
+--- a/drivers/net/ethernet/calxeda/Kconfig
++++ b/drivers/net/ethernet/calxeda/Kconfig
+@@ -1,6 +1,6 @@
+ config NET_CALXEDA_XGMAC
+ 	tristate "Calxeda 1G/10G XGMAC Ethernet driver"
+-	depends on HAS_IOMEM && HAS_DMA
++	depends on HAS_IOMEM
+ 	depends on ARCH_HIGHBANK || COMPILE_TEST
+ 	select CRC32
+ 	help
+diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/hisilicon/Kconfig
+index 91c7bdb9b43c..444bb4a140d9 100644
+--- a/drivers/net/ethernet/hisilicon/Kconfig
++++ b/drivers/net/ethernet/hisilicon/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_HISILICON
+ 	bool "Hisilicon devices"
+ 	default y
+-	depends on (OF || ACPI) && HAS_DMA
++	depends on OF || ACPI
+ 	depends on ARM || ARM64 || COMPILE_TEST
+ 	---help---
+ 	  If you have a network (Ethernet) card belonging to this class, say Y.
+diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
+index da6fb825afea..427fd075b164 100644
+--- a/drivers/net/ethernet/marvell/Kconfig
++++ b/drivers/net/ethernet/marvell/Kconfig
+@@ -18,8 +18,8 @@ if NET_VENDOR_MARVELL
+ 
+ config MV643XX_ETH
+ 	tristate "Marvell Discovery (643XX) and Orion ethernet support"
+-	depends on (MV64X60 || PPC32 || PLAT_ORION || COMPILE_TEST) && INET
+-	depends on HAS_DMA
++	depends on MV64X60 || PPC32 || PLAT_ORION || COMPILE_TEST
++	depends on INET
+ 	select PHYLIB
+ 	select MVMDIO
+ 	---help---
+@@ -58,7 +58,6 @@ config MVNETA_BM_ENABLE
+ config MVNETA
+ 	tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ 	depends on ARCH_MVEBU || COMPILE_TEST
+-	depends on HAS_DMA
+ 	select MVMDIO
+ 	select FIXED_PHY
+ 	---help---
+@@ -84,7 +83,6 @@ config MVNETA_BM
+ config MVPP2
+ 	tristate "Marvell Armada 375/7K/8K network interface support"
+ 	depends on ARCH_MVEBU || COMPILE_TEST
+-	depends on HAS_DMA
+ 	select MVMDIO
+ 	---help---
+ 	  This driver supports the network interface units in the
+@@ -92,7 +90,7 @@ config MVPP2
+ 
+ config PXA168_ETH
+ 	tristate "Marvell pxa168 ethernet support"
+-	depends on HAS_IOMEM && HAS_DMA
++	depends on HAS_IOMEM
+ 	depends on CPU_PXA168 || ARCH_BERLIN || COMPILE_TEST
+ 	select PHYLIB
+ 	---help---
+diff --git a/drivers/net/ethernet/mellanox/mlxsw/Kconfig b/drivers/net/ethernet/mellanox/mlxsw/Kconfig
+index d56eea310509..b591c8cc9896 100644
+--- a/drivers/net/ethernet/mellanox/mlxsw/Kconfig
++++ b/drivers/net/ethernet/mellanox/mlxsw/Kconfig
+@@ -30,7 +30,7 @@ config MLXSW_CORE_THERMAL
+ 
+ config MLXSW_PCI
+ 	tristate "PCI bus implementation for Mellanox Technologies Switch ASICs"
+-	depends on PCI && HAS_DMA && HAS_IOMEM && MLXSW_CORE
++	depends on PCI && HAS_IOMEM && MLXSW_CORE
+ 	default m
+ 	---help---
+ 	  This is PCI bus implementation for Mellanox Technologies Switch ASICs.
+diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig
+index 27be51f0a421..f3f7477043ce 100644
+--- a/drivers/net/ethernet/renesas/Kconfig
++++ b/drivers/net/ethernet/renesas/Kconfig
+@@ -17,7 +17,6 @@ if NET_VENDOR_RENESAS
+ 
+ config SH_ETH
+ 	tristate "Renesas SuperH Ethernet support"
+-	depends on HAS_DMA
+ 	depends on ARCH_RENESAS || SUPERH || COMPILE_TEST
+ 	select CRC32
+ 	select MII
+@@ -31,7 +30,6 @@ config SH_ETH
+ 
+ config RAVB
+ 	tristate "Renesas Ethernet AVB support"
+-	depends on HAS_DMA
+ 	depends on ARCH_RENESAS || COMPILE_TEST
+ 	select CRC32
+ 	select MII
+diff --git a/drivers/net/wireless/broadcom/brcm80211/Kconfig b/drivers/net/wireless/broadcom/brcm80211/Kconfig
+index 9d99eb42d917..6acba67bca07 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/Kconfig
++++ b/drivers/net/wireless/broadcom/brcm80211/Kconfig
+@@ -60,7 +60,6 @@ config BRCMFMAC_PCIE
+ 	bool "PCIE bus interface support for FullMAC driver"
+ 	depends on BRCMFMAC
+ 	depends on PCI
+-	depends on HAS_DMA
+ 	select BRCMFMAC_PROTO_MSGBUF
+ 	select FW_LOADER
+ 	---help---
+diff --git a/drivers/net/wireless/quantenna/qtnfmac/Kconfig b/drivers/net/wireless/quantenna/qtnfmac/Kconfig
+index 025fa6018550..8d1492a90bd1 100644
+--- a/drivers/net/wireless/quantenna/qtnfmac/Kconfig
++++ b/drivers/net/wireless/quantenna/qtnfmac/Kconfig
+@@ -7,7 +7,7 @@ config QTNFMAC
+ config QTNFMAC_PEARL_PCIE
+ 	tristate "Quantenna QSR10g PCIe support"
+ 	default n
+-	depends on HAS_DMA && PCI && CFG80211
++	depends on PCI && CFG80211
+ 	select QTNFMAC
+ 	select FW_LOADER
+ 	select CRC32
+-- 
+2.19.0
+
diff --git a/patches/1241-spi-sh-msiof-Simplify-calculation-of-divisors-for-tr.patch b/patches/1241-spi-sh-msiof-Simplify-calculation-of-divisors-for-tr.patch
new file mode 100644
index 00000000000000..23717d8dc9e869
--- /dev/null
+++ b/patches/1241-spi-sh-msiof-Simplify-calculation-of-divisors-for-tr.patch
@@ -0,0 +1,159 @@
+From b1201193f43dbbc8d5ebdf82fd37a4c8954b95b0 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Fri, 13 Apr 2018 15:44:17 +0300
+Subject: [PATCH 1241/1795] spi: sh-msiof: Simplify calculation of divisors for
+ transfer rate
+
+The change updates sh_msiof_spi_set_clk_regs() function by iterating
+over BRDV power values. Note that the change is a functional one, namely
+prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division
+rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms
+of written values to TSCR setting of 0x0107 is substituted by 0x0000,
+and for all input parameter cases this is the only functional change,
+which touches the controller.
+
+As a result of the rework the function is supposed to be slightly more
+efficient and more readable and maintainable in case of any further
+extensions.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 51093cba290a375d51749d5bd61835809fa44853)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/spi-sh-msiof.c | 67 ++++++++++++++++++++------------------
+ 1 file changed, 35 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index c1ea7965fe27..d1c51b49c8ce 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -38,7 +38,7 @@ struct sh_msiof_chipdata {
+ 	u16 tx_fifo_size;
+ 	u16 rx_fifo_size;
+ 	u16 master_flags;
+-	u16 min_div;
++	u16 min_div_pow;
+ };
+ 
+ struct sh_msiof_spi_priv {
+@@ -50,7 +50,7 @@ struct sh_msiof_spi_priv {
+ 	struct completion done;
+ 	unsigned int tx_fifo_size;
+ 	unsigned int rx_fifo_size;
+-	unsigned int min_div;
++	unsigned int min_div_pow;
+ 	void *tx_dma_page;
+ 	void *rx_dma_page;
+ 	dma_addr_t tx_dma_addr;
+@@ -243,43 +243,46 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static struct {
+-	unsigned short div;
+-	unsigned short brdv;
+-} const sh_msiof_spi_div_table[] = {
+-	{ 1,	SCR_BRDV_DIV_1 },
+-	{ 2,	SCR_BRDV_DIV_2 },
+-	{ 4,	SCR_BRDV_DIV_4 },
+-	{ 8,	SCR_BRDV_DIV_8 },
+-	{ 16,	SCR_BRDV_DIV_16 },
+-	{ 32,	SCR_BRDV_DIV_32 },
++static const u32 sh_msiof_spi_div_array[] = {
++	SCR_BRDV_DIV_1, SCR_BRDV_DIV_2,	 SCR_BRDV_DIV_4,
++	SCR_BRDV_DIV_8,	SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
+ };
+ 
+ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
+ 				      unsigned long parent_rate, u32 spi_hz)
+ {
+-	unsigned long div = 1024;
++	unsigned long div;
+ 	u32 brps, scr;
+-	size_t k;
++	unsigned int div_pow = p->min_div_pow;
+ 
+-	if (!WARN_ON(!spi_hz || !parent_rate))
+-		div = DIV_ROUND_UP(parent_rate, spi_hz);
+-
+-	div = max_t(unsigned long, div, p->min_div);
++	if (!spi_hz || !parent_rate) {
++		WARN(1, "Invalid clock rate parameters %lu and %u\n",
++		     parent_rate, spi_hz);
++		return;
++	}
+ 
+-	for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
+-		brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
++	div = DIV_ROUND_UP(parent_rate, spi_hz);
++	if (div <= 1024) {
+ 		/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
+-		if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
+-			continue;
+-		if (brps <= 32) /* max of brdv is 32 */
+-			break;
+-	}
++		if (!div_pow && div <= 32 && div > 2)
++			div_pow = 1;
+ 
+-	k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
+-	brps = min_t(int, brps, 32);
++		if (div_pow)
++			brps = (div + 1) >> div_pow;
++		else
++			brps = div;
++
++		for (; brps > 32; div_pow++)
++			brps = (brps + 1) >> 1;
++	} else {
++		/* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
++		dev_err(&p->pdev->dev,
++			"Requested SPI transfer rate %d is too low\n", spi_hz);
++		div_pow = 5;
++		brps = 32;
++	}
+ 
+-	scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
++	scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
+ 	sh_msiof_write(p, TSCR, scr);
+ 	if (!(p->master->flags & SPI_MASTER_MUST_TX))
+ 		sh_msiof_write(p, RSCR, scr);
+@@ -1028,21 +1031,21 @@ static const struct sh_msiof_chipdata sh_data = {
+ 	.tx_fifo_size = 64,
+ 	.rx_fifo_size = 64,
+ 	.master_flags = 0,
+-	.min_div = 1,
++	.min_div_pow = 0,
+ };
+ 
+ static const struct sh_msiof_chipdata rcar_gen2_data = {
+ 	.tx_fifo_size = 64,
+ 	.rx_fifo_size = 64,
+ 	.master_flags = SPI_MASTER_MUST_TX,
+-	.min_div = 1,
++	.min_div_pow = 0,
+ };
+ 
+ static const struct sh_msiof_chipdata rcar_gen3_data = {
+ 	.tx_fifo_size = 64,
+ 	.rx_fifo_size = 64,
+ 	.master_flags = SPI_MASTER_MUST_TX,
+-	.min_div = 2,
++	.min_div_pow = 1,
+ };
+ 
+ static const struct of_device_id sh_msiof_match[] = {
+@@ -1267,7 +1270,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
+ 	platform_set_drvdata(pdev, p);
+ 	p->master = master;
+ 	p->info = info;
+-	p->min_div = chipdata->min_div;
++	p->min_div_pow = chipdata->min_div_pow;
+ 
+ 	init_completion(&p->done);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1242-pinctrl-sh-pfc-r8a77965-Add-MSIOF-pins-groups-and-fu.patch b/patches/1242-pinctrl-sh-pfc-r8a77965-Add-MSIOF-pins-groups-and-fu.patch
new file mode 100644
index 00000000000000..2bc48e09502fab
--- /dev/null
+++ b/patches/1242-pinctrl-sh-pfc-r8a77965-Add-MSIOF-pins-groups-and-fu.patch
@@ -0,0 +1,969 @@
+From d4907d6636d69ff568a8429f2fe0456ccf6bed00 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 14 Dec 2017 13:06:13 +0900
+Subject: [PATCH 1242/1795] pinctrl: sh-pfc: r8a77965: Add MSIOF pins, groups
+ and functions
+
+This patch adds MSIOF{0,1,2,3} pins, groups and functions to the
+R8A77965 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[geert: Correct MSIOF3 SS2_E comment]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+
+(cherry picked from commit 2c77aa3d70b9fc798bdf6d60ef362cee6dccab02)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 912 ++++++++++++++++++++++++++
+ 1 file changed, 912 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index cea9d0599c12..54461ebd5db1 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1706,6 +1706,704 @@ static const unsigned int intc_ex_irq5_mux[] = {
+ 	IRQ5_MARK,
+ };
+ 
++/* - MSIOF0 ----------------------------------------------------------------- */
++static const unsigned int msiof0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 17),
++};
++static const unsigned int msiof0_clk_mux[] = {
++	MSIOF0_SCK_MARK,
++};
++static const unsigned int msiof0_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(5, 18),
++};
++static const unsigned int msiof0_sync_mux[] = {
++	MSIOF0_SYNC_MARK,
++};
++static const unsigned int msiof0_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(5, 19),
++};
++static const unsigned int msiof0_ss1_mux[] = {
++	MSIOF0_SS1_MARK,
++};
++static const unsigned int msiof0_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(5, 21),
++};
++static const unsigned int msiof0_ss2_mux[] = {
++	MSIOF0_SS2_MARK,
++};
++static const unsigned int msiof0_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(5, 20),
++};
++static const unsigned int msiof0_txd_mux[] = {
++	MSIOF0_TXD_MARK,
++};
++static const unsigned int msiof0_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(5, 22),
++};
++static const unsigned int msiof0_rxd_mux[] = {
++	MSIOF0_RXD_MARK,
++};
++/* - MSIOF1 ----------------------------------------------------------------- */
++static const unsigned int msiof1_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 8),
++};
++static const unsigned int msiof1_clk_a_mux[] = {
++	MSIOF1_SCK_A_MARK,
++};
++static const unsigned int msiof1_sync_a_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(6, 9),
++};
++static const unsigned int msiof1_sync_a_mux[] = {
++	MSIOF1_SYNC_A_MARK,
++};
++static const unsigned int msiof1_ss1_a_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(6, 5),
++};
++static const unsigned int msiof1_ss1_a_mux[] = {
++	MSIOF1_SS1_A_MARK,
++};
++static const unsigned int msiof1_ss2_a_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(6, 6),
++};
++static const unsigned int msiof1_ss2_a_mux[] = {
++	MSIOF1_SS2_A_MARK,
++};
++static const unsigned int msiof1_txd_a_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(6, 7),
++};
++static const unsigned int msiof1_txd_a_mux[] = {
++	MSIOF1_TXD_A_MARK,
++};
++static const unsigned int msiof1_rxd_a_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(6, 10),
++};
++static const unsigned int msiof1_rxd_a_mux[] = {
++	MSIOF1_RXD_A_MARK,
++};
++static const unsigned int msiof1_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 9),
++};
++static const unsigned int msiof1_clk_b_mux[] = {
++	MSIOF1_SCK_B_MARK,
++};
++static const unsigned int msiof1_sync_b_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(5, 3),
++};
++static const unsigned int msiof1_sync_b_mux[] = {
++	MSIOF1_SYNC_B_MARK,
++};
++static const unsigned int msiof1_ss1_b_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(5, 4),
++};
++static const unsigned int msiof1_ss1_b_mux[] = {
++	MSIOF1_SS1_B_MARK,
++};
++static const unsigned int msiof1_ss2_b_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(5, 0),
++};
++static const unsigned int msiof1_ss2_b_mux[] = {
++	MSIOF1_SS2_B_MARK,
++};
++static const unsigned int msiof1_txd_b_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(5, 8),
++};
++static const unsigned int msiof1_txd_b_mux[] = {
++	MSIOF1_TXD_B_MARK,
++};
++static const unsigned int msiof1_rxd_b_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(5, 7),
++};
++static const unsigned int msiof1_rxd_b_mux[] = {
++	MSIOF1_RXD_B_MARK,
++};
++static const unsigned int msiof1_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(6, 17),
++};
++static const unsigned int msiof1_clk_c_mux[] = {
++	MSIOF1_SCK_C_MARK,
++};
++static const unsigned int msiof1_sync_c_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(6, 18),
++};
++static const unsigned int msiof1_sync_c_mux[] = {
++	MSIOF1_SYNC_C_MARK,
++};
++static const unsigned int msiof1_ss1_c_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(6, 21),
++};
++static const unsigned int msiof1_ss1_c_mux[] = {
++	MSIOF1_SS1_C_MARK,
++};
++static const unsigned int msiof1_ss2_c_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(6, 27),
++};
++static const unsigned int msiof1_ss2_c_mux[] = {
++	MSIOF1_SS2_C_MARK,
++};
++static const unsigned int msiof1_txd_c_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(6, 20),
++};
++static const unsigned int msiof1_txd_c_mux[] = {
++	MSIOF1_TXD_C_MARK,
++};
++static const unsigned int msiof1_rxd_c_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(6, 19),
++};
++static const unsigned int msiof1_rxd_c_mux[] = {
++	MSIOF1_RXD_C_MARK,
++};
++static const unsigned int msiof1_clk_d_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 12),
++};
++static const unsigned int msiof1_clk_d_mux[] = {
++	MSIOF1_SCK_D_MARK,
++};
++static const unsigned int msiof1_sync_d_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(5, 15),
++};
++static const unsigned int msiof1_sync_d_mux[] = {
++	MSIOF1_SYNC_D_MARK,
++};
++static const unsigned int msiof1_ss1_d_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(5, 16),
++};
++static const unsigned int msiof1_ss1_d_mux[] = {
++	MSIOF1_SS1_D_MARK,
++};
++static const unsigned int msiof1_ss2_d_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(5, 21),
++};
++static const unsigned int msiof1_ss2_d_mux[] = {
++	MSIOF1_SS2_D_MARK,
++};
++static const unsigned int msiof1_txd_d_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(5, 14),
++};
++static const unsigned int msiof1_txd_d_mux[] = {
++	MSIOF1_TXD_D_MARK,
++};
++static const unsigned int msiof1_rxd_d_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(5, 13),
++};
++static const unsigned int msiof1_rxd_d_mux[] = {
++	MSIOF1_RXD_D_MARK,
++};
++static const unsigned int msiof1_clk_e_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int msiof1_clk_e_mux[] = {
++	MSIOF1_SCK_E_MARK,
++};
++static const unsigned int msiof1_sync_e_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int msiof1_sync_e_mux[] = {
++	MSIOF1_SYNC_E_MARK,
++};
++static const unsigned int msiof1_ss1_e_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int msiof1_ss1_e_mux[] = {
++	MSIOF1_SS1_E_MARK,
++};
++static const unsigned int msiof1_ss2_e_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int msiof1_ss2_e_mux[] = {
++	MSIOF1_SS2_E_MARK,
++};
++static const unsigned int msiof1_txd_e_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(3, 3),
++};
++static const unsigned int msiof1_txd_e_mux[] = {
++	MSIOF1_TXD_E_MARK,
++};
++static const unsigned int msiof1_rxd_e_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(3, 2),
++};
++static const unsigned int msiof1_rxd_e_mux[] = {
++	MSIOF1_RXD_E_MARK,
++};
++static const unsigned int msiof1_clk_f_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 23),
++};
++static const unsigned int msiof1_clk_f_mux[] = {
++	MSIOF1_SCK_F_MARK,
++};
++static const unsigned int msiof1_sync_f_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(5, 24),
++};
++static const unsigned int msiof1_sync_f_mux[] = {
++	MSIOF1_SYNC_F_MARK,
++};
++static const unsigned int msiof1_ss1_f_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(6, 1),
++};
++static const unsigned int msiof1_ss1_f_mux[] = {
++	MSIOF1_SS1_F_MARK,
++};
++static const unsigned int msiof1_ss2_f_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(6, 2),
++};
++static const unsigned int msiof1_ss2_f_mux[] = {
++	MSIOF1_SS2_F_MARK,
++};
++static const unsigned int msiof1_txd_f_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(6, 0),
++};
++static const unsigned int msiof1_txd_f_mux[] = {
++	MSIOF1_TXD_F_MARK,
++};
++static const unsigned int msiof1_rxd_f_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(5, 25),
++};
++static const unsigned int msiof1_rxd_f_mux[] = {
++	MSIOF1_RXD_F_MARK,
++};
++static const unsigned int msiof1_clk_g_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(3, 6),
++};
++static const unsigned int msiof1_clk_g_mux[] = {
++	MSIOF1_SCK_G_MARK,
++};
++static const unsigned int msiof1_sync_g_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(3, 7),
++};
++static const unsigned int msiof1_sync_g_mux[] = {
++	MSIOF1_SYNC_G_MARK,
++};
++static const unsigned int msiof1_ss1_g_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(3, 10),
++};
++static const unsigned int msiof1_ss1_g_mux[] = {
++	MSIOF1_SS1_G_MARK,
++};
++static const unsigned int msiof1_ss2_g_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(3, 11),
++};
++static const unsigned int msiof1_ss2_g_mux[] = {
++	MSIOF1_SS2_G_MARK,
++};
++static const unsigned int msiof1_txd_g_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(3, 9),
++};
++static const unsigned int msiof1_txd_g_mux[] = {
++	MSIOF1_TXD_G_MARK,
++};
++static const unsigned int msiof1_rxd_g_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int msiof1_rxd_g_mux[] = {
++	MSIOF1_RXD_G_MARK,
++};
++/* - MSIOF2 ----------------------------------------------------------------- */
++static const unsigned int msiof2_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 9),
++};
++static const unsigned int msiof2_clk_a_mux[] = {
++	MSIOF2_SCK_A_MARK,
++};
++static const unsigned int msiof2_sync_a_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(1, 8),
++};
++static const unsigned int msiof2_sync_a_mux[] = {
++	MSIOF2_SYNC_A_MARK,
++};
++static const unsigned int msiof2_ss1_a_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(1, 6),
++};
++static const unsigned int msiof2_ss1_a_mux[] = {
++	MSIOF2_SS1_A_MARK,
++};
++static const unsigned int msiof2_ss2_a_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(1, 7),
++};
++static const unsigned int msiof2_ss2_a_mux[] = {
++	MSIOF2_SS2_A_MARK,
++};
++static const unsigned int msiof2_txd_a_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int msiof2_txd_a_mux[] = {
++	MSIOF2_TXD_A_MARK,
++};
++static const unsigned int msiof2_rxd_a_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(1, 10),
++};
++static const unsigned int msiof2_rxd_a_mux[] = {
++	MSIOF2_RXD_A_MARK,
++};
++static const unsigned int msiof2_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 4),
++};
++static const unsigned int msiof2_clk_b_mux[] = {
++	MSIOF2_SCK_B_MARK,
++};
++static const unsigned int msiof2_sync_b_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(0, 5),
++};
++static const unsigned int msiof2_sync_b_mux[] = {
++	MSIOF2_SYNC_B_MARK,
++};
++static const unsigned int msiof2_ss1_b_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(0, 0),
++};
++static const unsigned int msiof2_ss1_b_mux[] = {
++	MSIOF2_SS1_B_MARK,
++};
++static const unsigned int msiof2_ss2_b_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(0, 1),
++};
++static const unsigned int msiof2_ss2_b_mux[] = {
++	MSIOF2_SS2_B_MARK,
++};
++static const unsigned int msiof2_txd_b_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(0, 7),
++};
++static const unsigned int msiof2_txd_b_mux[] = {
++	MSIOF2_TXD_B_MARK,
++};
++static const unsigned int msiof2_rxd_b_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(0, 6),
++};
++static const unsigned int msiof2_rxd_b_mux[] = {
++	MSIOF2_RXD_B_MARK,
++};
++static const unsigned int msiof2_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int msiof2_clk_c_mux[] = {
++	MSIOF2_SCK_C_MARK,
++};
++static const unsigned int msiof2_sync_c_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(2, 11),
++};
++static const unsigned int msiof2_sync_c_mux[] = {
++	MSIOF2_SYNC_C_MARK,
++};
++static const unsigned int msiof2_ss1_c_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(2, 10),
++};
++static const unsigned int msiof2_ss1_c_mux[] = {
++	MSIOF2_SS1_C_MARK,
++};
++static const unsigned int msiof2_ss2_c_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(2, 9),
++};
++static const unsigned int msiof2_ss2_c_mux[] = {
++	MSIOF2_SS2_C_MARK,
++};
++static const unsigned int msiof2_txd_c_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(2, 14),
++};
++static const unsigned int msiof2_txd_c_mux[] = {
++	MSIOF2_TXD_C_MARK,
++};
++static const unsigned int msiof2_rxd_c_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(2, 13),
++};
++static const unsigned int msiof2_rxd_c_mux[] = {
++	MSIOF2_RXD_C_MARK,
++};
++static const unsigned int msiof2_clk_d_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 8),
++};
++static const unsigned int msiof2_clk_d_mux[] = {
++	MSIOF2_SCK_D_MARK,
++};
++static const unsigned int msiof2_sync_d_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(0, 9),
++};
++static const unsigned int msiof2_sync_d_mux[] = {
++	MSIOF2_SYNC_D_MARK,
++};
++static const unsigned int msiof2_ss1_d_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int msiof2_ss1_d_mux[] = {
++	MSIOF2_SS1_D_MARK,
++};
++static const unsigned int msiof2_ss2_d_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(0, 13),
++};
++static const unsigned int msiof2_ss2_d_mux[] = {
++	MSIOF2_SS2_D_MARK,
++};
++static const unsigned int msiof2_txd_d_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(0, 11),
++};
++static const unsigned int msiof2_txd_d_mux[] = {
++	MSIOF2_TXD_D_MARK,
++};
++static const unsigned int msiof2_rxd_d_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(0, 10),
++};
++static const unsigned int msiof2_rxd_d_mux[] = {
++	MSIOF2_RXD_D_MARK,
++};
++/* - MSIOF3 ----------------------------------------------------------------- */
++static const unsigned int msiof3_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 0),
++};
++static const unsigned int msiof3_clk_a_mux[] = {
++	MSIOF3_SCK_A_MARK,
++};
++static const unsigned int msiof3_sync_a_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(0, 1),
++};
++static const unsigned int msiof3_sync_a_mux[] = {
++	MSIOF3_SYNC_A_MARK,
++};
++static const unsigned int msiof3_ss1_a_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(0, 14),
++};
++static const unsigned int msiof3_ss1_a_mux[] = {
++	MSIOF3_SS1_A_MARK,
++};
++static const unsigned int msiof3_ss2_a_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(0, 15),
++};
++static const unsigned int msiof3_ss2_a_mux[] = {
++	MSIOF3_SS2_A_MARK,
++};
++static const unsigned int msiof3_txd_a_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(0, 3),
++};
++static const unsigned int msiof3_txd_a_mux[] = {
++	MSIOF3_TXD_A_MARK,
++};
++static const unsigned int msiof3_rxd_a_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(0, 2),
++};
++static const unsigned int msiof3_rxd_a_mux[] = {
++	MSIOF3_RXD_A_MARK,
++};
++static const unsigned int msiof3_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 2),
++};
++static const unsigned int msiof3_clk_b_mux[] = {
++	MSIOF3_SCK_B_MARK,
++};
++static const unsigned int msiof3_sync_b_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int msiof3_sync_b_mux[] = {
++	MSIOF3_SYNC_B_MARK,
++};
++static const unsigned int msiof3_ss1_b_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(1, 4),
++};
++static const unsigned int msiof3_ss1_b_mux[] = {
++	MSIOF3_SS1_B_MARK,
++};
++static const unsigned int msiof3_ss2_b_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(1, 5),
++};
++static const unsigned int msiof3_ss2_b_mux[] = {
++	MSIOF3_SS2_B_MARK,
++};
++static const unsigned int msiof3_txd_b_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(1, 1),
++};
++static const unsigned int msiof3_txd_b_mux[] = {
++	MSIOF3_TXD_B_MARK,
++};
++static const unsigned int msiof3_rxd_b_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(1, 3),
++};
++static const unsigned int msiof3_rxd_b_mux[] = {
++	MSIOF3_RXD_B_MARK,
++};
++static const unsigned int msiof3_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 12),
++};
++static const unsigned int msiof3_clk_c_mux[] = {
++	MSIOF3_SCK_C_MARK,
++};
++static const unsigned int msiof3_sync_c_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(1, 13),
++};
++static const unsigned int msiof3_sync_c_mux[] = {
++	MSIOF3_SYNC_C_MARK,
++};
++static const unsigned int msiof3_txd_c_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(1, 15),
++};
++static const unsigned int msiof3_txd_c_mux[] = {
++	MSIOF3_TXD_C_MARK,
++};
++static const unsigned int msiof3_rxd_c_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(1, 14),
++};
++static const unsigned int msiof3_rxd_c_mux[] = {
++	MSIOF3_RXD_C_MARK,
++};
++static const unsigned int msiof3_clk_d_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int msiof3_clk_d_mux[] = {
++	MSIOF3_SCK_D_MARK,
++};
++static const unsigned int msiof3_sync_d_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int msiof3_sync_d_mux[] = {
++	MSIOF3_SYNC_D_MARK,
++};
++static const unsigned int msiof3_ss1_d_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(1, 26),
++};
++static const unsigned int msiof3_ss1_d_mux[] = {
++	MSIOF3_SS1_D_MARK,
++};
++static const unsigned int msiof3_txd_d_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int msiof3_txd_d_mux[] = {
++	MSIOF3_TXD_D_MARK,
++};
++static const unsigned int msiof3_rxd_d_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int msiof3_rxd_d_mux[] = {
++	MSIOF3_RXD_D_MARK,
++};
++static const unsigned int msiof3_clk_e_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int msiof3_clk_e_mux[] = {
++	MSIOF3_SCK_E_MARK,
++};
++static const unsigned int msiof3_sync_e_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int msiof3_sync_e_mux[] = {
++	MSIOF3_SYNC_E_MARK,
++};
++static const unsigned int msiof3_ss1_e_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int msiof3_ss1_e_mux[] = {
++	MSIOF3_SS1_E_MARK,
++};
++static const unsigned int msiof3_ss2_e_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int msiof3_ss2_e_mux[] = {
++	MSIOF3_SS2_E_MARK,
++};
++static const unsigned int msiof3_txd_e_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int msiof3_txd_e_mux[] = {
++	MSIOF3_TXD_E_MARK,
++};
++static const unsigned int msiof3_rxd_e_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int msiof3_rxd_e_mux[] = {
++	MSIOF3_RXD_E_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -1965,6 +2663,105 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(intc_ex_irq3),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq4),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq5),
++	SH_PFC_PIN_GROUP(msiof0_clk),
++	SH_PFC_PIN_GROUP(msiof0_sync),
++	SH_PFC_PIN_GROUP(msiof0_ss1),
++	SH_PFC_PIN_GROUP(msiof0_ss2),
++	SH_PFC_PIN_GROUP(msiof0_txd),
++	SH_PFC_PIN_GROUP(msiof0_rxd),
++	SH_PFC_PIN_GROUP(msiof1_clk_a),
++	SH_PFC_PIN_GROUP(msiof1_sync_a),
++	SH_PFC_PIN_GROUP(msiof1_ss1_a),
++	SH_PFC_PIN_GROUP(msiof1_ss2_a),
++	SH_PFC_PIN_GROUP(msiof1_txd_a),
++	SH_PFC_PIN_GROUP(msiof1_rxd_a),
++	SH_PFC_PIN_GROUP(msiof1_clk_b),
++	SH_PFC_PIN_GROUP(msiof1_sync_b),
++	SH_PFC_PIN_GROUP(msiof1_ss1_b),
++	SH_PFC_PIN_GROUP(msiof1_ss2_b),
++	SH_PFC_PIN_GROUP(msiof1_txd_b),
++	SH_PFC_PIN_GROUP(msiof1_rxd_b),
++	SH_PFC_PIN_GROUP(msiof1_clk_c),
++	SH_PFC_PIN_GROUP(msiof1_sync_c),
++	SH_PFC_PIN_GROUP(msiof1_ss1_c),
++	SH_PFC_PIN_GROUP(msiof1_ss2_c),
++	SH_PFC_PIN_GROUP(msiof1_txd_c),
++	SH_PFC_PIN_GROUP(msiof1_rxd_c),
++	SH_PFC_PIN_GROUP(msiof1_clk_d),
++	SH_PFC_PIN_GROUP(msiof1_sync_d),
++	SH_PFC_PIN_GROUP(msiof1_ss1_d),
++	SH_PFC_PIN_GROUP(msiof1_ss2_d),
++	SH_PFC_PIN_GROUP(msiof1_txd_d),
++	SH_PFC_PIN_GROUP(msiof1_rxd_d),
++	SH_PFC_PIN_GROUP(msiof1_clk_e),
++	SH_PFC_PIN_GROUP(msiof1_sync_e),
++	SH_PFC_PIN_GROUP(msiof1_ss1_e),
++	SH_PFC_PIN_GROUP(msiof1_ss2_e),
++	SH_PFC_PIN_GROUP(msiof1_txd_e),
++	SH_PFC_PIN_GROUP(msiof1_rxd_e),
++	SH_PFC_PIN_GROUP(msiof1_clk_f),
++	SH_PFC_PIN_GROUP(msiof1_sync_f),
++	SH_PFC_PIN_GROUP(msiof1_ss1_f),
++	SH_PFC_PIN_GROUP(msiof1_ss2_f),
++	SH_PFC_PIN_GROUP(msiof1_txd_f),
++	SH_PFC_PIN_GROUP(msiof1_rxd_f),
++	SH_PFC_PIN_GROUP(msiof1_clk_g),
++	SH_PFC_PIN_GROUP(msiof1_sync_g),
++	SH_PFC_PIN_GROUP(msiof1_ss1_g),
++	SH_PFC_PIN_GROUP(msiof1_ss2_g),
++	SH_PFC_PIN_GROUP(msiof1_txd_g),
++	SH_PFC_PIN_GROUP(msiof1_rxd_g),
++	SH_PFC_PIN_GROUP(msiof2_clk_a),
++	SH_PFC_PIN_GROUP(msiof2_sync_a),
++	SH_PFC_PIN_GROUP(msiof2_ss1_a),
++	SH_PFC_PIN_GROUP(msiof2_ss2_a),
++	SH_PFC_PIN_GROUP(msiof2_txd_a),
++	SH_PFC_PIN_GROUP(msiof2_rxd_a),
++	SH_PFC_PIN_GROUP(msiof2_clk_b),
++	SH_PFC_PIN_GROUP(msiof2_sync_b),
++	SH_PFC_PIN_GROUP(msiof2_ss1_b),
++	SH_PFC_PIN_GROUP(msiof2_ss2_b),
++	SH_PFC_PIN_GROUP(msiof2_txd_b),
++	SH_PFC_PIN_GROUP(msiof2_rxd_b),
++	SH_PFC_PIN_GROUP(msiof2_clk_c),
++	SH_PFC_PIN_GROUP(msiof2_sync_c),
++	SH_PFC_PIN_GROUP(msiof2_ss1_c),
++	SH_PFC_PIN_GROUP(msiof2_ss2_c),
++	SH_PFC_PIN_GROUP(msiof2_txd_c),
++	SH_PFC_PIN_GROUP(msiof2_rxd_c),
++	SH_PFC_PIN_GROUP(msiof2_clk_d),
++	SH_PFC_PIN_GROUP(msiof2_sync_d),
++	SH_PFC_PIN_GROUP(msiof2_ss1_d),
++	SH_PFC_PIN_GROUP(msiof2_ss2_d),
++	SH_PFC_PIN_GROUP(msiof2_txd_d),
++	SH_PFC_PIN_GROUP(msiof2_rxd_d),
++	SH_PFC_PIN_GROUP(msiof3_clk_a),
++	SH_PFC_PIN_GROUP(msiof3_sync_a),
++	SH_PFC_PIN_GROUP(msiof3_ss1_a),
++	SH_PFC_PIN_GROUP(msiof3_ss2_a),
++	SH_PFC_PIN_GROUP(msiof3_txd_a),
++	SH_PFC_PIN_GROUP(msiof3_rxd_a),
++	SH_PFC_PIN_GROUP(msiof3_clk_b),
++	SH_PFC_PIN_GROUP(msiof3_sync_b),
++	SH_PFC_PIN_GROUP(msiof3_ss1_b),
++	SH_PFC_PIN_GROUP(msiof3_ss2_b),
++	SH_PFC_PIN_GROUP(msiof3_txd_b),
++	SH_PFC_PIN_GROUP(msiof3_rxd_b),
++	SH_PFC_PIN_GROUP(msiof3_clk_c),
++	SH_PFC_PIN_GROUP(msiof3_sync_c),
++	SH_PFC_PIN_GROUP(msiof3_txd_c),
++	SH_PFC_PIN_GROUP(msiof3_rxd_c),
++	SH_PFC_PIN_GROUP(msiof3_clk_d),
++	SH_PFC_PIN_GROUP(msiof3_sync_d),
++	SH_PFC_PIN_GROUP(msiof3_ss1_d),
++	SH_PFC_PIN_GROUP(msiof3_txd_d),
++	SH_PFC_PIN_GROUP(msiof3_rxd_d),
++	SH_PFC_PIN_GROUP(msiof3_clk_e),
++	SH_PFC_PIN_GROUP(msiof3_sync_e),
++	SH_PFC_PIN_GROUP(msiof3_ss1_e),
++	SH_PFC_PIN_GROUP(msiof3_ss2_e),
++	SH_PFC_PIN_GROUP(msiof3_txd_e),
++	SH_PFC_PIN_GROUP(msiof3_rxd_e),
+ 	SH_PFC_PIN_GROUP(scif0_data),
+ 	SH_PFC_PIN_GROUP(scif0_clk),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl),
+@@ -2022,6 +2819,117 @@ static const char * const intc_ex_groups[] = {
+ 	"intc_ex_irq5",
+ };
+ 
++static const char * const msiof0_groups[] = {
++	"msiof0_clk",
++	"msiof0_sync",
++	"msiof0_ss1",
++	"msiof0_ss2",
++	"msiof0_txd",
++	"msiof0_rxd",
++};
++
++static const char * const msiof1_groups[] = {
++	"msiof1_clk_a",
++	"msiof1_sync_a",
++	"msiof1_ss1_a",
++	"msiof1_ss2_a",
++	"msiof1_txd_a",
++	"msiof1_rxd_a",
++	"msiof1_clk_b",
++	"msiof1_sync_b",
++	"msiof1_ss1_b",
++	"msiof1_ss2_b",
++	"msiof1_txd_b",
++	"msiof1_rxd_b",
++	"msiof1_clk_c",
++	"msiof1_sync_c",
++	"msiof1_ss1_c",
++	"msiof1_ss2_c",
++	"msiof1_txd_c",
++	"msiof1_rxd_c",
++	"msiof1_clk_d",
++	"msiof1_sync_d",
++	"msiof1_ss1_d",
++	"msiof1_ss2_d",
++	"msiof1_txd_d",
++	"msiof1_rxd_d",
++	"msiof1_clk_e",
++	"msiof1_sync_e",
++	"msiof1_ss1_e",
++	"msiof1_ss2_e",
++	"msiof1_txd_e",
++	"msiof1_rxd_e",
++	"msiof1_clk_f",
++	"msiof1_sync_f",
++	"msiof1_ss1_f",
++	"msiof1_ss2_f",
++	"msiof1_txd_f",
++	"msiof1_rxd_f",
++	"msiof1_clk_g",
++	"msiof1_sync_g",
++	"msiof1_ss1_g",
++	"msiof1_ss2_g",
++	"msiof1_txd_g",
++	"msiof1_rxd_g",
++};
++
++static const char * const msiof2_groups[] = {
++	"msiof2_clk_a",
++	"msiof2_sync_a",
++	"msiof2_ss1_a",
++	"msiof2_ss2_a",
++	"msiof2_txd_a",
++	"msiof2_rxd_a",
++	"msiof2_clk_b",
++	"msiof2_sync_b",
++	"msiof2_ss1_b",
++	"msiof2_ss2_b",
++	"msiof2_txd_b",
++	"msiof2_rxd_b",
++	"msiof2_clk_c",
++	"msiof2_sync_c",
++	"msiof2_ss1_c",
++	"msiof2_ss2_c",
++	"msiof2_txd_c",
++	"msiof2_rxd_c",
++	"msiof2_clk_d",
++	"msiof2_sync_d",
++	"msiof2_ss1_d",
++	"msiof2_ss2_d",
++	"msiof2_txd_d",
++	"msiof2_rxd_d",
++};
++
++static const char * const msiof3_groups[] = {
++	"msiof3_clk_a",
++	"msiof3_sync_a",
++	"msiof3_ss1_a",
++	"msiof3_ss2_a",
++	"msiof3_txd_a",
++	"msiof3_rxd_a",
++	"msiof3_clk_b",
++	"msiof3_sync_b",
++	"msiof3_ss1_b",
++	"msiof3_ss2_b",
++	"msiof3_txd_b",
++	"msiof3_rxd_b",
++	"msiof3_clk_c",
++	"msiof3_sync_c",
++	"msiof3_txd_c",
++	"msiof3_rxd_c",
++	"msiof3_clk_d",
++	"msiof3_sync_d",
++	"msiof3_ss1_d",
++	"msiof3_txd_d",
++	"msiof3_rxd_d",
++	"msiof3_clk_e",
++	"msiof3_sync_e",
++	"msiof3_ss1_e",
++	"msiof3_ss2_e",
++	"msiof3_txd_e",
++	"msiof3_rxd_e",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data",
+ 	"scif0_clk",
+@@ -2086,6 +2994,10 @@ static const char * const usb30_groups[] = {
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(intc_ex),
++	SH_PFC_FUNCTION(msiof0),
++	SH_PFC_FUNCTION(msiof1),
++	SH_PFC_FUNCTION(msiof2),
++	SH_PFC_FUNCTION(msiof3),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/1243-pinctrl-sh-pfc-r8a7795-Fix-comment-for-MSIOF3-SS2_E-.patch b/patches/1243-pinctrl-sh-pfc-r8a7795-Fix-comment-for-MSIOF3-SS2_E-.patch
new file mode 100644
index 00000000000000..d561c0e555bd61
--- /dev/null
+++ b/patches/1243-pinctrl-sh-pfc-r8a7795-Fix-comment-for-MSIOF3-SS2_E-.patch
@@ -0,0 +1,32 @@
+From ffd0a92ead0f19b45ab078bee3855f6b1589ac84 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 22 Mar 2018 15:01:13 +0100
+Subject: [PATCH 1243/1795] pinctrl: sh-pfc: r8a7795: Fix comment for MSIOF3
+ SS2_E pin
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 37880512858e929d2bab952028149c169aaccdea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 7100a2dd65f8..34626898f757 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -3122,7 +3122,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
+ 	MSIOF3_SS1_E_MARK,
+ };
+ static const unsigned int msiof3_ss2_e_pins[] = {
+-	/* SS1 */
++	/* SS2 */
+ 	RCAR_GP_PIN(2, 0),
+ };
+ static const unsigned int msiof3_ss2_e_mux[] = {
+-- 
+2.19.0
+
diff --git a/patches/1244-pinctrl-sh-pfc-r8a7796-Fix-comment-for-MSIOF3-SS2_E-.patch b/patches/1244-pinctrl-sh-pfc-r8a7796-Fix-comment-for-MSIOF3-SS2_E-.patch
new file mode 100644
index 00000000000000..2dff976dd7fe2b
--- /dev/null
+++ b/patches/1244-pinctrl-sh-pfc-r8a7796-Fix-comment-for-MSIOF3-SS2_E-.patch
@@ -0,0 +1,32 @@
+From 11d3f308572a5604800d36bb01e2343999ac70fb Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 22 Mar 2018 15:01:53 +0100
+Subject: [PATCH 1244/1795] pinctrl: sh-pfc: r8a7796: Fix comment for MSIOF3
+ SS2_E pin
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit fff8e331ef2bbf4c79c555f8c313de23e2abb331)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 4bc5b1f820c1..764afa13a8c6 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -3122,7 +3122,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
+ 	MSIOF3_SS1_E_MARK,
+ };
+ static const unsigned int msiof3_ss2_e_pins[] = {
+-	/* SS1 */
++	/* SS2 */
+ 	RCAR_GP_PIN(2, 0),
+ };
+ static const unsigned int msiof3_ss2_e_mux[] = {
+-- 
+2.19.0
+
diff --git a/patches/1245-pinctrl-sh-pfc-r8a77965-Add-PWM-pins-groups-and-func.patch b/patches/1245-pinctrl-sh-pfc-r8a77965-Add-PWM-pins-groups-and-func.patch
new file mode 100644
index 00000000000000..fd5fed9f56d872
--- /dev/null
+++ b/patches/1245-pinctrl-sh-pfc-r8a77965-Add-PWM-pins-groups-and-func.patch
@@ -0,0 +1,209 @@
+From b493b7f86f5a8da73e9a226e780b9f46e4fcb79d Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 23 Mar 2018 20:31:46 +0900
+Subject: [PATCH 1245/1795] pinctrl: sh-pfc: r8a77965: Add PWM pins, groups and
+ functions
+
+This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
+R8A77965 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 54b7f2da9760f5324b659d89466dc416f312264f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 153 ++++++++++++++++++++++++++
+ 1 file changed, 153 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 54461ebd5db1..3771b2d10f39 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -2404,6 +2404,105 @@ static const unsigned int msiof3_rxd_e_mux[] = {
+ 	MSIOF3_RXD_E_MARK,
+ };
+ 
++/* - PWM0 --------------------------------------------------------------------*/
++static const unsigned int pwm0_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 6),
++};
++static const unsigned int pwm0_mux[] = {
++	PWM0_MARK,
++};
++/* - PWM1 --------------------------------------------------------------------*/
++static const unsigned int pwm1_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 7),
++};
++static const unsigned int pwm1_a_mux[] = {
++	PWM1_A_MARK,
++};
++static const unsigned int pwm1_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 8),
++};
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++/* - PWM2 --------------------------------------------------------------------*/
++static const unsigned int pwm2_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 8),
++};
++static const unsigned int pwm2_a_mux[] = {
++	PWM2_A_MARK,
++};
++static const unsigned int pwm2_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++/* - PWM3 --------------------------------------------------------------------*/
++static const unsigned int pwm3_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int pwm3_a_mux[] = {
++	PWM3_A_MARK,
++};
++static const unsigned int pwm3_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++/* - PWM4 --------------------------------------------------------------------*/
++static const unsigned int pwm4_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 1),
++};
++static const unsigned int pwm4_a_mux[] = {
++	PWM4_A_MARK,
++};
++static const unsigned int pwm4_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int pwm4_b_mux[] = {
++	PWM4_B_MARK,
++};
++/* - PWM5 --------------------------------------------------------------------*/
++static const unsigned int pwm5_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 2),
++};
++static const unsigned int pwm5_a_mux[] = {
++	PWM5_A_MARK,
++};
++static const unsigned int pwm5_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int pwm5_b_mux[] = {
++	PWM5_B_MARK,
++};
++/* - PWM6 --------------------------------------------------------------------*/
++static const unsigned int pwm6_a_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(1, 3),
++};
++static const unsigned int pwm6_a_mux[] = {
++	PWM6_A_MARK,
++};
++static const unsigned int pwm6_b_pins[] = {
++	/* PWM */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int pwm6_b_mux[] = {
++	PWM6_B_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_pins[] = {
+ 	/* RX, TX */
+@@ -2762,6 +2861,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(msiof3_ss2_e),
+ 	SH_PFC_PIN_GROUP(msiof3_txd_e),
+ 	SH_PFC_PIN_GROUP(msiof3_rxd_e),
++	SH_PFC_PIN_GROUP(pwm0),
++	SH_PFC_PIN_GROUP(pwm1_a),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm2_a),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm3_a),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm4_a),
++	SH_PFC_PIN_GROUP(pwm4_b),
++	SH_PFC_PIN_GROUP(pwm5_a),
++	SH_PFC_PIN_GROUP(pwm5_b),
++	SH_PFC_PIN_GROUP(pwm6_a),
++	SH_PFC_PIN_GROUP(pwm6_b),
+ 	SH_PFC_PIN_GROUP(scif0_data),
+ 	SH_PFC_PIN_GROUP(scif0_clk),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl),
+@@ -2930,6 +3042,40 @@ static const char * const msiof3_groups[] = {
+ 	"msiof3_rxd_e",
+ };
+ 
++static const char * const pwm0_groups[] = {
++	"pwm0",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1_a",
++	"pwm1_b",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2_a",
++	"pwm2_b",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3_a",
++	"pwm3_b",
++};
++
++static const char * const pwm4_groups[] = {
++	"pwm4_a",
++	"pwm4_b",
++};
++
++static const char * const pwm5_groups[] = {
++	"pwm5_a",
++	"pwm5_b",
++};
++
++static const char * const pwm6_groups[] = {
++	"pwm6_a",
++	"pwm6_b",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data",
+ 	"scif0_clk",
+@@ -2998,6 +3144,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(msiof1),
+ 	SH_PFC_FUNCTION(msiof2),
+ 	SH_PFC_FUNCTION(msiof3),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
++	SH_PFC_FUNCTION(pwm4),
++	SH_PFC_FUNCTION(pwm5),
++	SH_PFC_FUNCTION(pwm6),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/1246-dt-bindings-pinctrl-sh-pfc-Document-r8a77470-PFC-sup.patch b/patches/1246-dt-bindings-pinctrl-sh-pfc-Document-r8a77470-PFC-sup.patch
new file mode 100644
index 00000000000000..ff43a2ebf92c5b
--- /dev/null
+++ b/patches/1246-dt-bindings-pinctrl-sh-pfc-Document-r8a77470-PFC-sup.patch
@@ -0,0 +1,35 @@
+From d872aba57564cd41ab0a30f482d7886b7e8f630d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 4 Apr 2018 16:22:57 +0100
+Subject: [PATCH 1246/1795] dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC
+ support
+
+Document PFC support for the R8A77470 SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 98c1c1f08adfda0d24f3bef9614a7117ef0c5495)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt          | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index 892d8fd7b700..4f5fca121d2a 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -15,6 +15,7 @@ Required Properties:
+     - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+     - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+     - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
++    - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
+     - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
+     - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+     - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+-- 
+2.19.0
+
diff --git a/patches/1247-pinctrl-sh-pfc-r8a77980-Add-pin-I-O-voltage-control-.patch b/patches/1247-pinctrl-sh-pfc-r8a77980-Add-pin-I-O-voltage-control-.patch
new file mode 100644
index 00000000000000..77d339d282161c
--- /dev/null
+++ b/patches/1247-pinctrl-sh-pfc-r8a77980-Add-pin-I-O-voltage-control-.patch
@@ -0,0 +1,104 @@
+From d0aae17759008301822c3fe86940e8adfcb85685 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 19 Apr 2018 21:27:34 +0300
+Subject: [PATCH 1247/1795] pinctrl: sh-pfc: r8a77980: Add pin I/O voltage
+ control support
+
+Add the pin I/O voltage level control support to the R8A77980 PFC driver.
+
+Loosely based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit b374c90f0a64784b26b3dfee2d9ba936d9520ad7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 52 +++++++++++++++++++++++++--
+ 1 file changed, 49 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+index 84c8f1c2f1d1..3f6967331f64 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+@@ -19,10 +19,10 @@
+ #include "sh_pfc.h"
+ 
+ #define CPU_ALL_PORT(fn, sfx)	\
+-	PORT_GP_22(0, fn, sfx),	\
++	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
+ 	PORT_GP_28(1, fn, sfx),	\
+-	PORT_GP_30(2, fn, sfx),	\
+-	PORT_GP_17(3, fn, sfx),	\
++	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
++	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ 	PORT_GP_25(4, fn, sfx),	\
+ 	PORT_GP_15(5, fn, sfx)
+ 
+@@ -2779,8 +2779,53 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ 	{ },
+ };
+ 
++enum ioctrl_regs {
++	IOCTRL30,
++	IOCTRL31,
++	IOCTRL32,
++	IOCTRL33,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[IOCTRL30] = { 0xe6060380, },
++	[IOCTRL31] = { 0xe6060384, },
++	[IOCTRL32] = { 0xe6060388, },
++	[IOCTRL33] = { 0xe606038c, },
++	{ /* sentinel */ },
++};
++
++static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
++				   u32 *pocctrl)
++{
++	int bit = pin & 0x1f;
++
++	*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
++	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
++		return bit;
++	else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
++		return bit + 22;
++
++	*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
++	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
++		return bit - 10;
++	if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
++	    (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
++		return bit + 7;
++
++	*pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg;
++	if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
++		return pin - 25;
++
++	return -EINVAL;
++}
++
++static const struct sh_pfc_soc_operations pinmux_ops = {
++	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
++};
++
+ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+ 	.name = "r8a77980_pfc",
++	.ops = &pinmux_ops,
+ 	.unlock_reg = 0xe6060000, /* PMMR */
+ 
+ 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+@@ -2793,6 +2838,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+ 	.nr_functions = ARRAY_SIZE(pinmux_functions),
+ 
+ 	.cfg_regs = pinmux_config_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/1248-pinctrl-sh-pfc-r8a77970-Fix-pin-I-O-voltage-control-.patch b/patches/1248-pinctrl-sh-pfc-r8a77970-Fix-pin-I-O-voltage-control-.patch
new file mode 100644
index 00000000000000..d3ae1e90295495
--- /dev/null
+++ b/patches/1248-pinctrl-sh-pfc-r8a77970-Fix-pin-I-O-voltage-control-.patch
@@ -0,0 +1,93 @@
+From 371bad9f4b420290dbd859e78ed2fc4a062a6dbe Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 19 Apr 2018 21:52:28 +0300
+Subject: [PATCH 1248/1795] pinctrl: sh-pfc: r8a77970: Fix pin I/O voltage
+ control support
+
+I've included the pin I/O voltage control into the R8A77970 PFC driver but
+it was incomplete because:
+- SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly;
+- sh_pfc_soc_info::ioctrl_regs wasn't set at all...
+
+Fixes: b92ac66a1819 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit f9931a4d8718d6f0cb244ae673ffe51fa1067f25)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 32 ++++++++++++++++++++-------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+index b1bb7263532b..b02caf316711 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+@@ -21,13 +21,15 @@
+ #include "core.h"
+ #include "sh_pfc.h"
+ 
++#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
++
+ #define CPU_ALL_PORT(fn, sfx)						\
+-	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+-	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+-	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+-	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+-	PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+-	PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
++	PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
++	PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),				\
++	PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
++	PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
++	PORT_GP_CFG_6(4,  fn, sfx, CFG_FLAGS),				\
++	PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
+ /*
+  * F_() : just information
+  * FM() : macro for FN_xxx / xxx_MARK
+@@ -2382,18 +2384,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ 	{ },
+ };
+ 
++enum ioctrl_regs {
++	IOCTRL30,
++	IOCTRL31,
++	IOCTRL32,
++};
++
++static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
++	[IOCTRL30] = { 0xe6060380 },
++	[IOCTRL31] = { 0xe6060384 },
++	[IOCTRL32] = { 0xe6060388 },
++	{ /* sentinel */ },
++};
++
+ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ 				   u32 *pocctrl)
+ {
+ 	int bit = pin & 0x1f;
+ 
+-	*pocctrl = 0xe6060380;
++	*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ 	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ 		return bit;
+ 	if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+ 		return bit + 22;
+ 
+-	*pocctrl += 4;
++	*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
+ 	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ 		return bit - 10;
+ 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+@@ -2421,6 +2436,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
+ 	.nr_functions = ARRAY_SIZE(pinmux_functions),
+ 
+ 	.cfg_regs = pinmux_config_regs,
++	.ioctrl_regs = pinmux_ioctrl_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/1249-pinctrl-sh-pfc-r8a77965-Fixup-incorrect-SPDX-identif.patch b/patches/1249-pinctrl-sh-pfc-r8a77965-Fixup-incorrect-SPDX-identif.patch
new file mode 100644
index 00000000000000..d749dead25ea64
--- /dev/null
+++ b/patches/1249-pinctrl-sh-pfc-r8a77965-Fixup-incorrect-SPDX-identif.patch
@@ -0,0 +1,35 @@
+From ffb6a83f20301d542783849f577b73c327723743 Mon Sep 17 00:00:00 2001
+From: Thomas Gleixner <tglx@linutronix.de>
+Date: Mon, 23 Apr 2018 00:02:10 +0200
+Subject: [PATCH 1249/1795] pinctrl: sh-pfc: r8a77965: Fixup incorrect SPDX
+ identifier
+
+GPL-2. is not a valid SPDX identifier. Make it GPL-2.0
+
+Fixes: 490e687eb8b2 ("pinctrl: sh-pfc: Initial R-Car M3-N support")
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Cc: Rob Herring <robh@kernel.org>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 3a4d17457dc9d27e4901a087cb5f444b6d83705d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 3771b2d10f39..0a4a088ddaf9 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * R8A77965 processor support - PFC hardware block.
+  *
+-- 
+2.19.0
+
diff --git a/patches/1250-pinctrl-sh-pfc-r8a77965-Add-DU-RGB-output-pins-group.patch b/patches/1250-pinctrl-sh-pfc-r8a77965-Add-DU-RGB-output-pins-group.patch
new file mode 100644
index 00000000000000..a605c968c574ca
--- /dev/null
+++ b/patches/1250-pinctrl-sh-pfc-r8a77965-Add-DU-RGB-output-pins-group.patch
@@ -0,0 +1,180 @@
+From 6ef89cb0af50489db5e7b47e37489610f57864c6 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 17:57:13 +0100
+Subject: [PATCH 1250/1795] pinctrl: sh-pfc: r8a77965: Add DU RGB output pins,
+ groups and functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds pins, groups and functions for parallel RGB output
+signals from DU. The HDMI and TCON pins are added to separate groups.
+
+Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund
+<niklas.soderlund+renesas@ragnatech.se>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[Kieran: Rebase on top of tree]
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+
+(cherry picked from commit a73ab128c33c3c6b34a77f490eae54dcc4187320)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 116 ++++++++++++++++++++++++++
+ 1 file changed, 116 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 0a4a088ddaf9..43022afe6400 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1662,6 +1662,102 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
+ 	AVB_AVTP_CAPTURE_B_MARK,
+ };
+ 
++/* - DU --------------------------------------------------------------------- */
++static const unsigned int du_rgb666_pins[] = {
++	/* R[7:2], G[7:2], B[7:2] */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
++	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
++};
++
++static const unsigned int du_rgb666_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
++	DU_DR3_MARK, DU_DR2_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
++	DU_DG3_MARK, DU_DG2_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
++	DU_DB3_MARK, DU_DB2_MARK,
++};
++
++static const unsigned int du_rgb888_pins[] = {
++	/* R[7:0], G[7:0], B[7:0] */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
++	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
++	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
++	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
++	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
++	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
++	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
++	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
++};
++
++static const unsigned int du_rgb888_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
++	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
++	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
++	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
++	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
++	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
++};
++
++static const unsigned int du_clk_out_0_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(1, 27),
++};
++
++static const unsigned int du_clk_out_0_mux[] = {
++	DU_DOTCLKOUT0_MARK
++};
++
++static const unsigned int du_clk_out_1_pins[] = {
++	/* CLKOUT */
++	RCAR_GP_PIN(2, 3),
++};
++
++static const unsigned int du_clk_out_1_mux[] = {
++	DU_DOTCLKOUT1_MARK
++};
++
++static const unsigned int du_sync_pins[] = {
++	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
++	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
++};
++
++static const unsigned int du_sync_mux[] = {
++	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
++};
++
++static const unsigned int du_oddf_pins[] = {
++	/* EXDISP/EXODDF/EXCDE */
++	RCAR_GP_PIN(2, 2),
++};
++
++static const unsigned int du_oddf_mux[] = {
++	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
++};
++
++static const unsigned int du_cde_pins[] = {
++	/* CDE */
++	RCAR_GP_PIN(2, 0),
++};
++
++static const unsigned int du_cde_mux[] = {
++	DU_CDE_MARK,
++};
++
++static const unsigned int du_disp_pins[] = {
++	/* DISP */
++	RCAR_GP_PIN(2, 1),
++};
++
++static const unsigned int du_disp_mux[] = {
++	DU_DISP_MARK,
++};
++
+ /* - INTC-EX ---------------------------------------------------------------- */
+ static const unsigned int intc_ex_irq0_pins[] = {
+ 	/* IRQ0 */
+@@ -2756,6 +2852,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
++	SH_PFC_PIN_GROUP(du_rgb666),
++	SH_PFC_PIN_GROUP(du_rgb888),
++	SH_PFC_PIN_GROUP(du_clk_out_0),
++	SH_PFC_PIN_GROUP(du_clk_out_1),
++	SH_PFC_PIN_GROUP(du_sync),
++	SH_PFC_PIN_GROUP(du_oddf),
++	SH_PFC_PIN_GROUP(du_cde),
++	SH_PFC_PIN_GROUP(du_disp),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq0),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq1),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq2),
+@@ -2922,6 +3026,17 @@ static const char * const avb_groups[] = {
+ 	"avb_avtp_capture_b",
+ };
+ 
++static const char * const du_groups[] = {
++	"du_rgb666",
++	"du_rgb888",
++	"du_clk_out_0",
++	"du_clk_out_1",
++	"du_sync",
++	"du_oddf",
++	"du_cde",
++	"du_disp",
++};
++
+ static const char * const intc_ex_groups[] = {
+ 	"intc_ex_irq0",
+ 	"intc_ex_irq1",
+@@ -3139,6 +3254,7 @@ static const char * const usb30_groups[] = {
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(du),
+ 	SH_PFC_FUNCTION(intc_ex),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+-- 
+2.19.0
+
diff --git a/patches/1251-pinctrl-sh-pfc-r8a77965-Add-SDHI-pins-groups-and-fun.patch b/patches/1251-pinctrl-sh-pfc-r8a77965-Add-SDHI-pins-groups-and-fun.patch
new file mode 100644
index 00000000000000..ee62a53653c869
--- /dev/null
+++ b/patches/1251-pinctrl-sh-pfc-r8a77965-Add-SDHI-pins-groups-and-fun.patch
@@ -0,0 +1,383 @@
+From 798b66cb571f67ced897864a8612ae689356e77e Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Mon, 30 Apr 2018 04:48:14 +0900
+Subject: [PATCH 1251/1795] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups
+ and functions
+
+This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
+SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Tested-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 16688c8b8644ad594be7d38a9e16b05e32e1823a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 ++++++++++++++++++++++++++
+ 1 file changed, 326 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 43022afe6400..4d944e3c73e9 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -2810,6 +2810,264 @@ static const unsigned int scif_clk_b_mux[] = {
+ 	SCIF_CLK_B_MARK,
+ };
+ 
++/* - SDHI0 ------------------------------------------------------------------ */
++static const unsigned int sdhi0_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 2),
++};
++
++static const unsigned int sdhi0_data1_mux[] = {
++	SD0_DAT0_MARK,
++};
++
++static const unsigned int sdhi0_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++};
++
++static const unsigned int sdhi0_data4_mux[] = {
++	SD0_DAT0_MARK, SD0_DAT1_MARK,
++	SD0_DAT2_MARK, SD0_DAT3_MARK,
++};
++
++static const unsigned int sdhi0_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
++};
++
++static const unsigned int sdhi0_ctrl_mux[] = {
++	SD0_CLK_MARK, SD0_CMD_MARK,
++};
++
++static const unsigned int sdhi0_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 12),
++};
++
++static const unsigned int sdhi0_cd_mux[] = {
++	SD0_CD_MARK,
++};
++
++static const unsigned int sdhi0_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 13),
++};
++
++static const unsigned int sdhi0_wp_mux[] = {
++	SD0_WP_MARK,
++};
++
++/* - SDHI1 ------------------------------------------------------------------ */
++static const unsigned int sdhi1_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 8),
++};
++
++static const unsigned int sdhi1_data1_mux[] = {
++	SD1_DAT0_MARK,
++};
++
++static const unsigned int sdhi1_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++
++static const unsigned int sdhi1_data4_mux[] = {
++	SD1_DAT0_MARK, SD1_DAT1_MARK,
++	SD1_DAT2_MARK, SD1_DAT3_MARK,
++};
++
++static const unsigned int sdhi1_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++};
++
++static const unsigned int sdhi1_ctrl_mux[] = {
++	SD1_CLK_MARK, SD1_CMD_MARK,
++};
++
++static const unsigned int sdhi1_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 14),
++};
++
++static const unsigned int sdhi1_cd_mux[] = {
++	SD1_CD_MARK,
++};
++
++static const unsigned int sdhi1_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 15),
++};
++
++static const unsigned int sdhi1_wp_mux[] = {
++	SD1_WP_MARK,
++};
++
++/* - SDHI2 ------------------------------------------------------------------ */
++static const unsigned int sdhi2_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(4, 2),
++};
++
++static const unsigned int sdhi2_data1_mux[] = {
++	SD2_DAT0_MARK,
++};
++
++static const unsigned int sdhi2_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++
++static const unsigned int sdhi2_data4_mux[] = {
++	SD2_DAT0_MARK, SD2_DAT1_MARK,
++	SD2_DAT2_MARK, SD2_DAT3_MARK,
++};
++
++static const unsigned int sdhi2_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
++	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
++	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++
++static const unsigned int sdhi2_data8_mux[] = {
++	SD2_DAT0_MARK, SD2_DAT1_MARK,
++	SD2_DAT2_MARK, SD2_DAT3_MARK,
++	SD2_DAT4_MARK, SD2_DAT5_MARK,
++	SD2_DAT6_MARK, SD2_DAT7_MARK,
++};
++
++static const unsigned int sdhi2_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
++};
++
++static const unsigned int sdhi2_ctrl_mux[] = {
++	SD2_CLK_MARK, SD2_CMD_MARK,
++};
++
++static const unsigned int sdhi2_cd_a_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(4, 13),
++};
++
++static const unsigned int sdhi2_cd_a_mux[] = {
++	SD2_CD_A_MARK,
++};
++
++static const unsigned int sdhi2_cd_b_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(5, 10),
++};
++
++static const unsigned int sdhi2_cd_b_mux[] = {
++	SD2_CD_B_MARK,
++};
++
++static const unsigned int sdhi2_wp_a_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(4, 14),
++};
++
++static const unsigned int sdhi2_wp_a_mux[] = {
++	SD2_WP_A_MARK,
++};
++
++static const unsigned int sdhi2_wp_b_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(5, 11),
++};
++
++static const unsigned int sdhi2_wp_b_mux[] = {
++	SD2_WP_B_MARK,
++};
++
++static const unsigned int sdhi2_ds_pins[] = {
++	/* DS */
++	RCAR_GP_PIN(4, 6),
++};
++
++static const unsigned int sdhi2_ds_mux[] = {
++	SD2_DS_MARK,
++};
++
++/* - SDHI3 ------------------------------------------------------------------ */
++static const unsigned int sdhi3_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(4, 9),
++};
++
++static const unsigned int sdhi3_data1_mux[] = {
++	SD3_DAT0_MARK,
++};
++
++static const unsigned int sdhi3_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
++	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
++};
++
++static const unsigned int sdhi3_data4_mux[] = {
++	SD3_DAT0_MARK, SD3_DAT1_MARK,
++	SD3_DAT2_MARK, SD3_DAT3_MARK,
++};
++
++static const unsigned int sdhi3_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
++	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
++	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
++	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
++};
++
++static const unsigned int sdhi3_data8_mux[] = {
++	SD3_DAT0_MARK, SD3_DAT1_MARK,
++	SD3_DAT2_MARK, SD3_DAT3_MARK,
++	SD3_DAT4_MARK, SD3_DAT5_MARK,
++	SD3_DAT6_MARK, SD3_DAT7_MARK,
++};
++
++static const unsigned int sdhi3_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
++};
++
++static const unsigned int sdhi3_ctrl_mux[] = {
++	SD3_CLK_MARK, SD3_CMD_MARK,
++};
++
++static const unsigned int sdhi3_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(4, 15),
++};
++
++static const unsigned int sdhi3_cd_mux[] = {
++	SD3_CD_MARK,
++};
++
++static const unsigned int sdhi3_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(4, 16),
++};
++
++static const unsigned int sdhi3_wp_mux[] = {
++	SD3_WP_MARK,
++};
++
++static const unsigned int sdhi3_ds_pins[] = {
++	/* DS */
++	RCAR_GP_PIN(4, 17),
++};
++
++static const unsigned int sdhi3_ds_mux[] = {
++	SD3_DS_MARK,
++};
++
+ /* - USB0 ------------------------------------------------------------------- */
+ static const unsigned int usb0_pins[] = {
+ 	/* PWEN, OVC */
+@@ -3007,6 +3265,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif5_clk_b),
+ 	SH_PFC_PIN_GROUP(scif_clk_a),
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(sdhi0_data1),
++	SH_PFC_PIN_GROUP(sdhi0_data4),
++	SH_PFC_PIN_GROUP(sdhi0_ctrl),
++	SH_PFC_PIN_GROUP(sdhi0_cd),
++	SH_PFC_PIN_GROUP(sdhi0_wp),
++	SH_PFC_PIN_GROUP(sdhi1_data1),
++	SH_PFC_PIN_GROUP(sdhi1_data4),
++	SH_PFC_PIN_GROUP(sdhi1_ctrl),
++	SH_PFC_PIN_GROUP(sdhi1_cd),
++	SH_PFC_PIN_GROUP(sdhi1_wp),
++	SH_PFC_PIN_GROUP(sdhi2_data1),
++	SH_PFC_PIN_GROUP(sdhi2_data4),
++	SH_PFC_PIN_GROUP(sdhi2_data8),
++	SH_PFC_PIN_GROUP(sdhi2_ctrl),
++	SH_PFC_PIN_GROUP(sdhi2_cd_a),
++	SH_PFC_PIN_GROUP(sdhi2_wp_a),
++	SH_PFC_PIN_GROUP(sdhi2_cd_b),
++	SH_PFC_PIN_GROUP(sdhi2_wp_b),
++	SH_PFC_PIN_GROUP(sdhi2_ds),
++	SH_PFC_PIN_GROUP(sdhi3_data1),
++	SH_PFC_PIN_GROUP(sdhi3_data4),
++	SH_PFC_PIN_GROUP(sdhi3_data8),
++	SH_PFC_PIN_GROUP(sdhi3_ctrl),
++	SH_PFC_PIN_GROUP(sdhi3_cd),
++	SH_PFC_PIN_GROUP(sdhi3_wp),
++	SH_PFC_PIN_GROUP(sdhi3_ds),
+ 	SH_PFC_PIN_GROUP(usb0),
+ 	SH_PFC_PIN_GROUP(usb1),
+ 	SH_PFC_PIN_GROUP(usb30),
+@@ -3240,6 +3524,44 @@ static const char * const scif_clk_groups[] = {
+ 	"scif_clk_b",
+ };
+ 
++static const char * const sdhi0_groups[] = {
++	"sdhi0_data1",
++	"sdhi0_data4",
++	"sdhi0_ctrl",
++	"sdhi0_cd",
++	"sdhi0_wp",
++};
++
++static const char * const sdhi1_groups[] = {
++	"sdhi1_data1",
++	"sdhi1_data4",
++	"sdhi1_ctrl",
++	"sdhi1_cd",
++	"sdhi1_wp",
++};
++
++static const char * const sdhi2_groups[] = {
++	"sdhi2_data1",
++	"sdhi2_data4",
++	"sdhi2_data8",
++	"sdhi2_ctrl",
++	"sdhi2_cd_a",
++	"sdhi2_wp_a",
++	"sdhi2_cd_b",
++	"sdhi2_wp_b",
++	"sdhi2_ds",
++};
++
++static const char * const sdhi3_groups[] = {
++	"sdhi3_data1",
++	"sdhi3_data4",
++	"sdhi3_data8",
++	"sdhi3_ctrl",
++	"sdhi3_cd",
++	"sdhi3_wp",
++	"sdhi3_ds",
++};
++
+ static const char * const usb0_groups[] = {
+ 	"usb0",
+ };
+@@ -3274,6 +3596,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(scif4),
+ 	SH_PFC_FUNCTION(scif5),
+ 	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(sdhi0),
++	SH_PFC_FUNCTION(sdhi1),
++	SH_PFC_FUNCTION(sdhi2),
++	SH_PFC_FUNCTION(sdhi3),
+ 	SH_PFC_FUNCTION(usb0),
+ 	SH_PFC_FUNCTION(usb1),
+ 	SH_PFC_FUNCTION(usb30),
+-- 
+2.19.0
+
diff --git a/patches/1252-pinctrl-sh-pfc-Add-r8a77470-PFC-support.patch b/patches/1252-pinctrl-sh-pfc-Add-r8a77470-PFC-support.patch
new file mode 100644
index 00000000000000..d468e916c12969
--- /dev/null
+++ b/patches/1252-pinctrl-sh-pfc-Add-r8a77470-PFC-support.patch
@@ -0,0 +1,2433 @@
+From b473edd57b777a33920ba20e0884d9f7139c6592 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 12:03:08 +0100
+Subject: [PATCH 1252/1795] pinctrl: sh-pfc: Add r8a77470 PFC support
+
+Add PFC support for the R8A77470 SoC including pin groups for
+some on-chip devices such as SCIF and MMC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 73dacc3403436fc246258c0933e35b6e809640ac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/Kconfig        |    5 +
+ drivers/pinctrl/sh-pfc/Makefile       |    1 +
+ drivers/pinctrl/sh-pfc/core.c         |    6 +
+ drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 2343 +++++++++++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h       |    1 +
+ 5 files changed, 2356 insertions(+)
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index c11b789ec583..1d9b7e04c0c6 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -44,6 +44,11 @@ config PINCTRL_PFC_R8A7745
+         depends on ARCH_R8A7745
+         select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A77470
++        def_bool y
++        depends on ARCH_R8A77470
++        select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_R8A7778
+ 	def_bool y
+ 	depends on ARCH_R8A7778
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index 463775f28cf1..b486fcdf4573 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7743)	+= pfc-r8a7791.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7745)	+= pfc-r8a7794.o
++obj-$(CONFIG_PINCTRL_PFC_R8A77470)	+= pfc-r8a77470.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7779)	+= pfc-r8a7779.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7790)	+= pfc-r8a7790.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 74861b7b5b0d..b069fe3bf75d 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -503,6 +503,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 		.data = &r8a7745_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A77470
++	{
++		.compatible = "renesas,pfc-r8a77470",
++		.data = &r8a77470_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_R8A7778
+ 	{
+ 		.compatible = "renesas,pfc-r8a7778",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+new file mode 100644
+index 000000000000..9d3ed438ec7b
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+@@ -0,0 +1,2343 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * R8A77470 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <linux/kernel.h>
++
++#include "sh_pfc.h"
++
++#define CPU_ALL_PORT(fn, sfx)						\
++	PORT_GP_23(0, fn, sfx),						\
++	PORT_GP_23(1, fn, sfx),						\
++	PORT_GP_32(2, fn, sfx),						\
++	PORT_GP_17(3, fn, sfx),						\
++	PORT_GP_1(3, 27, fn, sfx),					\
++	PORT_GP_1(3, 28, fn, sfx),					\
++	PORT_GP_1(3, 29, fn, sfx),					\
++	PORT_GP_26(4, fn, sfx),						\
++	PORT_GP_32(5, fn, sfx)
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++
++	/* GPSR0 */
++	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
++	FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
++	FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
++	FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
++	FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
++	FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
++
++	/* GPSR1 */
++	FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
++	FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
++	FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
++	FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
++	FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
++
++	/* GPSR2 */
++	FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
++	FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
++	FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
++	FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
++	FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
++	FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
++	FN_IP7_31_28, FN_IP8_3_0,
++
++	/* GPSR3 */
++	FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
++	FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
++	FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
++	FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
++
++	/* GPSR4 */
++	FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
++	FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
++	FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
++	FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
++	FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
++	FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
++
++	/* GPSR5 */
++	FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
++	FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
++	FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
++	FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
++	FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
++	FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
++	FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
++
++	/* IPSR0 */
++	FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
++	FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
++	FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
++	FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
++	FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
++	FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
++	FN_SD0_CD, FN_CAN0_RX_A,
++	FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
++
++	/* IPSR1 */
++	FN_MMC0_D4, FN_SD1_CD,
++	FN_MMC0_D5, FN_SD1_WP,
++	FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
++	FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
++	FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
++	FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
++	FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
++	FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
++
++	/* IPSR2 */
++	FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
++	FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
++	FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
++	FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
++	FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
++	FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
++	FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
++	FN_D13,	FN_MSIOF2_SYNC_A, FN_RX4_C,
++
++	/* IPSR3 */
++	FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
++	FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
++	FN_QSPI0_SPCLK, FN_WE0_N,
++	FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
++	FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
++	FN_QSPI0_IO2, FN_CS0_N,
++	FN_QSPI0_IO3, FN_RD_N,
++	FN_QSPI0_SSL, FN_WE1_N,
++
++	/* IPSR4 */
++	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
++	FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
++	FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
++	FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
++	FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
++	FN_DU0_DR4, FN_RX1_D, FN_A4,
++	FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
++	FN_DU0_DR6, FN_RX2_C, FN_A6,
++
++	/* IPSR5 */
++	FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
++	FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
++	FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
++	FN_DU0_DG2, FN_RX4_D, FN_A10,
++	FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
++	FN_DU0_DG4, FN_HRX0_A, FN_A12,
++	FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
++	FN_DU0_DG6, FN_HRX1_C, FN_A14,
++
++	/* IPSR6 */
++	FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
++	FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
++	FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
++	FN_DU0_DB2, FN_HCTS0_N, FN_A18,
++	FN_DU0_DB3, FN_HRTS0_N, FN_A19,
++	FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
++	FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
++	FN_DU0_DB6, FN_A22,
++
++	/* IPSR7 */
++	FN_DU0_DB7, FN_A23,
++	FN_DU0_DOTCLKIN, FN_A24,
++	FN_DU0_DOTCLKOUT0, FN_A25,
++	FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
++	FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
++	FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
++	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
++	FN_DU0_DISP, FN_CAN1_RX_C,
++
++	/* IPSR8 */
++	FN_DU0_CDE, FN_CAN1_TX_C,
++	FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
++	FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
++	FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
++	FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
++	FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
++	FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
++	FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
++
++	/* IPSR9 */
++	FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
++	FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
++	FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
++	FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
++	FN_VI1_HSYNC_N,	FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
++	FN_VI1_VSYNC_N,	FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
++	FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
++	FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
++
++	/* IPSR10 */
++	FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
++	FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
++	FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
++	FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
++	FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
++	FN_SCL0_A, FN_RX0_C, FN_PWM5_A,	FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
++	FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
++	FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
++
++	/* IPSR11 */
++	FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
++	FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
++	FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
++	FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
++	FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
++	FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
++	FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
++	FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
++
++	/* IPSR12 */
++	FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
++	FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
++	FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
++	FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
++	FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
++	FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
++	FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
++	FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
++
++	/* IPSR13 */
++	FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
++	FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
++	FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
++	FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
++	FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
++	FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
++	FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
++	FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
++
++	/* IPSR14 */
++	FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
++	FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
++	FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
++	FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
++	FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
++	FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
++	FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
++	FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
++
++	/* IPSR15 */
++	FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
++	FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
++	FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
++	FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
++	FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
++	FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
++	FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
++	FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
++
++	/* IPSR16 */
++	FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
++	FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
++	FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B,	FN_VI0_R7,
++	FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
++	FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
++	FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
++	FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
++	FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
++
++	/* IPSR17 */
++	FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
++	FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
++	FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
++	FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
++	FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
++	FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
++	FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
++
++	/* MOD_SEL0 */
++	FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
++	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
++	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
++	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
++	FN_SEL_I2C04_0, FN_SEL_I2C04_1,	FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
++	FN_SEL_I2C03_0,	FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
++	FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
++	FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
++	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
++	FN_SEL_AVB_0, FN_SEL_AVB_1,
++
++	/* MOD_SEL1 */
++	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
++	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,	FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
++	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,	FN_SEL_SCIF4_4,
++	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
++	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
++	FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
++	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,	FN_SEL_SCIF1_3,
++	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,	FN_SEL_SCIF0_3,
++	FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
++	FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
++	FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
++	FN_SEL_RCN_0, FN_SEL_RCN_1,
++	FN_SEL_TMU2_0, FN_SEL_TMU2_1,
++	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
++	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
++	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
++
++	/* MOD_SEL2 */
++	FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
++	FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
++	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
++	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
++	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
++	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
++	FN_SEL_SSI5_0, FN_SEL_SSI5_1,
++	FN_SEL_SSI4_0, FN_SEL_SSI4_1,
++	FN_SEL_SSI2_0, FN_SEL_SSI2_1,
++	FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
++	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
++	PINMUX_FUNCTION_END,
++
++	PINMUX_MARK_BEGIN,
++
++	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
++	CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
++	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
++	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
++	MMC0_D7_MARK,
++
++	/* IPSR0 */
++	SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
++	SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
++	SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
++	SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
++	SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
++	SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
++	SD0_CD_MARK, CAN0_RX_A_MARK,
++	SD0_WP_MARK, IRQ7_MARK,	CAN0_TX_A_MARK,
++
++	/* IPSR1 */
++	MMC0_D4_MARK, SD1_CD_MARK,
++	MMC0_D5_MARK, SD1_WP_MARK,
++	D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK,	SSI_SDATA5_B_MARK,
++	D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
++	D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
++	D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
++	D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
++	D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
++
++	/* IPSR2 */
++	D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
++	D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
++	D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK,	PWM3_C_MARK,
++	D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
++	D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
++	D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
++	D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
++	D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
++
++	/* IPSR3 */
++	D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
++	D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
++	QSPI0_SPCLK_MARK, WE0_N_MARK,
++	QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
++	QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
++	QSPI0_IO2_MARK, CS0_N_MARK,
++	QSPI0_IO3_MARK, RD_N_MARK,
++	QSPI0_SSL_MARK, WE1_N_MARK,
++
++	/* IPSR4 */
++	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
++	DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
++	DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
++	DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
++	DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
++	DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
++	DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
++	DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
++
++	/* IPSR5 */
++	DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
++	DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
++	DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
++	DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
++	DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
++	DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
++	DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
++	DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
++
++	/* IPSR6 */
++	DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
++	DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
++	DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
++	DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
++	DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
++	DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
++	DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
++	DU0_DB6_MARK, A22_MARK,
++
++	/* IPSR7 */
++	DU0_DB7_MARK, A23_MARK,
++	DU0_DOTCLKIN_MARK, A24_MARK,
++	DU0_DOTCLKOUT0_MARK, A25_MARK,
++	DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
++	DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
++	DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
++	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
++	DU0_DISP_MARK, CAN1_RX_C_MARK,
++
++	/* IPSR8 */
++	DU0_CDE_MARK, CAN1_TX_C_MARK,
++	VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
++	VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
++	VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
++	VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
++	VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
++	VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
++	VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
++
++	/* IPSR9 */
++	VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
++	VI1_DATA7_MARK,	AVB_RXD6_MARK, ETH_TX_EN_MARK,
++	VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
++	VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
++	VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
++	VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
++	VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
++	VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
++
++	/* IPSR10 */
++	VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
++	VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
++	AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
++	AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
++	AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
++	SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
++	SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
++	SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
++
++	/* IPSR11 */
++	SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
++	MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
++	MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
++	MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
++	MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
++	MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
++	MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
++	HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
++
++	/* IPSR12 */
++	HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
++	HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
++	HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
++	SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
++	SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
++	SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
++	SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
++	SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
++
++	/* IPSR13 */
++	SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
++	SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
++	SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
++	RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
++	TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
++	SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
++	SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
++	SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
++
++	/* IPSR14 */
++	SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
++	SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
++	SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
++	SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
++	SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
++	SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
++	SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
++	SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
++
++	/* IPSR15 */
++	SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
++	SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
++	SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
++	SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
++	SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
++	SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
++	SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
++	SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
++
++	/* IPSR16 */
++	SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
++	SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
++	SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
++	SSI_WS1_A_MARK,	TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
++	SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
++	SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
++	SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
++	SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
++
++	/* IPSR17 */
++	SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
++	SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
++	SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
++	AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
++	AUDIO_CLKB_A_MARK, SDA0_B_MARK,	VI0_FIELD_MARK,
++	AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
++	AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
++
++	PINMUX_MARK_END,
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
++
++	PINMUX_SINGLE(USB0_PWEN),
++	PINMUX_SINGLE(USB0_OVC),
++	PINMUX_SINGLE(USB1_PWEN),
++	PINMUX_SINGLE(USB1_OVC),
++	PINMUX_SINGLE(CLKOUT),
++	PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
++	PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
++	PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
++	PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
++	PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
++	PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
++	PINMUX_SINGLE(MMC0_D6),
++	PINMUX_SINGLE(MMC0_D7),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
++	PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
++	PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
++	PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
++	PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
++	PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
++	PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
++	PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
++	PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
++	PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
++	PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
++	PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
++	PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
++	PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
++	PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
++	PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
++	PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
++	PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
++	PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
++	PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
++	PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
++	PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
++	PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
++	PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
++	PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
++	PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
++	PINMUX_IPSR_GPSR(IP1_11_8, D0),
++	PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
++	PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
++	PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
++	PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
++	PINMUX_IPSR_GPSR(IP1_15_12, D1),
++	PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
++	PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
++	PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
++	PINMUX_IPSR_GPSR(IP1_19_16, D2),
++	PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
++	PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
++	PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
++	PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
++	PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
++	PINMUX_IPSR_GPSR(IP1_23_20, D3),
++	PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
++	PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
++	PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
++	PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
++	PINMUX_IPSR_GPSR(IP1_27_24, D4),
++	PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
++	PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
++	PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
++	PINMUX_IPSR_GPSR(IP1_31_28, D5),
++	PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
++	PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
++	PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
++	PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0, D6),
++	PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
++	PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
++	PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
++	PINMUX_IPSR_GPSR(IP2_7_4, D7),
++	PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
++	PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
++	PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
++	PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
++	PINMUX_IPSR_GPSR(IP2_11_8, D8),
++	PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
++	PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
++	PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
++	PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
++	PINMUX_IPSR_GPSR(IP2_15_12, D9),
++	PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
++	PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
++	PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
++	PINMUX_IPSR_GPSR(IP2_19_16, D10),
++	PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
++	PINMUX_IPSR_GPSR(IP2_23_20, D11),
++	PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
++	PINMUX_IPSR_GPSR(IP2_27_24, D12),
++	PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
++	PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
++	PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
++	PINMUX_IPSR_GPSR(IP2_31_28, D13),
++	PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0, D14),
++	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
++	PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
++	PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
++	PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
++	PINMUX_IPSR_GPSR(IP3_7_4, D15),
++	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
++	PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
++	PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
++	PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
++	PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
++	PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
++	PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
++	PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
++	PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
++	PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
++	PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
++	PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
++	PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
++	PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
++	PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
++	PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
++	PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
++	PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
++	PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
++	PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
++	PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
++	PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
++	PINMUX_IPSR_GPSR(IP4_7_4, A0),
++	PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
++	PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
++	PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
++	PINMUX_IPSR_GPSR(IP4_11_8, A1),
++	PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
++	PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
++	PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
++	PINMUX_IPSR_GPSR(IP4_15_12, A2),
++	PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
++	PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
++	PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
++	PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
++	PINMUX_IPSR_GPSR(IP4_19_16, A3),
++	PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
++	PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
++	PINMUX_IPSR_GPSR(IP4_23_20, A4),
++	PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
++	PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
++	PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
++	PINMUX_IPSR_GPSR(IP4_27_24, A5),
++	PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
++	PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
++	PINMUX_IPSR_GPSR(IP4_31_28, A6),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
++	PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
++	PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
++	PINMUX_IPSR_GPSR(IP5_3_0, A7),
++	PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
++	PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
++	PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
++	PINMUX_IPSR_GPSR(IP5_7_4, A8),
++	PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
++	PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
++	PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
++	PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
++	PINMUX_IPSR_GPSR(IP5_11_8, A9),
++	PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
++	PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
++	PINMUX_IPSR_GPSR(IP5_15_12, A10),
++	PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
++	PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
++	PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
++	PINMUX_IPSR_GPSR(IP5_19_16, A11),
++	PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
++	PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP5_23_20, A12),
++	PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
++	PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
++	PINMUX_IPSR_GPSR(IP5_27_24, A13),
++	PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
++	PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
++	PINMUX_IPSR_GPSR(IP5_31_28, A14),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
++	PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
++	PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
++	PINMUX_IPSR_GPSR(IP6_3_0, A15),
++	PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
++	PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
++	PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
++	PINMUX_IPSR_GPSR(IP6_7_4, A16),
++	PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
++	PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
++	PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
++	PINMUX_IPSR_GPSR(IP6_11_8, A17),
++	PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
++	PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
++	PINMUX_IPSR_GPSR(IP6_15_12, A18),
++	PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
++	PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
++	PINMUX_IPSR_GPSR(IP6_19_16, A19),
++	PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
++	PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
++	PINMUX_IPSR_GPSR(IP6_23_20, A20),
++	PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
++	PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
++	PINMUX_IPSR_GPSR(IP6_27_24, A21),
++	PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
++	PINMUX_IPSR_GPSR(IP6_31_28, A22),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
++	PINMUX_IPSR_GPSR(IP7_3_0, A23),
++	PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
++	PINMUX_IPSR_GPSR(IP7_7_4, A24),
++	PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
++	PINMUX_IPSR_GPSR(IP7_11_8, A25),
++	PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
++	PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
++	PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
++	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
++	PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
++	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
++	PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
++	PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
++	PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
++	PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
++
++	/* IPSR8 */
++	PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
++	PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
++	PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
++	PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
++	PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
++	PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
++	PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
++	PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
++	PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
++	PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
++	PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
++	PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
++	PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
++	PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
++	PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
++	PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
++	PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
++	PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
++	PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
++	PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
++	PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
++	PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
++	PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
++
++	/* IPSR9 */
++	PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
++	PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
++	PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
++	PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
++	PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
++	PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
++	PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
++	PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
++	PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
++	PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
++	PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
++	PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
++	PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
++	PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
++	PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
++	PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
++	PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
++	PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
++	PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
++	PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
++	PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
++	PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
++	PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
++	PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
++	PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
++	PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
++	PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
++	PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
++	PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
++	PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
++
++	/* IPSR10 */
++	PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
++	PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
++	PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
++	PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
++	PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
++	PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
++	PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
++	PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
++	PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
++	PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
++	PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
++	PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
++	PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
++	PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
++	PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
++	PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
++	PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
++	PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
++	PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
++	PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
++	PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
++	PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
++	PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
++	PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
++	PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
++	PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
++	PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
++	PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
++	PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
++	PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
++	PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
++	PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
++	PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
++	PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
++	PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
++	PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
++	PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
++	PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
++	PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
++	PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
++	PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
++
++	/* IPSR11 */
++	PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
++	PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
++	PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
++	PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
++	PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
++	PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
++	PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
++	PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
++	PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
++	PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
++	PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
++	PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
++	PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
++	PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
++	PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
++	PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
++	PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
++	PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
++	PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
++	PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
++	PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
++	PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
++	PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
++	PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
++	PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
++	PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
++	PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
++	PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
++	PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
++	PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
++	PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
++	PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
++	PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
++	PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
++	PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
++	PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
++
++	/* IPSR12 */
++	PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
++	PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
++	PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
++	PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
++	PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
++	PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
++	PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
++	PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
++	PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
++	PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
++	PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
++	PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
++	PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
++	PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
++	PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
++	PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
++	PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
++	PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
++	PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
++	PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
++	PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
++	PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
++	PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
++	PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
++	PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
++	PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
++	PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
++	PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
++	PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
++	PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
++	PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
++	PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
++	PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
++
++	/* IPSR13 */
++	PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
++	PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
++	PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
++	PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
++	PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
++	PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
++	PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
++	PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
++	PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
++	PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
++	PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
++	PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
++	PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
++	PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
++	PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
++	PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
++	PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
++	PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
++	PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
++	PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
++	PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
++	PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
++	PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
++	PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
++	PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
++	PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
++	PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
++	PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
++	PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
++	PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
++	PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
++	PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
++	PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
++
++	/* IPSR14 */
++	PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
++	PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
++	PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
++	PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
++	PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
++	PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
++	PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
++	PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
++	PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
++	PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
++	PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
++	PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
++	PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
++	PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
++	PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
++	PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
++	PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
++	PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
++	PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
++	PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
++	PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
++	PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
++	PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
++	PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
++	PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
++
++	/* IPSR15 */
++	PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
++	PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
++	PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
++	PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
++	PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
++	PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
++	PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
++	PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
++	PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
++	PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
++	PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
++	PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
++	PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
++	PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
++	PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
++	PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
++	PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
++	PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
++	PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
++	PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
++	PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
++	PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
++	PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
++	PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
++	PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
++	PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
++	PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
++	PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
++	PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
++	PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
++
++	/* IPSR16 */
++	PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
++	PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
++	PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
++	PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
++	PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
++	PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
++	PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
++	PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
++	PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
++	PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
++	PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
++	PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
++	PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
++	PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
++	PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
++	PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
++	PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
++	PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
++	PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
++	PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
++	PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
++	PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
++	PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
++	PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
++	PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
++	PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
++	PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
++	PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
++	PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
++	PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
++	PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
++	PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
++	PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
++
++	/* IPSR17 */
++	PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
++	PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
++	PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
++	PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
++	PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
++	PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
++	PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
++	PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
++	PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
++	PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
++	PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
++	PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
++	PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
++	PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
++	PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
++	PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
++	PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
++	PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
++	PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
++	PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
++	PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
++	PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
++};
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++};
++
++/* - MMC -------------------------------------------------------------------- */
++static const unsigned int mmc_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(0, 15),
++};
++static const unsigned int mmc_data1_mux[] = {
++	MMC0_D0_SDHI1_D0_MARK,
++};
++static const unsigned int mmc_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
++};
++static const unsigned int mmc_data4_mux[] = {
++	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
++	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
++};
++static const unsigned int mmc_data8_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
++	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
++	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
++};
++static const unsigned int mmc_data8_mux[] = {
++	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
++	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
++	MMC0_D4_MARK, MMC0_D5_MARK,
++	MMC0_D6_MARK, MMC0_D7_MARK,
++};
++static const unsigned int mmc_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int mmc_ctrl_mux[] = {
++	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
++};
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
++};
++static const unsigned int scif0_data_a_mux[] = {
++	RX0_A_MARK, TX0_A_MARK,
++};
++static const unsigned int scif0_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
++};
++static const unsigned int scif0_data_b_mux[] = {
++	RX0_B_MARK, TX0_B_MARK,
++};
++static const unsigned int scif0_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
++};
++static const unsigned int scif0_data_c_mux[] = {
++	RX0_C_MARK, TX0_C_MARK,
++};
++static const unsigned int scif0_data_d_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int scif0_data_d_mux[] = {
++	RX0_D_MARK, TX0_D_MARK,
++};
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
++};
++static const unsigned int scif1_data_a_mux[] = {
++	RX1_A_MARK, TX1_A_MARK,
++};
++static const unsigned int scif1_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 15),
++};
++static const unsigned int scif1_clk_a_mux[] = {
++	SCIF1_SCK_A_MARK,
++};
++static const unsigned int scif1_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
++};
++static const unsigned int scif1_data_b_mux[] = {
++	RX1_B_MARK, TX1_B_MARK,
++};
++static const unsigned int scif1_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 18),
++};
++static const unsigned int scif1_clk_b_mux[] = {
++	SCIF1_SCK_B_MARK,
++};
++static const unsigned int scif1_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
++};
++static const unsigned int scif1_data_c_mux[] = {
++	RX1_C_MARK, TX1_C_MARK,
++};
++static const unsigned int scif1_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 7),
++};
++static const unsigned int scif1_clk_c_mux[] = {
++	SCIF1_SCK_C_MARK,
++};
++static const unsigned int scif1_data_d_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++};
++static const unsigned int scif1_data_d_mux[] = {
++	RX1_D_MARK, TX1_D_MARK,
++};
++/* - SCIF2 ------------------------------------------------------------------ */
++static const unsigned int scif2_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
++};
++static const unsigned int scif2_data_a_mux[] = {
++	RX2_A_MARK, TX2_A_MARK,
++};
++static const unsigned int scif2_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 20),
++};
++static const unsigned int scif2_clk_a_mux[] = {
++	SCIF2_SCK_A_MARK,
++};
++static const unsigned int scif2_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
++};
++static const unsigned int scif2_data_b_mux[] = {
++	RX2_B_MARK, TX2_B_MARK,
++};
++static const unsigned int scif2_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 27),
++};
++static const unsigned int scif2_clk_b_mux[] = {
++	SCIF2_SCK_B_MARK,
++};
++static const unsigned int scif2_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++};
++static const unsigned int scif2_data_c_mux[] = {
++	RX2_C_MARK, TX2_C_MARK,
++};
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
++};
++static const unsigned int scif3_data_a_mux[] = {
++	RX3_A_MARK, TX3_A_MARK,
++};
++static const unsigned int scif3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 21),
++};
++static const unsigned int scif3_clk_mux[] = {
++	SCIF3_SCK_MARK,
++};
++static const unsigned int scif3_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int scif3_data_b_mux[] = {
++	RX3_B_MARK, TX3_B_MARK,
++};
++static const unsigned int scif3_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
++};
++static const unsigned int scif3_data_c_mux[] = {
++	RX3_C_MARK, TX3_C_MARK,
++};
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
++};
++static const unsigned int scif4_data_a_mux[] = {
++	RX4_A_MARK, TX4_A_MARK,
++};
++static const unsigned int scif4_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
++};
++static const unsigned int scif4_data_b_mux[] = {
++	RX4_B_MARK, TX4_B_MARK,
++};
++static const unsigned int scif4_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
++};
++static const unsigned int scif4_data_c_mux[] = {
++	RX4_C_MARK, TX4_C_MARK,
++};
++static const unsigned int scif4_data_d_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++};
++static const unsigned int scif4_data_d_mux[] = {
++	RX4_D_MARK, TX4_D_MARK,
++};
++static const unsigned int scif4_data_e_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
++};
++static const unsigned int scif4_data_e_mux[] = {
++	RX4_E_MARK, TX4_E_MARK,
++};
++/* - SCIF5 ------------------------------------------------------------------ */
++static const unsigned int scif5_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int scif5_data_a_mux[] = {
++	RX5_A_MARK, TX5_A_MARK,
++};
++static const unsigned int scif5_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
++};
++static const unsigned int scif5_data_b_mux[] = {
++	RX5_B_MARK, TX5_B_MARK,
++};
++static const unsigned int scif5_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
++};
++static const unsigned int scif5_data_c_mux[] = {
++	RX5_C_MARK, TX5_C_MARK,
++};
++static const unsigned int scif5_data_d_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
++};
++static const unsigned int scif5_data_d_mux[] = {
++	RX5_D_MARK, TX5_D_MARK,
++};
++static const unsigned int scif5_data_e_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
++};
++static const unsigned int scif5_data_e_mux[] = {
++	RX5_E_MARK, TX5_E_MARK,
++};
++static const unsigned int scif5_data_f_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
++};
++static const unsigned int scif5_data_f_mux[] = {
++	RX5_F_MARK, TX5_F_MARK,
++};
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(3, 29),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(mmc_data1),
++	SH_PFC_PIN_GROUP(mmc_data4),
++	SH_PFC_PIN_GROUP(mmc_data8),
++	SH_PFC_PIN_GROUP(mmc_ctrl),
++	SH_PFC_PIN_GROUP(scif0_data_a),
++	SH_PFC_PIN_GROUP(scif0_data_b),
++	SH_PFC_PIN_GROUP(scif0_data_c),
++	SH_PFC_PIN_GROUP(scif0_data_d),
++	SH_PFC_PIN_GROUP(scif1_data_a),
++	SH_PFC_PIN_GROUP(scif1_clk_a),
++	SH_PFC_PIN_GROUP(scif1_data_b),
++	SH_PFC_PIN_GROUP(scif1_clk_b),
++	SH_PFC_PIN_GROUP(scif1_data_c),
++	SH_PFC_PIN_GROUP(scif1_clk_c),
++	SH_PFC_PIN_GROUP(scif1_data_d),
++	SH_PFC_PIN_GROUP(scif2_data_a),
++	SH_PFC_PIN_GROUP(scif2_clk_a),
++	SH_PFC_PIN_GROUP(scif2_data_b),
++	SH_PFC_PIN_GROUP(scif2_clk_b),
++	SH_PFC_PIN_GROUP(scif2_data_c),
++	SH_PFC_PIN_GROUP(scif3_data_a),
++	SH_PFC_PIN_GROUP(scif3_clk),
++	SH_PFC_PIN_GROUP(scif3_data_b),
++	SH_PFC_PIN_GROUP(scif3_data_c),
++	SH_PFC_PIN_GROUP(scif4_data_a),
++	SH_PFC_PIN_GROUP(scif4_data_b),
++	SH_PFC_PIN_GROUP(scif4_data_c),
++	SH_PFC_PIN_GROUP(scif4_data_d),
++	SH_PFC_PIN_GROUP(scif4_data_e),
++	SH_PFC_PIN_GROUP(scif5_data_a),
++	SH_PFC_PIN_GROUP(scif5_data_b),
++	SH_PFC_PIN_GROUP(scif5_data_c),
++	SH_PFC_PIN_GROUP(scif5_data_d),
++	SH_PFC_PIN_GROUP(scif5_data_e),
++	SH_PFC_PIN_GROUP(scif5_data_f),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++};
++
++static const char * const mmc_groups[] = {
++	"mmc_data1",
++	"mmc_data4",
++	"mmc_data8",
++	"mmc_ctrl",
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data_a",
++	"scif0_data_b",
++	"scif0_data_c",
++	"scif0_data_d",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data_a",
++	"scif1_clk_a",
++	"scif1_data_b",
++	"scif1_clk_b",
++	"scif1_data_c",
++	"scif1_clk_c",
++	"scif1_data_d",
++};
++
++static const char * const scif2_groups[] = {
++	"scif2_data_a",
++	"scif2_clk_a",
++	"scif2_data_b",
++	"scif2_clk_b",
++	"scif2_data_c",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data_a",
++	"scif3_clk",
++	"scif3_data_b",
++	"scif3_data_c",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data_a",
++	"scif4_data_b",
++	"scif4_data_c",
++	"scif4_data_d",
++	"scif4_data_e",
++};
++
++static const char * const scif5_groups[] = {
++	"scif5_data_a",
++	"scif5_data_b",
++	"scif5_data_c",
++	"scif5_data_d",
++	"scif5_data_e",
++	"scif5_data_f",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(mmc),
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif2),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(scif5),
++	SH_PFC_FUNCTION(scif_clk),
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_22_FN, FN_MMC0_D7,
++		GP_0_21_FN, FN_MMC0_D6,
++		GP_0_20_FN, FN_IP1_7_4,
++		GP_0_19_FN, FN_IP1_3_0,
++		GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
++		GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
++		GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
++		GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
++		GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
++		GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
++		GP_0_12_FN, FN_IP0_31_28,
++		GP_0_11_FN, FN_IP0_27_24,
++		GP_0_10_FN, FN_IP0_23_20,
++		GP_0_9_FN, FN_IP0_19_16,
++		GP_0_8_FN, FN_IP0_15_12,
++		GP_0_7_FN, FN_IP0_11_8,
++		GP_0_6_FN, FN_IP0_7_4,
++		GP_0_5_FN, FN_IP0_3_0,
++		GP_0_4_FN, FN_CLKOUT,
++		GP_0_3_FN, FN_USB1_OVC,
++		GP_0_2_FN, FN_USB1_PWEN,
++		GP_0_1_FN, FN_USB0_OVC,
++		GP_0_0_FN, FN_USB0_PWEN, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_22_FN, FN_IP4_3_0,
++		GP_1_21_FN, FN_IP3_31_28,
++		GP_1_20_FN, FN_IP3_27_24,
++		GP_1_19_FN, FN_IP3_23_20,
++		GP_1_18_FN, FN_IP3_19_16,
++		GP_1_17_FN, FN_IP3_15_12,
++		GP_1_16_FN, FN_IP3_11_8,
++		GP_1_15_FN, FN_IP3_7_4,
++		GP_1_14_FN, FN_IP3_3_0,
++		GP_1_13_FN, FN_IP2_31_28,
++		GP_1_12_FN, FN_IP2_27_24,
++		GP_1_11_FN, FN_IP2_23_20,
++		GP_1_10_FN, FN_IP2_19_16,
++		GP_1_9_FN, FN_IP2_15_12,
++		GP_1_8_FN, FN_IP2_11_8,
++		GP_1_7_FN, FN_IP2_7_4,
++		GP_1_6_FN, FN_IP2_3_0,
++		GP_1_5_FN, FN_IP1_31_28,
++		GP_1_4_FN, FN_IP1_27_24,
++		GP_1_3_FN, FN_IP1_23_20,
++		GP_1_2_FN, FN_IP1_19_16,
++		GP_1_1_FN, FN_IP1_15_12,
++		GP_1_0_FN, FN_IP1_11_8, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
++		GP_2_31_FN, FN_IP8_3_0,
++		GP_2_30_FN, FN_IP7_31_28,
++		GP_2_29_FN, FN_IP7_27_24,
++		GP_2_28_FN, FN_IP7_23_20,
++		GP_2_27_FN, FN_IP7_19_16,
++		GP_2_26_FN, FN_IP7_15_12,
++		GP_2_25_FN, FN_IP7_11_8,
++		GP_2_24_FN, FN_IP7_7_4,
++		GP_2_23_FN, FN_IP7_3_0,
++		GP_2_22_FN, FN_IP6_31_28,
++		GP_2_21_FN, FN_IP6_27_24,
++		GP_2_20_FN, FN_IP6_23_20,
++		GP_2_19_FN, FN_IP6_19_16,
++		GP_2_18_FN, FN_IP6_15_12,
++		GP_2_17_FN, FN_IP6_11_8,
++		GP_2_16_FN, FN_IP6_7_4,
++		GP_2_15_FN, FN_IP6_3_0,
++		GP_2_14_FN, FN_IP5_31_28,
++		GP_2_13_FN, FN_IP5_27_24,
++		GP_2_12_FN, FN_IP5_23_20,
++		GP_2_11_FN, FN_IP5_19_16,
++		GP_2_10_FN, FN_IP5_15_12,
++		GP_2_9_FN, FN_IP5_11_8,
++		GP_2_8_FN, FN_IP5_7_4,
++		GP_2_7_FN, FN_IP5_3_0,
++		GP_2_6_FN, FN_IP4_31_28,
++		GP_2_5_FN, FN_IP4_27_24,
++		GP_2_4_FN, FN_IP4_23_20,
++		GP_2_3_FN, FN_IP4_19_16,
++		GP_2_2_FN, FN_IP4_15_12,
++		GP_2_1_FN, FN_IP4_11_8,
++		GP_2_0_FN, FN_IP4_7_4, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
++		0, 0,
++		0, 0,
++		GP_3_29_FN, FN_IP10_19_16,
++		GP_3_28_FN, FN_IP10_15_12,
++		GP_3_27_FN, FN_IP10_11_8,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_FN, FN_IP10_7_4,
++		GP_3_15_FN, FN_IP10_3_0,
++		GP_3_14_FN, FN_IP9_31_28,
++		GP_3_13_FN, FN_IP9_27_24,
++		GP_3_12_FN, FN_IP9_23_20,
++		GP_3_11_FN, FN_IP9_19_16,
++		GP_3_10_FN, FN_IP9_15_12,
++		GP_3_9_FN, FN_IP9_11_8,
++		GP_3_8_FN, FN_IP9_7_4,
++		GP_3_7_FN, FN_IP9_3_0,
++		GP_3_6_FN, FN_IP8_31_28,
++		GP_3_5_FN, FN_IP8_27_24,
++		GP_3_4_FN, FN_IP8_23_20,
++		GP_3_3_FN, FN_IP8_19_16,
++		GP_3_2_FN, FN_IP8_15_12,
++		GP_3_1_FN, FN_IP8_11_8,
++		GP_3_0_FN, FN_IP8_7_4, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_25_FN, FN_IP13_27_24,
++		GP_4_24_FN, FN_IP13_23_20,
++		GP_4_23_FN, FN_IP13_19_16,
++		GP_4_22_FN, FN_IP13_15_12,
++		GP_4_21_FN, FN_IP13_11_8,
++		GP_4_20_FN, FN_IP13_7_4,
++		GP_4_19_FN, FN_IP13_3_0,
++		GP_4_18_FN, FN_IP12_31_28,
++		GP_4_17_FN, FN_IP12_27_24,
++		GP_4_16_FN, FN_IP12_23_20,
++		GP_4_15_FN, FN_IP12_19_16,
++		GP_4_14_FN, FN_IP12_15_12,
++		GP_4_13_FN, FN_IP12_11_8,
++		GP_4_12_FN, FN_IP12_7_4,
++		GP_4_11_FN, FN_IP12_3_0,
++		GP_4_10_FN, FN_IP11_31_28,
++		GP_4_9_FN, FN_IP11_27_24,
++		GP_4_8_FN, FN_IP11_23_20,
++		GP_4_7_FN, FN_IP11_19_16,
++		GP_4_6_FN, FN_IP11_15_12,
++		GP_4_5_FN, FN_IP11_11_8,
++		GP_4_4_FN, FN_IP11_7_4,
++		GP_4_3_FN, FN_IP11_3_0,
++		GP_4_2_FN, FN_IP10_31_28,
++		GP_4_1_FN, FN_IP10_27_24,
++		GP_4_0_FN, FN_IP10_23_20, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
++		GP_5_31_FN, FN_IP17_27_24,
++		GP_5_30_FN, FN_IP17_23_20,
++		GP_5_29_FN, FN_IP17_19_16,
++		GP_5_28_FN, FN_IP17_15_12,
++		GP_5_27_FN, FN_IP17_11_8,
++		GP_5_26_FN, FN_IP17_7_4,
++		GP_5_25_FN, FN_IP17_3_0,
++		GP_5_24_FN, FN_IP16_31_28,
++		GP_5_23_FN, FN_IP16_27_24,
++		GP_5_22_FN, FN_IP16_23_20,
++		GP_5_21_FN, FN_IP16_19_16,
++		GP_5_20_FN, FN_IP16_15_12,
++		GP_5_19_FN, FN_IP16_11_8,
++		GP_5_18_FN, FN_IP16_7_4,
++		GP_5_17_FN, FN_IP16_3_0,
++		GP_5_16_FN, FN_IP15_31_28,
++		GP_5_15_FN, FN_IP15_27_24,
++		GP_5_14_FN, FN_IP15_23_20,
++		GP_5_13_FN, FN_IP15_19_16,
++		GP_5_12_FN, FN_IP15_15_12,
++		GP_5_11_FN, FN_IP15_11_8,
++		GP_5_10_FN, FN_IP15_7_4,
++		GP_5_9_FN, FN_IP15_3_0,
++		GP_5_8_FN, FN_IP14_31_28,
++		GP_5_7_FN, FN_IP14_27_24,
++		GP_5_6_FN, FN_IP14_23_20,
++		GP_5_5_FN, FN_IP14_19_16,
++		GP_5_4_FN, FN_IP14_15_12,
++		GP_5_3_FN, FN_IP14_11_8,
++		GP_5_2_FN, FN_IP14_7_4,
++		GP_5_1_FN, FN_IP14_3_0,
++		GP_5_0_FN, FN_IP13_31_28, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP0_31_28 [4] */
++		FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_27_24 [4] */
++		FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_23_20 [4] */
++		FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_19_16 [4] */
++		FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_15_12 [4] */
++		FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_11_8 [4] */
++		FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_7_4 [4] */
++		FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP0_3_0 [4] */
++		FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP1_31_28 [4] */
++		FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_27_24 [4] */
++		FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_23_20 [4] */
++		FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
++		FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_19_16 [4] */
++		FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
++		FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_15_12 [4] */
++		FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
++		FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_11_8 [4] */
++		FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
++		FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_7_4 [4] */
++		FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP1_3_0 [4] */
++		FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP2_31_28 [4] */
++		FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP2_27_24 [4] */
++		FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP2_23_20 [4] */
++		FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP2_19_16 [4] */
++		FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP2_15_12 [4] */
++		FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP2_11_8 [4] */
++		FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP2_7_4 [4] */
++		FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP2_3_0 [4] */
++		FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP3_31_28 [4] */
++		FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP3_27_24 [4] */
++		FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP3_23_20 [4] */
++		FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP3_19_16 [4] */
++		FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IP3_15_12 [4] */
++		FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0,
++		/* IP3_11_8 [4] */
++		FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP3_7_4 [4] */
++		FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
++		FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP3_3_0 [4] */
++		FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
++		0, FN_AVB_AVTP_CAPTURE_A,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP4_31_28 [4] */
++		FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_27_24 [4] */
++		FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_23_20 [4] */
++		FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP4_19_16 [4] */
++		FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
++		FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_15_12 [4] */
++		FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_11_8 [4] */
++		FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_7_4 [4] */
++		FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP4_3_0 [4] */
++		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP5_31_28 [4] */
++		FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14,  0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP5_27_24 [4] */
++		FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP5_23_20 [4] */
++		FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP5_19_16 [4] */
++		FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP5_15_12 [4] */
++		FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP5_11_8 [4] */
++		FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
++		FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP5_7_4 [4] */
++		FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP5_3_0 [4] */
++		FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP6_31_28 [4] */
++		FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP6_27_24 [4] */
++		FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
++		FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP6_23_20 [4] */
++		FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
++		FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP6_19_16 [4] */
++		FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP6_15_12 [4] */
++		FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP6_11_8 [4] */
++		FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP6_7_4 [4] */
++		FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP6_3_0 [4] */
++		FN_DU0_DG7, 0, FN_HTX1_C, 0,  FN_PWM6_B, 0, FN_A15,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP7_31_28 [4] */
++		FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP7_27_24 [4] */
++		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
++		0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP7_23_20 [4] */
++		FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
++		0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP7_19_16 [4] */
++		FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
++		0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP7_15_12 [4] */
++		FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
++		FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP7_11_8 [4] */
++		FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP7_7_4 [4] */
++		FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP7_3_0 [4] */
++		FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP8_31_28 [4] */
++		FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP8_27_24 [4] */
++		FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP8_23_20 [4] */
++		FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP8_19_16 [4] */
++		FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP8_15_12 [4] */
++		FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP8_11_8 [4] */
++		FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP8_7_4 [4] */
++		FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP8_3_0 [4] */
++		FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP9_31_28 [4] */
++		FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP9_27_24 [4] */
++		FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP9_23_20 [4] */
++		FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
++		FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP9_19_16 [4] */
++		FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
++		FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP9_15_12 [4] */
++		FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP9_11_8 [4] */
++		FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP9_7_4 [4] */
++		FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP9_3_0 [4] */
++		FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP10_31_28 [4] */
++		FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
++		FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP10_27_24 [4] */
++		FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
++		FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP10_23_20 [4] */
++		FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
++		FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP10_19_16 [4] */
++		FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
++		FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP10_15_12 [4] */
++		FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
++		FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP10_11_8 [4] */
++		FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
++		FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP10_7_4 [4] */
++		FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0,
++		/* IP10_3_0 [4] */
++		FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP11_31_28 [4] */
++		FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_27_24 [4] */
++		FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
++		FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_23_20 [4] */
++		FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
++		FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_19_16 [4] */
++		FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
++		0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IP11_15_12 [4] */
++		FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
++		0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_11_8 [4] */
++		FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
++		FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_7_4 [4] */
++		FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
++		FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP11_3_0 [4] */
++		FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
++		FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP12_31_28 [4] */
++		FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_27_24 [4] */
++		FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_23_20 [4] */
++		FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
++		FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_19_16 [4] */
++		FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
++		FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_15_12 [4] */
++		FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_11_8 [4] */
++		FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_7_4 [4] */
++		FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP12_3_0 [4] */
++		FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP13_31_28 [4] */
++		FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP13_27_24 [4] */
++		FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP13_23_20 [4] */
++		FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
++		FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP13_19_16 [4] */
++		FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
++		FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP13_15_12 [4] */
++		FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
++		FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0,
++		/* IP13_11_8 [4] */
++		FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP13_7_4 [4] */
++		FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP13_3_0 [4] */
++		FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP14_31_28 [4] */
++		FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
++		FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP14_27_24 [4] */
++		FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0,
++		/* IP14_23_20 [4] */
++		FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP14_19_16 [4] */
++		FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP14_15_12 [4] */
++		FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP14_11_8 [4] */
++		FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP14_7_4 [4] */
++		FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP14_3_0 [4] */
++		FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP15_31_28 [4] */
++		FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP15_27_24 [4] */
++		FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
++		0, 0, 0, 0, 0, 0,
++		/* IP15_23_20 [4] */
++		FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
++		FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP15_19_16 [4] */
++		FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
++		FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP15_15_12 [4] */
++		FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
++		FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP15_11_8 [4] */
++		FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
++		FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP15_7_4 [4] */
++		FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
++		FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP15_3_0 [4] */
++		FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
++		FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP16_31_28 [4] */
++		FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
++		FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_27_24 [4] */
++		FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
++		FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_23_20 [4] */
++		FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
++		FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_19_16 [4] */
++		FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
++		0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_15_12 [4] */
++		FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
++		FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0,
++		/* IP16_11_8 [4] */
++		FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
++		FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_7_4 [4] */
++		FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
++		FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP16_3_0 [4] */
++		FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
++			     4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IP17_31_28 [4] */
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_27_24 [4] */
++		FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
++		FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_23_20 [4] */
++		FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
++		FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_19_16 [4] */
++		FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
++		FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_15_12 [4] */
++		FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
++		FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_11_8 [4] */
++		FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
++		FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_7_4 [4] */
++		FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
++		FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++		/* IP17_3_0 [4] */
++		FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
++		FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
++			     1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3,
++				 1, 2, 3, 3, 1) {
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_ADGA [2] */
++		FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_CANCLK [2] */
++		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
++		FN_SEL_CANCLK_3,
++		/* SEL_CAN1 [2] */
++		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
++		/* SEL_CAN0 [2] */
++		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_I2C04 [3] */
++		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
++		FN_SEL_I2C04_4, 0, 0, 0,
++		/* SEL_I2C03 [3] */
++		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
++		FN_SEL_I2C03_4, 0, 0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_I2C02 [2] */
++		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
++		/* SEL_I2C01 [3] */
++		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
++		FN_SEL_I2C01_4, 0, 0, 0,
++		/* SEL_I2C00 [3] */
++		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
++		FN_SEL_I2C00_4, 0, 0, 0,
++		/* SEL_AVB [1] */
++		FN_SEL_AVB_0, FN_SEL_AVB_1, }
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
++			     1, 3, 3, 2, 2, 1, 2, 2,
++			     2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) {
++		/* SEL_SCIFCLK [1] */
++		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
++		/* SEL_SCIF5 [3] */
++		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
++		FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
++		/* SEL_SCIF4 [3] */
++		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
++		FN_SEL_SCIF4_4, 0, 0, 0,
++		/* SEL_SCIF3 [2] */
++		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
++		/* SEL_SCIF2 [2] */
++		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
++		/* SEL_SCIF2_CLK [1] */
++		FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
++		/* SEL_SCIF1 [2] */
++		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
++		/* SEL_SCIF0 [2] */
++		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
++		/* SEL_MSIOF2 [2] */
++		FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_MSIOF1 [1] */
++		FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_MSIOF0 [1] */
++		FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
++		/* SEL_RCN [1] */
++		FN_SEL_RCN_0, FN_SEL_RCN_1,
++		/* RESERVED [2] */
++		0, 0, 0, 0,
++		/* SEL_TMU2 [1] */
++		FN_SEL_TMU2_0, FN_SEL_TMU2_1,
++		/* SEL_TMU1 [1] */
++		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
++		/* RESERVED [2] */
++		0, 0, 0, 0,
++		/* SEL_HSCIF1 [2] */
++		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
++		/* SEL_HSCIF0 [1] */
++		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,}
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
++			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++				 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* RESERVED [1] */
++		0, 0,
++		/* SEL_ADGB [2] */
++		FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
++		/* SEL_ADGC [2] */
++		FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
++		/* SEL_SSI9 [2] */
++		FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
++		/* SEL_SSI8 [2] */
++		FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
++		/* SEL_SSI7 [2] */
++		FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
++		/* SEL_SSI6 [2] */
++		FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
++		/* SEL_SSI5 [2] */
++		FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
++		/* SEL_SSI4 [2] */
++		FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
++		/* SEL_SSI2 [2] */
++		FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
++		/* SEL_SSI1 [2] */
++		FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
++		/* SEL_SSI0 [2] */
++		FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, }
++	},
++	{ },
++};
++
++#ifdef CONFIG_PINCTRL_PFC_R8A77470
++const struct sh_pfc_soc_info r8a77470_pinmux_info = {
++	.name = "r8a77470_pfc",
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
++#endif
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 7fad897cd9f5..a466883c8f90 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -274,6 +274,7 @@ extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
++extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
+-- 
+2.19.0
+
diff --git a/patches/1253-pinctrl-sh-pfc-Add-PORT_GP_11-helper-macro.patch b/patches/1253-pinctrl-sh-pfc-Add-PORT_GP_11-helper-macro.patch
new file mode 100644
index 00000000000000..09f4377944e2b5
--- /dev/null
+++ b/patches/1253-pinctrl-sh-pfc-Add-PORT_GP_11-helper-macro.patch
@@ -0,0 +1,41 @@
+From b82d2650a865e60ccc72dd7c0e3d653bf09c59c3 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:22 +0900
+Subject: [PATCH 1253/1795] pinctrl: sh-pfc: Add PORT_GP_11 helper macro
+
+This follows the style of existion PORT_GP_X macros and
+will be used by a follow-up patch for the r8a77990 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit ec96db5868afa26ecf1b0b629f579fdb77530684)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index a466883c8f90..47b6e708984d 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -416,9 +416,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
+ 	PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
+ #define PORT_GP_10(bank, fn, sfx)	PORT_GP_CFG_10(bank, fn, sfx, 0)
+ 
+-#define PORT_GP_CFG_12(bank, fn, sfx, cfg)				\
++#define PORT_GP_CFG_11(bank, fn, sfx, cfg)				\
+ 	PORT_GP_CFG_10(bank, fn, sfx, cfg),				\
+-	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg),				\
++	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
++#define PORT_GP_11(bank, fn, sfx)	PORT_GP_CFG_11(bank, fn, sfx, 0)
++
++#define PORT_GP_CFG_12(bank, fn, sfx, cfg)				\
++	PORT_GP_CFG_11(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
+ #define PORT_GP_12(bank, fn, sfx)	PORT_GP_CFG_12(bank, fn, sfx, 0)
+ 
+-- 
+2.19.0
+
diff --git a/patches/1254-pinctrl-sh-pfc-Initial-R8A77990-PFC-support.patch b/patches/1254-pinctrl-sh-pfc-Initial-R8A77990-PFC-support.patch
new file mode 100644
index 00000000000000..f1cfa9aa486492
--- /dev/null
+++ b/patches/1254-pinctrl-sh-pfc-Initial-R8A77990-PFC-support.patch
@@ -0,0 +1,1829 @@
+From 066805ac9834e5ace66053af48a0456081be35db Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:23 +0900
+Subject: [PATCH 1254/1795] pinctrl: sh-pfc: Initial R8A77990 PFC support
+
+This patch adds initial pinctrl driver to support for the R8A77990 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6d4036a1e3b3ac0f3eebda5a0bbc6d78ebc14389)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/pinctrl/renesas,pfc-pinctrl.txt  |    1 +
+ drivers/pinctrl/sh-pfc/Kconfig                |    5 +
+ drivers/pinctrl/sh-pfc/Makefile               |    1 +
+ drivers/pinctrl/sh-pfc/core.c                 |    6 +
+ drivers/pinctrl/sh-pfc/pfc-r8a77990.c         | 1728 +++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h               |    1 +
+ 6 files changed, 1742 insertions(+)
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+index 4f5fca121d2a..abd8fbcf1e62 100644
+--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+@@ -28,6 +28,7 @@ Required Properties:
+     - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
+     - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
+     - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
++    - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.
+     - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
+     - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+ 
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index 1d9b7e04c0c6..43d950c16528 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -109,6 +109,11 @@ config PINCTRL_PFC_R8A77980
+ 	depends on ARCH_R8A77980
+ 	select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A77990
++        def_bool y
++        depends on ARCH_R8A77990
++        select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_R8A77995
+         def_bool y
+         depends on ARCH_R8A77995
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index b486fcdf4573..d0b29c51c159 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77965)	+= pfc-r8a77965.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77970)	+= pfc-r8a77970.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77980)	+= pfc-r8a77980.o
++obj-$(CONFIG_PINCTRL_PFC_R8A77990)	+= pfc-r8a77990.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index b069fe3bf75d..eb06981538b4 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -581,6 +581,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
+ 		.data = &r8a77980_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A77990
++	{
++		.compatible = "renesas,pfc-r8a77990",
++		.data = &r8a77990_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_R8A77995
+ 	{
+ 		.compatible = "renesas,pfc-r8a77995",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+new file mode 100644
+index 000000000000..0af2fefd3d9a
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+@@ -0,0 +1,1728 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * R8A77990 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ *
++ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++ *
++ * R8A7796 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2016-2017 Renesas Electronics Corp.
++ */
++
++#include <linux/kernel.h>
++
++#include "core.h"
++#include "sh_pfc.h"
++
++#define CPU_ALL_PORT(fn, sfx)	\
++	PORT_GP_18(0, fn, sfx),	\
++	PORT_GP_23(1, fn, sfx),	\
++	PORT_GP_26(2, fn, sfx),	\
++	PORT_GP_16(3, fn, sfx),	\
++	PORT_GP_11(4, fn, sfx),	\
++	PORT_GP_20(5, fn, sfx),	\
++	PORT_GP_18(6, fn, sfx)
++
++/*
++ * F_() : just information
++ * FM() : macro for FN_xxx / xxx_MARK
++ */
++
++/* GPSR0 */
++#define GPSR0_17	F_(SDA4,		IP7_27_24)
++#define GPSR0_16	F_(SCL4,		IP7_23_20)
++#define GPSR0_15	F_(D15,			IP7_19_16)
++#define GPSR0_14	F_(D14,			IP7_15_12)
++#define GPSR0_13	F_(D13,			IP7_11_8)
++#define GPSR0_12	F_(D12,			IP7_7_4)
++#define GPSR0_11	F_(D11,			IP7_3_0)
++#define GPSR0_10	F_(D10,			IP6_31_28)
++#define GPSR0_9		F_(D9,			IP6_27_24)
++#define GPSR0_8		F_(D8,			IP6_23_20)
++#define GPSR0_7		F_(D7,			IP6_19_16)
++#define GPSR0_6		F_(D6,			IP6_15_12)
++#define GPSR0_5		F_(D5,			IP6_11_8)
++#define GPSR0_4		F_(D4,			IP6_7_4)
++#define GPSR0_3		F_(D3,			IP6_3_0)
++#define GPSR0_2		F_(D2,			IP5_31_28)
++#define GPSR0_1		F_(D1,			IP5_27_24)
++#define GPSR0_0		F_(D0,			IP5_23_20)
++
++/* GPSR1 */
++#define GPSR1_22	F_(WE0_N,		IP5_19_16)
++#define GPSR1_21	F_(CS0_N,		IP5_15_12)
++#define GPSR1_20	FM(CLKOUT)
++#define GPSR1_19	F_(A19,			IP5_11_8)
++#define GPSR1_18	F_(A18,			IP5_7_4)
++#define GPSR1_17	F_(A17,			IP5_3_0)
++#define GPSR1_16	F_(A16,			IP4_31_28)
++#define GPSR1_15	F_(A15,			IP4_27_24)
++#define GPSR1_14	F_(A14,			IP4_23_20)
++#define GPSR1_13	F_(A13,			IP4_19_16)
++#define GPSR1_12	F_(A12,			IP4_15_12)
++#define GPSR1_11	F_(A11,			IP4_11_8)
++#define GPSR1_10	F_(A10,			IP4_7_4)
++#define GPSR1_9		F_(A9,			IP4_3_0)
++#define GPSR1_8		F_(A8,			IP3_31_28)
++#define GPSR1_7		F_(A7,			IP3_27_24)
++#define GPSR1_6		F_(A6,			IP3_23_20)
++#define GPSR1_5		F_(A5,			IP3_19_16)
++#define GPSR1_4		F_(A4,			IP3_15_12)
++#define GPSR1_3		F_(A3,			IP3_11_8)
++#define GPSR1_2		F_(A2,			IP3_7_4)
++#define GPSR1_1		F_(A1,			IP3_3_0)
++#define GPSR1_0		F_(A0,			IP2_31_28)
++
++/* GPSR2 */
++#define GPSR2_25	F_(EX_WAIT0,		IP2_27_24)
++#define GPSR2_24	F_(RD_WR_N,		IP2_23_20)
++#define GPSR2_23	F_(RD_N,		IP2_19_16)
++#define GPSR2_22	F_(BS_N,		IP2_15_12)
++#define GPSR2_21	FM(AVB_PHY_INT)
++#define GPSR2_20	F_(AVB_TXCREFCLK,	IP2_3_0)
++#define GPSR2_19	FM(AVB_RD3)
++#define GPSR2_18	F_(AVB_RD2,		IP1_31_28)
++#define GPSR2_17	F_(AVB_RD1,		IP1_27_24)
++#define GPSR2_16	F_(AVB_RD0,		IP1_23_20)
++#define GPSR2_15	FM(AVB_RXC)
++#define GPSR2_14	FM(AVB_RX_CTL)
++#define GPSR2_13	F_(RPC_RESET_N,		IP1_19_16)
++#define GPSR2_12	F_(RPC_INT_N,		IP1_15_12)
++#define GPSR2_11	F_(QSPI1_SSL,		IP1_11_8)
++#define GPSR2_10	F_(QSPI1_IO3,		IP1_7_4)
++#define GPSR2_9		F_(QSPI1_IO2,		IP1_3_0)
++#define GPSR2_8		F_(QSPI1_MISO_IO1,	IP0_31_28)
++#define GPSR2_7		F_(QSPI1_MOSI_IO0,	IP0_27_24)
++#define GPSR2_6		F_(QSPI1_SPCLK,		IP0_23_20)
++#define GPSR2_5		FM(QSPI0_SSL)
++#define GPSR2_4		F_(QSPI0_IO3,		IP0_19_16)
++#define GPSR2_3		F_(QSPI0_IO2,		IP0_15_12)
++#define GPSR2_2		F_(QSPI0_MISO_IO1,	IP0_11_8)
++#define GPSR2_1		F_(QSPI0_MOSI_IO0,	IP0_7_4)
++#define GPSR2_0		F_(QSPI0_SPCLK,		IP0_3_0)
++
++/* GPSR3 */
++#define GPSR3_15	F_(SD1_WP,		IP11_7_4)
++#define GPSR3_14	F_(SD1_CD,		IP11_3_0)
++#define GPSR3_13	F_(SD0_WP,		IP10_31_28)
++#define GPSR3_12	F_(SD0_CD,		IP10_27_24)
++#define GPSR3_11	F_(SD1_DAT3,		IP9_11_8)
++#define GPSR3_10	F_(SD1_DAT2,		IP9_7_4)
++#define GPSR3_9		F_(SD1_DAT1,		IP9_3_0)
++#define GPSR3_8		F_(SD1_DAT0,		IP8_31_28)
++#define GPSR3_7		F_(SD1_CMD,		IP8_27_24)
++#define GPSR3_6		F_(SD1_CLK,		IP8_23_20)
++#define GPSR3_5		F_(SD0_DAT3,		IP8_19_16)
++#define GPSR3_4		F_(SD0_DAT2,		IP8_15_12)
++#define GPSR3_3		F_(SD0_DAT1,		IP8_11_8)
++#define GPSR3_2		F_(SD0_DAT0,		IP8_7_4)
++#define GPSR3_1		F_(SD0_CMD,		IP8_3_0)
++#define GPSR3_0		F_(SD0_CLK,		IP7_31_28)
++
++/* GPSR4 */
++#define GPSR4_10	F_(SD3_DS,		IP10_23_20)
++#define GPSR4_9		F_(SD3_DAT7,		IP10_19_16)
++#define GPSR4_8		F_(SD3_DAT6,		IP10_15_12)
++#define GPSR4_7		F_(SD3_DAT5,		IP10_11_8)
++#define GPSR4_6		F_(SD3_DAT4,		IP10_7_4)
++#define GPSR4_5		F_(SD3_DAT3,		IP10_3_0)
++#define GPSR4_4		F_(SD3_DAT2,		IP9_31_28)
++#define GPSR4_3		F_(SD3_DAT1,		IP9_27_24)
++#define GPSR4_2		F_(SD3_DAT0,		IP9_23_20)
++#define GPSR4_1		F_(SD3_CMD,		IP9_19_16)
++#define GPSR4_0		F_(SD3_CLK,		IP9_15_12)
++
++/* GPSR5 */
++#define GPSR5_19	F_(MLB_DAT,		IP13_23_20)
++#define GPSR5_18	F_(MLB_SIG,		IP13_19_16)
++#define GPSR5_17	F_(MLB_CLK,		IP13_15_12)
++#define GPSR5_16	F_(SSI_SDATA9,		IP13_11_8)
++#define GPSR5_15	F_(MSIOF0_SS2,		IP13_7_4)
++#define GPSR5_14	F_(MSIOF0_SS1,		IP13_3_0)
++#define GPSR5_13	F_(MSIOF0_SYNC,		IP12_31_28)
++#define GPSR5_12	F_(MSIOF0_TXD,		IP12_27_24)
++#define GPSR5_11	F_(MSIOF0_RXD,		IP12_23_20)
++#define GPSR5_10	F_(MSIOF0_SCK,		IP12_19_16)
++#define GPSR5_9		F_(RX2_A,		IP12_15_12)
++#define GPSR5_8		F_(TX2_A,		IP12_11_8)
++#define GPSR5_7		F_(SCK2_A,		IP12_7_4)
++#define GPSR5_6		F_(TX1,			IP12_3_0)
++#define GPSR5_5		F_(RX1,			IP11_31_28)
++#define GPSR5_4		F_(RTS0_N_TANS_A,	IP11_23_20)
++#define GPSR5_3		F_(CTS0_N_A,		IP11_19_16)
++#define GPSR5_2		F_(TX0_A,		IP11_15_12)
++#define GPSR5_1		F_(RX0_A,		IP11_11_8)
++#define GPSR5_0		F_(SCK0_A,		IP11_27_24)
++
++/* GPSR6 */
++#define GPSR6_17	F_(USB30_PWEN,		IP15_27_24)
++#define GPSR6_16	F_(SSI_SDATA6,		IP15_19_16)
++#define GPSR6_15	F_(SSI_WS6,		IP15_15_12)
++#define GPSR6_14	F_(SSI_SCK6,		IP15_11_8)
++#define GPSR6_13	F_(SSI_SDATA5,		IP15_7_4)
++#define GPSR6_12	F_(SSI_WS5,		IP15_3_0)
++#define GPSR6_11	F_(SSI_SCK5,		IP14_31_28)
++#define GPSR6_10	F_(SSI_SDATA4,		IP14_27_24)
++#define GPSR6_9		F_(USB30_OVC,		IP15_31_28)
++#define GPSR6_8		F_(AUDIO_CLKA,		IP15_23_20)
++#define GPSR6_7		F_(SSI_SDATA3,		IP14_23_20)
++#define GPSR6_6		F_(SSI_WS349,		IP14_19_16)
++#define GPSR6_5		F_(SSI_SCK349,		IP14_15_12)
++#define GPSR6_4		F_(SSI_SDATA2,		IP14_11_8)
++#define GPSR6_3		F_(SSI_SDATA1,		IP14_7_4)
++#define GPSR6_2		F_(SSI_SDATA0,		IP14_3_0)
++#define GPSR6_1		F_(SSI_WS01239,		IP13_31_28)
++#define GPSR6_0		F_(SSI_SCK01239,	IP13_27_24)
++
++/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
++#define IP0_3_0		FM(QSPI0_SPCLK)		FM(HSCK4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_7_4		FM(QSPI0_MOSI_IO0)	FM(HCTS4_N_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_11_8	FM(QSPI0_MISO_IO1)	FM(HRTS4_N_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_15_12	FM(QSPI0_IO2)		FM(HTX4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_19_16	FM(QSPI0_IO3)		FM(HRX4_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_23_20	FM(QSPI1_SPCLK)		FM(RIF2_CLK_A)		FM(HSCK4_B)		FM(VI4_DATA0_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_27_24	FM(QSPI1_MOSI_IO0)	FM(RIF2_SYNC_A)		FM(HTX4_B)		FM(VI4_DATA1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP0_31_28	FM(QSPI1_MISO_IO1)	FM(RIF2_D0_A)		FM(HRX4_B)		FM(VI4_DATA2_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_3_0		FM(QSPI1_IO2)		FM(RIF2_D1_A)		FM(HTX3_C)		FM(VI4_DATA3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4		FM(QSPI1_IO3)		FM(RIF3_CLK_A)		FM(HRX3_C)		FM(VI4_DATA4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8	FM(QSPI1_SSL)		FM(RIF3_SYNC_A)		FM(HSCK3_C)		FM(VI4_DATA5_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12	FM(RPC_INT_N)		FM(RIF3_D0_A)		FM(HCTS3_N_C)		FM(VI4_DATA6_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16	FM(RPC_RESET_N)		FM(RIF3_D1_A)		FM(HRTS3_N_C)		FM(VI4_DATA7_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20	FM(AVB_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24	FM(AVB_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_31_28	FM(AVB_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_3_0		FM(AVB_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_7_4		FM(AVB_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_11_8	FM(AVB_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_15_12	FM(BS_N)		FM(PWM0_A)		FM(AVB_MAGIC)		FM(VI4_CLK)		F_(0, 0)		FM(TX3_C)	F_(0, 0)	FM(VI5_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_19_16	FM(RD_N)		FM(PWM1_A)		FM(AVB_LINK)		FM(VI4_FIELD)		F_(0, 0)		FM(RX3_C)	FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH_A)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE_A)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP2_31_28	FM(A0)			FM(IRQ0)		FM(PWM2_A)		FM(MSIOF3_SS1_B)	FM(VI5_CLK_A)		FM(DU_CDE)	FM(HRX3_D)	FM(IERX)	FM(QSTB_QHE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_3_0		FM(A1)			FM(IRQ1)		FM(PWM3_A)		FM(DU_DOTCLKIN1)	FM(VI5_DATA0_A)		FM(DU_DISP_CDE) FM(SDA6_B)	FM(IETX)	FM(QCPV_QDE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_7_4		FM(A2)			FM(IRQ2)		FM(AVB_AVTP_PPS)	FM(VI4_CLKENB)		FM(VI5_DATA1_A)		FM(DU_DISP)	FM(SCL6_B)	F_(0, 0)	FM(QSTVB_QVE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_11_8	FM(A3)			FM(CTS4_N_A)		FM(PWM4_A)		FM(VI4_DATA12)		F_(0, 0)		FM(DU_DOTCLKOUT0) FM(HTX3_D)	FM(IECLK)	FM(LCDOUT12)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_15_12	FM(A4)			FM(RTS4_N_TANS_A)	FM(MSIOF3_SYNC_B)	FM(VI4_DATA8)		FM(PWM2_B)		FM(DU_DG4)	FM(RIF2_CLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_19_16	FM(A5)			FM(SCK4_A)		FM(MSIOF3_SCK_B)	FM(VI4_DATA9)		FM(PWM3_B)		F_(0, 0)	FM(RIF2_SYNC_B)	F_(0, 0)	FM(QPOLA)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_23_20	FM(A6)			FM(RX4_A)		FM(MSIOF3_RXD_B)	FM(VI4_DATA10)		F_(0, 0)		F_(0, 0)	FM(RIF2_D0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_27_24	FM(A7)			FM(TX4_A)		FM(MSIOF3_TXD_B)	FM(VI4_DATA11)		F_(0, 0)		F_(0, 0)	FM(RIF2_D1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP3_31_28	FM(A8)			FM(SDA6_A)		FM(RX3_B)		FM(HRX4_C)		FM(VI5_HSYNC_N_A)	FM(DU_HSYNC)	FM(VI4_DATA0_B)	F_(0, 0)	FM(QSTH_QHS)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
++#define IP4_3_0		FM(A9)			FM(TX5_A)		FM(IRQ3)		FM(VI4_DATA16)		FM(VI5_VSYNC_N_A)	FM(DU_DG7)	F_(0, 0)	F_(0, 0)	FM(LCDOUT15)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_7_4		FM(A10)			FM(IRQ4)		FM(MSIOF2_SYNC_B)	FM(VI4_DATA13)		FM(VI5_FIELD_A)		FM(DU_DG5)	FM(FSCLKST2_N_B) F_(0, 0)	FM(LCDOUT13)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_11_8	FM(A11)			FM(SCL6_A)		FM(TX3_B)		FM(HTX4_C)		F_(0, 0)		FM(DU_VSYNC)	FM(VI4_DATA1_B)	F_(0, 0)	FM(QSTVA_QVS)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_15_12	FM(A12)			FM(RX5_A)		FM(MSIOF2_SS2_B)	FM(VI4_DATA17)		FM(VI5_DATA3_A)		FM(DU_DG6)	F_(0, 0)	F_(0, 0)	FM(LCDOUT14)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_19_16	FM(A13)			FM(SCK5_A)		FM(MSIOF2_SCK_B)	FM(VI4_DATA14)		FM(HRX4_D)		FM(DU_DB2)	F_(0, 0)	F_(0, 0)	FM(LCDOUT2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_23_20	FM(A14)			FM(MSIOF1_SS1)		FM(MSIOF2_RXD_B)	FM(VI4_DATA15)		FM(HTX4_D)		FM(DU_DB3)	F_(0, 0)	F_(0, 0)	FM(LCDOUT3)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_27_24	FM(A15)			FM(MSIOF1_SS2)		FM(MSIOF2_TXD_B)	FM(VI4_DATA18)		FM(VI5_DATA4_A)		FM(DU_DB4)	F_(0, 0)	F_(0, 0)	FM(LCDOUT4)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP4_31_28	FM(A16)			FM(MSIOF1_SYNC)		FM(MSIOF2_SS1_B)	FM(VI4_DATA19)		FM(VI5_DATA5_A)		FM(DU_DB5)	F_(0, 0)	F_(0, 0)	FM(LCDOUT5)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_3_0		FM(A17)			FM(MSIOF1_RXD)		F_(0, 0)		FM(VI4_DATA20)		FM(VI5_DATA6_A)		FM(DU_DB6)	F_(0, 0)	F_(0, 0)	FM(LCDOUT6)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_7_4		FM(A18)			FM(MSIOF1_TXD)		F_(0, 0)		FM(VI4_DATA21)		FM(VI5_DATA7_A)		FM(DU_DB0)	F_(0, 0)	FM(HRX4_E)	FM(LCDOUT0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_11_8	FM(A19)			FM(MSIOF1_SCK)		F_(0, 0)		FM(VI4_DATA22)		FM(VI5_DATA2_A)		FM(DU_DB1)	F_(0, 0)	FM(HTX4_E)	FM(LCDOUT1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_15_12	FM(CS0_N)		FM(SCL5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR0)	FM(VI4_DATA2_B)	F_(0, 0)	FM(LCDOUT16)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_19_16	FM(WE0_N)		FM(SDA5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR1)	FM(VI4_DATA3_B)	F_(0, 0)	FM(LCDOUT17)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_23_20	FM(D0)			FM(MSIOF3_SCK_A)	F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DR2)	FM(CTS4_N_C)	F_(0, 0)	FM(LCDOUT18)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_27_24	FM(D1)			FM(MSIOF3_SYNC_A)	FM(SCK3_A)		FM(VI4_DATA23)		FM(VI5_CLKENB_A)	FM(DU_DB7)	FM(RTS4_N_TANS_C) F_(0, 0)	FM(LCDOUT7)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP5_31_28	FM(D2)			FM(MSIOF3_RXD_A)	FM(RX5_C)		F_(0, 0)		FM(VI5_DATA14_A)	FM(DU_DR3)	FM(RX4_C)	F_(0, 0)	FM(LCDOUT19)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_3_0		FM(D3)			FM(MSIOF3_TXD_A)	FM(TX5_C)		F_(0, 0)		FM(VI5_DATA15_A)	FM(DU_DR4)	FM(TX4_C)	F_(0, 0)	FM(LCDOUT20)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_7_4		FM(D4)			FM(CANFD1_TX)		FM(HSCK3_B)		FM(CAN1_TX)		FM(RTS3_N_TANS_A)	FM(MSIOF3_SS2_A) F_(0, 0)	FM(VI5_DATA1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_11_8	FM(D5)			FM(RX3_A)		FM(HRX3_B)		F_(0, 0)		F_(0, 0)		FM(DU_DR5)	FM(VI4_DATA4_B)	F_(0, 0)	FM(LCDOUT21)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_15_12	FM(D6)			FM(TX3_A)		FM(HTX3_B)		F_(0, 0)		F_(0, 0)		FM(DU_DR6)	FM(VI4_DATA5_B)	F_(0, 0)	FM(LCDOUT22)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_19_16	FM(D7)			FM(CANFD1_RX)		FM(IRQ5)		FM(CAN1_RX)		FM(CTS3_N_A)		F_(0, 0)	F_(0, 0)	FM(VI5_DATA2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_23_20	FM(D8)			FM(MSIOF2_SCK_A)	FM(SCK4_B)		F_(0, 0)		FM(VI5_DATA12_A)	FM(DU_DR7)	FM(RIF3_CLK_B)	FM(HCTS3_N_E)	FM(LCDOUT23)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_27_24	FM(D9)			FM(MSIOF2_SYNC_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA10_A)	FM(DU_DG0)	FM(RIF3_SYNC_B)	FM(HRX3_E)	FM(LCDOUT8)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP6_31_28	FM(D10)			FM(MSIOF2_RXD_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA13_A)	FM(DU_DG1)	FM(RIF3_D0_B)	FM(HTX3_E)	FM(LCDOUT9)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_3_0		FM(D11)			FM(MSIOF2_TXD_A)	F_(0, 0)		F_(0, 0)		FM(VI5_DATA11_A)	FM(DU_DG2)	FM(RIF3_D1_B)	FM(HRTS3_N_E)	FM(LCDOUT10)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_7_4		FM(D12)			FM(CANFD0_TX)		FM(TX4_B)		FM(CAN0_TX)		FM(VI5_DATA8_A)		F_(0, 0)	F_(0, 0)	FM(VI5_DATA3_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_11_8	FM(D13)			FM(CANFD0_RX)		FM(RX4_B)		FM(CAN0_RX)		FM(VI5_DATA9_A)		FM(SCL7_B)	F_(0, 0)	FM(VI5_DATA4_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_15_12	FM(D14)			FM(CAN_CLK)		FM(HRX3_A)		FM(MSIOF2_SS2_A)	F_(0, 0)		FM(SDA7_B)	F_(0, 0)	FM(VI5_DATA5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_19_16	FM(D15)			FM(MSIOF2_SS1_A)	FM(HTX3_A)		FM(MSIOF3_SS1_A)	F_(0, 0)		FM(DU_DG3)	F_(0, 0)	F_(0, 0)	FM(LCDOUT11)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_23_20	FM(SCL4)		FM(CS1_N_A26)		F_(0, 0)		F_(0, 0)		F_(0, 0)		FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_27_24	FM(SDA4)		FM(WE1_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(VI4_DATA7_B)	FM(VI5_DATA7_B)	FM(QPOLB)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP7_31_28	FM(SD0_CLK)		FM(NFDATA8)		FM(SCL1_C)		FM(HSCK1_B)		FM(SDA2_E)		FM(FMCLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
++#define IP8_3_0		FM(SD0_CMD)		FM(NFDATA9)		F_(0, 0)		FM(HRX1_B)		F_(0, 0)		FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_7_4		FM(SD0_DAT0)		FM(NFDATA10)		F_(0, 0)		FM(HTX1_B)		F_(0, 0)		FM(REMOCON_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_11_8	FM(SD0_DAT1)		FM(NFDATA11)		FM(SDA2_C)		FM(HCTS1_N_B)		F_(0, 0)		FM(FMIN_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_15_12	FM(SD0_DAT2)		FM(NFDATA12)		FM(SCL2_C)		FM(HRTS1_N_B)		F_(0, 0)		FM(BPFCLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_19_16	FM(SD0_DAT3)		FM(NFDATA13)		FM(SDA1_C)		FM(SCL2_E)		FM(SPEEDIN_C)		FM(REMOCON_C)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_23_20	FM(SD1_CLK)		FM(NFDATA14_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_27_24	FM(SD1_CMD)		FM(NFDATA15_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP8_31_28	FM(SD1_DAT0)		FM(NFWP_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_3_0		FM(SD1_DAT1)		FM(NFCE_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_7_4		FM(SD1_DAT2)		FM(NFALE_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_11_8	FM(SD1_DAT3)		FM(NFRB_N_B)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_15_12	FM(SD3_CLK)		FM(NFWE_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_19_16	FM(SD3_CMD)		FM(NFRE_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_23_20	FM(SD3_DAT0)		FM(NFDATA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_27_24	FM(SD3_DAT1)		FM(NFDATA1)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP9_31_28	FM(SD3_DAT2)		FM(NFDATA2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_3_0	FM(SD3_DAT3)		FM(NFDATA3)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_7_4	FM(SD3_DAT4)		FM(NFDATA4)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_11_8	FM(SD3_DAT5)		FM(NFDATA5)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_15_12	FM(SD3_DAT6)		FM(NFDATA6)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_19_16	FM(SD3_DAT7)		FM(NFDATA7)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_23_20	FM(SD3_DS)		FM(NFCLE)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_27_24	FM(SD0_CD)		FM(NFALE_A)		FM(SD3_CD)		FM(RIF0_CLK_B)		FM(SCL2_B)		FM(TCLK1_A)	FM(SSI_SCK2_B)	FM(TS_SCK0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP10_31_28	FM(SD0_WP)		FM(NFRB_N_A)		FM(SD3_WP)		FM(RIF0_D0_B)		FM(SDA2_B)		FM(TCLK2_A)	FM(SSI_WS2_B)	FM(TS_SDAT0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_3_0	FM(SD1_CD)		FM(NFCE_N_A)		FM(SSI_SCK1)		FM(RIF0_D1_B)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SDEN0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_7_4	FM(SD1_WP)		FM(NFWP_N_A)		FM(SSI_WS1)		FM(RIF0_SYNC_B)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SPSYNC0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_11_8	FM(RX0_A)		FM(HRX1_A)		FM(SSI_SCK2_A)		FM(RIF1_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SCK1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_15_12	FM(TX0_A)		FM(HTX1_A)		FM(SSI_WS2_A)		FM(RIF1_D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SDAT1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_19_16	FM(CTS0_N_A)		FM(NFDATA14_A)		FM(AUDIO_CLKOUT_A)	FM(RIF1_D1)		FM(SCIF_CLK_A)		FM(FMCLK_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_23_20	FM(RTS0_N_TANS_A)	FM(NFDATA15_A)		FM(AUDIO_CLKOUT1_A)	FM(RIF1_CLK)		FM(SCL2_A)		FM(FMIN_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_27_24	FM(SCK0_A)		FM(HSCK1_A)		FM(USB3HS0_ID)		FM(RTS1_N_TANS)		FM(SDA2_A)		FM(FMCLK_C)	F_(0, 0)	F_(0, 0)	FM(USB1_ID)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP11_31_28	FM(RX1)			FM(HRX2_B)		FM(SSI_SCK9_B)		FM(AUDIO_CLKOUT1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++/* IPSRx */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 - F */
++#define IP12_3_0	FM(TX1)			FM(HTX2_B)		FM(SSI_WS9_B)		FM(AUDIO_CLKOUT3_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_7_4	FM(SCK2_A)		FM(HSCK0_A)		FM(AUDIO_CLKB_A)	FM(CTS1_N)		FM(RIF0_CLK_A)		FM(REMOCON_A)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_11_8	FM(TX2_A)		FM(HRX0_A)		FM(AUDIO_CLKOUT2_A)	F_(0, 0)		FM(SCL1_A)		F_(0, 0)	FM(FSO_CFE_0_N_A) FM(TS_SDEN1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_15_12	FM(RX2_A)		FM(HTX0_A)		FM(AUDIO_CLKOUT3_A)	F_(0, 0)		FM(SDA1_A)		F_(0, 0)	FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_19_16	FM(MSIOF0_SCK)		F_(0, 0)		FM(SSI_SCK78)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_23_20	FM(MSIOF0_RXD)		F_(0, 0)		FM(SSI_WS78)		F_(0, 0)		F_(0, 0)		FM(TX2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_27_24	FM(MSIOF0_TXD)		F_(0, 0)		FM(SSI_SDATA7)		F_(0, 0)		F_(0, 0)		FM(RX2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP12_31_28	FM(MSIOF0_SYNC)		FM(AUDIO_CLKOUT_B)	FM(SSI_SDATA8)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_3_0	FM(MSIOF0_SS1)		FM(HRX2_A)		FM(SSI_SCK4)		FM(HCTS0_N_A)		FM(BPFCLK_C)		FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_7_4	FM(MSIOF0_SS2)		FM(HTX2_A)		FM(SSI_WS4)		FM(HRTS0_N_A)		FM(FMIN_C)		FM(BPFCLK_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_11_8	FM(SSI_SDATA9)		F_(0, 0)		FM(AUDIO_CLKC_A)	FM(SCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_15_12	FM(MLB_CLK)		FM(RX0_B)		F_(0, 0)		FM(RIF0_D0_A)		FM(SCL1_B)		FM(TCLK1_B)	F_(0, 0)	F_(0, 0)	FM(SIM0_RST_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_19_16	FM(MLB_SIG)		FM(SCK0_B)		F_(0, 0)		FM(RIF0_D1_A)		FM(SDA1_B)		FM(TCLK2_B)	F_(0, 0)	F_(0, 0)	FM(SIM0_D_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_23_20	FM(MLB_DAT)		FM(TX0_B)		F_(0, 0)		FM(RIF0_SYNC_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_27_24	FM(SSI_SCK01239)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP13_31_28	FM(SSI_WS01239)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_3_0	FM(SSI_SDATA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_7_4	FM(SSI_SDATA1)		FM(AUDIO_CLKC_B)	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_11_8	FM(SSI_SDATA2)		FM(AUDIO_CLKOUT2_B)	FM(SSI_SCK9_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_15_12	FM(SSI_SCK349)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM2_C)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_19_16	FM(SSI_WS349)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM3_C)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_23_20	FM(SSI_SDATA3)		FM(AUDIO_CLKOUT1_C)	FM(AUDIO_CLKB_B)	F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_27_24	FM(SSI_SDATA4)		F_(0, 0)		FM(SSI_WS9_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP14_31_28	FM(SSI_SCK5)		FM(HRX0_B)		F_(0, 0)		FM(USB0_PWEN_B)		FM(SCL2_D)		F_(0, 0)	FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_3_0	FM(SSI_WS5)		FM(HTX0_B)		F_(0, 0)		FM(USB0_OVC_B)		FM(SDA2_D)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_7_4	FM(SSI_SDATA5)		FM(HSCK0_B)		FM(AUDIO_CLKB_C)	FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_11_8	FM(SSI_SCK6)		FM(HSCK2_A)		FM(AUDIO_CLKC_C)	FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	FM(FSO_CFE_0_N_B) F_(0, 0)	FM(SIM0_RST_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_15_12	FM(SSI_WS6)		FM(HCTS2_N_A)		FM(AUDIO_CLKOUT2_C)	FM(TPU0TO2)		FM(SDA1_D)		F_(0, 0)	FM(FSO_CFE_1_N_B) F_(0, 0)	FM(SIM0_D_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_19_16	FM(SSI_SDATA6)		FM(HRTS2_N_A)		FM(AUDIO_CLKOUT3_C)	FM(TPU0TO3)		FM(SCL1_D)		F_(0, 0)	FM(FSO_TOE_N_B)	F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_23_20	FM(AUDIO_CLKA)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_27_24	FM(USB30_PWEN)		FM(USB0_PWEN_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP15_31_28	FM(USB30_OVC)		FM(USB0_OVC_A)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(FSO_TOE_N_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++
++#define PINMUX_GPSR	\
++\
++													 \
++													 \
++													 \
++													 \
++													 \
++													 \
++				GPSR2_25								 \
++				GPSR2_24								 \
++				GPSR2_23								 \
++		GPSR1_22	GPSR2_22								 \
++		GPSR1_21	GPSR2_21								 \
++		GPSR1_20	GPSR2_20								 \
++		GPSR1_19	GPSR2_19					GPSR5_19		 \
++		GPSR1_18	GPSR2_18					GPSR5_18		 \
++GPSR0_17	GPSR1_17	GPSR2_17					GPSR5_17	GPSR6_17 \
++GPSR0_16	GPSR1_16	GPSR2_16					GPSR5_16	GPSR6_16 \
++GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15			GPSR5_15	GPSR6_15 \
++GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14	GPSR6_14 \
++GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13	GPSR6_13 \
++GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12	GPSR6_12 \
++GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11	GPSR6_11 \
++GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
++GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
++GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
++GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
++GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
++GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
++GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
++GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3 \
++GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2 \
++GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1 \
++GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0
++
++#define PINMUX_IPSR				\
++\
++FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
++FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
++FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
++FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
++FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
++FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
++FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
++FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
++\
++FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
++FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
++FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
++FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
++FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
++FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
++FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
++FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
++\
++FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
++FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
++FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
++FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
++FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
++FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
++FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
++FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
++\
++FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
++FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
++FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
++FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
++FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
++FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
++FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
++FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28
++
++/* MOD_SEL0 */			/* 0 */				/* 1 */				/* 2 */				/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */
++#define MOD_SEL0_30_29		FM(SEL_ADGB_0)			FM(SEL_ADGB_1)			FM(SEL_ADGB_2)			F_(0, 0)
++#define MOD_SEL0_28		FM(SEL_DRIF0_0)			FM(SEL_DRIF0_1)
++#define MOD_SEL0_27_26		FM(SEL_FM_0)			FM(SEL_FM_1)			FM(SEL_FM_2)			F_(0, 0)
++#define MOD_SEL0_25		FM(SEL_FSO_0)			FM(SEL_FSO_1)
++#define MOD_SEL0_24		FM(SEL_HSCIF0_0)		FM(SEL_HSCIF0_1)
++#define MOD_SEL0_23		FM(SEL_HSCIF1_0)		FM(SEL_HSCIF1_1)
++#define MOD_SEL0_22		FM(SEL_HSCIF2_0)		FM(SEL_HSCIF2_1)
++#define MOD_SEL0_21_20		FM(SEL_I2C1_0)			FM(SEL_I2C1_1)			FM(SEL_I2C1_2)			FM(SEL_I2C1_3)		FM(SEL_I2C1_4)		F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define MOD_SEL0_19_18_17	FM(SEL_I2C2_0)			FM(SEL_I2C2_1)			FM(SEL_I2C2_2)			FM(SEL_I2C2_3)		FM(SEL_I2C2_4)		F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define MOD_SEL0_16		FM(SEL_NDFC_0)			FM(SEL_NDFC_1)
++#define MOD_SEL0_15		FM(SEL_PWM0_0)			FM(SEL_PWM0_1)
++#define MOD_SEL0_14		FM(SEL_PWM1_0)			FM(SEL_PWM1_1)
++#define MOD_SEL0_13_12		FM(SEL_PWM2_0)			FM(SEL_PWM2_1)			FM(SEL_PWM2_2)			F_(0, 0)
++#define MOD_SEL0_11_10		FM(SEL_PWM3_0)			FM(SEL_PWM3_1)			FM(SEL_PWM3_2)			F_(0, 0)
++#define MOD_SEL0_9		FM(SEL_PWM4_0)			FM(SEL_PWM4_1)
++#define MOD_SEL0_8		FM(SEL_PWM5_0)			FM(SEL_PWM5_1)
++#define MOD_SEL0_7		FM(SEL_PWM6_0)			FM(SEL_PWM6_1)
++#define MOD_SEL0_6_5		FM(SEL_REMOCON_0)		FM(SEL_REMOCON_1)		FM(SEL_REMOCON_2)		F_(0, 0)
++#define MOD_SEL0_4		FM(SEL_SCIF_0)			FM(SEL_SCIF_1)
++#define MOD_SEL0_3		FM(SEL_SCIF0_0)			FM(SEL_SCIF0_1)
++#define MOD_SEL0_2		FM(SEL_SCIF2_0)			FM(SEL_SCIF2_1)
++#define MOD_SEL0_1_0		FM(SEL_SPEED_PULSE_IF_0)	FM(SEL_SPEED_PULSE_IF_1)	FM(SEL_SPEED_PULSE_IF_2)	F_(0, 0)
++
++/* MOD_SEL1 */			/* 0 */				/* 1 */				/* 2 */				/* 3 */			/* 4 */			/* 5 */		/* 6 */		/* 7 */
++#define MOD_SEL1_31		FM(SEL_SIMCARD_0)		FM(SEL_SIMCARD_1)
++#define MOD_SEL1_30		FM(SEL_SSI2_0)			FM(SEL_SSI2_1)
++#define MOD_SEL1_29		FM(SEL_TIMER_TMU_0)		FM(SEL_TIMER_TMU_1)
++#define MOD_SEL1_28		FM(SEL_USB_20_CH0_0)		FM(SEL_USB_20_CH0_1)
++#define MOD_SEL1_26		FM(SEL_DRIF2_0)			FM(SEL_DRIF2_1)
++#define MOD_SEL1_25		FM(SEL_DRIF3_0)			FM(SEL_DRIF3_1)
++#define MOD_SEL1_24_23_22	FM(SEL_HSCIF3_0)		FM(SEL_HSCIF3_1)		FM(SEL_HSCIF3_2)		FM(SEL_HSCIF3_3)	FM(SEL_HSCIF3_4)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define MOD_SEL1_21_20_19	FM(SEL_HSCIF4_0)		FM(SEL_HSCIF4_1)		FM(SEL_HSCIF4_2)		FM(SEL_HSCIF4_3)	FM(SEL_HSCIF4_4)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define MOD_SEL1_18		FM(SEL_I2C6_0)			FM(SEL_I2C6_1)
++#define MOD_SEL1_17		FM(SEL_I2C7_0)			FM(SEL_I2C7_1)
++#define MOD_SEL1_16		FM(SEL_MSIOF2_0)		FM(SEL_MSIOF2_1)
++#define MOD_SEL1_15		FM(SEL_MSIOF3_0)		FM(SEL_MSIOF3_1)
++#define MOD_SEL1_14_13		FM(SEL_SCIF3_0)			FM(SEL_SCIF3_1)			FM(SEL_SCIF3_2)			F_(0, 0)
++#define MOD_SEL1_12_11		FM(SEL_SCIF4_0)			FM(SEL_SCIF4_1)			FM(SEL_SCIF4_2)			F_(0, 0)
++#define MOD_SEL1_10_9		FM(SEL_SCIF5_0)			FM(SEL_SCIF5_1)			FM(SEL_SCIF5_2)			F_(0, 0)
++#define MOD_SEL1_8		FM(SEL_VIN4_0)			FM(SEL_VIN4_1)
++#define MOD_SEL1_7		FM(SEL_VIN5_0)			FM(SEL_VIN5_1)
++#define MOD_SEL1_6_5		FM(SEL_ADGC_0)			FM(SEL_ADGC_1)			FM(SEL_ADGC_2)			F_(0, 0)
++#define MOD_SEL1_4		FM(SEL_SSI9_0)			FM(SEL_SSI9_1)
++
++#define PINMUX_MOD_SELS	\
++\
++			MOD_SEL1_31 \
++MOD_SEL0_30_29		MOD_SEL1_30 \
++			MOD_SEL1_29 \
++MOD_SEL0_28		MOD_SEL1_28 \
++MOD_SEL0_27_26 \
++			MOD_SEL1_26 \
++MOD_SEL0_25		MOD_SEL1_25 \
++MOD_SEL0_24		MOD_SEL1_24_23_22 \
++MOD_SEL0_23 \
++MOD_SEL0_22 \
++MOD_SEL0_21_20		MOD_SEL1_21_20_19 \
++MOD_SEL0_19_18_17	MOD_SEL1_18 \
++			MOD_SEL1_17 \
++MOD_SEL0_16		MOD_SEL1_16 \
++MOD_SEL0_15		MOD_SEL1_15 \
++MOD_SEL0_14		MOD_SEL1_14_13 \
++MOD_SEL0_13_12 \
++			MOD_SEL1_12_11 \
++MOD_SEL0_11_10 \
++			MOD_SEL1_10_9 \
++MOD_SEL0_9 \
++MOD_SEL0_8		MOD_SEL1_8 \
++MOD_SEL0_7		MOD_SEL1_7 \
++MOD_SEL0_6_5		MOD_SEL1_6_5 \
++MOD_SEL0_4		MOD_SEL1_4 \
++MOD_SEL0_3 \
++MOD_SEL0_2 \
++MOD_SEL0_1_0
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++#define F_(x, y)
++#define FM(x)	FN_##x,
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_FUNCTION_END,
++#undef F_
++#undef FM
++
++#define F_(x, y)
++#define FM(x)	x##_MARK,
++	PINMUX_MARK_BEGIN,
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_MARK_END,
++#undef F_
++#undef FM
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0,		QSPI0_SPCLK),
++	PINMUX_IPSR_MSEL(IP0_3_0,		HSCK4_A,	SEL_HSCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_7_4,		QSPI0_MOSI_IO0),
++	PINMUX_IPSR_MSEL(IP0_7_4,		HCTS4_N_A,	SEL_HSCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_11_8,		QSPI0_MISO_IO1),
++	PINMUX_IPSR_MSEL(IP0_11_8,		HRTS4_N_A,	SEL_HSCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_15_12,		QSPI0_IO2),
++	PINMUX_IPSR_GPSR(IP0_15_12,		HTX4_A),
++
++	PINMUX_IPSR_GPSR(IP0_19_16,		QSPI0_IO3),
++	PINMUX_IPSR_MSEL(IP0_19_16,		HRX4_A,		SEL_HSCIF4_0),
++
++	PINMUX_IPSR_GPSR(IP0_23_20,		QSPI1_SPCLK),
++	PINMUX_IPSR_MSEL(IP0_23_20,		RIF2_CLK_A,	SEL_DRIF2_0),
++	PINMUX_IPSR_MSEL(IP0_23_20,		HSCK4_B,	SEL_HSCIF4_1),
++	PINMUX_IPSR_MSEL(IP0_23_20,		VI4_DATA0_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP0_27_24,		QSPI1_MOSI_IO0),
++	PINMUX_IPSR_MSEL(IP0_27_24,		RIF2_SYNC_A,	SEL_DRIF2_0),
++	PINMUX_IPSR_GPSR(IP0_27_24,		HTX4_B),
++	PINMUX_IPSR_MSEL(IP0_27_24,		VI4_DATA1_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP0_31_28,		QSPI1_MISO_IO1),
++	PINMUX_IPSR_MSEL(IP0_31_28,		RIF2_D0_A,	SEL_DRIF2_0),
++	PINMUX_IPSR_MSEL(IP0_31_28,		HRX4_B,		SEL_HSCIF4_1),
++	PINMUX_IPSR_MSEL(IP0_31_28,		VI4_DATA2_A,	SEL_VIN4_0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0,		QSPI1_IO2),
++	PINMUX_IPSR_MSEL(IP1_3_0,		RIF2_D1_A,	SEL_DRIF2_0),
++	PINMUX_IPSR_GPSR(IP1_3_0,		HTX3_C),
++	PINMUX_IPSR_MSEL(IP1_3_0,		VI4_DATA3_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP1_7_4,		QSPI1_IO3),
++	PINMUX_IPSR_MSEL(IP1_7_4,		RIF3_CLK_A,	SEL_DRIF3_0),
++	PINMUX_IPSR_MSEL(IP1_7_4,		HRX3_C,		SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP1_7_4,		VI4_DATA4_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP1_11_8,		QSPI1_SSL),
++	PINMUX_IPSR_MSEL(IP1_11_8,		RIF3_SYNC_A,	SEL_DRIF3_0),
++	PINMUX_IPSR_MSEL(IP1_11_8,		HSCK3_C,	SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP1_11_8,		VI4_DATA5_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP1_15_12,		RPC_INT_N),
++	PINMUX_IPSR_MSEL(IP1_15_12,		RIF3_D0_A,	SEL_DRIF3_0),
++	PINMUX_IPSR_MSEL(IP1_15_12,		HCTS3_N_C,	SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP1_15_12,		VI4_DATA6_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP1_19_16,		RPC_RESET_N),
++	PINMUX_IPSR_MSEL(IP1_19_16,		RIF3_D1_A,	SEL_DRIF3_0),
++	PINMUX_IPSR_MSEL(IP1_19_16,		HRTS3_N_C,	SEL_HSCIF3_2),
++	PINMUX_IPSR_MSEL(IP1_19_16,		VI4_DATA7_A,	SEL_VIN4_0),
++
++	PINMUX_IPSR_GPSR(IP1_23_20,		AVB_RD0),
++
++	PINMUX_IPSR_GPSR(IP1_27_24,		AVB_RD1),
++
++	PINMUX_IPSR_GPSR(IP1_31_28,		AVB_RD2),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0,		AVB_TXCREFCLK),
++
++	PINMUX_IPSR_GPSR(IP2_7_4,		AVB_MDIO),
++
++	PINMUX_IPSR_GPSR(IP2_11_8,		AVB_MDC),
++
++	PINMUX_IPSR_GPSR(IP2_15_12,		BS_N),
++	PINMUX_IPSR_MSEL(IP2_15_12,		PWM0_A,		SEL_PWM0_0),
++	PINMUX_IPSR_GPSR(IP2_15_12,		AVB_MAGIC),
++	PINMUX_IPSR_GPSR(IP2_15_12,		VI4_CLK),
++	PINMUX_IPSR_GPSR(IP2_15_12,		TX3_C),
++	PINMUX_IPSR_MSEL(IP2_15_12,		VI5_CLK_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP2_19_16,		RD_N),
++	PINMUX_IPSR_MSEL(IP2_19_16,		PWM1_A,		SEL_PWM1_0),
++	PINMUX_IPSR_GPSR(IP2_19_16,		AVB_LINK),
++	PINMUX_IPSR_GPSR(IP2_19_16,		VI4_FIELD),
++	PINMUX_IPSR_MSEL(IP2_19_16,		RX3_C,		SEL_SCIF3_2),
++	PINMUX_IPSR_GPSR(IP2_19_16,		FSCLKST2_N_A),
++	PINMUX_IPSR_MSEL(IP2_19_16,		VI5_DATA0_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP2_23_20,		RD_WR_N),
++	PINMUX_IPSR_MSEL(IP2_23_20,		SCL7_A,		SEL_I2C7_0),
++	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH_A),
++	PINMUX_IPSR_GPSR(IP2_23_20,		VI4_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP2_23_20,		TX5_B),
++	PINMUX_IPSR_MSEL(IP2_23_20,		SCK3_C,		SEL_SCIF3_2),
++	PINMUX_IPSR_MSEL(IP2_23_20,		PWM5_A,		SEL_PWM5_0),
++
++	PINMUX_IPSR_GPSR(IP2_27_24,		EX_WAIT0),
++	PINMUX_IPSR_MSEL(IP2_27_24,		SDA7_A,		SEL_I2C7_0),
++	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE_A),
++	PINMUX_IPSR_GPSR(IP2_27_24,		VI4_HSYNC_N),
++	PINMUX_IPSR_MSEL(IP2_27_24,		RX5_B,		SEL_SCIF5_1),
++	PINMUX_IPSR_MSEL(IP2_27_24,		PWM6_A,		SEL_PWM6_0),
++
++	PINMUX_IPSR_GPSR(IP2_31_28,		A0),
++	PINMUX_IPSR_GPSR(IP2_31_28,		IRQ0),
++	PINMUX_IPSR_MSEL(IP2_31_28,		PWM2_A,		SEL_PWM2_0),
++	PINMUX_IPSR_MSEL(IP2_31_28,		MSIOF3_SS1_B,	SEL_MSIOF3_1),
++	PINMUX_IPSR_MSEL(IP2_31_28,		VI5_CLK_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP2_31_28,		DU_CDE),
++	PINMUX_IPSR_MSEL(IP2_31_28,		HRX3_D,		SEL_HSCIF3_3),
++	PINMUX_IPSR_GPSR(IP2_31_28,		IERX),
++	PINMUX_IPSR_GPSR(IP2_31_28,		QSTB_QHE),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0,		A1),
++	PINMUX_IPSR_GPSR(IP3_3_0,		IRQ1),
++	PINMUX_IPSR_MSEL(IP3_3_0,		PWM3_A,		SEL_PWM3_0),
++	PINMUX_IPSR_GPSR(IP3_3_0,		DU_DOTCLKIN1),
++	PINMUX_IPSR_MSEL(IP3_3_0,		VI5_DATA0_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP3_3_0,		DU_DISP_CDE),
++	PINMUX_IPSR_MSEL(IP3_3_0,		SDA6_B,		SEL_I2C6_1),
++	PINMUX_IPSR_GPSR(IP3_3_0,		IETX),
++	PINMUX_IPSR_GPSR(IP3_3_0,		QCPV_QDE),
++
++	PINMUX_IPSR_GPSR(IP3_7_4,		A2),
++	PINMUX_IPSR_GPSR(IP3_7_4,		IRQ2),
++	PINMUX_IPSR_GPSR(IP3_7_4,		AVB_AVTP_PPS),
++	PINMUX_IPSR_GPSR(IP3_7_4,		VI4_CLKENB),
++	PINMUX_IPSR_MSEL(IP3_7_4,		VI5_DATA1_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP3_7_4,		DU_DISP),
++	PINMUX_IPSR_MSEL(IP3_7_4,		SCL6_B,		SEL_I2C6_1),
++	PINMUX_IPSR_GPSR(IP3_7_4,		QSTVB_QVE),
++
++	PINMUX_IPSR_GPSR(IP3_11_8,		A3),
++	PINMUX_IPSR_MSEL(IP3_11_8,		CTS4_N_A,	SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP3_11_8,		PWM4_A,		SEL_PWM4_0),
++	PINMUX_IPSR_GPSR(IP3_11_8,		VI4_DATA12),
++	PINMUX_IPSR_GPSR(IP3_11_8,		DU_DOTCLKOUT0),
++	PINMUX_IPSR_GPSR(IP3_11_8,		HTX3_D),
++	PINMUX_IPSR_GPSR(IP3_11_8,		IECLK),
++	PINMUX_IPSR_GPSR(IP3_11_8,		LCDOUT12),
++
++	PINMUX_IPSR_GPSR(IP3_15_12,		A4),
++	PINMUX_IPSR_MSEL(IP3_15_12,		RTS4_N_TANS_A,	SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP3_15_12,		MSIOF3_SYNC_B,	SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP3_15_12,		VI4_DATA8),
++	PINMUX_IPSR_MSEL(IP3_15_12,		PWM2_B,		SEL_PWM2_1),
++	PINMUX_IPSR_GPSR(IP3_15_12,		DU_DG4),
++	PINMUX_IPSR_MSEL(IP3_15_12,		RIF2_CLK_B,	SEL_DRIF2_1),
++
++	PINMUX_IPSR_GPSR(IP3_19_16,		A5),
++	PINMUX_IPSR_MSEL(IP3_19_16,		SCK4_A,		SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP3_19_16,		MSIOF3_SCK_B,	SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP3_19_16,		VI4_DATA9),
++	PINMUX_IPSR_MSEL(IP3_19_16,		PWM3_B,		SEL_PWM3_1),
++	PINMUX_IPSR_MSEL(IP3_19_16,		RIF2_SYNC_B,	SEL_DRIF2_1),
++	PINMUX_IPSR_GPSR(IP3_19_16,		QPOLA),
++
++	PINMUX_IPSR_GPSR(IP3_23_20,		A6),
++	PINMUX_IPSR_MSEL(IP3_23_20,		RX4_A,		SEL_SCIF4_0),
++	PINMUX_IPSR_MSEL(IP3_23_20,		MSIOF3_RXD_B,	SEL_MSIOF3_1),
++	PINMUX_IPSR_GPSR(IP3_23_20,		VI4_DATA10),
++	PINMUX_IPSR_MSEL(IP3_23_20,		RIF2_D0_B,	SEL_DRIF2_1),
++
++	PINMUX_IPSR_GPSR(IP3_27_24,		A7),
++	PINMUX_IPSR_GPSR(IP3_27_24,		TX4_A),
++	PINMUX_IPSR_GPSR(IP3_27_24,		MSIOF3_TXD_B),
++	PINMUX_IPSR_GPSR(IP3_27_24,		VI4_DATA11),
++	PINMUX_IPSR_MSEL(IP3_27_24,		RIF2_D1_B,	SEL_DRIF2_1),
++
++	PINMUX_IPSR_GPSR(IP3_31_28,		A8),
++	PINMUX_IPSR_MSEL(IP3_31_28,		SDA6_A,		SEL_I2C6_0),
++	PINMUX_IPSR_MSEL(IP3_31_28,		RX3_B,		SEL_SCIF3_1),
++	PINMUX_IPSR_MSEL(IP3_31_28,		HRX4_C,		SEL_HSCIF4_2),
++	PINMUX_IPSR_MSEL(IP3_31_28,		VI5_HSYNC_N_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP3_31_28,		DU_HSYNC),
++	PINMUX_IPSR_MSEL(IP3_31_28,		VI4_DATA0_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP3_31_28,		QSTH_QHS),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0,		A9),
++	PINMUX_IPSR_GPSR(IP4_3_0,		TX5_A),
++	PINMUX_IPSR_GPSR(IP4_3_0,		IRQ3),
++	PINMUX_IPSR_GPSR(IP4_3_0,		VI4_DATA16),
++	PINMUX_IPSR_MSEL(IP4_3_0,		VI5_VSYNC_N_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP4_3_0,		DU_DG7),
++	PINMUX_IPSR_GPSR(IP4_3_0,		LCDOUT15),
++
++	PINMUX_IPSR_GPSR(IP4_7_4,		A10),
++	PINMUX_IPSR_GPSR(IP4_7_4,		IRQ4),
++	PINMUX_IPSR_MSEL(IP4_7_4,		MSIOF2_SYNC_B,	SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP4_7_4,		VI4_DATA13),
++	PINMUX_IPSR_MSEL(IP4_7_4,		VI5_FIELD_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP4_7_4,		DU_DG5),
++	PINMUX_IPSR_GPSR(IP4_7_4,		FSCLKST2_N_B),
++	PINMUX_IPSR_GPSR(IP4_7_4,		LCDOUT13),
++
++	PINMUX_IPSR_GPSR(IP4_11_8,		A11),
++	PINMUX_IPSR_MSEL(IP4_11_8,		SCL6_A,		SEL_I2C6_0),
++	PINMUX_IPSR_GPSR(IP4_11_8,		TX3_B),
++	PINMUX_IPSR_GPSR(IP4_11_8,		HTX4_C),
++	PINMUX_IPSR_GPSR(IP4_11_8,		DU_VSYNC),
++	PINMUX_IPSR_MSEL(IP4_11_8,		VI4_DATA1_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP4_11_8,		QSTVA_QVS),
++
++	PINMUX_IPSR_GPSR(IP4_15_12,		A12),
++	PINMUX_IPSR_MSEL(IP4_15_12,		RX5_A,		SEL_SCIF5_0),
++	PINMUX_IPSR_GPSR(IP4_15_12,		MSIOF2_SS2_B),
++	PINMUX_IPSR_GPSR(IP4_15_12,		VI4_DATA17),
++	PINMUX_IPSR_MSEL(IP4_15_12,		VI5_DATA3_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP4_15_12,		DU_DG6),
++	PINMUX_IPSR_GPSR(IP4_15_12,		LCDOUT14),
++
++	PINMUX_IPSR_GPSR(IP4_19_16,		A13),
++	PINMUX_IPSR_MSEL(IP4_19_16,		SCK5_A,		SEL_SCIF5_0),
++	PINMUX_IPSR_MSEL(IP4_19_16,		MSIOF2_SCK_B,	SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP4_19_16,		VI4_DATA14),
++	PINMUX_IPSR_MSEL(IP4_19_16,		HRX4_D,		SEL_HSCIF4_3),
++	PINMUX_IPSR_GPSR(IP4_19_16,		DU_DB2),
++	PINMUX_IPSR_GPSR(IP4_19_16,		LCDOUT2),
++
++	PINMUX_IPSR_GPSR(IP4_23_20,		A14),
++	PINMUX_IPSR_GPSR(IP4_23_20,		MSIOF1_SS1),
++	PINMUX_IPSR_MSEL(IP4_23_20,		MSIOF2_RXD_B,	SEL_MSIOF2_1),
++	PINMUX_IPSR_GPSR(IP4_23_20,		VI4_DATA15),
++	PINMUX_IPSR_GPSR(IP4_23_20,		HTX4_D),
++	PINMUX_IPSR_GPSR(IP4_23_20,		DU_DB3),
++	PINMUX_IPSR_GPSR(IP4_23_20,		LCDOUT3),
++
++	PINMUX_IPSR_GPSR(IP4_27_24,		A15),
++	PINMUX_IPSR_GPSR(IP4_27_24,		MSIOF1_SS2),
++	PINMUX_IPSR_GPSR(IP4_27_24,		MSIOF2_TXD_B),
++	PINMUX_IPSR_GPSR(IP4_27_24,		VI4_DATA18),
++	PINMUX_IPSR_MSEL(IP4_27_24,		VI5_DATA4_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP4_27_24,		DU_DB4),
++	PINMUX_IPSR_GPSR(IP4_27_24,		LCDOUT4),
++
++	PINMUX_IPSR_GPSR(IP4_31_28,		A16),
++	PINMUX_IPSR_GPSR(IP4_31_28,		MSIOF1_SYNC),
++	PINMUX_IPSR_GPSR(IP4_31_28,		MSIOF2_SS1_B),
++	PINMUX_IPSR_GPSR(IP4_31_28,		VI4_DATA19),
++	PINMUX_IPSR_MSEL(IP4_31_28,		VI5_DATA5_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP4_31_28,		DU_DB5),
++	PINMUX_IPSR_GPSR(IP4_31_28,		LCDOUT5),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0,		A17),
++	PINMUX_IPSR_GPSR(IP5_3_0,		MSIOF1_RXD),
++	PINMUX_IPSR_GPSR(IP5_3_0,		VI4_DATA20),
++	PINMUX_IPSR_MSEL(IP5_3_0,		VI5_DATA6_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP5_3_0,		DU_DB6),
++	PINMUX_IPSR_GPSR(IP5_3_0,		LCDOUT6),
++
++	PINMUX_IPSR_GPSR(IP5_7_4,		A18),
++	PINMUX_IPSR_GPSR(IP5_7_4,		MSIOF1_TXD),
++	PINMUX_IPSR_GPSR(IP5_7_4,		VI4_DATA21),
++	PINMUX_IPSR_MSEL(IP5_7_4,		VI5_DATA7_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP5_7_4,		DU_DB0),
++	PINMUX_IPSR_MSEL(IP5_7_4,		HRX4_E,		SEL_HSCIF4_4),
++	PINMUX_IPSR_GPSR(IP5_7_4,		LCDOUT0),
++
++	PINMUX_IPSR_GPSR(IP5_11_8,		A19),
++	PINMUX_IPSR_GPSR(IP5_11_8,		MSIOF1_SCK),
++	PINMUX_IPSR_GPSR(IP5_11_8,		VI4_DATA22),
++	PINMUX_IPSR_MSEL(IP5_11_8,		VI5_DATA2_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP5_11_8,		DU_DB1),
++	PINMUX_IPSR_GPSR(IP5_11_8,		HTX4_E),
++	PINMUX_IPSR_GPSR(IP5_11_8,		LCDOUT1),
++
++	PINMUX_IPSR_GPSR(IP5_15_12,		CS0_N),
++	PINMUX_IPSR_GPSR(IP5_15_12,		SCL5),
++	PINMUX_IPSR_GPSR(IP5_15_12,		DU_DR0),
++	PINMUX_IPSR_MSEL(IP5_15_12,		VI4_DATA2_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP5_15_12,		LCDOUT16),
++
++	PINMUX_IPSR_GPSR(IP5_19_16,		WE0_N),
++	PINMUX_IPSR_GPSR(IP5_19_16,		SDA5),
++	PINMUX_IPSR_GPSR(IP5_19_16,		DU_DR1),
++	PINMUX_IPSR_MSEL(IP5_19_16,		VI4_DATA3_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP5_19_16,		LCDOUT17),
++
++	PINMUX_IPSR_GPSR(IP5_23_20,		D0),
++	PINMUX_IPSR_MSEL(IP5_23_20,		MSIOF3_SCK_A,	SEL_MSIOF3_0),
++	PINMUX_IPSR_GPSR(IP5_23_20,		DU_DR2),
++	PINMUX_IPSR_MSEL(IP5_23_20,		CTS4_N_C,	SEL_SCIF4_2),
++	PINMUX_IPSR_GPSR(IP5_23_20,		LCDOUT18),
++
++	PINMUX_IPSR_GPSR(IP5_27_24,		D1),
++	PINMUX_IPSR_MSEL(IP5_27_24,		MSIOF3_SYNC_A,	SEL_MSIOF3_0),
++	PINMUX_IPSR_MSEL(IP5_27_24,		SCK3_A,		SEL_SCIF3_0),
++	PINMUX_IPSR_GPSR(IP5_27_24,		VI4_DATA23),
++	PINMUX_IPSR_MSEL(IP5_27_24,		VI5_CLKENB_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP5_27_24,		DU_DB7),
++	PINMUX_IPSR_MSEL(IP5_27_24,		RTS4_N_TANS_C,	SEL_SCIF4_2),
++	PINMUX_IPSR_GPSR(IP5_27_24,		LCDOUT7),
++
++	PINMUX_IPSR_GPSR(IP5_31_28,		D2),
++	PINMUX_IPSR_MSEL(IP5_31_28,		MSIOF3_RXD_A,	SEL_MSIOF3_0),
++	PINMUX_IPSR_MSEL(IP5_31_28,		RX5_C,		SEL_SCIF5_2),
++	PINMUX_IPSR_MSEL(IP5_31_28,		VI5_DATA14_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP5_31_28,		DU_DR3),
++	PINMUX_IPSR_MSEL(IP5_31_28,		RX4_C,		SEL_SCIF4_2),
++	PINMUX_IPSR_GPSR(IP5_31_28,		LCDOUT19),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0,		D3),
++	PINMUX_IPSR_GPSR(IP6_3_0,		MSIOF3_TXD_A),
++	PINMUX_IPSR_GPSR(IP6_3_0,		TX5_C),
++	PINMUX_IPSR_MSEL(IP6_3_0,		VI5_DATA15_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP6_3_0,		DU_DR4),
++	PINMUX_IPSR_GPSR(IP6_3_0,		TX4_C),
++	PINMUX_IPSR_GPSR(IP6_3_0,		LCDOUT20),
++
++	PINMUX_IPSR_GPSR(IP6_7_4,		D4),
++	PINMUX_IPSR_GPSR(IP6_7_4,		CANFD1_TX),
++	PINMUX_IPSR_MSEL(IP6_7_4,		HSCK3_B,	SEL_HSCIF3_1),
++	PINMUX_IPSR_GPSR(IP6_7_4,		CAN1_TX),
++	PINMUX_IPSR_MSEL(IP6_7_4,		RTS3_N_TANS_A,	SEL_SCIF3_0),
++	PINMUX_IPSR_GPSR(IP6_7_4,		MSIOF3_SS2_A),
++	PINMUX_IPSR_MSEL(IP6_7_4,		VI5_DATA1_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP6_11_8,		D5),
++	PINMUX_IPSR_MSEL(IP6_11_8,		RX3_A,		SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP6_11_8,		HRX3_B,		SEL_HSCIF3_1),
++	PINMUX_IPSR_GPSR(IP6_11_8,		DU_DR5),
++	PINMUX_IPSR_MSEL(IP6_11_8,		VI4_DATA4_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP6_11_8,		LCDOUT21),
++
++	PINMUX_IPSR_GPSR(IP6_15_12,		D6),
++	PINMUX_IPSR_GPSR(IP6_15_12,		TX3_A),
++	PINMUX_IPSR_GPSR(IP6_15_12,		HTX3_B),
++	PINMUX_IPSR_GPSR(IP6_15_12,		DU_DR6),
++	PINMUX_IPSR_MSEL(IP6_15_12,		VI4_DATA5_B,	SEL_VIN4_1),
++	PINMUX_IPSR_GPSR(IP6_15_12,		LCDOUT22),
++
++	PINMUX_IPSR_GPSR(IP6_19_16,		D7),
++	PINMUX_IPSR_GPSR(IP6_19_16,		CANFD1_RX),
++	PINMUX_IPSR_GPSR(IP6_19_16,		IRQ5),
++	PINMUX_IPSR_GPSR(IP6_19_16,		CAN1_RX),
++	PINMUX_IPSR_MSEL(IP6_19_16,		CTS3_N_A,	SEL_SCIF3_0),
++	PINMUX_IPSR_MSEL(IP6_19_16,		VI5_DATA2_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP6_23_20,		D8),
++	PINMUX_IPSR_MSEL(IP6_23_20,		MSIOF2_SCK_A,	SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP6_23_20,		SCK4_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_MSEL(IP6_23_20,		VI5_DATA12_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP6_23_20,		DU_DR7),
++	PINMUX_IPSR_MSEL(IP6_23_20,		RIF3_CLK_B,	SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP6_23_20,		HCTS3_N_E,	SEL_HSCIF3_4),
++	PINMUX_IPSR_GPSR(IP6_23_20,		LCDOUT23),
++
++	PINMUX_IPSR_GPSR(IP6_27_24,		D9),
++	PINMUX_IPSR_MSEL(IP6_27_24,		MSIOF2_SYNC_A,	SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP6_27_24,		VI5_DATA10_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP6_27_24,		DU_DG0),
++	PINMUX_IPSR_MSEL(IP6_27_24,		RIF3_SYNC_B,	SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP6_27_24,		HRX3_E,		SEL_HSCIF3_4),
++	PINMUX_IPSR_GPSR(IP6_27_24,		LCDOUT8),
++
++	PINMUX_IPSR_GPSR(IP6_31_28,		D10),
++	PINMUX_IPSR_MSEL(IP6_31_28,		MSIOF2_RXD_A,	SEL_MSIOF2_0),
++	PINMUX_IPSR_MSEL(IP6_31_28,		VI5_DATA13_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP6_31_28,		DU_DG1),
++	PINMUX_IPSR_MSEL(IP6_31_28,		RIF3_D0_B,	SEL_DRIF3_1),
++	PINMUX_IPSR_GPSR(IP6_31_28,		HTX3_E),
++	PINMUX_IPSR_GPSR(IP6_31_28,		LCDOUT9),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0,		D11),
++	PINMUX_IPSR_GPSR(IP7_3_0,		MSIOF2_TXD_A),
++	PINMUX_IPSR_MSEL(IP7_3_0,		VI5_DATA11_A,	SEL_VIN5_0),
++	PINMUX_IPSR_GPSR(IP7_3_0,		DU_DG2),
++	PINMUX_IPSR_MSEL(IP7_3_0,		RIF3_D1_B,	SEL_DRIF3_1),
++	PINMUX_IPSR_MSEL(IP7_3_0,		HRTS3_N_E,	SEL_HSCIF3_4),
++	PINMUX_IPSR_GPSR(IP7_3_0,		LCDOUT10),
++
++	PINMUX_IPSR_GPSR(IP7_7_4,		D12),
++	PINMUX_IPSR_GPSR(IP7_7_4,		CANFD0_TX),
++	PINMUX_IPSR_GPSR(IP7_7_4,		TX4_B),
++	PINMUX_IPSR_GPSR(IP7_7_4,		CAN0_TX),
++	PINMUX_IPSR_MSEL(IP7_7_4,		VI5_DATA8_A,	SEL_VIN5_0),
++	PINMUX_IPSR_MSEL(IP7_7_4,		VI5_DATA3_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP7_11_8,		D13),
++	PINMUX_IPSR_GPSR(IP7_11_8,		CANFD0_RX),
++	PINMUX_IPSR_MSEL(IP7_11_8,		RX4_B,		SEL_SCIF4_1),
++	PINMUX_IPSR_GPSR(IP7_11_8,		CAN0_RX),
++	PINMUX_IPSR_MSEL(IP7_11_8,		VI5_DATA9_A,	SEL_VIN5_0),
++	PINMUX_IPSR_MSEL(IP7_11_8,		SCL7_B,		SEL_I2C7_1),
++	PINMUX_IPSR_MSEL(IP7_11_8,		VI5_DATA4_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP7_15_12,		D14),
++	PINMUX_IPSR_GPSR(IP7_15_12,		CAN_CLK),
++	PINMUX_IPSR_MSEL(IP7_15_12,		HRX3_A,		SEL_HSCIF3_0),
++	PINMUX_IPSR_GPSR(IP7_15_12,		MSIOF2_SS2_A),
++	PINMUX_IPSR_MSEL(IP7_15_12,		SDA7_B,		SEL_I2C7_1),
++	PINMUX_IPSR_MSEL(IP7_15_12,		VI5_DATA5_B,	SEL_VIN5_1),
++
++	PINMUX_IPSR_GPSR(IP7_19_16,		D15),
++	PINMUX_IPSR_GPSR(IP7_19_16,		MSIOF2_SS1_A),
++	PINMUX_IPSR_GPSR(IP7_19_16,		HTX3_A),
++	PINMUX_IPSR_GPSR(IP7_19_16,		MSIOF3_SS1_A),
++	PINMUX_IPSR_GPSR(IP7_19_16,		DU_DG3),
++	PINMUX_IPSR_GPSR(IP7_19_16,		LCDOUT11),
++
++	PINMUX_IPSR_GPSR(IP7_23_20,		SCL4),
++	PINMUX_IPSR_GPSR(IP7_23_20,		CS1_N_A26),
++	PINMUX_IPSR_GPSR(IP7_23_20,		DU_DOTCLKIN0),
++	PINMUX_IPSR_MSEL(IP7_23_20,		VI4_DATA6_B,	SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP7_23_20,		VI5_DATA6_B,	SEL_VIN5_1),
++	PINMUX_IPSR_GPSR(IP7_23_20,		QCLK),
++
++	PINMUX_IPSR_GPSR(IP7_27_24,		SDA4),
++	PINMUX_IPSR_GPSR(IP7_27_24,		WE1_N),
++	PINMUX_IPSR_MSEL(IP7_27_24,		VI4_DATA7_B,	SEL_VIN4_1),
++	PINMUX_IPSR_MSEL(IP7_27_24,		VI5_DATA7_B,	SEL_VIN5_1),
++	PINMUX_IPSR_GPSR(IP7_27_24,		QPOLB),
++
++	PINMUX_IPSR_GPSR(IP7_31_28,		SD0_CLK),
++	PINMUX_IPSR_GPSR(IP7_31_28,		NFDATA8),
++	PINMUX_IPSR_MSEL(IP7_31_28,		SCL1_C,		SEL_I2C1_2),
++	PINMUX_IPSR_MSEL(IP7_31_28,		HSCK1_B,	SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP7_31_28,		SDA2_E,		SEL_I2C2_4),
++	PINMUX_IPSR_MSEL(IP7_31_28,		FMCLK_B,	SEL_FM_1),
++
++	/* IPSR8 */
++	PINMUX_IPSR_GPSR(IP8_3_0,		SD0_CMD),
++	PINMUX_IPSR_GPSR(IP8_3_0,		NFDATA9),
++	PINMUX_IPSR_MSEL(IP8_3_0,		HRX1_B,		SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP8_3_0,		SPEEDIN_B,	SEL_SPEED_PULSE_IF_1),
++
++	PINMUX_IPSR_GPSR(IP8_7_4,		SD0_DAT0),
++	PINMUX_IPSR_GPSR(IP8_7_4,		NFDATA10),
++	PINMUX_IPSR_GPSR(IP8_7_4,		HTX1_B),
++	PINMUX_IPSR_MSEL(IP8_7_4,		REMOCON_B,	SEL_REMOCON_1),
++
++	PINMUX_IPSR_GPSR(IP8_11_8,		SD0_DAT1),
++	PINMUX_IPSR_GPSR(IP8_11_8,		NFDATA11),
++	PINMUX_IPSR_MSEL(IP8_11_8,		SDA2_C,		SEL_I2C2_2),
++	PINMUX_IPSR_MSEL(IP8_11_8,		HCTS1_N_B,	SEL_HSCIF1_1),
++	PINMUX_IPSR_MSEL(IP8_11_8,		FMIN_B,		SEL_FM_1),
++
++	PINMUX_IPSR_GPSR(IP8_15_12,		SD0_DAT2),
++	PINMUX_IPSR_GPSR(IP8_15_12,		NFDATA12),
++	PINMUX_IPSR_MSEL(IP8_15_12,		SCL2_C,		SEL_I2C2_2),
++	PINMUX_IPSR_MSEL(IP8_15_12,		HRTS1_N_B,	SEL_HSCIF1_1),
++	PINMUX_IPSR_GPSR(IP8_15_12,		BPFCLK_B),
++
++	PINMUX_IPSR_GPSR(IP8_19_16,		SD0_DAT3),
++	PINMUX_IPSR_GPSR(IP8_19_16,		NFDATA13),
++	PINMUX_IPSR_MSEL(IP8_19_16,		SDA1_C,		SEL_I2C1_2),
++	PINMUX_IPSR_MSEL(IP8_19_16,		SCL2_E,		SEL_I2C2_4),
++	PINMUX_IPSR_MSEL(IP8_19_16,		SPEEDIN_C,	SEL_SPEED_PULSE_IF_2),
++	PINMUX_IPSR_MSEL(IP8_19_16,		REMOCON_C,	SEL_REMOCON_2),
++
++	PINMUX_IPSR_GPSR(IP8_23_20,		SD1_CLK),
++	PINMUX_IPSR_MSEL(IP8_23_20,		NFDATA14_B,	SEL_NDFC_1),
++
++	PINMUX_IPSR_GPSR(IP8_27_24,		SD1_CMD),
++	PINMUX_IPSR_MSEL(IP8_27_24,		NFDATA15_B,	SEL_NDFC_1),
++
++	PINMUX_IPSR_GPSR(IP8_31_28,		SD1_DAT0),
++	PINMUX_IPSR_MSEL(IP8_31_28,		NFWP_N_B,	SEL_NDFC_1),
++
++	/* IPSR9 */
++	PINMUX_IPSR_GPSR(IP9_3_0,		SD1_DAT1),
++	PINMUX_IPSR_MSEL(IP9_3_0,		NFCE_N_B,	SEL_NDFC_1),
++
++	PINMUX_IPSR_GPSR(IP9_7_4,		SD1_DAT2),
++	PINMUX_IPSR_MSEL(IP9_7_4,		NFALE_B,	SEL_NDFC_1),
++
++	PINMUX_IPSR_GPSR(IP9_11_8,		SD1_DAT3),
++	PINMUX_IPSR_MSEL(IP9_11_8,		NFRB_N_B,	SEL_NDFC_1),
++
++	PINMUX_IPSR_GPSR(IP9_15_12,		SD3_CLK),
++	PINMUX_IPSR_GPSR(IP9_15_12,		NFWE_N),
++
++	PINMUX_IPSR_GPSR(IP9_19_16,		SD3_CMD),
++	PINMUX_IPSR_GPSR(IP9_19_16,		NFRE_N),
++
++	PINMUX_IPSR_GPSR(IP9_23_20,		SD3_DAT0),
++	PINMUX_IPSR_GPSR(IP9_23_20,		NFDATA0),
++
++	PINMUX_IPSR_GPSR(IP9_27_24,		SD3_DAT1),
++	PINMUX_IPSR_GPSR(IP9_27_24,		NFDATA1),
++
++	PINMUX_IPSR_GPSR(IP9_31_28,		SD3_DAT2),
++	PINMUX_IPSR_GPSR(IP9_31_28,		NFDATA2),
++
++	/* IPSR10 */
++	PINMUX_IPSR_GPSR(IP10_3_0,		SD3_DAT3),
++	PINMUX_IPSR_GPSR(IP10_3_0,		NFDATA3),
++
++	PINMUX_IPSR_GPSR(IP10_7_4,		SD3_DAT4),
++	PINMUX_IPSR_GPSR(IP10_7_4,		NFDATA4),
++
++	PINMUX_IPSR_GPSR(IP10_11_8,		SD3_DAT5),
++	PINMUX_IPSR_GPSR(IP10_11_8,		NFDATA5),
++
++	PINMUX_IPSR_GPSR(IP10_15_12,		SD3_DAT6),
++	PINMUX_IPSR_GPSR(IP10_15_12,		NFDATA6),
++
++	PINMUX_IPSR_GPSR(IP10_19_16,		SD3_DAT7),
++	PINMUX_IPSR_GPSR(IP10_19_16,		NFDATA7),
++
++	PINMUX_IPSR_GPSR(IP10_23_20,		SD3_DS),
++	PINMUX_IPSR_GPSR(IP10_23_20,		NFCLE),
++
++	PINMUX_IPSR_GPSR(IP10_27_24,		SD0_CD),
++	PINMUX_IPSR_GPSR(IP10_27_24,		NFALE_A),
++	PINMUX_IPSR_GPSR(IP10_27_24,		SD3_CD),
++	PINMUX_IPSR_MSEL(IP10_27_24,		RIF0_CLK_B,	SEL_DRIF0_1),
++	PINMUX_IPSR_MSEL(IP10_27_24,		SCL2_B,		SEL_I2C2_1),
++	PINMUX_IPSR_MSEL(IP10_27_24,		TCLK1_A,	SEL_TIMER_TMU_0),
++	PINMUX_IPSR_MSEL(IP10_27_24,		SSI_SCK2_B,	SEL_SSI2_1),
++	PINMUX_IPSR_GPSR(IP10_27_24,		TS_SCK0),
++
++	PINMUX_IPSR_GPSR(IP10_31_28,		SD0_WP),
++	PINMUX_IPSR_GPSR(IP10_31_28,		NFRB_N_A),
++	PINMUX_IPSR_GPSR(IP10_31_28,		SD3_WP),
++	PINMUX_IPSR_MSEL(IP10_31_28,		RIF0_D0_B,	SEL_DRIF0_1),
++	PINMUX_IPSR_MSEL(IP10_31_28,		SDA2_B,		SEL_I2C2_1),
++	PINMUX_IPSR_MSEL(IP10_31_28,		TCLK2_A,	SEL_TIMER_TMU_0),
++	PINMUX_IPSR_MSEL(IP10_31_28,		SSI_WS2_B,	SEL_SSI2_1),
++	PINMUX_IPSR_GPSR(IP10_31_28,		TS_SDAT0),
++
++	/* IPSR11 */
++	PINMUX_IPSR_GPSR(IP11_3_0,		SD1_CD),
++	PINMUX_IPSR_MSEL(IP11_3_0,		NFCE_N_A,	SEL_NDFC_0),
++	PINMUX_IPSR_GPSR(IP11_3_0,		SSI_SCK1),
++	PINMUX_IPSR_MSEL(IP11_3_0,		RIF0_D1_B,	SEL_DRIF0_1),
++	PINMUX_IPSR_GPSR(IP11_3_0,		TS_SDEN0),
++
++	PINMUX_IPSR_GPSR(IP11_7_4,		SD1_WP),
++	PINMUX_IPSR_MSEL(IP11_7_4,		NFWP_N_A,	SEL_NDFC_0),
++	PINMUX_IPSR_GPSR(IP11_7_4,		SSI_WS1),
++	PINMUX_IPSR_MSEL(IP11_7_4,		RIF0_SYNC_B,	SEL_DRIF0_1),
++	PINMUX_IPSR_GPSR(IP11_7_4,		TS_SPSYNC0),
++
++	PINMUX_IPSR_MSEL(IP11_11_8,		RX0_A,		SEL_SCIF0_0),
++	PINMUX_IPSR_MSEL(IP11_11_8,		HRX1_A,		SEL_HSCIF1_0),
++	PINMUX_IPSR_MSEL(IP11_11_8,		SSI_SCK2_A,	SEL_SSI2_0),
++	PINMUX_IPSR_GPSR(IP11_11_8,		RIF1_SYNC),
++	PINMUX_IPSR_GPSR(IP11_11_8,		TS_SCK1),
++
++	PINMUX_IPSR_GPSR(IP11_15_12,		TX0_A),
++	PINMUX_IPSR_GPSR(IP11_15_12,		HTX1_A),
++	PINMUX_IPSR_MSEL(IP11_15_12,		SSI_WS2_A,	SEL_SSI2_0),
++	PINMUX_IPSR_GPSR(IP11_15_12,		RIF1_D0),
++	PINMUX_IPSR_GPSR(IP11_15_12,		TS_SDAT1),
++
++	PINMUX_IPSR_MSEL(IP11_19_16,		CTS0_N_A,	SEL_SCIF0_0),
++	PINMUX_IPSR_MSEL(IP11_19_16,		NFDATA14_A,	SEL_NDFC_0),
++	PINMUX_IPSR_GPSR(IP11_19_16,		AUDIO_CLKOUT_A),
++	PINMUX_IPSR_GPSR(IP11_19_16,		RIF1_D1),
++	PINMUX_IPSR_MSEL(IP11_19_16,		SCIF_CLK_A,	SEL_SCIF_0),
++	PINMUX_IPSR_MSEL(IP11_19_16,		FMCLK_A,	SEL_FM_0),
++
++	PINMUX_IPSR_MSEL(IP11_23_20,		RTS0_N_TANS_A,	SEL_SCIF0_0),
++	PINMUX_IPSR_MSEL(IP11_23_20,		NFDATA15_A,	SEL_NDFC_0),
++	PINMUX_IPSR_GPSR(IP11_23_20,		AUDIO_CLKOUT1_A),
++	PINMUX_IPSR_GPSR(IP11_23_20,		RIF1_CLK),
++	PINMUX_IPSR_MSEL(IP11_23_20,		SCL2_A,		SEL_I2C2_0),
++	PINMUX_IPSR_MSEL(IP11_23_20,		FMIN_A,		SEL_FM_0),
++
++	PINMUX_IPSR_MSEL(IP11_27_24,		SCK0_A,		SEL_SCIF0_0),
++	PINMUX_IPSR_MSEL(IP11_27_24,		HSCK1_A,	SEL_HSCIF1_0),
++	PINMUX_IPSR_GPSR(IP11_27_24,		USB3HS0_ID),
++	PINMUX_IPSR_GPSR(IP11_27_24,		RTS1_N_TANS),
++	PINMUX_IPSR_MSEL(IP11_27_24,		SDA2_A,		SEL_I2C2_0),
++	PINMUX_IPSR_MSEL(IP11_27_24,		FMCLK_C,	SEL_FM_2),
++	PINMUX_IPSR_GPSR(IP11_27_24,		USB1_ID),
++
++	PINMUX_IPSR_GPSR(IP11_31_28,		RX1),
++	PINMUX_IPSR_MSEL(IP11_31_28,		HRX2_B,		SEL_HSCIF2_1),
++	PINMUX_IPSR_MSEL(IP11_31_28,		SSI_SCK9_B,	SEL_SSI9_1),
++	PINMUX_IPSR_GPSR(IP11_31_28,		AUDIO_CLKOUT1_B),
++
++	/* IPSR12 */
++	PINMUX_IPSR_GPSR(IP12_3_0,		TX1),
++	PINMUX_IPSR_GPSR(IP12_3_0,		HTX2_B),
++	PINMUX_IPSR_MSEL(IP12_3_0,		SSI_WS9_B,	SEL_SSI9_1),
++	PINMUX_IPSR_GPSR(IP12_3_0,		AUDIO_CLKOUT3_B),
++
++	PINMUX_IPSR_GPSR(IP12_7_4,		SCK2_A),
++	PINMUX_IPSR_MSEL(IP12_7_4,		HSCK0_A,	SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP12_7_4,		AUDIO_CLKB_A,	SEL_ADGB_0),
++	PINMUX_IPSR_GPSR(IP12_7_4,		CTS1_N),
++	PINMUX_IPSR_MSEL(IP12_7_4,		RIF0_CLK_A,	SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP12_7_4,		REMOCON_A,	SEL_REMOCON_0),
++	PINMUX_IPSR_MSEL(IP12_7_4,		SCIF_CLK_B,	SEL_SCIF_1),
++
++	PINMUX_IPSR_GPSR(IP12_11_8,		TX2_A),
++	PINMUX_IPSR_MSEL(IP12_11_8,		HRX0_A,		SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP12_11_8,		AUDIO_CLKOUT2_A),
++	PINMUX_IPSR_MSEL(IP12_11_8,		SCL1_A,		SEL_I2C1_0),
++	PINMUX_IPSR_MSEL(IP12_11_8,		FSO_CFE_0_N_A,	SEL_FSO_0),
++	PINMUX_IPSR_GPSR(IP12_11_8,		TS_SDEN1),
++
++	PINMUX_IPSR_GPSR(IP12_15_12,		RX2_A),
++	PINMUX_IPSR_GPSR(IP12_15_12,		HTX0_A),
++	PINMUX_IPSR_GPSR(IP12_15_12,		AUDIO_CLKOUT3_A),
++	PINMUX_IPSR_MSEL(IP12_15_12,		SDA1_A,		SEL_I2C1_0),
++	PINMUX_IPSR_MSEL(IP12_15_12,		FSO_CFE_1_N_A,	SEL_FSO_0),
++	PINMUX_IPSR_GPSR(IP12_15_12,		TS_SPSYNC1),
++
++	PINMUX_IPSR_GPSR(IP12_19_16,		MSIOF0_SCK),
++	PINMUX_IPSR_GPSR(IP12_19_16,		SSI_SCK78),
++
++	PINMUX_IPSR_GPSR(IP12_23_20,		MSIOF0_RXD),
++	PINMUX_IPSR_GPSR(IP12_23_20,		SSI_WS78),
++	PINMUX_IPSR_GPSR(IP12_23_20,		TX2_B),
++
++	PINMUX_IPSR_GPSR(IP12_27_24,		MSIOF0_TXD),
++	PINMUX_IPSR_GPSR(IP12_27_24,		SSI_SDATA7),
++	PINMUX_IPSR_GPSR(IP12_27_24,		RX2_B),
++
++	PINMUX_IPSR_GPSR(IP12_31_28,		MSIOF0_SYNC),
++	PINMUX_IPSR_GPSR(IP12_31_28,		AUDIO_CLKOUT_B),
++	PINMUX_IPSR_GPSR(IP12_31_28,		SSI_SDATA8),
++
++	/* IPSR13 */
++	PINMUX_IPSR_GPSR(IP13_3_0,		MSIOF0_SS1),
++	PINMUX_IPSR_MSEL(IP13_3_0,		HRX2_A,		SEL_HSCIF2_0),
++	PINMUX_IPSR_GPSR(IP13_3_0,		SSI_SCK4),
++	PINMUX_IPSR_MSEL(IP13_3_0,		HCTS0_N_A,	SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP13_3_0,		BPFCLK_C),
++	PINMUX_IPSR_MSEL(IP13_3_0,		SPEEDIN_A,	SEL_SPEED_PULSE_IF_0),
++
++	PINMUX_IPSR_GPSR(IP13_7_4,		MSIOF0_SS2),
++	PINMUX_IPSR_GPSR(IP13_7_4,		HTX2_A),
++	PINMUX_IPSR_GPSR(IP13_7_4,		SSI_WS4),
++	PINMUX_IPSR_MSEL(IP13_7_4,		HRTS0_N_A,	SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP13_7_4,		FMIN_C,		SEL_FM_2),
++	PINMUX_IPSR_GPSR(IP13_7_4,		BPFCLK_A),
++
++	PINMUX_IPSR_GPSR(IP13_11_8,		SSI_SDATA9),
++	PINMUX_IPSR_MSEL(IP13_11_8,		AUDIO_CLKC_A,	SEL_ADGC_0),
++	PINMUX_IPSR_GPSR(IP13_11_8,		SCK1),
++
++	PINMUX_IPSR_GPSR(IP13_15_12,		MLB_CLK),
++	PINMUX_IPSR_MSEL(IP13_15_12,		RX0_B,		SEL_SCIF0_1),
++	PINMUX_IPSR_MSEL(IP13_15_12,		RIF0_D0_A,	SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP13_15_12,		SCL1_B,		SEL_I2C1_1),
++	PINMUX_IPSR_MSEL(IP13_15_12,		TCLK1_B,	SEL_TIMER_TMU_1),
++	PINMUX_IPSR_GPSR(IP13_15_12,		SIM0_RST_A),
++
++	PINMUX_IPSR_GPSR(IP13_19_16,		MLB_SIG),
++	PINMUX_IPSR_MSEL(IP13_19_16,		SCK0_B,		SEL_SCIF0_1),
++	PINMUX_IPSR_MSEL(IP13_19_16,		RIF0_D1_A,	SEL_DRIF0_0),
++	PINMUX_IPSR_MSEL(IP13_19_16,		SDA1_B,		SEL_I2C1_1),
++	PINMUX_IPSR_MSEL(IP13_19_16,		TCLK2_B,	SEL_TIMER_TMU_1),
++	PINMUX_IPSR_MSEL(IP13_19_16,		SIM0_D_A,	SEL_SIMCARD_0),
++
++	PINMUX_IPSR_GPSR(IP13_23_20,		MLB_DAT),
++	PINMUX_IPSR_GPSR(IP13_23_20,		TX0_B),
++	PINMUX_IPSR_MSEL(IP13_23_20,		RIF0_SYNC_A,	SEL_DRIF0_0),
++	PINMUX_IPSR_GPSR(IP13_23_20,		SIM0_CLK_A),
++
++	PINMUX_IPSR_GPSR(IP13_27_24,		SSI_SCK01239),
++
++	PINMUX_IPSR_GPSR(IP13_31_28,		SSI_WS01239),
++
++	/* IPSR14 */
++	PINMUX_IPSR_GPSR(IP14_3_0,		SSI_SDATA0),
++
++	PINMUX_IPSR_GPSR(IP14_7_4,		SSI_SDATA1),
++	PINMUX_IPSR_MSEL(IP14_7_4,		AUDIO_CLKC_B,	SEL_ADGC_1),
++	PINMUX_IPSR_MSEL(IP14_7_4,		PWM0_B,		SEL_PWM0_1),
++
++	PINMUX_IPSR_GPSR(IP14_11_8,		SSI_SDATA2),
++	PINMUX_IPSR_GPSR(IP14_11_8,		AUDIO_CLKOUT2_B),
++	PINMUX_IPSR_MSEL(IP14_11_8,		SSI_SCK9_A,	SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP14_11_8,		PWM1_B,		SEL_PWM1_1),
++
++	PINMUX_IPSR_GPSR(IP14_15_12,		SSI_SCK349),
++	PINMUX_IPSR_MSEL(IP14_15_12,		PWM2_C,		SEL_PWM2_2),
++
++	PINMUX_IPSR_GPSR(IP14_19_16,		SSI_WS349),
++	PINMUX_IPSR_MSEL(IP14_19_16,		PWM3_C,		SEL_PWM3_2),
++
++	PINMUX_IPSR_GPSR(IP14_23_20,		SSI_SDATA3),
++	PINMUX_IPSR_GPSR(IP14_23_20,		AUDIO_CLKOUT1_C),
++	PINMUX_IPSR_MSEL(IP14_23_20,		AUDIO_CLKB_B,	SEL_ADGB_1),
++	PINMUX_IPSR_MSEL(IP14_23_20,		PWM4_B,		SEL_PWM4_1),
++
++	PINMUX_IPSR_GPSR(IP14_27_24,		SSI_SDATA4),
++	PINMUX_IPSR_MSEL(IP14_27_24,		SSI_WS9_A,	SEL_SSI9_0),
++	PINMUX_IPSR_MSEL(IP14_27_24,		PWM5_B,		SEL_PWM5_1),
++
++	PINMUX_IPSR_GPSR(IP14_31_28,		SSI_SCK5),
++	PINMUX_IPSR_MSEL(IP14_31_28,		HRX0_B,		SEL_HSCIF0_1),
++	PINMUX_IPSR_GPSR(IP14_31_28,		USB0_PWEN_B),
++	PINMUX_IPSR_MSEL(IP14_31_28,		SCL2_D,		SEL_I2C2_3),
++	PINMUX_IPSR_MSEL(IP14_31_28,		PWM6_B,		SEL_PWM6_1),
++
++	/* IPSR15 */
++	PINMUX_IPSR_GPSR(IP15_3_0,		SSI_WS5),
++	PINMUX_IPSR_GPSR(IP15_3_0,		HTX0_B),
++	PINMUX_IPSR_MSEL(IP15_3_0,		USB0_OVC_B,	SEL_USB_20_CH0_1),
++	PINMUX_IPSR_MSEL(IP15_3_0,		SDA2_D,		SEL_I2C2_3),
++
++	PINMUX_IPSR_GPSR(IP15_7_4,		SSI_SDATA5),
++	PINMUX_IPSR_MSEL(IP15_7_4,		HSCK0_B,	SEL_HSCIF0_1),
++	PINMUX_IPSR_MSEL(IP15_7_4,		AUDIO_CLKB_C,	SEL_ADGB_2),
++	PINMUX_IPSR_GPSR(IP15_7_4,		TPU0TO0),
++
++	PINMUX_IPSR_GPSR(IP15_11_8,		SSI_SCK6),
++	PINMUX_IPSR_MSEL(IP15_11_8,		HSCK2_A,	SEL_HSCIF2_0),
++	PINMUX_IPSR_MSEL(IP15_11_8,		AUDIO_CLKC_C,	SEL_ADGC_2),
++	PINMUX_IPSR_GPSR(IP15_11_8,		TPU0TO1),
++	PINMUX_IPSR_MSEL(IP15_11_8,		FSO_CFE_0_N_B,	SEL_FSO_1),
++	PINMUX_IPSR_GPSR(IP15_11_8,		SIM0_RST_B),
++
++	PINMUX_IPSR_GPSR(IP15_15_12,		SSI_WS6),
++	PINMUX_IPSR_MSEL(IP15_15_12,		HCTS2_N_A,	SEL_HSCIF2_0),
++	PINMUX_IPSR_GPSR(IP15_15_12,		AUDIO_CLKOUT2_C),
++	PINMUX_IPSR_GPSR(IP15_15_12,		TPU0TO2),
++	PINMUX_IPSR_MSEL(IP15_15_12,		SDA1_D,		SEL_I2C1_3),
++	PINMUX_IPSR_MSEL(IP15_15_12,		FSO_CFE_1_N_B,	SEL_FSO_1),
++	PINMUX_IPSR_MSEL(IP15_15_12,		SIM0_D_B,	SEL_SIMCARD_1),
++
++	PINMUX_IPSR_GPSR(IP15_19_16,		SSI_SDATA6),
++	PINMUX_IPSR_MSEL(IP15_19_16,		HRTS2_N_A,	SEL_HSCIF2_0),
++	PINMUX_IPSR_GPSR(IP15_19_16,		AUDIO_CLKOUT3_C),
++	PINMUX_IPSR_GPSR(IP15_19_16,		TPU0TO3),
++	PINMUX_IPSR_MSEL(IP15_19_16,		SCL1_D,		SEL_I2C1_3),
++	PINMUX_IPSR_MSEL(IP15_19_16,		FSO_TOE_N_B,	SEL_FSO_1),
++	PINMUX_IPSR_GPSR(IP15_19_16,		SIM0_CLK_B),
++
++	PINMUX_IPSR_GPSR(IP15_23_20,		AUDIO_CLKA),
++
++	PINMUX_IPSR_GPSR(IP15_27_24,		USB30_PWEN),
++	PINMUX_IPSR_GPSR(IP15_27_24,		USB0_PWEN_A),
++
++	PINMUX_IPSR_GPSR(IP15_31_28,		USB30_OVC),
++	PINMUX_IPSR_MSEL(IP15_31_28,		USB0_OVC_A,	SEL_USB_20_CH0_0),
++};
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++#define F_(x, y)	FN_##y
++#define FM(x)		FN_##x
++	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_17_FN,	GPSR0_17,
++		GP_0_16_FN,	GPSR0_16,
++		GP_0_15_FN,	GPSR0_15,
++		GP_0_14_FN,	GPSR0_14,
++		GP_0_13_FN,	GPSR0_13,
++		GP_0_12_FN,	GPSR0_12,
++		GP_0_11_FN,	GPSR0_11,
++		GP_0_10_FN,	GPSR0_10,
++		GP_0_9_FN,	GPSR0_9,
++		GP_0_8_FN,	GPSR0_8,
++		GP_0_7_FN,	GPSR0_7,
++		GP_0_6_FN,	GPSR0_6,
++		GP_0_5_FN,	GPSR0_5,
++		GP_0_4_FN,	GPSR0_4,
++		GP_0_3_FN,	GPSR0_3,
++		GP_0_2_FN,	GPSR0_2,
++		GP_0_1_FN,	GPSR0_1,
++		GP_0_0_FN,	GPSR0_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_22_FN,	GPSR1_22,
++		GP_1_21_FN,	GPSR1_21,
++		GP_1_20_FN,	GPSR1_20,
++		GP_1_19_FN,	GPSR1_19,
++		GP_1_18_FN,	GPSR1_18,
++		GP_1_17_FN,	GPSR1_17,
++		GP_1_16_FN,	GPSR1_16,
++		GP_1_15_FN,	GPSR1_15,
++		GP_1_14_FN,	GPSR1_14,
++		GP_1_13_FN,	GPSR1_13,
++		GP_1_12_FN,	GPSR1_12,
++		GP_1_11_FN,	GPSR1_11,
++		GP_1_10_FN,	GPSR1_10,
++		GP_1_9_FN,	GPSR1_9,
++		GP_1_8_FN,	GPSR1_8,
++		GP_1_7_FN,	GPSR1_7,
++		GP_1_6_FN,	GPSR1_6,
++		GP_1_5_FN,	GPSR1_5,
++		GP_1_4_FN,	GPSR1_4,
++		GP_1_3_FN,	GPSR1_3,
++		GP_1_2_FN,	GPSR1_2,
++		GP_1_1_FN,	GPSR1_1,
++		GP_1_0_FN,	GPSR1_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_2_25_FN,	GPSR2_25,
++		GP_2_24_FN,	GPSR2_24,
++		GP_2_23_FN,	GPSR2_23,
++		GP_2_22_FN,	GPSR2_22,
++		GP_2_21_FN,	GPSR2_21,
++		GP_2_20_FN,	GPSR2_20,
++		GP_2_19_FN,	GPSR2_19,
++		GP_2_18_FN,	GPSR2_18,
++		GP_2_17_FN,	GPSR2_17,
++		GP_2_16_FN,	GPSR2_16,
++		GP_2_15_FN,	GPSR2_15,
++		GP_2_14_FN,	GPSR2_14,
++		GP_2_13_FN,	GPSR2_13,
++		GP_2_12_FN,	GPSR2_12,
++		GP_2_11_FN,	GPSR2_11,
++		GP_2_10_FN,	GPSR2_10,
++		GP_2_9_FN,	GPSR2_9,
++		GP_2_8_FN,	GPSR2_8,
++		GP_2_7_FN,	GPSR2_7,
++		GP_2_6_FN,	GPSR2_6,
++		GP_2_5_FN,	GPSR2_5,
++		GP_2_4_FN,	GPSR2_4,
++		GP_2_3_FN,	GPSR2_3,
++		GP_2_2_FN,	GPSR2_2,
++		GP_2_1_FN,	GPSR2_1,
++		GP_2_0_FN,	GPSR2_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_15_FN,	GPSR3_15,
++		GP_3_14_FN,	GPSR3_14,
++		GP_3_13_FN,	GPSR3_13,
++		GP_3_12_FN,	GPSR3_12,
++		GP_3_11_FN,	GPSR3_11,
++		GP_3_10_FN,	GPSR3_10,
++		GP_3_9_FN,	GPSR3_9,
++		GP_3_8_FN,	GPSR3_8,
++		GP_3_7_FN,	GPSR3_7,
++		GP_3_6_FN,	GPSR3_6,
++		GP_3_5_FN,	GPSR3_5,
++		GP_3_4_FN,	GPSR3_4,
++		GP_3_3_FN,	GPSR3_3,
++		GP_3_2_FN,	GPSR3_2,
++		GP_3_1_FN,	GPSR3_1,
++		GP_3_0_FN,	GPSR3_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_10_FN,	GPSR4_10,
++		GP_4_9_FN,	GPSR4_9,
++		GP_4_8_FN,	GPSR4_8,
++		GP_4_7_FN,	GPSR4_7,
++		GP_4_6_FN,	GPSR4_6,
++		GP_4_5_FN,	GPSR4_5,
++		GP_4_4_FN,	GPSR4_4,
++		GP_4_3_FN,	GPSR4_3,
++		GP_4_2_FN,	GPSR4_2,
++		GP_4_1_FN,	GPSR4_1,
++		GP_4_0_FN,	GPSR4_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_19_FN,	GPSR5_19,
++		GP_5_18_FN,	GPSR5_18,
++		GP_5_17_FN,	GPSR5_17,
++		GP_5_16_FN,	GPSR5_16,
++		GP_5_15_FN,	GPSR5_15,
++		GP_5_14_FN,	GPSR5_14,
++		GP_5_13_FN,	GPSR5_13,
++		GP_5_12_FN,	GPSR5_12,
++		GP_5_11_FN,	GPSR5_11,
++		GP_5_10_FN,	GPSR5_10,
++		GP_5_9_FN,	GPSR5_9,
++		GP_5_8_FN,	GPSR5_8,
++		GP_5_7_FN,	GPSR5_7,
++		GP_5_6_FN,	GPSR5_6,
++		GP_5_5_FN,	GPSR5_5,
++		GP_5_4_FN,	GPSR5_4,
++		GP_5_3_FN,	GPSR5_3,
++		GP_5_2_FN,	GPSR5_2,
++		GP_5_1_FN,	GPSR5_1,
++		GP_5_0_FN,	GPSR5_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_6_17_FN,	GPSR6_17,
++		GP_6_16_FN,	GPSR6_16,
++		GP_6_15_FN,	GPSR6_15,
++		GP_6_14_FN,	GPSR6_14,
++		GP_6_13_FN,	GPSR6_13,
++		GP_6_12_FN,	GPSR6_12,
++		GP_6_11_FN,	GPSR6_11,
++		GP_6_10_FN,	GPSR6_10,
++		GP_6_9_FN,	GPSR6_9,
++		GP_6_8_FN,	GPSR6_8,
++		GP_6_7_FN,	GPSR6_7,
++		GP_6_6_FN,	GPSR6_6,
++		GP_6_5_FN,	GPSR6_5,
++		GP_6_4_FN,	GPSR6_4,
++		GP_6_3_FN,	GPSR6_3,
++		GP_6_2_FN,	GPSR6_2,
++		GP_6_1_FN,	GPSR6_1,
++		GP_6_0_FN,	GPSR6_0, }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
++		IP0_31_28
++		IP0_27_24
++		IP0_23_20
++		IP0_19_16
++		IP0_15_12
++		IP0_11_8
++		IP0_7_4
++		IP0_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
++		IP1_31_28
++		IP1_27_24
++		IP1_23_20
++		IP1_19_16
++		IP1_15_12
++		IP1_11_8
++		IP1_7_4
++		IP1_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
++		IP2_31_28
++		IP2_27_24
++		IP2_23_20
++		IP2_19_16
++		IP2_15_12
++		IP2_11_8
++		IP2_7_4
++		IP2_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
++		IP3_31_28
++		IP3_27_24
++		IP3_23_20
++		IP3_19_16
++		IP3_15_12
++		IP3_11_8
++		IP3_7_4
++		IP3_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
++		IP4_31_28
++		IP4_27_24
++		IP4_23_20
++		IP4_19_16
++		IP4_15_12
++		IP4_11_8
++		IP4_7_4
++		IP4_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
++		IP5_31_28
++		IP5_27_24
++		IP5_23_20
++		IP5_19_16
++		IP5_15_12
++		IP5_11_8
++		IP5_7_4
++		IP5_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
++		IP6_31_28
++		IP6_27_24
++		IP6_23_20
++		IP6_19_16
++		IP6_15_12
++		IP6_11_8
++		IP6_7_4
++		IP6_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
++		IP7_31_28
++		IP7_27_24
++		IP7_23_20
++		IP7_19_16
++		IP7_15_12
++		IP7_11_8
++		IP7_7_4
++		IP7_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
++		IP9_31_28
++		IP9_27_24
++		IP9_23_20
++		IP9_19_16
++		IP9_15_12
++		IP9_11_8
++		IP9_7_4
++		IP9_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
++		IP10_31_28
++		IP10_27_24
++		IP10_23_20
++		IP10_19_16
++		IP10_15_12
++		IP10_11_8
++		IP10_7_4
++		IP10_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
++		IP11_31_28
++		IP11_27_24
++		IP11_23_20
++		IP11_19_16
++		IP11_15_12
++		IP11_11_8
++		IP11_7_4
++		IP11_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
++		IP12_31_28
++		IP12_27_24
++		IP12_23_20
++		IP12_19_16
++		IP12_15_12
++		IP12_11_8
++		IP12_7_4
++		IP12_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
++		IP13_31_28
++		IP13_27_24
++		IP13_23_20
++		IP13_19_16
++		IP13_15_12
++		IP13_11_8
++		IP13_7_4
++		IP13_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
++		IP14_31_28
++		IP14_27_24
++		IP14_23_20
++		IP14_19_16
++		IP14_15_12
++		IP14_11_8
++		IP14_7_4
++		IP14_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
++		IP15_31_28
++		IP15_27_24
++		IP15_23_20
++		IP15_19_16
++		IP15_15_12
++		IP15_11_8
++		IP15_7_4
++		IP15_3_0 }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
++			     1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
++			     1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
++		/* RESERVED 31 */
++		0, 0,
++		MOD_SEL0_30_29
++		MOD_SEL0_28
++		MOD_SEL0_27_26
++		MOD_SEL0_25
++		MOD_SEL0_24
++		MOD_SEL0_23
++		MOD_SEL0_22
++		MOD_SEL0_21_20
++		MOD_SEL0_19_18_17
++		MOD_SEL0_16
++		MOD_SEL0_15
++		MOD_SEL0_14
++		MOD_SEL0_13_12
++		MOD_SEL0_11_10
++		MOD_SEL0_9
++		MOD_SEL0_8
++		MOD_SEL0_7
++		MOD_SEL0_6_5
++		MOD_SEL0_4
++		MOD_SEL0_3
++		MOD_SEL0_2
++		MOD_SEL0_1_0 }
++	},
++	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
++			     1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
++			     1, 2, 2, 2, 1, 1, 2, 1, 4) {
++		MOD_SEL1_31
++		MOD_SEL1_30
++		MOD_SEL1_29
++		MOD_SEL1_28
++		/* RESERVED 27 */
++		0, 0,
++		MOD_SEL1_26
++		MOD_SEL1_25
++		MOD_SEL1_24_23_22
++		MOD_SEL1_21_20_19
++		MOD_SEL1_18
++		MOD_SEL1_17
++		MOD_SEL1_16
++		MOD_SEL1_15
++		MOD_SEL1_14_13
++		MOD_SEL1_12_11
++		MOD_SEL1_10_9
++		MOD_SEL1_8
++		MOD_SEL1_7
++		MOD_SEL1_6_5
++		MOD_SEL1_4
++		/* RESERVED 3, 2, 1, 0  */
++		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
++	},
++	{ },
++};
++
++const struct sh_pfc_soc_info r8a77990_pinmux_info = {
++	.name = "r8a77990_pfc",
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 47b6e708984d..3d0b31636d6d 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -288,6 +288,7 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
++extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+-- 
+2.19.0
+
diff --git a/patches/1255-pinctrl-sh-pfc-r8a77990-Add-bias-pinconf-support.patch b/patches/1255-pinctrl-sh-pfc-r8a77990-Add-bias-pinconf-support.patch
new file mode 100644
index 00000000000000..e1e41fd6e017ca
--- /dev/null
+++ b/patches/1255-pinctrl-sh-pfc-r8a77990-Add-bias-pinconf-support.patch
@@ -0,0 +1,420 @@
+From 85730168043ab09b98ddf6ead3a768126d45cebe Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:24 +0900
+Subject: [PATCH 1255/1795] pinctrl: sh-pfc: r8a77990: Add bias pinconf support
+
+This patch implements control of pull-up and pull-down. On this SoC there
+is no simple mapping of GP pins to bias register bits, so we need a table.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 83f6941a42a5e773a5e850944a0f1200841eae65)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 340 +++++++++++++++++++++++++-
+ 1 file changed, 331 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+index 0af2fefd3d9a..62a13893d19c 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+@@ -16,15 +16,17 @@
+ #include "core.h"
+ #include "sh_pfc.h"
+ 
+-#define CPU_ALL_PORT(fn, sfx)	\
+-	PORT_GP_18(0, fn, sfx),	\
+-	PORT_GP_23(1, fn, sfx),	\
+-	PORT_GP_26(2, fn, sfx),	\
+-	PORT_GP_16(3, fn, sfx),	\
+-	PORT_GP_11(4, fn, sfx),	\
+-	PORT_GP_20(5, fn, sfx),	\
+-	PORT_GP_18(6, fn, sfx)
+-
++#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
++		   SH_PFC_PIN_CFG_PULL_DOWN)
++
++#define CPU_ALL_PORT(fn, sfx) \
++	PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
++	PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
+ /*
+  * F_() : just information
+  * FM() : macro for FN_xxx / xxx_MARK
+@@ -461,6 +463,17 @@ MOD_SEL0_3 \
+ MOD_SEL0_2 \
+ MOD_SEL0_1_0
+ 
++/*
++ * These pins are not able to be muxed but have other properties
++ * that can be set, such as pull-up/pull-down enable.
++ */
++#define PINMUX_STATIC \
++	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
++	FM(AVB_TD3) \
++	FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
++	FM(ASEBRK) \
++	FM(MLB_REF)
++
+ enum {
+ 	PINMUX_RESERVED = 0,
+ 
+@@ -485,6 +498,7 @@ enum {
+ 	PINMUX_GPSR
+ 	PINMUX_IPSR
+ 	PINMUX_MOD_SELS
++	PINMUX_STATIC
+ 	PINMUX_MARK_END,
+ #undef F_
+ #undef FM
+@@ -493,6 +507,13 @@ enum {
+ static const u16 pinmux_data[] = {
+ 	PINMUX_DATA_GP_ALL(),
+ 
++	PINMUX_SINGLE(CLKOUT),
++	PINMUX_SINGLE(AVB_PHY_INT),
++	PINMUX_SINGLE(AVB_RD3),
++	PINMUX_SINGLE(AVB_RXC),
++	PINMUX_SINGLE(AVB_RX_CTL),
++	PINMUX_SINGLE(QSPI0_SSL),
++
+ 	/* IPSR0 */
+ 	PINMUX_IPSR_GPSR(IP0_3_0,		QSPI0_SPCLK),
+ 	PINMUX_IPSR_MSEL(IP0_3_0,		HSCK4_A,	SEL_HSCIF4_0),
+@@ -1227,10 +1248,55 @@ static const u16 pinmux_data[] = {
+ 
+ 	PINMUX_IPSR_GPSR(IP15_31_28,		USB30_OVC),
+ 	PINMUX_IPSR_MSEL(IP15_31_28,		USB0_OVC_A,	SEL_USB_20_CH0_0),
++
++/*
++ * Static pins can not be muxed between different functions but
++ * still need mark entries in the pinmux list. Add each static
++ * pin to the list without an associated function. The sh-pfc
++ * core will do the right thing and skip trying to mux the pin
++ * while still applying configuration to it.
++ */
++#define FM(x)   PINMUX_DATA(x##_MARK, 0),
++	PINMUX_STATIC
++#undef FM
+ };
+ 
++/*
++ * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
++ * Physical layout rows: A - AE, cols: 1 - 25.
++ */
++#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
++#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
++#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
++#define PIN_NONE U16_MAX
++
+ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	PINMUX_GPIO_GP_ALL(),
++
++	/*
++	 * Pins not associated with a GPIO port.
++	 *
++	 * The pin positions are different between different R8A77990
++	 * packages, all that is needed for the pfc driver is a unique
++	 * number for each pin. To this end use the pin layout from
++	 * R8A77990 to calculate a unique number for each pin.
++	 */
++	SH_PFC_PIN_NAMED_CFG('F',  1, TRST_N,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('F',  3, TMS,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('F',  4, TCK,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('G',  2, TDI,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('G',  3, FSCLKST_N,	CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('H',  1, ASEBRK,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('N',  1, AVB_TXC,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('N',  2, AVB_TD0,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('N',  3, AVB_TD1,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('N',  5, AVB_TD2,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('N',  6, AVB_TD3,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('P',  3, AVB_TX_CTL,	CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('P',  4, AVB_MDIO,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('P',  5, AVB_MDC,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF,		CFG_FLAGS),
++	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
+@@ -1708,8 +1774,263 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ 	{ },
+ };
+ 
++static const struct pinmux_bias_reg pinmux_bias_regs[] = {
++	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
++		 [0] = RCAR_GP_PIN(2, 23),	/* RD# */
++		 [1] = RCAR_GP_PIN(2, 22),	/* BS# */
++		 [2] = RCAR_GP_PIN(2, 21),	/* AVB_PHY_INT */
++		 [3] = PIN_NUMBER('P', 5),	/* AVB_MDC */
++		 [4] = PIN_NUMBER('P', 4),	/* AVB_MDIO */
++		 [5] = RCAR_GP_PIN(2, 20),	/* AVB_TXCREFCLK */
++		 [6] = PIN_NUMBER('N', 6),	/* AVB_TD3 */
++		 [7] = PIN_NUMBER('N', 5),	/* AVB_TD2 */
++		 [8] = PIN_NUMBER('N', 3),	/* AVB_TD1 */
++		 [9] = PIN_NUMBER('N', 2),	/* AVB_TD0 */
++		[10] = PIN_NUMBER('N', 1),	/* AVB_TXC */
++		[11] = PIN_NUMBER('P', 3),	/* AVB_TX_CTL */
++		[12] = RCAR_GP_PIN(2, 19),	/* AVB_RD3 */
++		[13] = RCAR_GP_PIN(2, 18),	/* AVB_RD2 */
++		[14] = RCAR_GP_PIN(2, 17),	/* AVB_RD1 */
++		[15] = RCAR_GP_PIN(2, 16),	/* AVB_RD0 */
++		[16] = RCAR_GP_PIN(2, 15),	/* AVB_RXC */
++		[17] = RCAR_GP_PIN(2, 14),	/* AVB_RX_CTL */
++		[18] = RCAR_GP_PIN(2, 13),	/* RPC_RESET# */
++		[19] = RCAR_GP_PIN(2, 12),	/* RPC_INT# */
++		[20] = RCAR_GP_PIN(2, 11),	/* QSPI1_SSL */
++		[21] = RCAR_GP_PIN(2, 10),	/* QSPI1_IO3 */
++		[22] = RCAR_GP_PIN(2,  9),	/* QSPI1_IO2 */
++		[23] = RCAR_GP_PIN(2,  8),	/* QSPI1_MISO/IO1 */
++		[24] = RCAR_GP_PIN(2,  7),	/* QSPI1_MOSI/IO0 */
++		[25] = RCAR_GP_PIN(2,  6),	/* QSPI1_SPCLK */
++		[26] = RCAR_GP_PIN(2,  5),	/* QSPI0_SSL */
++		[27] = RCAR_GP_PIN(2,  4),	/* QSPI0_IO3 */
++		[28] = RCAR_GP_PIN(2,  3),	/* QSPI0_IO2 */
++		[29] = RCAR_GP_PIN(2,  2),	/* QSPI0_MISO/IO1 */
++		[30] = RCAR_GP_PIN(2,  1),	/* QSPI0_MOSI/IO0 */
++		[31] = RCAR_GP_PIN(2,  0),	/* QSPI0_SPCLK */
++	} },
++	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
++		 [0] = RCAR_GP_PIN(0,  4),	/* D4 */
++		 [1] = RCAR_GP_PIN(0,  3),	/* D3 */
++		 [2] = RCAR_GP_PIN(0,  2),	/* D2 */
++		 [3] = RCAR_GP_PIN(0,  1),	/* D1 */
++		 [4] = RCAR_GP_PIN(0,  0),	/* D0 */
++		 [5] = RCAR_GP_PIN(1, 22),	/* WE0# */
++		 [6] = RCAR_GP_PIN(1, 21),	/* CS0# */
++		 [7] = RCAR_GP_PIN(1, 20),	/* CLKOUT */
++		 [8] = RCAR_GP_PIN(1, 19),	/* A19 */
++		 [9] = RCAR_GP_PIN(1, 18),	/* A18 */
++		[10] = RCAR_GP_PIN(1, 17),	/* A17 */
++		[11] = RCAR_GP_PIN(1, 16),	/* A16 */
++		[12] = RCAR_GP_PIN(1, 15),	/* A15 */
++		[13] = RCAR_GP_PIN(1, 14),	/* A14 */
++		[14] = RCAR_GP_PIN(1, 13),	/* A13 */
++		[15] = RCAR_GP_PIN(1, 12),	/* A12 */
++		[16] = RCAR_GP_PIN(1, 11),	/* A11 */
++		[17] = RCAR_GP_PIN(1, 10),	/* A10 */
++		[18] = RCAR_GP_PIN(1,  9),	/* A9 */
++		[19] = RCAR_GP_PIN(1,  8),	/* A8 */
++		[20] = RCAR_GP_PIN(1,  7),	/* A7 */
++		[21] = RCAR_GP_PIN(1,  6),	/* A6 */
++		[22] = RCAR_GP_PIN(1,  5),	/* A5 */
++		[23] = RCAR_GP_PIN(1,  4),	/* A4 */
++		[24] = RCAR_GP_PIN(1,  3),	/* A3 */
++		[25] = RCAR_GP_PIN(1,  2),	/* A2 */
++		[26] = RCAR_GP_PIN(1,  1),	/* A1 */
++		[27] = RCAR_GP_PIN(1,  0),	/* A0 */
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = RCAR_GP_PIN(2, 25),	/* PUEN_EX_WAIT0 */
++		[31] = RCAR_GP_PIN(2, 24),	/* PUEN_RD/WR# */
++	} },
++	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
++		 [0] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
++		 [1] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
++		 [2] = PIN_NUMBER('H', 1),	/* ASEBRK */
++		 [3] = PIN_NONE,
++		 [4] = PIN_NUMBER('G', 2),	/* TDI */
++		 [5] = PIN_NUMBER('F', 3),	/* TMS */
++		 [6] = PIN_NUMBER('F', 4),	/* TCK */
++		 [7] = PIN_NUMBER('F', 1),	/* TRST# */
++		 [8] = PIN_NONE,
++		 [9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NUMBER('G', 3),	/* FSCLKST# */
++		[16] = RCAR_GP_PIN(0, 17),	/* SDA4 */
++		[17] = RCAR_GP_PIN(0, 16),	/* SCL4 */
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_A_NUMBER('D', 3),	/* PRESETOUT# */
++		[21] = RCAR_GP_PIN(0, 15),	/* D15 */
++		[22] = RCAR_GP_PIN(0, 14),	/* D14 */
++		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
++		[24] = RCAR_GP_PIN(0, 12),	/* D12 */
++		[25] = RCAR_GP_PIN(0, 11),	/* D11 */
++		[26] = RCAR_GP_PIN(0, 10),	/* D10 */
++		[27] = RCAR_GP_PIN(0,  9),	/* D9 */
++		[28] = RCAR_GP_PIN(0,  8),	/* D8 */
++		[29] = RCAR_GP_PIN(0,  7),	/* D7 */
++		[30] = RCAR_GP_PIN(0,  6),	/* D6 */
++		[31] = RCAR_GP_PIN(0,  5),	/* D5 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
++		 [0] = RCAR_GP_PIN(5,  0),	/* SCK0_A */
++		 [1] = RCAR_GP_PIN(5,  4),	/* RTS0#/TANS_A */
++		 [2] = RCAR_GP_PIN(5,  3),	/* CTS0#_A */
++		 [3] = RCAR_GP_PIN(5,  2),	/* TX0_A */
++		 [4] = RCAR_GP_PIN(5,  1),	/* RX0_A */
++		 [5] = PIN_NONE,
++		 [6] = PIN_NONE,
++		 [7] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
++		 [8] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
++		 [9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
++		[10] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
++		[11] = RCAR_GP_PIN(4, 10),	/* SD3_DS */
++		[12] = RCAR_GP_PIN(4,  9),	/* SD3_DAT7 */
++		[13] = RCAR_GP_PIN(4,  8),	/* SD3_DAT6 */
++		[14] = RCAR_GP_PIN(4,  7),	/* SD3_DAT5 */
++		[15] = RCAR_GP_PIN(4,  6),	/* SD3_DAT4 */
++		[16] = RCAR_GP_PIN(4,  5),	/* SD3_DAT3 */
++		[17] = RCAR_GP_PIN(4,  4),	/* SD3_DAT2 */
++		[18] = RCAR_GP_PIN(4,  3),	/* SD3_DAT1 */
++		[19] = RCAR_GP_PIN(4,  2),	/* SD3_DAT0 */
++		[20] = RCAR_GP_PIN(4,  1),	/* SD3_CMD */
++		[21] = RCAR_GP_PIN(4,  0),	/* SD3_CLK */
++		[22] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
++		[23] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
++		[24] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
++		[25] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
++		[26] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
++		[27] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
++		[28] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
++		[29] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
++		[30] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
++		[31] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
++		 [0] = RCAR_GP_PIN(6,  8),	/* AUDIO_CLKA */
++		 [1] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
++		 [2] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
++		 [3] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
++		 [4] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
++		 [5] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
++		 [6] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
++		 [7] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
++		 [8] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
++		 [9] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
++		[10] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
++		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2 */
++		[12] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1 */
++		[13] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
++		[14] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
++		[15] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
++		[16] = PIN_NUMBER('T', 21),	/* MLB_REF */
++		[17] = RCAR_GP_PIN(5, 19),	/* MLB_DAT */
++		[18] = RCAR_GP_PIN(5, 18),	/* MLB_SIG */
++		[19] = RCAR_GP_PIN(5, 17),	/* MLB_CLK */
++		[20] = RCAR_GP_PIN(5, 16),	/* SSI_SDATA9 */
++		[21] = RCAR_GP_PIN(5, 15),	/* MSIOF0_SS2 */
++		[22] = RCAR_GP_PIN(5, 14),	/* MSIOF0_SS1 */
++		[23] = RCAR_GP_PIN(5, 13),	/* MSIOF0_SYNC */
++		[24] = RCAR_GP_PIN(5, 12),	/* MSIOF0_TXD */
++		[25] = RCAR_GP_PIN(5, 11),	/* MSIOF0_RXD */
++		[26] = RCAR_GP_PIN(5, 10),	/* MSIOF0_SCK */
++		[27] = RCAR_GP_PIN(5,  9),	/* RX2_A */
++		[28] = RCAR_GP_PIN(5,  8),	/* TX2_A */
++		[29] = RCAR_GP_PIN(5,  7),	/* SCK2_A */
++		[30] = RCAR_GP_PIN(5,  6),	/* TX1 */
++		[31] = RCAR_GP_PIN(5,  5),	/* RX1 */
++	} },
++	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
++		 [0] = PIN_NONE,
++		 [1] = PIN_NONE,
++		 [2] = PIN_NONE,
++		 [3] = PIN_NONE,
++		 [4] = PIN_NONE,
++		 [5] = PIN_NONE,
++		 [6] = PIN_NONE,
++		 [7] = PIN_NONE,
++		 [8] = PIN_NONE,
++		 [9] = PIN_NONE,
++		[10] = PIN_NONE,
++		[11] = PIN_NONE,
++		[12] = PIN_NONE,
++		[13] = PIN_NONE,
++		[14] = PIN_NONE,
++		[15] = PIN_NONE,
++		[16] = PIN_NONE,
++		[17] = PIN_NONE,
++		[18] = PIN_NONE,
++		[19] = PIN_NONE,
++		[20] = PIN_NONE,
++		[21] = PIN_NONE,
++		[22] = PIN_NONE,
++		[23] = PIN_NONE,
++		[24] = PIN_NONE,
++		[25] = PIN_NONE,
++		[26] = PIN_NONE,
++		[27] = PIN_NONE,
++		[28] = PIN_NONE,
++		[29] = PIN_NONE,
++		[30] = RCAR_GP_PIN(6,  9),	/* PUEN_USB30_OVC */
++		[31] = RCAR_GP_PIN(6, 17),	/* PUEN_USB30_PWEN */
++	} },
++	{ /* sentinel */ },
++};
++
++static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
++					     unsigned int pin)
++{
++	const struct pinmux_bias_reg *reg;
++	unsigned int bit;
++
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
++		return PIN_CONFIG_BIAS_DISABLE;
++
++	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
++		return PIN_CONFIG_BIAS_DISABLE;
++	else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
++		return PIN_CONFIG_BIAS_PULL_UP;
++	else
++		return PIN_CONFIG_BIAS_PULL_DOWN;
++}
++
++static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
++				     unsigned int bias)
++{
++	const struct pinmux_bias_reg *reg;
++	u32 enable, updown;
++	unsigned int bit;
++
++	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
++	if (!reg)
++		return;
++
++	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
++	if (bias != PIN_CONFIG_BIAS_DISABLE)
++		enable |= BIT(bit);
++
++	updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
++	if (bias == PIN_CONFIG_BIAS_PULL_UP)
++		updown |= BIT(bit);
++
++	sh_pfc_write(pfc, reg->pud, updown);
++	sh_pfc_write(pfc, reg->puen, enable);
++}
++
++static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
++	.get_bias = r8a77990_pinmux_get_bias,
++	.set_bias = r8a77990_pinmux_set_bias,
++};
++
+ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
+ 	.name = "r8a77990_pfc",
++	.ops = &r8a77990_pinmux_ops,
+ 	.unlock_reg = 0xe6060000, /* PMMR */
+ 
+ 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+@@ -1722,6 +2043,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
+ 	.nr_functions = ARRAY_SIZE(pinmux_functions),
+ 
+ 	.cfg_regs = pinmux_config_regs,
++	.bias_regs = pinmux_bias_regs,
+ 
+ 	.pinmux_data = pinmux_data,
+ 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+-- 
+2.19.0
+
diff --git a/patches/1256-pinctrl-sh-pfc-r8a77990-Add-SCIF-pins-groups-and-fun.patch b/patches/1256-pinctrl-sh-pfc-r8a77990-Add-SCIF-pins-groups-and-fun.patch
new file mode 100644
index 00000000000000..50ff08325d8ab9
--- /dev/null
+++ b/patches/1256-pinctrl-sh-pfc-r8a77990-Add-SCIF-pins-groups-and-fun.patch
@@ -0,0 +1,402 @@
+From c9496cbaa94db62471018bbc2f493cff6c411e61 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:25 +0900
+Subject: [PATCH 1256/1795] pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups
+ and functions
+
+This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990
+SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6d3789e7051c5ca5bf0596f59c33cc4ce6400149)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 365 ++++++++++++++++++++++++++
+ 1 file changed, 365 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+index 62a13893d19c..5709f74ebfd8 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+@@ -1299,10 +1299,375 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+ };
+ 
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
++};
++
++static const unsigned int scif0_data_a_mux[] = {
++	RX0_A_MARK, TX0_A_MARK,
++};
++
++static const unsigned int scif0_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 0),
++};
++
++static const unsigned int scif0_clk_a_mux[] = {
++	SCK0_A_MARK,
++};
++
++static const unsigned int scif0_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
++};
++
++static const unsigned int scif0_ctrl_a_mux[] = {
++	RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
++};
++
++static const unsigned int scif0_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
++};
++
++static const unsigned int scif0_data_b_mux[] = {
++	RX0_B_MARK, TX0_B_MARK,
++};
++
++static const unsigned int scif0_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 18),
++};
++
++static const unsigned int scif0_clk_b_mux[] = {
++	SCK0_B_MARK,
++};
++
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
++};
++
++static const unsigned int scif1_data_mux[] = {
++	RX1_MARK, TX1_MARK,
++};
++
++static const unsigned int scif1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 16),
++};
++
++static const unsigned int scif1_clk_mux[] = {
++	SCK1_MARK,
++};
++
++static const unsigned int scif1_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
++};
++
++static const unsigned int scif1_ctrl_mux[] = {
++	RTS1_N_TANS_MARK, CTS1_N_MARK,
++};
++
++/* - SCIF2 ------------------------------------------------------------------ */
++static const unsigned int scif2_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
++};
++
++static const unsigned int scif2_data_a_mux[] = {
++	RX2_A_MARK, TX2_A_MARK,
++};
++
++static const unsigned int scif2_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(5, 7),
++};
++
++static const unsigned int scif2_clk_a_mux[] = {
++	SCK2_A_MARK,
++};
++
++static const unsigned int scif2_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
++};
++
++static const unsigned int scif2_data_b_mux[] = {
++	RX2_B_MARK, TX2_B_MARK,
++};
++
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
++};
++
++static const unsigned int scif3_data_a_mux[] = {
++	RX3_A_MARK, TX3_A_MARK,
++};
++
++static const unsigned int scif3_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 1),
++};
++
++static const unsigned int scif3_clk_a_mux[] = {
++	SCK3_A_MARK,
++};
++
++static const unsigned int scif3_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
++};
++
++static const unsigned int scif3_ctrl_a_mux[] = {
++	RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
++};
++
++static const unsigned int scif3_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
++};
++
++static const unsigned int scif3_data_b_mux[] = {
++	RX3_B_MARK, TX3_B_MARK,
++};
++
++static const unsigned int scif3_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
++};
++
++static const unsigned int scif3_data_c_mux[] = {
++	RX3_C_MARK, TX3_C_MARK,
++};
++
++static const unsigned int scif3_clk_c_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 24),
++};
++
++static const unsigned int scif3_clk_c_mux[] = {
++	SCK3_C_MARK,
++};
++
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
++};
++
++static const unsigned int scif4_data_a_mux[] = {
++	RX4_A_MARK, TX4_A_MARK,
++};
++
++static const unsigned int scif4_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 5),
++};
++
++static const unsigned int scif4_clk_a_mux[] = {
++	SCK4_A_MARK,
++};
++
++static const unsigned int scif4_ctrl_a_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
++};
++
++static const unsigned int scif4_ctrl_a_mux[] = {
++	RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
++};
++
++static const unsigned int scif4_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
++};
++
++static const unsigned int scif4_data_b_mux[] = {
++	RX4_B_MARK, TX4_B_MARK,
++};
++
++static const unsigned int scif4_clk_b_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 8),
++};
++
++static const unsigned int scif4_clk_b_mux[] = {
++	SCK4_B_MARK,
++};
++
++static const unsigned int scif4_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++
++static const unsigned int scif4_data_c_mux[] = {
++	RX4_C_MARK, TX4_C_MARK,
++};
++
++static const unsigned int scif4_ctrl_c_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
++};
++
++static const unsigned int scif4_ctrl_c_mux[] = {
++	RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
++};
++
++/* - SCIF5 ------------------------------------------------------------------ */
++static const unsigned int scif5_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
++};
++
++static const unsigned int scif5_data_a_mux[] = {
++	RX5_A_MARK, TX5_A_MARK,
++};
++
++static const unsigned int scif5_clk_a_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(1, 13),
++};
++
++static const unsigned int scif5_clk_a_mux[] = {
++	SCK5_A_MARK,
++};
++
++static const unsigned int scif5_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
++};
++
++static const unsigned int scif5_data_b_mux[] = {
++	RX5_B_MARK, TX5_B_MARK,
++};
++
++static const unsigned int scif5_data_c_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++};
++
++static const unsigned int scif5_data_c_mux[] = {
++	RX5_C_MARK, TX5_C_MARK,
++};
++
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(5, 3),
++};
++
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(5, 7),
++};
++
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(scif0_data_a),
++	SH_PFC_PIN_GROUP(scif0_clk_a),
++	SH_PFC_PIN_GROUP(scif0_ctrl_a),
++	SH_PFC_PIN_GROUP(scif0_data_b),
++	SH_PFC_PIN_GROUP(scif0_clk_b),
++	SH_PFC_PIN_GROUP(scif1_data),
++	SH_PFC_PIN_GROUP(scif1_clk),
++	SH_PFC_PIN_GROUP(scif1_ctrl),
++	SH_PFC_PIN_GROUP(scif2_data_a),
++	SH_PFC_PIN_GROUP(scif2_clk_a),
++	SH_PFC_PIN_GROUP(scif2_data_b),
++	SH_PFC_PIN_GROUP(scif3_data_a),
++	SH_PFC_PIN_GROUP(scif3_clk_a),
++	SH_PFC_PIN_GROUP(scif3_ctrl_a),
++	SH_PFC_PIN_GROUP(scif3_data_b),
++	SH_PFC_PIN_GROUP(scif3_data_c),
++	SH_PFC_PIN_GROUP(scif3_clk_c),
++	SH_PFC_PIN_GROUP(scif4_data_a),
++	SH_PFC_PIN_GROUP(scif4_clk_a),
++	SH_PFC_PIN_GROUP(scif4_ctrl_a),
++	SH_PFC_PIN_GROUP(scif4_data_b),
++	SH_PFC_PIN_GROUP(scif4_clk_b),
++	SH_PFC_PIN_GROUP(scif4_data_c),
++	SH_PFC_PIN_GROUP(scif4_ctrl_c),
++	SH_PFC_PIN_GROUP(scif5_data_a),
++	SH_PFC_PIN_GROUP(scif5_clk_a),
++	SH_PFC_PIN_GROUP(scif5_data_b),
++	SH_PFC_PIN_GROUP(scif5_data_c),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data_a",
++	"scif0_clk_a",
++	"scif0_ctrl_a",
++	"scif0_data_b",
++	"scif0_clk_b",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data",
++	"scif1_clk",
++	"scif1_ctrl",
++};
++
++static const char * const scif2_groups[] = {
++	"scif2_data_a",
++	"scif2_clk_a",
++	"scif2_data_b",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data_a",
++	"scif3_clk_a",
++	"scif3_ctrl_a",
++	"scif3_data_b",
++	"scif3_data_c",
++	"scif3_clk_c",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data_a",
++	"scif4_clk_a",
++	"scif4_ctrl_a",
++	"scif4_data_b",
++	"scif4_clk_b",
++	"scif4_data_c",
++	"scif4_ctrl_c",
++};
++
++static const char * const scif5_groups[] = {
++	"scif5_data_a",
++	"scif5_clk_a",
++	"scif5_data_b",
++	"scif5_data_c",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif2),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(scif5),
++	SH_PFC_FUNCTION(scif_clk),
+ };
+ 
+ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+-- 
+2.19.0
+
diff --git a/patches/1257-pinctrl-sh-pfc-r8a77990-Add-I2C-1-2-4-5-6-7-pins-gro.patch b/patches/1257-pinctrl-sh-pfc-r8a77990-Add-I2C-1-2-4-5-6-7-pins-gro.patch
new file mode 100644
index 00000000000000..ac06656bf7cbf1
--- /dev/null
+++ b/patches/1257-pinctrl-sh-pfc-r8a77990-Add-I2C-1-2-4-5-6-7-pins-gro.patch
@@ -0,0 +1,246 @@
+From 2f1e1ccfc5e7dcc19e7cd8003defcf34b8619823 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:26 +0900
+Subject: [PATCH 1257/1795] pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7}
+ pins, groups and functions
+
+This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to
+the R8A77990 SoC.
+
+NOTE: I2C0 and I2C3 are not pin multiplexed.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 33f8dadc27ae0ee37586319b3d3288ce1bcbb650)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 190 ++++++++++++++++++++++++++
+ 1 file changed, 190 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+index 5709f74ebfd8..9cd4d0799652 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+@@ -1299,6 +1299,142 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+ };
+ 
++/* - I2C -------------------------------------------------------------------- */
++static const unsigned int i2c1_a_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
++};
++
++static const unsigned int i2c1_a_mux[] = {
++	SCL1_A_MARK, SDA1_A_MARK,
++};
++
++static const unsigned int i2c1_b_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
++};
++
++static const unsigned int i2c1_b_mux[] = {
++	SCL1_B_MARK, SDA1_B_MARK,
++};
++
++static const unsigned int i2c1_c_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
++};
++
++static const unsigned int i2c1_c_mux[] = {
++	SCL1_C_MARK, SDA1_C_MARK,
++};
++
++static const unsigned int i2c1_d_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
++};
++
++static const unsigned int i2c1_d_mux[] = {
++	SCL1_D_MARK, SDA1_D_MARK,
++};
++
++static const unsigned int i2c2_a_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
++};
++
++static const unsigned int i2c2_a_mux[] = {
++	SCL2_A_MARK, SDA2_A_MARK,
++};
++
++static const unsigned int i2c2_b_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++};
++
++static const unsigned int i2c2_b_mux[] = {
++	SCL2_B_MARK, SDA2_B_MARK,
++};
++
++static const unsigned int i2c2_c_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
++};
++
++static const unsigned int i2c2_c_mux[] = {
++	SCL2_C_MARK, SDA2_C_MARK,
++};
++
++static const unsigned int i2c2_d_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
++};
++
++static const unsigned int i2c2_d_mux[] = {
++	SCL2_D_MARK, SDA2_D_MARK,
++};
++
++static const unsigned int i2c2_e_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
++};
++
++static const unsigned int i2c2_e_mux[] = {
++	SCL2_E_MARK, SDA2_E_MARK,
++};
++
++static const unsigned int i2c4_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
++};
++
++static const unsigned int i2c4_mux[] = {
++	SCL4_MARK, SDA4_MARK,
++};
++
++static const unsigned int i2c5_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
++};
++
++static const unsigned int i2c5_mux[] = {
++	SCL5_MARK, SDA5_MARK,
++};
++
++static const unsigned int i2c6_a_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
++};
++
++static const unsigned int i2c6_a_mux[] = {
++	SCL6_A_MARK, SDA6_A_MARK,
++};
++
++static const unsigned int i2c6_b_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
++};
++
++static const unsigned int i2c6_b_mux[] = {
++	SCL6_B_MARK, SDA6_B_MARK,
++};
++
++static const unsigned int i2c7_a_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
++};
++
++static const unsigned int i2c7_a_mux[] = {
++	SCL7_A_MARK, SDA7_A_MARK,
++};
++
++static const unsigned int i2c7_b_pins[] = {
++	/* SCL, SDA */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
++};
++
++static const unsigned int i2c7_b_mux[] = {
++	SCL7_B_MARK, SDA7_B_MARK,
++};
++
+ /* - SCIF0 ------------------------------------------------------------------ */
+ static const unsigned int scif0_data_a_pins[] = {
+ 	/* RX, TX */
+@@ -1577,6 +1713,21 @@ static const unsigned int scif_clk_b_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(i2c1_a),
++	SH_PFC_PIN_GROUP(i2c1_b),
++	SH_PFC_PIN_GROUP(i2c1_c),
++	SH_PFC_PIN_GROUP(i2c1_d),
++	SH_PFC_PIN_GROUP(i2c2_a),
++	SH_PFC_PIN_GROUP(i2c2_b),
++	SH_PFC_PIN_GROUP(i2c2_c),
++	SH_PFC_PIN_GROUP(i2c2_d),
++	SH_PFC_PIN_GROUP(i2c2_e),
++	SH_PFC_PIN_GROUP(i2c4),
++	SH_PFC_PIN_GROUP(i2c5),
++	SH_PFC_PIN_GROUP(i2c6_a),
++	SH_PFC_PIN_GROUP(i2c6_b),
++	SH_PFC_PIN_GROUP(i2c7_a),
++	SH_PFC_PIN_GROUP(i2c7_b),
+ 	SH_PFC_PIN_GROUP(scif0_data_a),
+ 	SH_PFC_PIN_GROUP(scif0_clk_a),
+ 	SH_PFC_PIN_GROUP(scif0_ctrl_a),
+@@ -1609,6 +1760,39 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
+ };
+ 
++static const char * const i2c1_groups[] = {
++	"i2c1_a",
++	"i2c1_b",
++	"i2c1_c",
++	"i2c1_d",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2_a",
++	"i2c2_b",
++	"i2c2_c",
++	"i2c2_d",
++	"i2c2_e",
++};
++
++static const char * const i2c4_groups[] = {
++	"i2c4",
++};
++
++static const char * const i2c5_groups[] = {
++	"i2c5",
++};
++
++static const char * const i2c6_groups[] = {
++	"i2c6_a",
++	"i2c6_b",
++};
++
++static const char * const i2c7_groups[] = {
++	"i2c7_a",
++	"i2c7_b",
++};
++
+ static const char * const scif0_groups[] = {
+ 	"scif0_data_a",
+ 	"scif0_clk_a",
+@@ -1661,6 +1845,12 @@ static const char * const scif_clk_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c4),
++	SH_PFC_FUNCTION(i2c5),
++	SH_PFC_FUNCTION(i2c6),
++	SH_PFC_FUNCTION(i2c7),
+ 	SH_PFC_FUNCTION(scif0),
+ 	SH_PFC_FUNCTION(scif1),
+ 	SH_PFC_FUNCTION(scif2),
+-- 
+2.19.0
+
diff --git a/patches/1258-pinctrl-sh-pfc-r8a77990-Add-EthernetAVB-pins-groups-.patch b/patches/1258-pinctrl-sh-pfc-r8a77990-Add-EthernetAVB-pins-groups-.patch
new file mode 100644
index 00000000000000..3c4edfb97b0c59
--- /dev/null
+++ b/patches/1258-pinctrl-sh-pfc-r8a77990-Add-EthernetAVB-pins-groups-.patch
@@ -0,0 +1,144 @@
+From a87bfd7c879f1c0d7d2cb93deefdf98dcbf56488 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 11 May 2018 12:22:27 +0900
+Subject: [PATCH 1258/1795] pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins,
+ groups and functions
+
+This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP
+pins for the R8A77990 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 7cf9733f699336087786a98e71d95649761471f0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 90 +++++++++++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+index 9cd4d0799652..a68fd658aada 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+@@ -1299,6 +1299,78 @@ static const struct sh_pfc_pin pinmux_pins[] = {
+ 	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+ };
+ 
++/* - EtherAVB --------------------------------------------------------------- */
++static const unsigned int avb_link_pins[] = {
++	/* AVB_LINK */
++	RCAR_GP_PIN(2, 23),
++};
++
++static const unsigned int avb_link_mux[] = {
++	AVB_LINK_MARK,
++};
++
++static const unsigned int avb_magic_pins[] = {
++	/* AVB_MAGIC */
++	RCAR_GP_PIN(2, 22),
++};
++
++static const unsigned int avb_magic_mux[] = {
++	AVB_MAGIC_MARK,
++};
++
++static const unsigned int avb_phy_int_pins[] = {
++	/* AVB_PHY_INT */
++	RCAR_GP_PIN(2, 21),
++};
++
++static const unsigned int avb_phy_int_mux[] = {
++	AVB_PHY_INT_MARK,
++};
++
++static const unsigned int avb_mii_pins[] = {
++	/*
++	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
++	 * AVB_RD1, AVB_RD2, AVB_RD3,
++	 * AVB_TXCREFCLK
++	 */
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
++	RCAR_GP_PIN(2, 20),
++};
++
++static const unsigned int avb_mii_mux[] = {
++	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
++	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
++	AVB_TXCREFCLK_MARK,
++};
++
++static const unsigned int avb_avtp_pps_pins[] = {
++	/* AVB_AVTP_PPS */
++	RCAR_GP_PIN(1, 2),
++};
++
++static const unsigned int avb_avtp_pps_mux[] = {
++	AVB_AVTP_PPS_MARK,
++};
++
++static const unsigned int avb_avtp_match_a_pins[] = {
++	/* AVB_AVTP_MATCH_A */
++	RCAR_GP_PIN(2, 24),
++};
++
++static const unsigned int avb_avtp_match_a_mux[] = {
++	AVB_AVTP_MATCH_A_MARK,
++};
++
++static const unsigned int avb_avtp_capture_a_pins[] = {
++	/* AVB_AVTP_CAPTURE_A */
++	RCAR_GP_PIN(2, 25),
++};
++
++static const unsigned int avb_avtp_capture_a_mux[] = {
++	AVB_AVTP_CAPTURE_A_MARK,
++};
++
+ /* - I2C -------------------------------------------------------------------- */
+ static const unsigned int i2c1_a_pins[] = {
+ 	/* SCL, SDA */
+@@ -1713,6 +1785,13 @@ static const unsigned int scif_clk_b_mux[] = {
+ };
+ 
+ static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb_link),
++	SH_PFC_PIN_GROUP(avb_magic),
++	SH_PFC_PIN_GROUP(avb_phy_int),
++	SH_PFC_PIN_GROUP(avb_mii),
++	SH_PFC_PIN_GROUP(avb_avtp_pps),
++	SH_PFC_PIN_GROUP(avb_avtp_match_a),
++	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ 	SH_PFC_PIN_GROUP(i2c1_a),
+ 	SH_PFC_PIN_GROUP(i2c1_b),
+ 	SH_PFC_PIN_GROUP(i2c1_c),
+@@ -1760,6 +1839,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(scif_clk_b),
+ };
+ 
++static const char * const avb_groups[] = {
++	"avb_link",
++	"avb_magic",
++	"avb_phy_int",
++	"avb_mii",
++	"avb_avtp_pps",
++	"avb_avtp_match_a",
++	"avb_avtp_capture_a",
++};
++
+ static const char * const i2c1_groups[] = {
+ 	"i2c1_a",
+ 	"i2c1_b",
+@@ -1845,6 +1934,7 @@ static const char * const scif_clk_groups[] = {
+ };
+ 
+ static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(i2c1),
+ 	SH_PFC_FUNCTION(i2c2),
+ 	SH_PFC_FUNCTION(i2c4),
+-- 
+2.19.0
+
diff --git a/patches/1259-pinctrl-sh-pfc-r8a77965-Add-I2C-pin-support.patch b/patches/1259-pinctrl-sh-pfc-r8a77965-Add-I2C-pin-support.patch
new file mode 100644
index 00000000000000..bf600c3714f5a4
--- /dev/null
+++ b/patches/1259-pinctrl-sh-pfc-r8a77965-Add-I2C-pin-support.patch
@@ -0,0 +1,130 @@
+From fa3bc3f91b4ebaf22aa790d9b5f4c0ca9c5e1ea1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sun, 13 May 2018 13:35:05 +0200
+Subject: [PATCH 1259/1795] pinctrl: sh-pfc: r8a77965: Add I2C pin support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 82540ebcc71037775aeab286448a118a9b635801)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 77 +++++++++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 4d944e3c73e9..8090c24712f8 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1758,6 +1758,57 @@ static const unsigned int du_disp_mux[] = {
+ 	DU_DISP_MARK,
+ };
+ 
++/* - I2C -------------------------------------------------------------------- */
++static const unsigned int i2c1_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
++};
++static const unsigned int i2c1_a_mux[] = {
++	SDA1_A_MARK, SCL1_A_MARK,
++};
++static const unsigned int i2c1_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
++};
++static const unsigned int i2c1_b_mux[] = {
++	SDA1_B_MARK, SCL1_B_MARK,
++};
++static const unsigned int i2c2_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
++};
++static const unsigned int i2c2_a_mux[] = {
++	SDA2_A_MARK, SCL2_A_MARK,
++};
++static const unsigned int i2c2_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
++};
++static const unsigned int i2c2_b_mux[] = {
++	SDA2_B_MARK, SCL2_B_MARK,
++};
++static const unsigned int i2c6_a_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
++};
++static const unsigned int i2c6_a_mux[] = {
++	SDA6_A_MARK, SCL6_A_MARK,
++};
++static const unsigned int i2c6_b_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
++};
++static const unsigned int i2c6_b_mux[] = {
++	SDA6_B_MARK, SCL6_B_MARK,
++};
++static const unsigned int i2c6_c_pins[] = {
++	/* SDA, SCL */
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int i2c6_c_mux[] = {
++	SDA6_C_MARK, SCL6_C_MARK,
++};
++
+ /* - INTC-EX ---------------------------------------------------------------- */
+ static const unsigned int intc_ex_irq0_pins[] = {
+ 	/* IRQ0 */
+@@ -3118,6 +3169,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
+ 	SH_PFC_PIN_GROUP(du_oddf),
+ 	SH_PFC_PIN_GROUP(du_cde),
+ 	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(i2c1_a),
++	SH_PFC_PIN_GROUP(i2c1_b),
++	SH_PFC_PIN_GROUP(i2c2_a),
++	SH_PFC_PIN_GROUP(i2c2_b),
++	SH_PFC_PIN_GROUP(i2c6_a),
++	SH_PFC_PIN_GROUP(i2c6_b),
++	SH_PFC_PIN_GROUP(i2c6_c),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq0),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq1),
+ 	SH_PFC_PIN_GROUP(intc_ex_irq2),
+@@ -3321,6 +3379,22 @@ static const char * const du_groups[] = {
+ 	"du_disp",
+ };
+ 
++static const char * const i2c1_groups[] = {
++	"i2c1_a",
++	"i2c1_b",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2_a",
++	"i2c2_b",
++};
++
++static const char * const i2c6_groups[] = {
++	"i2c6_a",
++	"i2c6_b",
++	"i2c6_c",
++};
++
+ static const char * const intc_ex_groups[] = {
+ 	"intc_ex_irq0",
+ 	"intc_ex_irq1",
+@@ -3577,6 +3651,9 @@ static const char * const usb30_groups[] = {
+ static const struct sh_pfc_function pinmux_functions[] = {
+ 	SH_PFC_FUNCTION(avb),
+ 	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c6),
+ 	SH_PFC_FUNCTION(intc_ex),
+ 	SH_PFC_FUNCTION(msiof0),
+ 	SH_PFC_FUNCTION(msiof1),
+-- 
+2.19.0
+
diff --git a/patches/1260-pinctrl-sh-pfc-rcar-gen3-Fix-grammar-in-static-pin-c.patch b/patches/1260-pinctrl-sh-pfc-rcar-gen3-Fix-grammar-in-static-pin-c.patch
new file mode 100644
index 00000000000000..10b07be9ae088d
--- /dev/null
+++ b/patches/1260-pinctrl-sh-pfc-rcar-gen3-Fix-grammar-in-static-pin-c.patch
@@ -0,0 +1,102 @@
+From 1c36d7e20b122cbfade39880accb7196cea39291 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 14 May 2018 21:30:02 +0200
+Subject: [PATCH 1260/1795] pinctrl: sh-pfc: rcar-gen3: Fix grammar in static
+ pin comments
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The comment block explaining the rationale for static pins contains
+grammar errors.  It appeared first in the pin control driver for R-Car
+H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later.
+
+Fix the grammar in all copies at once.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit db701f4bea09a0f9925e262753444e848c33af89)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 6 +++---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c     | 6 +++---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c     | 6 +++---
+ drivers/pinctrl/sh-pfc/pfc-r8a77965.c    | 6 +++---
+ 4 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+index 82a1c411c952..a6c5d50557e6 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+@@ -1432,10 +1432,10 @@ static const u16 pinmux_data[] = {
+ 
+ /*
+  * Static pins can not be muxed between different functions but
+- * still needs a mark entry in the pinmux list. Add each static
++ * still need mark entries in the pinmux list. Add each static
+  * pin to the list without an associated function. The sh-pfc
+- * core will do the right thing and skip trying to mux then pin
+- * while still applying configuration to it
++ * core will do the right thing and skip trying to mux the pin
++ * while still applying configuration to it.
+  */
+ #define FM(x)	PINMUX_DATA(x##_MARK, 0),
+ 	PINMUX_STATIC
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+index 34626898f757..4f55b1562ad4 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1493,10 +1493,10 @@ static const u16 pinmux_data[] = {
+ 
+ /*
+  * Static pins can not be muxed between different functions but
+- * still needs a mark entry in the pinmux list. Add each static
++ * still need mark entries in the pinmux list. Add each static
+  * pin to the list without an associated function. The sh-pfc
+- * core will do the right thing and skip trying to mux then pin
+- * while still applying configuration to it
++ * core will do the right thing and skip trying to mux the pin
++ * while still applying configuration to it.
+  */
+ #define FM(x)	PINMUX_DATA(x##_MARK, 0),
+ 	PINMUX_STATIC
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index 764afa13a8c6..3ea133cfb241 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -1499,10 +1499,10 @@ static const u16 pinmux_data[] = {
+ 
+ /*
+  * Static pins can not be muxed between different functions but
+- * still needs a mark entry in the pinmux list. Add each static
++ * still need mark entries in the pinmux list. Add each static
+  * pin to the list without an associated function. The sh-pfc
+- * core will do the right thing and skip trying to mux then pin
+- * while still applying configuration to it
++ * core will do the right thing and skip trying to mux the pin
++ * while still applying configuration to it.
+  */
+ #define FM(x)   PINMUX_DATA(x##_MARK, 0),
+ 	PINMUX_STATIC
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+index 8090c24712f8..d2bbee656381 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+@@ -1501,10 +1501,10 @@ static const u16 pinmux_data[] = {
+ 
+ /*
+  * Static pins can not be muxed between different functions but
+- * still needs a mark entry in the pinmux list. Add each static
++ * still need mark entries in the pinmux list. Add each static
+  * pin to the list without an associated function. The sh-pfc
+- * core will do the right thing and skip trying to mux then pin
+- * while still applying configuration to it
++ * core will do the right thing and skip trying to mux the pin
++ * while still applying configuration to it.
+  */
+ #define FM(x)   PINMUX_DATA(x##_MARK, 0),
+ 	PINMUX_STATIC
+-- 
+2.19.0
+
diff --git a/patches/1261-rtc-simplify-getting-.drvdata.patch b/patches/1261-rtc-simplify-getting-.drvdata.patch
new file mode 100644
index 00000000000000..f8067f72acd67b
--- /dev/null
+++ b/patches/1261-rtc-simplify-getting-.drvdata.patch
@@ -0,0 +1,722 @@
+From 9f3c3342b24d504e411310687d34bbd75c797bae Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 19 Apr 2018 16:06:14 +0200
+Subject: [PATCH 1261/1795] rtc: simplify getting .drvdata
+
+We should get drvdata from struct device directly. Going via
+platform_device is an unneeded step back and forth.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Acked-by: Michal Simek <michal.simek@xilinx.com> (for zynqmp)
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+(cherry picked from commit 85368bb9de6366654f442e26fdd571981f205291)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/rtc/rtc-bq4802.c   |  6 ++----
+ drivers/rtc/rtc-ds1216.c   |  6 ++----
+ drivers/rtc/rtc-ds1511.c   |  9 +++------
+ drivers/rtc/rtc-ds1553.c   | 15 +++++---------
+ drivers/rtc/rtc-ds1685.c   | 21 +++++++------------
+ drivers/rtc/rtc-ds1742.c   |  6 ++----
+ drivers/rtc/rtc-lpc32xx.c  | 16 ++++++---------
+ drivers/rtc/rtc-m48t59.c   | 41 +++++++++++++++-----------------------
+ drivers/rtc/rtc-mv.c       |  3 +--
+ drivers/rtc/rtc-mxc.c      | 21 +++++++------------
+ drivers/rtc/rtc-pcap.c     | 15 +++++---------
+ drivers/rtc/rtc-sh.c       | 15 +++++---------
+ drivers/rtc/rtc-stk17ta8.c | 15 +++++---------
+ drivers/rtc/rtc-test.c     |  3 +--
+ drivers/rtc/rtc-zynqmp.c   | 10 ++++------
+ 15 files changed, 71 insertions(+), 131 deletions(-)
+
+diff --git a/drivers/rtc/rtc-bq4802.c b/drivers/rtc/rtc-bq4802.c
+index bd170cb3361c..d768f6747961 100644
+--- a/drivers/rtc/rtc-bq4802.c
++++ b/drivers/rtc/rtc-bq4802.c
+@@ -48,8 +48,7 @@ static void bq4802_write_mem(struct bq4802 *p, int off, u8 val)
+ 
+ static int bq4802_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct bq4802 *p = platform_get_drvdata(pdev);
++	struct bq4802 *p = dev_get_drvdata(dev);
+ 	unsigned long flags;
+ 	unsigned int century;
+ 	u8 val;
+@@ -91,8 +90,7 @@ static int bq4802_read_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int bq4802_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct bq4802 *p = platform_get_drvdata(pdev);
++	struct bq4802 *p = dev_get_drvdata(dev);
+ 	u8 sec, min, hrs, day, mon, yrs, century, val;
+ 	unsigned long flags;
+ 	unsigned int year;
+diff --git a/drivers/rtc/rtc-ds1216.c b/drivers/rtc/rtc-ds1216.c
+index 9c82b1da2d45..0f601143e0a9 100644
+--- a/drivers/rtc/rtc-ds1216.c
++++ b/drivers/rtc/rtc-ds1216.c
+@@ -76,8 +76,7 @@ static void ds1216_switch_ds_to_clock(u8 __iomem *ioaddr)
+ 
+ static int ds1216_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1216_priv *priv = platform_get_drvdata(pdev);
++	struct ds1216_priv *priv = dev_get_drvdata(dev);
+ 	struct ds1216_regs regs;
+ 
+ 	ds1216_switch_ds_to_clock(priv->ioaddr);
+@@ -104,8 +103,7 @@ static int ds1216_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int ds1216_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1216_priv *priv = platform_get_drvdata(pdev);
++	struct ds1216_priv *priv = dev_get_drvdata(dev);
+ 	struct ds1216_regs regs;
+ 
+ 	ds1216_switch_ds_to_clock(priv->ioaddr);
+diff --git a/drivers/rtc/rtc-ds1511.c b/drivers/rtc/rtc-ds1511.c
+index 1b2dcb58c0ab..be0824308e03 100644
+--- a/drivers/rtc/rtc-ds1511.c
++++ b/drivers/rtc/rtc-ds1511.c
+@@ -318,8 +318,7 @@ ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
+ static int
+ ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -338,8 +337,7 @@ ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ static int
+ ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -377,8 +375,7 @@ ds1511_interrupt(int irq, void *dev_id)
+ 
+ static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+diff --git a/drivers/rtc/rtc-ds1553.c b/drivers/rtc/rtc-ds1553.c
+index 9961ec646fd2..2cff2576a337 100644
+--- a/drivers/rtc/rtc-ds1553.c
++++ b/drivers/rtc/rtc-ds1553.c
+@@ -73,8 +73,7 @@ struct rtc_plat_data {
+ 
+ static int ds1553_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	u8 century;
+ 
+@@ -98,8 +97,7 @@ static int ds1553_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int ds1553_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	unsigned int year, month, day, hour, minute, second, week;
+ 	unsigned int century;
+@@ -159,8 +157,7 @@ static void ds1553_rtc_update_alarm(struct rtc_plat_data *pdata)
+ 
+ static int ds1553_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -176,8 +173,7 @@ static int ds1553_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ 
+ static int ds1553_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -212,8 +208,7 @@ static irqreturn_t ds1553_rtc_interrupt(int irq, void *dev_id)
+ 
+ static int ds1553_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c
+index ed43b4311660..7a97cdef7eef 100644
+--- a/drivers/rtc/rtc-ds1685.c
++++ b/drivers/rtc/rtc-ds1685.c
+@@ -267,8 +267,7 @@ ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
+ static int
+ ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ctrlb, century;
+ 	u8 seconds, minutes, hours, wday, mday, month, years;
+ 
+@@ -317,8 +316,7 @@ ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ static int
+ ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
+ 
+ 	/* Fetch the time info from rtc_time. */
+@@ -394,8 +392,7 @@ ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ static int
+ ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
+ 	int ret;
+ 
+@@ -453,8 +450,7 @@ ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ static int
+ ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ctrlb, seconds, minutes, hours, mday;
+ 	int ret;
+ 
+@@ -1119,8 +1115,7 @@ static ssize_t
+ ds1685_rtc_sysfs_battery_show(struct device *dev,
+ 			      struct device_attribute *attr, char *buf)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ctrld;
+ 
+ 	ctrld = rtc->read(rtc, RTC_CTRL_D);
+@@ -1140,8 +1135,7 @@ static ssize_t
+ ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
+ 			      struct device_attribute *attr, char *buf)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ctrl4a;
+ 
+ 	ds1685_rtc_switch_to_bank1(rtc);
+@@ -1163,8 +1157,7 @@ static ssize_t
+ ds1685_rtc_sysfs_serial_show(struct device *dev,
+ 			     struct device_attribute *attr, char *buf)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct ds1685_priv *rtc = platform_get_drvdata(pdev);
++	struct ds1685_priv *rtc = dev_get_drvdata(dev);
+ 	u8 ssn[8];
+ 
+ 	ds1685_rtc_switch_to_bank1(rtc);
+diff --git a/drivers/rtc/rtc-ds1742.c b/drivers/rtc/rtc-ds1742.c
+index 3abf1cbfb8ce..bfaf3780d53a 100644
+--- a/drivers/rtc/rtc-ds1742.c
++++ b/drivers/rtc/rtc-ds1742.c
+@@ -60,8 +60,7 @@ struct rtc_plat_data {
+ 
+ static int ds1742_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr_rtc;
+ 	u8 century;
+ 
+@@ -85,8 +84,7 @@ static int ds1742_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int ds1742_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr_rtc;
+ 	unsigned int year, month, day, hour, minute, second, week;
+ 	unsigned int century;
+diff --git a/drivers/rtc/rtc-lpc32xx.c b/drivers/rtc/rtc-lpc32xx.c
+index 887871c3d526..815545661ad9 100644
+--- a/drivers/rtc/rtc-lpc32xx.c
++++ b/drivers/rtc/rtc-lpc32xx.c
+@@ -294,11 +294,10 @@ static int lpc32xx_rtc_remove(struct platform_device *pdev)
+ #ifdef CONFIG_PM
+ static int lpc32xx_rtc_suspend(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
++	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
+ 
+ 	if (rtc->irq >= 0) {
+-		if (device_may_wakeup(&pdev->dev))
++		if (device_may_wakeup(dev))
+ 			enable_irq_wake(rtc->irq);
+ 		else
+ 			disable_irq_wake(rtc->irq);
+@@ -309,10 +308,9 @@ static int lpc32xx_rtc_suspend(struct device *dev)
+ 
+ static int lpc32xx_rtc_resume(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
++	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
+ 
+-	if (rtc->irq >= 0 && device_may_wakeup(&pdev->dev))
++	if (rtc->irq >= 0 && device_may_wakeup(dev))
+ 		disable_irq_wake(rtc->irq);
+ 
+ 	return 0;
+@@ -321,8 +319,7 @@ static int lpc32xx_rtc_resume(struct device *dev)
+ /* Unconditionally disable the alarm */
+ static int lpc32xx_rtc_freeze(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
++	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
+ 
+ 	spin_lock_irq(&rtc->lock);
+ 
+@@ -337,8 +334,7 @@ static int lpc32xx_rtc_freeze(struct device *dev)
+ 
+ static int lpc32xx_rtc_thaw(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
++	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
+ 
+ 	if (rtc->alarm_enabled) {
+ 		spin_lock_irq(&rtc->lock);
+diff --git a/drivers/rtc/rtc-m48t59.c b/drivers/rtc/rtc-m48t59.c
+index d99a705bec07..3ed8eef289ba 100644
+--- a/drivers/rtc/rtc-m48t59.c
++++ b/drivers/rtc/rtc-m48t59.c
+@@ -47,8 +47,7 @@ struct m48t59_private {
+ static void
+ m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 
+ 	writeb(val, m48t59->ioaddr+ofs);
+ }
+@@ -56,8 +55,7 @@ m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
+ static u8
+ m48t59_mem_readb(struct device *dev, u32 ofs)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 
+ 	return readb(m48t59->ioaddr+ofs);
+ }
+@@ -67,9 +65,8 @@ m48t59_mem_readb(struct device *dev, u32 ofs)
+  */
+ static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	unsigned long flags;
+ 	u8 val;
+ 
+@@ -110,9 +107,8 @@ static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	unsigned long flags;
+ 	u8 val = 0;
+ 	int year = tm->tm_year;
+@@ -157,9 +153,8 @@ static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
+  */
+ static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	struct rtc_time *tm = &alrm->time;
+ 	unsigned long flags;
+ 	u8 val;
+@@ -204,9 +199,8 @@ static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+  */
+ static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	struct rtc_time *tm = &alrm->time;
+ 	u8 mday, hour, min, sec;
+ 	unsigned long flags;
+@@ -265,9 +259,8 @@ static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+  */
+ static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&m48t59->lock, flags);
+@@ -282,9 +275,8 @@ static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ 
+ static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	unsigned long flags;
+ 	u8 val;
+ 
+@@ -303,9 +295,8 @@ static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
+ static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
+ {
+ 	struct device *dev = (struct device *)dev_id;
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
+-	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
++	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
++	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
+ 	u8 event;
+ 
+ 	spin_lock(&m48t59->lock);
+diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
+index 79bb28617d45..e3a7819e915f 100644
+--- a/drivers/rtc/rtc-mv.c
++++ b/drivers/rtc/rtc-mv.c
+@@ -176,8 +176,7 @@ static int mv_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
+ 
+ static int mv_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 
+ 	if (pdata->irq < 0)
+diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
+index bce427d202ee..822ebe4be3c3 100644
+--- a/drivers/rtc/rtc-mxc.c
++++ b/drivers/rtc/rtc-mxc.c
+@@ -109,8 +109,7 @@ static inline int is_imx1_rtc(struct rtc_plat_data *data)
+  */
+ static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
+ 
+@@ -139,8 +138,7 @@ static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
+ static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
+ {
+ 	u32 tod, day, hr, min, sec, temp;
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 
+ 	day = div_s64_rem(time, 86400, &tod);
+@@ -176,8 +174,7 @@ static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
+ static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+ {
+ 	time64_t time;
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 
+ 	time = rtc_tm_to_time64(alrm);
+@@ -190,8 +187,7 @@ static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+ static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
+ 				unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	u32 reg;
+ 
+@@ -266,8 +262,7 @@ static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+  */
+ static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	/*
+ 	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
+@@ -295,8 +290,7 @@ static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
+  */
+ static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 
+ 	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
+@@ -310,8 +304,7 @@ static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+  */
+ static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	rtc_update_alarm(dev, &alrm->time);
+ 
+diff --git a/drivers/rtc/rtc-pcap.c b/drivers/rtc/rtc-pcap.c
+index c4433240d8a9..59aaa05f921e 100644
+--- a/drivers/rtc/rtc-pcap.c
++++ b/drivers/rtc/rtc-pcap.c
+@@ -43,8 +43,7 @@ static irqreturn_t pcap_rtc_irq(int irq, void *_pcap_rtc)
+ 
+ static int pcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct pcap_rtc *pcap_rtc = platform_get_drvdata(pdev);
++	struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
+ 	struct rtc_time *tm = &alrm->time;
+ 	unsigned long secs;
+ 	u32 tod;	/* time of day, seconds since midnight */
+@@ -63,8 +62,7 @@ static int pcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ 
+ static int pcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct pcap_rtc *pcap_rtc = platform_get_drvdata(pdev);
++	struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
+ 	struct rtc_time *tm = &alrm->time;
+ 	unsigned long secs;
+ 	u32 tod, days;
+@@ -82,8 +80,7 @@ static int pcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ 
+ static int pcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct pcap_rtc *pcap_rtc = platform_get_drvdata(pdev);
++	struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
+ 	unsigned long secs;
+ 	u32 tod, days;
+ 
+@@ -100,8 +97,7 @@ static int pcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int pcap_rtc_set_mmss(struct device *dev, unsigned long secs)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct pcap_rtc *pcap_rtc = platform_get_drvdata(pdev);
++	struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
+ 	u32 tod, days;
+ 
+ 	tod = secs % SEC_PER_DAY;
+@@ -115,8 +111,7 @@ static int pcap_rtc_set_mmss(struct device *dev, unsigned long secs)
+ 
+ static int pcap_rtc_irq_enable(struct device *dev, int pirq, unsigned int en)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct pcap_rtc *pcap_rtc = platform_get_drvdata(pdev);
++	struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
+ 
+ 	if (en)
+ 		enable_irq(pcap_to_irq(pcap_rtc->pcap, pirq));
+diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
+index 6c2d3989f967..735d122bdc74 100644
+--- a/drivers/rtc/rtc-sh.c
++++ b/drivers/rtc/rtc-sh.c
+@@ -359,8 +359,7 @@ static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+ 
+ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
++	struct sh_rtc *rtc = dev_get_drvdata(dev);
+ 	unsigned int sec128, sec2, yr, yr100, cf_bit;
+ 
+ 	do {
+@@ -419,8 +418,7 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
++	struct sh_rtc *rtc = dev_get_drvdata(dev);
+ 	unsigned int tmp;
+ 	int year;
+ 
+@@ -475,8 +473,7 @@ static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
+ 
+ static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
++	struct sh_rtc *rtc = dev_get_drvdata(dev);
+ 	struct rtc_time *tm = &wkalrm->time;
+ 
+ 	spin_lock_irq(&rtc->lock);
+@@ -509,8 +506,7 @@ static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
+ 
+ static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
++	struct sh_rtc *rtc = dev_get_drvdata(dev);
+ 	unsigned int rcr1;
+ 	struct rtc_time *tm = &wkalrm->time;
+ 	int mon;
+@@ -723,8 +719,7 @@ static int __exit sh_rtc_remove(struct platform_device *pdev)
+ 
+ static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
++	struct sh_rtc *rtc = dev_get_drvdata(dev);
+ 
+ 	irq_set_irq_wake(rtc->periodic_irq, enabled);
+ 
+diff --git a/drivers/rtc/rtc-stk17ta8.c b/drivers/rtc/rtc-stk17ta8.c
+index a456cb6177ea..2e30affd79d0 100644
+--- a/drivers/rtc/rtc-stk17ta8.c
++++ b/drivers/rtc/rtc-stk17ta8.c
+@@ -74,8 +74,7 @@ struct rtc_plat_data {
+ 
+ static int stk17ta8_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	u8 flags;
+ 
+@@ -97,8 +96,7 @@ static int stk17ta8_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ 
+ static int stk17ta8_rtc_read_time(struct device *dev, struct rtc_time *tm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 	void __iomem *ioaddr = pdata->ioaddr;
+ 	unsigned int year, month, day, hour, minute, second, week;
+ 	unsigned int century;
+@@ -167,8 +165,7 @@ static void stk17ta8_rtc_update_alarm(struct rtc_plat_data *pdata)
+ 
+ static int stk17ta8_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -184,8 +181,7 @@ static int stk17ta8_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ 
+ static int stk17ta8_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+@@ -221,8 +217,7 @@ static irqreturn_t stk17ta8_rtc_interrupt(int irq, void *dev_id)
+ static int stk17ta8_rtc_alarm_irq_enable(struct device *dev,
+ 	unsigned int enabled)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
++	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
+ 
+ 	if (pdata->irq <= 0)
+ 		return -EINVAL;
+diff --git a/drivers/rtc/rtc-test.c b/drivers/rtc/rtc-test.c
+index 3a2da4c892d6..390f928fd6fc 100644
+--- a/drivers/rtc/rtc-test.c
++++ b/drivers/rtc/rtc-test.c
+@@ -84,8 +84,7 @@ static ssize_t test_irq_store(struct device *dev,
+ 				const char *buf, size_t count)
+ {
+ 	int retval;
+-	struct platform_device *plat_dev = to_platform_device(dev);
+-	struct rtc_device *rtc = platform_get_drvdata(plat_dev);
++	struct rtc_device *rtc = dev_get_drvdata(dev);
+ 
+ 	retval = count;
+ 	if (strncmp(buf, "tick", 4) == 0 && rtc->pie_enabled)
+diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
+index da18a8ae3c1d..821b939836e1 100644
+--- a/drivers/rtc/rtc-zynqmp.c
++++ b/drivers/rtc/rtc-zynqmp.c
+@@ -278,10 +278,9 @@ static int xlnx_rtc_remove(struct platform_device *pdev)
+ 
+ static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
++	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
+ 
+-	if (device_may_wakeup(&pdev->dev))
++	if (device_may_wakeup(dev))
+ 		enable_irq_wake(xrtcdev->alarm_irq);
+ 	else
+ 		xlnx_rtc_alarm_irq_enable(dev, 0);
+@@ -291,10 +290,9 @@ static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
+ 
+ static int __maybe_unused xlnx_rtc_resume(struct device *dev)
+ {
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
++	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
+ 
+-	if (device_may_wakeup(&pdev->dev))
++	if (device_may_wakeup(dev))
+ 		disable_irq_wake(xrtcdev->alarm_irq);
+ 	else
+ 		xlnx_rtc_alarm_irq_enable(dev, 1);
+-- 
+2.19.0
+
diff --git a/patches/1262-serial-sh-sci-Add-support-for-dynamic-instances.patch b/patches/1262-serial-sh-sci-Add-support-for-dynamic-instances.patch
new file mode 100644
index 00000000000000..91eb7d4204c4fb
--- /dev/null
+++ b/patches/1262-serial-sh-sci-Add-support-for-dynamic-instances.patch
@@ -0,0 +1,101 @@
+From dfd1cc0d1f8680ba3c405fb479f4e65aba2c679c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 5 Mar 2018 18:17:40 +0100
+Subject: [PATCH 1262/1795] serial: sh-sci: Add support for dynamic instances
+
+On DT platforms, the sh-sci driver requires the presence of "serialN"
+aliases in DT, from which instance IDs are derived.  If a DT alias is
+missing, the drivers fails to probe the corresponding serial port.
+
+This becomes cumbersome when considering DT overlays, as currently
+there is no upstream support for dynamically updating the /aliases node
+in DT.  Furthermore, even in the presence of such support, hardcoded
+instance IDs in independent overlays are prone to conflicts.
+
+Hence add support for dynamic instance IDs, to be used in the absence of
+a DT alias.  This makes serial ports behave similar to I2C and SPI
+buses, which already support dynamic instances.
+
+Ports in use are tracked using a simple bitmask of type unsigned long,
+which is sufficient to handle all current hardware (max. 18 ports).
+The maximum number of serial ports is still fixed, and configurable
+through Kconfig.  Range validation is done through both Kconfig and a
+compile-time check.
+
+Due to the fixed maximum number of serial ports, dynamic and static
+instances share the same ID space.  Static instances added later are
+rejected when conflicting with dynamic instances registered earlier.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 7678f4c20fa7670fcc23e2537a26543c5c6a7772)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/Kconfig  | 2 ++
+ drivers/tty/serial/sh-sci.c | 8 ++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index 3682fd3e960c..76005dc5f624 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -762,6 +762,8 @@ config SERIAL_SH_SCI
+ 
+ config SERIAL_SH_SCI_NR_UARTS
+ 	int "Maximum number of SCI(F) serial ports" if EXPERT
++	range 1 64 if 64BIT
++	range 1 32 if !64BIT
+ 	depends on SERIAL_SH_SCI
+ 	default "3" if H8300
+ 	default "10" if SUPERH
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 2051a5309851..59fac9761e9c 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -160,6 +160,7 @@ struct sci_port {
+ #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
+ 
+ static struct sci_port sci_ports[SCI_NPORTS];
++static unsigned long sci_ports_in_use;
+ static struct uart_driver sci_uart_driver;
+ 
+ static inline struct sci_port *
+@@ -3024,6 +3025,7 @@ static int sci_remove(struct platform_device *dev)
+ {
+ 	struct sci_port *port = platform_get_drvdata(dev);
+ 
++	sci_ports_in_use &= ~BIT(port->port.line);
+ 	uart_remove_one_port(&sci_uart_driver, &port->port);
+ 
+ 	sci_cleanup_single(port);
+@@ -3105,6 +3107,8 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
+ 
+ 	/* Get the line number from the aliases node. */
+ 	id = of_alias_get_id(np, "serial");
++	if (id < 0 && ~sci_ports_in_use)
++		id = ffz(sci_ports_in_use);
+ 	if (id < 0) {
+ 		dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
+ 		return NULL;
+@@ -3139,6 +3143,9 @@ static int sci_probe_single(struct platform_device *dev,
+ 		dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
+ 		return -EINVAL;
+ 	}
++	BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
++	if (sci_ports_in_use & BIT(index))
++		return -EBUSY;
+ 
+ 	mutex_lock(&sci_uart_registration_lock);
+ 	if (!sci_uart_driver.state) {
+@@ -3237,6 +3244,7 @@ static int sci_probe(struct platform_device *dev)
+ 	sh_bios_gdb_detach();
+ #endif
+ 
++	sci_ports_in_use |= BIT(dev_id);
+ 	return 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1263-serial-sh-sci-Support-for-HSCIF-RX-sampling-point-ad.patch b/patches/1263-serial-sh-sci-Support-for-HSCIF-RX-sampling-point-ad.patch
new file mode 100644
index 00000000000000..8ef81688027a40
--- /dev/null
+++ b/patches/1263-serial-sh-sci-Support-for-HSCIF-RX-sampling-point-ad.patch
@@ -0,0 +1,132 @@
+From 2853a76c42b6ce0f1cad26374714ac91f163c7f4 Mon Sep 17 00:00:00 2001
+From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Date: Wed, 4 Apr 2018 17:48:51 +0200
+Subject: [PATCH 1263/1795] serial: sh-sci: Support for HSCIF RX sampling point
+ adjustment
+
+HSCIF has facilities that allow moving the RX sampling point by between
+-8 and 7 sampling cycles (one sampling cycles equals 1/15 of a bit
+by default) to improve the error margin in case of slightly mismatched
+bit rates between sender and receiver.
+
+This patch tries to determine if shifting the sampling point can improve
+the error margin and will enable it if so.
+
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 63ba1e00f178a4483b473489cadc4eb52a77df2a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/tty/serial/sh-sci.c | 65 ++++++++++++++++++++++++-------------
+ drivers/tty/serial/sh-sci.h |  4 +++
+ 2 files changed, 46 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
+index 59fac9761e9c..c181eb37f985 100644
+--- a/drivers/tty/serial/sh-sci.c
++++ b/drivers/tty/serial/sh-sci.c
+@@ -2391,6 +2391,27 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 
+ 	uart_update_timeout(port, termios->c_cflag, baud);
+ 
++	/* byte size and parity */
++	switch (termios->c_cflag & CSIZE) {
++	case CS5:
++		bits = 7;
++		break;
++	case CS6:
++		bits = 8;
++		break;
++	case CS7:
++		bits = 9;
++		break;
++	default:
++		bits = 10;
++		break;
++	}
++
++	if (termios->c_cflag & CSTOPB)
++		bits++;
++	if (termios->c_cflag & PARENB)
++		bits++;
++
+ 	if (best_clk >= 0) {
+ 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
+ 			switch (srr + 1) {
+@@ -2407,8 +2428,27 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
+ 		serial_port_out(port, SCSMR, smr_val);
+ 		serial_port_out(port, SCBRR, brr);
+-		if (sci_getreg(port, HSSRR)->size)
+-			serial_port_out(port, HSSRR, srr | HSCIF_SRE);
++		if (sci_getreg(port, HSSRR)->size) {
++			unsigned int hssrr = srr | HSCIF_SRE;
++			/* Calculate deviation from intended rate at the
++			 * center of the last stop bit in sampling clocks.
++			 */
++			int last_stop = bits * 2 - 1;
++			int deviation = min_err * srr * last_stop / 2 / baud;
++
++			if (abs(deviation) >= 2) {
++				/* At least two sampling clocks off at the
++				 * last stop bit; we can increase the error
++				 * margin by shifting the sampling point.
++				 */
++				int shift = min(-8, max(7, deviation / 2));
++
++				hssrr |= (shift << HSCIF_SRHP_SHIFT) &
++					 HSCIF_SRHP_MASK;
++				hssrr |= HSCIF_SRDE;
++			}
++			serial_port_out(port, HSSRR, hssrr);
++		}
+ 
+ 		/* Wait one bit interval */
+ 		udelay((1000000 + (baud - 1)) / baud);
+@@ -2475,27 +2515,6 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	 * value obtained by this formula is too small. Therefore, if the value
+ 	 * is smaller than 20ms, use 20ms as the timeout value for DMA.
+ 	 */
+-	/* byte size and parity */
+-	switch (termios->c_cflag & CSIZE) {
+-	case CS5:
+-		bits = 7;
+-		break;
+-	case CS6:
+-		bits = 8;
+-		break;
+-	case CS7:
+-		bits = 9;
+-		break;
+-	default:
+-		bits = 10;
+-		break;
+-	}
+-
+-	if (termios->c_cflag & CSTOPB)
+-		bits++;
+-	if (termios->c_cflag & PARENB)
+-		bits++;
+-
+ 	s->rx_frame = (10000 * bits) / (baud / 100);
+ #ifdef CONFIG_SERIAL_SH_SCI_DMA
+ 	s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
+diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
+index a5f792fd48d9..0b9e804e61a9 100644
+--- a/drivers/tty/serial/sh-sci.h
++++ b/drivers/tty/serial/sh-sci.h
+@@ -130,6 +130,10 @@ enum {
+ 
+ /* HSSRR HSCIF */
+ #define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */
++#define HSCIF_SRDE	BIT(14) /* Sampling Point Register Enable */
++
++#define HSCIF_SRHP_SHIFT	8
++#define HSCIF_SRHP_MASK		0x0f00
+ 
+ /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
+ #define SCPCR_RTSC	BIT(4)	/* Serial Port RTS# Pin / Output Pin */
+-- 
+2.19.0
+
diff --git a/patches/1264-staging-board-Replace-license-boilerplate-with-SPDX-.patch b/patches/1264-staging-board-Replace-license-boilerplate-with-SPDX-.patch
new file mode 100644
index 00000000000000..65a9aaf42d173e
--- /dev/null
+++ b/patches/1264-staging-board-Replace-license-boilerplate-with-SPDX-.patch
@@ -0,0 +1,63 @@
+From 4eb47167b82411d4a8e20d7c804fec7b4dcd0163 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sat, 5 May 2018 21:48:15 -0700
+Subject: [PATCH 1264/1795] staging: board: Replace license boilerplate with
+ SPDX identifiers
+
+This satisfies a checkpatch.pl warning and is the preferred method for
+notating the license due to its lack of ambiguity.
+
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 0a07573c290019b904da76de098e2d1114ea5ba1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/staging/board/armadillo800eva.c | 10 +---------
+ drivers/staging/board/board.c           |  5 +----
+ 2 files changed, 2 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/staging/board/armadillo800eva.c b/drivers/staging/board/armadillo800eva.c
+index 4de4fd06eebc..962cc0c79988 100644
+--- a/drivers/staging/board/armadillo800eva.c
++++ b/drivers/staging/board/armadillo800eva.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Staging board support for Armadillo 800 eva.
+  * Enable not-yet-DT-capable devices here.
+@@ -6,15 +7,6 @@
+  *
+  * Copyright (C) 2012 Renesas Solutions Corp.
+  * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+  */
+ 
+ #include <linux/dma-mapping.h>
+diff --git a/drivers/staging/board/board.c b/drivers/staging/board/board.c
+index 86dc41101610..cb6feb34dd40 100644
+--- a/drivers/staging/board/board.c
++++ b/drivers/staging/board/board.c
+@@ -1,10 +1,7 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Copyright (C) 2014 Magnus Damm
+  * Copyright (C) 2015 Glider bvba
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+  */
+ 
+ #define pr_fmt(fmt)	"board_staging: "  fmt
+-- 
+2.19.0
+
diff --git a/patches/1265-usb-gadget-udc-renesas_usb3-should-call-pm_runtime_e.patch b/patches/1265-usb-gadget-udc-renesas_usb3-should-call-pm_runtime_e.patch
new file mode 100644
index 00000000000000..bc558bc765a441
--- /dev/null
+++ b/patches/1265-usb-gadget-udc-renesas_usb3-should-call-pm_runtime_e.patch
@@ -0,0 +1,48 @@
+From 4f257c3938f60b154dfa66a2e9163f8f93adbc69 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 10 Apr 2018 14:38:51 +0900
+Subject: [PATCH 1265/1795] usb: gadget: udc: renesas_usb3: should call
+ pm_runtime_enable() before add udc
+
+This patch fixes an issue that this driver causes panic if a gadget
+driver is already loaded because usb_add_gadget_udc() might call
+renesas_usb3_start() via .udc_start, and then pm_runtime_get_sync()
+in renesas_usb3_start() doesn't work correctly.
+Note that the usb3_to_dev() macro should not be called at this timing
+because the macro uses the gadget structure.
+
+Fixes: cf06df3fae28 ("usb: gadget: udc: renesas_usb3: move pm_runtime_{en,dis}able()")
+Cc: <stable@vger.kernel.org> # v4.15+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit d998844016b24a8d71b9aa5eae7e51d70f2de438)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 94224101033e..2afb235006dc 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2641,6 +2641,7 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto err_alloc_prd;
+ 
++	pm_runtime_enable(&pdev->dev);
+ 	ret = usb_add_gadget_udc(&pdev->dev, &usb3->gadget);
+ 	if (ret < 0)
+ 		goto err_add_udc;
+@@ -2662,7 +2663,6 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	renesas_usb3_debugfs_init(usb3, &pdev->dev);
+ 
+ 	dev_info(&pdev->dev, "probed%s\n", usb3->phy ? " with phy" : "");
+-	pm_runtime_enable(usb3_to_dev(usb3));
+ 
+ 	return 0;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1266-usb-gadget-udc-renesas_usb3-should-call-devm_phy_get.patch b/patches/1266-usb-gadget-udc-renesas_usb3-should-call-devm_phy_get.patch
new file mode 100644
index 00000000000000..f38a350b62942f
--- /dev/null
+++ b/patches/1266-usb-gadget-udc-renesas_usb3-should-call-devm_phy_get.patch
@@ -0,0 +1,60 @@
+From d93de538a9adb7d280b89abc37647d6842854e6a Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 10 Apr 2018 14:38:52 +0900
+Subject: [PATCH 1266/1795] usb: gadget: udc: renesas_usb3: should call
+ devm_phy_get() before add udc
+
+This patch fixes an issue that this driver cannot call phy_init()
+if a gadget driver is alreadly loaded because usb_add_gadget_udc()
+might call renesas_usb3_start() via .udc_start.
+This patch also revises the typo (s/an optional/optional/).
+
+Fixes: 279d4bc64060 ("usb: gadget: udc: renesas_usb3: add support for generic phy")
+Cc: <stable@vger.kernel.org> # v4.15+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 003bc1dee216b1fb8e02040a95672bea0f1fe797)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 2afb235006dc..9a6e3d99dffd 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2641,6 +2641,14 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto err_alloc_prd;
+ 
++	/*
++	 * This is optional. So, if this driver cannot get a phy,
++	 * this driver will not handle a phy anymore.
++	 */
++	usb3->phy = devm_phy_get(&pdev->dev, "usb");
++	if (IS_ERR(usb3->phy))
++		usb3->phy = NULL;
++
+ 	pm_runtime_enable(&pdev->dev);
+ 	ret = usb_add_gadget_udc(&pdev->dev, &usb3->gadget);
+ 	if (ret < 0)
+@@ -2650,14 +2658,6 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto err_dev_create;
+ 
+-	/*
+-	 * This is an optional. So, if this driver cannot get a phy,
+-	 * this driver will not handle a phy anymore.
+-	 */
+-	usb3->phy = devm_phy_get(&pdev->dev, "usb");
+-	if (IS_ERR(usb3->phy))
+-		usb3->phy = NULL;
+-
+ 	usb3->workaround_for_vbus = priv->workaround_for_vbus;
+ 
+ 	renesas_usb3_debugfs_init(usb3, &pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/1267-usb-gadget-udc-renesas_usb3-should-fail-if-devm_phy_.patch b/patches/1267-usb-gadget-udc-renesas_usb3-should-fail-if-devm_phy_.patch
new file mode 100644
index 00000000000000..63db9031dcb1e6
--- /dev/null
+++ b/patches/1267-usb-gadget-udc-renesas_usb3-should-fail-if-devm_phy_.patch
@@ -0,0 +1,46 @@
+From 4e549ef17cbe9148465fcca9a5540d74c4cd05ce Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 10 Apr 2018 14:38:53 +0900
+Subject: [PATCH 1267/1795] usb: gadget: udc: renesas_usb3: should fail if
+ devm_phy_get() returns error
+
+This patch fixes an issue that this driver ignores errors other than
+the non-existence of the device, f.e. a memory allocation failure
+in devm_phy_get(). So, this patch replaces devm_phy_get() with
+devm_phy_optional_get().
+
+Reported-by: Simon Horman <horms+renesas@verge.net.au>
+Fixes: 279d4bc64060 ("usb: gadget: udc: renesas_usb3: add support for generic phy")
+Cc: <stable@vger.kernel.org> # v4.15+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 0259068f63f23a665ded28647f2f9cdb6b20dc72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 9a6e3d99dffd..2bb2cca5ca82 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2645,9 +2645,11 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	 * This is optional. So, if this driver cannot get a phy,
+ 	 * this driver will not handle a phy anymore.
+ 	 */
+-	usb3->phy = devm_phy_get(&pdev->dev, "usb");
+-	if (IS_ERR(usb3->phy))
+-		usb3->phy = NULL;
++	usb3->phy = devm_phy_optional_get(&pdev->dev, "usb");
++	if (IS_ERR(usb3->phy)) {
++		ret = PTR_ERR(usb3->phy);
++		goto err_add_udc;
++	}
+ 
+ 	pm_runtime_enable(&pdev->dev);
+ 	ret = usb_add_gadget_udc(&pdev->dev, &usb3->gadget);
+-- 
+2.19.0
+
diff --git a/patches/1268-usb-gadget-udc-renesas_usb3-fix-double-phy_put.patch b/patches/1268-usb-gadget-udc-renesas_usb3-fix-double-phy_put.patch
new file mode 100644
index 00000000000000..067b49ba3a7b4a
--- /dev/null
+++ b/patches/1268-usb-gadget-udc-renesas_usb3-fix-double-phy_put.patch
@@ -0,0 +1,38 @@
+From db4ed099a5dab53c92a29b9bd21696af3f7955da Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 2 Apr 2018 21:21:31 +0900
+Subject: [PATCH 1268/1795] usb: gadget: udc: renesas_usb3: fix double
+ phy_put()
+
+This patch fixes an issue that this driver cause double phy_put()
+calling. This driver must not call phy_put() in the remove because
+the driver calls devm_phy_get() in the probe.
+
+Fixes: 279d4bc64060 ("usb: gadget: udc: renesas_usb3: add support for generic phy")
+Cc: <stable@vger.kernel.org> # v4.15+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 8223b2f89ca63e203dcb54148e30d94979f17b0b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 2bb2cca5ca82..5caf78bbbf7c 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2421,8 +2421,6 @@ static int renesas_usb3_remove(struct platform_device *pdev)
+ 	renesas_usb3_dma_free_prd(usb3, &pdev->dev);
+ 
+ 	__renesas_usb3_ep_free_request(usb3->ep0_req);
+-	if (usb3->phy)
+-		phy_put(usb3->phy);
+ 	pm_runtime_disable(&pdev->dev);
+ 
+ 	return 0;
+-- 
+2.19.0
+
diff --git a/patches/1269-USB-gadget-udc-renesas_usb3-no-need-to-check-return-.patch b/patches/1269-USB-gadget-udc-renesas_usb3-no-need-to-check-return-.patch
new file mode 100644
index 00000000000000..22742cbec1c1dd
--- /dev/null
+++ b/patches/1269-USB-gadget-udc-renesas_usb3-no-need-to-check-return-.patch
@@ -0,0 +1,55 @@
+From e8fda16939fc9f87ad0832a942d1e521022c6f97 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Tue, 29 May 2018 17:31:06 +0200
+Subject: [PATCH 1269/1795] USB: gadget: udc: renesas_usb3: no need to check
+ return value of debugfs_create functions
+
+When calling debugfs functions, there is no need to ever check the
+return value.  The function can work or not, but the code logic should
+never do something different based on this.
+
+Cc: Felipe Balbi <balbi@kernel.org>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 743d1effe6c1c6b2b42e9e4ca958a4403373702d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/gadget/udc/renesas_usb3.c | 18 +++---------------
+ 1 file changed, 3 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 5caf78bbbf7c..977ea1a02cf9 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -2391,22 +2391,10 @@ static const struct file_operations renesas_usb3_b_device_fops = {
+ static void renesas_usb3_debugfs_init(struct renesas_usb3 *usb3,
+ 				      struct device *dev)
+ {
+-	struct dentry *root, *file;
++	usb3->dentry = debugfs_create_dir(dev_name(dev), NULL);
+ 
+-	root = debugfs_create_dir(dev_name(dev), NULL);
+-	if (IS_ERR_OR_NULL(root)) {
+-		dev_info(dev, "%s: Can't create the root\n", __func__);
+-		return;
+-	}
+-
+-	file = debugfs_create_file("b_device", 0644, root, usb3,
+-				   &renesas_usb3_b_device_fops);
+-	if (!file) {
+-		dev_info(dev, "%s: Can't create debugfs mode\n", __func__);
+-		debugfs_remove_recursive(root);
+-	} else {
+-		usb3->dentry = root;
+-	}
++	debugfs_create_file("b_device", 0644, usb3->dentry, usb3,
++			    &renesas_usb3_b_device_fops);
+ }
+ 
+ /*------- platform_driver ------------------------------------------------*/
+-- 
+2.19.0
+
diff --git a/patches/1270-USB-renesas_usbhs-drop-unused-legacy-phy-support.patch b/patches/1270-USB-renesas_usbhs-drop-unused-legacy-phy-support.patch
new file mode 100644
index 00000000000000..69dba5c1fc1ddf
--- /dev/null
+++ b/patches/1270-USB-renesas_usbhs-drop-unused-legacy-phy-support.patch
@@ -0,0 +1,101 @@
+From 51e70809b224797cd1267e2d0f06dd5f5d95219e Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Wed, 18 Apr 2018 11:26:23 +0200
+Subject: [PATCH 1270/1795] USB: renesas_usbhs: drop unused legacy-phy support
+
+Drop support for legacy phys for rcar2 which hasn't been used with a
+mainline kernel since commit 9080b8dc761a ("ARM: OMAP2+: Remove legacy
+usb-host.c platform init code"). Specifically, since that commit
+usb_get_phy_dev() have always returned -ENODEV and consequently this
+code has not been used.
+
+Note that the legacy-phy API is still being used in gadget mode to bind
+the peripheral controller.
+
+Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d8351953fbb6ed6d7834ac57d9d943d2177c2b20)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/renesas_usbhs/common.h |  1 -
+ drivers/usb/renesas_usbhs/rcar2.c  | 29 -----------------------------
+ 2 files changed, 30 deletions(-)
+
+diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
+index f619afeae2b8..6137f7942c05 100644
+--- a/drivers/usb/renesas_usbhs/common.h
++++ b/drivers/usb/renesas_usbhs/common.h
+@@ -276,7 +276,6 @@ struct usbhs_priv {
+ 	 */
+ 	struct usbhs_fifo_info fifo_info;
+ 
+-	struct usb_phy *usb_phy;
+ 	struct phy *phy;
+ };
+ 
+diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c
+index 85a0e0933917..0027092b1118 100644
+--- a/drivers/usb/renesas_usbhs/rcar2.c
++++ b/drivers/usb/renesas_usbhs/rcar2.c
+@@ -8,7 +8,6 @@
+ #include <linux/gpio.h>
+ #include <linux/of_gpio.h>
+ #include <linux/phy/phy.h>
+-#include <linux/usb/phy.h>
+ #include "common.h"
+ #include "rcar2.h"
+ 
+@@ -26,16 +25,6 @@ static int usbhs_rcar2_hardware_init(struct platform_device *pdev)
+ 		return 0;
+ 	}
+ 
+-	if (IS_ENABLED(CONFIG_USB_PHY)) {
+-		struct usb_phy *usb_phy = usb_get_phy_dev(&pdev->dev, 0);
+-
+-		if (IS_ERR(usb_phy))
+-			return PTR_ERR(usb_phy);
+-
+-		priv->usb_phy = usb_phy;
+-		return 0;
+-	}
+-
+ 	return -ENXIO;
+ }
+ 
+@@ -48,11 +37,6 @@ static int usbhs_rcar2_hardware_exit(struct platform_device *pdev)
+ 		priv->phy = NULL;
+ 	}
+ 
+-	if (priv->usb_phy) {
+-		usb_put_phy(priv->usb_phy);
+-		priv->usb_phy = NULL;
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -75,19 +59,6 @@ static int usbhs_rcar2_power_ctrl(struct platform_device *pdev,
+ 		}
+ 	}
+ 
+-	if (priv->usb_phy) {
+-		if (enable) {
+-			retval = usb_phy_init(priv->usb_phy);
+-
+-			if (!retval)
+-				retval = usb_phy_set_suspend(priv->usb_phy, 0);
+-		} else {
+-			usb_phy_set_suspend(priv->usb_phy, 1);
+-			usb_phy_shutdown(priv->usb_phy);
+-			retval = 0;
+-		}
+-	}
+-
+ 	return retval;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1271-watchdog-renesas-wdt-Remove-R-Car-M2-W-ES2.x-from-bl.patch b/patches/1271-watchdog-renesas-wdt-Remove-R-Car-M2-W-ES2.x-from-bl.patch
new file mode 100644
index 00000000000000..b7dfd5350813c1
--- /dev/null
+++ b/patches/1271-watchdog-renesas-wdt-Remove-R-Car-M2-W-ES2.x-from-bl.patch
@@ -0,0 +1,38 @@
+From 78314c2b56735462b1ee4ea73db0fb740ae777dd Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 18 May 2018 11:55:40 +0200
+Subject: [PATCH 1271/1795] watchdog: renesas-wdt: Remove R-Car M2-W ES2.x from
+ blacklist
+
+System restart triggered by watchdog time-out works fine on a Koelsch
+board with R-Car M2-W ES2.0.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+(cherry picked from commit 665f94423a74759a2b6daf6a5c827e6e9cd8a3a2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/watchdog/renesas_wdt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
+index 514db5cc1595..88d81feba4e6 100644
+--- a/drivers/watchdog/renesas_wdt.c
++++ b/drivers/watchdog/renesas_wdt.c
+@@ -146,7 +146,7 @@ static const struct soc_device_attribute rwdt_quirks_match[] = {
+ 		.data = (void *)1,	/* needs single CPU */
+ 	}, {
+ 		.soc_id = "r8a7791",
+-		.revision = "ES[12].*",
++		.revision = "ES1.*",
+ 		.data = (void *)1,	/* needs single CPU */
+ 	}, {
+ 		.soc_id = "r8a7792",
+-- 
+2.19.0
+
diff --git a/patches/1272-watchdog-renesas-wdt-Add-support-for-the-R8A77965-WD.patch b/patches/1272-watchdog-renesas-wdt-Add-support-for-the-R8A77965-WD.patch
new file mode 100644
index 00000000000000..8c5e13fa6be9c8
--- /dev/null
+++ b/patches/1272-watchdog-renesas-wdt-Add-support-for-the-R8A77965-WD.patch
@@ -0,0 +1,39 @@
+From a0e462a215ec91845db396f703aa89aca67655f0 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 7 May 2018 14:29:42 +0200
+Subject: [PATCH 1272/1795] watchdog: renesas-wdt: Add support for the R8A77965
+ WDT
+
+Document support for the Watchdog Timer (WDT) Controller in the Renesas
+R-Car M3-N (R8A77965) SoC. No driver update is needed.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[wsa: rebased to v4.17-rc3]
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+
+(cherry picked from commit b1eb8fedc01499132ced4b2a44b3ab3855c4e681)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/watchdog/renesas-wdt.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+index 74b2f03c1515..fa56697a1ba6 100644
+--- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
++++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+@@ -7,6 +7,7 @@ Required properties:
+ 	         - "renesas,r7s72100-wdt" (RZ/A1)
+ 	         - "renesas,r8a7795-wdt" (R-Car H3)
+ 	         - "renesas,r8a7796-wdt" (R-Car M3-W)
++		 - "renesas,r8a77965-wdt" (R-Car M3-N)
+ 	         - "renesas,r8a77970-wdt" (R-Car V3M)
+ 	         - "renesas,r8a77995-wdt" (R-Car D3)
+ 
+-- 
+2.19.0
+
diff --git a/patches/1273-dt-bindings-watchdog-renesas-wdt-Add-R-Car-Gen2-supp.patch b/patches/1273-dt-bindings-watchdog-renesas-wdt-Add-R-Car-Gen2-supp.patch
new file mode 100644
index 00000000000000..1ae4c55a59430a
--- /dev/null
+++ b/patches/1273-dt-bindings-watchdog-renesas-wdt-Add-R-Car-Gen2-supp.patch
@@ -0,0 +1,67 @@
+From c0e08a6d08d879463f039ce76b5269207449ee50 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:20 +0000
+Subject: [PATCH 1273/1795] dt-bindings: watchdog: renesas-wdt: Add R-Car Gen2
+ support
+
+This commit documents the compatibility with R-Car Gen2 and RZ/G
+devices by defining the generic compatible string "renesas,rcar-gen2-wdt".
+Also, this patch expands the list of SoC-specific compatible strings to
+include RZ/G and R-Car Gen2 devices.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+(cherry picked from commit 1c85ffc86a2b7b687b110b1427c7e701a453fc54)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/watchdog/renesas-wdt.txt         | 22 +++++++++++++------
+ 1 file changed, 15 insertions(+), 7 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+index fa56697a1ba6..f24d802b8056 100644
+--- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
++++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+@@ -1,19 +1,27 @@
+ Renesas Watchdog Timer (WDT) Controller
+ 
+ Required properties:
+-- compatible : Should be "renesas,<soctype>-wdt", and
+-	       "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback.
++ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
++		fallback compatible string when compatible with the generic
++		version.
+ 	       Examples with soctypes are:
+-	         - "renesas,r7s72100-wdt" (RZ/A1)
++		 - "renesas,r8a7743-wdt" (RZ/G1M)
++		 - "renesas,r8a7745-wdt" (RZ/G1E)
++	         - "renesas,r8a7790-wdt" (R-Car H2)
++	         - "renesas,r8a7791-wdt" (R-Car M2-W)
++	         - "renesas,r8a7792-wdt" (R-Car V2H)
++	         - "renesas,r8a7793-wdt" (R-Car M2-N)
++	         - "renesas,r8a7794-wdt" (R-Car E2)
+ 	         - "renesas,r8a7795-wdt" (R-Car H3)
+ 	         - "renesas,r8a7796-wdt" (R-Car M3-W)
+ 		 - "renesas,r8a77965-wdt" (R-Car M3-N)
+ 	         - "renesas,r8a77970-wdt" (R-Car V3M)
+ 	         - "renesas,r8a77995-wdt" (R-Car D3)
+-
+-  When compatible with the generic version, nodes must list the SoC-specific
+-  version corresponding to the platform first, followed by the generic
+-  version.
++	         - "renesas,r7s72100-wdt" (RZ/A1)
++		The generic compatible string must be:
++		 - "renesas,rza-wdt" for RZ/A
++		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G
++		 - "renesas,rcar-gen3-wdt" for R-Car Gen3
+ 
+ - reg : Should contain WDT registers location and length
+ - clocks : the clock feeding the watchdog timer.
+-- 
+2.19.0
+
diff --git a/patches/1274-spi-Expose-spi_-map-unmap-_buf-for-internal-use.patch b/patches/1274-spi-Expose-spi_-map-unmap-_buf-for-internal-use.patch
new file mode 100644
index 00000000000000..43e21ffd16d418
--- /dev/null
+++ b/patches/1274-spi-Expose-spi_-map-unmap-_buf-for-internal-use.patch
@@ -0,0 +1,131 @@
+From d56e188e7f9f51759079aadfc08fa40662848e26 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Sun, 22 Apr 2018 20:35:14 +0200
+Subject: [PATCH 1274/1795] spi: Expose spi_{map,unmap}_buf() for internal use
+
+spi_{map,unmap}_buf() are needed by the spi-mem logic that is about to
+be introduced to prepare data buffer for DMA operations.
+
+Remove the static specifier on these functions and add their prototypes
+to drivers/spi/internals.h. We do not export the symbols here because
+both SPI_MEM and SPI can't be enabled as modules and we'd like to
+prevent controller/device drivers from using these functions.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 46336966bf0852d76f76c1292c057635b05dbb1b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/internals.h | 41 +++++++++++++++++++++++++++++++++++++++++
+ drivers/spi/spi.c       | 25 +++++++------------------
+ 2 files changed, 48 insertions(+), 18 deletions(-)
+ create mode 100644 drivers/spi/internals.h
+
+diff --git a/drivers/spi/internals.h b/drivers/spi/internals.h
+new file mode 100644
+index 000000000000..dbe56c77b464
+--- /dev/null
++++ b/drivers/spi/internals.h
+@@ -0,0 +1,41 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2018 Exceet Electronics GmbH
++ * Copyright (C) 2018 Bootlin
++ *
++ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
++ *
++ * Helpers needed by the spi or spi-mem logic. Should not be used outside of
++ * spi-mem.c and spi.c.
++ */
++
++#ifndef __LINUX_SPI_INTERNALS_H
++#define __LINUX_SPI_INTERNALS_H
++
++#include <linux/device.h>
++#include <linux/dma-direction.h>
++#include <linux/scatterlist.h>
++#include <linux/spi/spi.h>
++
++#ifdef CONFIG_HAS_DMA
++int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
++		struct sg_table *sgt, void *buf, size_t len,
++		enum dma_data_direction dir);
++void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
++		   struct sg_table *sgt, enum dma_data_direction dir);
++#else /* !CONFIG_HAS_DMA */
++static inline int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
++			      struct sg_table *sgt, void *buf, size_t len,
++			      enum dma_data_direction dir)
++{
++	return -EINVAL;
++}
++
++static inline void spi_unmap_buf(struct spi_controller *ctlr,
++				 struct device *dev, struct sg_table *sgt,
++				 enum dma_data_direction dir)
++{
++}
++#endif /* CONFIG_HAS_DMA */
++
++#endif /* __LINUX_SPI_INTERNALS_H */
+diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
+index f85d30dc9187..ab173b06d147 100644
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -46,6 +46,8 @@
+ #define CREATE_TRACE_POINTS
+ #include <trace/events/spi.h>
+ 
++#include "internals.h"
++
+ static DEFINE_IDR(spi_master_idr);
+ 
+ static void spidev_release(struct device *dev)
+@@ -740,9 +742,9 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
+ }
+ 
+ #ifdef CONFIG_HAS_DMA
+-static int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+-		       struct sg_table *sgt, void *buf, size_t len,
+-		       enum dma_data_direction dir)
++int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
++		struct sg_table *sgt, void *buf, size_t len,
++		enum dma_data_direction dir)
+ {
+ 	const bool vmalloced_buf = is_vmalloc_addr(buf);
+ 	unsigned int max_seg_size = dma_get_max_seg_size(dev);
+@@ -821,8 +823,8 @@ static int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+ 	return 0;
+ }
+ 
+-static void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
+-			  struct sg_table *sgt, enum dma_data_direction dir)
++void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
++		   struct sg_table *sgt, enum dma_data_direction dir)
+ {
+ 	if (sgt->orig_nents) {
+ 		dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
+@@ -907,19 +909,6 @@ static int __spi_unmap_msg(struct spi_controller *ctlr, struct spi_message *msg)
+ 	return 0;
+ }
+ #else /* !CONFIG_HAS_DMA */
+-static inline int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+-			      struct sg_table *sgt, void *buf, size_t len,
+-			      enum dma_data_direction dir)
+-{
+-	return -EINVAL;
+-}
+-
+-static inline void spi_unmap_buf(struct spi_controller *ctlr,
+-				 struct device *dev, struct sg_table *sgt,
+-				 enum dma_data_direction dir)
+-{
+-}
+-
+ static inline int __spi_map_msg(struct spi_controller *ctlr,
+ 				struct spi_message *msg)
+ {
+-- 
+2.19.0
+
diff --git a/patches/1275-spi-Add-an-helper-to-flush-the-message-queue.patch b/patches/1275-spi-Add-an-helper-to-flush-the-message-queue.patch
new file mode 100644
index 00000000000000..37e76d894cb4ea
--- /dev/null
+++ b/patches/1275-spi-Add-an-helper-to-flush-the-message-queue.patch
@@ -0,0 +1,63 @@
+From 7223905929f916348961cc84f461e3d3452edf35 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Sun, 22 Apr 2018 20:35:15 +0200
+Subject: [PATCH 1275/1795] spi: Add an helper to flush the message queue
+
+This is needed by the spi-mem logic to force all messages that have been
+queued before a memory operation to be sent before we start the memory
+operation. We do that in order to guarantee that spi-mem operations do
+not preempt regular SPI transfers.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 988f259b46646934003ff8ae4966f7233691d1ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/internals.h |  2 ++
+ drivers/spi/spi.c       | 16 ++++++++++++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/spi/internals.h b/drivers/spi/internals.h
+index dbe56c77b464..4a28a8395552 100644
+--- a/drivers/spi/internals.h
++++ b/drivers/spi/internals.h
+@@ -17,6 +17,8 @@
+ #include <linux/scatterlist.h>
+ #include <linux/spi/spi.h>
+ 
++void spi_flush_queue(struct spi_controller *ctrl);
++
+ #ifdef CONFIG_HAS_DMA
+ int spi_map_buf(struct spi_controller *ctlr, struct device *dev,
+ 		struct sg_table *sgt, void *buf, size_t len,
+diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
+index ab173b06d147..0fb91af66efd 100644
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -1523,6 +1523,22 @@ static int spi_controller_initialize_queue(struct spi_controller *ctlr)
+ 	return ret;
+ }
+ 
++/**
++ * spi_flush_queue - Send all pending messages in the queue from the callers'
++ *		     context
++ * @ctlr: controller to process queue for
++ *
++ * This should be used when one wants to ensure all pending messages have been
++ * sent before doing something. Is used by the spi-mem code to make sure SPI
++ * memory operations do not preempt regular SPI transfers that have been queued
++ * before the spi-mem operation.
++ */
++void spi_flush_queue(struct spi_controller *ctlr)
++{
++	if (ctlr->transfer == spi_queued_transfer)
++		__spi_pump_messages(ctlr, false);
++}
++
+ /*-------------------------------------------------------------------------*/
+ 
+ #if defined(CONFIG_OF)
+-- 
+2.19.0
+
diff --git a/patches/1276-spi-Extend-the-core-to-ease-integration-of-SPI-memor.patch b/patches/1276-spi-Extend-the-core-to-ease-integration-of-SPI-memor.patch
new file mode 100644
index 00000000000000..a004de51d2e659
--- /dev/null
+++ b/patches/1276-spi-Extend-the-core-to-ease-integration-of-SPI-memor.patch
@@ -0,0 +1,768 @@
+From 659020c82ecd59d7bd7a34f2ce1fb32e5e5180b2 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 26 Apr 2018 18:18:14 +0200
+Subject: [PATCH 1276/1795] spi: Extend the core to ease integration of SPI
+ memory controllers
+
+Some controllers are exposing high-level interfaces to access various
+kind of SPI memories. Unfortunately they do not fit in the current
+spi_controller model and usually have drivers placed in
+drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
+memories in general.
+
+This is an attempt at defining a SPI memory interface which works for
+all kinds of SPI memories (NORs, NANDs, SRAMs).
+
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
+Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit c36ff266dc82f4ae797a6f3513c6ffa344f7f1c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/spi/Kconfig         |   7 +
+ drivers/spi/Makefile        |   1 +
+ drivers/spi/spi-mem.c       | 410 ++++++++++++++++++++++++++++++++++++
+ include/linux/spi/spi-mem.h | 249 ++++++++++++++++++++++
+ include/linux/spi/spi.h     |   7 +
+ 5 files changed, 674 insertions(+)
+ create mode 100644 drivers/spi/spi-mem.c
+ create mode 100644 include/linux/spi/spi-mem.h
+
+diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+index a75f2a2cf780..378e6a40b6a4 100644
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -51,6 +51,13 @@ config SPI_MASTER
+ 
+ if SPI_MASTER
+ 
++config SPI_MEM
++	bool "SPI memory extension"
++	help
++	  Enable this option if you want to enable the SPI memory extension.
++	  This extension is meant to simplify interaction with SPI memories
++	  by providing an high-level interface to send memory-like commands.
++
+ comment "SPI Master Controller Drivers"
+ 
+ config SPI_ALTERA
+diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
+index 8e0cda73b324..d95bfe95d295 100644
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -8,6 +8,7 @@ ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
+ # small core, mostly translating board-specific
+ # config declarations into driver model code
+ obj-$(CONFIG_SPI_MASTER)		+= spi.o
++obj-$(CONFIG_SPI_MEM)			+= spi-mem.o
+ obj-$(CONFIG_SPI_SPIDEV)		+= spidev.o
+ obj-$(CONFIG_SPI_LOOPBACK_TEST)		+= spi-loopback-test.o
+ 
+diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
+new file mode 100644
+index 000000000000..990770dfa5cf
+--- /dev/null
++++ b/drivers/spi/spi-mem.c
+@@ -0,0 +1,410 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2018 Exceet Electronics GmbH
++ * Copyright (C) 2018 Bootlin
++ *
++ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
++ */
++#include <linux/dmaengine.h>
++#include <linux/pm_runtime.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi-mem.h>
++
++#include "internals.h"
++
++/**
++ * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
++ *					  memory operation
++ * @ctlr: the SPI controller requesting this dma_map()
++ * @op: the memory operation containing the buffer to map
++ * @sgt: a pointer to a non-initialized sg_table that will be filled by this
++ *	 function
++ *
++ * Some controllers might want to do DMA on the data buffer embedded in @op.
++ * This helper prepares everything for you and provides a ready-to-use
++ * sg_table. This function is not intended to be called from spi drivers.
++ * Only SPI controller drivers should use it.
++ * Note that the caller must ensure the memory region pointed by
++ * op->data.buf.{in,out} is DMA-able before calling this function.
++ *
++ * Return: 0 in case of success, a negative error code otherwise.
++ */
++int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
++				       const struct spi_mem_op *op,
++				       struct sg_table *sgt)
++{
++	struct device *dmadev;
++
++	if (!op->data.nbytes)
++		return -EINVAL;
++
++	if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
++		dmadev = ctlr->dma_tx->device->dev;
++	else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
++		dmadev = ctlr->dma_rx->device->dev;
++	else
++		dmadev = ctlr->dev.parent;
++
++	if (!dmadev)
++		return -EINVAL;
++
++	return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes,
++			   op->data.dir == SPI_MEM_DATA_IN ?
++			   DMA_FROM_DEVICE : DMA_TO_DEVICE);
++}
++EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data);
++
++/**
++ * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a
++ *					    memory operation
++ * @ctlr: the SPI controller requesting this dma_unmap()
++ * @op: the memory operation containing the buffer to unmap
++ * @sgt: a pointer to an sg_table previously initialized by
++ *	 spi_controller_dma_map_mem_op_data()
++ *
++ * Some controllers might want to do DMA on the data buffer embedded in @op.
++ * This helper prepares things so that the CPU can access the
++ * op->data.buf.{in,out} buffer again.
++ *
++ * This function is not intended to be called from SPI drivers. Only SPI
++ * controller drivers should use it.
++ *
++ * This function should be called after the DMA operation has finished and is
++ * only valid if the previous spi_controller_dma_map_mem_op_data() call
++ * returned 0.
++ *
++ * Return: 0 in case of success, a negative error code otherwise.
++ */
++void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
++					  const struct spi_mem_op *op,
++					  struct sg_table *sgt)
++{
++	struct device *dmadev;
++
++	if (!op->data.nbytes)
++		return;
++
++	if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
++		dmadev = ctlr->dma_tx->device->dev;
++	else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
++		dmadev = ctlr->dma_rx->device->dev;
++	else
++		dmadev = ctlr->dev.parent;
++
++	spi_unmap_buf(ctlr, dmadev, sgt,
++		      op->data.dir == SPI_MEM_DATA_IN ?
++		      DMA_FROM_DEVICE : DMA_TO_DEVICE);
++}
++EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
++
++static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
++{
++	u32 mode = mem->spi->mode;
++
++	switch (buswidth) {
++	case 1:
++		return 0;
++
++	case 2:
++		if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) ||
++		    (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD))))
++			return 0;
++
++		break;
++
++	case 4:
++		if ((tx && (mode & SPI_TX_QUAD)) ||
++		    (!tx && (mode & SPI_RX_QUAD)))
++			return 0;
++
++		break;
++
++	default:
++		break;
++	}
++
++	return -ENOTSUPP;
++}
++
++static bool spi_mem_default_supports_op(struct spi_mem *mem,
++					const struct spi_mem_op *op)
++{
++	if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
++		return false;
++
++	if (op->addr.nbytes &&
++	    spi_check_buswidth_req(mem, op->addr.buswidth, true))
++		return false;
++
++	if (op->dummy.nbytes &&
++	    spi_check_buswidth_req(mem, op->dummy.buswidth, true))
++		return false;
++
++	if (op->data.nbytes &&
++	    spi_check_buswidth_req(mem, op->data.buswidth,
++				   op->data.dir == SPI_MEM_DATA_OUT))
++		return false;
++
++	return true;
++}
++EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
++
++/**
++ * spi_mem_supports_op() - Check if a memory device and the controller it is
++ *			   connected to support a specific memory operation
++ * @mem: the SPI memory
++ * @op: the memory operation to check
++ *
++ * Some controllers are only supporting Single or Dual IOs, others might only
++ * support specific opcodes, or it can even be that the controller and device
++ * both support Quad IOs but the hardware prevents you from using it because
++ * only 2 IO lines are connected.
++ *
++ * This function checks whether a specific operation is supported.
++ *
++ * Return: true if @op is supported, false otherwise.
++ */
++bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
++{
++	struct spi_controller *ctlr = mem->spi->controller;
++
++	if (ctlr->mem_ops && ctlr->mem_ops->supports_op)
++		return ctlr->mem_ops->supports_op(mem, op);
++
++	return spi_mem_default_supports_op(mem, op);
++}
++EXPORT_SYMBOL_GPL(spi_mem_supports_op);
++
++/**
++ * spi_mem_exec_op() - Execute a memory operation
++ * @mem: the SPI memory
++ * @op: the memory operation to execute
++ *
++ * Executes a memory operation.
++ *
++ * This function first checks that @op is supported and then tries to execute
++ * it.
++ *
++ * Return: 0 in case of success, a negative error code otherwise.
++ */
++int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
++{
++	unsigned int tmpbufsize, xferpos = 0, totalxferlen = 0;
++	struct spi_controller *ctlr = mem->spi->controller;
++	struct spi_transfer xfers[4] = { };
++	struct spi_message msg;
++	u8 *tmpbuf;
++	int ret;
++
++	if (!spi_mem_supports_op(mem, op))
++		return -ENOTSUPP;
++
++	if (ctlr->mem_ops) {
++		/*
++		 * Flush the message queue before executing our SPI memory
++		 * operation to prevent preemption of regular SPI transfers.
++		 */
++		spi_flush_queue(ctlr);
++
++		if (ctlr->auto_runtime_pm) {
++			ret = pm_runtime_get_sync(ctlr->dev.parent);
++			if (ret < 0) {
++				dev_err(&ctlr->dev,
++					"Failed to power device: %d\n",
++					ret);
++				return ret;
++			}
++		}
++
++		mutex_lock(&ctlr->bus_lock_mutex);
++		mutex_lock(&ctlr->io_mutex);
++		ret = ctlr->mem_ops->exec_op(mem, op);
++		mutex_unlock(&ctlr->io_mutex);
++		mutex_unlock(&ctlr->bus_lock_mutex);
++
++		if (ctlr->auto_runtime_pm)
++			pm_runtime_put(ctlr->dev.parent);
++
++		/*
++		 * Some controllers only optimize specific paths (typically the
++		 * read path) and expect the core to use the regular SPI
++		 * interface in other cases.
++		 */
++		if (!ret || ret != -ENOTSUPP)
++			return ret;
++	}
++
++	tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
++		     op->dummy.nbytes;
++
++	/*
++	 * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
++	 * we're guaranteed that this buffer is DMA-able, as required by the
++	 * SPI layer.
++	 */
++	tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
++	if (!tmpbuf)
++		return -ENOMEM;
++
++	spi_message_init(&msg);
++
++	tmpbuf[0] = op->cmd.opcode;
++	xfers[xferpos].tx_buf = tmpbuf;
++	xfers[xferpos].len = sizeof(op->cmd.opcode);
++	xfers[xferpos].tx_nbits = op->cmd.buswidth;
++	spi_message_add_tail(&xfers[xferpos], &msg);
++	xferpos++;
++	totalxferlen++;
++
++	if (op->addr.nbytes) {
++		int i;
++
++		for (i = 0; i < op->addr.nbytes; i++)
++			tmpbuf[i + 1] = op->addr.val >>
++					(8 * (op->addr.nbytes - i - 1));
++
++		xfers[xferpos].tx_buf = tmpbuf + 1;
++		xfers[xferpos].len = op->addr.nbytes;
++		xfers[xferpos].tx_nbits = op->addr.buswidth;
++		spi_message_add_tail(&xfers[xferpos], &msg);
++		xferpos++;
++		totalxferlen += op->addr.nbytes;
++	}
++
++	if (op->dummy.nbytes) {
++		memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
++		xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
++		xfers[xferpos].len = op->dummy.nbytes;
++		xfers[xferpos].tx_nbits = op->dummy.buswidth;
++		spi_message_add_tail(&xfers[xferpos], &msg);
++		xferpos++;
++		totalxferlen += op->dummy.nbytes;
++	}
++
++	if (op->data.nbytes) {
++		if (op->data.dir == SPI_MEM_DATA_IN) {
++			xfers[xferpos].rx_buf = op->data.buf.in;
++			xfers[xferpos].rx_nbits = op->data.buswidth;
++		} else {
++			xfers[xferpos].tx_buf = op->data.buf.out;
++			xfers[xferpos].tx_nbits = op->data.buswidth;
++		}
++
++		xfers[xferpos].len = op->data.nbytes;
++		spi_message_add_tail(&xfers[xferpos], &msg);
++		xferpos++;
++		totalxferlen += op->data.nbytes;
++	}
++
++	ret = spi_sync(mem->spi, &msg);
++
++	kfree(tmpbuf);
++
++	if (ret)
++		return ret;
++
++	if (msg.actual_length != totalxferlen)
++		return -EIO;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(spi_mem_exec_op);
++
++/**
++ * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
++ *			      match controller limitations
++ * @mem: the SPI memory
++ * @op: the operation to adjust
++ *
++ * Some controllers have FIFO limitations and must split a data transfer
++ * operation into multiple ones, others require a specific alignment for
++ * optimized accesses. This function allows SPI mem drivers to split a single
++ * operation into multiple sub-operations when required.
++ *
++ * Return: a negative error code if the controller can't properly adjust @op,
++ *	   0 otherwise. Note that @op->data.nbytes will be updated if @op
++ *	   can't be handled in a single step.
++ */
++int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
++{
++	struct spi_controller *ctlr = mem->spi->controller;
++
++	if (ctlr->mem_ops && ctlr->mem_ops->adjust_op_size)
++		return ctlr->mem_ops->adjust_op_size(mem, op);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
++
++static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv)
++{
++	return container_of(drv, struct spi_mem_driver, spidrv.driver);
++}
++
++static int spi_mem_probe(struct spi_device *spi)
++{
++	struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
++	struct spi_mem *mem;
++
++	mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL);
++	if (!mem)
++		return -ENOMEM;
++
++	mem->spi = spi;
++	spi_set_drvdata(spi, mem);
++
++	return memdrv->probe(mem);
++}
++
++static int spi_mem_remove(struct spi_device *spi)
++{
++	struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
++	struct spi_mem *mem = spi_get_drvdata(spi);
++
++	if (memdrv->remove)
++		return memdrv->remove(mem);
++
++	return 0;
++}
++
++static void spi_mem_shutdown(struct spi_device *spi)
++{
++	struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
++	struct spi_mem *mem = spi_get_drvdata(spi);
++
++	if (memdrv->shutdown)
++		memdrv->shutdown(mem);
++}
++
++/**
++ * spi_mem_driver_register_with_owner() - Register a SPI memory driver
++ * @memdrv: the SPI memory driver to register
++ * @owner: the owner of this driver
++ *
++ * Registers a SPI memory driver.
++ *
++ * Return: 0 in case of success, a negative error core otherwise.
++ */
++
++int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv,
++				       struct module *owner)
++{
++	memdrv->spidrv.probe = spi_mem_probe;
++	memdrv->spidrv.remove = spi_mem_remove;
++	memdrv->spidrv.shutdown = spi_mem_shutdown;
++
++	return __spi_register_driver(owner, &memdrv->spidrv);
++}
++EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner);
++
++/**
++ * spi_mem_driver_unregister_with_owner() - Unregister a SPI memory driver
++ * @memdrv: the SPI memory driver to unregister
++ *
++ * Unregisters a SPI memory driver.
++ */
++void spi_mem_driver_unregister(struct spi_mem_driver *memdrv)
++{
++	spi_unregister_driver(&memdrv->spidrv);
++}
++EXPORT_SYMBOL_GPL(spi_mem_driver_unregister);
+diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
+new file mode 100644
+index 000000000000..bb4bd15ae1f6
+--- /dev/null
++++ b/include/linux/spi/spi-mem.h
+@@ -0,0 +1,249 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2018 Exceet Electronics GmbH
++ * Copyright (C) 2018 Bootlin
++ *
++ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
++ */
++
++#ifndef __LINUX_SPI_MEM_H
++#define __LINUX_SPI_MEM_H
++
++#include <linux/spi/spi.h>
++
++#define SPI_MEM_OP_CMD(__opcode, __buswidth)			\
++	{							\
++		.buswidth = __buswidth,				\
++		.opcode = __opcode,				\
++	}
++
++#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth)		\
++	{							\
++		.nbytes = __nbytes,				\
++		.val = __val,					\
++		.buswidth = __buswidth,				\
++	}
++
++#define SPI_MEM_OP_NO_ADDR	{ }
++
++#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)			\
++	{							\
++		.nbytes = __nbytes,				\
++		.buswidth = __buswidth,				\
++	}
++
++#define SPI_MEM_OP_NO_DUMMY	{ }
++
++#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth)		\
++	{							\
++		.dir = SPI_MEM_DATA_IN,				\
++		.nbytes = __nbytes,				\
++		.buf.in = __buf,				\
++		.buswidth = __buswidth,				\
++	}
++
++#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth)	\
++	{							\
++		.dir = SPI_MEM_DATA_OUT,			\
++		.nbytes = __nbytes,				\
++		.buf.out = __buf,				\
++		.buswidth = __buswidth,				\
++	}
++
++#define SPI_MEM_OP_NO_DATA	{ }
++
++/**
++ * enum spi_mem_data_dir - describes the direction of a SPI memory data
++ *			   transfer from the controller perspective
++ * @SPI_MEM_DATA_IN: data coming from the SPI memory
++ * @SPI_MEM_DATA_OUT: data sent the SPI memory
++ */
++enum spi_mem_data_dir {
++	SPI_MEM_DATA_IN,
++	SPI_MEM_DATA_OUT,
++};
++
++/**
++ * struct spi_mem_op - describes a SPI memory operation
++ * @cmd.buswidth: number of IO lines used to transmit the command
++ * @cmd.opcode: operation opcode
++ * @addr.nbytes: number of address bytes to send. Can be zero if the operation
++ *		 does not need to send an address
++ * @addr.buswidth: number of IO lines used to transmit the address cycles
++ * @addr.val: address value. This value is always sent MSB first on the bus.
++ *	      Note that only @addr.nbytes are taken into account in this
++ *	      address value, so users should make sure the value fits in the
++ *	      assigned number of bytes.
++ * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
++ *		  be zero if the operation does not require dummy bytes
++ * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
++ * @data.buswidth: number of IO lanes used to send/receive the data
++ * @data.dir: direction of the transfer
++ * @data.buf.in: input buffer
++ * @data.buf.out: output buffer
++ */
++struct spi_mem_op {
++	struct {
++		u8 buswidth;
++		u8 opcode;
++	} cmd;
++
++	struct {
++		u8 nbytes;
++		u8 buswidth;
++		u64 val;
++	} addr;
++
++	struct {
++		u8 nbytes;
++		u8 buswidth;
++	} dummy;
++
++	struct {
++		u8 buswidth;
++		enum spi_mem_data_dir dir;
++		unsigned int nbytes;
++		/* buf.{in,out} must be DMA-able. */
++		union {
++			void *in;
++			const void *out;
++		} buf;
++	} data;
++};
++
++#define SPI_MEM_OP(__cmd, __addr, __dummy, __data)		\
++	{							\
++		.cmd = __cmd,					\
++		.addr = __addr,					\
++		.dummy = __dummy,				\
++		.data = __data,					\
++	}
++
++/**
++ * struct spi_mem - describes a SPI memory device
++ * @spi: the underlying SPI device
++ * @drvpriv: spi_mem_drviver private data
++ *
++ * Extra information that describe the SPI memory device and may be needed by
++ * the controller to properly handle this device should be placed here.
++ *
++ * One example would be the device size since some controller expose their SPI
++ * mem devices through a io-mapped region.
++ */
++struct spi_mem {
++	struct spi_device *spi;
++	void *drvpriv;
++};
++
++/**
++ * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem
++ *				  device
++ * @mem: memory device
++ * @data: data to attach to the memory device
++ */
++static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data)
++{
++	mem->drvpriv = data;
++}
++
++/**
++ * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem
++ *				  device
++ * @mem: memory device
++ *
++ * Return: the data attached to the mem device.
++ */
++static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
++{
++	return mem->drvpriv;
++}
++
++/**
++ * struct spi_controller_mem_ops - SPI memory operations
++ * @adjust_op_size: shrink the data xfer of an operation to match controller's
++ *		    limitations (can be alignment of max RX/TX size
++ *		    limitations)
++ * @supports_op: check if an operation is supported by the controller
++ * @exec_op: execute a SPI memory operation
++ *
++ * This interface should be implemented by SPI controllers providing an
++ * high-level interface to execute SPI memory operation, which is usually the
++ * case for QSPI controllers.
++ */
++struct spi_controller_mem_ops {
++	int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op);
++	bool (*supports_op)(struct spi_mem *mem,
++			    const struct spi_mem_op *op);
++	int (*exec_op)(struct spi_mem *mem,
++		       const struct spi_mem_op *op);
++};
++
++/**
++ * struct spi_mem_driver - SPI memory driver
++ * @spidrv: inherit from a SPI driver
++ * @probe: probe a SPI memory. Usually where detection/initialization takes
++ *	   place
++ * @remove: remove a SPI memory
++ * @shutdown: take appropriate action when the system is shutdown
++ *
++ * This is just a thin wrapper around a spi_driver. The core takes care of
++ * allocating the spi_mem object and forwarding the probe/remove/shutdown
++ * request to the spi_mem_driver. The reason we use this wrapper is because
++ * we might have to stuff more information into the spi_mem struct to let
++ * SPI controllers know more about the SPI memory they interact with, and
++ * having this intermediate layer allows us to do that without adding more
++ * useless fields to the spi_device object.
++ */
++struct spi_mem_driver {
++	struct spi_driver spidrv;
++	int (*probe)(struct spi_mem *mem);
++	int (*remove)(struct spi_mem *mem);
++	void (*shutdown)(struct spi_mem *mem);
++};
++
++#if IS_ENABLED(CONFIG_SPI_MEM)
++int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
++				       const struct spi_mem_op *op,
++				       struct sg_table *sg);
++
++void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
++					  const struct spi_mem_op *op,
++					  struct sg_table *sg);
++#else
++static inline int
++spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
++				   const struct spi_mem_op *op,
++				   struct sg_table *sg)
++{
++	return -ENOTSUPP;
++}
++
++static inline void
++spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
++				     const struct spi_mem_op *op,
++				     struct sg_table *sg)
++{
++}
++#endif /* CONFIG_SPI_MEM */
++
++int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
++
++bool spi_mem_supports_op(struct spi_mem *mem,
++			 const struct spi_mem_op *op);
++
++int spi_mem_exec_op(struct spi_mem *mem,
++		    const struct spi_mem_op *op);
++
++int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
++				       struct module *owner);
++
++void spi_mem_driver_unregister(struct spi_mem_driver *drv);
++
++#define spi_mem_driver_register(__drv)                                  \
++	spi_mem_driver_register_with_owner(__drv, THIS_MODULE)
++
++#define module_spi_mem_driver(__drv)                                    \
++	module_driver(__drv, spi_mem_driver_register,                   \
++		      spi_mem_driver_unregister)
++
++#endif /* __LINUX_SPI_MEM_H */
+diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
+index 7b2170bfd6e7..f49b684dc390 100644
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -27,6 +27,7 @@ struct property_entry;
+ struct spi_controller;
+ struct spi_transfer;
+ struct spi_flash_read_message;
++struct spi_controller_mem_ops;
+ 
+ /*
+  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
+@@ -376,6 +377,9 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
+  *                    transfer_one callback.
+  * @handle_err: the subsystem calls the driver to handle an error that occurs
+  *		in the generic implementation of transfer_one_message().
++ * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
++ *	     This field is optional and should only be implemented if the
++ *	     controller has native support for memory like operations.
+  * @unprepare_message: undo any work done by prepare_message().
+  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
+  * @spi_flash_read: to support spi-controller hardwares that provide
+@@ -564,6 +568,9 @@ struct spi_controller {
+ 	void (*handle_err)(struct spi_controller *ctlr,
+ 			   struct spi_message *message);
+ 
++	/* Optimized handlers for SPI memory-like operations. */
++	const struct spi_controller_mem_ops *mem_ops;
++
+ 	/* gpio chip select */
+ 	int			*cs_gpios;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1277-mtd-spi-nor-Use-the-spi_mem_xx-API.patch b/patches/1277-mtd-spi-nor-Use-the-spi_mem_xx-API.patch
new file mode 100644
index 00000000000000..b02c4a88617859
--- /dev/null
+++ b/patches/1277-mtd-spi-nor-Use-the-spi_mem_xx-API.patch
@@ -0,0 +1,400 @@
+From f04dfeb66b6484441a70beef2f46be730cd7a20b Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 26 Apr 2018 18:18:19 +0200
+Subject: [PATCH 1277/1795] mtd: spi-nor: Use the spi_mem_xx() API
+
+The spi_mem_xxx() API has been introduced to replace the
+spi_flash_read() one. Make use of it so we can get rid of
+spi_flash_read().
+
+Note that using spi_mem_xx() also simplifies the code because this API
+takes care of using the regular spi_sync() interface when the optimized
+->mem_ops interface is not implemented by the controller.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
+Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 4120f8d158ef904fb305b27e4a4524649faf3096)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mtd/devices/Kconfig  |   1 +
+ drivers/mtd/devices/m25p80.c | 236 ++++++++++++-----------------------
+ 2 files changed, 80 insertions(+), 157 deletions(-)
+
+diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
+index 6def5445e03e..57b02c4b3f63 100644
+--- a/drivers/mtd/devices/Kconfig
++++ b/drivers/mtd/devices/Kconfig
+@@ -81,6 +81,7 @@ config MTD_DATAFLASH_OTP
+ config MTD_M25P80
+ 	tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
+ 	depends on SPI_MASTER && MTD_SPI_NOR
++	select SPI_MEM
+ 	help
+ 	  This enables access to most modern SPI flash chips, used for
+ 	  program and data storage.   Series supported include Atmel AT26DF,
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index a4e18f6aaa33..3dc022d3b53e 100644
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -24,12 +24,13 @@
+ #include <linux/mtd/partitions.h>
+ 
+ #include <linux/spi/spi.h>
++#include <linux/spi/spi-mem.h>
+ #include <linux/spi/flash.h>
+ #include <linux/mtd/spi-nor.h>
+ 
+ #define	MAX_CMD_SIZE		6
+ struct m25p {
+-	struct spi_device	*spi;
++	struct spi_mem		*spimem;
+ 	struct spi_nor		spi_nor;
+ 	u8			command[MAX_CMD_SIZE];
+ };
+@@ -37,97 +38,68 @@ struct m25p {
+ static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
+ {
+ 	struct m25p *flash = nor->priv;
+-	struct spi_device *spi = flash->spi;
++	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
++					  SPI_MEM_OP_NO_ADDR,
++					  SPI_MEM_OP_NO_DUMMY,
++					  SPI_MEM_OP_DATA_IN(len, val, 1));
+ 	int ret;
+ 
+-	ret = spi_write_then_read(spi, &code, 1, val, len);
++	ret = spi_mem_exec_op(flash->spimem, &op);
+ 	if (ret < 0)
+-		dev_err(&spi->dev, "error %d reading %x\n", ret, code);
++		dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
++			code);
+ 
+ 	return ret;
+ }
+ 
+-static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
+-{
+-	/* opcode is in cmd[0] */
+-	cmd[1] = addr >> (nor->addr_width * 8 -  8);
+-	cmd[2] = addr >> (nor->addr_width * 8 - 16);
+-	cmd[3] = addr >> (nor->addr_width * 8 - 24);
+-	cmd[4] = addr >> (nor->addr_width * 8 - 32);
+-}
+-
+-static int m25p_cmdsz(struct spi_nor *nor)
+-{
+-	return 1 + nor->addr_width;
+-}
+-
+ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+ {
+ 	struct m25p *flash = nor->priv;
+-	struct spi_device *spi = flash->spi;
+-
+-	flash->command[0] = opcode;
+-	if (buf)
+-		memcpy(&flash->command[1], buf, len);
++	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
++					  SPI_MEM_OP_NO_ADDR,
++					  SPI_MEM_OP_NO_DUMMY,
++					  SPI_MEM_OP_DATA_OUT(len, buf, 1));
+ 
+-	return spi_write(spi, flash->command, len + 1);
++	return spi_mem_exec_op(flash->spimem, &op);
+ }
+ 
+ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+ 			    const u_char *buf)
+ {
+ 	struct m25p *flash = nor->priv;
+-	struct spi_device *spi = flash->spi;
+-	unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
+-	struct spi_transfer t[3] = {};
+-	struct spi_message m;
+-	int cmd_sz = m25p_cmdsz(nor);
+-	ssize_t ret;
++	struct spi_mem_op op =
++			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
++				   SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
++				   SPI_MEM_OP_DUMMY(0, 1),
++				   SPI_MEM_OP_DATA_OUT(len, buf, 1));
++	size_t remaining = len;
++	int ret;
+ 
+ 	/* get transfer protocols. */
+-	inst_nbits = spi_nor_get_protocol_inst_nbits(nor->write_proto);
+-	addr_nbits = spi_nor_get_protocol_addr_nbits(nor->write_proto);
+-	data_nbits = spi_nor_get_protocol_data_nbits(nor->write_proto);
+-
+-	spi_message_init(&m);
++	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
++	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
++	op.dummy.buswidth = op.addr.buswidth;
++	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+ 
+ 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+-		cmd_sz = 1;
+-
+-	flash->command[0] = nor->program_opcode;
+-	m25p_addr2cmd(nor, to, flash->command);
++		op.addr.nbytes = 0;
+ 
+-	t[0].tx_buf = flash->command;
+-	t[0].tx_nbits = inst_nbits;
+-	t[0].len = cmd_sz;
+-	spi_message_add_tail(&t[0], &m);
+-
+-	/* split the op code and address bytes into two transfers if needed. */
+-	data_idx = 1;
+-	if (addr_nbits != inst_nbits) {
+-		t[0].len = 1;
++	while (remaining) {
++		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
++		ret = spi_mem_adjust_op_size(flash->spimem, &op);
++		if (ret)
++			return ret;
+ 
+-		t[1].tx_buf = &flash->command[1];
+-		t[1].tx_nbits = addr_nbits;
+-		t[1].len = cmd_sz - 1;
+-		spi_message_add_tail(&t[1], &m);
++		ret = spi_mem_exec_op(flash->spimem, &op);
++		if (ret)
++			return ret;
+ 
+-		data_idx = 2;
++		op.addr.val += op.data.nbytes;
++		remaining -= op.data.nbytes;
++		op.data.buf.out += op.data.nbytes;
+ 	}
+ 
+-	t[data_idx].tx_buf = buf;
+-	t[data_idx].tx_nbits = data_nbits;
+-	t[data_idx].len = len;
+-	spi_message_add_tail(&t[data_idx], &m);
+-
+-	ret = spi_sync(spi, &m);
+-	if (ret)
+-		return ret;
+-
+-	ret = m.actual_length - cmd_sz;
+-	if (ret < 0)
+-		return -EIO;
+-	return ret;
++	return len;
+ }
+ 
+ /*
+@@ -138,92 +110,39 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+ 			   u_char *buf)
+ {
+ 	struct m25p *flash = nor->priv;
+-	struct spi_device *spi = flash->spi;
+-	unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;
+-	struct spi_transfer t[3];
+-	struct spi_message m;
+-	unsigned int dummy = nor->read_dummy;
+-	ssize_t ret;
+-	int cmd_sz;
++	struct spi_mem_op op =
++			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
++				   SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
++				   SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
++				   SPI_MEM_OP_DATA_IN(len, buf, 1));
++	size_t remaining = len;
++	int ret;
+ 
+ 	/* get transfer protocols. */
+-	inst_nbits = spi_nor_get_protocol_inst_nbits(nor->read_proto);
+-	addr_nbits = spi_nor_get_protocol_addr_nbits(nor->read_proto);
+-	data_nbits = spi_nor_get_protocol_data_nbits(nor->read_proto);
++	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
++	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
++	op.dummy.buswidth = op.addr.buswidth;
++	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
+ 
+ 	/* convert the dummy cycles to the number of bytes */
+-	dummy = (dummy * addr_nbits) / 8;
+-
+-	if (spi_flash_read_supported(spi)) {
+-		struct spi_flash_read_message msg;
+-
+-		memset(&msg, 0, sizeof(msg));
++	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
+ 
+-		msg.buf = buf;
+-		msg.from = from;
+-		msg.len = len;
+-		msg.read_opcode = nor->read_opcode;
+-		msg.addr_width = nor->addr_width;
+-		msg.dummy_bytes = dummy;
+-		msg.opcode_nbits = inst_nbits;
+-		msg.addr_nbits = addr_nbits;
+-		msg.data_nbits = data_nbits;
+-
+-		ret = spi_flash_read(spi, &msg);
+-		if (ret < 0)
++	while (remaining) {
++		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
++		ret = spi_mem_adjust_op_size(flash->spimem, &op);
++		if (ret)
+ 			return ret;
+-		return msg.retlen;
+-	}
+ 
+-	spi_message_init(&m);
+-	memset(t, 0, (sizeof t));
+-
+-	flash->command[0] = nor->read_opcode;
+-	m25p_addr2cmd(nor, from, flash->command);
+-
+-	t[0].tx_buf = flash->command;
+-	t[0].tx_nbits = inst_nbits;
+-	t[0].len = m25p_cmdsz(nor) + dummy;
+-	spi_message_add_tail(&t[0], &m);
+-
+-	/*
+-	 * Set all dummy/mode cycle bits to avoid sending some manufacturer
+-	 * specific pattern, which might make the memory enter its Continuous
+-	 * Read mode by mistake.
+-	 * Based on the different mode cycle bit patterns listed and described
+-	 * in the JESD216B specification, the 0xff value works for all memories
+-	 * and all manufacturers.
+-	 */
+-	cmd_sz = t[0].len;
+-	memset(flash->command + cmd_sz - dummy, 0xff, dummy);
+-
+-	/* split the op code and address bytes into two transfers if needed. */
+-	data_idx = 1;
+-	if (addr_nbits != inst_nbits) {
+-		t[0].len = 1;
+-
+-		t[1].tx_buf = &flash->command[1];
+-		t[1].tx_nbits = addr_nbits;
+-		t[1].len = cmd_sz - 1;
+-		spi_message_add_tail(&t[1], &m);
++		ret = spi_mem_exec_op(flash->spimem, &op);
++		if (ret)
++			return ret;
+ 
+-		data_idx = 2;
++		op.addr.val += op.data.nbytes;
++		remaining -= op.data.nbytes;
++		op.data.buf.in += op.data.nbytes;
+ 	}
+ 
+-	t[data_idx].rx_buf = buf;
+-	t[data_idx].rx_nbits = data_nbits;
+-	t[data_idx].len = min3(len, spi_max_transfer_size(spi),
+-			       spi_max_message_size(spi) - cmd_sz);
+-	spi_message_add_tail(&t[data_idx], &m);
+-
+-	ret = spi_sync(spi, &m);
+-	if (ret)
+-		return ret;
+-
+-	ret = m.actual_length - cmd_sz;
+-	if (ret < 0)
+-		return -EIO;
+-	return ret;
++	return len;
+ }
+ 
+ /*
+@@ -231,8 +150,9 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+  * matches what the READ command supports, at least until this driver
+  * understands FAST_READ (for clocks over 25 MHz).
+  */
+-static int m25p_probe(struct spi_device *spi)
++static int m25p_probe(struct spi_mem *spimem)
+ {
++	struct spi_device *spi = spimem->spi;
+ 	struct flash_platform_data	*data;
+ 	struct m25p *flash;
+ 	struct spi_nor *nor;
+@@ -244,9 +164,9 @@ static int m25p_probe(struct spi_device *spi)
+ 	char *flash_name;
+ 	int ret;
+ 
+-	data = dev_get_platdata(&spi->dev);
++	data = dev_get_platdata(&spimem->spi->dev);
+ 
+-	flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
++	flash = devm_kzalloc(&spimem->spi->dev, sizeof(*flash), GFP_KERNEL);
+ 	if (!flash)
+ 		return -ENOMEM;
+ 
+@@ -258,12 +178,12 @@ static int m25p_probe(struct spi_device *spi)
+ 	nor->write_reg = m25p80_write_reg;
+ 	nor->read_reg = m25p80_read_reg;
+ 
+-	nor->dev = &spi->dev;
++	nor->dev = &spimem->spi->dev;
+ 	spi_nor_set_flash_node(nor, spi->dev.of_node);
+ 	nor->priv = flash;
+ 
+ 	spi_set_drvdata(spi, flash);
+-	flash->spi = spi;
++	flash->spimem = spimem;
+ 
+ 	if (spi->mode & SPI_RX_QUAD) {
+ 		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
+@@ -303,9 +223,9 @@ static int m25p_probe(struct spi_device *spi)
+ }
+ 
+ 
+-static int m25p_remove(struct spi_device *spi)
++static int m25p_remove(struct spi_mem *spimem)
+ {
+-	struct m25p	*flash = spi_get_drvdata(spi);
++	struct m25p	*flash = spi_mem_get_drvdata(spimem);
+ 
+ 	spi_nor_restore(&flash->spi_nor);
+ 
+@@ -313,9 +233,9 @@ static int m25p_remove(struct spi_device *spi)
+ 	return mtd_device_unregister(&flash->spi_nor.mtd);
+ }
+ 
+-static void m25p_shutdown(struct spi_device *spi)
++static void m25p_shutdown(struct spi_mem *spimem)
+ {
+-	struct m25p *flash = spi_get_drvdata(spi);
++	struct m25p *flash = spi_mem_get_drvdata(spimem);
+ 
+ 	spi_nor_restore(&flash->spi_nor);
+ }
+@@ -386,12 +306,14 @@ static const struct of_device_id m25p_of_table[] = {
+ };
+ MODULE_DEVICE_TABLE(of, m25p_of_table);
+ 
+-static struct spi_driver m25p80_driver = {
+-	.driver = {
+-		.name	= "m25p80",
+-		.of_match_table = m25p_of_table,
++static struct spi_mem_driver m25p80_driver = {
++	.spidrv = {
++		.driver = {
++			.name	= "m25p80",
++			.of_match_table = m25p_of_table,
++		},
++		.id_table	= m25p_ids,
+ 	},
+-	.id_table	= m25p_ids,
+ 	.probe	= m25p_probe,
+ 	.remove	= m25p_remove,
+ 	.shutdown	= m25p_shutdown,
+@@ -402,7 +324,7 @@ static struct spi_driver m25p80_driver = {
+ 	 */
+ };
+ 
+-module_spi_driver(m25p80_driver);
++module_spi_mem_driver(m25p80_driver);
+ 
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Mike Lavender");
+-- 
+2.19.0
+
diff --git a/patches/1278-mtd-devices-m25p80-Use-spi_mem_set_drvdata-instead-o.patch b/patches/1278-mtd-devices-m25p80-Use-spi_mem_set_drvdata-instead-o.patch
new file mode 100644
index 00000000000000..fe77fbdf74e5b1
--- /dev/null
+++ b/patches/1278-mtd-devices-m25p80-Use-spi_mem_set_drvdata-instead-o.patch
@@ -0,0 +1,40 @@
+From 5bd419424d6a5274a071bbdcf9413df8f04a1a95 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Tue, 22 May 2018 12:55:14 +0200
+Subject: [PATCH 1278/1795] mtd: devices: m25p80: Use spi_mem_set_drvdata()
+ instead of spi_set_drvdata()
+
+SPI mem drivers should use spi_mem_set_drvdata() not spi_set_drvdata()
+to store their private data. Using spi_set_drvdata() will mess the
+spi -> spi-mem link up and cause a kernel panic at shutdown or
+device removal time.
+
+Fixes: 4120f8d158ef ("mtd: spi-nor: Use the spi_mem_xx() API")
+Reported-by: Marek Vasut <marek.vasut@gmail.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Marek Vasut <marek.vasut+renesas@gmail.com> on R8A7791 Porter
+Signed-off-by: Mark Brown <broonie@kernel.org>
+(cherry picked from commit 1e07392e7b147fd15082f9b755fc249e853f9b96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mtd/devices/m25p80.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index 3dc022d3b53e..e84563d2067f 100644
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -182,7 +182,7 @@ static int m25p_probe(struct spi_mem *spimem)
+ 	spi_nor_set_flash_node(nor, spi->dev.of_node);
+ 	nor->priv = flash;
+ 
+-	spi_set_drvdata(spi, flash);
++	spi_mem_set_drvdata(spimem, flash);
+ 	flash->spimem = spimem;
+ 
+ 	if (spi->mode & SPI_RX_QUAD) {
+-- 
+2.19.0
+
diff --git a/patches/1279-media-rcar-vin-Fix-image-alignment-for-setting-pre-c.patch b/patches/1279-media-rcar-vin-Fix-image-alignment-for-setting-pre-c.patch
new file mode 100644
index 00000000000000..f50ee5bffd966d
--- /dev/null
+++ b/patches/1279-media-rcar-vin-Fix-image-alignment-for-setting-pre-c.patch
@@ -0,0 +1,44 @@
+From e55fab9635160436279b7d2245cf57a250f918af Mon Sep 17 00:00:00 2001
+From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
+Date: Thu, 12 Apr 2018 22:18:13 -0400
+Subject: [PATCH 1279/1795] media: rcar-vin: Fix image alignment for setting
+ pre clipping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In Video Pixel/Line Pre-Clip Register, the setting value can be
+set in 1 line unit, but it can only be specified as a multiple of
+4 by v4l_bound_align_image function().
+So correct that it can be specified in 1 line unit with this patch.
+
+Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Hans Verkuil <hansverk@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 536f0f55384cfcc25d1f8f3cfd4a44048dca3b46)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index b479b882da12..a3c2daca1bf3 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -405,8 +405,8 @@ static int rvin_s_selection(struct file *file, void *fh,
+ 		max_rect.height = vin->source.height;
+ 		v4l2_rect_map_inside(&r, &max_rect);
+ 
+-		v4l_bound_align_image(&r.width, 2, vin->source.width, 1,
+-				      &r.height, 4, vin->source.height, 2, 0);
++		v4l_bound_align_image(&r.width, 6, vin->source.width, 0,
++				      &r.height, 2, vin->source.height, 0, 0);
+ 
+ 		r.top  = clamp_t(s32, r.top, 0, vin->source.height - r.height);
+ 		r.left = clamp_t(s32, r.left, 0, vin->source.width - r.width);
+-- 
+2.19.0
+
diff --git a/patches/1280-media-dt-bindings-media-rcar_vin-Reverse-SoC-part-nu.patch b/patches/1280-media-dt-bindings-media-rcar_vin-Reverse-SoC-part-nu.patch
new file mode 100644
index 00000000000000..39b51877a2e186
--- /dev/null
+++ b/patches/1280-media-dt-bindings-media-rcar_vin-Reverse-SoC-part-nu.patch
@@ -0,0 +1,57 @@
+From db57965af92ffb5ac8b9aeba0a78a3cd4276368e Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Sat, 14 Apr 2018 07:56:54 -0400
+Subject: [PATCH 1280/1795] media: dt-bindings: media: rcar_vin: Reverse SoC
+ part number list
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Change the sorting of the part numbers from descending to ascending to
+match with other documentation.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit aac7a6ccf2d44f8c19273dd5efd3c465a1ab5867)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/media/rcar_vin.txt         | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
+index 033246ab9a01..c0c0b422f615 100644
+--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
++++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
+@@ -6,14 +6,14 @@ family of devices. The current blocks are always slaves and suppot one input
+ channel which can be either RGB, YUYV or BT656.
+ 
+  - compatible: Must be one or more of the following
+-   - "renesas,vin-r8a7795" for the R8A7795 device
+-   - "renesas,vin-r8a7794" for the R8A7794 device
+-   - "renesas,vin-r8a7793" for the R8A7793 device
+-   - "renesas,vin-r8a7792" for the R8A7792 device
+-   - "renesas,vin-r8a7791" for the R8A7791 device
+-   - "renesas,vin-r8a7790" for the R8A7790 device
+-   - "renesas,vin-r8a7779" for the R8A7779 device
+    - "renesas,vin-r8a7778" for the R8A7778 device
++   - "renesas,vin-r8a7779" for the R8A7779 device
++   - "renesas,vin-r8a7790" for the R8A7790 device
++   - "renesas,vin-r8a7791" for the R8A7791 device
++   - "renesas,vin-r8a7792" for the R8A7792 device
++   - "renesas,vin-r8a7793" for the R8A7793 device
++   - "renesas,vin-r8a7794" for the R8A7794 device
++   - "renesas,vin-r8a7795" for the R8A7795 device
+    - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
+    - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
+ 
+-- 
+2.19.0
+
diff --git a/patches/1281-media-dt-bindings-media-rcar_vin-add-device-tree-sup.patch b/patches/1281-media-dt-bindings-media-rcar_vin-add-device-tree-sup.patch
new file mode 100644
index 00000000000000..d8203c30b2b1b1
--- /dev/null
+++ b/patches/1281-media-dt-bindings-media-rcar_vin-add-device-tree-sup.patch
@@ -0,0 +1,58 @@
+From 2b5cabd4f787aa61aae2e0f8f7f85b3c7eb416c0 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Sat, 14 Apr 2018 07:56:55 -0400
+Subject: [PATCH 1281/1795] media: dt-bindings: media: rcar_vin: add device
+ tree support for r8a774[35]
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add compatible strings for r8a7743 and r8a7745. No driver change
+is needed as "renesas,rcar-gen2-vin" will activate the right code.
+However, it is good practice to document compatible strings for the
+specific SoC as this allows SoC specific changes to the driver if
+needed, in addition to document SoC support and therefore allow
+checkpatch.pl to validate compatible string values.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 1d14a5eaa156b0b3898c749fb3f9da1ebbc3f4aa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/media/rcar_vin.txt | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
+index c0c0b422f615..c0c700a9a611 100644
+--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
++++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
+@@ -6,6 +6,8 @@ family of devices. The current blocks are always slaves and suppot one input
+ channel which can be either RGB, YUYV or BT656.
+ 
+  - compatible: Must be one or more of the following
++   - "renesas,vin-r8a7743" for the R8A7743 device
++   - "renesas,vin-r8a7745" for the R8A7745 device
+    - "renesas,vin-r8a7778" for the R8A7778 device
+    - "renesas,vin-r8a7779" for the R8A7779 device
+    - "renesas,vin-r8a7790" for the R8A7790 device
+@@ -14,7 +16,8 @@ channel which can be either RGB, YUYV or BT656.
+    - "renesas,vin-r8a7793" for the R8A7793 device
+    - "renesas,vin-r8a7794" for the R8A7794 device
+    - "renesas,vin-r8a7795" for the R8A7795 device
+-   - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
++   - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
++     device.
+    - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
+ 
+    When compatible with the generic version nodes must list the
+-- 
+2.19.0
+
diff --git a/patches/1282-media-rcar-vin-add-Gen3-devicetree-bindings-document.patch b/patches/1282-media-rcar-vin-add-Gen3-devicetree-bindings-document.patch
new file mode 100644
index 00000000000000..d2b8e17d24d3ab
--- /dev/null
+++ b/patches/1282-media-rcar-vin-add-Gen3-devicetree-bindings-document.patch
@@ -0,0 +1,198 @@
+From eead74b3a49b35e9a7ff56db6769414e34c03097 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:56:56 -0400
+Subject: [PATCH 1282/1795] media: rcar-vin: add Gen3 devicetree bindings
+ documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Document the devicetree bindings for the CSI-2 inputs available on Gen3.
+
+There is a need to add a custom property 'renesas,id' and to define
+which CSI-2 input is described in which endpoint under the port@1 node.
+This information is needed since there are a set of predefined routes
+between each VIN and CSI-2 block. This routing table will be kept
+inside the driver but in order for it to act on it it must know which
+VIN and CSI-2 is which.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a8966fb29e65340c303450aa4dad68af3c34a93c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/media/rcar_vin.txt    | 118 ++++++++++++++++--
+ 1 file changed, 106 insertions(+), 12 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
+index c0c700a9a611..67b312ff924b 100644
+--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
++++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
+@@ -2,8 +2,12 @@ Renesas R-Car Video Input driver (rcar_vin)
+ -------------------------------------------
+ 
+ The rcar_vin device provides video input capabilities for the Renesas R-Car
+-family of devices. The current blocks are always slaves and suppot one input
+-channel which can be either RGB, YUYV or BT656.
++family of devices.
++
++Each VIN instance has a single parallel input that supports RGB and YUV video,
++with both external synchronization and BT.656 synchronization for the latter.
++Depending on the instance the VIN input is connected to external SoC pins, or
++on Gen3 platforms to a CSI-2 receiver.
+ 
+  - compatible: Must be one or more of the following
+    - "renesas,vin-r8a7743" for the R8A7743 device
+@@ -16,6 +20,8 @@ channel which can be either RGB, YUYV or BT656.
+    - "renesas,vin-r8a7793" for the R8A7793 device
+    - "renesas,vin-r8a7794" for the R8A7794 device
+    - "renesas,vin-r8a7795" for the R8A7795 device
++   - "renesas,vin-r8a7796" for the R8A7796 device
++   - "renesas,vin-r8a77970" for the R8A77970 device
+    - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
+      device.
+    - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
+@@ -31,21 +37,38 @@ channel which can be either RGB, YUYV or BT656.
+ Additionally, an alias named vinX will need to be created to specify
+ which video input device this is.
+ 
+-The per-board settings:
++The per-board settings Gen2 platforms:
+  - port sub-node describing a single endpoint connected to the vin
+    as described in video-interfaces.txt[1]. Only the first one will
+    be considered as each vin interface has one input port.
+ 
+-   These settings are used to work out video input format and widths
+-   into the system.
++The per-board settings Gen3 platforms:
++
++Gen3 platforms can support both a single connected parallel input source
++from external SoC pins (port0) and/or multiple parallel input sources
++from local SoC CSI-2 receivers (port1) depending on SoC.
+ 
++- renesas,id - ID number of the VIN, VINx in the documentation.
++- ports
++    - port 0 - sub-node describing a single endpoint connected to the VIN
++      from external SoC pins described in video-interfaces.txt[1].
++      Describing more then one endpoint in port 0 is invalid. Only VIN
++      instances that are connected to external pins should have port 0.
++    - port 1 - sub-nodes describing one or more endpoints connected to
++      the VIN from local SoC CSI-2 receivers. The endpoint numbers must
++      use the following schema.
+ 
+-Device node example
+--------------------
++        - Endpoint 0 - sub-node describing the endpoint connected to CSI20
++        - Endpoint 1 - sub-node describing the endpoint connected to CSI21
++        - Endpoint 2 - sub-node describing the endpoint connected to CSI40
++        - Endpoint 3 - sub-node describing the endpoint connected to CSI41
+ 
+-	aliases {
+-	       vin0 = &vin0;
+-	};
++Device node example for Gen2 platforms
++--------------------------------------
++
++        aliases {
++                vin0 = &vin0;
++        };
+ 
+         vin0: vin@0xe6ef0000 {
+                 compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+@@ -55,8 +78,8 @@ Device node example
+                 status = "disabled";
+         };
+ 
+-Board setup example (vin1 composite video input)
+-------------------------------------------------
++Board setup example for Gen2 platforms (vin1 composite video input)
++-------------------------------------------------------------------
+ 
+ &i2c2   {
+         status = "okay";
+@@ -95,6 +118,77 @@ Board setup example (vin1 composite video input)
+         };
+ };
+ 
++Device node example for Gen3 platforms
++--------------------------------------
++
++        vin0: video@e6ef0000 {
++                compatible = "renesas,vin-r8a7795";
++                reg = <0 0xe6ef0000 0 0x1000>;
++                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++                clocks = <&cpg CPG_MOD 811>;
++                power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++                resets = <&cpg 811>;
++                renesas,id = <0>;
++
++                ports {
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++
++                        port@1 {
++                                #address-cells = <1>;
++                                #size-cells = <0>;
++
++                                reg = <1>;
++
++                                vin0csi20: endpoint@0 {
++                                        reg = <0>;
++                                        remote-endpoint= <&csi20vin0>;
++                                };
++                                vin0csi21: endpoint@1 {
++                                        reg = <1>;
++                                        remote-endpoint= <&csi21vin0>;
++                                };
++                                vin0csi40: endpoint@2 {
++                                        reg = <2>;
++                                        remote-endpoint= <&csi40vin0>;
++                                };
++                        };
++                };
++        };
++
++        csi20: csi2@fea80000 {
++                compatible = "renesas,r8a7795-csi2";
++                reg = <0 0xfea80000 0 0x10000>;
++                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++                clocks = <&cpg CPG_MOD 714>;
++                power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++                resets = <&cpg 714>;
++
++                ports {
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++
++                        port@0 {
++                                reg = <0>;
++                                csi20_in: endpoint {
++                                        clock-lanes = <0>;
++                                        data-lanes = <1>;
++                                        remote-endpoint = <&adv7482_txb>;
++                                };
++                        };
++
++                        port@1 {
++                                #address-cells = <1>;
++                                #size-cells = <0>;
+ 
++                                reg = <1>;
++
++                                csi20vin0: endpoint@0 {
++                                        reg = <0>;
++                                        remote-endpoint = <&vin0csi20>;
++                                };
++                        };
++                };
++        };
+ 
+ [1] video-interfaces.txt common video media interface
+-- 
+2.19.0
+
diff --git a/patches/1283-media-rcar-vin-rename-poorly-named-initialize-and-cl.patch b/patches/1283-media-rcar-vin-rename-poorly-named-initialize-and-cl.patch
new file mode 100644
index 00000000000000..e35457b97580c1
--- /dev/null
+++ b/patches/1283-media-rcar-vin-rename-poorly-named-initialize-and-cl.patch
@@ -0,0 +1,153 @@
+From d34c2d375c0578ca770fcd8378700dceecb71bc8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:56:57 -0400
+Subject: [PATCH 1283/1795] media: rcar-vin: rename poorly named initialize and
+ cleanup functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The functions to register and unregister the hardware and video device
+where poorly named from the start. Rename them to better describe their
+intended function.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit d6ad012ebf274bef78dac09c206edc4b54998dd1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 10 +++++-----
+ drivers/media/platform/rcar-vin/rcar-dma.c  |  6 +++---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c |  4 ++--
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  8 ++++----
+ 4 files changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 108d776f3265..f7a4c21909da 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -93,7 +93,7 @@ static int rvin_digital_notify_complete(struct v4l2_async_notifier *notifier)
+ 		return ret;
+ 	}
+ 
+-	return rvin_v4l2_probe(vin);
++	return rvin_v4l2_register(vin);
+ }
+ 
+ static void rvin_digital_notify_unbind(struct v4l2_async_notifier *notifier,
+@@ -103,7 +103,7 @@ static void rvin_digital_notify_unbind(struct v4l2_async_notifier *notifier,
+ 	struct rvin_dev *vin = notifier_to_vin(notifier);
+ 
+ 	vin_dbg(vin, "unbind digital subdev %s\n", subdev->name);
+-	rvin_v4l2_remove(vin);
++	rvin_v4l2_unregister(vin);
+ 	vin->digital->subdev = NULL;
+ }
+ 
+@@ -245,7 +245,7 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	if (irq < 0)
+ 		return irq;
+ 
+-	ret = rvin_dma_probe(vin, irq);
++	ret = rvin_dma_register(vin, irq);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -260,7 +260,7 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 
+ 	return 0;
+ error:
+-	rvin_dma_remove(vin);
++	rvin_dma_unregister(vin);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+ 	return ret;
+@@ -275,7 +275,7 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+-	rvin_dma_remove(vin);
++	rvin_dma_unregister(vin);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 4a40e6ad1be7..2aae3ca54eab 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -1087,14 +1087,14 @@ static const struct vb2_ops rvin_qops = {
+ 	.wait_finish		= vb2_ops_wait_finish,
+ };
+ 
+-void rvin_dma_remove(struct rvin_dev *vin)
++void rvin_dma_unregister(struct rvin_dev *vin)
+ {
+ 	mutex_destroy(&vin->lock);
+ 
+ 	v4l2_device_unregister(&vin->v4l2_dev);
+ }
+ 
+-int rvin_dma_probe(struct rvin_dev *vin, int irq)
++int rvin_dma_register(struct rvin_dev *vin, int irq)
+ {
+ 	struct vb2_queue *q = &vin->queue;
+ 	int i, ret;
+@@ -1142,7 +1142,7 @@ int rvin_dma_probe(struct rvin_dev *vin, int irq)
+ 
+ 	return 0;
+ error:
+-	rvin_dma_remove(vin);
++	rvin_dma_unregister(vin);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index a3c2daca1bf3..cab38e7a24a3 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -839,7 +839,7 @@ static const struct v4l2_file_operations rvin_fops = {
+ 	.read		= vb2_fop_read,
+ };
+ 
+-void rvin_v4l2_remove(struct rvin_dev *vin)
++void rvin_v4l2_unregister(struct rvin_dev *vin)
+ {
+ 	v4l2_info(&vin->v4l2_dev, "Removing %s\n",
+ 		  video_device_node_name(&vin->vdev));
+@@ -866,7 +866,7 @@ static void rvin_notify(struct v4l2_subdev *sd,
+ 	}
+ }
+ 
+-int rvin_v4l2_probe(struct rvin_dev *vin)
++int rvin_v4l2_register(struct rvin_dev *vin)
+ {
+ 	struct video_device *vdev = &vin->vdev;
+ 	struct v4l2_subdev *sd = vin_to_source(vin);
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 95897127cc41..385243e3d4da 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -153,11 +153,11 @@ struct rvin_dev {
+ #define vin_warn(d, fmt, arg...)	dev_warn(d->dev, fmt, ##arg)
+ #define vin_err(d, fmt, arg...)		dev_err(d->dev, fmt, ##arg)
+ 
+-int rvin_dma_probe(struct rvin_dev *vin, int irq);
+-void rvin_dma_remove(struct rvin_dev *vin);
++int rvin_dma_register(struct rvin_dev *vin, int irq);
++void rvin_dma_unregister(struct rvin_dev *vin);
+ 
+-int rvin_v4l2_probe(struct rvin_dev *vin);
+-void rvin_v4l2_remove(struct rvin_dev *vin);
++int rvin_v4l2_register(struct rvin_dev *vin);
++void rvin_v4l2_unregister(struct rvin_dev *vin);
+ 
+ const struct rvin_video_format *rvin_format_from_pixel(u32 pixelformat);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1284-media-rcar-vin-unregister-video-device-on-driver-rem.patch b/patches/1284-media-rcar-vin-unregister-video-device-on-driver-rem.patch
new file mode 100644
index 00000000000000..bb50168d18a066
--- /dev/null
+++ b/patches/1284-media-rcar-vin-unregister-video-device-on-driver-rem.patch
@@ -0,0 +1,58 @@
+From 9719e5954f0fa9914789cb5ec615440f8a98aadc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:56:58 -0400
+Subject: [PATCH 1284/1795] media: rcar-vin: unregister video device on driver
+ removal
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If the video device was registered by the complete() callback it should
+be unregistered when a device is unbound from the driver. Protect from
+printing an uninitialized video device node name by adding a check in
+rvin_v4l2_unregister() to identify that the video device is registered.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a31ffe939f0d1e425ddf7b8468efa6e6b746a0be)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 2 ++
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 3 +++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index f7a4c21909da..6d99542ec74b 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -272,6 +272,8 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 
+ 	pm_runtime_disable(&pdev->dev);
+ 
++	rvin_v4l2_unregister(vin);
++
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index cab38e7a24a3..953e48ef3390 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -841,6 +841,9 @@ static const struct v4l2_file_operations rvin_fops = {
+ 
+ void rvin_v4l2_unregister(struct rvin_dev *vin)
+ {
++	if (!video_is_registered(&vin->vdev))
++		return;
++
+ 	v4l2_info(&vin->v4l2_dev, "Removing %s\n",
+ 		  video_device_node_name(&vin->vdev));
+ 
+-- 
+2.19.0
+
diff --git a/patches/1285-media-rcar-vin-move-subdevice-handling-to-async-call.patch b/patches/1285-media-rcar-vin-move-subdevice-handling-to-async-call.patch
new file mode 100644
index 00000000000000..a6d898a350b35b
--- /dev/null
+++ b/patches/1285-media-rcar-vin-move-subdevice-handling-to-async-call.patch
@@ -0,0 +1,261 @@
+From 921899a4609557a53782b3579abddfada65031f0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:56:59 -0400
+Subject: [PATCH 1285/1795] media: rcar-vin: move subdevice handling to async
+ callbacks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In preparation for Gen3 support move the subdevice initialization and
+clean up from rvin_v4l2_{register,unregister}() directly to the async
+callbacks. This simplifies the addition of Gen3 support as the
+rvin_v4l2_register() can be shared for both Gen2 and Gen3 while direct
+subdevice control are only used on Gen2.
+
+While moving this code drop a large comment which is copied from the
+framework documentation and fold rvin_mbus_supported() into its only
+caller. Also move the initialization and cleanup code to separate
+functions to increase readability.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 23525ef9f87ebb3a2e3b9141aecd477b2729d669)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/media/platform/rcar-vin/rcar-core.c
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 100 ++++++++++++++------
+ drivers/media/platform/rcar-vin/rcar-v4l2.c |  35 -------
+ 2 files changed, 70 insertions(+), 65 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 6d99542ec74b..aa3a2729d6df 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -46,30 +46,82 @@ static int rvin_find_pad(struct v4l2_subdev *sd, int direction)
+ 	return -EINVAL;
+ }
+ 
+-static bool rvin_mbus_supported(struct rvin_graph_entity *entity)
++/* The vin lock should be held when calling the subdevice attach and detach */
++static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
++					 struct v4l2_subdev *subdev)
+ {
+-	struct v4l2_subdev *sd = entity->subdev;
+ 	struct v4l2_subdev_mbus_code_enum code = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ 	};
++	int ret;
++
++	/* Find source and sink pad of remote subdevice */
++	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
++	if (ret < 0)
++		return ret;
++	vin->digital->source_pad = ret;
+ 
++	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SINK);
++	vin->digital->sink_pad = ret < 0 ? 0 : ret;
++
++	/* Find compatible subdevices mbus format */
++	vin->digital->code = 0;
+ 	code.index = 0;
+-	code.pad = entity->source_pad;
+-	while (!v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code)) {
++	code.pad = vin->digital->source_pad;
++	while (!vin->digital->code &&
++	       !v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
+ 		code.index++;
+ 		switch (code.code) {
+ 		case MEDIA_BUS_FMT_YUYV8_1X16:
+ 		case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		case MEDIA_BUS_FMT_UYVY10_2X10:
+ 		case MEDIA_BUS_FMT_RGB888_1X24:
+-			entity->code = code.code;
+-			return true;
++			vin->digital->code = code.code;
++			vin_dbg(vin, "Found media bus format for %s: %d\n",
++				subdev->name, vin->digital->code);
++			break;
+ 		default:
+ 			break;
+ 		}
+ 	}
+ 
+-	return false;
++	if (!vin->digital->code) {
++		vin_err(vin, "Unsupported media bus format for %s\n",
++			subdev->name);
++		return -EINVAL;
++	}
++
++	/* Read tvnorms */
++	ret = v4l2_subdev_call(subdev, video, g_tvnorms, &vin->vdev.tvnorms);
++	if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
++		return ret;
++
++	/* Add the controls */
++	ret = v4l2_ctrl_handler_init(&vin->ctrl_handler, 16);
++	if (ret < 0)
++		return ret;
++
++	ret = v4l2_ctrl_add_handler(&vin->ctrl_handler, subdev->ctrl_handler,
++				    NULL);
++	if (ret < 0) {
++		v4l2_ctrl_handler_free(&vin->ctrl_handler);
++		return ret;
++	}
++
++	vin->vdev.ctrl_handler = &vin->ctrl_handler;
++
++	vin->digital->subdev = subdev;
++
++	return 0;
++}
++
++static void rvin_digital_subdevice_detach(struct rvin_dev *vin)
++{
++	rvin_v4l2_unregister(vin);
++	v4l2_ctrl_handler_free(&vin->ctrl_handler);
++
++	vin->vdev.ctrl_handler = NULL;
++	vin->digital->subdev = NULL;
+ }
+ 
+ static int rvin_digital_notify_complete(struct v4l2_async_notifier *notifier)
+@@ -77,16 +129,6 @@ static int rvin_digital_notify_complete(struct v4l2_async_notifier *notifier)
+ 	struct rvin_dev *vin = notifier_to_vin(notifier);
+ 	int ret;
+ 
+-	/* Verify subdevices mbus format */
+-	if (!rvin_mbus_supported(vin->digital)) {
+-		vin_err(vin, "Unsupported media bus format for %s\n",
+-			vin->digital->subdev->name);
+-		return -EINVAL;
+-	}
+-
+-	vin_dbg(vin, "Found media bus format for %s: %d\n",
+-		vin->digital->subdev->name, vin->digital->code);
+-
+ 	ret = v4l2_device_register_subdev_nodes(&vin->v4l2_dev);
+ 	if (ret < 0) {
+ 		vin_err(vin, "Failed to register subdev nodes\n");
+@@ -103,8 +145,10 @@ static void rvin_digital_notify_unbind(struct v4l2_async_notifier *notifier,
+ 	struct rvin_dev *vin = notifier_to_vin(notifier);
+ 
+ 	vin_dbg(vin, "unbind digital subdev %s\n", subdev->name);
+-	rvin_v4l2_unregister(vin);
+-	vin->digital->subdev = NULL;
++
++	mutex_lock(&vin->lock);
++	rvin_digital_subdevice_detach(vin);
++	mutex_unlock(&vin->lock);
+ }
+ 
+ static int rvin_digital_notify_bound(struct v4l2_async_notifier *notifier,
+@@ -114,19 +158,13 @@ static int rvin_digital_notify_bound(struct v4l2_async_notifier *notifier,
+ 	struct rvin_dev *vin = notifier_to_vin(notifier);
+ 	int ret;
+ 
+-	v4l2_set_subdev_hostdata(subdev, vin);
+-
+-	/* Find source and sink pad of remote subdevice */
+-
+-	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
+-	if (ret < 0)
++	mutex_lock(&vin->lock);
++	ret = rvin_digital_subdevice_attach(vin, subdev);
++	mutex_unlock(&vin->lock);
++	if (ret)
+ 		return ret;
+-	vin->digital->source_pad = ret;
+-
+-	ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SINK);
+-	vin->digital->sink_pad = ret < 0 ? 0 : ret;
+ 
+-	vin->digital->subdev = subdev;
++	v4l2_set_subdev_hostdata(subdev, vin);
+ 
+ 	vin_dbg(vin, "bound subdev %s source pad: %u sink pad: %u\n",
+ 		subdev->name, vin->digital->source_pad,
+@@ -277,6 +315,8 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
++	v4l2_ctrl_handler_free(&vin->ctrl_handler);
++
+ 	rvin_dma_unregister(vin);
+ 
+ 	return 0;
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 953e48ef3390..9df8ea0f54c9 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -847,9 +847,6 @@ void rvin_v4l2_unregister(struct rvin_dev *vin)
+ 	v4l2_info(&vin->v4l2_dev, "Removing %s\n",
+ 		  video_device_node_name(&vin->vdev));
+ 
+-	/* Checks internaly if handlers have been init or not */
+-	v4l2_ctrl_handler_free(&vin->ctrl_handler);
+-
+ 	/* Checks internaly if vdev have been init or not */
+ 	video_unregister_device(&vin->vdev);
+ }
+@@ -872,41 +869,10 @@ static void rvin_notify(struct v4l2_subdev *sd,
+ int rvin_v4l2_register(struct rvin_dev *vin)
+ {
+ 	struct video_device *vdev = &vin->vdev;
+-	struct v4l2_subdev *sd = vin_to_source(vin);
+ 	int ret;
+ 
+-	v4l2_set_subdev_hostdata(sd, vin);
+-
+ 	vin->v4l2_dev.notify = rvin_notify;
+ 
+-	ret = v4l2_subdev_call(sd, video, g_tvnorms, &vin->vdev.tvnorms);
+-	if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
+-		return ret;
+-
+-	if (vin->vdev.tvnorms == 0) {
+-		/* Disable the STD API if there are no tvnorms defined */
+-		v4l2_disable_ioctl(&vin->vdev, VIDIOC_G_STD);
+-		v4l2_disable_ioctl(&vin->vdev, VIDIOC_S_STD);
+-		v4l2_disable_ioctl(&vin->vdev, VIDIOC_QUERYSTD);
+-		v4l2_disable_ioctl(&vin->vdev, VIDIOC_ENUMSTD);
+-	}
+-
+-	/* Add the controls */
+-	/*
+-	 * Currently the subdev with the largest number of controls (13) is
+-	 * ov6550. So let's pick 16 as a hint for the control handler. Note
+-	 * that this is a hint only: too large and you waste some memory, too
+-	 * small and there is a (very) small performance hit when looking up
+-	 * controls in the internal hash.
+-	 */
+-	ret = v4l2_ctrl_handler_init(&vin->ctrl_handler, 16);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = v4l2_ctrl_add_handler(&vin->ctrl_handler, sd->ctrl_handler, NULL);
+-	if (ret < 0)
+-		return ret;
+-
+ 	/* video node */
+ 	vdev->fops = &rvin_fops;
+ 	vdev->v4l2_dev = &vin->v4l2_dev;
+@@ -915,7 +881,6 @@ int rvin_v4l2_register(struct rvin_dev *vin)
+ 	vdev->release = video_device_release_empty;
+ 	vdev->ioctl_ops = &rvin_ioctl_ops;
+ 	vdev->lock = &vin->lock;
+-	vdev->ctrl_handler = &vin->ctrl_handler;
+ 	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
+ 		V4L2_CAP_READWRITE;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1286-media-rcar-vin-move-model-information-to-own-struct.patch b/patches/1286-media-rcar-vin-move-model-information-to-own-struct.patch
new file mode 100644
index 00000000000000..acdbbf9dd0ae86
--- /dev/null
+++ b/patches/1286-media-rcar-vin-move-model-information-to-own-struct.patch
@@ -0,0 +1,174 @@
+From 8b7df2e1145fb754f0a9c3b1d7def36dcb535198 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:00 -0400
+Subject: [PATCH 1286/1795] media: rcar-vin: move model information to own
+ struct
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When Gen3 support is added to the driver more than model ID will be
+different for the different SoCs. To avoid a lot of if statements in the
+code create a struct rvin_info to store this information.
+
+While we are at it rename the poorly chosen enum which contains the
+different model IDs from chip_id to model_id. Also sort the compatible
+string entries and make use of of_device_get_match_data() which will
+always work as the driver is DT only, so there's always a valid match.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit bb3ed3fd66888f048cd99466751eeb98b031f676)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 56 +++++++++++++++------
+ drivers/media/platform/rcar-vin/rcar-v4l2.c |  3 +-
+ drivers/media/platform/rcar-vin/rcar-vin.h  | 14 ++++--
+ 3 files changed, 55 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index aa3a2729d6df..e65ede0a6cd1 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -241,21 +241,53 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+  * Platform Device Driver
+  */
+ 
++static const struct rvin_info rcar_info_h1 = {
++	.model = RCAR_H1,
++};
++
++static const struct rvin_info rcar_info_m1 = {
++	.model = RCAR_M1,
++};
++
++static const struct rvin_info rcar_info_gen2 = {
++	.model = RCAR_GEN2,
++};
++
+ static const struct of_device_id rvin_of_id_table[] = {
+-	{ .compatible = "renesas,vin-r8a7794", .data = (void *)RCAR_GEN2 },
+-	{ .compatible = "renesas,vin-r8a7793", .data = (void *)RCAR_GEN2 },
+-	{ .compatible = "renesas,vin-r8a7791", .data = (void *)RCAR_GEN2 },
+-	{ .compatible = "renesas,vin-r8a7790", .data = (void *)RCAR_GEN2 },
+-	{ .compatible = "renesas,vin-r8a7779", .data = (void *)RCAR_H1 },
+-	{ .compatible = "renesas,vin-r8a7778", .data = (void *)RCAR_M1 },
+-	{ .compatible = "renesas,rcar-gen2-vin", .data = (void *)RCAR_GEN2 },
+-	{ },
++	{
++		.compatible = "renesas,vin-r8a7778",
++		.data = &rcar_info_m1,
++	},
++	{
++		.compatible = "renesas,vin-r8a7779",
++		.data = &rcar_info_h1,
++	},
++	{
++		.compatible = "renesas,vin-r8a7790",
++		.data = &rcar_info_gen2,
++	},
++	{
++		.compatible = "renesas,vin-r8a7791",
++		.data = &rcar_info_gen2,
++	},
++	{
++		.compatible = "renesas,vin-r8a7793",
++		.data = &rcar_info_gen2,
++	},
++	{
++		.compatible = "renesas,vin-r8a7794",
++		.data = &rcar_info_gen2,
++	},
++	{
++		.compatible = "renesas,rcar-gen2-vin",
++		.data = &rcar_info_gen2,
++	},
++	{ /* Sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, rvin_of_id_table);
+ 
+ static int rcar_vin_probe(struct platform_device *pdev)
+ {
+-	const struct of_device_id *match;
+ 	struct rvin_dev *vin;
+ 	struct resource *mem;
+ 	int irq, ret;
+@@ -264,12 +296,8 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	if (!vin)
+ 		return -ENOMEM;
+ 
+-	match = of_match_device(of_match_ptr(rvin_of_id_table), &pdev->dev);
+-	if (!match)
+-		return -ENODEV;
+-
+ 	vin->dev = &pdev->dev;
+-	vin->chip = (enum chip_id)match->data;
++	vin->info = of_device_get_match_data(&pdev->dev);
+ 
+ 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (mem == NULL)
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 9df8ea0f54c9..97baea8fb7e6 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -266,7 +266,8 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	pix->sizeimage = max_t(u32, pix->sizeimage,
+ 			       rvin_format_sizeimage(pix));
+ 
+-	if (vin->chip == RCAR_M1 && pix->pixelformat == V4L2_PIX_FMT_XBGR32) {
++	if (vin->info->model == RCAR_M1 &&
++	    pix->pixelformat == V4L2_PIX_FMT_XBGR32) {
+ 		vin_err(vin, "pixel format XBGR32 not supported on M1\n");
+ 		return -EINVAL;
+ 	}
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 385243e3d4da..b63c4fce68ad 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -29,7 +29,7 @@
+ /* Address alignment mask for HW buffers */
+ #define HW_BUFFER_MASK 0x7f
+ 
+-enum chip_id {
++enum model_id {
+ 	RCAR_H1,
+ 	RCAR_M1,
+ 	RCAR_GEN2,
+@@ -86,11 +86,19 @@ struct rvin_graph_entity {
+ 	unsigned int sink_pad;
+ };
+ 
++/**
++ * struct rvin_info - Information about the particular VIN implementation
++ * @model:		VIN model
++ */
++struct rvin_info {
++	enum model_id model;
++};
++
+ /**
+  * struct rvin_dev - Renesas VIN device structure
+  * @dev:		(OF) device
+  * @base:		device I/O register space remapped to virtual memory
+- * @chip:		type of VIN chip
++ * @info:		info about VIN instance
+  *
+  * @vdev:		V4L2 video device associated with VIN
+  * @v4l2_dev:		V4L2 device
+@@ -119,7 +127,7 @@ struct rvin_graph_entity {
+ struct rvin_dev {
+ 	struct device *dev;
+ 	void __iomem *base;
+-	enum chip_id chip;
++	const struct rvin_info *info;
+ 
+ 	struct video_device vdev;
+ 	struct v4l2_device v4l2_dev;
+-- 
+2.19.0
+
diff --git a/patches/1287-media-rcar-vin-move-max-width-and-height-information.patch b/patches/1287-media-rcar-vin-move-max-width-and-height-information.patch
new file mode 100644
index 00000000000000..fdda205bc4d347
--- /dev/null
+++ b/patches/1287-media-rcar-vin-move-max-width-and-height-information.patch
@@ -0,0 +1,98 @@
+From 00f700ba2f7770c2a3a860bed2e4424ab208b01a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:01 -0400
+Subject: [PATCH 1287/1795] media: rcar-vin: move max width and height
+ information to chip information
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On Gen3 the max supported width and height will be different from Gen2.
+Move the limits to the struct rvin_info to prepare for Gen3 support.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 16cdb7d30ab8dda8155769269ccc102636413484)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 6 ++++++
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 6 ++----
+ drivers/media/platform/rcar-vin/rcar-vin.h  | 5 +++++
+ 3 files changed, 13 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index e65ede0a6cd1..b7cce37d78b8 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -243,14 +243,20 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 
+ static const struct rvin_info rcar_info_h1 = {
+ 	.model = RCAR_H1,
++	.max_width = 2048,
++	.max_height = 2048,
+ };
+ 
+ static const struct rvin_info rcar_info_m1 = {
+ 	.model = RCAR_M1,
++	.max_width = 2048,
++	.max_height = 2048,
+ };
+ 
+ static const struct rvin_info rcar_info_gen2 = {
+ 	.model = RCAR_GEN2,
++	.max_width = 2048,
++	.max_height = 2048,
+ };
+ 
+ static const struct of_device_id rvin_of_id_table[] = {
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 97baea8fb7e6..5af58e2787f8 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -23,8 +23,6 @@
+ #include "rcar-vin.h"
+ 
+ #define RVIN_DEFAULT_FORMAT	V4L2_PIX_FMT_YUYV
+-#define RVIN_MAX_WIDTH		2048
+-#define RVIN_MAX_HEIGHT		2048
+ 
+ /* -----------------------------------------------------------------------------
+  * Format Conversions
+@@ -258,8 +256,8 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	walign = vin->format.pixelformat == V4L2_PIX_FMT_NV16 ? 5 : 1;
+ 
+ 	/* Limit to VIN capabilities */
+-	v4l_bound_align_image(&pix->width, 2, RVIN_MAX_WIDTH, walign,
+-			      &pix->height, 4, RVIN_MAX_HEIGHT, 2, 0);
++	v4l_bound_align_image(&pix->width, 2, vin->info->max_width, walign,
++			      &pix->height, 4, vin->info->max_height, 2, 0);
+ 
+ 	pix->bytesperline = max_t(u32, pix->bytesperline,
+ 				  rvin_format_bytesperline(pix));
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index b63c4fce68ad..8d135ed3f7ab 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -89,9 +89,14 @@ struct rvin_graph_entity {
+ /**
+  * struct rvin_info - Information about the particular VIN implementation
+  * @model:		VIN model
++ * @max_width:		max input width the VIN supports
++ * @max_height:		max input height the VIN supports
+  */
+ struct rvin_info {
+ 	enum model_id model;
++
++	unsigned int max_width;
++	unsigned int max_height;
+ };
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1288-media-rcar-vin-move-functions-regarding-scaling.patch b/patches/1288-media-rcar-vin-move-functions-regarding-scaling.patch
new file mode 100644
index 00000000000000..321f01ade3af6b
--- /dev/null
+++ b/patches/1288-media-rcar-vin-move-functions-regarding-scaling.patch
@@ -0,0 +1,793 @@
+From b4621d5af324ee9aeaaf6a8f0a439018ee64d56b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:02 -0400
+Subject: [PATCH 1288/1795] media: rcar-vin: move functions regarding scaling
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In preparation of refactoring the scaling code move the code regarding
+scaling to to the top of the file to avoid the need to add forward
+declarations. No code is changed in this commit only whole functions
+moved inside the same file.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 0f4b33783389c7daaa67f9b0b7164a51fabe3644)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 718 +++++++++++----------
+ 1 file changed, 361 insertions(+), 357 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 2aae3ca54eab..23120901b0a0 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -138,267 +138,6 @@ static u32 rvin_read(struct rvin_dev *vin, u32 offset)
+ 	return ioread32(vin->base + offset);
+ }
+ 
+-static int rvin_setup(struct rvin_dev *vin)
+-{
+-	u32 vnmc, dmr, dmr2, interrupts;
+-	v4l2_std_id std;
+-	bool progressive = false, output_is_yuv = false, input_is_yuv = false;
+-
+-	switch (vin->format.field) {
+-	case V4L2_FIELD_TOP:
+-		vnmc = VNMC_IM_ODD;
+-		break;
+-	case V4L2_FIELD_BOTTOM:
+-		vnmc = VNMC_IM_EVEN;
+-		break;
+-	case V4L2_FIELD_INTERLACED:
+-		/* Default to TB */
+-		vnmc = VNMC_IM_FULL;
+-		/* Use BT if video standard can be read and is 60 Hz format */
+-		if (!v4l2_subdev_call(vin_to_source(vin), video, g_std, &std)) {
+-			if (std & V4L2_STD_525_60)
+-				vnmc = VNMC_IM_FULL | VNMC_FOC;
+-		}
+-		break;
+-	case V4L2_FIELD_INTERLACED_TB:
+-		vnmc = VNMC_IM_FULL;
+-		break;
+-	case V4L2_FIELD_INTERLACED_BT:
+-		vnmc = VNMC_IM_FULL | VNMC_FOC;
+-		break;
+-	case V4L2_FIELD_ALTERNATE:
+-	case V4L2_FIELD_NONE:
+-		vnmc = VNMC_IM_ODD_EVEN;
+-		progressive = true;
+-		break;
+-	default:
+-		vnmc = VNMC_IM_ODD;
+-		break;
+-	}
+-
+-	/*
+-	 * Input interface
+-	 */
+-	switch (vin->digital->code) {
+-	case MEDIA_BUS_FMT_YUYV8_1X16:
+-		/* BT.601/BT.1358 16bit YCbCr422 */
+-		vnmc |= VNMC_INF_YUV16;
+-		input_is_yuv = true;
+-		break;
+-	case MEDIA_BUS_FMT_UYVY8_2X8:
+-		/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
+-		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
+-			VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601;
+-		input_is_yuv = true;
+-		break;
+-	case MEDIA_BUS_FMT_RGB888_1X24:
+-		vnmc |= VNMC_INF_RGB888;
+-		break;
+-	case MEDIA_BUS_FMT_UYVY10_2X10:
+-		/* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
+-		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
+-			VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601;
+-		input_is_yuv = true;
+-		break;
+-	default:
+-		break;
+-	}
+-
+-	/* Enable VSYNC Field Toogle mode after one VSYNC input */
+-	dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
+-
+-	/* Hsync Signal Polarity Select */
+-	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+-		dmr2 |= VNDMR2_HPS;
+-
+-	/* Vsync Signal Polarity Select */
+-	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
+-		dmr2 |= VNDMR2_VPS;
+-
+-	/*
+-	 * Output format
+-	 */
+-	switch (vin->format.pixelformat) {
+-	case V4L2_PIX_FMT_NV16:
+-		rvin_write(vin,
+-			   ALIGN(vin->format.width * vin->format.height, 0x80),
+-			   VNUVAOF_REG);
+-		dmr = VNDMR_DTMD_YCSEP;
+-		output_is_yuv = true;
+-		break;
+-	case V4L2_PIX_FMT_YUYV:
+-		dmr = VNDMR_BPSM;
+-		output_is_yuv = true;
+-		break;
+-	case V4L2_PIX_FMT_UYVY:
+-		dmr = 0;
+-		output_is_yuv = true;
+-		break;
+-	case V4L2_PIX_FMT_XRGB555:
+-		dmr = VNDMR_DTMD_ARGB1555;
+-		break;
+-	case V4L2_PIX_FMT_RGB565:
+-		dmr = 0;
+-		break;
+-	case V4L2_PIX_FMT_XBGR32:
+-		/* Note: not supported on M1 */
+-		dmr = VNDMR_EXRGB;
+-		break;
+-	default:
+-		vin_err(vin, "Invalid pixelformat (0x%x)\n",
+-			vin->format.pixelformat);
+-		return -EINVAL;
+-	}
+-
+-	/* Always update on field change */
+-	vnmc |= VNMC_VUP;
+-
+-	/* If input and output use the same colorspace, use bypass mode */
+-	if (input_is_yuv == output_is_yuv)
+-		vnmc |= VNMC_BPS;
+-
+-	/* Progressive or interlaced mode */
+-	interrupts = progressive ? VNIE_FIE : VNIE_EFE;
+-
+-	/* Ack interrupts */
+-	rvin_write(vin, interrupts, VNINTS_REG);
+-	/* Enable interrupts */
+-	rvin_write(vin, interrupts, VNIE_REG);
+-	/* Start capturing */
+-	rvin_write(vin, dmr, VNDMR_REG);
+-	rvin_write(vin, dmr2, VNDMR2_REG);
+-
+-	/* Enable module */
+-	rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
+-
+-	return 0;
+-}
+-
+-static void rvin_disable_interrupts(struct rvin_dev *vin)
+-{
+-	rvin_write(vin, 0, VNIE_REG);
+-}
+-
+-static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
+-{
+-	return rvin_read(vin, VNINTS_REG);
+-}
+-
+-static void rvin_ack_interrupt(struct rvin_dev *vin)
+-{
+-	rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
+-}
+-
+-static bool rvin_capture_active(struct rvin_dev *vin)
+-{
+-	return rvin_read(vin, VNMS_REG) & VNMS_CA;
+-}
+-
+-static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
+-{
+-	if (vin->format.field == V4L2_FIELD_ALTERNATE) {
+-		/* If FS is set it's a Even field */
+-		if (vnms & VNMS_FS)
+-			return V4L2_FIELD_BOTTOM;
+-		return V4L2_FIELD_TOP;
+-	}
+-
+-	return vin->format.field;
+-}
+-
+-static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
+-{
+-	const struct rvin_video_format *fmt;
+-	int offsetx, offsety;
+-	dma_addr_t offset;
+-
+-	fmt = rvin_format_from_pixel(vin->format.pixelformat);
+-
+-	/*
+-	 * There is no HW support for composition do the beast we can
+-	 * by modifying the buffer offset
+-	 */
+-	offsetx = vin->compose.left * fmt->bpp;
+-	offsety = vin->compose.top * vin->format.bytesperline;
+-	offset = addr + offsetx + offsety;
+-
+-	/*
+-	 * The address needs to be 128 bytes aligned. Driver should never accept
+-	 * settings that do not satisfy this in the first place...
+-	 */
+-	if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
+-		return;
+-
+-	rvin_write(vin, offset, VNMB_REG(slot));
+-}
+-
+-/*
+- * Moves a buffer from the queue to the HW slot. If no buffer is
+- * available use the scratch buffer. The scratch buffer is never
+- * returned to userspace, its only function is to enable the capture
+- * loop to keep running.
+- */
+-static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
+-{
+-	struct rvin_buffer *buf;
+-	struct vb2_v4l2_buffer *vbuf;
+-	dma_addr_t phys_addr;
+-
+-	/* A already populated slot shall never be overwritten. */
+-	if (WARN_ON(vin->queue_buf[slot] != NULL))
+-		return;
+-
+-	vin_dbg(vin, "Filling HW slot: %d\n", slot);
+-
+-	if (list_empty(&vin->buf_list)) {
+-		vin->queue_buf[slot] = NULL;
+-		phys_addr = vin->scratch_phys;
+-	} else {
+-		/* Keep track of buffer we give to HW */
+-		buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
+-		vbuf = &buf->vb;
+-		list_del_init(to_buf_list(vbuf));
+-		vin->queue_buf[slot] = vbuf;
+-
+-		/* Setup DMA */
+-		phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
+-	}
+-
+-	rvin_set_slot_addr(vin, slot, phys_addr);
+-}
+-
+-static int rvin_capture_start(struct rvin_dev *vin)
+-{
+-	int slot, ret;
+-
+-	for (slot = 0; slot < HW_BUFFER_NUM; slot++)
+-		rvin_fill_hw_slot(vin, slot);
+-
+-	rvin_crop_scale_comp(vin);
+-
+-	ret = rvin_setup(vin);
+-	if (ret)
+-		return ret;
+-
+-	vin_dbg(vin, "Starting to capture\n");
+-
+-	/* Continuous Frame Capture Mode */
+-	rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
+-
+-	vin->state = RUNNING;
+-
+-	return 0;
+-}
+-
+-static void rvin_capture_stop(struct rvin_dev *vin)
+-{
+-	/* Set continuous & single transfer off */
+-	rvin_write(vin, 0, VNFC_REG);
+-
+-	/* Disable module */
+-	rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
+-}
+-
+ /* -----------------------------------------------------------------------------
+  * Crop and Scaling Gen2
+  */
+@@ -727,131 +466,396 @@ static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
+ 	const struct vin_coeff *p_prev_set = NULL;
+ 	const struct vin_coeff *p_set = NULL;
+ 
+-	/* Look for suitable coefficient values */
+-	for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
+-		p_prev_set = p_set;
+-		p_set = &vin_coeff_set[i];
++	/* Look for suitable coefficient values */
++	for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
++		p_prev_set = p_set;
++		p_set = &vin_coeff_set[i];
++
++		if (xs < p_set->xs_value)
++			break;
++	}
++
++	/* Use previous value if its XS value is closer */
++	if (p_prev_set && p_set &&
++	    xs - p_prev_set->xs_value < p_set->xs_value - xs)
++		p_set = p_prev_set;
++
++	/* Set coefficient registers */
++	rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
++	rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
++	rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
++
++	rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
++	rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
++	rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
++
++	rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
++	rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
++	rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
++
++	rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
++	rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
++	rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
++
++	rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
++	rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
++	rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
++
++	rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
++	rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
++	rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
++
++	rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
++	rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
++	rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
++
++	rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
++	rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
++	rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
++}
++
++void rvin_crop_scale_comp(struct rvin_dev *vin)
++{
++	u32 xs, ys;
++
++	/* Set Start/End Pixel/Line Pre-Clip */
++	rvin_write(vin, vin->crop.left, VNSPPRC_REG);
++	rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
++	switch (vin->format.field) {
++	case V4L2_FIELD_INTERLACED:
++	case V4L2_FIELD_INTERLACED_TB:
++	case V4L2_FIELD_INTERLACED_BT:
++		rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
++		rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
++			   VNELPRC_REG);
++		break;
++	default:
++		rvin_write(vin, vin->crop.top, VNSLPRC_REG);
++		rvin_write(vin, vin->crop.top + vin->crop.height - 1,
++			   VNELPRC_REG);
++		break;
++	}
++
++	/* Set scaling coefficient */
++	ys = 0;
++	if (vin->crop.height != vin->compose.height)
++		ys = (4096 * vin->crop.height) / vin->compose.height;
++	rvin_write(vin, ys, VNYS_REG);
++
++	xs = 0;
++	if (vin->crop.width != vin->compose.width)
++		xs = (4096 * vin->crop.width) / vin->compose.width;
++
++	/* Horizontal upscaling is up to double size */
++	if (xs > 0 && xs < 2048)
++		xs = 2048;
++
++	rvin_write(vin, xs, VNXS_REG);
++
++	/* Horizontal upscaling is done out by scaling down from double size */
++	if (xs < 4096)
++		xs *= 2;
++
++	rvin_set_coeff(vin, xs);
++
++	/* Set Start/End Pixel/Line Post-Clip */
++	rvin_write(vin, 0, VNSPPOC_REG);
++	rvin_write(vin, 0, VNSLPOC_REG);
++	rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
++	switch (vin->format.field) {
++	case V4L2_FIELD_INTERLACED:
++	case V4L2_FIELD_INTERLACED_TB:
++	case V4L2_FIELD_INTERLACED_BT:
++		rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
++		break;
++	default:
++		rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
++		break;
++	}
++
++	if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
++		rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
++	else
++		rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
++
++	vin_dbg(vin,
++		"Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
++		vin->crop.width, vin->crop.height, vin->crop.left,
++		vin->crop.top, ys, xs, vin->format.width, vin->format.height,
++		0, 0);
++}
++
++void rvin_scale_try(struct rvin_dev *vin, struct v4l2_pix_format *pix,
++		    u32 width, u32 height)
++{
++	/* All VIN channels on Gen2 have scalers */
++	pix->width = width;
++	pix->height = height;
++}
++
++/* -----------------------------------------------------------------------------
++ * Hardware setup
++ */
++
++static int rvin_setup(struct rvin_dev *vin)
++{
++	u32 vnmc, dmr, dmr2, interrupts;
++	v4l2_std_id std;
++	bool progressive = false, output_is_yuv = false, input_is_yuv = false;
++
++	switch (vin->format.field) {
++	case V4L2_FIELD_TOP:
++		vnmc = VNMC_IM_ODD;
++		break;
++	case V4L2_FIELD_BOTTOM:
++		vnmc = VNMC_IM_EVEN;
++		break;
++	case V4L2_FIELD_INTERLACED:
++		/* Default to TB */
++		vnmc = VNMC_IM_FULL;
++		/* Use BT if video standard can be read and is 60 Hz format */
++		if (!v4l2_subdev_call(vin_to_source(vin), video, g_std, &std)) {
++			if (std & V4L2_STD_525_60)
++				vnmc = VNMC_IM_FULL | VNMC_FOC;
++		}
++		break;
++	case V4L2_FIELD_INTERLACED_TB:
++		vnmc = VNMC_IM_FULL;
++		break;
++	case V4L2_FIELD_INTERLACED_BT:
++		vnmc = VNMC_IM_FULL | VNMC_FOC;
++		break;
++	case V4L2_FIELD_ALTERNATE:
++	case V4L2_FIELD_NONE:
++		vnmc = VNMC_IM_ODD_EVEN;
++		progressive = true;
++		break;
++	default:
++		vnmc = VNMC_IM_ODD;
++		break;
++	}
++
++	/*
++	 * Input interface
++	 */
++	switch (vin->digital->code) {
++	case MEDIA_BUS_FMT_YUYV8_1X16:
++		/* BT.601/BT.1358 16bit YCbCr422 */
++		vnmc |= VNMC_INF_YUV16;
++		input_is_yuv = true;
++		break;
++	case MEDIA_BUS_FMT_UYVY8_2X8:
++		/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
++		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
++			VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601;
++		input_is_yuv = true;
++		break;
++	case MEDIA_BUS_FMT_RGB888_1X24:
++		vnmc |= VNMC_INF_RGB888;
++		break;
++	case MEDIA_BUS_FMT_UYVY10_2X10:
++		/* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
++		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
++			VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601;
++		input_is_yuv = true;
++		break;
++	default:
++		break;
++	}
++
++	/* Enable VSYNC Field Toogle mode after one VSYNC input */
++	dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
++
++	/* Hsync Signal Polarity Select */
++	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
++		dmr2 |= VNDMR2_HPS;
++
++	/* Vsync Signal Polarity Select */
++	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
++		dmr2 |= VNDMR2_VPS;
+ 
+-		if (xs < p_set->xs_value)
+-			break;
++	/*
++	 * Output format
++	 */
++	switch (vin->format.pixelformat) {
++	case V4L2_PIX_FMT_NV16:
++		rvin_write(vin,
++			   ALIGN(vin->format.width * vin->format.height, 0x80),
++			   VNUVAOF_REG);
++		dmr = VNDMR_DTMD_YCSEP;
++		output_is_yuv = true;
++		break;
++	case V4L2_PIX_FMT_YUYV:
++		dmr = VNDMR_BPSM;
++		output_is_yuv = true;
++		break;
++	case V4L2_PIX_FMT_UYVY:
++		dmr = 0;
++		output_is_yuv = true;
++		break;
++	case V4L2_PIX_FMT_XRGB555:
++		dmr = VNDMR_DTMD_ARGB1555;
++		break;
++	case V4L2_PIX_FMT_RGB565:
++		dmr = 0;
++		break;
++	case V4L2_PIX_FMT_XBGR32:
++		/* Note: not supported on M1 */
++		dmr = VNDMR_EXRGB;
++		break;
++	default:
++		vin_err(vin, "Invalid pixelformat (0x%x)\n",
++			vin->format.pixelformat);
++		return -EINVAL;
+ 	}
+ 
+-	/* Use previous value if its XS value is closer */
+-	if (p_prev_set && p_set &&
+-	    xs - p_prev_set->xs_value < p_set->xs_value - xs)
+-		p_set = p_prev_set;
++	/* Always update on field change */
++	vnmc |= VNMC_VUP;
+ 
+-	/* Set coefficient registers */
+-	rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
+-	rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
+-	rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
++	/* If input and output use the same colorspace, use bypass mode */
++	if (input_is_yuv == output_is_yuv)
++		vnmc |= VNMC_BPS;
+ 
+-	rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
+-	rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
+-	rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
++	/* Progressive or interlaced mode */
++	interrupts = progressive ? VNIE_FIE : VNIE_EFE;
+ 
+-	rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
+-	rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
+-	rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
++	/* Ack interrupts */
++	rvin_write(vin, interrupts, VNINTS_REG);
++	/* Enable interrupts */
++	rvin_write(vin, interrupts, VNIE_REG);
++	/* Start capturing */
++	rvin_write(vin, dmr, VNDMR_REG);
++	rvin_write(vin, dmr2, VNDMR2_REG);
+ 
+-	rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
+-	rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
+-	rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
++	/* Enable module */
++	rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
+ 
+-	rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
+-	rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
+-	rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
++	return 0;
++}
+ 
+-	rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
+-	rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
+-	rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
++static void rvin_disable_interrupts(struct rvin_dev *vin)
++{
++	rvin_write(vin, 0, VNIE_REG);
++}
+ 
+-	rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
+-	rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
+-	rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
++static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
++{
++	return rvin_read(vin, VNINTS_REG);
++}
+ 
+-	rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
+-	rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
+-	rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
++static void rvin_ack_interrupt(struct rvin_dev *vin)
++{
++	rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
+ }
+ 
+-void rvin_crop_scale_comp(struct rvin_dev *vin)
++static bool rvin_capture_active(struct rvin_dev *vin)
+ {
+-	u32 xs, ys;
++	return rvin_read(vin, VNMS_REG) & VNMS_CA;
++}
+ 
+-	/* Set Start/End Pixel/Line Pre-Clip */
+-	rvin_write(vin, vin->crop.left, VNSPPRC_REG);
+-	rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
+-	switch (vin->format.field) {
+-	case V4L2_FIELD_INTERLACED:
+-	case V4L2_FIELD_INTERLACED_TB:
+-	case V4L2_FIELD_INTERLACED_BT:
+-		rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
+-		rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
+-			   VNELPRC_REG);
+-		break;
+-	default:
+-		rvin_write(vin, vin->crop.top, VNSLPRC_REG);
+-		rvin_write(vin, vin->crop.top + vin->crop.height - 1,
+-			   VNELPRC_REG);
+-		break;
++static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
++{
++	if (vin->format.field == V4L2_FIELD_ALTERNATE) {
++		/* If FS is set it's a Even field */
++		if (vnms & VNMS_FS)
++			return V4L2_FIELD_BOTTOM;
++		return V4L2_FIELD_TOP;
+ 	}
+ 
+-	/* Set scaling coefficient */
+-	ys = 0;
+-	if (vin->crop.height != vin->compose.height)
+-		ys = (4096 * vin->crop.height) / vin->compose.height;
+-	rvin_write(vin, ys, VNYS_REG);
++	return vin->format.field;
++}
+ 
+-	xs = 0;
+-	if (vin->crop.width != vin->compose.width)
+-		xs = (4096 * vin->crop.width) / vin->compose.width;
++static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
++{
++	const struct rvin_video_format *fmt;
++	int offsetx, offsety;
++	dma_addr_t offset;
+ 
+-	/* Horizontal upscaling is up to double size */
+-	if (xs > 0 && xs < 2048)
+-		xs = 2048;
++	fmt = rvin_format_from_pixel(vin->format.pixelformat);
+ 
+-	rvin_write(vin, xs, VNXS_REG);
++	/*
++	 * There is no HW support for composition do the beast we can
++	 * by modifying the buffer offset
++	 */
++	offsetx = vin->compose.left * fmt->bpp;
++	offsety = vin->compose.top * vin->format.bytesperline;
++	offset = addr + offsetx + offsety;
+ 
+-	/* Horizontal upscaling is done out by scaling down from double size */
+-	if (xs < 4096)
+-		xs *= 2;
++	/*
++	 * The address needs to be 128 bytes aligned. Driver should never accept
++	 * settings that do not satisfy this in the first place...
++	 */
++	if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
++		return;
+ 
+-	rvin_set_coeff(vin, xs);
++	rvin_write(vin, offset, VNMB_REG(slot));
++}
+ 
+-	/* Set Start/End Pixel/Line Post-Clip */
+-	rvin_write(vin, 0, VNSPPOC_REG);
+-	rvin_write(vin, 0, VNSLPOC_REG);
+-	rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
+-	switch (vin->format.field) {
+-	case V4L2_FIELD_INTERLACED:
+-	case V4L2_FIELD_INTERLACED_TB:
+-	case V4L2_FIELD_INTERLACED_BT:
+-		rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
+-		break;
+-	default:
+-		rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
+-		break;
++/*
++ * Moves a buffer from the queue to the HW slot. If no buffer is
++ * available use the scratch buffer. The scratch buffer is never
++ * returned to userspace, its only function is to enable the capture
++ * loop to keep running.
++ */
++static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
++{
++	struct rvin_buffer *buf;
++	struct vb2_v4l2_buffer *vbuf;
++	dma_addr_t phys_addr;
++
++	/* A already populated slot shall never be overwritten. */
++	if (WARN_ON(vin->queue_buf[slot] != NULL))
++		return;
++
++	vin_dbg(vin, "Filling HW slot: %d\n", slot);
++
++	if (list_empty(&vin->buf_list)) {
++		vin->queue_buf[slot] = NULL;
++		phys_addr = vin->scratch_phys;
++	} else {
++		/* Keep track of buffer we give to HW */
++		buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
++		vbuf = &buf->vb;
++		list_del_init(to_buf_list(vbuf));
++		vin->queue_buf[slot] = vbuf;
++
++		/* Setup DMA */
++		phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
+ 	}
+ 
+-	if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
+-		rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
+-	else
+-		rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
++	rvin_set_slot_addr(vin, slot, phys_addr);
++}
+ 
+-	vin_dbg(vin,
+-		"Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
+-		vin->crop.width, vin->crop.height, vin->crop.left,
+-		vin->crop.top, ys, xs, vin->format.width, vin->format.height,
+-		0, 0);
++static int rvin_capture_start(struct rvin_dev *vin)
++{
++	int slot, ret;
++
++	for (slot = 0; slot < HW_BUFFER_NUM; slot++)
++		rvin_fill_hw_slot(vin, slot);
++
++	rvin_crop_scale_comp(vin);
++
++	ret = rvin_setup(vin);
++	if (ret)
++		return ret;
++
++	vin_dbg(vin, "Starting to capture\n");
++
++	/* Continuous Frame Capture Mode */
++	rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
++
++	vin->state = RUNNING;
++
++	return 0;
+ }
+ 
+-void rvin_scale_try(struct rvin_dev *vin, struct v4l2_pix_format *pix,
+-		    u32 width, u32 height)
++static void rvin_capture_stop(struct rvin_dev *vin)
+ {
+-	/* All VIN channels on Gen2 have scalers */
+-	pix->width = width;
+-	pix->height = height;
++	/* Set continuous & single transfer off */
++	rvin_write(vin, 0, VNFC_REG);
++
++	/* Disable module */
++	rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+-- 
+2.19.0
+
diff --git a/patches/1289-media-rcar-vin-all-Gen2-boards-can-scale-simplify-lo.patch b/patches/1289-media-rcar-vin-all-Gen2-boards-can-scale-simplify-lo.patch
new file mode 100644
index 00000000000000..f02d3eb129a582
--- /dev/null
+++ b/patches/1289-media-rcar-vin-all-Gen2-boards-can-scale-simplify-lo.patch
@@ -0,0 +1,142 @@
+From acaba5798a5c5bbcbcac53ce5b83273f39bad55b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:03 -0400
+Subject: [PATCH 1289/1795] media: rcar-vin: all Gen2 boards can scale simplify
+ logic
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The logic to preserve the requested format width and height are too
+complex and come from a premature optimization for Gen3. All Gen2 SoC
+can scale and the Gen3 implementation will not use these functions at
+all so simply preserve the width and height when interacting with the
+subdevice much like the field is preserved simplifies the logic quite a
+bit.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit d1dc6bacefb9729089025555930a04f69498c121)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c  |  8 -------
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 25 +++++++++------------
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  2 --
+ 3 files changed, 11 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 23120901b0a0..4f48575f2008 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -585,14 +585,6 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ 		0, 0);
+ }
+ 
+-void rvin_scale_try(struct rvin_dev *vin, struct v4l2_pix_format *pix,
+-		    u32 width, u32 height)
+-{
+-	/* All VIN channels on Gen2 have scalers */
+-	pix->width = width;
+-	pix->height = height;
+-}
+-
+ /* -----------------------------------------------------------------------------
+  * Hardware setup
+  */
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 5af58e2787f8..4ef440049896 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -166,6 +166,7 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 		.which = which,
+ 	};
+ 	enum v4l2_field field;
++	u32 width, height;
+ 	int ret;
+ 
+ 	sd = vin_to_source(vin);
+@@ -178,7 +179,10 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 
+ 	format.pad = vin->digital->source_pad;
+ 
++	/* Allow the video device to override field and to scale */
+ 	field = pix->field;
++	width = pix->width;
++	height = pix->height;
+ 
+ 	ret = v4l2_subdev_call(sd, pad, set_fmt, pad_cfg, &format);
+ 	if (ret < 0 && ret != -ENOIOCTLCMD)
+@@ -186,11 +190,13 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 
+ 	v4l2_fill_pix_format(pix, &format.format);
+ 
+-	pix->field = field;
+-
+ 	source->width = pix->width;
+ 	source->height = pix->height;
+ 
++	pix->field = field;
++	pix->width = width;
++	pix->height = height;
++
+ 	vin_dbg(vin, "Source resolution: %ux%u\n", source->width,
+ 		source->height);
+ 
+@@ -204,13 +210,9 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 			     struct v4l2_pix_format *pix,
+ 			     struct rvin_source_fmt *source)
+ {
+-	u32 rwidth, rheight, walign;
++	u32 walign;
+ 	int ret;
+ 
+-	/* Requested */
+-	rwidth = pix->width;
+-	rheight = pix->height;
+-
+ 	/* Keep current field if no specific one is asked for */
+ 	if (pix->field == V4L2_FIELD_ANY)
+ 		pix->field = vin->format.field;
+@@ -248,10 +250,6 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 		break;
+ 	}
+ 
+-	/* If source can't match format try if VIN can scale */
+-	if (source->width != rwidth || source->height != rheight)
+-		rvin_scale_try(vin, pix, rwidth, rheight);
+-
+ 	/* HW limit width to a multiple of 32 (2^5) for NV16 else 2 (2^1) */
+ 	walign = vin->format.pixelformat == V4L2_PIX_FMT_NV16 ? 5 : 1;
+ 
+@@ -270,9 +268,8 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 		return -EINVAL;
+ 	}
+ 
+-	vin_dbg(vin, "Requested %ux%u Got %ux%u bpl: %d size: %d\n",
+-		rwidth, rheight, pix->width, pix->height,
+-		pix->bytesperline, pix->sizeimage);
++	vin_dbg(vin, "Format %ux%u bpl: %d size: %d\n",
++		pix->width, pix->height, pix->bytesperline, pix->sizeimage);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 8d135ed3f7ab..1c91b774205a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -175,8 +175,6 @@ void rvin_v4l2_unregister(struct rvin_dev *vin);
+ const struct rvin_video_format *rvin_format_from_pixel(u32 pixelformat);
+ 
+ /* Cropping, composing and scaling */
+-void rvin_scale_try(struct rvin_dev *vin, struct v4l2_pix_format *pix,
+-		    u32 width, u32 height);
+ void rvin_crop_scale_comp(struct rvin_dev *vin);
+ 
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/1290-media-rcar-vin-set-a-default-field-to-fallback-on.patch b/patches/1290-media-rcar-vin-set-a-default-field-to-fallback-on.patch
new file mode 100644
index 00000000000000..41f3b6deb3065e
--- /dev/null
+++ b/patches/1290-media-rcar-vin-set-a-default-field-to-fallback-on.patch
@@ -0,0 +1,80 @@
+From f05554c823054088a20415d8e44faf6708c00cc4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:04 -0400
+Subject: [PATCH 1290/1795] media: rcar-vin: set a default field to fallback on
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If the field is not supported by the driver it should not try to keep
+the current field. Instead it should set it to a default fallback. Since
+trying a format should always result in the same state regardless of the
+current state of the device.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 2db44b3dac9fb572707a20c38a334824f3684c24)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 4ef440049896..59ee69441936 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -23,6 +23,7 @@
+ #include "rcar-vin.h"
+ 
+ #define RVIN_DEFAULT_FORMAT	V4L2_PIX_FMT_YUYV
++#define RVIN_DEFAULT_FIELD	V4L2_FIELD_NONE
+ 
+ /* -----------------------------------------------------------------------------
+  * Format Conversions
+@@ -143,7 +144,7 @@ static int rvin_reset_format(struct rvin_dev *vin)
+ 	case V4L2_FIELD_INTERLACED:
+ 		break;
+ 	default:
+-		vin->format.field = V4L2_FIELD_NONE;
++		vin->format.field = RVIN_DEFAULT_FIELD;
+ 		break;
+ 	}
+ 
+@@ -193,7 +194,9 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 	source->width = pix->width;
+ 	source->height = pix->height;
+ 
+-	pix->field = field;
++	if (field != V4L2_FIELD_ANY)
++		pix->field = field;
++
+ 	pix->width = width;
+ 	pix->height = height;
+ 
+@@ -213,10 +216,6 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	u32 walign;
+ 	int ret;
+ 
+-	/* Keep current field if no specific one is asked for */
+-	if (pix->field == V4L2_FIELD_ANY)
+-		pix->field = vin->format.field;
+-
+ 	/* If requested format is not supported fallback to the default */
+ 	if (!rvin_format_from_pixel(pix->pixelformat)) {
+ 		vin_dbg(vin, "Format 0x%x not found, using default 0x%x\n",
+@@ -246,7 +245,7 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	case V4L2_FIELD_INTERLACED:
+ 		break;
+ 	default:
+-		pix->field = V4L2_FIELD_NONE;
++		pix->field = RVIN_DEFAULT_FIELD;
+ 		break;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/1291-media-rcar-vin-fix-handling-of-single-field-frames-t.patch b/patches/1291-media-rcar-vin-fix-handling-of-single-field-frames-t.patch
new file mode 100644
index 00000000000000..1888b7492490c2
--- /dev/null
+++ b/patches/1291-media-rcar-vin-fix-handling-of-single-field-frames-t.patch
@@ -0,0 +1,148 @@
+From 64b7079142e5a1cbc50012b8b38192abdd64b5b4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:05 -0400
+Subject: [PATCH 1291/1795] media: rcar-vin: fix handling of single field
+ frames (top, bottom and alternate fields)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There was never proper support in the VIN driver to deliver ALTERNATING
+field format to user-space, remove this field option. The problem is
+that ALTERNATING field order requires the sequence numbers of buffers
+returned to userspace to reflect if fields were dropped or not,
+something which is not possible with the VIN drivers capture logic.
+
+The VIN driver can still capture from a video source which delivers
+frames in ALTERNATING field order, but needs to combine them using the
+VIN hardware into INTERLACED field order. Before this change if a source
+was delivering fields using ALTERNATE the driver would default to
+combining them using this hardware feature. Only if the user explicitly
+requested ALTERNATE field order would incorrect frames be delivered.
+
+The height should not be cut in half for the format for TOP or BOTTOM
+fields settings. This was a mistake and it was made visible by the
+scaling refactoring. Correct behavior is that the user should request a
+frame size that fits the half height frame reflected in the field
+setting. If not the VIN will do its best to scale the top or bottom to
+the requested format and cropping and scaling do not work as expected.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 6c51f646f6414f7123395bbaa0449c8b5d2614ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c  | 15 +-------
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 40 +++++----------------
+ 2 files changed, 10 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 4f48575f2008..9233924e5b52 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -617,7 +617,6 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	case V4L2_FIELD_INTERLACED_BT:
+ 		vnmc = VNMC_IM_FULL | VNMC_FOC;
+ 		break;
+-	case V4L2_FIELD_ALTERNATE:
+ 	case V4L2_FIELD_NONE:
+ 		vnmc = VNMC_IM_ODD_EVEN;
+ 		progressive = true;
+@@ -745,18 +744,6 @@ static bool rvin_capture_active(struct rvin_dev *vin)
+ 	return rvin_read(vin, VNMS_REG) & VNMS_CA;
+ }
+ 
+-static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
+-{
+-	if (vin->format.field == V4L2_FIELD_ALTERNATE) {
+-		/* If FS is set it's a Even field */
+-		if (vnms & VNMS_FS)
+-			return V4L2_FIELD_BOTTOM;
+-		return V4L2_FIELD_TOP;
+-	}
+-
+-	return vin->format.field;
+-}
+-
+ static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
+ {
+ 	const struct rvin_video_format *fmt;
+@@ -892,7 +879,7 @@ static irqreturn_t rvin_irq(int irq, void *data)
+ 
+ 	/* Capture frame */
+ 	if (vin->queue_buf[slot]) {
+-		vin->queue_buf[slot]->field = rvin_get_active_field(vin, vnms);
++		vin->queue_buf[slot]->field = vin->format.field;
+ 		vin->queue_buf[slot]->sequence = vin->sequence;
+ 		vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
+ 		vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf,
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 59ee69441936..ce50bc29b29a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -121,33 +121,6 @@ static int rvin_reset_format(struct rvin_dev *vin)
+ 	vin->format.colorspace	= mf->colorspace;
+ 	vin->format.field	= mf->field;
+ 
+-	/*
+-	 * If the subdevice uses ALTERNATE field mode and G_STD is
+-	 * implemented use the VIN HW to combine the two fields to
+-	 * one INTERLACED frame. The ALTERNATE field mode can still
+-	 * be requested in S_FMT and be respected, this is just the
+-	 * default which is applied at probing or when S_STD is called.
+-	 */
+-	if (vin->format.field == V4L2_FIELD_ALTERNATE &&
+-	    v4l2_subdev_has_op(vin_to_source(vin), video, g_std))
+-		vin->format.field = V4L2_FIELD_INTERLACED;
+-
+-	switch (vin->format.field) {
+-	case V4L2_FIELD_TOP:
+-	case V4L2_FIELD_BOTTOM:
+-	case V4L2_FIELD_ALTERNATE:
+-		vin->format.height /= 2;
+-		break;
+-	case V4L2_FIELD_NONE:
+-	case V4L2_FIELD_INTERLACED_TB:
+-	case V4L2_FIELD_INTERLACED_BT:
+-	case V4L2_FIELD_INTERLACED:
+-		break;
+-	default:
+-		vin->format.field = RVIN_DEFAULT_FIELD;
+-		break;
+-	}
+-
+ 	rvin_reset_crop_compose(vin);
+ 
+ 	vin->format.bytesperline = rvin_format_bytesperline(&vin->format);
+@@ -235,15 +208,20 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	switch (pix->field) {
+ 	case V4L2_FIELD_TOP:
+ 	case V4L2_FIELD_BOTTOM:
+-	case V4L2_FIELD_ALTERNATE:
+-		pix->height /= 2;
+-		source->height /= 2;
+-		break;
+ 	case V4L2_FIELD_NONE:
+ 	case V4L2_FIELD_INTERLACED_TB:
+ 	case V4L2_FIELD_INTERLACED_BT:
+ 	case V4L2_FIELD_INTERLACED:
+ 		break;
++	case V4L2_FIELD_ALTERNATE:
++		/*
++		 * Driver does not (yet) support outputting ALTERNATE to a
++		 * userspace. It does support outputting INTERLACED so use
++		 * the VIN hardware to combine the two fields.
++		 */
++		pix->field = V4L2_FIELD_INTERLACED;
++		pix->height *= 2;
++		break;
+ 	default:
+ 		pix->field = RVIN_DEFAULT_FIELD;
+ 		break;
+-- 
+2.19.0
+
diff --git a/patches/1292-media-rcar-vin-update-bytesperline-and-sizeimage-cal.patch b/patches/1292-media-rcar-vin-update-bytesperline-and-sizeimage-cal.patch
new file mode 100644
index 00000000000000..9a7f68742447cb
--- /dev/null
+++ b/patches/1292-media-rcar-vin-update-bytesperline-and-sizeimage-cal.patch
@@ -0,0 +1,57 @@
+From 45d0ade51d7e230a1cd057e34bf7c2b0327a1aaa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:06 -0400
+Subject: [PATCH 1292/1795] media: rcar-vin: update bytesperline and sizeimage
+ calculation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove over complicated logic to calculate the value for bytesperline
+and sizeimage that was carried over from the soc_camera port. There is
+no need to find the max value of bytesperline and sizeimage from
+user-space as they are set to 0 before the max_t() operation.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 9f324784a6eb5f34b66da66c1d1eca340e7a045f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 10 ++--------
+ 1 file changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index ce50bc29b29a..05dd5d9256b9 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -196,10 +196,6 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 		pix->pixelformat = RVIN_DEFAULT_FORMAT;
+ 	}
+ 
+-	/* Always recalculate */
+-	pix->bytesperline = 0;
+-	pix->sizeimage = 0;
+-
+ 	/* Limit to source capabilities */
+ 	ret = __rvin_try_format_source(vin, which, pix, source);
+ 	if (ret)
+@@ -234,10 +230,8 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	v4l_bound_align_image(&pix->width, 2, vin->info->max_width, walign,
+ 			      &pix->height, 4, vin->info->max_height, 2, 0);
+ 
+-	pix->bytesperline = max_t(u32, pix->bytesperline,
+-				  rvin_format_bytesperline(pix));
+-	pix->sizeimage = max_t(u32, pix->sizeimage,
+-			       rvin_format_sizeimage(pix));
++	pix->bytesperline = rvin_format_bytesperline(pix);
++	pix->sizeimage = rvin_format_sizeimage(pix);
+ 
+ 	if (vin->info->model == RCAR_M1 &&
+ 	    pix->pixelformat == V4L2_PIX_FMT_XBGR32) {
+-- 
+2.19.0
+
diff --git a/patches/1293-media-rcar-vin-align-pixelformat-check.patch b/patches/1293-media-rcar-vin-align-pixelformat-check.patch
new file mode 100644
index 00000000000000..63df49ba3557b0
--- /dev/null
+++ b/patches/1293-media-rcar-vin-align-pixelformat-check.patch
@@ -0,0 +1,60 @@
+From 78521754382d6a7ff6da770e1aa7a57f6099c371 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:07 -0400
+Subject: [PATCH 1293/1795] media: rcar-vin: align pixelformat check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If the pixelformat is not supported it should not fail but be set to
+something that works. While we are at it move the two different
+checks of the pixelformat to the same statement.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a28bda47d085b6af7c7803a652a62650a40d3669)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 14 +++-----------
+ 1 file changed, 3 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 05dd5d9256b9..cc08fcc73ab2 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -189,12 +189,10 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	u32 walign;
+ 	int ret;
+ 
+-	/* If requested format is not supported fallback to the default */
+-	if (!rvin_format_from_pixel(pix->pixelformat)) {
+-		vin_dbg(vin, "Format 0x%x not found, using default 0x%x\n",
+-			pix->pixelformat, RVIN_DEFAULT_FORMAT);
++	if (!rvin_format_from_pixel(pix->pixelformat) ||
++	    (vin->info->model == RCAR_M1 &&
++	     pix->pixelformat == V4L2_PIX_FMT_XBGR32))
+ 		pix->pixelformat = RVIN_DEFAULT_FORMAT;
+-	}
+ 
+ 	/* Limit to source capabilities */
+ 	ret = __rvin_try_format_source(vin, which, pix, source);
+@@ -233,12 +231,6 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	pix->bytesperline = rvin_format_bytesperline(pix);
+ 	pix->sizeimage = rvin_format_sizeimage(pix);
+ 
+-	if (vin->info->model == RCAR_M1 &&
+-	    pix->pixelformat == V4L2_PIX_FMT_XBGR32) {
+-		vin_err(vin, "pixel format XBGR32 not supported on M1\n");
+-		return -EINVAL;
+-	}
+-
+ 	vin_dbg(vin, "Format %ux%u bpl: %d size: %d\n",
+ 		pix->width, pix->height, pix->bytesperline, pix->sizeimage);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1294-media-rcar-vin-break-out-format-alignment-and-checki.patch b/patches/1294-media-rcar-vin-break-out-format-alignment-and-checki.patch
new file mode 100644
index 00000000000000..f824f6b3015b83
--- /dev/null
+++ b/patches/1294-media-rcar-vin-break-out-format-alignment-and-checki.patch
@@ -0,0 +1,137 @@
+From 9b067d5f643be17c342aceb76d344d17684b6a7c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:08 -0400
+Subject: [PATCH 1294/1795] media: rcar-vin: break out format alignment and
+ checking
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Part of the format alignment and checking can be shared with the Gen3
+format handling. Break that part out to a separate function.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit a0b6d712f53ace54d4db8fcb99bc09415efc72fc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 85 ++++++++++++---------
+ 1 file changed, 48 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index cc08fcc73ab2..4a77bb4bb7c6 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -87,6 +87,53 @@ static u32 rvin_format_sizeimage(struct v4l2_pix_format *pix)
+ 	return pix->bytesperline * pix->height;
+ }
+ 
++static int rvin_format_align(struct rvin_dev *vin, struct v4l2_pix_format *pix)
++{
++	u32 walign;
++
++	if (!rvin_format_from_pixel(pix->pixelformat) ||
++	    (vin->info->model == RCAR_M1 &&
++	     pix->pixelformat == V4L2_PIX_FMT_XBGR32))
++		pix->pixelformat = RVIN_DEFAULT_FORMAT;
++
++	switch (pix->field) {
++	case V4L2_FIELD_TOP:
++	case V4L2_FIELD_BOTTOM:
++	case V4L2_FIELD_NONE:
++	case V4L2_FIELD_INTERLACED_TB:
++	case V4L2_FIELD_INTERLACED_BT:
++	case V4L2_FIELD_INTERLACED:
++		break;
++	case V4L2_FIELD_ALTERNATE:
++		/*
++		 * Driver does not (yet) support outputting ALTERNATE to a
++		 * userspace. It does support outputting INTERLACED so use
++		 * the VIN hardware to combine the two fields.
++		 */
++		pix->field = V4L2_FIELD_INTERLACED;
++		pix->height *= 2;
++		break;
++	default:
++		pix->field = RVIN_DEFAULT_FIELD;
++		break;
++	}
++
++	/* HW limit width to a multiple of 32 (2^5) for NV16 else 2 (2^1) */
++	walign = vin->format.pixelformat == V4L2_PIX_FMT_NV16 ? 5 : 1;
++
++	/* Limit to VIN capabilities */
++	v4l_bound_align_image(&pix->width, 2, vin->info->max_width, walign,
++			      &pix->height, 4, vin->info->max_height, 2, 0);
++
++	pix->bytesperline = rvin_format_bytesperline(pix);
++	pix->sizeimage = rvin_format_sizeimage(pix);
++
++	vin_dbg(vin, "Format %ux%u bpl: %u size: %u\n",
++		pix->width, pix->height, pix->bytesperline, pix->sizeimage);
++
++	return 0;
++}
++
+ /* -----------------------------------------------------------------------------
+  * V4L2
+  */
+@@ -186,7 +233,6 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 			     struct v4l2_pix_format *pix,
+ 			     struct rvin_source_fmt *source)
+ {
+-	u32 walign;
+ 	int ret;
+ 
+ 	if (!rvin_format_from_pixel(pix->pixelformat) ||
+@@ -199,42 +245,7 @@ static int __rvin_try_format(struct rvin_dev *vin,
+ 	if (ret)
+ 		return ret;
+ 
+-	switch (pix->field) {
+-	case V4L2_FIELD_TOP:
+-	case V4L2_FIELD_BOTTOM:
+-	case V4L2_FIELD_NONE:
+-	case V4L2_FIELD_INTERLACED_TB:
+-	case V4L2_FIELD_INTERLACED_BT:
+-	case V4L2_FIELD_INTERLACED:
+-		break;
+-	case V4L2_FIELD_ALTERNATE:
+-		/*
+-		 * Driver does not (yet) support outputting ALTERNATE to a
+-		 * userspace. It does support outputting INTERLACED so use
+-		 * the VIN hardware to combine the two fields.
+-		 */
+-		pix->field = V4L2_FIELD_INTERLACED;
+-		pix->height *= 2;
+-		break;
+-	default:
+-		pix->field = RVIN_DEFAULT_FIELD;
+-		break;
+-	}
+-
+-	/* HW limit width to a multiple of 32 (2^5) for NV16 else 2 (2^1) */
+-	walign = vin->format.pixelformat == V4L2_PIX_FMT_NV16 ? 5 : 1;
+-
+-	/* Limit to VIN capabilities */
+-	v4l_bound_align_image(&pix->width, 2, vin->info->max_width, walign,
+-			      &pix->height, 4, vin->info->max_height, 2, 0);
+-
+-	pix->bytesperline = rvin_format_bytesperline(pix);
+-	pix->sizeimage = rvin_format_sizeimage(pix);
+-
+-	vin_dbg(vin, "Format %ux%u bpl: %d size: %d\n",
+-		pix->width, pix->height, pix->bytesperline, pix->sizeimage);
+-
+-	return 0;
++	return rvin_format_align(vin, pix);
+ }
+ 
+ static int rvin_querycap(struct file *file, void *priv,
+-- 
+2.19.0
+
diff --git a/patches/1295-media-rcar-vin-simplify-how-formats-are-set-and-rese.patch b/patches/1295-media-rcar-vin-simplify-how-formats-are-set-and-rese.patch
new file mode 100644
index 00000000000000..631a552fef9759
--- /dev/null
+++ b/patches/1295-media-rcar-vin-simplify-how-formats-are-set-and-rese.patch
@@ -0,0 +1,296 @@
+From e37e089434cfbe49a779c6d1ac05250bbdeb4903 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:09 -0400
+Subject: [PATCH 1295/1795] media: rcar-vin: simplify how formats are set and
+ reset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the recent cleanup of the format code to prepare for Gen3 it's
+possible to simplify the Gen2 format code path as well. Clean up the
+process by defining two functions to handle the set format and reset of
+format when the standard is changed.
+
+While at it replace the driver local struct rvin_source_fmt with a
+struct v4l2_rect as all it's used for is keep track of the source
+dimensions.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 897e371389e7751438bf59409cc7098b9599ce21)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 120 +++++++++-----------
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  14 +--
+ 2 files changed, 53 insertions(+), 81 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 4a77bb4bb7c6..84cad5d8c93a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -87,7 +87,7 @@ static u32 rvin_format_sizeimage(struct v4l2_pix_format *pix)
+ 	return pix->bytesperline * pix->height;
+ }
+ 
+-static int rvin_format_align(struct rvin_dev *vin, struct v4l2_pix_format *pix)
++static void rvin_format_align(struct rvin_dev *vin, struct v4l2_pix_format *pix)
+ {
+ 	u32 walign;
+ 
+@@ -130,75 +130,63 @@ static int rvin_format_align(struct rvin_dev *vin, struct v4l2_pix_format *pix)
+ 
+ 	vin_dbg(vin, "Format %ux%u bpl: %u size: %u\n",
+ 		pix->width, pix->height, pix->bytesperline, pix->sizeimage);
+-
+-	return 0;
+ }
+ 
+ /* -----------------------------------------------------------------------------
+  * V4L2
+  */
+ 
+-static void rvin_reset_crop_compose(struct rvin_dev *vin)
+-{
+-	vin->crop.top = vin->crop.left = 0;
+-	vin->crop.width = vin->source.width;
+-	vin->crop.height = vin->source.height;
+-
+-	vin->compose.top = vin->compose.left = 0;
+-	vin->compose.width = vin->format.width;
+-	vin->compose.height = vin->format.height;
+-}
+-
+ static int rvin_reset_format(struct rvin_dev *vin)
+ {
+ 	struct v4l2_subdev_format fmt = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.pad = vin->digital->source_pad,
+ 	};
+-	struct v4l2_mbus_framefmt *mf = &fmt.format;
+ 	int ret;
+ 
+-	fmt.pad = vin->digital->source_pad;
+-
+ 	ret = v4l2_subdev_call(vin_to_source(vin), pad, get_fmt, NULL, &fmt);
+ 	if (ret)
+ 		return ret;
+ 
+-	vin->format.width	= mf->width;
+-	vin->format.height	= mf->height;
+-	vin->format.colorspace	= mf->colorspace;
+-	vin->format.field	= mf->field;
++	v4l2_fill_pix_format(&vin->format, &fmt.format);
++
++	rvin_format_align(vin, &vin->format);
+ 
+-	rvin_reset_crop_compose(vin);
++	vin->source.top = 0;
++	vin->source.left = 0;
++	vin->source.width = vin->format.width;
++	vin->source.height = vin->format.height;
+ 
+-	vin->format.bytesperline = rvin_format_bytesperline(&vin->format);
+-	vin->format.sizeimage = rvin_format_sizeimage(&vin->format);
++	vin->crop = vin->source;
++	vin->compose = vin->source;
+ 
+ 	return 0;
+ }
+ 
+-static int __rvin_try_format_source(struct rvin_dev *vin,
+-				    u32 which,
+-				    struct v4l2_pix_format *pix,
+-				    struct rvin_source_fmt *source)
++static int rvin_try_format(struct rvin_dev *vin, u32 which,
++			   struct v4l2_pix_format *pix,
++			   struct v4l2_rect *crop, struct v4l2_rect *compose)
+ {
+-	struct v4l2_subdev *sd;
++	struct v4l2_subdev *sd = vin_to_source(vin);
+ 	struct v4l2_subdev_pad_config *pad_cfg;
+ 	struct v4l2_subdev_format format = {
+ 		.which = which,
++		.pad = vin->digital->source_pad,
+ 	};
+ 	enum v4l2_field field;
+ 	u32 width, height;
+ 	int ret;
+ 
+-	sd = vin_to_source(vin);
+-
+-	v4l2_fill_mbus_format(&format.format, pix, vin->digital->code);
+-
+ 	pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ 	if (pad_cfg == NULL)
+ 		return -ENOMEM;
+ 
+-	format.pad = vin->digital->source_pad;
++	if (!rvin_format_from_pixel(pix->pixelformat) ||
++	    (vin->info->model == RCAR_M1 &&
++	     pix->pixelformat == V4L2_PIX_FMT_XBGR32))
++		pix->pixelformat = RVIN_DEFAULT_FORMAT;
++
++	v4l2_fill_mbus_format(&format.format, pix, vin->digital->code);
+ 
+ 	/* Allow the video device to override field and to scale */
+ 	field = pix->field;
+@@ -211,8 +199,19 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 
+ 	v4l2_fill_pix_format(pix, &format.format);
+ 
+-	source->width = pix->width;
+-	source->height = pix->height;
++	if (crop) {
++		crop->top = 0;
++		crop->left = 0;
++		crop->width = pix->width;
++		crop->height = pix->height;
++
++		/*
++		 * If source is ALTERNATE the driver will use the VIN hardware
++		 * to INTERLACE it. The crop height then needs to be doubled.
++		 */
++		if (pix->field == V4L2_FIELD_ALTERNATE)
++			crop->height *= 2;
++	}
+ 
+ 	if (field != V4L2_FIELD_ANY)
+ 		pix->field = field;
+@@ -220,32 +219,18 @@ static int __rvin_try_format_source(struct rvin_dev *vin,
+ 	pix->width = width;
+ 	pix->height = height;
+ 
+-	vin_dbg(vin, "Source resolution: %ux%u\n", source->width,
+-		source->height);
++	rvin_format_align(vin, pix);
+ 
++	if (compose) {
++		compose->top = 0;
++		compose->left = 0;
++		compose->width = pix->width;
++		compose->height = pix->height;
++	}
+ done:
+ 	v4l2_subdev_free_pad_config(pad_cfg);
+-	return ret;
+-}
+ 
+-static int __rvin_try_format(struct rvin_dev *vin,
+-			     u32 which,
+-			     struct v4l2_pix_format *pix,
+-			     struct rvin_source_fmt *source)
+-{
+-	int ret;
+-
+-	if (!rvin_format_from_pixel(pix->pixelformat) ||
+-	    (vin->info->model == RCAR_M1 &&
+-	     pix->pixelformat == V4L2_PIX_FMT_XBGR32))
+-		pix->pixelformat = RVIN_DEFAULT_FORMAT;
+-
+-	/* Limit to source capabilities */
+-	ret = __rvin_try_format_source(vin, which, pix, source);
+-	if (ret)
+-		return ret;
+-
+-	return rvin_format_align(vin, pix);
++	return 0;
+ }
+ 
+ static int rvin_querycap(struct file *file, void *priv,
+@@ -264,33 +249,30 @@ static int rvin_try_fmt_vid_cap(struct file *file, void *priv,
+ 				struct v4l2_format *f)
+ {
+ 	struct rvin_dev *vin = video_drvdata(file);
+-	struct rvin_source_fmt source;
+ 
+-	return __rvin_try_format(vin, V4L2_SUBDEV_FORMAT_TRY, &f->fmt.pix,
+-				 &source);
++	return rvin_try_format(vin, V4L2_SUBDEV_FORMAT_TRY, &f->fmt.pix, NULL,
++			       NULL);
+ }
+ 
+ static int rvin_s_fmt_vid_cap(struct file *file, void *priv,
+ 			      struct v4l2_format *f)
+ {
+ 	struct rvin_dev *vin = video_drvdata(file);
+-	struct rvin_source_fmt source;
++	struct v4l2_rect crop, compose;
+ 	int ret;
+ 
+ 	if (vb2_is_busy(&vin->queue))
+ 		return -EBUSY;
+ 
+-	ret = __rvin_try_format(vin, V4L2_SUBDEV_FORMAT_ACTIVE, &f->fmt.pix,
+-				&source);
++	ret = rvin_try_format(vin, V4L2_SUBDEV_FORMAT_ACTIVE, &f->fmt.pix,
++			      &crop, &compose);
+ 	if (ret)
+ 		return ret;
+ 
+-	vin->source.width = source.width;
+-	vin->source.height = source.height;
+-
+ 	vin->format = f->fmt.pix;
+-
+-	rvin_reset_crop_compose(vin);
++	vin->crop = crop;
++	vin->compose = compose;
++	vin->source = crop;
+ 
+ 	return 0;
+ }
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 1c91b774205a..e940366d7e8d 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -46,16 +46,6 @@ enum rvin_dma_state {
+ 	STOPPING,
+ };
+ 
+-/**
+- * struct rvin_source_fmt - Source information
+- * @width:	Width from source
+- * @height:	Height from source
+- */
+-struct rvin_source_fmt {
+-	u32 width;
+-	u32 height;
+-};
+-
+ /**
+  * struct rvin_video_format - Data format stored in memory
+  * @fourcc:	Pixelformat
+@@ -123,11 +113,11 @@ struct rvin_info {
+  * @sequence:		V4L2 buffers sequence number
+  * @state:		keeps track of operation state
+  *
+- * @source:		active format from the video source
+  * @format:		active V4L2 pixel format
+  *
+  * @crop:		active cropping
+  * @compose:		active composing
++ * @source:		active size of the video source
+  */
+ struct rvin_dev {
+ 	struct device *dev;
+@@ -151,11 +141,11 @@ struct rvin_dev {
+ 	unsigned int sequence;
+ 	enum rvin_dma_state state;
+ 
+-	struct rvin_source_fmt source;
+ 	struct v4l2_pix_format format;
+ 
+ 	struct v4l2_rect crop;
+ 	struct v4l2_rect compose;
++	struct v4l2_rect source;
+ };
+ 
+ #define vin_to_source(vin)		((vin)->digital->subdev)
+-- 
+2.19.0
+
diff --git a/patches/1296-media-rcar-vin-cache-video-standard.patch b/patches/1296-media-rcar-vin-cache-video-standard.patch
new file mode 100644
index 00000000000000..1cef1a27b8bdc8
--- /dev/null
+++ b/patches/1296-media-rcar-vin-cache-video-standard.patch
@@ -0,0 +1,121 @@
+From 0587faaf5e15a15d622b76154195dc41960ee501 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:10 -0400
+Subject: [PATCH 1296/1795] media: rcar-vin: cache video standard
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+At stream on time the driver should not query the subdevice for which
+standard are used. Instead it should be cached when userspace sets the
+standard and used at stream on time.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 4f554bde63f94539f7d4cc44e2f1f9f3cb9ccdb3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c |  6 ++++++
+ drivers/media/platform/rcar-vin/rcar-dma.c  |  7 ++-----
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 10 ++++++++--
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  2 ++
+ 4 files changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index b7cce37d78b8..813cf628297a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -96,6 +96,12 @@ static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
+ 	if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
+ 		return ret;
+ 
++	/* Read standard */
++	vin->std = V4L2_STD_UNKNOWN;
++	ret = v4l2_subdev_call(subdev, video, g_std, &vin->std);
++	if (ret < 0 && ret != -ENOIOCTLCMD)
++		return ret;
++
+ 	/* Add the controls */
+ 	ret = v4l2_ctrl_handler_init(&vin->ctrl_handler, 16);
+ 	if (ret < 0)
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 9233924e5b52..79f4074b931b 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -592,7 +592,6 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ static int rvin_setup(struct rvin_dev *vin)
+ {
+ 	u32 vnmc, dmr, dmr2, interrupts;
+-	v4l2_std_id std;
+ 	bool progressive = false, output_is_yuv = false, input_is_yuv = false;
+ 
+ 	switch (vin->format.field) {
+@@ -606,10 +605,8 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		/* Default to TB */
+ 		vnmc = VNMC_IM_FULL;
+ 		/* Use BT if video standard can be read and is 60 Hz format */
+-		if (!v4l2_subdev_call(vin_to_source(vin), video, g_std, &std)) {
+-			if (std & V4L2_STD_525_60)
+-				vnmc = VNMC_IM_FULL | VNMC_FOC;
+-		}
++		if (vin->std & V4L2_STD_525_60)
++			vnmc = VNMC_IM_FULL | VNMC_FOC;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_TB:
+ 		vnmc = VNMC_IM_FULL;
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 84cad5d8c93a..9cdd00391c5c 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -475,6 +475,8 @@ static int rvin_s_std(struct file *file, void *priv, v4l2_std_id a)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	vin->std = a;
++
+ 	/* Changing the standard will change the width/height */
+ 	return rvin_reset_format(vin);
+ }
+@@ -482,9 +484,13 @@ static int rvin_s_std(struct file *file, void *priv, v4l2_std_id a)
+ static int rvin_g_std(struct file *file, void *priv, v4l2_std_id *a)
+ {
+ 	struct rvin_dev *vin = video_drvdata(file);
+-	struct v4l2_subdev *sd = vin_to_source(vin);
+ 
+-	return v4l2_subdev_call(sd, video, g_std, a);
++	if (v4l2_subdev_has_op(vin_to_source(vin), pad, dv_timings_cap))
++		return -ENOIOCTLCMD;
++
++	*a = vin->std;
++
++	return 0;
+ }
+ 
+ static int rvin_subscribe_event(struct v4l2_fh *fh,
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index e940366d7e8d..06cec4f8e5ff 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -118,6 +118,7 @@ struct rvin_info {
+  * @crop:		active cropping
+  * @compose:		active composing
+  * @source:		active size of the video source
++ * @std:		active video standard of the video source
+  */
+ struct rvin_dev {
+ 	struct device *dev;
+@@ -146,6 +147,7 @@ struct rvin_dev {
+ 	struct v4l2_rect crop;
+ 	struct v4l2_rect compose;
+ 	struct v4l2_rect source;
++	v4l2_std_id std;
+ };
+ 
+ #define vin_to_source(vin)		((vin)->digital->subdev)
+-- 
+2.19.0
+
diff --git a/patches/1297-media-rcar-vin-move-media-bus-configuration-to-struc.patch b/patches/1297-media-rcar-vin-move-media-bus-configuration-to-struc.patch
new file mode 100644
index 00000000000000..b4f99e369829b9
--- /dev/null
+++ b/patches/1297-media-rcar-vin-move-media-bus-configuration-to-struc.patch
@@ -0,0 +1,189 @@
+From 16110e856cb08081da0154095f6404a7fea3f2a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:11 -0400
+Subject: [PATCH 1297/1795] media: rcar-vin: move media bus configuration to
+ struct rvin_dev
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Bus configuration will once the driver is extended to support Gen3
+contain information not specific to only the directly connected parallel
+subdevice. Move it to struct rvin_dev to show it's not always coupled
+to the parallel subdevice.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit c65c99b401fad51fd911c7c4f69b14146de925fd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 18 +++++++++---------
+ drivers/media/platform/rcar-vin/rcar-dma.c  | 10 +++++-----
+ drivers/media/platform/rcar-vin/rcar-v4l2.c |  2 +-
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  9 ++++-----
+ 4 files changed, 19 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 813cf628297a..021e66cca187 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -65,10 +65,10 @@ static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
+ 	vin->digital->sink_pad = ret < 0 ? 0 : ret;
+ 
+ 	/* Find compatible subdevices mbus format */
+-	vin->digital->code = 0;
++	vin->mbus_code = 0;
+ 	code.index = 0;
+ 	code.pad = vin->digital->source_pad;
+-	while (!vin->digital->code &&
++	while (!vin->mbus_code &&
+ 	       !v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
+ 		code.index++;
+ 		switch (code.code) {
+@@ -76,16 +76,16 @@ static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
+ 		case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		case MEDIA_BUS_FMT_UYVY10_2X10:
+ 		case MEDIA_BUS_FMT_RGB888_1X24:
+-			vin->digital->code = code.code;
++			vin->mbus_code = code.code;
+ 			vin_dbg(vin, "Found media bus format for %s: %d\n",
+-				subdev->name, vin->digital->code);
++				subdev->name, vin->mbus_code);
+ 			break;
+ 		default:
+ 			break;
+ 		}
+ 	}
+ 
+-	if (!vin->digital->code) {
++	if (!vin->mbus_code) {
+ 		vin_err(vin, "Unsupported media bus format for %s\n",
+ 			subdev->name);
+ 		return -EINVAL;
+@@ -196,16 +196,16 @@ static int rvin_digital_parse_v4l2(struct device *dev,
+ 	if (vep->base.port || vep->base.id)
+ 		return -ENOTCONN;
+ 
+-	rvge->mbus_cfg.type = vep->bus_type;
++	vin->mbus_cfg.type = vep->bus_type;
+ 
+-	switch (rvge->mbus_cfg.type) {
++	switch (vin->mbus_cfg.type) {
+ 	case V4L2_MBUS_PARALLEL:
+ 		vin_dbg(vin, "Found PARALLEL media bus\n");
+-		rvge->mbus_cfg.flags = vep->bus.parallel.flags;
++		vin->mbus_cfg.flags = vep->bus.parallel.flags;
+ 		break;
+ 	case V4L2_MBUS_BT656:
+ 		vin_dbg(vin, "Found BT656 media bus\n");
+-		rvge->mbus_cfg.flags = 0;
++		vin->mbus_cfg.flags = 0;
+ 		break;
+ 	default:
+ 		vin_err(vin, "Unknown media bus type\n");
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 79f4074b931b..41907a200037 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -626,7 +626,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	/*
+ 	 * Input interface
+ 	 */
+-	switch (vin->digital->code) {
++	switch (vin->mbus_code) {
+ 	case MEDIA_BUS_FMT_YUYV8_1X16:
+ 		/* BT.601/BT.1358 16bit YCbCr422 */
+ 		vnmc |= VNMC_INF_YUV16;
+@@ -634,7 +634,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
+-		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
++		vnmc |= vin->mbus_cfg.type == V4L2_MBUS_BT656 ?
+ 			VNMC_INF_YUV8_BT656 : VNMC_INF_YUV8_BT601;
+ 		input_is_yuv = true;
+ 		break;
+@@ -643,7 +643,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	case MEDIA_BUS_FMT_UYVY10_2X10:
+ 		/* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
+-		vnmc |= vin->digital->mbus_cfg.type == V4L2_MBUS_BT656 ?
++		vnmc |= vin->mbus_cfg.type == V4L2_MBUS_BT656 ?
+ 			VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601;
+ 		input_is_yuv = true;
+ 		break;
+@@ -655,11 +655,11 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
+ 
+ 	/* Hsync Signal Polarity Select */
+-	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
++	if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+ 		dmr2 |= VNDMR2_HPS;
+ 
+ 	/* Vsync Signal Polarity Select */
+-	if (!(vin->digital->mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
++	if (!(vin->mbus_cfg.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
+ 		dmr2 |= VNDMR2_VPS;
+ 
+ 	/*
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 9cdd00391c5c..22914d50040b 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -186,7 +186,7 @@ static int rvin_try_format(struct rvin_dev *vin, u32 which,
+ 	     pix->pixelformat == V4L2_PIX_FMT_XBGR32))
+ 		pix->pixelformat = RVIN_DEFAULT_FORMAT;
+ 
+-	v4l2_fill_mbus_format(&format.format, pix, vin->digital->code);
++	v4l2_fill_mbus_format(&format.format, pix, vin->mbus_code);
+ 
+ 	/* Allow the video device to override field and to scale */
+ 	field = pix->field;
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 06cec4f8e5ff..952d57f32873 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -60,8 +60,6 @@ struct rvin_video_format {
+  * struct rvin_graph_entity - Video endpoint from async framework
+  * @asd:	sub-device descriptor for async framework
+  * @subdev:	subdevice matched using async framework
+- * @code:	Media bus format from source
+- * @mbus_cfg:	Media bus format from DT
+  * @source_pad:	source pad of remote subdevice
+  * @sink_pad:	sink pad of remote subdevice
+  */
+@@ -69,9 +67,6 @@ struct rvin_graph_entity {
+ 	struct v4l2_async_subdev asd;
+ 	struct v4l2_subdev *subdev;
+ 
+-	u32 code;
+-	struct v4l2_mbus_config mbus_cfg;
+-
+ 	unsigned int source_pad;
+ 	unsigned int sink_pad;
+ };
+@@ -113,6 +108,8 @@ struct rvin_info {
+  * @sequence:		V4L2 buffers sequence number
+  * @state:		keeps track of operation state
+  *
++ * @mbus_cfg:		media bus configuration from DT
++ * @mbus_code:		media bus format code
+  * @format:		active V4L2 pixel format
+  *
+  * @crop:		active cropping
+@@ -142,6 +139,8 @@ struct rvin_dev {
+ 	unsigned int sequence;
+ 	enum rvin_dma_state state;
+ 
++	struct v4l2_mbus_config mbus_cfg;
++	u32 mbus_code;
+ 	struct v4l2_pix_format format;
+ 
+ 	struct v4l2_rect crop;
+-- 
+2.19.0
+
diff --git a/patches/1298-media-rcar-vin-enable-Gen3-hardware-configuration.patch b/patches/1298-media-rcar-vin-enable-Gen3-hardware-configuration.patch
new file mode 100644
index 00000000000000..d993a3af8ab84e
--- /dev/null
+++ b/patches/1298-media-rcar-vin-enable-Gen3-hardware-configuration.patch
@@ -0,0 +1,208 @@
+From 09d43bea4c759c941856f43549f707b040479081 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:12 -0400
+Subject: [PATCH 1298/1795] media: rcar-vin: enable Gen3 hardware configuration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the register needed to work with Gen3 hardware. This patch adds
+the logic for how to work with the Gen3 hardware. More work is required
+to enable the subdevice structure needed to configure capturing.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 4394eb24a8d4088c80886a6823bbc132ac1a320c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 93 ++++++++++++++--------
+ drivers/media/platform/rcar-vin/rcar-vin.h |  1 +
+ 2 files changed, 63 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 41907a200037..482d89bae657 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -33,21 +33,23 @@
+ #define VNELPRC_REG	0x10	/* Video n End Line Pre-Clip Register */
+ #define VNSPPRC_REG	0x14	/* Video n Start Pixel Pre-Clip Register */
+ #define VNEPPRC_REG	0x18	/* Video n End Pixel Pre-Clip Register */
+-#define VNSLPOC_REG	0x1C	/* Video n Start Line Post-Clip Register */
+-#define VNELPOC_REG	0x20	/* Video n End Line Post-Clip Register */
+-#define VNSPPOC_REG	0x24	/* Video n Start Pixel Post-Clip Register */
+-#define VNEPPOC_REG	0x28	/* Video n End Pixel Post-Clip Register */
+ #define VNIS_REG	0x2C	/* Video n Image Stride Register */
+ #define VNMB_REG(m)	(0x30 + ((m) << 2)) /* Video n Memory Base m Register */
+ #define VNIE_REG	0x40	/* Video n Interrupt Enable Register */
+ #define VNINTS_REG	0x44	/* Video n Interrupt Status Register */
+ #define VNSI_REG	0x48	/* Video n Scanline Interrupt Register */
+ #define VNMTC_REG	0x4C	/* Video n Memory Transfer Control Register */
+-#define VNYS_REG	0x50	/* Video n Y Scale Register */
+-#define VNXS_REG	0x54	/* Video n X Scale Register */
+ #define VNDMR_REG	0x58	/* Video n Data Mode Register */
+ #define VNDMR2_REG	0x5C	/* Video n Data Mode Register 2 */
+ #define VNUVAOF_REG	0x60	/* Video n UV Address Offset Register */
++
++/* Register offsets specific for Gen2 */
++#define VNSLPOC_REG	0x1C	/* Video n Start Line Post-Clip Register */
++#define VNELPOC_REG	0x20	/* Video n End Line Post-Clip Register */
++#define VNSPPOC_REG	0x24	/* Video n Start Pixel Post-Clip Register */
++#define VNEPPOC_REG	0x28	/* Video n End Pixel Post-Clip Register */
++#define VNYS_REG	0x50	/* Video n Y Scale Register */
++#define VNXS_REG	0x54	/* Video n X Scale Register */
+ #define VNC1A_REG	0x80	/* Video n Coefficient Set C1A Register */
+ #define VNC1B_REG	0x84	/* Video n Coefficient Set C1B Register */
+ #define VNC1C_REG	0x88	/* Video n Coefficient Set C1C Register */
+@@ -73,9 +75,13 @@
+ #define VNC8B_REG	0xF4	/* Video n Coefficient Set C8B Register */
+ #define VNC8C_REG	0xF8	/* Video n Coefficient Set C8C Register */
+ 
++/* Register offsets specific for Gen3 */
++#define VNCSI_IFMD_REG		0x20 /* Video n CSI2 Interface Mode Register */
+ 
+ /* Register bit fields for R-Car VIN */
+ /* Video n Main Control Register bits */
++#define VNMC_DPINE		(1 << 27) /* Gen3 specific */
++#define VNMC_SCLE		(1 << 26) /* Gen3 specific */
+ #define VNMC_FOC		(1 << 21)
+ #define VNMC_YCAL		(1 << 19)
+ #define VNMC_INF_YUV8_BT656	(0 << 16)
+@@ -119,6 +125,12 @@
+ #define VNDMR2_FTEV		(1 << 17)
+ #define VNDMR2_VLV(n)		((n & 0xf) << 12)
+ 
++/* Video n CSI2 Interface Mode Register (Gen3) */
++#define VNCSI_IFMD_DES1		(1 << 26)
++#define VNCSI_IFMD_DES0		(1 << 25)
++#define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
++#define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
++
+ struct rvin_buffer {
+ 	struct vb2_v4l2_buffer vb;
+ 	struct list_head list;
+@@ -514,28 +526,10 @@ static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
+ 	rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
+ }
+ 
+-void rvin_crop_scale_comp(struct rvin_dev *vin)
++static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
+ {
+ 	u32 xs, ys;
+ 
+-	/* Set Start/End Pixel/Line Pre-Clip */
+-	rvin_write(vin, vin->crop.left, VNSPPRC_REG);
+-	rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
+-	switch (vin->format.field) {
+-	case V4L2_FIELD_INTERLACED:
+-	case V4L2_FIELD_INTERLACED_TB:
+-	case V4L2_FIELD_INTERLACED_BT:
+-		rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
+-		rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
+-			   VNELPRC_REG);
+-		break;
+-	default:
+-		rvin_write(vin, vin->crop.top, VNSLPRC_REG);
+-		rvin_write(vin, vin->crop.top + vin->crop.height - 1,
+-			   VNELPRC_REG);
+-		break;
+-	}
+-
+ 	/* Set scaling coefficient */
+ 	ys = 0;
+ 	if (vin->crop.height != vin->compose.height)
+@@ -573,11 +567,6 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ 		break;
+ 	}
+ 
+-	if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
+-		rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
+-	else
+-		rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
+-
+ 	vin_dbg(vin,
+ 		"Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
+ 		vin->crop.width, vin->crop.height, vin->crop.left,
+@@ -585,6 +574,37 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ 		0, 0);
+ }
+ 
++void rvin_crop_scale_comp(struct rvin_dev *vin)
++{
++	/* Set Start/End Pixel/Line Pre-Clip */
++	rvin_write(vin, vin->crop.left, VNSPPRC_REG);
++	rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
++
++	switch (vin->format.field) {
++	case V4L2_FIELD_INTERLACED:
++	case V4L2_FIELD_INTERLACED_TB:
++	case V4L2_FIELD_INTERLACED_BT:
++		rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
++		rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
++			   VNELPRC_REG);
++		break;
++	default:
++		rvin_write(vin, vin->crop.top, VNSLPRC_REG);
++		rvin_write(vin, vin->crop.top + vin->crop.height - 1,
++			   VNELPRC_REG);
++		break;
++	}
++
++	/* TODO: Add support for the UDS scaler. */
++	if (vin->info->model != RCAR_GEN3)
++		rvin_crop_scale_comp_gen2(vin);
++
++	if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
++		rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
++	else
++		rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
++}
++
+ /* -----------------------------------------------------------------------------
+  * Hardware setup
+  */
+@@ -652,7 +672,10 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	}
+ 
+ 	/* Enable VSYNC Field Toogle mode after one VSYNC input */
+-	dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
++	if (vin->info->model == RCAR_GEN3)
++		dmr2 = VNDMR2_FTEV;
++	else
++		dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
+ 
+ 	/* Hsync Signal Polarity Select */
+ 	if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+@@ -704,6 +727,14 @@ static int rvin_setup(struct rvin_dev *vin)
+ 	if (input_is_yuv == output_is_yuv)
+ 		vnmc |= VNMC_BPS;
+ 
++	if (vin->info->model == RCAR_GEN3) {
++		/* Select between CSI-2 and Digital input */
++		if (vin->mbus_cfg.type == V4L2_MBUS_CSI2)
++			vnmc &= ~VNMC_DPINE;
++		else
++			vnmc |= VNMC_DPINE;
++	}
++
+ 	/* Progressive or interlaced mode */
+ 	interrupts = progressive ? VNIE_FIE : VNIE_EFE;
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 952d57f32873..321283f1618a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -33,6 +33,7 @@ enum model_id {
+ 	RCAR_H1,
+ 	RCAR_M1,
+ 	RCAR_GEN2,
++	RCAR_GEN3,
+ };
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1299-media-rcar-vin-add-function-to-manipulate-Gen3-chsel.patch b/patches/1299-media-rcar-vin-add-function-to-manipulate-Gen3-chsel.patch
new file mode 100644
index 00000000000000..a13ccc1ceb17af
--- /dev/null
+++ b/patches/1299-media-rcar-vin-add-function-to-manipulate-Gen3-chsel.patch
@@ -0,0 +1,99 @@
+From 1a6c2cd3b97eecba6327770092ab5841bcce0208 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:13 -0400
+Subject: [PATCH 1299/1795] media: rcar-vin: add function to manipulate Gen3
+ chsel value
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On Gen3 the CSI-2 routing is controlled by the VnCSI_IFMD register. One
+feature of this register is that it's only present in the VIN0 and VIN4
+instances. The register in VIN0 controls the routing for VIN0-3 and the
+register in VIN4 controls routing for VIN4-7.
+
+To be able to control routing from a media device this function is need
+to control runtime PM for the subgroup master (VIN0 and VIN4). The
+subgroup master must be switched on before the register is manipulated,
+once the operation is complete it's safe to switch the master off and
+the new routing will still be in effect.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 90dedce9bc5446411fde1229e212a9d2b07cd263)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 37 ++++++++++++++++++++++
+ drivers/media/platform/rcar-vin/rcar-vin.h |  2 ++
+ 2 files changed, 39 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 482d89bae657..905d975b2909 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -16,6 +16,7 @@
+ 
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
++#include <linux/pm_runtime.h>
+ 
+ #include <media/videobuf2-dma-contig.h>
+ 
+@@ -1157,3 +1158,39 @@ int rvin_dma_register(struct rvin_dev *vin, int irq)
+ 
+ 	return ret;
+ }
++
++/* -----------------------------------------------------------------------------
++ * Gen3 CHSEL manipulation
++ */
++
++/*
++ * There is no need to have locking around changing the routing
++ * as it's only possible to do so when no VIN in the group is
++ * streaming so nothing can race with the VNMC register.
++ */
++int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
++{
++	u32 ifmd, vnmc;
++	int ret;
++
++	ret = pm_runtime_get_sync(vin->dev);
++	if (ret < 0)
++		return ret;
++
++	/* Make register writes take effect immediately. */
++	vnmc = rvin_read(vin, VNMC_REG);
++	rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
++
++	ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
++
++	rvin_write(vin, ifmd, VNCSI_IFMD_REG);
++
++	vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
++
++	/* Restore VNMC. */
++	rvin_write(vin, vnmc, VNMC_REG);
++
++	pm_runtime_put(vin->dev);
++
++	return ret;
++}
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 321283f1618a..c19ddc5e08cb 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -169,4 +169,6 @@ const struct rvin_video_format *rvin_format_from_pixel(u32 pixelformat);
+ /* Cropping, composing and scaling */
+ void rvin_crop_scale_comp(struct rvin_dev *vin);
+ 
++int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel);
++
+ #endif
+-- 
+2.19.0
+
diff --git a/patches/1300-media-rcar-vin-add-flag-to-switch-to-media-controlle.patch b/patches/1300-media-rcar-vin-add-flag-to-switch-to-media-controlle.patch
new file mode 100644
index 00000000000000..b7d047dc06b813
--- /dev/null
+++ b/patches/1300-media-rcar-vin-add-flag-to-switch-to-media-controlle.patch
@@ -0,0 +1,87 @@
+From 2d246327438285c053b65c70769ad3941d5fbf36 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:14 -0400
+Subject: [PATCH 1300/1795] media: rcar-vin: add flag to switch to media
+ controller mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On Gen3 a media controller API needs to be used to allow userspace to
+configure the subdevices in the pipeline instead of directly controlling
+a single source subdevice, which is and will continue to be the mode of
+operation on Gen2.
+
+Prepare for these two modes of operation by adding a flag to struct
+rvin_info which will control which mode to use.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 47ba5bbfd9ec7150cbc6e0205b4d5524b1ba2be9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 6 +++++-
+ drivers/media/platform/rcar-vin/rcar-vin.h  | 2 ++
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 021e66cca187..9d5b1d152286 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -249,18 +249,21 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 
+ static const struct rvin_info rcar_info_h1 = {
+ 	.model = RCAR_H1,
++	.use_mc = false,
+ 	.max_width = 2048,
+ 	.max_height = 2048,
+ };
+ 
+ static const struct rvin_info rcar_info_m1 = {
+ 	.model = RCAR_M1,
++	.use_mc = false,
+ 	.max_width = 2048,
+ 	.max_height = 2048,
+ };
+ 
+ static const struct rvin_info rcar_info_gen2 = {
+ 	.model = RCAR_GEN2,
++	.use_mc = false,
+ 	.max_width = 2048,
+ 	.max_height = 2048,
+ };
+@@ -355,7 +358,8 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+-	v4l2_ctrl_handler_free(&vin->ctrl_handler);
++	if (!vin->info->use_mc)
++		v4l2_ctrl_handler_free(&vin->ctrl_handler);
+ 
+ 	rvin_dma_unregister(vin);
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index c19ddc5e08cb..e5668c1120a6 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -75,11 +75,13 @@ struct rvin_graph_entity {
+ /**
+  * struct rvin_info - Information about the particular VIN implementation
+  * @model:		VIN model
++ * @use_mc:		use media controller instead of controlling subdevice
+  * @max_width:		max input width the VIN supports
+  * @max_height:		max input height the VIN supports
+  */
+ struct rvin_info {
+ 	enum model_id model;
++	bool use_mc;
+ 
+ 	unsigned int max_width;
+ 	unsigned int max_height;
+-- 
+2.19.0
+
diff --git a/patches/1301-media-rcar-vin-use-different-v4l2-operations-in-medi.patch b/patches/1301-media-rcar-vin-use-different-v4l2-operations-in-medi.patch
new file mode 100644
index 00000000000000..a30aa9a2360e3a
--- /dev/null
+++ b/patches/1301-media-rcar-vin-use-different-v4l2-operations-in-medi.patch
@@ -0,0 +1,251 @@
+From 609fbbae401d15b47afc8515c471c3abaadd1267 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:15 -0400
+Subject: [PATCH 1301/1795] media: rcar-vin: use different v4l2 operations in
+ media controller mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When the driver runs in media controller mode it should not directly
+control the subdevice instead userspace will be responsible for
+configuring the pipeline. To be able to run in this mode a different set
+of v4l2 operations needs to be used.
+
+Add a new set of v4l2 operations to support operation without directly
+interacting with the source subdevice.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 5e7c623632fcf8f52c9a3f8192eb05909469ee1c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c  |   2 +-
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 158 +++++++++++++++++++-
+ 2 files changed, 156 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 905d975b2909..d70a689d9dd3 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -626,7 +626,7 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		/* Default to TB */
+ 		vnmc = VNMC_IM_FULL;
+ 		/* Use BT if video standard can be read and is 60 Hz format */
+-		if (vin->std & V4L2_STD_525_60)
++		if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
+ 			vnmc = VNMC_IM_FULL | VNMC_FOC;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_TB:
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 22914d50040b..2c94ca57e925 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -18,12 +18,16 @@
+ 
+ #include <media/v4l2-event.h>
+ #include <media/v4l2-ioctl.h>
++#include <media/v4l2-mc.h>
+ #include <media/v4l2-rect.h>
+ 
+ #include "rcar-vin.h"
+ 
+ #define RVIN_DEFAULT_FORMAT	V4L2_PIX_FMT_YUYV
++#define RVIN_DEFAULT_WIDTH	800
++#define RVIN_DEFAULT_HEIGHT	600
+ #define RVIN_DEFAULT_FIELD	V4L2_FIELD_NONE
++#define RVIN_DEFAULT_COLORSPACE	V4L2_COLORSPACE_SRGB
+ 
+ /* -----------------------------------------------------------------------------
+  * Format Conversions
+@@ -654,6 +658,73 @@ static const struct v4l2_ioctl_ops rvin_ioctl_ops = {
+ 	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
+ };
+ 
++/* -----------------------------------------------------------------------------
++ * V4L2 Media Controller
++ */
++
++static int rvin_mc_try_fmt_vid_cap(struct file *file, void *priv,
++				   struct v4l2_format *f)
++{
++	struct rvin_dev *vin = video_drvdata(file);
++
++	rvin_format_align(vin, &f->fmt.pix);
++
++	return 0;
++}
++
++static int rvin_mc_s_fmt_vid_cap(struct file *file, void *priv,
++				 struct v4l2_format *f)
++{
++	struct rvin_dev *vin = video_drvdata(file);
++
++	if (vb2_is_busy(&vin->queue))
++		return -EBUSY;
++
++	rvin_format_align(vin, &f->fmt.pix);
++
++	vin->format = f->fmt.pix;
++
++	return 0;
++}
++
++static int rvin_mc_enum_input(struct file *file, void *priv,
++			      struct v4l2_input *i)
++{
++	if (i->index != 0)
++		return -EINVAL;
++
++	i->type = V4L2_INPUT_TYPE_CAMERA;
++	strlcpy(i->name, "Camera", sizeof(i->name));
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops rvin_mc_ioctl_ops = {
++	.vidioc_querycap		= rvin_querycap,
++	.vidioc_try_fmt_vid_cap		= rvin_mc_try_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap		= rvin_g_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap		= rvin_mc_s_fmt_vid_cap,
++	.vidioc_enum_fmt_vid_cap	= rvin_enum_fmt_vid_cap,
++
++	.vidioc_enum_input		= rvin_mc_enum_input,
++	.vidioc_g_input			= rvin_g_input,
++	.vidioc_s_input			= rvin_s_input,
++
++	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
++	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
++	.vidioc_querybuf		= vb2_ioctl_querybuf,
++	.vidioc_qbuf			= vb2_ioctl_qbuf,
++	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
++	.vidioc_streamon		= vb2_ioctl_streamon,
++	.vidioc_streamoff		= vb2_ioctl_streamoff,
++
++	.vidioc_log_status		= v4l2_ctrl_log_status,
++	.vidioc_subscribe_event		= rvin_subscribe_event,
++	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
++};
++
+ /* -----------------------------------------------------------------------------
+  * File Operations
+  */
+@@ -797,6 +868,74 @@ static const struct v4l2_file_operations rvin_fops = {
+ 	.read		= vb2_fop_read,
+ };
+ 
++/* -----------------------------------------------------------------------------
++ * Media controller file operations
++ */
++
++static int rvin_mc_open(struct file *file)
++{
++	struct rvin_dev *vin = video_drvdata(file);
++	int ret;
++
++	ret = mutex_lock_interruptible(&vin->lock);
++	if (ret)
++		return ret;
++
++	ret = pm_runtime_get_sync(vin->dev);
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = v4l2_pipeline_pm_use(&vin->vdev.entity, 1);
++	if (ret < 0)
++		goto err_pm;
++
++	file->private_data = vin;
++
++	ret = v4l2_fh_open(file);
++	if (ret)
++		goto err_v4l2pm;
++
++	mutex_unlock(&vin->lock);
++
++	return 0;
++err_v4l2pm:
++	v4l2_pipeline_pm_use(&vin->vdev.entity, 0);
++err_pm:
++	pm_runtime_put(vin->dev);
++err_unlock:
++	mutex_unlock(&vin->lock);
++
++	return ret;
++}
++
++static int rvin_mc_release(struct file *file)
++{
++	struct rvin_dev *vin = video_drvdata(file);
++	int ret;
++
++	mutex_lock(&vin->lock);
++
++	/* the release helper will cleanup any on-going streaming. */
++	ret = _vb2_fop_release(file, NULL);
++
++	v4l2_pipeline_pm_use(&vin->vdev.entity, 0);
++	pm_runtime_put(vin->dev);
++
++	mutex_unlock(&vin->lock);
++
++	return ret;
++}
++
++static const struct v4l2_file_operations rvin_mc_fops = {
++	.owner		= THIS_MODULE,
++	.unlocked_ioctl	= video_ioctl2,
++	.open		= rvin_mc_open,
++	.release	= rvin_mc_release,
++	.poll		= vb2_fop_poll,
++	.mmap		= vb2_fop_mmap,
++	.read		= vb2_fop_read,
++};
++
+ void rvin_v4l2_unregister(struct rvin_dev *vin)
+ {
+ 	if (!video_is_registered(&vin->vdev))
+@@ -832,18 +971,31 @@ int rvin_v4l2_register(struct rvin_dev *vin)
+ 	vin->v4l2_dev.notify = rvin_notify;
+ 
+ 	/* video node */
+-	vdev->fops = &rvin_fops;
+ 	vdev->v4l2_dev = &vin->v4l2_dev;
+ 	vdev->queue = &vin->queue;
+ 	strlcpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
+ 	vdev->release = video_device_release_empty;
+-	vdev->ioctl_ops = &rvin_ioctl_ops;
+ 	vdev->lock = &vin->lock;
+ 	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
+ 		V4L2_CAP_READWRITE;
+ 
++	/* Set a default format */
+ 	vin->format.pixelformat	= RVIN_DEFAULT_FORMAT;
+-	rvin_reset_format(vin);
++	vin->format.width = RVIN_DEFAULT_WIDTH;
++	vin->format.height = RVIN_DEFAULT_HEIGHT;
++	vin->format.field = RVIN_DEFAULT_FIELD;
++	vin->format.colorspace = RVIN_DEFAULT_COLORSPACE;
++
++	if (vin->info->use_mc) {
++		vdev->fops = &rvin_mc_fops;
++		vdev->ioctl_ops = &rvin_mc_ioctl_ops;
++	} else {
++		vdev->fops = &rvin_fops;
++		vdev->ioctl_ops = &rvin_ioctl_ops;
++		rvin_reset_format(vin);
++	}
++
++	rvin_format_align(vin, &vin->format);
+ 
+ 	ret = video_register_device(&vin->vdev, VFL_TYPE_GRABBER, -1);
+ 	if (ret) {
+-- 
+2.19.0
+
diff --git a/patches/1302-media-rcar-vin-force-default-colorspace-for-media-ce.patch b/patches/1302-media-rcar-vin-force-default-colorspace-for-media-ce.patch
new file mode 100644
index 00000000000000..6e0f9a3e0760f6
--- /dev/null
+++ b/patches/1302-media-rcar-vin-force-default-colorspace-for-media-ce.patch
@@ -0,0 +1,75 @@
+From fe4ef42d304848a7a4e76c76ae7bce4d0539aaab Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:16 -0400
+Subject: [PATCH 1302/1795] media: rcar-vin: force default colorspace for media
+ centric mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The V4L2 specification clearly documents the colorspace fields as being
+set by drivers for capture devices. Using the values supplied by
+userspace thus wouldn't comply with the API. Until the API is updated to
+allow for userspace to set these Hans wants the fields to be set by the
+driver to fixed values.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit e812c94e3073d41e86c621e6e5d9cf796c107635)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 22 +++++++++++++++++++--
+ 1 file changed, 20 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 2c94ca57e925..c58424aa33c4 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -662,12 +662,30 @@ static const struct v4l2_ioctl_ops rvin_ioctl_ops = {
+  * V4L2 Media Controller
+  */
+ 
++static void rvin_mc_try_format(struct rvin_dev *vin,
++			       struct v4l2_pix_format *pix)
++{
++	/*
++	 * The V4L2 specification clearly documents the colorspace fields
++	 * as being set by drivers for capture devices. Using the values
++	 * supplied by userspace thus wouldn't comply with the API. Until
++	 * the API is updated force fixed vaules.
++	 */
++	pix->colorspace = RVIN_DEFAULT_COLORSPACE;
++	pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
++	pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
++	pix->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, pix->colorspace,
++							  pix->ycbcr_enc);
++
++	rvin_format_align(vin, pix);
++}
++
+ static int rvin_mc_try_fmt_vid_cap(struct file *file, void *priv,
+ 				   struct v4l2_format *f)
+ {
+ 	struct rvin_dev *vin = video_drvdata(file);
+ 
+-	rvin_format_align(vin, &f->fmt.pix);
++	rvin_mc_try_format(vin, &f->fmt.pix);
+ 
+ 	return 0;
+ }
+@@ -680,7 +698,7 @@ static int rvin_mc_s_fmt_vid_cap(struct file *file, void *priv,
+ 	if (vb2_is_busy(&vin->queue))
+ 		return -EBUSY;
+ 
+-	rvin_format_align(vin, &f->fmt.pix);
++	rvin_mc_try_format(vin, &f->fmt.pix);
+ 
+ 	vin->format = f->fmt.pix;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1303-media-rcar-vin-prepare-for-media-controller-mode-ini.patch b/patches/1303-media-rcar-vin-prepare-for-media-controller-mode-ini.patch
new file mode 100644
index 00000000000000..b62307ae012a8f
--- /dev/null
+++ b/patches/1303-media-rcar-vin-prepare-for-media-controller-mode-ini.patch
@@ -0,0 +1,99 @@
+From 15af81a3abe0be590d2f6c6b1e5776c8bf4725dd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:17 -0400
+Subject: [PATCH 1303/1795] media: rcar-vin: prepare for media controller mode
+ initialization
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Prepare for media controller by calling a different initialization then
+when running in device centric mode. Add trivial configuration of
+the mbus and creation of the media pad for the video device entity.
+
+While we are at it clearly mark the digital device centric notifier
+functions with a comment.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 68ee48d66648f8c800a640733ce774d0bdc06329)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 20 ++++++++++++++++++--
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  4 ++++
+ 2 files changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 9d5b1d152286..9e31c771917f 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -46,6 +46,10 @@ static int rvin_find_pad(struct v4l2_subdev *sd, int direction)
+ 	return -EINVAL;
+ }
+ 
++/* -----------------------------------------------------------------------------
++ * Digital async notifier
++ */
++
+ /* The vin lock should be held when calling the subdevice attach and detach */
+ static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
+ 					 struct v4l2_subdev *subdev)
+@@ -243,6 +247,16 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 	return 0;
+ }
+ 
++static int rvin_mc_init(struct rvin_dev *vin)
++{
++	/* All our sources are CSI-2 */
++	vin->mbus_cfg.type = V4L2_MBUS_CSI2;
++	vin->mbus_cfg.flags = 0;
++
++	vin->pad.flags = MEDIA_PAD_FL_SINK;
++	return media_entity_pads_init(&vin->vdev.entity, 1, &vin->pad);
++}
++
+ /* -----------------------------------------------------------------------------
+  * Platform Device Driver
+  */
+@@ -331,8 +345,10 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 		return ret;
+ 
+ 	platform_set_drvdata(pdev, vin);
+-
+-	ret = rvin_digital_graph_init(vin);
++	if (vin->info->use_mc)
++		ret = rvin_mc_init(vin);
++	else
++		ret = rvin_digital_graph_init(vin);
+ 	if (ret < 0)
+ 		goto error;
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index e5668c1120a6..5102ad254bff 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -99,6 +99,8 @@ struct rvin_info {
+  * @notifier:		V4L2 asynchronous subdevs notifier
+  * @digital:		entity in the DT for local digital subdevice
+  *
++ * @pad:		media pad for the video device entity
++ *
+  * @lock:		protects @queue
+  * @queue:		vb2 buffers queue
+  * @scratch:		cpu address for scratch buffer
+@@ -131,6 +133,8 @@ struct rvin_dev {
+ 	struct v4l2_async_notifier notifier;
+ 	struct rvin_graph_entity *digital;
+ 
++	struct media_pad pad;
++
+ 	struct mutex lock;
+ 	struct vb2_queue queue;
+ 	void *scratch;
+-- 
+2.19.0
+
diff --git a/patches/1304-media-rcar-vin-add-group-allocator-functions.patch b/patches/1304-media-rcar-vin-add-group-allocator-functions.patch
new file mode 100644
index 00000000000000..29b1f0006aae4e
--- /dev/null
+++ b/patches/1304-media-rcar-vin-add-group-allocator-functions.patch
@@ -0,0 +1,312 @@
+From 1f37e36d4f767811916620f9a6a183ede4a46b32 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:18 -0400
+Subject: [PATCH 1304/1795] media: rcar-vin: add group allocator functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In media controller mode all VIN instances needs to be part of the same
+media graph. There is also a need for each VIN instance to know about
+and in some cases be able to communicate with other VIN instances.
+
+Add an allocator framework where the first VIN instance to be probed
+creates a shared data structure and registers a media device.
+Consecutive VINs insert themself into the global group.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 3bb4c3bc85bf77a76c921671800bde2e1bf82a88)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 174 +++++++++++++++++++-
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  31 ++++
+ 2 files changed, 203 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 9e31c771917f..5f9e31a0b89e 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -20,12 +20,174 @@
+ #include <linux/of_graph.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/slab.h>
+ 
+ #include <media/v4l2-async.h>
+ #include <media/v4l2-fwnode.h>
+ 
+ #include "rcar-vin.h"
+ 
++/* -----------------------------------------------------------------------------
++ * Gen3 CSI2 Group Allocator
++ */
++
++/* FIXME:  This should if we find a system that supports more
++ * than one group for the whole system be replaced with a linked
++ * list of groups. And eventually all of this should be replaced
++ * with a global device allocator API.
++ *
++ * But for now this works as on all supported systems there will
++ * be only one group for all instances.
++ */
++
++static DEFINE_MUTEX(rvin_group_lock);
++static struct rvin_group *rvin_group_data;
++
++static void rvin_group_cleanup(struct rvin_group *group)
++{
++	media_device_unregister(&group->mdev);
++	media_device_cleanup(&group->mdev);
++	mutex_destroy(&group->lock);
++}
++
++static int rvin_group_init(struct rvin_group *group, struct rvin_dev *vin)
++{
++	struct media_device *mdev = &group->mdev;
++	const struct of_device_id *match;
++	struct device_node *np;
++	int ret;
++
++	mutex_init(&group->lock);
++
++	/* Count number of VINs in the system */
++	group->count = 0;
++	for_each_matching_node(np, vin->dev->driver->of_match_table)
++		if (of_device_is_available(np))
++			group->count++;
++
++	vin_dbg(vin, "found %u enabled VIN's in DT", group->count);
++
++	mdev->dev = vin->dev;
++
++	match = of_match_node(vin->dev->driver->of_match_table,
++			      vin->dev->of_node);
++
++	strlcpy(mdev->driver_name, KBUILD_MODNAME, sizeof(mdev->driver_name));
++	strlcpy(mdev->model, match->compatible, sizeof(mdev->model));
++	snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s",
++		 dev_name(mdev->dev));
++
++	media_device_init(mdev);
++
++	ret = media_device_register(&group->mdev);
++	if (ret)
++		rvin_group_cleanup(group);
++
++	return ret;
++}
++
++static void rvin_group_release(struct kref *kref)
++{
++	struct rvin_group *group =
++		container_of(kref, struct rvin_group, refcount);
++
++	mutex_lock(&rvin_group_lock);
++
++	rvin_group_data = NULL;
++
++	rvin_group_cleanup(group);
++
++	kfree(group);
++
++	mutex_unlock(&rvin_group_lock);
++}
++
++static int rvin_group_get(struct rvin_dev *vin)
++{
++	struct rvin_group *group;
++	u32 id;
++	int ret;
++
++	/* Make sure VIN id is present and sane */
++	ret = of_property_read_u32(vin->dev->of_node, "renesas,id", &id);
++	if (ret) {
++		vin_err(vin, "%pOF: No renesas,id property found\n",
++			vin->dev->of_node);
++		return -EINVAL;
++	}
++
++	if (id >= RCAR_VIN_NUM) {
++		vin_err(vin, "%pOF: Invalid renesas,id '%u'\n",
++			vin->dev->of_node, id);
++		return -EINVAL;
++	}
++
++	/* Join or create a VIN group */
++	mutex_lock(&rvin_group_lock);
++	if (rvin_group_data) {
++		group = rvin_group_data;
++		kref_get(&group->refcount);
++	} else {
++		group = kzalloc(sizeof(*group), GFP_KERNEL);
++		if (!group) {
++			ret = -ENOMEM;
++			goto err_group;
++		}
++
++		ret = rvin_group_init(group, vin);
++		if (ret) {
++			kfree(group);
++			vin_err(vin, "Failed to initialize group\n");
++			goto err_group;
++		}
++
++		kref_init(&group->refcount);
++
++		rvin_group_data = group;
++	}
++	mutex_unlock(&rvin_group_lock);
++
++	/* Add VIN to group */
++	mutex_lock(&group->lock);
++
++	if (group->vin[id]) {
++		vin_err(vin, "Duplicate renesas,id property value %u\n", id);
++		mutex_unlock(&group->lock);
++		kref_put(&group->refcount, rvin_group_release);
++		return -EINVAL;
++	}
++
++	group->vin[id] = vin;
++
++	vin->id = id;
++	vin->group = group;
++	vin->v4l2_dev.mdev = &group->mdev;
++
++	mutex_unlock(&group->lock);
++
++	return 0;
++err_group:
++	mutex_unlock(&rvin_group_lock);
++	return ret;
++}
++
++static void rvin_group_put(struct rvin_dev *vin)
++{
++	mutex_lock(&vin->group->lock);
++
++	vin->group = NULL;
++	vin->v4l2_dev.mdev = NULL;
++
++	if (WARN_ON(vin->group->vin[vin->id] != vin))
++		goto out;
++
++	vin->group->vin[vin->id] = NULL;
++out:
++	mutex_unlock(&vin->group->lock);
++
++	kref_put(&vin->group->refcount, rvin_group_release);
++}
++
+ /* -----------------------------------------------------------------------------
+  * Async notifier
+  */
+@@ -249,12 +411,18 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 
+ static int rvin_mc_init(struct rvin_dev *vin)
+ {
++	int ret;
++
+ 	/* All our sources are CSI-2 */
+ 	vin->mbus_cfg.type = V4L2_MBUS_CSI2;
+ 	vin->mbus_cfg.flags = 0;
+ 
+ 	vin->pad.flags = MEDIA_PAD_FL_SINK;
+-	return media_entity_pads_init(&vin->vdev.entity, 1, &vin->pad);
++	ret = media_entity_pads_init(&vin->vdev.entity, 1, &vin->pad);
++	if (ret)
++		return ret;
++
++	return rvin_group_get(vin);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -374,7 +542,9 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+-	if (!vin->info->use_mc)
++	if (vin->info->use_mc)
++		rvin_group_put(vin);
++	else
+ 		v4l2_ctrl_handler_free(&vin->ctrl_handler);
+ 
+ 	rvin_dma_unregister(vin);
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 5102ad254bff..cf5c467d45e1 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -17,6 +17,8 @@
+ #ifndef __RCAR_VIN__
+ #define __RCAR_VIN__
+ 
++#include <linux/kref.h>
++
+ #include <media/v4l2-async.h>
+ #include <media/v4l2-ctrls.h>
+ #include <media/v4l2-dev.h>
+@@ -29,6 +31,11 @@
+ /* Address alignment mask for HW buffers */
+ #define HW_BUFFER_MASK 0x7f
+ 
++/* Max number on VIN instances that can be in a system */
++#define RCAR_VIN_NUM 8
++
++struct rvin_group;
++
+ enum model_id {
+ 	RCAR_H1,
+ 	RCAR_M1,
+@@ -99,6 +106,8 @@ struct rvin_info {
+  * @notifier:		V4L2 asynchronous subdevs notifier
+  * @digital:		entity in the DT for local digital subdevice
+  *
++ * @group:		Gen3 CSI group
++ * @id:			Gen3 group id for this VIN
+  * @pad:		media pad for the video device entity
+  *
+  * @lock:		protects @queue
+@@ -133,6 +142,8 @@ struct rvin_dev {
+ 	struct v4l2_async_notifier notifier;
+ 	struct rvin_graph_entity *digital;
+ 
++	struct rvin_group *group;
++	unsigned int id;
+ 	struct media_pad pad;
+ 
+ 	struct mutex lock;
+@@ -164,6 +175,26 @@ struct rvin_dev {
+ #define vin_warn(d, fmt, arg...)	dev_warn(d->dev, fmt, ##arg)
+ #define vin_err(d, fmt, arg...)		dev_err(d->dev, fmt, ##arg)
+ 
++/**
++ * struct rvin_group - VIN CSI2 group information
++ * @refcount:		number of VIN instances using the group
++ *
++ * @mdev:		media device which represents the group
++ *
++ * @lock:		protects the count and vin members
++ * @count:		number of enabled VIN instances found in DT
++ * @vin:		VIN instances which are part of the group
++ */
++struct rvin_group {
++	struct kref refcount;
++
++	struct media_device mdev;
++
++	struct mutex lock;
++	unsigned int count;
++	struct rvin_dev *vin[RCAR_VIN_NUM];
++};
++
+ int rvin_dma_register(struct rvin_dev *vin, int irq);
+ void rvin_dma_unregister(struct rvin_dev *vin);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1305-media-rcar-vin-change-name-of-video-device.patch b/patches/1305-media-rcar-vin-change-name-of-video-device.patch
new file mode 100644
index 00000000000000..f5029004f7ae08
--- /dev/null
+++ b/patches/1305-media-rcar-vin-change-name-of-video-device.patch
@@ -0,0 +1,40 @@
+From 4d6013e36f197a0fe955bd2db449ac31422359f9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:19 -0400
+Subject: [PATCH 1305/1795] media: rcar-vin: change name of video device
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The rcar-vin driver needs to be part of a media controller to support
+Gen3. Give each VIN instance a unique name so it can be referenced from
+userspace.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit e806e328c8ca6d71806e517e6134590404817eaa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index c58424aa33c4..2fb8587116f2 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -991,7 +991,7 @@ int rvin_v4l2_register(struct rvin_dev *vin)
+ 	/* video node */
+ 	vdev->v4l2_dev = &vin->v4l2_dev;
+ 	vdev->queue = &vin->queue;
+-	strlcpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
++	snprintf(vdev->name, sizeof(vdev->name), "VIN%u output", vin->id);
+ 	vdev->release = video_device_release_empty;
+ 	vdev->lock = &vin->lock;
+ 	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
+-- 
+2.19.0
+
diff --git a/patches/1306-media-rcar-vin-add-chsel-information-to-rvin_info.patch b/patches/1306-media-rcar-vin-add-chsel-information-to-rvin_info.patch
new file mode 100644
index 00000000000000..2e123d91580f1b
--- /dev/null
+++ b/patches/1306-media-rcar-vin-add-chsel-information-to-rvin_info.patch
@@ -0,0 +1,100 @@
+From 648d6b4515774568b4a3cca54a102a870f9632c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:20 -0400
+Subject: [PATCH 1306/1795] media: rcar-vin: add chsel information to rvin_info
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Each Gen3 SoC has a limited set of predefined routing possibilities for
+which CSI-2 device and channel can be routed to which VIN instance.
+Prepare to store this information in the struct rvin_info.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 23fd542e6305f9f3d9b651a46a07c1d3b4c8871a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-vin.h | 42 ++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index cf5c467d45e1..93eb40856b86 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -43,6 +43,14 @@ enum model_id {
+ 	RCAR_GEN3,
+ };
+ 
++enum rvin_csi_id {
++	RVIN_CSI20,
++	RVIN_CSI21,
++	RVIN_CSI40,
++	RVIN_CSI41,
++	RVIN_CSI_MAX,
++};
++
+ /**
+  * STOPPED  - No operation in progress
+  * RUNNING  - Operation in progress have buffers
+@@ -79,12 +87,45 @@ struct rvin_graph_entity {
+ 	unsigned int sink_pad;
+ };
+ 
++/**
++ * struct rvin_group_route - describes a route from a channel of a
++ *	CSI-2 receiver to a VIN
++ *
++ * @csi:	CSI-2 receiver ID.
++ * @channel:	Output channel of the CSI-2 receiver.
++ * @vin:	VIN ID.
++ * @mask:	Bitmask of the different CHSEL register values that
++ *		allow for a route from @csi + @chan to @vin.
++ *
++ * .. note::
++ *	Each R-Car CSI-2 receiver has four output channels facing the VIN
++ *	devices, each channel can carry one CSI-2 Virtual Channel (VC).
++ *	There is no correlation between channel number and CSI-2 VC. It's
++ *	up to the CSI-2 receiver driver to configure which VC is output
++ *	on which channel, the VIN devices only care about output channels.
++ *
++ *	There are in some cases multiple CHSEL register settings which would
++ *	allow for the same route from @csi + @channel to @vin. For example
++ *	on R-Car H3 both the CHSEL values 0 and 3 allow for a route from
++ *	CSI40/VC0 to VIN0. All possible CHSEL values for a route need to be
++ *	recorded as a bitmask in @mask, in this example bit 0 and 3 should
++ *	be set.
++ */
++struct rvin_group_route {
++	enum rvin_csi_id csi;
++	unsigned int channel;
++	unsigned int vin;
++	unsigned int mask;
++};
++
+ /**
+  * struct rvin_info - Information about the particular VIN implementation
+  * @model:		VIN model
+  * @use_mc:		use media controller instead of controlling subdevice
+  * @max_width:		max input width the VIN supports
+  * @max_height:		max input height the VIN supports
++ * @routes:		list of possible routes from the CSI-2 recivers to
++ *			all VINs. The list mush be NULL terminated.
+  */
+ struct rvin_info {
+ 	enum model_id model;
+@@ -92,6 +133,7 @@ struct rvin_info {
+ 
+ 	unsigned int max_width;
+ 	unsigned int max_height;
++	const struct rvin_group_route *routes;
+ };
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1307-media-rcar-vin-parse-Gen3-OF-and-setup-media-graph.patch b/patches/1307-media-rcar-vin-parse-Gen3-OF-and-setup-media-graph.patch
new file mode 100644
index 00000000000000..bcf14b96de7f26
--- /dev/null
+++ b/patches/1307-media-rcar-vin-parse-Gen3-OF-and-setup-media-graph.patch
@@ -0,0 +1,352 @@
+From b333a675fb29fac85c70efa81d621850e8ff1d3b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:21 -0400
+Subject: [PATCH 1307/1795] media: rcar-vin: parse Gen3 OF and setup media
+ graph
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The parsing and registering CSI-2 subdevices with the v4l2 async
+framework is a collaborative effort shared between the VIN instances
+which are part of the group. When the last VIN in the group is probed it
+asks all other VINs to parse its share of OF and record the async
+subdevices it finds in the notifier belonging to the last probed VIN.
+
+Once all CSI-2 subdevices in this notifier are bound proceed to register
+all VIN video devices of the group and crate media device links between
+all CSI-2 and VIN entities according to the SoC specific routing
+configuration.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit c7e80b67b63046ffa299a471e42be3eddc2e1d31)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts
+	drivers/media/platform/rcar-vin/rcar-core.c
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 246 +++++++++++++++++++-
+ drivers/media/platform/rcar-vin/rcar-vin.h  |  12 +-
+ 2 files changed, 254 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 5f9e31a0b89e..844606c7ab58 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -27,6 +27,23 @@
+ 
+ #include "rcar-vin.h"
+ 
++/*
++ * The companion CSI-2 receiver driver (rcar-csi2) is known
++ * and we know it has one source pad (pad 0) and four sink
++ * pads (pad 1-4). So to translate a pad on the remote
++ * CSI-2 receiver to/from the VIN internal channel number simply
++ * subtract/add one from the pad/channel number.
++ */
++#define rvin_group_csi_pad_to_channel(pad) ((pad) - 1)
++#define rvin_group_csi_channel_to_pad(channel) ((channel) + 1)
++
++/*
++ * Not all VINs are created equal, master VINs control the
++ * routing for other VIN's. We can figure out which VIN is
++ * master by looking at a VINs id.
++ */
++#define rvin_group_id_to_master(vin) ((vin) < 4 ? 0 : 4)
++
+ /* -----------------------------------------------------------------------------
+  * Gen3 CSI2 Group Allocator
+  */
+@@ -409,6 +426,216 @@ static int rvin_digital_graph_init(struct rvin_dev *vin)
+ 	return 0;
+ }
+ 
++/* -----------------------------------------------------------------------------
++ * Group async notifier
++ */
++
++static int rvin_group_notify_complete(struct v4l2_async_notifier *notifier)
++{
++	struct rvin_dev *vin = notifier_to_vin(notifier);
++	const struct rvin_group_route *route;
++	unsigned int i;
++	int ret;
++
++	ret = v4l2_device_register_subdev_nodes(&vin->v4l2_dev);
++	if (ret) {
++		vin_err(vin, "Failed to register subdev nodes\n");
++		return ret;
++	}
++
++	/* Register all video nodes for the group. */
++	for (i = 0; i < RCAR_VIN_NUM; i++) {
++		if (vin->group->vin[i]) {
++			ret = rvin_v4l2_register(vin->group->vin[i]);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Create all media device links between VINs and CSI-2's. */
++	mutex_lock(&vin->group->lock);
++	for (route = vin->info->routes; route->mask; route++) {
++		struct media_pad *source_pad, *sink_pad;
++		struct media_entity *source, *sink;
++		unsigned int source_idx;
++
++		/* Check that VIN is part of the group. */
++		if (!vin->group->vin[route->vin])
++			continue;
++
++		/* Check that VIN' master is part of the group. */
++		if (!vin->group->vin[rvin_group_id_to_master(route->vin)])
++			continue;
++
++		/* Check that CSI-2 is part of the group. */
++		if (!vin->group->csi[route->csi].subdev)
++			continue;
++
++		source = &vin->group->csi[route->csi].subdev->entity;
++		source_idx = rvin_group_csi_channel_to_pad(route->channel);
++		source_pad = &source->pads[source_idx];
++
++		sink = &vin->group->vin[route->vin]->vdev.entity;
++		sink_pad = &sink->pads[0];
++
++		/* Skip if link already exists. */
++		if (media_entity_find_link(source_pad, sink_pad))
++			continue;
++
++		ret = media_create_pad_link(source, source_idx, sink, 0, 0);
++		if (ret) {
++			vin_err(vin, "Error adding link from %s to %s\n",
++				source->name, sink->name);
++			break;
++		}
++	}
++	mutex_unlock(&vin->group->lock);
++
++	return ret;
++}
++
++static void rvin_group_notify_unbind(struct v4l2_async_notifier *notifier,
++				     struct v4l2_subdev *subdev,
++				     struct v4l2_async_subdev *asd)
++{
++	struct rvin_dev *vin = notifier_to_vin(notifier);
++	unsigned int i;
++
++	for (i = 0; i < RCAR_VIN_NUM; i++)
++		if (vin->group->vin[i])
++			rvin_v4l2_unregister(vin->group->vin[i]);
++
++	mutex_lock(&vin->group->lock);
++
++	for (i = 0; i < RVIN_CSI_MAX; i++) {
++		if (vin->group->csi[i].fwnode != asd->match.fwnode.fwnode)
++			continue;
++		vin->group->csi[i].subdev = NULL;
++		vin_dbg(vin, "Unbind CSI-2 %s from slot %u\n", subdev->name, i);
++		break;
++	}
++
++	mutex_unlock(&vin->group->lock);
++}
++
++static int rvin_group_notify_bound(struct v4l2_async_notifier *notifier,
++				   struct v4l2_subdev *subdev,
++				   struct v4l2_async_subdev *asd)
++{
++	struct rvin_dev *vin = notifier_to_vin(notifier);
++	unsigned int i;
++
++	mutex_lock(&vin->group->lock);
++
++	for (i = 0; i < RVIN_CSI_MAX; i++) {
++		if (vin->group->csi[i].fwnode != asd->match.fwnode.fwnode)
++			continue;
++		vin->group->csi[i].subdev = subdev;
++		vin_dbg(vin, "Bound CSI-2 %s to slot %u\n", subdev->name, i);
++		break;
++	}
++
++	mutex_unlock(&vin->group->lock);
++
++	return 0;
++}
++
++static const struct v4l2_async_notifier_operations rvin_group_notify_ops = {
++	.bound = rvin_group_notify_bound,
++	.unbind = rvin_group_notify_unbind,
++	.complete = rvin_group_notify_complete,
++};
++
++static int rvin_mc_parse_of_endpoint(struct device *dev,
++				     struct v4l2_fwnode_endpoint *vep,
++				     struct v4l2_async_subdev *asd)
++{
++	struct rvin_dev *vin = dev_get_drvdata(dev);
++
++	if (vep->base.port != 1 || vep->base.id >= RVIN_CSI_MAX)
++		return -EINVAL;
++
++	if (!of_device_is_available(to_of_node(asd->match.fwnode.fwnode))) {
++
++		vin_dbg(vin, "OF device %pOF disabled, ignoring\n",
++			to_of_node(asd->match.fwnode.fwnode));
++		return -ENOTCONN;
++
++	}
++
++	if (vin->group->csi[vep->base.id].fwnode) {
++		vin_dbg(vin, "OF device %pOF already handled\n",
++			to_of_node(asd->match.fwnode.fwnode));
++		return -ENOTCONN;
++	}
++
++	vin->group->csi[vep->base.id].fwnode = asd->match.fwnode.fwnode;
++
++	vin_dbg(vin, "Add group OF device %pOF to slot %u\n",
++		to_of_node(asd->match.fwnode.fwnode), vep->base.id);
++
++	return 0;
++}
++
++static int rvin_mc_parse_of_graph(struct rvin_dev *vin)
++{
++	unsigned int count = 0;
++	unsigned int i;
++	int ret;
++
++	mutex_lock(&vin->group->lock);
++
++	/* If there already is a notifier something has gone wrong, bail out. */
++	if (WARN_ON(vin->group->notifier)) {
++		mutex_unlock(&vin->group->lock);
++		return -EINVAL;
++	}
++
++	/* If not all VIN's are registered don't register the notifier. */
++	for (i = 0; i < RCAR_VIN_NUM; i++)
++		if (vin->group->vin[i])
++			count++;
++
++	if (vin->group->count != count) {
++		mutex_unlock(&vin->group->lock);
++		return 0;
++	}
++
++	/*
++	 * Have all VIN's look for subdevices. Some subdevices will overlap
++	 * but the parser function can handle it, so each subdevice will
++	 * only be registered once with the notifier.
++	 */
++
++	vin->group->notifier = &vin->notifier;
++
++	for (i = 0; i < RCAR_VIN_NUM; i++) {
++		if (!vin->group->vin[i])
++			continue;
++
++		ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
++				vin->group->vin[i]->dev, vin->group->notifier,
++				sizeof(struct v4l2_async_subdev), 1,
++				rvin_mc_parse_of_endpoint);
++		if (ret) {
++			mutex_unlock(&vin->group->lock);
++			return ret;
++		}
++	}
++
++	mutex_unlock(&vin->group->lock);
++
++	vin->group->notifier->ops = &rvin_group_notify_ops;
++
++	ret = v4l2_async_notifier_register(&vin->v4l2_dev, &vin->notifier);
++	if (ret < 0) {
++		vin_err(vin, "Notifier registration failed\n");
++		return ret;
++	}
++
++	return 0;
++}
++
+ static int rvin_mc_init(struct rvin_dev *vin)
+ {
+ 	int ret;
+@@ -422,7 +649,15 @@ static int rvin_mc_init(struct rvin_dev *vin)
+ 	if (ret)
+ 		return ret;
+ 
+-	return rvin_group_get(vin);
++	ret = rvin_group_get(vin);
++	if (ret)
++		return ret;
++
++	ret = rvin_mc_parse_of_graph(vin);
++	if (ret)
++		rvin_group_put(vin);
++
++	return ret;
+ }
+ 
+ /* -----------------------------------------------------------------------------
+@@ -542,10 +777,15 @@ static int rcar_vin_remove(struct platform_device *pdev)
+ 	v4l2_async_notifier_unregister(&vin->notifier);
+ 	v4l2_async_notifier_cleanup(&vin->notifier);
+ 
+-	if (vin->info->use_mc)
++	if (vin->info->use_mc) {
++		mutex_lock(&vin->group->lock);
++		if (vin->group->notifier == &vin->notifier)
++			vin->group->notifier = NULL;
++		mutex_unlock(&vin->group->lock);
+ 		rvin_group_put(vin);
+-	else
++	} else {
+ 		v4l2_ctrl_handler_free(&vin->ctrl_handler);
++	}
+ 
+ 	rvin_dma_unregister(vin);
+ 
+diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
+index 93eb40856b86..c2aef789b491 100644
+--- a/drivers/media/platform/rcar-vin/rcar-vin.h
++++ b/drivers/media/platform/rcar-vin/rcar-vin.h
+@@ -223,9 +223,13 @@ struct rvin_dev {
+  *
+  * @mdev:		media device which represents the group
+  *
+- * @lock:		protects the count and vin members
++ * @lock:		protects the count, notifier, vin and csi members
+  * @count:		number of enabled VIN instances found in DT
++ * @notifier:		pointer to the notifier of a VIN which handles the
++ *			groups async sub-devices.
+  * @vin:		VIN instances which are part of the group
++ * @csi:		array of pairs of fwnode and subdev pointers
++ *			to all CSI-2 subdevices.
+  */
+ struct rvin_group {
+ 	struct kref refcount;
+@@ -234,7 +238,13 @@ struct rvin_group {
+ 
+ 	struct mutex lock;
+ 	unsigned int count;
++	struct v4l2_async_notifier *notifier;
+ 	struct rvin_dev *vin[RCAR_VIN_NUM];
++
++	struct {
++		struct fwnode_handle *fwnode;
++		struct v4l2_subdev *subdev;
++	} csi[RVIN_CSI_MAX];
+ };
+ 
+ int rvin_dma_register(struct rvin_dev *vin, int irq);
+-- 
+2.19.0
+
diff --git a/patches/1308-media-rcar-vin-add-link-notify-for-Gen3.patch b/patches/1308-media-rcar-vin-add-link-notify-for-Gen3.patch
new file mode 100644
index 00000000000000..88ac7a7afce094
--- /dev/null
+++ b/patches/1308-media-rcar-vin-add-link-notify-for-Gen3.patch
@@ -0,0 +1,214 @@
+From 1fb261506d1ddba86a4e8ff5721d3ff3305dd528 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:22 -0400
+Subject: [PATCH 1308/1795] media: rcar-vin: add link notify for Gen3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the ability to process media device link change requests. Link
+enabling is a bit complicated on Gen3, whether or not it's possible to
+enable a link depends on what other links already are enabled. On Gen3
+the 8 VINs are split into two subgroup's (VIN0-3 and VIN4-7) and from a
+routing perspective these two groups are independent of each other.
+Each subgroup's routing is controlled by the subgroup VIN master
+instance (VIN0 and VIN4).
+
+There are a limited number of possible route setups available for each
+subgroup and the configuration of each setup is dictated by the
+hardware. On H3 for example there are 6 possible route setups for each
+subgroup to choose from.
+
+This leads to the media device link notification code being rather large
+since it will find the best routing configuration to try and accommodate
+as many links as possible. When it's not possible to enable a new link
+due to hardware constrains the link_notifier callback will return
+-EMLINK.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit c0cc5aef31704c824271b9c8043e7107acebc888)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 147 ++++++++++++++++++++
+ 1 file changed, 147 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 844606c7ab58..8f622b47d5c0 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -24,6 +24,7 @@
+ 
+ #include <media/v4l2-async.h>
+ #include <media/v4l2-fwnode.h>
++#include <media/v4l2-mc.h>
+ 
+ #include "rcar-vin.h"
+ 
+@@ -44,6 +45,151 @@
+  */
+ #define rvin_group_id_to_master(vin) ((vin) < 4 ? 0 : 4)
+ 
++/* -----------------------------------------------------------------------------
++ * Media Controller link notification
++ */
++
++/* group lock should be held when calling this function. */
++static int rvin_group_entity_to_csi_id(struct rvin_group *group,
++				       struct media_entity *entity)
++{
++	struct v4l2_subdev *sd;
++	unsigned int i;
++
++	sd = media_entity_to_v4l2_subdev(entity);
++
++	for (i = 0; i < RVIN_CSI_MAX; i++)
++		if (group->csi[i].subdev == sd)
++			return i;
++
++	return -ENODEV;
++}
++
++static unsigned int rvin_group_get_mask(struct rvin_dev *vin,
++					enum rvin_csi_id csi_id,
++					unsigned char channel)
++{
++	const struct rvin_group_route *route;
++	unsigned int mask = 0;
++
++	for (route = vin->info->routes; route->mask; route++) {
++		if (route->vin == vin->id &&
++		    route->csi == csi_id &&
++		    route->channel == channel) {
++			vin_dbg(vin,
++				"Adding route: vin: %d csi: %d channel: %d\n",
++				route->vin, route->csi, route->channel);
++			mask |= route->mask;
++		}
++	}
++
++	return mask;
++}
++
++/*
++ * Link setup for the links between a VIN and a CSI-2 receiver is a bit
++ * complex. The reason for this is that the register controlling routing
++ * is not present in each VIN instance. There are special VINs which
++ * control routing for themselves and other VINs. There are not many
++ * different possible links combinations that can be enabled at the same
++ * time, therefor all already enabled links which are controlled by a
++ * master VIN need to be taken into account when making the decision
++ * if a new link can be enabled or not.
++ *
++ * 1. Find out which VIN the link the user tries to enable is connected to.
++ * 2. Lookup which master VIN controls the links for this VIN.
++ * 3. Start with a bitmask with all bits set.
++ * 4. For each previously enabled link from the master VIN bitwise AND its
++ *    route mask (see documentation for mask in struct rvin_group_route)
++ *    with the bitmask.
++ * 5. Bitwise AND the mask for the link the user tries to enable to the bitmask.
++ * 6. If the bitmask is not empty at this point the new link can be enabled
++ *    while keeping all previous links enabled. Update the CHSEL value of the
++ *    master VIN and inform the user that the link could be enabled.
++ *
++ * Please note that no link can be enabled if any VIN in the group is
++ * currently open.
++ */
++static int rvin_group_link_notify(struct media_link *link, u32 flags,
++				  unsigned int notification)
++{
++	struct rvin_group *group = container_of(link->graph_obj.mdev,
++						struct rvin_group, mdev);
++	unsigned int master_id, channel, mask_new, i;
++	unsigned int mask = ~0;
++	struct media_entity *entity;
++	struct video_device *vdev;
++	struct media_pad *csi_pad;
++	struct rvin_dev *vin = NULL;
++	int csi_id, ret;
++
++	ret = v4l2_pipeline_link_notify(link, flags, notification);
++	if (ret)
++		return ret;
++
++	/* Only care about link enablement for VIN nodes. */
++	if (!(flags & MEDIA_LNK_FL_ENABLED) ||
++	    !is_media_entity_v4l2_video_device(link->sink->entity))
++		return 0;
++
++	/* If any entity is in use don't allow link changes. */
++	media_device_for_each_entity(entity, &group->mdev)
++		if (entity->use_count)
++			return -EBUSY;
++
++	mutex_lock(&group->lock);
++
++	/* Find the master VIN that controls the routes. */
++	vdev = media_entity_to_video_device(link->sink->entity);
++	vin = container_of(vdev, struct rvin_dev, vdev);
++	master_id = rvin_group_id_to_master(vin->id);
++
++	if (WARN_ON(!group->vin[master_id])) {
++		ret = -ENODEV;
++		goto out;
++	}
++
++	/* Build a mask for already enabled links. */
++	for (i = master_id; i < master_id + 4; i++) {
++		if (!group->vin[i])
++			continue;
++
++		/* Get remote CSI-2, if any. */
++		csi_pad = media_entity_remote_pad(
++				&group->vin[i]->vdev.entity.pads[0]);
++		if (!csi_pad)
++			continue;
++
++		csi_id = rvin_group_entity_to_csi_id(group, csi_pad->entity);
++		channel = rvin_group_csi_pad_to_channel(csi_pad->index);
++
++		mask &= rvin_group_get_mask(group->vin[i], csi_id, channel);
++	}
++
++	/* Add the new link to the existing mask and check if it works. */
++	csi_id = rvin_group_entity_to_csi_id(group, link->source->entity);
++	channel = rvin_group_csi_pad_to_channel(link->source->index);
++	mask_new = mask & rvin_group_get_mask(vin, csi_id, channel);
++
++	vin_dbg(vin, "Try link change mask: 0x%x new: 0x%x\n", mask, mask_new);
++
++	if (!mask_new) {
++		ret = -EMLINK;
++		goto out;
++	}
++
++	/* New valid CHSEL found, set the new value. */
++	ret = rvin_set_channel_routing(group->vin[master_id], __ffs(mask_new));
++out:
++	mutex_unlock(&group->lock);
++
++	return ret;
++}
++
++static const struct media_device_ops rvin_media_ops = {
++	.link_notify = rvin_group_link_notify,
++};
++
+ /* -----------------------------------------------------------------------------
+  * Gen3 CSI2 Group Allocator
+  */
+@@ -85,6 +231,7 @@ static int rvin_group_init(struct rvin_group *group, struct rvin_dev *vin)
+ 	vin_dbg(vin, "found %u enabled VIN's in DT", group->count);
+ 
+ 	mdev->dev = vin->dev;
++	mdev->ops = &rvin_media_ops;
+ 
+ 	match = of_match_node(vin->dev->driver->of_match_table,
+ 			      vin->dev->of_node);
+-- 
+2.19.0
+
diff --git a/patches/1309-media-rcar-vin-extend-start-stop-_streaming-to-work-.patch b/patches/1309-media-rcar-vin-extend-start-stop-_streaming-to-work-.patch
new file mode 100644
index 00000000000000..6839a2b875301e
--- /dev/null
+++ b/patches/1309-media-rcar-vin-extend-start-stop-_streaming-to-work-.patch
@@ -0,0 +1,209 @@
+From 7122d4fd6346567403b228288be4e7f58d143277 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:23 -0400
+Subject: [PATCH 1309/1795] media: rcar-vin: extend {start, stop}_streaming to
+ work with media controller
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The procedure to start or stop streaming using the non-MC single
+subdevice and the MC graph and multiple subdevices are quite different.
+Create a new function to abstract which method is used based on which
+mode the driver is running in and add logic to start the MC graph.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 7b7eb115322890bfbb813be00f65ae88bfe36ae2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 135 +++++++++++++++++++--
+ 1 file changed, 127 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index d70a689d9dd3..4a3a195e7f59 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -996,10 +996,126 @@ static void rvin_buffer_queue(struct vb2_buffer *vb)
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+ }
+ 
++static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
++				   struct media_pad *pad)
++{
++	struct v4l2_subdev_format fmt = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++
++	fmt.pad = pad->index;
++	if (v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt))
++		return -EPIPE;
++
++	switch (fmt.format.code) {
++	case MEDIA_BUS_FMT_YUYV8_1X16:
++	case MEDIA_BUS_FMT_UYVY8_2X8:
++	case MEDIA_BUS_FMT_UYVY10_2X10:
++	case MEDIA_BUS_FMT_RGB888_1X24:
++		vin->mbus_code = fmt.format.code;
++		break;
++	default:
++		return -EPIPE;
++	}
++
++	switch (fmt.format.field) {
++	case V4L2_FIELD_TOP:
++	case V4L2_FIELD_BOTTOM:
++	case V4L2_FIELD_NONE:
++	case V4L2_FIELD_INTERLACED_TB:
++	case V4L2_FIELD_INTERLACED_BT:
++	case V4L2_FIELD_INTERLACED:
++	case V4L2_FIELD_SEQ_TB:
++	case V4L2_FIELD_SEQ_BT:
++		/* Supported natively */
++		break;
++	case V4L2_FIELD_ALTERNATE:
++		switch (vin->format.field) {
++		case V4L2_FIELD_TOP:
++		case V4L2_FIELD_BOTTOM:
++		case V4L2_FIELD_NONE:
++			break;
++		case V4L2_FIELD_INTERLACED_TB:
++		case V4L2_FIELD_INTERLACED_BT:
++		case V4L2_FIELD_INTERLACED:
++		case V4L2_FIELD_SEQ_TB:
++		case V4L2_FIELD_SEQ_BT:
++			/* Use VIN hardware to combine the two fields */
++			fmt.format.height *= 2;
++			break;
++		default:
++			return -EPIPE;
++		}
++		break;
++	default:
++		return -EPIPE;
++	}
++
++	if (fmt.format.width != vin->format.width ||
++	    fmt.format.height != vin->format.height ||
++	    fmt.format.code != vin->mbus_code)
++		return -EPIPE;
++
++	return 0;
++}
++
++static int rvin_set_stream(struct rvin_dev *vin, int on)
++{
++	struct media_pipeline *pipe;
++	struct media_device *mdev;
++	struct v4l2_subdev *sd;
++	struct media_pad *pad;
++	int ret;
++
++	/* No media controller used, simply pass operation to subdevice. */
++	if (!vin->info->use_mc) {
++		ret = v4l2_subdev_call(vin->digital->subdev, video, s_stream,
++				       on);
++
++		return ret == -ENOIOCTLCMD ? 0 : ret;
++	}
++
++	pad = media_entity_remote_pad(&vin->pad);
++	if (!pad)
++		return -EPIPE;
++
++	sd = media_entity_to_v4l2_subdev(pad->entity);
++
++	if (!on) {
++		media_pipeline_stop(&vin->vdev.entity);
++		return v4l2_subdev_call(sd, video, s_stream, 0);
++	}
++
++	ret = rvin_mc_validate_format(vin, sd, pad);
++	if (ret)
++		return ret;
++
++	/*
++	 * The graph lock needs to be taken to protect concurrent
++	 * starts of multiple VIN instances as they might share
++	 * a common subdevice down the line and then should use
++	 * the same pipe.
++	 */
++	mdev = vin->vdev.entity.graph_obj.mdev;
++	mutex_lock(&mdev->graph_mutex);
++	pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe;
++	ret = __media_pipeline_start(&vin->vdev.entity, pipe);
++	mutex_unlock(&mdev->graph_mutex);
++	if (ret)
++		return ret;
++
++	ret = v4l2_subdev_call(sd, video, s_stream, 1);
++	if (ret == -ENOIOCTLCMD)
++		ret = 0;
++	if (ret)
++		media_pipeline_stop(&vin->vdev.entity);
++
++	return ret;
++}
++
+ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ {
+ 	struct rvin_dev *vin = vb2_get_drv_priv(vq);
+-	struct v4l2_subdev *sd;
+ 	unsigned long flags;
+ 	int ret;
+ 
+@@ -1014,8 +1130,13 @@ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 		return -ENOMEM;
+ 	}
+ 
+-	sd = vin_to_source(vin);
+-	v4l2_subdev_call(sd, video, s_stream, 1);
++	ret = rvin_set_stream(vin, 1);
++	if (ret) {
++		spin_lock_irqsave(&vin->qlock, flags);
++		return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
++		spin_unlock_irqrestore(&vin->qlock, flags);
++		goto out;
++	}
+ 
+ 	spin_lock_irqsave(&vin->qlock, flags);
+ 
+@@ -1024,11 +1145,11 @@ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ 	ret = rvin_capture_start(vin);
+ 	if (ret) {
+ 		return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
+-		v4l2_subdev_call(sd, video, s_stream, 0);
++		rvin_set_stream(vin, 0);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+-
++out:
+ 	if (ret)
+ 		dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
+ 				  vin->scratch_phys);
+@@ -1039,7 +1160,6 @@ static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+ static void rvin_stop_streaming(struct vb2_queue *vq)
+ {
+ 	struct rvin_dev *vin = vb2_get_drv_priv(vq);
+-	struct v4l2_subdev *sd;
+ 	unsigned long flags;
+ 	int retries = 0;
+ 
+@@ -1078,8 +1198,7 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
+ 
+ 	spin_unlock_irqrestore(&vin->qlock, flags);
+ 
+-	sd = vin_to_source(vin);
+-	v4l2_subdev_call(sd, video, s_stream, 0);
++	rvin_set_stream(vin, 0);
+ 
+ 	/* disable interrupts */
+ 	rvin_disable_interrupts(vin);
+-- 
+2.19.0
+
diff --git a/patches/1310-media-rcar-vin-enable-support-for-r8a7795.patch b/patches/1310-media-rcar-vin-enable-support-for-r8a7795.patch
new file mode 100644
index 00000000000000..970701902b353d
--- /dev/null
+++ b/patches/1310-media-rcar-vin-enable-support-for-r8a7795.patch
@@ -0,0 +1,197 @@
+From 00d12dde9473d501e9442bdc5389d5ae739af4eb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:24 -0400
+Subject: [PATCH 1310/1795] media: rcar-vin: enable support for r8a7795
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the SoC specific information for Renesas r8a7795 ES1.x and ES2.0.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 48ad6c2b551207588925937b6e969c7322247a26)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/Kconfig     |   2 +-
+ drivers/media/platform/rcar-vin/rcar-core.c | 120 ++++++++++++++++++++
+ 2 files changed, 121 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/rcar-vin/Kconfig b/drivers/media/platform/rcar-vin/Kconfig
+index af4c98b44d2e..8fa7ee468c63 100644
+--- a/drivers/media/platform/rcar-vin/Kconfig
++++ b/drivers/media/platform/rcar-vin/Kconfig
+@@ -6,7 +6,7 @@ config VIDEO_RCAR_VIN
+ 	select V4L2_FWNODE
+ 	---help---
+ 	  Support for Renesas R-Car Video Input (VIN) driver.
+-	  Supports R-Car Gen2 SoCs.
++	  Supports R-Car Gen2 and Gen3 SoCs.
+ 
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called rcar-vin.
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index 8f622b47d5c0..de7e1033e5d5 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -21,6 +21,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
++#include <linux/sys_soc.h>
+ 
+ #include <media/v4l2-async.h>
+ #include <media/v4l2-fwnode.h>
+@@ -832,6 +833,104 @@ static const struct rvin_info rcar_info_gen2 = {
+ 	.max_height = 2048,
+ };
+ 
++static const struct rvin_group_route rcar_info_r8a7795_routes[] = {
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
++	{ .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
++	{ .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
++	{ .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) },
++	{ .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
++	{ /* Sentinel */ }
++};
++
++static const struct rvin_info rcar_info_r8a7795 = {
++	.model = RCAR_GEN3,
++	.use_mc = true,
++	.max_width = 4096,
++	.max_height = 4096,
++	.routes = rcar_info_r8a7795_routes,
++};
++
++static const struct rvin_group_route rcar_info_r8a7795es1_routes[] = {
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 0, .mask = BIT(2) | BIT(5) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 1, .mask = BIT(1) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 1, .vin = 1, .mask = BIT(5) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 2, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 2, .vin = 2, .mask = BIT(5) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) },
++	{ .csi = RVIN_CSI21, .channel = 1, .vin = 3, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 3, .vin = 3, .mask = BIT(5) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 4, .mask = BIT(2) | BIT(5) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 5, .mask = BIT(1) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) },
++	{ .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 1, .vin = 5, .mask = BIT(5) },
++	{ .csi = RVIN_CSI21, .channel = 0, .vin = 6, .mask = BIT(0) },
++	{ .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
++	{ .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 2, .vin = 6, .mask = BIT(5) },
++	{ .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) },
++	{ .csi = RVIN_CSI21, .channel = 1, .vin = 7, .mask = BIT(2) },
++	{ .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
++	{ .csi = RVIN_CSI21, .channel = 3, .vin = 7, .mask = BIT(5) },
++	{ /* Sentinel */ }
++};
++
++static const struct rvin_info rcar_info_r8a7795es1 = {
++	.model = RCAR_GEN3,
++	.use_mc = true,
++	.max_width = 4096,
++	.max_height = 4096,
++	.routes = rcar_info_r8a7795es1_routes,
++};
++
+ static const struct of_device_id rvin_of_id_table[] = {
+ 	{
+ 		.compatible = "renesas,vin-r8a7778",
+@@ -861,12 +960,25 @@ static const struct of_device_id rvin_of_id_table[] = {
+ 		.compatible = "renesas,rcar-gen2-vin",
+ 		.data = &rcar_info_gen2,
+ 	},
++	{
++		.compatible = "renesas,vin-r8a7795",
++		.data = &rcar_info_r8a7795,
++	},
+ 	{ /* Sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, rvin_of_id_table);
+ 
++static const struct soc_device_attribute r8a7795es1[] = {
++	{
++		.soc_id = "r8a7795", .revision = "ES1.*",
++		.data = &rcar_info_r8a7795es1,
++	},
++	{ /* Sentinel */ }
++};
++
+ static int rcar_vin_probe(struct platform_device *pdev)
+ {
++	const struct soc_device_attribute *attr;
+ 	struct rvin_dev *vin;
+ 	struct resource *mem;
+ 	int irq, ret;
+@@ -878,6 +990,14 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	vin->dev = &pdev->dev;
+ 	vin->info = of_device_get_match_data(&pdev->dev);
+ 
++	/*
++	 * Special care is needed on r8a7795 ES1.x since it
++	 * uses different routing than r8a7795 ES2.0.
++	 */
++	attr = soc_device_match(r8a7795es1);
++	if (attr)
++		vin->info = attr->data;
++
+ 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (mem == NULL)
+ 		return -EINVAL;
+-- 
+2.19.0
+
diff --git a/patches/1311-media-rcar-vin-enable-support-for-r8a7796.patch b/patches/1311-media-rcar-vin-enable-support-for-r8a7796.patch
new file mode 100644
index 00000000000000..5e5cba4af38766
--- /dev/null
+++ b/patches/1311-media-rcar-vin-enable-support-for-r8a7796.patch
@@ -0,0 +1,87 @@
+From 01451b19e704e6e6289f749b8ca452974c0bb7a5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:25 -0400
+Subject: [PATCH 1311/1795] media: rcar-vin: enable support for r8a7796
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the SoC specific information for Renesas r8a7796.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 2f42acf84d1c5d9bc7fa1247dd0e2e87de6969e0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 44 +++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index de7e1033e5d5..ac4d5dd4b580 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -931,6 +931,46 @@ static const struct rvin_info rcar_info_r8a7795es1 = {
+ 	.routes = rcar_info_r8a7795es1_routes,
+ };
+ 
++static const struct rvin_group_route rcar_info_r8a7796_routes[] = {
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) },
++	{ .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) },
++	{ .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) },
++	{ .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) },
++	{ .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) },
++	{ .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
++	{ /* Sentinel */ }
++};
++
++static const struct rvin_info rcar_info_r8a7796 = {
++	.model = RCAR_GEN3,
++	.use_mc = true,
++	.max_width = 4096,
++	.max_height = 4096,
++	.routes = rcar_info_r8a7796_routes,
++};
++
+ static const struct of_device_id rvin_of_id_table[] = {
+ 	{
+ 		.compatible = "renesas,vin-r8a7778",
+@@ -964,6 +1004,10 @@ static const struct of_device_id rvin_of_id_table[] = {
+ 		.compatible = "renesas,vin-r8a7795",
+ 		.data = &rcar_info_r8a7795,
+ 	},
++	{
++		.compatible = "renesas,vin-r8a7796",
++		.data = &rcar_info_r8a7796,
++	},
+ 	{ /* Sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, rvin_of_id_table);
+-- 
+2.19.0
+
diff --git a/patches/1312-media-rcar-vin-enable-support-for-r8a77970.patch b/patches/1312-media-rcar-vin-enable-support-for-r8a77970.patch
new file mode 100644
index 00000000000000..dcea429ab152f7
--- /dev/null
+++ b/patches/1312-media-rcar-vin-enable-support-for-r8a77970.patch
@@ -0,0 +1,66 @@
+From 52df94dce56ee79f6cc30b3bd7f6638237e82fd2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Sat, 14 Apr 2018 07:57:26 -0400
+Subject: [PATCH 1312/1795] media: rcar-vin: enable support for r8a77970
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the SoC specific information for Renesas r8a77970.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
+(cherry picked from commit 2e1cd38dc3ccd7b8721e1e03160012b56f1e6042)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 23 +++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index ac4d5dd4b580..dd903a9e650a 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -971,6 +971,25 @@ static const struct rvin_info rcar_info_r8a7796 = {
+ 	.routes = rcar_info_r8a7796_routes,
+ };
+ 
++static const struct rvin_group_route _rcar_info_r8a77970_routes[] = {
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) },
++	{ .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
++	{ .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
++	{ .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
++	{ .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
++	{ /* Sentinel */ }
++};
++
++static const struct rvin_info rcar_info_r8a77970 = {
++	.model = RCAR_GEN3,
++	.use_mc = true,
++	.max_width = 4096,
++	.max_height = 4096,
++	.routes = _rcar_info_r8a77970_routes,
++};
++
+ static const struct of_device_id rvin_of_id_table[] = {
+ 	{
+ 		.compatible = "renesas,vin-r8a7778",
+@@ -1008,6 +1027,10 @@ static const struct of_device_id rvin_of_id_table[] = {
+ 		.compatible = "renesas,vin-r8a7796",
+ 		.data = &rcar_info_r8a7796,
+ 	},
++	{
++		.compatible = "renesas,vin-r8a77970",
++		.data = &rcar_info_r8a77970,
++	},
+ 	{ /* Sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, rvin_of_id_table);
+-- 
+2.19.0
+
diff --git a/patches/1313-media-rcar-vin-remove-generic-gen3-compatible-string.patch b/patches/1313-media-rcar-vin-remove-generic-gen3-compatible-string.patch
new file mode 100644
index 00000000000000..962b4cbd60d2d9
--- /dev/null
+++ b/patches/1313-media-rcar-vin-remove-generic-gen3-compatible-string.patch
@@ -0,0 +1,42 @@
+From e417aa928869b4bd46e83429ef76825a3b319bec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 24 Apr 2018 19:43:21 -0400
+Subject: [PATCH 1313/1795] media: rcar-vin: remove generic gen3 compatible
+ string
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The compatible string "renesas,rcar-gen3-vin" was added before the
+Gen3 driver code was added but it's not possible to use. Each SoC in the
+Gen3 series require SoC specific knowledge in the driver to function.
+Remove it before it is added to any device tree descriptions.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit ec2b0d04631748a799ded5f15926846c712062cb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/media/rcar_vin.txt | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
+index 67b312ff924b..e28a41c76633 100644
+--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
++++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
+@@ -24,7 +24,6 @@ on Gen3 platforms to a CSI-2 receiver.
+    - "renesas,vin-r8a77970" for the R8A77970 device
+    - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
+      device.
+-   - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
+ 
+    When compatible with the generic version nodes must list the
+    SoC-specific version corresponding to the platform first
+-- 
+2.19.0
+
diff --git a/patches/1314-media-rcar-vin-fix-null-pointer-dereference-in-rvin_.patch b/patches/1314-media-rcar-vin-fix-null-pointer-dereference-in-rvin_.patch
new file mode 100644
index 00000000000000..4c15d71ca06a3e
--- /dev/null
+++ b/patches/1314-media-rcar-vin-fix-null-pointer-dereference-in-rvin_.patch
@@ -0,0 +1,59 @@
+From dba9a66944c89f8d9f9c888ea8e27174df38753b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 24 Apr 2018 19:45:06 -0400
+Subject: [PATCH 1314/1795] media: rcar-vin: fix null pointer dereference in
+ rvin_group_get()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Store the group pointer before disassociating the VIN from the group.
+
+Fixes: 3bb4c3bc85bf77a7 ("media: rcar-vin: add group allocator functions")
+
+Reported-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 16cedd99c64cc9f128a3e9bb0613980833b7f938)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index dd903a9e650a..a75104766c90 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -338,19 +338,21 @@ static int rvin_group_get(struct rvin_dev *vin)
+ 
+ static void rvin_group_put(struct rvin_dev *vin)
+ {
+-	mutex_lock(&vin->group->lock);
++	struct rvin_group *group = vin->group;
++
++	mutex_lock(&group->lock);
+ 
+ 	vin->group = NULL;
+ 	vin->v4l2_dev.mdev = NULL;
+ 
+-	if (WARN_ON(vin->group->vin[vin->id] != vin))
++	if (WARN_ON(group->vin[vin->id] != vin))
+ 		goto out;
+ 
+-	vin->group->vin[vin->id] = NULL;
++	group->vin[vin->id] = NULL;
+ out:
+-	mutex_unlock(&vin->group->lock);
++	mutex_unlock(&group->lock);
+ 
+-	kref_put(&vin->group->refcount, rvin_group_release);
++	kref_put(&group->refcount, rvin_group_release);
+ }
+ 
+ /* -----------------------------------------------------------------------------
+-- 
+2.19.0
+
diff --git a/patches/1315-media-rcar-vin-add-support-for-MEDIA_BUS_FMT_UYVY8_1.patch b/patches/1315-media-rcar-vin-add-support-for-MEDIA_BUS_FMT_UYVY8_1.patch
new file mode 100644
index 00000000000000..5f1cf9e850ea1e
--- /dev/null
+++ b/patches/1315-media-rcar-vin-add-support-for-MEDIA_BUS_FMT_UYVY8_1.patch
@@ -0,0 +1,62 @@
+From 66d97be13bcde9bb635b5f930e3ec4c673e1b8d0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 24 Apr 2018 19:46:07 -0400
+Subject: [PATCH 1315/1795] media: rcar-vin: add support for
+ MEDIA_BUS_FMT_UYVY8_1X16
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+By setting VNMC_YCAL rcar-vin can support input video in
+MEDIA_BUS_FMT_UYVY8_1X16 format.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 01d72e9d06082666c34ec4b033f61007e47490d9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-core.c | 1 +
+ drivers/media/platform/rcar-vin/rcar-dma.c  | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
+index a75104766c90..378a16ad3a55 100644
+--- a/drivers/media/platform/rcar-vin/rcar-core.c
++++ b/drivers/media/platform/rcar-vin/rcar-core.c
+@@ -406,6 +406,7 @@ static int rvin_digital_subdevice_attach(struct rvin_dev *vin,
+ 		code.index++;
+ 		switch (code.code) {
+ 		case MEDIA_BUS_FMT_YUYV8_1X16:
++		case MEDIA_BUS_FMT_UYVY8_1X16:
+ 		case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		case MEDIA_BUS_FMT_UYVY10_2X10:
+ 		case MEDIA_BUS_FMT_RGB888_1X24:
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index 4a3a195e7f59..ac07f99e3516 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -653,6 +653,10 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		vnmc |= VNMC_INF_YUV16;
+ 		input_is_yuv = true;
+ 		break;
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++		vnmc |= VNMC_INF_YUV16 | VNMC_YCAL;
++		input_is_yuv = true;
++		break;
+ 	case MEDIA_BUS_FMT_UYVY8_2X8:
+ 		/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
+ 		vnmc |= vin->mbus_cfg.type == V4L2_MBUS_BT656 ?
+@@ -1009,6 +1013,7 @@ static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
+ 
+ 	switch (fmt.format.code) {
+ 	case MEDIA_BUS_FMT_YUYV8_1X16:
++	case MEDIA_BUS_FMT_UYVY8_1X16:
+ 	case MEDIA_BUS_FMT_UYVY8_2X8:
+ 	case MEDIA_BUS_FMT_UYVY10_2X10:
+ 	case MEDIA_BUS_FMT_RGB888_1X24:
+-- 
+2.19.0
+
diff --git a/patches/1316-media-rcar-vin-enable-field-toggle-after-a-set-numbe.patch b/patches/1316-media-rcar-vin-enable-field-toggle-after-a-set-numbe.patch
new file mode 100644
index 00000000000000..e07f398921069c
--- /dev/null
+++ b/patches/1316-media-rcar-vin-enable-field-toggle-after-a-set-numbe.patch
@@ -0,0 +1,101 @@
+From 1d67718dbadd0645908184e6471e361ba87b402a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 24 Apr 2018 19:56:52 -0400
+Subject: [PATCH 1316/1795] media: rcar-vin: enable field toggle after a set
+ number of lines for Gen3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The VIN Gen3 hardware don't have Line Post-Clip capabilities as VIN Gen2
+hardware have. To protect against writing outside the capture window
+enable field toggle after a set number of lines have been captured.
+
+Capturing outside the allocated capture buffer where observed on R-Car
+Gen3 Salvator-XS H3 from the CVBS input if the standard is
+misconfigured. That is if a PAL source is connected to the system but
+the adv748x standard is set to NTSC. In this case the format reported by
+the adv748x is 720x480 and that is what is used for the media pipeline.
+The PAL source generates frames in the format of 720x576 and the field
+is not toggled until the VSYNC is detected and at that time data have
+already been written outside the allocated capture buffer.
+
+With this change the capture in the situation described above results in
+garbage frames but that is far better then writing outside the capture
+buffer.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 015060cb7795eac34454696cc9c9f8b76926a401)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 20 +++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index ac07f99e3516..b41ba9a4a2b3 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -124,7 +124,9 @@
+ #define VNDMR2_VPS		(1 << 30)
+ #define VNDMR2_HPS		(1 << 29)
+ #define VNDMR2_FTEV		(1 << 17)
++#define VNDMR2_FTEH		(1 << 16)
+ #define VNDMR2_VLV(n)		((n & 0xf) << 12)
++#define VNDMR2_HLV(n)		((n) & 0xfff)
+ 
+ /* Video n CSI2 Interface Mode Register (Gen3) */
+ #define VNCSI_IFMD_DES1		(1 << 26)
+@@ -612,8 +614,9 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ 
+ static int rvin_setup(struct rvin_dev *vin)
+ {
+-	u32 vnmc, dmr, dmr2, interrupts;
++	u32 vnmc, dmr, dmr2, interrupts, lines;
+ 	bool progressive = false, output_is_yuv = false, input_is_yuv = false;
++	bool halfsize = false;
+ 
+ 	switch (vin->format.field) {
+ 	case V4L2_FIELD_TOP:
+@@ -628,12 +631,15 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		/* Use BT if video standard can be read and is 60 Hz format */
+ 		if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
+ 			vnmc = VNMC_IM_FULL | VNMC_FOC;
++		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_TB:
+ 		vnmc = VNMC_IM_FULL;
++		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_BT:
+ 		vnmc = VNMC_IM_FULL | VNMC_FOC;
++		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_NONE:
+ 		vnmc = VNMC_IM_ODD_EVEN;
+@@ -676,11 +682,15 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	}
+ 
+-	/* Enable VSYNC Field Toogle mode after one VSYNC input */
+-	if (vin->info->model == RCAR_GEN3)
+-		dmr2 = VNDMR2_FTEV;
+-	else
++	if (vin->info->model == RCAR_GEN3) {
++		/* Enable HSYNC Field Toggle mode after height HSYNC inputs. */
++		lines = vin->format.height / (halfsize ? 2 : 1);
++		dmr2 = VNDMR2_FTEH | VNDMR2_HLV(lines);
++		vin_dbg(vin, "Field Toogle after %u lines\n", lines);
++	} else {
++		/* Enable VSYNC Field Toogle mode after one VSYNC input. */
+ 		dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
++	}
+ 
+ 	/* Hsync Signal Polarity Select */
+ 	if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+-- 
+2.19.0
+
diff --git a/patches/1317-media-Revert-media-rcar-vin-enable-field-toggle-afte.patch b/patches/1317-media-Revert-media-rcar-vin-enable-field-toggle-afte.patch
new file mode 100644
index 00000000000000..2a344fe59865ec
--- /dev/null
+++ b/patches/1317-media-Revert-media-rcar-vin-enable-field-toggle-afte.patch
@@ -0,0 +1,92 @@
+From e6aa4f336a7e51045bb0fb75e0d45bb5c80ba21b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 11 May 2018 10:41:25 -0400
+Subject: [PATCH 1317/1795] media: Revert "media: rcar-vin: enable field toggle
+ after a set number of lines for Gen3"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The offending commit was an attempt to fix the issue of writing outside
+the capture buffer for VIN Gen3. Unfortunately it only fixed the symptom
+of the problem to such a degree I could no longer reproduce it. Revert
+the offending commit before a proper fix can be added in a follow-up
+patch.
+
+This reverts commit 015060cb7795eac34454696cc9c9f8b76926a401.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Hans Verkuil <hansverk@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit d73c3357c8a844d108083f4df2837adab9ebb265)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-dma.c | 20 +++++---------------
+ 1 file changed, 5 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
+index b41ba9a4a2b3..ac07f99e3516 100644
+--- a/drivers/media/platform/rcar-vin/rcar-dma.c
++++ b/drivers/media/platform/rcar-vin/rcar-dma.c
+@@ -124,9 +124,7 @@
+ #define VNDMR2_VPS		(1 << 30)
+ #define VNDMR2_HPS		(1 << 29)
+ #define VNDMR2_FTEV		(1 << 17)
+-#define VNDMR2_FTEH		(1 << 16)
+ #define VNDMR2_VLV(n)		((n & 0xf) << 12)
+-#define VNDMR2_HLV(n)		((n) & 0xfff)
+ 
+ /* Video n CSI2 Interface Mode Register (Gen3) */
+ #define VNCSI_IFMD_DES1		(1 << 26)
+@@ -614,9 +612,8 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
+ 
+ static int rvin_setup(struct rvin_dev *vin)
+ {
+-	u32 vnmc, dmr, dmr2, interrupts, lines;
++	u32 vnmc, dmr, dmr2, interrupts;
+ 	bool progressive = false, output_is_yuv = false, input_is_yuv = false;
+-	bool halfsize = false;
+ 
+ 	switch (vin->format.field) {
+ 	case V4L2_FIELD_TOP:
+@@ -631,15 +628,12 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		/* Use BT if video standard can be read and is 60 Hz format */
+ 		if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
+ 			vnmc = VNMC_IM_FULL | VNMC_FOC;
+-		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_TB:
+ 		vnmc = VNMC_IM_FULL;
+-		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_INTERLACED_BT:
+ 		vnmc = VNMC_IM_FULL | VNMC_FOC;
+-		halfsize = true;
+ 		break;
+ 	case V4L2_FIELD_NONE:
+ 		vnmc = VNMC_IM_ODD_EVEN;
+@@ -682,15 +676,11 @@ static int rvin_setup(struct rvin_dev *vin)
+ 		break;
+ 	}
+ 
+-	if (vin->info->model == RCAR_GEN3) {
+-		/* Enable HSYNC Field Toggle mode after height HSYNC inputs. */
+-		lines = vin->format.height / (halfsize ? 2 : 1);
+-		dmr2 = VNDMR2_FTEH | VNDMR2_HLV(lines);
+-		vin_dbg(vin, "Field Toogle after %u lines\n", lines);
+-	} else {
+-		/* Enable VSYNC Field Toogle mode after one VSYNC input. */
++	/* Enable VSYNC Field Toogle mode after one VSYNC input */
++	if (vin->info->model == RCAR_GEN3)
++		dmr2 = VNDMR2_FTEV;
++	else
+ 		dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
+-	}
+ 
+ 	/* Hsync Signal Polarity Select */
+ 	if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+-- 
+2.19.0
+
diff --git a/patches/1318-media-rcar-vin-fix-crop-and-compose-handling-for-Gen.patch b/patches/1318-media-rcar-vin-fix-crop-and-compose-handling-for-Gen.patch
new file mode 100644
index 00000000000000..57b43514a43624
--- /dev/null
+++ b/patches/1318-media-rcar-vin-fix-crop-and-compose-handling-for-Gen.patch
@@ -0,0 +1,48 @@
+From ee5669e8ecc94500e3b4658ef2e1263e4547b1cb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 11 May 2018 10:41:26 -0400
+Subject: [PATCH 1318/1795] media: rcar-vin: fix crop and compose handling for
+ Gen3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When refactoring the Gen3 enablement series crop and compose handling
+where broken. This went unnoticed but can result in writing out side the
+capture buffer. Fix this by restoring the crop and compose to reflect
+the format dimensions as we have not yet enabled the scaler for Gen3.
+
+Fixes: 5e7c623632fcf8f5 ("media: rcar-vin: use different v4l2 operations in media controller mode")
+
+Reported-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Hans Verkuil <hansverk@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 3997716898a90954e00e4a5d5f1eacb94fbc41d9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-v4l2.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+index 2fb8587116f2..e78fba84d590 100644
+--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
++++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
+@@ -702,6 +702,12 @@ static int rvin_mc_s_fmt_vid_cap(struct file *file, void *priv,
+ 
+ 	vin->format = f->fmt.pix;
+ 
++	vin->crop.top = 0;
++	vin->crop.left = 0;
++	vin->crop.width = vin->format.width;
++	vin->crop.height = vin->format.height;
++	vin->compose = vin->crop;
++
+ 	return 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1319-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch b/patches/1319-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
new file mode 100644
index 00000000000000..4e2ec08998d0e4
--- /dev/null
+++ b/patches/1319-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
@@ -0,0 +1,158 @@
+From efe7f291cfb4964416b15353ef7d3ffecd44b185 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Mon, 14 May 2018 20:56:34 -0400
+Subject: [PATCH 1319/1795] media: rcar-csi2: add Renesas R-Car MIPI CSI-2
+ receiver documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Documentation for Renesas R-Car MIPI CSI-2 receiver. The CSI-2 receivers
+are located between the video sources (CSI-2 transmitters) and the video
+grabbers (VIN) on Gen3 of Renesas R-Car SoC.
+
+Each CSI-2 device is connected to more than one VIN device which
+simultaneously can receive video from the same CSI-2 device. Each VIN
+device can also be connected to more than one CSI-2 device. The routing
+of which links are used is controlled by the VIN devices. There are only
+a few possible routes which are set by hardware limitations, which are
+different for each SoC in the Gen3 family.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 385c83ebc36baa117702a15ba584c65d0e15b4bf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/media/renesas,rcar-csi2.txt      | 101 ++++++++++++++++++
+ MAINTAINERS                                   |   1 +
+ 2 files changed, 102 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt
+
+diff --git a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt
+new file mode 100644
+index 000000000000..2d385b65b275
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt
+@@ -0,0 +1,101 @@
++Renesas R-Car MIPI CSI-2
++------------------------
++
++The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
++Renesas R-Car family of devices. It is used in conjunction with the
++R-Car VIN module, which provides the video capture capabilities.
++
++Mandatory properties
++--------------------
++ - compatible: Must be one or more of the following
++   - "renesas,r8a7795-csi2" for the R8A7795 device.
++   - "renesas,r8a7796-csi2" for the R8A7796 device.
++   - "renesas,r8a77965-csi2" for the R8A77965 device.
++   - "renesas,r8a77970-csi2" for the R8A77970 device.
++
++ - reg: the register base and size for the device registers
++ - interrupts: the interrupt for the device
++ - clocks: reference to the parent clock
++
++The device node shall contain two 'port' child nodes according to the
++bindings defined in Documentation/devicetree/bindings/media/
++video-interfaces.txt. port@0 shall connect to the CSI-2 source. port@1
++shall connect to all the R-Car VIN modules that have a hardware
++connection to the CSI-2 receiver.
++
++- port@0- Video source (mandatory)
++	- endpoint@0 - sub-node describing the endpoint that is the video source
++
++- port@1 - VIN instances (optional)
++	- One endpoint sub-node for every R-Car VIN instance which is connected
++	  to the R-Car CSI-2 receiver.
++
++Example:
++
++	csi20: csi2@fea80000 {
++		compatible = "renesas,r8a7796-csi2";
++		reg = <0 0xfea80000 0 0x10000>;
++		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 714>;
++		power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++		resets = <&cpg 714>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				reg = <0>;
++
++				csi20_in: endpoint@0 {
++					reg = <0>;
++					clock-lanes = <0>;
++					data-lanes = <1>;
++					remote-endpoint = <&adv7482_txb>;
++				};
++			};
++
++			port@1 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				reg = <1>;
++
++				csi20vin0: endpoint@0 {
++					reg = <0>;
++					remote-endpoint = <&vin0csi20>;
++				};
++				csi20vin1: endpoint@1 {
++					reg = <1>;
++					remote-endpoint = <&vin1csi20>;
++				};
++				csi20vin2: endpoint@2 {
++					reg = <2>;
++					remote-endpoint = <&vin2csi20>;
++				};
++				csi20vin3: endpoint@3 {
++					reg = <3>;
++					remote-endpoint = <&vin3csi20>;
++				};
++				csi20vin4: endpoint@4 {
++					reg = <4>;
++					remote-endpoint = <&vin4csi20>;
++				};
++				csi20vin5: endpoint@5 {
++					reg = <5>;
++					remote-endpoint = <&vin5csi20>;
++				};
++				csi20vin6: endpoint@6 {
++					reg = <6>;
++					remote-endpoint = <&vin6csi20>;
++				};
++				csi20vin7: endpoint@7 {
++					reg = <7>;
++					remote-endpoint = <&vin7csi20>;
++				};
++			};
++		};
++	};
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 8fec63f3fcbc..e2d8f38a5091 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -8544,6 +8544,7 @@ L:	linux-media@vger.kernel.org
+ L:	linux-renesas-soc@vger.kernel.org
+ T:	git git://linuxtv.org/media_tree.git
+ S:	Supported
++F:	Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt
+ F:	Documentation/devicetree/bindings/media/rcar_vin.txt
+ F:	drivers/media/platform/rcar-vin/
+ 
+-- 
+2.19.0
+
diff --git a/patches/1320-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch b/patches/1320-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
new file mode 100644
index 00000000000000..2507d7c8fa8480
--- /dev/null
+++ b/patches/1320-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
@@ -0,0 +1,1157 @@
+From 0755dbe03a2e677a246b77efecb61fb225666b5e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Mon, 14 May 2018 20:56:35 -0400
+Subject: [PATCH 1320/1795] media: rcar-csi2: add Renesas R-Car MIPI CSI-2
+ receiver driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+A V4L2 driver for Renesas R-Car MIPI CSI-2 receiver. The driver
+supports the R-Car Gen3 SoCs where separate CSI-2 hardware blocks are
+connected between the video sources and the video grabbers (VIN).
+
+Driver is based on a prototype by Koji Matsuoka in the Renesas BSP.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 769afd212b160df7b041e9fa8f97ca498ef94d55)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts
+	drivers/media/platform/rcar-vin/rcar-csi2.c
+---
+ drivers/media/platform/rcar-vin/Kconfig     |   12 +
+ drivers/media/platform/rcar-vin/Makefile    |    1 +
+ drivers/media/platform/rcar-vin/rcar-csi2.c | 1085 +++++++++++++++++++
+ 3 files changed, 1098 insertions(+)
+ create mode 100644 drivers/media/platform/rcar-vin/rcar-csi2.c
+
+diff --git a/drivers/media/platform/rcar-vin/Kconfig b/drivers/media/platform/rcar-vin/Kconfig
+index 8fa7ee468c63..d5835da6d410 100644
+--- a/drivers/media/platform/rcar-vin/Kconfig
++++ b/drivers/media/platform/rcar-vin/Kconfig
+@@ -1,3 +1,15 @@
++config VIDEO_RCAR_CSI2
++	tristate "R-Car MIPI CSI-2 Receiver"
++	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
++	depends on ARCH_RENESAS || COMPILE_TEST
++	select V4L2_FWNODE
++	help
++	  Support for Renesas R-Car MIPI CSI-2 receiver.
++	  Supports R-Car Gen3 SoCs.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called rcar-csi2.
++
+ config VIDEO_RCAR_VIN
+ 	tristate "R-Car Video Input (VIN) Driver"
+ 	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF && HAS_DMA && MEDIA_CONTROLLER
+diff --git a/drivers/media/platform/rcar-vin/Makefile b/drivers/media/platform/rcar-vin/Makefile
+index 48c5632c21dc..5ab803d3e7c1 100644
+--- a/drivers/media/platform/rcar-vin/Makefile
++++ b/drivers/media/platform/rcar-vin/Makefile
+@@ -1,3 +1,4 @@
+ rcar-vin-objs = rcar-core.o rcar-dma.o rcar-v4l2.o
+ 
++obj-$(CONFIG_VIDEO_RCAR_CSI2) += rcar-csi2.o
+ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vin.o
+diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c
+new file mode 100644
+index 000000000000..5272399accc0
+--- /dev/null
++++ b/drivers/media/platform/rcar-vin/rcar-csi2.c
+@@ -0,0 +1,1085 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for Renesas R-Car MIPI CSI-2 Receiver
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_graph.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/sys_soc.h>
++
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-mc.h>
++#include <media/v4l2-subdev.h>
++
++struct rcar_csi2;
++
++/* Register offsets and bits */
++
++/* Control Timing Select */
++#define TREF_REG			0x00
++#define TREF_TREF			BIT(0)
++
++/* Software Reset */
++#define SRST_REG			0x04
++#define SRST_SRST			BIT(0)
++
++/* PHY Operation Control */
++#define PHYCNT_REG			0x08
++#define PHYCNT_SHUTDOWNZ		BIT(17)
++#define PHYCNT_RSTZ			BIT(16)
++#define PHYCNT_ENABLECLK		BIT(4)
++#define PHYCNT_ENABLE_3			BIT(3)
++#define PHYCNT_ENABLE_2			BIT(2)
++#define PHYCNT_ENABLE_1			BIT(1)
++#define PHYCNT_ENABLE_0			BIT(0)
++
++/* Checksum Control */
++#define CHKSUM_REG			0x0c
++#define CHKSUM_ECC_EN			BIT(1)
++#define CHKSUM_CRC_EN			BIT(0)
++
++/*
++ * Channel Data Type Select
++ * VCDT[0-15]:  Channel 1 VCDT[16-31]:  Channel 2
++ * VCDT2[0-15]: Channel 3 VCDT2[16-31]: Channel 4
++ */
++#define VCDT_REG			0x10
++#define VCDT2_REG			0x14
++#define VCDT_VCDTN_EN			BIT(15)
++#define VCDT_SEL_VC(n)			(((n) & 0x3) << 8)
++#define VCDT_SEL_DTN_ON			BIT(6)
++#define VCDT_SEL_DT(n)			(((n) & 0x3f) << 0)
++
++/* Frame Data Type Select */
++#define FRDT_REG			0x18
++
++/* Field Detection Control */
++#define FLD_REG				0x1c
++#define FLD_FLD_NUM(n)			(((n) & 0xff) << 16)
++#define FLD_FLD_EN4			BIT(3)
++#define FLD_FLD_EN3			BIT(2)
++#define FLD_FLD_EN2			BIT(1)
++#define FLD_FLD_EN			BIT(0)
++
++/* Automatic Standby Control */
++#define ASTBY_REG			0x20
++
++/* Long Data Type Setting 0 */
++#define LNGDT0_REG			0x28
++
++/* Long Data Type Setting 1 */
++#define LNGDT1_REG			0x2c
++
++/* Interrupt Enable */
++#define INTEN_REG			0x30
++
++/* Interrupt Source Mask */
++#define INTCLOSE_REG			0x34
++
++/* Interrupt Status Monitor */
++#define INTSTATE_REG			0x38
++#define INTSTATE_INT_ULPS_START		BIT(7)
++#define INTSTATE_INT_ULPS_END		BIT(6)
++
++/* Interrupt Error Status Monitor */
++#define INTERRSTATE_REG			0x3c
++
++/* Short Packet Data */
++#define SHPDAT_REG			0x40
++
++/* Short Packet Count */
++#define SHPCNT_REG			0x44
++
++/* LINK Operation Control */
++#define LINKCNT_REG			0x48
++#define LINKCNT_MONITOR_EN		BIT(31)
++#define LINKCNT_REG_MONI_PACT_EN	BIT(25)
++#define LINKCNT_ICLK_NONSTOP		BIT(24)
++
++/* Lane Swap */
++#define LSWAP_REG			0x4c
++#define LSWAP_L3SEL(n)			(((n) & 0x3) << 6)
++#define LSWAP_L2SEL(n)			(((n) & 0x3) << 4)
++#define LSWAP_L1SEL(n)			(((n) & 0x3) << 2)
++#define LSWAP_L0SEL(n)			(((n) & 0x3) << 0)
++
++/* PHY Test Interface Write Register */
++#define PHTW_REG			0x50
++#define PHTW_DWEN			BIT(24)
++#define PHTW_TESTDIN_DATA(n)		(((n & 0xff)) << 16)
++#define PHTW_CWEN			BIT(8)
++#define PHTW_TESTDIN_CODE(n)		((n & 0xff))
++
++struct phtw_value {
++	u16 data;
++	u16 code;
++};
++
++struct rcsi2_mbps_reg {
++	u16 mbps;
++	u16 reg;
++};
++
++static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
++	{ .mbps =   80, .reg = 0x86 },
++	{ .mbps =   90, .reg = 0x86 },
++	{ .mbps =  100, .reg = 0x87 },
++	{ .mbps =  110, .reg = 0x87 },
++	{ .mbps =  120, .reg = 0x88 },
++	{ .mbps =  130, .reg = 0x88 },
++	{ .mbps =  140, .reg = 0x89 },
++	{ .mbps =  150, .reg = 0x89 },
++	{ .mbps =  160, .reg = 0x8a },
++	{ .mbps =  170, .reg = 0x8a },
++	{ .mbps =  180, .reg = 0x8b },
++	{ .mbps =  190, .reg = 0x8b },
++	{ .mbps =  205, .reg = 0x8c },
++	{ .mbps =  220, .reg = 0x8d },
++	{ .mbps =  235, .reg = 0x8e },
++	{ .mbps =  250, .reg = 0x8e },
++	{ /* sentinel */ },
++};
++
++static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
++	{ .mbps =   80, .reg = 0x00 },
++	{ .mbps =   90, .reg = 0x20 },
++	{ .mbps =  100, .reg = 0x40 },
++	{ .mbps =  110, .reg = 0x02 },
++	{ .mbps =  130, .reg = 0x22 },
++	{ .mbps =  140, .reg = 0x42 },
++	{ .mbps =  150, .reg = 0x04 },
++	{ .mbps =  170, .reg = 0x24 },
++	{ .mbps =  180, .reg = 0x44 },
++	{ .mbps =  200, .reg = 0x06 },
++	{ .mbps =  220, .reg = 0x26 },
++	{ .mbps =  240, .reg = 0x46 },
++	{ .mbps =  250, .reg = 0x08 },
++	{ .mbps =  270, .reg = 0x28 },
++	{ .mbps =  300, .reg = 0x0a },
++	{ .mbps =  330, .reg = 0x2a },
++	{ .mbps =  360, .reg = 0x4a },
++	{ .mbps =  400, .reg = 0x0c },
++	{ .mbps =  450, .reg = 0x2c },
++	{ .mbps =  500, .reg = 0x0e },
++	{ .mbps =  550, .reg = 0x2e },
++	{ .mbps =  600, .reg = 0x10 },
++	{ .mbps =  650, .reg = 0x30 },
++	{ .mbps =  700, .reg = 0x12 },
++	{ .mbps =  750, .reg = 0x32 },
++	{ .mbps =  800, .reg = 0x52 },
++	{ .mbps =  850, .reg = 0x72 },
++	{ .mbps =  900, .reg = 0x14 },
++	{ .mbps =  950, .reg = 0x34 },
++	{ .mbps = 1000, .reg = 0x54 },
++	{ .mbps = 1050, .reg = 0x74 },
++	{ .mbps = 1125, .reg = 0x16 },
++	{ /* sentinel */ },
++};
++
++/* PHY Test Interface Clear */
++#define PHTC_REG			0x58
++#define PHTC_TESTCLR			BIT(0)
++
++/* PHY Frequency Control */
++#define PHYPLL_REG			0x68
++#define PHYPLL_HSFREQRANGE(n)		((n) << 16)
++
++static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
++	{ .mbps =   80, .reg = 0x00 },
++	{ .mbps =   90, .reg = 0x10 },
++	{ .mbps =  100, .reg = 0x20 },
++	{ .mbps =  110, .reg = 0x30 },
++	{ .mbps =  120, .reg = 0x01 },
++	{ .mbps =  130, .reg = 0x11 },
++	{ .mbps =  140, .reg = 0x21 },
++	{ .mbps =  150, .reg = 0x31 },
++	{ .mbps =  160, .reg = 0x02 },
++	{ .mbps =  170, .reg = 0x12 },
++	{ .mbps =  180, .reg = 0x22 },
++	{ .mbps =  190, .reg = 0x32 },
++	{ .mbps =  205, .reg = 0x03 },
++	{ .mbps =  220, .reg = 0x13 },
++	{ .mbps =  235, .reg = 0x23 },
++	{ .mbps =  250, .reg = 0x33 },
++	{ .mbps =  275, .reg = 0x04 },
++	{ .mbps =  300, .reg = 0x14 },
++	{ .mbps =  325, .reg = 0x25 },
++	{ .mbps =  350, .reg = 0x35 },
++	{ .mbps =  400, .reg = 0x05 },
++	{ .mbps =  450, .reg = 0x16 },
++	{ .mbps =  500, .reg = 0x26 },
++	{ .mbps =  550, .reg = 0x37 },
++	{ .mbps =  600, .reg = 0x07 },
++	{ .mbps =  650, .reg = 0x18 },
++	{ .mbps =  700, .reg = 0x28 },
++	{ .mbps =  750, .reg = 0x39 },
++	{ .mbps =  800, .reg = 0x09 },
++	{ .mbps =  850, .reg = 0x19 },
++	{ .mbps =  900, .reg = 0x29 },
++	{ .mbps =  950, .reg = 0x3a },
++	{ .mbps = 1000, .reg = 0x0a },
++	{ .mbps = 1050, .reg = 0x1a },
++	{ .mbps = 1100, .reg = 0x2a },
++	{ .mbps = 1150, .reg = 0x3b },
++	{ .mbps = 1200, .reg = 0x0b },
++	{ .mbps = 1250, .reg = 0x1b },
++	{ .mbps = 1300, .reg = 0x2b },
++	{ .mbps = 1350, .reg = 0x3c },
++	{ .mbps = 1400, .reg = 0x0c },
++	{ .mbps = 1450, .reg = 0x1c },
++	{ .mbps = 1500, .reg = 0x2c },
++	{ /* sentinel */ },
++};
++
++static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
++	{ .mbps =   80,	.reg = 0x00 },
++	{ .mbps =   90,	.reg = 0x10 },
++	{ .mbps =  100,	.reg = 0x20 },
++	{ .mbps =  110,	.reg = 0x30 },
++	{ .mbps =  120,	.reg = 0x01 },
++	{ .mbps =  130,	.reg = 0x11 },
++	{ .mbps =  140,	.reg = 0x21 },
++	{ .mbps =  150,	.reg = 0x31 },
++	{ .mbps =  160,	.reg = 0x02 },
++	{ .mbps =  170,	.reg = 0x12 },
++	{ .mbps =  180,	.reg = 0x22 },
++	{ .mbps =  190,	.reg = 0x32 },
++	{ .mbps =  205,	.reg = 0x03 },
++	{ .mbps =  220,	.reg = 0x13 },
++	{ .mbps =  235,	.reg = 0x23 },
++	{ .mbps =  250,	.reg = 0x33 },
++	{ .mbps =  275,	.reg = 0x04 },
++	{ .mbps =  300,	.reg = 0x14 },
++	{ .mbps =  325,	.reg = 0x05 },
++	{ .mbps =  350,	.reg = 0x15 },
++	{ .mbps =  400,	.reg = 0x25 },
++	{ .mbps =  450,	.reg = 0x06 },
++	{ .mbps =  500,	.reg = 0x16 },
++	{ .mbps =  550,	.reg = 0x07 },
++	{ .mbps =  600,	.reg = 0x17 },
++	{ .mbps =  650,	.reg = 0x08 },
++	{ .mbps =  700,	.reg = 0x18 },
++	{ .mbps =  750,	.reg = 0x09 },
++	{ .mbps =  800,	.reg = 0x19 },
++	{ .mbps =  850,	.reg = 0x29 },
++	{ .mbps =  900,	.reg = 0x39 },
++	{ .mbps =  950,	.reg = 0x0a },
++	{ .mbps = 1000,	.reg = 0x1a },
++	{ .mbps = 1050,	.reg = 0x2a },
++	{ .mbps = 1100,	.reg = 0x3a },
++	{ .mbps = 1150,	.reg = 0x0b },
++	{ .mbps = 1200,	.reg = 0x1b },
++	{ .mbps = 1250,	.reg = 0x2b },
++	{ .mbps = 1300,	.reg = 0x3b },
++	{ .mbps = 1350,	.reg = 0x0c },
++	{ .mbps = 1400,	.reg = 0x1c },
++	{ .mbps = 1450,	.reg = 0x2c },
++	{ .mbps = 1500,	.reg = 0x3c },
++	{ /* sentinel */ },
++};
++
++/* PHY ESC Error Monitor */
++#define PHEERM_REG			0x74
++
++/* PHY Clock Lane Monitor */
++#define PHCLM_REG			0x78
++#define PHCLM_STOPSTATECKL		BIT(0)
++
++/* PHY Data Lane Monitor */
++#define PHDLM_REG			0x7c
++
++/* CSI0CLK Frequency Configuration Preset Register */
++#define CSI0CLKFCPR_REG			0x260
++#define CSI0CLKFREQRANGE(n)		((n & 0x3f) << 16)
++
++struct rcar_csi2_format {
++	u32 code;
++	unsigned int datatype;
++	unsigned int bpp;
++};
++
++static const struct rcar_csi2_format rcar_csi2_formats[] = {
++	{ .code = MEDIA_BUS_FMT_RGB888_1X24,	.datatype = 0x24, .bpp = 24 },
++	{ .code = MEDIA_BUS_FMT_UYVY8_1X16,	.datatype = 0x1e, .bpp = 16 },
++	{ .code = MEDIA_BUS_FMT_YUYV8_1X16,	.datatype = 0x1e, .bpp = 16 },
++	{ .code = MEDIA_BUS_FMT_UYVY8_2X8,	.datatype = 0x1e, .bpp = 16 },
++	{ .code = MEDIA_BUS_FMT_YUYV10_2X10,	.datatype = 0x1e, .bpp = 20 },
++};
++
++static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
++{
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
++		if (rcar_csi2_formats[i].code == code)
++			return &rcar_csi2_formats[i];
++
++	return NULL;
++}
++
++enum rcar_csi2_pads {
++	RCAR_CSI2_SINK,
++	RCAR_CSI2_SOURCE_VC0,
++	RCAR_CSI2_SOURCE_VC1,
++	RCAR_CSI2_SOURCE_VC2,
++	RCAR_CSI2_SOURCE_VC3,
++	NR_OF_RCAR_CSI2_PAD,
++};
++
++struct rcar_csi2_info {
++	int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
++	const struct rcsi2_mbps_reg *hsfreqrange;
++	unsigned int csi0clkfreqrange;
++	bool clear_ulps;
++};
++
++struct rcar_csi2 {
++	struct device *dev;
++	void __iomem *base;
++	const struct rcar_csi2_info *info;
++
++	struct v4l2_subdev subdev;
++	struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
++
++	struct v4l2_async_notifier notifier;
++	struct v4l2_async_subdev asd;
++	struct v4l2_subdev *remote;
++
++	struct v4l2_mbus_framefmt mf;
++
++	struct mutex lock;
++	int stream_count;
++
++	unsigned short lanes;
++	unsigned char lane_swap[4];
++};
++
++static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct rcar_csi2, subdev);
++}
++
++static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
++{
++	return container_of(n, struct rcar_csi2, notifier);
++}
++
++static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
++{
++	return ioread32(priv->base + reg);
++}
++
++static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
++{
++	iowrite32(data, priv->base + reg);
++}
++
++static void rcsi2_reset(struct rcar_csi2 *priv)
++{
++	rcsi2_write(priv, SRST_REG, SRST_SRST);
++	usleep_range(100, 150);
++	rcsi2_write(priv, SRST_REG, 0);
++}
++
++static int rcsi2_wait_phy_start(struct rcar_csi2 *priv)
++{
++	unsigned int timeout;
++
++	/* Wait for the clock and data lanes to enter LP-11 state. */
++	for (timeout = 0; timeout <= 20; timeout++) {
++		const u32 lane_mask = (1 << priv->lanes) - 1;
++
++		if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL)  &&
++		    (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
++			return 0;
++
++		usleep_range(1000, 2000);
++	}
++
++	dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
++
++	return -ETIMEDOUT;
++}
++
++static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
++{
++	const struct rcsi2_mbps_reg *hsfreq;
++
++	for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
++		if (hsfreq->mbps >= mbps)
++			break;
++
++	if (!hsfreq->mbps) {
++		dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
++		return -ERANGE;
++	}
++
++	rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
++
++	return 0;
++}
++
++static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp)
++{
++	struct v4l2_subdev *source;
++	struct v4l2_ctrl *ctrl;
++	u64 mbps;
++
++	if (!priv->remote)
++		return -ENODEV;
++
++	source = priv->remote;
++
++	/* Read the pixel rate control from remote. */
++	ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
++	if (!ctrl) {
++		dev_err(priv->dev, "no pixel rate control in subdev %s\n",
++			source->name);
++		return -EINVAL;
++	}
++
++	/*
++	 * Calculate the phypll in mbps.
++	 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
++	 * bps = link_freq * 2
++	 */
++	mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
++	do_div(mbps, priv->lanes * 1000000);
++
++	return mbps;
++}
++
++static int rcsi2_start(struct rcar_csi2 *priv)
++{
++	const struct rcar_csi2_format *format;
++	u32 phycnt, vcdt = 0, vcdt2 = 0;
++	unsigned int i;
++	int mbps, ret;
++
++	dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
++		priv->mf.width, priv->mf.height,
++		priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
++
++	/* Code is validated in set_fmt. */
++	format = rcsi2_code_to_fmt(priv->mf.code);
++
++	/*
++	 * Enable all Virtual Channels.
++	 *
++	 * NOTE: It's not possible to get individual datatype for each
++	 *       source virtual channel. Once this is possible in V4L2
++	 *       it should be used here.
++	 */
++	for (i = 0; i < 4; i++) {
++		u32 vcdt_part;
++
++		vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
++			VCDT_SEL_DT(format->datatype);
++
++		/* Store in correct reg and offset. */
++		if (i < 2)
++			vcdt |= vcdt_part << ((i % 2) * 16);
++		else
++			vcdt2 |= vcdt_part << ((i % 2) * 16);
++	}
++
++	phycnt = PHYCNT_ENABLECLK;
++	phycnt |= (1 << priv->lanes) - 1;
++
++	mbps = rcsi2_calc_mbps(priv, format->bpp);
++	if (mbps < 0)
++		return mbps;
++
++	/* Init */
++	rcsi2_write(priv, TREF_REG, TREF_TREF);
++	rcsi2_reset(priv);
++	rcsi2_write(priv, PHTC_REG, 0);
++
++	/* Configure */
++	rcsi2_write(priv, FLD_REG, FLD_FLD_NUM(2) | FLD_FLD_EN4 |
++		    FLD_FLD_EN3 | FLD_FLD_EN2 | FLD_FLD_EN);
++	rcsi2_write(priv, VCDT_REG, vcdt);
++	rcsi2_write(priv, VCDT2_REG, vcdt2);
++	/* Lanes are zero indexed. */
++	rcsi2_write(priv, LSWAP_REG,
++		    LSWAP_L0SEL(priv->lane_swap[0] - 1) |
++		    LSWAP_L1SEL(priv->lane_swap[1] - 1) |
++		    LSWAP_L2SEL(priv->lane_swap[2] - 1) |
++		    LSWAP_L3SEL(priv->lane_swap[3] - 1));
++
++	/* Start */
++	if (priv->info->init_phtw) {
++		ret = priv->info->init_phtw(priv, mbps);
++		if (ret)
++			return ret;
++	}
++
++	if (priv->info->hsfreqrange) {
++		ret = rcsi2_set_phypll(priv, mbps);
++		if (ret)
++			return ret;
++	}
++
++	if (priv->info->csi0clkfreqrange)
++		rcsi2_write(priv, CSI0CLKFCPR_REG,
++			    CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
++
++	rcsi2_write(priv, PHYCNT_REG, phycnt);
++	rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
++		    LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
++	rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
++	rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
++
++	ret = rcsi2_wait_phy_start(priv);
++	if (ret)
++		return ret;
++
++	/* Clear Ultra Low Power interrupt. */
++	if (priv->info->clear_ulps)
++		rcsi2_write(priv, INTSTATE_REG,
++			    INTSTATE_INT_ULPS_START |
++			    INTSTATE_INT_ULPS_END);
++	return 0;
++}
++
++static void rcsi2_stop(struct rcar_csi2 *priv)
++{
++	rcsi2_write(priv, PHYCNT_REG, 0);
++
++	rcsi2_reset(priv);
++
++	rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
++}
++
++static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct rcar_csi2 *priv = sd_to_csi2(sd);
++	struct v4l2_subdev *nextsd;
++	int ret = 0;
++
++	mutex_lock(&priv->lock);
++
++	if (!priv->remote) {
++		ret = -ENODEV;
++		goto out;
++	}
++
++	nextsd = priv->remote;
++
++	if (enable && priv->stream_count == 0) {
++		pm_runtime_get_sync(priv->dev);
++
++		ret = rcsi2_start(priv);
++		if (ret) {
++			pm_runtime_put(priv->dev);
++			goto out;
++		}
++
++		ret = v4l2_subdev_call(nextsd, video, s_stream, 1);
++		if (ret) {
++			rcsi2_stop(priv);
++			pm_runtime_put(priv->dev);
++			goto out;
++		}
++	} else if (!enable && priv->stream_count == 1) {
++		rcsi2_stop(priv);
++		v4l2_subdev_call(nextsd, video, s_stream, 0);
++		pm_runtime_put(priv->dev);
++	}
++
++	priv->stream_count += enable ? 1 : -1;
++out:
++	mutex_unlock(&priv->lock);
++
++	return ret;
++}
++
++static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
++				struct v4l2_subdev_pad_config *cfg,
++				struct v4l2_subdev_format *format)
++{
++	struct rcar_csi2 *priv = sd_to_csi2(sd);
++	struct v4l2_mbus_framefmt *framefmt;
++
++	if (!rcsi2_code_to_fmt(format->format.code))
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
++		priv->mf = format->format;
++	} else {
++		framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
++		*framefmt = format->format;
++	}
++
++	return 0;
++}
++
++static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
++				struct v4l2_subdev_pad_config *cfg,
++				struct v4l2_subdev_format *format)
++{
++	struct rcar_csi2 *priv = sd_to_csi2(sd);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		format->format = priv->mf;
++	else
++		format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
++
++	return 0;
++}
++
++static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
++	.s_stream = rcsi2_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
++	.set_fmt = rcsi2_set_pad_format,
++	.get_fmt = rcsi2_get_pad_format,
++};
++
++static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
++	.video	= &rcar_csi2_video_ops,
++	.pad	= &rcar_csi2_pad_ops,
++};
++
++/* -----------------------------------------------------------------------------
++ * Async handling and registration of subdevices and links.
++ */
++
++static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
++			      struct v4l2_subdev *subdev,
++			      struct v4l2_async_subdev *asd)
++{
++	struct rcar_csi2 *priv = notifier_to_csi2(notifier);
++	int pad;
++
++	pad = media_entity_get_fwnode_pad(&subdev->entity,
++					  asd->match.fwnode.fwnode,
++					  MEDIA_PAD_FL_SOURCE);
++	if (pad < 0) {
++		dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
++		return pad;
++	}
++
++	priv->remote = subdev;
++
++	dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
++
++	return media_create_pad_link(&subdev->entity, pad,
++				     &priv->subdev.entity, 0,
++				     MEDIA_LNK_FL_ENABLED |
++				     MEDIA_LNK_FL_IMMUTABLE);
++}
++
++static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
++				struct v4l2_subdev *subdev,
++				struct v4l2_async_subdev *asd)
++{
++	struct rcar_csi2 *priv = notifier_to_csi2(notifier);
++
++	priv->remote = NULL;
++
++	dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
++}
++
++static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
++	.bound = rcsi2_notify_bound,
++	.unbind = rcsi2_notify_unbind,
++};
++
++static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
++			    struct v4l2_fwnode_endpoint *vep)
++{
++	unsigned int i;
++
++	/* Only port 0 endpoint 0 is valid. */
++	if (vep->base.port || vep->base.id)
++		return -ENOTCONN;
++
++	if (vep->bus_type != V4L2_MBUS_CSI2) {
++		dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
++		return -EINVAL;
++	}
++
++	priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
++	if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
++		dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
++			priv->lanes);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
++		priv->lane_swap[i] = i < priv->lanes ?
++			vep->bus.mipi_csi2.data_lanes[i] : i;
++
++		/* Check for valid lane number. */
++		if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
++			dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int rcsi2_parse_dt(struct rcar_csi2 *priv)
++{
++	struct device_node *ep;
++	struct v4l2_fwnode_endpoint v4l2_ep;
++	int ret;
++
++	ep = of_graph_get_endpoint_by_regs(priv->dev->of_node, 0, 0);
++	if (!ep) {
++		dev_err(priv->dev, "Not connected to subdevice\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
++	if (ret) {
++		dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
++		of_node_put(ep);
++		return -EINVAL;
++	}
++
++	ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
++	if (ret) {
++		of_node_put(ep);
++		return ret;
++	}
++
++	priv->asd.match.fwnode.fwnode =
++		fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep));
++	priv->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
++
++	of_node_put(ep);
++
++	priv->notifier.subdevs = devm_kzalloc(priv->dev,
++					      sizeof(*priv->notifier.subdevs),
++					      GFP_KERNEL);
++	if (!priv->notifier.subdevs)
++		return -ENOMEM;
++
++	priv->notifier.num_subdevs = 1;
++	priv->notifier.subdevs[0] = &priv->asd;
++	priv->notifier.ops = &rcar_csi2_notify_ops;
++
++	dev_dbg(priv->dev, "Found '%pOF'\n",
++		to_of_node(priv->asd.match.fwnode.fwnode));
++
++	return v4l2_async_subdev_notifier_register(&priv->subdev,
++						   &priv->notifier);
++}
++
++/* -----------------------------------------------------------------------------
++ * PHTW initialization sequences.
++ *
++ * NOTE: Magic values are from the datasheet and lack documentation.
++ */
++
++static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
++{
++	unsigned int timeout;
++
++	rcsi2_write(priv, PHTW_REG,
++		    PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
++		    PHTW_CWEN | PHTW_TESTDIN_CODE(code));
++
++	/* Wait for DWEN and CWEN to be cleared by hardware. */
++	for (timeout = 0; timeout <= 20; timeout++) {
++		if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
++			return 0;
++
++		usleep_range(1000, 2000);
++	}
++
++	dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
++
++	return -ETIMEDOUT;
++}
++
++static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
++				  const struct phtw_value *values)
++{
++	const struct phtw_value *value;
++	int ret;
++
++	for (value = values; value->data || value->code; value++) {
++		ret = rcsi2_phtw_write(priv, value->data, value->code);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
++				 const struct rcsi2_mbps_reg *values, u16 code)
++{
++	const struct rcsi2_mbps_reg *value;
++
++	for (value = values; value->mbps; value++)
++		if (value->mbps >= mbps)
++			break;
++
++	if (!value->mbps) {
++		dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
++		return -ERANGE;
++	}
++
++	return rcsi2_phtw_write(priv, value->reg, code);
++}
++
++static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
++{
++	static const struct phtw_value step1[] = {
++		{ .data = 0xcc, .code = 0xe2 },
++		{ .data = 0x01, .code = 0xe3 },
++		{ .data = 0x11, .code = 0xe4 },
++		{ .data = 0x01, .code = 0xe5 },
++		{ .data = 0x10, .code = 0x04 },
++		{ /* sentinel */ },
++	};
++
++	static const struct phtw_value step2[] = {
++		{ .data = 0x38, .code = 0x08 },
++		{ .data = 0x01, .code = 0x00 },
++		{ .data = 0x4b, .code = 0xac },
++		{ .data = 0x03, .code = 0x00 },
++		{ .data = 0x80, .code = 0x07 },
++		{ /* sentinel */ },
++	};
++
++	int ret;
++
++	ret = rcsi2_phtw_write_array(priv, step1);
++	if (ret)
++		return ret;
++
++	if (mbps <= 250) {
++		ret = rcsi2_phtw_write(priv, 0x39, 0x05);
++		if (ret)
++			return ret;
++
++		ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
++					    0xf1);
++		if (ret)
++			return ret;
++	}
++
++	return rcsi2_phtw_write_array(priv, step2);
++}
++
++static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
++{
++	static const struct phtw_value step1[] = {
++		{ .data = 0xed, .code = 0x34 },
++		{ .data = 0xed, .code = 0x44 },
++		{ .data = 0xed, .code = 0x54 },
++		{ .data = 0xed, .code = 0x84 },
++		{ .data = 0xed, .code = 0x94 },
++		{ /* sentinel */ },
++	};
++
++	int ret;
++
++	ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
++	if (ret)
++		return ret;
++
++	return rcsi2_phtw_write_array(priv, step1);
++}
++
++/* -----------------------------------------------------------------------------
++ * Platform Device Driver.
++ */
++
++static const struct media_entity_operations rcar_csi2_entity_ops = {
++	.link_validate = v4l2_subdev_link_validate,
++};
++
++static int rcsi2_probe_resources(struct rcar_csi2 *priv,
++				 struct platform_device *pdev)
++{
++	struct resource *res;
++	int irq;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	priv->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(priv->base))
++		return PTR_ERR(priv->base);
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return irq;
++
++	return 0;
++}
++
++static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
++	.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
++	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
++	.csi0clkfreqrange = 0x20,
++	.clear_ulps = true,
++};
++
++static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
++	.hsfreqrange = hsfreqrange_m3w_h3es1,
++};
++
++static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
++	.hsfreqrange = hsfreqrange_m3w_h3es1,
++};
++
++static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
++	.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
++	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
++	.csi0clkfreqrange = 0x20,
++	.clear_ulps = true,
++};
++
++static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
++	.init_phtw = rcsi2_init_phtw_v3m_e3,
++};
++
++static const struct of_device_id rcar_csi2_of_table[] = {
++	{
++		.compatible = "renesas,r8a7795-csi2",
++		.data = &rcar_csi2_info_r8a7795,
++	},
++	{
++		.compatible = "renesas,r8a7796-csi2",
++		.data = &rcar_csi2_info_r8a7796,
++	},
++	{
++		.compatible = "renesas,r8a77965-csi2",
++		.data = &rcar_csi2_info_r8a77965,
++	},
++	{
++		.compatible = "renesas,r8a77970-csi2",
++		.data = &rcar_csi2_info_r8a77970,
++	},
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
++
++static const struct soc_device_attribute r8a7795es1[] = {
++	{
++		.soc_id = "r8a7795", .revision = "ES1.*",
++		.data = &rcar_csi2_info_r8a7795es1,
++	},
++	{ /* sentinel */ },
++};
++
++static int rcsi2_probe(struct platform_device *pdev)
++{
++	const struct soc_device_attribute *attr;
++	struct rcar_csi2 *priv;
++	unsigned int i;
++	int ret;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->info = of_device_get_match_data(&pdev->dev);
++
++	/*
++	 * r8a7795 ES1.x behaves differently than the ES2.0+ but doesn't
++	 * have it's own compatible string.
++	 */
++	attr = soc_device_match(r8a7795es1);
++	if (attr)
++		priv->info = attr->data;
++
++	priv->dev = &pdev->dev;
++
++	mutex_init(&priv->lock);
++	priv->stream_count = 0;
++
++	ret = rcsi2_probe_resources(priv, pdev);
++	if (ret) {
++		dev_err(priv->dev, "Failed to get resources\n");
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, priv);
++
++	ret = rcsi2_parse_dt(priv);
++	if (ret)
++		return ret;
++
++	priv->subdev.owner = THIS_MODULE;
++	priv->subdev.dev = &pdev->dev;
++	v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
++	v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
++	snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
++		 KBUILD_MODNAME, dev_name(&pdev->dev));
++	priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
++	priv->subdev.entity.ops = &rcar_csi2_entity_ops;
++
++	priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
++	for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
++		priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
++				     priv->pads);
++	if (ret)
++		goto error;
++
++	pm_runtime_enable(&pdev->dev);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto error;
++
++	dev_info(priv->dev, "%d lanes found\n", priv->lanes);
++
++	return 0;
++
++error:
++	v4l2_async_notifier_unregister(&priv->notifier);
++	v4l2_async_notifier_cleanup(&priv->notifier);
++
++	return ret;
++}
++
++static int rcsi2_remove(struct platform_device *pdev)
++{
++	struct rcar_csi2 *priv = platform_get_drvdata(pdev);
++
++	v4l2_async_notifier_unregister(&priv->notifier);
++	v4l2_async_notifier_cleanup(&priv->notifier);
++	v4l2_async_unregister_subdev(&priv->subdev);
++
++	pm_runtime_disable(&pdev->dev);
++
++	return 0;
++}
++
++static struct platform_driver rcar_csi2_pdrv = {
++	.remove	= rcsi2_remove,
++	.probe	= rcsi2_probe,
++	.driver	= {
++		.name	= "rcar-csi2",
++		.of_match_table	= rcar_csi2_of_table,
++	},
++};
++
++module_platform_driver(rcar_csi2_pdrv);
++
++MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
++MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
++MODULE_LICENSE("GPL");
+-- 
+2.19.0
+
diff --git a/patches/1321-media-rcar-csi2-set-default-format-if-a-unsupported-.patch b/patches/1321-media-rcar-csi2-set-default-format-if-a-unsupported-.patch
new file mode 100644
index 00000000000000..6f75ecd5070730
--- /dev/null
+++ b/patches/1321-media-rcar-csi2-set-default-format-if-a-unsupported-.patch
@@ -0,0 +1,40 @@
+From ec6cc6f7880c2a495bdde9070f095b63dfbd8709 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 19:04:33 -0400
+Subject: [PATCH 1321/1795] media: rcar-csi2: set default format if a
+ unsupported one is requested
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Instead of failing the set_fmt() if a unsupported format is requested
+set a default one and return the changed format to the user.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reported-by: Sakari Ailus <sakari.ailus@iki.fi>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 7be8c4f7da9722ff7bf878cd75fa8bf54f1e821a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/rcar-vin/rcar-csi2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c
+index 5272399accc0..6e961336f52c 100644
+--- a/drivers/media/platform/rcar-vin/rcar-csi2.c
++++ b/drivers/media/platform/rcar-vin/rcar-csi2.c
+@@ -613,7 +613,7 @@ static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
+ 	struct v4l2_mbus_framefmt *framefmt;
+ 
+ 	if (!rcsi2_code_to_fmt(format->format.code))
+-		return -EINVAL;
++		format->format.code = rcar_csi2_formats[0].code;
+ 
+ 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ 		priv->mf = format->format;
+-- 
+2.19.0
+
diff --git a/patches/1322-drm-Fix-modifiers_property-kernel-doc.patch b/patches/1322-drm-Fix-modifiers_property-kernel-doc.patch
new file mode 100644
index 00000000000000..15adf9fd157cf2
--- /dev/null
+++ b/patches/1322-drm-Fix-modifiers_property-kernel-doc.patch
@@ -0,0 +1,41 @@
+From d2f0dcd44e8b2e2daf1e64e859a62f0e856e9c32 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 24 Aug 2017 22:10:58 +0300
+Subject: [PATCH 1322/1795] drm: Fix modifiers_property kernel doc
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The member is called 'modifiers_property' instead of 'modifiers'. Adjust
+the kernel docs to match.
+
+Cc: dri-devel@lists.freedesktop.org
+Cc: Ben Widawsky <ben@bwidawsk.net>
+Cc: Jason Ekstrand <jason@jlekstrand.net>
+Cc: Daniel Stone <daniels@collabora.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170824191100.10949-11-ville.syrjala@linux.intel.com
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit dadcc5e02f675947b22bfd2df14dbf77f6888613)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/drm/drm_mode_config.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
+index 1b37368416c8..6040c4b73e6d 100644
+--- a/include/drm/drm_mode_config.h
++++ b/include/drm/drm_mode_config.h
+@@ -758,7 +758,7 @@ struct drm_mode_config {
+ 	bool allow_fb_modifiers;
+ 
+ 	/**
+-	 * @modifiers: Plane property to list support modifier/format
++	 * @modifiers_property: Plane property to list support modifier/format
+ 	 * combination.
+ 	 */
+ 	struct drm_property *modifiers_property;
+-- 
+2.19.0
+
diff --git a/patches/1323-drm-Add-drm_mode_config-normalize_zpos-boolean.patch b/patches/1323-drm-Add-drm_mode_config-normalize_zpos-boolean.patch
new file mode 100644
index 00000000000000..04febd118c1a43
--- /dev/null
+++ b/patches/1323-drm-Add-drm_mode_config-normalize_zpos-boolean.patch
@@ -0,0 +1,87 @@
+From 83607894a4e378ea2cd7ea06e1f099c39d639502 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Wed, 21 Mar 2018 12:20:24 +0200
+Subject: [PATCH 1323/1795] drm: Add drm_mode_config->normalize_zpos boolean
+
+Instead of drivers duplicating the drm_atomic_helper_check() code to be
+able to normalize the zpos they can use the normalize_zpos flag to let the
+drm core to do it.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180321102029.15248-2-peter.ujfalusi@ti.com
+(cherry picked from commit 49efffc7fbd48d5ea3d0dd60c218c7502d4a179d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/drm_atomic_helper.c | 11 +++++++++++
+ include/drm/drm_mode_config.h       |  8 ++++++++
+ include/drm/drm_plane.h             |  4 ++--
+ 3 files changed, 21 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
+index ca3e44daa4b3..e5b6d2a2a4f8 100644
+--- a/drivers/gpu/drm/drm_atomic_helper.c
++++ b/drivers/gpu/drm/drm_atomic_helper.c
+@@ -873,6 +873,11 @@ EXPORT_SYMBOL(drm_atomic_helper_check_planes);
+  * functions depend upon an updated adjusted_mode.clock to e.g. properly compute
+  * watermarks.
+  *
++ * Note that zpos normalization will add all enable planes to the state which
++ * might not desired for some drivers.
++ * For example enable/disable of a cursor plane which have fixed zpos value
++ * would trigger all other enabled planes to be forced to the state change.
++ *
+  * RETURNS:
+  * Zero for success or -errno
+  */
+@@ -885,6 +890,12 @@ int drm_atomic_helper_check(struct drm_device *dev,
+ 	if (ret)
+ 		return ret;
+ 
++	if (dev->mode_config.normalize_zpos) {
++		ret = drm_atomic_normalize_zpos(dev, state);
++		if (ret)
++			return ret;
++	}
++
+ 	ret = drm_atomic_helper_check_planes(dev, state);
+ 	if (ret)
+ 		return ret;
+diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
+index 6040c4b73e6d..e09bc98e0b75 100644
+--- a/include/drm/drm_mode_config.h
++++ b/include/drm/drm_mode_config.h
+@@ -757,6 +757,14 @@ struct drm_mode_config {
+ 	 */
+ 	bool allow_fb_modifiers;
+ 
++	/**
++	 * @normalize_zpos:
++	 *
++	 * If true the drm core will call drm_atomic_normalize_zpos() as part of
++	 * atomic mode checking from drm_atomic_helper_check()
++	 */
++	bool normalize_zpos;
++
+ 	/**
+ 	 * @modifiers_property: Plane property to list support modifier/format
+ 	 * combination.
+diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
+index 73f90f9d057f..655a4dc8d76e 100644
+--- a/include/drm/drm_plane.h
++++ b/include/drm/drm_plane.h
+@@ -50,8 +50,8 @@ struct drm_modeset_acquire_ctx;
+  *	plane with a lower ID.
+  * @normalized_zpos: normalized value of zpos: unique, range from 0 to N-1
+  *	where N is the number of active planes for given crtc. Note that
+- *	the driver must call drm_atomic_normalize_zpos() to update this before
+- *	it can be trusted.
++ *	the driver must set drm_mode_config.normalize_zpos or call
++ *	drm_atomic_normalize_zpos() to update this before it can be trusted.
+  * @src: clipped source coordinates of the plane (in 16.16)
+  * @dst: clipped destination coordinates of the plane
+  * @state: backpointer to global drm_atomic_state
+-- 
+2.19.0
+
diff --git a/patches/1324-drm-blend-Add-a-generic-alpha-property.patch b/patches/1324-drm-blend-Add-a-generic-alpha-property.patch
new file mode 100644
index 00000000000000..97091341d6ce88
--- /dev/null
+++ b/patches/1324-drm-blend-Add-a-generic-alpha-property.patch
@@ -0,0 +1,185 @@
+From 6b7223dd78d79c9f825f8b78e1e08ea16a382518 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@bootlin.com>
+Date: Wed, 11 Apr 2018 09:39:25 +0200
+Subject: [PATCH 1324/1795] drm/blend: Add a generic alpha property
+
+Some drivers duplicate the logic to create a property to store a per-plane
+alpha.
+
+This is especially useful if we ever want to support extra protocols for
+Wayland like:
+https://lists.freedesktop.org/archives/wayland-devel/2017-August/034741.html
+
+Let's create a helper in order to move that to the core.
+
+Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Acked-by: Sean Paul <seanpaul@chromium.org>
+Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/6e1ce0db78fcfc407e94913c64819e65109d034d.1523432341.git-series.maxime.ripard@bootlin.com
+(cherry picked from commit ae0e28265e216dad11d4cbde42fc15e92919af78)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/gpu/drm/drm_blend.c
+---
+ drivers/gpu/drm/drm_atomic.c        |  4 +++
+ drivers/gpu/drm/drm_atomic_helper.c |  4 +++
+ drivers/gpu/drm/drm_blend.c         | 39 +++++++++++++++++++++++++++++
+ include/drm/drm_blend.h             |  3 +++
+ include/drm/drm_plane.h             |  6 +++++
+ 5 files changed, 56 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
+index bb5cc15fa0b9..3c1f97743303 100644
+--- a/drivers/gpu/drm/drm_atomic.c
++++ b/drivers/gpu/drm/drm_atomic.c
+@@ -763,6 +763,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
+ 		state->src_w = val;
+ 	} else if (property == config->prop_src_h) {
+ 		state->src_h = val;
++	} else if (property == plane->alpha_property) {
++		state->alpha = val;
+ 	} else if (property == plane->rotation_property) {
+ 		if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK))
+ 			return -EINVAL;
+@@ -824,6 +826,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
+ 		*val = state->src_w;
+ 	} else if (property == config->prop_src_h) {
+ 		*val = state->src_h;
++	} else if (property == plane->alpha_property) {
++		*val = state->alpha;
+ 	} else if (property == plane->rotation_property) {
+ 		*val = state->rotation;
+ 	} else if (property == plane->zpos_property) {
+diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
+index e5b6d2a2a4f8..17becffe2767 100644
+--- a/drivers/gpu/drm/drm_atomic_helper.c
++++ b/drivers/gpu/drm/drm_atomic_helper.c
+@@ -3371,6 +3371,10 @@ void drm_atomic_helper_plane_reset(struct drm_plane *plane)
+ 	if (plane->state) {
+ 		plane->state->plane = plane;
+ 		plane->state->rotation = DRM_MODE_ROTATE_0;
++
++		/* Reset the alpha value to fully opaque if it matters */
++		if (plane->alpha_property)
++			plane->state->alpha = plane->alpha_property->values[1];
+ 	}
+ }
+ EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
+diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
+index 2e5e089dd912..42ab5dcd7814 100644
+--- a/drivers/gpu/drm/drm_blend.c
++++ b/drivers/gpu/drm/drm_blend.c
+@@ -88,6 +88,13 @@
+  * On top of this basic transformation additional properties can be exposed by
+  * the driver:
+  *
++ * alpha:
++ * 	Alpha is setup with drm_plane_create_alpha_property(). It controls the
++ * 	plane-wide opacity, from transparent (0) to opaque (0xffff). It can be
++ * 	combined with pixel alpha.
++ *	The pixel values in the framebuffers are expected to not be
++ *	pre-multiplied by the global alpha associated to the plane.
++ *
+  * - Rotation is set up with drm_plane_create_rotation_property(). It adds a
+  *   rotation and reflection step between the source and destination rectangles.
+  *   Without this property the rectangle is only scaled, but not rotated or
+@@ -103,6 +110,38 @@
+  * exposed and assumed to be black).
+  */
+ 
++/**
++ * drm_plane_create_alpha_property - create a new alpha property
++ * @plane: drm plane
++ *
++ * This function creates a generic, mutable, alpha property and enables support
++ * for it in the DRM core. It is attached to @plane.
++ *
++ * The alpha property will be allowed to be within the bounds of 0
++ * (transparent) to 0xffff (opaque).
++ *
++ * Returns:
++ * 0 on success, negative error code on failure.
++ */
++int drm_plane_create_alpha_property(struct drm_plane *plane)
++{
++	struct drm_property *prop;
++
++	prop = drm_property_create_range(plane->dev, 0, "alpha",
++					 0, DRM_BLEND_ALPHA_OPAQUE);
++	if (!prop)
++		return -ENOMEM;
++
++	drm_object_attach_property(&plane->base, prop, DRM_BLEND_ALPHA_OPAQUE);
++	plane->alpha_property = prop;
++
++	if (plane->state)
++		plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_plane_create_alpha_property);
++
+ /**
+  * drm_plane_create_rotation_property - create a new rotation property
+  * @plane: drm plane
+diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h
+index 17606026590b..330c561c4c11 100644
+--- a/include/drm/drm_blend.h
++++ b/include/drm/drm_blend.h
+@@ -36,6 +36,9 @@ static inline bool drm_rotation_90_or_270(unsigned int rotation)
+ 	return rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270);
+ }
+ 
++#define DRM_BLEND_ALPHA_OPAQUE		0xffff
++
++int drm_plane_create_alpha_property(struct drm_plane *plane);
+ int drm_plane_create_rotation_property(struct drm_plane *plane,
+ 				       unsigned int rotation,
+ 				       unsigned int supported_rotations);
+diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
+index 655a4dc8d76e..b81e40912495 100644
+--- a/include/drm/drm_plane.h
++++ b/include/drm/drm_plane.h
+@@ -42,6 +42,7 @@ struct drm_modeset_acquire_ctx;
+  *	plane (in 16.16)
+  * @src_w: width of visible portion of plane (in 16.16)
+  * @src_h: height of visible portion of plane (in 16.16)
++ * @alpha: opacity of the plane
+  * @rotation: rotation of the plane
+  * @zpos: priority of the given plane on crtc (optional)
+  *	Note that multiple active planes on the same crtc can have an identical
+@@ -105,6 +106,9 @@ struct drm_plane_state {
+ 	uint32_t src_x, src_y;
+ 	uint32_t src_h, src_w;
+ 
++	/* Plane opacity */
++	u16 alpha;
++
+ 	/* Plane rotation */
+ 	unsigned int rotation;
+ 
+@@ -473,6 +477,7 @@ enum drm_plane_type {
+  * @funcs: helper functions
+  * @properties: property tracking for this plane
+  * @type: type of plane (overlay, primary, cursor)
++ * @alpha_property: alpha property for this plane
+  * @zpos_property: zpos property for this plane
+  * @rotation_property: rotation property for this plane
+  * @helper_private: mid-layer private data
+@@ -538,6 +543,7 @@ struct drm_plane {
+ 	 */
+ 	struct drm_plane_state *state;
+ 
++	struct drm_property *alpha_property;
+ 	struct drm_property *zpos_property;
+ 	struct drm_property *rotation_property;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1325-drm-rcar-du-Let-core-take-care-of-normalizing-the-zp.patch b/patches/1325-drm-rcar-du-Let-core-take-care-of-normalizing-the-zp.patch
new file mode 100644
index 00000000000000..6cf8deafdbd0eb
--- /dev/null
+++ b/patches/1325-drm-rcar-du-Let-core-take-care-of-normalizing-the-zp.patch
@@ -0,0 +1,53 @@
+From a474ac81df0757cdf2bfbcc326989f085ccdb384 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Wed, 21 Mar 2018 12:20:28 +0200
+Subject: [PATCH 1325/1795] drm: rcar-du: Let core take care of normalizing the
+ zpos
+
+Set the drm_mode_config->normalize_zpos and call drm_atomic_helper_check()
+from rcar_du_atomic_check() instead of re implementing the function locally.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+CC: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180321102029.15248-6-peter.ujfalusi@ti.com
+(cherry picked from commit 75def7785f4901b65a89dc99ea9506b1395242fa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index 0329b354bfa0..ab59d2061e06 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -233,15 +233,7 @@ static int rcar_du_atomic_check(struct drm_device *dev,
+ 	struct rcar_du_device *rcdu = dev->dev_private;
+ 	int ret;
+ 
+-	ret = drm_atomic_helper_check_modeset(dev, state);
+-	if (ret)
+-		return ret;
+-
+-	ret = drm_atomic_normalize_zpos(dev, state);
+-	if (ret)
+-		return ret;
+-
+-	ret = drm_atomic_helper_check_planes(dev, state);
++	ret = drm_atomic_helper_check(dev, state);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -529,6 +521,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	dev->mode_config.min_height = 0;
+ 	dev->mode_config.max_width = 4095;
+ 	dev->mode_config.max_height = 2047;
++	dev->mode_config.normalize_zpos = true;
+ 	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
+ 	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1326-drm-rcar-du-Convert-to-the-new-generic-alpha-propert.patch b/patches/1326-drm-rcar-du-Convert-to-the-new-generic-alpha-propert.patch
new file mode 100644
index 00000000000000..7b201557f17c49
--- /dev/null
+++ b/patches/1326-drm-rcar-du-Convert-to-the-new-generic-alpha-propert.patch
@@ -0,0 +1,251 @@
+From 0087bc5eb9992fd10cdff69a6ff287a3301850af Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@bootlin.com>
+Date: Wed, 11 Apr 2018 09:39:27 +0200
+Subject: [PATCH 1326/1795] drm/rcar-du: Convert to the new generic alpha
+ property
+
+Now that we have support for per-plane alpha in the core, let's use it.
+
+Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Acked-by: Sean Paul <seanpaul@chromium.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/a343697b87109cd8d9675ea8bce2e561051a696f.1523432341.git-series.maxime.ripard@bootlin.com
+(cherry picked from commit 301a9b8d545690f7bd91e1794e1498aa62902d13)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.h   |  1 -
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c   |  5 ---
+ drivers/gpu/drm/rcar-du/rcar_du_plane.c | 15 +++------
+ drivers/gpu/drm/rcar-du/rcar_du_plane.h |  2 --
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c   | 42 +++----------------------
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.h   |  3 --
+ 6 files changed, 9 insertions(+), 59 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+index 5c7ec15818c7..131d8e88b06c 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+@@ -87,7 +87,6 @@ struct rcar_du_device {
+ 	struct rcar_du_vsp vsps[RCAR_DU_MAX_VSPS];
+ 
+ 	struct {
+-		struct drm_property *alpha;
+ 		struct drm_property *colorkey;
+ 	} props;
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index ab59d2061e06..f4ac0f884f00 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -407,11 +407,6 @@ static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
+ 
+ static int rcar_du_properties_init(struct rcar_du_device *rcdu)
+ {
+-	rcdu->props.alpha =
+-		drm_property_create_range(rcdu->ddev, 0, "alpha", 0, 255);
+-	if (rcdu->props.alpha == NULL)
+-		return -ENOMEM;
+-
+ 	/*
+ 	 * The color key is expressed as an RGB888 triplet stored in a 32-bit
+ 	 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+index 5687a94d4cb1..93249c7592cd 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+@@ -423,7 +423,7 @@ static void rcar_du_plane_setup_mode(struct rcar_du_group *rgrp,
+ 		rcar_du_plane_write(rgrp, index, PnALPHAR, PnALPHAR_ABIT_0);
+ 	else
+ 		rcar_du_plane_write(rgrp, index, PnALPHAR,
+-				    PnALPHAR_ABIT_X | state->alpha);
++				    PnALPHAR_ABIT_X | state->state.alpha >> 8);
+ 
+ 	pnmr = PnMR_BM_MD | state->format->pnmr;
+ 
+@@ -697,11 +697,11 @@ static void rcar_du_plane_reset(struct drm_plane *plane)
+ 
+ 	state->hwindex = -1;
+ 	state->source = RCAR_DU_PLANE_MEMORY;
+-	state->alpha = 255;
+ 	state->colorkey = RCAR_DU_COLORKEY_NONE;
+ 	state->state.zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
+ 
+ 	plane->state = &state->state;
++	plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
+ 	plane->state->plane = plane;
+ }
+ 
+@@ -713,9 +713,7 @@ static int rcar_du_plane_atomic_set_property(struct drm_plane *plane,
+ 	struct rcar_du_plane_state *rstate = to_rcar_plane_state(state);
+ 	struct rcar_du_device *rcdu = to_rcar_plane(plane)->group->dev;
+ 
+-	if (property == rcdu->props.alpha)
+-		rstate->alpha = val;
+-	else if (property == rcdu->props.colorkey)
++	if (property == rcdu->props.colorkey)
+ 		rstate->colorkey = val;
+ 	else
+ 		return -EINVAL;
+@@ -731,9 +729,7 @@ static int rcar_du_plane_atomic_get_property(struct drm_plane *plane,
+ 		container_of(state, const struct rcar_du_plane_state, state);
+ 	struct rcar_du_device *rcdu = to_rcar_plane(plane)->group->dev;
+ 
+-	if (property == rcdu->props.alpha)
+-		*val = rstate->alpha;
+-	else if (property == rcdu->props.colorkey)
++	if (property == rcdu->props.colorkey)
+ 		*val = rstate->colorkey;
+ 	else
+ 		return -EINVAL;
+@@ -801,11 +797,10 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp)
+ 		if (type == DRM_PLANE_TYPE_PRIMARY)
+ 			continue;
+ 
+-		drm_object_attach_property(&plane->plane.base,
+-					   rcdu->props.alpha, 255);
+ 		drm_object_attach_property(&plane->plane.base,
+ 					   rcdu->props.colorkey,
+ 					   RCAR_DU_COLORKEY_NONE);
++		drm_plane_create_alpha_property(&plane->plane);
+ 		drm_plane_create_zpos_property(&plane->plane, 1, 1, 7);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+index 890321b4665d..5c19c69e4691 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+@@ -50,7 +50,6 @@ static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane)
+  * @state: base DRM plane state
+  * @format: information about the pixel format used by the plane
+  * @hwindex: 0-based hardware plane index, -1 means unused
+- * @alpha: value of the plane alpha property
+  * @colorkey: value of the plane colorkey property
+  */
+ struct rcar_du_plane_state {
+@@ -60,7 +59,6 @@ struct rcar_du_plane_state {
+ 	int hwindex;
+ 	enum rcar_du_plane_source source;
+ 
+-	unsigned int alpha;
+ 	unsigned int colorkey;
+ };
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index bdcec201591f..2fc61253a095 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -54,6 +54,7 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
+ 	};
+ 	struct rcar_du_plane_state state = {
+ 		.state = {
++			.alpha = DRM_BLEND_ALPHA_OPAQUE,
+ 			.crtc = &crtc->crtc,
+ 			.dst.x1 = 0,
+ 			.dst.y1 = 0,
+@@ -67,7 +68,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
+ 		},
+ 		.format = rcar_du_format_info(DRM_FORMAT_ARGB8888),
+ 		.source = RCAR_DU_PLANE_VSPD1,
+-		.alpha = 255,
+ 		.colorkey = 0,
+ 	};
+ 
+@@ -175,7 +175,7 @@ static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
+ 	struct vsp1_du_atomic_config cfg = {
+ 		.pixelformat = 0,
+ 		.pitch = fb->pitches[0],
+-		.alpha = state->alpha,
++		.alpha = state->state.alpha >> 8,
+ 		.zpos = state->state.zpos,
+ 	};
+ 	unsigned int i;
+@@ -337,44 +337,13 @@ static void rcar_du_vsp_plane_reset(struct drm_plane *plane)
+ 	if (state == NULL)
+ 		return;
+ 
+-	state->alpha = 255;
++	state->state.alpha = DRM_BLEND_ALPHA_OPAQUE;
+ 	state->state.zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
+ 
+ 	plane->state = &state->state;
+ 	plane->state->plane = plane;
+ }
+ 
+-static int rcar_du_vsp_plane_atomic_set_property(struct drm_plane *plane,
+-	struct drm_plane_state *state, struct drm_property *property,
+-	uint64_t val)
+-{
+-	struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
+-	struct rcar_du_device *rcdu = to_rcar_vsp_plane(plane)->vsp->dev;
+-
+-	if (property == rcdu->props.alpha)
+-		rstate->alpha = val;
+-	else
+-		return -EINVAL;
+-
+-	return 0;
+-}
+-
+-static int rcar_du_vsp_plane_atomic_get_property(struct drm_plane *plane,
+-	const struct drm_plane_state *state, struct drm_property *property,
+-	uint64_t *val)
+-{
+-	const struct rcar_du_vsp_plane_state *rstate =
+-		container_of(state, const struct rcar_du_vsp_plane_state, state);
+-	struct rcar_du_device *rcdu = to_rcar_vsp_plane(plane)->vsp->dev;
+-
+-	if (property == rcdu->props.alpha)
+-		*val = rstate->alpha;
+-	else
+-		return -EINVAL;
+-
+-	return 0;
+-}
+-
+ static const struct drm_plane_funcs rcar_du_vsp_plane_funcs = {
+ 	.update_plane = drm_atomic_helper_update_plane,
+ 	.disable_plane = drm_atomic_helper_disable_plane,
+@@ -382,8 +351,6 @@ static const struct drm_plane_funcs rcar_du_vsp_plane_funcs = {
+ 	.destroy = drm_plane_cleanup,
+ 	.atomic_duplicate_state = rcar_du_vsp_plane_atomic_duplicate_state,
+ 	.atomic_destroy_state = rcar_du_vsp_plane_atomic_destroy_state,
+-	.atomic_set_property = rcar_du_vsp_plane_atomic_set_property,
+-	.atomic_get_property = rcar_du_vsp_plane_atomic_get_property,
+ };
+ 
+ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
+@@ -440,8 +407,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
+ 		if (type == DRM_PLANE_TYPE_PRIMARY)
+ 			continue;
+ 
+-		drm_object_attach_property(&plane->plane.base,
+-					   rcdu->props.alpha, 255);
++		drm_plane_create_alpha_property(&plane->plane);
+ 		drm_plane_create_zpos_property(&plane->plane, 1, 1,
+ 					       vsp->num_planes - 1);
+ 	}
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+index 4c5d7bbce6aa..8a8a25c8c8e8 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+@@ -44,15 +44,12 @@ static inline struct rcar_du_vsp_plane *to_rcar_vsp_plane(struct drm_plane *p)
+  * @state: base DRM plane state
+  * @format: information about the pixel format used by the plane
+  * @sg_tables: scatter-gather tables for the frame buffer memory
+- * @alpha: value of the plane alpha property
+  */
+ struct rcar_du_vsp_plane_state {
+ 	struct drm_plane_state state;
+ 
+ 	const struct rcar_du_format_info *format;
+ 	struct sg_table sg_tables[3];
+-
+-	unsigned int alpha;
+ };
+ 
+ static inline struct rcar_du_vsp_plane_state *
+-- 
+2.19.0
+
diff --git a/patches/1327-drm-rcar-du-Zero-out-sg_tables-when-duplicating-plan.patch b/patches/1327-drm-rcar-du-Zero-out-sg_tables-when-duplicating-plan.patch
new file mode 100644
index 00000000000000..0193a067147233
--- /dev/null
+++ b/patches/1327-drm-rcar-du-Zero-out-sg_tables-when-duplicating-plan.patch
@@ -0,0 +1,53 @@
+From 5712107e1ff253cdc7f0b34cbce7945d62f0c005 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Wed, 17 Jan 2018 22:18:41 +0200
+Subject: [PATCH 1327/1795] drm: rcar-du: Zero-out sg_tables when duplicating
+ plane state
+
+The state structure for VSP-backed planes, rcar_du_vsp_plane_state,
+contains sg tables that track framebuffer mapping performed in the
+.prepare_fb() operation to unmap them in .cleanup_fb(). The tables are
+incorrectly copied when duplicating state, which can result :
+
+Zero-out sg_tables in original plane, effectively introducing move
+semantic. Seems, this fixes issue with double-free,
+when rcar_du_vsp_plane_cleanup_fb() freed the same sg_table
+both in original plane and in the copy.
+
+Reported-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 75a07f399cd43bc7fb41a13723fbe04e61c5c470)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index 2fc61253a095..b2ef0f5631e7 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -301,18 +301,17 @@ static const struct drm_plane_helper_funcs rcar_du_vsp_plane_helper_funcs = {
+ static struct drm_plane_state *
+ rcar_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane)
+ {
+-	struct rcar_du_vsp_plane_state *state;
+ 	struct rcar_du_vsp_plane_state *copy;
+ 
+ 	if (WARN_ON(!plane->state))
+ 		return NULL;
+ 
+-	state = to_rcar_vsp_plane_state(plane->state);
+-	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
++	copy = kzalloc(sizeof(*copy), GFP_KERNEL);
+ 	if (copy == NULL)
+ 		return NULL;
+ 
+ 	__drm_atomic_helper_plane_duplicate_state(plane, &copy->state);
++	copy->alpha = to_rcar_vsp_plane_state(plane->state)->alpha;
+ 
+ 	return &copy->state;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1328-drm-rcar-du-of-Include-header-to-define-prototypes.patch b/patches/1328-drm-rcar-du-of-Include-header-to-define-prototypes.patch
new file mode 100644
index 00000000000000..8242ee97842319
--- /dev/null
+++ b/patches/1328-drm-rcar-du-of-Include-header-to-define-prototypes.patch
@@ -0,0 +1,44 @@
+From b2728c9d6aad1d09d3cd578656cfcc9f4f4dc60b Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Tue, 24 Apr 2018 16:39:42 +0100
+Subject: [PATCH 1328/1795] drm: rcar-du: of: Include header to define
+ prototypes
+
+The symbol 'rcar_du_of_init' is defined by the rcar_du_of module header,
+but it is not included by the C implementation.
+
+Include the header to correctly define the function prototypes.
+
+Fixes the following warning:
+
+linux/drivers/gpu/drm/rcar-du/rcar_du_of.c:319:13:
+   warning: symbol 'rcar_du_of_init' was not declared. Should it be static?
+    CC      drivers/gpu/drm/rcar-du/rcar_du_of.o
+
+Fixes: 81c0e3dd8292 ("drm: rcar-du: Fix legacy DT to create LVDS encoder nodes")
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Vaishali Thakkar <vthakkar@vaishalithakkar.in>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit c18e9a098605abe5a1dc1c5dd9cfeda322ed36d8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_of.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of.c b/drivers/gpu/drm/rcar-du/rcar_du_of.c
+index 68a0b82cb17e..afef69669bb4 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_of.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of.c
+@@ -18,6 +18,7 @@
+ 
+ #include "rcar_du_crtc.h"
+ #include "rcar_du_drv.h"
++#include "rcar_du_of.h"
+ 
+ /* -----------------------------------------------------------------------------
+  * Generic Overlay Handling
+-- 
+2.19.0
+
diff --git a/patches/1329-drm-rcar-du-Use-NULL-for-table-initialisation.patch b/patches/1329-drm-rcar-du-Use-NULL-for-table-initialisation.patch
new file mode 100644
index 00000000000000..a7ceb892df9849
--- /dev/null
+++ b/patches/1329-drm-rcar-du-Use-NULL-for-table-initialisation.patch
@@ -0,0 +1,41 @@
+From 124eaef23775dbcf56b2f5ef0b285526058cb41f Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Tue, 24 Apr 2018 16:40:03 +0100
+Subject: [PATCH 1329/1795] drm: rcar-du: Use NULL for table initialisation
+
+Replace the initialisation of the vsps table with a NULL specifier.
+
+Fixes the following warning:
+ linux/drivers/gpu/drm/rcar-du/rcar_du_kms.c:483:40:
+    warning: Using plain integer as NULL pointer
+      CC      drivers/gpu/drm/rcar-du/rcar_du_kms.o
+
+Fixes: 3e81374e2014 ("drm: rcar-du: Support multiple sources from the same VSP")
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Vaishali Thakkar <vthakkar@vaishalithakkar.in>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 3b0033eb39360dc655466c5f1e6852d5a83b384d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index f4ac0f884f00..8b56e7108a09 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -428,7 +428,7 @@ static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
+ 	struct {
+ 		struct device_node *np;
+ 		unsigned int crtcs_mask;
+-	} vsps[RCAR_DU_MAX_VSPS] = { { 0, }, };
++	} vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
+ 	unsigned int vsps_count = 0;
+ 	unsigned int cells;
+ 	unsigned int i;
+-- 
+2.19.0
+
diff --git a/patches/1330-dt-bindings-display-renesas-du-Increase-indent-in-ou.patch b/patches/1330-dt-bindings-display-renesas-du-Increase-indent-in-ou.patch
new file mode 100644
index 00000000000000..a270b62fa369db
--- /dev/null
+++ b/patches/1330-dt-bindings-display-renesas-du-Increase-indent-in-ou.patch
@@ -0,0 +1,64 @@
+From 84b51e93391165cbab2226736590b9287412b3c4 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 26 Apr 2018 17:53:30 +0100
+Subject: [PATCH 1330/1795] dt-bindings: display: renesas: du: Increase indent
+ in output table
+
+The DU output table lists the port combinations for each supported DU
+type.  Newer models of R-Car Gen3 platforms have an increased string
+length.
+
+Increase the table indentation in preparation for supporting new target
+types.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit a4af8423cfe50e5cafa1893fc40643245793e3cd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/display/renesas,du.txt           | 26 +++++++++----------
+ 1 file changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index c9cd17f99702..a36a6e7ee54f 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -47,20 +47,20 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
+ The following table lists for each supported model the port number
+ corresponding to each DU output.
+ 
+-                      Port0          Port1          Port2          Port3
++                        Port0          Port1          Port2          Port3
+ -----------------------------------------------------------------------------
+- R8A7743 (RZ/G1M)     DPAD 0         LVDS 0         -              -
+- R8A7745 (RZ/G1E)     DPAD 0         DPAD 1         -              -
+- R8A7779 (R-Car H1)   DPAD 0         DPAD 1         -              -
+- R8A7790 (R-Car H2)   DPAD 0         LVDS 0         LVDS 1         -
+- R8A7791 (R-Car M2-W) DPAD 0         LVDS 0         -              -
+- R8A7792 (R-Car V2H)  DPAD 0         DPAD 1         -              -
+- R8A7793 (R-Car M2-N) DPAD 0         LVDS 0         -              -
+- R8A7794 (R-Car E2)   DPAD 0         DPAD 1         -              -
+- R8A7795 (R-Car H3)   DPAD 0         HDMI 0         HDMI 1         LVDS 0
+- R8A7796 (R-Car M3-W) DPAD 0         HDMI 0         LVDS 0         -
+- R8A77970 (R-Car V3M) DPAD 0         LVDS 0         -              -
+- R8A77995 (R-Car D3)  DPAD 0         LVDS 0         LVDS 1         -
++ R8A7743 (RZ/G1M)       DPAD 0         LVDS 0         -              -
++ R8A7745 (RZ/G1E)       DPAD 0         DPAD 1         -              -
++ R8A7779 (R-Car H1)     DPAD 0         DPAD 1         -              -
++ R8A7790 (R-Car H2)     DPAD 0         LVDS 0         LVDS 1         -
++ R8A7791 (R-Car M2-W)   DPAD 0         LVDS 0         -              -
++ R8A7792 (R-Car V2H)    DPAD 0         DPAD 1         -              -
++ R8A7793 (R-Car M2-N)   DPAD 0         LVDS 0         -              -
++ R8A7794 (R-Car E2)     DPAD 0         DPAD 1         -              -
++ R8A7795 (R-Car H3)     DPAD 0         HDMI 0         HDMI 1         LVDS 0
++ R8A7796 (R-Car M3-W)   DPAD 0         HDMI 0         LVDS 0         -
++ R8A77970 (R-Car V3M)   DPAD 0         LVDS 0         -              -
++ R8A77995 (R-Car D3)    DPAD 0         LVDS 0         LVDS 1         -
+ 
+ 
+ Example: R8A7795 (R-Car H3) ES2.0 DU
+-- 
+2.19.0
+
diff --git a/patches/1331-dt-bindings-display-renesas-du-Document-the-r8a77965.patch b/patches/1331-dt-bindings-display-renesas-du-Document-the-r8a77965.patch
new file mode 100644
index 00000000000000..6bfaa32eb0536e
--- /dev/null
+++ b/patches/1331-dt-bindings-display-renesas-du-Document-the-r8a77965.patch
@@ -0,0 +1,41 @@
+From 7b43eb62598eda7b95b09256a3caba2e72cb6299 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 26 Apr 2018 17:53:31 +0100
+Subject: [PATCH 1331/1795] dt-bindings: display: renesas: du: Document the
+ r8a77965 bindings
+
+Document the M3-N (r8a77965) SoC in the R-Car DU bindings.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit dc8142901befabea974393d49b803f131243feb4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
+index a36a6e7ee54f..7c6854bd0a04 100644
+--- a/Documentation/devicetree/bindings/display/renesas,du.txt
++++ b/Documentation/devicetree/bindings/display/renesas,du.txt
+@@ -13,6 +13,7 @@ Required Properties:
+     - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
+     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
+     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
++    - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
+     - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
+     - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
+ 
+@@ -59,6 +60,7 @@ corresponding to each DU output.
+  R8A7794 (R-Car E2)     DPAD 0         DPAD 1         -              -
+  R8A7795 (R-Car H3)     DPAD 0         HDMI 0         HDMI 1         LVDS 0
+  R8A7796 (R-Car M3-W)   DPAD 0         HDMI 0         LVDS 0         -
++ R8A77965 (R-Car M3-N)  DPAD 0         HDMI 0         LVDS 0         -
+  R8A77970 (R-Car V3M)   DPAD 0         LVDS 0         -              -
+  R8A77995 (R-Car D3)    DPAD 0         LVDS 0         LVDS 1         -
+ 
+-- 
+2.19.0
+
diff --git a/patches/1332-drm-rcar-du-Use-the-correct-naming-for-ODPM-fields-i.patch b/patches/1332-drm-rcar-du-Use-the-correct-naming-for-ODPM-fields-i.patch
new file mode 100644
index 00000000000000..88b54370aa2573
--- /dev/null
+++ b/patches/1332-drm-rcar-du-Use-the-correct-naming-for-ODPM-fields-i.patch
@@ -0,0 +1,70 @@
+From ba757a9f38cc06fc87033d37e04b1966da0b8fbc Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 26 Apr 2018 17:53:33 +0100
+Subject: [PATCH 1332/1795] drm: rcar-du: Use the correct naming for ODPM
+ fields in DEFR6
+
+The naming of the fields for the ODPM signals in the DU extensional
+function control register 6 (DEFR6) is incorrect against the data sheets
+for both R-Car Gen2 and R-Car Gen3.
+
+Rename the fields to match the datasheet.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 4012532e040ba4c6bba0883c27b57adb1fd88db8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_group.c |  4 ++--
+ drivers/gpu/drm/rcar-du/rcar_du_regs.h  | 16 ++++++++--------
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+index 2f37ea901873..eead202c95c7 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+@@ -46,10 +46,10 @@ void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
+ 
+ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
+ {
+-	u32 defr6 = DEFR6_CODE | DEFR6_ODPM12_DISP;
++	u32 defr6 = DEFR6_CODE | DEFR6_ODPM02_DISP;
+ 
+ 	if (rgrp->num_crtcs > 1)
+-		defr6 |= DEFR6_ODPM22_DISP;
++		defr6 |= DEFR6_ODPM12_DISP;
+ 
+ 	rcar_du_group_write(rgrp, DEFR6, defr6);
+ }
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+index d5bae99d3cfe..9dfd220ceda1 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+@@ -187,14 +187,14 @@
+ 
+ #define DEFR6			0x000e8
+ #define DEFR6_CODE		(0x7778 << 16)
+-#define DEFR6_ODPM22_DSMR	(0 << 10)
+-#define DEFR6_ODPM22_DISP	(2 << 10)
+-#define DEFR6_ODPM22_CDE	(3 << 10)
+-#define DEFR6_ODPM22_MASK	(3 << 10)
+-#define DEFR6_ODPM12_DSMR	(0 << 8)
+-#define DEFR6_ODPM12_DISP	(2 << 8)
+-#define DEFR6_ODPM12_CDE	(3 << 8)
+-#define DEFR6_ODPM12_MASK	(3 << 8)
++#define DEFR6_ODPM12_DSMR	(0 << 10)
++#define DEFR6_ODPM12_DISP	(2 << 10)
++#define DEFR6_ODPM12_CDE	(3 << 10)
++#define DEFR6_ODPM12_MASK	(3 << 10)
++#define DEFR6_ODPM02_DSMR	(0 << 8)
++#define DEFR6_ODPM02_DISP	(2 << 8)
++#define DEFR6_ODPM02_CDE	(3 << 8)
++#define DEFR6_ODPM02_MASK	(3 << 8)
+ #define DEFR6_TCNE1		(1 << 6)
+ #define DEFR6_TCNE0		(1 << 4)
+ #define DEFR6_MLOS1		(1 << 2)
+-- 
+2.19.0
+
diff --git a/patches/1333-drm-rcar-du-Split-CRTC-handling-to-support-hardware-.patch b/patches/1333-drm-rcar-du-Split-CRTC-handling-to-support-hardware-.patch
new file mode 100644
index 00000000000000..c94948b52a7db3
--- /dev/null
+++ b/patches/1333-drm-rcar-du-Split-CRTC-handling-to-support-hardware-.patch
@@ -0,0 +1,322 @@
+From 243d5b25daba68ed9f71d2babca1f52311175558 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:21:52 +0100
+Subject: [PATCH 1333/1795] drm: rcar-du: Split CRTC handling to support
+ hardware indexing
+
+The DU CRTC driver does not support distinguishing between a hardware
+index, and a software (CRTC) index in the event that a DU channel might
+not be populated by the hardware.
+
+Support this by adapting the rcar_du_device_info structure to store a
+bitmask of available channels rather than a count of CRTCs. The count
+can then be obtained by determining the hamming weight of the bitmask.
+
+This allows the rcar_du_crtc_create() function to distinguish between
+both index types, and non-populated DU channels will be skipped without
+leaving a gap in the software CRTC indexes.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 5361cc7f8e9146f393cfcb76890d8c80a4e73086)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 26 ++++++++++++++------------
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.h |  3 ++-
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c  | 22 +++++++++++-----------
+ drivers/gpu/drm/rcar-du/rcar_du_drv.h  |  4 ++--
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c  | 18 +++++++++++++-----
+ 5 files changed, 42 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index c4420538ec85..f2a0bd1e5119 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -767,7 +767,8 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
+  * Initialization
+  */
+ 
+-int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
++int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
++			unsigned int hwindex)
+ {
+ 	static const unsigned int mmio_offsets[] = {
+ 		DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
+@@ -775,7 +776,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 
+ 	struct rcar_du_device *rcdu = rgrp->dev;
+ 	struct platform_device *pdev = to_platform_device(rcdu->dev);
+-	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
++	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
+ 	struct drm_crtc *crtc = &rcrtc->crtc;
+ 	struct drm_plane *primary;
+ 	unsigned int irqflags;
+@@ -787,7 +788,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 
+ 	/* Get the CRTC clock and the optional external clock. */
+ 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
+-		sprintf(clk_name, "du.%u", index);
++		sprintf(clk_name, "du.%u", hwindex);
+ 		name = clk_name;
+ 	} else {
+ 		name = NULL;
+@@ -795,16 +796,16 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 
+ 	rcrtc->clock = devm_clk_get(rcdu->dev, name);
+ 	if (IS_ERR(rcrtc->clock)) {
+-		dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
++		dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
+ 		return PTR_ERR(rcrtc->clock);
+ 	}
+ 
+-	sprintf(clk_name, "dclkin.%u", index);
++	sprintf(clk_name, "dclkin.%u", hwindex);
+ 	clk = devm_clk_get(rcdu->dev, clk_name);
+ 	if (!IS_ERR(clk)) {
+ 		rcrtc->extclock = clk;
+ 	} else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
+-		dev_info(rcdu->dev, "can't get external clock %u\n", index);
++		dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);
+ 		return -EPROBE_DEFER;
+ 	}
+ 
+@@ -813,13 +814,13 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 	spin_lock_init(&rcrtc->vblank_lock);
+ 
+ 	rcrtc->group = rgrp;
+-	rcrtc->mmio_offset = mmio_offsets[index];
+-	rcrtc->index = index;
++	rcrtc->mmio_offset = mmio_offsets[hwindex];
++	rcrtc->index = hwindex;
+ 
+ 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
+ 		primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
+ 	else
+-		primary = &rgrp->planes[index % 2].plane;
++		primary = &rgrp->planes[swindex % 2].plane;
+ 
+ 	ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary,
+ 					NULL, &crtc_funcs, NULL);
+@@ -833,7 +834,8 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 
+ 	/* Register the interrupt handler. */
+ 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
+-		irq = platform_get_irq(pdev, index);
++		/* The IRQ's are associated with the CRTC (sw)index. */
++		irq = platform_get_irq(pdev, swindex);
+ 		irqflags = 0;
+ 	} else {
+ 		irq = platform_get_irq(pdev, 0);
+@@ -841,7 +843,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 	}
+ 
+ 	if (irq < 0) {
+-		dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
++		dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
+ 		return irq;
+ 	}
+ 
+@@ -849,7 +851,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
+ 			       dev_name(rcdu->dev), rcrtc);
+ 	if (ret < 0) {
+ 		dev_err(rcdu->dev,
+-			"failed to register IRQ for CRTC %u\n", index);
++			"failed to register IRQ for CRTC %u\n", swindex);
+ 		return ret;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+index fdc2bf99bda1..84b5e23a85b1 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+@@ -80,7 +80,8 @@ enum rcar_du_output {
+ 	RCAR_DU_OUTPUT_MAX,
+ };
+ 
+-int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index);
++int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
++			unsigned int hwindex);
+ void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc);
+ void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc);
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index 3917d839c04c..2aa392b03e73 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -40,7 +40,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7743 has one RGB output and one LVDS output
+@@ -61,7 +61,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7745 has two RGB outputs
+@@ -80,7 +80,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
+ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
+ 	.gen = 2,
+ 	.features = 0,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7779 has two RGB outputs and one (currently unsupported)
+@@ -102,7 +102,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+ 	.quirks = RCAR_DU_QUIRK_ALIGN_128B,
+-	.num_crtcs = 3,
++	.channels_mask = BIT(2) | BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7790 has one RGB output, two LVDS outputs and one
+@@ -129,7 +129,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A779[13] has one RGB output, one LVDS output and one
+@@ -151,7 +151,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/* R8A7792 has two RGB outputs. */
+ 		[RCAR_DU_OUTPUT_DPAD0] = {
+@@ -169,7 +169,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
+ 	.gen = 2,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+-	.num_crtcs = 2,
++	.channels_mask = BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7794 has two RGB outputs and one (currently unsupported)
+@@ -191,7 +191,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
+ 		  | RCAR_DU_FEATURE_VSP1_SOURCE,
+-	.num_crtcs = 4,
++	.channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7795 has one RGB output, two HDMI outputs and one
+@@ -215,7 +215,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
+ 		},
+ 	},
+ 	.num_lvds = 1,
+-	.dpll_ch =  BIT(1) | BIT(2),
++	.dpll_ch =  BIT(2) | BIT(1),
+ };
+ 
+ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+@@ -223,7 +223,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
+ 		  | RCAR_DU_FEATURE_VSP1_SOURCE,
+-	.num_crtcs = 3,
++	.channels_mask = BIT(2) | BIT(1) | BIT(0),
+ 	.routes = {
+ 		/*
+ 		 * R8A7796 has one RGB output, one LVDS output and one HDMI
+@@ -251,7 +251,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ 		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
+ 		  | RCAR_DU_FEATURE_VSP1_SOURCE,
+-	.num_crtcs = 1,
++	.channels_mask = BIT(0),
+ 	.routes = {
+ 		/* R8A77970 has one RGB output and one LVDS output. */
+ 		[RCAR_DU_OUTPUT_DPAD0] = {
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+index 131d8e88b06c..b3a25e8e07d0 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+@@ -52,7 +52,7 @@ struct rcar_du_output_routing {
+  * @gen: device generation (2 or 3)
+  * @features: device features (RCAR_DU_FEATURE_*)
+  * @quirks: device quirks (RCAR_DU_QUIRK_*)
+- * @num_crtcs: total number of CRTCs
++ * @channels_mask: bit mask of available DU channels
+  * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
+  * @num_lvds: number of internal LVDS encoders
+  */
+@@ -60,7 +60,7 @@ struct rcar_du_device_info {
+ 	unsigned int gen;
+ 	unsigned int features;
+ 	unsigned int quirks;
+-	unsigned int num_crtcs;
++	unsigned int channels_mask;
+ 	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
+ 	unsigned int num_lvds;
+ 	unsigned int dpll_ch;
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index 8b56e7108a09..9da976f26225 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -507,6 +507,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	struct drm_fbdev_cma *fbdev;
+ 	unsigned int num_encoders;
+ 	unsigned int num_groups;
++	unsigned int swindex;
++	unsigned int hwindex;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -520,7 +522,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
+ 	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
+ 
+-	rcdu->num_crtcs = rcdu->info->num_crtcs;
++	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
+ 
+ 	ret = rcar_du_properties_init(rcdu);
+ 	if (ret < 0)
+@@ -530,7 +532,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	 * Initialize vertical blanking interrupts handling. Start with vblank
+ 	 * disabled for all CRTCs.
+ 	 */
+-	ret = drm_vblank_init(dev, (1 << rcdu->info->num_crtcs) - 1);
++	ret = drm_vblank_init(dev, (1 << rcdu->num_crtcs) - 1);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -572,10 +574,16 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 	}
+ 
+ 	/* Create the CRTCs. */
+-	for (i = 0; i < rcdu->num_crtcs; ++i) {
+-		struct rcar_du_group *rgrp = &rcdu->groups[i / 2];
++	for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
++		struct rcar_du_group *rgrp;
++
++		/* Skip unpopulated DU channels. */
++		if (!(rcdu->info->channels_mask & BIT(hwindex)))
++			continue;
++
++		rgrp = &rcdu->groups[hwindex / 2];
+ 
+-		ret = rcar_du_crtc_create(rgrp, i);
++		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
+ 		if (ret < 0)
+ 			return ret;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1334-drm-rcar-du-Allow-DU-groups-to-work-with-hardware-in.patch b/patches/1334-drm-rcar-du-Allow-DU-groups-to-work-with-hardware-in.patch
new file mode 100644
index 00000000000000..f90a17de009dd0
--- /dev/null
+++ b/patches/1334-drm-rcar-du-Allow-DU-groups-to-work-with-hardware-in.patch
@@ -0,0 +1,101 @@
+From a4eaf031beac2dc92fc50b56aeb98e6dd460c629 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:21:53 +0100
+Subject: [PATCH 1334/1795] drm: rcar-du: Allow DU groups to work with hardware
+ indexing
+
+The group objects assume linear indexing, and more so always assume that
+channel 0 of any active group is used.
+
+Now that the CRTC objects support non-linear indexing, adapt the groups
+to remove assumptions that channel 0 is utilised in each group by using
+the channel mask provided in the device structures.
+
+Finally ensure that the RGB routing is determined from the index of the
+CRTC object (which represents the hardware DU channel index).
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit 7ae90455bc865ab1c30fb4db53ac56ec32741ab9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_group.c | 14 +++++++++-----
+ drivers/gpu/drm/rcar-du/rcar_du_group.h |  2 ++
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c   |  5 ++++-
+ 3 files changed, 15 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+index eead202c95c7..d539cb290a35 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+@@ -46,9 +46,12 @@ void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
+ 
+ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
+ {
+-	u32 defr6 = DEFR6_CODE | DEFR6_ODPM02_DISP;
++	u32 defr6 = DEFR6_CODE;
+ 
+-	if (rgrp->num_crtcs > 1)
++	if (rgrp->channels_mask & BIT(0))
++		defr6 |= DEFR6_ODPM02_DISP;
++
++	if (rgrp->channels_mask & BIT(1))
+ 		defr6 |= DEFR6_ODPM12_DISP;
+ 
+ 	rcar_du_group_write(rgrp, DEFR6, defr6);
+@@ -80,10 +83,11 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
+ 		 * On Gen3 VSPD routing can't be configured, but DPAD routing
+ 		 * needs to be set despite having a single option available.
+ 		 */
+-		u32 crtc = ffs(possible_crtcs) - 1;
++		unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
++		struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
+ 
+-		if (crtc / 2 == rgrp->index)
+-			defr8 |= DEFR8_DRGBS_DU(crtc);
++		if (crtc->index / 2 == rgrp->index)
++			defr8 |= DEFR8_DRGBS_DU(crtc->index);
+ 	}
+ 
+ 	rcar_du_group_write(rgrp, DEFR8, defr8);
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h
+index 5e3adc6b31b5..42105aedecc8 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_group.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h
+@@ -25,6 +25,7 @@ struct rcar_du_device;
+  * @dev: the DU device
+  * @mmio_offset: registers offset in the device memory map
+  * @index: group index
++ * @channels_mask: bitmask of populated DU channels in this group
+  * @num_crtcs: number of CRTCs in this group (1 or 2)
+  * @use_count: number of users of the group (rcar_du_group_(get|put))
+  * @used_crtcs: number of CRTCs currently in use
+@@ -39,6 +40,7 @@ struct rcar_du_group {
+ 	unsigned int mmio_offset;
+ 	unsigned int index;
+ 
++	unsigned int channels_mask;
+ 	unsigned int num_crtcs;
+ 	unsigned int use_count;
+ 	unsigned int used_crtcs;
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+index 9da976f26225..f0bc7cc0e913 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+@@ -547,7 +547,10 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
+ 		rgrp->dev = rcdu;
+ 		rgrp->mmio_offset = mmio_offsets[i];
+ 		rgrp->index = i;
+-		rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U);
++		/* Extract the channel mask for this group only. */
++		rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
++				   & GENMASK(1, 0);
++		rgrp->num_crtcs = hweight8(rgrp->channels_mask);
+ 
+ 		/*
+ 		 * If we have more than one CRTCs in this group pre-associate
+-- 
+2.19.0
+
diff --git a/patches/1335-drm-rcar-du-Add-R8A77965-support.patch b/patches/1335-drm-rcar-du-Add-R8A77965-support.patch
new file mode 100644
index 00000000000000..2aef0746090d84
--- /dev/null
+++ b/patches/1335-drm-rcar-du-Add-R8A77965-support.patch
@@ -0,0 +1,70 @@
+From b888322339e47e00f21958e147d92a858e9f1dac Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:21:54 +0100
+Subject: [PATCH 1335/1795] drm: rcar-du: Add R8A77965 support
+
+The R8A77965 (M3-N) SoC provides RGB, HDMI and LVDS output.
+
+This platform is unusual in that the RGB is connected to DU3 leaving DU2
+unpopulated. This is reflected by the channels_mask accordingly.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit f1e9a22ac3cff749077f40bf1a149aaaf587ae2d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 29 +++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index 2aa392b03e73..02aee6cb0e53 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -246,6 +246,34 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
+ 	.dpll_ch =  BIT(1),
+ };
+ 
++static const struct rcar_du_device_info rcar_du_r8a77965_info = {
++	.gen = 3,
++	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
++		  | RCAR_DU_FEATURE_EXT_CTRL_REGS
++		  | RCAR_DU_FEATURE_VSP1_SOURCE,
++	.channels_mask = BIT(3) | BIT(1) | BIT(0),
++	.routes = {
++		/*
++		 * R8A77965 has one RGB output, one LVDS output and one HDMI
++		 * output.
++		 */
++		[RCAR_DU_OUTPUT_DPAD0] = {
++			.possible_crtcs = BIT(2),
++			.port = 0,
++		},
++		[RCAR_DU_OUTPUT_HDMI0] = {
++			.possible_crtcs = BIT(1),
++			.port = 1,
++		},
++		[RCAR_DU_OUTPUT_LVDS0] = {
++			.possible_crtcs = BIT(0),
++			.port = 2,
++		},
++	},
++	.num_lvds = 1,
++	.dpll_ch =  BIT(1),
++};
++
+ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
+ 	.gen = 3,
+ 	.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+@@ -277,6 +305,7 @@ static const struct of_device_id rcar_du_of_table[] = {
+ 	{ .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
+ 	{ .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
+ 	{ .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
++	{ .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
+ 	{ .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
+ 	{ }
+ };
+-- 
+2.19.0
+
diff --git a/patches/1336-drm-rcar-du-Track-dma-buf-fences.patch b/patches/1336-drm-rcar-du-Track-dma-buf-fences.patch
new file mode 100644
index 00000000000000..bb5b3f059c0820
--- /dev/null
+++ b/patches/1336-drm-rcar-du-Track-dma-buf-fences.patch
@@ -0,0 +1,49 @@
+From 291f16ff62bdf957e6b744a0325a3f3996732c4e Mon Sep 17 00:00:00 2001
+From: Emre Ucan <eucan@de.adit-jv.com>
+Date: Mon, 30 Apr 2018 14:02:04 +0200
+Subject: [PATCH 1336/1795] drm: rcar-du: Track dma-buf fences
+
+We have to check dma-buf reservation objects of our framebuffers before
+we use them. Otherwise, another driver might be writing on the same
+buffer which we are using. This would cause visible tearing effects
+on display.
+
+We can use existing atomic helper functions to solve this problem.
+
+Signed-off-by: Emre Ucan <eucan@de.adit-jv.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+(cherry picked from commit b06078de418d6f77c81aa74516f787663f51a262)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index b2ef0f5631e7..ae95e2010a5e 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -17,6 +17,7 @@
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
++#include <drm/drm_gem_framebuffer_helper.h>
+ #include <drm/drm_plane_helper.h>
+ 
+ #include <linux/bitops.h>
+@@ -239,6 +240,10 @@ static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
+ 		}
+ 	}
+ 
++	ret = drm_gem_fb_prepare_fb(plane, state);
++	if (ret)
++		goto fail;
++
+ 	return 0;
+ 
+ fail:
+-- 
+2.19.0
+
diff --git a/patches/1337-drm-rcar-du-Fix-rcar_du_of_init-stub.patch b/patches/1337-drm-rcar-du-Fix-rcar_du_of_init-stub.patch
new file mode 100644
index 00000000000000..ef70f12ae46a6b
--- /dev/null
+++ b/patches/1337-drm-rcar-du-Fix-rcar_du_of_init-stub.patch
@@ -0,0 +1,40 @@
+From aa95abf6e2d56b0f9374fbe973321b676e5b6735 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 May 2018 18:57:36 +0300
+Subject: [PATCH 1337/1795] drm: rcar-du: Fix rcar_du_of_init() stub
+
+The rcar_du_of_init() function is supposed to be defined as a stub when
+CONFIG_DRM_RCAR_LVDS is disabled as the rcar_du_of.c file isn't compiled
+in that case. However, a bug in the configuration option check makes it
+a stub when CONFIG_DRM_RCAR_LVDS=m as well, which prevents legacy DTs
+from being fixed at boot time. Fix the configuration option check by
+using IS_ENABLED.
+
+Fixes: 81c0e3dd8292 ("drm: rcar-du: Fix legacy DT to create LVDS encoder nodes")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180515155736.3379-1-laurent.pinchart+renesas@ideasonboard.com
+(cherry picked from commit dd856d924b2471bf28e7c60df881529525a1192c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_of.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_of.h b/drivers/gpu/drm/rcar-du/rcar_du_of.h
+index c2e65a727e91..8dd3fbe96650 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_of.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_of.h
+@@ -11,7 +11,7 @@
+ 
+ struct of_device_id;
+ 
+-#ifdef CONFIG_DRM_RCAR_LVDS
++#if IS_ENABLED(CONFIG_DRM_RCAR_LVDS)
+ void __init rcar_du_of_init(const struct of_device_id *of_ids);
+ #else
+ static inline void rcar_du_of_init(const struct of_device_id *of_ids) { }
+-- 
+2.19.0
+
diff --git a/patches/1338-drm-rcar-du-Fix-build-failure.patch b/patches/1338-drm-rcar-du-Fix-build-failure.patch
new file mode 100644
index 00000000000000..7ede2700ce8546
--- /dev/null
+++ b/patches/1338-drm-rcar-du-Fix-build-failure.patch
@@ -0,0 +1,40 @@
+From 3e6ae2773f78d3d08f136c2f58dad615775d4838 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Tue, 15 May 2018 20:47:52 +0300
+Subject: [PATCH 1338/1795] drm: rcar-du: Fix build failure
+
+Commit 75a07f399cd4 ("drm: rcar-du: Zero-out sg_tables when duplicating
+plane state") introduced a reference to the alpha field of struct
+rcar_du_vsp_plane_state that got removed in commit 301a9b8d5456
+("drm/rcar-du: Convert to the new generic alpha property"). The issue
+stems from the merge of the two commits through separate branches and
+breaks compilation of the driver. Fix it.
+
+Fixes: 75a07f399cd4 ("drm: rcar-du: Zero-out sg_tables when duplicating plane state")
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180515174752.28954-1-laurent.pinchart+renesas@ideasonboard.com
+(cherry picked from commit 315852b422972e6ebb1dfddaadada09e46a2681a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index ae95e2010a5e..21cbe741d0b4 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -316,7 +316,6 @@ rcar_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane)
+ 		return NULL;
+ 
+ 	__drm_atomic_helper_plane_duplicate_state(plane, &copy->state);
+-	copy->alpha = to_rcar_vsp_plane_state(plane->state)->alpha;
+ 
+ 	return &copy->state;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1339-media-drm-rcar-du-Add-support-for-CRC-computation.patch b/patches/1339-media-drm-rcar-du-Add-support-for-CRC-computation.patch
new file mode 100644
index 00000000000000..44cd14317c3b0b
--- /dev/null
+++ b/patches/1339-media-drm-rcar-du-Add-support-for-CRC-computation.patch
@@ -0,0 +1,268 @@
+From 059bbdc61ba8e541b1ffdc15485e35b316a69f80 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 1 Dec 2017 06:59:55 -0500
+Subject: [PATCH 1339/1795] media: drm: rcar-du: Add support for CRC
+ computation
+
+Implement CRC computation configuration and reporting through the DRM
+debugfs-based CRC API. The CRC source can be configured to any input
+plane or the pipeline output.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 47a52d024e89be114df910d8331c5cabd229da98)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 156 ++++++++++++++++++++++++-
+ drivers/gpu/drm/rcar-du/rcar_du_crtc.h |  15 +++
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c  |   6 +
+ 3 files changed, 171 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+index f2a0bd1e5119..15dc9caa128b 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+@@ -691,6 +691,52 @@ static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
+ 	.atomic_disable = rcar_du_crtc_atomic_disable,
+ };
+ 
++static struct drm_crtc_state *
++rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
++{
++	struct rcar_du_crtc_state *state;
++	struct rcar_du_crtc_state *copy;
++
++	if (WARN_ON(!crtc->state))
++		return NULL;
++
++	state = to_rcar_crtc_state(crtc->state);
++	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
++	if (copy == NULL)
++		return NULL;
++
++	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
++
++	return &copy->state;
++}
++
++static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
++					      struct drm_crtc_state *state)
++{
++	__drm_atomic_helper_crtc_destroy_state(state);
++	kfree(to_rcar_crtc_state(state));
++}
++
++static void rcar_du_crtc_reset(struct drm_crtc *crtc)
++{
++	struct rcar_du_crtc_state *state;
++
++	if (crtc->state) {
++		rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
++		crtc->state = NULL;
++	}
++
++	state = kzalloc(sizeof(*state), GFP_KERNEL);
++	if (state == NULL)
++		return;
++
++	state->crc.source = VSP1_DU_CRC_NONE;
++	state->crc.index = 0;
++
++	crtc->state = &state->state;
++	crtc->state->crtc = crtc;
++}
++
+ static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
+ {
+ 	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+@@ -710,15 +756,111 @@ static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
+ 	rcrtc->vblank_enable = false;
+ }
+ 
+-static const struct drm_crtc_funcs crtc_funcs = {
+-	.reset = drm_atomic_helper_crtc_reset,
++static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
++				       const char *source_name,
++				       size_t *values_cnt)
++{
++	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
++	struct drm_modeset_acquire_ctx ctx;
++	struct drm_crtc_state *crtc_state;
++	struct drm_atomic_state *state;
++	enum vsp1_du_crc_source source;
++	unsigned int index = 0;
++	unsigned int i;
++	int ret;
++
++	/*
++	 * Parse the source name. Supported values are "plane%u" to compute the
++	 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
++	 * CRC on the composer (VSP) output.
++	 */
++	if (!source_name) {
++		source = VSP1_DU_CRC_NONE;
++	} else if (!strcmp(source_name, "auto")) {
++		source = VSP1_DU_CRC_OUTPUT;
++	} else if (strstarts(source_name, "plane")) {
++		source = VSP1_DU_CRC_PLANE;
++
++		ret = kstrtouint(source_name + strlen("plane"), 10, &index);
++		if (ret < 0)
++			return ret;
++
++		for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
++			if (index == rcrtc->vsp->planes[i].plane.base.id) {
++				index = i;
++				break;
++			}
++		}
++
++		if (i >= rcrtc->vsp->num_planes)
++			return -EINVAL;
++	} else {
++		return -EINVAL;
++	}
++
++	*values_cnt = 1;
++
++	/* Perform an atomic commit to set the CRC source. */
++	drm_modeset_acquire_init(&ctx, 0);
++
++	state = drm_atomic_state_alloc(crtc->dev);
++	if (!state) {
++		ret = -ENOMEM;
++		goto unlock;
++	}
++
++	state->acquire_ctx = &ctx;
++
++retry:
++	crtc_state = drm_atomic_get_crtc_state(state, crtc);
++	if (!IS_ERR(crtc_state)) {
++		struct rcar_du_crtc_state *rcrtc_state;
++
++		rcrtc_state = to_rcar_crtc_state(crtc_state);
++		rcrtc_state->crc.source = source;
++		rcrtc_state->crc.index = index;
++
++		ret = drm_atomic_commit(state);
++	} else {
++		ret = PTR_ERR(crtc_state);
++	}
++
++	if (ret == -EDEADLK) {
++		drm_atomic_state_clear(state);
++		drm_modeset_backoff(&ctx);
++		goto retry;
++	}
++
++	drm_atomic_state_put(state);
++
++unlock:
++	drm_modeset_drop_locks(&ctx);
++	drm_modeset_acquire_fini(&ctx);
++
++	return 0;
++}
++
++static const struct drm_crtc_funcs crtc_funcs_gen2 = {
++	.reset = rcar_du_crtc_reset,
++	.destroy = drm_crtc_cleanup,
++	.set_config = drm_atomic_helper_set_config,
++	.page_flip = drm_atomic_helper_page_flip,
++	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
++	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
++	.enable_vblank = rcar_du_crtc_enable_vblank,
++	.disable_vblank = rcar_du_crtc_disable_vblank,
++};
++
++static const struct drm_crtc_funcs crtc_funcs_gen3 = {
++	.reset = rcar_du_crtc_reset,
+ 	.destroy = drm_crtc_cleanup,
+ 	.set_config = drm_atomic_helper_set_config,
+ 	.page_flip = drm_atomic_helper_page_flip,
+-	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+-	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
++	.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
++	.atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
+ 	.enable_vblank = rcar_du_crtc_enable_vblank,
+ 	.disable_vblank = rcar_du_crtc_disable_vblank,
++	.set_crc_source = rcar_du_crtc_set_crc_source,
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -822,8 +964,10 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
+ 	else
+ 		primary = &rgrp->planes[swindex % 2].plane;
+ 
+-	ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary,
+-					NULL, &crtc_funcs, NULL);
++	ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
++					rcdu->info->gen <= 2 ?
++					&crtc_funcs_gen2 : &crtc_funcs_gen3,
++					NULL);
+ 	if (ret < 0)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+index 84b5e23a85b1..7680cb2636c8 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+@@ -21,6 +21,8 @@
+ #include <drm/drmP.h>
+ #include <drm/drm_crtc.h>
+ 
++#include <media/vsp1.h>
++
+ struct rcar_du_group;
+ struct rcar_du_vsp;
+ 
+@@ -69,6 +71,19 @@ struct rcar_du_crtc {
+ 
+ #define to_rcar_crtc(c)	container_of(c, struct rcar_du_crtc, crtc)
+ 
++/**
++ * struct rcar_du_crtc_state - Driver-specific CRTC state
++ * @state: base DRM CRTC state
++ * @crc: CRC computation configuration
++ */
++struct rcar_du_crtc_state {
++	struct drm_crtc_state state;
++
++	struct vsp1_du_crc_config crc;
++};
++
++#define to_rcar_crtc_state(s) container_of(s, struct rcar_du_crtc_state, state)
++
+ enum rcar_du_output {
+ 	RCAR_DU_OUTPUT_DPAD0,
+ 	RCAR_DU_OUTPUT_DPAD1,
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+index 21cbe741d0b4..72eebeda518e 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+@@ -41,6 +41,8 @@ static void rcar_du_vsp_complete(void *private, bool completed, u32 crc)
+ 
+ 	if (completed)
+ 		rcar_du_crtc_finish_page_flip(crtc);
++
++	drm_crtc_add_crc_entry(&crtc->crtc, false, 0, &crc);
+ }
+ 
+ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
+@@ -104,6 +106,10 @@ void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
+ void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
+ {
+ 	struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
++	struct rcar_du_crtc_state *state;
++
++	state = to_rcar_crtc_state(crtc->crtc.state);
++	cfg.crc = state->crc;
+ 
+ 	vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, &cfg);
+ }
+-- 
+2.19.0
+
diff --git a/patches/1340-soc-renesas-rcar-sysc-Add-r8a77470-support.patch b/patches/1340-soc-renesas-rcar-sysc-Add-r8a77470-support.patch
new file mode 100644
index 00000000000000..6682033611bfd5
--- /dev/null
+++ b/patches/1340-soc-renesas-rcar-sysc-Add-r8a77470-support.patch
@@ -0,0 +1,166 @@
+From fa2add1a9dc5fe535e4b29a4978764733f7fa072 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 28 Mar 2018 20:26:09 +0100
+Subject: [PATCH 1340/1795] soc: renesas: rcar-sysc: Add r8a77470 support
+
+Add support for RZ/G1C (R8A77470) SoC power areas to the R-Car SYSC
+driver.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 964f7c0dd23de68c0a3f33a91ca10775ef39ad71)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/power/renesas,rcar-sysc.txt      |  1 +
+ drivers/soc/renesas/Kconfig                   |  5 ++++
+ drivers/soc/renesas/Makefile                  |  1 +
+ drivers/soc/renesas/r8a77470-sysc.c           | 29 +++++++++++++++++++
+ drivers/soc/renesas/rcar-sysc.c               |  3 ++
+ drivers/soc/renesas/rcar-sysc.h               |  1 +
+ include/dt-bindings/power/r8a77470-sysc.h     | 22 ++++++++++++++
+ 7 files changed, 62 insertions(+)
+ create mode 100644 drivers/soc/renesas/r8a77470-sysc.c
+ create mode 100644 include/dt-bindings/power/r8a77470-sysc.h
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+index ab399e559257..3e91d2032253 100644
+--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
++++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+@@ -9,6 +9,7 @@ Required properties:
+   - compatible: Must contain exactly one of the following:
+       - "renesas,r8a7743-sysc" (RZ/G1M)
+       - "renesas,r8a7745-sysc" (RZ/G1E)
++      - "renesas,r8a77470-sysc" (RZ/G1C)
+       - "renesas,r8a7779-sysc" (R-Car H1)
+       - "renesas,r8a7790-sysc" (R-Car H2)
+       - "renesas,r8a7791-sysc" (R-Car M2-W)
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index b747aa317647..c0e0286a2360 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -8,6 +8,7 @@ config SOC_RENESAS
+ 			   ARCH_R8A77995
+ 	select SYSC_R8A7743 if ARCH_R8A7743
+ 	select SYSC_R8A7745 if ARCH_R8A7745
++	select SYSC_R8A77470 if ARCH_R8A77470
+ 	select SYSC_R8A7779 if ARCH_R8A7779
+ 	select SYSC_R8A7790 if ARCH_R8A7790
+ 	select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
+@@ -31,6 +32,10 @@ config SYSC_R8A7745
+ 	bool "RZ/G1E System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+ 
++config SYSC_R8A77470
++	bool "RZ/G1C System Controller support" if COMPILE_TEST
++	select SYSC_RCAR
++
+ config SYSC_R8A7779
+ 	bool "R-Car H1 System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index ccb5ec57a262..a86ece7b84d1 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -5,6 +5,7 @@ obj-$(CONFIG_SOC_RENESAS)	+= renesas-soc.o
+ # SoC
+ obj-$(CONFIG_SYSC_R8A7743)	+= r8a7743-sysc.o
+ obj-$(CONFIG_SYSC_R8A7745)	+= r8a7745-sysc.o
++obj-$(CONFIG_SYSC_R8A77470)	+= r8a77470-sysc.o
+ obj-$(CONFIG_SYSC_R8A7779)	+= r8a7779-sysc.o
+ obj-$(CONFIG_SYSC_R8A7790)	+= r8a7790-sysc.o
+ obj-$(CONFIG_SYSC_R8A7791)	+= r8a7791-sysc.o
+diff --git a/drivers/soc/renesas/r8a77470-sysc.c b/drivers/soc/renesas/r8a77470-sysc.c
+new file mode 100644
+index 000000000000..cfa015e208ef
+--- /dev/null
++++ b/drivers/soc/renesas/r8a77470-sysc.c
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Renesas RZ/G1C System Controller
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a77470-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a77470_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A77470_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
++	{ "ca7-scu",	0x100, 0, R8A77470_PD_CA7_SCU,	R8A77470_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca7-cpu0",	0x1c0, 0, R8A77470_PD_CA7_CPU0,	R8A77470_PD_CA7_SCU,
++	  PD_CPU_NOCR },
++	{ "ca7-cpu1",	0x1c0, 1, R8A77470_PD_CA7_CPU1,	R8A77470_PD_CA7_SCU,
++	  PD_CPU_NOCR },
++	{ "sgx",	 0xc0, 0, R8A77470_PD_SGX, R8A77470_PD_ALWAYS_ON },
++};
++
++const struct rcar_sysc_info r8a77470_sysc_info __initconst = {
++	.areas = r8a77470_areas,
++	.num_areas = ARRAY_SIZE(r8a77470_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index faf20e719361..99203bdc333a 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -261,6 +261,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
+ #ifdef CONFIG_SYSC_R8A7745
+ 	{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
+ #endif
++#ifdef CONFIG_SYSC_R8A77470
++	{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
++#endif
+ #ifdef CONFIG_SYSC_R8A7779
+ 	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
+ #endif
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index dcdc9ec8eba7..9b24e3af288f 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -51,6 +51,7 @@ struct rcar_sysc_info {
+ 
+ extern const struct rcar_sysc_info r8a7743_sysc_info;
+ extern const struct rcar_sysc_info r8a7745_sysc_info;
++extern const struct rcar_sysc_info r8a77470_sysc_info;
+ extern const struct rcar_sysc_info r8a7779_sysc_info;
+ extern const struct rcar_sysc_info r8a7790_sysc_info;
+ extern const struct rcar_sysc_info r8a7791_sysc_info;
+diff --git a/include/dt-bindings/power/r8a77470-sysc.h b/include/dt-bindings/power/r8a77470-sysc.h
+new file mode 100644
+index 000000000000..8bf4db187c31
+--- /dev/null
++++ b/include/dt-bindings/power/r8a77470-sysc.h
+@@ -0,0 +1,22 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A77470_PD_CA7_CPU0		 5
++#define R8A77470_PD_CA7_CPU1		 6
++#define R8A77470_PD_SGX			20
++#define R8A77470_PD_CA7_SCU		21
++
++/* Always-on power area */
++#define R8A77470_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1341-soc-renesas-Add-r8a77990-SYSC-PM-Domain-Binding-Defi.patch b/patches/1341-soc-renesas-Add-r8a77990-SYSC-PM-Domain-Binding-Defi.patch
new file mode 100644
index 00000000000000..62587871b18db1
--- /dev/null
+++ b/patches/1341-soc-renesas-Add-r8a77990-SYSC-PM-Domain-Binding-Defi.patch
@@ -0,0 +1,57 @@
+From ccfadc59ce6859ac6de53f53682da1ac93e1e9f9 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Wed, 11 Apr 2018 18:36:24 +0900
+Subject: [PATCH 1341/1795] soc: renesas: Add r8a77990 SYSC PM Domain Binding
+ Definitions
+
+This patch adds power domain indices for R-Car E3.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[shimoda: add commit log and SPDX-License-Identifier]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 355f9e6482b2e5c34aa46cac199eff56de286514)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/power/r8a77990-sysc.h | 26 +++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+ create mode 100644 include/dt-bindings/power/r8a77990-sysc.h
+
+diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
+new file mode 100644
+index 000000000000..944d85beec15
+--- /dev/null
++++ b/include/dt-bindings/power/r8a77990-sysc.h
+@@ -0,0 +1,26 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A77990_PD_CA53_CPU0		5
++#define R8A77990_PD_CA53_CPU1		6
++#define R8A77990_PD_CR7			13
++#define R8A77990_PD_A3VC		14
++#define R8A77990_PD_3DG_A		17
++#define R8A77990_PD_3DG_B		18
++#define R8A77990_PD_CA53_SCU		21
++#define R8A77990_PD_A2VC1		26
++
++/* Always-on power area */
++#define R8A77990_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1342-soc-renesas-r8a77995-sysc-Cleanups.patch b/patches/1342-soc-renesas-r8a77995-sysc-Cleanups.patch
new file mode 100644
index 00000000000000..09d73e3d15711e
--- /dev/null
+++ b/patches/1342-soc-renesas-r8a77995-sysc-Cleanups.patch
@@ -0,0 +1,40 @@
+From fe159e5c70594933e2cd3b750bc4f662f42cb46c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 18 Apr 2018 16:58:18 +0200
+Subject: [PATCH 1342/1795] soc: renesas: r8a77995-sysc: Cleanups
+
+Minor cleanup of artefacts caused by deriving from r8a7795-sysc.c:
+  - Remove unused inclusion of <linux/sys_soc.h>,
+  - Make r8a77995_areas[] const.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a3daeedad3828cea21a50b02866ec62d98ad90ea)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/r8a77995-sysc.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/soc/renesas/r8a77995-sysc.c b/drivers/soc/renesas/r8a77995-sysc.c
+index f718429cab02..1b2ef415bbe1 100644
+--- a/drivers/soc/renesas/r8a77995-sysc.c
++++ b/drivers/soc/renesas/r8a77995-sysc.c
+@@ -10,13 +10,12 @@
+ 
+ #include <linux/bug.h>
+ #include <linux/kernel.h>
+-#include <linux/sys_soc.h>
+ 
+ #include <dt-bindings/power/r8a77995-sysc.h>
+ 
+ #include "rcar-sysc.h"
+ 
+-static struct rcar_sysc_area r8a77995_areas[] __initdata = {
++static const struct rcar_sysc_area r8a77995_areas[] __initconst = {
+ 	{ "always-on",     0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ 	{ "ca53-scu",  0x140, 0, R8A77995_PD_CA53_SCU,  R8A77995_PD_ALWAYS_ON,
+ 	  PD_SCU },
+-- 
+2.19.0
+
diff --git a/patches/1343-soc-renesas-rcar-sysc-Add-support-for-R-Car-E3-power.patch b/patches/1343-soc-renesas-rcar-sysc-Add-support-for-R-Car-E3-power.patch
new file mode 100644
index 00000000000000..f9281f17896d93
--- /dev/null
+++ b/patches/1343-soc-renesas-rcar-sysc-Add-support-for-R-Car-E3-power.patch
@@ -0,0 +1,143 @@
+From 1776bdfa8e29fc8b5b839df57849ff420c69bec2 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Tue, 15 May 2018 21:07:38 +0900
+Subject: [PATCH 1343/1795] soc: renesas: rcar-sysc: Add support for R-Car E3
+ power areas
+
+This patch adds Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC,
+A2VC1 and 3DG-{A,B} power domain areas for the R8A77990 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[shimoda: fix 3DG-{A,B} and add SPDX-License-Identifier]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 44b12d4311d7e296d178cbad019d0537de4f8890)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/power/renesas,rcar-sysc.txt      |  1 +
+ drivers/soc/renesas/Kconfig                   |  5 +++
+ drivers/soc/renesas/Makefile                  |  1 +
+ drivers/soc/renesas/r8a77990-sysc.c           | 33 +++++++++++++++++++
+ drivers/soc/renesas/rcar-sysc.c               |  3 ++
+ drivers/soc/renesas/rcar-sysc.h               |  1 +
+ 6 files changed, 44 insertions(+)
+ create mode 100644 drivers/soc/renesas/r8a77990-sysc.c
+
+diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+index 3e91d2032253..180ae65be753 100644
+--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
++++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+@@ -21,6 +21,7 @@ Required properties:
+       - "renesas,r8a77965-sysc" (R-Car M3-N)
+       - "renesas,r8a77970-sysc" (R-Car V3M)
+       - "renesas,r8a77980-sysc" (R-Car V3H)
++      - "renesas,r8a77990-sysc" (R-Car E3)
+       - "renesas,r8a77995-sysc" (R-Car D3)
+   - reg: Address start and address range for the device.
+   - #power-domain-cells: Must be 1.
+diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
+index c0e0286a2360..1d824cbd462d 100644
+--- a/drivers/soc/renesas/Kconfig
++++ b/drivers/soc/renesas/Kconfig
+@@ -19,6 +19,7 @@ config SOC_RENESAS
+ 	select SYSC_R8A77965 if ARCH_R8A77965
+ 	select SYSC_R8A77970 if ARCH_R8A77970
+ 	select SYSC_R8A77980 if ARCH_R8A77980
++	select SYSC_R8A77990 if ARCH_R8A77990
+ 	select SYSC_R8A77995 if ARCH_R8A77995
+ 
+ if SOC_RENESAS
+@@ -76,6 +77,10 @@ config SYSC_R8A77980
+ 	bool "R-Car V3H System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+ 
++config SYSC_R8A77990
++	bool "R-Car E3 System Controller support" if COMPILE_TEST
++	select SYSC_RCAR
++
+ config SYSC_R8A77995
+ 	bool "R-Car D3 System Controller support" if COMPILE_TEST
+ 	select SYSC_RCAR
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index a86ece7b84d1..7dc0f20d7907 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_SYSC_R8A7796)	+= r8a7796-sysc.o
+ obj-$(CONFIG_SYSC_R8A77965)	+= r8a77965-sysc.o
+ obj-$(CONFIG_SYSC_R8A77970)	+= r8a77970-sysc.o
+ obj-$(CONFIG_SYSC_R8A77980)	+= r8a77980-sysc.o
++obj-$(CONFIG_SYSC_R8A77990)	+= r8a77990-sysc.o
+ obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
+ 
+ # Family
+diff --git a/drivers/soc/renesas/r8a77990-sysc.c b/drivers/soc/renesas/r8a77990-sysc.c
+new file mode 100644
+index 000000000000..a8c6417fcd2b
+--- /dev/null
++++ b/drivers/soc/renesas/r8a77990-sysc.c
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Renesas R-Car E3 System Controller
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a77990-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a77990_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A77990_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
++	{ "ca53-scu",	0x140, 0, R8A77990_PD_CA53_SCU,  R8A77990_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca53-cpu0",	0x200, 0, R8A77990_PD_CA53_CPU0, R8A77990_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu1",	0x200, 1, R8A77990_PD_CA53_CPU1, R8A77990_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "cr7",	0x240, 0, R8A77990_PD_CR7,	R8A77990_PD_ALWAYS_ON },
++	{ "a3vc",	0x380, 0, R8A77990_PD_A3VC,	R8A77990_PD_ALWAYS_ON },
++	{ "a2vc1",	0x3c0, 1, R8A77990_PD_A2VC1,	R8A77990_PD_A3VC },
++	{ "3dg-a",	0x100, 0, R8A77990_PD_3DG_A,	R8A77990_PD_ALWAYS_ON },
++	{ "3dg-b",	0x100, 1, R8A77990_PD_3DG_B,	R8A77990_PD_3DG_A },
++};
++
++const struct rcar_sysc_info r8a77990_sysc_info __initconst = {
++	.areas = r8a77990_areas,
++	.num_areas = ARRAY_SIZE(r8a77990_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 99203bdc333a..95120acc4d80 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -296,6 +296,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
+ #ifdef CONFIG_SYSC_R8A77980
+ 	{ .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
+ #endif
++#ifdef CONFIG_SYSC_R8A77990
++	{ .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
++#endif
+ #ifdef CONFIG_SYSC_R8A77995
+ 	{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
+ #endif
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index 9b24e3af288f..a22e7cf25e30 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -62,6 +62,7 @@ extern const struct rcar_sysc_info r8a7796_sysc_info;
+ extern const struct rcar_sysc_info r8a77965_sysc_info;
+ extern const struct rcar_sysc_info r8a77970_sysc_info;
+ extern const struct rcar_sysc_info r8a77980_sysc_info;
++extern const struct rcar_sysc_info r8a77990_sysc_info;
+ extern const struct rcar_sysc_info r8a77995_sysc_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/1344-soc-renesas-r8a77990-sysc-Add-workaround-for-3DG-A-B.patch b/patches/1344-soc-renesas-r8a77990-sysc-Add-workaround-for-3DG-A-B.patch
new file mode 100644
index 00000000000000..4ea940c12113e2
--- /dev/null
+++ b/patches/1344-soc-renesas-r8a77990-sysc-Add-workaround-for-3DG-A-B.patch
@@ -0,0 +1,83 @@
+From 871b829084a170c1305996410f6f11fd6195f142 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Tue, 15 May 2018 21:07:39 +0900
+Subject: [PATCH 1344/1795] soc: renesas: r8a77990-sysc: Add workaround for
+ 3DG-{A,B}
+
+This patch adds workaround for 3DG-{A,B} of R-Car E3 ES1.0 because
+the SoC has a restriction about the order.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 086b399965a7ee7e50c3b3c57f2dba30ff0334b0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/r8a77990-sysc.c | 37 ++++++++++++++++++++++++++++-
+ 1 file changed, 36 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/soc/renesas/r8a77990-sysc.c b/drivers/soc/renesas/r8a77990-sysc.c
+index a8c6417fcd2b..15579ebc5ed2 100644
+--- a/drivers/soc/renesas/r8a77990-sysc.c
++++ b/drivers/soc/renesas/r8a77990-sysc.c
+@@ -7,12 +7,13 @@
+ 
+ #include <linux/bug.h>
+ #include <linux/kernel.h>
++#include <linux/sys_soc.h>
+ 
+ #include <dt-bindings/power/r8a77990-sysc.h>
+ 
+ #include "rcar-sysc.h"
+ 
+-static const struct rcar_sysc_area r8a77990_areas[] __initconst = {
++static struct rcar_sysc_area r8a77990_areas[] __initdata = {
+ 	{ "always-on",	    0, 0, R8A77990_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ 	{ "ca53-scu",	0x140, 0, R8A77990_PD_CA53_SCU,  R8A77990_PD_ALWAYS_ON,
+ 	  PD_SCU },
+@@ -27,7 +28,41 @@ static const struct rcar_sysc_area r8a77990_areas[] __initconst = {
+ 	{ "3dg-b",	0x100, 1, R8A77990_PD_3DG_B,	R8A77990_PD_3DG_A },
+ };
+ 
++static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
++					unsigned int num_areas, u8 id,
++					int new_parent)
++{
++	unsigned int i;
++
++	for (i = 0; i < num_areas; i++)
++		if (areas[i].isr_bit == id) {
++			areas[i].parent = new_parent;
++			return;
++		}
++}
++
++/* Fixups for R-Car E3 ES1.0 revision */
++static const struct soc_device_attribute r8a77990[] __initconst = {
++	{ .soc_id = "r8a77990", .revision = "ES1.0" },
++	{ /* sentinel */ }
++};
++
++static int __init r8a77990_sysc_init(void)
++{
++	if (soc_device_match(r8a77990)) {
++		rcar_sysc_fix_parent(r8a77990_areas,
++				     ARRAY_SIZE(r8a77990_areas),
++				     R8A77990_PD_3DG_A, R8A77990_PD_3DG_B);
++		rcar_sysc_fix_parent(r8a77990_areas,
++				     ARRAY_SIZE(r8a77990_areas),
++				     R8A77990_PD_3DG_B, R8A77990_PD_ALWAYS_ON);
++	}
++
++	return 0;
++}
++
+ const struct rcar_sysc_info r8a77990_sysc_info __initconst = {
++	.init = r8a77990_sysc_init,
+ 	.areas = r8a77990_areas,
+ 	.num_areas = ARRAY_SIZE(r8a77990_areas),
+ };
+-- 
+2.19.0
+
diff --git a/patches/1345-soc-renesas-rcar-sysc-Make-PM-domain-initialization-.patch b/patches/1345-soc-renesas-rcar-sysc-Make-PM-domain-initialization-.patch
new file mode 100644
index 00000000000000..77c868d82db03a
--- /dev/null
+++ b/patches/1345-soc-renesas-rcar-sysc-Make-PM-domain-initialization-.patch
@@ -0,0 +1,111 @@
+From 1660bfe98b429367aa157505741a55ec26bb84e4 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 5 Jun 2018 17:05:15 +0200
+Subject: [PATCH 1345/1795] soc: renesas: rcar-sysc: Make PM domain
+ initialization more robust
+
+The quirk for R-Car E3 ES1.0 added in commit 086b399965a7ee7e ("soc:
+renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}") makes the 3DG-A
+PM domain a subdomain of the 3DG-B PM domain.  However, registering
+3DG-A with its parent fails silently, as the 3DG-B PM domain hasn't been
+registered yet, and such failures are never reported.
+
+Fix this by:
+  1. Splitting PM Domain initialization in two steps, so all PM domains
+     are registered before any child-parent links are established,
+  2. Reporting any failures in establishing child-parent relations.
+
+Check for and report pm_genpd_init() failures, too, as that function
+gained a return value in commit 7eb231c337e00735 ("PM / Domains: Convert
+pm_genpd_init() to return an error code").
+
+Fixes: 086b399965a7ee7e ("soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 977d5ba4507dfe5b1346597ee57750262d8d2b19)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/soc/renesas/rcar-sysc.c | 35 +++++++++++++++++++++++++++------
+ 1 file changed, 29 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 95120acc4d80..50d03d8b4f9a 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -194,11 +194,12 @@ static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
+ 
+ static bool has_cpg_mstp;
+ 
+-static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
++static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+ {
+ 	struct generic_pm_domain *genpd = &pd->genpd;
+ 	const char *name = pd->genpd.name;
+ 	struct dev_power_governor *gov = &simple_qos_governor;
++	int error;
+ 
+ 	if (pd->flags & PD_CPU) {
+ 		/*
+@@ -251,7 +252,11 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+ 	rcar_sysc_power_up(&pd->ch);
+ 
+ finalize:
+-	pm_genpd_init(genpd, gov, false);
++	error = pm_genpd_init(genpd, gov, false);
++	if (error)
++		pr_err("Failed to init PM domain %s: %d\n", name, error);
++
++	return error;
+ }
+ 
+ static const struct of_device_id rcar_sysc_matches[] __initconst = {
+@@ -375,6 +380,9 @@ static int __init rcar_sysc_pd_init(void)
+ 	pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
+ 	iowrite32(syscier, base + SYSCIER);
+ 
++	/*
++	 * First, create all PM domains
++	 */
+ 	for (i = 0; i < info->num_areas; i++) {
+ 		const struct rcar_sysc_area *area = &info->areas[i];
+ 		struct rcar_sysc_pd *pd;
+@@ -397,14 +405,29 @@ static int __init rcar_sysc_pd_init(void)
+ 		pd->ch.isr_bit = area->isr_bit;
+ 		pd->flags = area->flags;
+ 
+-		rcar_sysc_pd_setup(pd);
+-		if (area->parent >= 0)
+-			pm_genpd_add_subdomain(domains->domains[area->parent],
+-					       &pd->genpd);
++		error = rcar_sysc_pd_setup(pd);
++		if (error)
++			goto out_put;
+ 
+ 		domains->domains[area->isr_bit] = &pd->genpd;
+ 	}
+ 
++	/*
++	 * Second, link all PM domains to their parents
++	 */
++	for (i = 0; i < info->num_areas; i++) {
++		const struct rcar_sysc_area *area = &info->areas[i];
++
++		if (!area->name || area->parent < 0)
++			continue;
++
++		error = pm_genpd_add_subdomain(domains->domains[area->parent],
++					       domains->domains[area->isr_bit]);
++		if (error)
++			pr_warn("Failed to add PM subdomain %s to parent %u\n",
++				area->name, area->parent);
++	}
++
+ 	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
+ 
+ out_put:
+-- 
+2.19.0
+
diff --git a/patches/1346-ARM-smp-Add-initialization-of-CNTVOFF.patch b/patches/1346-ARM-smp-Add-initialization-of-CNTVOFF.patch
new file mode 100644
index 00000000000000..9f7ec67cba92b0
--- /dev/null
+++ b/patches/1346-ARM-smp-Add-initialization-of-CNTVOFF.patch
@@ -0,0 +1,102 @@
+From d491e3f0ab50adb4c609808f6ec7aa0a09f1dbd9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
+Date: Fri, 4 May 2018 21:05:39 +0200
+Subject: [PATCH 1346/1795] ARM: smp: Add initialization of CNTVOFF
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The CNTVOFF register from arch timer is uninitialized.
+It should be done by the bootloader but it is currently not the case,
+even for boot CPU because this SoC is booting in secure mode.
+It leads to an random offset value meaning that each CPU will have a
+different time, which isn't working very well.
+
+Add assembly code used for boot CPU and secondary CPU cores to make
+sure that the CNTVOFF register is initialized. Because this code can
+be used by different platforms, add this assembly file in ARM's common
+folder.
+
+Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+(cherry picked from commit 7c607944bc65761666dcccc1170398f17d1f919e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/common/Makefile              |  1 +
+ arch/arm/common/secure_cntvoff.S      | 32 +++++++++++++++++++++++++++
+ arch/arm/include/asm/secure_cntvoff.h |  8 +++++++
+ 3 files changed, 41 insertions(+)
+ create mode 100644 arch/arm/common/secure_cntvoff.S
+ create mode 100644 arch/arm/include/asm/secure_cntvoff.h
+
+diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
+index 70b4a14ed993..1e9f7af8f70f 100644
+--- a/arch/arm/common/Makefile
++++ b/arch/arm/common/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
+ obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
+ obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
+ obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
++obj-$(CONFIG_SMP)		+= secure_cntvoff.o
+ obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
+ obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
+ CFLAGS_REMOVE_mcpm_entry.o	= -pg
+diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
+new file mode 100644
+index 000000000000..53fc7bdb6c2e
+--- /dev/null
++++ b/arch/arm/common/secure_cntvoff.S
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2014 Renesas Electronics Corporation
++ *
++ * Initialization of CNTVOFF register from secure mode
++ *
++ */
++
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++
++ENTRY(secure_cntvoff_init)
++	.arch	armv7-a
++	/*
++	 * CNTVOFF has to be initialized either from non-secure Hypervisor
++	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
++	 * then it should be handled by the secure code. The CPU must implement
++	 * the virtualization extensions.
++	 */
++	cps	#MON_MODE
++	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
++	orr	r0, r1, #1
++	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
++	isb
++	mov	r0, #0
++	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
++	isb
++	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
++	isb
++	cps	#SVC_MODE
++	ret	lr
++ENDPROC(secure_cntvoff_init)
+diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
+new file mode 100644
+index 000000000000..1f93aee1f630
+--- /dev/null
++++ b/arch/arm/include/asm/secure_cntvoff.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef __ASMARM_ARCH_CNTVOFF_H
++#define __ASMARM_ARCH_CNTVOFF_H
++
++extern void secure_cntvoff_init(void);
++
++#endif
+-- 
+2.19.0
+
diff --git a/patches/1347-ARM-Always-build-secure_cntvoff.S-on-ARM-V7-to-fix-s.patch b/patches/1347-ARM-Always-build-secure_cntvoff.S-on-ARM-V7-to-fix-s.patch
new file mode 100644
index 00000000000000..03943944a46c22
--- /dev/null
+++ b/patches/1347-ARM-Always-build-secure_cntvoff.S-on-ARM-V7-to-fix-s.patch
@@ -0,0 +1,50 @@
+From 5a09905f34d68e75c275401bdeb4c91484ba07b9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 6 Jun 2018 11:25:16 +0200
+Subject: [PATCH 1347/1795] ARM: Always build secure_cntvoff.S on ARM V7 to fix
+ shmobile !SMP build
+
+If CONFIG_SMP=n, building a kernel for R-Car Gen2 fails with:
+
+    arch/arm/mach-shmobile/setup-rcar-gen2.o: In function `rcar_gen2_timer_init':
+    setup-rcar-gen2.c:(.init.text+0x30): undefined reference to `secure_cntvoff_init'
+
+Indeed, on R-Car Gen2 SoCs, secure_cntvoff_init() is not only needed for
+secondary CPUs, but also for the boot CPU.  This is most visible on SoCs
+with Cortex A7 cores (e.g. R-Car E2, cfr. commit 9ce3fa6816c2fb59 ("ARM:
+shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794")),
+but Cortex A15 is affected, too.
+
+Fix this by always providing secure_cntvoff_init() when building for ARM
+V7.
+
+Reported-by: Arnd Bergmann <arnd@arndb.de>
+Fixes: 7c607944bc657616 ("ARM: smp: Add initialization of CNTVOFF")
+Fixes: cad160ed0a94927e ("ARM: shmobile: Convert file to use cntvoff")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+(cherry picked from commit 0fff9001840c314fa4473dee256976b1e4535e73)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/common/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
+index 1e9f7af8f70f..3157be413297 100644
+--- a/arch/arm/common/Makefile
++++ b/arch/arm/common/Makefile
+@@ -10,7 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
+ obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
+ obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
+ obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+-obj-$(CONFIG_SMP)		+= secure_cntvoff.o
++obj-$(CONFIG_CPU_V7)		+= secure_cntvoff.o
+ obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
+ obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
+ CFLAGS_REMOVE_mcpm_entry.o	= -pg
+-- 
+2.19.0
+
diff --git a/patches/1348-ARM-shmobile-r8a77470-basic-SoC-support.patch b/patches/1348-ARM-shmobile-r8a77470-basic-SoC-support.patch
new file mode 100644
index 00000000000000..30a516358d1a58
--- /dev/null
+++ b/patches/1348-ARM-shmobile-r8a77470-basic-SoC-support.patch
@@ -0,0 +1,71 @@
+From 63816a233635ba73b52bc412061bbb77e7a752a2 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 28 Mar 2018 20:26:13 +0100
+Subject: [PATCH 1348/1795] ARM: shmobile: r8a77470: basic SoC support
+
+Add minimal support for the RZ/G1C (R8A77470) SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0c1d543b75f242f08b08e7fb63a1df2ada025903)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ arch/arm/mach-shmobile/Kconfig                     | 4 ++++
+ arch/arm/mach-shmobile/setup-rcar-gen2.c           | 2 ++
+ 3 files changed, 8 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index d3d1df97834f..86ac320323a7 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -21,6 +21,8 @@ SoCs:
+     compatible = "renesas,r8a7744"
+   - RZ/G1E (R8A77450)
+     compatible = "renesas,r8a7745"
++  - RZ/G1C (R8A77470)
++    compatible = "renesas,r8a77470"
+   - R-Car M1A (R8A77781)
+     compatible = "renesas,r8a7778"
+   - R-Car H1 (R8A77790)
+diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
+index 280e7312a9e1..6b9111455a30 100644
+--- a/arch/arm/mach-shmobile/Kconfig
++++ b/arch/arm/mach-shmobile/Kconfig
+@@ -75,6 +75,10 @@ config ARCH_R8A7745
+ 	bool "RZ/G1E (R8A77450)"
+ 	select ARCH_RCAR_GEN2
+ 
++config ARCH_R8A77470
++	bool "RZ/G1C (R8A77470)"
++	select ARCH_RCAR_GEN2
++
+ config ARCH_R8A7778
+ 	bool "R-Car M1A (R8A77781)"
+ 	select ARCH_RCAR_GEN1
+diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+index 5561dbed7a33..80de6be912e1 100644
+--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+@@ -73,6 +73,7 @@ void __init rcar_gen2_timer_init(void)
+ 	shmobile_init_cntvoff();
+ 
+ 	if (of_machine_is_compatible("renesas,r8a7745") ||
++	    of_machine_is_compatible("renesas,r8a77470") ||
+ 	    of_machine_is_compatible("renesas,r8a7792") ||
+ 	    of_machine_is_compatible("renesas,r8a7794")) {
+ 		freq = 260000000 / 8;	/* ZS / 8 */
+@@ -205,6 +206,7 @@ MACHINE_END
+ static const char * const rz_g1_boards_compat_dt[] __initconst = {
+ 	"renesas,r8a7743",
+ 	"renesas,r8a7745",
++	"renesas,r8a77470",
+ 	NULL,
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1349-ARM-shmobile-Add-the-RZ-N1-arch-to-the-shmobile-Kcon.patch b/patches/1349-ARM-shmobile-Add-the-RZ-N1-arch-to-the-shmobile-Kcon.patch
new file mode 100644
index 00000000000000..16bd3619deb5b9
--- /dev/null
+++ b/patches/1349-ARM-shmobile-Add-the-RZ-N1-arch-to-the-shmobile-Kcon.patch
@@ -0,0 +1,38 @@
+From 708c6571baf4f4dbc6768dc0bee2c8f119352799 Mon Sep 17 00:00:00 2001
+From: Michel Pollet <michel.pollet@bp.renesas.com>
+Date: Thu, 29 Mar 2018 08:47:01 +0100
+Subject: [PATCH 1349/1795] ARM: shmobile: Add the RZ/N1 arch to the shmobile
+ Kconfig
+
+Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
+the Renesas SoC collection.
+
+Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 465bb120a87793037886024aace63365ff13108b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/Kconfig | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
+index 6b9111455a30..96672da02f5f 100644
+--- a/arch/arm/mach-shmobile/Kconfig
++++ b/arch/arm/mach-shmobile/Kconfig
+@@ -114,6 +114,11 @@ config ARCH_R8A7794
+ 	bool "R-Car E2 (R8A77940)"
+ 	select ARCH_RCAR_GEN2
+ 
++config ARCH_RZN1
++	bool "RZ/N1 (R9A06G0xx) Family"
++	select ARM_AMBA
++	select CPU_V7
++
+ config ARCH_SH73A0
+ 	bool "SH-Mobile AG5 (R8A73A00)"
+ 	select ARCH_RMOBILE
+-- 
+2.19.0
+
diff --git a/patches/1350-ARM-dts-r7s72100-add-USB-device-to-device-tree.patch b/patches/1350-ARM-dts-r7s72100-add-USB-device-to-device-tree.patch
new file mode 100644
index 00000000000000..65ac4d67adf852
--- /dev/null
+++ b/patches/1350-ARM-dts-r7s72100-add-USB-device-to-device-tree.patch
@@ -0,0 +1,49 @@
+From eb717b5bf19a9c988d40e1d5f7f75382ec15d2bd Mon Sep 17 00:00:00 2001
+From: Chris Brandt <chris.brandt@renesas.com>
+Date: Mon, 8 Jan 2018 07:30:55 -0500
+Subject: [PATCH 1350/1795] ARM: dts: r7s72100: add USB device to device tree
+
+Add USB device support.
+
+Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f8ce138029058fb7b144b866ae5cdb98db58f4fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index ab9645a42eca..bd6366d1800b 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -667,4 +667,24 @@
+ 		power-domains = <&cpg_clocks>;
+ 		status = "disabled";
+ 	};
++
++	usbhs0: usb@e8010000 {
++		compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++		reg = <0xe8010000 0x1a0>;
++		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&mstp7_clks R7S72100_CLK_USB0>;
++		renesas,buswait = <4>;
++		power-domains = <&cpg_clocks>;
++		status = "disabled";
++	};
++
++	usbhs1: usb@e8207000 {
++		compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++		reg = <0xe8207000 0x1a0>;
++		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&mstp7_clks R7S72100_CLK_USB1>;
++		renesas,buswait = <4>;
++		power-domains = <&cpg_clocks>;
++		status = "disabled";
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1351-ARM-dts-r7s72100-add-soc-node.patch b/patches/1351-ARM-dts-r7s72100-add-soc-node.patch
new file mode 100644
index 00000000000000..51eda9dbe73e9d
--- /dev/null
+++ b/patches/1351-ARM-dts-r7s72100-add-soc-node.patch
@@ -0,0 +1,1007 @@
+From efd09b1670b0a0cd167a453ed79aa71b721844e0 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 12 Feb 2018 15:39:27 +0100
+Subject: [PATCH 1351/1795] ARM: dts: r7s72100: add soc node
+
+Add soc node to represent the bus and move all nodes with a base address
+into this node. This is consistent with handling of R-Car Gen3 and Gen2
+SoCs in mainline. It is intended to migrate other Renesas ARM-based
+SoCs to this scheme.
+
+The ordering is derived from simply moving each node with an address up to
+before any nodes without a base address that occur before the soc node.  To
+improve maintainability follow-up patches will sort subnodes of both the
+new soc node and the root node.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit b1548238b2252199b7ea217abbc3d96b742c7e63)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 910 ++++++++++++++++----------------
+ 1 file changed, 459 insertions(+), 451 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index bd6366d1800b..0aa74355e24f 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -15,7 +15,6 @@
+ 
+ / {
+ 	compatible = "renesas,r7s72100";
+-	interrupt-parent = <&gic>;
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
+@@ -87,6 +86,29 @@
+ 			clock-mult = <1>;
+ 			clock-div = <12>;
+ 		};
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0>;
++			clock-frequency = <400000000>;
++			clocks = <&cpg_clocks R7S72100_CLK_I>;
++			next-level-cache = <&L2>;
++		};
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
+ 
+ 		/* Special CPG clocks */
+ 		cpg_clocks: cpg_clocks@fcfe0000 {
+@@ -192,499 +214,485 @@
+ 			>;
+ 			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
+ 		};
+-	};
+-
+-	cpus {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+ 
+-		cpu@0 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a9";
+-			reg = <0>;
+-			clock-frequency = <400000000>;
+-			clocks = <&cpg_clocks R7S72100_CLK_I>;
+-			next-level-cache = <&L2>;
++		pinctrl: pin-controller@fcfe3000 {
++			compatible = "renesas,r7s72100-ports";
++
++			reg = <0xfcfe3000 0x4230>;
++
++			port0: gpio-0 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 0 6>;
++			};
++
++			port1: gpio-1 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 16 16>;
++			};
++
++			port2: gpio-2 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 32 16>;
++			};
++
++			port3: gpio-3 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 48 16>;
++			};
++
++			port4: gpio-4 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 64 16>;
++			};
++
++			port5: gpio-5 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 80 11>;
++			};
++
++			port6: gpio-6 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 96 16>;
++			};
++
++			port7: gpio-7 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 112 16>;
++			};
++
++			port8: gpio-8 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 128 16>;
++			};
++
++			port9: gpio-9 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 144 8>;
++			};
++
++			port10: gpio-10 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 160 16>;
++			};
++
++			port11: gpio-11 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 176 16>;
++			};
+ 		};
+-	};
+ 
+-	pinctrl: pin-controller@fcfe3000 {
+-		compatible = "renesas,r7s72100-ports";
+-
+-		reg = <0xfcfe3000 0x4230>;
+-
+-		port0: gpio-0 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 0 6>;
++		scif0: serial@e8007000 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8007000 64>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port1: gpio-1 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 16 16>;
++		scif1: serial@e8007800 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8007800 64>;
++			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port2: gpio-2 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 32 16>;
++		scif2: serial@e8008000 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8008000 64>;
++			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port3: gpio-3 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 48 16>;
++		scif3: serial@e8008800 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8008800 64>;
++			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port4: gpio-4 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 64 16>;
++		scif4: serial@e8009000 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8009000 64>;
++			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port5: gpio-5 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 80 11>;
++		scif5: serial@e8009800 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe8009800 64>;
++			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port6: gpio-6 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 96 16>;
++		scif6: serial@e800a000 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe800a000 64>;
++			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port7: gpio-7 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 112 16>;
++		scif7: serial@e800a800 {
++			compatible = "renesas,scif-r7s72100", "renesas,scif";
++			reg = <0xe800a800 64>;
++			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
+ 		};
+ 
+-		port8: gpio-8 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 128 16>;
++		spi0: spi@e800c800 {
++			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
++			reg = <0xe800c800 0x24>;
++			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error", "rx", "tx";
++			clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
++			power-domains = <&cpg_clocks>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+-		port9: gpio-9 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 144 8>;
++		spi1: spi@e800d000 {
++			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
++			reg = <0xe800d000 0x24>;
++			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error", "rx", "tx";
++			clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
++			power-domains = <&cpg_clocks>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+-		port10: gpio-10 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 160 16>;
++		spi2: spi@e800d800 {
++			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
++			reg = <0xe800d800 0x24>;
++			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error", "rx", "tx";
++			clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
++			power-domains = <&cpg_clocks>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+-		port11: gpio-11 {
+-			gpio-controller;
+-			#gpio-cells = <2>;
+-			gpio-ranges = <&pinctrl 0 176 16>;
++		spi3: spi@e800e000 {
++			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
++			reg = <0xe800e000 0x24>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error", "rx", "tx";
++			clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
++			power-domains = <&cpg_clocks>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+-	};
+-
+-	scif0: serial@e8007000 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8007000 64>;
+-		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif1: serial@e8007800 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8007800 64>;
+-		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif2: serial@e8008000 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8008000 64>;
+-		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif3: serial@e8008800 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8008800 64>;
+-		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif4: serial@e8009000 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8009000 64>;
+-		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif5: serial@e8009800 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe8009800 64>;
+-		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif6: serial@e800a000 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe800a000 64>;
+-		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	scif7: serial@e800a800 {
+-		compatible = "renesas,scif-r7s72100", "renesas,scif";
+-		reg = <0xe800a800 64>;
+-		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
+-
+-	spi0: spi@e800c800 {
+-		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+-		reg = <0xe800c800 0x24>;
+-		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error", "rx", "tx";
+-		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+-		power-domains = <&cpg_clocks>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	spi1: spi@e800d000 {
+-		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+-		reg = <0xe800d000 0x24>;
+-		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error", "rx", "tx";
+-		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+-		power-domains = <&cpg_clocks>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	spi2: spi@e800d800 {
+-		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+-		reg = <0xe800d800 0x24>;
+-		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error", "rx", "tx";
+-		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+-		power-domains = <&cpg_clocks>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+ 
+-	spi3: spi@e800e000 {
+-		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+-		reg = <0xe800e000 0x24>;
+-		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error", "rx", "tx";
+-		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+-		power-domains = <&cpg_clocks>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
+-
+-	spi4: spi@e800e800 {
+-		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+-		reg = <0xe800e800 0x24>;
+-		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "error", "rx", "tx";
+-		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+-		power-domains = <&cpg_clocks>;
+-		num-cs = <1>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		spi4: spi@e800e800 {
++			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
++			reg = <0xe800e800 0x24>;
++			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error", "rx", "tx";
++			clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
++			power-domains = <&cpg_clocks>;
++			num-cs = <1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	gic: interrupt-controller@e8201000 {
+-		compatible = "arm,pl390";
+-		#interrupt-cells = <3>;
+-		#address-cells = <0>;
+-		interrupt-controller;
+-		reg = <0xe8201000 0x1000>,
+-			<0xe8202000 0x1000>;
+-	};
++		gic: interrupt-controller@e8201000 {
++			compatible = "arm,pl390";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0xe8201000 0x1000>,
++				<0xe8202000 0x1000>;
++		};
+ 
+-	L2: cache-controller@3ffff000 {
+-		compatible = "arm,pl310-cache";
+-		reg = <0x3ffff000 0x1000>;
+-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		arm,early-bresp-disable;
+-		arm,full-line-zero-disable;
+-		cache-unified;
+-		cache-level = <2>;
+-	};
++		L2: cache-controller@3ffff000 {
++			compatible = "arm,pl310-cache";
++			reg = <0x3ffff000 0x1000>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			arm,early-bresp-disable;
++			arm,full-line-zero-disable;
++			cache-unified;
++			cache-level = <2>;
++		};
+ 
+-	wdt: watchdog@fcfe0000 {
+-		compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+-		reg = <0xfcfe0000 0x6>;
+-		interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+-		clocks = <&p0_clk>;
+-	};
++		wdt: watchdog@fcfe0000 {
++			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
++			reg = <0xfcfe0000 0x6>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
++			clocks = <&p0_clk>;
++		};
+ 
+-	i2c0: i2c@fcfee000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+-		reg = <0xfcfee000 0x44>;
+-		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+-		clock-frequency = <100000>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		i2c0: i2c@fcfee000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
++			reg = <0xfcfee000 0x44>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
++			clock-frequency = <100000>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	i2c1: i2c@fcfee400 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+-		reg = <0xfcfee400 0x44>;
+-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
+-		clock-frequency = <100000>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		i2c1: i2c@fcfee400 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
++			reg = <0xfcfee400 0x44>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
++			clock-frequency = <100000>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	i2c2: i2c@fcfee800 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+-		reg = <0xfcfee800 0x44>;
+-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
+-		clock-frequency = <100000>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		i2c2: i2c@fcfee800 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
++			reg = <0xfcfee800 0x44>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
++			clock-frequency = <100000>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	i2c3: i2c@fcfeec00 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+-		reg = <0xfcfeec00 0x44>;
+-		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+-			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
+-		clock-frequency = <100000>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		i2c3: i2c@fcfeec00 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
++			reg = <0xfcfeec00 0x44>;
++			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
++			clock-frequency = <100000>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	mtu2: timer@fcff0000 {
+-		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+-		reg = <0xfcff0000 0x400>;
+-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "tgi0a";
+-		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+-		clock-names = "fck";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		mtu2: timer@fcff0000 {
++			compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
++			reg = <0xfcff0000 0x400>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "tgi0a";
++			clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
++			clock-names = "fck";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	ether: ethernet@e8203000 {
+-		compatible = "renesas,ether-r7s72100";
+-		reg = <0xe8203000 0x800>,
+-		      <0xe8204800 0x200>;
+-		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
+-		power-domains = <&cpg_clocks>;
+-		phy-mode = "mii";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-	};
++		ether: ethernet@e8203000 {
++			compatible = "renesas,ether-r7s72100";
++			reg = <0xe8203000 0x800>,
++			      <0xe8204800 0x200>;
++			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
++			power-domains = <&cpg_clocks>;
++			phy-mode = "mii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-	mmcif: mmc@e804c800 {
+-		compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
+-		reg = <0xe804c800 0x80>;
+-		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+-		power-domains = <&cpg_clocks>;
+-		reg-io-width = <4>;
+-		bus-width = <8>;
+-		status = "disabled";
+-	};
++		mmcif: mmc@e804c800 {
++			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
++			reg = <0xe804c800 0x80>;
++			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
++			power-domains = <&cpg_clocks>;
++			reg-io-width = <4>;
++			bus-width = <8>;
++			status = "disabled";
++		};
+ 
+-	sdhi0: sd@e804e000 {
+-		compatible = "renesas,sdhi-r7s72100";
+-		reg = <0xe804e000 0x100>;
+-		interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+-			 <&mstp12_clks R7S72100_CLK_SDHI01>;
+-		clock-names = "core", "cd";
+-		power-domains = <&cpg_clocks>;
+-		cap-sd-highspeed;
+-		cap-sdio-irq;
+-		status = "disabled";
+-	};
++		sdhi0: sd@e804e000 {
++			compatible = "renesas,sdhi-r7s72100";
++			reg = <0xe804e000 0x100>;
++			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++
++			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
++				 <&mstp12_clks R7S72100_CLK_SDHI01>;
++			clock-names = "core", "cd";
++			power-domains = <&cpg_clocks>;
++			cap-sd-highspeed;
++			cap-sdio-irq;
++			status = "disabled";
++		};
+ 
+-	sdhi1: sd@e804e800 {
+-		compatible = "renesas,sdhi-r7s72100";
+-		reg = <0xe804e800 0x100>;
+-		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
+-			      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+-
+-		clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+-			 <&mstp12_clks R7S72100_CLK_SDHI11>;
+-		clock-names = "core", "cd";
+-		power-domains = <&cpg_clocks>;
+-		cap-sd-highspeed;
+-		cap-sdio-irq;
+-		status = "disabled";
+-	};
++		sdhi1: sd@e804e800 {
++			compatible = "renesas,sdhi-r7s72100";
++			reg = <0xe804e800 0x100>;
++			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
++
++			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
++				 <&mstp12_clks R7S72100_CLK_SDHI11>;
++			clock-names = "core", "cd";
++			power-domains = <&cpg_clocks>;
++			cap-sd-highspeed;
++			cap-sdio-irq;
++			status = "disabled";
++		};
+ 
+-	ostm0: timer@fcfec000 {
+-		compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+-		reg = <0xfcfec000 0x30>;
+-		interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+-		clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		ostm0: timer@fcfec000 {
++			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
++			reg = <0xfcfec000 0x30>;
++			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
++			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	ostm1: timer@fcfec400 {
+-		compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+-		reg = <0xfcfec400 0x30>;
+-		interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+-		clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		ostm1: timer@fcfec400 {
++			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
++			reg = <0xfcfec400 0x30>;
++			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
++			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	rtc: rtc@fcff1000 {
+-		compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+-		reg = <0xfcff1000 0x2e>;
+-		interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
+-			      GIC_SPI 277 IRQ_TYPE_EDGE_RISING
+-			      GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
+-		interrupt-names = "alarm", "period", "carry";
+-		clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+-			 <&rtc_x3_clk>, <&extal_clk>;
+-		clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		rtc: rtc@fcff1000 {
++			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
++			reg = <0xfcff1000 0x2e>;
++			interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
++				      GIC_SPI 277 IRQ_TYPE_EDGE_RISING
++				      GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
++			interrupt-names = "alarm", "period", "carry";
++			clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
++				 <&rtc_x3_clk>, <&extal_clk>;
++			clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	usbhs0: usb@e8010000 {
+-		compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+-		reg = <0xe8010000 0x1a0>;
+-		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R7S72100_CLK_USB0>;
+-		renesas,buswait = <4>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
+-	};
++		usbhs0: usb@e8010000 {
++			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++			reg = <0xe8010000 0x1a0>;
++			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_USB0>;
++			renesas,buswait = <4>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 
+-	usbhs1: usb@e8207000 {
+-		compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+-		reg = <0xe8207000 0x1a0>;
+-		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&mstp7_clks R7S72100_CLK_USB1>;
+-		renesas,buswait = <4>;
+-		power-domains = <&cpg_clocks>;
+-		status = "disabled";
++		usbhs1: usb@e8207000 {
++			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++			reg = <0xe8207000 0x1a0>;
++			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_USB1>;
++			renesas,buswait = <4>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1352-ARM-dts-r7s72100-sort-subnodes-of-soc-node.patch b/patches/1352-ARM-dts-r7s72100-sort-subnodes-of-soc-node.patch
new file mode 100644
index 00000000000000..e7df7f53e7c43f
--- /dev/null
+++ b/patches/1352-ARM-dts-r7s72100-sort-subnodes-of-soc-node.patch
@@ -0,0 +1,638 @@
+From b0819d0fe56d661e62320a951eebe57456d8b30d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 12 Feb 2018 15:39:28 +0100
+Subject: [PATCH 1352/1795] ARM: dts: r7s72100: sort subnodes of soc node
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort key is the address on the bus with instances of the same
+IP block grouped together and sorted alphabetically.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f7255d1fa215fd68be876b0de5e2bf68eadfe9cf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 570 ++++++++++++++++----------------
+ 1 file changed, 285 insertions(+), 285 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index 0aa74355e24f..0d63dbe11e0d 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -110,187 +110,14 @@
+ 		#size-cells = <1>;
+ 		ranges;
+ 
+-		/* Special CPG clocks */
+-		cpg_clocks: cpg_clocks@fcfe0000 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-cpg-clocks",
+-				     "renesas,rz-cpg-clocks";
+-			reg = <0xfcfe0000 0x18>;
+-			clocks = <&extal_clk>, <&usb_x1_clk>;
+-			clock-output-names = "pll", "i", "g";
+-			#power-domain-cells = <0>;
+-		};
+-
+-		/* MSTP clocks */
+-		mstp3_clks: mstp3_clks@fcfe0420 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0420 4>;
+-			clocks = <&p0_clk>;
+-			clock-indices = <R7S72100_CLK_MTU2>;
+-			clock-output-names = "mtu2";
+-		};
+-
+-		mstp4_clks: mstp4_clks@fcfe0424 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0424 4>;
+-			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+-				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+-			clock-indices = <
+-				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
+-				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
+-			>;
+-			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
+-		};
+-
+-		mstp5_clks: mstp5_clks@fcfe0428 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0428 4>;
+-			clocks = <&p0_clk>, <&p0_clk>;
+-			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
+-			clock-output-names = "ostm0", "ostm1";
+-		};
+-
+-		mstp6_clks: mstp6_clks@fcfe042c {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe042c 4>;
+-			clocks = <&p0_clk>;
+-			clock-indices = <R7S72100_CLK_RTC>;
+-			clock-output-names = "rtc";
+-		};
+-
+-		mstp7_clks: mstp7_clks@fcfe0430 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0430 4>;
+-			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
+-			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
+-			clock-output-names = "ether", "usb0", "usb1";
+-		};
+-
+-		mstp8_clks: mstp8_clks@fcfe0434 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0434 4>;
+-			clocks = <&p1_clk>;
+-			clock-indices = <R7S72100_CLK_MMCIF>;
+-			clock-output-names = "mmcif";
+-		};
+-
+-		mstp9_clks: mstp9_clks@fcfe0438 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0438 4>;
+-			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+-			clock-indices = <
+-				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+-			>;
+-			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+-		};
+-
+-		mstp10_clks: mstp10_clks@fcfe043c {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe043c 4>;
+-			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+-				 <&p1_clk>;
+-			clock-indices = <
+-				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
+-				R7S72100_CLK_SPI4
+-			>;
+-			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
+-		};
+-		mstp12_clks: mstp12_clks@fcfe0444 {
+-			#clock-cells = <1>;
+-			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+-			reg = <0xfcfe0444 4>;
+-			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+-			clock-indices = <
+-				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+-				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+-			>;
+-			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
+-		};
+-
+-		pinctrl: pin-controller@fcfe3000 {
+-			compatible = "renesas,r7s72100-ports";
+-
+-			reg = <0xfcfe3000 0x4230>;
+-
+-			port0: gpio-0 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 0 6>;
+-			};
+-
+-			port1: gpio-1 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 16 16>;
+-			};
+-
+-			port2: gpio-2 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 32 16>;
+-			};
+-
+-			port3: gpio-3 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 48 16>;
+-			};
+-
+-			port4: gpio-4 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 64 16>;
+-			};
+-
+-			port5: gpio-5 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 80 11>;
+-			};
+-
+-			port6: gpio-6 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 96 16>;
+-			};
+-
+-			port7: gpio-7 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 112 16>;
+-			};
+-
+-			port8: gpio-8 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 128 16>;
+-			};
+-
+-			port9: gpio-9 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 144 8>;
+-			};
+-
+-			port10: gpio-10 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 160 16>;
+-			};
+-
+-			port11: gpio-11 {
+-				gpio-controller;
+-				#gpio-cells = <2>;
+-				gpio-ranges = <&pinctrl 0 176 16>;
+-			};
++		L2: cache-controller@3ffff000 {
++			compatible = "arm,pl310-cache";
++			reg = <0x3ffff000 0x1000>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			arm,early-bresp-disable;
++			arm,full-line-zero-disable;
++			cache-unified;
++			cache-level = <2>;
+ 		};
+ 
+ 		scif0: serial@e8007000 {
+@@ -472,6 +299,71 @@
+ 			status = "disabled";
+ 		};
+ 
++		usbhs0: usb@e8010000 {
++			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++			reg = <0xe8010000 0x1a0>;
++			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_USB0>;
++			renesas,buswait = <4>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
++
++		usbhs1: usb@e8207000 {
++			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
++			reg = <0xe8207000 0x1a0>;
++			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_USB1>;
++			renesas,buswait = <4>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
++
++		mmcif: mmc@e804c800 {
++			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
++			reg = <0xe804c800 0x80>;
++			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
++			power-domains = <&cpg_clocks>;
++			reg-io-width = <4>;
++			bus-width = <8>;
++			status = "disabled";
++		};
++
++		sdhi0: sd@e804e000 {
++			compatible = "renesas,sdhi-r7s72100";
++			reg = <0xe804e000 0x100>;
++			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
++
++			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
++				 <&mstp12_clks R7S72100_CLK_SDHI01>;
++			clock-names = "core", "cd";
++			power-domains = <&cpg_clocks>;
++			cap-sd-highspeed;
++			cap-sdio-irq;
++			status = "disabled";
++		};
++
++		sdhi1: sd@e804e800 {
++			compatible = "renesas,sdhi-r7s72100";
++			reg = <0xe804e800 0x100>;
++			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
++
++			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
++				 <&mstp12_clks R7S72100_CLK_SDHI11>;
++			clock-names = "core", "cd";
++			power-domains = <&cpg_clocks>;
++			cap-sd-highspeed;
++			cap-sdio-irq;
++			status = "disabled";
++		};
++
+ 		gic: interrupt-controller@e8201000 {
+ 			compatible = "arm,pl390";
+ 			#interrupt-cells = <3>;
+@@ -481,14 +373,17 @@
+ 				<0xe8202000 0x1000>;
+ 		};
+ 
+-		L2: cache-controller@3ffff000 {
+-			compatible = "arm,pl310-cache";
+-			reg = <0x3ffff000 0x1000>;
+-			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-			arm,early-bresp-disable;
+-			arm,full-line-zero-disable;
+-			cache-unified;
+-			cache-level = <2>;
++		ether: ethernet@e8203000 {
++			compatible = "renesas,ether-r7s72100";
++			reg = <0xe8203000 0x800>,
++			      <0xe8204800 0x200>;
++			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
++			power-domains = <&cpg_clocks>;
++			phy-mode = "mii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		wdt: watchdog@fcfe0000 {
+@@ -498,6 +393,207 @@
+ 			clocks = <&p0_clk>;
+ 		};
+ 
++		/* Special CPG clocks */
++		cpg_clocks: cpg_clocks@fcfe0000 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-cpg-clocks",
++				     "renesas,rz-cpg-clocks";
++			reg = <0xfcfe0000 0x18>;
++			clocks = <&extal_clk>, <&usb_x1_clk>;
++			clock-output-names = "pll", "i", "g";
++			#power-domain-cells = <0>;
++		};
++
++		/* MSTP clocks */
++		mstp3_clks: mstp3_clks@fcfe0420 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0420 4>;
++			clocks = <&p0_clk>;
++			clock-indices = <R7S72100_CLK_MTU2>;
++			clock-output-names = "mtu2";
++		};
++
++		mstp4_clks: mstp4_clks@fcfe0424 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0424 4>;
++			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
++				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
++			clock-indices = <
++				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
++				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
++			>;
++			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
++		};
++
++		mstp5_clks: mstp5_clks@fcfe0428 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0428 4>;
++			clocks = <&p0_clk>, <&p0_clk>;
++			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
++			clock-output-names = "ostm0", "ostm1";
++		};
++
++		mstp6_clks: mstp6_clks@fcfe042c {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe042c 4>;
++			clocks = <&p0_clk>;
++			clock-indices = <R7S72100_CLK_RTC>;
++			clock-output-names = "rtc";
++		};
++
++		mstp7_clks: mstp7_clks@fcfe0430 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0430 4>;
++			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
++			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
++			clock-output-names = "ether", "usb0", "usb1";
++		};
++
++		mstp8_clks: mstp8_clks@fcfe0434 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0434 4>;
++			clocks = <&p1_clk>;
++			clock-indices = <R7S72100_CLK_MMCIF>;
++			clock-output-names = "mmcif";
++		};
++
++		mstp9_clks: mstp9_clks@fcfe0438 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0438 4>;
++			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
++			clock-indices = <
++				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
++			>;
++			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
++		};
++
++		mstp10_clks: mstp10_clks@fcfe043c {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe043c 4>;
++			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
++				 <&p1_clk>;
++			clock-indices = <
++				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
++				R7S72100_CLK_SPI4
++			>;
++			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
++		};
++		mstp12_clks: mstp12_clks@fcfe0444 {
++			#clock-cells = <1>;
++			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
++			reg = <0xfcfe0444 4>;
++			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
++			clock-indices = <
++				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
++				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
++			>;
++			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
++		};
++
++		pinctrl: pin-controller@fcfe3000 {
++			compatible = "renesas,r7s72100-ports";
++
++			reg = <0xfcfe3000 0x4230>;
++
++			port0: gpio-0 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 0 6>;
++			};
++
++			port1: gpio-1 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 16 16>;
++			};
++
++			port2: gpio-2 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 32 16>;
++			};
++
++			port3: gpio-3 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 48 16>;
++			};
++
++			port4: gpio-4 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 64 16>;
++			};
++
++			port5: gpio-5 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 80 11>;
++			};
++
++			port6: gpio-6 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 96 16>;
++			};
++
++			port7: gpio-7 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 112 16>;
++			};
++
++			port8: gpio-8 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 128 16>;
++			};
++
++			port9: gpio-9 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 144 8>;
++			};
++
++			port10: gpio-10 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 160 16>;
++			};
++
++			port11: gpio-11 {
++				gpio-controller;
++				#gpio-cells = <2>;
++				gpio-ranges = <&pinctrl 0 176 16>;
++			};
++		};
++
++		ostm0: timer@fcfec000 {
++			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
++			reg = <0xfcfec000 0x30>;
++			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
++			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
++
++		ostm1: timer@fcfec400 {
++			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
++			reg = <0xfcfec400 0x30>;
++			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
++			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
++
+ 		i2c0: i2c@fcfee000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -585,82 +681,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		ether: ethernet@e8203000 {
+-			compatible = "renesas,ether-r7s72100";
+-			reg = <0xe8203000 0x800>,
+-			      <0xe8204800 0x200>;
+-			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
+-			power-domains = <&cpg_clocks>;
+-			phy-mode = "mii";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		mmcif: mmc@e804c800 {
+-			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
+-			reg = <0xe804c800 0x80>;
+-			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+-			power-domains = <&cpg_clocks>;
+-			reg-io-width = <4>;
+-			bus-width = <8>;
+-			status = "disabled";
+-		};
+-
+-		sdhi0: sd@e804e000 {
+-			compatible = "renesas,sdhi-r7s72100";
+-			reg = <0xe804e000 0x100>;
+-			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+-				 <&mstp12_clks R7S72100_CLK_SDHI01>;
+-			clock-names = "core", "cd";
+-			power-domains = <&cpg_clocks>;
+-			cap-sd-highspeed;
+-			cap-sdio-irq;
+-			status = "disabled";
+-		};
+-
+-		sdhi1: sd@e804e800 {
+-			compatible = "renesas,sdhi-r7s72100";
+-			reg = <0xe804e800 0x100>;
+-			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+-
+-			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+-				 <&mstp12_clks R7S72100_CLK_SDHI11>;
+-			clock-names = "core", "cd";
+-			power-domains = <&cpg_clocks>;
+-			cap-sd-highspeed;
+-			cap-sdio-irq;
+-			status = "disabled";
+-		};
+-
+-		ostm0: timer@fcfec000 {
+-			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+-			reg = <0xfcfec000 0x30>;
+-			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+-			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+-			power-domains = <&cpg_clocks>;
+-			status = "disabled";
+-		};
+-
+-		ostm1: timer@fcfec400 {
+-			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+-			reg = <0xfcfec400 0x30>;
+-			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+-			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+-			power-domains = <&cpg_clocks>;
+-			status = "disabled";
+-		};
+-
+ 		rtc: rtc@fcff1000 {
+ 			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+ 			reg = <0xfcff1000 0x2e>;
+@@ -674,25 +694,5 @@
+ 			power-domains = <&cpg_clocks>;
+ 			status = "disabled";
+ 		};
+-
+-		usbhs0: usb@e8010000 {
+-			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+-			reg = <0xe8010000 0x1a0>;
+-			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R7S72100_CLK_USB0>;
+-			renesas,buswait = <4>;
+-			power-domains = <&cpg_clocks>;
+-			status = "disabled";
+-		};
+-
+-		usbhs1: usb@e8207000 {
+-			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+-			reg = <0xe8207000 0x1a0>;
+-			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&mstp7_clks R7S72100_CLK_USB1>;
+-			renesas,buswait = <4>;
+-			power-domains = <&cpg_clocks>;
+-			status = "disabled";
+-		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1353-ARM-dts-r7s72100-stop-grouping-clocks-under-a-clocks.patch b/patches/1353-ARM-dts-r7s72100-stop-grouping-clocks-under-a-clocks.patch
new file mode 100644
index 00000000000000..b0d11b630c3c1f
--- /dev/null
+++ b/patches/1353-ARM-dts-r7s72100-stop-grouping-clocks-under-a-clocks.patch
@@ -0,0 +1,139 @@
+From edfd933e82e79e3a98773691af9ff45361953aca Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 12 Feb 2018 15:39:29 +0100
+Subject: [PATCH 1353/1795] ARM: dts: r7s72100: stop grouping clocks under a
+ "clocks" subnode
+
+The current practice is to not group clocks under a "clocks" subnode,
+but just put them together with the other on-SoC devices.
+
+As per updates for R-Car Gen2 SoCs by Geert Uytterhoeven.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6f9fe6a6521c84f267a08ee74090fc45d3ee199b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 104 +++++++++++++++-----------------
+ 1 file changed, 49 insertions(+), 55 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index 0d63dbe11e0d..d69d4810e597 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -30,62 +30,56 @@
+ 		spi4 = &spi4;
+ 	};
+ 
+-	clocks {
+-		ranges;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
++	/* External clocks */
++	extal_clk: extal {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board */
++		clock-frequency = <0>;
++	};
+ 
+-		/* External clocks */
+-		extal_clk: extal {
+-			#clock-cells = <0>;
+-			compatible = "fixed-clock";
+-			/* If clk present, value must be set by board */
+-			clock-frequency = <0>;
+-		};
+-
+-		usb_x1_clk: usb_x1 {
+-			#clock-cells = <0>;
+-			compatible = "fixed-clock";
+-			/* If clk present, value must be set by board */
+-			clock-frequency = <0>;
+-		};
+-
+-		rtc_x1_clk: rtc_x1 {
+-			#clock-cells = <0>;
+-			compatible = "fixed-clock";
+-			/* If clk present, value must be set by board to 32678 */
+-			clock-frequency = <0>;
+-		};
+-
+-		rtc_x3_clk: rtc_x3 {
+-			#clock-cells = <0>;
+-			compatible = "fixed-clock";
+-			/* If clk present, value must be set by board to 4000000 */
+-			clock-frequency = <0>;
+-		};
+-
+-		/* Fixed factor clocks */
+-		b_clk: b {
+-			#clock-cells = <0>;
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+-			clock-mult = <1>;
+-			clock-div = <3>;
+-		};
+-		p1_clk: p1 {
+-			#clock-cells = <0>;
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+-			clock-mult = <1>;
+-			clock-div = <6>;
+-		};
+-		p0_clk: p0 {
+-			#clock-cells = <0>;
+-			compatible = "fixed-factor-clock";
+-			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+-			clock-mult = <1>;
+-			clock-div = <12>;
+-		};
++	usb_x1_clk: usb_x1 {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board */
++		clock-frequency = <0>;
++	};
++
++	rtc_x1_clk: rtc_x1 {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board to 32678 */
++		clock-frequency = <0>;
++	};
++
++	rtc_x3_clk: rtc_x3 {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board to 4000000 */
++		clock-frequency = <0>;
++	};
++
++	/* Fixed factor clocks */
++	b_clk: b {
++		#clock-cells = <0>;
++		compatible = "fixed-factor-clock";
++		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
++		clock-mult = <1>;
++		clock-div = <3>;
++	};
++	p1_clk: p1 {
++		#clock-cells = <0>;
++		compatible = "fixed-factor-clock";
++		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
++		clock-mult = <1>;
++		clock-div = <6>;
++	};
++	p0_clk: p0 {
++		#clock-cells = <0>;
++		compatible = "fixed-factor-clock";
++		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
++		clock-mult = <1>;
++		clock-div = <12>;
+ 	};
+ 
+ 	cpus {
+-- 
+2.19.0
+
diff --git a/patches/1354-ARM-dts-r7s72100-sort-subnodes-of-root-node.patch b/patches/1354-ARM-dts-r7s72100-sort-subnodes-of-root-node.patch
new file mode 100644
index 00000000000000..b1a7102e5b0658
--- /dev/null
+++ b/patches/1354-ARM-dts-r7s72100-sort-subnodes-of-root-node.patch
@@ -0,0 +1,142 @@
+From bcb7d5a0079dd3813b1b9f7c6569ddbb71113586 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 12 Feb 2018 15:39:30 +0100
+Subject: [PATCH 1354/1795] ARM: dts: r7s72100: sort subnodes of root node
+
+Sort the subnodes of the soc node to improve maintainability.
+The sort has been done alphabetically with the node name as the key.
+
+This patch should not introduce any functional change.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5db40d7b26d30ac8b7c21313afe03d678cfffaa9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 78 +++++++++++++++++----------------
+ 1 file changed, 40 insertions(+), 38 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index d69d4810e597..ecf9516bcda8 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -30,43 +30,45 @@
+ 		spi4 = &spi4;
+ 	};
+ 
+-	/* External clocks */
+-	extal_clk: extal {
++	/* Fixed factor clocks */
++	b_clk: b {
+ 		#clock-cells = <0>;
+-		compatible = "fixed-clock";
+-		/* If clk present, value must be set by board */
+-		clock-frequency = <0>;
++		compatible = "fixed-factor-clock";
++		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
++		clock-mult = <1>;
++		clock-div = <3>;
+ 	};
+ 
+-	usb_x1_clk: usb_x1 {
+-		#clock-cells = <0>;
+-		compatible = "fixed-clock";
+-		/* If clk present, value must be set by board */
+-		clock-frequency = <0>;
+-	};
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
+ 
+-	rtc_x1_clk: rtc_x1 {
+-		#clock-cells = <0>;
+-		compatible = "fixed-clock";
+-		/* If clk present, value must be set by board to 32678 */
+-		clock-frequency = <0>;
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0>;
++			clock-frequency = <400000000>;
++			clocks = <&cpg_clocks R7S72100_CLK_I>;
++			next-level-cache = <&L2>;
++		};
+ 	};
+ 
+-	rtc_x3_clk: rtc_x3 {
++	/* External clocks */
++	extal_clk: extal {
+ 		#clock-cells = <0>;
+ 		compatible = "fixed-clock";
+-		/* If clk present, value must be set by board to 4000000 */
++		/* If clk present, value must be set by board */
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* Fixed factor clocks */
+-	b_clk: b {
++	p0_clk: p0 {
+ 		#clock-cells = <0>;
+ 		compatible = "fixed-factor-clock";
+ 		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+ 		clock-mult = <1>;
+-		clock-div = <3>;
++		clock-div = <12>;
+ 	};
++
+ 	p1_clk: p1 {
+ 		#clock-cells = <0>;
+ 		compatible = "fixed-factor-clock";
+@@ -74,26 +76,19 @@
+ 		clock-mult = <1>;
+ 		clock-div = <6>;
+ 	};
+-	p0_clk: p0 {
++
++	rtc_x1_clk: rtc_x1 {
+ 		#clock-cells = <0>;
+-		compatible = "fixed-factor-clock";
+-		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+-		clock-mult = <1>;
+-		clock-div = <12>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board to 32678 */
++		clock-frequency = <0>;
+ 	};
+ 
+-	cpus {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+-		cpu@0 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a9";
+-			reg = <0>;
+-			clock-frequency = <400000000>;
+-			clocks = <&cpg_clocks R7S72100_CLK_I>;
+-			next-level-cache = <&L2>;
+-		};
++	rtc_x3_clk: rtc_x3 {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board to 4000000 */
++		clock-frequency = <0>;
+ 	};
+ 
+ 	soc {
+@@ -689,4 +684,11 @@
+ 			status = "disabled";
+ 		};
+ 	};
++
++	usb_x1_clk: usb_x1 {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		/* If clk present, value must be set by board */
++		clock-frequency = <0>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1355-ARM-dts-r8a77470-Initial-SoC-device-tree.patch b/patches/1355-ARM-dts-r8a77470-Initial-SoC-device-tree.patch
new file mode 100644
index 00000000000000..99852db1b802dc
--- /dev/null
+++ b/patches/1355-ARM-dts-r8a77470-Initial-SoC-device-tree.patch
@@ -0,0 +1,183 @@
+From 56ae4898315f0c4d976543666ca09c883b0137f4 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 3 Apr 2018 12:19:38 +0100
+Subject: [PATCH 1355/1795] ARM: dts: r8a77470: Initial SoC device tree
+
+The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
+CPG, and the required clock descriptions.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6929dfc5918049272e07653b1760b0b305f098e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 154 ++++++++++++++++++++++++++++++++
+ 1 file changed, 154 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a77470.dtsi
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+new file mode 100644
+index 000000000000..45785828771b
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -0,0 +1,154 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the r8a77470 SoC
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++/ {
++	compatible = "renesas,r8a77470";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a7";
++			reg = <0>;
++			clock-frequency = <1000000000>;
++			clocks = <&cpg CPG_CORE 0>;
++			power-domains = <&sysc 5>;
++			next-level-cache = <&L2_CA7>;
++		};
++
++
++		L2_CA7: cache-controller-0 {
++			compatible = "cache";
++			cache-unified;
++			cache-level = <2>;
++			power-domains = <&sysc 21>;
++		};
++	};
++
++	/* External root clock */
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board. */
++		clock-frequency = <0>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77470-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&usb_extal_clk>;
++			clock-names = "extal", "usb_extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77470-rst";
++			reg = <0 0xe6160000 0 0x100>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77470-sysc";
++			reg = <0 0xe6180000 0 0x200>;
++			#power-domain-cells = <1>;
++		};
++
++		icram0:	sram@e63a0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63a0000 0 0x12000>;
++		};
++
++		icram1:	sram@e63c0000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe63c0000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0xe63c0000 0x1000>;
++
++			smp-sram@0 {
++				compatible = "renesas,smp-sram";
++				reg = <0 0x100>;
++			};
++		};
++
++		icram2:	sram@e6300000 {
++			compatible = "mmio-sram";
++			reg = <0 0xe6300000 0 0x20000>;
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 0x40>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&cpg CPG_MOD 720>,
++				 <&cpg CPG_CORE 6>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 720>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1001000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
++			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
++		};
++
++		prr: chipid@ff000044 {
++			compatible = "renesas,prr";
++			reg = <0 0xff000044 0 4>;
++		};
++	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	/* External USB clock - can be overridden by the board */
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <48000000>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1356-ARM-dts-iwg23s-sbc-Add-support-for-iWave-G23S-SBC-ba.patch b/patches/1356-ARM-dts-iwg23s-sbc-Add-support-for-iWave-G23S-SBC-ba.patch
new file mode 100644
index 00000000000000..23d3b9103eb515
--- /dev/null
+++ b/patches/1356-ARM-dts-iwg23s-sbc-Add-support-for-iWave-G23S-SBC-ba.patch
@@ -0,0 +1,78 @@
+From 564dc97d95d612777cf60d4c2f71b896a358860b Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 3 Apr 2018 12:19:39 +0100
+Subject: [PATCH 1356/1795] ARM: dts: iwg23s-sbc: Add support for iWave
+ G23S-SBC based on RZ/G1C
+
+Add support for iWave iW-RainboW-G23S single board computer based on
+ RZ/G1C.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f922fb5af1584c35bcd8bf661738b16dd4f65441)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/Makefile                |  1 +
+ arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 35 +++++++++++++++++++++++
+ 2 files changed, 36 insertions(+)
+ create mode 100644 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index e820cd2fe07f..1525c1d58417 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -730,6 +730,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
+ 	r8a7745-iwg22d-sodimm.dtb \
+ 	r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
+ 	r8a7745-sk-rzg1e.dtb \
++	r8a77470-iwg23s-sbc.dtb \
+ 	r8a7778-bockw.dtb \
+ 	r8a7779-marzen.dtb \
+ 	r8a7790-lager.dtb \
+diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+new file mode 100644
+index 000000000000..d21baad9f0ad
+--- /dev/null
++++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+@@ -0,0 +1,35 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the iWave-RZ/G1C single board computer
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++/dts-v1/;
++#include "r8a77470.dtsi"
++/ {
++	model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
++	compatible = "iwave,g23s", "renesas,r8a77470";
++
++	aliases {
++		serial1 = &scif1;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel";
++		stdout-path = "serial1:115200n8";
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0 0x40000000 0 0x20000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <20000000>;
++};
++
++&scif1 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1357-dt-bindings-arm-Document-iW-RainboW-G23S-single-boar.patch b/patches/1357-dt-bindings-arm-Document-iW-RainboW-G23S-single-boar.patch
new file mode 100644
index 00000000000000..c1426e0682c3a0
--- /dev/null
+++ b/patches/1357-dt-bindings-arm-Document-iW-RainboW-G23S-single-boar.patch
@@ -0,0 +1,36 @@
+From d7560a5827aebddebdc5bdd2d9e13748bed0b145 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 27 Mar 2018 15:37:20 +0100
+Subject: [PATCH 1357/1795] dt-bindings: arm: Document iW-RainboW-G23S single
+ board computer
+
+Document the iW-RainboW-G23S single board computer device tree bindings,
+listing it as a supported board.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7625f03be3177d63cc6e5763b0c2dfecc371ca95)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 86ac320323a7..4401369e471f 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -80,6 +80,8 @@ Boards:
+     compatible = "renesas,h3ulcb", "renesas,r8a7795"
+   - Henninger
+     compatible = "renesas,henninger", "renesas,r8a7791"
++  - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
++    compatible = "iwave,g23s", "renesas,r8a77470"
+   - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+     compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
+   - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+-- 
+2.19.0
+
diff --git a/patches/1358-dt-bindings-arm-Document-R-Car-E3-SoC-DT-bindings.patch b/patches/1358-dt-bindings-arm-Document-R-Car-E3-SoC-DT-bindings.patch
new file mode 100644
index 00000000000000..02fa5009e14bae
--- /dev/null
+++ b/patches/1358-dt-bindings-arm-Document-R-Car-E3-SoC-DT-bindings.patch
@@ -0,0 +1,34 @@
+From 8102f2309c83fdc3e5db3b6fb1aed0dddde44a86 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 11 Apr 2018 18:35:51 +0900
+Subject: [PATCH 1358/1795] dt-bindings: arm: Document R-Car E3 SoC DT bindings
+
+This patch adds device tree bindings documentation for Renesas R-Car
+E3 (r8a77990).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6fdc4f90b4950a7df1d314bdc53e25c1c4e70dc9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 4401369e471f..5d21d489f61a 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -47,6 +47,8 @@ SoCs:
+     compatible = "renesas,r8a77970"
+   - R-Car V3H (R8A77980)
+     compatible = "renesas,r8a77980"
++  - R-Car E3 (R8A77990)
++    compatible = "renesas,r8a77990"
+   - R-Car D3 (R8A77995)
+     compatible = "renesas,r8a77995"
+ 
+-- 
+2.19.0
+
diff --git a/patches/1359-dt-bindings-arm-Document-Renesas-Ebisu-board-DT-bind.patch b/patches/1359-dt-bindings-arm-Document-Renesas-Ebisu-board-DT-bind.patch
new file mode 100644
index 00000000000000..9052b166f1d596
--- /dev/null
+++ b/patches/1359-dt-bindings-arm-Document-Renesas-Ebisu-board-DT-bind.patch
@@ -0,0 +1,35 @@
+From 7ddd700f0716abcdc471d9dd881a6175de304c6b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 11 Apr 2018 18:35:52 +0900
+Subject: [PATCH 1359/1795] dt-bindings: arm: Document Renesas Ebisu board DT
+ bindings
+
+This patch adds device tree bindings documentation for Renesas
+Ebisu board (RTP0RC77990SEB0010S).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d2ba004b0341e63dc49f640ddd8e79c764ff16c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 5d21d489f61a..61b486fb5793 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -71,6 +71,8 @@ Boards:
+     compatible = "renesas,draak", "renesas,r8a77995"
+   - Eagle (RTP0RC77970SEB0010S)
+     compatible = "renesas,eagle", "renesas,r8a77970"
++  - Ebisu (RTP0RC77990SEB0010S)
++    compatible = "renesas,ebisu", "renesas,r8a77990"
+   - Genmai (RTK772100BC00000BR)
+     compatible = "renesas,genmai", "renesas,r7s72100"
+   - GR-Peach (X28A-M01-E/F)
+-- 
+2.19.0
+
diff --git a/patches/1360-ARM-shmobile-defconfig-Enable-r8a77470-SoC.patch b/patches/1360-ARM-shmobile-defconfig-Enable-r8a77470-SoC.patch
new file mode 100644
index 00000000000000..35898ba48ea6e3
--- /dev/null
+++ b/patches/1360-ARM-shmobile-defconfig-Enable-r8a77470-SoC.patch
@@ -0,0 +1,33 @@
+From 3743621a7cbf0b017d4f89c5a787393fdff0d0d4 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 27 Mar 2018 15:37:22 +0100
+Subject: [PATCH 1360/1795] ARM: shmobile: defconfig: Enable r8a77470 SoC
+
+Enable recently added r8a77470 (RZ/G1C) SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f794fa1e8f0f7e308edae8eaef2f9cd59aa62bc6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index a701601fbd76..dc650db70063 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -14,6 +14,7 @@ CONFIG_ARCH_R8A73A4=y
+ CONFIG_ARCH_R8A7740=y
+ CONFIG_ARCH_R8A7743=y
+ CONFIG_ARCH_R8A7745=y
++CONFIG_ARCH_R8A77470=y
+ CONFIG_ARCH_R8A7778=y
+ CONFIG_ARCH_R8A7779=y
+ CONFIG_ARCH_R8A7790=y
+-- 
+2.19.0
+
diff --git a/patches/1361-ARM-dts-wheat-Fix-ADV7513-address-usage.patch b/patches/1361-ARM-dts-wheat-Fix-ADV7513-address-usage.patch
new file mode 100644
index 00000000000000..d00249a7cff1eb
--- /dev/null
+++ b/patches/1361-ARM-dts-wheat-Fix-ADV7513-address-usage.patch
@@ -0,0 +1,64 @@
+From 2695e0ddc0e448c16843a31b98bd9972a103d94d Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Thu, 22 Mar 2018 21:30:40 +0000
+Subject: [PATCH 1361/1795] ARM: dts: wheat: Fix ADV7513 address usage
+
+The r8a7792 Wheat board has two ADV7513 devices sharing a single I2C
+bus, however in low power mode the ADV7513 will reset it's slave maps to
+use the hardware defined default addresses.
+
+The ADV7511 driver was adapted to allow the two devices to be registered
+correctly - but it did not take into account the fault whereby the
+devices reset the addresses.
+
+This results in an address conflict between the device using the default
+addresses, and the other device if it is in low-power-mode.
+
+Repair this issue by moving both devices away from the default address
+definitions.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Fixes: f6eea82a87db ("ARM: dts: wheat: add DU support")
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1d26a5217187189fdbee15bc03d3713d8e8ae7e9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792-wheat.dts | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
+index b9471b67b728..95aab56a56ab 100644
+--- a/arch/arm/boot/dts/r8a7792-wheat.dts
++++ b/arch/arm/boot/dts/r8a7792-wheat.dts
+@@ -240,9 +240,15 @@
+ 	status = "okay";
+ 	clock-frequency = <400000>;
+ 
++	/*
++	 * The adv75xx resets its addresses to defaults during low power mode.
++	 * Because we have two ADV7513 devices on the same bus, we must change
++	 * both of them away from the defaults so that they do not conflict.
++	 */
+ 	hdmi@3d {
+ 		compatible = "adi,adv7513";
+-		reg = <0x3d>;
++		reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
++		reg-names = "main", "cec", "edid", "packet";
+ 
+ 		adi,input-depth = <8>;
+ 		adi,input-colorspace = "rgb";
+@@ -272,7 +278,8 @@
+ 
+ 	hdmi@39 {
+ 		compatible = "adi,adv7513";
+-		reg = <0x39>;
++		reg = <0x39>, <0x29>, <0x49>, <0x59>;
++		reg-names = "main", "cec", "edid", "packet";
+ 
+ 		adi,input-depth = <8>;
+ 		adi,input-colorspace = "rgb";
+-- 
+2.19.0
+
diff --git a/patches/1362-ARM-dts-renesas-replace-toshiba-mmc-wrprotect-disabl.patch b/patches/1362-ARM-dts-renesas-replace-toshiba-mmc-wrprotect-disabl.patch
new file mode 100644
index 00000000000000..2533992ca38207
--- /dev/null
+++ b/patches/1362-ARM-dts-renesas-replace-toshiba-mmc-wrprotect-disabl.patch
@@ -0,0 +1,68 @@
+From 7e10cadd0a51b6c4770944340abeedbee96868de Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Tue, 17 Apr 2018 00:02:32 +0900
+Subject: [PATCH 1362/1795] ARM: dts: renesas: replace toshiba,
+ mmc-wrprotect-disable with disable-wp
+
+Follow up commit 788778b0d21a ("mmc: tmio: deprecate "toshiba,
+mmc-wrprotect-disable" DT property").
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9eb663e838aba244b97fed0000cb3917f6013e96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a73a4-ape6evm.dts | 4 ++--
+ arch/arm/boot/dts/sh73a0.dtsi         | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+index ec7c86e06538..125c39c0222f 100644
+--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
++++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+@@ -234,7 +234,7 @@
+ &sdhi0 {
+ 	vmmc-supply = <&vcc_sdhi0>;
+ 	bus-width = <4>;
+-	toshiba,mmc-wrprotect-disable;
++	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdhi0_pins>;
+ 	status = "okay";
+@@ -244,7 +244,7 @@
+ 	vmmc-supply = <&ape6evm_fixed_3v3>;
+ 	bus-width = <4>;
+ 	broken-cd;
+-	toshiba,mmc-wrprotect-disable;
++	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdhi1_pins>;
+ 	status = "okay";
+diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
+index b0c20544df20..c953648a5f41 100644
+--- a/arch/arm/boot/dts/sh73a0.dtsi
++++ b/arch/arm/boot/dts/sh73a0.dtsi
+@@ -337,7 +337,7 @@
+ 			      GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
+ 		power-domains = <&pd_a3sp>;
+-		toshiba,mmc-wrprotect-disable;
++		disable-wp;
+ 		cap-sd-highspeed;
+ 		status = "disabled";
+ 	};
+@@ -349,7 +349,7 @@
+ 			      GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
+ 		power-domains = <&pd_a3sp>;
+-		toshiba,mmc-wrprotect-disable;
++		disable-wp;
+ 		cap-sd-highspeed;
+ 		status = "disabled";
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1363-arm-shmobile-Add-the-RZ-N1D-R9A06G032-to-the-shmobil.patch b/patches/1363-arm-shmobile-Add-the-RZ-N1D-R9A06G032-to-the-shmobil.patch
new file mode 100644
index 00000000000000..371df5f8e1cf74
--- /dev/null
+++ b/patches/1363-arm-shmobile-Add-the-RZ-N1D-R9A06G032-to-the-shmobil.patch
@@ -0,0 +1,35 @@
+From b921d8b3d39d6ab3b9b0ede45341c6311f998ffc Mon Sep 17 00:00:00 2001
+From: Michel Pollet <michel.pollet@bp.renesas.com>
+Date: Tue, 17 Apr 2018 12:04:16 +0100
+Subject: [PATCH 1363/1795] arm: shmobile: Add the RZ/N1D (R9A06G032) to the
+ shmobile Kconfig
+
+Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
+
+Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d9dcd6c1c646496e5e306baabce330457cdf478c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/Kconfig | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
+index 96672da02f5f..fcc273f127bf 100644
+--- a/arch/arm/mach-shmobile/Kconfig
++++ b/arch/arm/mach-shmobile/Kconfig
+@@ -114,6 +114,10 @@ config ARCH_R8A7794
+ 	bool "R-Car E2 (R8A77940)"
+ 	select ARCH_RCAR_GEN2
+ 
++config ARCH_R9A06G032
++	bool "RZ/N1D (R9A06G032)"
++	select ARCH_RZN1
++
+ config ARCH_RZN1
+ 	bool "RZ/N1 (R9A06G0xx) Family"
+ 	select ARM_AMBA
+-- 
+2.19.0
+
diff --git a/patches/1364-ARM-shmobile-defconfig-Disable-CONFIG_FB_SH_MOBILE_M.patch b/patches/1364-ARM-shmobile-defconfig-Disable-CONFIG_FB_SH_MOBILE_M.patch
new file mode 100644
index 00000000000000..e9b2fdb3263050
--- /dev/null
+++ b/patches/1364-ARM-shmobile-defconfig-Disable-CONFIG_FB_SH_MOBILE_M.patch
@@ -0,0 +1,35 @@
+From 523c7b5e8ace291fb71d33f6d59693bb6d607804 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 20 Apr 2018 15:15:40 +0200
+Subject: [PATCH 1364/1795] ARM: shmobile: defconfig: Disable
+ CONFIG_FB_SH_MOBILE_MERAM
+
+The last Renesas ARM platform using this driver was removed in commit
+a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C board
+code").
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ddba297cc1cc01c70cd08dd4647d46ea33f942a1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index dc650db70063..dd95d395f565 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -157,7 +157,6 @@ CONFIG_DRM_DUMB_VGA_DAC=y
+ CONFIG_DRM_I2C_ADV7511=y
+ CONFIG_DRM_I2C_ADV7511_AUDIO=y
+ CONFIG_FB_SH_MOBILE_LCDC=y
+-CONFIG_FB_SH_MOBILE_MERAM=y
+ # CONFIG_LCD_CLASS_DEVICE is not set
+ # CONFIG_BACKLIGHT_GENERIC is not set
+ CONFIG_BACKLIGHT_PWM=y
+-- 
+2.19.0
+
diff --git a/patches/1365-ARM-dts-renesas-r8a7791-Add-FDP1-instances.patch b/patches/1365-ARM-dts-renesas-r8a7791-Add-FDP1-instances.patch
new file mode 100644
index 00000000000000..dfe1ad66ffa434
--- /dev/null
+++ b/patches/1365-ARM-dts-renesas-r8a7791-Add-FDP1-instances.patch
@@ -0,0 +1,49 @@
+From dddbac217dd063fcf068ba83c2c337e0a33e2204 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sun, 22 Apr 2018 13:35:26 +0300
+Subject: [PATCH 1365/1795] ARM: dts: renesas: r8a7791: Add FDP1 instances
+
+The r8a7791 has two FDP1 instances.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e7f36fb8ffafbda9c168e1aafab5b5ebe54ebaa8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 506b20885413..0787068d109c 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -1621,6 +1621,24 @@
+ 			resets = <&cpg 127>;
+ 		};
+ 
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 119>;
++		};
++
++		fdp1@fe944000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe944000 0 0x2400>;
++			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 118>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 118>;
++		};
++
+ 		jpu: jpeg-codec@fe980000 {
+ 			compatible = "renesas,jpu-r8a7791",
+ 				     "renesas,rcar-gen2-jpu";
+-- 
+2.19.0
+
diff --git a/patches/1366-ARM-dts-renesas-r8a7793-Add-FDP1-instances.patch b/patches/1366-ARM-dts-renesas-r8a7793-Add-FDP1-instances.patch
new file mode 100644
index 00000000000000..76fc64a093acb0
--- /dev/null
+++ b/patches/1366-ARM-dts-renesas-r8a7793-Add-FDP1-instances.patch
@@ -0,0 +1,49 @@
+From 6f6fb03698bdbbfe2ab980471716341bce77354c Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sun, 22 Apr 2018 13:35:27 +0300
+Subject: [PATCH 1366/1795] ARM: dts: renesas: r8a7793: Add FDP1 instances
+
+The r8a7793 has two FDP1 instances.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d7ce14dfbaff685a65b56bdb6622b430ae9ad57a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 4f526030dc7c..751bb424d11b 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -1290,6 +1290,24 @@
+ 			resets = <&cpg 408>;
+ 		};
+ 
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 119>;
++		};
++
++		fdp1@fe944000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe944000 0 0x2400>;
++			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 118>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 118>;
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7793";
+ 			reg = <0 0xfeb00000 0 0x40000>;
+-- 
+2.19.0
+
diff --git a/patches/1367-ARM-dts-renesas-r8a7794-Add-FDP1-instances.patch b/patches/1367-ARM-dts-renesas-r8a7794-Add-FDP1-instances.patch
new file mode 100644
index 00000000000000..07fb0861ef941d
--- /dev/null
+++ b/patches/1367-ARM-dts-renesas-r8a7794-Add-FDP1-instances.patch
@@ -0,0 +1,40 @@
+From 4f72e112a3241713181982d53a16fc206b8c7cb7 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sun, 22 Apr 2018 13:35:28 +0300
+Subject: [PATCH 1367/1795] ARM: dts: renesas: r8a7794: Add FDP1 instances
+
+The r8a7794 has one FDP1 instance.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 898cf5a67c169a8efb41cc6483935f1bc61e8157)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index d588efa6aeaa..56f5fa6a2c0f 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -1323,6 +1323,15 @@
+ 			resets = <&cpg 128>;
+ 		};
+ 
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 119>;
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a7794";
+ 			reg = <0 0xfeb00000 0 0x40000>;
+-- 
+2.19.0
+
diff --git a/patches/1368-ARM-dts-r8a77470-Add-SYS-DMAC-support.patch b/patches/1368-ARM-dts-r8a77470-Add-SYS-DMAC-support.patch
new file mode 100644
index 00000000000000..a877f847196b1f
--- /dev/null
+++ b/patches/1368-ARM-dts-r8a77470-Add-SYS-DMAC-support.patch
@@ -0,0 +1,98 @@
+From 7e74004f97eae8f7f620cabe6fdc7adf25a9622d Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 20 Apr 2018 16:27:06 +0100
+Subject: [PATCH 1368/1795] ARM: dts: r8a77470: Add SYS-DMAC support
+
+Describe SYS-DMAC0/1 in the R8A77470 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2e5775e3fd0667f7140a00748465af1c3d0aa5bb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 66 +++++++++++++++++++++++++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+index 45785828771b..c39acebc6a72 100644
+--- a/arch/arm/boot/dts/r8a77470.dtsi
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -104,6 +104,72 @@
+ 			reg = <0 0xe6300000 0 0x20000>;
+ 		};
+ 
++		dmac0: dma-controller@e6700000 {
++			compatible = "renesas,dmac-r8a77470",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6700000 0 0x20000>;
++			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 219>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 219>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
++
++		dmac1: dma-controller@e6720000 {
++			compatible = "renesas,dmac-r8a77470",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe6720000 0 0x20000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <15>;
++		};
++
+ 		scif1: serial@e6e68000 {
+ 			compatible = "renesas,scif-r8a77470",
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+-- 
+2.19.0
+
diff --git a/patches/1369-ARM-dts-r8a77470-Add-IRQC-support.patch b/patches/1369-ARM-dts-r8a77470-Add-IRQC-support.patch
new file mode 100644
index 00000000000000..91e4d3e72cba2d
--- /dev/null
+++ b/patches/1369-ARM-dts-r8a77470-Add-IRQC-support.patch
@@ -0,0 +1,52 @@
+From 6bc6014399d953fa64e0720c7f48f03c3b41b1ab Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Fri, 20 Apr 2018 16:27:07 +0100
+Subject: [PATCH 1369/1795] ARM: dts: r8a77470: Add IRQC support
+
+Describe the IRQC interrupt controller in the R8A77470 device tree.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 141fb10294e3ba5ee2d34d464ddc8a9952bd3372)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+index c39acebc6a72..2f89f33f5b88 100644
+--- a/arch/arm/boot/dts/r8a77470.dtsi
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -81,6 +81,26 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		irqc: interrupt-controller@e61c0000 {
++			compatible = "renesas,irqc-r8a77470", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 407>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 407>;
++		};
++
+ 		icram0:	sram@e63a0000 {
+ 			compatible = "mmio-sram";
+ 			reg = <0 0xe63a0000 0 0x12000>;
+-- 
+2.19.0
+
diff --git a/patches/1370-ARM-dts-r7s72100-Add-Capture-Engine-Unit-CEU.patch b/patches/1370-ARM-dts-r7s72100-Add-Capture-Engine-Unit-CEU.patch
new file mode 100644
index 00000000000000..d48f2946566ea2
--- /dev/null
+++ b/patches/1370-ARM-dts-r7s72100-Add-Capture-Engine-Unit-CEU.patch
@@ -0,0 +1,57 @@
+From 3dad36e4b7bfc5cef436189973dda8a299eb4737 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 22 Feb 2018 11:37:20 +0100
+Subject: [PATCH 1370/1795] ARM: dts: r7s72100: Add Capture Engine Unit (CEU)
+
+Add Capture Engine Unit (CEU) node to device tree.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
+[simon: rebased]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit f558d42a9d1c4724a8b3880fe230a66fa16e21c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index ecf9516bcda8..4a1aade0e751 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -375,6 +375,15 @@
+ 			status = "disabled";
+ 		};
+ 
++		ceu: camera@e8210000 {
++			reg = <0xe8210000 0x3000>;
++			compatible = "renesas,r7s72100-ceu";
++			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&mstp6_clks R7S72100_CLK_CEU>;
++			power-domains = <&cpg_clocks>;
++			status = "disabled";
++		};
++
+ 		wdt: watchdog@fcfe0000 {
+ 			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+ 			reg = <0xfcfe0000 0x6>;
+@@ -429,9 +438,9 @@
+ 			#clock-cells = <1>;
+ 			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ 			reg = <0xfcfe042c 4>;
+-			clocks = <&p0_clk>;
+-			clock-indices = <R7S72100_CLK_RTC>;
+-			clock-output-names = "rtc";
++			clocks = <&b_clk>, <&p0_clk>;
++			clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
++			clock-output-names = "ceu", "rtc";
+ 		};
+ 
+ 		mstp7_clks: mstp7_clks@fcfe0430 {
+-- 
+2.19.0
+
diff --git a/patches/1371-ARM-dts-r8a7743-Adjust-SMP-routine-size.patch b/patches/1371-ARM-dts-r8a7743-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..b47cd4d379b613
--- /dev/null
+++ b/patches/1371-ARM-dts-r8a7743-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From b97c10070114e5011a4b0c420246a2030b7674c7 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:11 +0000
+Subject: [PATCH 1371/1795] ARM: dts: r8a7743: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0b7d5ccacac9cd54785a2cf1695a0601907f3e78)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 1d9073ba0ce0..0381b86b7591 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -407,7 +407,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1372-ARM-dts-r8a7745-Adjust-SMP-routine-size.patch b/patches/1372-ARM-dts-r8a7745-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..e43849af674b43
--- /dev/null
+++ b/patches/1372-ARM-dts-r8a7745-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From ebc530d97ff720ea8a338009cbe9798bdc251682 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:12 +0000
+Subject: [PATCH 1372/1795] ARM: dts: r8a7745: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7270dedc8438c7247474a33a8334f3920816e2c2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index dd49a8b48f3e..0c3f4c5b345b 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -360,7 +360,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1373-ARM-dts-r8a7790-Adjust-SMP-routine-size.patch b/patches/1373-ARM-dts-r8a7790-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..f09928c85d470b
--- /dev/null
+++ b/patches/1373-ARM-dts-r8a7790-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From 0ba418931a0a503ad779d6b5a8e8c1d9e22aba81 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:13 +0000
+Subject: [PATCH 1373/1795] ARM: dts: r8a7790: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5c6c17a51f809bf831086d014f8655fa5a9f421b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 05a0fc23ac88..faab908274d7 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -443,7 +443,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1374-ARM-dts-r8a7791-Adjust-SMP-routine-size.patch b/patches/1374-ARM-dts-r8a7791-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..53551c58f235a9
--- /dev/null
+++ b/patches/1374-ARM-dts-r8a7791-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From dc068ceaed86d6116c4418427202f75847c6a84f Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:14 +0000
+Subject: [PATCH 1374/1795] ARM: dts: r8a7791: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a332210049e3d0e502253afdc52640bc2a87ac91)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 0787068d109c..65a8664ed0b1 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -407,7 +407,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1375-ARM-dts-r8a7792-Adjust-SMP-routine-size.patch b/patches/1375-ARM-dts-r8a7792-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..7f65ad6b8d5fbb
--- /dev/null
+++ b/patches/1375-ARM-dts-r8a7792-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From 6a0e066676b02f8ffc9af0e99c6edae80efb9bda Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:15 +0000
+Subject: [PATCH 1375/1795] ARM: dts: r8a7792: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 75f666509fe6545754755a166cc00f84e8018866)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index 268987ff0201..bea0f12f03d3 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -341,7 +341,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1376-ARM-dts-r8a7793-Adjust-SMP-routine-size.patch b/patches/1376-ARM-dts-r8a7793-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..36b2f803b429aa
--- /dev/null
+++ b/patches/1376-ARM-dts-r8a7793-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From 4d1eba506590aed146f7779bd89ce074005d11c8 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:16 +0000
+Subject: [PATCH 1376/1795] ARM: dts: r8a7793: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f515e5996a85fd4e042f3eec38d82a4250ac1a6c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 751bb424d11b..cf33dd9c8c05 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -392,7 +392,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1377-ARM-dts-r8a7794-Adjust-SMP-routine-size.patch b/patches/1377-ARM-dts-r8a7794-Adjust-SMP-routine-size.patch
new file mode 100644
index 00000000000000..642346ffd147e0
--- /dev/null
+++ b/patches/1377-ARM-dts-r8a7794-Adjust-SMP-routine-size.patch
@@ -0,0 +1,36 @@
+From b965db80b7c086c44241058fbf40b53e7bb059cf Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:17 +0000
+Subject: [PATCH 1377/1795] ARM: dts: r8a7794: Adjust SMP routine size
+
+This patch adjusts the definition of the SMP routine size according
+to the latest changes made by commit:
+"ARM: shmobile: Add watchdog support"
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8bcbcfd9e3ea981c188cb21cac5add7784580ee4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 56f5fa6a2c0f..34c111907eb7 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -348,7 +348,7 @@
+ 
+ 			smp-sram@0 {
+ 				compatible = "renesas,smp-sram";
+-				reg = <0 0x10>;
++				reg = <0 0x100>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1378-ARM-dts-r8a7743-Add-watchdog-support-to-SoC-dtsi.patch b/patches/1378-ARM-dts-r8a7743-Add-watchdog-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..37082902817f05
--- /dev/null
+++ b/patches/1378-ARM-dts-r8a7743-Add-watchdog-support-to-SoC-dtsi.patch
@@ -0,0 +1,43 @@
+From 0fb378027d08f4628844a58184ade97b62a9ef90 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:29 +0000
+Subject: [PATCH 1378/1795] ARM: dts: r8a7743: Add watchdog support to SoC dtsi
+
+This patch adds watchdog support to the r8a7743 SoC dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b5beb5d4c81c358f50a8310108e7d8614eec8bfd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 0381b86b7591..69d8f7e0f053 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -297,6 +297,16 @@
+ 			reg = <0 0xe6160000 0 0x100>;
+ 		};
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7743-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		sysc: system-controller@e6180000 {
+ 			compatible = "renesas,r8a7743-sysc";
+ 			reg = <0 0xe6180000 0 0x200>;
+-- 
+2.19.0
+
diff --git a/patches/1379-ARM-dts-r8a7745-Add-watchdog-support-to-SoC-dtsi.patch b/patches/1379-ARM-dts-r8a7745-Add-watchdog-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..e61f6c1f67c084
--- /dev/null
+++ b/patches/1379-ARM-dts-r8a7745-Add-watchdog-support-to-SoC-dtsi.patch
@@ -0,0 +1,43 @@
+From ab505bf1e5322c59b585df7cbe3f0f46f275ba5a Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:30 +0000
+Subject: [PATCH 1379/1795] ARM: dts: r8a7745: Add watchdog support to SoC dtsi
+
+This patch adds watchdog support to the r8a7745 SoC dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5f39290ff3e5f56c78adf16a8c7a0a2938c733f5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 0c3f4c5b345b..3de69cb66c44 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -262,6 +262,16 @@
+ 			reg = <0 0xe6160000 0 0x100>;
+ 		};
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7745-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		sysc: system-controller@e6180000 {
+ 			compatible = "renesas,r8a7745-sysc";
+ 			reg = <0 0xe6180000 0 0x200>;
+-- 
+2.19.0
+
diff --git a/patches/1380-ARM-dts-r8a7790-Add-watchdog-support-to-SoC-dtsi.patch b/patches/1380-ARM-dts-r8a7790-Add-watchdog-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..98a85dd4a64a2a
--- /dev/null
+++ b/patches/1380-ARM-dts-r8a7790-Add-watchdog-support-to-SoC-dtsi.patch
@@ -0,0 +1,43 @@
+From cb30303d72fd3967f39bf6b28907820df797fdc9 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:31 +0000
+Subject: [PATCH 1380/1795] ARM: dts: r8a7790: Add watchdog support to SoC dtsi
+
+This commit adds watchdog support to the r8a7790 dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c69f844380966ccd305ede64e568d81f0e0cfa85)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index faab908274d7..5a5d79788914 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -218,6 +218,16 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7790-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7790",
+ 				     "renesas,rcar-gen2-gpio";
+-- 
+2.19.0
+
diff --git a/patches/1381-ARM-dts-r8a7791-Add-watchdog-support-to-SoC-dtsi.patch b/patches/1381-ARM-dts-r8a7791-Add-watchdog-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..1e15a4641dd099
--- /dev/null
+++ b/patches/1381-ARM-dts-r8a7791-Add-watchdog-support-to-SoC-dtsi.patch
@@ -0,0 +1,43 @@
+From 1219c381906a13101e1e259cbe8b636a1a964aab Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:32 +0000
+Subject: [PATCH 1381/1795] ARM: dts: r8a7791: Add watchdog support to SoC dtsi
+
+This commit adds watchdog support to the r8a7791 dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6912394d66471296d4cd16e41e70f4758827a3e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 65a8664ed0b1..58f694eb411b 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -142,6 +142,16 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7791-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7791",
+ 				     "renesas,rcar-gen2-gpio";
+-- 
+2.19.0
+
diff --git a/patches/1382-ARM-dts-r8a7794-Add-watchdog-support-to-SoC-dtsi.patch b/patches/1382-ARM-dts-r8a7794-Add-watchdog-support-to-SoC-dtsi.patch
new file mode 100644
index 00000000000000..522d2680548fbd
--- /dev/null
+++ b/patches/1382-ARM-dts-r8a7794-Add-watchdog-support-to-SoC-dtsi.patch
@@ -0,0 +1,43 @@
+From 76ae7df5b7e951638e4d2f2499d14d7adc97d4d5 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:33 +0000
+Subject: [PATCH 1382/1795] ARM: dts: r8a7794: Add watchdog support to SoC dtsi
+
+This commit adds watchdog support to the r8a7794 dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aaef9f5051935c3b174df3fd7e73171b84c81485)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 34c111907eb7..76aadcdf9d37 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -119,6 +119,16 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7794-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7794",
+ 				     "renesas,rcar-gen2-gpio";
+-- 
+2.19.0
+
diff --git a/patches/1383-ARM-dts-iwg20m-Add-watchdog-support-to-SoM-dtsi.patch b/patches/1383-ARM-dts-iwg20m-Add-watchdog-support-to-SoM-dtsi.patch
new file mode 100644
index 00000000000000..1ae508ac2e9a95
--- /dev/null
+++ b/patches/1383-ARM-dts-iwg20m-Add-watchdog-support-to-SoM-dtsi.patch
@@ -0,0 +1,38 @@
+From 160a641305ec1bb95d14e2e964673cf43c533986 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:34 +0000
+Subject: [PATCH 1383/1795] ARM: dts: iwg20m: Add watchdog support to SoM dtsi
+
+This patch enables the watchdog from within the iwg20m SoM dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fc9d3be893f8f175879657f844040d0722eb17fe)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+index 1d3e9503c5bd..d364685d9184 100644
+--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
++++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+@@ -91,6 +91,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &sdhi0 {
+ 	pinctrl-0 = <&sdhi0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1384-ARM-dts-iwg22m-Add-watchdog-support-to-SoM-dtsi.patch b/patches/1384-ARM-dts-iwg22m-Add-watchdog-support-to-SoM-dtsi.patch
new file mode 100644
index 00000000000000..eb52965b94463b
--- /dev/null
+++ b/patches/1384-ARM-dts-iwg22m-Add-watchdog-support-to-SoM-dtsi.patch
@@ -0,0 +1,38 @@
+From 45222e808bd3091d47036a679303e7040cf17dc3 Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:35 +0000
+Subject: [PATCH 1384/1795] ARM: dts: iwg22m: Add watchdog support to SoM dtsi
+
+This patch enables the watchdog from within the iwg20m SoM dtsi.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a8e2c377fe2483f7fcd5746ab4e0c43c3262c1de)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+index 8d0a392b6811..29b6e10fdf96 100644
+--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
++++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+@@ -91,6 +91,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &sdhi1 {
+ 	pinctrl-0 = <&sdhi1_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1385-ARM-dts-r8a7792-Add-RWDT-node.patch b/patches/1385-ARM-dts-r8a7792-Add-RWDT-node.patch
new file mode 100644
index 00000000000000..942665fe8e8c63
--- /dev/null
+++ b/patches/1385-ARM-dts-r8a7792-Add-RWDT-node.patch
@@ -0,0 +1,42 @@
+From 9ff2686e6321ea44a509584ae99d18dd2b22c19d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:08 +0100
+Subject: [PATCH 1385/1795] ARM: dts: r8a7792: Add RWDT node
+
+Add a device node for the Watchdog Timer (WDT) controller on the Renesas
+R-Car V2H (r8a7792) SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 49dba98c1981da471739e44a74244f658777c6fd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index bea0f12f03d3..d2cf8dd2d9b0 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -101,6 +101,16 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7792-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7792",
+ 				     "renesas,rcar-gen2-gpio";
+-- 
+2.19.0
+
diff --git a/patches/1386-ARM-dts-r8a7793-Add-RWDT-node.patch b/patches/1386-ARM-dts-r8a7793-Add-RWDT-node.patch
new file mode 100644
index 00000000000000..c19e360a550eb8
--- /dev/null
+++ b/patches/1386-ARM-dts-r8a7793-Add-RWDT-node.patch
@@ -0,0 +1,42 @@
+From b7f431dc2f93de1891de551cdca7d832fab61a4b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:09 +0100
+Subject: [PATCH 1386/1795] ARM: dts: r8a7793: Add RWDT node
+
+Add a device node for the Watchdog Timer (WDT) controller on the Renesas
+R-Car M2-N (r8a7793) SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5ba173e677100a79bc6bcfb063c3ea736f7319a1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index cf33dd9c8c05..2fa052200495 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -126,6 +126,16 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		rwdt: watchdog@e6020000 {
++			compatible = "renesas,r8a7793-wdt",
++				     "renesas,rcar-gen2-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
++			resets = <&cpg 402>;
++			status = "disabled";
++		};
++
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a7793",
+ 				     "renesas,rcar-gen2-gpio";
+-- 
+2.19.0
+
diff --git a/patches/1387-ARM-dts-lager-Enable-watchdog-support.patch b/patches/1387-ARM-dts-lager-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..d94e5482a5b8a4
--- /dev/null
+++ b/patches/1387-ARM-dts-lager-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 6bbf8f81573438e39527cd995d055324abfbdfd3 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:10 +0100
+Subject: [PATCH 1387/1795] ARM: dts: lager: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 53e480fcb1cb00a74d6af2070bfcd1e995b19d47)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index f07f9018c3e7..7576f9f9bdba 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -929,6 +929,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &ssi1 {
+ 	shared-pin;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1388-ARM-dts-koelsch-Enable-watchdog-support.patch b/patches/1388-ARM-dts-koelsch-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..92f9d0c58a5d42
--- /dev/null
+++ b/patches/1388-ARM-dts-koelsch-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From e637dee4cb967d06c8f243a962bb07412cbb1f05 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:11 +0100
+Subject: [PATCH 1388/1795] ARM: dts: koelsch: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9245dccc4a198997d2b0d2b51eef14763ccf2b30)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index 9d7213a0b8b8..e394e0487416 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -643,6 +643,11 @@
+ 	status = "okay";
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &sata0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/1389-ARM-dts-porter-Enable-watchdog-support.patch b/patches/1389-ARM-dts-porter-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..eb642ece8dafd2
--- /dev/null
+++ b/patches/1389-ARM-dts-porter-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 72413e31cd79fdf8b93d9fd333c0e2cbbe187c96 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:12 +0100
+Subject: [PATCH 1389/1795] ARM: dts: porter: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 389f6f8b3eb00972f05f0ca03295c2d00ddef53d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-porter.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
+index ae9ed9ff53ef..c336aa17b79e 100644
+--- a/arch/arm/boot/dts/r8a7791-porter.dts
++++ b/arch/arm/boot/dts/r8a7791-porter.dts
+@@ -481,6 +481,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &ssi1 {
+ 	shared-pin;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1390-ARM-dts-blanche-Enable-watchdog-support.patch b/patches/1390-ARM-dts-blanche-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..8c385f9cf66f4d
--- /dev/null
+++ b/patches/1390-ARM-dts-blanche-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 303ace07d3fb415a1c8cb01463bd472ab588fd01 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:13 +0100
+Subject: [PATCH 1390/1795] ARM: dts: blanche: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b27f039979a057c66e67c9310a625152b473cbe8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792-blanche.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
+index 9b67dca6c9ef..04fb70931b3b 100644
+--- a/arch/arm/boot/dts/r8a7792-blanche.dts
++++ b/arch/arm/boot/dts/r8a7792-blanche.dts
+@@ -239,6 +239,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &scif0 {
+ 	pinctrl-0 = <&scif0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1391-ARM-dts-wheat-Enable-watchdog-support.patch b/patches/1391-ARM-dts-wheat-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..f10f6636f53961
--- /dev/null
+++ b/patches/1391-ARM-dts-wheat-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 0da674409e7d42828714dd0e071d3b842e2e6163 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:14 +0100
+Subject: [PATCH 1391/1795] ARM: dts: wheat: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9a3b0adee13a9a65bee0c305286793ebb96a1cd8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792-wheat.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
+index 95aab56a56ab..db01de7a3811 100644
+--- a/arch/arm/boot/dts/r8a7792-wheat.dts
++++ b/arch/arm/boot/dts/r8a7792-wheat.dts
+@@ -168,6 +168,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &scif0 {
+ 	pinctrl-0 = <&scif0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1392-ARM-dts-gose-Enable-watchdog-support.patch b/patches/1392-ARM-dts-gose-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..3f0d1079b8e882
--- /dev/null
+++ b/patches/1392-ARM-dts-gose-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 77d416dd480e4ec75285066c37626ab785001fc0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:15 +0100
+Subject: [PATCH 1392/1795] ARM: dts: gose: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 80aed52aff94875c600d976d6d94126f31c7c052)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 96e117d8b2cc..4c10285d769a 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -599,6 +599,11 @@
+ 	status = "okay";
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &scif0 {
+ 	pinctrl-0 = <&scif0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1393-ARM-dts-alt-Enable-watchdog-support.patch b/patches/1393-ARM-dts-alt-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..5698fa2a25f300
--- /dev/null
+++ b/patches/1393-ARM-dts-alt-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From fdac5b2552d472281289f9f363677ff7933ffebc Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:16 +0100
+Subject: [PATCH 1393/1795] ARM: dts: alt: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2d8cc50d9633fd4145272e10080ed6ac086129d4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index 26a883484ea8..1ecc5b9135f3 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -330,6 +330,11 @@
+ 	status = "okay";
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &sdhi0 {
+ 	pinctrl-0 = <&sdhi0_pins>;
+ 	pinctrl-1 = <&sdhi0_pins_uhs>;
+-- 
+2.19.0
+
diff --git a/patches/1394-ARM-dts-silk-Enable-watchdog-support.patch b/patches/1394-ARM-dts-silk-Enable-watchdog-support.patch
new file mode 100644
index 00000000000000..5b28a2e8d40c03
--- /dev/null
+++ b/patches/1394-ARM-dts-silk-Enable-watchdog-support.patch
@@ -0,0 +1,37 @@
+From 353ad25d3b73553883b7036481f56b56bb40b4ec Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 8 Feb 2018 11:34:17 +0100
+Subject: [PATCH 1394/1795] ARM: dts: silk: Enable watchdog support
+
+Enable the watchdog, so the board can be restarted by a watchdog
+timeout.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c9603026f9dd47f5f4b079a3ca587e135ccd4e72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-silk.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index 351cb3b3d966..e2642d2c2eed 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -540,6 +540,11 @@
+ 	};
+ };
+ 
++&rwdt {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
+ &ssi1 {
+ 	shared-pin;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1395-ARM-dts-r8a77470-Add-SCIF-support.patch b/patches/1395-ARM-dts-r8a77470-Add-SCIF-support.patch
new file mode 100644
index 00000000000000..7b941bf9ceb0e2
--- /dev/null
+++ b/patches/1395-ARM-dts-r8a77470-Add-SCIF-support.patch
@@ -0,0 +1,114 @@
+From 5b265c5724c08d720e8d8b65e99ad9f842b63a67 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 09:56:03 +0100
+Subject: [PATCH 1395/1795] ARM: dts: r8a77470: Add SCIF support
+
+Describe SCIF ports in the R8A77470 device tree.
+Also it fixes the CPG clock index ZS from 6 to 5.
+
+Fixes: 6929dfc5918049 ("ARM: dts: r8a77470: Initial SoC device tree")
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8cdb8f1ab7efbd88868d3067ec1f211ff289bc01)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 69 ++++++++++++++++++++++++++++++++-
+ 1 file changed, 67 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+index 2f89f33f5b88..39549f28be85 100644
+--- a/arch/arm/boot/dts/r8a77470.dtsi
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -190,19 +190,84 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 0x40>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 721>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 721>;
++			status = "disabled";
++		};
++
+ 		scif1: serial@e6e68000 {
+ 			compatible = "renesas,scif-r8a77470",
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+ 			reg = <0 0xe6e68000 0 0x40>;
+ 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-				clocks = <&cpg CPG_MOD 720>,
+-				 <&cpg CPG_CORE 6>, <&scif_clk>;
++			clocks = <&cpg CPG_MOD 720>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 720>;
+ 			status = "disabled";
+ 		};
+ 
++		scif2: serial@e6e58000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6e58000 0 0x40>;
++			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 719>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 719>;
++			status = "disabled";
++		};
++
++		scif3: serial@e6ea8000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ea8000 0 0x40>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 718>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 718>;
++			status = "disabled";
++		};
++
++		scif4: serial@e6ee0000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee0000 0 0x40>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 715>;
++			status = "disabled";
++		};
++
++		scif5: serial@e6ee8000 {
++			compatible = "renesas,scif-r8a77470",
++				     "renesas,rcar-gen2-scif", "renesas,scif";
++			reg = <0 0xe6ee8000 0 0x40>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>,
++				 <&cpg CPG_CORE 5>, <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 714>;
++			status = "disabled";
++		};
++
+ 		gic: interrupt-controller@f1001000 {
+ 			compatible = "arm,gic-400";
+ 			#interrupt-cells = <3>;
+-- 
+2.19.0
+
diff --git a/patches/1396-ARM-dts-r8a77470-Add-SCIF-DMA-support.patch b/patches/1396-ARM-dts-r8a77470-Add-SCIF-DMA-support.patch
new file mode 100644
index 00000000000000..64e6e942254c2a
--- /dev/null
+++ b/patches/1396-ARM-dts-r8a77470-Add-SCIF-DMA-support.patch
@@ -0,0 +1,85 @@
+From 67d0d86165583e7407331fe0483a0959481648f1 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 09:56:04 +0100
+Subject: [PATCH 1396/1795] ARM: dts: r8a77470: Add SCIF DMA support
+
+Add SCIF DMA support for R8A77470 SoC.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e4696122205634f40e26f9c33359a71823d1e68c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+index 39549f28be85..baec3cae49d5 100644
+--- a/arch/arm/boot/dts/r8a77470.dtsi
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -198,6 +198,9 @@
+ 			clocks = <&cpg CPG_MOD 721>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
++			       <&dmac1 0x29>, <&dmac1 0x2a>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 721>;
+ 			status = "disabled";
+@@ -211,6 +214,9 @@
+ 			clocks = <&cpg CPG_MOD 720>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
++			       <&dmac1 0x2d>, <&dmac1 0x2e>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 720>;
+ 			status = "disabled";
+@@ -224,6 +230,9 @@
+ 			clocks = <&cpg CPG_MOD 719>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
++			       <&dmac1 0x2b>, <&dmac1 0x2c>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 719>;
+ 			status = "disabled";
+@@ -237,6 +246,9 @@
+ 			clocks = <&cpg CPG_MOD 718>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
++			       <&dmac1 0x2f>, <&dmac1 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 718>;
+ 			status = "disabled";
+@@ -250,6 +262,9 @@
+ 			clocks = <&cpg CPG_MOD 715>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
++			       <&dmac1 0xfb>, <&dmac1 0xfc>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 715>;
+ 			status = "disabled";
+@@ -263,6 +278,9 @@
+ 			clocks = <&cpg CPG_MOD 714>,
+ 				 <&cpg CPG_CORE 5>, <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
++			       <&dmac1 0xfd>, <&dmac1 0xfe>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 714>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/1397-ARM-dts-renesas-r8a7790-Add-FDP1-instances.patch b/patches/1397-ARM-dts-renesas-r8a7790-Add-FDP1-instances.patch
new file mode 100644
index 00000000000000..8c017a5a10f742
--- /dev/null
+++ b/patches/1397-ARM-dts-renesas-r8a7790-Add-FDP1-instances.patch
@@ -0,0 +1,58 @@
+From 34131db3700bc5583f136b11bad1caf488d2df31 Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Sun, 22 Apr 2018 13:35:25 +0300
+Subject: [PATCH 1397/1795] ARM: dts: renesas: r8a7790: Add FDP1 instances
+
+The r8a7790 has three FDP1 instances.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5d3b50d3c04dc277258dfca02afdddd8e69ecd29)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 5a5d79788914..c244aae7a026 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1616,6 +1616,33 @@
+ 			resets = <&cpg 128>;
+ 		};
+ 
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 119>;
++		};
++
++		fdp1@fe944000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe944000 0 0x2400>;
++			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 118>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 118>;
++		};
++
++		fdp1@fe948000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe948000 0 0x2400>;
++			interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 117>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 117>;
++		};
++
+ 		vsp@fe938000 {
+ 			compatible = "renesas,vsp1";
+ 			reg = <0 0xfe938000 0 0x8000>;
+-- 
+2.19.0
+
diff --git a/patches/1398-ARM-dts-r8a77470-Add-EtherAVB-support.patch b/patches/1398-ARM-dts-r8a77470-Add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..090e196ebed51b
--- /dev/null
+++ b/patches/1398-ARM-dts-r8a77470-Add-EtherAVB-support.patch
@@ -0,0 +1,44 @@
+From 5cc67247010f215cc068a28db78cf42befe7fcf5 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 16:37:32 +0100
+Subject: [PATCH 1398/1795] ARM: dts: r8a77470: Add EtherAVB support
+
+Define the generic R8A77470 part of the EtherAVB device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f70b0958c044a73188056a231d40a8af55c04dd2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470.dtsi | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
+index baec3cae49d5..c85032f9605b 100644
+--- a/arch/arm/boot/dts/r8a77470.dtsi
++++ b/arch/arm/boot/dts/r8a77470.dtsi
+@@ -190,6 +190,19 @@
+ 			dma-channels = <15>;
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77470",
++				     "renesas,etheravb-rcar-gen2";
++			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
++			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 812>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		scif0: serial@e6e60000 {
+ 			compatible = "renesas,scif-r8a77470",
+ 				     "renesas,rcar-gen2-scif", "renesas,scif";
+-- 
+2.19.0
+
diff --git a/patches/1399-ARM-dts-iwg23s-sbc-Add-EtherAVB-support.patch b/patches/1399-ARM-dts-iwg23s-sbc-Add-EtherAVB-support.patch
new file mode 100644
index 00000000000000..519b0be3170245
--- /dev/null
+++ b/patches/1399-ARM-dts-iwg23s-sbc-Add-EtherAVB-support.patch
@@ -0,0 +1,58 @@
+From befea5659cd4f98619a924a77173c42f33cca830 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 16:37:33 +0100
+Subject: [PATCH 1399/1795] ARM: dts: iwg23s-sbc: Add EtherAVB support
+
+Define the iW-RainboW-G23S board dependent part of the
+EtherAVB device node.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b6ef074bcadf9f89295bc7ee19424714b6ffc4c8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+index d21baad9f0ad..e3585daafdd6 100644
+--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
++++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+@@ -12,11 +12,12 @@
+ 	compatible = "iwave,g23s", "renesas,r8a77470";
+ 
+ 	aliases {
++		ethernet0 = &avb;
+ 		serial1 = &scif1;
+ 	};
+ 
+ 	chosen {
+-		bootargs = "ignore_loglevel";
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ 		stdout-path = "serial1:115200n8";
+ 	};
+ 
+@@ -26,6 +27,18 @@
+ 	};
+ };
+ 
++&avb {
++	phy-handle = <&phy3>;
++	phy-mode = "gmii";
++	renesas,no-ether-link;
++	status = "okay";
++
++	phy3: ethernet-phy@3 {
++		reg = <3>;
++		micrel,led-mode = <1>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <20000000>;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1400-ARM-dts-r8a7790-Fix-sort-order-of-VSP1-FDP1-nodes.patch b/patches/1400-ARM-dts-r8a7790-Fix-sort-order-of-VSP1-FDP1-nodes.patch
new file mode 100644
index 00000000000000..42ed5f707d2f3f
--- /dev/null
+++ b/patches/1400-ARM-dts-r8a7790-Fix-sort-order-of-VSP1-FDP1-nodes.patch
@@ -0,0 +1,61 @@
+From 7c0f88cee0862789ea2b4666b3573c163d54eb24 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Mon, 30 Apr 2018 11:53:25 +0100
+Subject: [PATCH 1400/1795] ARM: dts: r8a7790: Fix sort order of VSP1/FDP1
+ nodes
+
+Commit 5d3b50d3c04d ("ARM: dts: renesas: r8a7790: Add FDP1 instances")
+introduced the FDP1 for the r8a7790, but broke the sort ordering of the
+device tree nodes.
+
+Move the last VSP up to it's peers to correct the ordering.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b9ac80c815eabb81b66dc2dad2bb1a376915aeca)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index c244aae7a026..b66a18af28f1 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1616,6 +1616,15 @@
+ 			resets = <&cpg 128>;
+ 		};
+ 
++		vsp@fe938000 {
++			compatible = "renesas,vsp1";
++			reg = <0 0xfe938000 0 0x8000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 127>;
++			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
++			resets = <&cpg 127>;
++		};
++
+ 		fdp1@fe940000 {
+ 			compatible = "renesas,fdp1";
+ 			reg = <0 0xfe940000 0 0x2400>;
+@@ -1643,15 +1652,6 @@
+ 			resets = <&cpg 117>;
+ 		};
+ 
+-		vsp@fe938000 {
+-			compatible = "renesas,vsp1";
+-			reg = <0 0xfe938000 0 0x8000>;
+-			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 127>;
+-			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+-			resets = <&cpg 127>;
+-		};
+-
+ 		jpu: jpeg-codec@fe980000 {
+ 			compatible = "renesas,jpu-r8a7790",
+ 				     "renesas,rcar-gen2-jpu";
+-- 
+2.19.0
+
diff --git a/patches/1401-dt-bindings-arm-consistently-name-r8a77965-as-M3-N.patch b/patches/1401-dt-bindings-arm-consistently-name-r8a77965-as-M3-N.patch
new file mode 100644
index 00000000000000..960382272c97bc
--- /dev/null
+++ b/patches/1401-dt-bindings-arm-consistently-name-r8a77965-as-M3-N.patch
@@ -0,0 +1,34 @@
+From a2959da6c9e791c9acd27ad60a3a2b98d0a2d9d4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 24 Apr 2018 07:54:42 +0200
+Subject: [PATCH 1401/1795] dt-bindings: arm: consistently name r8a77965 as
+ M3-N
+
+There is an inconsistency between the use of M3N and M3-N.
+This patch resolves this by consistently using the latter.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 519df0e05d2796805ee6d6e396423e60f3743b97)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 61b486fb5793..02c5d261683f 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -116,7 +116,7 @@ Boards:
+     compatible = "renesas,salvator-x", "renesas,r8a7795"
+   - Salvator-X (RTP0RC7796SIPB0011S)
+     compatible = "renesas,salvator-x", "renesas,r8a7796"
+-  - Salvator-X (RTP0RC7796SIPB0011S (M3N))
++  - Salvator-X (RTP0RC7796SIPB0011S (M3-N))
+     compatible = "renesas,salvator-x", "renesas,r8a77965"
+   - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+     compatible = "renesas,salvator-xs", "renesas,r8a7795"
+-- 
+2.19.0
+
diff --git a/patches/1402-ARM-dts-lager-Drop-unnecessary-address-properties-fr.patch b/patches/1402-ARM-dts-lager-Drop-unnecessary-address-properties-fr.patch
new file mode 100644
index 00000000000000..de8727be68a277
--- /dev/null
+++ b/patches/1402-ARM-dts-lager-Drop-unnecessary-address-properties-fr.patch
@@ -0,0 +1,42 @@
+From f285a5b14ab4ba5120c92e209e55a57f46c7e6b8 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1402/1795] ARM: dts: lager: Drop unnecessary address
+ properties from port node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port node does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7790-lager.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit bedbe61959a803b54350df93a517d98329ec160e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790-lager.dts | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
+index 7576f9f9bdba..092610e3f953 100644
+--- a/arch/arm/boot/dts/r8a7790-lager.dts
++++ b/arch/arm/boot/dts/r8a7790-lager.dts
+@@ -902,9 +902,6 @@
+ 	status = "okay";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin1ep0: endpoint {
+ 			remote-endpoint = <&adv7180>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1403-ARM-dts-porter-Drop-unnecessary-address-properties-f.patch b/patches/1403-ARM-dts-porter-Drop-unnecessary-address-properties-f.patch
new file mode 100644
index 00000000000000..895d1b191def80
--- /dev/null
+++ b/patches/1403-ARM-dts-porter-Drop-unnecessary-address-properties-f.patch
@@ -0,0 +1,42 @@
+From 3c9cd25d20e6317264bf608d6d50895ec935cca3 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1403/1795] ARM: dts: porter: Drop unnecessary address
+ properties from vin port node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port node does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7791-porter.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 99a755f586ac113cfd2c4355f7a794b3b2361229)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-porter.dts | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
+index c336aa17b79e..a01101b49d99 100644
+--- a/arch/arm/boot/dts/r8a7791-porter.dts
++++ b/arch/arm/boot/dts/r8a7791-porter.dts
+@@ -386,9 +386,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin0ep: endpoint {
+ 			remote-endpoint = <&adv7180>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1404-ARM-dts-gose-Drop-unnecessary-address-properties-fro.patch b/patches/1404-ARM-dts-gose-Drop-unnecessary-address-properties-fro.patch
new file mode 100644
index 00000000000000..a1296afee6a435
--- /dev/null
+++ b/patches/1404-ARM-dts-gose-Drop-unnecessary-address-properties-fro.patch
@@ -0,0 +1,53 @@
+From f619cb6262b3fda6cc9ffb15a86591b661aef29c Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1404/1795] ARM: dts: gose: Drop unnecessary address properties
+ from port nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port nodes does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+ arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit c1eb7457ad6e9f3e2937f39ebfefb82cd729d625)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793-gose.dts | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
+index 4c10285d769a..aa209f6e5d71 100644
+--- a/arch/arm/boot/dts/r8a7793-gose.dts
++++ b/arch/arm/boot/dts/r8a7793-gose.dts
+@@ -763,9 +763,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin0ep2: endpoint {
+ 			remote-endpoint = <&adv7612_out>;
+ 			bus-width = <24>;
+@@ -785,9 +782,6 @@
+ 	status = "okay";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin1ep: endpoint {
+ 			remote-endpoint = <&adv7180_out>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1405-ARM-dts-koelsch-Drop-unnecessary-address-properties-.patch b/patches/1405-ARM-dts-koelsch-Drop-unnecessary-address-properties-.patch
new file mode 100644
index 00000000000000..c160e7784aa90e
--- /dev/null
+++ b/patches/1405-ARM-dts-koelsch-Drop-unnecessary-address-properties-.patch
@@ -0,0 +1,53 @@
+From d42fd4bc320aa93a891e4cfd28b15266ee7d00d9 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1405/1795] ARM: dts: koelsch: Drop unnecessary address
+ properties from port nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port nodes does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+ arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 778dff91e83da64c55dd7cbe3489793797a9775e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791-koelsch.dts | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
+index e394e0487416..8ab793d8b2fd 100644
+--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
+@@ -855,9 +855,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin0ep2: endpoint {
+ 			remote-endpoint = <&adv7612_out>;
+ 			bus-width = <24>;
+@@ -876,9 +873,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin1ep: endpoint {
+ 			remote-endpoint = <&adv7180>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1406-ARM-dts-alt-Drop-unnecessary-address-properties-from.patch b/patches/1406-ARM-dts-alt-Drop-unnecessary-address-properties-from.patch
new file mode 100644
index 00000000000000..8105ad9baf51ac
--- /dev/null
+++ b/patches/1406-ARM-dts-alt-Drop-unnecessary-address-properties-from.patch
@@ -0,0 +1,42 @@
+From 9a549db0a4957a2faae7a44fbc857fbc181cbd9d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1406/1795] ARM: dts: alt: Drop unnecessary address properties
+ from vin port node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port node does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7794-alt.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 03c3a66b4d72aa1ad9bf7a943270f1794c443e50)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index 1ecc5b9135f3..c210412f80ec 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -380,9 +380,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin0ep: endpoint {
+ 			remote-endpoint = <&adv7180>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1407-ARM-dts-silk-Drop-unnecessary-address-properties-fro.patch b/patches/1407-ARM-dts-silk-Drop-unnecessary-address-properties-fro.patch
new file mode 100644
index 00000000000000..c778166446f13c
--- /dev/null
+++ b/patches/1407-ARM-dts-silk-Drop-unnecessary-address-properties-fro.patch
@@ -0,0 +1,42 @@
+From 098fd441d3a0afbdb819f73f1027f99ea7bdf1da Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1407/1795] ARM: dts: silk: Drop unnecessary address properties
+ from vin port node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The vin port node does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/r8a7794-silk.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit d6e801d102b6d970a2d0b328b8bf589eee977e3e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-silk.dts | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
+index e2642d2c2eed..7808aaee6644 100644
+--- a/arch/arm/boot/dts/r8a7794-silk.dts
++++ b/arch/arm/boot/dts/r8a7794-silk.dts
+@@ -475,9 +475,6 @@
+ 	pinctrl-names = "default";
+ 
+ 	port {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		vin0ep: endpoint {
+ 			remote-endpoint = <&adv7180>;
+ 			bus-width = <8>;
+-- 
+2.19.0
+
diff --git a/patches/1408-ARM-dts-kzm9d-Drop-unnecessary-address-properties-fr.patch b/patches/1408-ARM-dts-kzm9d-Drop-unnecessary-address-properties-fr.patch
new file mode 100644
index 00000000000000..f7753763093e68
--- /dev/null
+++ b/patches/1408-ARM-dts-kzm9d-Drop-unnecessary-address-properties-fr.patch
@@ -0,0 +1,42 @@
+From 0e659733054bcae7630190f217a1669ad9add32e Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1408/1795] ARM: dts: kzm9d: Drop unnecessary address
+ properties from gpio_keys node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The gpio_keys node does not have an address and thus does not need
+address-cells or address size-properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ arch/arm/boot/dts/emev2-kzm9d.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 715d571162e0956a332ef52c5ba465f4f7089746)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/emev2-kzm9d.dts | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
+index c238407133bf..0af44b7eadb9 100644
+--- a/arch/arm/boot/dts/emev2-kzm9d.dts
++++ b/arch/arm/boot/dts/emev2-kzm9d.dts
+@@ -34,9 +34,6 @@
+ 
+ 	gpio_keys {
+ 		compatible = "gpio-keys";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		one {
+ 			debounce-interval = <50>;
+ 			wakeup-source;
+-- 
+2.19.0
+
diff --git a/patches/1409-ARM-shmobile-Convert-file-to-use-cntvoff.patch b/patches/1409-ARM-shmobile-Convert-file-to-use-cntvoff.patch
new file mode 100644
index 00000000000000..a3a433ad1d5dcc
--- /dev/null
+++ b/patches/1409-ARM-shmobile-Convert-file-to-use-cntvoff.patch
@@ -0,0 +1,97 @@
+From 699548e07afca717ba65cc95242b536c18c50ae6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
+Date: Fri, 4 May 2018 21:05:45 +0200
+Subject: [PATCH 1409/1795] ARM: shmobile: Convert file to use cntvoff
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Now that a common function is available for CNTVOFF's
+initialization, let's convert shmobile-apmu code to use
+this function.
+
+Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+(cherry picked from commit cad160ed0a94927e59bb5e31ab192d70f08decae)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/mach-shmobile/common.h          |  1 -
+ arch/arm/mach-shmobile/headsmp-apmu.S    | 22 +---------------------
+ arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
+ 3 files changed, 3 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
+index 43c1ac696274..2109f123bdfb 100644
+--- a/arch/arm/mach-shmobile/common.h
++++ b/arch/arm/mach-shmobile/common.h
+@@ -2,7 +2,6 @@
+ #ifndef __ARCH_MACH_COMMON_H
+ #define __ARCH_MACH_COMMON_H
+ 
+-extern void shmobile_init_cntvoff(void);
+ extern void shmobile_init_delay(void);
+ extern void shmobile_boot_vector(void);
+ extern unsigned long shmobile_boot_fn;
+diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
+index 5672b5849401..d49ab194766a 100644
+--- a/arch/arm/mach-shmobile/headsmp-apmu.S
++++ b/arch/arm/mach-shmobile/headsmp-apmu.S
+@@ -11,29 +11,9 @@
+ #include <linux/linkage.h>
+ #include <asm/assembler.h>
+ 
+-ENTRY(shmobile_init_cntvoff)
+-	/*
+-	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+-	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+-	 * then it should be handled by the secure code
+-	 */
+-	cps	#MON_MODE
+-	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+-	orr	r0, r1, #1
+-	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+-	instr_sync
+-	mov	r0, #0
+-	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+-	instr_sync
+-	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+-	instr_sync
+-	cps	#SVC_MODE
+-	ret	lr
+-ENDPROC(shmobile_init_cntvoff)
+-
+ #ifdef CONFIG_SMP
+ ENTRY(shmobile_boot_apmu)
+-	bl	shmobile_init_cntvoff
++	bl	secure_cntvoff_init
+ 	b	secondary_startup
+ ENDPROC(shmobile_boot_apmu)
+ #endif
+diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+index 80de6be912e1..88fdc1801d90 100644
+--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
++++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
+@@ -26,6 +26,7 @@
+ #include <linux/of_fdt.h>
+ #include <linux/of_platform.h>
+ #include <asm/mach/arch.h>
++#include <asm/secure_cntvoff.h>
+ #include "common.h"
+ #include "rcar-gen2.h"
+ 
+@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
+ 	void __iomem *base;
+ 	u32 freq;
+ 
+-	shmobile_init_cntvoff();
++	secure_cntvoff_init();
+ 
+ 	if (of_machine_is_compatible("renesas,r8a7745") ||
+ 	    of_machine_is_compatible("renesas,r8a77470") ||
+-- 
+2.19.0
+
diff --git a/patches/1410-ARM-shmobile-r8a7794-alt-add-EEPROM-to-DTS.patch b/patches/1410-ARM-shmobile-r8a7794-alt-add-EEPROM-to-DTS.patch
new file mode 100644
index 00000000000000..134546835a754a
--- /dev/null
+++ b/patches/1410-ARM-shmobile-r8a7794-alt-add-EEPROM-to-DTS.patch
@@ -0,0 +1,37 @@
+From c2c83ce05d2f840f3fcc834bed891860f91b48ba Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Mon, 7 May 2018 14:40:02 +0200
+Subject: [PATCH 1410/1795] ARM: shmobile: r8a7794: alt: add EEPROM to DTS
+
+Same EEPROM as on Koelsch, et al.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0b3d8740a835b7e5476be617b77f1c494236c306)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794-alt.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
+index c210412f80ec..e17027532941 100644
+--- a/arch/arm/boot/dts/r8a7794-alt.dts
++++ b/arch/arm/boot/dts/r8a7794-alt.dts
+@@ -181,6 +181,12 @@
+ 				};
+ 			};
+ 		};
++
++		eeprom@50 {
++			compatible = "renesas,r1ex24002", "atmel,24c02";
++			reg = <0x50>;
++			pagesize = <16>;
++		};
+ 	};
+ 
+ 	/*
+-- 
+2.19.0
+
diff --git a/patches/1411-ARM-dts-r8a7790-Correct-mask-for-GIC-PPI-interrupts.patch b/patches/1411-ARM-dts-r8a7790-Correct-mask-for-GIC-PPI-interrupts.patch
new file mode 100644
index 00000000000000..df55899d90dbaa
--- /dev/null
+++ b/patches/1411-ARM-dts-r8a7790-Correct-mask-for-GIC-PPI-interrupts.patch
@@ -0,0 +1,51 @@
+From 08e0fa45b6a1cb035a24493e51d0199fb7789158 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:19:52 +0200
+Subject: [PATCH 1411/1795] ARM: dts: r8a7790: Correct mask for GIC PPI
+ interrupts
+
+R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
+hence the second interrupt specifier cell for Private Peripheral
+Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
+can be delivered to all 8 processor cores.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2acb79e15119512da9b6a49906840e7678cfb618)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index b66a18af28f1..47a51cd71434 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -1554,7 +1554,7 @@
+ 			interrupt-controller;
+ 			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ 			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+ 			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+@@ -1810,10 +1810,10 @@
+ 
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+ 	/* External USB clock - can be overridden by the board */
+-- 
+2.19.0
+
diff --git a/patches/1412-ARM-dts-r8a73a4-Correct-mask-for-GIC-PPI-interrupts.patch b/patches/1412-ARM-dts-r8a73a4-Correct-mask-for-GIC-PPI-interrupts.patch
new file mode 100644
index 00000000000000..da39d2f86dc081
--- /dev/null
+++ b/patches/1412-ARM-dts-r8a73a4-Correct-mask-for-GIC-PPI-interrupts.patch
@@ -0,0 +1,51 @@
+From 64022298f37754b2d590e9df4619b804f7160e9e Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:19:53 +0200
+Subject: [PATCH 1412/1795] ARM: dts: r8a73a4: Correct mask for GIC PPI
+ interrupts
+
+R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
+cores, hence the second interrupt specifier cell for Private Peripheral
+Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are
+delivered to all 8 processor cores.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 45e75c425bdd1dd75d93eeaaef4c81d1563f2efa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
+index 8e48090e4fdc..080d037f5733 100644
+--- a/arch/arm/boot/dts/r8a73a4.dtsi
++++ b/arch/arm/boot/dts/r8a73a4.dtsi
+@@ -57,10 +57,10 @@
+ 
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
+ 	dbsc1: memory-controller@e6790000 {
+@@ -464,7 +464,7 @@
+ 			<0 0xf1002000 0 0x2000>,
+ 			<0 0xf1004000 0 0x2000>,
+ 			<0 0xf1006000 0 0x2000>;
+-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ 		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
+ 		clock-names = "clk";
+ 		power-domains = <&pd_c4>;
+-- 
+2.19.0
+
diff --git a/patches/1413-ARM-dts-r7s72100-Correct-watchdog-timer-interrupt-ty.patch b/patches/1413-ARM-dts-r7s72100-Correct-watchdog-timer-interrupt-ty.patch
new file mode 100644
index 00000000000000..ab651f04d803d3
--- /dev/null
+++ b/patches/1413-ARM-dts-r7s72100-Correct-watchdog-timer-interrupt-ty.patch
@@ -0,0 +1,35 @@
+From cd14a30d946b566210e755a97bee91529f619d2d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:24:48 +0200
+Subject: [PATCH 1413/1795] ARM: dts: r7s72100: Correct watchdog timer
+ interrupt type
+
+According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware
+User's Manual rev. 3.00, the watchdog timer interrupt is a level
+interrupt.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c02cc235a215e9c518f98da25753b9e02bb7144f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index 4a1aade0e751..c7b3dca6d81c 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -387,7 +387,7 @@
+ 		wdt: watchdog@fcfe0000 {
+ 			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+ 			reg = <0xfcfe0000 0x6>;
+-			interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&p0_clk>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1414-ARM-dts-r7s72100-Correct-RTC-interrupt-types.patch b/patches/1414-ARM-dts-r7s72100-Correct-RTC-interrupt-types.patch
new file mode 100644
index 00000000000000..88cb0d0d54af39
--- /dev/null
+++ b/patches/1414-ARM-dts-r7s72100-Correct-RTC-interrupt-types.patch
@@ -0,0 +1,38 @@
+From bfd8e378988a537f0220868e12dac26d12b765c2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:24:49 +0200
+Subject: [PATCH 1414/1795] ARM: dts: r7s72100: Correct RTC interrupt types
+
+According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware
+User's Manual rev. 3.00, the realtime clock interrupts are level not
+edge interrupts.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cad8e5a7a1e27e9efe4e706ace75e0826a79707f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index c7b3dca6d81c..eb2e6f95a2e8 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -682,9 +682,9 @@
+ 		rtc: rtc@fcff1000 {
+ 			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+ 			reg = <0xfcff1000 0x2e>;
+-			interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
+-				      GIC_SPI 277 IRQ_TYPE_EDGE_RISING
+-				      GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
++			interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "alarm", "period", "carry";
+ 			clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+ 				 <&rtc_x3_clk>, <&extal_clk>;
+-- 
+2.19.0
+
diff --git a/patches/1415-ARM-dts-r7s72100-Add-PMU-device-node.patch b/patches/1415-ARM-dts-r7s72100-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..5a16301b4656b6
--- /dev/null
+++ b/patches/1415-ARM-dts-r7s72100-Add-PMU-device-node.patch
@@ -0,0 +1,40 @@
+From 86abea82ff413f3976c5b24ff7ecbe525053ba6f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:00 +0200
+Subject: [PATCH 1415/1795] ARM: dts: r7s72100: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A9
+CPU core on RZ/A1H by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 74a0e50d70aa8f7baeaad7a5c5f7d6bdaf92ff1a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r7s72100.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
+index eb2e6f95a2e8..a54822e97bac 100644
+--- a/arch/arm/boot/dts/r7s72100.dtsi
++++ b/arch/arm/boot/dts/r7s72100.dtsi
+@@ -77,6 +77,11 @@
+ 		clock-div = <6>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a9-pmu";
++		interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
+ 	rtc_x1_clk: rtc_x1 {
+ 		#clock-cells = <0>;
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1416-ARM-dts-r8a7790-Add-PMU-device-nodes.patch b/patches/1416-ARM-dts-r8a7790-Add-PMU-device-nodes.patch
new file mode 100644
index 00000000000000..4dccf07389851e
--- /dev/null
+++ b/patches/1416-ARM-dts-r8a7790-Add-PMU-device-nodes.patch
@@ -0,0 +1,59 @@
+From bbf364d897c5a614e21560badd00bcccc736a51f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:01 +0200
+Subject: [PATCH 1416/1795] ARM: dts: r8a7790: Add PMU device nodes
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A15
+and Cortex-A7 CPU cores on R-Car H2 by adding device nodes for the two
+PMUs.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
+    hw perfevents: /pmu-1: failed to probe PMU!
+    hw perfevents: /pmu-1: failed to register PMU devices!
+
+The last two lines are due to the Cortex-A7 CPU cores being described in
+DT, but not enabled by the firmware.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5b68384469af764caa2c02f2c651409c6930c767)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7790.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
+index 47a51cd71434..4d06b154bd7e 100644
+--- a/arch/arm/boot/dts/r8a7790.dtsi
++++ b/arch/arm/boot/dts/r8a7790.dtsi
+@@ -202,6 +202,24 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu-0 {
++		compatible = "arm,cortex-a15-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
++	};
++
++	pmu-1 {
++		compatible = "arm,cortex-a7-pmu";
++		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1417-ARM-dts-r8a7791-Add-PMU-device-node.patch b/patches/1417-ARM-dts-r8a7791-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..59d53cb6724f43
--- /dev/null
+++ b/patches/1417-ARM-dts-r8a7791-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 70c988001084f645df232498a6f6328bcfb9df18 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:02 +0200
+Subject: [PATCH 1417/1795] ARM: dts: r8a7791: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A15
+CPU cores on R-Car M2-W by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8607428c96b94e9f53f46b6e5aa3b9dbd604ad07)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
+index 58f694eb411b..6e1dd7ad7bd6 100644
+--- a/arch/arm/boot/dts/r8a7791.dtsi
++++ b/arch/arm/boot/dts/r8a7791.dtsi
+@@ -126,6 +126,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a15-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1418-ARM-dts-r8a7792-Add-PMU-device-node.patch b/patches/1418-ARM-dts-r8a7792-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..5ec49dbc6b4762
--- /dev/null
+++ b/patches/1418-ARM-dts-r8a7792-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 13c0946255f3325651c9a0227ab545b0318ddfde Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:03 +0200
+Subject: [PATCH 1418/1795] ARM: dts: r8a7792: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A15
+CPU cores on R-Car V2H by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0f2bcba999463fcc2ad2d6ae0c91b62649d45190)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7792.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
+index d2cf8dd2d9b0..f44257dd86f6 100644
+--- a/arch/arm/boot/dts/r8a7792.dtsi
++++ b/arch/arm/boot/dts/r8a7792.dtsi
+@@ -85,6 +85,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a15-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1419-ARM-dts-r8a7793-Add-PMU-device-node.patch b/patches/1419-ARM-dts-r8a7793-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..1b1c36bafd547f
--- /dev/null
+++ b/patches/1419-ARM-dts-r8a7793-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 9e7ec0e6edf76baf2caab759edc4aee35f3c9dc1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:04 +0200
+Subject: [PATCH 1419/1795] ARM: dts: r8a7793: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A15
+CPU cores on R-Car M2-N by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cd1ce84a08e69450ee196edcb7686c78ff5b57c5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
+index 2fa052200495..4abecfc0ca98 100644
+--- a/arch/arm/boot/dts/r8a7793.dtsi
++++ b/arch/arm/boot/dts/r8a7793.dtsi
+@@ -110,6 +110,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a15-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1420-ARM-dts-r8a7794-Add-PMU-device-node.patch b/patches/1420-ARM-dts-r8a7794-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..fdd8a41bce3ca6
--- /dev/null
+++ b/patches/1420-ARM-dts-r8a7794-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 384a7308b42e5fa88759052f37228a923a8ccc57 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:05 +0200
+Subject: [PATCH 1420/1795] ARM: dts: r8a7794: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A7
+CPU cores on R-Car E2 by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 123703f0beebcd432ea204e9ac83150b23646088)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
+index 76aadcdf9d37..736196903d22 100644
+--- a/arch/arm/boot/dts/r8a7794.dtsi
++++ b/arch/arm/boot/dts/r8a7794.dtsi
+@@ -103,6 +103,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a7-pmu";
++		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1421-ARM-dts-r8a7743-Add-PMU-device-node.patch b/patches/1421-ARM-dts-r8a7743-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..fc0a746bb987d3
--- /dev/null
+++ b/patches/1421-ARM-dts-r8a7743-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 7c28c518d85583894454f2bfaaf88bffcf4f1b81 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:06 +0200
+Subject: [PATCH 1421/1795] ARM: dts: r8a7743: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A15
+CPU cores on RZ/G1M by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit fe60e933b053f00e53cd01fe323f25ebe8fecd52)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7743.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
+index 69d8f7e0f053..142949d7066f 100644
+--- a/arch/arm/boot/dts/r8a7743.dtsi
++++ b/arch/arm/boot/dts/r8a7743.dtsi
+@@ -125,6 +125,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a15-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1422-ARM-dts-r8a7745-Add-PMU-device-node.patch b/patches/1422-ARM-dts-r8a7745-Add-PMU-device-node.patch
new file mode 100644
index 00000000000000..d9d50d5399093e
--- /dev/null
+++ b/patches/1422-ARM-dts-r8a7745-Add-PMU-device-node.patch
@@ -0,0 +1,42 @@
+From 5cbff780a35ca8951084b2b72e466ec83afdf5e7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 7 May 2018 15:57:07 +0200
+Subject: [PATCH 1422/1795] ARM: dts: r8a7745: Add PMU device node
+
+Enable support for the ARM Performance Monitor Units in the Cortex-A7
+CPU cores on RZ/G1E by adding a device node for the PMU.
+
+New Linux output:
+
+    hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9562a6b1d0f6a287f5dda16a4538526c59408927)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7745.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
+index 3de69cb66c44..1cb7a7ab0418 100644
+--- a/arch/arm/boot/dts/r8a7745.dtsi
++++ b/arch/arm/boot/dts/r8a7745.dtsi
+@@ -105,6 +105,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu {
++		compatible = "arm,cortex-a7-pmu";
++		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>, <&cpu1>;
++	};
++
+ 	/* External SCIF clock */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1423-dt-bindings-arm-document-Renesas-V3HSK-board-binding.patch b/patches/1423-dt-bindings-arm-document-Renesas-V3HSK-board-binding.patch
new file mode 100644
index 00000000000000..22bb4a3ac87f1e
--- /dev/null
+++ b/patches/1423-dt-bindings-arm-document-Renesas-V3HSK-board-binding.patch
@@ -0,0 +1,38 @@
+From 62028f733b532bb6a22b54eff7dad804e10b0fb6 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 10 May 2018 21:09:40 +0300
+Subject: [PATCH 1423/1795] dt-bindings: arm: document Renesas V3HSK board
+ bindings
+
+Document the V3H Starter Kit device tree bindings, listing it as
+a supported board.
+
+This allows to use checkpatch.pl to validate .dts files referring to
+the V3HSK board.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c92db4a4a4c6c176c34604e456d6d355803d9ada)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
+index 02c5d261683f..d8cf740132c6 100644
+--- a/Documentation/devicetree/bindings/arm/shmobile.txt
++++ b/Documentation/devicetree/bindings/arm/shmobile.txt
+@@ -132,6 +132,8 @@ Boards:
+     compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
+   - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+     compatible = "renesas,stout", "renesas,r8a7790"
++  - V3HSK (Y-ASK-RCAR-V3H-WS10)
++    compatible = "renesas,v3hsk", "renesas,r8a77980"
+   - V3MSK (Y-ASK-RCAR-V3M-WS10)
+     compatible = "renesas,v3msk", "renesas,r8a77970"
+   - Wheat (RTP0RC7792ASKB0000JE)
+-- 
+2.19.0
+
diff --git a/patches/1424-ARM-dts-r8a7740-Add-CEU0.patch b/patches/1424-ARM-dts-r8a7740-Add-CEU0.patch
new file mode 100644
index 00000000000000..40b8e7f782b7c0
--- /dev/null
+++ b/patches/1424-ARM-dts-r8a7740-Add-CEU0.patch
@@ -0,0 +1,43 @@
+From 704a5d7da963c5f1ad175d2656557553c425d42a Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 26 Apr 2018 20:24:43 +0200
+Subject: [PATCH 1424/1795] ARM: dts: r8a7740: Add CEU0
+
+Describe CEU0 peripheral for Renesas R-Mobile A1 R8A7740 Soc.
+
+Reported-by: Geert Uytterhoeven <geert@glider.be>
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: dropped clock-names property]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 6ff6991bb4adc74cc248f2aaea2e5560671b34c2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
+index afd3bc5e6cf2..180eb9d2a390 100644
+--- a/arch/arm/boot/dts/r8a7740.dtsi
++++ b/arch/arm/boot/dts/r8a7740.dtsi
+@@ -67,6 +67,15 @@
+ 		power-domains = <&pd_d4>;
+ 	};
+ 
++	ceu0: ceu@fe910000 {
++		reg = <0xfe910000 0x3000>;
++		compatible = "renesas,r8a7740-ceu";
++		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
++		power-domains = <&pd_a4r>;
++		status = "disabled";
++	};
++
+ 	cmt1: timer@e6138000 {
+ 		compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
+ 		reg = <0xe6138000 0x170>;
+-- 
+2.19.0
+
diff --git a/patches/1425-ARM-dts-r8a7740-Add-CEU1.patch b/patches/1425-ARM-dts-r8a7740-Add-CEU1.patch
new file mode 100644
index 00000000000000..102bc89579a133
--- /dev/null
+++ b/patches/1425-ARM-dts-r8a7740-Add-CEU1.patch
@@ -0,0 +1,40 @@
+From 6621cedb1bddf76da386d72dafdc10a0967f30fe Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 15 May 2018 10:00:38 +0200
+Subject: [PATCH 1425/1795] ARM: dts: r8a7740: Add CEU1
+
+Describe CEU1 peripheral for Renesas R-Mobile A1 R8A7740 Soc.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+(cherry picked from commit 7fad92d05887319998b8d2bb40082b8b224d5ef5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
+index 180eb9d2a390..eb9a911deefb 100644
+--- a/arch/arm/boot/dts/r8a7740.dtsi
++++ b/arch/arm/boot/dts/r8a7740.dtsi
+@@ -76,6 +76,15 @@
+ 		status = "disabled";
+ 	};
+ 
++	ceu1: ceu@fe914000 {
++		reg = <0xfe914000 0x3000>;
++		compatible = "renesas,r8a7740-ceu";
++		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
++		power-domains = <&pd_a4r>;
++		status = "disabled";
++	};
++
+ 	cmt1: timer@e6138000 {
+ 		compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
+ 		reg = <0xe6138000 0x170>;
+-- 
+2.19.0
+
diff --git a/patches/1426-ARM-shmobile-defconfig-Enable-RENESAS_WDT_GEN.patch b/patches/1426-ARM-shmobile-defconfig-Enable-RENESAS_WDT_GEN.patch
new file mode 100644
index 00000000000000..23d0d37fe6b4a1
--- /dev/null
+++ b/patches/1426-ARM-shmobile-defconfig-Enable-RENESAS_WDT_GEN.patch
@@ -0,0 +1,34 @@
+From 5db24c191452ca6fbd3009963711bc2a877fdb4d Mon Sep 17 00:00:00 2001
+From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Date: Mon, 12 Feb 2018 17:44:23 +0000
+Subject: [PATCH 1426/1795] ARM: shmobile: defconfig: Enable RENESAS_WDT_GEN
+
+R-Car Gen2 and RZ/G1 platforms come with a watchdog IP, therefore enable
+its driver by default.
+
+Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0743559383d4e5371b120b8d452262a85c5d3951)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm/configs/shmobile_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
+index dd95d395f565..b49887e86a3d 100644
+--- a/arch/arm/configs/shmobile_defconfig
++++ b/arch/arm/configs/shmobile_defconfig
+@@ -128,6 +128,7 @@ CONFIG_CPU_THERMAL=y
+ CONFIG_RCAR_THERMAL=y
+ CONFIG_WATCHDOG=y
+ CONFIG_DA9063_WATCHDOG=y
++CONFIG_RENESAS_WDT=y
+ CONFIG_MFD_AS3711=y
+ CONFIG_MFD_DA9063=y
+ CONFIG_REGULATOR_FIXED_VOLTAGE=y
+-- 
+2.19.0
+
diff --git a/patches/1427-PCI-rcar-Use-runtime-PM-to-control-controller-clock.patch b/patches/1427-PCI-rcar-Use-runtime-PM-to-control-controller-clock.patch
new file mode 100644
index 00000000000000..ad78b30c3e0f67
--- /dev/null
+++ b/patches/1427-PCI-rcar-Use-runtime-PM-to-control-controller-clock.patch
@@ -0,0 +1,123 @@
+From b8a125653020622994ad1c9b87638637d113e20b Mon Sep 17 00:00:00 2001
+From: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Date: Sun, 8 Apr 2018 15:09:25 +0200
+Subject: [PATCH 1427/1795] PCI: rcar: Use runtime PM to control controller
+ clock
+
+The controller clock can be switched off during suspend/resume,
+let runtime PM take care of that.
+
+Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
+Signed-off-by: Hien Dang <hien.dang.eb@renesas.com>
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+To: linux-pci@vger.kernel.org
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 0df6150e7ceb8967c0f4e953a4468a5c7b184be8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 38 ++++++++++++------------------------
+ 1 file changed, 12 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index c37699d0dcf9..dc0d1f4c6517 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -145,7 +145,6 @@ struct rcar_pcie {
+ 	void __iomem		*base;
+ 	struct list_head	resources;
+ 	int			root_bus_nr;
+-	struct clk		*clk;
+ 	struct clk		*bus_clk;
+ 	struct			rcar_msi msi;
+ };
+@@ -917,24 +916,14 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 	if (IS_ERR(pcie->base))
+ 		return PTR_ERR(pcie->base);
+ 
+-	pcie->clk = devm_clk_get(dev, "pcie");
+-	if (IS_ERR(pcie->clk)) {
+-		dev_err(dev, "cannot get platform clock\n");
+-		return PTR_ERR(pcie->clk);
+-	}
+-	err = clk_prepare_enable(pcie->clk);
+-	if (err)
+-		return err;
+-
+ 	pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
+ 	if (IS_ERR(pcie->bus_clk)) {
+ 		dev_err(dev, "cannot get pcie bus clock\n");
+-		err = PTR_ERR(pcie->bus_clk);
+-		goto fail_clk;
++		return PTR_ERR(pcie->bus_clk);
+ 	}
+ 	err = clk_prepare_enable(pcie->bus_clk);
+ 	if (err)
+-		goto fail_clk;
++		return err;
+ 
+ 	i = irq_of_parse_and_map(dev->of_node, 0);
+ 	if (!i) {
+@@ -956,8 +945,6 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 
+ err_map_reg:
+ 	clk_disable_unprepare(pcie->bus_clk);
+-fail_clk:
+-	clk_disable_unprepare(pcie->clk);
+ 
+ 	return err;
+ }
+@@ -1127,22 +1114,22 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	if (err)
+ 		goto err_free_bridge;
+ 
++	pm_runtime_enable(pcie->dev);
++	err = pm_runtime_get_sync(pcie->dev);
++	if (err < 0) {
++		dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
++		goto err_pm_disable;
++	}
++
+ 	err = rcar_pcie_get_resources(pcie);
+ 	if (err < 0) {
+ 		dev_err(dev, "failed to request resources: %d\n", err);
+-		goto err_free_resource_list;
++		goto err_pm_put;
+ 	}
+ 
+ 	err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
+ 	if (err)
+-		goto err_free_resource_list;
+-
+-	pm_runtime_enable(dev);
+-	err = pm_runtime_get_sync(dev);
+-	if (err < 0) {
+-		dev_err(dev, "pm_runtime_get_sync failed\n");
+-		goto err_pm_disable;
+-	}
++		goto err_pm_put;
+ 
+ 	/* Failure to get a link might just be that no cards are inserted */
+ 	hw_init_fn = of_device_get_match_data(dev);
+@@ -1177,9 +1164,8 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 
+ err_pm_disable:
+ 	pm_runtime_disable(dev);
+-
+-err_free_resource_list:
+ 	pci_free_resource_list(&pcie->resources);
++
+ err_free_bridge:
+ 	pci_free_host_bridge(bridge);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1428-PCI-rcar-Clean-up-the-macros.patch b/patches/1428-PCI-rcar-Clean-up-the-macros.patch
new file mode 100644
index 00000000000000..6a4d8133567873
--- /dev/null
+++ b/patches/1428-PCI-rcar-Clean-up-the-macros.patch
@@ -0,0 +1,151 @@
+From bf06a84e84271319ab4dad4e7245316112e60146 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Sun, 8 Apr 2018 20:04:31 +0200
+Subject: [PATCH 1428/1795] PCI: rcar: Clean up the macros
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch replaces the (1 << n) with BIT(n) and cleans up whitespace,
+no functional change.
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Acked-by: Randy Dunlap <rdunlap@infradead.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0ee40820989b330e24926d82953ffb9e1c7a8425)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 53 ++++++++++++++++++------------------
+ 1 file changed, 27 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index dc0d1f4c6517..3fb9fb4ac2e7 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -14,6 +14,7 @@
+  * warranty of any kind, whether express or implied.
+  */
+ 
++#include <linux/bitops.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -33,9 +34,9 @@
+ 
+ #define PCIECAR			0x000010
+ #define PCIECCTLR		0x000018
+-#define  CONFIG_SEND_ENABLE	(1 << 31)
++#define  CONFIG_SEND_ENABLE	BIT(31)
+ #define  TYPE0			(0 << 8)
+-#define  TYPE1			(1 << 8)
++#define  TYPE1			BIT(8)
+ #define PCIECDR			0x000020
+ #define PCIEMSR			0x000028
+ #define PCIEINTXR		0x000400
+@@ -47,7 +48,7 @@
+ #define PCIETSTR		0x02004
+ #define  DATA_LINK_ACTIVE	1
+ #define PCIEERRFR		0x02020
+-#define  UNSUPPORTED_REQUEST	(1 << 4)
++#define  UNSUPPORTED_REQUEST	BIT(4)
+ #define PCIEMSIFR		0x02044
+ #define PCIEMSIALR		0x02048
+ #define  MSIFE			1
+@@ -60,17 +61,17 @@
+ /* local address reg & mask */
+ #define PCIELAR(x)		(0x02200 + ((x) * 0x20))
+ #define PCIELAMR(x)		(0x02208 + ((x) * 0x20))
+-#define  LAM_PREFETCH		(1 << 3)
+-#define  LAM_64BIT		(1 << 2)
+-#define  LAR_ENABLE		(1 << 1)
++#define  LAM_PREFETCH		BIT(3)
++#define  LAM_64BIT		BIT(2)
++#define  LAR_ENABLE		BIT(1)
+ 
+ /* PCIe address reg & mask */
+ #define PCIEPALR(x)		(0x03400 + ((x) * 0x20))
+ #define PCIEPAUR(x)		(0x03404 + ((x) * 0x20))
+ #define PCIEPAMR(x)		(0x03408 + ((x) * 0x20))
+ #define PCIEPTCTLR(x)		(0x0340c + ((x) * 0x20))
+-#define  PAR_ENABLE		(1 << 31)
+-#define  IO_SPACE		(1 << 8)
++#define  PAR_ENABLE		BIT(31)
++#define  IO_SPACE		BIT(8)
+ 
+ /* Configuration */
+ #define PCICONF(x)		(0x010000 + ((x) * 0x4))
+@@ -82,23 +83,23 @@
+ #define IDSETR1			0x011004
+ #define TLCTLR			0x011048
+ #define MACSR			0x011054
+-#define  SPCHGFIN		(1 << 4)
+-#define  SPCHGFAIL		(1 << 6)
+-#define  SPCHGSUC		(1 << 7)
++#define  SPCHGFIN		BIT(4)
++#define  SPCHGFAIL		BIT(6)
++#define  SPCHGSUC		BIT(7)
+ #define  LINK_SPEED		(0xf << 16)
+ #define  LINK_SPEED_2_5GTS	(1 << 16)
+ #define  LINK_SPEED_5_0GTS	(2 << 16)
+ #define MACCTLR			0x011058
+-#define  SPEED_CHANGE		(1 << 24)
+-#define  SCRAMBLE_DISABLE	(1 << 27)
++#define  SPEED_CHANGE		BIT(24)
++#define  SCRAMBLE_DISABLE	BIT(27)
+ #define MACS2R			0x011078
+ #define MACCGSPSETR		0x011084
+-#define  SPCNGRSN		(1 << 31)
++#define  SPCNGRSN		BIT(31)
+ 
+ /* R-Car H1 PHY */
+ #define H1_PCIEPHYADRR		0x04000c
+-#define  WRITE_CMD		(1 << 16)
+-#define  PHY_ACK		(1 << 24)
++#define  WRITE_CMD		BIT(16)
++#define  PHY_ACK		BIT(24)
+ #define  RATE_POS		12
+ #define  LANE_POS		8
+ #define  ADR_POS		0
+@@ -110,19 +111,19 @@
+ #define GEN2_PCIEPHYDATA	0x784
+ #define GEN2_PCIEPHYCTRL	0x78c
+ 
+-#define INT_PCI_MSI_NR	32
++#define INT_PCI_MSI_NR		32
+ 
+-#define RCONF(x)	(PCICONF(0)+(x))
+-#define RPMCAP(x)	(PMCAP(0)+(x))
+-#define REXPCAP(x)	(EXPCAP(0)+(x))
+-#define RVCCAP(x)	(VCCAP(0)+(x))
++#define RCONF(x)		(PCICONF(0) + (x))
++#define RPMCAP(x)		(PMCAP(0) + (x))
++#define REXPCAP(x)		(EXPCAP(0) + (x))
++#define RVCCAP(x)		(VCCAP(0) + (x))
+ 
+-#define  PCIE_CONF_BUS(b)	(((b) & 0xff) << 24)
+-#define  PCIE_CONF_DEV(d)	(((d) & 0x1f) << 19)
+-#define  PCIE_CONF_FUNC(f)	(((f) & 0x7) << 16)
++#define PCIE_CONF_BUS(b)	(((b) & 0xff) << 24)
++#define PCIE_CONF_DEV(d)	(((d) & 0x1f) << 19)
++#define PCIE_CONF_FUNC(f)	(((f) & 0x7) << 16)
+ 
+-#define RCAR_PCI_MAX_RESOURCES 4
+-#define MAX_NR_INBOUND_MAPS 6
++#define RCAR_PCI_MAX_RESOURCES	4
++#define MAX_NR_INBOUND_MAPS	6
+ 
+ struct rcar_msi {
+ 	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
+-- 
+2.19.0
+
diff --git a/patches/1429-PCI-rcar-Poll-PHYRDY-in-rcar_pcie_hw_init.patch b/patches/1429-PCI-rcar-Poll-PHYRDY-in-rcar_pcie_hw_init.patch
new file mode 100644
index 00000000000000..44e9c6362704d8
--- /dev/null
+++ b/patches/1429-PCI-rcar-Poll-PHYRDY-in-rcar_pcie_hw_init.patch
@@ -0,0 +1,73 @@
+From f87e2479cd0afe0065244c6640f600111900841c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 3 May 2018 22:36:37 +0300
+Subject: [PATCH 1429/1795] PCI: rcar: Poll PHYRDY in rcar_pcie_hw_init()
+
+In all the R-Car gen1/2/3 manuals, we are instructed to poll PCIEPHYSR
+for PHYRDY=1 at an early stage of the PCIEC initialization -- while
+the driver only does this on R-Car H1 (polling a PHY specific register).
+Add the PHYRDY polling to rcar_pcie_hw_init(). Note that without the
+special PHY driver on the R-Car V3H (R8A77980) the PCIEC initialization
+just freezes the kernel -- adding the PHYRDY polling allows the init code
+to exit gracefully on timeout (PHY starts powered down after reset on this
+SoC).
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3ad1d32744ef4f0eb92b1989ef7b488cb7dc740d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 3fb9fb4ac2e7..93f83fb65940 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -40,6 +40,8 @@
+ #define PCIECDR			0x000020
+ #define PCIEMSR			0x000028
+ #define PCIEINTXR		0x000400
++#define PCIEPHYSR		0x0007f0
++#define  PHYRDY			BIT(0)
+ #define PCIEMSITXR		0x000840
+ 
+ /* Transfer control */
+@@ -530,6 +532,20 @@ static void phy_write_reg(struct rcar_pcie *pcie,
+ 	phy_wait_for_ack(pcie);
+ }
+ 
++static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
++{
++	unsigned int timeout = 10;
++
++	while (timeout--) {
++		if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
++			return 0;
++
++		msleep(5);
++	}
++
++	return -ETIMEDOUT;
++}
++
+ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+ {
+ 	unsigned int timeout = 10;
+@@ -554,6 +570,10 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
+ 	/* Set mode */
+ 	rcar_pci_write_reg(pcie, 1, PCIEMSR);
+ 
++	err = rcar_pcie_wait_for_phyrdy(pcie);
++	if (err)
++		return err;
++
+ 	/*
+ 	 * Initial header for port config space is type 1, set the device
+ 	 * class to match. Hardware takes care of propagating the IDSETR
+-- 
+2.19.0
+
diff --git a/patches/1430-PCI-rcar-Remove-PHYRDY-polling-from-rcar_pcie_hw_ini.patch b/patches/1430-PCI-rcar-Remove-PHYRDY-polling-from-rcar_pcie_hw_ini.patch
new file mode 100644
index 00000000000000..2efafad0f9f9d3
--- /dev/null
+++ b/patches/1430-PCI-rcar-Remove-PHYRDY-polling-from-rcar_pcie_hw_ini.patch
@@ -0,0 +1,63 @@
+From 81049c91bb75c2f2d4be7d4795e9d2e17a4e37d3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 3 May 2018 22:37:52 +0300
+Subject: [PATCH 1430/1795] PCI: rcar: Remove PHYRDY polling from
+ rcar_pcie_hw_init_h1()
+
+Since rcar_pcie_hw_init() is polling PCIEPHYSR.PHYRDY there is no need
+anymore for polling the PHY specific register in rcar_pcie_hw_init_h1().
+
+Remove it.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+[lorenzo.pieralisi@arm.com: updated commit log]
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit bd7b6d147a14c308a0227852334e01723451c73c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 12 +-----------
+ 1 file changed, 1 insertion(+), 11 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 93f83fb65940..d8a2849a941f 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -106,7 +106,6 @@
+ #define  LANE_POS		8
+ #define  ADR_POS		0
+ #define H1_PCIEPHYDOUTR		0x040014
+-#define H1_PCIEPHYSR		0x040018
+ 
+ /* R-Car Gen2 PHY */
+ #define GEN2_PCIEPHYADDR	0x780
+@@ -630,8 +629,6 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
+ 
+ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
+ {
+-	unsigned int timeout = 10;
+-
+ 	/* Initialize the phy */
+ 	phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
+ 	phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
+@@ -650,14 +647,7 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
+ 	phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
+ 	phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
+ 
+-	while (timeout--) {
+-		if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
+-			return rcar_pcie_hw_init(pcie);
+-
+-		msleep(5);
+-	}
+-
+-	return -ETIMEDOUT;
++	return rcar_pcie_hw_init(pcie);
+ }
+ 
+ static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
+-- 
+2.19.0
+
diff --git a/patches/1431-PCI-rcar-Add-R-Car-gen3-PHY-support.patch b/patches/1431-PCI-rcar-Add-R-Car-gen3-PHY-support.patch
new file mode 100644
index 00000000000000..f2646797c6ba72
--- /dev/null
+++ b/patches/1431-PCI-rcar-Add-R-Car-gen3-PHY-support.patch
@@ -0,0 +1,110 @@
+From 7eeab08976490e3ebb71ebbab0c0e7221b3b5a65 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 3 May 2018 22:40:54 +0300
+Subject: [PATCH 1431/1795] PCI: rcar: Add R-Car gen3 PHY support
+
+On R-Car gen3 SoCs the PCIe PHY has its own register region, thus we
+need to add the corresponding code in rcar_pcie_hw_init_gen3() and call
+devm_phy_optional_get() at the driver's probing time, so that the
+existing R-Car gen3 device trees (not having a PHY node) would still
+work (we only need to power up the PHY on R-Car V3H).
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+[lorenzo.pieralisi@arm.com: updated commit log]
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+
+(cherry picked from commit 517ca93a7159eb94eeef829f6ca036456050115c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/pci/rcar-pci.txt      |  5 ++++
+ drivers/pci/host/pcie-rcar.c                  | 27 +++++++++++++++++--
+ 2 files changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+index 1fb614e615da..4376c69ea20a 100644
+--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
++++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+@@ -32,6 +32,11 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
+ 	and PCIe bus clocks.
+ - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
+ 
++Optional properties:
++- phys: from common PHY binding: PHY phandle and specifier (only make sense
++	for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
++- phy-names: from common PHY binding: should be "pcie".
++
+ Example:
+ 
+ SoC-specific DT Entry:
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index d8a2849a941f..695465df4580 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -28,6 +28,7 @@
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+ #include <linux/pci.h>
++#include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
+@@ -144,6 +145,7 @@ static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
+ /* Structure representing the PCIe interface */
+ struct rcar_pcie {
+ 	struct device		*dev;
++	struct phy		*phy;
+ 	void __iomem		*base;
+ 	struct list_head	resources;
+ 	int			root_bus_nr;
+@@ -670,6 +672,21 @@ static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
+ 	return rcar_pcie_hw_init(pcie);
+ }
+ 
++static int rcar_pcie_hw_init_gen3(struct rcar_pcie *pcie)
++{
++	int err;
++
++	err = phy_init(pcie->phy);
++	if (err)
++		return err;
++
++	err = phy_power_on(pcie->phy);
++	if (err)
++		return err;
++
++	return rcar_pcie_hw_init(pcie);
++}
++
+ static int rcar_msi_alloc(struct rcar_msi *chip)
+ {
+ 	int msi;
+@@ -919,6 +936,10 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 	struct resource res;
+ 	int err, i;
+ 
++	pcie->phy = devm_phy_optional_get(dev, "pcie");
++	if (IS_ERR(pcie->phy))
++		return PTR_ERR(pcie->phy);
++
+ 	err = of_address_to_resource(dev->of_node, 0, &res);
+ 	if (err)
+ 		return err;
+@@ -1059,8 +1080,10 @@ static const struct of_device_id rcar_pcie_of_match[] = {
+ 	  .data = rcar_pcie_hw_init_gen2 },
+ 	{ .compatible = "renesas,pcie-rcar-gen2",
+ 	  .data = rcar_pcie_hw_init_gen2 },
+-	{ .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
+-	{ .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init },
++	{ .compatible = "renesas,pcie-r8a7795",
++	  .data = rcar_pcie_hw_init_gen3 },
++	{ .compatible = "renesas,pcie-rcar-gen3",
++	  .data = rcar_pcie_hw_init_gen3 },
+ 	{},
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1432-PCI-rcar-Factor-out-rcar_pcie_hw_init-call.patch b/patches/1432-PCI-rcar-Factor-out-rcar_pcie_hw_init-call.patch
new file mode 100644
index 00000000000000..45616da82f739d
--- /dev/null
+++ b/patches/1432-PCI-rcar-Factor-out-rcar_pcie_hw_init-call.patch
@@ -0,0 +1,130 @@
+From 847371fa592da758284c0e69cc434ef1265b5bc7 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 3 May 2018 22:43:13 +0300
+Subject: [PATCH 1432/1795] PCI: rcar: Factor out rcar_pcie_hw_init() call
+
+rcar_pcie_hw_init_{h1|gen2|gen3}() only differ in the PCIe PHY init code
+and all end with a call to rcar_pcie_hw_init(), thus it makes sense to
+move that call into the driver's probe() method and then rename those
+functions to rcar_pcie_phy_init_{h1|gen2|gen3}().
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+[lorenzo.pieralisi@arm.com: updated commit log]
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 9d5014e90e6d62eabe03946dbba27076b77b31e1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 42 +++++++++++++++++++-----------------
+ 1 file changed, 22 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 695465df4580..09b0b0af782c 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -629,7 +629,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
+ 	return 0;
+ }
+ 
+-static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
++static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
+ {
+ 	/* Initialize the phy */
+ 	phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
+@@ -649,10 +649,10 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
+ 	phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
+ 	phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
+ 
+-	return rcar_pcie_hw_init(pcie);
++	return 0;
+ }
+ 
+-static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
++static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
+ {
+ 	/*
+ 	 * These settings come from the R-Car Series, 2nd Generation User's
+@@ -669,10 +669,10 @@ static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
+ 	rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
+ 	rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
+ 
+-	return rcar_pcie_hw_init(pcie);
++	return 0;
+ }
+ 
+-static int rcar_pcie_hw_init_gen3(struct rcar_pcie *pcie)
++static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
+ {
+ 	int err;
+ 
+@@ -680,11 +680,7 @@ static int rcar_pcie_hw_init_gen3(struct rcar_pcie *pcie)
+ 	if (err)
+ 		return err;
+ 
+-	err = phy_power_on(pcie->phy);
+-	if (err)
+-		return err;
+-
+-	return rcar_pcie_hw_init(pcie);
++	return phy_power_on(pcie->phy);
+ }
+ 
+ static int rcar_msi_alloc(struct rcar_msi *chip)
+@@ -1073,17 +1069,18 @@ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
+ }
+ 
+ static const struct of_device_id rcar_pcie_of_match[] = {
+-	{ .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
++	{ .compatible = "renesas,pcie-r8a7779",
++	  .data = rcar_pcie_phy_init_h1 },
+ 	{ .compatible = "renesas,pcie-r8a7790",
+-	  .data = rcar_pcie_hw_init_gen2 },
++	  .data = rcar_pcie_phy_init_gen2 },
+ 	{ .compatible = "renesas,pcie-r8a7791",
+-	  .data = rcar_pcie_hw_init_gen2 },
++	  .data = rcar_pcie_phy_init_gen2 },
+ 	{ .compatible = "renesas,pcie-rcar-gen2",
+-	  .data = rcar_pcie_hw_init_gen2 },
++	  .data = rcar_pcie_phy_init_gen2 },
+ 	{ .compatible = "renesas,pcie-r8a7795",
+-	  .data = rcar_pcie_hw_init_gen3 },
++	  .data = rcar_pcie_phy_init_gen3 },
+ 	{ .compatible = "renesas,pcie-rcar-gen3",
+-	  .data = rcar_pcie_hw_init_gen3 },
++	  .data = rcar_pcie_phy_init_gen3 },
+ 	{},
+ };
+ 
+@@ -1131,7 +1128,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	struct rcar_pcie *pcie;
+ 	unsigned int data;
+ 	int err;
+-	int (*hw_init_fn)(struct rcar_pcie *);
++	int (*phy_init_fn)(struct rcar_pcie *);
+ 	struct pci_host_bridge *bridge;
+ 
+ 	bridge = pci_alloc_host_bridge(sizeof(*pcie));
+@@ -1165,10 +1162,15 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	if (err)
+ 		goto err_pm_put;
+ 
+-	/* Failure to get a link might just be that no cards are inserted */
+-	hw_init_fn = of_device_get_match_data(dev);
+-	err = hw_init_fn(pcie);
++	phy_init_fn = of_device_get_match_data(dev);
++	err = phy_init_fn(pcie);
+ 	if (err) {
++		dev_err(dev, "failed to init PCIe PHY\n");
++		goto err_pm_put;
++	}
++
++	/* Failure to get a link might just be that no cards are inserted */
++	if (rcar_pcie_hw_init(pcie)) {
+ 		dev_info(dev, "PCIe link down\n");
+ 		err = -ENODEV;
+ 		goto err_pm_put;
+-- 
+2.19.0
+
diff --git a/patches/1433-DT-pci-rcar-pci-document-R8A77980-bindings.patch b/patches/1433-DT-pci-rcar-pci-document-R8A77980-bindings.patch
new file mode 100644
index 00000000000000..4c039716b01182
--- /dev/null
+++ b/patches/1433-DT-pci-rcar-pci-document-R8A77980-bindings.patch
@@ -0,0 +1,36 @@
+From 6f5af49401d65c448faedfde9bfb16cc743d4c93 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 3 May 2018 22:44:58 +0300
+Subject: [PATCH 1433/1795] DT: pci: rcar-pci: document R8A77980 bindings
+
+Document the R-Car V3H (R8A77980) SoC in the R-Car PCIe bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+(cherry picked from commit 2a291ead5e5e699ab1b08fc109e25e721a25b5e5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	Documentation/devicetree/bindings/pci/rcar-pci.txt
+---
+ Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+index 4376c69ea20a..a5f7fc62d10e 100644
+--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
++++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
+@@ -8,6 +8,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
+ 	    "renesas,pcie-r8a7793" for the R8A7793 SoC;
+ 	    "renesas,pcie-r8a7795" for the R8A7795 SoC;
+ 	    "renesas,pcie-r8a7796" for the R8A7796 SoC;
++	    "renesas,pcie-r8a77980" for the R8A77980 SoC;
+ 	    "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
+ 				     RZ/G1 compatible device.
+ 	    "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
+-- 
+2.19.0
+
diff --git a/patches/1434-PCI-rcar-Reuse-generic-pci_parse_request_of_pci_rang.patch b/patches/1434-PCI-rcar-Reuse-generic-pci_parse_request_of_pci_rang.patch
new file mode 100644
index 00000000000000..cf4b18793caebe
--- /dev/null
+++ b/patches/1434-PCI-rcar-Reuse-generic-pci_parse_request_of_pci_rang.patch
@@ -0,0 +1,86 @@
+From 49e4c27d24a190e67bfc27f2cd37bd287acdac77 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 25 Apr 2018 18:21:25 +0300
+Subject: [PATCH 1434/1795] PCI: rcar: Reuse generic
+ pci_parse_request_of_pci_ranges() function
+
+The non-functional change removes a custom function to parse and
+allocate PCI resources in favour of pci_parse_request_of_pci_ranges().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit f7e1c6461e04afb8574cd91864f316cfcb8969f4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/pci/host/pcie-rcar.c
+---
+ drivers/pci/host/pcie-rcar.c | 42 +-----------------------------------
+ 1 file changed, 1 insertion(+), 41 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 09b0b0af782c..92b2b7725b9c 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -1084,44 +1084,6 @@ static const struct of_device_id rcar_pcie_of_match[] = {
+ 	{},
+ };
+ 
+-static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
+-{
+-	int err;
+-	struct device *dev = pci->dev;
+-	struct device_node *np = dev->of_node;
+-	resource_size_t iobase;
+-	struct resource_entry *win, *tmp;
+-
+-	err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
+-					       &iobase);
+-	if (err)
+-		return err;
+-
+-	err = devm_request_pci_bus_resources(dev, &pci->resources);
+-	if (err)
+-		goto out_release_res;
+-
+-	resource_list_for_each_entry_safe(win, tmp, &pci->resources) {
+-		struct resource *res = win->res;
+-
+-		if (resource_type(res) == IORESOURCE_IO) {
+-			err = devm_pci_remap_iospace(dev, res, iobase);
+-			if (err) {
+-				dev_warn(dev, "error %d: failed to map resource %pR\n",
+-					 err, res);
+-
+-				resource_list_destroy_entry(win);
+-			}
+-		}
+-	}
+-
+-	return 0;
+-
+-out_release_res:
+-	pci_free_resource_list(&pci->resources);
+-	return err;
+-}
+-
+ static int rcar_pcie_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -1139,9 +1101,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 
+ 	pcie->dev = dev;
+ 
+-	INIT_LIST_HEAD(&pcie->resources);
+-
+-	err = rcar_pcie_parse_request_of_pci_ranges(pcie);
++	err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
+ 	if (err)
+ 		goto err_free_bridge;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1435-PCI-rcar-Poll-more-often-in-rcar_pcie_wait_for_dl.patch b/patches/1435-PCI-rcar-Poll-more-often-in-rcar_pcie_wait_for_dl.patch
new file mode 100644
index 00000000000000..339bd754f27aff
--- /dev/null
+++ b/patches/1435-PCI-rcar-Poll-more-often-in-rcar_pcie_wait_for_dl.patch
@@ -0,0 +1,53 @@
+From f1965c85a5e37140640cab2e9956d99799662398 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 22 May 2018 14:24:20 +0200
+Subject: [PATCH 1435/1795] PCI: rcar: Poll more often in
+ rcar_pcie_wait_for_dl()
+
+The data link active signal usually takes ~20 uSec to be asserted, poll
+the bit more often to avoid useless delays in this function.
+
+Use udelay() instead of usleep() for such a small delay as suggested by
+the timer documentation.
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+[lorenzo.pieralisi@arm.com: updated commit log]
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+
+(cherry picked from commit 0353ff29b3881a8d9df65ce08a01e636868c1ef2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 92b2b7725b9c..dc2166ec097c 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -549,13 +549,14 @@ static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
+ 
+ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+ {
+-	unsigned int timeout = 10;
++	unsigned int timeout = 10000;
+ 
+ 	while (timeout--) {
+ 		if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+ 			return 0;
+ 
+-		msleep(5);
++		udelay(5);
++		cpu_relax();
+ 	}
+ 
+ 	return -ETIMEDOUT;
+-- 
+2.19.0
+
diff --git a/patches/1436-PCI-rcar-Pull-bus-clock-enable-disable-from-rcar_pci.patch b/patches/1436-PCI-rcar-Pull-bus-clock-enable-disable-from-rcar_pci.patch
new file mode 100644
index 00000000000000..4a6a07cbaa55f5
--- /dev/null
+++ b/patches/1436-PCI-rcar-Pull-bus-clock-enable-disable-from-rcar_pci.patch
@@ -0,0 +1,130 @@
+From cbcdfcc3d27c1180c0e77a1819efd2bb5494a33a Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 24 May 2018 16:36:19 +0200
+Subject: [PATCH 1436/1795] PCI: rcar: Pull bus clock enable/disable from
+ rcar_pcie_get_resources()
+
+The rcar_pcie_get_resources() is another misnomer with a side effect.
+The function does not only get resources, but also enables/disables bus
+clock. This is forgotten in the probe() function though and if anything
+in probe() fails after rcar_pcie_get_resources() is called, the bus
+clock are never disabled.
+
+This patch pulls the clock handling out of the rcar_pcie_get_resources()
+and enables clock after all the resources were requested. Moreover, this
+patch also always disables the clock in case of failure.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+(cherry picked from commit 80b8471e69d706d7622bbd633aca611d11b389b7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 33 ++++++++++++++++-----------------
+ 1 file changed, 16 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index dc2166ec097c..3da458b953c3 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -950,32 +950,22 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 		dev_err(dev, "cannot get pcie bus clock\n");
+ 		return PTR_ERR(pcie->bus_clk);
+ 	}
+-	err = clk_prepare_enable(pcie->bus_clk);
+-	if (err)
+-		return err;
+ 
+ 	i = irq_of_parse_and_map(dev->of_node, 0);
+ 	if (!i) {
+ 		dev_err(dev, "cannot get platform resources for msi interrupt\n");
+-		err = -ENOENT;
+-		goto err_map_reg;
++		return -ENOENT;
+ 	}
+ 	pcie->msi.irq1 = i;
+ 
+ 	i = irq_of_parse_and_map(dev->of_node, 1);
+ 	if (!i) {
+ 		dev_err(dev, "cannot get platform resources for msi interrupt\n");
+-		err = -ENOENT;
+-		goto err_map_reg;
++		return -ENOENT;
+ 	}
+ 	pcie->msi.irq2 = i;
+ 
+ 	return 0;
+-
+-err_map_reg:
+-	clk_disable_unprepare(pcie->bus_clk);
+-
+-	return err;
+ }
+ 
+ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
+@@ -1119,22 +1109,28 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 		goto err_pm_put;
+ 	}
+ 
++	err = clk_prepare_enable(pcie->bus_clk);
++	if (err) {
++		dev_err(dev, "failed to enable bus clock: %d\n", err);
++		goto err_pm_put;
++	}
++
+ 	err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
+ 	if (err)
+-		goto err_pm_put;
++		goto err_clk_disable;
+ 
+ 	phy_init_fn = of_device_get_match_data(dev);
+ 	err = phy_init_fn(pcie);
+ 	if (err) {
+ 		dev_err(dev, "failed to init PCIe PHY\n");
+-		goto err_pm_put;
++		goto err_clk_disable;
+ 	}
+ 
+ 	/* Failure to get a link might just be that no cards are inserted */
+ 	if (rcar_pcie_hw_init(pcie)) {
+ 		dev_info(dev, "PCIe link down\n");
+ 		err = -ENODEV;
+-		goto err_pm_put;
++		goto err_clk_disable;
+ 	}
+ 
+ 	data = rcar_pci_read_reg(pcie, MACSR);
+@@ -1146,16 +1142,19 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 			dev_err(dev,
+ 				"failed to enable MSI support: %d\n",
+ 				err);
+-			goto err_pm_put;
++			goto err_clk_disable;
+ 		}
+ 	}
+ 
+ 	err = rcar_pcie_enable(pcie);
+ 	if (err)
+-		goto err_pm_put;
++		goto err_clk_disable;
+ 
+ 	return 0;
+ 
++err_clk_disable:
++	clk_disable_unprepare(pcie->bus_clk);
++
+ err_pm_put:
+ 	pm_runtime_put(dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1437-PCI-rcar-Add-missing-irq_dispose_mapping-into-failpa.patch b/patches/1437-PCI-rcar-Add-missing-irq_dispose_mapping-into-failpa.patch
new file mode 100644
index 00000000000000..be5e79b0636e61
--- /dev/null
+++ b/patches/1437-PCI-rcar-Add-missing-irq_dispose_mapping-into-failpa.patch
@@ -0,0 +1,87 @@
+From c8d1f6b2f4b0eb9b3d4f024b41ad1725ec42bd6c Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 24 May 2018 16:36:20 +0200
+Subject: [PATCH 1437/1795] PCI: rcar: Add missing irq_dispose_mapping() into
+ failpath
+
+The rcar_pcie_get_resources() is another misnomer with a side effect.
+The function does not only get resources, but also maps MSI IRQs via
+irq_of_parse_and_map(). In case anything fails afterward, the IRQ
+mapping must be disposed through irq_dispose_mapping() which is not
+done.
+
+This patch handles irq_of_parse_and_map() failures in by disposing
+of the mapping in rcar_pcie_get_resources() as well as in probe.
+
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+(cherry picked from commit 53f1aebfbe46ffe422138758c9d015502740f714)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 3da458b953c3..382780353f64 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -954,18 +954,25 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 	i = irq_of_parse_and_map(dev->of_node, 0);
+ 	if (!i) {
+ 		dev_err(dev, "cannot get platform resources for msi interrupt\n");
+-		return -ENOENT;
++		err = -ENOENT;
++		goto err_irq1;
+ 	}
+ 	pcie->msi.irq1 = i;
+ 
+ 	i = irq_of_parse_and_map(dev->of_node, 1);
+ 	if (!i) {
+ 		dev_err(dev, "cannot get platform resources for msi interrupt\n");
+-		return -ENOENT;
++		err = -ENOENT;
++		goto err_irq2;
+ 	}
+ 	pcie->msi.irq2 = i;
+ 
+ 	return 0;
++
++err_irq2:
++	irq_dispose_mapping(pcie->msi.irq1);
++err_irq1:
++	return err;
+ }
+ 
+ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
+@@ -1112,7 +1119,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	err = clk_prepare_enable(pcie->bus_clk);
+ 	if (err) {
+ 		dev_err(dev, "failed to enable bus clock: %d\n", err);
+-		goto err_pm_put;
++		goto err_unmap_msi_irqs;
+ 	}
+ 
+ 	err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
+@@ -1155,6 +1162,10 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ err_clk_disable:
+ 	clk_disable_unprepare(pcie->bus_clk);
+ 
++err_unmap_msi_irqs:
++	irq_dispose_mapping(pcie->msi.irq2);
++	irq_dispose_mapping(pcie->msi.irq1);
++
+ err_pm_put:
+ 	pm_runtime_put(dev);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1438-PCI-rcar-Teardown-MSI-setup-if-rcar_pcie_enable-fail.patch b/patches/1438-PCI-rcar-Teardown-MSI-setup-if-rcar_pcie_enable-fail.patch
new file mode 100644
index 00000000000000..1b0dcffc1b4e04
--- /dev/null
+++ b/patches/1438-PCI-rcar-Teardown-MSI-setup-if-rcar_pcie_enable-fail.patch
@@ -0,0 +1,81 @@
+From c3bb029a7c7324ad488b6069ab0114ec45d79a24 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 24 May 2018 16:36:21 +0200
+Subject: [PATCH 1438/1795] PCI: rcar: Teardown MSI setup if rcar_pcie_enable()
+ fails
+
+If the rcar_pcie_enable() fails and MSIs are enabled, the setup done in
+rcar_pcie_enable_msi() is never undone. Add a function to tear down the
+MSI setup by disabling the MSI handling in the PCIe block, deallocating
+the pages requested for the MSIs and zapping the IRQ mapping.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+(cherry picked from commit 1aea58be739816f05232c64f970784d75a84cd96)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 28 +++++++++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 382780353f64..f5307b61d7e0 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -927,6 +927,28 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
+ 	return err;
+ }
+ 
++static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
++{
++	struct rcar_msi *msi = &pcie->msi;
++	int irq, i;
++
++	/* Disable all MSI interrupts */
++	rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
++
++	/* Disable address decoding of the MSI interrupt, MSIFE */
++	rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
++
++	free_pages(msi->pages, 0);
++
++	for (i = 0; i < INT_PCI_MSI_NR; i++) {
++		irq = irq_find_mapping(msi->domain, i);
++		if (irq > 0)
++			irq_dispose_mapping(irq);
++	}
++
++	irq_domain_remove(msi->domain);
++}
++
+ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ {
+ 	struct device *dev = pcie->dev;
+@@ -1155,10 +1177,14 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 
+ 	err = rcar_pcie_enable(pcie);
+ 	if (err)
+-		goto err_clk_disable;
++		goto err_msi_teardown;
+ 
+ 	return 0;
+ 
++err_msi_teardown:
++	if (IS_ENABLED(CONFIG_PCI_MSI))
++		rcar_pcie_teardown_msi(pcie);
++
+ err_clk_disable:
+ 	clk_disable_unprepare(pcie->bus_clk);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1439-PCI-rcar-Remove-IRQ-mappings-in-rcar_pcie_enable_msi.patch b/patches/1439-PCI-rcar-Remove-IRQ-mappings-in-rcar_pcie_enable_msi.patch
new file mode 100644
index 00000000000000..bf952b4c66f6aa
--- /dev/null
+++ b/patches/1439-PCI-rcar-Remove-IRQ-mappings-in-rcar_pcie_enable_msi.patch
@@ -0,0 +1,89 @@
+From 09a8253b226ec6c8db875653f73328a547e86563 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Thu, 24 May 2018 16:36:23 +0200
+Subject: [PATCH 1439/1795] PCI: rcar: Remove IRQ mappings in
+ rcar_pcie_enable_msi() failpath
+
+The rcar_pcie_enable_msi() creates IRQ mappings using irq_create_mapping()
+before requesting the IRQs using devm_request_irq(). If devm_request_irq()
+fails for some reason, rcar_pcie_enable_msi() does not remove the mapping.
+
+Pull out the code for disposing IRQ mappings from rcar_pcie_teardown_msi()
+into a separate function and call it from both rcar_pcie_teardown_msi()
+and rcar_pcie_enable_msi() failpath to remove the mappings correctly.
+
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Simon Horman <horms+renesas@verge.net.au>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+Cc: linux-renesas-soc@vger.kernel.org
+(cherry picked from commit 0bbf6b9230df602616a6c6f5861e8964e9162f4a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pci/host/pcie-rcar.c | 25 ++++++++++++++++---------
+ 1 file changed, 16 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index f5307b61d7e0..23251c6cde5c 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -869,6 +869,20 @@ static const struct irq_domain_ops msi_domain_ops = {
+ 	.map = rcar_msi_map,
+ };
+ 
++static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie)
++{
++	struct rcar_msi *msi = &pcie->msi;
++	int i, irq;
++
++	for (i = 0; i < INT_PCI_MSI_NR; i++) {
++		irq = irq_find_mapping(msi->domain, i);
++		if (irq > 0)
++			irq_dispose_mapping(irq);
++	}
++
++	irq_domain_remove(msi->domain);
++}
++
+ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
+ {
+ 	struct device *dev = pcie->dev;
+@@ -923,14 +937,13 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
+ 	return 0;
+ 
+ err:
+-	irq_domain_remove(msi->domain);
++	rcar_pcie_unmap_msi(pcie);
+ 	return err;
+ }
+ 
+ static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
+ {
+ 	struct rcar_msi *msi = &pcie->msi;
+-	int irq, i;
+ 
+ 	/* Disable all MSI interrupts */
+ 	rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
+@@ -940,13 +953,7 @@ static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
+ 
+ 	free_pages(msi->pages, 0);
+ 
+-	for (i = 0; i < INT_PCI_MSI_NR; i++) {
+-		irq = irq_find_mapping(msi->domain, i);
+-		if (irq > 0)
+-			irq_dispose_mapping(irq);
+-	}
+-
+-	irq_domain_remove(msi->domain);
++	rcar_pcie_unmap_msi(pcie);
+ }
+ 
+ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+-- 
+2.19.0
+
diff --git a/patches/1440-xhci-Create-new-structures-to-store-xhci-port-inform.patch b/patches/1440-xhci-Create-new-structures-to-store-xhci-port-inform.patch
new file mode 100644
index 00000000000000..43fbb735563828
--- /dev/null
+++ b/patches/1440-xhci-Create-new-structures-to-store-xhci-port-inform.patch
@@ -0,0 +1,219 @@
+From 7ac4a0bd38eaceca547d7cb24ca59d82eca7a225 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:52 +0300
+Subject: [PATCH 1440/1795] xhci: Create new structures to store xhci port
+ information
+
+Current way of having one array telling only the port speed,
+and then two separate arrays with mmio addresses for usb2 and usb3 ports
+requeres helper functions to transate  hw to hcd, and hcd to hw port
+numbers, and is hard to expand.
+
+Instead create a structure describing a port, including the mmio address,
+the port hardware index, hcd port index, and a pointer to the roothub
+it belongs to.
+
+Create one array containing all port structures in the same order the
+hardware controller sees them. Then add an array of port pointers to
+each xhci hub structure pointing to the ports that belonging to the
+roothub.
+
+This way we can easily convert hw indexed port events to usb core
+hcd port numbers, and vice versa usb core hub hcd port numbers
+to hw index and mmio address.
+
+Other benefit is that we can easily find the parent hcd and xhci
+structure of a port structure. This is useful in debugfs where
+we can give one port structure pointer as parameter and get both
+the correct mmio address and xhci lock needed to set some port
+parameter.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit bcaa9d5c59005eceed5f2112c13240401f0fb93b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-mem.c | 58 ++++++++++++++++++++++++++++++++++++-
+ drivers/usb/host/xhci.h     | 21 ++++++++++----
+ 2 files changed, 73 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 0b424a4b58ec..76ec1cfb746b 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -1892,16 +1892,24 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
+ 	xhci->cmd_ring_reserved_trbs = 0;
+ 	xhci->num_usb2_ports = 0;
+ 	xhci->num_usb3_ports = 0;
++	xhci->usb2_rhub.num_ports = 0;
++	xhci->usb3_rhub.num_ports = 0;
+ 	xhci->num_active_eps = 0;
+ 	kfree(xhci->usb2_ports);
+ 	kfree(xhci->usb3_ports);
+ 	kfree(xhci->port_array);
++	kfree(xhci->usb2_rhub.ports);
++	kfree(xhci->usb3_rhub.ports);
++	kfree(xhci->hw_ports);
+ 	kfree(xhci->rh_bw);
+ 	kfree(xhci->ext_caps);
+ 
+ 	xhci->usb2_ports = NULL;
+ 	xhci->usb3_ports = NULL;
+ 	xhci->port_array = NULL;
++	xhci->usb2_rhub.ports = NULL;
++	xhci->usb3_rhub.ports = NULL;
++	xhci->hw_ports = NULL;
+ 	xhci->rh_bw = NULL;
+ 	xhci->ext_caps = NULL;
+ 
+@@ -2186,8 +2194,10 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
+ 
+ 	port_offset--;
+ 	for (i = port_offset; i < (port_offset + port_count); i++) {
++		struct xhci_port *hw_port = &xhci->hw_ports[i];
+ 		/* Duplicate entry.  Ignore the port if the revisions differ. */
+-		if (xhci->port_array[i] != 0) {
++		if (xhci->port_array[i] != 0 ||
++		    hw_port->rhub) {
+ 			xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
+ 					" port %u\n", addr, i);
+ 			xhci_warn(xhci, "Port was marked as USB %u, "
+@@ -2205,9 +2215,16 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
+ 				xhci->port_array[i] = DUPLICATE_ENTRY;
+ 			}
+ 			/* FIXME: Should we disable the port? */
++			if (hw_port->rhub != rhub &&
++				 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
++				hw_port->rhub->num_ports--;
++				hw_port->hcd_portnum = DUPLICATE_ENTRY;
++			}
+ 			continue;
+ 		}
+ 		xhci->port_array[i] = major_revision;
++		hw_port->rhub = rhub;
++		rhub->num_ports++;
+ 		if (major_revision == 0x03)
+ 			xhci->num_usb3_ports++;
+ 		else
+@@ -2216,6 +2233,27 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
+ 	/* FIXME: Should we disable ports not in the Extended Capabilities? */
+ }
+ 
++static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
++					struct xhci_hub *rhub, gfp_t flags)
++{
++	int port_index = 0;
++	int i;
++
++	if (!rhub->num_ports)
++		return;
++	rhub->ports = kcalloc(rhub->num_ports, sizeof(rhub->ports), flags);
++	for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
++		if (xhci->hw_ports[i].rhub != rhub ||
++		    xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
++			continue;
++		xhci->hw_ports[i].hcd_portnum = port_index;
++		rhub->ports[port_index] = &xhci->hw_ports[i];
++		port_index++;
++		if (port_index == rhub->num_ports)
++			break;
++	}
++}
++
+ /*
+  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
+  * specify what speeds each port is supposed to be.  We can't count on the port
+@@ -2234,9 +2272,16 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 
+ 	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
+ 	xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
++	xhci->hw_ports = kcalloc(num_ports, sizeof(*xhci->hw_ports), flags);
+ 	if (!xhci->port_array)
+ 		return -ENOMEM;
+ 
++	for (i = 0; i < num_ports; i++) {
++		xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
++			NUM_PORT_REGS * i;
++		xhci->hw_ports[i].hw_portnum = i;
++	}
++
+ 	xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
+ 	if (!xhci->rh_bw)
+ 		return -ENOMEM;
+@@ -2274,6 +2319,9 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 		xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
+ 		if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports)
+ 			break;
++		if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
++		    num_ports)
++			break;
+ 		offset = xhci_find_next_ext_cap(base, offset,
+ 						XHCI_EXT_CAPS_PROTOCOL);
+ 	}
+@@ -2282,6 +2330,10 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 		xhci_warn(xhci, "No ports on the roothubs?\n");
+ 		return -ENODEV;
+ 	}
++	if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
++		xhci_warn(xhci, "No ports on the roothubs?\n");
++		return -ENODEV;
++	}
+ 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ 			"Found %u USB 2.0 ports and %u USB 3.0 ports.",
+ 			xhci->num_usb2_ports, xhci->num_usb3_ports);
+@@ -2306,6 +2358,10 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 	 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
+ 	 * Not sure how the USB core will handle a hub with no ports...
+ 	 */
++
++	xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
++	xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
++
+ 	if (xhci->num_usb2_ports) {
+ 		xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
+ 				xhci->num_usb2_ports, flags);
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 9751c1373fbb..2ec0ca2cd87f 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1687,13 +1687,23 @@ static inline unsigned int hcd_index(struct usb_hcd *hcd)
+ 	else
+ 		return 1;
+ }
++struct xhci_port {
++	__le32 __iomem		*addr;
++	int			hw_portnum;
++	int			hcd_portnum;
++	struct xhci_hub		*rhub;
++};
+ 
+ struct xhci_hub {
+-	u8	maj_rev;
+-	u8	min_rev;
+-	u32	*psi;		/* array of protocol speed ID entries */
+-	u8	psi_count;
+-	u8	psi_uid_count;
++	struct xhci_port	**ports;
++	unsigned int		num_ports;
++	struct usb_hcd		*hcd;
++	/* supported prococol extended capabiliy values */
++	u8			maj_rev;
++	u8			min_rev;
++	u32			*psi;	/* array of protocol speed ID entries */
++	u8			psi_count;
++	u8			psi_uid_count;
+ };
+ 
+ /* There is one xhci_hcd structure per controller */
+@@ -1842,6 +1852,7 @@ struct xhci_hcd {
+ 	struct xhci_bus_state   bus_state[2];
+ 	/* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
+ 	u8			*port_array;
++	struct xhci_port	*hw_ports;
+ 	/* Array of pointers to USB 3.0 PORTSC registers */
+ 	__le32 __iomem		**usb3_ports;
+ 	unsigned int		num_usb3_ports;
+-- 
+2.19.0
+
diff --git a/patches/1441-xhci-set-hcd-pointers-for-xhci-usb2-and-usb3-roothub.patch b/patches/1441-xhci-set-hcd-pointers-for-xhci-usb2-and-usb3-roothub.patch
new file mode 100644
index 00000000000000..dae8edb5789f0d
--- /dev/null
+++ b/patches/1441-xhci-set-hcd-pointers-for-xhci-usb2-and-usb3-roothub.patch
@@ -0,0 +1,41 @@
+From a219de7e91ea0bc6d6462c07491da5130cef858d Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:53 +0300
+Subject: [PATCH 1441/1795] xhci: set hcd pointers for xhci usb2 and usb3
+ roothub structures
+
+Allows us to know the correct hcd a xhci roothub and its ports
+belong to.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 9ea95ecc7ffd338a62972ddd6b0ac46bdc5e7d49)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 5466d4db6ffe..7155659bb920 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -4898,6 +4898,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 
+ 	if (usb_hcd_is_primary_hcd(hcd)) {
+ 		xhci->main_hcd = hcd;
++		xhci->usb2_rhub.hcd = hcd;
+ 		/* Mark the first roothub as being USB 2.0.
+ 		 * The xHCI driver will register the USB 3.0 roothub.
+ 		 */
+@@ -4923,6 +4924,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 			  minor_rev,
+ 			  minor_rev ? "Enhanced" : "");
+ 
++		xhci->usb3_rhub.hcd = hcd;
+ 		/* xHCI private pointer was set in xhci_pci_probe for the second
+ 		 * registered roothub.
+ 		 */
+-- 
+2.19.0
+
diff --git a/patches/1442-xhci-Add-helper-to-get-xhci-roothub-from-hcd.patch b/patches/1442-xhci-Add-helper-to-get-xhci-roothub-from-hcd.patch
new file mode 100644
index 00000000000000..c5f772bdb269f5
--- /dev/null
+++ b/patches/1442-xhci-Add-helper-to-get-xhci-roothub-from-hcd.patch
@@ -0,0 +1,54 @@
+From 5b55ffb6c6963078ac0dfade101764cd0b66c31b Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:54 +0300
+Subject: [PATCH 1442/1795] xhci: Add helper to get xhci roothub from hcd
+
+quick way to get the xhci roothub and thus all the ports
+belonging to a certain hcd
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ffd4b4fc0b9a1526b64240676d309506b2d5eceb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 9 +++++++++
+ drivers/usb/host/xhci.h     | 2 ++
+ 2 files changed, 11 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 32cd52ca8318..b6fd26fa7faf 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -554,6 +554,15 @@ static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
+ 	return max_ports;
+ }
+ 
++struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
++{
++	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
++
++	if (hcd->speed >= HCD_USB3)
++		return &xhci->usb3_rhub;
++	return &xhci->usb2_rhub;
++}
++
+ static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
+ {
+ 	__le32 __iomem **port_array;
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 2ec0ca2cd87f..d90b97ec20a2 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2114,6 +2114,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
+ 		char *buf, u16 wLength);
+ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
+ int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
++struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
++
+ void xhci_hc_died(struct xhci_hcd *xhci);
+ 
+ #ifdef CONFIG_PM
+-- 
+2.19.0
+
diff --git a/patches/1443-xhci-xhci-hub-use-new-port-structures-to-get-port-ad.patch b/patches/1443-xhci-xhci-hub-use-new-port-structures-to-get-port-ad.patch
new file mode 100644
index 00000000000000..b3fbc853d52222
--- /dev/null
+++ b/patches/1443-xhci-xhci-hub-use-new-port-structures-to-get-port-ad.patch
@@ -0,0 +1,467 @@
+From 72e2a5bda63b24bd137609611e18382586f9166a Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:55 +0300
+Subject: [PATCH 1443/1795] xhci: xhci-hub: use new port structures to get port
+ address instead of port array
+
+Use the new port structures for functions in xhci-hub.c to get
+port mmio address of portsc register instead of the port array
+
+xhci_get_port_io_addr() is no longer needeed and is removed.
+Plan is to get rid of the mmio port array completely.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit e740b019d7c6b4de38f57a26d4cf1b15125bdcbf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 140 ++++++++++++++++++++----------------
+ 1 file changed, 78 insertions(+), 62 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index b6fd26fa7faf..0796f08934fb 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -189,9 +189,10 @@ static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
+ 	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
+ 	u32 portsc;
+ 	unsigned int i;
++	struct xhci_hub *rhub;
+ 
+-	ports = xhci->num_usb2_ports;
+-
++	rhub = &xhci->usb2_rhub;
++	ports = rhub->num_ports;
+ 	xhci_common_hub_descriptor(xhci, desc, ports);
+ 	desc->bDescriptorType = USB_DT_HUB;
+ 	temp = 1 + (ports / 8);
+@@ -202,7 +203,7 @@ static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
+ 	 */
+ 	memset(port_removable, 0, sizeof(port_removable));
+ 	for (i = 0; i < ports; i++) {
+-		portsc = readl(xhci->usb2_ports[i]);
++		portsc = readl(rhub->ports[i]->addr);
+ 		/* If a device is removable, PORTSC reports a 0, same as in the
+ 		 * hub descriptor DeviceRemovable bits.
+ 		 */
+@@ -241,8 +242,10 @@ static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
+ 	u16 port_removable;
+ 	u32 portsc;
+ 	unsigned int i;
++	struct xhci_hub *rhub;
+ 
+-	ports = xhci->num_usb3_ports;
++	rhub = &xhci->usb3_rhub;
++	ports = rhub->num_ports;
+ 	xhci_common_hub_descriptor(xhci, desc, ports);
+ 	desc->bDescriptorType = USB_DT_SS_HUB;
+ 	desc->bDescLength = USB_DT_SS_HUB_SIZE;
+@@ -256,7 +259,7 @@ static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
+ 	port_removable = 0;
+ 	/* bit 0 is reserved, bit 1 is for port 1, etc. */
+ 	for (i = 0; i < ports; i++) {
+-		portsc = readl(xhci->usb3_ports[i]);
++		portsc = readl(rhub->ports[i]->addr);
+ 		if (portsc & PORT_DEV_REMOVE)
+ 			port_removable |= 1 << (i + 1);
+ 	}
+@@ -563,14 +566,6 @@ struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
+ 	return &xhci->usb2_rhub;
+ }
+ 
+-static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
+-{
+-	__le32 __iomem **port_array;
+-
+-	xhci_get_ports(hcd, &port_array);
+-	return port_array[index];
+-}
+-
+ /*
+  * xhci_set_port_power() must be called with xhci->lock held.
+  * It will release and re-aquire the lock while calling ACPI
+@@ -579,21 +574,23 @@ static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
+ static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
+ 				u16 index, bool on, unsigned long *flags)
+ {
+-	__le32 __iomem *addr;
++	struct xhci_hub *rhub;
++	struct xhci_port *port;
+ 	u32 temp;
+ 
+-	addr = xhci_get_port_io_addr(hcd, index);
+-	temp = readl(addr);
++	rhub = xhci_get_rhub(hcd);
++	port = rhub->ports[index];
++	temp = readl(port->addr);
+ 	temp = xhci_port_state_to_neutral(temp);
+ 	if (on) {
+ 		/* Power on */
+-		writel(temp | PORT_POWER, addr);
+-		temp = readl(addr);
++		writel(temp | PORT_POWER, port->addr);
++		temp = readl(port->addr);
+ 		xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
+ 						index, temp);
+ 	} else {
+ 		/* Power off */
+-		writel(temp & ~PORT_POWER, addr);
++		writel(temp & ~PORT_POWER, port->addr);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&xhci->lock, *flags);
+@@ -609,13 +606,13 @@ static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
+ 	u16 test_mode, u16 wIndex)
+ {
+ 	u32 temp;
+-	__le32 __iomem *addr;
++	struct xhci_port *port;
+ 
+-	/* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
+-	addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
+-	temp = readl(addr + PORTPMSC);
++	/* xhci only supports test mode for usb2 ports */
++	port = xhci->usb2_rhub.ports[wIndex];
++	temp = readl(port->addr + PORTPMSC);
+ 	temp |= test_mode << PORT_TEST_MODE_SHIFT;
+-	writel(temp, addr + PORTPMSC);
++	writel(temp, port->addr + PORTPMSC);
+ 	xhci->test_mode = test_mode;
+ 	if (test_mode == TEST_FORCE_EN)
+ 		xhci_start(xhci);
+@@ -642,10 +639,10 @@ static int xhci_enter_test_mode(struct xhci_hcd *xhci,
+ 	/* Put all ports to the Disable state by clear PP */
+ 	xhci_dbg(xhci, "Disable all port (PP = 0)\n");
+ 	/* Power off USB3 ports*/
+-	for (i = 0; i < xhci->num_usb3_ports; i++)
++	for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
+ 		xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
+ 	/* Power off USB2 ports*/
+-	for (i = 0; i < xhci->num_usb2_ports; i++)
++	for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
+ 		xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
+ 	/* Stop the controller */
+ 	xhci_dbg(xhci, "Stop controller\n");
+@@ -803,7 +800,7 @@ static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
+ static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
+ 				    u16 wIndex)
+ {
+-	u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
++	u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
+ 	bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
+ 
+ 	if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
+@@ -858,6 +855,11 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
+ 	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ 	u32 status = 0;
+ 	int slot_id;
++	struct xhci_hub *rhub;
++	struct xhci_port *port;
++
++	rhub = xhci_get_rhub(hcd);
++	port = rhub->ports[wIndex];
+ 
+ 	/* wPortChange bits */
+ 	if (raw_port_status & PORT_CSC)
+@@ -949,7 +951,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
+ 				}
+ 				xhci_ring_device(xhci, slot_id);
+ 			} else {
+-				int port_status = readl(port_array[wIndex]);
++				int port_status = readl(port->addr);
+ 				xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
+ 						XHCI_MAX_REXIT_TIMEOUT,
+ 						port_status);
+@@ -1040,7 +1042,11 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 	u16 wake_mask = 0;
+ 	u16 timeout = 0;
+ 	u16 test_mode = 0;
++	struct xhci_hub *rhub;
++	struct xhci_port **ports;
+ 
++	rhub = xhci_get_rhub(hcd);
++	ports = rhub->ports;
+ 	max_ports = xhci_get_ports(hcd, &port_array);
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+@@ -1079,7 +1085,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 		if (!wIndex || wIndex > max_ports)
+ 			goto error;
+ 		wIndex--;
+-		temp = readl(port_array[wIndex]);
++		temp = readl(ports[wIndex]->addr);
+ 		if (temp == ~(u32)0) {
+ 			xhci_hc_died(xhci);
+ 			retval = -ENODEV;
+@@ -1105,7 +1111,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 				retval = -EINVAL;
+ 				break;
+ 			}
+-			port_li = readl(port_array[wIndex] + PORTLI);
++			port_li = readl(ports[wIndex]->addr + PORTLI);
+ 			status = xhci_get_ext_port_status(temp, port_li);
+ 			put_unaligned_le32(cpu_to_le32(status), &buf[4]);
+ 		}
+@@ -1123,7 +1129,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 		if (!wIndex || wIndex > max_ports)
+ 			goto error;
+ 		wIndex--;
+-		temp = readl(port_array[wIndex]);
++		temp = readl(ports[wIndex]->addr);
+ 		if (temp == ~(u32)0) {
+ 			xhci_hc_died(xhci);
+ 			retval = -ENODEV;
+@@ -1133,7 +1139,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 		/* FIXME: What new port features do we need to support? */
+ 		switch (wValue) {
+ 		case USB_PORT_FEAT_SUSPEND:
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			if ((temp & PORT_PLS_MASK) != XDEV_U0) {
+ 				/* Resume the port to U0 first */
+ 				xhci_set_link_state(xhci, port_array, wIndex,
+@@ -1146,7 +1152,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			 * a port unless the port reports that it is in the
+ 			 * enabled (PED = ‘1’,PLS < ‘3’) state.
+ 			 */
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
+ 				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
+ 				xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
+@@ -1170,12 +1176,11 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			msleep(10); /* wait device to enter */
+ 			spin_lock_irqsave(&xhci->lock, flags);
+ 
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			bus_state->suspended_ports |= 1 << wIndex;
+ 			break;
+ 		case USB_PORT_FEAT_LINK_STATE:
+-			temp = readl(port_array[wIndex]);
+-
++			temp = readl(ports[wIndex]->addr);
+ 			/* Disable port */
+ 			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
+ 				xhci_dbg(xhci, "Disable port %d\n", wIndex);
+@@ -1187,8 +1192,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 				temp |= PORT_CSC | PORT_PEC | PORT_WRC |
+ 					PORT_OCC | PORT_RC | PORT_PLC |
+ 					PORT_CEC;
+-				writel(temp | PORT_PE, port_array[wIndex]);
+-				temp = readl(port_array[wIndex]);
++				writel(temp | PORT_PE, ports[wIndex]->addr);
++				temp = readl(ports[wIndex]->addr);
+ 				break;
+ 			}
+ 
+@@ -1197,7 +1202,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 				xhci_dbg(xhci, "Enable port %d\n", wIndex);
+ 				xhci_set_link_state(xhci, port_array, wIndex,
+ 						link_state);
+-				temp = readl(port_array[wIndex]);
++				temp = readl(ports[wIndex]->addr);
+ 				break;
+ 			}
+ 
+@@ -1230,7 +1235,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 						wIndex);
+ 				xhci_set_link_state(xhci, port_array, wIndex,
+ 						link_state);
+-				temp = readl(port_array[wIndex]);
++				temp = readl(ports[wIndex]->addr);
+ 				break;
+ 			}
+ 			/* Port must be enabled */
+@@ -1264,7 +1269,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			msleep(20); /* wait device to enter */
+ 			spin_lock_irqsave(&xhci->lock, flags);
+ 
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			if (link_state == USB_SS_PORT_LS_U3)
+ 				bus_state->suspended_ports |= 1 << wIndex;
+ 			break;
+@@ -1279,40 +1284,39 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			break;
+ 		case USB_PORT_FEAT_RESET:
+ 			temp = (temp | PORT_RESET);
+-			writel(temp, port_array[wIndex]);
++			writel(temp, ports[wIndex]->addr);
+ 
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
+ 			break;
+ 		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
+ 			xhci_set_remote_wake_mask(xhci, port_array,
+ 					wIndex, wake_mask);
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			xhci_dbg(xhci, "set port remote wake mask, "
+ 					"actual port %d status  = 0x%x\n",
+ 					wIndex, temp);
+ 			break;
+ 		case USB_PORT_FEAT_BH_PORT_RESET:
+ 			temp |= PORT_WR;
+-			writel(temp, port_array[wIndex]);
+-
+-			temp = readl(port_array[wIndex]);
++			writel(temp, ports[wIndex]->addr);
++			temp = readl(ports[wIndex]->addr);
+ 			break;
+ 		case USB_PORT_FEAT_U1_TIMEOUT:
+ 			if (hcd->speed < HCD_USB3)
+ 				goto error;
+-			temp = readl(port_array[wIndex] + PORTPMSC);
++			temp = readl(ports[wIndex]->addr + PORTPMSC);
+ 			temp &= ~PORT_U1_TIMEOUT_MASK;
+ 			temp |= PORT_U1_TIMEOUT(timeout);
+-			writel(temp, port_array[wIndex] + PORTPMSC);
++			writel(temp, ports[wIndex]->addr + PORTPMSC);
+ 			break;
+ 		case USB_PORT_FEAT_U2_TIMEOUT:
+ 			if (hcd->speed < HCD_USB3)
+ 				goto error;
+-			temp = readl(port_array[wIndex] + PORTPMSC);
++			temp = readl(ports[wIndex]->addr + PORTPMSC);
+ 			temp &= ~PORT_U2_TIMEOUT_MASK;
+ 			temp |= PORT_U2_TIMEOUT(timeout);
+-			writel(temp, port_array[wIndex] + PORTPMSC);
++			writel(temp, ports[wIndex]->addr + PORTPMSC);
+ 			break;
+ 		case USB_PORT_FEAT_TEST:
+ 			/* 4.19.6 Port Test Modes (USB2 Test Mode) */
+@@ -1327,13 +1331,13 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			goto error;
+ 		}
+ 		/* unblock any posted writes */
+-		temp = readl(port_array[wIndex]);
++		temp = readl(ports[wIndex]->addr);
+ 		break;
+ 	case ClearPortFeature:
+ 		if (!wIndex || wIndex > max_ports)
+ 			goto error;
+ 		wIndex--;
+-		temp = readl(port_array[wIndex]);
++		temp = readl(ports[wIndex]->addr);
+ 		if (temp == ~(u32)0) {
+ 			xhci_hc_died(xhci);
+ 			retval = -ENODEV;
+@@ -1343,7 +1347,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 		temp = xhci_port_state_to_neutral(temp);
+ 		switch (wValue) {
+ 		case USB_PORT_FEAT_SUSPEND:
+-			temp = readl(port_array[wIndex]);
++			temp = readl(ports[wIndex]->addr);
+ 			xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
+ 			xhci_dbg(xhci, "PORTSC %04x\n", temp);
+ 			if (temp & PORT_RESET)
+@@ -1383,11 +1387,11 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 		case USB_PORT_FEAT_C_PORT_LINK_STATE:
+ 		case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
+ 			xhci_clear_port_change_bit(xhci, wValue, wIndex,
+-					port_array[wIndex], temp);
++					ports[wIndex]->addr, temp);
+ 			break;
+ 		case USB_PORT_FEAT_ENABLE:
+ 			xhci_disable_port(hcd, xhci, wIndex,
+-					port_array[wIndex], temp);
++					ports[wIndex]->addr, temp);
+ 			break;
+ 		case USB_PORT_FEAT_POWER:
+ 			xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
+@@ -1427,7 +1431,11 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+ 	__le32 __iomem **port_array;
+ 	struct xhci_bus_state *bus_state;
+ 	bool reset_change = false;
++	struct xhci_hub *rhub;
++	struct xhci_port **ports;
+ 
++	rhub = xhci_get_rhub(hcd);
++	ports = rhub->ports;
+ 	max_ports = xhci_get_ports(hcd, &port_array);
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+@@ -1446,7 +1454,7 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+ 	spin_lock_irqsave(&xhci->lock, flags);
+ 	/* For each port, did anything change?  If so, set that bit in buf. */
+ 	for (i = 0; i < max_ports; i++) {
+-		temp = readl(port_array[i]);
++		temp = readl(ports[i]->addr);
+ 		if (temp == ~(u32)0) {
+ 			xhci_hc_died(xhci);
+ 			retval = -ENODEV;
+@@ -1481,7 +1489,11 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+ 	__le32 __iomem **port_array;
+ 	struct xhci_bus_state *bus_state;
+ 	unsigned long flags;
++	struct xhci_hub *rhub;
++	struct xhci_port **ports;
+ 
++	rhub = xhci_get_rhub(hcd);
++	ports = rhub->ports;
+ 	max_ports = xhci_get_ports(hcd, &port_array);
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+@@ -1503,7 +1515,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+ 		u32 t1, t2;
+ 		int slot_id;
+ 
+-		t1 = readl(port_array[port_index]);
++		t1 = readl(ports[port_index]->addr);
+ 		t2 = xhci_port_state_to_neutral(t1);
+ 
+ 		if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
+@@ -1543,7 +1555,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+ 
+ 		t1 = xhci_port_state_to_neutral(t1);
+ 		if (t1 != t2)
+-			writel(t2, port_array[port_index]);
++			writel(t2, ports[port_index]->addr);
+ 	}
+ 	hcd->state = HC_STATE_SUSPENDED;
+ 	bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
+@@ -1591,7 +1603,11 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 	int sret;
+ 	u32 next_state;
+ 	u32 temp, portsc;
++	struct xhci_hub *rhub;
++	struct xhci_port **ports;
+ 
++	rhub = xhci_get_rhub(hcd);
++	ports = rhub->ports;
+ 	max_ports = xhci_get_ports(hcd, &port_array);
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+@@ -1617,7 +1633,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 
+ 	port_index = max_ports;
+ 	while (port_index--) {
+-		portsc = readl(port_array[port_index]);
++		portsc = readl(ports[port_index]->addr);
+ 
+ 		/* warm reset CAS limited ports stuck in polling/compliance */
+ 		if ((xhci->quirks & XHCI_MISSING_CAS) &&
+@@ -1646,7 +1662,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 			}
+ 		/* disable wake for all ports, write new link state if needed */
+ 		portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
+-		writel(portsc, port_array[port_index]);
++		writel(portsc, ports[port_index]->addr);
+ 	}
+ 
+ 	/* USB2 specific resume signaling delay and U0 link state transition */
+@@ -1668,7 +1684,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 
+ 	/* poll for U0 link state complete, both USB2 and USB3 */
+ 	for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
+-		sret = xhci_handshake(port_array[port_index], PORT_PLC,
++		sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
+ 				      PORT_PLC, 10 * 1000);
+ 		if (sret) {
+ 			xhci_warn(xhci, "port %d resume PLC timeout\n",
+-- 
+2.19.0
+
diff --git a/patches/1444-xhci-xhci-hub-use-new-port-structures-for-cas-and-wa.patch b/patches/1444-xhci-xhci-hub-use-new-port-structures-for-cas-and-wa.patch
new file mode 100644
index 00000000000000..65aa6a867d21cf
--- /dev/null
+++ b/patches/1444-xhci-xhci-hub-use-new-port-structures-for-cas-and-wa.patch
@@ -0,0 +1,96 @@
+From e6cf7019c7f29e36cea724220bfcc0e705077fcf Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:56 +0300
+Subject: [PATCH 1444/1795] xhci: xhci-hub: use new port structures for cas and
+ wake mask functions.
+
+Use port structures instead of mmio port arrays for
+xhci_port_missing_cas_quirk() and xhci_set_remote_wake_mask() in
+xhci-hub.c
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fdcf74ffef640fd30402863877d442c8bada7582)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 21 ++++++++++-----------
+ 1 file changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 0796f08934fb..372b4486c52a 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -691,11 +691,11 @@ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+ }
+ 
+ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
+-		__le32 __iomem **port_array, int port_id, u16 wake_mask)
++				      struct xhci_port *port, u16 wake_mask)
+ {
+ 	u32 temp;
+ 
+-	temp = readl(port_array[port_id]);
++	temp = readl(port->addr);
+ 	temp = xhci_port_state_to_neutral(temp);
+ 
+ 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
+@@ -713,7 +713,7 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
+ 	else
+ 		temp &= ~PORT_WKOC_E;
+ 
+-	writel(temp, port_array[port_id]);
++	writel(temp, port->addr);
+ }
+ 
+ /* Test and clear port RWC bit */
+@@ -1290,8 +1290,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
+ 			break;
+ 		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
+-			xhci_set_remote_wake_mask(xhci, port_array,
+-					wIndex, wake_mask);
++			xhci_set_remote_wake_mask(xhci, ports[wIndex],
++						  wake_mask);
+ 			temp = readl(ports[wIndex]->addr);
+ 			xhci_dbg(xhci, "set port remote wake mask, "
+ 					"actual port %d status  = 0x%x\n",
+@@ -1568,12 +1568,11 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+  * warm reset a USB3 device stuck in polling or compliance mode after resume.
+  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
+  */
+-static bool xhci_port_missing_cas_quirk(int port_index,
+-					     __le32 __iomem **port_array)
++static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
+ {
+ 	u32 portsc;
+ 
+-	portsc = readl(port_array[port_index]);
++	portsc = readl(port->addr);
+ 
+ 	/* if any of these are set we are not stuck */
+ 	if (portsc & (PORT_CONNECT | PORT_CAS))
+@@ -1586,9 +1585,9 @@ static bool xhci_port_missing_cas_quirk(int port_index,
+ 	/* clear wakeup/change bits, and do a warm port reset */
+ 	portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
+ 	portsc |= PORT_WR;
+-	writel(portsc, port_array[port_index]);
++	writel(portsc, port->addr);
+ 	/* flush write */
+-	readl(port_array[port_index]);
++	readl(port->addr);
+ 	return true;
+ }
+ 
+@@ -1638,7 +1637,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 		/* warm reset CAS limited ports stuck in polling/compliance */
+ 		if ((xhci->quirks & XHCI_MISSING_CAS) &&
+ 		    (hcd->speed >= HCD_USB3) &&
+-		    xhci_port_missing_cas_quirk(port_index, port_array)) {
++		    xhci_port_missing_cas_quirk(ports[port_index])) {
+ 			xhci_dbg(xhci, "reset stuck port %d\n", port_index);
+ 			clear_bit(port_index, &bus_state->bus_suspended);
+ 			continue;
+-- 
+2.19.0
+
diff --git a/patches/1445-xhci-xhci-ring-use-port-structures-for-port-event-ha.patch b/patches/1445-xhci-xhci-ring-use-port-structures-for-port-event-ha.patch
new file mode 100644
index 00000000000000..0f740370b069ce
--- /dev/null
+++ b/patches/1445-xhci-xhci-ring-use-port-structures-for-port-event-ha.patch
@@ -0,0 +1,140 @@
+From 841eb2cc7c527c95bc90074be43c1861202c08d3 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:57 +0300
+Subject: [PATCH 1445/1795] xhci: xhci-ring: use port structures for port event
+ handler
+
+use port structures in the port event handler.
+Getting the right hcd and hcd portnumber from the hardware port number
+is a lot easier with port structures, and allows us to remove a lot
+of the previous code, including the find_faked_portnum_from_hw_index()
+function
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 52c7755ba19ee2ae97fe5bfea7627bb27d5d7602)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 79 ++++--------------------------------
+ 1 file changed, 8 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 91a1a824673d..4d2d0e8fe22d 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1497,44 +1497,6 @@ static void handle_vendor_event(struct xhci_hcd *xhci,
+ 		handle_cmd_completion(xhci, &event->event_cmd);
+ }
+ 
+-/* @port_id: the one-based port ID from the hardware (indexed from array of all
+- * port registers -- USB 3.0 and USB 2.0).
+- *
+- * Returns a zero-based port number, which is suitable for indexing into each of
+- * the split roothubs' port arrays and bus state arrays.
+- * Add one to it in order to call xhci_find_slot_id_by_port.
+- */
+-static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
+-		struct xhci_hcd *xhci, u32 port_id)
+-{
+-	unsigned int i;
+-	unsigned int num_similar_speed_ports = 0;
+-
+-	/* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
+-	 * and usb2_ports are 0-based indexes.  Count the number of similar
+-	 * speed ports, up to 1 port before this port.
+-	 */
+-	for (i = 0; i < (port_id - 1); i++) {
+-		u8 port_speed = xhci->port_array[i];
+-
+-		/*
+-		 * Skip ports that don't have known speeds, or have duplicate
+-		 * Extended Capabilities port speed entries.
+-		 */
+-		if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
+-			continue;
+-
+-		/*
+-		 * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
+-		 * 1.1 ports are under the USB 2.0 hub.  If the port speed
+-		 * matches the device speed, it's a similar speed port.
+-		 */
+-		if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
+-			num_similar_speed_ports++;
+-	}
+-	return num_similar_speed_ports;
+-}
+-
+ static void handle_device_notification(struct xhci_hcd *xhci,
+ 		union xhci_trb *event)
+ {
+@@ -1564,10 +1526,10 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	int max_ports;
+ 	int slot_id;
+ 	unsigned int faked_port_index;
+-	u8 major_revision;
+ 	struct xhci_bus_state *bus_state;
+ 	__le32 __iomem **port_array;
+ 	bool bogus_port_status = false;
++	struct xhci_port *port;
+ 
+ 	/* Port status change events always have a successful completion code */
+ 	if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
+@@ -1584,47 +1546,22 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 		return;
+ 	}
+ 
+-	/* Figure out which usb_hcd this port is attached to:
+-	 * is it a USB 3.0 port or a USB 2.0/1.1 port?
+-	 */
+-	major_revision = xhci->port_array[port_id - 1];
+-
+-	/* Find the right roothub. */
+-	hcd = xhci_to_hcd(xhci);
+-	if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
+-		hcd = xhci->shared_hcd;
+-
+-	if (major_revision == 0) {
+-		xhci_warn(xhci, "Event for port %u not in "
+-				"Extended Capabilities, ignoring.\n",
+-				port_id);
+-		bogus_port_status = true;
+-		goto cleanup;
+-	}
+-	if (major_revision == DUPLICATE_ENTRY) {
+-		xhci_warn(xhci, "Event for port %u duplicated in"
+-				"Extended Capabilities, ignoring.\n",
+-				port_id);
++	port = &xhci->hw_ports[port_id - 1];
++	if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
++		xhci_warn(xhci, "Event for invalid port %u\n", port_id);
+ 		bogus_port_status = true;
+ 		goto cleanup;
+ 	}
+ 
+-	/*
+-	 * Hardware port IDs reported by a Port Status Change Event include USB
+-	 * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
+-	 * resume event, but we first need to translate the hardware port ID
+-	 * into the index into the ports on the correct split roothub, and the
+-	 * correct bus_state structure.
+-	 */
++	hcd = port->rhub->hcd;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 	if (hcd->speed >= HCD_USB3)
+ 		port_array = xhci->usb3_ports;
+ 	else
+ 		port_array = xhci->usb2_ports;
+-	/* Find the faked port hub number */
+-	faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
+-			port_id);
+-	portsc = readl(port_array[faked_port_index]);
++
++	faked_port_index = port->hcd_portnum;
++	portsc = readl(port->addr);
+ 
+ 	trace_xhci_handle_port_status(faked_port_index, portsc);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1446-xhci-rename-faked_port_index-to-hcd_portnum.patch b/patches/1446-xhci-rename-faked_port_index-to-hcd_portnum.patch
new file mode 100644
index 00000000000000..d8248809647998
--- /dev/null
+++ b/patches/1446-xhci-rename-faked_port_index-to-hcd_portnum.patch
@@ -0,0 +1,136 @@
+From ada571d3f7e3d9e6aa55b01057d83f9df21bcd07 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:58 +0300
+Subject: [PATCH 1446/1795] xhci: rename faked_port_index to hcd_portnum
+
+hcd_portnum is a better desctiption than faked_port_index, and
+is in line with the name the port structure uses.
+
+No functional changes
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 74e6ad583aa34a8de3ab3bc209256c3b53a1af4b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-ring.c | 41 +++++++++++++++++-------------------
+ 1 file changed, 19 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 4d2d0e8fe22d..31b72133d7a3 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1525,7 +1525,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	u32 portsc, cmd_reg;
+ 	int max_ports;
+ 	int slot_id;
+-	unsigned int faked_port_index;
++	unsigned int hcd_portnum;
+ 	struct xhci_bus_state *bus_state;
+ 	__le32 __iomem **port_array;
+ 	bool bogus_port_status = false;
+@@ -1560,10 +1560,10 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	else
+ 		port_array = xhci->usb2_ports;
+ 
+-	faked_port_index = port->hcd_portnum;
++	hcd_portnum = port->hcd_portnum;
+ 	portsc = readl(port->addr);
+ 
+-	trace_xhci_handle_port_status(faked_port_index, portsc);
++	trace_xhci_handle_port_status(hcd_portnum, portsc);
+ 
+ 	if (hcd->state == HC_STATE_SUSPENDED) {
+ 		xhci_dbg(xhci, "resume root hub\n");
+@@ -1571,7 +1571,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	}
+ 
+ 	if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE)
+-		bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
++		bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
+ 
+ 	if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
+ 		xhci_dbg(xhci, "port resume event for port %d\n", port_id);
+@@ -1588,29 +1588,28 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 			 * so we can tell the difference between the end of
+ 			 * device and host initiated resume.
+ 			 */
+-			bus_state->port_remote_wakeup |= 1 << faked_port_index;
++			bus_state->port_remote_wakeup |= 1 << hcd_portnum;
+ 			xhci_test_and_clear_bit(xhci, port_array,
+-					faked_port_index, PORT_PLC);
+-			xhci_set_link_state(xhci, port_array, faked_port_index,
++					hcd_portnum, PORT_PLC);
++			xhci_set_link_state(xhci, port_array, hcd_portnum,
+ 						XDEV_U0);
+ 			/* Need to wait until the next link state change
+ 			 * indicates the device is actually in U0.
+ 			 */
+ 			bogus_port_status = true;
+ 			goto cleanup;
+-		} else if (!test_bit(faked_port_index,
+-				     &bus_state->resuming_ports)) {
++		} else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
+ 			xhci_dbg(xhci, "resume HS port %d\n", port_id);
+-			bus_state->resume_done[faked_port_index] = jiffies +
++			bus_state->resume_done[hcd_portnum] = jiffies +
+ 				msecs_to_jiffies(USB_RESUME_TIMEOUT);
+-			set_bit(faked_port_index, &bus_state->resuming_ports);
++			set_bit(hcd_portnum, &bus_state->resuming_ports);
+ 			/* Do the rest in GetPortStatus after resume time delay.
+ 			 * Avoid polling roothub status before that so that a
+ 			 * usb device auto-resume latency around ~40ms.
+ 			 */
+ 			set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+ 			mod_timer(&hcd->rh_timer,
+-				  bus_state->resume_done[faked_port_index]);
++				  bus_state->resume_done[hcd_portnum]);
+ 			bogus_port_status = true;
+ 		}
+ 	}
+@@ -1625,17 +1624,15 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 		 * so the roothub behavior is consistent with external
+ 		 * USB 3.0 hub behavior.
+ 		 */
+-		slot_id = xhci_find_slot_id_by_port(hcd, xhci,
+-				faked_port_index + 1);
++		slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
+ 		if (slot_id && xhci->devs[slot_id])
+ 			xhci_ring_device(xhci, slot_id);
+-		if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
+-			bus_state->port_remote_wakeup &=
+-				~(1 << faked_port_index);
++		if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
++			bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
+ 			xhci_test_and_clear_bit(xhci, port_array,
+-					faked_port_index, PORT_PLC);
++					hcd_portnum, PORT_PLC);
+ 			usb_wakeup_notification(hcd->self.root_hub,
+-					faked_port_index + 1);
++					hcd_portnum + 1);
+ 			bogus_port_status = true;
+ 			goto cleanup;
+ 		}
+@@ -1647,15 +1644,15 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	 * out of the RExit state.
+ 	 */
+ 	if (!DEV_SUPERSPEED_ANY(portsc) &&
+-			test_and_clear_bit(faked_port_index,
++			test_and_clear_bit(hcd_portnum,
+ 				&bus_state->rexit_ports)) {
+-		complete(&bus_state->rexit_done[faked_port_index]);
++		complete(&bus_state->rexit_done[hcd_portnum]);
+ 		bogus_port_status = true;
+ 		goto cleanup;
+ 	}
+ 
+ 	if (hcd->speed < HCD_USB3)
+-		xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
++		xhci_test_and_clear_bit(xhci, port_array, hcd_portnum,
+ 					PORT_PLC);
+ 
+ cleanup:
+-- 
+2.19.0
+
diff --git a/patches/1447-xhci-change-xhci_set_link_state-to-work-with-port-st.patch b/patches/1447-xhci-change-xhci_set_link_state-to-work-with-port-st.patch
new file mode 100644
index 00000000000000..e34b7eb6e17a1c
--- /dev/null
+++ b/patches/1447-xhci-change-xhci_set_link_state-to-work-with-port-st.patch
@@ -0,0 +1,163 @@
+From 0251503d5d7b9e01f59702d87ec5d1f3744aaa16 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:39:59 +0300
+Subject: [PATCH 1447/1795] xhci: change xhci_set_link_state() to work with
+ port structures
+
+Remove old iomem port array and index as parameters, just
+send a ponter to a port strucure instread
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 6b7f40f712344ec8fdca10450834825094e797fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c  | 34 ++++++++++++++++------------------
+ drivers/usb/host/xhci-ring.c |  3 +--
+ drivers/usb/host/xhci.h      |  4 ++--
+ 3 files changed, 19 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 372b4486c52a..e3be8d15c078 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -678,16 +678,16 @@ static int xhci_exit_test_mode(struct xhci_hcd *xhci)
+ 	return xhci_reset(xhci);
+ }
+ 
+-void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+-				int port_id, u32 link_state)
++void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
++			 u32 link_state)
+ {
+ 	u32 temp;
+ 
+-	temp = readl(port_array[port_id]);
++	temp = readl(port->addr);
+ 	temp = xhci_port_state_to_neutral(temp);
+ 	temp &= ~PORT_PLS_MASK;
+ 	temp |= PORT_LINK_STROBE | link_state;
+-	writel(temp, port_array[port_id]);
++	writel(temp, port->addr);
+ }
+ 
+ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
+@@ -932,8 +932,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
+ 
+ 			xhci_test_and_clear_bit(xhci, port_array, wIndex,
+ 						PORT_PLC);
+-			xhci_set_link_state(xhci, port_array, wIndex,
+-					XDEV_U0);
++			xhci_set_link_state(xhci, port, XDEV_U0);
+ 
+ 			spin_unlock_irqrestore(&xhci->lock, flags);
+ 			time_left = wait_for_completion_timeout(
+@@ -1142,7 +1141,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			temp = readl(ports[wIndex]->addr);
+ 			if ((temp & PORT_PLS_MASK) != XDEV_U0) {
+ 				/* Resume the port to U0 first */
+-				xhci_set_link_state(xhci, port_array, wIndex,
++				xhci_set_link_state(xhci, ports[wIndex],
+ 							XDEV_U0);
+ 				spin_unlock_irqrestore(&xhci->lock, flags);
+ 				msleep(10);
+@@ -1170,7 +1169,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			xhci_stop_device(xhci, slot_id, 1);
+ 			spin_lock_irqsave(&xhci->lock, flags);
+ 
+-			xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
++			xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
+ 
+ 			spin_unlock_irqrestore(&xhci->lock, flags);
+ 			msleep(10); /* wait device to enter */
+@@ -1200,8 +1199,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			/* Put link in RxDetect (enable port) */
+ 			if (link_state == USB_SS_PORT_LS_RX_DETECT) {
+ 				xhci_dbg(xhci, "Enable port %d\n", wIndex);
+-				xhci_set_link_state(xhci, port_array, wIndex,
+-						link_state);
++				xhci_set_link_state(xhci, ports[wIndex],
++							link_state);
+ 				temp = readl(ports[wIndex]->addr);
+ 				break;
+ 			}
+@@ -1233,8 +1232,9 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 
+ 				xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
+ 						wIndex);
+-				xhci_set_link_state(xhci, port_array, wIndex,
++				xhci_set_link_state(xhci, ports[wIndex],
+ 						link_state);
++
+ 				temp = readl(ports[wIndex]->addr);
+ 				break;
+ 			}
+@@ -1262,8 +1262,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 				}
+ 			}
+ 
+-			xhci_set_link_state(xhci, port_array, wIndex,
+-						link_state);
++			xhci_set_link_state(xhci, ports[wIndex], link_state);
+ 
+ 			spin_unlock_irqrestore(&xhci->lock, flags);
+ 			msleep(20); /* wait device to enter */
+@@ -1357,12 +1356,12 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 					goto error;
+ 
+ 				set_bit(wIndex, &bus_state->resuming_ports);
+-				xhci_set_link_state(xhci, port_array, wIndex,
+-							XDEV_RESUME);
++				xhci_set_link_state(xhci, ports[wIndex],
++						    XDEV_RESUME);
+ 				spin_unlock_irqrestore(&xhci->lock, flags);
+ 				msleep(USB_RESUME_TIMEOUT);
+ 				spin_lock_irqsave(&xhci->lock, flags);
+-				xhci_set_link_state(xhci, port_array, wIndex,
++				xhci_set_link_state(xhci, ports[wIndex],
+ 							XDEV_U0);
+ 				clear_bit(wIndex, &bus_state->resuming_ports);
+ 			}
+@@ -1676,8 +1675,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 			/* Clear PLC to poll it later for U0 transition */
+ 			xhci_test_and_clear_bit(xhci, port_array, port_index,
+ 						PORT_PLC);
+-			xhci_set_link_state(xhci, port_array, port_index,
+-					    XDEV_U0);
++			xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
+ 		}
+ 	}
+ 
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 31b72133d7a3..6e4211eea0e2 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1591,8 +1591,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 			bus_state->port_remote_wakeup |= 1 << hcd_portnum;
+ 			xhci_test_and_clear_bit(xhci, port_array,
+ 					hcd_portnum, PORT_PLC);
+-			xhci_set_link_state(xhci, port_array, hcd_portnum,
+-						XDEV_U0);
++			xhci_set_link_state(xhci, port, XDEV_U0);
+ 			/* Need to wait until the next link state change
+ 			 * indicates the device is actually in U0.
+ 			 */
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index d90b97ec20a2..11f8f747fe56 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2106,8 +2106,8 @@ void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
+ unsigned int count_trbs(u64 addr, u64 len);
+ 
+ /* xHCI roothub code */
+-void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+-				int port_id, u32 link_state);
++void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
++				u32 link_state);
+ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+ 				int port_id, u32 port_bit);
+ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
+-- 
+2.19.0
+
diff --git a/patches/1448-xhci-change-xhci_test_and_clear_bit-to-use-new-port-.patch b/patches/1448-xhci-change-xhci_test_and_clear_bit-to-use-new-port-.patch
new file mode 100644
index 00000000000000..c78a8be1dc666b
--- /dev/null
+++ b/patches/1448-xhci-change-xhci_test_and_clear_bit-to-use-new-port-.patch
@@ -0,0 +1,171 @@
+From f9d3fd4b193f485563710056d2a6e397ba6472fb Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:40:00 +0300
+Subject: [PATCH 1448/1795] xhci: change xhci_test_and_clear_bit() to use new
+ port structure
+
+Don't use pointers to port array and port index as function parameters
+in xhci_test_and_clear_bit(), just use a pointer to the right port
+structure.
+
+xhci_test_and_clear_bit() was the last port_array user in
+xhci_get_port_status() and handle_port_status(), so remove the
+port_array from them as well.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit eaefcf246b56ec888ccbbb6b39da688166d4d4fb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c  | 22 ++++++++++------------
+ drivers/usb/host/xhci-ring.c | 15 +++------------
+ drivers/usb/host/xhci.h      |  4 ++--
+ 3 files changed, 15 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index e3be8d15c078..05115b81f6bd 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -717,16 +717,16 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
+ }
+ 
+ /* Test and clear port RWC bit */
+-void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+-				int port_id, u32 port_bit)
++void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
++			     u32 port_bit)
+ {
+ 	u32 temp;
+ 
+-	temp = readl(port_array[port_id]);
++	temp = readl(port->addr);
+ 	if (temp & port_bit) {
+ 		temp = xhci_port_state_to_neutral(temp);
+ 		temp |= port_bit;
+-		writel(temp, port_array[port_id]);
++		writel(temp, port->addr);
+ 	}
+ }
+ 
+@@ -846,8 +846,7 @@ static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
+  */
+ static u32 xhci_get_port_status(struct usb_hcd *hcd,
+ 		struct xhci_bus_state *bus_state,
+-		__le32 __iomem **port_array,
+-		u16 wIndex, u32 raw_port_status,
++	u16 wIndex, u32 raw_port_status,
+ 		unsigned long flags)
+ 	__releases(&xhci->lock)
+ 	__acquires(&xhci->lock)
+@@ -930,8 +929,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
+ 
+ 			set_bit(wIndex, &bus_state->rexit_ports);
+ 
+-			xhci_test_and_clear_bit(xhci, port_array, wIndex,
+-						PORT_PLC);
++			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
+ 			xhci_set_link_state(xhci, port, XDEV_U0);
+ 
+ 			spin_unlock_irqrestore(&xhci->lock, flags);
+@@ -1091,8 +1089,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 			break;
+ 		}
+ 		trace_xhci_get_port_status(wIndex, temp);
+-		status = xhci_get_port_status(hcd, bus_state, port_array,
+-				wIndex, temp, flags);
++		status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
++					      flags);
+ 		if (status == 0xffffffff)
+ 			goto error;
+ 
+@@ -1673,7 +1671,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 		for_each_set_bit(port_index, &bus_state->bus_suspended,
+ 				 BITS_PER_LONG) {
+ 			/* Clear PLC to poll it later for U0 transition */
+-			xhci_test_and_clear_bit(xhci, port_array, port_index,
++			xhci_test_and_clear_bit(xhci, ports[port_index],
+ 						PORT_PLC);
+ 			xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
+ 		}
+@@ -1688,7 +1686,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 				  port_index);
+ 			continue;
+ 		}
+-		xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
++		xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
+ 		slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
+ 		if (slot_id)
+ 			xhci_ring_device(xhci, slot_id);
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index 6e4211eea0e2..f0a99aa0ac58 100644
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1527,7 +1527,6 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	int slot_id;
+ 	unsigned int hcd_portnum;
+ 	struct xhci_bus_state *bus_state;
+-	__le32 __iomem **port_array;
+ 	bool bogus_port_status = false;
+ 	struct xhci_port *port;
+ 
+@@ -1555,11 +1554,6 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 
+ 	hcd = port->rhub->hcd;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+-	if (hcd->speed >= HCD_USB3)
+-		port_array = xhci->usb3_ports;
+-	else
+-		port_array = xhci->usb2_ports;
+-
+ 	hcd_portnum = port->hcd_portnum;
+ 	portsc = readl(port->addr);
+ 
+@@ -1589,8 +1583,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 			 * device and host initiated resume.
+ 			 */
+ 			bus_state->port_remote_wakeup |= 1 << hcd_portnum;
+-			xhci_test_and_clear_bit(xhci, port_array,
+-					hcd_portnum, PORT_PLC);
++			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
+ 			xhci_set_link_state(xhci, port, XDEV_U0);
+ 			/* Need to wait until the next link state change
+ 			 * indicates the device is actually in U0.
+@@ -1628,8 +1621,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 			xhci_ring_device(xhci, slot_id);
+ 		if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
+ 			bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
+-			xhci_test_and_clear_bit(xhci, port_array,
+-					hcd_portnum, PORT_PLC);
++			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
+ 			usb_wakeup_notification(hcd->self.root_hub,
+ 					hcd_portnum + 1);
+ 			bogus_port_status = true;
+@@ -1651,8 +1643,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
+ 	}
+ 
+ 	if (hcd->speed < HCD_USB3)
+-		xhci_test_and_clear_bit(xhci, port_array, hcd_portnum,
+-					PORT_PLC);
++		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
+ 
+ cleanup:
+ 	/* Update event ring dequeue pointer before dropping the lock */
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 11f8f747fe56..e195b745a2a7 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -2108,8 +2108,8 @@ unsigned int count_trbs(u64 addr, u64 len);
+ /* xHCI roothub code */
+ void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
+ 				u32 link_state);
+-void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
+-				int port_id, u32 port_bit);
++void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
++				u32 port_bit);
+ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
+ 		char *buf, u16 wLength);
+ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
+-- 
+2.19.0
+
diff --git a/patches/1449-xhci-use-port-structures-instead-of-port-arrays-in-x.patch b/patches/1449-xhci-use-port-structures-instead-of-port-arrays-in-x.patch
new file mode 100644
index 00000000000000..02ceaa281644f6
--- /dev/null
+++ b/patches/1449-xhci-use-port-structures-instead-of-port-arrays-in-x.patch
@@ -0,0 +1,158 @@
+From bdfd8965087554748d0e3de0fe01a61f3f40afd2 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:40:01 +0300
+Subject: [PATCH 1449/1795] xhci: use port structures instead of port arrays in
+ xhci.c functions
+
+get rid of port iomem arrays and use port structures in the following
+functions:
+xhci_find_raw_port_number()
+xhci_disable_port_wake_on_bits()
+xhci_set_usb2_hardware_lpm()
+xhci_all_ports_seen_u0()
+compliance_mode_recovery()
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 38986ffa6a74899be83126d55f043a1c034cba7d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/usb/host/xhci.c
+---
+ drivers/usb/host/xhci.c | 50 ++++++++++++++++++-----------------------
+ 1 file changed, 22 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 7155659bb920..57d6fe654712 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -400,13 +400,15 @@ static void compliance_mode_recovery(unsigned long arg)
+ {
+ 	struct xhci_hcd *xhci;
+ 	struct usb_hcd *hcd;
++	struct xhci_hub *rhub;
+ 	u32 temp;
+ 	int i;
+ 
+ 	xhci = (struct xhci_hcd *)arg;
++	rhub = &xhci->usb3_rhub;
+ 
+-	for (i = 0; i < xhci->num_usb3_ports; i++) {
+-		temp = readl(xhci->usb3_ports[i]);
++	for (i = 0; i < rhub->num_ports; i++) {
++		temp = readl(rhub->ports[i]->addr);
+ 		if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
+ 			/*
+ 			 * Compliance Mode Detected. Letting USB Core
+@@ -426,7 +428,7 @@ static void compliance_mode_recovery(unsigned long arg)
+ 		}
+ 	}
+ 
+-	if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
++	if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
+ 		mod_timer(&xhci->comp_mode_recovery_timer,
+ 			jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
+ }
+@@ -483,7 +485,7 @@ static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
+ 
+ static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
+ {
+-	return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
++	return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
+ }
+ 
+ 
+@@ -812,33 +814,33 @@ static void xhci_clear_command_ring(struct xhci_hcd *xhci)
+ 
+ static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
+ {
++	struct xhci_port **ports;
+ 	int port_index;
+-	__le32 __iomem **port_array;
+ 	unsigned long flags;
+ 	u32 t1, t2;
+ 
+ 	spin_lock_irqsave(&xhci->lock, flags);
+ 
+ 	/* disable usb3 ports Wake bits */
+-	port_index = xhci->num_usb3_ports;
+-	port_array = xhci->usb3_ports;
++	port_index = xhci->usb3_rhub.num_ports;
++	ports = xhci->usb3_rhub.ports;
+ 	while (port_index--) {
+-		t1 = readl(port_array[port_index]);
++		t1 = readl(ports[port_index]->addr);
+ 		t1 = xhci_port_state_to_neutral(t1);
+ 		t2 = t1 & ~PORT_WAKE_BITS;
+ 		if (t1 != t2)
+-			writel(t2, port_array[port_index]);
++			writel(t2, ports[port_index]->addr);
+ 	}
+ 
+ 	/* disable usb2 ports Wake bits */
+-	port_index = xhci->num_usb2_ports;
+-	port_array = xhci->usb2_ports;
++	port_index = xhci->usb2_rhub.num_ports;
++	ports = xhci->usb2_rhub.ports;
+ 	while (port_index--) {
+-		t1 = readl(port_array[port_index]);
++		t1 = readl(ports[port_index]->addr);
+ 		t1 = xhci_port_state_to_neutral(t1);
+ 		t2 = t1 & ~PORT_WAKE_BITS;
+ 		if (t1 != t2)
+-			writel(t2, port_array[port_index]);
++			writel(t2, ports[port_index]->addr);
+ 	}
+ 
+ 	spin_unlock_irqrestore(&xhci->lock, flags);
+@@ -4016,18 +4018,10 @@ static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
+  */
+ int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
+ {
+-	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+-	__le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
+-	__le32 __iomem *addr;
+-	int raw_port;
+-
+-	if (hcd->speed < HCD_USB3)
+-		addr = xhci->usb2_ports[port1 - 1];
+-	else
+-		addr = xhci->usb3_ports[port1 - 1];
++	struct xhci_hub *rhub;
+ 
+-	raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
+-	return raw_port;
++	rhub = xhci_get_rhub(hcd);
++	return rhub->ports[port1 - 1]->hw_portnum + 1;
+ }
+ 
+ /*
+@@ -4160,7 +4154,7 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
+ 			struct usb_device *udev, int enable)
+ {
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+-	__le32 __iomem	**port_array;
++	struct xhci_port **ports;
+ 	__le32 __iomem	*pm_addr, *hlpm_addr;
+ 	u32		pm_val, hlpm_val, field;
+ 	unsigned int	port_num;
+@@ -4181,11 +4175,11 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
+ 
+ 	spin_lock_irqsave(&xhci->lock, flags);
+ 
+-	port_array = xhci->usb2_ports;
++	ports = xhci->usb2_rhub.ports;
+ 	port_num = udev->portnum - 1;
+-	pm_addr = port_array[port_num] + PORTPMSC;
++	pm_addr = ports[port_num]->addr + PORTPMSC;
+ 	pm_val = readl(pm_addr);
+-	hlpm_addr = port_array[port_num] + PORTHLPMC;
++	hlpm_addr = ports[port_num]->addr + PORTHLPMC;
+ 	field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
+ 
+ 	xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
+-- 
+2.19.0
+
diff --git a/patches/1450-xhci-xhci-hub-use-port-structure-members-instead-of-.patch b/patches/1450-xhci-xhci-hub-use-port-structure-members-instead-of-.patch
new file mode 100644
index 00000000000000..50e90f45a56ccc
--- /dev/null
+++ b/patches/1450-xhci-xhci-hub-use-port-structure-members-instead-of-.patch
@@ -0,0 +1,118 @@
+From 64d0a58daf575acf10618040ef6f24aa9fa40f79 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Mon, 21 May 2018 16:40:02 +0300
+Subject: [PATCH 1450/1795] xhci: xhci-hub: use port structure members instead
+ of xhci_get_ports()
+
+xhci_get_ports() is one of the last functions using port_arrays in
+xhci-hub.c. We get the same data directly from hub and port structures
+instead, so convert and remove both xhci_get_ports() and port_arrays from
+all function that no longer need it.
+
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 925f349d4dca1357813efdc37ec08134d79b3288)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-hub.c | 28 ++++------------------------
+ 1 file changed, 4 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
+index 05115b81f6bd..a4b95d019f84 100644
+--- a/drivers/usb/host/xhci-hub.c
++++ b/drivers/usb/host/xhci-hub.c
+@@ -541,22 +541,6 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
+ 			port_change_bit, wIndex, port_status);
+ }
+ 
+-static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
+-{
+-	int max_ports;
+-	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+-
+-	if (hcd->speed >= HCD_USB3) {
+-		max_ports = xhci->num_usb3_ports;
+-		*port_array = xhci->usb3_ports;
+-	} else {
+-		max_ports = xhci->num_usb2_ports;
+-		*port_array = xhci->usb2_ports;
+-	}
+-
+-	return max_ports;
+-}
+-
+ struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
+ {
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+@@ -1032,7 +1016,6 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 	unsigned long flags;
+ 	u32 temp, status;
+ 	int retval = 0;
+-	__le32 __iomem **port_array;
+ 	int slot_id;
+ 	struct xhci_bus_state *bus_state;
+ 	u16 link_state = 0;
+@@ -1044,7 +1027,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ 
+ 	rhub = xhci_get_rhub(hcd);
+ 	ports = rhub->ports;
+-	max_ports = xhci_get_ports(hcd, &port_array);
++	max_ports = rhub->num_ports;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+ 	spin_lock_irqsave(&xhci->lock, flags);
+@@ -1425,7 +1408,6 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+ 	int i, retval;
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+ 	int max_ports;
+-	__le32 __iomem **port_array;
+ 	struct xhci_bus_state *bus_state;
+ 	bool reset_change = false;
+ 	struct xhci_hub *rhub;
+@@ -1433,7 +1415,7 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+ 
+ 	rhub = xhci_get_rhub(hcd);
+ 	ports = rhub->ports;
+-	max_ports = xhci_get_ports(hcd, &port_array);
++	max_ports = rhub->num_ports;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+ 	/* Initial status is no changes */
+@@ -1483,7 +1465,6 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+ {
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+ 	int max_ports, port_index;
+-	__le32 __iomem **port_array;
+ 	struct xhci_bus_state *bus_state;
+ 	unsigned long flags;
+ 	struct xhci_hub *rhub;
+@@ -1491,7 +1472,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
+ 
+ 	rhub = xhci_get_rhub(hcd);
+ 	ports = rhub->ports;
+-	max_ports = xhci_get_ports(hcd, &port_array);
++	max_ports = rhub->num_ports;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+ 	spin_lock_irqsave(&xhci->lock, flags);
+@@ -1592,7 +1573,6 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ {
+ 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+ 	struct xhci_bus_state *bus_state;
+-	__le32 __iomem **port_array;
+ 	unsigned long flags;
+ 	int max_ports, port_index;
+ 	int slot_id;
+@@ -1604,7 +1584,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
+ 
+ 	rhub = xhci_get_rhub(hcd);
+ 	ports = rhub->ports;
+-	max_ports = xhci_get_ports(hcd, &port_array);
++	max_ports = rhub->num_ports;
+ 	bus_state = &xhci->bus_state[hcd_index(hcd)];
+ 
+ 	if (time_before(jiffies, bus_state->next_statechange))
+-- 
+2.19.0
+
diff --git a/patches/1451-usb-xhci-force-all-memory-allocations-to-node.patch b/patches/1451-usb-xhci-force-all-memory-allocations-to-node.patch
new file mode 100644
index 00000000000000..e68d926f0b7809
--- /dev/null
+++ b/patches/1451-usb-xhci-force-all-memory-allocations-to-node.patch
@@ -0,0 +1,233 @@
+From ce1cb998d0fa43dbb80cf18453358a756b8fb46e Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 12 Jul 2018 09:59:57 +0200
+Subject: [PATCH 1451/1795] usb: xhci: force all memory allocations to node
+
+The xhci driver forces DMA memory to be node aware, however, there are
+several ring-related memory allocations that are not memory node aware.
+This patch resolves those *alloc functions to be allocated on the proper
+memory node.
+
+Signed-off-by: Adam Wallis <awallis@codeaurora.org>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit a965315e59f3cbceb5d27d0feb68a456544f0f8d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/host/xhci-mem.c
+---
+ drivers/usb/host/xhci-mem.c | 60 ++++++++++++++++++++++++-------------
+ 1 file changed, 40 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 76ec1cfb746b..08a1a67ae9a7 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -33,8 +33,9 @@ static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
+ 	struct xhci_segment *seg;
+ 	dma_addr_t	dma;
+ 	int		i;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+-	seg = kzalloc(sizeof *seg, flags);
++	seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
+ 	if (!seg)
+ 		return NULL;
+ 
+@@ -45,7 +46,8 @@ static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
+ 	}
+ 
+ 	if (max_packet) {
+-		seg->bounce_buf = kzalloc(max_packet, flags);
++		seg->bounce_buf = kzalloc_node(max_packet, flags,
++					dev_to_node(dev));
+ 		if (!seg->bounce_buf) {
+ 			dma_pool_free(xhci->segment_pool, seg->trbs, dma);
+ 			kfree(seg);
+@@ -363,8 +365,9 @@ struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
+ {
+ 	struct xhci_ring	*ring;
+ 	int ret;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+-	ring = kzalloc(sizeof *(ring), flags);
++	ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
+ 	if (!ring)
+ 		return NULL;
+ 
+@@ -458,11 +461,12 @@ struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
+ 						    int type, gfp_t flags)
+ {
+ 	struct xhci_container_ctx *ctx;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
+ 		return NULL;
+ 
+-	ctx = kzalloc(sizeof(*ctx), flags);
++	ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
+ 	if (!ctx)
+ 		return NULL;
+ 
+@@ -615,6 +619,7 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ 	struct xhci_ring *cur_ring;
+ 	u64 addr;
+ 	int ret;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	xhci_dbg(xhci, "Allocating %u streams and %u "
+ 			"stream context array entries.\n",
+@@ -625,7 +630,8 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ 	}
+ 	xhci->cmd_ring_reserved_trbs++;
+ 
+-	stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
++	stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
++			dev_to_node(dev));
+ 	if (!stream_info)
+ 		goto cleanup_trbs;
+ 
+@@ -633,9 +639,9 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
+ 	stream_info->num_stream_ctxs = num_stream_ctxs;
+ 
+ 	/* Initialize the array of virtual pointers to stream rings. */
+-	stream_info->stream_rings = kzalloc(
+-			sizeof(struct xhci_ring *)*num_streams,
+-			mem_flags);
++	stream_info->stream_rings = kcalloc_node(
++			num_streams, sizeof(struct xhci_ring *), mem_flags,
++			dev_to_node(dev));
+ 	if (!stream_info->stream_rings)
+ 		goto cleanup_info;
+ 
+@@ -831,6 +837,7 @@ int xhci_alloc_tt_info(struct xhci_hcd *xhci,
+ 	struct xhci_tt_bw_info		*tt_info;
+ 	unsigned int			num_ports;
+ 	int				i, j;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	if (!tt->multi)
+ 		num_ports = 1;
+@@ -840,7 +847,8 @@ int xhci_alloc_tt_info(struct xhci_hcd *xhci,
+ 	for (i = 0; i < num_ports; i++, tt_info++) {
+ 		struct xhci_interval_bw_table *bw_table;
+ 
+-		tt_info = kzalloc(sizeof(*tt_info), mem_flags);
++		tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
++				dev_to_node(dev));
+ 		if (!tt_info)
+ 			goto free_tts;
+ 		INIT_LIST_HEAD(&tt_info->tt_list);
+@@ -1642,7 +1650,8 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
+ 	if (!num_sp)
+ 		return 0;
+ 
+-	xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
++	xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
++				dev_to_node(dev));
+ 	if (!xhci->scratchpad)
+ 		goto fail_sp;
+ 
+@@ -1652,7 +1661,8 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
+ 	if (!xhci->scratchpad->sp_array)
+ 		goto fail_sp2;
+ 
+-	xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
++	xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
++					flags, dev_to_node(dev));
+ 	if (!xhci->scratchpad->sp_buffers)
+ 		goto fail_sp3;
+ 
+@@ -1720,14 +1730,16 @@ struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
+ 		bool allocate_completion, gfp_t mem_flags)
+ {
+ 	struct xhci_command *command;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+-	command = kzalloc(sizeof(*command), mem_flags);
++	command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
+ 	if (!command)
+ 		return NULL;
+ 
+ 	if (allocate_completion) {
+ 		command->completion =
+-			kzalloc(sizeof(struct completion), mem_flags);
++			kzalloc_node(sizeof(struct completion), mem_flags,
++				dev_to_node(dev));
+ 		if (!command->completion) {
+ 			kfree(command);
+ 			return NULL;
+@@ -2108,6 +2120,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
+ 	int i;
+ 	u8 major_revision, minor_revision;
+ 	struct xhci_hub *rhub;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	temp = readl(addr);
+ 	major_revision = XHCI_EXT_PORT_MAJOR(temp);
+@@ -2144,8 +2157,8 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
+ 
+ 	rhub->psi_count = XHCI_EXT_PORT_PSIC(temp);
+ 	if (rhub->psi_count) {
+-		rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi),
+-				    GFP_KERNEL);
++		rhub->psi = kcalloc_node(rhub->psi_count, sizeof(*rhub->psi),
++				    GFP_KERNEL, dev_to_node(dev));
+ 		if (!rhub->psi)
+ 			rhub->psi_count = 0;
+ 
+@@ -2238,10 +2251,12 @@ static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
+ {
+ 	int port_index = 0;
+ 	int i;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	if (!rhub->num_ports)
+ 		return;
+-	rhub->ports = kcalloc(rhub->num_ports, sizeof(rhub->ports), flags);
++	rhub->ports = kcalloc_node(rhub->num_ports, sizeof(rhub->ports), flags,
++			dev_to_node(dev));
+ 	for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
+ 		if (xhci->hw_ports[i].rhub != rhub ||
+ 		    xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
+@@ -2269,10 +2284,13 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 	int i, j, port_index;
+ 	int cap_count = 0;
+ 	u32 cap_start;
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
+ 
+ 	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
+-	xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
+-	xhci->hw_ports = kcalloc(num_ports, sizeof(*xhci->hw_ports), flags);
++	xhci->port_array = kzalloc_node(sizeof(*xhci->port_array)*num_ports,
++					flags, dev_to_node(dev));
++	xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
++				flags, dev_to_node(dev));
+ 	if (!xhci->port_array)
+ 		return -ENOMEM;
+ 
+@@ -2282,7 +2300,8 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 		xhci->hw_ports[i].hw_portnum = i;
+ 	}
+ 
+-	xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
++	xhci->rh_bw = kzalloc_node(sizeof(*xhci->rh_bw)*num_ports, flags,
++			dev_to_node(dev));
+ 	if (!xhci->rh_bw)
+ 		return -ENOMEM;
+ 	for (i = 0; i < num_ports; i++) {
+@@ -2309,7 +2328,8 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
+ 						      XHCI_EXT_CAPS_PROTOCOL);
+ 	}
+ 
+-	xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
++	xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps),
++				flags, dev_to_node(dev));
+ 	if (!xhci->ext_caps)
+ 		return -ENOMEM;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1452-xhci-Allow-more-than-32-quirks.patch b/patches/1452-xhci-Allow-more-than-32-quirks.patch
new file mode 100644
index 00000000000000..0662dccbcf516f
--- /dev/null
+++ b/patches/1452-xhci-Allow-more-than-32-quirks.patch
@@ -0,0 +1,140 @@
+From 8a58d139b3646032b301487d2d743e9b693c5152 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Wed, 23 May 2018 18:41:36 +0100
+Subject: [PATCH 1452/1795] xhci: Allow more than 32 quirks
+
+We now have 32 different quirks, and the field that holds them
+is full. Let's bump it up to the next stage so that we can handle
+some more... The type is now an unsigned long long, which is 64bit
+on most architectures.
+
+We take this opportunity to change the quirks from using (1 << x)
+to BIT_ULL(x).
+
+Tested-by: Domenico Andreoli <domenico.andreoli@linux.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Tested-by: Faiz Abbas <faiz_abbas@ti.com>
+Tested-by: Domenico Andreoli <domenico.andreoli@linux.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 36b6857932f380fcb55c31ac75857e3e81dd583a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c |  6 ++--
+ drivers/usb/host/xhci.h | 66 ++++++++++++++++++++---------------------
+ 2 files changed, 36 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 57d6fe654712..eb16066906a6 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -33,8 +33,8 @@ static int link_quirk;
+ module_param(link_quirk, int, S_IRUGO | S_IWUSR);
+ MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
+ 
+-static unsigned int quirks;
+-module_param(quirks, uint, S_IRUGO);
++static unsigned long long quirks;
++module_param(quirks, ullong, S_IRUGO);
+ MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
+ 
+ /* TODO: copied from ehci-hcd.c - can this be refactored? */
+@@ -4999,7 +4999,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 		return retval;
+ 	xhci_dbg(xhci, "Called HCD init\n");
+ 
+-	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
++	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
+ 		  xhci->hcc_params, xhci->hci_version, xhci->quirks);
+ 
+ 	return 0;
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index e195b745a2a7..d985210dda2d 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1801,12 +1801,12 @@ struct xhci_hcd {
+ #define XHCI_STATE_DYING	(1 << 0)
+ #define XHCI_STATE_HALTED	(1 << 1)
+ #define XHCI_STATE_REMOVING	(1 << 2)
+-	unsigned int		quirks;
+-#define	XHCI_LINK_TRB_QUIRK	(1 << 0)
+-#define XHCI_RESET_EP_QUIRK	(1 << 1)
+-#define XHCI_NEC_HOST		(1 << 2)
+-#define XHCI_AMD_PLL_FIX	(1 << 3)
+-#define XHCI_SPURIOUS_SUCCESS	(1 << 4)
++	unsigned long long	quirks;
++#define	XHCI_LINK_TRB_QUIRK	BIT_ULL(0)
++#define XHCI_RESET_EP_QUIRK	BIT_ULL(1)
++#define XHCI_NEC_HOST		BIT_ULL(2)
++#define XHCI_AMD_PLL_FIX	BIT_ULL(3)
++#define XHCI_SPURIOUS_SUCCESS	BIT_ULL(4)
+ /*
+  * Certain Intel host controllers have a limit to the number of endpoint
+  * contexts they can handle.  Ideally, they would signal that they can't handle
+@@ -1816,35 +1816,35 @@ struct xhci_hcd {
+  * commands, reset device commands, disable slot commands, and address device
+  * commands.
+  */
+-#define XHCI_EP_LIMIT_QUIRK	(1 << 5)
+-#define XHCI_BROKEN_MSI		(1 << 6)
+-#define XHCI_RESET_ON_RESUME	(1 << 7)
+-#define	XHCI_SW_BW_CHECKING	(1 << 8)
+-#define XHCI_AMD_0x96_HOST	(1 << 9)
+-#define XHCI_TRUST_TX_LENGTH	(1 << 10)
+-#define XHCI_LPM_SUPPORT	(1 << 11)
+-#define XHCI_INTEL_HOST		(1 << 12)
+-#define XHCI_SPURIOUS_REBOOT	(1 << 13)
+-#define XHCI_COMP_MODE_QUIRK	(1 << 14)
+-#define XHCI_AVOID_BEI		(1 << 15)
+-#define XHCI_PLAT		(1 << 16)
+-#define XHCI_SLOW_SUSPEND	(1 << 17)
+-#define XHCI_SPURIOUS_WAKEUP	(1 << 18)
++#define XHCI_EP_LIMIT_QUIRK	BIT_ULL(5)
++#define XHCI_BROKEN_MSI		BIT_ULL(6)
++#define XHCI_RESET_ON_RESUME	BIT_ULL(7)
++#define	XHCI_SW_BW_CHECKING	BIT_ULL(8)
++#define XHCI_AMD_0x96_HOST	BIT_ULL(9)
++#define XHCI_TRUST_TX_LENGTH	BIT_ULL(10)
++#define XHCI_LPM_SUPPORT	BIT_ULL(11)
++#define XHCI_INTEL_HOST		BIT_ULL(12)
++#define XHCI_SPURIOUS_REBOOT	BIT_ULL(13)
++#define XHCI_COMP_MODE_QUIRK	BIT_ULL(14)
++#define XHCI_AVOID_BEI		BIT_ULL(15)
++#define XHCI_PLAT		BIT_ULL(16)
++#define XHCI_SLOW_SUSPEND	BIT_ULL(17)
++#define XHCI_SPURIOUS_WAKEUP	BIT_ULL(18)
+ /* For controllers with a broken beyond repair streams implementation */
+-#define XHCI_BROKEN_STREAMS	(1 << 19)
+-#define XHCI_PME_STUCK_QUIRK	(1 << 20)
+-#define XHCI_MTK_HOST		(1 << 21)
+-#define XHCI_SSIC_PORT_UNUSED	(1 << 22)
+-#define XHCI_NO_64BIT_SUPPORT	(1 << 23)
+-#define XHCI_MISSING_CAS	(1 << 24)
++#define XHCI_BROKEN_STREAMS	BIT_ULL(19)
++#define XHCI_PME_STUCK_QUIRK	BIT_ULL(20)
++#define XHCI_MTK_HOST		BIT_ULL(21)
++#define XHCI_SSIC_PORT_UNUSED	BIT_ULL(22)
++#define XHCI_NO_64BIT_SUPPORT	BIT_ULL(23)
++#define XHCI_MISSING_CAS	BIT_ULL(24)
+ /* For controller with a broken Port Disable implementation */
+-#define XHCI_BROKEN_PORT_PED	(1 << 25)
+-#define XHCI_LIMIT_ENDPOINT_INTERVAL_7	(1 << 26)
+-#define XHCI_U2_DISABLE_WAKE	(1 << 27)
+-#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL	(1 << 28)
+-#define XHCI_HW_LPM_DISABLE	(1 << 29)
+-#define XHCI_SUSPEND_DELAY	(1 << 30)
+-#define XHCI_INTEL_USB_ROLE_SW	(1 << 31)
++#define XHCI_BROKEN_PORT_PED	BIT_ULL(25)
++#define XHCI_LIMIT_ENDPOINT_INTERVAL_7	BIT_ULL(26)
++#define XHCI_U2_DISABLE_WAKE	BIT_ULL(27)
++#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL	BIT_ULL(28)
++#define XHCI_HW_LPM_DISABLE	BIT_ULL(29)
++#define XHCI_SUSPEND_DELAY	BIT_ULL(30)
++#define XHCI_INTEL_USB_ROLE_SW	BIT_ULL(31)
+ 
+ 	unsigned int		num_active_eps;
+ 	unsigned int		limit_active_eps;
+-- 
+2.19.0
+
diff --git a/patches/1453-xhci-Add-quirk-to-zero-64bit-registers-on-Renesas-PC.patch b/patches/1453-xhci-Add-quirk-to-zero-64bit-registers-on-Renesas-PC.patch
new file mode 100644
index 00000000000000..42b300dd039cd7
--- /dev/null
+++ b/patches/1453-xhci-Add-quirk-to-zero-64bit-registers-on-Renesas-PC.patch
@@ -0,0 +1,165 @@
+From 2a609f9fa4c30be3bf31fe594f509995c6ee20af Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Wed, 23 May 2018 18:41:37 +0100
+Subject: [PATCH 1453/1795] xhci: Add quirk to zero 64bit registers on Renesas
+ PCIe controllers
+
+Some Renesas controllers get into a weird state if they are reset while
+programmed with 64bit addresses (they will preserve the top half of the
+address in internal, non visible registers).
+
+You end up with half the address coming from the kernel, and the other
+half coming from the firmware.
+
+Also, changing the programming leads to extra accesses even if the
+controller is supposed to be halted. The controller ends up with a fatal
+fault, and is then ripe for being properly reset. On the flip side,
+this is completely unsafe if the defvice isn't behind an IOMMU, so
+we have to make sure that this is the case. Can you say "broken"?
+
+This is an alternative method to the one introduced in 8466489ef5ba
+("xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue"),
+which will subsequently be removed.
+
+Tested-by: Domenico Andreoli <domenico.andreoli@linux.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Tested-by: Faiz Abbas <faiz_abbas@ti.com>
+Tested-by: Domenico Andreoli <domenico.andreoli@linux.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 12de0a35c996c3a75d050bff748815db3432849c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci-pci.c |  8 +++--
+ drivers/usb/host/xhci.c     | 65 +++++++++++++++++++++++++++++++++++++
+ drivers/usb/host/xhci.h     |  1 +
+ 3 files changed, 72 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index 85ffda85f8ab..e0a0a12871e2 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -196,11 +196,15 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
+ 		xhci->quirks |= XHCI_BROKEN_STREAMS;
+ 	}
+ 	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
+-			pdev->device == 0x0014)
++	    pdev->device == 0x0014) {
+ 		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
++		xhci->quirks |= XHCI_ZERO_64B_REGS;
++	}
+ 	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
+-			pdev->device == 0x0015)
++	    pdev->device == 0x0015) {
+ 		xhci->quirks |= XHCI_RESET_ON_RESUME;
++		xhci->quirks |= XHCI_ZERO_64B_REGS;
++	}
+ 	if (pdev->vendor == PCI_VENDOR_ID_VIA)
+ 		xhci->quirks |= XHCI_RESET_ON_RESUME;
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index eb16066906a6..0b41acd84137 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -209,6 +209,68 @@ int xhci_reset(struct xhci_hcd *xhci)
+ 	return ret;
+ }
+ 
++static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
++{
++	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
++	int err, i;
++	u64 val;
++
++	/*
++	 * Some Renesas controllers get into a weird state if they are
++	 * reset while programmed with 64bit addresses (they will preserve
++	 * the top half of the address in internal, non visible
++	 * registers). You end up with half the address coming from the
++	 * kernel, and the other half coming from the firmware. Also,
++	 * changing the programming leads to extra accesses even if the
++	 * controller is supposed to be halted. The controller ends up with
++	 * a fatal fault, and is then ripe for being properly reset.
++	 *
++	 * Special care is taken to only apply this if the device is behind
++	 * an iommu. Doing anything when there is no iommu is definitely
++	 * unsafe...
++	 */
++	if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !dev->iommu_group)
++		return;
++
++	xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
++
++	/* Clear HSEIE so that faults do not get signaled */
++	val = readl(&xhci->op_regs->command);
++	val &= ~CMD_HSEIE;
++	writel(val, &xhci->op_regs->command);
++
++	/* Clear HSE (aka FATAL) */
++	val = readl(&xhci->op_regs->status);
++	val |= STS_FATAL;
++	writel(val, &xhci->op_regs->status);
++
++	/* Now zero the registers, and brace for impact */
++	val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
++	if (upper_32_bits(val))
++		xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
++	val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
++	if (upper_32_bits(val))
++		xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
++
++	for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
++		struct xhci_intr_reg __iomem *ir;
++
++		ir = &xhci->run_regs->ir_set[i];
++		val = xhci_read_64(xhci, &ir->erst_base);
++		if (upper_32_bits(val))
++			xhci_write_64(xhci, 0, &ir->erst_base);
++		val= xhci_read_64(xhci, &ir->erst_dequeue);
++		if (upper_32_bits(val))
++			xhci_write_64(xhci, 0, &ir->erst_dequeue);
++	}
++
++	/* Wait for the fault to appear. It will be cleared on reset */
++	err = xhci_handshake(&xhci->op_regs->status,
++			     STS_FATAL, STS_FATAL,
++			     XHCI_MAX_HALT_USEC);
++	if (!err)
++		xhci_info(xhci, "Fault detected\n");
++}
+ 
+ #ifdef CONFIG_USB_PCI
+ /*
+@@ -1046,6 +1108,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
+ 
+ 		xhci_dbg(xhci, "Stop HCD\n");
+ 		xhci_halt(xhci);
++		xhci_zero_64b_regs(xhci);
+ 		xhci_reset(xhci);
+ 		spin_unlock_irq(&xhci->lock);
+ 		xhci_cleanup_msix(xhci);
+@@ -4957,6 +5020,8 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 	if (retval)
+ 		return retval;
+ 
++	xhci_zero_64b_regs(xhci);
++
+ 	xhci_dbg(xhci, "Resetting HCD\n");
+ 	/* Reset the internal HC memory state and registers. */
+ 	retval = xhci_reset(xhci);
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index d985210dda2d..ccf372e58521 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1845,6 +1845,7 @@ struct xhci_hcd {
+ #define XHCI_HW_LPM_DISABLE	BIT_ULL(29)
+ #define XHCI_SUSPEND_DELAY	BIT_ULL(30)
+ #define XHCI_INTEL_USB_ROLE_SW	BIT_ULL(31)
++#define XHCI_ZERO_64B_REGS	BIT_ULL(32)
+ 
+ 	unsigned int		num_active_eps;
+ 	unsigned int		limit_active_eps;
+-- 
+2.19.0
+
diff --git a/patches/1454-xhci-Fix-perceived-dead-host-due-to-runtime-suspend-.patch b/patches/1454-xhci-Fix-perceived-dead-host-due-to-runtime-suspend-.patch
new file mode 100644
index 00000000000000..8ff55f9b43d322
--- /dev/null
+++ b/patches/1454-xhci-Fix-perceived-dead-host-due-to-runtime-suspend-.patch
@@ -0,0 +1,96 @@
+From a8a2528d03669310db2ea91c596377cc4daadeaf Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Thu, 21 Jun 2018 16:19:41 +0300
+Subject: [PATCH 1454/1795] xhci: Fix perceived dead host due to runtime
+ suspend race with event handler
+
+Don't rely on event interrupt (EINT) bit alone to detect pending port
+change in resume. If no change event is detected the host may be suspended
+again, oterwise roothubs are resumed.
+
+There is a lag in xHC setting EINT. If we don't notice the pending change
+in resume, and the controller is runtime suspeded again, it causes the
+event handler to assume host is dead as it will fail to read xHC registers
+once PCI puts the controller to D3 state.
+
+[  268.520969] xhci_hcd: xhci_resume: starting port polling.
+[  268.520985] xhci_hcd: xhci_hub_status_data: stopping port polling.
+[  268.521030] xhci_hcd: xhci_suspend: stopping port polling.
+[  268.521040] xhci_hcd: // Setting command ring address to 0x349bd001
+[  268.521139] xhci_hcd: Port Status Change Event for port 3
+[  268.521149] xhci_hcd: resume root hub
+[  268.521163] xhci_hcd: port resume event for port 3
+[  268.521168] xhci_hcd: xHC is not running.
+[  268.521174] xhci_hcd: handle_port_status: starting port polling.
+[  268.596322] xhci_hcd: xhci_hc_died: xHCI host controller not responding, assume dead
+
+The EINT lag is described in a additional note in xhci specs 4.19.2:
+
+"Due to internal xHC scheduling and system delays, there will be a lag
+between a change bit being set and the Port Status Change Event that it
+generated being written to the Event Ring. If SW reads the PORTSC and
+sees a change bit set, there is no guarantee that the corresponding Port
+Status Change Event has already been written into the Event Ring."
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 229bc19fd7aca4f37964af06e3583c1c8f36b5d6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/host/xhci.c
+---
+ drivers/usb/host/xhci.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 0b41acd84137..f4e3db0826ef 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -910,7 +910,7 @@ static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
+ 
+ static bool xhci_pending_portevent(struct xhci_hcd *xhci)
+ {
+-	__le32 __iomem		**port_array;
++	struct xhci_port	**ports;
+ 	int			port_index;
+ 	u32			status;
+ 	u32			portsc;
+@@ -924,18 +924,18 @@ static bool xhci_pending_portevent(struct xhci_hcd *xhci)
+ 	 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
+ 	 */
+ 
+-	port_index = xhci->num_usb2_ports;
+-	port_array = xhci->usb2_ports;
++	port_index = xhci->usb2_rhub.num_ports;
++	ports = xhci->usb2_rhub.ports;
+ 	while (port_index--) {
+-		portsc = readl(port_array[port_index]);
++		portsc = readl(ports[port_index]->addr);
+ 		if (portsc & PORT_CHANGE_MASK ||
+ 		    (portsc & PORT_PLS_MASK) == XDEV_RESUME)
+ 			return true;
+ 	}
+-	port_index = xhci->num_usb3_ports;
+-	port_array = xhci->usb3_ports;
++	port_index = xhci->usb3_rhub.num_ports;
++	ports = xhci->usb3_rhub.ports;
+ 	while (port_index--) {
+-		portsc = readl(port_array[port_index]);
++		portsc = readl(ports[port_index]->addr);
+ 		if (portsc & PORT_CHANGE_MASK ||
+ 		    (portsc & PORT_PLS_MASK) == XDEV_RESUME)
+ 			return true;
+@@ -3724,7 +3724,6 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+ 		virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
+ 		del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
+ 	}
+-
+ 	xhci_debugfs_remove_slot(xhci, udev->slot_id);
+ 	virt_dev->udev = NULL;
+ 	ret = xhci_disable_slot(xhci, udev->slot_id);
+-- 
+2.19.0
+
diff --git a/patches/1455-drm-shmobile-remove-unused-MERAM-support.patch b/patches/1455-drm-shmobile-remove-unused-MERAM-support.patch
new file mode 100644
index 00000000000000..adadb6c803aa47
--- /dev/null
+++ b/patches/1455-drm-shmobile-remove-unused-MERAM-support.patch
@@ -0,0 +1,292 @@
+From 333c23b1a2d1a8b1a1f6a827be72773d552d5a75 Mon Sep 17 00:00:00 2001
+From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+Date: Mon, 14 May 2018 15:47:30 +0200
+Subject: [PATCH 1455/1795] drm: shmobile: remove unused MERAM support
+
+Since commit a521422ea4ae  ("ARM: shmobile: mackerel: Remove Legacy C
+board code") MERAM functionality is unused. Remove it.
+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Daniel Vetter <daniel@ffwll.ch>
+Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+(cherry picked from commit e7deb3c7741eaa558458696e55f57141886fcc5c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpu/drm/shmobile/Kconfig           |  1 -
+ drivers/gpu/drm/shmobile/shmob_drm_crtc.c  | 42 ----------------------
+ drivers/gpu/drm/shmobile/shmob_drm_crtc.h  |  1 -
+ drivers/gpu/drm/shmobile/shmob_drm_drv.h   |  2 --
+ drivers/gpu/drm/shmobile/shmob_drm_kms.c   | 11 ------
+ drivers/gpu/drm/shmobile/shmob_drm_kms.h   |  1 -
+ drivers/gpu/drm/shmobile/shmob_drm_plane.c |  2 --
+ include/linux/platform_data/shmob_drm.h    |  4 ---
+ 8 files changed, 64 deletions(-)
+
+diff --git a/drivers/gpu/drm/shmobile/Kconfig b/drivers/gpu/drm/shmobile/Kconfig
+index c987c826daa3..0426d66660d1 100644
+--- a/drivers/gpu/drm/shmobile/Kconfig
++++ b/drivers/gpu/drm/shmobile/Kconfig
+@@ -2,7 +2,6 @@ config DRM_SHMOBILE
+ 	tristate "DRM Support for SH Mobile"
+ 	depends on DRM && ARM
+ 	depends on ARCH_SHMOBILE || COMPILE_TEST
+-	depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM
+ 	select BACKLIGHT_CLASS_DEVICE
+ 	select BACKLIGHT_LCD_SUPPORT
+ 	select DRM_KMS_HELPER
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
+index e7738939a86d..40df8887fc17 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
++++ b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
+@@ -21,8 +21,6 @@
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_plane_helper.h>
+ 
+-#include <video/sh_mobile_meram.h>
+-
+ #include "shmob_drm_backlight.h"
+ #include "shmob_drm_crtc.h"
+ #include "shmob_drm_drv.h"
+@@ -47,20 +45,12 @@ static int shmob_drm_clk_on(struct shmob_drm_device *sdev)
+ 		if (ret < 0)
+ 			return ret;
+ 	}
+-#if 0
+-	if (sdev->meram_dev && sdev->meram_dev->pdev)
+-		pm_runtime_get_sync(&sdev->meram_dev->pdev->dev);
+-#endif
+ 
+ 	return 0;
+ }
+ 
+ static void shmob_drm_clk_off(struct shmob_drm_device *sdev)
+ {
+-#if 0
+-	if (sdev->meram_dev && sdev->meram_dev->pdev)
+-		pm_runtime_put_sync(&sdev->meram_dev->pdev->dev);
+-#endif
+ 	if (sdev->clock)
+ 		clk_disable_unprepare(sdev->clock);
+ }
+@@ -269,12 +259,6 @@ static void shmob_drm_crtc_stop(struct shmob_drm_crtc *scrtc)
+ 	if (!scrtc->started)
+ 		return;
+ 
+-	/* Disable the MERAM cache. */
+-	if (scrtc->cache) {
+-		sh_mobile_meram_cache_free(sdev->meram, scrtc->cache);
+-		scrtc->cache = NULL;
+-	}
+-
+ 	/* Stop the LCDC. */
+ 	shmob_drm_crtc_start_stop(scrtc, false);
+ 
+@@ -305,7 +289,6 @@ static void shmob_drm_crtc_compute_base(struct shmob_drm_crtc *scrtc,
+ {
+ 	struct drm_crtc *crtc = &scrtc->crtc;
+ 	struct drm_framebuffer *fb = crtc->primary->fb;
+-	struct shmob_drm_device *sdev = crtc->dev->dev_private;
+ 	struct drm_gem_cma_object *gem;
+ 	unsigned int bpp;
+ 
+@@ -321,11 +304,6 @@ static void shmob_drm_crtc_compute_base(struct shmob_drm_crtc *scrtc,
+ 			      + y / (bpp == 4 ? 2 : 1) * fb->pitches[1]
+ 			      + x * (bpp == 16 ? 2 : 1);
+ 	}
+-
+-	if (scrtc->cache)
+-		sh_mobile_meram_cache_update(sdev->meram, scrtc->cache,
+-					     scrtc->dma[0], scrtc->dma[1],
+-					     &scrtc->dma[0], &scrtc->dma[1]);
+ }
+ 
+ static void shmob_drm_crtc_update_base(struct shmob_drm_crtc *scrtc)
+@@ -372,9 +350,7 @@ static int shmob_drm_crtc_mode_set(struct drm_crtc *crtc,
+ {
+ 	struct shmob_drm_crtc *scrtc = to_shmob_crtc(crtc);
+ 	struct shmob_drm_device *sdev = crtc->dev->dev_private;
+-	const struct sh_mobile_meram_cfg *mdata = sdev->pdata->meram;
+ 	const struct shmob_drm_format_info *format;
+-	void *cache;
+ 
+ 	format = shmob_drm_format_info(crtc->primary->fb->format->format);
+ 	if (format == NULL) {
+@@ -386,24 +362,6 @@ static int shmob_drm_crtc_mode_set(struct drm_crtc *crtc,
+ 	scrtc->format = format;
+ 	scrtc->line_size = crtc->primary->fb->pitches[0];
+ 
+-	if (sdev->meram) {
+-		/* Enable MERAM cache if configured. We need to de-init
+-		 * configured ICBs before we can re-initialize them.
+-		 */
+-		if (scrtc->cache) {
+-			sh_mobile_meram_cache_free(sdev->meram, scrtc->cache);
+-			scrtc->cache = NULL;
+-		}
+-
+-		cache = sh_mobile_meram_cache_alloc(sdev->meram, mdata,
+-						    crtc->primary->fb->pitches[0],
+-						    adjusted_mode->vdisplay,
+-						    format->meram,
+-						    &scrtc->line_size);
+-		if (!IS_ERR(cache))
+-			scrtc->cache = cache;
+-	}
+-
+ 	shmob_drm_crtc_compute_base(scrtc, x, y);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.h b/drivers/gpu/drm/shmobile/shmob_drm_crtc.h
+index f152973df11c..c11f421737dc 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_crtc.h
++++ b/drivers/gpu/drm/shmobile/shmob_drm_crtc.h
+@@ -28,7 +28,6 @@ struct shmob_drm_crtc {
+ 	int dpms;
+ 
+ 	const struct shmob_drm_format_info *format;
+-	void *cache;
+ 	unsigned long dma[2];
+ 	unsigned int line_size;
+ 	bool started;
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.h b/drivers/gpu/drm/shmobile/shmob_drm_drv.h
+index 02ea315ba69a..088a6e55fa29 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_drv.h
++++ b/drivers/gpu/drm/shmobile/shmob_drm_drv.h
+@@ -23,7 +23,6 @@
+ struct clk;
+ struct device;
+ struct drm_device;
+-struct sh_mobile_meram_info;
+ 
+ struct shmob_drm_device {
+ 	struct device *dev;
+@@ -31,7 +30,6 @@ struct shmob_drm_device {
+ 
+ 	void __iomem *mmio;
+ 	struct clk *clock;
+-	struct sh_mobile_meram_info *meram;
+ 	u32 lddckr;
+ 	u32 ldmt1r;
+ 
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_kms.c b/drivers/gpu/drm/shmobile/shmob_drm_kms.c
+index 388a0fc13564..41cafeb4f7b3 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_kms.c
++++ b/drivers/gpu/drm/shmobile/shmob_drm_kms.c
+@@ -17,8 +17,6 @@
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
+ 
+-#include <video/sh_mobile_meram.h>
+-
+ #include "shmob_drm_crtc.h"
+ #include "shmob_drm_drv.h"
+ #include "shmob_drm_kms.h"
+@@ -34,55 +32,46 @@ static const struct shmob_drm_format_info shmob_drm_format_infos[] = {
+ 		.bpp = 16,
+ 		.yuv = false,
+ 		.lddfr = LDDFR_PKF_RGB16,
+-		.meram = SH_MOBILE_MERAM_PF_RGB,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_RGB888,
+ 		.bpp = 24,
+ 		.yuv = false,
+ 		.lddfr = LDDFR_PKF_RGB24,
+-		.meram = SH_MOBILE_MERAM_PF_RGB,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_ARGB8888,
+ 		.bpp = 32,
+ 		.yuv = false,
+ 		.lddfr = LDDFR_PKF_ARGB32,
+-		.meram = SH_MOBILE_MERAM_PF_RGB,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV12,
+ 		.bpp = 12,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_420,
+-		.meram = SH_MOBILE_MERAM_PF_NV,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV21,
+ 		.bpp = 12,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_420,
+-		.meram = SH_MOBILE_MERAM_PF_NV,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV16,
+ 		.bpp = 16,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_422,
+-		.meram = SH_MOBILE_MERAM_PF_NV,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV61,
+ 		.bpp = 16,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_422,
+-		.meram = SH_MOBILE_MERAM_PF_NV,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV24,
+ 		.bpp = 24,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_444,
+-		.meram = SH_MOBILE_MERAM_PF_NV24,
+ 	}, {
+ 		.fourcc = DRM_FORMAT_NV42,
+ 		.bpp = 24,
+ 		.yuv = true,
+ 		.lddfr = LDDFR_CC | LDDFR_YF_444,
+-		.meram = SH_MOBILE_MERAM_PF_NV24,
+ 	},
+ };
+ 
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_kms.h b/drivers/gpu/drm/shmobile/shmob_drm_kms.h
+index 06d5b7caa026..753e2817dc2c 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_kms.h
++++ b/drivers/gpu/drm/shmobile/shmob_drm_kms.h
+@@ -24,7 +24,6 @@ struct shmob_drm_format_info {
+ 	unsigned int bpp;
+ 	bool yuv;
+ 	u32 lddfr;
+-	unsigned int meram;
+ };
+ 
+ const struct shmob_drm_format_info *shmob_drm_format_info(u32 fourcc);
+diff --git a/drivers/gpu/drm/shmobile/shmob_drm_plane.c b/drivers/gpu/drm/shmobile/shmob_drm_plane.c
+index 97f6e4a3eb0d..1d0359f713ca 100644
+--- a/drivers/gpu/drm/shmobile/shmob_drm_plane.c
++++ b/drivers/gpu/drm/shmobile/shmob_drm_plane.c
+@@ -17,8 +17,6 @@
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
+ 
+-#include <video/sh_mobile_meram.h>
+-
+ #include "shmob_drm_drv.h"
+ #include "shmob_drm_kms.h"
+ #include "shmob_drm_plane.h"
+diff --git a/include/linux/platform_data/shmob_drm.h b/include/linux/platform_data/shmob_drm.h
+index 7c686d335c12..ee495d707f17 100644
+--- a/include/linux/platform_data/shmob_drm.h
++++ b/include/linux/platform_data/shmob_drm.h
+@@ -18,9 +18,6 @@
+ 
+ #include <drm/drm_mode.h>
+ 
+-struct sh_mobile_meram_cfg;
+-struct sh_mobile_meram_info;
+-
+ enum shmob_drm_clk_source {
+ 	SHMOB_DRM_CLK_BUS,
+ 	SHMOB_DRM_CLK_PERIPHERAL,
+@@ -93,7 +90,6 @@ struct shmob_drm_platform_data {
+ 	struct shmob_drm_interface_data iface;
+ 	struct shmob_drm_panel_data panel;
+ 	struct shmob_drm_backlight_data backlight;
+-	const struct sh_mobile_meram_cfg *meram;
+ };
+ 
+ #endif /* __SHMOB_DRM_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1456-video-fbdev-sh_mobile_lcdcfb-remove-unused-MERAM-sup.patch b/patches/1456-video-fbdev-sh_mobile_lcdcfb-remove-unused-MERAM-sup.patch
new file mode 100644
index 00000000000000..041042a15cf1b7
--- /dev/null
+++ b/patches/1456-video-fbdev-sh_mobile_lcdcfb-remove-unused-MERAM-sup.patch
@@ -0,0 +1,215 @@
+From 35cf20259f21891084d42e07a2d3b101f8020abc Mon Sep 17 00:00:00 2001
+From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+Date: Mon, 14 May 2018 15:47:30 +0200
+Subject: [PATCH 1456/1795] video: fbdev: sh_mobile_lcdcfb: remove unused MERAM
+ support
+
+Since commit a521422ea4ae  ("ARM: shmobile: mackerel: Remove Legacy C
+board code") MERAM functionality is unused. Remove it.
+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Daniel Vetter <daniel@ffwll.ch>
+Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+(cherry picked from commit 9076aa994a9e3b63ed9c79f5f46ffa2b5a001249)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/video/fbdev/Kconfig            |  1 -
+ drivers/video/fbdev/sh_mobile_lcdcfb.c | 63 +-------------------------
+ drivers/video/fbdev/sh_mobile_lcdcfb.h |  1 -
+ include/video/sh_mobile_lcdc.h         |  3 --
+ 4 files changed, 1 insertion(+), 67 deletions(-)
+
+diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
+index 5e58f5ec0a28..c22b9ddb882d 100644
+--- a/drivers/video/fbdev/Kconfig
++++ b/drivers/video/fbdev/Kconfig
+@@ -1996,7 +1996,6 @@ config FB_W100
+ config FB_SH_MOBILE_LCDC
+ 	tristate "SuperH Mobile LCDC framebuffer support"
+ 	depends on FB && (SUPERH || ARCH_RENESAS) && HAVE_CLK
+-	depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM
+ 	select FB_SYS_FILLRECT
+ 	select FB_SYS_COPYAREA
+ 	select FB_SYS_IMAGEBLIT
+diff --git a/drivers/video/fbdev/sh_mobile_lcdcfb.c b/drivers/video/fbdev/sh_mobile_lcdcfb.c
+index c3a46506e47e..eb657e73766f 100644
+--- a/drivers/video/fbdev/sh_mobile_lcdcfb.c
++++ b/drivers/video/fbdev/sh_mobile_lcdcfb.c
+@@ -29,7 +29,6 @@
+ #include <linux/vmalloc.h>
+ 
+ #include <video/sh_mobile_lcdc.h>
+-#include <video/sh_mobile_meram.h>
+ 
+ #include "sh_mobile_lcdcfb.h"
+ 
+@@ -217,7 +216,6 @@ struct sh_mobile_lcdc_priv {
+ 	struct notifier_block notifier;
+ 	int started;
+ 	int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
+-	struct sh_mobile_meram_info *meram_dev;
+ };
+ 
+ /* -----------------------------------------------------------------------------
+@@ -346,16 +344,12 @@ static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
+ 		if (priv->dot_clk)
+ 			clk_prepare_enable(priv->dot_clk);
+ 		pm_runtime_get_sync(priv->dev);
+-		if (priv->meram_dev && priv->meram_dev->pdev)
+-			pm_runtime_get_sync(&priv->meram_dev->pdev->dev);
+ 	}
+ }
+ 
+ static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
+ {
+ 	if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
+-		if (priv->meram_dev && priv->meram_dev->pdev)
+-			pm_runtime_put_sync(&priv->meram_dev->pdev->dev);
+ 		pm_runtime_put(priv->dev);
+ 		if (priv->dot_clk)
+ 			clk_disable_unprepare(priv->dot_clk);
+@@ -1073,7 +1067,6 @@ static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
+ 
+ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
+ {
+-	struct sh_mobile_meram_info *mdev = priv->meram_dev;
+ 	struct sh_mobile_lcdc_chan *ch;
+ 	unsigned long tmp;
+ 	int ret;
+@@ -1106,9 +1099,6 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
+ 
+ 	/* Compute frame buffer base address and pitch for each channel. */
+ 	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
+-		int pixelformat;
+-		void *cache;
+-
+ 		ch = &priv->ch[k];
+ 		if (!ch->enabled)
+ 			continue;
+@@ -1117,45 +1107,6 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
+ 		ch->base_addr_c = ch->dma_handle
+ 				+ ch->xres_virtual * ch->yres_virtual;
+ 		ch->line_size = ch->pitch;
+-
+-		/* Enable MERAM if possible. */
+-		if (mdev == NULL || ch->cfg->meram_cfg == NULL)
+-			continue;
+-
+-		/* Free the allocated MERAM cache. */
+-		if (ch->cache) {
+-			sh_mobile_meram_cache_free(mdev, ch->cache);
+-			ch->cache = NULL;
+-		}
+-
+-		switch (ch->format->fourcc) {
+-		case V4L2_PIX_FMT_NV12:
+-		case V4L2_PIX_FMT_NV21:
+-		case V4L2_PIX_FMT_NV16:
+-		case V4L2_PIX_FMT_NV61:
+-			pixelformat = SH_MOBILE_MERAM_PF_NV;
+-			break;
+-		case V4L2_PIX_FMT_NV24:
+-		case V4L2_PIX_FMT_NV42:
+-			pixelformat = SH_MOBILE_MERAM_PF_NV24;
+-			break;
+-		case V4L2_PIX_FMT_RGB565:
+-		case V4L2_PIX_FMT_BGR24:
+-		case V4L2_PIX_FMT_BGR32:
+-		default:
+-			pixelformat = SH_MOBILE_MERAM_PF_RGB;
+-			break;
+-		}
+-
+-		cache = sh_mobile_meram_cache_alloc(mdev, ch->cfg->meram_cfg,
+-					ch->pitch, ch->yres, pixelformat,
+-					&ch->line_size);
+-		if (!IS_ERR(cache)) {
+-			sh_mobile_meram_cache_update(mdev, cache,
+-					ch->base_addr_y, ch->base_addr_c,
+-					&ch->base_addr_y, &ch->base_addr_c);
+-			ch->cache = cache;
+-		}
+ 	}
+ 
+ 	for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
+@@ -1223,13 +1174,6 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
+ 		}
+ 
+ 		sh_mobile_lcdc_display_off(ch);
+-
+-		/* Free the MERAM cache. */
+-		if (ch->cache) {
+-			sh_mobile_meram_cache_free(priv->meram_dev, ch->cache);
+-			ch->cache = NULL;
+-		}
+-
+ 	}
+ 
+ 	/* stop the lcdc */
+@@ -1851,11 +1795,6 @@ static int sh_mobile_lcdc_pan(struct fb_var_screeninfo *var,
+ 	base_addr_c = ch->dma_handle + ch->xres_virtual * ch->yres_virtual
+ 		    + c_offset;
+ 
+-	if (ch->cache)
+-		sh_mobile_meram_cache_update(priv->meram_dev, ch->cache,
+-					     base_addr_y, base_addr_c,
+-					     &base_addr_y, &base_addr_c);
+-
+ 	ch->base_addr_y = base_addr_y;
+ 	ch->base_addr_c = base_addr_c;
+ 	ch->pan_y_offset = y_offset;
+@@ -2724,7 +2663,7 @@ static int sh_mobile_lcdc_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	priv->dev = &pdev->dev;
+-	priv->meram_dev = pdata->meram_dev;
++
+ 	for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
+ 		mutex_init(&priv->ch[i].open_lock);
+ 	platform_set_drvdata(pdev, priv);
+diff --git a/drivers/video/fbdev/sh_mobile_lcdcfb.h b/drivers/video/fbdev/sh_mobile_lcdcfb.h
+index cc52c74721fe..b8e47a8bd8ab 100644
+--- a/drivers/video/fbdev/sh_mobile_lcdcfb.h
++++ b/drivers/video/fbdev/sh_mobile_lcdcfb.h
+@@ -61,7 +61,6 @@ struct sh_mobile_lcdc_chan {
+ 	unsigned long *reg_offs;
+ 	unsigned long ldmt1r_value;
+ 	unsigned long enabled; /* ME and SE in LDCNT2R */
+-	void *cache;
+ 
+ 	struct mutex open_lock;		/* protects the use counter */
+ 	int use_count;
+diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
+index f706b0fed399..84aa976ca4ea 100644
+--- a/include/video/sh_mobile_lcdc.h
++++ b/include/video/sh_mobile_lcdc.h
+@@ -3,7 +3,6 @@
+ #define __ASM_SH_MOBILE_LCDC_H__
+ 
+ #include <linux/fb.h>
+-#include <video/sh_mobile_meram.h>
+ 
+ /* Register definitions */
+ #define _LDDCKR			0x410
+@@ -184,7 +183,6 @@ struct sh_mobile_lcdc_chan_cfg {
+ 	struct sh_mobile_lcdc_panel_cfg panel_cfg;
+ 	struct sh_mobile_lcdc_bl_info bl_info;
+ 	struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
+-	const struct sh_mobile_meram_cfg *meram_cfg;
+ 
+ 	struct platform_device *tx_dev;	/* HDMI/DSI transmitter device */
+ };
+@@ -193,7 +191,6 @@ struct sh_mobile_lcdc_info {
+ 	int clock_source;
+ 	struct sh_mobile_lcdc_chan_cfg ch[2];
+ 	struct sh_mobile_lcdc_overlay_cfg overlays[4];
+-	struct sh_mobile_meram_info *meram_dev;
+ };
+ 
+ #endif /* __ASM_SH_MOBILE_LCDC_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1457-video-fbdev-remove-unused-sh_mobile_meram-driver.patch b/patches/1457-video-fbdev-remove-unused-sh_mobile_meram-driver.patch
new file mode 100644
index 00000000000000..de58ec507021d2
--- /dev/null
+++ b/patches/1457-video-fbdev-remove-unused-sh_mobile_meram-driver.patch
@@ -0,0 +1,932 @@
+From b11f0f672c9ea72311158228904811a33e121556 Mon Sep 17 00:00:00 2001
+From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+Date: Mon, 14 May 2018 15:47:30 +0200
+Subject: [PATCH 1457/1795] video: fbdev: remove unused sh_mobile_meram driver
+
+Since commit a521422ea4ae  ("ARM: shmobile: mackerel: Remove Legacy C
+board code") MERAM functionality is unused. Remove it.
+
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Acked-by: Daniel Vetter <daniel@ffwll.ch>
+Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+(cherry picked from commit 187a60358a90125e97671e6e4e5a1e412667bdab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+Conflicts:
+	drivers/video/fbdev/Kconfig
+	drivers/video/fbdev/sh_mobile_meram.c
+---
+ drivers/video/fbdev/Kconfig           |  12 -
+ drivers/video/fbdev/Makefile          |   1 -
+ drivers/video/fbdev/sh_mobile_meram.c | 758 --------------------------
+ include/video/sh_mobile_meram.h       |  95 ----
+ 4 files changed, 866 deletions(-)
+ delete mode 100644 drivers/video/fbdev/sh_mobile_meram.c
+ delete mode 100644 include/video/sh_mobile_meram.h
+
+diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
+index c22b9ddb882d..d08961396b36 100644
+--- a/drivers/video/fbdev/Kconfig
++++ b/drivers/video/fbdev/Kconfig
+@@ -2454,18 +2454,6 @@ source "drivers/video/fbdev/omap/Kconfig"
+ source "drivers/video/fbdev/omap2/Kconfig"
+ source "drivers/video/fbdev/mmp/Kconfig"
+ 
+-config FB_SH_MOBILE_MERAM
+-	tristate "SuperH Mobile MERAM read ahead support"
+-	depends on (SUPERH || ARCH_SHMOBILE)
+-	select GENERIC_ALLOCATOR
+-	---help---
+-	  Enable MERAM support for the SuperH controller.
+-
+-	  This will allow for caching of the framebuffer to provide more
+-	  reliable access under heavy main memory bus traffic situations.
+-	  Up to 4 memory channels can be configured, allowing 4 RGB or
+-	  2 YCbCr framebuffers to be configured.
+-
+ config FB_SSD1307
+ 	tristate "Solomon SSD1307 framebuffer support"
+ 	depends on FB && I2C
+diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
+index 8895536a20d6..0ce86961973a 100644
+--- a/drivers/video/fbdev/Makefile
++++ b/drivers/video/fbdev/Makefile
+@@ -117,7 +117,6 @@ obj-$(CONFIG_FB_SM501)            += sm501fb.o
+ obj-$(CONFIG_FB_UDL)		  += udlfb.o
+ obj-$(CONFIG_FB_SMSCUFX)	  += smscufx.o
+ obj-$(CONFIG_FB_XILINX)           += xilinxfb.o
+-obj-$(CONFIG_FB_SH_MOBILE_MERAM)  += sh_mobile_meram.o
+ obj-$(CONFIG_FB_SH_MOBILE_LCDC)	  += sh_mobile_lcdcfb.o
+ obj-$(CONFIG_FB_OMAP)             += omap/
+ obj-y                             += omap2/
+diff --git a/drivers/video/fbdev/sh_mobile_meram.c b/drivers/video/fbdev/sh_mobile_meram.c
+deleted file mode 100644
+index baadfb207b2e..000000000000
+--- a/drivers/video/fbdev/sh_mobile_meram.c
++++ /dev/null
+@@ -1,758 +0,0 @@
+-/*
+- * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
+- *
+- * Copyright (c) 2011	Damian Hobson-Garcia <dhobsong@igel.co.jp>
+- *                      Takanari Hayama <taki@igel.co.jp>
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- */
+-
+-#include <linux/device.h>
+-#include <linux/err.h>
+-#include <linux/export.h>
+-#include <linux/genalloc.h>
+-#include <linux/io.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/platform_device.h>
+-#include <linux/pm_runtime.h>
+-#include <linux/slab.h>
+-
+-#include <video/sh_mobile_meram.h>
+-
+-/* -----------------------------------------------------------------------------
+- * MERAM registers
+- */
+-
+-#define MEVCR1			0x4
+-#define MEVCR1_RST		(1 << 31)
+-#define MEVCR1_WD		(1 << 30)
+-#define MEVCR1_AMD1		(1 << 29)
+-#define MEVCR1_AMD0		(1 << 28)
+-#define MEQSEL1			0x40
+-#define MEQSEL2			0x44
+-
+-#define MExxCTL			0x400
+-#define MExxCTL_BV		(1 << 31)
+-#define MExxCTL_BSZ_SHIFT	28
+-#define MExxCTL_MSAR_MASK	(0x7ff << MExxCTL_MSAR_SHIFT)
+-#define MExxCTL_MSAR_SHIFT	16
+-#define MExxCTL_NXT_MASK	(0x1f << MExxCTL_NXT_SHIFT)
+-#define MExxCTL_NXT_SHIFT	11
+-#define MExxCTL_WD1		(1 << 10)
+-#define MExxCTL_WD0		(1 << 9)
+-#define MExxCTL_WS		(1 << 8)
+-#define MExxCTL_CB		(1 << 7)
+-#define MExxCTL_WBF		(1 << 6)
+-#define MExxCTL_WF		(1 << 5)
+-#define MExxCTL_RF		(1 << 4)
+-#define MExxCTL_CM		(1 << 3)
+-#define MExxCTL_MD_READ		(1 << 0)
+-#define MExxCTL_MD_WRITE	(2 << 0)
+-#define MExxCTL_MD_ICB_WB	(3 << 0)
+-#define MExxCTL_MD_ICB		(4 << 0)
+-#define MExxCTL_MD_FB		(7 << 0)
+-#define MExxCTL_MD_MASK		(7 << 0)
+-#define MExxBSIZE		0x404
+-#define MExxBSIZE_RCNT_SHIFT	28
+-#define MExxBSIZE_YSZM1_SHIFT	16
+-#define MExxBSIZE_XSZM1_SHIFT	0
+-#define MExxMNCF		0x408
+-#define MExxMNCF_KWBNM_SHIFT	28
+-#define MExxMNCF_KRBNM_SHIFT	24
+-#define MExxMNCF_BNM_SHIFT	16
+-#define MExxMNCF_XBV		(1 << 15)
+-#define MExxMNCF_CPL_YCBCR444	(1 << 12)
+-#define MExxMNCF_CPL_YCBCR420	(2 << 12)
+-#define MExxMNCF_CPL_YCBCR422	(3 << 12)
+-#define MExxMNCF_CPL_MSK	(3 << 12)
+-#define MExxMNCF_BL		(1 << 2)
+-#define MExxMNCF_LNM_SHIFT	0
+-#define MExxSARA		0x410
+-#define MExxSARB		0x414
+-#define MExxSBSIZE		0x418
+-#define MExxSBSIZE_HDV		(1 << 31)
+-#define MExxSBSIZE_HSZ16	(0 << 28)
+-#define MExxSBSIZE_HSZ32	(1 << 28)
+-#define MExxSBSIZE_HSZ64	(2 << 28)
+-#define MExxSBSIZE_HSZ128	(3 << 28)
+-#define MExxSBSIZE_SBSIZZ_SHIFT	0
+-
+-#define MERAM_MExxCTL_VAL(next, addr)	\
+-	((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \
+-	 (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK))
+-#define	MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \
+-	(((rcnt) << MExxBSIZE_RCNT_SHIFT) | \
+-	 ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \
+-	 ((xszm1) << MExxBSIZE_XSZM1_SHIFT))
+-
+-static const unsigned long common_regs[] = {
+-	MEVCR1,
+-	MEQSEL1,
+-	MEQSEL2,
+-};
+-#define MERAM_REGS_SIZE ARRAY_SIZE(common_regs)
+-
+-static const unsigned long icb_regs[] = {
+-	MExxCTL,
+-	MExxBSIZE,
+-	MExxMNCF,
+-	MExxSARA,
+-	MExxSARB,
+-	MExxSBSIZE,
+-};
+-#define ICB_REGS_SIZE ARRAY_SIZE(icb_regs)
+-
+-/*
+- * sh_mobile_meram_icb - MERAM ICB information
+- * @regs: Registers cache
+- * @index: ICB index
+- * @offset: MERAM block offset
+- * @size: MERAM block size in KiB
+- * @cache_unit: Bytes to cache per ICB
+- * @pixelformat: Video pixel format of the data stored in the ICB
+- * @current_reg: Which of Start Address Register A (0) or B (1) is in use
+- */
+-struct sh_mobile_meram_icb {
+-	unsigned long regs[ICB_REGS_SIZE];
+-	unsigned int index;
+-	unsigned long offset;
+-	unsigned int size;
+-
+-	unsigned int cache_unit;
+-	unsigned int pixelformat;
+-	unsigned int current_reg;
+-};
+-
+-#define MERAM_ICB_NUM			32
+-
+-struct sh_mobile_meram_fb_plane {
+-	struct sh_mobile_meram_icb *marker;
+-	struct sh_mobile_meram_icb *cache;
+-};
+-
+-struct sh_mobile_meram_fb_cache {
+-	unsigned int nplanes;
+-	struct sh_mobile_meram_fb_plane planes[2];
+-};
+-
+-/*
+- * sh_mobile_meram_priv - MERAM device
+- * @base: Registers base address
+- * @meram: MERAM physical address
+- * @regs: Registers cache
+- * @lock: Protects used_icb and icbs
+- * @used_icb: Bitmask of used ICBs
+- * @icbs: ICBs
+- * @pool: Allocation pool to manage the MERAM
+- */
+-struct sh_mobile_meram_priv {
+-	void __iomem *base;
+-	unsigned long meram;
+-	unsigned long regs[MERAM_REGS_SIZE];
+-
+-	struct mutex lock;
+-	unsigned long used_icb;
+-	struct sh_mobile_meram_icb icbs[MERAM_ICB_NUM];
+-
+-	struct gen_pool *pool;
+-};
+-
+-/* settings */
+-#define MERAM_GRANULARITY		1024
+-#define MERAM_SEC_LINE			15
+-#define MERAM_LINE_WIDTH		2048
+-
+-/* -----------------------------------------------------------------------------
+- * Registers access
+- */
+-
+-#define MERAM_ICB_OFFSET(base, idx, off)	((base) + (off) + (idx) * 0x20)
+-
+-static inline void meram_write_icb(void __iomem *base, unsigned int idx,
+-				   unsigned int off, unsigned long val)
+-{
+-	iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
+-}
+-
+-static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx,
+-					   unsigned int off)
+-{
+-	return ioread32(MERAM_ICB_OFFSET(base, idx, off));
+-}
+-
+-static inline void meram_write_reg(void __iomem *base, unsigned int off,
+-				   unsigned long val)
+-{
+-	iowrite32(val, base + off);
+-}
+-
+-static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off)
+-{
+-	return ioread32(base + off);
+-}
+-
+-/* -----------------------------------------------------------------------------
+- * MERAM allocation and free
+- */
+-
+-static unsigned long meram_alloc(struct sh_mobile_meram_priv *priv, size_t size)
+-{
+-	return gen_pool_alloc(priv->pool, size);
+-}
+-
+-static void meram_free(struct sh_mobile_meram_priv *priv, unsigned long mem,
+-		       size_t size)
+-{
+-	gen_pool_free(priv->pool, mem, size);
+-}
+-
+-/* -----------------------------------------------------------------------------
+- * LCDC cache planes allocation, init, cleanup and free
+- */
+-
+-/* Allocate ICBs and MERAM for a plane. */
+-static int meram_plane_alloc(struct sh_mobile_meram_priv *priv,
+-			     struct sh_mobile_meram_fb_plane *plane,
+-			     size_t size)
+-{
+-	unsigned long mem;
+-	unsigned long idx;
+-
+-	idx = find_first_zero_bit(&priv->used_icb, 28);
+-	if (idx == 28)
+-		return -ENOMEM;
+-	plane->cache = &priv->icbs[idx];
+-
+-	idx = find_next_zero_bit(&priv->used_icb, 32, 28);
+-	if (idx == 32)
+-		return -ENOMEM;
+-	plane->marker = &priv->icbs[idx];
+-
+-	mem = meram_alloc(priv, size * 1024);
+-	if (mem == 0)
+-		return -ENOMEM;
+-
+-	__set_bit(plane->marker->index, &priv->used_icb);
+-	__set_bit(plane->cache->index, &priv->used_icb);
+-
+-	plane->marker->offset = mem - priv->meram;
+-	plane->marker->size = size;
+-
+-	return 0;
+-}
+-
+-/* Free ICBs and MERAM for a plane. */
+-static void meram_plane_free(struct sh_mobile_meram_priv *priv,
+-			     struct sh_mobile_meram_fb_plane *plane)
+-{
+-	meram_free(priv, priv->meram + plane->marker->offset,
+-		   plane->marker->size * 1024);
+-
+-	__clear_bit(plane->marker->index, &priv->used_icb);
+-	__clear_bit(plane->cache->index, &priv->used_icb);
+-}
+-
+-/* Is this a YCbCr(NV12, NV16 or NV24) colorspace? */
+-static int is_nvcolor(int cspace)
+-{
+-	if (cspace == SH_MOBILE_MERAM_PF_NV ||
+-	    cspace == SH_MOBILE_MERAM_PF_NV24)
+-		return 1;
+-	return 0;
+-}
+-
+-/* Set the next address to fetch. */
+-static void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
+-				struct sh_mobile_meram_fb_cache *cache,
+-				unsigned long base_addr_y,
+-				unsigned long base_addr_c)
+-{
+-	struct sh_mobile_meram_icb *icb = cache->planes[0].marker;
+-	unsigned long target;
+-
+-	icb->current_reg ^= 1;
+-	target = icb->current_reg ? MExxSARB : MExxSARA;
+-
+-	/* set the next address to fetch */
+-	meram_write_icb(priv->base, cache->planes[0].cache->index, target,
+-			base_addr_y);
+-	meram_write_icb(priv->base, cache->planes[0].marker->index, target,
+-			base_addr_y + cache->planes[0].marker->cache_unit);
+-
+-	if (cache->nplanes == 2) {
+-		meram_write_icb(priv->base, cache->planes[1].cache->index,
+-				target, base_addr_c);
+-		meram_write_icb(priv->base, cache->planes[1].marker->index,
+-				target, base_addr_c +
+-				cache->planes[1].marker->cache_unit);
+-	}
+-}
+-
+-/* Get the next ICB address. */
+-static void
+-meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
+-			struct sh_mobile_meram_fb_cache *cache,
+-			unsigned long *icb_addr_y, unsigned long *icb_addr_c)
+-{
+-	struct sh_mobile_meram_icb *icb = cache->planes[0].marker;
+-	unsigned long icb_offset;
+-
+-	if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
+-		icb_offset = 0x80000000 | (icb->current_reg << 29);
+-	else
+-		icb_offset = 0xc0000000 | (icb->current_reg << 23);
+-
+-	*icb_addr_y = icb_offset | (cache->planes[0].marker->index << 24);
+-	if (cache->nplanes == 2)
+-		*icb_addr_c = icb_offset
+-			    | (cache->planes[1].marker->index << 24);
+-}
+-
+-#define MERAM_CALC_BYTECOUNT(x, y) \
+-	(((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
+-
+-/* Initialize MERAM. */
+-static int meram_plane_init(struct sh_mobile_meram_priv *priv,
+-			    struct sh_mobile_meram_fb_plane *plane,
+-			    unsigned int xres, unsigned int yres,
+-			    unsigned int *out_pitch)
+-{
+-	struct sh_mobile_meram_icb *marker = plane->marker;
+-	unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
+-	unsigned long bnm;
+-	unsigned int lcdc_pitch;
+-	unsigned int xpitch;
+-	unsigned int line_cnt;
+-	unsigned int save_lines;
+-
+-	/* adjust pitch to 1024, 2048, 4096 or 8192 */
+-	lcdc_pitch = (xres - 1) | 1023;
+-	lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
+-	lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
+-	lcdc_pitch += 1;
+-
+-	/* derive settings */
+-	if (lcdc_pitch == 8192 && yres >= 1024) {
+-		lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
+-		line_cnt = total_byte_count >> 11;
+-		*out_pitch = xres;
+-		save_lines = plane->marker->size / 16 / MERAM_SEC_LINE;
+-		save_lines *= MERAM_SEC_LINE;
+-	} else {
+-		xpitch = xres;
+-		line_cnt = yres;
+-		*out_pitch = lcdc_pitch;
+-		save_lines = plane->marker->size / (lcdc_pitch >> 10) / 2;
+-		save_lines &= 0xff;
+-	}
+-	bnm = (save_lines - 1) << 16;
+-
+-	/* TODO: we better to check if we have enough MERAM buffer size */
+-
+-	/* set up ICB */
+-	meram_write_icb(priv->base, plane->cache->index,  MExxBSIZE,
+-			MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
+-	meram_write_icb(priv->base, plane->marker->index, MExxBSIZE,
+-			MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
+-
+-	meram_write_icb(priv->base, plane->cache->index,  MExxMNCF, bnm);
+-	meram_write_icb(priv->base, plane->marker->index, MExxMNCF, bnm);
+-
+-	meram_write_icb(priv->base, plane->cache->index,  MExxSBSIZE, xpitch);
+-	meram_write_icb(priv->base, plane->marker->index, MExxSBSIZE, xpitch);
+-
+-	/* save a cache unit size */
+-	plane->cache->cache_unit = xres * save_lines;
+-	plane->marker->cache_unit = xres * save_lines;
+-
+-	/*
+-	 * Set MERAM for framebuffer
+-	 *
+-	 * we also chain the cache_icb and the marker_icb.
+-	 * we also split the allocated MERAM buffer between two ICBs.
+-	 */
+-	meram_write_icb(priv->base, plane->cache->index, MExxCTL,
+-			MERAM_MExxCTL_VAL(plane->marker->index, marker->offset)
+-			| MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
+-			MExxCTL_MD_FB);
+-	meram_write_icb(priv->base, plane->marker->index, MExxCTL,
+-			MERAM_MExxCTL_VAL(plane->cache->index, marker->offset +
+-					  plane->marker->size / 2) |
+-			MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
+-			MExxCTL_MD_FB);
+-
+-	return 0;
+-}
+-
+-static void meram_plane_cleanup(struct sh_mobile_meram_priv *priv,
+-				struct sh_mobile_meram_fb_plane *plane)
+-{
+-	/* disable ICB */
+-	meram_write_icb(priv->base, plane->cache->index,  MExxCTL,
+-			MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
+-	meram_write_icb(priv->base, plane->marker->index, MExxCTL,
+-			MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
+-
+-	plane->cache->cache_unit = 0;
+-	plane->marker->cache_unit = 0;
+-}
+-
+-/* -----------------------------------------------------------------------------
+- * MERAM operations
+- */
+-
+-unsigned long sh_mobile_meram_alloc(struct sh_mobile_meram_info *pdata,
+-				    size_t size)
+-{
+-	struct sh_mobile_meram_priv *priv = pdata->priv;
+-
+-	return meram_alloc(priv, size);
+-}
+-EXPORT_SYMBOL_GPL(sh_mobile_meram_alloc);
+-
+-void sh_mobile_meram_free(struct sh_mobile_meram_info *pdata, unsigned long mem,
+-			  size_t size)
+-{
+-	struct sh_mobile_meram_priv *priv = pdata->priv;
+-
+-	meram_free(priv, mem, size);
+-}
+-EXPORT_SYMBOL_GPL(sh_mobile_meram_free);
+-
+-/* Allocate memory for the ICBs and mark them as used. */
+-static struct sh_mobile_meram_fb_cache *
+-meram_cache_alloc(struct sh_mobile_meram_priv *priv,
+-		  const struct sh_mobile_meram_cfg *cfg,
+-		  int pixelformat)
+-{
+-	unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1;
+-	struct sh_mobile_meram_fb_cache *cache;
+-	int ret;
+-
+-	cache = kzalloc(sizeof(*cache), GFP_KERNEL);
+-	if (cache == NULL)
+-		return ERR_PTR(-ENOMEM);
+-
+-	cache->nplanes = nplanes;
+-
+-	ret = meram_plane_alloc(priv, &cache->planes[0],
+-				cfg->icb[0].meram_size);
+-	if (ret < 0)
+-		goto error;
+-
+-	cache->planes[0].marker->current_reg = 1;
+-	cache->planes[0].marker->pixelformat = pixelformat;
+-
+-	if (cache->nplanes == 1)
+-		return cache;
+-
+-	ret = meram_plane_alloc(priv, &cache->planes[1],
+-				cfg->icb[1].meram_size);
+-	if (ret < 0) {
+-		meram_plane_free(priv, &cache->planes[0]);
+-		goto error;
+-	}
+-
+-	return cache;
+-
+-error:
+-	kfree(cache);
+-	return ERR_PTR(-ENOMEM);
+-}
+-
+-void *sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *pdata,
+-				  const struct sh_mobile_meram_cfg *cfg,
+-				  unsigned int xres, unsigned int yres,
+-				  unsigned int pixelformat, unsigned int *pitch)
+-{
+-	struct sh_mobile_meram_fb_cache *cache;
+-	struct sh_mobile_meram_priv *priv = pdata->priv;
+-	struct platform_device *pdev = pdata->pdev;
+-	unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1;
+-	unsigned int out_pitch;
+-
+-	if (priv == NULL)
+-		return ERR_PTR(-ENODEV);
+-
+-	if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
+-	    pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
+-	    pixelformat != SH_MOBILE_MERAM_PF_RGB)
+-		return ERR_PTR(-EINVAL);
+-
+-	dev_dbg(&pdev->dev, "registering %dx%d (%s)", xres, yres,
+-		!pixelformat ? "yuv" : "rgb");
+-
+-	/* we can't handle wider than 8192px */
+-	if (xres > 8192) {
+-		dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
+-		return ERR_PTR(-EINVAL);
+-	}
+-
+-	if (cfg->icb[0].meram_size == 0)
+-		return ERR_PTR(-EINVAL);
+-
+-	if (nplanes == 2 && cfg->icb[1].meram_size == 0)
+-		return ERR_PTR(-EINVAL);
+-
+-	mutex_lock(&priv->lock);
+-
+-	/* We now register the ICBs and allocate the MERAM regions. */
+-	cache = meram_cache_alloc(priv, cfg, pixelformat);
+-	if (IS_ERR(cache)) {
+-		dev_err(&pdev->dev, "MERAM allocation failed (%ld).",
+-			PTR_ERR(cache));
+-		goto err;
+-	}
+-
+-	/* initialize MERAM */
+-	meram_plane_init(priv, &cache->planes[0], xres, yres, &out_pitch);
+-	*pitch = out_pitch;
+-	if (pixelformat == SH_MOBILE_MERAM_PF_NV)
+-		meram_plane_init(priv, &cache->planes[1],
+-				 xres, (yres + 1) / 2, &out_pitch);
+-	else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
+-		meram_plane_init(priv, &cache->planes[1],
+-				 2 * xres, (yres + 1) / 2, &out_pitch);
+-
+-err:
+-	mutex_unlock(&priv->lock);
+-	return cache;
+-}
+-EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_alloc);
+-
+-void
+-sh_mobile_meram_cache_free(struct sh_mobile_meram_info *pdata, void *data)
+-{
+-	struct sh_mobile_meram_fb_cache *cache = data;
+-	struct sh_mobile_meram_priv *priv = pdata->priv;
+-
+-	mutex_lock(&priv->lock);
+-
+-	/* Cleanup and free. */
+-	meram_plane_cleanup(priv, &cache->planes[0]);
+-	meram_plane_free(priv, &cache->planes[0]);
+-
+-	if (cache->nplanes == 2) {
+-		meram_plane_cleanup(priv, &cache->planes[1]);
+-		meram_plane_free(priv, &cache->planes[1]);
+-	}
+-
+-	kfree(cache);
+-
+-	mutex_unlock(&priv->lock);
+-}
+-EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_free);
+-
+-void
+-sh_mobile_meram_cache_update(struct sh_mobile_meram_info *pdata, void *data,
+-			     unsigned long base_addr_y,
+-			     unsigned long base_addr_c,
+-			     unsigned long *icb_addr_y,
+-			     unsigned long *icb_addr_c)
+-{
+-	struct sh_mobile_meram_fb_cache *cache = data;
+-	struct sh_mobile_meram_priv *priv = pdata->priv;
+-
+-	mutex_lock(&priv->lock);
+-
+-	meram_set_next_addr(priv, cache, base_addr_y, base_addr_c);
+-	meram_get_next_icb_addr(pdata, cache, icb_addr_y, icb_addr_c);
+-
+-	mutex_unlock(&priv->lock);
+-}
+-EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_update);
+-
+-/* -----------------------------------------------------------------------------
+- * Power management
+- */
+-
+-#ifdef CONFIG_PM
+-static int sh_mobile_meram_suspend(struct device *dev)
+-{
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
+-	unsigned int i, j;
+-
+-	for (i = 0; i < MERAM_REGS_SIZE; i++)
+-		priv->regs[i] = meram_read_reg(priv->base, common_regs[i]);
+-
+-	for (i = 0; i < 32; i++) {
+-		if (!test_bit(i, &priv->used_icb))
+-			continue;
+-		for (j = 0; j < ICB_REGS_SIZE; j++) {
+-			priv->icbs[i].regs[j] =
+-				meram_read_icb(priv->base, i, icb_regs[j]);
+-			/* Reset ICB on resume */
+-			if (icb_regs[j] == MExxCTL)
+-				priv->icbs[i].regs[j] |=
+-					MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF;
+-		}
+-	}
+-	return 0;
+-}
+-
+-static int sh_mobile_meram_resume(struct device *dev)
+-{
+-	struct platform_device *pdev = to_platform_device(dev);
+-	struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
+-	unsigned int i, j;
+-
+-	for (i = 0; i < 32; i++) {
+-		if (!test_bit(i, &priv->used_icb))
+-			continue;
+-		for (j = 0; j < ICB_REGS_SIZE; j++)
+-			meram_write_icb(priv->base, i, icb_regs[j],
+-					priv->icbs[i].regs[j]);
+-	}
+-
+-	for (i = 0; i < MERAM_REGS_SIZE; i++)
+-		meram_write_reg(priv->base, common_regs[i], priv->regs[i]);
+-	return 0;
+-}
+-#endif /* CONFIG_PM */
+-
+-static UNIVERSAL_DEV_PM_OPS(sh_mobile_meram_dev_pm_ops,
+-			    sh_mobile_meram_suspend,
+-			    sh_mobile_meram_resume, NULL);
+-
+-/* -----------------------------------------------------------------------------
+- * Probe/remove and driver init/exit
+- */
+-
+-static int sh_mobile_meram_probe(struct platform_device *pdev)
+-{
+-	struct sh_mobile_meram_priv *priv;
+-	struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
+-	struct resource *regs;
+-	struct resource *meram;
+-	unsigned int i;
+-	int error;
+-
+-	if (!pdata) {
+-		dev_err(&pdev->dev, "no platform data defined\n");
+-		return -EINVAL;
+-	}
+-
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	if (regs == NULL || meram == NULL) {
+-		dev_err(&pdev->dev, "cannot get platform resources\n");
+-		return -ENOENT;
+-	}
+-
+-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+-	if (!priv) {
+-		dev_err(&pdev->dev, "cannot allocate device data\n");
+-		return -ENOMEM;
+-	}
+-
+-	/* Initialize private data. */
+-	mutex_init(&priv->lock);
+-	priv->used_icb = pdata->reserved_icbs;
+-
+-	for (i = 0; i < MERAM_ICB_NUM; ++i)
+-		priv->icbs[i].index = i;
+-
+-	pdata->priv = priv;
+-	pdata->pdev = pdev;
+-
+-	/* Request memory regions and remap the registers. */
+-	if (!request_mem_region(regs->start, resource_size(regs), pdev->name)) {
+-		dev_err(&pdev->dev, "MERAM registers region already claimed\n");
+-		error = -EBUSY;
+-		goto err_req_regs;
+-	}
+-
+-	if (!request_mem_region(meram->start, resource_size(meram),
+-				pdev->name)) {
+-		dev_err(&pdev->dev, "MERAM memory region already claimed\n");
+-		error = -EBUSY;
+-		goto err_req_meram;
+-	}
+-
+-	priv->base = ioremap_nocache(regs->start, resource_size(regs));
+-	if (!priv->base) {
+-		dev_err(&pdev->dev, "ioremap failed\n");
+-		error = -EFAULT;
+-		goto err_ioremap;
+-	}
+-
+-	priv->meram = meram->start;
+-
+-	/* Create and initialize the MERAM memory pool. */
+-	priv->pool = gen_pool_create(ilog2(MERAM_GRANULARITY), -1);
+-	if (priv->pool == NULL) {
+-		error = -ENOMEM;
+-		goto err_genpool;
+-	}
+-
+-	error = gen_pool_add(priv->pool, meram->start, resource_size(meram),
+-			     -1);
+-	if (error < 0)
+-		goto err_genpool;
+-
+-	/* initialize ICB addressing mode */
+-	if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
+-		meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
+-
+-	platform_set_drvdata(pdev, priv);
+-	pm_runtime_enable(&pdev->dev);
+-
+-	dev_info(&pdev->dev, "sh_mobile_meram initialized.");
+-
+-	return 0;
+-
+-err_genpool:
+-	if (priv->pool)
+-		gen_pool_destroy(priv->pool);
+-	iounmap(priv->base);
+-err_ioremap:
+-	release_mem_region(meram->start, resource_size(meram));
+-err_req_meram:
+-	release_mem_region(regs->start, resource_size(regs));
+-err_req_regs:
+-	mutex_destroy(&priv->lock);
+-	kfree(priv);
+-
+-	return error;
+-}
+-
+-
+-static int sh_mobile_meram_remove(struct platform_device *pdev)
+-{
+-	struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
+-	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	struct resource *meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-
+-	pm_runtime_disable(&pdev->dev);
+-
+-	gen_pool_destroy(priv->pool);
+-
+-	iounmap(priv->base);
+-	release_mem_region(meram->start, resource_size(meram));
+-	release_mem_region(regs->start, resource_size(regs));
+-
+-	mutex_destroy(&priv->lock);
+-
+-	kfree(priv);
+-
+-	return 0;
+-}
+-
+-static struct platform_driver sh_mobile_meram_driver = {
+-	.driver	= {
+-		.name		= "sh_mobile_meram",
+-		.pm		= &sh_mobile_meram_dev_pm_ops,
+-	},
+-	.probe		= sh_mobile_meram_probe,
+-	.remove		= sh_mobile_meram_remove,
+-};
+-
+-module_platform_driver(sh_mobile_meram_driver);
+-
+-MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
+-MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
+-MODULE_LICENSE("GPL v2");
+diff --git a/include/video/sh_mobile_meram.h b/include/video/sh_mobile_meram.h
+deleted file mode 100644
+index f4efc21e205d..000000000000
+--- a/include/video/sh_mobile_meram.h
++++ /dev/null
+@@ -1,95 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-#ifndef __VIDEO_SH_MOBILE_MERAM_H__
+-#define __VIDEO_SH_MOBILE_MERAM_H__
+-
+-/* For sh_mobile_meram_info.addr_mode */
+-enum {
+-	SH_MOBILE_MERAM_MODE0 = 0,
+-	SH_MOBILE_MERAM_MODE1
+-};
+-
+-enum {
+-	SH_MOBILE_MERAM_PF_NV = 0,
+-	SH_MOBILE_MERAM_PF_RGB,
+-	SH_MOBILE_MERAM_PF_NV24
+-};
+-
+-
+-struct sh_mobile_meram_priv;
+-
+-/*
+- * struct sh_mobile_meram_info - MERAM platform data
+- * @reserved_icbs: Bitmask of reserved ICBs (for instance used through UIO)
+- */
+-struct sh_mobile_meram_info {
+-	int				addr_mode;
+-	u32				reserved_icbs;
+-	struct sh_mobile_meram_priv	*priv;
+-	struct platform_device		*pdev;
+-};
+-
+-/* icb config */
+-struct sh_mobile_meram_icb_cfg {
+-	unsigned int meram_size;	/* MERAM Buffer Size to use */
+-};
+-
+-struct sh_mobile_meram_cfg {
+-	struct sh_mobile_meram_icb_cfg icb[2];
+-};
+-
+-#if defined(CONFIG_FB_SH_MOBILE_MERAM) || \
+-    defined(CONFIG_FB_SH_MOBILE_MERAM_MODULE)
+-unsigned long sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev,
+-				    size_t size);
+-void sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev,
+-			  unsigned long mem, size_t size);
+-void *sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev,
+-				  const struct sh_mobile_meram_cfg *cfg,
+-				  unsigned int xres, unsigned int yres,
+-				  unsigned int pixelformat,
+-				  unsigned int *pitch);
+-void sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data);
+-void sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data,
+-				  unsigned long base_addr_y,
+-				  unsigned long base_addr_c,
+-				  unsigned long *icb_addr_y,
+-				  unsigned long *icb_addr_c);
+-#else
+-static inline unsigned long
+-sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev, size_t size)
+-{
+-	return 0;
+-}
+-
+-static inline void
+-sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev,
+-		     unsigned long mem, size_t size)
+-{
+-}
+-
+-static inline void *
+-sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev,
+-			    const struct sh_mobile_meram_cfg *cfg,
+-			    unsigned int xres, unsigned int yres,
+-			    unsigned int pixelformat,
+-			    unsigned int *pitch)
+-{
+-	return ERR_PTR(-ENODEV);
+-}
+-
+-static inline void
+-sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data)
+-{
+-}
+-
+-static inline void
+-sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data,
+-			     unsigned long base_addr_y,
+-			     unsigned long base_addr_c,
+-			     unsigned long *icb_addr_y,
+-			     unsigned long *icb_addr_c)
+-{
+-}
+-#endif
+-
+-#endif /* __VIDEO_SH_MOBILE_MERAM_H__  */
+-- 
+2.19.0
+
diff --git a/patches/1458-arm64-dts-renesas-r8a77965-add-usb2_phy-nodes.patch b/patches/1458-arm64-dts-renesas-r8a77965-add-usb2_phy-nodes.patch
new file mode 100644
index 00000000000000..452b0e692eabbc
--- /dev/null
+++ b/patches/1458-arm64-dts-renesas-r8a77965-add-usb2_phy-nodes.patch
@@ -0,0 +1,52 @@
+From 650cf4fc89eb93b3cadf777e6680180edc820b5e Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:21 +0900
+Subject: [PATCH 1458/1795] arm64: dts: renesas: r8a77965: add usb2_phy nodes
+
+This patch add usb2_phy nodes for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b5857630a829a8d567627e5925a5710e5a80491a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index f0871fcdd984..d498274fa0f3 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -650,13 +650,26 @@
+ 		};
+ 
+ 		usb2_phy0: usb-phy@ee080200 {
++			compatible = "renesas,usb2-phy-r8a77965",
++				     "renesas,rcar-gen3-usb2-phy";
+ 			reg = <0 0xee080200 0 0x700>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 703>;
++			#phy-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		usb2_phy1: usb-phy@ee0a0200 {
++			compatible = "renesas,usb2-phy-r8a77965",
++				     "renesas,rcar-gen3-usb2-phy";
+ 			reg = <0 0xee0a0200 0 0x700>;
+-			/* placeholder */
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 703>;
++			#phy-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		ohci1: usb@ee0a0000 {
+-- 
+2.19.0
+
diff --git a/patches/1459-arm64-dts-renesas-r8a77965-add-usb3_phy-node.patch b/patches/1459-arm64-dts-renesas-r8a77965-add-usb3_phy-node.patch
new file mode 100644
index 00000000000000..4a96d7d9ec5746
--- /dev/null
+++ b/patches/1459-arm64-dts-renesas-r8a77965-add-usb3_phy-node.patch
@@ -0,0 +1,41 @@
+From 541cd13fb28857a71d68cceb2860741ef20ac036 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:22 +0900
+Subject: [PATCH 1459/1795] arm64: dts: renesas: r8a77965: add usb3_phy node
+
+This patch adds usb3_phy node for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7a4a541eed654d62f82146f71b8aed869254e9ad)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index d498274fa0f3..abb4d4dcc0ed 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -868,9 +868,16 @@
+ 		};
+ 
+ 		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a77965-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
+ 			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
+ 			#phy-cells = <0>;
+-			/* placeholder */
++			status = "disabled";
+ 		};
+ 
+ 		usb3_peri0: usb@ee020000 {
+-- 
+2.19.0
+
diff --git a/patches/1460-arm64-dts-renesas-r8a77965-add-USB-2.0-host-nodes.patch b/patches/1460-arm64-dts-renesas-r8a77965-add-USB-2.0-host-nodes.patch
new file mode 100644
index 00000000000000..95cd316ea6e0a1
--- /dev/null
+++ b/patches/1460-arm64-dts-renesas-r8a77965-add-USB-2.0-host-nodes.patch
@@ -0,0 +1,86 @@
+From 1f5b3c775e36a0566416bbd3cfa156a10f1491e7 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:23 +0900
+Subject: [PATCH 1460/1795] arm64: dts: renesas: r8a77965: add USB 2.0 host
+ nodes
+
+This patch adds USB 2.0 host (EHCI/OHCI) nodes for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1dfa66cd906a06fe05703b32d3fe818710414aaf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 38 ++++++++++++++++++++---
+ 1 file changed, 34 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index abb4d4dcc0ed..ecc34ced3be2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -640,13 +640,28 @@
+ 		};
+ 
+ 		ohci0: usb@ee080000 {
++			compatible = "generic-ohci";
+ 			reg = <0 0xee080000 0 0x100>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 703>;
++			status = "disabled";
+ 		};
+ 
+ 		ehci0: usb@ee080100 {
++			compatible = "generic-ehci";
+ 			reg = <0 0xee080100 0 0x100>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			companion = <&ohci0>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 703>;
++			status = "disabled";
+ 		};
+ 
+ 		usb2_phy0: usb-phy@ee080200 {
+@@ -673,13 +688,28 @@
+ 		};
+ 
+ 		ohci1: usb@ee0a0000 {
++			compatible = "generic-ohci";
+ 			reg = <0 0xee0a0000 0 0x100>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 702>;
++			status = "disabled";
+ 		};
+ 
+ 		ehci1: usb@ee0a0100 {
++			compatible = "generic-ehci";
+ 			reg = <0 0xee0a0100 0 0x100>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			companion = <&ohci1>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 702>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c0: i2c@e6500000 {
+-- 
+2.19.0
+
diff --git a/patches/1461-arm64-dts-renesas-r8a77965-add-usb_dmac-nodes.patch b/patches/1461-arm64-dts-renesas-r8a77965-add-usb_dmac-nodes.patch
new file mode 100644
index 00000000000000..ae7a1115ff9dc1
--- /dev/null
+++ b/patches/1461-arm64-dts-renesas-r8a77965-add-usb_dmac-nodes.patch
@@ -0,0 +1,58 @@
+From 78dab89ed3a42c02ba3a073653b7400f1e099a0d Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:24 +0900
+Subject: [PATCH 1461/1795] arm64: dts: renesas: r8a77965: add usb_dmac nodes
+
+This patch adds USB-DMAC nodes for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit dc68285152674f0178aff7004613a29efae23531)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 28 +++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index ecc34ced3be2..e5a5dd9d43da 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -832,6 +832,34 @@
+ 			};
+ 		};
+ 
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a77965-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a77965-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
+ 		hsusb: usb@e6590000 {
+ 			reg = <0 0xe6590000 0 0x100>;
+ 			/* placeholder */
+-- 
+2.19.0
+
diff --git a/patches/1462-arm64-dts-renesas-r8a77965-add-HS-USB-node.patch b/patches/1462-arm64-dts-renesas-r8a77965-add-HS-USB-node.patch
new file mode 100644
index 00000000000000..5f5d79f913c1d0
--- /dev/null
+++ b/patches/1462-arm64-dts-renesas-r8a77965-add-HS-USB-node.patch
@@ -0,0 +1,45 @@
+From 278fc68eebaad1dfb42ed464e4efef8ceb59c018 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:25 +0900
+Subject: [PATCH 1462/1795] arm64: dts: renesas: r8a77965: add HS-USB node
+
+This patch adds HS-USB node for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a06e8af801760a98fd1d1355cafa92f89c78c771)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index e5a5dd9d43da..ac74413d006f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -861,8 +861,20 @@
+ 		};
+ 
+ 		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7796",
++				     "renesas,rcar-gen3-usbhs";
+ 			reg = <0 0xe6590000 0 0x100>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			renesas,buswait = <11>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 704>;
++			status = "disabled";
+ 		};
+ 
+ 		pciec0: pcie@fe000000 {
+-- 
+2.19.0
+
diff --git a/patches/1463-arm64-dts-renesas-r8a77965-add-USB-3.0-host-node.patch b/patches/1463-arm64-dts-renesas-r8a77965-add-USB-3.0-host-node.patch
new file mode 100644
index 00000000000000..de7abbced8cf46
--- /dev/null
+++ b/patches/1463-arm64-dts-renesas-r8a77965-add-USB-3.0-host-node.patch
@@ -0,0 +1,40 @@
+From 3d95e7180a545a1c93cd7c4499e9b6b70db35620 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:26 +0900
+Subject: [PATCH 1463/1795] arm64: dts: renesas: r8a77965: add USB 3.0 host
+ node
+
+This patch adds USB 3.0 host node for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e3cee8902e79705526c75efd5187081347c76ecf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index ac74413d006f..a34b80a0f304 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -956,8 +956,14 @@
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
++			compatible = "renesas,xhci-r8a77965",
++				     "renesas,rcar-gen3-xhci";
+ 			reg = <0 0xee000000 0 0xc00>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
++			status = "disabled";
+ 		};
+ 
+ 		wdt0: watchdog@e6020000 {
+-- 
+2.19.0
+
diff --git a/patches/1464-arm64-dts-renesas-r8a77965-add-USB-3.0-peripheral-no.patch b/patches/1464-arm64-dts-renesas-r8a77965-add-USB-3.0-peripheral-no.patch
new file mode 100644
index 00000000000000..e8bb6a52f7602b
--- /dev/null
+++ b/patches/1464-arm64-dts-renesas-r8a77965-add-USB-3.0-peripheral-no.patch
@@ -0,0 +1,40 @@
+From b92a0c008e40ae31620a963d5dc7d7290d91c3a4 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 19 Mar 2018 21:28:27 +0900
+Subject: [PATCH 1464/1795] arm64: dts: renesas: r8a77965: add USB 3.0
+ peripheral node
+
+This patch adds USB 3.0 peripheral node for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3a7dc06d833bd88f26c66fb16f56d93771cd4c2f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index a34b80a0f304..6f748e94a901 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -951,8 +951,14 @@
+ 		};
+ 
+ 		usb3_peri0: usb@ee020000 {
++			compatible = "renesas,r8a77965-usb3-peri",
++				     "renesas,rcar-gen3-usb3-peri";
+ 			reg = <0 0xee020000 0 0x400>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
++			status = "disabled";
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
+-- 
+2.19.0
+
diff --git a/patches/1465-arm64-dts-renesas-r8a77970-Update-IPMMU-DS1-bit-numb.patch b/patches/1465-arm64-dts-renesas-r8a77970-Update-IPMMU-DS1-bit-numb.patch
new file mode 100644
index 00000000000000..b204fba25443b9
--- /dev/null
+++ b/patches/1465-arm64-dts-renesas-r8a77970-Update-IPMMU-DS1-bit-numb.patch
@@ -0,0 +1,38 @@
+From 760e57fa39dd7c4ac4c01d0fad04c2865d107776 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Tue, 20 Mar 2018 16:51:07 +0900
+Subject: [PATCH 1465/1795] arm64: dts: renesas: r8a77970: Update IPMMU DS1 bit
+ number
+
+Judging by "R-Car-Gen3-rev0.80" IPMMU IMSSTR register documentation
+for [R-Car V3M] the DS1 bit field should be bit 0.
+
+Update the ipmmu-main property to make it match the data sheet.
+
+Fixes: ce3b52a1595b ("arm64: dts: renesas: r8a77970: Add IPMMU device nodes")
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d2b860cb303fdeffa886c20bfbdbfd88cc52c85f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index c6db8ea43906..e8358d9bfd66 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -160,7 +160,7 @@
+ 		ipmmu_ds1: mmu@e7740000 {
+ 			compatible = "renesas,ipmmu-r8a77970";
+ 			reg = <0 0xe7740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/1466-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-root-.patch b/patches/1466-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-root-.patch
new file mode 100644
index 00000000000000..c15e4fa97dc729
--- /dev/null
+++ b/patches/1466-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-root-.patch
@@ -0,0 +1,233 @@
+From b6c62aa3cb5b6b4347edc35110c00945af89eb3d Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 23 Mar 2018 11:04:07 +0100
+Subject: [PATCH 1466/1795] arm64: dts: renesas: r8a7796: sort subnodes of the
+ root node
+
+Sort subnodes of the root node alphanumerically.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 6ef5e21294dfd2edcc3e1bb547aef3333d42e86d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 162 +++++++++++------------
+ 1 file changed, 81 insertions(+), 81 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 556eb8e45499..78fbb4fd34bf 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -60,6 +60,72 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	cluster0_opp: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1500000000 {
++			opp-hz = /bits/ 64 <1500000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1600000000 {
++			opp-hz = /bits/ 64 <1600000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1700000000 {
++			opp-hz = /bits/ 64 <1700000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <960000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++	};
++
++	cluster1_opp: opp_table1 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-800000000 {
++			opp-hz = /bits/ 64 <800000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1300000000 {
++			opp-hz = /bits/ 64 <1300000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -161,72 +227,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	cluster0_opp: opp_table0 {
+-		compatible = "operating-points-v2";
+-		opp-shared;
+-
+-		opp-500000000 {
+-			opp-hz = /bits/ 64 <500000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1000000000 {
+-			opp-hz = /bits/ 64 <1000000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1500000000 {
+-			opp-hz = /bits/ 64 <1500000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1600000000 {
+-			opp-hz = /bits/ 64 <1600000000>;
+-			opp-microvolt = <900000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-		opp-1700000000 {
+-			opp-hz = /bits/ 64 <1700000000>;
+-			opp-microvolt = <900000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-		opp-1800000000 {
+-			opp-hz = /bits/ 64 <1800000000>;
+-			opp-microvolt = <960000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-	};
+-
+-	cluster1_opp: opp_table1 {
+-		compatible = "operating-points-v2";
+-		opp-shared;
+-
+-		opp-800000000 {
+-			opp-hz = /bits/ 64 <800000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1000000000 {
+-			opp-hz = /bits/ 64 <1000000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1300000000 {
+-			opp-hz = /bits/ 64 <1300000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-	};
+-
+ 	/* External PCIe clock - can be overridden by the board */
+ 	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+@@ -234,13 +234,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	pmu_a57 {
+-		compatible = "arm,cortex-a57-pmu";
+-		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-affinity = <&a57_0>, <&a57_1>;
+-	};
+-
+ 	pmu_a53 {
+ 		compatible = "arm,cortex-a53-pmu";
+ 		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+@@ -250,6 +243,13 @@
+ 		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ 	};
+ 
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>, <&a57_1>;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -2063,14 +2063,6 @@
+ 		};
+ 	};
+ 
+-	timer {
+-		compatible = "arm,armv8-timer";
+-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
+-
+ 	thermal-zones {
+ 		sensor_thermal1: sensor-thermal1 {
+ 			polling-delay-passive = <250>;
+@@ -2151,6 +2143,14 @@
+ 		};
+ 	};
+ 
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
+ 	/* External USB clocks - can be overridden by the board */
+ 	usb3s0_clk: usb3s0 {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1467-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-soc-n.patch b/patches/1467-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-soc-n.patch
new file mode 100644
index 00000000000000..df2e6034571301
--- /dev/null
+++ b/patches/1467-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-soc-n.patch
@@ -0,0 +1,2055 @@
+From 6fdeb4c2177b2af3a6c993a6033b671a08e2a638 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 23 Mar 2018 11:04:08 +0100
+Subject: [PATCH 1467/1795] arm64: dts: renesas: r8a7796: sort subnodes of the
+ soc node
+
+Sort subnodes of the soc node.
+- The primary key is the bus address.
+- The secondary key is the IP block.
+- The tertiary key is the node name.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3684a030bd0fded121bbce9af0d2126fe894d700)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 1824 +++++++++++-----------
+ 1 file changed, 912 insertions(+), 912 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 78fbb4fd34bf..55a64169d3d4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -269,23 +269,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		gic: interrupt-controller@f1010000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0x0 0xf1010000 0 0x1000>,
+-			      <0x0 0xf1020000 0 0x20000>,
+-			      <0x0 0xf1040000 0 0x20000>,
+-			      <0x0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9
+-					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		wdt0: watchdog@e6020000 {
+ 			compatible = "renesas,r8a7796-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -421,100 +404,6 @@
+ 			reg = <0 0xe6060000 0 0x50c>;
+ 		};
+ 
+-		ipmmu_vi0: mmu@febd0000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xfebd0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 9>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_vc0: mmu@fe6b0000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xfe6b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 8>;
+-			power-domains = <&sysc R8A7796_PD_A3VC>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_pv0: mmu@fd800000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xfd800000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 5>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_pv1: mmu@fd950000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xfd950000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 6>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_ir: mmu@ff8b0000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xff8b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 3>;
+-			power-domains = <&sysc R8A7796_PD_A3IR>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_hc: mmu@e6570000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xe6570000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 2>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 7>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_mp: mmu@ec670000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xec670000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 4>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_ds0: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 0>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_ds1: mmu@e7740000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xe7740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 1>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_mm: mmu@e67b0000 {
+-			compatible = "renesas,ipmmu-r8a7796";
+-			reg = <0 0xe67b0000 0 0x1000>;
+-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7796-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+@@ -530,17 +419,27 @@
+ 			reg = <0 0xe6160000 0 0x0200>;
+ 		};
+ 
+-		prr: chipid@fff00044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xfff00044 0 4>;
+-		};
+-
+ 		sysc: system-controller@e6180000 {
+ 			compatible = "renesas,r8a7796-sysc";
+ 			reg = <0 0xe6180000 0 0x0400>;
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		tsc: thermal@e6198000 {
++			compatible = "renesas,r8a7796-thermal";
++			reg = <0 0xe6198000 0 0x100>,
++			      <0 0xe61a0000 0 0x100>,
++			      <0 0xe61a8000 0 0x100>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <1>;
++			status = "okay";
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -557,92 +456,6 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		i2c_dvfs: i2c@e60b0000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7796",
+-				     "renesas,rcar-gen3-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe60b0000 0 0x425>;
+-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 926>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 926>;
+-			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+-			dma-names = "tx", "rx";
+-			status = "disabled";
+-		};
+-
+-		pwm0: pwm@e6e30000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e30000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm1: pwm@e6e31000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e31000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm2: pwm@e6e32000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e32000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm3: pwm@e6e33000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e33000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm4: pwm@e6e34000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e34000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm5: pwm@e6e35000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e35000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+-		pwm6: pwm@e6e36000 {
+-			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+-			reg = <0 0xe6e36000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			status = "disabled";
+-		};
+-
+ 		i2c0: i2c@e6500000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -758,226 +571,19 @@
+ 			status = "disabled";
+ 		};
+ 
+-		can0: can@e6c30000 {
+-			compatible = "renesas,can-r8a7796",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c30000 0 0x1000>;
+-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 916>,
+-			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
++		i2c_dvfs: i2c@e60b0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7796",
++				     "renesas,rcar-gen3-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 916>;
+-			status = "disabled";
+-		};
+-
+-		can1: can@e6c38000 {
+-			compatible = "renesas,can-r8a7796",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c38000 0 0x1000>;
+-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 915>,
+-			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
+-			status = "disabled";
+-		};
+-
+-		canfd: can@e66c0000 {
+-			compatible = "renesas,r8a7796-canfd",
+-				     "renesas,rcar-gen3-canfd";
+-			reg = <0 0xe66c0000 0 0x8000>;
+-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+-				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 914>,
+-			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "fck", "canfd", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 914>;
+-			status = "disabled";
+-
+-			channel0 {
+-				status = "disabled";
+-			};
+-
+-			channel1 {
+-				status = "disabled";
+-			};
+-		};
+-
+-		drif00: rif@e6f40000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f40000 0 0x64>;
+-			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 515>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 515>;
+-			renesas,bonding = <&drif01>;
+-			status = "disabled";
+-		};
+-
+-		drif01: rif@e6f50000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f50000 0 0x64>;
+-			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 514>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 514>;
+-			renesas,bonding = <&drif00>;
+-			status = "disabled";
+-		};
+-
+-		drif10: rif@e6f60000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f60000 0 0x64>;
+-			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 513>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 513>;
+-			renesas,bonding = <&drif11>;
+-			status = "disabled";
+-		};
+-
+-		drif11: rif@e6f70000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f70000 0 0x64>;
+-			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 512>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 512>;
+-			renesas,bonding = <&drif10>;
+-			status = "disabled";
+-		};
+-
+-		drif20: rif@e6f80000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f80000 0 0x64>;
+-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 511>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 511>;
+-			renesas,bonding = <&drif21>;
+-			status = "disabled";
+-		};
+-
+-		drif21: rif@e6f90000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f90000 0 0x64>;
+-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 510>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 510>;
+-			renesas,bonding = <&drif20>;
+-			status = "disabled";
+-		};
+-
+-		drif30: rif@e6fa0000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6fa0000 0 0x64>;
+-			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 509>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 509>;
+-			renesas,bonding = <&drif31>;
+-			status = "disabled";
+-		};
+-
+-		drif31: rif@e6fb0000 {
+-			compatible = "renesas,r8a7796-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6fb0000 0 0x64>;
+-			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 508>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+-			dma-names = "rx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 508>;
+-			renesas,bonding = <&drif30>;
+-			status = "disabled";
+-		};
+-
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7796",
+-				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14", "ch15",
+-					  "ch16", "ch17", "ch18", "ch19",
+-					  "ch20", "ch21", "ch22", "ch23",
+-					  "ch24";
+-			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			phy-mode = "rgmii";
+-			iommus = <&ipmmu_ds0 16>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 926>;
++			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
++			dma-names = "tx", "rx";
+ 			status = "disabled";
+ 		};
+ 
+@@ -1069,162 +675,61 @@
+ 			status = "disabled";
+ 		};
+ 
+-		scif0: serial@e6e60000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e60000 0 64>;
+-			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 207>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+-			       <&dmac2 0x51>, <&dmac2 0x50>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7796",
++				     "renesas,rcar-gen3-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			renesas,buswait = <11>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 207>;
++			resets = <&cpg 704>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif1: serial@e6e68000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e68000 0 64>;
+-			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 206>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+-			       <&dmac2 0x53>, <&dmac2 0x52>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7796-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 206>;
+-			status = "disabled";
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
+ 		};
+ 
+-		scif2: serial@e6e88000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e88000 0 64>;
+-			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 310>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 310>;
+-			status = "disabled";
+-		};
+-
+-		scif3: serial@e6c50000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6c50000 0 64>;
+-			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 204>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+-			dma-names = "tx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 204>;
+-			status = "disabled";
+-		};
+-
+-		scif4: serial@e6c40000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6c40000 0 64>;
+-			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 203>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+-			dma-names = "tx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 203>;
+-			status = "disabled";
+-		};
+-
+-		scif5: serial@e6f30000 {
+-			compatible = "renesas,scif-r8a7796",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6f30000 0 64>;
+-			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 202>,
+-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+-			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 202>;
+-			status = "disabled";
+-		};
+-
+-		msiof0: spi@e6e90000 {
+-			compatible = "renesas,msiof-r8a7796",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6e90000 0 0x0064>;
+-			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 211>;
+-			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+-			       <&dmac2 0x41>, <&dmac2 0x40>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 211>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		msiof1: spi@e6ea0000 {
+-			compatible = "renesas,msiof-r8a7796",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6ea0000 0 0x0064>;
+-			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 210>;
+-			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+-			       <&dmac2 0x43>, <&dmac2 0x42>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 210>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		msiof2: spi@e6c00000 {
+-			compatible = "renesas,msiof-r8a7796",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c00000 0 0x0064>;
+-			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 209>;
+-			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+-			dma-names = "tx", "rx";
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7796-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 209>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
+ 		};
+ 
+-		msiof3: spi@e6c10000 {
+-			compatible = "renesas,msiof-r8a7796",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c10000 0 0x0064>;
+-			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 208>;
+-			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+-			dma-names = "tx", "rx";
++		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a7796-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
++			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 208>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 328>;
++			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1354,304 +859,550 @@
+ 			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7796",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14", "ch15";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <16>;
+-			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
+-			       <&ipmmu_mp 2>, <&ipmmu_mp 3>,
+-			       <&ipmmu_mp 4>, <&ipmmu_mp 5>,
+-			       <&ipmmu_mp 6>, <&ipmmu_mp 7>,
+-			       <&ipmmu_mp 8>, <&ipmmu_mp 9>,
+-			       <&ipmmu_mp 10>, <&ipmmu_mp 11>,
+-			       <&ipmmu_mp 12>, <&ipmmu_mp 13>,
+-			       <&ipmmu_mp 14>, <&ipmmu_mp 15>;
++			#iommu-cells = <1>;
+ 		};
+ 
+-		audma1: dma-controller@ec720000 {
+-			compatible = "renesas,dmac-r8a7796",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec720000 0 0x10000>;
+-			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14", "ch15";
+-			clocks = <&cpg CPG_MOD 501>;
+-			clock-names = "fck";
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 501>;
+-			#dma-cells = <1>;
+-			dma-channels = <16>;
+-			iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
+-			       <&ipmmu_mp 18>, <&ipmmu_mp 19>,
+-			       <&ipmmu_mp 20>, <&ipmmu_mp 21>,
+-			       <&ipmmu_mp 22>, <&ipmmu_mp 23>,
+-			       <&ipmmu_mp 24>, <&ipmmu_mp 25>,
+-			       <&ipmmu_mp 26>, <&ipmmu_mp 27>,
+-			       <&ipmmu_mp 28>, <&ipmmu_mp 29>,
+-			       <&ipmmu_mp 30>, <&ipmmu_mp 31>;
++			#iommu-cells = <1>;
+ 		};
+ 
+-		usb_dmac0: dma-controller@e65a0000 {
+-			compatible = "renesas,r8a7796-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65a0000 0 0x100>;
+-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 330>;
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 330>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		usb_dmac1: dma-controller@e65b0000 {
+-			compatible = "renesas,r8a7796-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65b0000 0 0x100>;
+-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 331>;
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A7796_PD_A3IR>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 331>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
++			#iommu-cells = <1>;
+ 		};
+ 
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7796",
+-				     "renesas,rcar-gen3-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			renesas,buswait = <11>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
++		ipmmu_mp: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 5>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_pv1: mmu@fd950000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfd950000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 8>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a7796";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7796",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			iommus = <&ipmmu_ds0 16>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		can0: can@e6c30000 {
++			compatible = "renesas,can-r8a7796",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c30000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 916>;
++			status = "disabled";
++		};
++
++		can1: can@e6c38000 {
++			compatible = "renesas,can-r8a7796",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c38000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 915>;
++			status = "disabled";
++		};
++
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a7796-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e35000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
++			reg = <0 0xe6e36000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 206>;
++			status = "disabled";
++		};
++
++		scif2: serial@e6e88000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e88000 0 64>;
++			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 310>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 310>;
++			status = "disabled";
++		};
++
++		scif3: serial@e6c50000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 204>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
++			resets = <&cpg 204>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb3_phy0: usb-phy@e65ee000 {
+-			compatible = "renesas,r8a7796-usb3-phy",
+-				     "renesas,rcar-gen3-usb3-phy";
+-			reg = <0 0xe65ee000 0 0x90>;
+-			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+-				 <&usb_extal_clk>;
+-			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++		scif4: serial@e6c40000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 203>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 328>;
+-			#phy-cells = <0>;
++			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
+ 
+-		xhci0: usb@ee000000 {
+-			compatible = "renesas,xhci-r8a7796",
+-				     "renesas,rcar-gen3-xhci";
+-			reg = <0 0xee000000 0 0xc00>;
+-			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 328>;
++		scif5: serial@e6f30000 {
++			compatible = "renesas,scif-r8a7796",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6f30000 0 64>;
++			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 202>,
++				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
++			       <&dmac2 0x5b>, <&dmac2 0x5a>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 328>;
++			resets = <&cpg 202>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb3_peri0: usb@ee020000 {
+-			compatible = "renesas,r8a7796-usb3-peri",
+-				     "renesas,rcar-gen3-usb3-peri";
+-			reg = <0 0xee020000 0 0x400>;
+-			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 328>;
++		msiof0: spi@e6e90000 {
++			compatible = "renesas,msiof-r8a7796",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6e90000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 211>;
++			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
++			       <&dmac2 0x41>, <&dmac2 0x40>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 328>;
++			resets = <&cpg 211>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci0: usb@ee080000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee080000 0 0x100>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
++		msiof1: spi@e6ea0000 {
++			compatible = "renesas,msiof-r8a7796",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6ea0000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 210>;
++			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
++			       <&dmac2 0x43>, <&dmac2 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
++			resets = <&cpg 210>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		ehci0: usb@ee080100 {
+-			compatible = "generic-ehci";
+-			reg = <0 0xee080100 0 0x100>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
+-			companion= <&ohci0>;
++		msiof2: spi@e6c00000 {
++			compatible = "renesas,msiof-r8a7796",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 209>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
++			resets = <&cpg 209>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb2_phy0: usb-phy@ee080200 {
+-			compatible = "renesas,usb2-phy-r8a7796",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee080200 0 0x700>;
+-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 703>;
++		msiof3: spi@e6c10000 {
++			compatible = "renesas,msiof-r8a7796",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c10000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 703>;
+-			#phy-cells = <0>;
++			resets = <&cpg 208>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci1: usb@ee0a0000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee0a0000 0 0x100>;
+-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 702>;
+-			phys = <&usb2_phy1>;
+-			phy-names = "usb";
++		drif00: rif@e6f40000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f40000 0 0x64>;
++			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 515>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x20>, <&dmac2 0x20>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 702>;
++			resets = <&cpg 515>;
++			renesas,bonding = <&drif01>;
+ 			status = "disabled";
+ 		};
+ 
+-		ehci1: usb@ee0a0100 {
+-			compatible = "generic-ehci";
+-			reg = <0 0xee0a0100 0 0x100>;
+-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 702>;
+-			phys = <&usb2_phy1>;
+-			phy-names = "usb";
+-			companion= <&ohci1>;
++		drif01: rif@e6f50000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f50000 0 0x64>;
++			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 514>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x22>, <&dmac2 0x22>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 702>;
++			resets = <&cpg 514>;
++			renesas,bonding = <&drif00>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb2_phy1: usb-phy@ee0a0200 {
+-			compatible = "renesas,usb2-phy-r8a7796",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee0a0200 0 0x700>;
+-			clocks = <&cpg CPG_MOD 702>;
++		drif10: rif@e6f60000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f60000 0 0x64>;
++			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 513>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x24>, <&dmac2 0x24>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 702>;
+-			#phy-cells = <0>;
++			resets = <&cpg 513>;
++			renesas,bonding = <&drif11>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7796",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee100000 0 0x2000>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			max-frequency = <200000000>;
++		drif11: rif@e6f70000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f70000 0 0x64>;
++			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 512>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x26>, <&dmac2 0x26>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
++			resets = <&cpg 512>;
++			renesas,bonding = <&drif10>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi1: sd@ee120000 {
+-			compatible = "renesas,sdhi-r8a7796",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee120000 0 0x2000>;
+-			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 313>;
+-			max-frequency = <200000000>;
++		drif20: rif@e6f80000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f80000 0 0x64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 511>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x28>, <&dmac2 0x28>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 313>;
++			resets = <&cpg 511>;
++			renesas,bonding = <&drif21>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7796",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee140000 0 0x2000>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			max-frequency = <200000000>;
++		drif21: rif@e6f90000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f90000 0 0x64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 510>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
++			resets = <&cpg 510>;
++			renesas,bonding = <&drif20>;
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi3: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7796",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee160000 0 0x2000>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			max-frequency = <200000000>;
++		drif30: rif@e6fa0000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6fa0000 0 0x64>;
++			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 509>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
++			resets = <&cpg 509>;
++			renesas,bonding = <&drif31>;
+ 			status = "disabled";
+ 		};
+ 
+-		tsc: thermal@e6198000 {
+-			compatible = "renesas,r8a7796-thermal";
+-			reg = <0 0xe6198000 0 0x100>,
+-			      <0 0xe61a0000 0 0x100>,
+-			      <0 0xe61a8000 0 0x100>;
+-			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 522>;
++		drif31: rif@e6fb0000 {
++			compatible = "renesas,r8a7796-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6fb0000 0 0x64>;
++			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 508>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 522>;
+-			#thermal-sensor-cells = <1>;
+-			status = "okay";
++			resets = <&cpg 508>;
++			renesas,bonding = <&drif30>;
++			status = "disabled";
+ 		};
+ 
+ 		rcar_sound: sound@ec500000 {
+@@ -1796,58 +1547,302 @@
+ 				};
+ 			};
+ 
+-			rcar_sound,ssi {
+-				ssi0: ssi-0 {
+-					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi1: ssi-1 {
+-					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi2: ssi-2 {
+-					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi3: ssi-3 {
+-					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi4: ssi-4 {
+-					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi5: ssi-5 {
+-					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi6: ssi-6 {
+-					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi7: ssi-7 {
+-					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi8: ssi-8 {
+-					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-				ssi9: ssi-9 {
+-					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+-					dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+-					dma-names = "rx", "tx", "rxu", "txu";
+-				};
+-			};
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi1: ssi-1 {
++					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi2: ssi-2 {
++					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi3: ssi-3 {
++					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi4: ssi-4 {
++					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi5: ssi-5 {
++					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi6: ssi-6 {
++					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi7: ssi-7 {
++					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi8: ssi-8 {
++					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++				ssi9: ssi-9 {
++					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
++					dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
++					dma-names = "rx", "tx", "rxu", "txu";
++				};
++			};
++		};
++
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7796",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
++			       <&ipmmu_mp 2>, <&ipmmu_mp 3>,
++			       <&ipmmu_mp 4>, <&ipmmu_mp 5>,
++			       <&ipmmu_mp 6>, <&ipmmu_mp 7>,
++			       <&ipmmu_mp 8>, <&ipmmu_mp 9>,
++			       <&ipmmu_mp 10>, <&ipmmu_mp 11>,
++			       <&ipmmu_mp 12>, <&ipmmu_mp 13>,
++			       <&ipmmu_mp 14>, <&ipmmu_mp 15>;
++		};
++
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7796",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
++			       <&ipmmu_mp 18>, <&ipmmu_mp 19>,
++			       <&ipmmu_mp 20>, <&ipmmu_mp 21>,
++			       <&ipmmu_mp 22>, <&ipmmu_mp 23>,
++			       <&ipmmu_mp 24>, <&ipmmu_mp 25>,
++			       <&ipmmu_mp 26>, <&ipmmu_mp 27>,
++			       <&ipmmu_mp 28>, <&ipmmu_mp 29>,
++			       <&ipmmu_mp 30>, <&ipmmu_mp 31>;
++		};
++
++		xhci0: usb@ee000000 {
++			compatible = "renesas,xhci-r8a7796",
++				     "renesas,rcar-gen3-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
++		usb3_peri0: usb@ee020000 {
++			compatible = "renesas,r8a7796-usb3-peri",
++				     "renesas,rcar-gen3-usb3-peri";
++			reg = <0 0xee020000 0 0x400>;
++			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
++		ohci0: usb@ee080000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee080000 0 0x100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++		};
++
++		ohci1: usb@ee0a0000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee0a0000 0 0x100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 702>;
++			status = "disabled";
++		};
++
++		ehci0: usb@ee080100 {
++			compatible = "generic-ehci";
++			reg = <0 0xee080100 0 0x100>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			companion= <&ohci0>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			status = "disabled";
++		};
++
++		ehci1: usb@ee0a0100 {
++			compatible = "generic-ehci";
++			reg = <0 0xee0a0100 0 0x100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			companion= <&ohci1>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 702>;
++			status = "disabled";
++		};
++
++		usb2_phy0: usb-phy@ee080200 {
++			compatible = "renesas,usb2-phy-r8a7796",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee080200 0 0x700>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 703>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 703>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		usb2_phy1: usb-phy@ee0a0200 {
++			compatible = "renesas,usb2-phy-r8a7796",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee0a0200 0 0x700>;
++			clocks = <&cpg CPG_MOD 702>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 702>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee100000 0 0x2000>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee120000 {
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee120000 0 0x2000>;
++			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 313>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 313>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		sdhi3: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7796",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee160000 0 0x2000>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
+ 		};
+ 
+ 		pciec0: pcie@fe000000 {
+@@ -1860,6 +1855,26 @@
+ 			/* placeholder */
+ 		};
+ 
++		imr-lx4@fe860000 {
++			compatible = "renesas,r8a7796-imr-lx4",
++				     "renesas,imr-lx4";
++			reg = <0 0xfe860000 0 0x2000>;
++			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 823>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			resets = <&cpg 823>;
++		};
++
++		imr-lx4@fe870000 {
++			compatible = "renesas,r8a7796-imr-lx4",
++				     "renesas,imr-lx4";
++			reg = <0 0xfe870000 0 0x2000>;
++			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 822>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			resets = <&cpg 822>;
++		};
++
+ 		fdp1@fe940000 {
+ 			compatible = "renesas,fdp1";
+ 			reg = <0 0xfe940000 0 0x2400>;
+@@ -1878,17 +1893,6 @@
+ 			resets = <&cpg 615>;
+ 		};
+ 
+-		vspb: vsp@fe960000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe960000 0 0x8000>;
+-			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 626>;
+-			power-domains = <&sysc R8A7796_PD_A3VC>;
+-			resets = <&cpg 626>;
+-
+-			renesas,fcp = <&fcpvb0>;
+-		};
+-
+ 		fcpvb0: fcp@fe96f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe96f000 0 0x200>;
+@@ -1897,17 +1901,6 @@
+ 			resets = <&cpg 607>;
+ 		};
+ 
+-		vspi0: vsp@fe9a0000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe9a0000 0 0x8000>;
+-			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 631>;
+-			power-domains = <&sysc R8A7796_PD_A3VC>;
+-			resets = <&cpg 631>;
+-
+-			renesas,fcp = <&fcpvi0>;
+-		};
+-
+ 		fcpvi0: fcp@fe9af000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe9af000 0 0x200>;
+@@ -1917,6 +1910,44 @@
+ 			iommus = <&ipmmu_vc0 19>;
+ 		};
+ 
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
++		};
++
++		fcpvd1: fcp@fea2f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea2f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 602>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 602>;
++			iommus = <&ipmmu_vi0 9>;
++		};
++
++		fcpvd2: fcp@fea37000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea37000 0 0x200>;
++			clocks = <&cpg CPG_MOD 601>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 601>;
++			iommus = <&ipmmu_vi0 10>;
++		};
++
++		vspb: vsp@fe960000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe960000 0 0x8000>;
++			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 626>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			resets = <&cpg 626>;
++
++			renesas,fcp = <&fcpvb0>;
++		};
++
+ 		vspd0: vsp@fea20000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea20000 0 0x8000>;
+@@ -1928,15 +1959,6 @@
+ 			renesas,fcp = <&fcpvd0>;
+ 		};
+ 
+-		fcpvd0: fcp@fea27000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea27000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 603>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 603>;
+-			iommus = <&ipmmu_vi0 8>;
+-		};
+-
+ 		vspd1: vsp@fea28000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea28000 0 0x8000>;
+@@ -1948,15 +1970,6 @@
+ 			renesas,fcp = <&fcpvd1>;
+ 		};
+ 
+-		fcpvd1: fcp@fea2f000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea2f000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 602>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 602>;
+-			iommus = <&ipmmu_vi0 9>;
+-		};
+-
+ 		vspd2: vsp@fea30000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea30000 0 0x8000>;
+@@ -1968,13 +1981,15 @@
+ 			renesas,fcp = <&fcpvd2>;
+ 		};
+ 
+-		fcpvd2: fcp@fea37000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea37000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 601>;
+-			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+-			resets = <&cpg 601>;
+-			iommus = <&ipmmu_vi0 10>;
++		vspi0: vsp@fe9a0000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe9a0000 0 0x8000>;
++			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 631>;
++			power-domains = <&sysc R8A7796_PD_A3VC>;
++			resets = <&cpg 631>;
++
++			renesas,fcp = <&fcpvi0>;
+ 		};
+ 
+ 		hdmi0: hdmi@fead0000 {
+@@ -2042,24 +2057,9 @@
+ 			};
+ 		};
+ 
+-		imr-lx4@fe860000 {
+-			compatible = "renesas,r8a7796-imr-lx4",
+-				     "renesas,imr-lx4";
+-			reg = <0 0xfe860000 0 0x2000>;
+-			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 823>;
+-			power-domains = <&sysc R8A7796_PD_A3VC>;
+-			resets = <&cpg 823>;
+-		};
+-
+-		imr-lx4@fe870000 {
+-			compatible = "renesas,r8a7796-imr-lx4",
+-				     "renesas,imr-lx4";
+-			reg = <0 0xfe870000 0 0x2000>;
+-			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 822>;
+-			power-domains = <&sysc R8A7796_PD_A3VC>;
+-			resets = <&cpg 822>;
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1468-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-root-.patch b/patches/1468-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-root-.patch
new file mode 100644
index 00000000000000..bc4dfbc878d1f7
--- /dev/null
+++ b/patches/1468-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-root-.patch
@@ -0,0 +1,292 @@
+From 51ce2d369ed1463aa80f9cc5f7cb26179a732bde Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 23 Mar 2018 11:04:05 +0100
+Subject: [PATCH 1468/1795] arm64: dts: renesas: r8a7795: sort subnodes of the
+ root node
+
+Sort subnodes of the root node alphanumerically.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+Also remove excessive line-wrapping of interrupts-extended property of
+timer node.
+
+This should not have any run-time effect.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 82cf1d158ed6a0bd53b10e0eac4d8fd1b8f9c9e7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 218 +++++++++++------------
+ 1 file changed, 105 insertions(+), 113 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 1d5e3ac0231c..bb96c7e23370 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -30,6 +30,91 @@
+ 		i2c7 = &i2c_dvfs;
+ 	};
+ 
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	cluster0_opp: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1500000000 {
++			opp-hz = /bits/ 64 <1500000000>;
++			opp-microvolt = <830000>;
++			clock-latency-ns = <300000>;
++			opp-suspend;
++		};
++		opp-1600000000 {
++			opp-hz = /bits/ 64 <1600000000>;
++			opp-microvolt = <900000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++		opp-1700000000 {
++			opp-hz = /bits/ 64 <1700000000>;
++			opp-microvolt = <960000>;
++			clock-latency-ns = <300000>;
++			turbo-mode;
++		};
++	};
++
++	cluster1_opp: opp_table1 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-800000000 {
++			opp-hz = /bits/ 64 <800000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <820000>;
++			clock-latency-ns = <300000>;
++		};
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -155,91 +240,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_b: audio_clk_b {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External CAN clock - to be overridden by boards that provide it */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	cluster0_opp: opp_table0 {
+-		compatible = "operating-points-v2";
+-		opp-shared;
+-
+-		opp-500000000 {
+-			opp-hz = /bits/ 64 <500000000>;
+-			opp-microvolt = <830000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1000000000 {
+-			opp-hz = /bits/ 64 <1000000000>;
+-			opp-microvolt = <830000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1500000000 {
+-			opp-hz = /bits/ 64 <1500000000>;
+-			opp-microvolt = <830000>;
+-			clock-latency-ns = <300000>;
+-			opp-suspend;
+-		};
+-		opp-1600000000 {
+-			opp-hz = /bits/ 64 <1600000000>;
+-			opp-microvolt = <900000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-		opp-1700000000 {
+-			opp-hz = /bits/ 64 <1700000000>;
+-			opp-microvolt = <960000>;
+-			clock-latency-ns = <300000>;
+-			turbo-mode;
+-		};
+-	};
+-
+-	cluster1_opp: opp_table1 {
+-		compatible = "operating-points-v2";
+-		opp-shared;
+-
+-		opp-800000000 {
+-			opp-hz = /bits/ 64 <800000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1000000000 {
+-			opp-hz = /bits/ 64 <1000000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <820000>;
+-			clock-latency-ns = <300000>;
+-		};
+-	};
+-
+ 	/* External PCIe clock - can be overridden by the board */
+ 	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+@@ -247,18 +247,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	pmu_a57 {
+-		compatible = "arm,cortex-a57-pmu";
+-		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-		                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+-				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+-				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-affinity = <&a57_0>,
+-				     <&a57_1>,
+-				     <&a57_2>,
+-				     <&a57_3>;
+-	};
+-
+ 	pmu_a53 {
+ 		compatible = "arm,cortex-a53-pmu";
+ 		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+@@ -271,6 +259,18 @@
+ 				     <&a53_3>;
+ 	};
+ 
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++		                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>,
++				     <&a57_1>,
++				     <&a57_2>,
++				     <&a57_3>;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+@@ -2428,22 +2428,6 @@
+ 		};
+ 	};
+ 
+-	timer {
+-		compatible = "arm,armv8-timer";
+-		interrupts-extended = <&gic GIC_PPI 13
+-				       (GIC_CPU_MASK_SIMPLE(8) |
+-				       IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 14
+-				       (GIC_CPU_MASK_SIMPLE(8) |
+-				       IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 11
+-				       (GIC_CPU_MASK_SIMPLE(8) |
+-				       IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 10
+-				       (GIC_CPU_MASK_SIMPLE(8) |
+-				       IRQ_TYPE_LEVEL_LOW)>;
+-	};
+-
+ 	thermal-zones {
+ 		sensor_thermal1: sensor-thermal1 {
+ 			polling-delay-passive = <250>;
+@@ -2524,6 +2508,14 @@
+ 		};
+ 	};
+ 
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
+ 	/* External USB clocks - can be overridden by the board */
+ 	usb3s0_clk: usb3s0 {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1469-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-soc-n.patch b/patches/1469-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-soc-n.patch
new file mode 100644
index 00000000000000..c58fb81775618f
--- /dev/null
+++ b/patches/1469-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-soc-n.patch
@@ -0,0 +1,2274 @@
+From 11d3979051c3460ab7417469cc52abb961da64cb Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Fri, 23 Mar 2018 11:04:06 +0100
+Subject: [PATCH 1469/1795] arm64: dts: renesas: r8a7795: sort subnodes of the
+ soc node
+
+Sort subnodes of the soc node.
+- The primary key is the bus address.
+- The secondary key is the IP block.
+- The tertiary key is the node name.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit e0f0bda79337701a08141a6ec5417be96b12a265)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 1858 +++++++++++-----------
+ 1 file changed, 929 insertions(+), 929 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index bb96c7e23370..0e958ecd2a41 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -291,23 +291,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		gic: interrupt-controller@f1010000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0x0 0xf1010000 0 0x1000>,
+-			      <0x0 0xf1020000 0 0x20000>,
+-			      <0x0 0xf1040000 0 0x20000>,
+-			      <0x0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9
+-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		wdt0: watchdog@e6020000 {
+ 			compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
+ 			reg = <0 0xe6020000 0 0x0c>;
+@@ -437,6 +420,11 @@
+ 			resets = <&cpg 905>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a7795";
++			reg = <0 0xe6060000 0 0x50c>;
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a7795-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+@@ -452,20 +440,25 @@
+ 			reg = <0 0xe6160000 0 0x0200>;
+ 		};
+ 
+-		prr: chipid@fff00044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xfff00044 0 4>;
+-		};
+-
+ 		sysc: system-controller@e6180000 {
+ 			compatible = "renesas,r8a7795-sysc";
+ 			reg = <0 0xe6180000 0 0x0400>;
+ 			#power-domain-cells = <1>;
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a7795";
+-			reg = <0 0xe6060000 0 0x50c>;
++		tsc: thermal@e6198000 {
++			compatible = "renesas,r8a7795-thermal";
++			reg = <0 0xe6198000 0 0x100>,
++			      <0 0xe61a0000 0 0x100>,
++			      <0 0xe61a8000 0 0x100>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <1>;
++			status = "okay";
+ 		};
+ 
+ 		intc_ex: interrupt-controller@e61c0000 {
+@@ -484,153 +477,326 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		ipmmu_vi0: mmu@febd0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfebd0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 14>;
++		i2c0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6500000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 931>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+-		ipmmu_vi1: mmu@febe0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfebe0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 15>;
++		i2c1: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 930>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_vp0: mmu@fe990000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfe990000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 16>;
+-			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			#iommu-cells = <1>;
++		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6510000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_vp1: mmu@fe980000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfe980000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 17>;
+-			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_vc0: mmu@fe6b0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfe6b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 12>;
+-			power-domains = <&sysc R8A7795_PD_A3VC>;
+-			#iommu-cells = <1>;
++		i2c3: i2c@e66d0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d0000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_vc1: mmu@fe6f0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfe6f0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 13>;
+-			power-domains = <&sysc R8A7795_PD_A3VC>;
+-			#iommu-cells = <1>;
++		i2c4: i2c@e66d8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d8000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_pv0: mmu@fd800000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfd800000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 6>;
++		i2c5: i2c@e66e0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66e0000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 919>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 919>;
++			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_pv1: mmu@fd950000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfd950000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 7>;
++		i2c6: i2c@e66e8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7795",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66e8000 0 0x40>;
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 918>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 918>;
++			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_pv2: mmu@fd960000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfd960000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 8>;
++		i2c_dvfs: i2c@e60b0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a7795",
++				     "renesas,rcar-gen3-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 926>;
++			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
++			dma-names = "tx", "rx";
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_pv3: mmu@fd970000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xfd970000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 9>;
++		hscif0: serial@e6540000 {
++			compatible = "renesas,hscif-r8a7795",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6540000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 520>,
++				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
++			       <&dmac2 0x31>, <&dmac2 0x30>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 520>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_ir: mmu@ff8b0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xff8b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 3>;
+-			power-domains = <&sysc R8A7795_PD_A3IR>;
+-			#iommu-cells = <1>;
++		hscif1: serial@e6550000 {
++			compatible = "renesas,hscif-r8a7795",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6550000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 519>,
++				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
++			       <&dmac2 0x33>, <&dmac2 0x32>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 519>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_hc: mmu@e6570000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xe6570000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 2>;
++		hscif2: serial@e6560000 {
++			compatible = "renesas,hscif-r8a7795",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6560000 0 96>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 518>,
++				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
++			       <&dmac2 0x35>, <&dmac2 0x34>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 518>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 10>;
++		hscif3: serial@e66a0000 {
++			compatible = "renesas,hscif-r8a7795",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe66a0000 0 96>;
++			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 517>,
++				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 517>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_mp0: mmu@ec670000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xec670000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 4>;
++		hscif4: serial@e66b0000 {
++			compatible = "renesas,hscif-r8a7795",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe66b0000 0 96>;
++			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 516>,
++				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
++			dma-names = "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 516>;
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_ds0: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 0>;
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7795",
++				     "renesas,rcar-gen3-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			renesas,buswait = <11>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 704>;
++			status = "disabled";
+ 		};
+ 
+-		ipmmu_ds1: mmu@e7740000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xe7740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 1>;
++		hsusb3: usb@e659c000 {
++			compatible = "renesas,usbhs-r8a7795",
++				     "renesas,rcar-gen3-usbhs";
++			reg = <0 0xe659c000 0 0x100>;
++			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 705>;
++			dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
++			       <&usb_dmac3 0>, <&usb_dmac3 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			renesas,buswait = <11>;
++			phys = <&usb2_phy3>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 705>;
++			status = "disabled";
+ 		};
+ 
+-		ipmmu_mm: mmu@e67b0000 {
+-			compatible = "renesas,ipmmu-r8a7795";
+-			reg = <0 0xe67b0000 0 0x1000>;
+-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a7795-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a7795-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac2: dma-controller@e6460000 {
++			compatible = "renesas,r8a7795-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe6460000 0 0x100>;
++			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 326>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 326>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac3: dma-controller@e6470000 {
++			compatible = "renesas,r8a7795-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe6470000 0 0x100>;
++			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 329>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 329>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a7795-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
++			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 328>;
++			#phy-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		dmac0: dma-controller@e6700000 {
+@@ -759,460 +925,325 @@
+ 			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ 		};
+ 
+-		audma0: dma-controller@ec700000 {
+-			compatible = "renesas,dmac-r8a7795",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec700000 0 0x10000>;
+-			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14", "ch15";
+-			clocks = <&cpg CPG_MOD 502>;
+-			clock-names = "fck";
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 502>;
+-			#dma-cells = <1>;
+-			dma-channels = <16>;
+-			iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
+-			       <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
+-			       <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
+-			       <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
+-			       <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
+-			       <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
+-			       <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
+-			       <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
++			#iommu-cells = <1>;
+ 		};
+ 
+-		audma1: dma-controller@ec720000 {
+-			compatible = "renesas,dmac-r8a7795",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xec720000 0 0x10000>;
+-			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					"ch0", "ch1", "ch2", "ch3",
+-					"ch4", "ch5", "ch6", "ch7",
+-					"ch8", "ch9", "ch10", "ch11",
+-					"ch12", "ch13", "ch14", "ch15";
+-			clocks = <&cpg CPG_MOD 501>;
+-			clock-names = "fck";
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 501>;
+-			#dma-cells = <1>;
+-			dma-channels = <16>;
+-			iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
+-			       <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
+-			       <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
+-			       <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
+-			       <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
+-			       <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
+-			       <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
+-			       <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
++			#iommu-cells = <1>;
+ 		};
+ 
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a7795",
+-				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14", "ch15",
+-					  "ch16", "ch17", "ch18", "ch19",
+-					  "ch20", "ch21", "ch22", "ch23",
+-					  "ch24";
+-			clocks = <&cpg CPG_MOD 812>;
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			phy-mode = "rgmii";
+-			iommus = <&ipmmu_ds0 16>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		can0: can@e6c30000 {
+-			compatible = "renesas,can-r8a7795",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c30000 0 0x1000>;
+-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 916>,
+-			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 916>;
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A7795_PD_A3IR>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		can1: can@e6c38000 {
+-			compatible = "renesas,can-r8a7795",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c38000 0 0x1000>;
+-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 915>,
+-			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
+-			status = "disabled";
++			#iommu-cells = <1>;
+ 		};
+ 
+-		canfd: can@e66c0000 {
+-			compatible = "renesas,r8a7795-canfd",
+-				     "renesas,rcar-gen3-canfd";
+-			reg = <0 0xe66c0000 0 0x8000>;
+-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+-				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 914>,
+-			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "fck", "canfd", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
++		ipmmu_mp0: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 914>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+-
+-			channel0 {
+-				status = "disabled";
+-			};
+-
+-			channel1 {
+-				status = "disabled";
+-			};
+ 		};
+ 
+-		drif00: rif@e6f40000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f40000 0 0x64>;
+-			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 515>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+-			dma-names = "rx", "rx";
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 515>;
+-			renesas,bonding = <&drif01>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif01: rif@e6f50000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f50000 0 0x64>;
+-			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 514>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+-			dma-names = "rx", "rx";
++		ipmmu_pv1: mmu@fd950000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd950000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 514>;
+-			renesas,bonding = <&drif00>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif10: rif@e6f60000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f60000 0 0x64>;
+-			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 513>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+-			dma-names = "rx", "rx";
++		ipmmu_pv2: mmu@fd960000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd960000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 8>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 513>;
+-			renesas,bonding = <&drif11>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif11: rif@e6f70000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f70000 0 0x64>;
+-			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 512>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+-			dma-names = "rx", "rx";
++		ipmmu_pv3: mmu@fd970000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfd970000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 512>;
+-			renesas,bonding = <&drif10>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif20: rif@e6f80000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f80000 0 0x64>;
+-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 511>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+-			dma-names = "rx", "rx";
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 10>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 511>;
+-			renesas,bonding = <&drif21>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif21: rif@e6f90000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6f90000 0 0x64>;
+-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 510>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+-			dma-names = "rx", "rx";
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 12>;
++			power-domains = <&sysc R8A7795_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc1: mmu@fe6f0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe6f0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 13>;
++			power-domains = <&sysc R8A7795_PD_A3VC>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 14>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 510>;
+-			renesas,bonding = <&drif20>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_vi1: mmu@febe0000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfebe0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 15>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif30: rif@e6fa0000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6fa0000 0 0x64>;
+-			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 509>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+-			dma-names = "rx", "rx";
++		ipmmu_vp0: mmu@fe990000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe990000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 16>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vp1: mmu@fe980000 {
++			compatible = "renesas,ipmmu-r8a7795";
++			reg = <0 0xfe980000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 17>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			#iommu-cells = <1>;
++		};
++
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7795",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 509>;
+-			renesas,bonding = <&drif31>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			iommus = <&ipmmu_ds0 16>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		drif31: rif@e6fb0000 {
+-			compatible = "renesas,r8a7795-drif",
+-				     "renesas,rcar-gen3-drif";
+-			reg = <0 0xe6fb0000 0 0x64>;
+-			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 508>;
+-			clock-names = "fck";
+-			dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+-			dma-names = "rx", "rx";
++		can0: can@e6c30000 {
++			compatible = "renesas,can-r8a7795",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c30000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 508>;
+-			renesas,bonding = <&drif30>;
++			resets = <&cpg 916>;
+ 			status = "disabled";
+ 		};
+ 
+-		hscif0: serial@e6540000 {
+-			compatible = "renesas,hscif-r8a7795",
+-				     "renesas,rcar-gen3-hscif",
+-				     "renesas,hscif";
+-			reg = <0 0xe6540000 0 96>;
+-			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 520>,
+-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+-			       <&dmac2 0x31>, <&dmac2 0x30>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		can1: can@e6c38000 {
++			compatible = "renesas,can-r8a7795",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c38000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 520>;
++			resets = <&cpg 915>;
+ 			status = "disabled";
+ 		};
+ 
+-		hscif1: serial@e6550000 {
+-			compatible = "renesas,hscif-r8a7795",
+-				     "renesas,rcar-gen3-hscif",
+-				     "renesas,hscif";
+-			reg = <0 0xe6550000 0 96>;
+-			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 519>,
+-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+-			       <&dmac2 0x33>, <&dmac2 0x32>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a7795-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 519>;
++			resets = <&cpg 914>;
+ 			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
+ 		};
+ 
+-		hscif2: serial@e6560000 {
+-			compatible = "renesas,hscif-r8a7795",
+-				     "renesas,rcar-gen3-hscif",
+-				     "renesas,hscif";
+-			reg = <0 0xe6560000 0 96>;
+-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 518>,
+-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+-			       <&dmac2 0x35>, <&dmac2 0x34>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 518>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		hscif3: serial@e66a0000 {
+-			compatible = "renesas,hscif-r8a7795",
+-				     "renesas,rcar-gen3-hscif",
+-				     "renesas,hscif";
+-			reg = <0 0xe66a0000 0 96>;
+-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 517>,
+-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+-			dma-names = "tx", "rx";
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 517>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		hscif4: serial@e66b0000 {
+-			compatible = "renesas,hscif-r8a7795",
+-				     "renesas,rcar-gen3-hscif",
+-				     "renesas,hscif";
+-			reg = <0 0xe66b0000 0 96>;
+-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 516>,
+-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+-			dma-names = "tx", "rx";
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 516>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		msiof0: spi@e6e90000 {
+-			compatible = "renesas,msiof-r8a7795",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6e90000 0 0x0064>;
+-			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 211>;
+-			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+-			       <&dmac2 0x41>, <&dmac2 0x40>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 211>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		msiof1: spi@e6ea0000 {
+-			compatible = "renesas,msiof-r8a7795",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6ea0000 0 0x0064>;
+-			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 210>;
+-			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+-			       <&dmac2 0x43>, <&dmac2 0x42>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 210>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		msiof2: spi@e6c00000 {
+-			compatible = "renesas,msiof-r8a7795",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c00000 0 0x0064>;
+-			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 209>;
+-			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+-			dma-names = "tx", "rx";
++		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e35000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 209>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+-		msiof3: spi@e6c10000 {
+-			compatible = "renesas,msiof-r8a7795",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c10000 0 0x0064>;
+-			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 208>;
+-			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+-			dma-names = "tx", "rx";
++		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
++			reg = <0 0xe6e36000 0 0x8>;
++			clocks = <&cpg CPG_MOD 523>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 208>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 523>;
++			#pwm-cells = <2>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1316,204 +1347,185 @@
+ 			status = "disabled";
+ 		};
+ 
+-		i2c_dvfs: i2c@e60b0000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a7795",
+-				     "renesas,rcar-gen3-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe60b0000 0 0x425>;
+-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 926>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 926>;
+-			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+-			dma-names = "tx", "rx";
+-			status = "disabled";
+-		};
+-
+-		i2c0: i2c@e6500000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6500000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
+-			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+-			       <&dmac2 0x91>, <&dmac2 0x90>;
++		msiof0: spi@e6e90000 {
++			compatible = "renesas,msiof-r8a7795",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6e90000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 211>;
++			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
++			       <&dmac2 0x41>, <&dmac2 0x40>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <110>;
+-			status = "disabled";
+-		};
+-
+-		i2c1: i2c@e6508000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+-			       <&dmac2 0x93>, <&dmac2 0x92>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c2: i2c@e6510000 {
++			resets = <&cpg 211>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6510000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+-			       <&dmac2 0x95>, <&dmac2 0x94>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c3: i2c@e66d0000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe66d0000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
++		msiof1: spi@e6ea0000 {
++			compatible = "renesas,msiof-r8a7795",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6ea0000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 210>;
++			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
++			       <&dmac2 0x43>, <&dmac2 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+-			dma-names = "tx", "rx";
+-			i2c-scl-internal-delay-ns = <110>;
++			resets = <&cpg 210>;
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c4: i2c@e66d8000 {
++		msiof2: spi@e6c00000 {
++			compatible = "renesas,msiof-r8a7795",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 209>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 209>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe66d8000 0 0x40>;
+-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 927>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 927>;
+-			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+-			dma-names = "tx", "rx";
+-			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c5: i2c@e66e0000 {
++		msiof3: spi@e6c10000 {
++			compatible = "renesas,msiof-r8a7795",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c10000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 208>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe66e0000 0 0x40>;
+-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 919>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 919>;
+-			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+-			dma-names = "tx", "rx";
+-			i2c-scl-internal-delay-ns = <110>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c6: i2c@e66e8000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a7795",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe66e8000 0 0x40>;
+-			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 918>;
++		drif00: rif@e6f40000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f40000 0 0x64>;
++			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 515>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x20>, <&dmac2 0x20>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 918>;
+-			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+-			dma-names = "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 515>;
++			renesas,bonding = <&drif01>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm0: pwm@e6e30000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e30000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif01: rif@e6f50000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f50000 0 0x64>;
++			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 514>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x22>, <&dmac2 0x22>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 514>;
++			renesas,bonding = <&drif00>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm1: pwm@e6e31000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e31000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif10: rif@e6f60000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f60000 0 0x64>;
++			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 513>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x24>, <&dmac2 0x24>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 513>;
++			renesas,bonding = <&drif11>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm2: pwm@e6e32000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e32000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif11: rif@e6f70000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f70000 0 0x64>;
++			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 512>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x26>, <&dmac2 0x26>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 512>;
++			renesas,bonding = <&drif10>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm3: pwm@e6e33000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e33000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif20: rif@e6f80000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f80000 0 0x64>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 511>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x28>, <&dmac2 0x28>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 511>;
++			renesas,bonding = <&drif21>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm4: pwm@e6e34000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e34000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif21: rif@e6f90000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6f90000 0 0x64>;
++			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 510>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 510>;
++			renesas,bonding = <&drif20>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm5: pwm@e6e35000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e35000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif30: rif@e6fa0000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6fa0000 0 0x64>;
++			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 509>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 509>;
++			renesas,bonding = <&drif31>;
+ 			status = "disabled";
+ 		};
+ 
+-		pwm6: pwm@e6e36000 {
+-			compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
+-			reg = <0 0xe6e36000 0 0x8>;
+-			clocks = <&cpg CPG_MOD 523>;
++		drif31: rif@e6fb0000 {
++			compatible = "renesas,r8a7795-drif",
++				     "renesas,rcar-gen3-drif";
++			reg = <0 0xe6fb0000 0 0x64>;
++			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 508>;
++			clock-names = "fck";
++			dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
++			dma-names = "rx", "rx";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 523>;
+-			#pwm-cells = <2>;
++			resets = <&cpg 508>;
++			renesas,bonding = <&drif30>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1713,29 +1725,88 @@
+ 			};
+ 		};
+ 
+-		sata: sata@ee300000 {
+-			compatible = "renesas,sata-r8a7795",
+-				     "renesas,rcar-gen3-sata";
+-			reg = <0 0xee300000 0 0x200000>;
+-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 815>;
++		audma0: dma-controller@ec700000 {
++			compatible = "renesas,dmac-r8a7795",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec700000 0 0x10000>;
++			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 502>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 815>;
+-			status = "disabled";
+-			iommus = <&ipmmu_hc 2>;
++			resets = <&cpg 502>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
++			       <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
++			       <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
++			       <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
++			       <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
++			       <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
++			       <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
++			       <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
+ 		};
+ 
+-		usb3_phy0: usb-phy@e65ee000 {
+-			compatible = "renesas,r8a7795-usb3-phy",
+-				     "renesas,rcar-gen3-usb3-phy";
+-			reg = <0 0xe65ee000 0 0x90>;
+-			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+-				 <&usb_extal_clk>;
+-			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++		audma1: dma-controller@ec720000 {
++			compatible = "renesas,dmac-r8a7795",
++				     "renesas,rcar-dmac";
++			reg = <0 0xec720000 0 0x10000>;
++			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 501>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 328>;
+-			#phy-cells = <0>;
+-			status = "disabled";
++			resets = <&cpg 501>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
++			       <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
++			       <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
++			       <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
++			       <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
++			       <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
++			       <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
++			       <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
+@@ -1759,153 +1830,51 @@
+ 			status = "disabled";
+ 		};
+ 
+-		usb_dmac0: dma-controller@e65a0000 {
+-			compatible = "renesas,r8a7795-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65a0000 0 0x100>;
+-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 330>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 330>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		usb_dmac1: dma-controller@e65b0000 {
+-			compatible = "renesas,r8a7795-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65b0000 0 0x100>;
+-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 331>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 331>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		usb_dmac2: dma-controller@e6460000 {
+-			compatible = "renesas,r8a7795-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe6460000 0 0x100>;
+-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 326>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 326>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		usb_dmac3: dma-controller@e6470000 {
+-			compatible = "renesas,r8a7795-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe6470000 0 0x100>;
+-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 329>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 329>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		sdhi0: sd@ee100000 {
+-			compatible = "renesas,sdhi-r8a7795",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee100000 0 0x2000>;
+-			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 314>;
+-			max-frequency = <200000000>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 314>;
+-			status = "disabled";
+-		};
+-
+-		sdhi1: sd@ee120000 {
+-			compatible = "renesas,sdhi-r8a7795",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee120000 0 0x2000>;
+-			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 313>;
+-			max-frequency = <200000000>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 313>;
+-			status = "disabled";
+-		};
+-
+-		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a7795",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee140000 0 0x2000>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			max-frequency = <200000000>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
+-			status = "disabled";
+-		};
+-
+-		sdhi3: sd@ee160000 {
+-			compatible = "renesas,sdhi-r8a7795",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee160000 0 0x2000>;
+-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 311>;
+-			max-frequency = <200000000>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 311>;
+-			status = "disabled";
+-		};
+-
+-		usb2_phy0: usb-phy@ee080200 {
+-			compatible = "renesas,usb2-phy-r8a7795",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee080200 0 0x700>;
++		ohci0: usb@ee080000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee080000 0 0x100>;
+ 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 703>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+-			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb2_phy1: usb-phy@ee0a0200 {
+-			compatible = "renesas,usb2-phy-r8a7795",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee0a0200 0 0x700>;
++		ohci1: usb@ee0a0000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee0a0000 0 0x100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 702>;
+-			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb2_phy2: usb-phy@ee0c0200 {
+-			compatible = "renesas,usb2-phy-r8a7795",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee0c0200 0 0x700>;
++		ohci2: usb@ee0c0000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee0c0000 0 0x100>;
++			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 701>;
++			phys = <&usb2_phy2>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 701>;
+-			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		usb2_phy3: usb-phy@ee0e0200 {
+-			compatible = "renesas,usb2-phy-r8a7795",
+-				     "renesas,rcar-gen3-usb2-phy";
+-			reg = <0 0xee0e0200 0 0x700>;
++		ohci3: usb@ee0e0000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee0e0000 0 0x100>;
+ 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 700>;
++			phys = <&usb2_phy3>;
++			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 700>;
+-			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -1961,86 +1930,127 @@
+ 			status = "disabled";
+ 		};
+ 
+-		ohci0: usb@ee080000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee080000 0 0x100>;
++		usb2_phy0: usb-phy@ee080200 {
++			compatible = "renesas,usb2-phy-r8a7795",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee080200 0 0x700>;
+ 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 703>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
++			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci1: usb@ee0a0000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee0a0000 0 0x100>;
+-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++		usb2_phy1: usb-phy@ee0a0200 {
++			compatible = "renesas,usb2-phy-r8a7795",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee0a0200 0 0x700>;
+ 			clocks = <&cpg CPG_MOD 702>;
+-			phys = <&usb2_phy1>;
+-			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			resets = <&cpg 702>;
++			#phy-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci2: usb@ee0c0000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee0c0000 0 0x100>;
+-			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++		usb2_phy2: usb-phy@ee0c0200 {
++			compatible = "renesas,usb2-phy-r8a7795",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee0c0200 0 0x700>;
+ 			clocks = <&cpg CPG_MOD 701>;
+-			phys = <&usb2_phy2>;
+-			phy-names = "usb";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 701>;
++			resets = <&cpg 701>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		usb2_phy3: usb-phy@ee0e0200 {
++			compatible = "renesas,usb2-phy-r8a7795",
++				     "renesas,rcar-gen3-usb2-phy";
++			reg = <0 0xee0e0200 0 0x700>;
++			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 700>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 700>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee100000 0 0x2000>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
++		};
++
++		sdhi1: sd@ee120000 {
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee120000 0 0x2000>;
++			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 313>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 313>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci3: usb@ee0e0000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee0e0000 0 0x100>;
+-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 700>;
+-			phys = <&usb2_phy3>;
+-			phy-names = "usb";
++		sdhi3: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a7795",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee160000 0 0x2000>;
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			max-frequency = <200000000>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 700>;
++			resets = <&cpg 311>;
+ 			status = "disabled";
+ 		};
+ 
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7795",
+-				     "renesas,rcar-gen3-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			renesas,buswait = <11>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
++		sata: sata@ee300000 {
++			compatible = "renesas,sata-r8a7795",
++				     "renesas,rcar-gen3-sata";
++			reg = <0 0xee300000 0 0x200000>;
++			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 815>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 704>;
++			resets = <&cpg 815>;
+ 			status = "disabled";
++			iommus = <&ipmmu_hc 2>;
+ 		};
+ 
+-		hsusb3: usb@e659c000 {
+-			compatible = "renesas,usbhs-r8a7795",
+-				     "renesas,rcar-gen3-usbhs";
+-			reg = <0 0xe659c000 0 0x100>;
+-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 705>;
+-			dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
+-			       <&usb_dmac3 0>, <&usb_dmac3 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			renesas,buswait = <11>;
+-			phys = <&usb2_phy3>;
+-			phy-names = "usb";
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 705>;
+-			status = "disabled";
++			resets = <&cpg 408>;
+ 		};
+ 
+ 		pciec0: pcie@fe000000 {
+@@ -2137,24 +2147,24 @@
+ 			resets = <&cpg 820>;
+ 		};
+ 
+-		vspbc: vsp@fe920000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe920000 0 0x8000>;
+-			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 624>;
++		fdp1@fe940000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe940000 0 0x2400>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 119>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 624>;
+-
+-			renesas,fcp = <&fcpvb1>;
++			resets = <&cpg 119>;
++			renesas,fcp = <&fcpf0>;
+ 		};
+ 
+-		fcpvb1: fcp@fe92f000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfe92f000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 606>;
++		fdp1@fe944000 {
++			compatible = "renesas,fdp1";
++			reg = <0 0xfe944000 0 0x2400>;
++			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 118>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 606>;
+-			iommus = <&ipmmu_vp1 7>;
++			resets = <&cpg 118>;
++			renesas,fcp = <&fcpf1>;
+ 		};
+ 
+ 		fcpf0: fcp@fe950000 {
+@@ -2175,17 +2185,6 @@
+ 			iommus = <&ipmmu_vp1 1>;
+ 		};
+ 
+-		vspbd: vsp@fe960000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe960000 0 0x8000>;
+-			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 626>;
+-			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 626>;
+-
+-			renesas,fcp = <&fcpvb0>;
+-		};
+-
+ 		fcpvb0: fcp@fe96f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe96f000 0 0x200>;
+@@ -2195,15 +2194,13 @@
+ 			iommus = <&ipmmu_vp0 5>;
+ 		};
+ 
+-		vspi0: vsp@fe9a0000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe9a0000 0 0x8000>;
+-			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 631>;
++		fcpvb1: fcp@fe92f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfe92f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 606>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 631>;
+-
+-			renesas,fcp = <&fcpvi0>;
++			resets = <&cpg 606>;
++			iommus = <&ipmmu_vp1 7>;
+ 		};
+ 
+ 		fcpvi0: fcp@fe9af000 {
+@@ -2215,17 +2212,6 @@
+ 			iommus = <&ipmmu_vp0 8>;
+ 		};
+ 
+-		vspi1: vsp@fe9b0000 {
+-			compatible = "renesas,vsp2";
+-			reg = <0 0xfe9b0000 0 0x8000>;
+-			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 630>;
+-			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 630>;
+-
+-			renesas,fcp = <&fcpvi1>;
+-		};
+-
+ 		fcpvi1: fcp@fe9bf000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe9bf000 0 0x200>;
+@@ -2235,6 +2221,55 @@
+ 			iommus = <&ipmmu_vp1 9>;
+ 		};
+ 
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
++		};
++
++		fcpvd1: fcp@fea2f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea2f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 602>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 602>;
++			iommus = <&ipmmu_vi0 9>;
++		};
++
++		fcpvd2: fcp@fea37000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea37000 0 0x200>;
++			clocks = <&cpg CPG_MOD 601>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 601>;
++			iommus = <&ipmmu_vi1 10>;
++		};
++
++		vspbd: vsp@fe960000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe960000 0 0x8000>;
++			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 626>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			resets = <&cpg 626>;
++
++			renesas,fcp = <&fcpvb0>;
++		};
++
++		vspbc: vsp@fe920000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe920000 0 0x8000>;
++			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 624>;
++			power-domains = <&sysc R8A7795_PD_A3VP>;
++			resets = <&cpg 624>;
++
++			renesas,fcp = <&fcpvb1>;
++		};
++
+ 		vspd0: vsp@fea20000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea20000 0 0x8000>;
+@@ -2246,15 +2281,6 @@
+ 			renesas,fcp = <&fcpvd0>;
+ 		};
+ 
+-		fcpvd0: fcp@fea27000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea27000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 603>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 603>;
+-			iommus = <&ipmmu_vi0 8>;
+-		};
+-
+ 		vspd1: vsp@fea28000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea28000 0 0x8000>;
+@@ -2266,15 +2292,6 @@
+ 			renesas,fcp = <&fcpvd1>;
+ 		};
+ 
+-		fcpvd1: fcp@fea2f000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea2f000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 602>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 602>;
+-			iommus = <&ipmmu_vi0 9>;
+-		};
+-
+ 		vspd2: vsp@fea30000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea30000 0 0x8000>;
+@@ -2286,33 +2303,26 @@
+ 			renesas,fcp = <&fcpvd2>;
+ 		};
+ 
+-		fcpvd2: fcp@fea37000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea37000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 601>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 601>;
+-			iommus = <&ipmmu_vi1 10>;
+-		};
+-
+-		fdp1@fe940000 {
+-			compatible = "renesas,fdp1";
+-			reg = <0 0xfe940000 0 0x2400>;
+-			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 119>;
++		vspi0: vsp@fe9a0000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe9a0000 0 0x8000>;
++			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 631>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 119>;
+-			renesas,fcp = <&fcpf0>;
++			resets = <&cpg 631>;
++
++			renesas,fcp = <&fcpvi0>;
+ 		};
+ 
+-		fdp1@fe944000 {
+-			compatible = "renesas,fdp1";
+-			reg = <0 0xfe944000 0 0x2400>;
+-			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 118>;
++		vspi1: vsp@fe9b0000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe9b0000 0 0x8000>;
++			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 630>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+-			resets = <&cpg 118>;
+-			renesas,fcp = <&fcpf1>;
++			resets = <&cpg 630>;
++
++			renesas,fcp = <&fcpvi1>;
+ 		};
+ 
+ 		hdmi0: hdmi@fead0000 {
+@@ -2412,19 +2422,9 @@
+ 			};
+ 		};
+ 
+-		tsc: thermal@e6198000 {
+-			compatible = "renesas,r8a7795-thermal";
+-			reg = <0 0xe6198000 0 0x100>,
+-			      <0 0xe61a0000 0 0x100>,
+-			      <0 0xe61a8000 0 0x100>;
+-			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 522>;
+-			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+-			resets = <&cpg 522>;
+-			#thermal-sensor-cells = <1>;
+-			status = "okay";
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1470-arm64-dts-renesas-r8a77965-Add-all-MSIOF-device-node.patch b/patches/1470-arm64-dts-renesas-r8a77965-Add-all-MSIOF-device-node.patch
new file mode 100644
index 00000000000000..949cc4d175061c
--- /dev/null
+++ b/patches/1470-arm64-dts-renesas-r8a77965-Add-all-MSIOF-device-node.patch
@@ -0,0 +1,100 @@
+From 476f09a8b9c4a6925ae02788ddf29f31e954bee4 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 23 Mar 2018 10:19:09 +0100
+Subject: [PATCH 1470/1795] arm64: dts: renesas: r8a77965: Add all MSIOF device
+ nodes
+
+Add the device nodes for all MSIOF SPI controllers.
+
+Based on several similar patches of the R8A7796 device tree
+by Geert Uytterhoeven <geert+renesas@glider.be>
+and Simon Horman <horms+renesas@verge.net.au>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[geert: Use numerical power domain indices for initial r8a77965.dtsi]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 93b0e5643a684ff0843b9d0222eae168838b2ffa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 62 +++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 6f748e94a901..4371be3e869a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -805,6 +805,68 @@
+ 			/* placeholder */
+ 		};
+ 
++		msiof0: spi@e6e90000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6e90000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 211>;
++			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
++			       <&dmac2 0x41>, <&dmac2 0x40>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 211>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof1: spi@e6ea0000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6ea0000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 210>;
++			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
++			       <&dmac2 0x43>, <&dmac2 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 210>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof2: spi@e6c00000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 209>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 209>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		msiof3: spi@e6c10000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c10000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 208>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		du: display@feb00000 {
+ 			reg = <0 0xfeb00000 0 0x80000>,
+ 			      <0 0xfeb90000 0 0x14>;
+-- 
+2.19.0
+
diff --git a/patches/1471-arm64-dts-renesas-r8a77965-Add-PWM-device-nodes.patch b/patches/1471-arm64-dts-renesas-r8a77965-Add-PWM-device-nodes.patch
new file mode 100644
index 00000000000000..54c4a412039b43
--- /dev/null
+++ b/patches/1471-arm64-dts-renesas-r8a77965-Add-PWM-device-nodes.patch
@@ -0,0 +1,104 @@
+From d29433ccd2ae97fec28e8ddfb34d85a6a53f9f86 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 23 Mar 2018 20:32:51 +0900
+Subject: [PATCH 1471/1795] arm64: dts: renesas: r8a77965: Add PWM device nodes
+
+This patch adds PWM device nodes for r8a77965.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e3ddf00f87d998e81ac1e5c925145c24bb10411d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 48 +++++++++++++++++++----
+ 1 file changed, 41 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 4371be3e869a..a41f91653d93 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -770,39 +770,73 @@
+ 		};
+ 
+ 		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e30000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e31000 0 8>;
+ 			#pwm-cells = <2>;
+-			/* placeholder */
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e32000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e33000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e34000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e35000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+ 			reg = <0 0xe6e36000 0 8>;
+-			/* placeholder */
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
+ 		};
+ 
+ 		msiof0: spi@e6e90000 {
+-- 
+2.19.0
+
diff --git a/patches/1472-arm64-dts-renesas-r8a77970-add-FCPVD-support.patch b/patches/1472-arm64-dts-renesas-r8a77970-add-FCPVD-support.patch
new file mode 100644
index 00000000000000..91a900854cc29d
--- /dev/null
+++ b/patches/1472-arm64-dts-renesas-r8a77970-add-FCPVD-support.patch
@@ -0,0 +1,48 @@
+From 49a9f9ca549d9459feb6bded412dfb20b651caa6 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 6 Apr 2018 15:08:06 +0200
+Subject: [PATCH 1472/1795] arm64: dts: renesas: r8a77970: add FCPVD support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Describe FCPVD0 in the R8A77970 device tree; it will be used by VSPD0 in
+the next patch...
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit faa5c3176a67ed53a5bfefdf8b5e91dab9785d0d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index e8358d9bfd66..71f466daa036 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -617,6 +617,14 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
++
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1473-arm64-defconfig-makes-SND_SIMPLE_CARD-to-module.patch b/patches/1473-arm64-defconfig-makes-SND_SIMPLE_CARD-to-module.patch
new file mode 100644
index 00000000000000..7af6d8a1e03461
--- /dev/null
+++ b/patches/1473-arm64-defconfig-makes-SND_SIMPLE_CARD-to-module.patch
@@ -0,0 +1,30 @@
+From 20a20803606982e0d210fe29c6fbbacca80a7661 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Thu, 26 Apr 2018 07:13:54 +0000
+Subject: [PATCH 1473/1795] arm64: defconfig: makes SND_SIMPLE_CARD to module
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 93f7bfd930c04039288db0a6bc46596aad5bd8b9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 3b93432ee64f..39b23ccf392a 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -441,7 +441,7 @@ CONFIG_SND_BCM2835_SOC_I2S=m
+ CONFIG_SND_SOC_SAMSUNG=y
+ CONFIG_SND_SOC_RCAR=m
+ CONFIG_SND_SOC_AK4613=m
+-CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_SIMPLE_CARD=m
+ CONFIG_USB=y
+ CONFIG_USB_OTG=y
+ CONFIG_USB_XHCI_HCD=y
+-- 
+2.19.0
+
diff --git a/patches/1474-arm64-defconfig-Enable-CONFIG_SND_AUDIO_GRAPH_CARD.patch b/patches/1474-arm64-defconfig-Enable-CONFIG_SND_AUDIO_GRAPH_CARD.patch
new file mode 100644
index 00000000000000..6df71a5d064483
--- /dev/null
+++ b/patches/1474-arm64-defconfig-Enable-CONFIG_SND_AUDIO_GRAPH_CARD.patch
@@ -0,0 +1,32 @@
+From 445a56fbc79826a16490dc4dddcfe833dcbeacd0 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Thu, 26 Apr 2018 07:14:14 +0000
+Subject: [PATCH 1474/1795] arm64: defconfig: Enable
+ CONFIG_SND_AUDIO_GRAPH_CARD
+
+CONFIG_SND_AUDIO_GRAPH_CARD is needed to use HDMI sound with video
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit ddf3fa8b8a16e076f247c115a73356b4b0d83a33)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 39b23ccf392a..dd8f608074c3 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -442,6 +442,7 @@ CONFIG_SND_SOC_SAMSUNG=y
+ CONFIG_SND_SOC_RCAR=m
+ CONFIG_SND_SOC_AK4613=m
+ CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
+ CONFIG_USB=y
+ CONFIG_USB_OTG=y
+ CONFIG_USB_XHCI_HCD=y
+-- 
+2.19.0
+
diff --git a/patches/1475-arm64-dts-renesas-r8a7795-decrease-temperature-hyste.patch b/patches/1475-arm64-dts-renesas-r8a7795-decrease-temperature-hyste.patch
new file mode 100644
index 00000000000000..18ab799518f331
--- /dev/null
+++ b/patches/1475-arm64-dts-renesas-r8a7795-decrease-temperature-hyste.patch
@@ -0,0 +1,74 @@
+From b686ac09dbf6e3c186d8aebb380790e3f3137418 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 17 Apr 2018 22:54:27 +0200
+Subject: [PATCH 1475/1795] arm64: dts: renesas: r8a7795: decrease temperature
+ hysteresis
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To incorporate more tests by the hardware team decrease the hysteresis
+value to 1C.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 02f15e4be78610fbde26aa182ff147f2cc8d2e77)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 0e958ecd2a41..acf0c6f72a4d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2437,12 +2437,12 @@
+ 			trips {
+ 				sensor1_passive: sensor1-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor1_crit: sensor1-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+@@ -2463,12 +2463,12 @@
+ 			trips {
+ 				sensor2_passive: sensor2-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor2_crit: sensor2-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+@@ -2489,12 +2489,12 @@
+ 			trips {
+ 				sensor3_passive: sensor3-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor3_crit: sensor3-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1476-arm64-dts-renesas-r8a7796-decrease-temperature-hyste.patch b/patches/1476-arm64-dts-renesas-r8a7796-decrease-temperature-hyste.patch
new file mode 100644
index 00000000000000..db23eb75bf3ee7
--- /dev/null
+++ b/patches/1476-arm64-dts-renesas-r8a7796-decrease-temperature-hyste.patch
@@ -0,0 +1,74 @@
+From e5ddd815dd7956e8e492edaae5a6b40f0eb3d37b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 17 Apr 2018 22:54:28 +0200
+Subject: [PATCH 1476/1795] arm64: dts: renesas: r8a7796: decrease temperature
+ hysteresis
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To incorporate more tests by the hardware team decrease the hysteresis
+value to 1C.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1f153093b0bb6a9b46cb410ee3535d990348a2b3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 55a64169d3d4..e6254711556c 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -2072,12 +2072,12 @@
+ 			trips {
+ 				sensor1_passive: sensor1-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor1_crit: sensor1-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+@@ -2098,12 +2098,12 @@
+ 			trips {
+ 				sensor2_passive: sensor2-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor2_crit: sensor2-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+@@ -2124,12 +2124,12 @@
+ 			trips {
+ 				sensor3_passive: sensor3-passive {
+ 					temperature = <95000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "passive";
+ 				};
+ 				sensor3_crit: sensor3-crit {
+ 					temperature = <120000>;
+-					hysteresis = <2000>;
++					hysteresis = <1000>;
+ 					type = "critical";
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1477-arm64-dts-renesas-r8a77970-add-VSPD-support.patch b/patches/1477-arm64-dts-renesas-r8a77970-add-VSPD-support.patch
new file mode 100644
index 00000000000000..683b36246d500a
--- /dev/null
+++ b/patches/1477-arm64-dts-renesas-r8a77970-add-VSPD-support.patch
@@ -0,0 +1,51 @@
+From 4519a622fd0c62bda87366e8acfe580b3b52a332 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 12 Apr 2018 10:13:58 +0200
+Subject: [PATCH 1477/1795] arm64: dts: renesas: r8a77970: add VSPD support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Describe VSPD0 in the R8A77970 device tree; it will be used by DU in
+the next patch...
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b4f92030d5d39df427e72ace7f7db04dc8b35ddb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 71f466daa036..9a7cf2ab099e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -625,6 +625,16 @@
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			resets = <&cpg 603>;
+ 		};
++
++		vspd0: vsp@fea20000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea20000 0 0x8000>;
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 623>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 623>;
++			renesas,fcp = <&fcpvd0>;
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1478-arm64-dts-renesas-r8a77970-add-DU-support.patch b/patches/1478-arm64-dts-renesas-r8a77970-add-DU-support.patch
new file mode 100644
index 00000000000000..2f53200d131277
--- /dev/null
+++ b/patches/1478-arm64-dts-renesas-r8a77970-add-DU-support.patch
@@ -0,0 +1,64 @@
+From 8d40fa7f5e30dc7c845dced8eb7f7fd2136d531a Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 12 Apr 2018 10:13:59 +0200
+Subject: [PATCH 1478/1795] arm64: dts: renesas: r8a77970: add DU support
+
+Define the generic R8A77970 part of the DU device node.
+
+Based on the original (and large) patch by Daisuke Matsushita
+<daisuke.matsushita.ns@hitachi.com>.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f66598b95dbac72365f5b81ffa61ca6357af6b22)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 29 +++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 9a7cf2ab099e..8efb5c3a5da1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -635,6 +635,35 @@
+ 			resets = <&cpg 623>;
+ 			renesas,fcp = <&fcpvd0>;
+ 		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a77970";
++			reg = <0 0xfeb00000 0 0x80000>;
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>;
++			clock-names = "du.0";
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 724>;
++			vsps = <&vspd0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_rgb: endpoint {
++					};
++				};
++
++				port@1 {
++					reg = <1>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1479-arm64-dts-renesas-r8a77970-add-LVDS-support.patch b/patches/1479-arm64-dts-renesas-r8a77970-add-LVDS-support.patch
new file mode 100644
index 00000000000000..eb0c47e4b2f64c
--- /dev/null
+++ b/patches/1479-arm64-dts-renesas-r8a77970-add-LVDS-support.patch
@@ -0,0 +1,58 @@
+From 9a3b92c40b581902e9fb8baae7a69bab512d7eb3 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 12 Apr 2018 10:14:00 +0200
+Subject: [PATCH 1479/1795] arm64: dts: renesas: r8a77970: add LVDS support
+
+Define the generic R8A77970 part of the LVDS device node.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3cd0bd7d92bb54dc224e23dcb2cc319ff83b7b73)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 28 +++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 8efb5c3a5da1..a194cb8d7d62 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -660,6 +660,34 @@
+ 				port@1 {
+ 					reg = <1>;
+ 					du_out_lvds0: endpoint {
++						remote-endpoint = <&lvds0_in>;
++					};
++				};
++			};
++		};
++
++		lvds0: lvds-encoder@feb90000 {
++			compatible = "renesas,r8a77970-lvds";
++			reg = <0 0xfeb90000 0 0x14>;
++			clocks = <&cpg CPG_MOD 727>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 727>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					lvds0_in: endpoint {
++						remote-endpoint =
++							<&du_out_lvds0>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++					lvds0_out: endpoint {
+ 					};
+ 				};
+ 			};
+-- 
+2.19.0
+
diff --git a/patches/1480-arm64-dts-renesas-eagle-Enable-HDMI-output.patch b/patches/1480-arm64-dts-renesas-eagle-Enable-HDMI-output.patch
new file mode 100644
index 00000000000000..6e388bc3154347
--- /dev/null
+++ b/patches/1480-arm64-dts-renesas-eagle-Enable-HDMI-output.patch
@@ -0,0 +1,146 @@
+From 3a06d8c15a1510297339d86a5aa41c6018788660 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 12 Apr 2018 10:14:01 +0200
+Subject: [PATCH 1480/1795] arm64: dts: renesas: eagle: Enable HDMI output
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enable HDMI output on Renesas R-Car V3M Eagle board.
+
+The HDMI output is enabled connecting the DU LVDS output to the
+transparent LVDS converter THC63LVD1024, and successively routing its
+RGB output to the ADV7511W HDMI encoder.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+[for THC63LVD1024: ]
+Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 3c3d1672664aff2f7f938d2d206e47cecdf6b4ef)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 93 +++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index 3c5f598c9766..ebfbb51ab168 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -31,6 +31,51 @@
+ 		/* first 128MB is reserved for secure area. */
+ 		reg = <0x0 0x48000000 0x0 0x38000000>;
+ 	};
++
++	hdmi-out {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_out: endpoint {
++				remote-endpoint = <&adv7511_out>;
++			};
++		};
++	};
++
++	d3p3: regulator-fixed {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	lvds-decoder {
++		compatible = "thine,thc63lvd1024";
++
++		vcc-supply = <&d3p3>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				thc63lvd1024_in: endpoint {
++					remote-endpoint = <&lvds0_out>;
++				};
++			};
++
++			port@2 {
++				reg = <2>;
++				thc63lvd1024_out: endpoint {
++					remote-endpoint = <&adv7511_in>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &avb {
+@@ -68,6 +113,38 @@
+ 		gpio-controller;
+ 		#gpio-cells = <2>;
+ 	};
++
++	hdmi@39 {
++		compatible = "adi,adv7511w";
++		reg = <0x39>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
++
++		adi,input-depth = <8>;
++		adi,input-colorspace = "rgb";
++		adi,input-clock = "1x";
++		adi,input-style = <1>;
++		adi,input-justification = "evenly";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7511_in: endpoint {
++					remote-endpoint = <&thc63lvd1024_out>;
++				};
++			};
++
++			port@1 {
++				reg = <1>;
++				adv7511_out: endpoint {
++					remote-endpoint = <&hdmi_con_out>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &pfc {
+@@ -93,3 +170,19 @@
+ 
+ 	status = "okay";
+ };
++
++&du {
++	status = "okay";
++};
++
++&lvds0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			lvds0_out: endpoint {
++				remote-endpoint = <&thc63lvd1024_in>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1481-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-root.patch b/patches/1481-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-root.patch
new file mode 100644
index 00000000000000..4bb6e4027dd02d
--- /dev/null
+++ b/patches/1481-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-root.patch
@@ -0,0 +1,68 @@
+From 9994eade777ea4294d54f60aeef46b761a243aed Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Thu, 19 Apr 2018 05:14:36 +0900
+Subject: [PATCH 1481/1795] arm64: dts: renesas: r8a77995: sort subnodes of the
+ root node
+
+Sort subnodes of the root node alphanumerically.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 21559e2b0448cb43e880d46b1381008dc5e9707d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index 82aed7ee984c..cf476556504a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -18,9 +18,11 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+-	psci {
+-		compatible = "arm,psci-1.0", "arm,psci-0.2";
+-		method = "smc";
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
+ 	};
+ 
+ 	cpus {
+@@ -51,18 +53,16 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* External CAN clock - to be overridden by boards that provide it */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+ 	pmu_a53 {
+ 		compatible = "arm,cortex-a53-pmu";
+ 		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
++	};
++
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+-- 
+2.19.0
+
diff --git a/patches/1482-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-soc-.patch b/patches/1482-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-soc-.patch
new file mode 100644
index 00000000000000..b693d070a5a55d
--- /dev/null
+++ b/patches/1482-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-soc-.patch
@@ -0,0 +1,871 @@
+From 6bac2cf8dd6ccc4ad8223ea019feeb3365522f0f Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Thu, 19 Apr 2018 05:14:37 +0900
+Subject: [PATCH 1482/1795] arm64: dts: renesas: r8a77995: sort subnodes of the
+ soc node
+
+Sort subnodes of the soc node.
+- The primary key is the bus address.
+- The secondary key is the IP block.
+- The tertiary key is the node name.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7c55747fbe82237b4e22eaae3673e7d166c175d6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 697 +++++++++++-----------
+ 1 file changed, 348 insertions(+), 349 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index cf476556504a..a97830589b0d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -76,23 +76,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		gic: interrupt-controller@f1010000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0x0 0xf1010000 0 0x1000>,
+-			      <0x0 0xf1020000 0 0x20000>,
+-			      <0x0 0xf1040000 0 0x20000>,
+-			      <0x0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9
+-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		rwdt: watchdog@e6020000 {
+ 			compatible = "renesas,r8a77995-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -103,88 +86,123 @@
+ 			status = "disabled";
+ 		};
+ 
+-		ipmmu_vi0: mmu@febd0000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xfebd0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 14>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_vp0: mmu@fe990000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xfe990000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 16>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_vc0: mmu@fe6b0000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xfe6b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 12>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 9>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 912>;
+ 		};
+ 
+-		ipmmu_pv0: mmu@fd800000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xfd800000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 6>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 911>;
+ 		};
+ 
+-		ipmmu_hc: mmu@e6570000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xe6570000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 2>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 910>;
+ 		};
+ 
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 10>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 10>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 909>;
+ 		};
+ 
+-		ipmmu_mp: mmu@ec670000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xec670000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 4>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 32>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 908>;
+ 		};
+ 
+-		ipmmu_ds0: mmu@e6740000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xe6740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 0>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 21>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 907>;
+ 		};
+ 
+-		ipmmu_ds1: mmu@e7740000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xe7740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 1>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a77995",
++				     "renesas,rcar-gen3-gpio",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 14>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 906>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 906>;
+ 		};
+ 
+-		ipmmu_mm: mmu@e67b0000 {
+-			compatible = "renesas,ipmmu-r8a77995";
+-			reg = <0 0xe67b0000 0 0x1000>;
+-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77995";
++			reg = <0 0xe6060000 0 0x508>;
+ 		};
+ 
+-
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a77995-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+@@ -200,16 +218,6 @@
+ 			reg = <0 0xe6160000 0 0x0200>;
+ 		};
+ 
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a77995";
+-			reg = <0 0xe6060000 0 0x508>;
+-		};
+-
+-		prr: chipid@fff00044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xfff00044 0 4>;
+-		};
+-
+ 		sysc: system-controller@e6180000 {
+ 			compatible = "renesas,r8a77995-sysc";
+ 			reg = <0 0xe6180000 0 0x0400>;
+@@ -232,6 +240,98 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		i2c0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6500000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe6510000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e66d0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77995",
++				     "renesas,rcar-gen3-i2c";
++			reg = <0 0xe66d0000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a77995-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
+ 		dmac0: dma-controller@e6700000 {
+ 			compatible = "renesas,dmac-r8a77995",
+ 				     "renesas,rcar-dmac";
+@@ -304,173 +404,85 @@
+ 			dma-channels = <8>;
+ 		};
+ 
+-		gpio0: gpio@e6050000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6050000 0 0x50>;
+-			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 0 9>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 912>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 912>;
+-		};
+-
+-		gpio1: gpio@e6051000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6051000 0 0x50>;
+-			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 32 32>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 911>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 911>;
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe6740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		gpio2: gpio@e6052000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6052000 0 0x50>;
+-			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 64 32>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 910>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 910>;
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 1>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		gpio3: gpio@e6053000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6053000 0 0x50>;
+-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 96 10>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 909>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 909>;
++		ipmmu_hc: mmu@e6570000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe6570000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 2>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		gpio4: gpio@e6054000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6054000 0 0x50>;
+-			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 128 32>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 908>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 908>;
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		gpio5: gpio@e6055000 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6055000 0 0x50>;
+-			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 160 21>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 907>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 907>;
++		ipmmu_mp: mmu@ec670000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xec670000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 4>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		gpio6: gpio@e6055400 {
+-			compatible = "renesas,gpio-r8a77995",
+-				     "renesas,rcar-gen3-gpio",
+-				     "renesas,gpio-rcar";
+-			reg = <0 0xe6055400 0 0x50>;
+-			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+-			#gpio-cells = <2>;
+-			gpio-controller;
+-			gpio-ranges = <&pfc 0 192 14>;
+-			#interrupt-cells = <2>;
+-			interrupt-controller;
+-			clocks = <&cpg CPG_MOD 906>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 906>;
++		ipmmu_pv0: mmu@fd800000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfd800000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 6>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+-		can0: can@e6c30000 {
+-			compatible = "renesas,can-r8a77995",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c30000 0 0x1000>;
+-			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 916>,
+-			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 916>;
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 10>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		can1: can@e6c38000 {
+-			compatible = "renesas,can-r8a77995",
+-				     "renesas,rcar-gen3-can";
+-			reg = <0 0xe6c38000 0 0x1000>;
+-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 915>,
+-			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "clkp1", "clkp2", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 915>;
++		ipmmu_vc0: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfe6b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 12>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
+ 		};
+ 
+-		canfd: can@e66c0000 {
+-			compatible = "renesas,r8a77995-canfd",
+-				     "renesas,rcar-gen3-canfd";
+-			reg = <0 0xe66c0000 0 0x8000>;
+-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+-				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 914>,
+-			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
+-			       <&can_clk>;
+-			clock-names = "fck", "canfd", "can_clk";
+-			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
+-			assigned-clock-rates = <40000000>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 914>;
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 14>;
++			#iommu-cells = <1>;
+ 			status = "disabled";
++		};
+ 
+-			channel0 {
+-				status = "disabled";
+-			};
+-
+-			channel1 {
+-				status = "disabled";
+-			};
++		ipmmu_vp0: mmu@fe990000 {
++			compatible = "renesas,ipmmu-r8a77995";
++			reg = <0 0xfe990000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 16>;
++			#iommu-cells = <1>;
++			status = "disabled";
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+@@ -519,87 +531,35 @@
+ 			status = "disabled";
+ 		};
+ 
+-		scif2: serial@e6e88000 {
+-			compatible = "renesas,scif-r8a77995",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e88000 0 64>;
+-			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 310>,
+-				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+-			       <&dmac2 0x13>, <&dmac2 0x12>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 310>;
+-			status = "disabled";
+-		};
+-
+-		i2c0: i2c@e6500000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a77995",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6500000 0 0x40>;
+-			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 931>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 931>;
+-			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+-			       <&dmac2 0x91>, <&dmac2 0x90>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c1: i2c@e6508000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a77995",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6508000 0 0x40>;
+-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 930>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 930>;
+-			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+-			       <&dmac2 0x93>, <&dmac2 0x92>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
+-			status = "disabled";
+-		};
+-
+-		i2c2: i2c@e6510000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a77995",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe6510000 0 0x40>;
+-			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 929>;
++		can0: can@e6c30000 {
++			compatible = "renesas,can-r8a77995",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c30000 0 0x1000>;
++			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 916>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 929>;
+-			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+-			       <&dmac2 0x95>, <&dmac2 0x94>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 916>;
+ 			status = "disabled";
+ 		};
+ 
+-		i2c3: i2c@e66d0000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,i2c-r8a77995",
+-				     "renesas,rcar-gen3-i2c";
+-			reg = <0 0xe66d0000 0 0x40>;
+-			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 928>;
++		can1: can@e6c38000 {
++			compatible = "renesas,can-r8a77995",
++				     "renesas,rcar-gen3-can";
++			reg = <0 0xe6c38000 0 0x1000>;
++			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 915>,
++			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "clkp1", "clkp2", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 928>;
+-			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+-			dma-names = "tx", "rx";
+-			i2c-scl-internal-delay-ns = <6>;
++			resets = <&cpg 915>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -643,38 +603,43 @@
+ 			status = "disabled";
+ 		};
+ 
+-		sdhi2: sd@ee140000 {
+-			compatible = "renesas,sdhi-r8a77995",
+-				     "renesas,rcar-gen3-sdhi";
+-			reg = <0 0xee140000 0 0x2000>;
+-			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 312>;
+-			max-frequency = <200000000>;
++		scif2: serial@e6e88000 {
++			compatible = "renesas,scif-r8a77995",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e88000 0 64>;
++			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 310>,
++				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
++			       <&dmac2 0x13>, <&dmac2 0x12>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 312>;
++			resets = <&cpg 310>;
+ 			status = "disabled";
+ 		};
+ 
+-		ehci0: usb@ee080100 {
+-			compatible = "generic-ehci";
+-			reg = <0 0xee080100 0 0x100>;
++		ohci0: usb@ee080000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee080000 0 0x100>;
+ 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 703>;
+ 			phys = <&usb2_phy0>;
+ 			phy-names = "usb";
+-			companion = <&ohci0>;
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			status = "disabled";
+ 		};
+ 
+-		ohci0: usb@ee080000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee080000 0 0x100>;
++		ehci0: usb@ee080100 {
++			compatible = "generic-ehci";
++			reg = <0 0xee080100 0 0x100>;
+ 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 703>;
+ 			phys = <&usb2_phy0>;
+ 			phy-names = "usb";
++			companion = <&ohci0>;
+ 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			status = "disabled";
+@@ -692,6 +657,35 @@
+ 			status = "disabled";
+ 		};
+ 
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a77995",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
++		};
++
+ 		vspbs: vsp@fe960000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfe960000 0 0x8000>;
+@@ -702,15 +696,6 @@
+ 			renesas,fcp = <&fcpvb0>;
+ 		};
+ 
+-		fcpvb0: fcp@fe96f000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfe96f000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 607>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 607>;
+-			iommus = <&ipmmu_vp0 5>;
+-		};
+-
+ 		vspd0: vsp@fea20000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea20000 0 0x8000>;
+@@ -721,15 +706,6 @@
+ 			renesas,fcp = <&fcpvd0>;
+ 		};
+ 
+-		fcpvd0: fcp@fea27000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea27000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 603>;
+-			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+-			resets = <&cpg 603>;
+-			iommus = <&ipmmu_vi0 8>;
+-		};
+-
+ 		vspd1: vsp@fea28000 {
+ 			compatible = "renesas,vsp2";
+ 			reg = <0 0xfea28000 0 0x8000>;
+@@ -740,6 +716,24 @@
+ 			renesas,fcp = <&fcpvd1>;
+ 		};
+ 
++		fcpvb0: fcp@fe96f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfe96f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 607>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 607>;
++			iommus = <&ipmmu_vp0 5>;
++		};
++
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++			iommus = <&ipmmu_vi0 8>;
++		};
++
+ 		fcpvd1: fcp@fea2f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfea2f000 0 0x200>;
+@@ -783,6 +777,11 @@
+ 				};
+ 			};
+ 		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1483-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-root.patch b/patches/1483-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-root.patch
new file mode 100644
index 00000000000000..7a533ead4538a4
--- /dev/null
+++ b/patches/1483-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-root.patch
@@ -0,0 +1,182 @@
+From 4c007ece7da97fd72a47e368baee216eb93f7629 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Thu, 19 Apr 2018 05:14:38 +0900
+Subject: [PATCH 1483/1795] arm64: dts: renesas: r8a77965: sort subnodes of the
+ root node
+
+Sort subnodes of the root node alphanumerically.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 001f3b032fa12069244d17a15ecd06cbf3040880)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 +++++++++++-----------
+ 1 file changed, 60 insertions(+), 60 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index a41f91653d93..d110382276b7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -22,9 +22,34 @@
+ 		i2c7 = &i2c_dvfs;
+ 	};
+ 
+-	psci {
+-		compatible = "arm,psci-1.0", "arm,psci-0.2";
+-		method = "smc";
++	/*
++	 * The external audio clocks are configured as 0 Hz fixed frequency
++	 * clocks by default.
++	 * Boards that provide audio clocks should override them.
++	 */
++	audio_clk_a: audio_clk_a {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_b: audio_clk_b {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	audio_clk_c: audio_clk_c {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
+ 	};
+ 
+ 	cpus {
+@@ -71,34 +96,24 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/*
+-	 * The external audio clocks are configured as 0 Hz fixed frequency
+-	 * clocks by default.
+-	 * Boards that provide audio clocks should override them.
+-	 */
+-	audio_clk_a: audio_clk_a {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	audio_clk_b: audio_clk_b {
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	audio_clk_c: audio_clk_c {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
++	pmu_a57 {
++		compatible = "arm,cortex-a57-pmu";
++		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a57_0>,
++				     <&a57_1>;
+ 	};
+ 
+-	/* External CAN clock - to be overridden by boards that provide it */
+-	can_clk: can {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
++	psci {
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
++		method = "smc";
+ 	};
+ 
+ 	/* External SCIF clock - to be overridden by boards that provide it */
+@@ -108,42 +123,6 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
+-	/* External PCIe clock - can be overridden by the board */
+-	pcie_bus_clk: pcie_bus {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	/* External USB clocks - can be overridden by the board */
+-	usb3s0_clk: usb3s0 {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	usb_extal_clk: usb_extal {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <0>;
+-	};
+-
+-	timer {
+-		compatible = "arm,armv8-timer";
+-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+-	};
+-
+-	pmu_a57 {
+-		compatible = "arm,cortex-a57-pmu";
+-		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-affinity = <&a57_0>,
+-				     <&a57_1>;
+-	};
+-
+ 	soc {
+ 		compatible = "simple-bus";
+ 		interrupt-parent = <&gic>;
+@@ -1073,4 +1052,25 @@
+ 			/* placeholder */
+ 		};
+ 	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	/* External USB clocks - can be overridden by the board */
++	usb3s0_clk: usb3s0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	usb_extal_clk: usb_extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1484-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-soc-.patch b/patches/1484-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-soc-.patch
new file mode 100644
index 00000000000000..645f48d4107d68
--- /dev/null
+++ b/patches/1484-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-soc-.patch
@@ -0,0 +1,1051 @@
+From 4ddda417cad51f31f104207073ee1533d7bfa5ad Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Thu, 19 Apr 2018 05:14:39 +0900
+Subject: [PATCH 1484/1795] arm64: dts: renesas: r8a77965: sort subnodes of the
+ soc node
+
+Sort subnodes of the soc node.
+- The primary key is the bus address.
+- The secondary key is the IP block.
+- The tertiary key is the node name.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2af6f5a3fd585427fcab5848e87223a486e74c37)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 912 +++++++++++-----------
+ 1 file changed, 456 insertions(+), 456 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index d110382276b7..b12f41755aea 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -130,52 +130,9 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		gic: interrupt-controller@f1010000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0x0 0xf1010000 0 0x1000>,
+-			      <0x0 0xf1020000 0 0x20000>,
+-			      <0x0 0xf1040000 0 0x20000>,
+-			      <0x0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9
+-					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 408>;
+-		};
+-
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a77965";
+-			reg = <0 0xe6060000 0 0x50c>;
+-		};
+-
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a77965-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&extalr_clk>;
+-			clock-names = "extal", "extalr";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
+-		};
+-
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a77965-rst";
+-			reg = <0 0xe6160000 0 0x0200>;
+-		};
+-
+-		prr: chipid@fff00044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xfff00044 0 4>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a77965-sysc";
+-			reg = <0 0xe6180000 0 0x0400>;
+-			#power-domain-cells = <1>;
++		wdt0: watchdog@e6020000 {
++			reg = <0 0xe6020000 0 0x0c>;
++			/* placeholder */
+ 		};
+ 
+ 		gpio0: gpio@e6050000 {
+@@ -298,6 +255,32 @@
+ 			resets = <&cpg 905>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77965";
++			reg = <0 0xe6060000 0 0x50c>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77965-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77965-rst";
++			reg = <0 0xe6160000 0 0x0200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77965-sysc";
++			reg = <0 0xe6180000 0 0x0400>;
++			#power-domain-cells = <1>;
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -314,6 +297,121 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
++		i2c0: i2c@e6500000 {
++			reg = <0 0xe6500000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c1: i2c@e6508000 {
++			reg = <0 0xe6508000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			reg = <0 0xe6510000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c3: i2c@e66d0000 {
++			reg = <0 0xe66d0000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c4: i2c@e66d8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			reg = <0 0xe66d8000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c5: i2c@e66e0000 {
++			reg = <0 0xe66e0000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c6: i2c@e66e8000 {
++			reg = <0 0xe66e8000 0 0x40>;
++			/* placeholder */
++		};
++
++		i2c_dvfs: i2c@e60b0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,iic-r8a77965",
++				     "renesas,rcar-gen3-iic",
++				     "renesas,rmobile-iic";
++			reg = <0 0xe60b0000 0 0x425>;
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 926>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 926>;
++			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
++			dma-names = "tx", "rx";
++			status = "disabled";
++		};
++
++		hsusb: usb@e6590000 {
++			compatible = "renesas,usbhs-r8a7796",
++				     "renesas,rcar-gen3-usbhs";
++			reg = <0 0xe6590000 0 0x100>;
++			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 704>;
++			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
++			       <&usb_dmac1 0>, <&usb_dmac1 1>;
++			dma-names = "ch0", "ch1", "ch2", "ch3";
++			renesas,buswait = <11>;
++			phys = <&usb2_phy0>;
++			phy-names = "usb";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 704>;
++			status = "disabled";
++		};
++
++		usb_dmac0: dma-controller@e65a0000 {
++			compatible = "renesas,r8a77965-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65a0000 0 0x100>;
++			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 330>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 330>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb_dmac1: dma-controller@e65b0000 {
++			compatible = "renesas,r8a77965-usb-dmac",
++				     "renesas,usb-dmac";
++			reg = <0 0xe65b0000 0 0x100>;
++			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1";
++			clocks = <&cpg CPG_MOD 331>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 331>;
++			#dma-cells = <1>;
++			dma-channels = <2>;
++		};
++
++		usb3_phy0: usb-phy@e65ee000 {
++			compatible = "renesas,r8a77965-usb3-phy",
++				     "renesas,rcar-gen3-usb3-phy";
++			reg = <0 0xe65ee000 0 0x90>;
++			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
++				 <&usb_extal_clk>;
++			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
+ 		dmac0: dma-controller@e6700000 {
+ 			compatible = "renesas,dmac-r8a77965",
+ 				     "renesas,rcar-dmac";
+@@ -416,35 +514,150 @@
+ 			dma-channels = <16>;
+ 		};
+ 
+-		scif0: serial@e6e60000 {
+-			compatible = "renesas,scif-r8a77965",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e60000 0 64>;
+-			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 207>,
+-				 <&cpg CPG_CORE 20>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+-			       <&dmac2 0x51>, <&dmac2 0x50>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77965",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
+ 			power-domains = <&sysc 32>;
+-			resets = <&cpg 207>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		scif1: serial@e6e68000 {
+-			compatible = "renesas,scif-r8a77965",
+-				     "renesas,rcar-gen3-scif", "renesas,scif";
+-			reg = <0 0xe6e68000 0 64>;
+-			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 206>,
+-				 <&cpg CPG_CORE 20>,
+-				 <&scif_clk>;
+-			clock-names = "fck", "brg_int", "scif_clk";
+-			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+-			       <&dmac2 0x53>, <&dmac2 0x52>;
+-			dma-names = "tx", "rx", "tx", "rx";
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm5: pwm@e6e35000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e35000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		pwm6: pwm@e6e36000 {
++			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
++			reg = <0 0xe6e36000 0 8>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;
++			resets = <&cpg 523>;
++			power-domains = <&sysc 32>;
++			status = "disabled";
++		};
++
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
++			       <&dmac2 0x51>, <&dmac2 0x50>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 207>;
++			status = "disabled";
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a77965",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE 20>,
++				 <&scif_clk>;
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
++			       <&dmac2 0x53>, <&dmac2 0x52>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+ 			resets = <&cpg 206>;
+ 			status = "disabled";
+@@ -513,69 +726,66 @@
+ 			status = "disabled";
+ 		};
+ 
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a77965",
+-				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14", "ch15",
+-					  "ch16", "ch17", "ch18", "ch19",
+-					  "ch20", "ch21", "ch22", "ch23",
+-					  "ch24";
+-			clocks = <&cpg CPG_MOD 812>;
++		msiof0: spi@e6e90000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6e90000 0 0x0064>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 211>;
++			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
++			       <&dmac2 0x41>, <&dmac2 0x40>;
++			dma-names = "tx", "rx", "tx", "rx";
+ 			power-domains = <&sysc 32>;
+-			resets = <&cpg 812>;
+-			phy-mode = "rgmii";
++			resets = <&cpg 211>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			status = "disabled";
+ 		};
+ 
+-		csi20: csi2@fea80000 {
+-			reg = <0 0xfea80000 0 0x10000>;
+-			/* placeholder */
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-			};
++		msiof1: spi@e6ea0000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6ea0000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 210>;
++			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
++			       <&dmac2 0x43>, <&dmac2 0x42>;
++			dma-names = "tx", "rx", "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 210>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+-		csi40: csi2@feaa0000 {
+-			reg = <0 0xfeaa0000 0 0x10000>;
+-			/* placeholder */
++		msiof2: spi@e6c00000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 209>;
++			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 209>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
+ 
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-			};
++		msiof3: spi@e6c10000 {
++			compatible = "renesas,msiof-r8a77965",
++				     "renesas,rcar-gen3-msiof";
++			reg = <0 0xe6c10000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>;
++			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 208>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		vin0: video@e6ef0000 {
+@@ -618,6 +828,58 @@
+ 			/* placeholder */
+ 		};
+ 
++		rcar_sound: sound@ec500000 {
++			reg =	<0 0xec500000 0 0x1000>, /* SCU */
++				<0 0xec5a0000 0 0x100>,  /* ADG */
++				<0 0xec540000 0 0x1000>, /* SSIU */
++				<0 0xec541000 0 0x280>,  /* SSI */
++				<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
++			/* placeholder */
++
++			rcar_sound,dvc {
++				dvc0: dvc-0 {
++				};
++				dvc1: dvc-1 {
++				};
++			};
++
++			rcar_sound,src {
++				src0: src-0 {
++				};
++				src1: src-1 {
++				};
++			};
++
++			rcar_sound,ssi {
++				ssi0: ssi-0 {
++				};
++				ssi1: ssi-1 {
++				};
++			};
++		};
++
++		xhci0: usb@ee000000 {
++			compatible = "renesas,xhci-r8a77965",
++				     "renesas,rcar-gen3-xhci";
++			reg = <0 0xee000000 0 0xc00>;
++			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
++		usb3_peri0: usb@ee020000 {
++			compatible = "renesas,r8a77965-usb3-peri",
++				     "renesas,rcar-gen3-usb3-peri";
++			reg = <0 0xee020000 0 0x400>;
++			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 328>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 328>;
++			status = "disabled";
++		};
++
+ 		ohci0: usb@ee080000 {
+ 			compatible = "generic-ohci";
+ 			reg = <0 0xee080000 0 0x100>;
+@@ -630,6 +892,18 @@
+ 			status = "disabled";
+ 		};
+ 
++		ohci1: usb@ee0a0000 {
++			compatible = "generic-ohci";
++			reg = <0 0xee0a0000 0 0x100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 702>;
++			status = "disabled";
++		};
++
+ 		ehci0: usb@ee080100 {
+ 			compatible = "generic-ehci";
+ 			reg = <0 0xee080100 0 0x100>;
+@@ -643,6 +917,19 @@
+ 			status = "disabled";
+ 		};
+ 
++		ehci1: usb@ee0a0100 {
++			compatible = "generic-ehci";
++			reg = <0 0xee0a0100 0 0x100>;
++			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 702>;
++			phys = <&usb2_phy1>;
++			phy-names = "usb";
++			companion = <&ohci1>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 702>;
++			status = "disabled";
++		};
++
+ 		usb2_phy0: usb-phy@ee080200 {
+ 			compatible = "renesas,usb2-phy-r8a77965",
+ 				     "renesas,rcar-gen3-usb2-phy";
+@@ -666,218 +953,71 @@
+ 			status = "disabled";
+ 		};
+ 
+-		ohci1: usb@ee0a0000 {
+-			compatible = "generic-ohci";
+-			reg = <0 0xee0a0000 0 0x100>;
+-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 702>;
+-			phys = <&usb2_phy1>;
+-			phy-names = "usb";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 702>;
+-			status = "disabled";
+-		};
+-
+-		ehci1: usb@ee0a0100 {
+-			compatible = "generic-ehci";
+-			reg = <0 0xee0a0100 0 0x100>;
+-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 702>;
+-			phys = <&usb2_phy1>;
+-			phy-names = "usb";
+-			companion = <&ohci1>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 702>;
+-			status = "disabled";
+-		};
+-
+-		i2c0: i2c@e6500000 {
+-			reg = <0 0xe6500000 0 0x40>;
++		sdhi0: sd@ee100000 {
++			reg = <0 0xee100000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c1: i2c@e6508000 {
+-			reg = <0 0xe6508000 0 0x40>;
++		sdhi1: sd@ee120000 {
++			reg = <0 0xee120000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c2: i2c@e6510000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			reg = <0 0xe6510000 0 0x40>;
++		sdhi2: sd@ee140000 {
++			reg = <0 0xee140000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c3: i2c@e66d0000 {
+-			reg = <0 0xe66d0000 0 0x40>;
++		sdhi3: sd@ee160000 {
++			reg = <0 0xee160000 0 0x2000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c4: i2c@e66d8000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			reg = <0 0xe66d8000 0 0x40>;
+-			/* placeholder */
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
+ 		};
+ 
+-		i2c5: i2c@e66e0000 {
+-			reg = <0 0xe66e0000 0 0x40>;
++		pciec0: pcie@fe000000 {
++			reg = <0 0xfe000000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c6: i2c@e66e8000 {
+-			reg = <0 0xe66e8000 0 0x40>;
++		pciec1: pcie@ee800000 {
++			reg = <0 0xee800000 0 0x80000>;
+ 			/* placeholder */
+ 		};
+ 
+-		i2c_dvfs: i2c@e60b0000 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			compatible = "renesas,iic-r8a77965",
+-				     "renesas,rcar-gen3-iic",
+-				     "renesas,rmobile-iic";
+-			reg = <0 0xe60b0000 0 0x425>;
+-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 926>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 926>;
+-			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+-			dma-names = "tx", "rx";
+-			status = "disabled";
+-		};
+-
+-		pwm0: pwm@e6e30000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e30000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm1: pwm@e6e31000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e31000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm2: pwm@e6e32000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e32000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm3: pwm@e6e33000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e33000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm4: pwm@e6e34000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e34000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm5: pwm@e6e35000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e35000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		pwm6: pwm@e6e36000 {
+-			compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
+-			reg = <0 0xe6e36000 0 8>;
+-			#pwm-cells = <2>;
+-			clocks = <&cpg CPG_MOD 523>;
+-			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
+-			status = "disabled";
+-		};
+-
+-		msiof0: spi@e6e90000 {
+-			compatible = "renesas,msiof-r8a77965",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6e90000 0 0x0064>;
+-			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 211>;
+-			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+-			       <&dmac2 0x41>, <&dmac2 0x40>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 211>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
++		csi20: csi2@fea80000 {
++			reg = <0 0xfea80000 0 0x10000>;
++			/* placeholder */
+ 
+-		msiof1: spi@e6ea0000 {
+-			compatible = "renesas,msiof-r8a77965",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6ea0000 0 0x0064>;
+-			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 210>;
+-			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+-			       <&dmac2 0x43>, <&dmac2 0x42>;
+-			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 210>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
+ 		};
+ 
+-		msiof2: spi@e6c00000 {
+-			compatible = "renesas,msiof-r8a77965",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c00000 0 0x0064>;
+-			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 209>;
+-			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+-			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 209>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
+-		};
++		csi40: csi2@feaa0000 {
++			reg = <0 0xfeaa0000 0 0x10000>;
++			/* placeholder */
+ 
+-		msiof3: spi@e6c10000 {
+-			compatible = "renesas,msiof-r8a77965",
+-				     "renesas,rcar-gen3-msiof";
+-			reg = <0 0xe6c10000 0 0x0064>;
+-			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 208>;
+-			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+-			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 208>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			status = "disabled";
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
+ 		};
+ 
+ 		du: display@feb00000 {
+@@ -907,149 +1047,9 @@
+ 			};
+ 		};
+ 
+-		usb_dmac0: dma-controller@e65a0000 {
+-			compatible = "renesas,r8a77965-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65a0000 0 0x100>;
+-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 330>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 330>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		usb_dmac1: dma-controller@e65b0000 {
+-			compatible = "renesas,r8a77965-usb-dmac",
+-				     "renesas,usb-dmac";
+-			reg = <0 0xe65b0000 0 0x100>;
+-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1";
+-			clocks = <&cpg CPG_MOD 331>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 331>;
+-			#dma-cells = <1>;
+-			dma-channels = <2>;
+-		};
+-
+-		hsusb: usb@e6590000 {
+-			compatible = "renesas,usbhs-r8a7796",
+-				     "renesas,rcar-gen3-usbhs";
+-			reg = <0 0xe6590000 0 0x100>;
+-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 704>;
+-			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+-			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+-			dma-names = "ch0", "ch1", "ch2", "ch3";
+-			renesas,buswait = <11>;
+-			phys = <&usb2_phy0>;
+-			phy-names = "usb";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 704>;
+-			status = "disabled";
+-		};
+-
+-		pciec0: pcie@fe000000 {
+-			reg = <0 0xfe000000 0 0x80000>;
+-			/* placeholder */
+-		};
+-
+-		pciec1: pcie@ee800000 {
+-			reg = <0 0xee800000 0 0x80000>;
+-			/* placeholder */
+-		};
+-
+-		rcar_sound: sound@ec500000 {
+-			reg =	<0 0xec500000 0 0x1000>, /* SCU */
+-				<0 0xec5a0000 0 0x100>,  /* ADG */
+-				<0 0xec540000 0 0x1000>, /* SSIU */
+-				<0 0xec541000 0 0x280>,  /* SSI */
+-				<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+-			/* placeholder */
+-
+-			rcar_sound,dvc {
+-				dvc0: dvc-0 {
+-				};
+-				dvc1: dvc-1 {
+-				};
+-			};
+-
+-			rcar_sound,src {
+-				src0: src-0 {
+-				};
+-				src1: src-1 {
+-				};
+-			};
+-
+-			rcar_sound,ssi {
+-				ssi0: ssi-0 {
+-				};
+-				ssi1: ssi-1 {
+-				};
+-			};
+-		};
+-
+-		sdhi0: sd@ee100000 {
+-			reg = <0 0xee100000 0 0x2000>;
+-			/* placeholder */
+-		};
+-
+-		sdhi1: sd@ee120000 {
+-			reg = <0 0xee120000 0 0x2000>;
+-			/* placeholder */
+-		};
+-
+-		sdhi2: sd@ee140000 {
+-			reg = <0 0xee140000 0 0x2000>;
+-			/* placeholder */
+-		};
+-
+-		sdhi3: sd@ee160000 {
+-			reg = <0 0xee160000 0 0x2000>;
+-			/* placeholder */
+-		};
+-
+-		usb3_phy0: usb-phy@e65ee000 {
+-			compatible = "renesas,r8a77965-usb3-phy",
+-				     "renesas,rcar-gen3-usb3-phy";
+-			reg = <0 0xe65ee000 0 0x90>;
+-			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+-				 <&usb_extal_clk>;
+-			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 328>;
+-			#phy-cells = <0>;
+-			status = "disabled";
+-		};
+-
+-		usb3_peri0: usb@ee020000 {
+-			compatible = "renesas,r8a77965-usb3-peri",
+-				     "renesas,rcar-gen3-usb3-peri";
+-			reg = <0 0xee020000 0 0x400>;
+-			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 328>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 328>;
+-			status = "disabled";
+-		};
+-
+-		xhci0: usb@ee000000 {
+-			compatible = "renesas,xhci-r8a77965",
+-				     "renesas,rcar-gen3-xhci";
+-			reg = <0 0xee000000 0 0xc00>;
+-			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&cpg CPG_MOD 328>;
+-			power-domains = <&sysc 32>;
+-			resets = <&cpg 328>;
+-			status = "disabled";
+-		};
+-
+-		wdt0: watchdog@e6020000 {
+-			reg = <0 0xe6020000 0 0x0c>;
+-			/* placeholder */
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
+ 		};
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1485-arm64-dts-renesas-r8a77970-sort-subnodes-of-the-soc-.patch b/patches/1485-arm64-dts-renesas-r8a77970-sort-subnodes-of-the-soc-.patch
new file mode 100644
index 00000000000000..4525c4347b6343
--- /dev/null
+++ b/patches/1485-arm64-dts-renesas-r8a77970-sort-subnodes-of-the-soc-.patch
@@ -0,0 +1,482 @@
+From e1097102247583d3cab505a76c449b7c71eac2a3 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Date: Thu, 19 Apr 2018 05:14:40 +0900
+Subject: [PATCH 1485/1795] arm64: dts: renesas: r8a77970: sort subnodes of the
+ soc node
+
+Sort subnodes of the soc node.
+- The primary key is the bus address.
+- The secondary key is the IP block.
+- The tertiary key is the node name.
+
+This is part of an ongoing effort to provide consistent node
+order in the DT of Renesas SoCs to improve maintainability.
+
+This should not have any run-time effect.
+
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+[simon: rebased; move fcpvd0 to after vspd0]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 2964d7546f71c793581382a518b3f2da7a2ad5b6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 388 +++++++++++-----------
+ 1 file changed, 194 insertions(+), 194 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index a194cb8d7d62..c06d7fbfb7be 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -83,23 +83,6 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
+-		gic: interrupt-controller@f1010000 {
+-			compatible = "arm,gic-400";
+-			#interrupt-cells = <3>;
+-			#address-cells = <0>;
+-			interrupt-controller;
+-			reg = <0 0xf1010000 0 0x1000>,
+-			      <0 0xf1020000 0 0x20000>,
+-			      <0 0xf1040000 0 0x20000>,
+-			      <0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
+-				      IRQ_TYPE_LEVEL_HIGH)>;
+-			clocks = <&cpg CPG_MOD 408>;
+-			clock-names = "clk";
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			resets = <&cpg 408>;
+-		};
+-
+ 		rwdt: watchdog@e6020000 {
+ 			compatible = "renesas,r8a77970-wdt",
+ 				     "renesas,rcar-gen3-wdt";
+@@ -110,75 +93,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		cpg: clock-controller@e6150000 {
+-			compatible = "renesas,r8a77970-cpg-mssr";
+-			reg = <0 0xe6150000 0 0x1000>;
+-			clocks = <&extal_clk>, <&extalr_clk>;
+-			clock-names = "extal", "extalr";
+-			#clock-cells = <2>;
+-			#power-domain-cells = <0>;
+-			#reset-cells = <1>;
+-		};
+-
+-		rst: reset-controller@e6160000 {
+-			compatible = "renesas,r8a77970-rst";
+-			reg = <0 0xe6160000 0 0x200>;
+-		};
+-
+-		sysc: system-controller@e6180000 {
+-			compatible = "renesas,r8a77970-sysc";
+-			reg = <0 0xe6180000 0 0x440>;
+-			#power-domain-cells = <1>;
+-		};
+-
+-		ipmmu_vi0: mmu@febd0000 {
+-			compatible = "renesas,ipmmu-r8a77970";
+-			reg = <0 0xfebd0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 9>;
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_ir: mmu@ff8b0000 {
+-			compatible = "renesas,ipmmu-r8a77970";
+-			reg = <0 0xff8b0000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 3>;
+-			power-domains = <&sysc R8A77970_PD_A3IR>;
+-			#iommu-cells = <1>;
+-			status = "disabled";
+-		};
+-
+-		ipmmu_rt: mmu@ffc80000 {
+-			compatible = "renesas,ipmmu-r8a77970";
+-			reg = <0 0xffc80000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 7>;
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_ds1: mmu@e7740000 {
+-			compatible = "renesas,ipmmu-r8a77970";
+-			reg = <0 0xe7740000 0 0x1000>;
+-			renesas,ipmmu-main = <&ipmmu_mm 0>;
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		ipmmu_mm: mmu@e67b0000 {
+-			compatible = "renesas,ipmmu-r8a77970";
+-			reg = <0 0xe67b0000 0 0x1000>;
+-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			#iommu-cells = <1>;
+-		};
+-
+-		pfc: pin-controller@e6060000 {
+-			compatible = "renesas,pfc-r8a77970";
+-			reg = <0 0xe6060000 0 0x504>;
+-		};
+-
+ 		gpio0: gpio@e6050000 {
+ 			compatible = "renesas,gpio-r8a77970",
+ 				     "renesas,rcar-gen3-gpio";
+@@ -269,6 +183,32 @@
+ 			resets = <&cpg 907>;
+ 		};
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77970";
++			reg = <0 0xe6060000 0 0x504>;
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77970-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77970-rst";
++			reg = <0 0xe6160000 0 0x200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77970-sysc";
++			reg = <0 0xe6180000 0 0x440>;
++			#power-domain-cells = <1>;
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -285,67 +225,6 @@
+ 			resets = <&cpg 407>;
+ 		};
+ 
+-		prr: chipid@fff00044 {
+-			compatible = "renesas,prr";
+-			reg = <0 0xfff00044 0 4>;
+-		};
+-
+-		dmac1: dma-controller@e7300000 {
+-			compatible = "renesas,dmac-r8a77970",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe7300000 0 0x10000>;
+-			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7";
+-			clocks = <&cpg CPG_MOD 218>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			resets = <&cpg 218>;
+-			#dma-cells = <1>;
+-			dma-channels = <8>;
+-			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+-			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+-			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+-			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
+-		};
+-
+-		dmac2: dma-controller@e7310000 {
+-			compatible = "renesas,dmac-r8a77970",
+-				     "renesas,rcar-dmac";
+-			reg = <0 0xe7310000 0 0x10000>;
+-			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+-				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "error",
+-					  "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7";
+-			clocks = <&cpg CPG_MOD 217>;
+-			clock-names = "fck";
+-			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			resets = <&cpg 217>;
+-			#dma-cells = <1>;
+-			dma-channels = <8>;
+-			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+-			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+-			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+-			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
+-		};
+-
+ 		i2c0: i2c@e6500000 {
+ 			compatible = "renesas,i2c-r8a77970",
+ 				     "renesas,rcar-gen3-i2c";
+@@ -502,6 +381,51 @@
+ 			status = "disabled";
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77970",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			iommus = <&ipmmu_rt 3>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 		scif0: serial@e6e60000 {
+ 			compatible = "renesas,scif-r8a77970",
+ 				     "renesas,rcar-gen3-scif",
+@@ -573,57 +497,120 @@
+ 			status = "disabled";
+ 		};
+ 
+-		avb: ethernet@e6800000 {
+-			compatible = "renesas,etheravb-r8a77970",
+-				     "renesas,etheravb-rcar-gen3";
+-			reg = <0 0xe6800000 0 0x800>;
+-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+-				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+-					  "ch4", "ch5", "ch6", "ch7",
+-					  "ch8", "ch9", "ch10", "ch11",
+-					  "ch12", "ch13", "ch14", "ch15",
+-					  "ch16", "ch17", "ch18", "ch19",
+-					  "ch20", "ch21", "ch22", "ch23",
+-					  "ch24";
+-			clocks = <&cpg CPG_MOD 812>;
++		dmac1: dma-controller@e7300000 {
++			compatible = "renesas,dmac-r8a77970",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			resets = <&cpg 812>;
+-			phy-mode = "rgmii";
+-			iommus = <&ipmmu_rt 3>;
+-			#address-cells = <1>;
+-			#size-cells = <0>;
++			resets = <&cpg 218>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
++			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
++			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
++			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
+ 		};
+ 
+-		fcpvd0: fcp@fea27000 {
+-			compatible = "renesas,fcpv";
+-			reg = <0 0xfea27000 0 0x200>;
+-			clocks = <&cpg CPG_MOD 603>;
++		dmac2: dma-controller@e7310000 {
++			compatible = "renesas,dmac-r8a77970",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "error",
++					  "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7";
++			clocks = <&cpg CPG_MOD 217>;
++			clock-names = "fck";
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+-			resets = <&cpg 603>;
++			resets = <&cpg 217>;
++			#dma-cells = <1>;
++			dma-channels = <8>;
++			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
++			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
++			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
++			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
++		};
++
++		ipmmu_ds1: mmu@e7740000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xe7740000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xff8b0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			power-domains = <&sysc R8A77970_PD_A3IR>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xe67b0000 0 0x1000>;
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xffc80000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 7>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++		};
++
++		ipmmu_vi0: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a77970";
++			reg = <0 0xfebd0000 0 0x1000>;
++			renesas,ipmmu-main = <&ipmmu_mm 9>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0 0xf1010000 0 0x1000>,
++			      <0 0xf1020000 0 0x20000>,
++			      <0 0xf1040000 0 0x20000>,
++			      <0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
++				      IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 408>;
+ 		};
+ 
+ 		vspd0: vsp@fea20000 {
+@@ -636,6 +623,14 @@
+ 			renesas,fcp = <&fcpvd0>;
+ 		};
+ 
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a77970";
+ 			reg = <0 0xfeb00000 0 0x80000>;
+@@ -692,6 +687,11 @@
+ 				};
+ 			};
+ 		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
+ 	};
+ 
+ 	timer {
+-- 
+2.19.0
+
diff --git a/patches/1486-arm64-dts-renesas-Add-Renesas-R8A77990-SoC-support.patch b/patches/1486-arm64-dts-renesas-Add-Renesas-R8A77990-SoC-support.patch
new file mode 100644
index 00000000000000..eb4468c67556c4
--- /dev/null
+++ b/patches/1486-arm64-dts-renesas-Add-Renesas-R8A77990-SoC-support.patch
@@ -0,0 +1,167 @@
+From 6346b5116ac92f295d7259d0cc09ec971a66212e Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 20 Apr 2018 21:28:16 +0900
+Subject: [PATCH 1486/1795] arm64: dts: renesas: Add Renesas R8A77990 SoC
+ support
+
+This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
+  - PSCI
+  - CPU (single)
+  - Cache controller
+  - Main clocks and controller
+  - Interrupt controller
+  - Timer
+  - PMU
+  - Reset controller
+  - Product register
+  - System controller
+  - UART for console
+
+Inspried by a patch by Takeshi Kihara in the BSP.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit f37a7767f6c4ec66c3df227ad4028e5390322202)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 127 ++++++++++++++++++++++
+ 1 file changed, 127 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+new file mode 100644
+index 000000000000..3a19b9ebdd6e
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -0,0 +1,127 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Device Tree Source for the r8a77990 SoC
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++	compatible = "renesas,r8a77990";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/* 1 core only at this point */
++		a53_0: cpu@0 {
++			compatible = "arm,cortex-a53", "arm,armv8";
++			reg = <0x0>;
++			device_type = "cpu";
++			power-domains = <&sysc 5>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++		};
++
++		L2_CA53: cache-controller@0 {
++			compatible = "cache";
++			reg = <0>;
++			power-domains = <&sysc 21>;
++			cache-unified;
++			cache-level = <2>;
++		};
++	};
++
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	pmu_a53 {
++		compatible = "arm,cortex-a53-pmu";
++		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a53_0>;
++	};
++
++	psci {
++		compatible = "arm,psci-0.2";
++		method = "smc";
++	};
++
++	soc: soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a77990-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>;
++			clock-names = "extal";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++			#reset-cells = <1>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a77990-rst";
++			reg = <0 0xe6160000 0 0x0200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a77990-sysc";
++			reg = <0 0xe6180000 0 0x0400>;
++			#power-domain-cells = <1>;
++		};
++
++		scif2: serial@e6e88000 {
++			compatible = "renesas,scif-r8a77990",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e88000 0 64>;
++			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 310>;
++			clock-names = "fck";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 310>;
++			status = "disabled";
++		};
++
++		gic: interrupt-controller@f1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
++			clocks = <&cpg CPG_MOD 408>;
++			clock-names = "clk";
++			power-domains = <&sysc 32>;
++			resets = <&cpg 408>;
++		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1487-arm64-dts-renesas-Add-Renesas-Ebisu-board-support.patch b/patches/1487-arm64-dts-renesas-Add-Renesas-Ebisu-board-support.patch
new file mode 100644
index 00000000000000..c85c1ae635fd69
--- /dev/null
+++ b/patches/1487-arm64-dts-renesas-Add-Renesas-Ebisu-board-support.patch
@@ -0,0 +1,84 @@
+From 0fbb2b769a96b650c38ce718676bc92f79ddee33 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 20 Apr 2018 21:28:17 +0900
+Subject: [PATCH 1487/1795] arm64: dts: renesas: Add Renesas Ebisu board
+ support
+
+Basic support for the Renesas Ebisu board based on R-Car E3:
+  - Memory,
+  - Main crystal,
+  - Serial console,
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[shimoda: rebase and add SPDX-License-Identifier]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 77049191b24b45868f68b34f43d6eb072b26c847)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  1 +
+ .../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 37 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 554e31ac8bc3..12b65594451d 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
++dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+ always		:= $(dtb-y)
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+new file mode 100644
+index 000000000000..63ee1347bb19
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Device Tree Source for the ebisu board
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++/dts-v1/;
++#include "r8a77990.dtsi"
++
++/ {
++	model = "Renesas Ebisu board based on r8a77990";
++	compatible = "renesas,ebisu", "renesas,r8a77990";
++
++	aliases {
++		serial0 = &scif2;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel";
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x38000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <48000000>;
++};
++
++&scif2 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1488-arm64-dts-renesas-r8a7795-Enable-IPMMU-devices.patch b/patches/1488-arm64-dts-renesas-r8a7795-Enable-IPMMU-devices.patch
new file mode 100644
index 00000000000000..ccdb5a46e82c70
--- /dev/null
+++ b/patches/1488-arm64-dts-renesas-r8a7795-Enable-IPMMU-devices.patch
@@ -0,0 +1,121 @@
+From 503f338a8a43ce2d62f8fdc009e256314778bb66 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Sun, 22 Apr 2018 19:08:15 +0900
+Subject: [PATCH 1488/1795] arm64: dts: renesas: r8a7795: Enable IPMMU devices
+
+Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
+in DT on the r8a7795 SoC.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d2ed9ffcab09f251aae6ac1d5da8a6ae62501150)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index acf0c6f72a4d..32870cbaf94d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -947,7 +947,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 2>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ir: mmu@ff8b0000 {
+@@ -956,7 +955,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 3>;
+ 			power-domains = <&sysc R8A7795_PD_A3IR>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -974,7 +972,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 4>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv0: mmu@fd800000 {
+@@ -983,7 +980,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 6>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv1: mmu@fd950000 {
+@@ -992,7 +988,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 7>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv2: mmu@fd960000 {
+@@ -1001,7 +996,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 8>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv3: mmu@fd970000 {
+@@ -1010,7 +1004,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 9>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_rt: mmu@ffc80000 {
+@@ -1019,7 +1012,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 10>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc0: mmu@fe6b0000 {
+@@ -1028,7 +1020,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 12>;
+ 			power-domains = <&sysc R8A7795_PD_A3VC>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc1: mmu@fe6f0000 {
+@@ -1037,7 +1028,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 13>;
+ 			power-domains = <&sysc R8A7795_PD_A3VC>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vi0: mmu@febd0000 {
+@@ -1054,7 +1044,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 15>;
+ 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vp0: mmu@fe990000 {
+@@ -1063,7 +1052,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 16>;
+ 			power-domains = <&sysc R8A7795_PD_A3VP>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vp1: mmu@fe980000 {
+-- 
+2.19.0
+
diff --git a/patches/1489-arm64-dts-renesas-r8a7796-Enable-IPMMU-devices.patch b/patches/1489-arm64-dts-renesas-r8a7796-Enable-IPMMU-devices.patch
new file mode 100644
index 00000000000000..c40494cec0db3b
--- /dev/null
+++ b/patches/1489-arm64-dts-renesas-r8a7796-Enable-IPMMU-devices.patch
@@ -0,0 +1,65 @@
+From 01698e209ade30512cf758df596ae7934c403833 Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Sun, 22 Apr 2018 19:08:24 +0900
+Subject: [PATCH 1489/1795] arm64: dts: renesas: r8a7796: Enable IPMMU devices
+
+Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
+in DT on the r8a7796 SoC.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 330f2dc009e937efe6618096718f12a4a5a847f8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index e6254711556c..f33063dd7cd7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -881,7 +881,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 2>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ir: mmu@ff8b0000 {
+@@ -890,7 +889,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 3>;
+ 			power-domains = <&sysc R8A7796_PD_A3IR>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -924,7 +922,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 6>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_rt: mmu@ffc80000 {
+@@ -933,7 +930,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 7>;
+ 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc0: mmu@fe6b0000 {
+@@ -942,7 +938,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 8>;
+ 			power-domains = <&sysc R8A7796_PD_A3VC>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vi0: mmu@febd0000 {
+-- 
+2.19.0
+
diff --git a/patches/1490-arm64-dts-renesas-r8a77970-Enable-IPMMU-devices.patch b/patches/1490-arm64-dts-renesas-r8a77970-Enable-IPMMU-devices.patch
new file mode 100644
index 00000000000000..b90969288cbcd7
--- /dev/null
+++ b/patches/1490-arm64-dts-renesas-r8a77970-Enable-IPMMU-devices.patch
@@ -0,0 +1,43 @@
+From 3d6d3e22642f139033a18cbb61e7cdd9e8ac2a7f Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Sun, 22 Apr 2018 19:08:32 +0900
+Subject: [PATCH 1490/1795] arm64: dts: renesas: r8a77970: Enable IPMMU devices
+
+Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
+in DT on the r8a77970 SoC.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: rebased]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 344aa8f37ebf2a028fb5a1d7fac68b9b1817a2c3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index c06d7fbfb7be..6ed2e95eb53d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -567,7 +567,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 3>;
+ 			power-domains = <&sysc R8A77970_PD_A3IR>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -593,7 +592,6 @@
+ 			renesas,ipmmu-main = <&ipmmu_mm 9>;
+ 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		gic: interrupt-controller@f1010000 {
+-- 
+2.19.0
+
diff --git a/patches/1491-arm64-dts-renesas-r8a77995-Enable-IPMMU-devices.patch b/patches/1491-arm64-dts-renesas-r8a77995-Enable-IPMMU-devices.patch
new file mode 100644
index 00000000000000..2e564db63f0284
--- /dev/null
+++ b/patches/1491-arm64-dts-renesas-r8a77995-Enable-IPMMU-devices.patch
@@ -0,0 +1,107 @@
+From 935095e9131fd1e18858c727edec447d0480a4df Mon Sep 17 00:00:00 2001
+From: Magnus Damm <damm+renesas@opensource.se>
+Date: Sun, 22 Apr 2018 19:08:41 +0900
+Subject: [PATCH 1491/1795] arm64: dts: renesas: r8a77995: Enable IPMMU devices
+
+Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
+in DT on the r8a77995 SoC.
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+[simon: rebased]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 1c2a0de390c8c4c27c2c1dbacbecf85fcbbf9f76)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index a97830589b0d..ba98865b0c9b 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -409,7 +409,6 @@
+ 			reg = <0 0xe6740000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 0>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_ds1: mmu@e7740000 {
+@@ -417,7 +416,6 @@
+ 			reg = <0 0xe7740000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 1>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_hc: mmu@e6570000 {
+@@ -425,7 +423,6 @@
+ 			reg = <0 0xe6570000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 2>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mm: mmu@e67b0000 {
+@@ -434,7 +431,6 @@
+ 			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_mp: mmu@ec670000 {
+@@ -442,7 +438,6 @@
+ 			reg = <0 0xec670000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 4>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_pv0: mmu@fd800000 {
+@@ -450,7 +445,6 @@
+ 			reg = <0 0xfd800000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 6>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_rt: mmu@ffc80000 {
+@@ -458,7 +452,6 @@
+ 			reg = <0 0xffc80000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 10>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vc0: mmu@fe6b0000 {
+@@ -466,7 +459,6 @@
+ 			reg = <0 0xfe6b0000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 12>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vi0: mmu@febd0000 {
+@@ -474,7 +466,6 @@
+ 			reg = <0 0xfebd0000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 14>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		ipmmu_vp0: mmu@fe990000 {
+@@ -482,7 +473,6 @@
+ 			reg = <0 0xfe990000 0 0x1000>;
+ 			renesas,ipmmu-main = <&ipmmu_mm 16>;
+ 			#iommu-cells = <1>;
+-			status = "disabled";
+ 		};
+ 
+ 		avb: ethernet@e6800000 {
+-- 
+2.19.0
+
diff --git a/patches/1492-arm64-dts-renesas-draak-Rename-EtherAVB-mdc-pin-grou.patch b/patches/1492-arm64-dts-renesas-draak-Rename-EtherAVB-mdc-pin-grou.patch
new file mode 100644
index 00000000000000..b72e14dbdd2b65
--- /dev/null
+++ b/patches/1492-arm64-dts-renesas-draak-Rename-EtherAVB-mdc-pin-grou.patch
@@ -0,0 +1,36 @@
+From 676f69f848787b4fb5cf6f4f1939264463ad5b1a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 16:12:00 +0100
+Subject: [PATCH 1492/1795] arm64: dts: renesas: draak: Rename EtherAVB "mdc"
+ pin group to "mdio"
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, now the pinctrl drivers for
+R-Car H3, M3-W, and M3-N have gained support for the traditional pin
+group name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5f7d7808ae1162d55b835cb2faf31db19b69fdf2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+index d03f19414028..9d73de8bc94d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+@@ -91,7 +91,7 @@
+ &pfc {
+ 	avb0_pins: avb {
+ 		mux {
+-			groups = "avb0_link", "avb0_mdc", "avb0_mii";
++			groups = "avb0_link", "avb0_mdio", "avb0_mii";
+ 			function = "avb0";
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1493-arm64-dts-renesas-salvator-common-Rename-EtherAVB-md.patch b/patches/1493-arm64-dts-renesas-salvator-common-Rename-EtherAVB-md.patch
new file mode 100644
index 00000000000000..713faa68fcfacc
--- /dev/null
+++ b/patches/1493-arm64-dts-renesas-salvator-common-Rename-EtherAVB-md.patch
@@ -0,0 +1,43 @@
+From 16b88768fefbf72cf78cbeb230c95f593e0fac77 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 16:11:58 +0100
+Subject: [PATCH 1493/1795] arm64: dts: renesas: salvator-common: Rename
+ EtherAVB "mdc" pin group to "mdio"
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, now the pinctrl drivers for
+R-Car H3, M3-W, and M3-N have gained support for the traditional pin
+group name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 77bf06adb128ef0b47b9c49b1ae8f3313c684a70)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 326ee6b59aaa..9116f4caa3c6 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -414,12 +414,12 @@
+ 
+ 	avb_pins: avb {
+ 		mux {
+-			groups = "avb_link", "avb_mdc", "avb_mii";
++			groups = "avb_link", "avb_mdio", "avb_mii";
+ 			function = "avb";
+ 		};
+ 
+-		pins_mdc {
+-			groups = "avb_mdc";
++		pins_mdio {
++			groups = "avb_mdio";
+ 			drive-strength = <24>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1494-arm64-dts-renesas-ulcb-Rename-EtherAVB-mdc-pin-group.patch b/patches/1494-arm64-dts-renesas-ulcb-Rename-EtherAVB-mdc-pin-group.patch
new file mode 100644
index 00000000000000..f757ac2abccb8e
--- /dev/null
+++ b/patches/1494-arm64-dts-renesas-ulcb-Rename-EtherAVB-mdc-pin-group.patch
@@ -0,0 +1,43 @@
+From 217d9d45a6bd9538ea7997b82a15228cce5bb172 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 16:11:59 +0100
+Subject: [PATCH 1494/1795] arm64: dts: renesas: ulcb: Rename EtherAVB "mdc"
+ pin group to "mdio"
+
+On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
+instead of "mdc".  Fix the inconsistency, now the pinctrl drivers for
+R-Car H3, M3-W, and M3-N have gained support for the traditional pin
+group name.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1518ad140b9ea73cee8bc89e39f8962fbd2bb7bb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index 6f814845f8b6..93402783d52f 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -255,12 +255,12 @@
+ 
+ 	avb_pins: avb {
+ 		mux {
+-			groups = "avb_link", "avb_mdc", "avb_mii";
++			groups = "avb_link", "avb_mdio", "avb_mii";
+ 			function = "avb";
+ 		};
+ 
+-		pins_mdc {
+-			groups = "avb_mdc";
++		pins_mdio {
++			groups = "avb_mdio";
+ 			drive-strength = <24>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1495-arm64-dts-renesas-eagle-add-EtherAVB-pins.patch b/patches/1495-arm64-dts-renesas-eagle-add-EtherAVB-pins.patch
new file mode 100644
index 00000000000000..63dcaae1ec13e6
--- /dev/null
+++ b/patches/1495-arm64-dts-renesas-eagle-add-EtherAVB-pins.patch
@@ -0,0 +1,46 @@
+From 96ad49a2613aa4f61dea231de69d6001a381a461 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 14 Mar 2018 22:58:33 +0300
+Subject: [PATCH 1495/1795] arm64: dts: renesas: eagle: add EtherAVB pins
+
+Add the (previously omitted) EtherAVB pin data to the Eagle board's
+device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1119cffef3bf69e4904f5ea690dcbf70e3372d58)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index ebfbb51ab168..b800a119753b 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -79,6 +79,9 @@
+ };
+ 
+ &avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
+ 	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
+ 	phy-mode = "rgmii-id";
+@@ -148,6 +151,11 @@
+ };
+ 
+ &pfc {
++	avb_pins: avb0 {
++		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
++		function = "avb0";
++	};
++
+ 	i2c0_pins: i2c0 {
+ 		groups = "i2c0";
+ 		function = "i2c0";
+-- 
+2.19.0
+
diff --git a/patches/1496-arm64-dts-renesas-v3msk-add-EtherAVB-pins.patch b/patches/1496-arm64-dts-renesas-v3msk-add-EtherAVB-pins.patch
new file mode 100644
index 00000000000000..4ca151e0299c8e
--- /dev/null
+++ b/patches/1496-arm64-dts-renesas-v3msk-add-EtherAVB-pins.patch
@@ -0,0 +1,46 @@
+From 345d598bb26554b4bafd93315a935a5f5a15fbc4 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 14 Mar 2018 23:30:34 +0300
+Subject: [PATCH 1496/1795] arm64: dts: renesas: v3msk: add EtherAVB pins
+
+Add the (previously omitted) EtherAVB pin data to the V3M Starter Kit
+board's device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 68d3b03fcb5a2e7c71b1e72c6d856e6030c4f2fd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+index a8ceeac77992..55aa01b663e5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -32,6 +32,9 @@
+ };
+ 
+ &avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
+ 	renesas,no-ether-link;
+ 	phy-handle = <&phy0>;
+ 	phy-mode = "rgmii-id";
+@@ -52,6 +55,11 @@
+ };
+ 
+ &pfc {
++	avb_pins: avb0 {
++		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
++		function = "avb0";
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data";
+ 		function = "scif0";
+-- 
+2.19.0
+
diff --git a/patches/1497-arm64-dts-renesas-r8a77980-add-PFC-support.patch b/patches/1497-arm64-dts-renesas-r8a77980-add-PFC-support.patch
new file mode 100644
index 00000000000000..c6057dc5f5921c
--- /dev/null
+++ b/patches/1497-arm64-dts-renesas-r8a77980-add-PFC-support.patch
@@ -0,0 +1,36 @@
+From cbea0f5ba220f8c3d55c86aa1b56840daa4f05aa Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 9 Mar 2018 15:06:32 +0300
+Subject: [PATCH 1497/1795] arm64: dts: renesas: r8a77980: add PFC support
+
+Define the generic R8A77980 part of the PFC device node.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cef26946f247c75a3b1c7919ea801d2ea8511f00)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 03845fd74996..08c6708eb9dd 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -71,6 +71,11 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77980";
++			reg = <0 0xe6060000 0 0x50c>;
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a77980-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/1498-arm64-dts-renesas-condor-add-SCIF0-pins.patch b/patches/1498-arm64-dts-renesas-condor-add-SCIF0-pins.patch
new file mode 100644
index 00000000000000..4fb2909765f5d0
--- /dev/null
+++ b/patches/1498-arm64-dts-renesas-condor-add-SCIF0-pins.patch
@@ -0,0 +1,48 @@
+From 977885ff661eec07cba599175bf966adae334c0d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 9 Mar 2018 15:07:51 +0300
+Subject: [PATCH 1498/1795] arm64: dts: renesas: condor: add SCIF0 pins
+
+Add the (previously omitted) SCIF0 pin data to the Condor board's
+device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a824e63cfcfd60289023d990fe01839ec0db5950)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+index 06cf6845765a..38f11cee42dc 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -49,7 +49,22 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&pfc {
++	scif0_pins: scif0 {
++		groups = "scif0_data";
++		function = "scif0";
++	};
++
++	scif_clk_pins: scif_clk {
++		groups = "scif_clk_b";
++		function = "scif_clk";
++	};
++};
++
+ &scif0 {
++	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
++	pinctrl-names = "default";
++
+ 	status = "okay";
+ };
+ 
+-- 
+2.19.0
+
diff --git a/patches/1499-arm64-dts-renesas-condor-add-EtherAVB-pins.patch b/patches/1499-arm64-dts-renesas-condor-add-EtherAVB-pins.patch
new file mode 100644
index 00000000000000..77ffcc39a513c9
--- /dev/null
+++ b/patches/1499-arm64-dts-renesas-condor-add-EtherAVB-pins.patch
@@ -0,0 +1,46 @@
+From 5f6a6e20d9ede3292128135664995418117adfe2 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 9 Mar 2018 15:09:38 +0300
+Subject: [PATCH 1499/1795] arm64: dts: renesas: condor: add EtherAVB pins
+
+Add the (previously omitted) EtherAVB pin data to the Condor board's
+device tree.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 55cda28160e1ea852955ee17464d0dccfa67fa72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+index 38f11cee42dc..7af5afa41795 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -30,6 +30,9 @@
+ };
+ 
+ &avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++
+ 	phy-mode = "rgmii-id";
+ 	phy-handle = <&phy0>;
+ 	renesas,no-ether-link;
+@@ -50,6 +53,11 @@
+ };
+ 
+ &pfc {
++	avb_pins: avb {
++		groups = "avb_mdio", "avb_rgmii";
++		function = "avb";
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data";
+ 		function = "scif0";
+-- 
+2.19.0
+
diff --git a/patches/1500-arm64-dts-renesas-r8a77980-add-MMC-support.patch b/patches/1500-arm64-dts-renesas-r8a77980-add-MMC-support.patch
new file mode 100644
index 00000000000000..1203952dabfdaf
--- /dev/null
+++ b/patches/1500-arm64-dts-renesas-r8a77980-add-MMC-support.patch
@@ -0,0 +1,42 @@
+From db805fb328b310f4809456c3dd955f19cbf17bb0 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sat, 14 Apr 2018 22:27:04 +0300
+Subject: [PATCH 1500/1795] arm64: dts: renesas: r8a77980: add MMC support
+
+Define the generic R8A77980 part of the MMC0 (SDHI2) device node.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 63eb8ee5333657677789ba3454dd5b86fc53311b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 08c6708eb9dd..d27b80bcdbb4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -353,6 +353,18 @@
+ 			dma-channels = <16>;
+ 		};
+ 
++		mmc0: mmc@ee140000 {
++			compatible = "renesas,sdhi-r8a77980",
++				     "renesas,rcar-gen3-sdhi";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 314>;
++			max-frequency = <200000000>;
++			status = "disabled";
++		};
++
+ 		gic: interrupt-controller@f1010000 {
+ 			compatible = "arm,gic-400";
+ 			#interrupt-cells = <3>;
+-- 
+2.19.0
+
diff --git a/patches/1501-arm64-dts-renesas-r8a7795-add-HDMI-sound-support.patch b/patches/1501-arm64-dts-renesas-r8a7795-add-HDMI-sound-support.patch
new file mode 100644
index 00000000000000..8dff2354f73732
--- /dev/null
+++ b/patches/1501-arm64-dts-renesas-r8a7795-add-HDMI-sound-support.patch
@@ -0,0 +1,45 @@
+From ccf33bdb9f90c4235b662f9e9d119516dad28ef1 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:39:39 +0000
+Subject: [PATCH 1501/1795] arm64: dts: renesas: r8a7795: add HDMI sound
+ support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5a0d8a6f504b04b26ae52449941c45263dd3a478)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 32870cbaf94d..b1c52dae4d49 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -2335,6 +2335,10 @@
+ 				port@1 {
+ 					reg = <1>;
+ 				};
++				port@2 {
++					/* HDMI sound */
++					reg = <2>;
++				};
+ 			};
+ 		};
+ 
+@@ -2360,6 +2364,10 @@
+ 				port@1 {
+ 					reg = <1>;
+ 				};
++				port@2 {
++					/* HDMI sound */
++					reg = <2>;
++				};
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1502-arm64-dts-renesas-r8a7796-add-HDMI-sound-support.patch b/patches/1502-arm64-dts-renesas-r8a7796-add-HDMI-sound-support.patch
new file mode 100644
index 00000000000000..8e1723818c1f72
--- /dev/null
+++ b/patches/1502-arm64-dts-renesas-r8a7796-add-HDMI-sound-support.patch
@@ -0,0 +1,34 @@
+From f7745dc2a9a9052288f5b62a8539590d0ae006e4 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:39:56 +0000
+Subject: [PATCH 1502/1795] arm64: dts: renesas: r8a7796: add HDMI sound
+ support
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c39f09876275022cd3e0095b9ed0a2875a065a3e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index f33063dd7cd7..f41bc25b3933 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -2009,6 +2009,10 @@
+ 				port@1 {
+ 					reg = <1>;
+ 				};
++				port@2 {
++					/* HDMI sound */
++					reg = <2>;
++				};
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1503-arm64-dts-renesas-r8a7795-es1-salvator-x-enable-HDMI.patch b/patches/1503-arm64-dts-renesas-r8a7795-es1-salvator-x-enable-HDMI.patch
new file mode 100644
index 00000000000000..e88cec39754600
--- /dev/null
+++ b/patches/1503-arm64-dts-renesas-r8a7795-es1-salvator-x-enable-HDMI.patch
@@ -0,0 +1,97 @@
+From d9f08536fb7834b01f8f5170e7407cfbd4062794 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:40:34 +0000
+Subject: [PATCH 1503/1795] arm64: dts: renesas: r8a7795-es1-salvator-x: enable
+ HDMI sound
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 6b39e3b68babb7a85b1c4070229c001ca19a6a80)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../dts/renesas/r8a7795-es1-salvator-x.dts    | 46 +++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+index 7f2a3d923f21..3f46345a4644 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+@@ -56,6 +56,12 @@
+ 	status = "okay";
+ };
+ 
++&sound_card {
++	dais = <&rsnd_port0	/* ak4613 */
++		&rsnd_port1	/* HDMI0  */
++		&rsnd_port2>;	/* HDMI1  */
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ 
+@@ -66,6 +72,12 @@
+ 				remote-endpoint = <&hdmi0_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi0_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint1>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -83,6 +95,12 @@
+ 				remote-endpoint = <&hdmi1_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi1_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint2>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -94,6 +112,34 @@
+ 	status = "okay";
+ };
+ 
++&rcar_sound {
++	ports {
++		/* rsnd_port0 is on salvator-common */
++		rsnd_port1: port@1 {
++			rsnd_endpoint1: endpoint {
++				remote-endpoint = <&dw_hdmi0_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint1>;
++				frame-master = <&rsnd_endpoint1>;
++
++				playback = <&ssi2>;
++			};
++		};
++		rsnd_port2: port@2 {
++			rsnd_endpoint2: endpoint {
++				remote-endpoint = <&dw_hdmi1_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint2>;
++				frame-master = <&rsnd_endpoint2>;
++
++				playback = <&ssi3>;
++			};
++		};
++	};
++};
++
+ &pfc {
+ 	usb2_pins: usb2 {
+ 		groups = "usb2";
+-- 
+2.19.0
+
diff --git a/patches/1504-arm64-dts-renesas-r8a7795-salvator-xs-enable-HDMI-so.patch b/patches/1504-arm64-dts-renesas-r8a7795-salvator-xs-enable-HDMI-so.patch
new file mode 100644
index 00000000000000..bd6b3a04e0f31c
--- /dev/null
+++ b/patches/1504-arm64-dts-renesas-r8a7795-salvator-xs-enable-HDMI-so.patch
@@ -0,0 +1,97 @@
+From 8d2099212f051d2ba0d41110351e334dc015d9bb Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:40:52 +0000
+Subject: [PATCH 1504/1795] arm64: dts: renesas: r8a7795-salvator-xs: enable
+ HDMI sound
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit b27ebfa73de08c55414514f632758402529226b4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a7795-salvator-xs.dts  | 46 +++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+index 8b50ceb746e8..83676684c6b4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+@@ -56,6 +56,12 @@
+ 	status = "okay";
+ };
+ 
++&sound_card {
++	dais = <&rsnd_port0	/* ak4613 */
++		&rsnd_port1	/* HDMI0  */
++		&rsnd_port2>;	/* HDMI1  */
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ 
+@@ -66,6 +72,12 @@
+ 				remote-endpoint = <&hdmi0_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi0_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint1>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -83,6 +95,12 @@
+ 				remote-endpoint = <&hdmi1_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi1_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint2>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -94,6 +112,34 @@
+ 	status = "okay";
+ };
+ 
++&rcar_sound {
++	ports {
++		/* rsnd_port0 is on salvator-common */
++		rsnd_port1: port@1 {
++			rsnd_endpoint1: endpoint {
++				remote-endpoint = <&dw_hdmi0_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint1>;
++				frame-master = <&rsnd_endpoint1>;
++
++				playback = <&ssi2>;
++			};
++		};
++		rsnd_port2: port@2 {
++			rsnd_endpoint2: endpoint {
++				remote-endpoint = <&dw_hdmi1_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint2>;
++				frame-master = <&rsnd_endpoint2>;
++
++				playback = <&ssi3>;
++			};
++		};
++	};
++};
++
+ &pfc {
+ 	usb2_pins: usb2 {
+ 		groups = "usb2";
+-- 
+2.19.0
+
diff --git a/patches/1505-arm64-dts-renesas-r8a7796-salvator-xs-enable-HDMI-so.patch b/patches/1505-arm64-dts-renesas-r8a7796-salvator-xs-enable-HDMI-so.patch
new file mode 100644
index 00000000000000..9286e5fe397957
--- /dev/null
+++ b/patches/1505-arm64-dts-renesas-r8a7796-salvator-xs-enable-HDMI-so.patch
@@ -0,0 +1,68 @@
+From 5a685b0de3915fd63179f45387a1c91f62a19869 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:41:07 +0000
+Subject: [PATCH 1505/1795] arm64: dts: renesas: r8a7796-salvator-xs: enable
+ HDMI sound
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d134635f1cd2ba47edbb4c120769f22406373384)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a7796-salvator-xs.dts  | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+index 2c37055efa94..ddf35d4cd5e5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+@@ -40,6 +40,11 @@
+ 		      "dclkin.0", "dclkin.1", "dclkin.2";
+ };
+ 
++&sound_card {
++	dais = <&rsnd_port0	/* ak4613 */
++		&rsnd_port1>;	/* HDMI0  */
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ 
+@@ -50,9 +55,32 @@
+ 				remote-endpoint = <&hdmi0_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi0_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint1>;
++			};
++		};
+ 	};
+ };
+ 
+ &hdmi0_con {
+ 	remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
++
++&rcar_sound {
++	ports {
++		/* rsnd_port0 is on salvator-common */
++		rsnd_port1: port@1 {
++			rsnd_endpoint1: endpoint {
++				remote-endpoint = <&dw_hdmi0_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint1>;
++				frame-master = <&rsnd_endpoint1>;
++
++				playback = <&ssi2>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1506-arm64-dts-renesas-r8a7795-salvator-x-enable-HDMI-sou.patch b/patches/1506-arm64-dts-renesas-r8a7795-salvator-x-enable-HDMI-sou.patch
new file mode 100644
index 00000000000000..2781381d22652b
--- /dev/null
+++ b/patches/1506-arm64-dts-renesas-r8a7795-salvator-x-enable-HDMI-sou.patch
@@ -0,0 +1,97 @@
+From ac1e9ea89e75e31bbc4ff623293d4e80e914d485 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:41:23 +0000
+Subject: [PATCH 1506/1795] arm64: dts: renesas: r8a7795-salvator-x: enable
+ HDMI sound
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a4ff9aed55eb0172291005f0b1a0174be257b892)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a7795-salvator-x.dts   | 46 +++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+index af467419266a..0efbef5ea9b7 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+@@ -56,6 +56,12 @@
+ 	status = "okay";
+ };
+ 
++&sound_card {
++	dais = <&rsnd_port0	/* ak4613 */
++		&rsnd_port1	/* HDMI0  */
++		&rsnd_port2>;	/* HDMI1  */
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ 
+@@ -66,6 +72,12 @@
+ 				remote-endpoint = <&hdmi0_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi0_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint1>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -83,6 +95,12 @@
+ 				remote-endpoint = <&hdmi1_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi1_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint2>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -94,6 +112,34 @@
+ 	status = "okay";
+ };
+ 
++&rcar_sound {
++	ports {
++		/* rsnd_port0 is on salvator-common */
++		rsnd_port1: port@1 {
++			rsnd_endpoint1: endpoint {
++				remote-endpoint = <&dw_hdmi0_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint1>;
++				frame-master = <&rsnd_endpoint1>;
++
++				playback = <&ssi2>;
++			};
++		};
++		rsnd_port2: port@2 {
++			rsnd_endpoint2: endpoint {
++				remote-endpoint = <&dw_hdmi1_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint2>;
++				frame-master = <&rsnd_endpoint2>;
++
++				playback = <&ssi3>;
++			};
++		};
++	};
++};
++
+ &pfc {
+ 	usb2_pins: usb2 {
+ 		groups = "usb2";
+-- 
+2.19.0
+
diff --git a/patches/1507-arm64-dts-renesas-r8a7796-salvator-x-enable-HDMI-sou.patch b/patches/1507-arm64-dts-renesas-r8a7796-salvator-x-enable-HDMI-sou.patch
new file mode 100644
index 00000000000000..0837a1187fd179
--- /dev/null
+++ b/patches/1507-arm64-dts-renesas-r8a7796-salvator-x-enable-HDMI-sou.patch
@@ -0,0 +1,68 @@
+From 709a2be6cf2ffbacb13979ae032229e712c85c46 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Mon, 23 Apr 2018 01:41:39 +0000
+Subject: [PATCH 1507/1795] arm64: dts: renesas: r8a7796-salvator-x: enable
+ HDMI sound
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5c29ba526ca8f4e34a3f2935651f1ab4592c03a3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a7796-salvator-x.dts   | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+index 498c9e807dc4..90cca09b9a5e 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+@@ -40,6 +40,11 @@
+ 		      "dclkin.0", "dclkin.1", "dclkin.2";
+ };
+ 
++&sound_card {
++	dais = <&rsnd_port0	/* ak4613 */
++		&rsnd_port1>;	/* HDMI0  */
++};
++
+ &hdmi0 {
+ 	status = "okay";
+ 
+@@ -50,9 +55,32 @@
+ 				remote-endpoint = <&hdmi0_con>;
+ 			};
+ 		};
++		port@2 {
++			reg = <2>;
++			dw_hdmi0_snd_in: endpoint {
++				remote-endpoint = <&rsnd_endpoint1>;
++			};
++		};
+ 	};
+ };
+ 
+ &hdmi0_con {
+ 	remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
++
++&rcar_sound {
++	ports {
++		/* rsnd_port0 is on salvator-common */
++		rsnd_port1: port@1 {
++			rsnd_endpoint1: endpoint {
++				remote-endpoint = <&dw_hdmi0_snd_in>;
++
++				dai-format = "i2s";
++				bitclock-master = <&rsnd_endpoint1>;
++				frame-master = <&rsnd_endpoint1>;
++
++				playback = <&ssi2>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1508-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-devices.patch b/patches/1508-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-devices.patch
new file mode 100644
index 00000000000000..54906c1cd5314c
--- /dev/null
+++ b/patches/1508-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-devices.patch
@@ -0,0 +1,37 @@
+From db8bc9fb56e1a8b0851aabeade20994699777ec9 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 24 Apr 2018 11:26:59 +0200
+Subject: [PATCH 1508/1795] arm64: dts: renesas: r8a7795-es1: Enable IPMMU
+ devices
+
+Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
+in DT on the r8a7795 ES1.0 Soc.
+
+This is a follow up for a patch by Magnus Damm for the
+the r8a7795 ES2.0 and other R-Car Gen 3 SoCs.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2246f002595aa942b906fc631b7a5e830aa74a39)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index f9acd125d687..0177f5e60e5a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -39,7 +39,6 @@
+ 		reg = <0 0xe7730000 0 0x1000>;
+ 		renesas,ipmmu-main = <&ipmmu_mm 8>;
+ 		#iommu-cells = <1>;
+-		status = "disabled";
+ 	};
+ 
+ 	/delete-node/ usb-phy@ee0e0200;
+-- 
+2.19.0
+
diff --git a/patches/1509-arm64-dts-renesas-r8a77990-Revise-the-psci-node.patch b/patches/1509-arm64-dts-renesas-r8a77990-Revise-the-psci-node.patch
new file mode 100644
index 00000000000000..e5c82d7efc54cd
--- /dev/null
+++ b/patches/1509-arm64-dts-renesas-r8a77990-Revise-the-psci-node.patch
@@ -0,0 +1,35 @@
+From bdf85ab60cc19fbdf6dbf0bb7f31d9321914800b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 25 Apr 2018 17:20:10 +0900
+Subject: [PATCH 1509/1795] arm64: dts: renesas: r8a77990: Revise the psci node
+
+The basic support patch 9491a8b17530 ("arm64: dts: renesas: Add Renesas
+R8A77990 SoC support") lacks the compatible "arm,psci-1.0" in the psci
+node. So, this patch revises it.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bc26b8f4e43acc4d2e3ae0bbf8f20515b4de5c5b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+index 3a19b9ebdd6e..19c1f7cea913 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -50,7 +50,7 @@
+ 	};
+ 
+ 	psci {
+-		compatible = "arm,psci-0.2";
++		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+ 	};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1510-arm64-dts-renesas-r8a77990-Revise-the-cache-controll.patch b/patches/1510-arm64-dts-renesas-r8a77990-Revise-the-cache-controll.patch
new file mode 100644
index 00000000000000..e230382ef8d6b2
--- /dev/null
+++ b/patches/1510-arm64-dts-renesas-r8a77990-Revise-the-cache-controll.patch
@@ -0,0 +1,37 @@
+From b8e6308825bf247b26d2cfe89a6510823b756b2b Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 25 Apr 2018 17:20:09 +0900
+Subject: [PATCH 1510/1795] arm64: dts: renesas: r8a77990: Revise the cache
+ controller node
+
+The cache controller node should not have unit-addresses and reg
+properties. So, this patch removes them.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit de1eb23c6d0f08f6a2eff99afe29b08f023e392d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+index 19c1f7cea913..46580290b7fb 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -27,9 +27,8 @@
+ 			enable-method = "psci";
+ 		};
+ 
+-		L2_CA53: cache-controller@0 {
++		L2_CA53: cache-controller-0 {
+ 			compatible = "cache";
+-			reg = <0>;
+ 			power-domains = <&sysc 21>;
+ 			cache-unified;
+ 			cache-level = <2>;
+-- 
+2.19.0
+
diff --git a/patches/1511-arm64-dts-renesas-r8a77965-Add-FCPF-and-FCPV-instanc.patch b/patches/1511-arm64-dts-renesas-r8a77965-Add-FCPF-and-FCPV-instanc.patch
new file mode 100644
index 00000000000000..dde4737585057d
--- /dev/null
+++ b/patches/1511-arm64-dts-renesas-r8a77965-Add-FCPF-and-FCPV-instanc.patch
@@ -0,0 +1,87 @@
+From 8b0389f304e1dba43ae8c239c55470560c1ea1ea Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:15 +0100
+Subject: [PATCH 1511/1795] arm64: dts: renesas: r8a77965: Add FCPF and FCPV
+ instances
+
+The FCPs handle the interface between various IP cores and memory. Add
+the instances related to the FDPs and VSP2s.
+
+Based on a similar patch of the R8A7796 device tree
+by Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[Kieran: Rebase to top of tree]
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 104243b2e831fd0a5cf86429b9bcea271f7a3d4d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 41 +++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index b12f41755aea..74a7ae4ebccc 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -10,6 +10,7 @@
+ 
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/power/r8a77965-sysc.h>
+ 
+ #define CPG_AUDIO_CLK_I		10
+ 
+@@ -1000,6 +1001,46 @@
+ 			/* placeholder */
+ 		};
+ 
++		fcpf0: fcp@fe950000 {
++			compatible = "renesas,fcpf";
++			reg = <0 0xfe950000 0 0x200>;
++			clocks = <&cpg CPG_MOD 615>;
++			power-domains = <&sysc R8A77965_PD_A3VP>;
++			resets = <&cpg 615>;
++		};
++
++		fcpvb0: fcp@fe96f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfe96f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 607>;
++			power-domains = <&sysc R8A77965_PD_A3VP>;
++			resets = <&cpg 607>;
++		};
++
++		fcpvi0: fcp@fe9af000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfe9af000 0 0x200>;
++			clocks = <&cpg CPG_MOD 611>;
++			power-domains = <&sysc R8A77965_PD_A3VP>;
++			resets = <&cpg 611>;
++		};
++
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 603>;
++		};
++
++		fcpvd1: fcp@fea2f000 {
++			compatible = "renesas,fcpv";
++			reg = <0 0xfea2f000 0 0x200>;
++			clocks = <&cpg CPG_MOD 602>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 602>;
++		};
++
+ 		csi20: csi2@fea80000 {
+ 			reg = <0 0xfea80000 0 0x10000>;
+ 			/* placeholder */
+-- 
+2.19.0
+
diff --git a/patches/1512-arm64-dts-renesas-r8a77965-Add-VSP-instances.patch b/patches/1512-arm64-dts-renesas-r8a77965-Add-VSP-instances.patch
new file mode 100644
index 00000000000000..1df63154eefd62
--- /dev/null
+++ b/patches/1512-arm64-dts-renesas-r8a77965-Add-VSP-instances.patch
@@ -0,0 +1,102 @@
+From 243c1e1c39e2e05d088d912f082312a9dfde530c Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:16 +0100
+Subject: [PATCH 1512/1795] arm64: dts: renesas: r8a77965: Add VSP instances
+
+The r8a77965 has 4 VSP instances.
+
+Based on a similar patch of the R8A7796 device tree
+by Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[Kieran: Rebased to top of tree, fixed sort orders]
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 85cb3229218a99bc0084d58a438d00b36713fd1b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 74a7ae4ebccc..362eddc6b3d1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -1009,6 +1009,17 @@
+ 			resets = <&cpg 615>;
+ 		};
+ 
++		vspb: vsp@fe960000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe960000 0 0x8000>;
++			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 626>;
++			power-domains = <&sysc R8A77965_PD_A3VP>;
++			resets = <&cpg 626>;
++
++			renesas,fcp = <&fcpvb0>;
++		};
++
+ 		fcpvb0: fcp@fe96f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe96f000 0 0x200>;
+@@ -1017,6 +1028,17 @@
+ 			resets = <&cpg 607>;
+ 		};
+ 
++		vspi0: vsp@fe9a0000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfe9a0000 0 0x8000>;
++			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 631>;
++			power-domains = <&sysc R8A77965_PD_A3VP>;
++			resets = <&cpg 631>;
++
++			renesas,fcp = <&fcpvi0>;
++		};
++
+ 		fcpvi0: fcp@fe9af000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfe9af000 0 0x200>;
+@@ -1025,6 +1047,17 @@
+ 			resets = <&cpg 611>;
+ 		};
+ 
++		vspd0: vsp@fea20000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea20000 0 0x8000>;
++			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 623>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 623>;
++
++			renesas,fcp = <&fcpvd0>;
++		};
++
+ 		fcpvd0: fcp@fea27000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfea27000 0 0x200>;
+@@ -1033,6 +1066,17 @@
+ 			resets = <&cpg 603>;
+ 		};
+ 
++		vspd1: vsp@fea28000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea28000 0 0x8000>;
++			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 622>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 622>;
++
++			renesas,fcp = <&fcpvd1>;
++		};
++
+ 		fcpvd1: fcp@fea2f000 {
+ 			compatible = "renesas,fcpv";
+ 			reg = <0 0xfea2f000 0 0x200>;
+-- 
+2.19.0
+
diff --git a/patches/1513-arm64-dts-renesas-r8a77965-Populate-the-DU-instance-.patch b/patches/1513-arm64-dts-renesas-r8a77965-Populate-the-DU-instance-.patch
new file mode 100644
index 00000000000000..9ed427586039f9
--- /dev/null
+++ b/patches/1513-arm64-dts-renesas-r8a77965-Populate-the-DU-instance-.patch
@@ -0,0 +1,49 @@
+From d17a85412a681dcbd9b69a906bfb8acb8b4eeeb4 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:17 +0100
+Subject: [PATCH 1513/1795] arm64: dts: renesas: r8a77965: Populate the DU
+ instance placeholder
+
+The DU entity node has been previously added but only as a placeholder.
+Populate the node with the properties to use the device.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 2f2c71bfc8c5ee3d17304a61c69a4b8ea200b9f9)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 362eddc6b3d1..a35ea2f32da2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -1106,9 +1106,19 @@
+ 		};
+ 
+ 		du: display@feb00000 {
+-			reg = <0 0xfeb00000 0 0x80000>,
+-			      <0 0xfeb90000 0 0x14>;
+-			/* placeholder */
++			compatible = "renesas,du-r8a77965";
++			reg = <0 0xfeb00000 0 0x80000>;
++			reg-names = "du";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 723>,
++				 <&cpg CPG_MOD 721>;
++			clock-names = "du.0", "du.1", "du.3";
++			status = "disabled";
++
++			vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
+ 
+ 			ports {
+ 				#address-cells = <1>;
+-- 
+2.19.0
+
diff --git a/patches/1514-arm64-dts-renesas-r8a77965-Add-HDMI-encoder-instance.patch b/patches/1514-arm64-dts-renesas-r8a77965-Add-HDMI-encoder-instance.patch
new file mode 100644
index 00000000000000..548b26e40fc48f
--- /dev/null
+++ b/patches/1514-arm64-dts-renesas-r8a77965-Add-HDMI-encoder-instance.patch
@@ -0,0 +1,82 @@
+From 83b582e5478ae6e0841f5c69e2d09ba29c83270e Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:18 +0100
+Subject: [PATCH 1514/1795] arm64: dts: renesas: r8a77965: Add HDMI encoder
+ instance
+
+Add the HDMI encoder to the R8A77965 DT in disabled state.
+
+Based on a similar patch of the R8A7796 device tree
+by Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[Kieran: Rebase to top of tree]
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 5daa6f9f160bcc63664aeb6fd597a9e712bcd4d0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 30 ++++++++++++++++++++++-
+ 1 file changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index a35ea2f32da2..b46af2744135 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -8,7 +8,7 @@
+  * Copyright (C) 2016 Renesas Electronics Corp.
+  */
+ 
+-#include <dt-bindings/clock/renesas-cpg-mssr.h>
++#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a77965-sysc.h>
+ 
+@@ -1105,6 +1105,33 @@
+ 			};
+ 		};
+ 
++		hdmi0: hdmi@fead0000 {
++			compatible = "renesas,r8a77965-hdmi",
++				     "renesas,rcar-gen3-hdmi";
++			reg = <0 0xfead0000 0 0x10000>;
++			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 729>,
++				 <&cpg CPG_CORE R8A77965_CLK_HDMI>;
++			clock-names = "iahb", "isfr";
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 729>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				port@0 {
++					reg = <0>;
++					dw_hdmi0_in: endpoint {
++						remote-endpoint = <&du_out_hdmi0>;
++					};
++				};
++				port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a77965";
+ 			reg = <0 0xfeb00000 0 0x80000>;
+@@ -1132,6 +1159,7 @@
+ 				port@1 {
+ 					reg = <1>;
+ 					du_out_hdmi0: endpoint {
++						remote-endpoint = <&dw_hdmi0_in>;
+ 					};
+ 				};
+ 				port@2 {
+-- 
+2.19.0
+
diff --git a/patches/1515-arm64-dts-renesas-r8a77965-salvator-x-Enable-DU-exte.patch b/patches/1515-arm64-dts-renesas-r8a77965-salvator-x-Enable-DU-exte.patch
new file mode 100644
index 00000000000000..eeb8a9d6ef0739
--- /dev/null
+++ b/patches/1515-arm64-dts-renesas-r8a77965-salvator-x-Enable-DU-exte.patch
@@ -0,0 +1,64 @@
+From 81d3453e01b7fb3a93e665965b406774d48b0d9f Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:19 +0100
+Subject: [PATCH 1515/1795] arm64: dts: renesas: r8a77965-salvator-x: Enable DU
+ external clocks and HDMI
+
+The DU1 external dot clock is provided by the fixed frequency clock
+generator X21, while the DU0 and DU3 clocks are provided by the
+programmable Versaclock5 clock generator.
+
+Enable the clocks, and the HDMI encoder for the M3-N Salvator-X board
+and hook it up to the HDMI connector.
+
+Based on patches from Takeshi Kihara <takeshi.kihara.df@renesas.com>
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a0b0be30a096a18f050bc53eed6c9b814d84cfac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a77965-salvator-x.dts  | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+index 75d890d91df9..340a3c72b65a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+@@ -19,3 +19,31 @@
+ 		reg = <0x0 0x48000000 0x0 0x78000000>;
+ 	};
+ };
++
++&du {
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 721>,
++		 <&versaclock5 1>,
++		 <&x21_clk>,
++		 <&versaclock5 2>;
++	clock-names = "du.0", "du.1", "du.3",
++		      "dclkin.0", "dclkin.1", "dclkin.3";
++};
++
++&hdmi0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			reg = <1>;
++			rcar_dw_hdmi0_out: endpoint {
++				remote-endpoint = <&hdmi0_con>;
++			};
++		};
++	};
++};
++
++&hdmi0_con {
++	remote-endpoint = <&rcar_dw_hdmi0_out>;
++};
+-- 
+2.19.0
+
diff --git a/patches/1516-arm64-dts-renesas-r8a77965-salvator-xs-Enable-DU-ext.patch b/patches/1516-arm64-dts-renesas-r8a77965-salvator-xs-Enable-DU-ext.patch
new file mode 100644
index 00000000000000..e066e105164d72
--- /dev/null
+++ b/patches/1516-arm64-dts-renesas-r8a77965-salvator-xs-Enable-DU-ext.patch
@@ -0,0 +1,64 @@
+From 56e2840fdb5e0a368c1f3c5586d039ee713164ac Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Fri, 27 Apr 2018 23:02:20 +0100
+Subject: [PATCH 1516/1795] arm64: dts: renesas: r8a77965-salvator-xs: Enable
+ DU external clocks and HDMI
+
+The DU1 external dot clock is provided by the fixed frequency clock
+generator X21, while the DU0 and DU3 clocks are provided by the
+programmable Versaclock6 clock generator.
+
+Enable the clocks, and the HDMI encoder for the M3-N Salvator-XS, and
+hook it up to the HDMI connector
+
+Based on patches from Takeshi Kihara <takeshi.kihara.df@renesas.com>
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a1f23ed4539ef113397afa69bd227d8a561fb9ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a77965-salvator-xs.dts | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+index a83a00deed9e..9de4e3db1621 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+@@ -19,3 +19,31 @@
+ 		reg = <0x0 0x48000000 0x0 0x78000000>;
+ 	};
+ };
++
++&du {
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 721>,
++		 <&versaclock6 1>,
++		 <&x21_clk>,
++		 <&versaclock6 2>;
++	clock-names = "du.0", "du.1", "du.3",
++		      "dclkin.0", "dclkin.1", "dclkin.3";
++};
++
++&hdmi0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			reg = <1>;
++			rcar_dw_hdmi0_out: endpoint {
++				remote-endpoint = <&hdmi0_con>;
++			};
++		};
++	};
++};
++
++&hdmi0_con {
++	remote-endpoint = <&rcar_dw_hdmi0_out>;
++};
+-- 
+2.19.0
+
diff --git a/patches/1517-arm64-dts-renesas-condor-add-eMMC-support.patch b/patches/1517-arm64-dts-renesas-condor-add-eMMC-support.patch
new file mode 100644
index 00000000000000..eb0dd57f14ebde
--- /dev/null
+++ b/patches/1517-arm64-dts-renesas-condor-add-eMMC-support.patch
@@ -0,0 +1,87 @@
+From 778c415971d9bf8c2b9ffd1e153bce9a408d45ab Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 24 Apr 2018 22:25:24 +0300
+Subject: [PATCH 1517/1795] arm64: dts: renesas: condor: add eMMC support
+
+Define the Condor board dependent part of the MMC0 (connected to eMMC chip)
+device node along with the necessary voltage regulators...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cc9222448a339b62a05bb7cc6f3a091718ff182e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a77980-condor.dts      | 43 +++++++++++++++++++
+ 1 file changed, 43 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+index 7af5afa41795..b8df7604dece 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -27,6 +27,24 @@
+ 		/* first 128MB is reserved for secure area. */
+ 		reg = <0 0x48000000 0 0x78000000>;
+ 	};
++
++	d3_3v: regulator-0 {
++		compatible = "regulator-fixed";
++		regulator-name = "D3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vddq_vin01: regulator-1 {
++		compatible = "regulator-fixed";
++		regulator-name = "VDDQ_VIN01";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
+ };
+ 
+ &avb {
+@@ -52,12 +70,37 @@
+ 	clock-frequency = <32768>;
+ };
+ 
++&mmc0 {
++	pinctrl-0 = <&mmc_pins>;
++	pinctrl-1 = <&mmc_pins_uhs>;
++	pinctrl-names = "default", "state_uhs";
++
++	vmmc-supply = <&d3_3v>;
++	vqmmc-supply = <&vddq_vin01>;
++	mmc-hs200-1_8v;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
+ &pfc {
+ 	avb_pins: avb {
+ 		groups = "avb_mdio", "avb_rgmii";
+ 		function = "avb";
+ 	};
+ 
++	mmc_pins: mmc {
++		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
++		function = "mmc";
++		power-source = <3300>;
++	};
++
++	mmc_pins_uhs: mmc_uhs {
++		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
++		function = "mmc";
++		power-source = <1800>;
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data";
+ 		function = "scif0";
+-- 
+2.19.0
+
diff --git a/patches/1518-arm64-dts-renesas-v3msk-add-DU-LVDS-HDMI-support.patch b/patches/1518-arm64-dts-renesas-v3msk-add-DU-LVDS-HDMI-support.patch
new file mode 100644
index 00000000000000..7a6078d79385b7
--- /dev/null
+++ b/patches/1518-arm64-dts-renesas-v3msk-add-DU-LVDS-HDMI-support.patch
@@ -0,0 +1,185 @@
+From 6d0949f9669f7bd4b317bcefd8863ef904169a2b Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Mon, 23 Apr 2018 23:45:49 +0300
+Subject: [PATCH 1518/1795] arm64: dts: renesas: v3msk: add DU/LVDS/HDMI
+ support
+
+Define the V3M Starter Kit board dependent part of the DU and LVDS device
+nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
+Analog Devices ADV7511W HDMI transmitter...
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0c1861fe0a39e1f4d5d2684f1aec5a60b30c7400)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77970-v3msk.dts | 129 ++++++++++++++++++
+ 1 file changed, 129 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+index 55aa01b663e5..9fce031a596f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+@@ -29,6 +29,65 @@
+ 		/* first 128MB is reserved for secure area. */
+ 		reg = <0x0 0x48000000 0x0 0x38000000>;
+ 	};
++
++	osc5_clk: osc5-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <148500000>;
++	};
++
++	vcc_d1_8v: regulator-0 {
++		compatible = "regulator-fixed";
++		regulator-name = "VCC_D1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_d3_3v: regulator-1 {
++		compatible = "regulator-fixed";
++		regulator-name = "VCC_D3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	lvds-decoder {
++		compatible = "thine,thc63lvd1024";
++		vcc-supply = <&vcc_d3_3v>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				thc63lvd1024_in: endpoint {
++					remote-endpoint = <&lvds0_out>;
++				};
++			};
++
++			port@2 {
++				reg = <2>;
++				thc63lvd1024_out: endpoint {
++					remote-endpoint = <&adv7511_in>;
++				};
++			};
++		};
++	};
++
++	hdmi-out {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con: endpoint {
++				remote-endpoint = <&adv7511_out>;
++			};
++		};
++	};
+ };
+ 
+ &avb {
+@@ -46,6 +105,13 @@
+ 	};
+ };
+ 
++&du {
++	clocks = <&cpg CPG_MOD 724>,
++		 <&osc5_clk>;
++	clock-names = "du.0", "dclkin.0";
++	status = "okay";
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+@@ -60,12 +126,75 @@
+ 		function = "avb0";
+ 	};
+ 
++	i2c0_pins: i2c0 {
++		groups = "i2c0";
++		function = "i2c0";
++	};
++
+ 	scif0_pins: scif0 {
+ 		groups = "scif0_data";
+ 		function = "scif0";
+ 	};
+ };
+ 
++&i2c0 {
++	pinctrl-0 = <&i2c0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	hdmi@39{
++		compatible = "adi,adv7511w";
++		#sound-dai-cells = <0>;
++		reg = <0x39>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
++		avdd-supply = <&vcc_d1_8v>;
++		dvdd-supply = <&vcc_d1_8v>;
++		pvdd-supply = <&vcc_d1_8v>;
++		bgvdd-supply = <&vcc_d1_8v>;
++		dvdd-3v-supply = <&vcc_d3_3v>;
++
++		adi,input-depth = <8>;
++		adi,input-colorspace = "rgb";
++		adi,input-clock = "1x";
++		adi,input-style = <1>;
++		adi,input-justification = "evenly";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7511_in: endpoint {
++					remote-endpoint = <&thc63lvd1024_out>;
++				};
++			};
++
++			port@1 {
++				reg = <1>;
++				adv7511_out: endpoint {
++					remote-endpoint = <&hdmi_con>;
++				};
++			};
++		};
++	};
++};
++
++&lvds0 {
++	status = "okay";
++
++	ports {
++		port@1 {
++			lvds0_out: endpoint {
++				remote-endpoint = <&thc63lvd1024_in>;
++			};
++		};
++	};
++};
++
+ &scif0 {
+ 	pinctrl-0 = <&scif0_pins>;
+ 	pinctrl-names = "default";
+-- 
+2.19.0
+
diff --git a/patches/1519-arm64-dts-renesas-r8a7795-Add-address-properties-to-.patch b/patches/1519-arm64-dts-renesas-r8a7795-Add-address-properties-to-.patch
new file mode 100644
index 00000000000000..bb4bb27ea3d040
--- /dev/null
+++ b/patches/1519-arm64-dts-renesas-r8a7795-Add-address-properties-to-.patch
@@ -0,0 +1,70 @@
+From af2fe4ab3a32d2f9c70b61d15cab63d9eb71957f Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1519/1795] arm64: dts: renesas: r8a7795: Add address
+ properties to rcar_sound port nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The rcar_sound port nodes have unit names and thus should have register
+properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ ...
+ DTC     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb
+ arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property
+  ...
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property
+  DTC     arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property
+arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@2: node has a unit name, but no reg property
+
+Prior to this patch the port nodes only defined in board DTS files.
+As the register properties are common this patch defines the port nodes
+and provides register properties in the SoC DTS file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 2d87dc0e5be26fd45d7e5d0a8e59aad6c74d54c1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index b1c52dae4d49..9b080a864ea1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1711,6 +1711,20 @@
+ 					dma-names = "rx", "tx", "rxu", "txu";
+ 				};
+ 			};
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				port@0 {
++					reg = <0>;
++				};
++				port@1 {
++					reg = <1>;
++				};
++				port@2 {
++					reg = <2>;
++				};
++			};
+ 		};
+ 
+ 		audma0: dma-controller@ec700000 {
+-- 
+2.19.0
+
diff --git a/patches/1520-arm64-dts-renesas-r8a7796-Add-address-properties-to-.patch b/patches/1520-arm64-dts-renesas-r8a7796-Add-address-properties-to-.patch
new file mode 100644
index 00000000000000..8bd93bca79c7dd
--- /dev/null
+++ b/patches/1520-arm64-dts-renesas-r8a7796-Add-address-properties-to-.patch
@@ -0,0 +1,61 @@
+From 00b4bd36e185c9d28315eb2f90265d64e8730691 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1520/1795] arm64: dts: renesas: r8a7796: Add address
+ properties to rcar_sound port nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The rcar_sound port nodes have unit names and thus should have register
+properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ ...
+ DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb
+ arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+ arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property
+ ...
+ DTC     arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb
+ arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+ arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@1: node has a unit name, but no reg property
+
+Prior to this patch the port nodes only defined in board DTS files.
+As the register properties are common this patch defines the port nodes
+and provides register properties in the SoC DTS file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit 78bc93b3ffb2cd71341a3373fd14b62847091b7e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index f41bc25b3933..3fbd86590fb0 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1594,6 +1594,17 @@
+ 					dma-names = "rx", "tx", "rxu", "txu";
+ 				};
+ 			};
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				port@0 {
++					reg = <0>;
++				};
++				port@1 {
++					reg = <1>;
++				};
++			};
+ 		};
+ 
+ 		audma0: dma-controller@ec700000 {
+-- 
+2.19.0
+
diff --git a/patches/1521-arm64-dts-renesas-r8a77965-Add-address-properties-to.patch b/patches/1521-arm64-dts-renesas-r8a77965-Add-address-properties-to.patch
new file mode 100644
index 00000000000000..b5e53cb0146777
--- /dev/null
+++ b/patches/1521-arm64-dts-renesas-r8a77965-Add-address-properties-to.patch
@@ -0,0 +1,55 @@
+From 2395a265061876fd3406860dc890dd459709e1a4 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Thu, 26 Apr 2018 11:42:43 +0200
+Subject: [PATCH 1521/1795] arm64: dts: renesas: r8a77965: Add address
+ properties to rcar_sound port nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The rcar_sound port nodes have unit names and thus should have register
+properties.
+
+This is flagged by dtc as follows:
+ # make dtbs W=1
+ ...
+ DTC     arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dtb
+arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+ DTC     arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dtb
+arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dtb: Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property
+
+Prior to this patch the port nodes only defined in board DTS files.
+As the register properties are common this patch defines the port nodes
+and provides register properties in the SoC DTS file.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+(cherry picked from commit e94ac4c7f4f0b9b2c28cfba3b7c6ba089092a22d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index b46af2744135..7c9555309c0a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -857,6 +857,14 @@
+ 				ssi1: ssi-1 {
+ 				};
+ 			};
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				port@0 {
++					reg = <0>;
++				};
++			};
+ 		};
+ 
+ 		xhci0: usb@ee000000 {
+-- 
+2.19.0
+
diff --git a/patches/1522-arm64-dts-renesas-r8a77980-use-CPG-core-clock-macros.patch b/patches/1522-arm64-dts-renesas-r8a77980-use-CPG-core-clock-macros.patch
new file mode 100644
index 00000000000000..7a679cbe1eb31a
--- /dev/null
+++ b/patches/1522-arm64-dts-renesas-r8a77980-use-CPG-core-clock-macros.patch
@@ -0,0 +1,119 @@
+From 15b7c22f60daba4277ac8d5eb2a1677f022d8a99 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 26 Apr 2018 13:43:56 +0300
+Subject: [PATCH 1522/1795] arm64: dts: renesas: r8a77980: use CPG core clock
+ macros
+
+Now that the commit 35b3c462dae1 ("dt-bindings: clock: add R8A77980 CPG
+core clock definitions") has hit Linus' tree, we can replace the bare
+numbers (we had to use to avoid a cross tree dependency) with these macro
+definitions...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c64cc3683ff2622fe3528af93a5df01a6584e871)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index d27b80bcdbb4..fddbaf250087 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -6,9 +6,9 @@
+  * Copyright (C) 2018 Cogent Embedded, Inc.
+  */
+ 
++#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+-#include <dt-bindings/clock/renesas-cpg-mssr.h>
+ 
+ / {
+ 	compatible = "renesas,r8a77980";
+@@ -23,7 +23,7 @@
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0>;
+-			clocks = <&cpg CPG_CORE 0>;
++			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ 			power-domains = <&sysc 5>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
+@@ -104,7 +104,7 @@
+ 			reg = <0 0xe6540000 0 0x60>;
+ 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 520>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+@@ -122,7 +122,7 @@
+ 			reg = <0 0xe6550000 0 0x60>;
+ 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 519>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+@@ -140,7 +140,7 @@
+ 			reg = <0 0xe6560000 0 0x60>;
+ 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 518>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+@@ -158,7 +158,7 @@
+ 			reg = <0 0xe66a0000 0 0x60>;
+ 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 517>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+@@ -220,7 +220,7 @@
+ 			reg = <0 0xe6e60000 0 0x40>;
+ 			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 207>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+@@ -238,7 +238,7 @@
+ 			reg = <0 0xe6e68000 0 0x40>;
+ 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 206>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+@@ -256,7 +256,7 @@
+ 			reg = <0 0xe6c50000 0 0x40>;
+ 			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 204>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+@@ -274,7 +274,7 @@
+ 			reg = <0 0xe6c40000 0 0x40>;
+ 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 203>,
+-				 <&cpg CPG_CORE 19>,
++				 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+-- 
+2.19.0
+
diff --git a/patches/1523-arm64-dts-renesas-r8a77980-use-SYSC-power-domain-mac.patch b/patches/1523-arm64-dts-renesas-r8a77980-use-SYSC-power-domain-mac.patch
new file mode 100644
index 00000000000000..f6ef0bcee67da8
--- /dev/null
+++ b/patches/1523-arm64-dts-renesas-r8a77980-use-SYSC-power-domain-mac.patch
@@ -0,0 +1,169 @@
+From d92a9de0be745991a73b7e0017c65c4ac65b33b0 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 26 Apr 2018 13:45:21 +0300
+Subject: [PATCH 1523/1795] arm64: dts: renesas: r8a77980: use SYSC power
+ domain macros
+
+Now that the commit 7755b40d07a8 ("dt-bindings: power: add R8A77980 SYSC
+power domain definitions") has hit Linus' tree, we can replace  the bare
+numbers (we had to use to avoid a cross tree dependency) with these macro
+definitions...
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1184ea3fd4c83a7bf6a8f51fcf73d620706557ce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 31 ++++++++++++-----------
+ 1 file changed, 16 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index fddbaf250087..5c865fcd3986 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/power/r8a77980-sysc.h>
+ 
+ / {
+ 	compatible = "renesas,r8a77980";
+@@ -24,14 +25,14 @@
+ 			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0>;
+ 			clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+-			power-domains = <&sysc 5>;
++			power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
+ 			next-level-cache = <&L2_CA53>;
+ 			enable-method = "psci";
+ 		};
+ 
+ 		L2_CA53: cache-controller {
+ 			compatible = "cache";
+-			power-domains = <&sysc 21>;
++			power-domains = <&sysc R8A77980_PD_CA53_SCU>;
+ 			cache-unified;
+ 			cache-level = <2>;
+ 		};
+@@ -110,7 +111,7 @@
+ 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ 			       <&dmac2 0x31>, <&dmac2 0x30>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 520>;
+ 			status = "disabled";
+ 		};
+@@ -128,7 +129,7 @@
+ 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ 			       <&dmac2 0x33>, <&dmac2 0x32>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 519>;
+ 			status = "disabled";
+ 		};
+@@ -146,7 +147,7 @@
+ 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ 			       <&dmac2 0x35>, <&dmac2 0x34>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 518>;
+ 			status = "disabled";
+ 		};
+@@ -164,7 +165,7 @@
+ 			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ 			       <&dmac2 0x37>, <&dmac2 0x36>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 517>;
+ 			status = "disabled";
+ 		};
+@@ -206,7 +207,7 @@
+ 					  "ch20", "ch21", "ch22", "ch23",
+ 					  "ch24";
+ 			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii";
+ 			#address-cells = <1>;
+@@ -226,7 +227,7 @@
+ 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ 			       <&dmac2 0x51>, <&dmac2 0x50>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 207>;
+ 			status = "disabled";
+ 		};
+@@ -244,7 +245,7 @@
+ 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ 			       <&dmac2 0x53>, <&dmac2 0x52>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 206>;
+ 			status = "disabled";
+ 		};
+@@ -262,7 +263,7 @@
+ 			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ 			       <&dmac2 0x57>, <&dmac2 0x56>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 204>;
+ 			status = "disabled";
+ 		};
+@@ -280,7 +281,7 @@
+ 			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ 			       <&dmac2 0x59>, <&dmac2 0x58>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
+@@ -313,7 +314,7 @@
+ 					  "ch12", "ch13", "ch14", "ch15";
+ 			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
+@@ -347,7 +348,7 @@
+ 					  "ch12", "ch13", "ch14", "ch15";
+ 			clocks = <&cpg CPG_MOD 217>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
+@@ -359,7 +360,7 @@
+ 			reg = <0 0xee140000 0 0x2000>;
+ 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 314>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 314>;
+ 			max-frequency = <200000000>;
+ 			status = "disabled";
+@@ -378,7 +379,7 @@
+ 				      IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ 			resets = <&cpg 408>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1524-arm64-dts-renesas-r8a77965-use-r8a77965-sysc-binding.patch b/patches/1524-arm64-dts-renesas-r8a77965-use-r8a77965-sysc-binding.patch
new file mode 100644
index 00000000000000..41372873b1ce7b
--- /dev/null
+++ b/patches/1524-arm64-dts-renesas-r8a77965-use-r8a77965-sysc-binding.patch
@@ -0,0 +1,453 @@
+From c4b6c2007932f8517dd7da96df6c56984acc52fb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 26 Apr 2018 21:34:47 +0200
+Subject: [PATCH 1524/1795] arm64: dts: renesas: r8a77965: use r8a77965-sysc
+ binding definitions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Replace the hardcoded power domain indices by R8A77965_PD_* symbols.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
+[simon: dropped hunk to include r8a77965-sysc.h which is already present]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 7e26520fb466ddbecf7d0c1eea44126c1a353a19)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 94 +++++++++++------------
+ 1 file changed, 47 insertions(+), 47 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 7c9555309c0a..536fed8eec6a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -61,7 +61,7 @@
+ 			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x0>;
+ 			device_type = "cpu";
+-			power-domains = <&sysc 0>;
++			power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
+ 		};
+@@ -70,14 +70,14 @@
+ 			compatible = "arm,cortex-a57","arm,armv8";
+ 			reg = <0x1>;
+ 			device_type = "cpu";
+-			power-domains = <&sysc 1>;
++			power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
+ 			next-level-cache = <&L2_CA57>;
+ 			enable-method = "psci";
+ 		};
+ 
+ 		L2_CA57: cache-controller-0 {
+ 			compatible = "cache";
+-			power-domains = <&sysc 12>;
++			power-domains = <&sysc R8A77965_PD_CA57_SCU>;
+ 			cache-unified;
+ 			cache-level = <2>;
+ 		};
+@@ -147,7 +147,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 912>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 912>;
+ 		};
+ 
+@@ -162,7 +162,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 911>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 911>;
+ 		};
+ 
+@@ -177,7 +177,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 910>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 910>;
+ 		};
+ 
+@@ -192,7 +192,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 909>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 909>;
+ 		};
+ 
+@@ -207,7 +207,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 908>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 908>;
+ 		};
+ 
+@@ -222,7 +222,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 907>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 907>;
+ 		};
+ 
+@@ -237,7 +237,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 906>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 906>;
+ 		};
+ 
+@@ -252,7 +252,7 @@
+ 			#interrupt-cells = <2>;
+ 			interrupt-controller;
+ 			clocks = <&cpg CPG_MOD 905>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 905>;
+ 		};
+ 
+@@ -294,7 +294,7 @@
+ 				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ 				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 407>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 407>;
+ 		};
+ 
+@@ -348,7 +348,7 @@
+ 			reg = <0 0xe60b0000 0 0x425>;
+ 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 926>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 926>;
+ 			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ 			dma-names = "tx", "rx";
+@@ -367,7 +367,7 @@
+ 			renesas,buswait = <11>;
+ 			phys = <&usb2_phy0>;
+ 			phy-names = "usb";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 704>;
+ 			status = "disabled";
+ 		};
+@@ -380,7 +380,7 @@
+ 				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "ch0", "ch1";
+ 			clocks = <&cpg CPG_MOD 330>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 330>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <2>;
+@@ -394,7 +394,7 @@
+ 				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "ch0", "ch1";
+ 			clocks = <&cpg CPG_MOD 331>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 331>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <2>;
+@@ -407,7 +407,7 @@
+ 			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+ 				 <&usb_extal_clk>;
+ 			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 328>;
+ 			#phy-cells = <0>;
+ 			status = "disabled";
+@@ -441,7 +441,7 @@
+ 					"ch12", "ch13", "ch14", "ch15";
+ 			clocks = <&cpg CPG_MOD 219>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 219>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
+@@ -475,7 +475,7 @@
+ 					"ch12", "ch13", "ch14", "ch15";
+ 			clocks = <&cpg CPG_MOD 218>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 218>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
+@@ -509,7 +509,7 @@
+ 					"ch12", "ch13", "ch14", "ch15";
+ 			clocks = <&cpg CPG_MOD 217>;
+ 			clock-names = "fck";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 217>;
+ 			#dma-cells = <1>;
+ 			dma-channels = <16>;
+@@ -552,7 +552,7 @@
+ 					  "ch20", "ch21", "ch22", "ch23",
+ 					  "ch24";
+ 			clocks = <&cpg CPG_MOD 812>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 812>;
+ 			phy-mode = "rgmii";
+ 			#address-cells = <1>;
+@@ -566,7 +566,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -576,7 +576,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -586,7 +586,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -596,7 +596,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -606,7 +606,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -616,7 +616,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -626,7 +626,7 @@
+ 			#pwm-cells = <2>;
+ 			clocks = <&cpg CPG_MOD 523>;
+ 			resets = <&cpg 523>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -642,7 +642,7 @@
+ 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ 			       <&dmac2 0x51>, <&dmac2 0x50>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 207>;
+ 			status = "disabled";
+ 		};
+@@ -659,7 +659,7 @@
+ 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ 			       <&dmac2 0x53>, <&dmac2 0x52>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 206>;
+ 			status = "disabled";
+ 		};
+@@ -673,7 +673,7 @@
+ 				 <&cpg CPG_CORE 20>,
+ 				 <&scif_clk>;
+ 			clock-names = "fck", "brg_int", "scif_clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 310>;
+ 			status = "disabled";
+ 		};
+@@ -689,7 +689,7 @@
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ 			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 204>;
+ 			status = "disabled";
+ 		};
+@@ -705,7 +705,7 @@
+ 			clock-names = "fck", "brg_int", "scif_clk";
+ 			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ 			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 203>;
+ 			status = "disabled";
+ 		};
+@@ -722,7 +722,7 @@
+ 			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ 			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 202>;
+ 			status = "disabled";
+ 		};
+@@ -736,7 +736,7 @@
+ 			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ 			       <&dmac2 0x41>, <&dmac2 0x40>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 211>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -752,7 +752,7 @@
+ 			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ 			       <&dmac2 0x43>, <&dmac2 0x42>;
+ 			dma-names = "tx", "rx", "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 210>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -767,7 +767,7 @@
+ 			clocks = <&cpg CPG_MOD 209>;
+ 			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+ 			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 209>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -782,7 +782,7 @@
+ 			clocks = <&cpg CPG_MOD 208>;
+ 			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+ 			dma-names = "tx", "rx";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 208>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -873,7 +873,7 @@
+ 			reg = <0 0xee000000 0 0xc00>;
+ 			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 328>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 328>;
+ 			status = "disabled";
+ 		};
+@@ -884,7 +884,7 @@
+ 			reg = <0 0xee020000 0 0x400>;
+ 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 328>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 328>;
+ 			status = "disabled";
+ 		};
+@@ -896,7 +896,7 @@
+ 			clocks = <&cpg CPG_MOD 703>;
+ 			phys = <&usb2_phy0>;
+ 			phy-names = "usb";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			status = "disabled";
+ 		};
+@@ -908,7 +908,7 @@
+ 			clocks = <&cpg CPG_MOD 702>;
+ 			phys = <&usb2_phy1>;
+ 			phy-names = "usb";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 702>;
+ 			status = "disabled";
+ 		};
+@@ -921,7 +921,7 @@
+ 			phys = <&usb2_phy0>;
+ 			phy-names = "usb";
+ 			companion = <&ohci0>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			status = "disabled";
+ 		};
+@@ -934,7 +934,7 @@
+ 			phys = <&usb2_phy1>;
+ 			phy-names = "usb";
+ 			companion = <&ohci1>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 702>;
+ 			status = "disabled";
+ 		};
+@@ -945,7 +945,7 @@
+ 			reg = <0 0xee080200 0 0x700>;
+ 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			#phy-cells = <0>;
+ 			status = "disabled";
+@@ -956,7 +956,7 @@
+ 				     "renesas,rcar-gen3-usb2-phy";
+ 			reg = <0 0xee0a0200 0 0x700>;
+ 			clocks = <&cpg CPG_MOD 703>;
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 703>;
+ 			#phy-cells = <0>;
+ 			status = "disabled";
+@@ -995,7 +995,7 @@
+ 					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+-			power-domains = <&sysc 32>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ 			resets = <&cpg 408>;
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1525-arm64-dts-renesas-r8a77965-Add-R-Car-Gen3-thermal-su.patch b/patches/1525-arm64-dts-renesas-r8a77965-Add-R-Car-Gen3-thermal-su.patch
new file mode 100644
index 00000000000000..3b09528556ee95
--- /dev/null
+++ b/patches/1525-arm64-dts-renesas-r8a77965-Add-R-Car-Gen3-thermal-su.patch
@@ -0,0 +1,103 @@
+From b5d44e5b6a8dcd6537ee3aeca0cbbbf55ad9f967 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Thu, 26 Apr 2018 21:49:06 +0200
+Subject: [PATCH 1525/1795] arm64: dts: renesas: r8a77965: Add R-Car Gen3
+ thermal support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Based on previous work by Ryo Kataoka <ryo.kataoka.wt@renesas.com>.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+[simon: moved thermal node to preseve ordering of nodes by bus address]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 4c529600eef0a6b77e9fd27d89fbe0d2f030ede4)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 59 +++++++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 536fed8eec6a..b93281affd63 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -282,6 +282,21 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		tsc: thermal@e6198000 {
++			compatible = "renesas,r8a77965-thermal";
++			reg = <0 0xe6198000 0 0x100>,
++			      <0 0xe61a0000 0 0x100>,
++			      <0 0xe61a8000 0 0x100>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 522>;
++			#thermal-sensor-cells = <1>;
++			status = "okay";
++		};
++
+ 		intc_ex: interrupt-controller@e61c0000 {
+ 			compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
+ 			#interrupt-cells = <2>;
+@@ -1192,6 +1207,50 @@
+ 				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ 
++	thermal-zones {
++		sensor_thermal1: sensor-thermal1 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 0>;
++
++			trips {
++				sensor1_crit: sensor1-crit {
++					temperature = <120000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		sensor_thermal2: sensor-thermal2 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 1>;
++
++			trips {
++				sensor2_crit: sensor2-crit {
++					temperature = <120000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++
++		sensor_thermal3: sensor-thermal3 {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++			thermal-sensors = <&tsc 2>;
++
++			trips {
++				sensor3_crit: sensor3-crit {
++					temperature = <120000>;
++					hysteresis = <1000>;
++					type = "critical";
++				};
++			};
++		};
++	};
++
+ 	/* External USB clocks - can be overridden by the board */
+ 	usb3s0_clk: usb3s0 {
+ 		compatible = "fixed-clock";
+-- 
+2.19.0
+
diff --git a/patches/1526-arm64-dts-renesas-r8a77970-add-CAN-FD-support.patch b/patches/1526-arm64-dts-renesas-r8a77970-add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..c0c0a551ce621f
--- /dev/null
+++ b/patches/1526-arm64-dts-renesas-r8a77970-add-CAN-FD-support.patch
@@ -0,0 +1,73 @@
+From 3437095ecd4e1fda4f4369c4ec72e94621d10255 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 26 Apr 2018 23:33:14 +0300
+Subject: [PATCH 1526/1795] arm64: dts: renesas: r8a77970: add CAN-FD support
+
+Define the generic R8A77970 part of the CAN-FD device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 81a579d53a89dbf8380cefff37794c0321cfbed5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 6ed2e95eb53d..37b843c0677a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -68,6 +68,13 @@
+ 		method = "smc";
+ 	};
+ 
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	/* External SCIF clock - to be overridden by boards that provide it */
+ 	scif_clk: scif {
+ 		compatible = "fixed-clock";
+@@ -381,6 +388,31 @@
+ 			status = "disabled";
+ 		};
+ 
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a77970-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++				 <&cpg CPG_CORE R8A77970_CLK_CANFD>,
++				 <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77970",
+ 				     "renesas,etheravb-rcar-gen3";
+-- 
+2.19.0
+
diff --git a/patches/1527-arm64-dts-renesas-eagle-add-CAN-FD-support.patch b/patches/1527-arm64-dts-renesas-eagle-add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..f5671b09610d05
--- /dev/null
+++ b/patches/1527-arm64-dts-renesas-eagle-add-CAN-FD-support.patch
@@ -0,0 +1,56 @@
+From 26ec5f4ce821f6b595aa6aada4cb006e1f2d3960 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 26 Apr 2018 23:34:35 +0300
+Subject: [PATCH 1527/1795] arm64: dts: renesas: eagle: add CAN-FD support
+
+Define the Eagle board dependent part of the CAN-FD device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Acked-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit bb8d20331f051a920df21aaf263a189e2ede20e6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+index b800a119753b..21f9cf5c6e84 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+@@ -95,6 +95,16 @@
+ 	};
+ };
+ 
++&canfd {
++	pinctrl-0 = <&canfd0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	channel0 {
++		status = "okay";
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+@@ -156,6 +166,11 @@
+ 		function = "avb0";
+ 	};
+ 
++	canfd0_pins: canfd0 {
++		groups = "canfd0_data_a";
++		function = "canfd0";
++	};
++
+ 	i2c0_pins: i2c0 {
+ 		groups = "i2c0";
+ 		function = "i2c0";
+-- 
+2.19.0
+
diff --git a/patches/1528-arm64-dts-renesas-r8a77980-add-CAN-FD-support.patch b/patches/1528-arm64-dts-renesas-r8a77980-add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..cd76e5afd077e5
--- /dev/null
+++ b/patches/1528-arm64-dts-renesas-r8a77980-add-CAN-FD-support.patch
@@ -0,0 +1,73 @@
+From 5bfda709fb6e8aa880852bb26b30c3bd6f3fde11 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 27 Apr 2018 22:12:51 +0300
+Subject: [PATCH 1528/1795] arm64: dts: renesas: r8a77980: add CAN-FD support
+
+Define the generic R8A77980 part of the CAN-FD device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+[simon: consistently use tabs for indentation]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit f38c41727211f2cdd9bb6f2999d46daafeacc5aa)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 31 +++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 5c865fcd3986..3a127643d1dc 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -38,6 +38,13 @@
+ 		};
+ 	};
+ 
++	/* External CAN clock - to be overridden by boards that provide it */
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
+ 	extal_clk: extal {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+@@ -170,6 +177,30 @@
+ 			status = "disabled";
+ 		};
+ 
++		canfd: can@e66c0000 {
++			compatible = "renesas,r8a77980-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++				 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
++				 <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
+ 		avb: ethernet@e6800000 {
+ 			compatible = "renesas,etheravb-r8a77980",
+ 				     "renesas,etheravb-rcar-gen3";
+-- 
+2.19.0
+
diff --git a/patches/1529-arm64-dts-renesas-condor-add-CAN-FD-support.patch b/patches/1529-arm64-dts-renesas-condor-add-CAN-FD-support.patch
new file mode 100644
index 00000000000000..d641cab10659b5
--- /dev/null
+++ b/patches/1529-arm64-dts-renesas-condor-add-CAN-FD-support.patch
@@ -0,0 +1,55 @@
+From bd2c221250b4191d5def2a5557cbefd63d400eff Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 27 Apr 2018 22:14:26 +0300
+Subject: [PATCH 1529/1795] arm64: dts: renesas: condor: add CAN-FD support
+
+Define the Condor board dependent part of the CAN-FD device node.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 7a9706d25fe4707ee35be543f3e7ae01183ae86d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+index b8df7604dece..0b93a7d76585 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+@@ -62,6 +62,16 @@
+ 	};
+ };
+ 
++&canfd {
++	pinctrl-0 = <&canfd0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	channel0 {
++		status = "okay";
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <16666666>;
+ };
+@@ -89,6 +99,11 @@
+ 		function = "avb";
+ 	};
+ 
++	canfd0_pins: canfd0 {
++		groups = "canfd0_data_a";
++		function = "canfd0";
++	};
++
+ 	mmc_pins: mmc {
+ 		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+ 		function = "mmc";
+-- 
+2.19.0
+
diff --git a/patches/1530-arm64-dts-renesas-salvator-common-add-eeprom.patch b/patches/1530-arm64-dts-renesas-salvator-common-add-eeprom.patch
new file mode 100644
index 00000000000000..30637cd18bd71b
--- /dev/null
+++ b/patches/1530-arm64-dts-renesas-salvator-common-add-eeprom.patch
@@ -0,0 +1,37 @@
+From 4b24f4c5e3832a93fbf337b498ebb3ecc5e528b9 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sun, 29 Apr 2018 20:26:39 +0200
+Subject: [PATCH 1530/1795] arm64: dts: renesas: salvator-common: add eeprom
+
+Add the EEPROM found on Salvator-X and -XS boards for H3, M3-W, and M3-N
+on the IIC_DVFS bus.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 99b1eb0f62f90159da2c0ff7791f4db9f9c66f64)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 9116f4caa3c6..803220a02f50 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -385,6 +385,12 @@
+ 			};
+ 		};
+ 	};
++
++	eeprom@50 {
++		compatible = "rohm,br24t01", "atmel,24c01";
++		reg = <0x50>;
++		pagesize = <8>;
++	};
+ };
+ 
+ &ohci0 {
+-- 
+2.19.0
+
diff --git a/patches/1531-arm64-dts-renesas-r8a7795-salvator-xs-enable-usb2_ph.patch b/patches/1531-arm64-dts-renesas-r8a7795-salvator-xs-enable-usb2_ph.patch
new file mode 100644
index 00000000000000..7bd4c8146c8d07
--- /dev/null
+++ b/patches/1531-arm64-dts-renesas-r8a7795-salvator-xs-enable-usb2_ph.patch
@@ -0,0 +1,60 @@
+From 2dda1b1bff3b1372e8dbfde6868a492bda347746 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 27 Apr 2018 15:34:30 +0900
+Subject: [PATCH 1531/1795] arm64: dts: renesas: r8a7795: salvator-xs: enable
+ usb2_phy3 node
+
+This patch enables usb2_phy3 node for r8a7795 with Salvator-XS.
+You must change the SW31 to OFF-OFF-ON-ON-ON-ON on the board.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cd49f631dd7dc2dcd08a22c0f78197aa7970fe5d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/r8a7795-salvator-xs.dts  | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+index 83676684c6b4..622b2a22ab0f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+@@ -145,6 +145,23 @@
+ 		groups = "usb2";
+ 		function = "usb2";
+ 	};
++
++	/*
++	 * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
++	 *   (when SW31 is the default setting on Salvator-XS).
++	 * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
++	 *   r8a7795 with Salvator-XS.
++	 *   Hence the SW31 setting must be changed like 2) below.
++	 *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
++	 *	- Connect GP6_3[01] to ADV7842.
++	 *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
++	 *	- Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
++	 *	- Connect GP6_{04,21} to ADV7842.
++	 */
++	usb2_ch3_pins: usb2_ch3 {
++		groups = "usb2_ch3";
++		function = "usb2_ch3";
++	};
+ };
+ 
+ &usb2_phy2 {
+@@ -153,3 +170,10 @@
+ 
+ 	status = "okay";
+ };
++
++&usb2_phy3 {
++	pinctrl-0 = <&usb2_ch3_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1532-arm64-dts-renesas-r8a7795-salvator-xs-enable-hsusb-c.patch b/patches/1532-arm64-dts-renesas-r8a7795-salvator-xs-enable-hsusb-c.patch
new file mode 100644
index 00000000000000..cdc043161e2358
--- /dev/null
+++ b/patches/1532-arm64-dts-renesas-r8a7795-salvator-xs-enable-hsusb-c.patch
@@ -0,0 +1,36 @@
+From 25d8e705623306214fe1bf01e981c4bfe7d9816f Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 27 Apr 2018 15:34:31 +0900
+Subject: [PATCH 1532/1795] arm64: dts: renesas: r8a7795: salvator-xs: enable
+ hsusb channel 3 node
+
+This patch enables HS-USB channel3 node for r8a7795 with Salvator-XS.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 5650011a0607930b1691108ad66034aef1a75fa0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+index 622b2a22ab0f..bbf5a8812b70 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+@@ -56,6 +56,11 @@
+ 	status = "okay";
+ };
+ 
++&hsusb3 {
++	dr_mode = "otg";
++	status = "okay";
++};
++
+ &sound_card {
+ 	dais = <&rsnd_port0	/* ak4613 */
+ 		&rsnd_port1	/* HDMI0  */
+-- 
+2.19.0
+
diff --git a/patches/1533-arm64-dts-renesas-r8a7795-salvator-xs-enable-USB2.0-.patch b/patches/1533-arm64-dts-renesas-r8a7795-salvator-xs-enable-USB2.0-.patch
new file mode 100644
index 00000000000000..3b506db0cb0b2c
--- /dev/null
+++ b/patches/1533-arm64-dts-renesas-r8a7795-salvator-xs-enable-USB2.0-.patch
@@ -0,0 +1,48 @@
+From a2cff71cebfbd453c03249b1c2666f35abd59ce9 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 27 Apr 2018 15:34:32 +0900
+Subject: [PATCH 1533/1795] arm64: dts: renesas: r8a7795: salvator-xs: enable
+ USB2.0 host channel 3
+
+This patch enables USB2.0 host channel 3 for r8a7795 with Salvator-XS.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 610fd5deb11ab0ec0af318e0912da8b1dcb5637d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+index bbf5a8812b70..e231b5a7cbab 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+@@ -56,6 +56,11 @@
+ 	status = "okay";
+ };
+ 
++&ehci3 {
++	dr_mode = "otg";
++	status = "okay";
++};
++
+ &hsusb3 {
+ 	dr_mode = "otg";
+ 	status = "okay";
+@@ -117,6 +122,11 @@
+ 	status = "okay";
+ };
+ 
++&ohci3 {
++	dr_mode = "otg";
++	status = "okay";
++};
++
+ &rcar_sound {
+ 	ports {
+ 		/* rsnd_port0 is on salvator-common */
+-- 
+2.19.0
+
diff --git a/patches/1534-arm64-dts-renesas-r8a7795-Correct-whitespace.patch b/patches/1534-arm64-dts-renesas-r8a7795-Correct-whitespace.patch
new file mode 100644
index 00000000000000..c6f197136df774
--- /dev/null
+++ b/patches/1534-arm64-dts-renesas-r8a7795-Correct-whitespace.patch
@@ -0,0 +1,87 @@
+From 3a5581553799f777ebaacac07894503b384a575f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:38:28 +0200
+Subject: [PATCH 1534/1795] arm64: dts: renesas: r8a7795: Correct whitespace
+
+Add missing spaces after commas.
+Replace 8 consecutive spaces by a TAB.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 399ec3ffb161ccfa0a6aba4e3162a1c5ec90af71)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 9b080a864ea1..91486b4910ce 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -132,7 +132,7 @@
+ 		};
+ 
+ 		a57_1: cpu@1 {
+-			compatible = "arm,cortex-a57","arm,armv8";
++			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x1>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
+@@ -144,7 +144,7 @@
+ 		};
+ 
+ 		a57_2: cpu@2 {
+-			compatible = "arm,cortex-a57","arm,armv8";
++			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x2>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
+@@ -156,7 +156,7 @@
+ 		};
+ 
+ 		a57_3: cpu@3 {
+-			compatible = "arm,cortex-a57","arm,armv8";
++			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x3>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
+@@ -179,7 +179,7 @@
+ 		};
+ 
+ 		a53_1: cpu@101 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x101>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+@@ -190,7 +190,7 @@
+ 		};
+ 
+ 		a53_2: cpu@102 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x102>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+@@ -201,7 +201,7 @@
+ 		};
+ 
+ 		a53_3: cpu@103 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x103>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+@@ -262,7 +262,7 @@
+ 	pmu_a57 {
+ 		compatible = "arm,cortex-a57-pmu";
+ 		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+-		                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ 				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ 				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-affinity = <&a57_0>,
+-- 
+2.19.0
+
diff --git a/patches/1535-arm64-dts-renesas-r8a7796-Correct-whitespace.patch b/patches/1535-arm64-dts-renesas-r8a7796-Correct-whitespace.patch
new file mode 100644
index 00000000000000..a118fb154a1fa2
--- /dev/null
+++ b/patches/1535-arm64-dts-renesas-r8a7796-Correct-whitespace.patch
@@ -0,0 +1,59 @@
+From b94ce2b9a62ddb97c1a81817edd40fc60d4eb03c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:38:29 +0200
+Subject: [PATCH 1535/1795] arm64: dts: renesas: r8a7796: Correct whitespace
+
+Add missing spaces after commas.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e4d9242a30dce2ec01e8a321237c4b8d08c12c7b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 3fbd86590fb0..6ffab2da07cb 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -143,7 +143,7 @@
+ 		};
+ 
+ 		a57_1: cpu@1 {
+-			compatible = "arm,cortex-a57","arm,armv8";
++			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x1>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
+@@ -166,7 +166,7 @@
+ 		};
+ 
+ 		a53_1: cpu@101 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x101>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
+@@ -177,7 +177,7 @@
+ 		};
+ 
+ 		a53_2: cpu@102 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x102>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
+@@ -188,7 +188,7 @@
+ 		};
+ 
+ 		a53_3: cpu@103 {
+-			compatible = "arm,cortex-a53","arm,armv8";
++			compatible = "arm,cortex-a53", "arm,armv8";
+ 			reg = <0x103>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
+-- 
+2.19.0
+
diff --git a/patches/1536-arm64-dts-renesas-r8a77965-Correct-whitespace.patch b/patches/1536-arm64-dts-renesas-r8a77965-Correct-whitespace.patch
new file mode 100644
index 00000000000000..72488abb691848
--- /dev/null
+++ b/patches/1536-arm64-dts-renesas-r8a77965-Correct-whitespace.patch
@@ -0,0 +1,32 @@
+From ec6d3d66c143422377122a6a67aa1982ef0f758c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:38:30 +0200
+Subject: [PATCH 1536/1795] arm64: dts: renesas: r8a77965: Correct whitespace
+
+Add missing space after comma.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 80f7297c08079055d9c651f5827e26aa73bd1403)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index b93281affd63..ba0edda431a5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -67,7 +67,7 @@
+ 		};
+ 
+ 		a57_1: cpu@1 {
+-			compatible = "arm,cortex-a57","arm,armv8";
++			compatible = "arm,cortex-a57", "arm,armv8";
+ 			reg = <0x1>;
+ 			device_type = "cpu";
+ 			power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
+-- 
+2.19.0
+
diff --git a/patches/1537-arm64-dts-renesas-ulcb-Add-BD9571-PMIC.patch b/patches/1537-arm64-dts-renesas-ulcb-Add-BD9571-PMIC.patch
new file mode 100644
index 00000000000000..dee7e59d4dea39
--- /dev/null
+++ b/patches/1537-arm64-dts-renesas-ulcb-Add-BD9571-PMIC.patch
@@ -0,0 +1,70 @@
+From 90d1405196b26436444e687aab189c8a97025d62 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:30:49 +0200
+Subject: [PATCH 1537/1795] arm64: dts: renesas: ulcb: Add BD9571 PMIC
+
+Add a device node for the ROHM BD9571MWV PMIC.
+
+This was based on the example in the DT binding documentation, but using
+IRQ0 instead of a GPIO interrupt, as that matches the schematics, and
+because INTC-EX is a simpler block.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 786f3cc022f73973eda247a0f80f73971ebda764)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 29 +++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index 93402783d52f..ee4249287fbd 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -243,6 +243,30 @@
+ 
+ &i2c_dvfs {
+ 	status = "okay";
++
++	pmic: pmic@30 {
++		pinctrl-0 = <&irq0_pins>;
++		pinctrl-names = "default";
++
++		compatible = "rohm,bd9571mwv";
++		reg = <0x30>;
++		interrupt-parent = <&intc_ex>;
++		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		regulators {
++			dvfs: dvfs {
++				regulator-name = "dvfs";
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1030000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++		};
++	};
+ };
+ 
+ &ohci1 {
+@@ -276,6 +300,11 @@
+ 		function = "i2c2";
+ 	};
+ 
++	irq0_pins: irq0 {
++		groups = "intc_ex_irq0";
++		function = "intc_ex";
++	};
++
+ 	scif2_pins: scif2 {
+ 		groups = "scif2_data_a";
+ 		function = "scif2";
+-- 
+2.19.0
+
diff --git a/patches/1538-arm64-dts-renesas-salvator-common-Add-PMIC-DDR-Backu.patch b/patches/1538-arm64-dts-renesas-salvator-common-Add-PMIC-DDR-Backu.patch
new file mode 100644
index 00000000000000..ca58aa19de4f9a
--- /dev/null
+++ b/patches/1538-arm64-dts-renesas-salvator-common-Add-PMIC-DDR-Backu.patch
@@ -0,0 +1,38 @@
+From 1bb3a1702702bceb286032359f13bbea3323a0b7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:30:50 +0200
+Subject: [PATCH 1538/1795] arm64: dts: renesas: salvator-common: Add PMIC DDR
+ Backup Power config
+
+On Salvator-X(S), all of the DDR0, DDR1, DDR0C, and DDR1C power rails
+need to be kept powered when backup mode is enabled.  Reflect this in
+the "rohm,ddr-backup-power" property for the BD9571MWV PMIC node.
+
+The accessory power switch (SW23) is a toggle switch, hence specify
+"rohm,rstbmode-level".
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d666493fd6da3b13b9a0d4957ee1d0e52ece0e13)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 803220a02f50..96b51e572666 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -374,6 +374,8 @@
+ 		#interrupt-cells = <2>;
+ 		gpio-controller;
+ 		#gpio-cells = <2>;
++		rohm,ddr-backup-power = <0xf>;
++		rohm,rstbmode-level;
+ 
+ 		regulators {
+ 			dvfs: dvfs {
+-- 
+2.19.0
+
diff --git a/patches/1539-arm64-dts-renesas-ulcb-Add-PMIC-DDR-Backup-Power-con.patch b/patches/1539-arm64-dts-renesas-ulcb-Add-PMIC-DDR-Backup-Power-con.patch
new file mode 100644
index 00000000000000..4d9702a0478126
--- /dev/null
+++ b/patches/1539-arm64-dts-renesas-ulcb-Add-PMIC-DDR-Backup-Power-con.patch
@@ -0,0 +1,39 @@
+From 65948fcf9c64a93f6bc9eb8b3da8889ab2f18ff9 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 3 May 2018 14:30:51 +0200
+Subject: [PATCH 1539/1795] arm64: dts: renesas: ulcb: Add PMIC DDR Backup
+ Power config
+
+On the R-Car Starter Kit Premier/Pro, all of the DDR0, DDR1, DDR0C, and
+DDR1C power rails need to be kept powered when backup mode is enabled.
+Reflect this in the "rohm,ddr-backup-power" property for the BD9571MWV
+PMIC node.
+
+The accessory power switch (SW8) is a momentary switch, hense specify
+"rohm,rstbmode-pulse".
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 1c81a633de0e271d1f6f75f7f3e8a515d4a3085e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+index ee4249287fbd..0edb16e6b372 100644
+--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
++++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
+@@ -256,6 +256,8 @@
+ 		#interrupt-cells = <2>;
+ 		gpio-controller;
+ 		#gpio-cells = <2>;
++		rohm,ddr-backup-power = <0xf>;
++		rohm,rstbmode-pulse;
+ 
+ 		regulators {
+ 			dvfs: dvfs {
+-- 
+2.19.0
+
diff --git a/patches/1540-arm64-dts-renesas-r8a77965-Add-SDHI-device-nodes.patch b/patches/1540-arm64-dts-renesas-r8a77965-Add-SDHI-device-nodes.patch
new file mode 100644
index 00000000000000..fa61cc7e219160
--- /dev/null
+++ b/patches/1540-arm64-dts-renesas-r8a77965-Add-SDHI-device-nodes.patch
@@ -0,0 +1,85 @@
+From d98d0defd65754bb894dc2b0ff7ff57faeefd1e2 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Wed, 9 May 2018 21:38:24 +0900
+Subject: [PATCH 1540/1795] arm64: dts: renesas: r8a77965: Add SDHI device
+ nodes
+
+Add SDHI nodes to the DT of the r8a77965 SoC.
+
+Based on several similar patches of the R8A7796 device tree
+by Simon Horman <horms+renesas@verge.net.au>.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit aa7a6365d03aacd4714ae62630f0262cac82a478)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 36 ++++++++++++++++++++---
+ 1 file changed, 32 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index ba0edda431a5..f51c1b2cbae4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -978,23 +978,51 @@
+ 		};
+ 
+ 		sdhi0: sd@ee100000 {
++			compatible = "renesas,sdhi-r8a77965",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee100000 0 0x2000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 314>;
++			status = "disabled";
+ 		};
+ 
+ 		sdhi1: sd@ee120000 {
++			compatible = "renesas,sdhi-r8a77965",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee120000 0 0x2000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 313>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 313>;
++			status = "disabled";
+ 		};
+ 
+ 		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a77965",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee140000 0 0x2000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 312>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 312>;
++			status = "disabled";
+ 		};
+ 
+ 		sdhi3: sd@ee160000 {
++			compatible = "renesas,sdhi-r8a77965",
++				     "renesas,rcar-gen3-sdhi";
+ 			reg = <0 0xee160000 0 0x2000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 311>;
++			max-frequency = <200000000>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 311>;
++			status = "disabled";
+ 		};
+ 
+ 		gic: interrupt-controller@f1010000 {
+-- 
+2.19.0
+
diff --git a/patches/1541-arm64-dts-renesas-r8a77970-Add-secondary-CA53-CPU-co.patch b/patches/1541-arm64-dts-renesas-r8a77970-Add-secondary-CA53-CPU-co.patch
new file mode 100644
index 00000000000000..aeee05e72da6ff
--- /dev/null
+++ b/patches/1541-arm64-dts-renesas-r8a77970-Add-secondary-CA53-CPU-co.patch
@@ -0,0 +1,66 @@
+From d228a84202226e7e15dd76eb4eb1885bdf93fa7a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 9 May 2018 17:23:22 +0200
+Subject: [PATCH 1541/1795] arm64: dts: renesas: r8a77970: Add secondary CA53
+ CPU core
+
+Add a device node for the second Cortex-A53 CPU core on the Renesas
+R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
+ARM Generic Interrupt Controller and Architectured Timer.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 77899dd2c094fc99413e18264384cc428c23cd23)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 +++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 37b843c0677a..1efaad71804d 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -41,6 +41,16 @@
+ 			enable-method = "psci";
+ 		};
+ 
++		a53_1: cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53", "arm,armv8";
++			reg = <1>;
++			clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
++			power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++		};
++
+ 		L2_CA53: cache-controller {
+ 			compatible = "cache";
+ 			power-domains = <&sysc R8A77970_PD_CA53_SCU>;
+@@ -635,7 +645,7 @@
+ 			      <0 0xf1020000 0 0x20000>,
+ 			      <0 0xf1040000 0 0x20000>,
+ 			      <0 0xf1060000 0 0x20000>;
+-			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
++			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(2) |
+ 				      IRQ_TYPE_LEVEL_HIGH)>;
+ 			clocks = <&cpg CPG_MOD 408>;
+ 			clock-names = "clk";
+@@ -726,9 +736,9 @@
+ 
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
++		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1542-arm64-dts-renesas-r8a77970-Add-Cortex-A53-PMU-node.patch b/patches/1542-arm64-dts-renesas-r8a77970-Add-Cortex-A53-PMU-node.patch
new file mode 100644
index 00000000000000..8dae51a48262ae
--- /dev/null
+++ b/patches/1542-arm64-dts-renesas-r8a77970-Add-Cortex-A53-PMU-node.patch
@@ -0,0 +1,39 @@
+From 1b375735d66039808f50bfabb5bc1ebc21141376 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 9 May 2018 17:23:23 +0200
+Subject: [PATCH 1542/1795] arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU
+ node
+
+Enable the performance monitor unit for the Cortex-A53 cores on the
+R-Car V3M (r8a77970) SoC.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit d005b562be9c3379151f40b70a774ba61ed8bb0e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 1efaad71804d..50046405d348 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -73,6 +73,13 @@
+ 		clock-frequency = <0>;
+ 	};
+ 
++	pmu_a53 {
++		compatible = "arm,cortex-a53-pmu";
++		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
++				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&a53_0>, <&a53_1>;
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+-- 
+2.19.0
+
diff --git a/patches/1543-arm64-dts-renesas-r8a77980-add-resets-property-to-CA.patch b/patches/1543-arm64-dts-renesas-r8a77980-add-resets-property-to-CA.patch
new file mode 100644
index 00000000000000..8f56a49cc8a013
--- /dev/null
+++ b/patches/1543-arm64-dts-renesas-r8a77980-add-resets-property-to-CA.patch
@@ -0,0 +1,34 @@
+From e31d395ba41be4498fdd9688b5b8db1420189b32 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Wed, 9 May 2018 19:54:09 +0200
+Subject: [PATCH 1543/1795] arm64: dts: renesas: r8a77980: add resets property
+ to CAN-FD node
+
+Add resets property to CAN-FD node to describe it in the reset topology of
+on-SoC devices.  This allows to reset the CAN-FD device using the Reset
+Controller API.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 22fb06cd54f92132bf7a8b7740abc7db79a5130b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 3a127643d1dc..32db26f2c8b5 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -190,6 +190,7 @@
+ 			assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
+ 			assigned-clock-rates = <40000000>;
+ 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++			resets = <&cpg 914>;
+ 			status = "disabled";
+ 
+ 			channel0 {
+-- 
+2.19.0
+
diff --git a/patches/1544-arm64-dts-renesas-r8a77995-Add-VIN4.patch b/patches/1544-arm64-dts-renesas-r8a77995-Add-VIN4.patch
new file mode 100644
index 00000000000000..2d04aa51a33189
--- /dev/null
+++ b/patches/1544-arm64-dts-renesas-r8a77995-Add-VIN4.patch
@@ -0,0 +1,48 @@
+From 644d2e5879d3939549a928343f2f3ee1f2663217 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 11 May 2018 12:00:01 +0200
+Subject: [PATCH 1544/1795] arm64: dts: renesas: r8a77995: Add VIN4
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Describe VIN4 interface for R-Car D3 R8A77995 SoC.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+[simon: sorted node by bus address]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+(cherry picked from commit d86bd47fefbb6e4db53d733fe95bc13bc9ddedb1)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+index ba98865b0c9b..2506f46293e8 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+@@ -610,6 +610,17 @@
+ 			status = "disabled";
+ 		};
+ 
++		vin4: video@e6ef4000 {
++			compatible = "renesas,vin-r8a77995";
++			reg = <0 0xe6ef4000 0 0x1000>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 807>;
++			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
++			resets = <&cpg 807>;
++			renesas,id = <4>;
++			status = "disabled";
++		};
++
+ 		ohci0: usb@ee080000 {
+ 			compatible = "generic-ohci";
+ 			reg = <0 0xee080000 0 0x100>;
+-- 
+2.19.0
+
diff --git a/patches/1545-arm64-dts-renesas-r8a77970-disable-EtherAVB.patch b/patches/1545-arm64-dts-renesas-r8a77970-disable-EtherAVB.patch
new file mode 100644
index 00000000000000..e13d16953d2297
--- /dev/null
+++ b/patches/1545-arm64-dts-renesas-r8a77970-disable-EtherAVB.patch
@@ -0,0 +1,37 @@
+From 65d88991df029b2dc8e4e10d8ed6faaa14040e4e Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 11 May 2018 23:21:57 +0300
+Subject: [PATCH 1545/1795] arm64: dts: renesas: r8a77970: disable EtherAVB
+
+When adding the R8A77970 EtherAVB device I failed to notice that it does
+not have the usual "status" property disabling the described devices in
+anticipation that the board device trees enable the devices according to
+their needs. This causes the EtherAVB driver to successfully probe despite
+e.g. the needed pins not having been configured -- luckily, "eth<n>" device
+can't be opened anyway...
+
+Fixes: bea2ab136eaa ("arm64: dts: renesas: r8a77970: add EtherAVB support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 9223eef03f2659bd9650c2bc4364b1748e62eade)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index 50046405d348..c8464d1ef1b2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -473,6 +473,7 @@
+ 			iommus = <&ipmmu_rt 3>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		scif0: serial@e6e60000 {
+-- 
+2.19.0
+
diff --git a/patches/1546-arm64-dts-renesas-r8a77980-disable-EtherAVB.patch b/patches/1546-arm64-dts-renesas-r8a77980-disable-EtherAVB.patch
new file mode 100644
index 00000000000000..58cc6e71eba3a8
--- /dev/null
+++ b/patches/1546-arm64-dts-renesas-r8a77980-disable-EtherAVB.patch
@@ -0,0 +1,37 @@
+From 6978b1a9f7943f4757dccba3150a615c01f12e6d Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 11 May 2018 23:23:26 +0300
+Subject: [PATCH 1546/1795] arm64: dts: renesas: r8a77980: disable EtherAVB
+
+When adding the R8A77980 EtherAVB device I failed to notice that it does
+not have the usual "status" property disabling the described devices in
+anticipation that the board device trees enable the devices according to
+their needs. This causes the EtherAVB driver to successfully probe despite
+e.g. the needed pins not having been configured -- luckily, "eth<n>" device
+can't be opened anyway...
+
+Fixes: bf6f90832f81 ("arm64: dts: renesas: r8a77980: add EtherAVB support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 52d2e0cec73e61123860230d6d034cd07775dd78)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 32db26f2c8b5..4c40f9f0ebc9 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -244,6 +244,7 @@
+ 			phy-mode = "rgmii";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			status = "disabled";
+ 		};
+ 
+ 		scif0: serial@e6e60000 {
+-- 
+2.19.0
+
diff --git a/patches/1547-arm64-dts-renesas-initial-V3HSK-board-device-tree.patch b/patches/1547-arm64-dts-renesas-initial-V3HSK-board-device-tree.patch
new file mode 100644
index 00000000000000..c5e0e43e4aebea
--- /dev/null
+++ b/patches/1547-arm64-dts-renesas-initial-V3HSK-board-device-tree.patch
@@ -0,0 +1,106 @@
+From 18fd924490b4103dc9b3036e4a12370dedad098b Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 10 May 2018 21:12:30 +0300
+Subject: [PATCH 1547/1795] arm64: dts: renesas: initial V3HSK board device
+ tree
+
+Add the initial device  tree for  the V3H Starter Kit board.
+The board has 1 debug serial port (SCIF0); include support for it,
+so that the serial console can work.
+
+Based on the original (and large) patch by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 116a12f7d6c00e1e477aaec9e486cd510fa1895c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/Makefile          |  2 +-
+ .../arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 60 +++++++++++++++++++
+ 2 files changed, 61 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index 12b65594451d..f24fde5566a1 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -9,7 +9,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+-dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
++dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
+ dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
+ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+ 
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+new file mode 100644
+index 000000000000..c9680994555d
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+@@ -0,0 +1,60 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree Source for the V3H Starter Kit board
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ */
++
++/dts-v1/;
++#include "r8a77980.dtsi"
++
++/ {
++	model = "Renesas V3H Starter Kit board";
++	compatible = "renesas,v3hsk", "renesas,r8a77980";
++
++	aliases {
++		serial0 = &scif0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0 0x48000000 0 0x78000000>;
++	};
++};
++
++&extal_clk {
++	clock-frequency = <16666666>;
++};
++
++&extalr_clk {
++	clock-frequency = <32768>;
++};
++
++&pfc {
++	scif0_pins: scif0 {
++		groups = "scif0_data";
++		function = "scif0";
++	};
++
++	scif_clk_pins: scif_clk {
++		groups = "scif_clk_b";
++		function = "scif_clk";
++	};
++};
++
++&scif0 {
++	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&scif_clk {
++	clock-frequency = <14745600>;
++};
+-- 
+2.19.0
+
diff --git a/patches/1548-arm64-dts-renesas-r8a77990-Add-PFC-device-node.patch b/patches/1548-arm64-dts-renesas-r8a77990-Add-PFC-device-node.patch
new file mode 100644
index 00000000000000..1279ebd74eb3c1
--- /dev/null
+++ b/patches/1548-arm64-dts-renesas-r8a77990-Add-PFC-device-node.patch
@@ -0,0 +1,36 @@
+From 8a277c2381944819cb1226dee69b87a90c7ebdaf Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 13:31:18 +0900
+Subject: [PATCH 1548/1795] arm64: dts: renesas: r8a77990: Add PFC device node
+
+This patch adds PFC device node for r8a77990 (R-Car E3).
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 4ab0df3399699c3d440940863234d318fa649b72)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+index 46580290b7fb..efc3c0ba36c2 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -60,6 +60,11 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		pfc: pin-controller@e6060000 {
++			compatible = "renesas,pfc-r8a77990";
++			reg = <0 0xe6060000 0 0x508>;
++		};
++
+ 		cpg: clock-controller@e6150000 {
+ 			compatible = "renesas,r8a77990-cpg-mssr";
+ 			reg = <0 0xe6150000 0 0x1000>;
+-- 
+2.19.0
+
diff --git a/patches/1549-arm64-dts-renesas-r8a77990-Add-GPIO-device-nodes.patch b/patches/1549-arm64-dts-renesas-r8a77990-Add-GPIO-device-nodes.patch
new file mode 100644
index 00000000000000..792abed2dad7ab
--- /dev/null
+++ b/patches/1549-arm64-dts-renesas-r8a77990-Add-GPIO-device-nodes.patch
@@ -0,0 +1,140 @@
+From 726e702efec3e533d5505b10d721a14be78deab7 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 13:31:19 +0900
+Subject: [PATCH 1549/1795] arm64: dts: renesas: r8a77990: Add GPIO device
+ nodes
+
+This patch adds GPIO nodes for r8a77990 (R-Car E3).
+
+Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+[simon: dropped use of deprecated "renesas,gpio-rcar"]
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+
+(cherry picked from commit 0d292de1ebe0cfc599d7eeccdff4aa0d77a03f55)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 105 ++++++++++++++++++++++
+ 1 file changed, 105 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+index efc3c0ba36c2..bbc3db50bc01 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -60,6 +60,111 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 18>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 912>;
++		};
++
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 23>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 911>;
++		};
++
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 26>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 910>;
++		};
++
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 16>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 909>;
++		};
++
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 11>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 908>;
++		};
++
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 20>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 907>;
++		};
++
++		gpio6: gpio@e6055400 {
++			compatible = "renesas,gpio-r8a77990",
++				     "renesas,rcar-gen3-gpio";
++			reg = <0 0xe6055400 0 0x50>;
++			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 192 18>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 906>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 906>;
++		};
++
+ 		pfc: pin-controller@e6060000 {
+ 			compatible = "renesas,pfc-r8a77990";
+ 			reg = <0 0xe6060000 0 0x508>;
+-- 
+2.19.0
+
diff --git a/patches/1550-arm64-dts-renesas-r8a77990-Add-EthernetAVB-device-no.patch b/patches/1550-arm64-dts-renesas-r8a77990-Add-EthernetAVB-device-no.patch
new file mode 100644
index 00000000000000..2b9bbca1cd4d83
--- /dev/null
+++ b/patches/1550-arm64-dts-renesas-r8a77990-Add-EthernetAVB-device-no.patch
@@ -0,0 +1,78 @@
+From 928998dd694fc537c4ff85295e28c9893518f446 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 13:31:20 +0900
+Subject: [PATCH 1550/1795] arm64: dts: renesas: r8a77990: Add EthernetAVB
+ device nodes
+
+This patch adds EthernetAVB node for r8a77990 (R-Car E3).
+
+Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 913a78b575c313b8bee8384a542e637049232e40)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 +++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+index bbc3db50bc01..be4f519711a1 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+@@ -191,6 +191,51 @@
+ 			#power-domain-cells = <1>;
+ 		};
+ 
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a77990",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;
++			power-domains = <&sysc 32>;
++			resets = <&cpg 812>;
++			phy-mode = "rgmii";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		scif2: serial@e6e88000 {
+ 			compatible = "renesas,scif-r8a77990",
+ 				     "renesas,rcar-gen3-scif", "renesas,scif";
+-- 
+2.19.0
+
diff --git a/patches/1551-arm64-dts-renesas-r8a77990-ebisu-Enable-EthernetAVB.patch b/patches/1551-arm64-dts-renesas-r8a77990-ebisu-Enable-EthernetAVB.patch
new file mode 100644
index 00000000000000..cea7bfbb4c0857
--- /dev/null
+++ b/patches/1551-arm64-dts-renesas-r8a77990-ebisu-Enable-EthernetAVB.patch
@@ -0,0 +1,79 @@
+From 96e46707443ba90088553cab8697c42ba701b021 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 13:31:21 +0900
+Subject: [PATCH 1551/1795] arm64: dts: renesas: r8a77990: ebisu: Enable
+ EthernetAVB
+
+This patch enables EthernetAVB for r8a77990 Ebisu board.
+
+Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 8441ef643d7dc8b4df85cbd7d8b99efc08ec00f3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+index 63ee1347bb19..7a09d0524f9b 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
++++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+@@ -7,6 +7,7 @@
+ 
+ /dts-v1/;
+ #include "r8a77990.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	model = "Renesas Ebisu board based on r8a77990";
+@@ -14,6 +15,7 @@
+ 
+ 	aliases {
+ 		serial0 = &scif2;
++		ethernet0 = &avb;
+ 	};
+ 
+ 	chosen {
+@@ -28,10 +30,36 @@
+ 	};
+ };
+ 
++&avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	phy-mode = "rgmii-txid";
++	status = "okay";
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		reg = <0>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
++	};
++};
++
+ &extal_clk {
+ 	clock-frequency = <48000000>;
+ };
+ 
++&pfc {
++	avb_pins: avb {
++		mux {
++			groups = "avb_link", "avb_mii";
++			function = "avb";
++		};
++	};
++};
++
+ &scif2 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/1552-arm64-dts-renesas-r8a77965-add-I2C-support.patch b/patches/1552-arm64-dts-renesas-r8a77965-add-I2C-support.patch
new file mode 100644
index 00000000000000..99cca675e502bd
--- /dev/null
+++ b/patches/1552-arm64-dts-renesas-r8a77965-add-I2C-support.patch
@@ -0,0 +1,167 @@
+From 9b3b0770569f2d5e54ceca6ee1919d94ec5867da Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Fri, 11 May 2018 16:00:29 +0200
+Subject: [PATCH 1552/1795] arm64: dts: renesas: r8a77965: add I2C support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 111d3ffe1692af078609516b407e494ac985684b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 99 ++++++++++++++++++++---
+ 1 file changed, 90 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index f51c1b2cbae4..1f67aea49305 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -20,6 +20,13 @@
+ 	#size-cells = <2>;
+ 
+ 	aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		i2c5 = &i2c5;
++		i2c6 = &i2c6;
+ 		i2c7 = &i2c_dvfs;
+ 	};
+ 
+@@ -314,44 +321,118 @@
+ 		};
+ 
+ 		i2c0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe6500000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 931>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
++			       <&dmac2 0x91>, <&dmac2 0x90>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c1: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe6508000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 930>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
++			       <&dmac2 0x93>, <&dmac2 0x92>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c2: i2c@e6510000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe6510000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 929>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
++			       <&dmac2 0x95>, <&dmac2 0x94>;
++			dma-names = "tx", "rx", "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c3: i2c@e66d0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe66d0000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 928>;
++			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c4: i2c@e66d8000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe66d8000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 927>;
++			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c5: i2c@e66e0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe66e0000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 919>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 919>;
++			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <110>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c6: i2c@e66e8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a77965",
++				     "renesas,rcar-gen3-i2c";
+ 			reg = <0 0xe66e8000 0 0x40>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 918>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 918>;
++			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
+ 		};
+ 
+ 		i2c_dvfs: i2c@e60b0000 {
+-- 
+2.19.0
+
diff --git a/patches/1553-arm64-dts-renesas-r8a7795-add-VIN-and-CSI-2-nodes.patch b/patches/1553-arm64-dts-renesas-r8a7795-add-VIN-and-CSI-2-nodes.patch
new file mode 100644
index 00000000000000..0582a619d603e9
--- /dev/null
+++ b/patches/1553-arm64-dts-renesas-r8a7795-add-VIN-and-CSI-2-nodes.patch
@@ -0,0 +1,429 @@
+From 6b9c6a07aaae1a90ef910284ff2af3ada4d45c33 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:48 +0200
+Subject: [PATCH 1553/1795] arm64: dts: renesas: r8a7795: add VIN and CSI-2
+ nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 15da7132f1da1c0c42c175a0b938af1e0615de90)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 389 +++++++++++++++++++++++
+ 1 file changed, 389 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+index 91486b4910ce..d842940b2f43 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+@@ -1397,6 +1397,262 @@
+ 			status = "disabled";
+ 		};
+ 
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			renesas,id = <0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin0csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin0>;
++					};
++					vin0csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin0>;
++					};
++				};
++			};
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			renesas,id = <1>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin1csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin1>;
++					};
++					vin1csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin1>;
++					};
++				};
++			};
++		};
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			renesas,id = <2>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin2csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin2>;
++					};
++					vin2csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin2>;
++					};
++				};
++			};
++		};
++
++		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef3000 0 0x1000>;
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
++			renesas,id = <3>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin3csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin3>;
++					};
++					vin3csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin3>;
++					};
++				};
++			};
++		};
++
++		vin4: video@e6ef4000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef4000 0 0x1000>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 807>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 807>;
++			renesas,id = <4>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin4csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin4>;
++					};
++					vin4csi41: endpoint@3 {
++						reg = <3>;
++						remote-endpoint= <&csi41vin4>;
++					};
++				};
++			};
++		};
++
++		vin5: video@e6ef5000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef5000 0 0x1000>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 806>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 806>;
++			renesas,id = <5>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin5csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin5>;
++					};
++					vin5csi41: endpoint@3 {
++						reg = <3>;
++						remote-endpoint= <&csi41vin5>;
++					};
++				};
++			};
++		};
++
++		vin6: video@e6ef6000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef6000 0 0x1000>;
++			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 805>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 805>;
++			renesas,id = <6>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin6csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin6>;
++					};
++					vin6csi41: endpoint@3 {
++						reg = <3>;
++						remote-endpoint= <&csi41vin6>;
++					};
++				};
++			};
++		};
++
++		vin7: video@e6ef7000 {
++			compatible = "renesas,vin-r8a7795";
++			reg = <0 0xe6ef7000 0 0x1000>;
++			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 804>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 804>;
++			renesas,id = <7>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin7csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin7>;
++					};
++					vin7csi41: endpoint@3 {
++						reg = <3>;
++						remote-endpoint= <&csi41vin7>;
++					};
++				};
++			};
++		};
++
+ 		drif00: rif@e6f40000 {
+ 			compatible = "renesas,r8a7795-drif",
+ 				     "renesas,rcar-gen3-drif";
+@@ -2327,6 +2583,139 @@
+ 			renesas,fcp = <&fcpvi1>;
+ 		};
+ 
++		csi20: csi2@fea80000 {
++			compatible = "renesas,r8a7795-csi2";
++			reg = <0 0xfea80000 0 0x10000>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi20vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi20>;
++					};
++					csi20vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi20>;
++					};
++					csi20vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi20>;
++					};
++					csi20vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi20>;
++					};
++					csi20vin4: endpoint@4 {
++						reg = <4>;
++						remote-endpoint = <&vin4csi20>;
++					};
++					csi20vin5: endpoint@5 {
++						reg = <5>;
++						remote-endpoint = <&vin5csi20>;
++					};
++					csi20vin6: endpoint@6 {
++						reg = <6>;
++						remote-endpoint = <&vin6csi20>;
++					};
++					csi20vin7: endpoint@7 {
++						reg = <7>;
++						remote-endpoint = <&vin7csi20>;
++					};
++				};
++			};
++		};
++
++		csi40: csi2@feaa0000 {
++			compatible = "renesas,r8a7795-csi2";
++			reg = <0 0xfeaa0000 0 0x10000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi40vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi40>;
++					};
++					csi40vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi40>;
++					};
++					csi40vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi40>;
++					};
++					csi40vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi40>;
++					};
++				};
++			};
++		};
++
++		csi41: csi2@feab0000 {
++			compatible = "renesas,r8a7795-csi2";
++			reg = <0 0xfeab0000 0 0x10000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>;
++			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++			resets = <&cpg 715>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi41vin4: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin4csi41>;
++					};
++					csi41vin5: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin5csi41>;
++					};
++					csi41vin6: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin6csi41>;
++					};
++					csi41vin7: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin7csi41>;
++					};
++				};
++			};
++		};
++
+ 		hdmi0: hdmi@fead0000 {
+ 			compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ 			reg = <0 0xfead0000 0 0x10000>;
+-- 
+2.19.0
+
diff --git a/patches/1554-arm64-dts-renesas-r8a7795-es1-add-CSI-2-node.patch b/patches/1554-arm64-dts-renesas-r8a7795-es1-add-CSI-2-node.patch
new file mode 100644
index 00000000000000..bc05675ce5e13b
--- /dev/null
+++ b/patches/1554-arm64-dts-renesas-r8a7795-es1-add-CSI-2-node.patch
@@ -0,0 +1,182 @@
+From 76ecdda6855d0f1e5c124986f422aaf6f050dd39 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:49 +0200
+Subject: [PATCH 1554/1795] arm64: dts: renesas: r8a7795-es1: add CSI-2 node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Renesas H3 ES1.0 have one extra CSI-2 node, CSI21 which is not present
+for later ES versions of H3.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit e51c09d53719c0d348f07af7deb14463ec1aeec7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 143 +++++++++++++++++++
+ 1 file changed, 143 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+index 0177f5e60e5a..e19dcd6cb767 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+@@ -107,6 +107,61 @@
+ 		resets = <&cpg 117>;
+ 		renesas,fcp = <&fcpf2>;
+ 	};
++
++	csi21: csi2@fea90000 {
++		compatible = "renesas,r8a7795-csi2";
++		reg = <0 0xfea90000 0 0x10000>;
++		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cpg CPG_MOD 713>;
++		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
++		resets = <&cpg 713>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@1 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				reg = <1>;
++
++				csi21vin0: endpoint@0 {
++					reg = <0>;
++					remote-endpoint = <&vin0csi21>;
++				};
++				csi21vin1: endpoint@1 {
++					reg = <1>;
++					remote-endpoint = <&vin1csi21>;
++				};
++				csi21vin2: endpoint@2 {
++					reg = <2>;
++					remote-endpoint = <&vin2csi21>;
++				};
++				csi21vin3: endpoint@3 {
++					reg = <3>;
++					remote-endpoint = <&vin3csi21>;
++				};
++				csi21vin4: endpoint@4 {
++					reg = <4>;
++					remote-endpoint = <&vin4csi21>;
++				};
++				csi21vin5: endpoint@5 {
++					reg = <5>;
++					remote-endpoint = <&vin5csi21>;
++				};
++				csi21vin6: endpoint@6 {
++					reg = <6>;
++					remote-endpoint = <&vin6csi21>;
++				};
++				csi21vin7: endpoint@7 {
++					reg = <7>;
++					remote-endpoint = <&vin7csi21>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &gpio1 {
+@@ -174,3 +229,91 @@
+ &du {
+ 	vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+ };
++
++&vin0 {
++	ports {
++		port@1 {
++			vin0csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin0>;
++			};
++		};
++	};
++};
++
++&vin1 {
++	ports {
++		port@1 {
++			vin1csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin1>;
++			};
++		};
++	};
++};
++
++&vin2 {
++	ports {
++		port@1 {
++			vin2csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin2>;
++			};
++		};
++	};
++};
++
++&vin3 {
++	ports {
++		port@1 {
++			vin3csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin3>;
++			};
++		};
++	};
++};
++
++&vin4 {
++	ports {
++		port@1 {
++			vin4csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin4>;
++			};
++		};
++	};
++};
++
++&vin5 {
++	ports {
++		port@1 {
++			vin5csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin5>;
++			};
++		};
++	};
++};
++
++&vin6 {
++	ports {
++		port@1 {
++			vin6csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin6>;
++			};
++		};
++	};
++};
++
++&vin7 {
++	ports {
++		port@1 {
++			vin7csi21: endpoint@1 {
++				reg = <1>;
++				remote-endpoint= <&csi21vin7>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1555-arm64-dts-renesas-r8a7796-add-VIN-and-CSI-2-nodes.patch b/patches/1555-arm64-dts-renesas-r8a7796-add-VIN-and-CSI-2-nodes.patch
new file mode 100644
index 00000000000000..349cf898c80f56
--- /dev/null
+++ b/patches/1555-arm64-dts-renesas-r8a7796-add-VIN-and-CSI-2-nodes.patch
@@ -0,0 +1,407 @@
+From 61d8d9401de6442bc32814ada8c181b380ad4ce0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:50 +0200
+Subject: [PATCH 1555/1795] arm64: dts: renesas: r8a7796: add VIN and CSI-2
+ nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 0e5819f10bb1230088c9893aaad7e6884611b061)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 367 +++++++++++++++++++++++
+ 1 file changed, 367 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+index 6ffab2da07cb..7c25be6b5af3 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+@@ -1280,6 +1280,262 @@
+ 			status = "disabled";
+ 		};
+ 
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			renesas,id = <0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin0csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin0>;
++					};
++					vin0csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin0>;
++					};
++				};
++			};
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			renesas,id = <1>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin1csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin1>;
++					};
++					vin1csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin1>;
++					};
++				};
++			};
++		};
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			renesas,id = <2>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin2csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin2>;
++					};
++					vin2csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin2>;
++					};
++				};
++			};
++		};
++
++		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef3000 0 0x1000>;
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
++			renesas,id = <3>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin3csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin3>;
++					};
++					vin3csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin3>;
++					};
++				};
++			};
++		};
++
++		vin4: video@e6ef4000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef4000 0 0x1000>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 807>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 807>;
++			renesas,id = <4>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin4csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin4>;
++					};
++					vin4csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin4>;
++					};
++				};
++			};
++		};
++
++		vin5: video@e6ef5000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef5000 0 0x1000>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 806>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 806>;
++			renesas,id = <5>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin5csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin5>;
++					};
++					vin5csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin5>;
++					};
++				};
++			};
++		};
++
++		vin6: video@e6ef6000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef6000 0 0x1000>;
++			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 805>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 805>;
++			renesas,id = <6>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin6csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin6>;
++					};
++					vin6csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin6>;
++					};
++				};
++			};
++		};
++
++		vin7: video@e6ef7000 {
++			compatible = "renesas,vin-r8a7796";
++			reg = <0 0xe6ef7000 0 0x1000>;
++			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 804>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 804>;
++			renesas,id = <7>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin7csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin7>;
++					};
++					vin7csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin7>;
++					};
++				};
++			};
++		};
++
+ 		drif00: rif@e6f40000 {
+ 			compatible = "renesas,r8a7796-drif",
+ 				     "renesas,rcar-gen3-drif";
+@@ -1998,6 +2254,117 @@
+ 			renesas,fcp = <&fcpvi0>;
+ 		};
+ 
++		csi20: csi2@fea80000 {
++			compatible = "renesas,r8a7796-csi2";
++			reg = <0 0xfea80000 0 0x10000>;
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi20vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi20>;
++					};
++					csi20vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi20>;
++					};
++					csi20vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi20>;
++					};
++					csi20vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi20>;
++					};
++					csi20vin4: endpoint@4 {
++						reg = <4>;
++						remote-endpoint = <&vin4csi20>;
++					};
++					csi20vin5: endpoint@5 {
++						reg = <5>;
++						remote-endpoint = <&vin5csi20>;
++					};
++					csi20vin6: endpoint@6 {
++						reg = <6>;
++						remote-endpoint = <&vin6csi20>;
++					};
++					csi20vin7: endpoint@7 {
++						reg = <7>;
++						remote-endpoint = <&vin7csi20>;
++					};
++				};
++			};
++		};
++
++		csi40: csi2@feaa0000 {
++			compatible = "renesas,r8a7796-csi2";
++			reg = <0 0xfeaa0000 0 0x10000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>;
++			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi40vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi40>;
++					};
++					csi40vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi40>;
++					};
++					csi40vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi40>;
++					};
++					csi40vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi40>;
++					};
++					csi40vin4: endpoint@4 {
++						reg = <4>;
++						remote-endpoint = <&vin4csi40>;
++					};
++					csi40vin5: endpoint@5 {
++						reg = <5>;
++						remote-endpoint = <&vin5csi40>;
++					};
++					csi40vin6: endpoint@6 {
++						reg = <6>;
++						remote-endpoint = <&vin6csi40>;
++					};
++					csi40vin7: endpoint@7 {
++						reg = <7>;
++						remote-endpoint = <&vin7csi40>;
++					};
++				};
++
++			};
++		};
++
+ 		hdmi0: hdmi@fead0000 {
+ 			compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
+ 			reg = <0 0xfead0000 0 0x10000>;
+-- 
+2.19.0
+
diff --git a/patches/1556-arm64-dts-renesas-r8a77965-add-VIN-and-CSI-2-nodes.patch b/patches/1556-arm64-dts-renesas-r8a77965-add-VIN-and-CSI-2-nodes.patch
new file mode 100644
index 00000000000000..27104322154417
--- /dev/null
+++ b/patches/1556-arm64-dts-renesas-r8a77965-add-VIN-and-CSI-2-nodes.patch
@@ -0,0 +1,409 @@
+From bbedfe08793a4ce511ae2dde5e495a52f738aaad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:51 +0200
+Subject: [PATCH 1556/1795] arm64: dts: renesas: r8a77965: add VIN and CSI-2
+ nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 98b6badf77d5a877c918ae12b070caae8f1df968)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 326 +++++++++++++++++++++-
+ 1 file changed, 316 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+index 1f67aea49305..486aecacb22a 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+@@ -886,43 +886,259 @@
+ 		};
+ 
+ 		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef0000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			renesas,id = <0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin0csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin0>;
++					};
++					vin0csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin0>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef1000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			renesas,id = <1>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin1csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin1>;
++					};
++					vin1csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin1>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef2000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			renesas,id = <2>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin2csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin2>;
++					};
++					vin2csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin2>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef3000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
++			renesas,id = <3>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin3csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin3>;
++					};
++					vin3csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin3>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin4: video@e6ef4000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef4000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 807>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 807>;
++			renesas,id = <4>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin4csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin4>;
++					};
++					vin4csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin4>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin5: video@e6ef5000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef5000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 806>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 806>;
++			renesas,id = <5>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin5csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin5>;
++					};
++					vin5csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin5>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin6: video@e6ef6000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef6000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 805>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 805>;
++			renesas,id = <6>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin6csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin6>;
++					};
++					vin6csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin6>;
++					};
++				};
++			};
+ 		};
+ 
+ 		vin7: video@e6ef7000 {
++			compatible = "renesas,vin-r8a77965";
+ 			reg = <0 0xe6ef7000 0 0x1000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 804>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 804>;
++			renesas,id = <7>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin7csi20: endpoint@0 {
++						reg = <0>;
++						remote-endpoint= <&csi20vin7>;
++					};
++					vin7csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin7>;
++					};
++				};
++			};
+ 		};
+ 
+ 		rcar_sound: sound@ec500000 {
+@@ -1218,22 +1434,112 @@
+ 		};
+ 
+ 		csi20: csi2@fea80000 {
++			compatible = "renesas,r8a77965-csi2";
+ 			reg = <0 0xfea80000 0 0x10000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 714>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 714>;
++			status = "disabled";
+ 
+ 			ports {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi20vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi20>;
++					};
++					csi20vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi20>;
++					};
++					csi20vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi20>;
++					};
++					csi20vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi20>;
++					};
++					csi20vin4: endpoint@4 {
++						reg = <4>;
++						remote-endpoint = <&vin4csi20>;
++					};
++					csi20vin5: endpoint@5 {
++						reg = <5>;
++						remote-endpoint = <&vin5csi20>;
++					};
++					csi20vin6: endpoint@6 {
++						reg = <6>;
++						remote-endpoint = <&vin6csi20>;
++					};
++					csi20vin7: endpoint@7 {
++						reg = <7>;
++						remote-endpoint = <&vin7csi20>;
++					};
++				};
+ 			};
+ 		};
+ 
+ 		csi40: csi2@feaa0000 {
++			compatible = "renesas,r8a77965-csi2";
+ 			reg = <0 0xfeaa0000 0 0x10000>;
+-			/* placeholder */
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>;
++			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
+ 
+ 			ports {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi40vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi40>;
++					};
++					csi40vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi40>;
++					};
++					csi40vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi40>;
++					};
++					csi40vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi40>;
++					};
++					csi40vin4: endpoint@4 {
++						reg = <4>;
++						remote-endpoint = <&vin4csi40>;
++					};
++					csi40vin5: endpoint@5 {
++						reg = <5>;
++						remote-endpoint = <&vin5csi40>;
++					};
++					csi40vin6: endpoint@6 {
++						reg = <6>;
++						remote-endpoint = <&vin6csi40>;
++					};
++					csi40vin7: endpoint@7 {
++						reg = <7>;
++						remote-endpoint = <&vin7csi40>;
++					};
++				};
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1557-arm64-dts-renesas-r8a77970-add-VIN-and-CSI-2-nodes.patch b/patches/1557-arm64-dts-renesas-r8a77970-add-VIN-and-CSI-2-nodes.patch
new file mode 100644
index 00000000000000..766a8d0e1e7891
--- /dev/null
+++ b/patches/1557-arm64-dts-renesas-r8a77970-add-VIN-and-CSI-2-nodes.patch
@@ -0,0 +1,192 @@
+From 85f3e193c20fdc237a61d14e3b6e78165afaf370 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:52 +0200
+Subject: [PATCH 1557/1795] arm64: dts: renesas: r8a77970: add VIN and CSI-2
+ nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 51b09327863d7a97e5e284262daf44c9aa60827e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 152 ++++++++++++++++++++++
+ 1 file changed, 152 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index c8464d1ef1b2..98a2317a16c4 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -547,6 +547,119 @@
+ 			status = "disabled";
+ 		};
+ 
++
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a77970";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 811>;
++			renesas,id = <0>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin0csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin0>;
++					};
++				};
++			};
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a77970";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 810>;
++			renesas,id = <1>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin1csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin1>;
++					};
++				};
++			};
++		};
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a77970";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 809>;
++			renesas,id = <2>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin2csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin2>;
++					};
++				};
++			};
++		};
++
++		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a77970";
++			reg = <0 0xe6ef3000 0 0x1000>;
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 808>;
++			renesas,id = <3>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					vin3csi40: endpoint@2 {
++						reg = <2>;
++						remote-endpoint= <&csi40vin3>;
++					};
++				};
++			};
++		};
++
+ 		dmac1: dma-controller@e7300000 {
+ 			compatible = "renesas,dmac-r8a77970",
+ 				     "renesas,rcar-dmac";
+@@ -679,6 +792,45 @@
+ 			resets = <&cpg 603>;
+ 		};
+ 
++		csi40: csi2@feaa0000 {
++			compatible = "renesas,r8a77970-csi2";
++			reg = <0 0xfeaa0000 0 0x10000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>;
++			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++			resets = <&cpg 716>;
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					reg = <1>;
++
++					csi40vin0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&vin0csi40>;
++					};
++					csi40vin1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&vin1csi40>;
++					};
++					csi40vin2: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&vin2csi40>;
++					};
++					csi40vin3: endpoint@3 {
++						reg = <3>;
++						remote-endpoint = <&vin3csi40>;
++					};
++				};
++			};
++		};
++
+ 		du: display@feb00000 {
+ 			compatible = "renesas,du-r8a77970";
+ 			reg = <0 0xfeb00000 0 0x80000>;
+-- 
+2.19.0
+
diff --git a/patches/1558-arm64-dts-renesas-salvator-common-enable-VIN.patch b/patches/1558-arm64-dts-renesas-salvator-common-enable-VIN.patch
new file mode 100644
index 00000000000000..eb97e8558d50fd
--- /dev/null
+++ b/patches/1558-arm64-dts-renesas-salvator-common-enable-VIN.patch
@@ -0,0 +1,64 @@
+From aa5143b9d4c9fda45d34111a3df545b9cddccf50 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Wed, 16 May 2018 03:58:54 +0200
+Subject: [PATCH 1558/1795] arm64: dts: renesas: salvator-common: enable VIN
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit afa6dceca1fb55d6124825fb0f6c3d611b991aa3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/salvator-common.dtsi     | 32 +++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 96b51e572666..263e5787270e 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -703,6 +703,38 @@
+ 	clock-frequency = <100000000>;
+ };
+ 
++&vin0 {
++	status = "okay";
++};
++
++&vin1 {
++	status = "okay";
++};
++
++&vin2 {
++	status = "okay";
++};
++
++&vin3 {
++	status = "okay";
++};
++
++&vin4 {
++	status = "okay";
++};
++
++&vin5 {
++	status = "okay";
++};
++
++&vin6 {
++	status = "okay";
++};
++
++&vin7 {
++	status = "okay";
++};
++
+ &wdt0 {
+ 	timeout-sec = <60>;
+ 	status = "okay";
+-- 
+2.19.0
+
diff --git a/patches/1559-arm64-defconfig-enable-R8A77990-SoC.patch b/patches/1559-arm64-defconfig-enable-R8A77990-SoC.patch
new file mode 100644
index 00000000000000..2d635e8b4873c9
--- /dev/null
+++ b/patches/1559-arm64-defconfig-enable-R8A77990-SoC.patch
@@ -0,0 +1,31 @@
+From cc0ad4ec54cf4fa0ad1b405005e8a81f85eab480 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Mon, 23 Apr 2018 12:45:56 +0200
+Subject: [PATCH 1559/1795] arm64: defconfig: enable R8A77990 SoC
+
+Enable the Renesas R-Car E3 (R8A77990) SoC in the ARM64 defconfig.
+
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit c1fcd2ec1b1970e0e7b0c40c64bc51cf667b1a75)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index dd8f608074c3..badb02434344 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -53,6 +53,7 @@ CONFIG_ARCH_R8A7796=y
+ CONFIG_ARCH_R8A77965=y
+ CONFIG_ARCH_R8A77970=y
+ CONFIG_ARCH_R8A77980=y
++CONFIG_ARCH_R8A77990=y
+ CONFIG_ARCH_R8A77995=y
+ CONFIG_ARCH_STRATIX10=y
+ CONFIG_ARCH_TEGRA=y
+-- 
+2.19.0
+
diff --git a/patches/1560-arm64-dts-renesas-salvator-common-Add-ADV7482-suppor.patch b/patches/1560-arm64-dts-renesas-salvator-common-Add-ADV7482-suppor.patch
new file mode 100644
index 00000000000000..da84b5d82b7447
--- /dev/null
+++ b/patches/1560-arm64-dts-renesas-salvator-common-Add-ADV7482-suppor.patch
@@ -0,0 +1,156 @@
+From 3043f5c7040af46b5efc9908f6af48d908835ca9 Mon Sep 17 00:00:00 2001
+From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Date: Wed, 16 May 2018 03:58:53 +0200
+Subject: [PATCH 1560/1795] arm64: dts: renesas: salvator-common: Add ADV7482
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Salvator boards use an ADV7482 receiver for HDMI and CVBS inputs.
+
+Provide ADV7482 node on the i2c4 bus, along with connectors for the
+hdmi and cvbs inputs, and link to the csi20 and csi40 nodes as outputs.
+
+Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 908001d778eba06ee1d832863d4e9a1e2cfd4746)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/renesas/salvator-common.dtsi     | 103 ++++++++++++++++++
+ 1 file changed, 103 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+index 263e5787270e..9256fbaaab7f 100644
+--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
++++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+@@ -66,6 +66,29 @@
+ 		enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ 	};
+ 
++	cvbs-in {
++		compatible = "composite-video-connector";
++		label = "CVBS IN";
++
++		port {
++			cvbs_con: endpoint {
++				remote-endpoint = <&adv7482_ain7>;
++			};
++		};
++	};
++
++	hdmi-in {
++		compatible = "hdmi-connector";
++		label = "HDMI IN";
++		type = "a";
++
++		port {
++			hdmi_in_con: endpoint {
++				remote-endpoint = <&adv7482_hdmi>;
++			};
++		};
++	};
++
+ 	reg_1p8v: regulator0 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "fixed-1.8V";
+@@ -260,6 +283,37 @@
+ 	};
+ };
+ 
++&csi20 {
++	status = "okay";
++
++	ports {
++		port@0 {
++			reg = <0>;
++			csi20_in: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1>;
++				remote-endpoint = <&adv7482_txb>;
++			};
++		};
++	};
++};
++
++&csi40 {
++	status = "okay";
++
++	ports {
++		port@0 {
++			reg = <0>;
++
++			csi40_in: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&adv7482_txa>;
++			};
++		};
++	};
++};
++
+ &du {
+ 	pinctrl-0 = <&du_pins>;
+ 	pinctrl-names = "default";
+@@ -357,6 +411,55 @@
+ 
+ 		shunt-resistor-micro-ohms = <5000>;
+ 	};
++
++	video-receiver@70 {
++		compatible = "adi,adv7482";
++		reg = <0x70>;
++
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		interrupt-parent = <&gpio6>;
++		interrupt-names = "intrq1", "intrq2";
++		interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
++			     <31 IRQ_TYPE_LEVEL_LOW>;
++
++		port@7 {
++			reg = <7>;
++
++			adv7482_ain7: endpoint {
++				remote-endpoint = <&cvbs_con>;
++			};
++		};
++
++		port@8 {
++			reg = <8>;
++
++			adv7482_hdmi: endpoint {
++				remote-endpoint = <&hdmi_in_con>;
++			};
++		};
++
++		port@10 {
++			reg = <10>;
++
++			adv7482_txa: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&csi40_in>;
++			};
++		};
++
++		port@11 {
++			reg = <11>;
++
++			adv7482_txb: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1>;
++				remote-endpoint = <&csi20_in>;
++			};
++		};
++	};
+ };
+ 
+ &i2c_dvfs {
+-- 
+2.19.0
+
diff --git a/patches/1561-arm64-dts-renesas-Add-Renesas-R8A77990-Kconfig-suppo.patch b/patches/1561-arm64-dts-renesas-Add-Renesas-R8A77990-Kconfig-suppo.patch
new file mode 100644
index 00000000000000..9c8482ea81b631
--- /dev/null
+++ b/patches/1561-arm64-dts-renesas-Add-Renesas-R8A77990-Kconfig-suppo.patch
@@ -0,0 +1,38 @@
+From ef2d5ec51ed5b9a121128f21a47bf8910a920fcb Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 11 Apr 2018 18:35:53 +0900
+Subject: [PATCH 1561/1795] arm64: dts: renesas: Add Renesas R8A77990 Kconfig
+ support
+
+Add configuration option for the R-Car E3 (R8A77990) SoC.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit c4e96f74ad46d1139e1f31ec925c5bb21aa9830e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/Kconfig.platforms | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index 3a96d394aea4..53abe5fe6209 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -203,6 +203,12 @@ config ARCH_R8A77980
+ 	help
+ 	  This enables support for the Renesas R-Car V3H SoC.
+ 
++config ARCH_R8A77990
++	bool "Renesas R-Car E3 SoC Platform"
++	depends on ARCH_RENESAS
++	help
++	  This enables support for the Renesas R-Car E3 SoC.
++
+ config ARCH_R8A77995
+ 	bool "Renesas R-Car D3 SoC Platform"
+ 	depends on ARCH_RENESAS
+-- 
+2.19.0
+
diff --git a/patches/1562-PCI-rcar-Shut-the-PHY-down-in-failpath.patch b/patches/1562-PCI-rcar-Shut-the-PHY-down-in-failpath.patch
new file mode 100644
index 00000000000000..86e1047495f342
--- /dev/null
+++ b/patches/1562-PCI-rcar-Shut-the-PHY-down-in-failpath.patch
@@ -0,0 +1,69 @@
+From 8bea6b4f39d8099d95679ee330137b73dce46aef Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Fri, 29 Jun 2018 13:47:38 -0500
+Subject: [PATCH 1562/1795] PCI: rcar: Shut the PHY down in failpath
+
+If anything fails past phy_init_fn() and the system is a Gen3 with
+a PHY, the PHY will be left on and inited. This is caused by the
+phy_init_fn, which is in fact a pointer to rcar_pcie_phy_init_gen3()
+function, which starts the PHY, yet has no counterpart in the failpath.
+Add that counterpart.
+
+Fixes: 517ca93a7159 ("PCI: rcar: Add R-Car gen3 PHY support")
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 4050360f964694a3ac0c83badd1a441207c86889)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/pci/controller/pcie-rcar.c
+	drivers/pci/host/pcie-rcar.c
+---
+ drivers/pci/host/pcie-rcar.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 23251c6cde5c..2c0af4772c39 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -1166,7 +1166,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	if (rcar_pcie_hw_init(pcie)) {
+ 		dev_info(dev, "PCIe link down\n");
+ 		err = -ENODEV;
+-		goto err_clk_disable;
++		goto err_phy_shutdown;
+ 	}
+ 
+ 	data = rcar_pci_read_reg(pcie, MACSR);
+@@ -1178,7 +1178,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 			dev_err(dev,
+ 				"failed to enable MSI support: %d\n",
+ 				err);
+-			goto err_clk_disable;
++			goto err_phy_shutdown;
+ 		}
+ 	}
+ 
+@@ -1192,6 +1192,12 @@ static int rcar_pcie_probe(struct platform_device *pdev)
+ 	if (IS_ENABLED(CONFIG_PCI_MSI))
+ 		rcar_pcie_teardown_msi(pcie);
+ 
++err_phy_shutdown:
++	if (pcie->phy) {
++		phy_power_off(pcie->phy);
++		phy_exit(pcie->phy);
++	}
++
+ err_clk_disable:
+ 	clk_disable_unprepare(pcie->bus_clk);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1563-PCI-rcar-Clean-up-PHY-init-on-failure.patch b/patches/1563-PCI-rcar-Clean-up-PHY-init-on-failure.patch
new file mode 100644
index 00000000000000..c7e60eb0193516
--- /dev/null
+++ b/patches/1563-PCI-rcar-Clean-up-PHY-init-on-failure.patch
@@ -0,0 +1,50 @@
+From 0d00f6d5fea59ec4e3cab31df1d60b3337500702 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Fri, 29 Jun 2018 13:48:15 -0500
+Subject: [PATCH 1563/1795] PCI: rcar: Clean up PHY init on failure
+
+If the Gen3 PHY fails to power up, the code does not undo the
+initialization caused by phy_init(). Add the missing failure
+handling to the rcar_pcie_phy_init_gen3() function.
+
+Fixes: 517ca93a7159 ("PCI: rcar: Add R-Car gen3 PHY support")
+Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Simon Horman <horms+renesas@verge.net.au>
+Cc: Geert Uytterhoeven <geert+renesas@glider.be>
+Cc: Phil Edworthy <phil.edworthy@renesas.com>
+Cc: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 3c5777c372b6eb2e17802b3dc4bd5ebea45d9bcc)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/pci/controller/pcie-rcar.c
+	drivers/pci/host/pcie-rcar.c
+---
+ drivers/pci/host/pcie-rcar.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index 2c0af4772c39..2edd2155a012 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -681,7 +681,11 @@ static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
+ 	if (err)
+ 		return err;
+ 
+-	return phy_power_on(pcie->phy);
++	err = phy_power_on(pcie->phy);
++	if (err)
++		phy_exit(pcie->phy);
++
++	return err;
+ }
+ 
+ static int rcar_msi_alloc(struct rcar_msi *chip)
+-- 
+2.19.0
+
diff --git a/patches/1564-media-renesas-ceu-Set-mbus_fmt-on-subdev-operations.patch b/patches/1564-media-renesas-ceu-Set-mbus_fmt-on-subdev-operations.patch
new file mode 100644
index 00000000000000..429ca640aa5e2c
--- /dev/null
+++ b/patches/1564-media-renesas-ceu-Set-mbus_fmt-on-subdev-operations.patch
@@ -0,0 +1,98 @@
+From 39982adff49de505026c3c2a8423a640f40d6dd5 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Fri, 4 May 2018 05:32:17 -0400
+Subject: [PATCH 1564/1795] media: renesas-ceu: Set mbus_fmt on subdev
+ operations
+
+The renesas-ceu driver intializes the desired mbus_format at 'complete'
+time, inspecting the supported subdevice ones, and tuning some
+parameters to produce the requested memory format from what the sensor
+can produce. Although, the initially selected mbus_format was not
+provided to the subdevice during set_fmt and try_fmt operations,
+providing instead a '0' mbus format code.
+
+As long as the sensor defaults to a compatible mbus_format when an
+invalid code as '0' is provided, capture operations work correctly. If
+the subdevice defaults to an unsupported format (eg. some RGB
+permutations) capture does not work properly due to a mismatch on the
+expected and received image format on the wire.
+
+Fix that by re-using the initially selected mbus_format code during
+set_fmt and try_fmt subdevice operation calls.
+
+Tested by printing out the format selection procedure with ov7670
+sensor.
+
+Before this patch:
+[    0.866001] ov7670_try_fmt_internal -- Looking for mbus_code 0x0000
+[    0.870882] ov7670_try_fmt_internal -- Try mbus_code 0x2008
+[    0.876336] ov7670_try_fmt_internal -- Try mbus_code 0x1002
+[    0.881387] ov7670_try_fmt_internal -- Try mbus_code 0x1008
+[    0.886537] ov7670_try_fmt_internal -- Try mbus_code 0x3001
+[    0.891584] ov7670_try_fmt_internal -- mbus_code defaulted to 0x2008
+
+With this patch applied:
+[    0.867015] ov7670_try_fmt_internal -- Looking for mbus_code 0x2008
+[    0.873205] ov7670_try_fmt_internal -- Try mbus_code 0x2008: match
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit d3a67f27471d4792caf84132228def2b18617932)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/renesas-ceu.c | 20 +++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+index 49592030f2f1..7214ccdbb152 100644
+--- a/drivers/media/platform/renesas-ceu.c
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -777,8 +777,15 @@ static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
+ 	const struct ceu_fmt *ceu_fmt;
+ 	int ret;
+ 
++	/*
++	 * Set format on sensor sub device: bus format used to produce memory
++	 * format is selected at initialization time.
++	 */
+ 	struct v4l2_subdev_format sd_format = {
+-		.which = V4L2_SUBDEV_FORMAT_TRY,
++		.which	= V4L2_SUBDEV_FORMAT_TRY,
++		.format	= {
++			.code = ceu_sd->mbus_fmt.mbus_code,
++		},
+ 	};
+ 
+ 	switch (pix->pixelformat) {
+@@ -800,10 +807,6 @@ static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
+ 	v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
+ 			      &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
+ 
+-	/*
+-	 * Set format on sensor sub device: bus format used to produce memory
+-	 * format is selected at initialization time.
+-	 */
+ 	v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
+ 	ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_cfg, &sd_format);
+ 	if (ret)
+@@ -827,8 +830,15 @@ static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
+ 	struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
+ 	int ret;
+ 
++	/*
++	 * Set format on sensor sub device: bus format used to produce memory
++	 * format is selected at initialization time.
++	 */
+ 	struct v4l2_subdev_format format = {
+ 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.format	= {
++			.code = ceu_sd->mbus_fmt.mbus_code,
++		},
+ 	};
+ 
+ 	ret = ceu_try_fmt(ceudev, v4l2_fmt);
+-- 
+2.19.0
+
diff --git a/patches/1565-media-dt-bindings-media-renesas-ceu-Add-R-Mobile-R8A.patch b/patches/1565-media-dt-bindings-media-renesas-ceu-Add-R-Mobile-R8A.patch
new file mode 100644
index 00000000000000..79eea416369cec
--- /dev/null
+++ b/patches/1565-media-dt-bindings-media-renesas-ceu-Add-R-Mobile-R8A.patch
@@ -0,0 +1,59 @@
+From 55a23ec24200c1c7d48156856c89dfb280ef490c Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Thu, 26 Apr 2018 14:24:42 -0400
+Subject: [PATCH 1565/1795] media: dt-bindings: media: renesas-ceu: Add
+ R-Mobile R8A7740
+
+Add R-Mobile A1 R8A7740 SoC to the list of compatible values for the CEU
+unit.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 5377f3c3312e14b6f664b2db80ab3915e247ab28)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/media/renesas,ceu.txt | 7 ++++---
+ drivers/media/platform/renesas-ceu.c                    | 1 +
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt
+index 3fc66dfb192c..8a7a616e9019 100644
+--- a/Documentation/devicetree/bindings/media/renesas,ceu.txt
++++ b/Documentation/devicetree/bindings/media/renesas,ceu.txt
+@@ -2,14 +2,15 @@ Renesas Capture Engine Unit (CEU)
+ ----------------------------------------------
+ 
+ The Capture Engine Unit is the image capture interface found in the Renesas
+-SH Mobile and RZ SoCs.
++SH Mobile, R-Mobile and RZ SoCs.
+ 
+ The interface supports a single parallel input with data bus width of 8 or 16
+ bits.
+ 
+ Required properties:
+-- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
+-  and RZ/A1M SoCs.
++- compatible: Shall be one of the following values:
++	"renesas,r7s72100-ceu" for CEU units found in RZ/A1H and RZ/A1M SoCs
++	"renesas,r8a7740-ceu" for CEU units found in R-Mobile A1 R8A7740 SoCs
+ - reg: Registers address base and size.
+ - interrupts: The interrupt specifier.
+ 
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+index 7214ccdbb152..7d4b07d6c505 100644
+--- a/drivers/media/platform/renesas-ceu.c
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -1555,6 +1555,7 @@ static const struct ceu_data ceu_data_sh4 = {
+ #if IS_ENABLED(CONFIG_OF)
+ static const struct of_device_id ceu_of_match[] = {
+ 	{ .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
++	{ .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, ceu_of_match);
+-- 
+2.19.0
+
diff --git a/patches/1566-media-renesas-ceu-fix-compiler-warning.patch b/patches/1566-media-renesas-ceu-fix-compiler-warning.patch
new file mode 100644
index 00000000000000..b6b9dc29a3f52b
--- /dev/null
+++ b/patches/1566-media-renesas-ceu-fix-compiler-warning.patch
@@ -0,0 +1,37 @@
+From 5f8e3af8a09b430b076fbd431864390556a3bc63 Mon Sep 17 00:00:00 2001
+From: Hans Verkuil <hans.verkuil@cisco.com>
+Date: Mon, 14 May 2018 09:08:52 -0400
+Subject: [PATCH 1566/1795] media: renesas-ceu: fix compiler warning
+
+In function 'strncpy',
+    inlined from 'ceu_notify_complete' at drivers/media/platform/renesas-ceu.c:1378:2:
+include/linux/string.h:246:9: warning: '__builtin_strncpy' output truncated before terminating nul copying 11 bytes from a string of the same length [-Wstringop-truncation]
+  return __builtin_strncpy(p, q, size);
+         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
+Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 660f059782616aa883bd4e16dbb3c56961275c4e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/renesas-ceu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
+index 7d4b07d6c505..b2546eb26050 100644
+--- a/drivers/media/platform/renesas-ceu.c
++++ b/drivers/media/platform/renesas-ceu.c
+@@ -1375,7 +1375,7 @@ static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
+ 		return ret;
+ 
+ 	/* Register the video device. */
+-	strncpy(vdev->name, DRIVER_NAME, strlen(DRIVER_NAME));
++	strlcpy(vdev->name, DRIVER_NAME, sizeof(vdev->name));
+ 	vdev->v4l2_dev		= v4l2_dev;
+ 	vdev->lock		= &ceudev->mlock;
+ 	vdev->queue		= &ceudev->vb2_vq;
+-- 
+2.19.0
+
diff --git a/patches/1567-mmc-renesas_sdhi_internal_dmac-Fix-missing-unmap-in-.patch b/patches/1567-mmc-renesas_sdhi_internal_dmac-Fix-missing-unmap-in-.patch
new file mode 100644
index 00000000000000..f21b9396ace543
--- /dev/null
+++ b/patches/1567-mmc-renesas_sdhi_internal_dmac-Fix-missing-unmap-in-.patch
@@ -0,0 +1,60 @@
+From a3d80824d93c41026247effd658c504dd0233938 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 29 Jun 2018 19:01:44 +0900
+Subject: [PATCH 1567/1795] mmc: renesas_sdhi_internal_dmac: Fix missing unmap
+ in error patch
+
+This patch fixes an issue that lacks the dma_unmap_sg() calling in
+the error patch of renesas_sdhi_internal_dmac_start_dma().
+
+Fixes: 0cbc94daa554 ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs")
+Cc: <stable@vger.kernel.org> # v4.17+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit fe6e04941aa12479a1a58656362bec74100bf7d7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index e521f486b430..884034f10cbc 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -164,17 +164,14 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 		goto force_pio;
+ 
+ 	/* This DMAC cannot handle if buffer is not 8-bytes alignment */
+-	if (!IS_ALIGNED(sg_dma_address(sg), 8)) {
+-		dma_unmap_sg(&host->pdev->dev, sg, host->sg_len,
+-			     mmc_get_dma_dir(data));
+-		goto force_pio;
+-	}
++	if (!IS_ALIGNED(sg_dma_address(sg), 8))
++		goto force_pio_with_unmap;
+ 
+ 	if (data->flags & MMC_DATA_READ) {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+ 		if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
+ 		    test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
+-			goto force_pio;
++			goto force_pio_with_unmap;
+ 	} else {
+ 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+ 	}
+@@ -189,6 +186,9 @@ renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+ 
+ 	return;
+ 
++force_pio_with_unmap:
++	dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
++
+ force_pio:
+ 	host->force_pio = true;
+ 	renesas_sdhi_internal_dmac_enable_dma(host, false);
+-- 
+2.19.0
+
diff --git a/patches/1568-mmc-renesas_sdhi_internal_dmac-Cannot-clear-the-RX_I.patch b/patches/1568-mmc-renesas_sdhi_internal_dmac-Cannot-clear-the-RX_I.patch
new file mode 100644
index 00000000000000..c14befd0a10ba7
--- /dev/null
+++ b/patches/1568-mmc-renesas_sdhi_internal_dmac-Cannot-clear-the-RX_I.patch
@@ -0,0 +1,44 @@
+From a2dca6f42afc96b4a5c4242b3467bf05882ded10 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 29 Jun 2018 19:01:45 +0900
+Subject: [PATCH 1568/1795] mmc: renesas_sdhi_internal_dmac: Cannot clear the
+ RX_IN_USE in abort
+
+This patch is fixes an issue that the SDHI_INTERNAL_DMAC_RX_IN_USE
+flag cannot be cleared because tmio_mmc_core sets the host->data
+to NULL before the tmio_mmc_core calls tmio_mmc_abort_dma().
+
+So, this patch clears the SDHI_INTERNAL_DMAC_RX_IN_USE in
+the renesas_sdhi_internal_dmac_abort_dma() anyway. This doesn't
+cause any side effects.
+
+Fixes: 0cbc94daa554 ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs")
+Cc: <stable@vger.kernel.org> # v4.17+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 25a98edd5795719c5187e16ea271e8de86e02809)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+index 884034f10cbc..3109066e59cd 100644
+--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
++++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+@@ -139,8 +139,7 @@ renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+ 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+ 					    RST_RESERVED_BITS | val);
+ 
+-	if (host->data && host->data->flags & MMC_DATA_READ)
+-		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
++	clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
+ 
+ 	renesas_sdhi_internal_dmac_enable_dma(host, true);
+ }
+-- 
+2.19.0
+
diff --git a/patches/1569-ravb-simplify-link-auto-negotiation-by-ethtool.patch b/patches/1569-ravb-simplify-link-auto-negotiation-by-ethtool.patch
new file mode 100644
index 00000000000000..7d0ecf91e9ab5f
--- /dev/null
+++ b/patches/1569-ravb-simplify-link-auto-negotiation-by-ethtool.patch
@@ -0,0 +1,36 @@
+From 035ef37756e4d88c89f47c3fc727808c222a42e9 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:16:08 +0300
+Subject: [PATCH 1569/1795] ravb: simplify link auto-negotiation by ethtool
+
+There is no need to call a heavyweight phy_start_aneg() for phy
+auto-negotiation by ethtool, the phy is already initialized and
+link auto-negotiation is started by calling phy_start() from
+ravb_phy_start() when a network device is opened.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 2a150c504ac20bd978ae599ba8139e6658d64fd7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 40266fe01186..31913a469001 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1136,7 +1136,7 @@ static int ravb_nway_reset(struct net_device *ndev)
+ 	int error = -ENODEV;
+ 
+ 	if (ndev->phydev)
+-		error = phy_start_aneg(ndev->phydev);
++		error = phy_restart_aneg(ndev->phydev);
+ 
+ 	return error;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1570-ravb-remove-custom-.nway_reset-from-ethtool-ops.patch b/patches/1570-ravb-remove-custom-.nway_reset-from-ethtool-ops.patch
new file mode 100644
index 00000000000000..312282768b8a64
--- /dev/null
+++ b/patches/1570-ravb-remove-custom-.nway_reset-from-ethtool-ops.patch
@@ -0,0 +1,51 @@
+From 95c76a983d080d4a0bd1e18f98fbaaf9692e0746 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:16:09 +0300
+Subject: [PATCH 1570/1795] ravb: remove custom .nway_reset from ethtool ops
+
+The generic phy_ethtool_nway_reset() function from phylib can be used
+instead of in-house ravb_nway_reset().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit eeb07284717be2950c3b501df2debc0373eae19a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 12 +-----------
+ 1 file changed, 1 insertion(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 31913a469001..6002132093cd 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1131,16 +1131,6 @@ static int ravb_set_link_ksettings(struct net_device *ndev,
+ 	return phy_ethtool_ksettings_set(ndev->phydev, cmd);
+ }
+ 
+-static int ravb_nway_reset(struct net_device *ndev)
+-{
+-	int error = -ENODEV;
+-
+-	if (ndev->phydev)
+-		error = phy_restart_aneg(ndev->phydev);
+-
+-	return error;
+-}
+-
+ static u32 ravb_get_msglevel(struct net_device *ndev)
+ {
+ 	struct ravb_private *priv = netdev_priv(ndev);
+@@ -1353,7 +1343,7 @@ static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ }
+ 
+ static const struct ethtool_ops ravb_ethtool_ops = {
+-	.nway_reset		= ravb_nway_reset,
++	.nway_reset		= phy_ethtool_nway_reset,
+ 	.get_msglevel		= ravb_get_msglevel,
+ 	.set_msglevel		= ravb_set_msglevel,
+ 	.get_link		= ethtool_op_get_link,
+-- 
+2.19.0
+
diff --git a/patches/1571-ravb-remove-useless-serialization-in-ravb_get_link_k.patch b/patches/1571-ravb-remove-useless-serialization-in-ravb_get_link_k.patch
new file mode 100644
index 00000000000000..7d6c35c0bfe2a7
--- /dev/null
+++ b/patches/1571-ravb-remove-useless-serialization-in-ravb_get_link_k.patch
@@ -0,0 +1,43 @@
+From 003e0609368205c1957c601345f55d0e85f07bfc Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:16:10 +0300
+Subject: [PATCH 1571/1795] ravb: remove useless serialization in
+ ravb_get_link_ksettings()
+
+phy_ethtool_ksettings_get() call does not modify device state or device
+driver state, hence there is no need to utilize a driver specific
+spinlock.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit efdf75112d89e28c928a22c3a38456b49927f445)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 6002132093cd..772687a5faee 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1109,15 +1109,10 @@ static int ravb_phy_start(struct net_device *ndev)
+ static int ravb_get_link_ksettings(struct net_device *ndev,
+ 				   struct ethtool_link_ksettings *cmd)
+ {
+-	struct ravb_private *priv = netdev_priv(ndev);
+-	unsigned long flags;
+-
+ 	if (!ndev->phydev)
+ 		return -ENODEV;
+ 
+-	spin_lock_irqsave(&priv->lock, flags);
+ 	phy_ethtool_ksettings_get(ndev->phydev, cmd);
+-	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1572-ravb-remove-custom-.get_link_ksettings-from-ethtool-.patch b/patches/1572-ravb-remove-custom-.get_link_ksettings-from-ethtool-.patch
new file mode 100644
index 00000000000000..e24e907c128853
--- /dev/null
+++ b/patches/1572-ravb-remove-custom-.get_link_ksettings-from-ethtool-.patch
@@ -0,0 +1,53 @@
+From 9764852a7726eeb0027a48fecffa2bcb63c35452 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:16:11 +0300
+Subject: [PATCH 1572/1795] ravb: remove custom .get_link_ksettings from
+ ethtool ops
+
+The generic phy_ethtool_get_link_ksettings() function from phylib can be
+used instead of in-house ravb_get_link_ksettings().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 468e40b5fe4fe18e8468dfd03ba4457a9102d066)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 772687a5faee..9fe01259be6f 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1106,17 +1106,6 @@ static int ravb_phy_start(struct net_device *ndev)
+ 	return 0;
+ }
+ 
+-static int ravb_get_link_ksettings(struct net_device *ndev,
+-				   struct ethtool_link_ksettings *cmd)
+-{
+-	if (!ndev->phydev)
+-		return -ENODEV;
+-
+-	phy_ethtool_ksettings_get(ndev->phydev, cmd);
+-
+-	return 0;
+-}
+-
+ static int ravb_set_link_ksettings(struct net_device *ndev,
+ 				   const struct ethtool_link_ksettings *cmd)
+ {
+@@ -1348,7 +1337,7 @@ static const struct ethtool_ops ravb_ethtool_ops = {
+ 	.get_ringparam		= ravb_get_ringparam,
+ 	.set_ringparam		= ravb_set_ringparam,
+ 	.get_ts_info		= ravb_get_ts_info,
+-	.get_link_ksettings	= ravb_get_link_ksettings,
++	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
+ 	.set_link_ksettings	= ravb_set_link_ksettings,
+ 	.get_wol		= ravb_get_wol,
+ 	.set_wol		= ravb_set_wol,
+-- 
+2.19.0
+
diff --git a/patches/1573-ravb-remove-custom-.set_link_ksettings-from-ethtool-.patch b/patches/1573-ravb-remove-custom-.set_link_ksettings-from-ethtool-.patch
new file mode 100644
index 00000000000000..345135a533138a
--- /dev/null
+++ b/patches/1573-ravb-remove-custom-.set_link_ksettings-from-ethtool-.patch
@@ -0,0 +1,51 @@
+From fca4b0160703f9c6132525dbb7c82b3049004ebe Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:16:12 +0300
+Subject: [PATCH 1573/1795] ravb: remove custom .set_link_ksettings from
+ ethtool ops
+
+The generic phy_ethtool_set_link_ksettings() function from phylib can
+be used instead of in-house ravb_set_link_ksettings().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 44f3d5581ebbdff59311d45cf862d2e040aeefeb)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/ravb_main.c | 11 +----------
+ 1 file changed, 1 insertion(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 9fe01259be6f..0d811c02ff34 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1106,15 +1106,6 @@ static int ravb_phy_start(struct net_device *ndev)
+ 	return 0;
+ }
+ 
+-static int ravb_set_link_ksettings(struct net_device *ndev,
+-				   const struct ethtool_link_ksettings *cmd)
+-{
+-	if (!ndev->phydev)
+-		return -ENODEV;
+-
+-	return phy_ethtool_ksettings_set(ndev->phydev, cmd);
+-}
+-
+ static u32 ravb_get_msglevel(struct net_device *ndev)
+ {
+ 	struct ravb_private *priv = netdev_priv(ndev);
+@@ -1338,7 +1329,7 @@ static const struct ethtool_ops ravb_ethtool_ops = {
+ 	.set_ringparam		= ravb_set_ringparam,
+ 	.get_ts_info		= ravb_get_ts_info,
+ 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
+-	.set_link_ksettings	= ravb_set_link_ksettings,
++	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
+ 	.get_wol		= ravb_get_wol,
+ 	.set_wol		= ravb_set_wol,
+ };
+-- 
+2.19.0
+
diff --git a/patches/1574-sh_eth-simplify-link-auto-negotiation-by-ethtool.patch b/patches/1574-sh_eth-simplify-link-auto-negotiation-by-ethtool.patch
new file mode 100644
index 00000000000000..ff7ae310b4502a
--- /dev/null
+++ b/patches/1574-sh_eth-simplify-link-auto-negotiation-by-ethtool.patch
@@ -0,0 +1,36 @@
+From cb33249bea8088b080595f2c7e60a1732b3b5bf1 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:12:41 +0300
+Subject: [PATCH 1574/1795] sh_eth: simplify link auto-negotiation by ethtool
+
+There is no need to call a heavyweight phy_start_aneg() for phy
+auto-negotiation by ethtool, the phy is already initialized and
+link auto-negotiation is started by calling phy_start() from
+sh_eth_phy_start() when a network device is opened.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit e0afa1030b7ffc2fb68d38fb859837f13cdd3807)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index d83683961d87..4b31f794c8db 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2249,7 +2249,7 @@ static int sh_eth_nway_reset(struct net_device *ndev)
+ 	if (!ndev->phydev)
+ 		return -ENODEV;
+ 
+-	return phy_start_aneg(ndev->phydev);
++	return phy_restart_aneg(ndev->phydev);
+ }
+ 
+ static u32 sh_eth_get_msglevel(struct net_device *ndev)
+-- 
+2.19.0
+
diff --git a/patches/1575-sh_eth-remove-custom-.nway_reset-from-ethtool-ops.patch b/patches/1575-sh_eth-remove-custom-.nway_reset-from-ethtool-ops.patch
new file mode 100644
index 00000000000000..15044b6e414a38
--- /dev/null
+++ b/patches/1575-sh_eth-remove-custom-.nway_reset-from-ethtool-ops.patch
@@ -0,0 +1,49 @@
+From d54e4fe5434d44ea3bee1e8cfed5e620deb04dc1 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:12:42 +0300
+Subject: [PATCH 1575/1795] sh_eth: remove custom .nway_reset from ethtool ops
+
+The generic phy_ethtool_nway_reset() function from phylib can be used
+instead of in-house sh_eth_nway_reset().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 4c10628afda78dbf5dffc13360b576370ee98aab)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 10 +---------
+ 1 file changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 4b31f794c8db..ad8f1d9edf01 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2244,14 +2244,6 @@ static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
+ 	pm_runtime_put_sync(&mdp->pdev->dev);
+ }
+ 
+-static int sh_eth_nway_reset(struct net_device *ndev)
+-{
+-	if (!ndev->phydev)
+-		return -ENODEV;
+-
+-	return phy_restart_aneg(ndev->phydev);
+-}
+-
+ static u32 sh_eth_get_msglevel(struct net_device *ndev)
+ {
+ 	struct sh_eth_private *mdp = netdev_priv(ndev);
+@@ -2402,7 +2394,7 @@ static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
+ static const struct ethtool_ops sh_eth_ethtool_ops = {
+ 	.get_regs_len	= sh_eth_get_regs_len,
+ 	.get_regs	= sh_eth_get_regs,
+-	.nway_reset	= sh_eth_nway_reset,
++	.nway_reset	= phy_ethtool_nway_reset,
+ 	.get_msglevel	= sh_eth_get_msglevel,
+ 	.set_msglevel	= sh_eth_set_msglevel,
+ 	.get_link	= ethtool_op_get_link,
+-- 
+2.19.0
+
diff --git a/patches/1576-sh_eth-remove-useless-serialization-in-sh_eth_get_li.patch b/patches/1576-sh_eth-remove-useless-serialization-in-sh_eth_get_li.patch
new file mode 100644
index 00000000000000..d2b865af3f52d5
--- /dev/null
+++ b/patches/1576-sh_eth-remove-useless-serialization-in-sh_eth_get_li.patch
@@ -0,0 +1,43 @@
+From 01100d6436dac14967691643d1f6b4aca7a76fb2 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:14:47 +0300
+Subject: [PATCH 1576/1795] sh_eth: remove useless serialization in
+ sh_eth_get_link_ksettings()
+
+phy_ethtool_ksettings_get() call does not modify device state or device
+driver state, hence there is no need to utilize a driver specific
+spinlock.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit f3146f3774c8657b25326313ce807a5d4eac1d40)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index ad8f1d9edf01..1887ae80fa47 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2043,15 +2043,10 @@ static int sh_eth_phy_start(struct net_device *ndev)
+ static int sh_eth_get_link_ksettings(struct net_device *ndev,
+ 				     struct ethtool_link_ksettings *cmd)
+ {
+-	struct sh_eth_private *mdp = netdev_priv(ndev);
+-	unsigned long flags;
+-
+ 	if (!ndev->phydev)
+ 		return -ENODEV;
+ 
+-	spin_lock_irqsave(&mdp->lock, flags);
+ 	phy_ethtool_ksettings_get(ndev->phydev, cmd);
+-	spin_unlock_irqrestore(&mdp->lock, flags);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1577-sh_eth-remove-custom-.get_link_ksettings-from-ethtoo.patch b/patches/1577-sh_eth-remove-custom-.get_link_ksettings-from-ethtoo.patch
new file mode 100644
index 00000000000000..f9ea2376900841
--- /dev/null
+++ b/patches/1577-sh_eth-remove-custom-.get_link_ksettings-from-ethtoo.patch
@@ -0,0 +1,53 @@
+From b613d922e8c944e6652fe1193618c92c2b4d61e2 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:14:48 +0300
+Subject: [PATCH 1577/1795] sh_eth: remove custom .get_link_ksettings from
+ ethtool ops
+
+The generic phy_ethtool_get_link_ksettings() function from phylib can be
+used instead of in-house sh_eth_get_link_ksettings().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 45abbd431939fe77b365949e946fb29094d72656)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index 1887ae80fa47..bd4b64220fff 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2040,17 +2040,6 @@ static int sh_eth_phy_start(struct net_device *ndev)
+ 	return 0;
+ }
+ 
+-static int sh_eth_get_link_ksettings(struct net_device *ndev,
+-				     struct ethtool_link_ksettings *cmd)
+-{
+-	if (!ndev->phydev)
+-		return -ENODEV;
+-
+-	phy_ethtool_ksettings_get(ndev->phydev, cmd);
+-
+-	return 0;
+-}
+-
+ static int sh_eth_set_link_ksettings(struct net_device *ndev,
+ 				     const struct ethtool_link_ksettings *cmd)
+ {
+@@ -2398,7 +2387,7 @@ static const struct ethtool_ops sh_eth_ethtool_ops = {
+ 	.get_sset_count     = sh_eth_get_sset_count,
+ 	.get_ringparam	= sh_eth_get_ringparam,
+ 	.set_ringparam	= sh_eth_set_ringparam,
+-	.get_link_ksettings = sh_eth_get_link_ksettings,
++	.get_link_ksettings = phy_ethtool_get_link_ksettings,
+ 	.set_link_ksettings = sh_eth_set_link_ksettings,
+ 	.get_wol	= sh_eth_get_wol,
+ 	.set_wol	= sh_eth_set_wol,
+-- 
+2.19.0
+
diff --git a/patches/1578-sh_eth-remove-custom-.set_link_ksettings-from-ethtoo.patch b/patches/1578-sh_eth-remove-custom-.set_link_ksettings-from-ethtoo.patch
new file mode 100644
index 00000000000000..86e51ebd91f909
--- /dev/null
+++ b/patches/1578-sh_eth-remove-custom-.set_link_ksettings-from-ethtoo.patch
@@ -0,0 +1,51 @@
+From edb02a174f7abd5edf23f73c77622e0588f4f5c1 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Date: Wed, 4 Jul 2018 11:14:49 +0300
+Subject: [PATCH 1578/1795] sh_eth: remove custom .set_link_ksettings from
+ ethtool ops
+
+The generic phy_ethtool_set_link_ksettings() function from phylib can
+be used instead of in-house sh_eth_set_link_ksettings().
+
+Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 6783f50ed144aafe8c3aceb223db2c7956278a1f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 11 +----------
+ 1 file changed, 1 insertion(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
+index bd4b64220fff..87a6bcdda05a 100644
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -2040,15 +2040,6 @@ static int sh_eth_phy_start(struct net_device *ndev)
+ 	return 0;
+ }
+ 
+-static int sh_eth_set_link_ksettings(struct net_device *ndev,
+-				     const struct ethtool_link_ksettings *cmd)
+-{
+-	if (!ndev->phydev)
+-		return -ENODEV;
+-
+-	return phy_ethtool_ksettings_set(ndev->phydev, cmd);
+-}
+-
+ /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
+  * version must be bumped as well.  Just adding registers up to that
+  * limit is fine, as long as the existing register indices don't
+@@ -2388,7 +2379,7 @@ static const struct ethtool_ops sh_eth_ethtool_ops = {
+ 	.get_ringparam	= sh_eth_get_ringparam,
+ 	.set_ringparam	= sh_eth_set_ringparam,
+ 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
+-	.set_link_ksettings = sh_eth_set_link_ksettings,
++	.set_link_ksettings = phy_ethtool_set_link_ksettings,
+ 	.get_wol	= sh_eth_get_wol,
+ 	.set_wol	= sh_eth_set_wol,
+ };
+-- 
+2.19.0
+
diff --git a/patches/1579-pinctrl-sh-pfc-r8a77970-remove-SH_PFC_PIN_CFG_DRIVE_.patch b/patches/1579-pinctrl-sh-pfc-r8a77970-remove-SH_PFC_PIN_CFG_DRIVE_.patch
new file mode 100644
index 00000000000000..7c67b7bb029a36
--- /dev/null
+++ b/patches/1579-pinctrl-sh-pfc-r8a77970-remove-SH_PFC_PIN_CFG_DRIVE_.patch
@@ -0,0 +1,63 @@
+From de6a3a7331d02680b3f5a79d1181b720afc5545e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Tue, 3 Jul 2018 17:18:42 +0200
+Subject: [PATCH 1579/1795] pinctrl: sh-pfc: r8a77970: remove
+ SH_PFC_PIN_CFG_DRIVE_STRENGTH flag
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The datasheet does not document any registers to control drive strength,
+and no drive strength registers are for this reason described for this
+SoC. The flags indicating that drive strength can be controlled are
+however set for some pins in the driver.
+
+This leads to a NULL pointer dereference when the sh-pfc core tries to
+access the struct describing the drive strength registers, for example
+when reading the sysfs file pinconf-pins.
+
+Fix this by removing the SH_PFC_PIN_CFG_DRIVE_STRENGTH from all pins.
+
+Fixes: b92ac66a1819602b ("pinctrl: sh-pfc: Add R8A77970 PFC support")
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 550b6f7e8cf93fc2753aa01e655ed5471012ab5a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 14 ++++++--------
+ 1 file changed, 6 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+index b02caf316711..eeb58b3bbc9a 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+@@ -21,15 +21,13 @@
+ #include "core.h"
+ #include "sh_pfc.h"
+ 
+-#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
+-
+ #define CPU_ALL_PORT(fn, sfx)						\
+-	PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+-	PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),				\
+-	PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+-	PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+-	PORT_GP_CFG_6(4,  fn, sfx, CFG_FLAGS),				\
+-	PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
++	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
++	PORT_GP_28(1, fn, sfx),						\
++	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
++	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
++	PORT_GP_6(4,  fn, sfx),						\
++	PORT_GP_15(5, fn, sfx)
+ /*
+  * F_() : just information
+  * FM() : macro for FN_xxx / xxx_MARK
+-- 
+2.19.0
+
diff --git a/patches/1580-gpio-pca953x-Use-of_device_get_match_data.patch b/patches/1580-gpio-pca953x-Use-of_device_get_match_data.patch
new file mode 100644
index 00000000000000..851b237e06d075
--- /dev/null
+++ b/patches/1580-gpio-pca953x-Use-of_device_get_match_data.patch
@@ -0,0 +1,41 @@
+From 1b5e69f6b66b74be7129e90b698a6f893bb1b36a Mon Sep 17 00:00:00 2001
+From: Thierry Reding <treding@nvidia.com>
+Date: Mon, 30 Apr 2018 09:38:14 +0200
+Subject: [PATCH 1580/1795] gpio: pca953x: Use of_device_get_match_data()
+
+Use of_device_get_match_data() instead of open-coding it.
+
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 67bab9353391f65a497442b1f9f920d452790c5a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index c8bfd4acb40d..6d202acf853e 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -810,13 +810,11 @@ static int pca953x_probe(struct i2c_client *client,
+ 		chip->driver_data = i2c_id->driver_data;
+ 	} else {
+ 		const struct acpi_device_id *acpi_id;
+-		const struct of_device_id *match;
++		struct device *dev = &client->dev;
+ 
+-		match = of_match_device(pca953x_dt_ids, &client->dev);
+-		if (match) {
+-			chip->driver_data = (int)(uintptr_t)match->data;
+-		} else {
+-			acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
++		chip->driver_data = (uintptr_t)of_device_get_match_data(dev);
++		if (!chip->driver_data) {
++			acpi_id = acpi_match_device(pca953x_acpi_ids, dev);
+ 			if (!acpi_id) {
+ 				ret = -ENODEV;
+ 				goto err_exit;
+-- 
+2.19.0
+
diff --git a/patches/1581-gpio-pca953x-convert-register-constants-to-hex.patch b/patches/1581-gpio-pca953x-convert-register-constants-to-hex.patch
new file mode 100644
index 00000000000000..51dbfa895f23f8
--- /dev/null
+++ b/patches/1581-gpio-pca953x-convert-register-constants-to-hex.patch
@@ -0,0 +1,66 @@
+From c8a4040d188a106f693fbede39e32a5691f04eff Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 28 Apr 2018 18:31:31 +0200
+Subject: [PATCH 1581/1795] gpio: pca953x: convert register constants to hex
+
+which makes it easier to match them with the data sheets.
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 0950c19acaaa8f899f715954e2918ff45e5b2fc8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 32 ++++++++++++++++----------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index 6d202acf853e..d18eeaa48189 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -25,25 +25,25 @@
+ 
+ #include <asm/unaligned.h>
+ 
+-#define PCA953X_INPUT		0
+-#define PCA953X_OUTPUT		1
+-#define PCA953X_INVERT		2
+-#define PCA953X_DIRECTION	3
++#define PCA953X_INPUT		0x00
++#define PCA953X_OUTPUT		0x01
++#define PCA953X_INVERT		0x02
++#define PCA953X_DIRECTION	0x03
+ 
+ #define REG_ADDR_AI		0x80
+ 
+-#define PCA957X_IN		0
+-#define PCA957X_INVRT		1
+-#define PCA957X_BKEN		2
+-#define PCA957X_PUPD		3
+-#define PCA957X_CFG		4
+-#define PCA957X_OUT		5
+-#define PCA957X_MSK		6
+-#define PCA957X_INTS		7
+-
+-#define PCAL953X_IN_LATCH	34
+-#define PCAL953X_INT_MASK	37
+-#define PCAL953X_INT_STAT	38
++#define PCA957X_IN		0x00
++#define PCA957X_INVRT		0x01
++#define PCA957X_BKEN		0x02
++#define PCA957X_PUPD		0x03
++#define PCA957X_CFG		0x04
++#define PCA957X_OUT		0x05
++#define PCA957X_MSK		0x06
++#define PCA957X_INTS		0x07
++
++#define PCAL953X_IN_LATCH	0x22
++#define PCAL953X_INT_MASK	0x25
++#define PCAL953X_INT_STAT	0x26
+ 
+ #define PCA_GPIO_MASK		0x00FF
+ #define PCA_INT			0x0100
+-- 
+2.19.0
+
diff --git a/patches/1582-gpio-pca953x-add-more-register-definitions-for-pcal9.patch b/patches/1582-gpio-pca953x-add-more-register-definitions-for-pcal9.patch
new file mode 100644
index 00000000000000..c8a134e4d96120
--- /dev/null
+++ b/patches/1582-gpio-pca953x-add-more-register-definitions-for-pcal9.patch
@@ -0,0 +1,41 @@
+From c690f95b6d7977443dc687304e22dbee35031a71 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 28 Apr 2018 18:31:32 +0200
+Subject: [PATCH 1582/1795] gpio: pca953x: add more register definitions for
+ pcal953x
+
+PCAL chips ("L" seems to stand for "latched") have additional
+registers starting at address 0x40 to control the latches,
+interrupt mask, pull-up and pull down etc.
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 6315d231efdc6ff1f3344e2d3c66dabcf6e7c27f)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index d18eeaa48189..fbe99e741da6 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -41,9 +41,13 @@
+ #define PCA957X_MSK		0x06
+ #define PCA957X_INTS		0x07
+ 
++#define PCAL953X_OUT_STRENGTH	0x20
+ #define PCAL953X_IN_LATCH	0x22
++#define PCAL953X_PULL_EN	0x23
++#define PCAL953X_PULL_SEL	0x24
+ #define PCAL953X_INT_MASK	0x25
+ #define PCAL953X_INT_STAT	0x26
++#define PCAL953X_OUT_CONF	0x27
+ 
+ #define PCA_GPIO_MASK		0x00FF
+ #define PCA_INT			0x0100
+-- 
+2.19.0
+
diff --git a/patches/1583-gpio-pca953x-add-more-register-definitions-for-pcal6.patch b/patches/1583-gpio-pca953x-add-more-register-definitions-for-pcal6.patch
new file mode 100644
index 00000000000000..cfd0ee5b5c778f
--- /dev/null
+++ b/patches/1583-gpio-pca953x-add-more-register-definitions-for-pcal6.patch
@@ -0,0 +1,39 @@
+From 859f5e498c6c59a3ff28d319c7fd6071c1efc58a Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 28 Apr 2018 18:31:33 +0200
+Subject: [PATCH 1583/1795] gpio: pca953x: add more register definitions for
+ pcal6524
+
+The pcal6524 has another set of registers to fine control
+the interrupt handling.
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit a0ecbcccb5478e55293424ec4a5515498b234bf2)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index fbe99e741da6..34ea3f46bf26 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -49,6 +49,12 @@
+ #define PCAL953X_INT_STAT	0x26
+ #define PCAL953X_OUT_CONF	0x27
+ 
++#define PCAL6524_INT_EDGE	0x28
++#define PCAL6524_INT_CLR	0x2a
++#define PCAL6524_IN_STATUS	0x2b
++#define PCAL6524_OUT_INDCONF	0x2c
++#define PCAL6524_DEBOUNCE	0x2d
++
+ #define PCA_GPIO_MASK		0x00FF
+ #define PCA_INT			0x0100
+ #define PCA_PCAL		0x0200
+-- 
+2.19.0
+
diff --git a/patches/1584-DTS-Bindings-pca953x-add-an-optional-vcc-supply-prop.patch b/patches/1584-DTS-Bindings-pca953x-add-an-optional-vcc-supply-prop.patch
new file mode 100644
index 00000000000000..93cf202db6d4f8
--- /dev/null
+++ b/patches/1584-DTS-Bindings-pca953x-add-an-optional-vcc-supply-prop.patch
@@ -0,0 +1,34 @@
+From 094c69f7ea5602e6991bf5a5ed12d7c3d80a3478 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 28 Apr 2018 18:31:36 +0200
+Subject: [PATCH 1584/1795] DTS: Bindings: pca953x add an optional vcc-supply
+ property
+
+Hardware can have a switchable Vcc supply, so let's add it to
+the bindings (the current Linux driver code already supports it).
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit adc07ab7459d0d4c7c86ffdcf3a0a72c8803803c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+index d2a937682836..6a7cddb187c1 100644
+--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+@@ -35,6 +35,7 @@ Required properties:
+ Optional properties:
+  - reset-gpios: GPIO specification for the RESET input. This is an
+ 		active low signal to the PCA953x.
++ - vcc-supply:	power supply regulator.
+ 
+ Example:
+ 
+-- 
+2.19.0
+
diff --git a/patches/1585-pca953x-add-example-how-to-use-interrupt-controller-.patch b/patches/1585-pca953x-add-example-how-to-use-interrupt-controller-.patch
new file mode 100644
index 00000000000000..f7a56f7a0e4ac4
--- /dev/null
+++ b/patches/1585-pca953x-add-example-how-to-use-interrupt-controller-.patch
@@ -0,0 +1,70 @@
+From dae17cb695268e4cd9a34a13f4624c6aa0da9116 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Sat, 28 Apr 2018 18:31:37 +0200
+Subject: [PATCH 1585/1795] pca953x: add example how to use
+ interrupt-controller and gpio-controller
+
+It is not completely obvious that these are required and
+how to use them. So we provide a tested example.
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 6906a4f9d10b27853e80998afcfb290d8f91c071)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../devicetree/bindings/gpio/gpio-pca953x.txt | 33 +++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+index 6a7cddb187c1..88f228665507 100644
+--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+@@ -31,6 +31,10 @@ Required properties:
+ 	ti,tca9554
+ 	onnn,pca9654
+ 	exar,xra1202
++ - gpio-controller: if used as gpio expander.
++ - #gpio-cells: if used as gpio expander.
++ - interrupt-controller: if to be used as interrupt expander.
++ - #interrupt-cells: if to be used as interrupt expander.
+ 
+ Optional properties:
+  - reset-gpios: GPIO specification for the RESET input. This is an
+@@ -48,3 +52,32 @@ Example:
+ 		interrupt-parent = <&gpio3>;
+ 		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ 	};
++
++
++Example with Interrupts:
++
++
++	gpio99: gpio@22 {
++		compatible = "nxp,pcal6524";
++		reg = <0x22>;
++		interrupt-parent = <&gpio6>;
++		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;	/* gpio6_161 */
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		vcc-supply = <&vdds_1v8_main>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		gpio-line-names =
++			"hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03", "vibra", "fault2", "p06", "p07",
++			"en-usb", "en-host1", "en-host2", "chg-int", "p14", "p15", "mic-int", "en-modem",
++			"shdn-hs-amp", "chg-status+red", "green", "blue", "en-esata", "fault1", "p26", "p27";
++	};
++
++	ts3a227@3b {
++		compatible = "ti,ts3a227e";
++		reg = <0x3b>;
++		interrupt-parent = <&gpio99>;
++		interrupts = <14 IRQ_TYPE_EDGE_RISING>;
++		ti,micbias = <0>;	/* 2.1V */
++	};
++
+-- 
+2.19.0
+
diff --git a/patches/1586-gpio-pca953x-Clear-irq-trigger-type-on-irq-shutdown.patch b/patches/1586-gpio-pca953x-Clear-irq-trigger-type-on-irq-shutdown.patch
new file mode 100644
index 00000000000000..f2932598f4e685
--- /dev/null
+++ b/patches/1586-gpio-pca953x-Clear-irq-trigger-type-on-irq-shutdown.patch
@@ -0,0 +1,54 @@
+From d67249cb6cda73338d386bcf5f06c11fd9f9177c Mon Sep 17 00:00:00 2001
+From: Grigoryev Denis <grigoryev@fastwel.ru>
+Date: Fri, 4 May 2018 16:53:18 +0000
+Subject: [PATCH 1586/1795] gpio: pca953x: Clear irq trigger type on irq
+ shutdown
+
+The driver stores the result of irq_set_type() in the internal variables
+irq_trig_raise and irq_trig_fall, which later are used to determine
+the GPIOs that must be re-configured as input. These variables retain their
+value between gpiolib's  export / unexport, resulting in an incorrect
+state in some cases. The corresponding bits in the variables
+irq_trig_raise and irq_trig_fall should be cleared in irq_shutdown().
+
+Signed-off-by: Denis Grigoryev <grigoryev@fastwel.ru>
+Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 0a70fe00efea7c6ac087a10aa57131e59d63e194)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index 34ea3f46bf26..b0fe0189de62 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -532,6 +532,15 @@ static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
+ 	return 0;
+ }
+ 
++static void pca953x_irq_shutdown(struct irq_data *d)
++{
++	struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
++	u8 mask = 1 << (d->hwirq % BANK_SZ);
++
++	chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask;
++	chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask;
++}
++
+ static struct irq_chip pca953x_irq_chip = {
+ 	.name			= "pca953x",
+ 	.irq_mask		= pca953x_irq_mask,
+@@ -539,6 +548,7 @@ static struct irq_chip pca953x_irq_chip = {
+ 	.irq_bus_lock		= pca953x_irq_bus_lock,
+ 	.irq_bus_sync_unlock	= pca953x_irq_bus_sync_unlock,
+ 	.irq_set_type		= pca953x_irq_set_type,
++	.irq_shutdown		= pca953x_irq_shutdown,
+ };
+ 
+ static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
+-- 
+2.19.0
+
diff --git a/patches/1587-gpio-pca953x-set-the-PCA_PCAL-flag-also-when-matchin.patch b/patches/1587-gpio-pca953x-set-the-PCA_PCAL-flag-also-when-matchin.patch
new file mode 100644
index 00000000000000..7a5e8043e9bc58
--- /dev/null
+++ b/patches/1587-gpio-pca953x-set-the-PCA_PCAL-flag-also-when-matchin.patch
@@ -0,0 +1,47 @@
+From 81341d5d1fa297150011cec1ee475693f98174c6 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Thu, 17 May 2018 06:59:47 +0200
+Subject: [PATCH 1587/1795] gpio: pca953x: set the PCA_PCAL flag also when
+ matching by DT
+
+The of_device_table is missing the PCA_PCAL flag so the
+pcal6524 would be operated in tca6424 compatibility mode which
+does not handle the new interrupt mask registers.
+
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 0cdf21b34e3062af8da0a2a1c419654263c21b87)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index b0fe0189de62..9efb573421b4 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -58,6 +58,7 @@
+ #define PCA_GPIO_MASK		0x00FF
+ #define PCA_INT			0x0100
+ #define PCA_PCAL		0x0200
++#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
+ #define PCA953X_TYPE		0x1000
+ #define PCA957X_TYPE		0x2000
+ #define PCA_TYPE_MASK		0xF000
+@@ -954,8 +955,8 @@ static const struct of_device_id pca953x_dt_ids[] = {
+ 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+ 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ 
+-	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_INT), },
+-	{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_INT), },
++	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
++	{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
+ 
+ 	{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
+ 	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+-- 
+2.19.0
+
diff --git a/patches/1588-gpio-pca953x-define-masks-for-addressing-common-and-.patch b/patches/1588-gpio-pca953x-define-masks-for-addressing-common-and-.patch
new file mode 100644
index 00000000000000..042b771f1cad76
--- /dev/null
+++ b/patches/1588-gpio-pca953x-define-masks-for-addressing-common-and-.patch
@@ -0,0 +1,38 @@
+From 47bd6e6280da441966dccee43144c34227435533 Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Thu, 17 May 2018 06:59:48 +0200
+Subject: [PATCH 1588/1795] gpio: pca953x: define masks for addressing common
+ and extended registers
+
+These mask bits are to be used to map the extended register
+addresses (which are defined for an unsupported 8-bit pcal chip)
+to 16 and 24 bit chips (pcal6524).
+
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 394aeef83c7080c9fd850e3479e0cd58e510163b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index 9efb573421b4..9aabe2091af0 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -56,6 +56,10 @@
+ #define PCAL6524_DEBOUNCE	0x2d
+ 
+ #define PCA_GPIO_MASK		0x00FF
++
++#define PCAL_GPIO_MASK		0x1f
++#define PCAL_PINCTRL_MASK	0xe0
++
+ #define PCA_INT			0x0100
+ #define PCA_PCAL		0x0200
+ #define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
+-- 
+2.19.0
+
diff --git a/patches/1589-gpio-pca953x-fix-address-calculation-for-pcal6524.patch b/patches/1589-gpio-pca953x-fix-address-calculation-for-pcal6524.patch
new file mode 100644
index 00000000000000..95b23a3eb77b8b
--- /dev/null
+++ b/patches/1589-gpio-pca953x-fix-address-calculation-for-pcal6524.patch
@@ -0,0 +1,66 @@
+From dff66169ef56103337ae2677c9b46733535df78f Mon Sep 17 00:00:00 2001
+From: "H. Nikolaus Schaller" <hns@goldelico.com>
+Date: Thu, 17 May 2018 06:59:49 +0200
+Subject: [PATCH 1589/1795] gpio: pca953x: fix address calculation for pcal6524
+
+The register constants are so far defined in a way that they fit
+for the pcal9555a when shifted by the number of banks, i.e. are
+multiplied by 2 in the accessor function.
+
+Now, the pcal6524 has 3 banks which means the relative offset
+is multiplied by 4 for the standard registers.
+
+Simply applying the bit shift to the extended registers gives
+a wrong result, since the base offset is already included in
+the offset.
+
+Therefore, we have to add code to the 24 bit accessor functions
+that adjusts the register number for these exended registers.
+
+The formula finally used was developed and proposed by
+Andy Shevchenko <andy.shevchenko@gmail.com>.
+
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit d5dbf9c266ccf632cdf259146e4ec62b381db655)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index 9aabe2091af0..f7301d03bb07 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -222,9 +222,11 @@ static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
+ static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
+ {
+ 	int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
++	int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
++	int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
+ 
+ 	return i2c_smbus_write_i2c_block_data(chip->client,
+-					      (reg << bank_shift) | REG_ADDR_AI,
++					      pinctrl | addr | REG_ADDR_AI,
+ 					      NBANK(chip), val);
+ }
+ 
+@@ -264,9 +266,11 @@ static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
+ static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
+ {
+ 	int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
++	int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
++	int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
+ 
+ 	return i2c_smbus_read_i2c_block_data(chip->client,
+-					     (reg << bank_shift) | REG_ADDR_AI,
++					     pinctrl | addr | REG_ADDR_AI,
+ 					     NBANK(chip), val);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1590-gpio-pca953x-Include-the-right-header.patch b/patches/1590-gpio-pca953x-Include-the-right-header.patch
new file mode 100644
index 00000000000000..bfc57c4c37e21b
--- /dev/null
+++ b/patches/1590-gpio-pca953x-Include-the-right-header.patch
@@ -0,0 +1,31 @@
+From 58ee3b8b4caeea230ef7f7fde3d0883dbae05b52 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 24 May 2018 14:26:20 +0200
+Subject: [PATCH 1590/1795] gpio: pca953x: Include the right header
+
+This is a GPIO driver, include only <linux/gpio/driver.h>.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 644f3da0b42aa299554c9c09a96d23c03957c6b0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/gpio/gpio-pca953x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index f7301d03bb07..587bb3e9e6c1 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -12,7 +12,7 @@
+  */
+ 
+ #include <linux/acpi.h>
+-#include <linux/gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/i2c.h>
+ #include <linux/init.h>
+-- 
+2.19.0
+
diff --git a/patches/1591-usb-xhci-Fix-memory-leak-in-xhci_endpoint_reset.patch b/patches/1591-usb-xhci-Fix-memory-leak-in-xhci_endpoint_reset.patch
new file mode 100644
index 00000000000000..3b77218529d065
--- /dev/null
+++ b/patches/1591-usb-xhci-Fix-memory-leak-in-xhci_endpoint_reset.patch
@@ -0,0 +1,34 @@
+From 4f2c667f7e1018bd8e411c469492ef4ffffb2aef Mon Sep 17 00:00:00 2001
+From: Zheng Xiaowei <zhengxiaowei@ruijie.com.cn>
+Date: Fri, 20 Jul 2018 18:05:11 +0300
+Subject: [PATCH 1591/1795] usb: xhci: Fix memory leak in xhci_endpoint_reset()
+
+If td_list is not empty the cfg_cmd will not be freed,
+call xhci_free_command to free it.
+
+Signed-off-by: Zheng Xiaowei <zhengxiaowei@ruijie.com.cn>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d89b7664f76047e7beca8f07e86f2ccfad085a28)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/host/xhci.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index f4e3db0826ef..21736f55e39c 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -3051,6 +3051,7 @@ static void xhci_endpoint_reset(struct usb_hcd *hcd,
+ 	if (!list_empty(&ep->ring->td_list)) {
+ 		dev_err(&udev->dev, "EP not empty, refuse reset\n");
+ 		spin_unlock_irqrestore(&xhci->lock, flags);
++		xhci_free_command(xhci, cfg_cmd);
+ 		goto cleanup;
+ 	}
+ 	xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
+-- 
+2.19.0
+
diff --git a/patches/1592-media-v4l-vsp1-Fix-deadlock-in-VSPDL-DRM-pipelines.patch b/patches/1592-media-v4l-vsp1-Fix-deadlock-in-VSPDL-DRM-pipelines.patch
new file mode 100644
index 00000000000000..dbab06845154c9
--- /dev/null
+++ b/patches/1592-media-v4l-vsp1-Fix-deadlock-in-VSPDL-DRM-pipelines.patch
@@ -0,0 +1,72 @@
+From 3d59169bdb54c2322a1c19f62dad601597c8116f Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Date: Fri, 27 Jul 2018 13:19:45 -0400
+Subject: [PATCH 1592/1795] media: v4l: vsp1: Fix deadlock in VSPDL DRM
+ pipelines
+
+The VSP uses a lock to protect the BRU and BRS assignment when
+configuring pipelines. The lock is taken in vsp1_du_atomic_begin() and
+released in vsp1_du_atomic_flush(), as well as taken and released in
+vsp1_du_setup_lif(). This guards against multiple pipelines trying to
+assign the same BRU and BRS at the same time.
+
+The DRM framework calls the .atomic_begin() operations in a loop over
+all CRTCs included in an atomic commit. On a VSPDL (the only VSP type
+where this matters), a single VSP instance handles two CRTCs, with a
+single lock. This results in a deadlock when the .atomic_begin()
+operation is called on the second CRTC.
+
+The DRM framework serializes atomic commits that affect the same CRTCs,
+but doesn't know about two CRTCs sharing the same VSPDL. Two commits
+affecting the VSPDL LIF0 and LIF1 respectively can thus race each other,
+hence the need for a lock.
+
+This could be fixed on the DRM side by forcing serialization of commits
+affecting CRTCs backed by the same VSPDL, but that would negatively
+affect performances, as the locking is only needed when the BRU and BRS
+need to be reassigned, which is an uncommon case.
+
+The lock protects the whole .atomic_begin() to .atomic_flush() sequence.
+The only operation that can occur in-between is vsp1_du_atomic_update(),
+which doesn't touch the BRU and BRS, and thus doesn't need to be
+protected by the lock. We can thus only take the lock around the
+pipeline setup calls in vsp1_du_atomic_flush(), which fixes the
+deadlock.
+
+Fixes: f81f9adc4ee1 ("media: v4l: vsp1: Assign BRU and BRS to pipelines dynamically")
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
+(cherry picked from commit 8eb0e6421958e9777db98448a4030d8ae940c9a0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/media/platform/vsp1/vsp1_drm.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c
+index edb35a5c57ea..a99fc0ced7a7 100644
+--- a/drivers/media/platform/vsp1/vsp1_drm.c
++++ b/drivers/media/platform/vsp1/vsp1_drm.c
+@@ -728,9 +728,6 @@ EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
+  */
+ void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
+ {
+-	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
+-
+-	mutex_lock(&vsp1->drm->lock);
+ }
+ EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
+ 
+@@ -846,6 +843,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
+ 
+ 	drm_pipe->crc = cfg->crc;
+ 
++	mutex_lock(&vsp1->drm->lock);
+ 	vsp1_du_pipeline_setup_inputs(vsp1, pipe);
+ 	vsp1_du_pipeline_configure(pipe);
+ 	mutex_unlock(&vsp1->drm->lock);
+-- 
+2.19.0
+
diff --git a/patches/1593-dt-bindings-gpio-rcar-Add-r8a77470-RZ-G1C-support.patch b/patches/1593-dt-bindings-gpio-rcar-Add-r8a77470-RZ-G1C-support.patch
new file mode 100644
index 00000000000000..9835885c385ef5
--- /dev/null
+++ b/patches/1593-dt-bindings-gpio-rcar-Add-r8a77470-RZ-G1C-support.patch
@@ -0,0 +1,36 @@
+From 708257b07ea7998c59a8409b965ad7648e01de38 Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Tue, 24 Apr 2018 09:27:05 +0100
+Subject: [PATCH 1593/1795] dt-bindings: gpio: rcar: Add r8a77470 (RZ/G1C)
+ support
+
+Renesas RZ/G1C (R8A77470) SoC GPIO blocks are identical to the R-Car Gen2
+family. Add support for its GPIO controllers.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 856ac1d26b5d64fcf3b9d6d889ec1a61fd745a8e)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index 9474138d776e..bd2b80296626 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -5,6 +5,7 @@ Required Properties:
+   - compatible: should contain one or more of the following:
+     - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+     - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
++    - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller.
+     - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
+     - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
+     - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/1594-dt-bindings-gpio-Add-support-for-r8a77965.patch b/patches/1594-dt-bindings-gpio-Add-support-for-r8a77965.patch
new file mode 100644
index 00000000000000..2e5e3d1868c351
--- /dev/null
+++ b/patches/1594-dt-bindings-gpio-Add-support-for-r8a77965.patch
@@ -0,0 +1,34 @@
+From 86efba5e51a7346cd04338bd5c1e858aaf3cbdb5 Mon Sep 17 00:00:00 2001
+From: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Date: Mon, 16 Apr 2018 20:55:56 +0200
+Subject: [PATCH 1594/1795] dt-bindings: gpio: Add support for r8a77965
+
+Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.
+
+Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 537a1dc10fa09b1e51555feef912de498e6ff9de)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index bd2b80296626..9744d422d52e 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -15,6 +15,7 @@ Required Properties:
+     - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
+     - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
+     - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
++    - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller.
+     - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
+     - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
+     - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/1595-gpio-rcar-Add-DT-binding-for-r8a77990.patch b/patches/1595-gpio-rcar-Add-DT-binding-for-r8a77990.patch
new file mode 100644
index 00000000000000..13aea0b15bc2d2
--- /dev/null
+++ b/patches/1595-gpio-rcar-Add-DT-binding-for-r8a77990.patch
@@ -0,0 +1,32 @@
+From 2cb73a6582bd47cb4200c3ae00cf0b6666b7bfda Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 11 May 2018 12:13:05 +0900
+Subject: [PATCH 1595/1795] gpio: rcar: Add DT binding for r8a77990
+
+Add compatible string for R-Car E3 (r8a77990) in gpio-rcar.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit c65ef0ced1da5a323c3d6d251aef911943a53479)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+index 9744d422d52e..378f1322211e 100644
+--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
++++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+@@ -17,6 +17,7 @@ Required Properties:
+     - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
+     - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller.
+     - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
++    - "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO controller.
+     - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
+     - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+     - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+-- 
+2.19.0
+
diff --git a/patches/1596-clk-renesas-r8a77965-Add-MSIOF-controller-clocks.patch b/patches/1596-clk-renesas-r8a77965-Add-MSIOF-controller-clocks.patch
new file mode 100644
index 00000000000000..08e4e68e0113a2
--- /dev/null
+++ b/patches/1596-clk-renesas-r8a77965-Add-MSIOF-controller-clocks.patch
@@ -0,0 +1,35 @@
+From 2d7a37327007bfa848c5eb4cdbc6e9b7bf4cc6af Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 14 Dec 2017 22:34:07 +0900
+Subject: [PATCH 1596/1795] clk: renesas: r8a77965: Add MSIOF controller clocks
+
+This patch adds MSIOF{0,1,2,3} clocks to the R8A77965 SoC.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit cdc749e22925d5b370cb51ace3cace940bd76cb5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+index b1acfb60351c..8fae5e9c4a77 100644
+--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
+@@ -116,6 +116,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ 	DEF_MOD("scif3",		204,	R8A77965_CLK_S3D4),
+ 	DEF_MOD("scif1",		206,	R8A77965_CLK_S3D4),
+ 	DEF_MOD("scif0",		207,	R8A77965_CLK_S3D4),
++	DEF_MOD("msiof3",		208,	R8A77965_CLK_MSO),
++	DEF_MOD("msiof2",		209,	R8A77965_CLK_MSO),
++	DEF_MOD("msiof1",		210,	R8A77965_CLK_MSO),
++	DEF_MOD("msiof0",		211,	R8A77965_CLK_MSO),
+ 	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S0D3),
+ 	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S0D3),
+ 	DEF_MOD("sys-dmac0",		219,	R8A77965_CLK_S0D3),
+-- 
+2.19.0
+
diff --git a/patches/1597-clk-renesas-Add-r8a77470-CPG-Core-Clock-Definitions.patch b/patches/1597-clk-renesas-Add-r8a77470-CPG-Core-Clock-Definitions.patch
new file mode 100644
index 00000000000000..a827ca3a785867
--- /dev/null
+++ b/patches/1597-clk-renesas-Add-r8a77470-CPG-Core-Clock-Definitions.patch
@@ -0,0 +1,68 @@
+From bcd89712fc25251be5b4975f889c590d4f4592ab Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 28 Mar 2018 20:26:11 +0100
+Subject: [PATCH 1597/1795] clk: renesas: Add r8a77470 CPG Core Clock
+ Definitions
+
+Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
+Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
+Manual.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+[geert: Use consecutive numbering]
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 343e64a6c48a6c86552db945d842283eee9f528b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/clock/r8a77470-cpg-mssr.h | 36 +++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+ create mode 100644 include/dt-bindings/clock/r8a77470-cpg-mssr.h
+
+diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
+new file mode 100644
+index 000000000000..34cba49d0f84
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
+@@ -0,0 +1,36 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a77470 CPG Core Clocks */
++#define R8A77470_CLK_Z2		0
++#define R8A77470_CLK_ZTR	1
++#define R8A77470_CLK_ZTRD2	2
++#define R8A77470_CLK_ZT		3
++#define R8A77470_CLK_ZX		4
++#define R8A77470_CLK_ZS		5
++#define R8A77470_CLK_HP		6
++#define R8A77470_CLK_B		7
++#define R8A77470_CLK_LB		8
++#define R8A77470_CLK_P		9
++#define R8A77470_CLK_CL		10
++#define R8A77470_CLK_CP		11
++#define R8A77470_CLK_M2		12
++#define R8A77470_CLK_ZB3	13
++#define R8A77470_CLK_SDH	14
++#define R8A77470_CLK_SD0	15
++#define R8A77470_CLK_SD1	16
++#define R8A77470_CLK_SD2	17
++#define R8A77470_CLK_MP		18
++#define R8A77470_CLK_QSPI	19
++#define R8A77470_CLK_CPEX	20
++#define R8A77470_CLK_RCAN	21
++#define R8A77470_CLK_R		22
++#define R8A77470_CLK_OSC	23
++
++#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1598-clk-renesas-cpg-mssr-Add-r8a77470-support.patch b/patches/1598-clk-renesas-cpg-mssr-Add-r8a77470-support.patch
new file mode 100644
index 00000000000000..95e4ce4d0f5188
--- /dev/null
+++ b/patches/1598-clk-renesas-cpg-mssr-Add-r8a77470-support.patch
@@ -0,0 +1,397 @@
+From 7913bfcfb6db49f9845db4dfda5edbb423e34e9c Mon Sep 17 00:00:00 2001
+From: Biju Das <biju.das@bp.renesas.com>
+Date: Wed, 28 Mar 2018 20:26:12 +0100
+Subject: [PATCH 1598/1795] clk: renesas: cpg-mssr: Add r8a77470 support
+
+Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software
+Reset support.
+
+Signed-off-by: Biju Das <biju.das@bp.renesas.com>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 5bf2fbbef50ca521ade4d4fbd366e9273743c503)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/renesas,cpg-mssr.txt       |   9 +-
+ drivers/clk/renesas/Kconfig                   |   5 +
+ drivers/clk/renesas/Makefile                  |   1 +
+ drivers/clk/renesas/r8a77470-cpg-mssr.c       | 229 ++++++++++++++++++
+ drivers/clk/renesas/rcar-gen2-cpg.c           |  12 +
+ drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
+ 7 files changed, 260 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/clk/renesas/r8a77470-cpg-mssr.c
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+index 773a5226342f..c3473df23abb 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+@@ -15,6 +15,7 @@ Required Properties:
+   - compatible: Must be one of:
+       - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
+       - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
++      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
+       - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
+       - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
+       - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
+@@ -33,10 +34,12 @@ Required Properties:
+   - clocks: References to external parent clocks, one entry for each entry in
+     clock-names
+   - clock-names: List of external parent clock names. Valid names are:
+-      - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+-		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
++      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
++		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
++		 r8a77980, r8a77995)
+       - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
+-      - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
++      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
++		     r8a7794)
+ 
+   - #clock-cells: Must be 2
+       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index ef76c861ec84..f32896fa9dda 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -7,6 +7,7 @@ config CLK_RENESAS
+ 	select CLK_R8A7740 if ARCH_R8A7740
+ 	select CLK_R8A7743 if ARCH_R8A7743
+ 	select CLK_R8A7745 if ARCH_R8A7745
++	select CLK_R8A77470 if ARCH_R8A77470
+ 	select CLK_R8A7778 if ARCH_R8A7778
+ 	select CLK_R8A7779 if ARCH_R8A7779
+ 	select CLK_R8A7790 if ARCH_R8A7790
+@@ -60,6 +61,10 @@ config CLK_R8A7745
+ 	bool "RZ/G1E clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN2_CPG
+ 
++config CLK_R8A77470
++	bool "RZ/G1C clock support" if COMPILE_TEST
++	select CLK_RCAR_GEN2_CPG
++
+ config CLK_R8A7778
+ 	bool "R-Car M1A clock support" if COMPILE_TEST
+ 	select CLK_RENESAS_CPG_MSTP
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index 6c0f19636e3e..a4edea99c4ec 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4)		+= clk-r8a73a4.o
+ obj-$(CONFIG_CLK_R8A7740)		+= clk-r8a7740.o
+ obj-$(CONFIG_CLK_R8A7743)		+= r8a7743-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7745)		+= r8a7745-cpg-mssr.o
++obj-$(CONFIG_CLK_R8A77470)		+= r8a77470-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A7778)		+= clk-r8a7778.o
+ obj-$(CONFIG_CLK_R8A7779)		+= clk-r8a7779.o
+ obj-$(CONFIG_CLK_R8A7790)		+= r8a7790-cpg-mssr.o
+diff --git a/drivers/clk/renesas/r8a77470-cpg-mssr.c b/drivers/clk/renesas/r8a77470-cpg-mssr.c
+new file mode 100644
+index 000000000000..ab0fb10b6bf0
+--- /dev/null
++++ b/drivers/clk/renesas/r8a77470-cpg-mssr.c
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * r8a77470 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++
++#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen2-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++	CLK_USB_EXTAL,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL0,
++	CLK_PLL1,
++	CLK_PLL3,
++	CLK_PLL1_DIV2,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",	CLK_EXTAL),
++	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
++	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
++	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
++	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
++
++	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
++
++	/* Core Clock Outputs */
++	DEF_BASE("sdh",  R8A77470_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
++	DEF_BASE("sd0",  R8A77470_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
++	DEF_BASE("sd1",  R8A77470_CLK_SD1,  CLK_TYPE_GEN2_SD1,	CLK_PLL1),
++	DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
++	DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
++
++	DEF_FIXED("z2",    R8A77470_CLK_Z2,	CLK_PLL0,	    1, 1),
++	DEF_FIXED("zx",    R8A77470_CLK_ZX,	CLK_PLL1,	    3, 1),
++	DEF_FIXED("zs",    R8A77470_CLK_ZS,	CLK_PLL1,	    6, 1),
++	DEF_FIXED("hp",    R8A77470_CLK_HP,	CLK_PLL1,	   12, 1),
++	DEF_FIXED("b",     R8A77470_CLK_B,	CLK_PLL1,	   12, 1),
++	DEF_FIXED("lb",	   R8A77470_CLK_LB,     CLK_PLL1,	   24, 1),
++	DEF_FIXED("p",     R8A77470_CLK_P,	CLK_PLL1,	   24, 1),
++	DEF_FIXED("cl",    R8A77470_CLK_CL,	CLK_PLL1,	   48, 1),
++	DEF_FIXED("cp",    R8A77470_CLK_CP,	CLK_PLL1,	   48, 1),
++	DEF_FIXED("m2",    R8A77470_CLK_M2,	CLK_PLL1,	    8, 1),
++	DEF_FIXED("zb3",   R8A77470_CLK_ZB3,	CLK_PLL3,	    4, 1),
++	DEF_FIXED("mp",    R8A77470_CLK_MP,	CLK_PLL1_DIV2,	   15, 1),
++	DEF_FIXED("cpex",  R8A77470_CLK_CPEX,	CLK_EXTAL,	    2, 1),
++	DEF_FIXED("r",     R8A77470_CLK_R,	CLK_PLL1,	49152, 1),
++	DEF_FIXED("osc",   R8A77470_CLK_OSC,	CLK_PLL1,	12288, 1),
++
++	DEF_DIV6P1("sd2",  R8A77470_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
++};
++
++static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
++	DEF_MOD("msiof0",		   0,	R8A77470_CLK_MP),
++	DEF_MOD("vcp0",			 101,	R8A77470_CLK_ZS),
++	DEF_MOD("vpc0",			 103,	R8A77470_CLK_ZS),
++	DEF_MOD("tmu1",			 111,	R8A77470_CLK_P),
++	DEF_MOD("3dg",			 112,	R8A77470_CLK_ZS),
++	DEF_MOD("2d-dmac",		 115,	R8A77470_CLK_ZS),
++	DEF_MOD("fdp1-0",		 119,	R8A77470_CLK_ZS),
++	DEF_MOD("tmu3",			 121,	R8A77470_CLK_P),
++	DEF_MOD("tmu2",			 122,	R8A77470_CLK_P),
++	DEF_MOD("cmt0",			 124,	R8A77470_CLK_R),
++	DEF_MOD("vsp1du0",		 128,	R8A77470_CLK_ZS),
++	DEF_MOD("vsp1-sy",		 131,	R8A77470_CLK_ZS),
++	DEF_MOD("msiof2",		 205,	R8A77470_CLK_MP),
++	DEF_MOD("msiof1",		 208,	R8A77470_CLK_MP),
++	DEF_MOD("sys-dmac1",		 218,	R8A77470_CLK_ZS),
++	DEF_MOD("sys-dmac0",		 219,	R8A77470_CLK_ZS),
++	DEF_MOD("sdhi2",		 312,	R8A77470_CLK_SD2),
++	DEF_MOD("sdhi1",		 313,	R8A77470_CLK_SD1),
++	DEF_MOD("sdhi0",		 314,	R8A77470_CLK_SD0),
++	DEF_MOD("usbhs-dmac0-ch1",	 326,	R8A77470_CLK_HP),
++	DEF_MOD("usbhs-dmac1-ch1",	 327,	R8A77470_CLK_HP),
++	DEF_MOD("cmt1",			 329,	R8A77470_CLK_R),
++	DEF_MOD("usbhs-dmac0-ch0",	 330,	R8A77470_CLK_HP),
++	DEF_MOD("usbhs-dmac1-ch0",	 331,	R8A77470_CLK_HP),
++	DEF_MOD("rwdt",			 402,	R8A77470_CLK_R),
++	DEF_MOD("irqc",			 407,	R8A77470_CLK_CP),
++	DEF_MOD("intc-sys",		 408,	R8A77470_CLK_ZS),
++	DEF_MOD("audio-dmac0",		 502,	R8A77470_CLK_HP),
++	DEF_MOD("pwm",			 523,	R8A77470_CLK_P),
++	DEF_MOD("usb-ehci-0",		 703,	R8A77470_CLK_MP),
++	DEF_MOD("usbhs-0",		 704,	R8A77470_CLK_HP),
++	DEF_MOD("usb-ehci-1",		 705,	R8A77470_CLK_MP),
++	DEF_MOD("usbhs-1",		 706,	R8A77470_CLK_HP),
++	DEF_MOD("hscif2",		 713,	R8A77470_CLK_ZS),
++	DEF_MOD("scif5",		 714,	R8A77470_CLK_P),
++	DEF_MOD("scif4",		 715,	R8A77470_CLK_P),
++	DEF_MOD("hscif1",		 716,	R8A77470_CLK_ZS),
++	DEF_MOD("hscif0",		 717,	R8A77470_CLK_ZS),
++	DEF_MOD("scif3",		 718,	R8A77470_CLK_P),
++	DEF_MOD("scif2",		 719,	R8A77470_CLK_P),
++	DEF_MOD("scif1",		 720,	R8A77470_CLK_P),
++	DEF_MOD("scif0",		 721,	R8A77470_CLK_P),
++	DEF_MOD("du1",			 723,	R8A77470_CLK_ZX),
++	DEF_MOD("du0",			 724,	R8A77470_CLK_ZX),
++	DEF_MOD("ipmmu-sgx",		 800,	R8A77470_CLK_ZX),
++	DEF_MOD("etheravb",		 812,	R8A77470_CLK_HP),
++	DEF_MOD("ether",		 813,	R8A77470_CLK_P),
++	DEF_MOD("gpio5",		 907,	R8A77470_CLK_CP),
++	DEF_MOD("gpio4",		 908,	R8A77470_CLK_CP),
++	DEF_MOD("gpio3",		 909,	R8A77470_CLK_CP),
++	DEF_MOD("gpio2",		 910,	R8A77470_CLK_CP),
++	DEF_MOD("gpio1",		 911,	R8A77470_CLK_CP),
++	DEF_MOD("gpio0",		 912,	R8A77470_CLK_CP),
++	DEF_MOD("can1",			 915,	R8A77470_CLK_P),
++	DEF_MOD("can0",			 916,	R8A77470_CLK_P),
++	DEF_MOD("qspi_mod-1",		 917,	R8A77470_CLK_QSPI),
++	DEF_MOD("qspi_mod-0",		 918,	R8A77470_CLK_QSPI),
++	DEF_MOD("i2c4",			 927,	R8A77470_CLK_HP),
++	DEF_MOD("i2c3",			 928,	R8A77470_CLK_HP),
++	DEF_MOD("i2c2",			 929,	R8A77470_CLK_HP),
++	DEF_MOD("i2c1",			 930,	R8A77470_CLK_HP),
++	DEF_MOD("i2c0",			 931,	R8A77470_CLK_HP),
++	DEF_MOD("ssi-all",		1005,	R8A77470_CLK_P),
++	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
++	DEF_MOD("scu-all",		1017,	R8A77470_CLK_P),
++	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
++};
++
++static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(402),	/* RWDT */
++	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
++};
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ *    MD	EXTAL		PLL0	PLL1	PLL3
++ * 14 13	(MHz)		*1	*2
++ *---------------------------------------------------
++ * 0  0		20		x80	x78	x50
++ * 0  1		26		x60	x60	x56
++ * 1  0		Prohibitted setting
++ * 1  1		30		x52	x52	x50
++ *
++ * *1 :	Table 7.4 indicates VCO output (PLL0 = VCO)
++ * *2 :	Table 7.4 indicates VCO output (PLL1 = VCO)
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
++					 (((md) & BIT(13)) >> 13))
++
++static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
++	/* EXTAL div	PLL1 mult x2	PLL3 mult */
++	{ 1,		156,		50,	},
++	{ 1,		120,		56,	},
++	{ /* Invalid*/				},
++	{ 1,		104,		50,	},
++};
++
++static int __init r8a77470_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++
++	return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
++}
++
++const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks = r8a77470_core_clks,
++	.num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
++	.last_dt_core_clk = LAST_DT_CORE_CLK,
++	.num_total_core_clks = MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks = r8a77470_mod_clks,
++	.num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
++	.num_hw_mod_clks = 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks = r8a77470_crit_mod_clks,
++	.num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
++
++	/* Callbacks */
++	.init = r8a77470_cpg_mssr_init,
++	.cpg_clk_register = rcar_gen2_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
+index feb14579a71b..0c49f59d5074 100644
+--- a/drivers/clk/renesas/rcar-gen2-cpg.c
++++ b/drivers/clk/renesas/rcar-gen2-cpg.c
+@@ -16,6 +16,7 @@
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/slab.h>
++#include <linux/sys_soc.h>
+ 
+ #include "renesas-cpg-mssr.h"
+ #include "rcar-gen2-cpg.h"
+@@ -261,6 +262,11 @@ static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
+ static unsigned int cpg_pll0_div __initdata;
+ static u32 cpg_mode __initdata;
+ 
++static const struct soc_device_attribute soc_r8a77470[] = {
++	{ .soc_id = "r8a77470" },
++	{ /* sentinel */ }
++};
++
+ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+ 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+ 	struct clk **clks, void __iomem *base,
+@@ -327,11 +333,17 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+ 
+ 	case CLK_TYPE_GEN2_SD0:
+ 		table = cpg_sd01_div_table;
++		if (soc_device_match(soc_r8a77470))
++			table++;
++
+ 		shift = 4;
+ 		break;
+ 
+ 	case CLK_TYPE_GEN2_SD1:
+ 		table = cpg_sd01_div_table;
++		if (soc_device_match(soc_r8a77470))
++			table++;
++
+ 		shift = 0;
+ 		break;
+ 
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 69a7c756658b..3ddd6208df4e 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -653,6 +653,12 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a7745_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_CLK_R8A77470
++	{
++		.compatible = "renesas,r8a77470-cpg-mssr",
++		.data = &r8a77470_cpg_mssr_info,
++	},
++#endif
+ #ifdef CONFIG_CLK_R8A7790
+ 	{
+ 		.compatible = "renesas,r8a7790-cpg-mssr",
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index 97ccb093c10f..efe2a149acce 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -133,6 +133,7 @@ struct cpg_mssr_info {
+ 
+ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
+-- 
+2.19.0
+
diff --git a/patches/1599-clk-renesas-r8a7743-Fix-LB-clock-divider.patch b/patches/1599-clk-renesas-r8a7743-Fix-LB-clock-divider.patch
new file mode 100644
index 00000000000000..e4abf7526baceb
--- /dev/null
+++ b/patches/1599-clk-renesas-r8a7743-Fix-LB-clock-divider.patch
@@ -0,0 +1,44 @@
+From bf3d01120d291bb1915d05ff133a62bfb0c023ce Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 10:59:14 +0200
+Subject: [PATCH 1599/1795] clk: renesas: r8a7743: Fix LB clock divider
+
+The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
+the LB clock divider depends on the value of the MD18 pin.
+
+On RZ/G1M, the LB clock divider is fixed to 24.  Hence model the clock
+as a fixed factor clock instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 2c2557e3901e861c78020a3bb202dffc264119cf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
+index d3c8b1e2969f..011c170ec3f9 100644
+--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
+@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+ 
+ 	/* Core Clock Outputs */
+ 	DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,	CLK_PLL0),
+-	DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+ 	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+ 	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+ 	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+ 	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),
+ 	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),
+ 	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),
++	DEF_FIXED("lb",    R8A7743_CLK_LB,	CLK_PLL1,	   24, 1),
+ 	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),
+ 	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),
+ 	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),
+-- 
+2.19.0
+
diff --git a/patches/1600-clk-renesas-r8a7745-Fix-LB-clock-divider.patch b/patches/1600-clk-renesas-r8a7745-Fix-LB-clock-divider.patch
new file mode 100644
index 00000000000000..020cbb11ef236b
--- /dev/null
+++ b/patches/1600-clk-renesas-r8a7745-Fix-LB-clock-divider.patch
@@ -0,0 +1,44 @@
+From 3b04309dcf01feb55fa9ce705c9edb7445ff73f8 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 11:01:47 +0200
+Subject: [PATCH 1600/1795] clk: renesas: r8a7745: Fix LB clock divider
+
+The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
+the LB clock divider depends on the value of the MD18 pin.
+
+On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
+as a fixed factor clock instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 83fab8ea62ca74eaa51613ba8eeaf925f4f8087c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+index 87f5a3619e4f..4b0a9243b748 100644
+--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
+ 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ 
+ 	/* Core Clock Outputs */
+-	DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+ 	DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+ 	DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+ 	DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
+ 	DEF_FIXED("zs",    R8A7745_CLK_ZS,	CLK_PLL1,	    6, 1),
+ 	DEF_FIXED("hp",    R8A7745_CLK_HP,	CLK_PLL1,	   12, 1),
+ 	DEF_FIXED("b",     R8A7745_CLK_B,	CLK_PLL1,	   12, 1),
++	DEF_FIXED("lb",    R8A7745_CLK_LB,	CLK_PLL1,	   24, 1),
+ 	DEF_FIXED("p",     R8A7745_CLK_P,	CLK_PLL1,	   24, 1),
+ 	DEF_FIXED("cl",    R8A7745_CLK_CL,	CLK_PLL1,	   48, 1),
+ 	DEF_FIXED("cp",    R8A7745_CLK_CP,	CLK_PLL1,	   48, 1),
+-- 
+2.19.0
+
diff --git a/patches/1601-clk-renesas-r8a7791-r8a7793-Fix-LB-clock-divider.patch b/patches/1601-clk-renesas-r8a7791-r8a7793-Fix-LB-clock-divider.patch
new file mode 100644
index 00000000000000..58cdb24524bb68
--- /dev/null
+++ b/patches/1601-clk-renesas-r8a7791-r8a7793-Fix-LB-clock-divider.patch
@@ -0,0 +1,44 @@
+From 3c54e187d03e0a96df8e7c4abff76d1a4d7ea9f7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 11:02:18 +0200
+Subject: [PATCH 1601/1795] clk: renesas: r8a7791/r8a7793: Fix LB clock divider
+
+The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
+the LB clock divider depends on the value of the MD18 pin.
+
+On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
+model the clock as a fixed factor clock instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 6041ce57f2c8c231017a1b4f7a71b606bb1c1016)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
+index 820b220b09cc..1b91f03b7598 100644
+--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
+@@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
+ 
+ 	/* Core Clock Outputs */
+ 	DEF_BASE("z",    R8A7791_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
+-	DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
+ 	DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ 	DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
+ 	DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
+@@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
+ 	DEF_FIXED("hp",     R8A7791_CLK_HP,    CLK_PLL1,         12, 1),
+ 	DEF_FIXED("i",      R8A7791_CLK_I,     CLK_PLL1,          2, 1),
+ 	DEF_FIXED("b",      R8A7791_CLK_B,     CLK_PLL1,         12, 1),
++	DEF_FIXED("lb",     R8A7791_CLK_LB,    CLK_PLL1,         24, 1),
+ 	DEF_FIXED("p",      R8A7791_CLK_P,     CLK_PLL1,         24, 1),
+ 	DEF_FIXED("cl",     R8A7791_CLK_CL,    CLK_PLL1,         48, 1),
+ 	DEF_FIXED("m2",     R8A7791_CLK_M2,    CLK_PLL1,          8, 1),
+-- 
+2.19.0
+
diff --git a/patches/1602-clk-renesas-r8a7792-Fix-LB-clock-divider.patch b/patches/1602-clk-renesas-r8a7792-Fix-LB-clock-divider.patch
new file mode 100644
index 00000000000000..a18806300df796
--- /dev/null
+++ b/patches/1602-clk-renesas-r8a7792-Fix-LB-clock-divider.patch
@@ -0,0 +1,44 @@
+From a2c2896e9cf43c5b1332057b6552656466c691c1 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 11:02:42 +0200
+Subject: [PATCH 1602/1795] clk: renesas: r8a7792: Fix LB clock divider
+
+The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
+the LB clock divider depends on the value of the MD18 pin.
+
+On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
+clock as a fixed factor clock instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 0873305e68ac2a4665f1f3d27bb0b98a4312e5bd)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
+index 609a54080496..493e07859f5f 100644
+--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
+@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+ 	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ 
+ 	/* Core Clock Outputs */
+-	DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
+ 	DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ 
+ 	DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
+@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+ 	DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
+ 	DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
+ 	DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
++	DEF_FIXED("lb",     R8A7792_CLK_LB,    CLK_PLL1,         24, 1),
+ 	DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
+ 	DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
+ 	DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
+-- 
+2.19.0
+
diff --git a/patches/1603-clk-renesas-r8a7794-Fix-LB-clock-divider.patch b/patches/1603-clk-renesas-r8a7794-Fix-LB-clock-divider.patch
new file mode 100644
index 00000000000000..819ca160942987
--- /dev/null
+++ b/patches/1603-clk-renesas-r8a7794-Fix-LB-clock-divider.patch
@@ -0,0 +1,44 @@
+From 7b49510bee7492225c373452af27dcec83548f8f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 11:03:00 +0200
+Subject: [PATCH 1603/1795] clk: renesas: r8a7794: Fix LB clock divider
+
+The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
+the LB clock divider depends on the value of the MD18 pin.
+
+On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
+as a fixed factor clock instead.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
+(cherry picked from commit 279ebbcae5a1298433c1b4f9425c89897d017cc0)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
+index 2a40bbeaeeaf..088f4b79fdfc 100644
+--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
+@@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+ 	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ 
+ 	/* Core Clock Outputs */
+-	DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
+ 	DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ 	DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
+ 	DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
+@@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+ 	DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
+ 	DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
+ 	DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
++	DEF_FIXED("lb",     R8A7794_CLK_LB,    CLK_PLL1,         24, 1),
+ 	DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
+ 	DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
+ 	DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
+-- 
+2.19.0
+
diff --git a/patches/1604-clk-renesas-r8a77980-Correct-parent-clock-of-PCIEC0.patch b/patches/1604-clk-renesas-r8a77980-Correct-parent-clock-of-PCIEC0.patch
new file mode 100644
index 00000000000000..d3a2ca6082776d
--- /dev/null
+++ b/patches/1604-clk-renesas-r8a77980-Correct-parent-clock-of-PCIEC0.patch
@@ -0,0 +1,36 @@
+From bbd7f9729e4492600434d9fb2c1153b9735780f5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 9 Apr 2018 13:50:41 +0200
+Subject: [PATCH 1604/1795] clk: renesas: r8a77980: Correct parent clock of
+ PCIEC0
+
+According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
+December 22, 2017, the parent clock of the PCIe module clock on R-Car
+V3H is S2D2.
+
+Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit 246e232437e5a045792aee95b2f9c7718516596c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/r8a77980-cpg-mssr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
+index 7aaae73a321a..d7ebd9ec0059 100644
+--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
+@@ -116,7 +116,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
+ 	DEF_MOD("sys-dmac1",		 218,	R8A77980_CLK_S0D3),
+ 	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),
+ 	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),
+-	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S3D1),
++	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S2D2),
+ 	DEF_MOD("intc-ex",		 407,	R8A77980_CLK_CP),
+ 	DEF_MOD("intc-ap",		 408,	R8A77980_CLK_S0D3),
+ 	DEF_MOD("hscif3",		 517,	R8A77980_CLK_S3D1),
+-- 
+2.19.0
+
diff --git a/patches/1605-clk-renesas-rcar-gen2-Centralize-quirks-handling.patch b/patches/1605-clk-renesas-rcar-gen2-Centralize-quirks-handling.patch
new file mode 100644
index 00000000000000..917cf28be73fd3
--- /dev/null
+++ b/patches/1605-clk-renesas-rcar-gen2-Centralize-quirks-handling.patch
@@ -0,0 +1,82 @@
+From 50464d8b237b30683ce1938c112b6ea061a43238 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 29 Mar 2018 10:56:56 +0200
+Subject: [PATCH 1605/1795] clk: renesas: rcar-gen2: Centralize quirks handling
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Introduce centralized quirks handling like on R-Car Gen3, and convert
+the RZ/G1C SD clock table handling over to it.
+
+This makes it easier to add more quirks later, if/when needed.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Reviewed-by: Biju Das <biju.das@bp.renesas.com>
+(cherry picked from commit a34f778cb89a8554a5d1f5a75b297c07c672afce)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/renesas/rcar-gen2-cpg.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
+index 0c49f59d5074..daf88bc2cdae 100644
+--- a/drivers/clk/renesas/rcar-gen2-cpg.c
++++ b/drivers/clk/renesas/rcar-gen2-cpg.c
+@@ -261,9 +261,15 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
+ static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
+ static unsigned int cpg_pll0_div __initdata;
+ static u32 cpg_mode __initdata;
++static u32 cpg_quirks __initdata;
+ 
+-static const struct soc_device_attribute soc_r8a77470[] = {
+-	{ .soc_id = "r8a77470" },
++#define SD_SKIP_FIRST	BIT(0)		/* Skip first clock in SD table */
++
++static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
++	{
++		.soc_id = "r8a77470",
++		.data = (void *)SD_SKIP_FIRST,
++	},
+ 	{ /* sentinel */ }
+ };
+ 
+@@ -333,7 +339,7 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+ 
+ 	case CLK_TYPE_GEN2_SD0:
+ 		table = cpg_sd01_div_table;
+-		if (soc_device_match(soc_r8a77470))
++		if (cpg_quirks & SD_SKIP_FIRST)
+ 			table++;
+ 
+ 		shift = 4;
+@@ -341,7 +347,7 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+ 
+ 	case CLK_TYPE_GEN2_SD1:
+ 		table = cpg_sd01_div_table;
+-		if (soc_device_match(soc_r8a77470))
++		if (cpg_quirks & SD_SKIP_FIRST)
+ 			table++;
+ 
+ 		shift = 0;
+@@ -372,9 +378,15 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
+ int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
+ 			      unsigned int pll0_div, u32 mode)
+ {
++	const struct soc_device_attribute *attr;
++
+ 	cpg_pll_config = config;
+ 	cpg_pll0_div = pll0_div;
+ 	cpg_mode = mode;
++	attr = soc_device_match(cpg_quirks_match);
++	if (attr)
++		cpg_quirks = (uintptr_t)attr->data;
++	pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
+ 
+ 	spin_lock_init(&cpg_lock);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1606-clk-renesas-Add-r8a77990-CPG-Core-Clock-Definitions.patch b/patches/1606-clk-renesas-Add-r8a77990-CPG-Core-Clock-Definitions.patch
new file mode 100644
index 00000000000000..fe45b9e1cb4d45
--- /dev/null
+++ b/patches/1606-clk-renesas-Add-r8a77990-CPG-Core-Clock-Definitions.patch
@@ -0,0 +1,96 @@
+From 43dcc230b4a1af6042295898b0be0264afc6d2db Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 20 Apr 2018 21:27:43 +0900
+Subject: [PATCH 1606/1795] clk: renesas: Add r8a77990 CPG Core Clock
+ Definitions
+
+This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
+
+Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not
+included, as they are used as internal clock sources only, and never
+referenced from DT.
+
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+[shimoda: add SPDX-License-Identifier]
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+(cherry picked from commit 9a31fa395c19d5873190bf84c8192f5799861342)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/dt-bindings/clock/r8a77990-cpg-mssr.h | 62 +++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+ create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h
+
+diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
+new file mode 100644
+index 000000000000..a596a482f3a9
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
+@@ -0,0 +1,62 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a77990 CPG Core Clocks */
++#define R8A77990_CLK_Z2			0
++#define R8A77990_CLK_ZR			1
++#define R8A77990_CLK_ZG			2
++#define R8A77990_CLK_ZTR		3
++#define R8A77990_CLK_ZT			4
++#define R8A77990_CLK_ZX			5
++#define R8A77990_CLK_S0D1		6
++#define R8A77990_CLK_S0D3		7
++#define R8A77990_CLK_S0D6		8
++#define R8A77990_CLK_S0D12		9
++#define R8A77990_CLK_S0D24		10
++#define R8A77990_CLK_S1D1		11
++#define R8A77990_CLK_S1D2		12
++#define R8A77990_CLK_S1D4		13
++#define R8A77990_CLK_S2D1		14
++#define R8A77990_CLK_S2D2		15
++#define R8A77990_CLK_S2D4		16
++#define R8A77990_CLK_S3D1		17
++#define R8A77990_CLK_S3D2		18
++#define R8A77990_CLK_S3D4		19
++#define R8A77990_CLK_S0D6C		20
++#define R8A77990_CLK_S3D1C		21
++#define R8A77990_CLK_S3D2C		22
++#define R8A77990_CLK_S3D4C		23
++#define R8A77990_CLK_LB			24
++#define R8A77990_CLK_CL			25
++#define R8A77990_CLK_ZB3		26
++#define R8A77990_CLK_ZB3D2		27
++#define R8A77990_CLK_CR			28
++#define R8A77990_CLK_CRD2		29
++#define R8A77990_CLK_SD0H		30
++#define R8A77990_CLK_SD0		31
++#define R8A77990_CLK_SD1H		32
++#define R8A77990_CLK_SD1		33
++#define R8A77990_CLK_SD3H		34
++#define R8A77990_CLK_SD3		35
++#define R8A77990_CLK_RPC		36
++#define R8A77990_CLK_RPCD2		37
++#define R8A77990_CLK_ZA2		38
++#define R8A77990_CLK_ZA8		39
++#define R8A77990_CLK_Z2D		40
++#define R8A77990_CLK_CANFD		41
++#define R8A77990_CLK_MSO		42
++#define R8A77990_CLK_R			43
++#define R8A77990_CLK_OSC		44
++#define R8A77990_CLK_LV0		45
++#define R8A77990_CLK_LV1		46
++#define R8A77990_CLK_CSI0		47
++#define R8A77990_CLK_CP			48
++#define R8A77990_CLK_CPEX		49
++
++#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
+-- 
+2.19.0
+
diff --git a/patches/1607-clk-renesas-cpg-mssr-Add-support-for-R-Car-E3.patch b/patches/1607-clk-renesas-cpg-mssr-Add-support-for-R-Car-E3.patch
new file mode 100644
index 00000000000000..9c78feccc319fa
--- /dev/null
+++ b/patches/1607-clk-renesas-cpg-mssr-Add-support-for-R-Car-E3.patch
@@ -0,0 +1,411 @@
+From 198389956bf1d492c6c98f53ad87480a9ffa4def Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 20 Apr 2018 21:27:44 +0900
+Subject: [PATCH 1607/1795] clk: renesas: cpg-mssr: Add support for R-Car E3
+
+Initial support for R-Car E3 (r8a77990), including core and module
+clocks.
+
+Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
+Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".
+
+Inspried by patches by Takeshi Kihara in the BSP.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+(cherry picked from commit 3570a2af473789c5d5f5b9e04f72295102967824)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/renesas,cpg-mssr.txt       |   3 +-
+ drivers/clk/renesas/Kconfig                   |   5 +
+ drivers/clk/renesas/Makefile                  |   1 +
+ drivers/clk/renesas/r8a77990-cpg-mssr.c       | 289 ++++++++++++++++++
+ drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
+ 6 files changed, 304 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c
+
+diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+index c3473df23abb..db542abadb75 100644
+--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
++++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+@@ -26,6 +26,7 @@ Required Properties:
+       - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
+       - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+       - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
++      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
+       - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
+ 
+   - reg: Base address and length of the memory resource used by the CPG/MSSR
+@@ -36,7 +37,7 @@ Required Properties:
+   - clock-names: List of external parent clock names. Valid names are:
+       - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
+ 		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
+-		 r8a77980, r8a77995)
++		 r8a77980, r8a77990, r8a77995)
+       - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
+       - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
+ 		     r8a7794)
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index f32896fa9dda..f9ba71311727 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -19,6 +19,7 @@ config CLK_RENESAS
+ 	select CLK_R8A77965 if ARCH_R8A77965
+ 	select CLK_R8A77970 if ARCH_R8A77970
+ 	select CLK_R8A77980 if ARCH_R8A77980
++	select CLK_R8A77990 if ARCH_R8A77990
+ 	select CLK_R8A77995 if ARCH_R8A77995
+ 	select CLK_SH73A0 if ARCH_SH73A0
+ 
+@@ -116,6 +117,10 @@ config CLK_R8A77980
+ 	bool "R-Car V3H clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+ 
++config CLK_R8A77990
++	bool "R-Car E3 clock support" if COMPILE_TEST
++	select CLK_RCAR_GEN3_CPG
++
+ config CLK_R8A77995
+ 	bool "R-Car D3 clock support" if COMPILE_TEST
+ 	select CLK_RCAR_GEN3_CPG
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index a4edea99c4ec..fe5bac9215e5 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77965)		+= r8a77965-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o
++obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o
+ obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
+ obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
+ 
+diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
+new file mode 100644
+index 000000000000..9e14f1486fbb
+--- /dev/null
++++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
+@@ -0,0 +1,289 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ *
++ * Based on r8a7795-cpg-mssr.c
++ *
++ * Copyright (C) 2015 Glider bvba
++ * Copyright (C) 2015 Renesas Electronics Corp.
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++
++#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen3-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL0,
++	CLK_PLL1,
++	CLK_PLL3,
++	CLK_PLL0D4,
++	CLK_PLL0D6,
++	CLK_PLL0D8,
++	CLK_PLL0D20,
++	CLK_PLL0D24,
++	CLK_PLL1D2,
++	CLK_PE,
++	CLK_S0,
++	CLK_S1,
++	CLK_S2,
++	CLK_S3,
++	CLK_SDSRC,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",     CLK_EXTAL),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
++	DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
++	DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
++
++	DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,	   1, 100),
++	DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),
++	DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),
++	DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),
++	DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),
++	DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
++	DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
++	DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D20,    1, 1),
++	DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
++	DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
++	DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
++	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
++	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
++
++	/* Core Clock Outputs */
++	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
++	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
++	DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
++	DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
++	DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
++	DEF_FIXED("s0d1",      R8A77990_CLK_S0D1,  CLK_S0,         1, 1),
++	DEF_FIXED("s0d3",      R8A77990_CLK_S0D3,  CLK_S0,         3, 1),
++	DEF_FIXED("s0d6",      R8A77990_CLK_S0D6,  CLK_S0,         6, 1),
++	DEF_FIXED("s0d12",     R8A77990_CLK_S0D12, CLK_S0,        12, 1),
++	DEF_FIXED("s0d24",     R8A77990_CLK_S0D24, CLK_S0,        24, 1),
++	DEF_FIXED("s1d1",      R8A77990_CLK_S1D1,  CLK_S1,         1, 1),
++	DEF_FIXED("s1d2",      R8A77990_CLK_S1D2,  CLK_S1,         2, 1),
++	DEF_FIXED("s1d4",      R8A77990_CLK_S1D4,  CLK_S1,         4, 1),
++	DEF_FIXED("s2d1",      R8A77990_CLK_S2D1,  CLK_S2,         1, 1),
++	DEF_FIXED("s2d2",      R8A77990_CLK_S2D2,  CLK_S2,         2, 1),
++	DEF_FIXED("s2d4",      R8A77990_CLK_S2D4,  CLK_S2,         4, 1),
++	DEF_FIXED("s3d1",      R8A77990_CLK_S3D1,  CLK_S3,         1, 1),
++	DEF_FIXED("s3d2",      R8A77990_CLK_S3D2,  CLK_S3,         2, 1),
++	DEF_FIXED("s3d4",      R8A77990_CLK_S3D4,  CLK_S3,         4, 1),
++
++	DEF_GEN3_SD("sd0",     R8A77990_CLK_SD0,   CLK_SDSRC,	  0x0074),
++	DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,	  0x0078),
++	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,	  0x026c),
++
++	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
++	DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
++	DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
++	DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),
++	DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),
++
++	DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
++	DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
++	DEF_GEN3_PE("s3d2c",   R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
++	DEF_GEN3_PE("s3d4c",   R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
++
++	DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
++	DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
++	DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
++};
++
++static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
++	DEF_MOD("scif5",		 202,	R8A77990_CLK_S3D4C),
++	DEF_MOD("scif4",		 203,	R8A77990_CLK_S3D4C),
++	DEF_MOD("scif3",		 204,	R8A77990_CLK_S3D4C),
++	DEF_MOD("scif1",		 206,	R8A77990_CLK_S3D4C),
++	DEF_MOD("scif0",		 207,	R8A77990_CLK_S3D4C),
++	DEF_MOD("msiof3",		 208,	R8A77990_CLK_MSO),
++	DEF_MOD("msiof2",		 209,	R8A77990_CLK_MSO),
++	DEF_MOD("msiof1",		 210,	R8A77990_CLK_MSO),
++	DEF_MOD("msiof0",		 211,	R8A77990_CLK_MSO),
++	DEF_MOD("sys-dmac2",		 217,	R8A77990_CLK_S3D1),
++	DEF_MOD("sys-dmac1",		 218,	R8A77990_CLK_S3D1),
++	DEF_MOD("sys-dmac0",		 219,	R8A77990_CLK_S3D1),
++
++	DEF_MOD("cmt3",			 300,	R8A77990_CLK_R),
++	DEF_MOD("cmt2",			 301,	R8A77990_CLK_R),
++	DEF_MOD("cmt1",			 302,	R8A77990_CLK_R),
++	DEF_MOD("cmt0",			 303,	R8A77990_CLK_R),
++	DEF_MOD("scif2",		 310,	R8A77990_CLK_S3D4C),
++	DEF_MOD("sdif3",		 311,	R8A77990_CLK_SD3),
++	DEF_MOD("sdif1",		 313,	R8A77990_CLK_SD1),
++	DEF_MOD("sdif0",		 314,	R8A77990_CLK_SD0),
++	DEF_MOD("pcie0",		 319,	R8A77990_CLK_S3D1),
++	DEF_MOD("usb3-if0",		 328,	R8A77990_CLK_S3D1),
++	DEF_MOD("usb-dmac0",		 330,	R8A77990_CLK_S3D1),
++	DEF_MOD("usb-dmac1",		 331,	R8A77990_CLK_S3D1),
++
++	DEF_MOD("rwdt",			 402,	R8A77990_CLK_R),
++	DEF_MOD("intc-ex",		 407,	R8A77990_CLK_CP),
++	DEF_MOD("intc-ap",		 408,	R8A77990_CLK_S0D3),
++
++	DEF_MOD("audmac0",		 502,	R8A77990_CLK_S3D4),
++	DEF_MOD("drif7",		 508,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif6",		 509,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif5",		 510,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif4",		 511,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif3",		 512,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif2",		 513,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif1",		 514,	R8A77990_CLK_S3D2),
++	DEF_MOD("drif0",		 515,	R8A77990_CLK_S3D2),
++	DEF_MOD("hscif4",		 516,	R8A77990_CLK_S3D1C),
++	DEF_MOD("hscif3",		 517,	R8A77990_CLK_S3D1C),
++	DEF_MOD("hscif2",		 518,	R8A77990_CLK_S3D1C),
++	DEF_MOD("hscif1",		 519,	R8A77990_CLK_S3D1C),
++	DEF_MOD("hscif0",		 520,	R8A77990_CLK_S3D1C),
++	DEF_MOD("thermal",		 522,	R8A77990_CLK_CP),
++	DEF_MOD("pwm",			 523,	R8A77990_CLK_S3D4C),
++
++	DEF_MOD("fcpvd1",		 602,	R8A77990_CLK_S1D2),
++	DEF_MOD("fcpvd0",		 603,	R8A77990_CLK_S1D2),
++	DEF_MOD("fcpvb0",		 607,	R8A77990_CLK_S0D1),
++	DEF_MOD("fcpvi0",		 611,	R8A77990_CLK_S0D1),
++	DEF_MOD("fcpf0",		 615,	R8A77990_CLK_S0D1),
++	DEF_MOD("fcpcs",		 619,	R8A77990_CLK_S0D1),
++	DEF_MOD("vspd1",		 622,	R8A77990_CLK_S1D2),
++	DEF_MOD("vspd0",		 623,	R8A77990_CLK_S1D2),
++	DEF_MOD("vspb",			 626,	R8A77990_CLK_S0D1),
++	DEF_MOD("vspi0",		 631,	R8A77990_CLK_S0D1),
++
++	DEF_MOD("ehci0",		 703,	R8A77990_CLK_S3D4),
++	DEF_MOD("hsusb",		 704,	R8A77990_CLK_S3D4),
++	DEF_MOD("csi40",		 716,	R8A77990_CLK_CSI0),
++	DEF_MOD("du1",			 723,	R8A77990_CLK_S2D1),
++	DEF_MOD("du0",			 724,	R8A77990_CLK_S2D1),
++	DEF_MOD("lvds",			 727,	R8A77990_CLK_S2D1),
++
++	DEF_MOD("vin5",			 806,	R8A77990_CLK_S1D2),
++	DEF_MOD("vin4",			 807,	R8A77990_CLK_S1D2),
++	DEF_MOD("etheravb",		 812,	R8A77990_CLK_S3D2),
++
++	DEF_MOD("gpio6",		 906,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio5",		 907,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio4",		 908,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio3",		 909,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio2",		 910,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio1",		 911,	R8A77990_CLK_S3D4),
++	DEF_MOD("gpio0",		 912,	R8A77990_CLK_S3D4),
++	DEF_MOD("can-fd",		 914,	R8A77990_CLK_S3D2),
++	DEF_MOD("can-if1",		 915,	R8A77990_CLK_S3D4),
++	DEF_MOD("can-if0",		 916,	R8A77990_CLK_S3D4),
++	DEF_MOD("i2c6",			 918,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c5",			 919,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c-dvfs",		 926,	R8A77990_CLK_CP),
++	DEF_MOD("i2c4",			 927,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c3",			 928,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c2",			 929,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c1",			 930,	R8A77990_CLK_S3D2),
++	DEF_MOD("i2c0",			 931,	R8A77990_CLK_S3D2),
++
++	DEF_MOD("ssi-all",		1005,	R8A77990_CLK_S3D4),
++	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
++	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
++	DEF_MOD("scu-all",		1017,	R8A77990_CLK_S3D4),
++	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
++	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
++};
++
++static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
++};
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
++ *--------------------------------------------------------------------
++ * 0		48 x 1		x100/4		x100/3		x100/3
++ * 1		48 x 1		x100/4		x100/3		 x58/3
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
++
++static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
++	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
++	{ 1,		100,	3,	100,	3,	},
++	{ 1,		100,	3,	 58,	3,	},
++};
++
++static int __init r8a77990_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++
++	return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
++}
++
++const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks = r8a77990_core_clks,
++	.num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
++	.last_dt_core_clk = LAST_DT_CORE_CLK,
++	.num_total_core_clks = MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks = r8a77990_mod_clks,
++	.num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
++	.num_hw_mod_clks = 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks = r8a77990_crit_mod_clks,
++	.num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
++
++	/* Callbacks */
++	.init = r8a77990_cpg_mssr_init,
++	.cpg_clk_register = rcar_gen3_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index 3ddd6208df4e..f4b013e9352d 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -718,6 +718,12 @@ static const struct of_device_id cpg_mssr_match[] = {
+ 		.data = &r8a77980_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_CLK_R8A77990
++	{
++		.compatible = "renesas,r8a77990-cpg-mssr",
++		.data = &r8a77990_cpg_mssr_info,
++	},
++#endif
+ #ifdef CONFIG_CLK_R8A77995
+ 	{
+ 		.compatible = "renesas,r8a77995-cpg-mssr",
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index efe2a149acce..642f720b9b05 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -143,6 +143,7 @@ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+ 
+ 
+-- 
+2.19.0
+
diff --git a/patches/1608-i2c-recovery-if-possible-send-STOP-with-recovery-pul.patch b/patches/1608-i2c-recovery-if-possible-send-STOP-with-recovery-pul.patch
new file mode 100644
index 00000000000000..8c1a355a65d346
--- /dev/null
+++ b/patches/1608-i2c-recovery-if-possible-send-STOP-with-recovery-pul.patch
@@ -0,0 +1,47 @@
+From 62b661577abd1ab4c6cb8393ca52a2503cf01a1e Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 10 Jul 2018 23:42:15 +0200
+Subject: [PATCH 1608/1795] i2c: recovery: if possible send STOP with recovery
+ pulses
+
+I2C clients may misunderstand recovery pulses if they can't read SDA to
+bail out early. In the worst case, as a write operation. To avoid that
+and if we can write SDA, try to send STOP to avoid the
+misinterpretation.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Peter Rosin <peda@axentia.se>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Cc: stable@kernel.org
+(cherry picked from commit abe41184abac487264a4904bfcff2d5500dccce6)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 268f12f421af..4566f9dd26cf 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -232,7 +232,16 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 
+ 		val = !val;
+ 		bri->set_scl(adap, val);
+-		ndelay(RECOVERY_NDELAY);
++
++		/*
++		 * If we can set SDA, we will always create STOP here to ensure
++		 * the additional pulses will do no harm. This is achieved by
++		 * letting SDA follow SCL half a cycle later.
++		 */
++		ndelay(RECOVERY_NDELAY / 2);
++		if (bri->set_sda)
++			bri->set_sda(adap, val);
++		ndelay(RECOVERY_NDELAY / 2);
+ 	}
+ 
+ 	/* check if recovery actually succeeded */
+-- 
+2.19.0
+
diff --git a/patches/1609-i2c-rcar-enhance-comment-to-avoid-regressions.patch b/patches/1609-i2c-rcar-enhance-comment-to-avoid-regressions.patch
new file mode 100644
index 00000000000000..63dbdb5080f59a
--- /dev/null
+++ b/patches/1609-i2c-rcar-enhance-comment-to-avoid-regressions.patch
@@ -0,0 +1,33 @@
+From ba02dea17614ea02ad362efc3178c73c3f1d333e Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Sat, 28 Apr 2018 22:01:02 +0200
+Subject: [PATCH 1609/1795] i2c: rcar: enhance comment to avoid regressions
+
+Give a clear testcase for people wishing to change this code. It is also
+a reminder for me if people ask about it.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit b1437dcb973de79d1f9bca55c6056e8b40ff7ba7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index c6915b835396..9d8d5b91220f 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -542,6 +542,8 @@ static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
+ 	 * If next received data is the _LAST_, go to STOP phase. Might be
+ 	 * overwritten by REP START when setting up a new msg. Not elegant
+ 	 * but the only stable sequence for REP START I have found so far.
++	 * If you want to change this code, make sure sending one transfer with
++	 * four messages (WR-RD-WR-RD) works!
+ 	 */
+ 	if (priv->pos + 1 >= msg->len)
+ 		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
+-- 
+2.19.0
+
diff --git a/patches/1610-i2c-rcar-document-R8A77980-bindings.patch b/patches/1610-i2c-rcar-document-R8A77980-bindings.patch
new file mode 100644
index 00000000000000..5b30a8b03a2a2a
--- /dev/null
+++ b/patches/1610-i2c-rcar-document-R8A77980-bindings.patch
@@ -0,0 +1,34 @@
+From f8c1671680de7aed5184b15d575b04a2be8bd91c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Mon, 28 May 2018 22:39:05 +0300
+Subject: [PATCH 1610/1795] i2c: rcar: document R8A77980 bindings
+
+R-Car V3H (R8A77980) SoC also has the R-Car gen3 compatible I2C controller,
+so document the SoC  specific bindings.
+
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit b80646be4c171f6b59f3145ee3b8872b56e0ac4c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+index 4a7811ecd954..7ce8fae55537 100644
+--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
++++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+@@ -15,6 +15,7 @@ Required properties:
+ 	"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ 	"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
+ 	"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
++	"renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
+ 	"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
+ 	"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+ 	"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+-- 
+2.19.0
+
diff --git a/patches/1611-i2c-rcar-handle-RXDMA-HW-behaviour-on-Gen3.patch b/patches/1611-i2c-rcar-handle-RXDMA-HW-behaviour-on-Gen3.patch
new file mode 100644
index 00000000000000..9a820f35017324
--- /dev/null
+++ b/patches/1611-i2c-rcar-handle-RXDMA-HW-behaviour-on-Gen3.patch
@@ -0,0 +1,142 @@
+From a73fed954fbf1e4d994588489961bef14404e816 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Thu, 28 Jun 2018 22:45:38 +0200
+Subject: [PATCH 1611/1795] i2c: rcar: handle RXDMA HW behaviour on Gen3
+
+On Gen3, we can only do RXDMA once per transfer reliably. For that, we
+must reset the device, then we can have RXDMA once. This patch
+implements this. When there is no reset controller or the reset fails,
+RXDMA will be blocked completely. Otherwise, it will be disabled after
+the first RXDMA transfer. Based on a commit from the BSP by Hiromitsu
+Yamasaki, yet completely refactored to handle multiple read messages
+within one transfer.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Cc: stable@kernel.org
+(cherry picked from commit 2b16fd63059ab9a46d473620749672dc342e1d21)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 54 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 51 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 9d8d5b91220f..41159ac2a320 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -32,6 +32,7 @@
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/reset.h>
+ #include <linux/slab.h>
+ 
+ /* register offsets */
+@@ -111,8 +112,9 @@
+ #define ID_ARBLOST	(1 << 3)
+ #define ID_NACK		(1 << 4)
+ /* persistent flags */
++#define ID_P_NO_RXDMA	(1 << 30) /* HW forbids RXDMA sometimes */
+ #define ID_P_PM_BLOCKED	(1 << 31)
+-#define ID_P_MASK	ID_P_PM_BLOCKED
++#define ID_P_MASK	(ID_P_PM_BLOCKED | ID_P_NO_RXDMA)
+ 
+ enum rcar_i2c_type {
+ 	I2C_RCAR_GEN1,
+@@ -141,6 +143,8 @@ struct rcar_i2c_priv {
+ 	struct dma_chan *dma_rx;
+ 	struct scatterlist sg;
+ 	enum dma_data_direction dma_direction;
++
++	struct reset_control *rstc;
+ };
+ 
+ #define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
+@@ -370,6 +374,11 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
+ 	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
+ 			 sg_dma_len(&priv->sg), priv->dma_direction);
+ 
++	/* Gen3 can only do one RXDMA per transfer and we just completed it */
++	if (priv->devtype == I2C_RCAR_GEN3 &&
++	    priv->dma_direction == DMA_FROM_DEVICE)
++		priv->flags |= ID_P_NO_RXDMA;
++
+ 	priv->dma_direction = DMA_NONE;
+ }
+ 
+@@ -407,8 +416,9 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
+ 	unsigned char *buf;
+ 	int len;
+ 
+-	/* Do not use DMA if it's not available or for messages < 8 bytes */
+-	if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE))
++	/* Do various checks to see if DMA is feasible at all */
++	if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) ||
++	    (read && priv->flags & ID_P_NO_RXDMA))
+ 		return;
+ 
+ 	if (read) {
+@@ -739,6 +749,25 @@ static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
+ 	}
+ }
+ 
++/* I2C is a special case, we need to poll the status of a reset */
++static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
++{
++	int i, ret;
++
++	ret = reset_control_reset(priv->rstc);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < LOOP_TIMEOUT; i++) {
++		ret = reset_control_status(priv->rstc);
++		if (ret == 0)
++			return 0;
++		udelay(1);
++	}
++
++	return -ETIMEDOUT;
++}
++
+ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
+ 				struct i2c_msg *msgs,
+ 				int num)
+@@ -750,6 +779,16 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
+ 
+ 	pm_runtime_get_sync(dev);
+ 
++	/* Gen3 needs a reset before allowing RXDMA once */
++	if (priv->devtype == I2C_RCAR_GEN3) {
++		priv->flags |= ID_P_NO_RXDMA;
++		if (!IS_ERR(priv->rstc)) {
++			ret = rcar_i2c_do_reset(priv);
++			if (ret == 0)
++				priv->flags &= ~ID_P_NO_RXDMA;
++		}
++	}
++
+ 	rcar_i2c_init(priv);
+ 
+ 	ret = rcar_i2c_bus_barrier(priv);
+@@ -920,6 +959,15 @@ static int rcar_i2c_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto out_pm_put;
+ 
++	if (priv->devtype == I2C_RCAR_GEN3) {
++		priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++		if (!IS_ERR(priv->rstc)) {
++			ret = reset_control_status(priv->rstc);
++			if (ret < 0)
++				priv->rstc = ERR_PTR(-ENOTSUPP);
++		}
++	}
++
+ 	/* Stay always active when multi-master to keep arbitration working */
+ 	if (of_property_read_bool(dev->of_node, "multi-master"))
+ 		priv->flags |= ID_P_PM_BLOCKED;
+-- 
+2.19.0
+
diff --git a/patches/1612-dmaengine-rcar-dmac-Document-R8A77990-bindings.patch b/patches/1612-dmaengine-rcar-dmac-Document-R8A77990-bindings.patch
new file mode 100644
index 00000000000000..491e0db594cffc
--- /dev/null
+++ b/patches/1612-dmaengine-rcar-dmac-Document-R8A77990-bindings.patch
@@ -0,0 +1,36 @@
+From 46ee25d3987586d3aeeaae84e49b925a7232a496 Mon Sep 17 00:00:00 2001
+From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Date: Wed, 20 Jun 2018 14:01:37 +0200
+Subject: [PATCH 1612/1795] dmaengine: rcar-dmac: Document R8A77990 bindings
+
+Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
+controllers, so document the SoC specific binding.
+
+Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit eb9fe6029ad49469b072a09a7fbfab34661e171a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+index b1ba639554c0..946229c48657 100644
+--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
++++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+@@ -29,6 +29,7 @@ Required Properties:
+ 		- "renesas,dmac-r8a77965" (R-Car M3-N)
+ 		- "renesas,dmac-r8a77970" (R-Car V3M)
+ 		- "renesas,dmac-r8a77980" (R-Car V3H)
++		- "renesas,dmac-r8a77990" (R-Car E3)
+ 		- "renesas,dmac-r8a77995" (R-Car D3)
+ 
+ - reg: base address and length of the registers block for the DMAC
+-- 
+2.19.0
+
diff --git a/patches/1613-dmaengine-rcar-dmac-don-t-use-DMAC-error-interrupt.patch b/patches/1613-dmaengine-rcar-dmac-don-t-use-DMAC-error-interrupt.patch
new file mode 100644
index 00000000000000..e78e5086ca7b90
--- /dev/null
+++ b/patches/1613-dmaengine-rcar-dmac-don-t-use-DMAC-error-interrupt.patch
@@ -0,0 +1,194 @@
+From ef15cfcf5b9536479e11f24b21d1fbda4eacadd6 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Fri, 15 Jun 2018 00:53:33 +0000
+Subject: [PATCH 1613/1795] dmaengine: rcar-dmac: don't use DMAC error
+ interrupt
+
+rcar-dmac has 2 types of interrupt, 1) error IRQ (for all),
+2) IRQ for each channels.
+If error happens on some channels, the error IRQ will be handled
+by 1), and "all" channels will be restarted.
+But in this design, error handling itself will be problem for
+non error channel users.
+This patch removes 1) handler, and handles error IRQ on 2)
+
+Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
+[Kuninori: updated patch to adjust DMACHCR/DMAOR]
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Tested-by: Nguyen Viet Dung <nv-dung@jinso.co.jp>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+
+(cherry picked from commit 9203dbec90a68103644ad9bf3ccf16461d67fcac)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 72 ++++++++++++--------------------------
+ 1 file changed, 22 insertions(+), 50 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 2a2ccd9c78e4..279c930c4a76 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -431,7 +431,8 @@ static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
+ 		chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
+ 	}
+ 
+-	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE);
++	rcar_dmac_chan_write(chan, RCAR_DMACHCR,
++			     chcr | RCAR_DMACHCR_DE | RCAR_DMACHCR_CAIE);
+ }
+ 
+ static int rcar_dmac_init(struct rcar_dmac *dmac)
+@@ -783,7 +784,8 @@ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+ 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+ 
+ 	chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
+-		  RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
++		  RCAR_DMACHCR_TE | RCAR_DMACHCR_DE |
++		  RCAR_DMACHCR_CAE | RCAR_DMACHCR_CAIE);
+ 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
+ 	rcar_dmac_chcr_de_barrier(chan);
+ }
+@@ -812,12 +814,7 @@ static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
+ 	}
+ }
+ 
+-static void rcar_dmac_stop(struct rcar_dmac *dmac)
+-{
+-	rcar_dmac_write(dmac, RCAR_DMAOR, 0);
+-}
+-
+-static void rcar_dmac_abort(struct rcar_dmac *dmac)
++static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
+ {
+ 	unsigned int i;
+ 
+@@ -829,11 +826,10 @@ static void rcar_dmac_abort(struct rcar_dmac *dmac)
+ 		spin_lock(&chan->lock);
+ 		rcar_dmac_chan_halt(chan);
+ 		spin_unlock(&chan->lock);
+-
+-		rcar_dmac_chan_reinit(chan);
+ 	}
+ }
+ 
++
+ /* -----------------------------------------------------------------------------
+  * Descriptors preparation
+  */
+@@ -1522,11 +1518,18 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
+ 	u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
+ 	struct rcar_dmac_chan *chan = dev;
+ 	irqreturn_t ret = IRQ_NONE;
++	bool reinit = false;
+ 	u32 chcr;
+ 
+ 	spin_lock(&chan->lock);
+ 
+ 	chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
++	if (chcr & RCAR_DMACHCR_CAE) {
++		rcar_dmac_chan_halt(chan);
++		reinit = true;
++		goto spin_lock_end;
++	}
++
+ 	if (chcr & RCAR_DMACHCR_TE)
+ 		mask |= RCAR_DMACHCR_DE;
+ 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
+@@ -1539,8 +1542,16 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
+ 	if (chcr & RCAR_DMACHCR_TE)
+ 		ret |= rcar_dmac_isr_transfer_end(chan);
+ 
++spin_lock_end:
+ 	spin_unlock(&chan->lock);
+ 
++	if (reinit) {
++		dev_err(chan->chan.device->dev, "Channel Address Error\n");
++
++		rcar_dmac_chan_reinit(chan);
++		ret = IRQ_HANDLED;
++	}
++
+ 	return ret;
+ }
+ 
+@@ -1597,24 +1608,6 @@ static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static irqreturn_t rcar_dmac_isr_error(int irq, void *data)
+-{
+-	struct rcar_dmac *dmac = data;
+-
+-	if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE))
+-		return IRQ_NONE;
+-
+-	/*
+-	 * An unrecoverable error occurred on an unknown channel. Halt the DMAC,
+-	 * abort transfers on all channels, and reinitialize the DMAC.
+-	 */
+-	rcar_dmac_stop(dmac);
+-	rcar_dmac_abort(dmac);
+-	rcar_dmac_init(dmac);
+-
+-	return IRQ_HANDLED;
+-}
+-
+ /* -----------------------------------------------------------------------------
+  * OF xlate and channel filter
+  */
+@@ -1784,8 +1777,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
+ 	struct rcar_dmac *dmac;
+ 	struct resource *mem;
+ 	unsigned int i;
+-	char *irqname;
+-	int irq;
+ 	int ret;
+ 
+ 	dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
+@@ -1824,17 +1815,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
+ 	if (IS_ERR(dmac->iomem))
+ 		return PTR_ERR(dmac->iomem);
+ 
+-	irq = platform_get_irq_byname(pdev, "error");
+-	if (irq < 0) {
+-		dev_err(&pdev->dev, "no error IRQ specified\n");
+-		return -ENODEV;
+-	}
+-
+-	irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error",
+-				 dev_name(dmac->dev));
+-	if (!irqname)
+-		return -ENOMEM;
+-
+ 	/* Enable runtime PM and initialize the device. */
+ 	pm_runtime_enable(&pdev->dev);
+ 	ret = pm_runtime_get_sync(&pdev->dev);
+@@ -1885,14 +1865,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
+ 			goto error;
+ 	}
+ 
+-	ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0,
+-			       irqname, dmac);
+-	if (ret) {
+-		dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
+-			irq, ret);
+-		return ret;
+-	}
+-
+ 	/* Register the DMAC as a DMA provider for DT. */
+ 	ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate,
+ 					 NULL);
+@@ -1932,7 +1904,7 @@ static void rcar_dmac_shutdown(struct platform_device *pdev)
+ {
+ 	struct rcar_dmac *dmac = platform_get_drvdata(pdev);
+ 
+-	rcar_dmac_stop(dmac);
++	rcar_dmac_stop_all_chan(dmac);
+ }
+ 
+ static const struct of_device_id rcar_dmac_of_ids[] = {
+-- 
+2.19.0
+
diff --git a/patches/1614-dmaengine-rcar-dmac-convert-to-SPDX-identifiers.patch b/patches/1614-dmaengine-rcar-dmac-convert-to-SPDX-identifiers.patch
new file mode 100644
index 00000000000000..1fa4e0ffcccc2d
--- /dev/null
+++ b/patches/1614-dmaengine-rcar-dmac-convert-to-SPDX-identifiers.patch
@@ -0,0 +1,41 @@
+From f870d5bd487f732da753cf20168d7e136d4885d7 Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Wed, 4 Jul 2018 00:34:10 +0000
+Subject: [PATCH 1614/1795] dmaengine: rcar-dmac: convert to SPDX identifiers
+
+This patch is using C++ comment style for SPDX line only,
+because driver author want it.
+
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit b9b0a74aad1ca47544f875d6afac4d91e789f67c)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 279c930c4a76..6b3cdb709287 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -1,13 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Renesas R-Car Gen2 DMA Controller Driver
+  *
+  * Copyright (C) 2014 Renesas Electronics Inc.
+  *
+  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+- *
+- * This is free software; you can redistribute it and/or modify
+- * it under the terms of version 2 of the GNU General Public License as
+- * published by the Free Software Foundation.
+  */
+ 
+ #include <linux/delay.h>
+-- 
+2.19.0
+
diff --git a/patches/1615-dmaengine-rcar-dmac-Disable-interrupts-while-stoppin.patch b/patches/1615-dmaengine-rcar-dmac-Disable-interrupts-while-stoppin.patch
new file mode 100644
index 00000000000000..9a286b0a334e7b
--- /dev/null
+++ b/patches/1615-dmaengine-rcar-dmac-Disable-interrupts-while-stoppin.patch
@@ -0,0 +1,111 @@
+From 02145262d34ab1a6e68690c0271111566ded7c6d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 2 Jul 2018 17:02:06 +0200
+Subject: [PATCH 1615/1795] dmaengine: rcar-dmac: Disable interrupts while
+ stopping channels
+
+During system reboot or halt, with lockdep enabled:
+
+    ================================
+    WARNING: inconsistent lock state
+    4.18.0-rc1-salvator-x-00002-g9203dbec90a68103 #41 Tainted: G        W
+    --------------------------------
+    inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
+    reboot/2779 [HC0[0]:SC0[0]:HE1:SE1] takes:
+    0000000098ae4ad3 (&(&rchan->lock)->rlock){?.-.}, at: rcar_dmac_shutdown+0x58/0x6c
+    {IN-HARDIRQ-W} state was registered at:
+      lock_acquire+0x208/0x238
+      _raw_spin_lock+0x40/0x54
+      rcar_dmac_isr_channel+0x28/0x200
+      __handle_irq_event_percpu+0x1c0/0x3c8
+      handle_irq_event_percpu+0x34/0x88
+      handle_irq_event+0x48/0x78
+      handle_fasteoi_irq+0xc4/0x12c
+      generic_handle_irq+0x18/0x2c
+      __handle_domain_irq+0xa8/0xac
+      gic_handle_irq+0x78/0xbc
+      el1_irq+0xec/0x1c0
+      arch_cpu_idle+0xe8/0x1bc
+      default_idle_call+0x2c/0x30
+      do_idle+0x144/0x234
+      cpu_startup_entry+0x20/0x24
+      rest_init+0x27c/0x290
+      start_kernel+0x430/0x45c
+    irq event stamp: 12177
+    hardirqs last  enabled at (12177): [<ffffff800881d804>] _raw_spin_unlock_irq+0x2c/0x4c
+    hardirqs last disabled at (12176): [<ffffff800881d638>] _raw_spin_lock_irq+0x1c/0x60
+    softirqs last  enabled at (11948): [<ffffff8008081da8>] __do_softirq+0x160/0x4ec
+    softirqs last disabled at (11935): [<ffffff80080ec948>] irq_exit+0xa0/0xfc
+
+    other info that might help us debug this:
+     Possible unsafe locking scenario:
+
+	   CPU0
+	   ----
+      lock(&(&rchan->lock)->rlock);
+      <Interrupt>
+	lock(&(&rchan->lock)->rlock);
+
+     *** DEADLOCK ***
+
+    3 locks held by reboot/2779:
+     #0: 00000000bfabfa74 (reboot_mutex){+.+.}, at: sys_reboot+0xdc/0x208
+     #1: 00000000c75d8c3a (&dev->mutex){....}, at: device_shutdown+0xc8/0x1c4
+     #2: 00000000ebec58ec (&dev->mutex){....}, at: device_shutdown+0xd8/0x1c4
+
+    stack backtrace:
+    CPU: 6 PID: 2779 Comm: reboot Tainted: G        W         4.18.0-rc1-salvator-x-00002-g9203dbec90a68103 #41
+    Hardware name: Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+ (DT)
+    Call trace:
+     dump_backtrace+0x0/0x148
+     show_stack+0x14/0x1c
+     dump_stack+0xb0/0xf0
+     print_usage_bug.part.26+0x1c4/0x27c
+     mark_lock+0x38c/0x610
+     __lock_acquire+0x3fc/0x14d4
+     lock_acquire+0x208/0x238
+     _raw_spin_lock+0x40/0x54
+     rcar_dmac_shutdown+0x58/0x6c
+     platform_drv_shutdown+0x20/0x2c
+     device_shutdown+0x160/0x1c4
+     kernel_restart_prepare+0x34/0x3c
+     kernel_restart+0x14/0x5c
+     sys_reboot+0x160/0x208
+     el0_svc_naked+0x30/0x34
+
+rcar_dmac_stop_all_chan() takes the channel lock while stopping a
+channel, but does not disable interrupts, leading to a deadlock when a
+DMAC interrupt comes in.  Before, the same code block was called from an
+interrupt handler, hence taking the spinlock was sufficient.
+
+Fix this by disabling local interrupts while taking the spinlock.
+
+Fixes: 9203dbec90a68103 ("dmaengine: rcar-dmac: don't use DMAC error interrupt")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 45c9a603a4dfde06f53446ce1db218958442849b)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 6b3cdb709287..af2f2639cec9 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -820,9 +820,9 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
+ 		struct rcar_dmac_chan *chan = &dmac->channels[i];
+ 
+ 		/* Stop and reinitialize the channel. */
+-		spin_lock(&chan->lock);
++		spin_lock_irq(&chan->lock);
+ 		rcar_dmac_chan_halt(chan);
+-		spin_unlock(&chan->lock);
++		spin_unlock_irq(&chan->lock);
+ 	}
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1616-dmaengine-rcar-dmac-clear-channel-register-when-erro.patch b/patches/1616-dmaengine-rcar-dmac-clear-channel-register-when-erro.patch
new file mode 100644
index 00000000000000..038926c58ea14b
--- /dev/null
+++ b/patches/1616-dmaengine-rcar-dmac-clear-channel-register-when-erro.patch
@@ -0,0 +1,50 @@
+From 3f36ccad4927b5658f0697f87947c631051e276b Mon Sep 17 00:00:00 2001
+From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Date: Tue, 3 Jul 2018 00:29:29 +0000
+Subject: [PATCH 1616/1795] dmaengine: rcar-dmac: clear channel register when
+ error
+
+We need to clear channel register in error case as recovery.
+The channel is already stopped in such case, thus we don't need to call
+rcar_dmac_chan_halt() before clearing.
+
+rcar_dmac_chan_halt() will clear and confirm DE bit.
+But it will be failed because channel is already stopped in error case.
+In other words, we shouldn't call it then.
+
+Reported-by: Hiroki Negishi <hiroki.negishi.bx@renesas.com>
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Reviewed-by: Hiroki Negishi <hiroki.negishi.bx@renesas.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit e919417bd6468b7f1b2899200a78f1ad078757d3)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index af2f2639cec9..9dc73ac92359 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -1522,7 +1522,15 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
+ 
+ 	chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+ 	if (chcr & RCAR_DMACHCR_CAE) {
+-		rcar_dmac_chan_halt(chan);
++		struct rcar_dmac *dmac = to_rcar_dmac(chan->chan.device);
++
++		/*
++		 * We don't need to call rcar_dmac_chan_halt()
++		 * because channel is already stopped in error case.
++		 * We need to clear register and check DE bit as recovery.
++		 */
++		rcar_dmac_write(dmac, RCAR_DMACHCLR, 1 << chan->index);
++		rcar_dmac_chcr_de_barrier(chan);
+ 		reinit = true;
+ 		goto spin_lock_end;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1617-dmaengine-sh-rcar-dmac-avoid-to-write-CHCR.TE-to-1-i.patch b/patches/1617-dmaengine-sh-rcar-dmac-avoid-to-write-CHCR.TE-to-1-i.patch
new file mode 100644
index 00000000000000..94c440aaa00a68
--- /dev/null
+++ b/patches/1617-dmaengine-sh-rcar-dmac-avoid-to-write-CHCR.TE-to-1-i.patch
@@ -0,0 +1,51 @@
+From 069b8f108d9d621dc3c8ea913af0194256cb1600 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Mon, 2 Jul 2018 18:18:03 +0900
+Subject: [PATCH 1617/1795] dmaengine: sh: rcar-dmac: avoid to write CHCR.TE to
+ 1 if TCR is set to 0
+
+This patch fixes an issue that unexpected retransfering happens
+if TCR is set to 0 before rcar_dmac_sync_tcr() writes DE bit to
+the CHCR register. For example, sh-sci driver can reproduce this
+issue like below:
+
+ In rx_timer_fn():		/* CHCR DE bit may be set to 1 */
+  dmaengine_tx_status()
+   rcar_dmac_tx_status()
+    rcar_dmac_chan_get_residue()
+     rcar_dmac_sync_tcr()	/* TCR is possible to be set to 0 */
+
+According to the description of commit 73a47bd0da66 ("dmaengine:
+rcar-dmac: use TCRB instead of TCR for residue"), "this buffered data
+will be transferred if CHCR::DE bit was cleared". So, this patch
+doesn't need to check TCRB register.
+
+Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for residue")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 538603c6026ce769eec633bb79349f5f287519c7)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 9dc73ac92359..9906a9c7220b 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -772,8 +772,9 @@ static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
+ 	/* make sure all remaining data was flushed */
+ 	rcar_dmac_chcr_de_barrier(chan);
+ 
+-	/* back DE */
+-	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
++	/* back DE if remain data exists */
++	if (rcar_dmac_chan_read(chan, RCAR_DMATCR))
++		rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
+ }
+ 
+ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+-- 
+2.19.0
+
diff --git a/patches/1618-dmaengine-sh-rcar-dmac-add-a-new-function-to-clear-C.patch b/patches/1618-dmaengine-sh-rcar-dmac-add-a-new-function-to-clear-C.patch
new file mode 100644
index 00000000000000..559cf33604f1c3
--- /dev/null
+++ b/patches/1618-dmaengine-sh-rcar-dmac-add-a-new-function-to-clear-C.patch
@@ -0,0 +1,55 @@
+From 555ba44c5c53e5120c18f2556d2a4704718b10dd Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 11 Jul 2018 11:10:15 +0900
+Subject: [PATCH 1618/1795] dmaengine: sh: rcar-dmac: add a new function to
+ clear CHCR.DE with barrier
+
+This patch adds a new function rcar_dmac_clear_chcr_de() to simplify
+adding pause function later.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 4de1247a9826cec0ba054479124bd9aa60fb71a5)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index 9906a9c7220b..d3b7388645bc 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -759,18 +759,25 @@ static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
+ 	dev_err(chan->chan.device->dev, "CHCR DE check error\n");
+ }
+ 
+-static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
++static void rcar_dmac_clear_chcr_de(struct rcar_dmac_chan *chan)
+ {
+ 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+ 
+-	if (!(chcr & RCAR_DMACHCR_DE))
+-		return;
+-
+ 	/* set DE=0 and flush remaining data */
+ 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, (chcr & ~RCAR_DMACHCR_DE));
+ 
+ 	/* make sure all remaining data was flushed */
+ 	rcar_dmac_chcr_de_barrier(chan);
++}
++
++static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
++{
++	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
++
++	if (!(chcr & RCAR_DMACHCR_DE))
++		return;
++
++	rcar_dmac_clear_chcr_de(chan);
+ 
+ 	/* back DE if remain data exists */
+ 	if (rcar_dmac_chan_read(chan, RCAR_DMATCR))
+-- 
+2.19.0
+
diff --git a/patches/1619-dmaengine-sh-rcar-dmac-Add-dma_pause-operation.patch b/patches/1619-dmaengine-sh-rcar-dmac-Add-dma_pause-operation.patch
new file mode 100644
index 00000000000000..047b2bd145ed17
--- /dev/null
+++ b/patches/1619-dmaengine-sh-rcar-dmac-Add-dma_pause-operation.patch
@@ -0,0 +1,62 @@
+From afe6b324aa933ef81755430b6204cca9ab518a15 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 11 Jul 2018 11:10:16 +0900
+Subject: [PATCH 1619/1795] dmaengine: sh: rcar-dmac: Add dma_pause operation
+
+This patch adds dma_pause operation. This patch is based on
+Muhammad Hamza Farooq's patch.
+
+After this patch applied, an issue that the sh-sci driver with
+high baud rate might cause data lost disappeared because the DMAC
+is possible to transmit between [1] and [2] below, and then
+the residue of [1] is not true:
+
+In rx_timer_fn() of the sh-sci.c:
+	dmaengine_pause();
+	...
+	dmaengine_tx_status();		/* [1] */
+	...
+	dmaengine_terminate_all();	/* [2] */
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 8115ce745fa26ccffe7d1a542ab4322acf4a682d)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index d3b7388645bc..be82d6997a55 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -834,6 +834,17 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
+ 	}
+ }
+ 
++static int rcar_dmac_chan_pause(struct dma_chan *chan)
++{
++	unsigned long flags;
++	struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
++
++	spin_lock_irqsave(&rchan->lock, flags);
++	rcar_dmac_clear_chcr_de(rchan);
++	spin_unlock_irqrestore(&rchan->lock, flags);
++
++	return 0;
++}
+ 
+ /* -----------------------------------------------------------------------------
+  * Descriptors preparation
+@@ -1864,6 +1875,7 @@ static int rcar_dmac_probe(struct platform_device *pdev)
+ 	engine->device_prep_slave_sg		= rcar_dmac_prep_slave_sg;
+ 	engine->device_prep_dma_cyclic		= rcar_dmac_prep_dma_cyclic;
+ 	engine->device_config			= rcar_dmac_device_config;
++	engine->device_pause			= rcar_dmac_chan_pause;
+ 	engine->device_terminate_all		= rcar_dmac_chan_terminate_all;
+ 	engine->device_tx_status		= rcar_dmac_tx_status;
+ 	engine->device_issue_pending		= rcar_dmac_issue_pending;
+-- 
+2.19.0
+
diff --git a/patches/1620-dmaengine-sh-rcar-dmac-Should-not-stop-the-DMAC-by-r.patch b/patches/1620-dmaengine-sh-rcar-dmac-Should-not-stop-the-DMAC-by-r.patch
new file mode 100644
index 00000000000000..d5cf588d1d3dfd
--- /dev/null
+++ b/patches/1620-dmaengine-sh-rcar-dmac-Should-not-stop-the-DMAC-by-r.patch
@@ -0,0 +1,91 @@
+From bfe0631b164fef465be6c9cf56a065205c76cfd8 Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Wed, 25 Jul 2018 17:27:04 +0900
+Subject: [PATCH 1620/1795] dmaengine: sh: rcar-dmac: Should not stop the DMAC
+ by rcar_dmac_sync_tcr()
+
+rcar_dmac_chan_get_residue() should not stop the DMAC, because
+the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
+CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
+issue. But it had caused the next issue which might stop the cyclic
+mode transferring. Thus, for example R-Car sound might be stopped
+suddenly.
+
+According to the commit 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB
+instead of TCR for residue"), the purpose of clearing CHCR.DE bit is
+flushing buffered data to calculate the exact residue.
+
+Such the "exact" residue had been required by sh-sci driver. sh-sci
+driver is calling dmaengine_pause() to stop transferring, and get
+"exact" residue. Otherwise, it might receive extra data during
+getting residue without pausing.
+
+In rx_timer_fn() of sh-sci driver:
+	dmaengine_tx_status();		/* For checking roughly */
+ 	dmaengine_pause();
+	dmaengine_tx_status();		/* For getting residue */
+	dmaengine_terminate_all();
+
+But, unfortunately the rcar-dmac driver didn't support dmaengine_pause()
+at that time. So, the sh-sci driver cannot get the "exact" residue
+without stopping the transferring, because rcar-dmac is buffering data
+inside.
+
+Because of these backgrounds, rcar-dmac had been cleared/set CHCR.DE
+bit in rcar_dmac_chan_get_residue() to synchronizing data and getting
+"exact" residue.
+
+However, rcar-dmac driver has rcar_dmac_chan_pause() now, and clearing
+CHCR.DE bit in rcar_dmac_chan_get_residue() doesn't need anymore.
+So, this patch removes the rcar_dmac_sync_tcr().
+
+Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for residue")
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+(cherry picked from commit 218c21043d0037f616bd8af406de55a01e3fa381)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/dma/sh/rcar-dmac.c | 17 -----------------
+ 1 file changed, 17 deletions(-)
+
+diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
+index be82d6997a55..48ee35e2bce6 100644
+--- a/drivers/dma/sh/rcar-dmac.c
++++ b/drivers/dma/sh/rcar-dmac.c
+@@ -770,20 +770,6 @@ static void rcar_dmac_clear_chcr_de(struct rcar_dmac_chan *chan)
+ 	rcar_dmac_chcr_de_barrier(chan);
+ }
+ 
+-static void rcar_dmac_sync_tcr(struct rcar_dmac_chan *chan)
+-{
+-	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+-
+-	if (!(chcr & RCAR_DMACHCR_DE))
+-		return;
+-
+-	rcar_dmac_clear_chcr_de(chan);
+-
+-	/* back DE if remain data exists */
+-	if (rcar_dmac_chan_read(chan, RCAR_DMATCR))
+-		rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
+-}
+-
+ static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
+ {
+ 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
+@@ -1367,9 +1353,6 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
+ 		residue += chunk->size;
+ 	}
+ 
+-	if (desc->direction == DMA_DEV_TO_MEM)
+-		rcar_dmac_sync_tcr(chan);
+-
+ 	/* Add the residue for the current chunk. */
+ 	residue += rcar_dmac_chan_read(chan, RCAR_DMATCRB) << desc->xfer_shift;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1621-thermal-rcar_thermal-avoid-NULL-dereference-in-absen.patch b/patches/1621-thermal-rcar_thermal-avoid-NULL-dereference-in-absen.patch
new file mode 100644
index 00000000000000..42338a8041d0b6
--- /dev/null
+++ b/patches/1621-thermal-rcar_thermal-avoid-NULL-dereference-in-absen.patch
@@ -0,0 +1,47 @@
+From 010f23c070332db10c67d3f4758bdcdd38858b24 Mon Sep 17 00:00:00 2001
+From: Simon Horman <horms+renesas@verge.net.au>
+Date: Tue, 24 Jul 2018 13:14:13 +0200
+Subject: [PATCH 1621/1795] thermal: rcar_thermal: avoid NULL dereference in
+ absence of IRQ resources
+
+Ensure that the base address used by a call to rcar_thermal_common_write()
+may be NULL if the SOC supports interrupts for use with the thermal device
+but none are defined in DT as is the case for R-Car H1 (r8a7779). Guard
+against this condition to prevent a NULL dereference when the device is
+probed.
+
+Tested on:
+* R-Mobile APE6 (r8a73a4) / APE6EVM
+* R-Car H1 (r8a7779) / Marzen
+* R-Car H2 (r8a7790) / Lager
+* R-Car M2-W (r8a7791) / Koelsch
+* R-Car M2-N (r8a7793) / Gose
+* R-Car D3 ES1.0 (r8a77995) / Draak
+
+Fixes: 1969d9dc2079 ("thermal: rcar_thermal: add r8a77995 support")
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+(cherry picked from commit 542cdf4068049458e1411b120bd5a4bbe3ddc49a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/thermal/rcar_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
+index 45fb284d4c11..e77e63070e99 100644
+--- a/drivers/thermal/rcar_thermal.c
++++ b/drivers/thermal/rcar_thermal.c
+@@ -598,7 +598,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
+ 			enr_bits |= 3 << (i * 8);
+ 	}
+ 
+-	if (enr_bits)
++	if (common->base && enr_bits)
+ 		rcar_thermal_common_write(common, ENR, enr_bits);
+ 
+ 	dev_info(dev, "%d sensor probed\n", i);
+-- 
+2.19.0
+
diff --git a/patches/1622-usb-gadget-udc-renesas_usb3-Add-register-of-usb-role.patch b/patches/1622-usb-gadget-udc-renesas_usb3-Add-register-of-usb-role.patch
new file mode 100644
index 00000000000000..c33f3ac4e14864
--- /dev/null
+++ b/patches/1622-usb-gadget-udc-renesas_usb3-Add-register-of-usb-role.patch
@@ -0,0 +1,206 @@
+From 22b0fb1431f5378ad37927c3cf7027017679a73a Mon Sep 17 00:00:00 2001
+From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Date: Fri, 27 Jul 2018 10:50:40 +0900
+Subject: [PATCH 1622/1795] usb: gadget: udc: renesas_usb3: Add register of usb
+ role switch
+
+This patch adds role switch support for R-Car SoCs into the USB 3.0
+peripheral driver. Some R-Car SoCs (e.g. R-Car H3) have USB 3.0
+dual-role device controller which has the USB 3.0 xHCI host and
+Renesas USB 3.0 peripheral.
+
+Unfortunately, the mode change register (DRD_CON) contains
+the USB 3.0 peripheral controller side only. So, this renesas_usb3
+driver manages the DRD_CON now. However, in peripheral mode, the host
+should stop. Also the host hardware needs to reinitialize its own
+registers when the mode changes from peripheral to host mode.
+Otherwise, the host cannot work correctly (e.g. detect a device
+as high-speed).
+
+To achieve this reinitialization by a driver, this driver also
+registers a role switch driver to manage the DRD_CON and get
+a device pointer of usb 3.0 host from "companion" property of OF.
+Then, when the usb role is changed, renesas_usb3_role_switch_set()
+will attach/release the xhci-plat driver to reinitialize the host
+hardware.
+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit 39facfa01c9fc64f90233d1734882f0a0cafe36a)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+
+ Conflicts:
+	drivers/usb/gadget/udc/Kconfig
+---
+ drivers/usb/gadget/udc/Kconfig        |  1 +
+ drivers/usb/gadget/udc/renesas_usb3.c | 84 ++++++++++++++++++++++++++-
+ 2 files changed, 84 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig
+index 1e9567091d86..1d0ff704bfa8 100644
+--- a/drivers/usb/gadget/udc/Kconfig
++++ b/drivers/usb/gadget/udc/Kconfig
+@@ -193,6 +193,7 @@ config USB_RENESAS_USB3
+ 	tristate 'Renesas USB3.0 Peripheral controller'
+ 	depends on ARCH_RENESAS || COMPILE_TEST
+ 	depends on EXTCON && HAS_DMA
++	select USB_ROLE_SWITCH
+ 	help
+ 	   Renesas USB3.0 Peripheral controller is a USB peripheral controller
+ 	   that supports super, high, and full speed USB 3.0 data transfers.
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 977ea1a02cf9..a94fd09ee6f4 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -23,6 +23,8 @@
+ #include <linux/uaccess.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
++#include <linux/usb/of.h>
++#include <linux/usb/role.h>
+ 
+ /* register definitions */
+ #define USB3_AXI_INT_STA	0x008
+@@ -335,6 +337,11 @@ struct renesas_usb3 {
+ 	struct phy *phy;
+ 	struct dentry *dentry;
+ 
++	struct usb_role_switch *role_sw;
++	struct device *host_dev;
++	struct work_struct role_work;
++	enum usb_role role;
++
+ 	struct renesas_usb3_ep *usb3_ep;
+ 	int num_usb3_eps;
+ 
+@@ -651,6 +658,14 @@ static void usb3_check_vbus(struct renesas_usb3 *usb3)
+ 	}
+ }
+ 
++static void renesas_usb3_role_work(struct work_struct *work)
++{
++	struct renesas_usb3 *usb3 =
++			container_of(work, struct renesas_usb3, role_work);
++
++	usb_role_switch_set_role(usb3->role_sw, usb3->role);
++}
++
+ static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
+ {
+ 	if (host)
+@@ -659,6 +674,16 @@ static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
+ 		usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON);
+ }
+ 
++static void usb3_set_mode_by_role_sw(struct renesas_usb3 *usb3, bool host)
++{
++	if (usb3->role_sw) {
++		usb3->role = host ? USB_ROLE_HOST : USB_ROLE_DEVICE;
++		schedule_work(&usb3->role_work);
++	} else {
++		usb3_set_mode(usb3, host);
++	}
++}
++
+ static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable)
+ {
+ 	if (enable)
+@@ -672,7 +697,7 @@ static void usb3_mode_config(struct renesas_usb3 *usb3, bool host, bool a_dev)
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&usb3->lock, flags);
+-	usb3_set_mode(usb3, host);
++	usb3_set_mode_by_role_sw(usb3, host);
+ 	usb3_vbus_out(usb3, a_dev);
+ 	/* for A-Peripheral or forced B-device mode */
+ 	if ((!host && a_dev) ||
+@@ -2302,6 +2327,41 @@ static const struct usb_gadget_ops renesas_usb3_gadget_ops = {
+ 	.set_selfpowered	= renesas_usb3_set_selfpowered,
+ };
+ 
++static enum usb_role renesas_usb3_role_switch_get(struct device *dev)
++{
++	struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
++	enum usb_role cur_role;
++
++	pm_runtime_get_sync(dev);
++	cur_role = usb3_is_host(usb3) ? USB_ROLE_HOST : USB_ROLE_DEVICE;
++	pm_runtime_put(dev);
++
++	return cur_role;
++}
++
++static int renesas_usb3_role_switch_set(struct device *dev,
++					enum usb_role role)
++{
++	struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
++	struct device *host = usb3->host_dev;
++	enum usb_role cur_role = renesas_usb3_role_switch_get(dev);
++
++	pm_runtime_get_sync(dev);
++	if (cur_role == USB_ROLE_HOST && role == USB_ROLE_DEVICE) {
++		device_release_driver(host);
++		usb3_set_mode(usb3, false);
++	} else if (cur_role == USB_ROLE_DEVICE && role == USB_ROLE_HOST) {
++		/* Must set the mode before device_attach of the host */
++		usb3_set_mode(usb3, true);
++		/* This device_attach() might sleep */
++		if (device_attach(host) < 0)
++			dev_err(dev, "device_attach(host) failed\n");
++	}
++	pm_runtime_put(dev);
++
++	return 0;
++}
++
+ static ssize_t role_store(struct device *dev, struct device_attribute *attr,
+ 			  const char *buf, size_t count)
+ {
+@@ -2405,6 +2465,8 @@ static int renesas_usb3_remove(struct platform_device *pdev)
+ 	debugfs_remove_recursive(usb3->dentry);
+ 	device_remove_file(&pdev->dev, &dev_attr_role);
+ 
++	usb_role_switch_unregister(usb3->role_sw);
++
+ 	usb_del_gadget_udc(&usb3->gadget);
+ 	renesas_usb3_dma_free_prd(usb3, &pdev->dev);
+ 
+@@ -2561,6 +2623,12 @@ static const unsigned int renesas_usb3_cable[] = {
+ 	EXTCON_NONE,
+ };
+ 
++static const struct usb_role_switch_desc renesas_usb3_role_switch_desc = {
++	.set = renesas_usb3_role_switch_set,
++	.get = renesas_usb3_role_switch_get,
++	.allow_userspace_control = true,
++};
++
+ static int renesas_usb3_probe(struct platform_device *pdev)
+ {
+ 	struct renesas_usb3 *usb3;
+@@ -2646,6 +2714,20 @@ static int renesas_usb3_probe(struct platform_device *pdev)
+ 	if (ret < 0)
+ 		goto err_dev_create;
+ 
++	INIT_WORK(&usb3->role_work, renesas_usb3_role_work);
++	usb3->role_sw = usb_role_switch_register(&pdev->dev,
++					&renesas_usb3_role_switch_desc);
++	if (!IS_ERR(usb3->role_sw)) {
++		usb3->host_dev = usb_of_get_companion_dev(&pdev->dev);
++		if (!usb3->host_dev) {
++			/* If not found, this driver will not use a role sw */
++			usb_role_switch_unregister(usb3->role_sw);
++			usb3->role_sw = NULL;
++		}
++	} else {
++		usb3->role_sw = NULL;
++	}
++
+ 	usb3->workaround_for_vbus = priv->workaround_for_vbus;
+ 
+ 	renesas_usb3_debugfs_init(usb3, &pdev->dev);
+-- 
+2.19.0
+
diff --git a/patches/1623-i2c-recovery-require-either-get_sda-or-set_sda.patch b/patches/1623-i2c-recovery-require-either-get_sda-or-set_sda.patch
new file mode 100644
index 00000000000000..c6ef2c3b06ee16
--- /dev/null
+++ b/patches/1623-i2c-recovery-require-either-get_sda-or-set_sda.patch
@@ -0,0 +1,72 @@
+From 756cbbbd828bf0a5e67e9e95fb873155a0e00360 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 10 Jul 2018 23:42:16 +0200
+Subject: [PATCH 1623/1795] i2c: recovery: require either get_sda or set_sda
+
+For bus recovery, we either need to bail out early if we can read SDA or
+we need to send STOP after every pulse. Otherwise recovery might be
+misinterpreted as an unwanted write. So, require one of those SDA
+handling functions to avoid this problem.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Acked-by: Peter Rosin <peda@axentia.se>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit ffc59c496bf8498657321c59433f55bbcf2d9c38)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c |  7 ++++++-
+ include/linux/i2c.h         | 12 ++++++------
+ 2 files changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 4566f9dd26cf..ea4cc8defada 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -236,7 +236,8 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 		/*
+ 		 * If we can set SDA, we will always create STOP here to ensure
+ 		 * the additional pulses will do no harm. This is achieved by
+-		 * letting SDA follow SCL half a cycle later.
++		 * letting SDA follow SCL half a cycle later. Check the
++		 * 'incomplete_write_byte' fault injector for details.
+ 		 */
+ 		ndelay(RECOVERY_NDELAY / 2);
+ 		if (bri->set_sda)
+@@ -342,6 +343,10 @@ static void i2c_init_recovery(struct i2c_adapter *adap)
+ 			err_str = "no {get|set}_scl() found";
+ 			goto err;
+ 		}
++		if (!bri->set_sda && !bri->get_sda) {
++			err_str = "either get_sda() or set_sda() needed";
++			goto err;
++		}
+ 	}
+ 
+ 	return;
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index fef505ecab2b..6bc0ddb850c8 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -488,12 +488,12 @@ struct i2c_timings {
+  *      recovery. Populated internally for generic GPIO recovery.
+  * @set_scl: This sets/clears the SCL line. Mandatory for generic SCL recovery.
+  *      Populated internally for generic GPIO recovery.
+- * @get_sda: This gets current value of SDA line. Optional for generic SCL
+- *      recovery. Populated internally, if sda_gpio is a valid GPIO, for generic
+- *      GPIO recovery.
+- * @set_sda: This sets/clears the SDA line. Optional for generic SCL recovery.
+- *	Populated internally, if sda_gpio is a valid GPIO, for generic GPIO
+- *	recovery.
++ * @get_sda: This gets current value of SDA line. This or set_sda() is mandatory
++ *	for generic SCL recovery. Populated internally, if sda_gpio is a valid
++ *	GPIO, for generic GPIO recovery.
++ * @set_sda: This sets/clears the SDA line. This or get_sda() is mandatory for
++ *	generic SCL recovery. Populated internally, if sda_gpio is a valid GPIO,
++ *	for generic GPIO recovery.
+  * @prepare_recovery: This will be called before starting recovery. Platform may
+  *	configure padmux here for SDA/SCL line or something else they want.
+  * @unprepare_recovery: This will be called after completing recovery. Platform
+-- 
+2.19.0
+
diff --git a/patches/1624-i2c-recovery-refactor-recovery-function.patch b/patches/1624-i2c-recovery-refactor-recovery-function.patch
new file mode 100644
index 00000000000000..fc01611283e816
--- /dev/null
+++ b/patches/1624-i2c-recovery-refactor-recovery-function.patch
@@ -0,0 +1,68 @@
+From 637c5e7113abc07e2f1eeeb405abf04b451e9320 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 10 Jul 2018 23:42:17 +0200
+Subject: [PATCH 1624/1795] i2c: recovery: refactor recovery function
+
+After exiting the while loop, we checked if recovery was successful and
+sent a STOP to the clients. Meanwhile however, we send a STOP after
+every pulse, so it is not needed after the loop. If we move the check
+for a free bus to the end of the while loop, we can shorten and simplify
+the logic. It is still ensured that at least one STOP will be sent to
+the wire even if SDA was not stuck low.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Peter Rosin <peda@axentia.se>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 0b71026c69caa10261218528326721828d29a481)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 24 ++++++------------------
+ 1 file changed, 6 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index ea4cc8defada..7f768c99464f 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -225,9 +225,6 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 				ret = -EBUSY;
+ 				break;
+ 			}
+-			/* Break if SDA is high */
+-			if (bri->get_sda && bri->get_sda(adap))
+-				break;
+ 		}
+ 
+ 		val = !val;
+@@ -243,22 +240,13 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 		if (bri->set_sda)
+ 			bri->set_sda(adap, val);
+ 		ndelay(RECOVERY_NDELAY / 2);
+-	}
+-
+-	/* check if recovery actually succeeded */
+-	if (bri->get_sda && !bri->get_sda(adap))
+-		ret = -EBUSY;
+ 
+-	/* If all went well, send STOP for a sane bus state. */
+-	if (ret == 0 && bri->set_sda) {
+-		bri->set_scl(adap, 0);
+-		ndelay(RECOVERY_NDELAY / 2);
+-		bri->set_sda(adap, 0);
+-		ndelay(RECOVERY_NDELAY / 2);
+-		bri->set_scl(adap, 1);
+-		ndelay(RECOVERY_NDELAY / 2);
+-		bri->set_sda(adap, 1);
+-		ndelay(RECOVERY_NDELAY / 2);
++		/* Break if SDA is high */
++		if (val && bri->get_sda) {
++			ret = bri->get_sda(adap) ? 0 : -EBUSY;
++			if (ret == 0)
++				break;
++		}
+ 	}
+ 
+ 	if (bri->unprepare_recovery)
+-- 
+2.19.0
+
diff --git a/patches/1625-i2c-recovery-add-get_bus_free-callback.patch b/patches/1625-i2c-recovery-add-get_bus_free-callback.patch
new file mode 100644
index 00000000000000..4cb4110e22df2c
--- /dev/null
+++ b/patches/1625-i2c-recovery-add-get_bus_free-callback.patch
@@ -0,0 +1,100 @@
+From 4dbf3c9b62c97f070a17ee45c6006ebf79747979 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 11 Jul 2018 00:24:22 +0200
+Subject: [PATCH 1625/1795] i2c: recovery: add get_bus_free callback
+
+Some IP cores have an internal 'bus free' logic which may be more
+advanced than just checking if SDA is high. Add a separate callback to
+get this status. Filling it is optional.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 7ca5f6be7900ca753ed01c0202dc5f998a41f4ee)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 27 +++++++++++++++++++++++----
+ include/linux/i2c.h         |  3 +++
+ 2 files changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index 7f768c99464f..e48dae0dea7d 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -192,6 +192,22 @@ static void set_sda_gpio_value(struct i2c_adapter *adap, int val)
+ 	gpiod_set_value_cansleep(adap->bus_recovery_info->sda_gpiod, val);
+ }
+ 
++static int i2c_generic_bus_free(struct i2c_adapter *adap)
++{
++	struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
++	int ret = -EOPNOTSUPP;
++
++	if (bri->get_bus_free)
++		ret = bri->get_bus_free(adap);
++	else if (bri->get_sda)
++		ret = bri->get_sda(adap);
++
++	if (ret < 0)
++		return ret;
++
++	return ret ? 0 : -EBUSY;
++}
++
+ /*
+  * We are generating clock pulses. ndelay() determines durating of clk pulses.
+  * We will generate clock with rate 100 KHz and so duration of both clock levels
+@@ -203,7 +219,7 @@ static void set_sda_gpio_value(struct i2c_adapter *adap, int val)
+ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ {
+ 	struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
+-	int i = 0, val = 1, ret = 0;
++	int i = 0, val = 1, ret;
+ 
+ 	if (bri->prepare_recovery)
+ 		bri->prepare_recovery(adap);
+@@ -241,14 +257,17 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 			bri->set_sda(adap, val);
+ 		ndelay(RECOVERY_NDELAY / 2);
+ 
+-		/* Break if SDA is high */
+-		if (val && bri->get_sda) {
+-			ret = bri->get_sda(adap) ? 0 : -EBUSY;
++		if (val) {
++			ret = i2c_generic_bus_free(adap);
+ 			if (ret == 0)
+ 				break;
+ 		}
+ 	}
+ 
++	/* If we can't check bus status, assume recovery worked */
++	if (ret == -EOPNOTSUPP)
++		ret = 0;
++
+ 	if (bri->unprepare_recovery)
+ 		bri->unprepare_recovery(adap);
+ 
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index 6bc0ddb850c8..c3387435e55f 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -494,6 +494,8 @@ struct i2c_timings {
+  * @set_sda: This sets/clears the SDA line. This or get_sda() is mandatory for
+  *	generic SCL recovery. Populated internally, if sda_gpio is a valid GPIO,
+  *	for generic GPIO recovery.
++ * @get_bus_free: Returns the bus free state as seen from the IP core in case it
++ *	has a more complex internal logic than just reading SDA. Optional.
+  * @prepare_recovery: This will be called before starting recovery. Platform may
+  *	configure padmux here for SDA/SCL line or something else they want.
+  * @unprepare_recovery: This will be called after completing recovery. Platform
+@@ -510,6 +512,7 @@ struct i2c_bus_recovery_info {
+ 	void (*set_scl)(struct i2c_adapter *adap, int val);
+ 	int (*get_sda)(struct i2c_adapter *adap);
+ 	void (*set_sda)(struct i2c_adapter *adap, int val);
++	int (*get_bus_free)(struct i2c_adapter *adap);
+ 
+ 	void (*prepare_recovery)(struct i2c_adapter *adap);
+ 	void (*unprepare_recovery)(struct i2c_adapter *adap);
+-- 
+2.19.0
+
diff --git a/patches/1626-i2c-recovery-rename-variable-for-easier-understandin.patch b/patches/1626-i2c-recovery-rename-variable-for-easier-understandin.patch
new file mode 100644
index 00000000000000..db7a856ae9c6bb
--- /dev/null
+++ b/patches/1626-i2c-recovery-rename-variable-for-easier-understandin.patch
@@ -0,0 +1,74 @@
+From 6789ebcebce0a8eb71b279625acb3dd2c5aa31e7 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 11 Jul 2018 00:27:22 +0200
+Subject: [PATCH 1626/1795] i2c: recovery: rename variable for easier
+ understanding
+
+While refactoring the routine before, it occurred to me that this will
+make the code much easier to understand.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Acked-by: Peter Rosin <peda@axentia.se>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit f7ff75e2a88f9246dace2195e9dedd98df41d416)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index e48dae0dea7d..bd8e9ef048e1 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -219,12 +219,12 @@ static int i2c_generic_bus_free(struct i2c_adapter *adap)
+ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ {
+ 	struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
+-	int i = 0, val = 1, ret;
++	int i = 0, scl = 1, ret;
+ 
+ 	if (bri->prepare_recovery)
+ 		bri->prepare_recovery(adap);
+ 
+-	bri->set_scl(adap, val);
++	bri->set_scl(adap, scl);
+ 	if (bri->set_sda)
+ 		bri->set_sda(adap, 1);
+ 	ndelay(RECOVERY_NDELAY);
+@@ -233,7 +233,7 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 	 * By this time SCL is high, as we need to give 9 falling-rising edges
+ 	 */
+ 	while (i++ < RECOVERY_CLK_CNT * 2) {
+-		if (val) {
++		if (scl) {
+ 			/* SCL shouldn't be low here */
+ 			if (!bri->get_scl(adap)) {
+ 				dev_err(&adap->dev,
+@@ -243,8 +243,8 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 			}
+ 		}
+ 
+-		val = !val;
+-		bri->set_scl(adap, val);
++		scl = !scl;
++		bri->set_scl(adap, scl);
+ 
+ 		/*
+ 		 * If we can set SDA, we will always create STOP here to ensure
+@@ -254,10 +254,10 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 		 */
+ 		ndelay(RECOVERY_NDELAY / 2);
+ 		if (bri->set_sda)
+-			bri->set_sda(adap, val);
++			bri->set_sda(adap, scl);
+ 		ndelay(RECOVERY_NDELAY / 2);
+ 
+-		if (val) {
++		if (scl) {
+ 			ret = i2c_generic_bus_free(adap);
+ 			if (ret == 0)
+ 				break;
+-- 
+2.19.0
+
diff --git a/patches/1627-i2c-recovery-make-pin-init-look-like-STOP.patch b/patches/1627-i2c-recovery-make-pin-init-look-like-STOP.patch
new file mode 100644
index 00000000000000..c460ca2b10c76d
--- /dev/null
+++ b/patches/1627-i2c-recovery-make-pin-init-look-like-STOP.patch
@@ -0,0 +1,62 @@
+From 6d04466f49f54a4f3ccb6a358d4ee92bcb14556d Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Tue, 17 Jul 2018 11:00:05 +0200
+Subject: [PATCH 1627/1795] i2c: recovery: make pin init look like STOP
+
+When we initialize the pins, make sure it looks like STOP by dividing
+the delay into halves. It shouldn't matter because SDA is expected to be
+held low by a device, but for super-safety, let's do it.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Peter Rosin <peda@axentia.se>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit c4ae05b976b2a67fb24f35d21731b4da2c235bbf)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/i2c-core-base.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
+index bd8e9ef048e1..50b8c9cbd139 100644
+--- a/drivers/i2c/i2c-core-base.c
++++ b/drivers/i2c/i2c-core-base.c
+@@ -224,10 +224,17 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 	if (bri->prepare_recovery)
+ 		bri->prepare_recovery(adap);
+ 
++	/*
++	 * If we can set SDA, we will always create a STOP to ensure additional
++	 * pulses will do no harm. This is achieved by letting SDA follow SCL
++	 * half a cycle later. Check the 'incomplete_write_byte' fault injector
++	 * for details.
++	 */
+ 	bri->set_scl(adap, scl);
++	ndelay(RECOVERY_NDELAY / 2);
+ 	if (bri->set_sda)
+-		bri->set_sda(adap, 1);
+-	ndelay(RECOVERY_NDELAY);
++		bri->set_sda(adap, scl);
++	ndelay(RECOVERY_NDELAY / 2);
+ 
+ 	/*
+ 	 * By this time SCL is high, as we need to give 9 falling-rising edges
+@@ -245,13 +252,7 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
+ 
+ 		scl = !scl;
+ 		bri->set_scl(adap, scl);
+-
+-		/*
+-		 * If we can set SDA, we will always create STOP here to ensure
+-		 * the additional pulses will do no harm. This is achieved by
+-		 * letting SDA follow SCL half a cycle later. Check the
+-		 * 'incomplete_write_byte' fault injector for details.
+-		 */
++		/* Creating STOP again, see above */
+ 		ndelay(RECOVERY_NDELAY / 2);
+ 		if (bri->set_sda)
+ 			bri->set_sda(adap, scl);
+-- 
+2.19.0
+
diff --git a/patches/1628-i2c-rcar-use-the-new-get_bus_free-callback.patch b/patches/1628-i2c-rcar-use-the-new-get_bus_free-callback.patch
new file mode 100644
index 00000000000000..57d708edd9864a
--- /dev/null
+++ b/patches/1628-i2c-rcar-use-the-new-get_bus_free-callback.patch
@@ -0,0 +1,77 @@
+From 1cf216006d6a72dfd6cb7c047a7411fb0790bcd7 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 11 Jul 2018 00:24:23 +0200
+Subject: [PATCH 1628/1795] i2c: rcar: use the new get_bus_free callback
+
+To break out of recovery as early as possible, feed back the bus_free
+logic state.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 4fe10de535ead365351d49e0ff625769b08f6eca)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 41159ac2a320..e9fa7cdb83f0 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -183,8 +183,6 @@ static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
+ 	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
+ };
+ 
+-/* No get_sda, because the HW only reports its bus free logic, not SDA itself */
+-
+ static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
+ {
+ 	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
+@@ -197,10 +195,19 @@ static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
+ 	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
+ };
+ 
++static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
++{
++	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
++
++	return !(rcar_i2c_read(priv, ICMCR) & FSDA);
++
++};
++
+ static struct i2c_bus_recovery_info rcar_i2c_bri = {
+ 	.get_scl = rcar_i2c_get_scl,
+ 	.set_scl = rcar_i2c_set_scl,
+ 	.set_sda = rcar_i2c_set_sda,
++	.get_bus_free = rcar_i2c_get_bus_free,
+ 	.recover_bus = i2c_generic_scl_recovery,
+ };
+ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
+@@ -215,7 +222,7 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
+ 
+ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
+ {
+-	int i, ret;
++	int i;
+ 
+ 	for (i = 0; i < LOOP_TIMEOUT; i++) {
+ 		/* make sure that bus is not busy */
+@@ -226,13 +233,7 @@ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
+ 
+ 	/* Waiting did not help, try to recover */
+ 	priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
+-	ret = i2c_recover_bus(&priv->adap);
+-
+-	/* No failure when recovering, so check bus busy bit again */
+-	if (ret == 0)
+-		ret = (rcar_i2c_read(priv, ICMCR) & FSDA) ? -EBUSY : 0;
+-
+-	return ret;
++	return i2c_recover_bus(&priv->adap);
+ }
+ 
+ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
+-- 
+2.19.0
+
diff --git a/patches/1629-clk-socfpga-stratix10-add-clock-driver-for-Stratix10.patch b/patches/1629-clk-socfpga-stratix10-add-clock-driver-for-Stratix10.patch
new file mode 100644
index 00000000000000..456ae85d3ab274
--- /dev/null
+++ b/patches/1629-clk-socfpga-stratix10-add-clock-driver-for-Stratix10.patch
@@ -0,0 +1,962 @@
+From a26975acd9757c633f678e3bd67ff7268ac5e97f Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 21 Mar 2018 09:20:12 -0500
+Subject: [PATCH 1629/1795] clk: socfpga: stratix10: add clock driver for
+ Stratix10 platform
+
+Add a clock driver for the Stratix10 SoC. The driver is similar to the
+Cyclone5/Arria10 platforms, with the exception that this driver only uses
+one single clock binding.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+(cherry picked from commit 07afb8db7340f9b6051a26c5c28f2ce74148f6b5)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/Makefile                 |   1 +
+ drivers/clk/socfpga/Makefile         |   9 +-
+ drivers/clk/socfpga/clk-gate-s10.c   | 125 ++++++++++
+ drivers/clk/socfpga/clk-periph-s10.c | 149 ++++++++++++
+ drivers/clk/socfpga/clk-pll-s10.c    | 146 ++++++++++++
+ drivers/clk/socfpga/clk-s10.c        | 345 +++++++++++++++++++++++++++
+ drivers/clk/socfpga/clk.h            |   4 +
+ drivers/clk/socfpga/stratix10-clk.h  |  80 +++++++
+ 8 files changed, 854 insertions(+), 5 deletions(-)
+ create mode 100644 drivers/clk/socfpga/clk-gate-s10.c
+ create mode 100644 drivers/clk/socfpga/clk-periph-s10.c
+ create mode 100644 drivers/clk/socfpga/clk-pll-s10.c
+ create mode 100644 drivers/clk/socfpga/clk-s10.c
+ create mode 100644 drivers/clk/socfpga/stratix10-clk.h
+
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index f7f761b02bed..9b9267af1d2c 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -86,6 +86,7 @@ obj-$(CONFIG_ARCH_SIRF)			+= sirf/
+ obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
+ obj-$(CONFIG_PLAT_SPEAR)		+= spear/
+ obj-$(CONFIG_ARCH_STI)			+= st/
++obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
+ obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/
+ obj-$(CONFIG_ARCH_SUNXI)		+= sunxi-ng/
+ obj-$(CONFIG_ARCH_TEGRA)		+= tegra/
+diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
+index 9146c20fe21f..ce5aa7802eb8 100644
+--- a/drivers/clk/socfpga/Makefile
++++ b/drivers/clk/socfpga/Makefile
+@@ -1,6 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+-obj-y += clk.o
+-obj-y += clk-gate.o
+-obj-y += clk-pll.o
+-obj-y += clk-periph.o
+-obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
++obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
++obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
++obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
++obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
+new file mode 100644
+index 000000000000..eee2d48ab656
+--- /dev/null
++++ b/drivers/clk/socfpga/clk-gate-s10.c
+@@ -0,0 +1,125 @@
++// SPDX-License-Identifier:	GPL-2.0
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++#include <linux/clk-provider.h>
++#include <linux/slab.h>
++#include "stratix10-clk.h"
++#include "clk.h"
++
++#define SOCFPGA_CS_PDBG_CLK	"cs_pdbg_clk"
++#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
++
++static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
++						  unsigned long parent_rate)
++{
++	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
++	u32 div = 1, val;
++
++	if (socfpgaclk->fixed_div) {
++		div = socfpgaclk->fixed_div;
++	} else if (socfpgaclk->div_reg) {
++		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
++		val &= GENMASK(socfpgaclk->width - 1, 0);
++		div = (1 << val);
++	}
++	return parent_rate / div;
++}
++
++static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
++						  unsigned long parent_rate)
++{
++	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
++	u32 div = 1, val;
++
++	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
++	val &= GENMASK(socfpgaclk->width - 1, 0);
++	div = (1 << val);
++	div = div ? 4 : 1;
++
++	return parent_rate / div;
++}
++
++static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
++{
++	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
++	u32 mask;
++	u8 parent = 0;
++
++	if (socfpgaclk->bypass_reg) {
++		mask = (0x1 << socfpgaclk->bypass_shift);
++		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
++			  socfpgaclk->bypass_shift);
++	}
++	return parent;
++}
++
++static struct clk_ops gateclk_ops = {
++	.recalc_rate = socfpga_gate_clk_recalc_rate,
++	.get_parent = socfpga_gate_get_parent,
++};
++
++static const struct clk_ops dbgclk_ops = {
++	.recalc_rate = socfpga_dbg_clk_recalc_rate,
++	.get_parent = socfpga_gate_get_parent,
++};
++
++struct clk *s10_register_gate(const char *name, const char *parent_name,
++			      const char * const *parent_names,
++			      u8 num_parents, unsigned long flags,
++			      void __iomem *regbase, unsigned long gate_reg,
++			      unsigned long gate_idx, unsigned long div_reg,
++			      unsigned long div_offset, u8 div_width,
++			      unsigned long bypass_reg, u8 bypass_shift,
++			      u8 fixed_div)
++{
++	struct clk *clk;
++	struct socfpga_gate_clk *socfpga_clk;
++	struct clk_init_data init;
++
++	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
++	if (!socfpga_clk)
++		return NULL;
++
++	socfpga_clk->hw.reg = regbase + gate_reg;
++	socfpga_clk->hw.bit_idx = gate_idx;
++
++	gateclk_ops.enable = clk_gate_ops.enable;
++	gateclk_ops.disable = clk_gate_ops.disable;
++
++	socfpga_clk->fixed_div = fixed_div;
++
++	if (div_reg)
++		socfpga_clk->div_reg = regbase + div_reg;
++	else
++		socfpga_clk->div_reg = NULL;
++
++	socfpga_clk->width = div_width;
++	socfpga_clk->shift = div_offset;
++
++	if (bypass_reg)
++		socfpga_clk->bypass_reg = regbase + bypass_reg;
++	else
++		socfpga_clk->bypass_reg = NULL;
++	socfpga_clk->bypass_shift = bypass_shift;
++
++	if (streq(name, "cs_pdbg_clk"))
++		init.ops = &dbgclk_ops;
++	else
++		init.ops = &gateclk_ops;
++
++	init.name = name;
++	init.flags = flags;
++
++	init.num_parents = num_parents;
++	init.parent_names = parent_names ? parent_names : &parent_name;
++	socfpga_clk->hw.hw.init = &init;
++
++	clk = clk_register(NULL, &socfpga_clk->hw.hw);
++	if (WARN_ON(IS_ERR(clk))) {
++		kfree(socfpga_clk);
++		return NULL;
++	}
++
++	return clk;
++}
+diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
+new file mode 100644
+index 000000000000..568f59b58ddf
+--- /dev/null
++++ b/drivers/clk/socfpga/clk-periph-s10.c
+@@ -0,0 +1,149 @@
++// SPDX-License-Identifier:	GPL-2.0
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++
++#include "stratix10-clk.h"
++#include "clk.h"
++
++#define CLK_MGR_FREE_SHIFT		16
++#define CLK_MGR_FREE_MASK		0x7
++#define SWCTRLBTCLKSEN_SHIFT		8
++
++#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
++
++static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
++					     unsigned long parent_rate)
++{
++	struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
++	unsigned long div = 1;
++	u32 val;
++
++	val = readl(socfpgaclk->hw.reg);
++	val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
++	parent_rate /= val;
++
++	return parent_rate / div;
++}
++
++static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
++					     unsigned long parent_rate)
++{
++	struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
++	unsigned long div = 1;
++
++	if (socfpgaclk->fixed_div) {
++		div = socfpgaclk->fixed_div;
++	} else {
++		if (!socfpgaclk->bypass_reg)
++			div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
++	}
++
++	return parent_rate / div;
++}
++
++static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
++{
++	struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
++	u32 clk_src, mask;
++	u8 parent;
++
++	if (socfpgaclk->bypass_reg) {
++		mask = (0x1 << socfpgaclk->bypass_shift);
++		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
++			   socfpgaclk->bypass_shift);
++	} else {
++		clk_src = readl(socfpgaclk->hw.reg);
++		parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
++			CLK_MGR_FREE_MASK;
++	}
++	return parent;
++}
++
++static const struct clk_ops peri_c_clk_ops = {
++	.recalc_rate = clk_peri_c_clk_recalc_rate,
++	.get_parent = clk_periclk_get_parent,
++};
++
++static const struct clk_ops peri_cnt_clk_ops = {
++	.recalc_rate = clk_peri_cnt_clk_recalc_rate,
++	.get_parent = clk_periclk_get_parent,
++};
++
++struct clk *s10_register_periph(const char *name, const char *parent_name,
++				const char * const *parent_names,
++				u8 num_parents, unsigned long flags,
++				void __iomem *reg, unsigned long offset)
++{
++	struct clk *clk;
++	struct socfpga_periph_clk *periph_clk;
++	struct clk_init_data init;
++
++	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
++	if (WARN_ON(!periph_clk))
++		return NULL;
++
++	periph_clk->hw.reg = reg + offset;
++
++	init.name = name;
++	init.ops = &peri_c_clk_ops;
++	init.flags = flags;
++
++	init.num_parents = num_parents;
++	init.parent_names = parent_names ? parent_names : &parent_name;
++
++	periph_clk->hw.hw.init = &init;
++
++	clk = clk_register(NULL, &periph_clk->hw.hw);
++	if (WARN_ON(IS_ERR(clk))) {
++		kfree(periph_clk);
++		return NULL;
++	}
++	return clk;
++}
++
++struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
++				    const char * const *parent_names,
++				    u8 num_parents, unsigned long flags,
++				    void __iomem *regbase, unsigned long offset,
++				    u8 fixed_divider, unsigned long bypass_reg,
++				    unsigned long bypass_shift)
++{
++	struct clk *clk;
++	struct socfpga_periph_clk *periph_clk;
++	struct clk_init_data init;
++
++	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
++	if (WARN_ON(!periph_clk))
++		return NULL;
++
++	if (offset)
++		periph_clk->hw.reg = regbase + offset;
++	else
++		periph_clk->hw.reg = NULL;
++
++	if (bypass_reg)
++		periph_clk->bypass_reg = regbase + bypass_reg;
++	else
++		periph_clk->bypass_reg = NULL;
++	periph_clk->bypass_shift = bypass_shift;
++	periph_clk->fixed_div = fixed_divider;
++
++	init.name = name;
++	init.ops = &peri_cnt_clk_ops;
++	init.flags = flags;
++
++	init.num_parents = num_parents;
++	init.parent_names = parent_names ? parent_names : &parent_name;
++
++	periph_clk->hw.hw.init = &init;
++
++	clk = clk_register(NULL, &periph_clk->hw.hw);
++	if (WARN_ON(IS_ERR(clk))) {
++		kfree(periph_clk);
++		return NULL;
++	}
++	return clk;
++}
+diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
+new file mode 100644
+index 000000000000..2d5d8b43727e
+--- /dev/null
++++ b/drivers/clk/socfpga/clk-pll-s10.c
+@@ -0,0 +1,146 @@
++// SPDX-License-Identifier:	GPL-2.0
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++
++#include "stratix10-clk.h"
++#include "clk.h"
++
++/* Clock Manager offsets */
++#define CLK_MGR_PLL_CLK_SRC_SHIFT	16
++#define CLK_MGR_PLL_CLK_SRC_MASK	0x3
++
++/* PLL Clock enable bits */
++#define SOCFPGA_PLL_POWER		0
++#define SOCFPGA_PLL_RESET_MASK		0x2
++#define SOCFPGA_PLL_REFDIV_MASK		0x00003F00
++#define SOCFPGA_PLL_REFDIV_SHIFT	8
++#define SOCFPGA_PLL_MDIV_MASK		0xFF000000
++#define SOCFPGA_PLL_MDIV_SHIFT		24
++#define SWCTRLBTCLKSEL_MASK		0x200
++#define SWCTRLBTCLKSEL_SHIFT		9
++
++#define SOCFPGA_BOOT_CLK		"boot_clk"
++
++#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
++
++static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
++					 unsigned long parent_rate)
++{
++	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
++	unsigned long mdiv;
++	unsigned long refdiv;
++	unsigned long reg;
++	unsigned long long vco_freq;
++
++	/* read VCO1 reg for numerator and denominator */
++	reg = readl(socfpgaclk->hw.reg);
++	refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
++	vco_freq = (unsigned long long)parent_rate / refdiv;
++
++	/* Read mdiv and fdiv from the fdbck register */
++	reg = readl(socfpgaclk->hw.reg + 0x4);
++	mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
++	vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
++
++	return (unsigned long)vco_freq;
++}
++
++static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
++					 unsigned long parent_rate)
++{
++	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
++	u32 div = 1;
++
++	div = ((readl(socfpgaclk->hw.reg) &
++		SWCTRLBTCLKSEL_MASK) >>
++		SWCTRLBTCLKSEL_SHIFT);
++	div += 1;
++	return parent_rate /= div;
++}
++
++
++static u8 clk_pll_get_parent(struct clk_hw *hwclk)
++{
++	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
++	u32 pll_src;
++
++	pll_src = readl(socfpgaclk->hw.reg);
++	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
++		CLK_MGR_PLL_CLK_SRC_MASK;
++}
++
++static u8 clk_boot_get_parent(struct clk_hw *hwclk)
++{
++	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
++	u32 pll_src;
++
++	pll_src = readl(socfpgaclk->hw.reg);
++	return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
++		SWCTRLBTCLKSEL_MASK;
++}
++
++static int clk_pll_prepare(struct clk_hw *hwclk)
++{
++	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
++	u32 reg;
++
++	/* Bring PLL out of reset */
++	reg = readl(socfpgaclk->hw.reg);
++	reg |= SOCFPGA_PLL_RESET_MASK;
++	writel(reg, socfpgaclk->hw.reg);
++
++	return 0;
++}
++
++static struct clk_ops clk_pll_ops = {
++	.recalc_rate = clk_pll_recalc_rate,
++	.get_parent = clk_pll_get_parent,
++	.prepare = clk_pll_prepare,
++};
++
++static struct clk_ops clk_boot_ops = {
++	.recalc_rate = clk_boot_clk_recalc_rate,
++	.get_parent = clk_boot_get_parent,
++	.prepare = clk_pll_prepare,
++};
++
++struct clk *s10_register_pll(const char *name, const char * const *parent_names,
++				    u8 num_parents, unsigned long flags,
++				    void __iomem *reg, unsigned long offset)
++{
++	struct clk *clk;
++	struct socfpga_pll *pll_clk;
++	struct clk_init_data init;
++
++	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
++	if (WARN_ON(!pll_clk))
++		return NULL;
++
++	pll_clk->hw.reg = reg + offset;
++
++	if (streq(name, SOCFPGA_BOOT_CLK))
++		init.ops = &clk_boot_ops;
++	else
++		init.ops = &clk_pll_ops;
++
++	init.name = name;
++	init.flags = flags;
++
++	init.num_parents = num_parents;
++	init.parent_names = parent_names;
++	pll_clk->hw.hw.init = &init;
++
++	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
++	clk_pll_ops.enable = clk_gate_ops.enable;
++	clk_pll_ops.disable = clk_gate_ops.disable;
++
++	clk = clk_register(NULL, &pll_clk->hw.hw);
++	if (WARN_ON(IS_ERR(clk))) {
++		kfree(pll_clk);
++		return NULL;
++	}
++	return clk;
++}
+diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
+new file mode 100644
+index 000000000000..3a11c382a663
+--- /dev/null
++++ b/drivers/clk/socfpga/clk-s10.c
+@@ -0,0 +1,345 @@
++// SPDX-License-Identifier:	GPL-2.0
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++
++#include <dt-bindings/clock/stratix10-clock.h>
++
++#include "stratix10-clk.h"
++
++static const char * const pll_mux[] = { "osc1", "cb_intosc_hs_div2_clk",
++					"f2s_free_clk",};
++static const char * const cntr_mux[] = { "main_pll", "periph_pll",
++					 "osc1", "cb_intosc_hs_div2_clk",
++					 "f2s_free_clk"};
++static const char * const boot_mux[] = { "osc1", "cb_intosc_hs_div2_clk",};
++
++static const char * const noc_free_mux[] = {"main_noc_base_clk",
++					    "peri_noc_base_clk",
++					    "osc1", "cb_intosc_hs_div2_clk",
++					    "f2s_free_clk"};
++
++static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
++static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
++static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
++static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
++static const char * const sdmmc_free_mux[] = {"peri_sdmmc_clk", "boot_clk"};
++static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
++static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
++static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
++
++static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
++static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
++static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
++
++/* clocks in AO (always on) controller */
++static const struct stratix10_pll_clock s10_pll_clks[] = {
++	{ STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
++	  0x0},
++	{ STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
++	  0, 0x74},
++	{ STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
++	  0, 0xe4},
++};
++
++static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
++	{ STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
++	{ STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
++	{ STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
++	  0xF4},
++	{ STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
++	  0xF8},
++};
++
++static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
++	{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	   0, 0x48, 0, 0, 0},
++	{ STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
++	  0, 0x4C, 0, 0, 0},
++	{ STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x50, 0, 0, 0},
++	{ STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x54, 0, 0, 0},
++	{ STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x58, 0, 0, 0},
++	{ STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x5C, 0, 0, 0},
++	{ STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x60, 0, 0, 0},
++	{ STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0x64, 0, 0, 0},
++	{ STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x68, 0, 0, 0},
++	{ STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
++	  0x6C, 0, 0, 0},
++	{ STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xBC, 0, 0, 0},
++	{ STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xC0, 0, 0, 0},
++	{ STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xC4, 0, 0, 0},
++	{ STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xC8, 0, 0, 0},
++	{ STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xCC, 0, 0, 0},
++	{ STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
++	  0xD0, 0, 0, 0},
++	{ STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	  0, 0xD4, 0, 0, 0},
++	{ STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
++	  0xD8, 0, 0, 0},
++	{ STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
++	  0, 4, 0, 0},
++	{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
++	  0, 0, 0, 0x3C, 1},
++	{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
++	  0, 0, 4, 0xB0, 0},
++	{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
++	  0, 0, 4, 0xB0, 1},
++	{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
++	  ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
++	{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
++	  ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
++	{ STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
++	  ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
++	{ STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
++	  ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
++	{ STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
++	  ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
++};
++
++static const struct stratix10_gate_clock s10_gate_clks[] = {
++	{ STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
++	  0, 0, 0, 0, 0x3C, 0, 0},
++	{ STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
++	  0, 0, 0, 0, 0, 0, 4},
++	{ STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
++	  0, 0, 0, 0, 0, 0, 2},
++	{ STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30,
++	  1, 0x70, 0, 2, 0, 0, 0},
++	{ STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30,
++	  2, 0x70, 8, 2, 0, 0, 0},
++	{ STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30,
++	  3, 0x70, 16, 2, 0, 0, 0},
++	{ STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30,
++	  4, 0x70, 24, 2, 0, 0, 0},
++	{ STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30,
++	  4, 0x70, 26, 2, 0, 0, 0},
++	{ STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
++	  4, 0x70, 28, 1, 0, 0, 0},
++	{ STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30,
++	  5, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
++	  6, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
++	  0, 0, 0, 0, 0xDC, 26, 0},
++	{ STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
++	  1, 0, 0, 0, 0xDC, 27, 0},
++	{ STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
++	  2, 0, 0, 0, 0xDC, 28, 0},
++	{ STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4,
++	  3, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4,
++	  4, 0xE0, 0, 16, 0, 0, 0},
++	{ STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4,
++	  5, 0, 0, 0, 0, 0, 4},
++	{ STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4,
++	  6, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4,
++	  7, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
++	  8, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
++	  9, 0, 0, 0, 0, 0, 0},
++	{ STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4,
++	  10, 0, 0, 0, 0, 0, 0},
++};
++
++static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
++				    int nums, struct stratix10_clock_data *data)
++{
++	struct clk *clk;
++	void __iomem *base = data->base;
++	int i;
++
++	for (i = 0; i < nums; i++) {
++		clk = s10_register_periph(clks[i].name, clks[i].parent_name,
++					  clks[i].parent_names, clks[i].num_parents,
++					  clks[i].flags, base, clks[i].offset);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n",
++			       __func__, clks[i].name);
++			continue;
++		}
++		data->clk_data.clks[clks[i].id] = clk;
++	}
++	return 0;
++}
++
++static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
++				      int nums, struct stratix10_clock_data *data)
++{
++	struct clk *clk;
++	void __iomem *base = data->base;
++	int i;
++
++	for (i = 0; i < nums; i++) {
++		clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
++					      clks[i].parent_names,
++					      clks[i].num_parents,
++					      clks[i].flags, base,
++					      clks[i].offset,
++					      clks[i].fixed_divider,
++					      clks[i].bypass_reg,
++					      clks[i].bypass_shift);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n",
++			       __func__, clks[i].name);
++			continue;
++		}
++		data->clk_data.clks[clks[i].id] = clk;
++	}
++
++	return 0;
++}
++
++static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
++				 int nums, struct stratix10_clock_data *data)
++{
++	struct clk *clk;
++	void __iomem *base = data->base;
++	int i;
++
++	for (i = 0; i < nums; i++) {
++		clk = s10_register_gate(clks[i].name, clks[i].parent_name,
++					clks[i].parent_names,
++					clks[i].num_parents,
++					clks[i].flags, base,
++					clks[i].gate_reg,
++					clks[i].gate_idx, clks[i].div_reg,
++					clks[i].div_offset, clks[i].div_width,
++					clks[i].bypass_reg,
++					clks[i].bypass_shift,
++					clks[i].fixed_div);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n",
++			       __func__, clks[i].name);
++			continue;
++		}
++		data->clk_data.clks[clks[i].id] = clk;
++	}
++
++	return 0;
++}
++
++static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
++				 int nums, struct stratix10_clock_data *data)
++{
++	struct clk *clk;
++	void __iomem *base = data->base;
++	int i;
++
++	for (i = 0; i < nums; i++) {
++		clk = s10_register_pll(clks[i].name, clks[i].parent_names,
++				    clks[i].num_parents,
++				    clks[i].flags, base,
++				    clks[i].offset);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n",
++			       __func__, clks[i].name);
++			continue;
++		}
++		data->clk_data.clks[clks[i].id] = clk;
++	}
++
++	return 0;
++}
++
++static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
++						    int nr_clks)
++{
++	struct stratix10_clock_data *clk_data;
++	struct clk **clk_table;
++	void __iomem *base;
++
++	base = of_iomap(np, 0);
++	if (!base) {
++		pr_err("%s: failed to map clock registers\n", __func__);
++		goto err;
++	}
++
++	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
++	if (!clk_data)
++		goto err;
++
++	clk_data->base = base;
++	clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
++	if (!clk_table)
++		goto err_data;
++
++	clk_data->clk_data.clks = clk_table;
++	clk_data->clk_data.clk_num = nr_clks;
++	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
++	return clk_data;
++
++err_data:
++	kfree(clk_data);
++err:
++	return NULL;
++}
++
++static int s10_clkmgr_init(struct device_node *np)
++{
++	struct stratix10_clock_data *clk_data;
++
++	clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
++	if (!clk_data)
++		return -ENOMEM;
++
++	s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
++
++	s10_clk_register_c_perip(s10_main_perip_c_clks,
++				 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
++
++	s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
++				   ARRAY_SIZE(s10_main_perip_cnt_clks),
++				   clk_data);
++
++	s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
++			      clk_data);
++	return 0;
++}
++
++static int s10_clkmgr_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++
++	s10_clkmgr_init(np);
++
++	return 0;
++}
++
++static const struct of_device_id stratix10_clkmgr_match_table[] = {
++	{ .compatible = "intel,stratix10-clkmgr",
++	  .data = s10_clkmgr_init },
++	{ }
++};
++
++static struct platform_driver stratix10_clkmgr_driver = {
++	.probe		= s10_clkmgr_probe,
++	.driver		= {
++		.name	= "stratix10-clkmgr",
++		.of_match_table = stratix10_clkmgr_match_table,
++	},
++};
++
++static int __init s10_clk_init(void)
++{
++	return platform_driver_register(&stratix10_clkmgr_driver);
++}
++core_initcall(s10_clk_init);
+diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
+index 9cf1230115b1..26c3a265cf78 100644
+--- a/drivers/clk/socfpga/clk.h
++++ b/drivers/clk/socfpga/clk.h
+@@ -54,9 +54,11 @@ struct socfpga_gate_clk {
+ 	char *parent_name;
+ 	u32 fixed_div;
+ 	void __iomem *div_reg;
++	void __iomem *bypass_reg;
+ 	struct regmap *sys_mgr_base_addr;
+ 	u32 width;	/* only valid if div_reg != 0 */
+ 	u32 shift;	/* only valid if div_reg != 0 */
++	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
+ 	u32 clk_phase[2];
+ };
+ 
+@@ -65,8 +67,10 @@ struct socfpga_periph_clk {
+ 	char *parent_name;
+ 	u32 fixed_div;
+ 	void __iomem *div_reg;
++	void __iomem *bypass_reg;
+ 	u32 width;      /* only valid if div_reg != 0 */
+ 	u32 shift;      /* only valid if div_reg != 0 */
++	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
+ };
+ 
+ #endif /* SOCFPGA_CLK_H */
+diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
+new file mode 100644
+index 000000000000..e8e121907952
+--- /dev/null
++++ b/drivers/clk/socfpga/stratix10-clk.h
+@@ -0,0 +1,80 @@
++/* SPDX-License-Identifier:    GPL-2.0 */
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++
++#ifndef	__STRATIX10_CLK_H
++#define	__STRATIX10_CLK_H
++
++struct stratix10_clock_data {
++	struct clk_onecell_data	clk_data;
++	void __iomem		*base;
++};
++
++struct stratix10_pll_clock {
++	unsigned int		id;
++	const char		*name;
++	const char		*const *parent_names;
++	u8			num_parents;
++	unsigned long		flags;
++	unsigned long		offset;
++};
++
++struct stratix10_perip_c_clock {
++	unsigned int		id;
++	const char		*name;
++	const char		*parent_name;
++	const char		*const *parent_names;
++	u8			num_parents;
++	unsigned long		flags;
++	unsigned long		offset;
++};
++
++struct stratix10_perip_cnt_clock {
++	unsigned int		id;
++	const char		*name;
++	const char		*parent_name;
++	const char		*const *parent_names;
++	u8			num_parents;
++	unsigned long		flags;
++	unsigned long		offset;
++	u8			fixed_divider;
++	unsigned long		bypass_reg;
++	unsigned long		bypass_shift;
++};
++
++struct stratix10_gate_clock {
++	unsigned int		id;
++	const char		*name;
++	const char		*parent_name;
++	const char		*const *parent_names;
++	u8			num_parents;
++	unsigned long		flags;
++	unsigned long		gate_reg;
++	u8			gate_idx;
++	unsigned long		div_reg;
++	u8			div_offset;
++	u8			div_width;
++	unsigned long		bypass_reg;
++	u8			bypass_shift;
++	u8			fixed_div;
++};
++
++struct clk *s10_register_pll(const char *, const char *const *, u8,
++			     unsigned long, void __iomem *, unsigned long);
++
++struct clk *s10_register_periph(const char *, const char *,
++				const char * const *, u8, unsigned long,
++				void __iomem *, unsigned long);
++struct clk *s10_register_cnt_periph(const char *, const char *,
++				    const char * const *, u8,
++				    unsigned long, void __iomem *,
++				    unsigned long, u8, unsigned long,
++				    unsigned long);
++struct clk *s10_register_gate(const char *, const char *,
++			      const char * const *, u8,
++			      unsigned long, void __iomem *,
++			      unsigned long, unsigned long,
++			      unsigned long, unsigned long, u8,
++			      unsigned long, u8, u8);
++#endif	/* __STRATIX10_CLK_H */
+-- 
+2.19.0
+
diff --git a/patches/1630-clk-socfpga-stratix10-use-platform-driver-APIs.patch b/patches/1630-clk-socfpga-stratix10-use-platform-driver-APIs.patch
new file mode 100644
index 00000000000000..b1e371159d9ca9
--- /dev/null
+++ b/patches/1630-clk-socfpga-stratix10-use-platform-driver-APIs.patch
@@ -0,0 +1,102 @@
+From 430ecbe90173baba89ff55910e9143eb04f34e00 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 2 May 2018 09:28:32 -0500
+Subject: [PATCH 1630/1795] clk: socfpga: stratix10: use platform driver APIs
+
+Use platform driver APIs to map memory so that it will automatically free
+the memory in case of errors.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+[sboyd@kernel.org: Return -ENOMEM error pointers, check for error
+pointer at call site]
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+
+(cherry picked from commit 1ace0dfd754feef171e9209c8266efb198f5c19c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/socfpga/clk-s10.c | 39 +++++++++++++++--------------------
+ 1 file changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
+index 3a11c382a663..1ffe3f05f2fc 100644
+--- a/drivers/clk/socfpga/clk-s10.c
++++ b/drivers/clk/socfpga/clk-s10.c
+@@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
+ 	return 0;
+ }
+ 
+-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
++static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
+ 						    int nr_clks)
+ {
++	struct device_node *np = pdev->dev.of_node;
++	struct device *dev = &pdev->dev;
+ 	struct stratix10_clock_data *clk_data;
+ 	struct clk **clk_table;
++	struct resource *res;
+ 	void __iomem *base;
+ 
+-	base = of_iomap(np, 0);
+-	if (!base) {
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(base)) {
+ 		pr_err("%s: failed to map clock registers\n", __func__);
+-		goto err;
++		return ERR_CAST(base);
+ 	}
+ 
+-	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
++	clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+ 	if (!clk_data)
+-		goto err;
++		return ERR_PTR(-ENOMEM);
+ 
+ 	clk_data->base = base;
+-	clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
++	clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
+ 	if (!clk_table)
+-		goto err_data;
++		return ERR_PTR(-ENOMEM);
+ 
+ 	clk_data->clk_data.clks = clk_table;
+ 	clk_data->clk_data.clk_num = nr_clks;
+ 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
+ 	return clk_data;
+-
+-err_data:
+-	kfree(clk_data);
+-err:
+-	return NULL;
+ }
+ 
+-static int s10_clkmgr_init(struct device_node *np)
++static int s10_clkmgr_init(struct platform_device *pdev)
+ {
+ 	struct stratix10_clock_data *clk_data;
+ 
+-	clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
+-	if (!clk_data)
+-		return -ENOMEM;
++	clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
++	if (IS_ERR(clk_data))
++		return PTR_ERR(clk_data);
+ 
+ 	s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
+ 
+@@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
+ 
+ static int s10_clkmgr_probe(struct platform_device *pdev)
+ {
+-	struct device_node *np = pdev->dev.of_node;
+-
+-	s10_clkmgr_init(np);
+-
+-	return 0;
++	return	s10_clkmgr_init(pdev);
+ }
+ 
+ static const struct of_device_id stratix10_clkmgr_match_table[] = {
+-- 
+2.19.0
+
diff --git a/patches/1631-clk-socfpga-stratix10-suppress-unbinding-platform-s-.patch b/patches/1631-clk-socfpga-stratix10-suppress-unbinding-platform-s-.patch
new file mode 100644
index 00000000000000..ee3823bca1f73a
--- /dev/null
+++ b/patches/1631-clk-socfpga-stratix10-suppress-unbinding-platform-s-.patch
@@ -0,0 +1,32 @@
+From b3841ad35d269824002312274e011f0bb276dbf0 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 2 May 2018 09:28:33 -0500
+Subject: [PATCH 1631/1795] clk: socfpga: stratix10: suppress unbinding
+ platform's clock driver
+
+The Stratix10 clock driver is essential to system operation, so their
+removal should never happen.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+(cherry picked from commit a61315473a93e2d36bca276f9b03738936d94a1c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/socfpga/clk-s10.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
+index 1ffe3f05f2fc..72714633e39c 100644
+--- a/drivers/clk/socfpga/clk-s10.c
++++ b/drivers/clk/socfpga/clk-s10.c
+@@ -329,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
+ 	.probe		= s10_clkmgr_probe,
+ 	.driver		= {
+ 		.name	= "stratix10-clkmgr",
++		.suppress_bind_attrs = true,
+ 		.of_match_table = stratix10_clkmgr_match_table,
+ 	},
+ };
+-- 
+2.19.0
+
diff --git a/patches/1632-clk-socfpga-stratix10-fix-the-parents-of-mpu_free_cl.patch b/patches/1632-clk-socfpga-stratix10-fix-the-parents-of-mpu_free_cl.patch
new file mode 100644
index 00000000000000..b21054d7c019e5
--- /dev/null
+++ b/patches/1632-clk-socfpga-stratix10-fix-the-parents-of-mpu_free_cl.patch
@@ -0,0 +1,44 @@
+From fb9766c9a82fa2b064c0ec5c26fcfafd4d33f53d Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Tue, 26 Jun 2018 08:28:09 -0500
+Subject: [PATCH 1632/1795] clk: socfpga: stratix10: fix the parents of
+ mpu_free_clk
+
+Add a clock mux that is used as a parent for the mpu_free_clk.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+(cherry picked from commit 2772ffd979baa1893c1fa75041c59b507716dcc7)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/socfpga/clk-s10.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
+index 72714633e39c..a15769f9985b 100644
+--- a/drivers/clk/socfpga/clk-s10.c
++++ b/drivers/clk/socfpga/clk-s10.c
+@@ -37,6 +37,11 @@ static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
+ static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
+ static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
+ 
++static const char * const mpu_free_mux[] = {"main_mpu_base_clk",
++					    "peri_mpu_base_clk",
++					    "osc1", "cb_intosc_hs_div2_clk",
++					    "f2s_free_clk"};
++
+ /* clocks in AO (always on) controller */
+ static const struct stratix10_pll_clock s10_pll_clks[] = {
+ 	{ STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
+@@ -57,7 +62,7 @@ static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
+ };
+ 
+ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
+-	{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
++	{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
+ 	   0, 0x48, 0, 0, 0},
+ 	{ STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
+ 	  0, 0x4C, 0, 0, 0},
+-- 
+2.19.0
+
diff --git a/patches/1633-clk-socfpga-stratix10-fix-the-sdmmc_free_clk-mux.patch b/patches/1633-clk-socfpga-stratix10-fix-the-sdmmc_free_clk-mux.patch
new file mode 100644
index 00000000000000..59ba76998aaffd
--- /dev/null
+++ b/patches/1633-clk-socfpga-stratix10-fix-the-sdmmc_free_clk-mux.patch
@@ -0,0 +1,31 @@
+From bc0bd3a30674966263b9dbb5b0dcd1bc0b3415b2 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Tue, 26 Jun 2018 08:28:10 -0500
+Subject: [PATCH 1633/1795] clk: socfpga: stratix10: fix the sdmmc_free_clk mux
+
+The first parent of the sdmmc_free_clk should be the main_sdmmc_clk.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+(cherry picked from commit 51b9a379a843c288b07b501784a5cc52b2c5aa69)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/clk/socfpga/clk-s10.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
+index a15769f9985b..5b238fc314ac 100644
+--- a/drivers/clk/socfpga/clk-s10.c
++++ b/drivers/clk/socfpga/clk-s10.c
+@@ -28,7 +28,7 @@ static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
+ static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
+ static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
+ static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
+-static const char * const sdmmc_free_mux[] = {"peri_sdmmc_clk", "boot_clk"};
++static const char * const sdmmc_free_mux[] = {"main_sdmmc_clk", "boot_clk"};
+ static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
+ static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
+ static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
+-- 
+2.19.0
+
diff --git a/patches/1634-arm64-dts-stratix10-fix-up-the-gic-register-for-the-.patch b/patches/1634-arm64-dts-stratix10-fix-up-the-gic-register-for-the-.patch
new file mode 100644
index 00000000000000..6834388ccaab7b
--- /dev/null
+++ b/patches/1634-arm64-dts-stratix10-fix-up-the-gic-register-for-the-.patch
@@ -0,0 +1,37 @@
+From 693a5c7aa5dcb10d894f54f031a1a382049f8606 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Fri, 23 Jun 2017 09:21:41 -0500
+Subject: [PATCH 1634/1795] arm64: dts: stratix10: fix up the gic register for
+ the Stratix10 platform
+
+The register entries for the ARM GIC-400 should have a 2nd set of address.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit f973bfa075cc05a891cfb0ac44212aa2a27ac54f)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index c2b9bcb0ef61..631e09aa1b48 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -75,10 +75,10 @@
+ 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ 		#interrupt-cells = <3>;
+ 		interrupt-controller;
+-		reg = <0x0 0xfffc1000 0x1000>,
+-		      <0x0 0xfffc2000 0x2000>,
+-		      <0x0 0xfffc4000 0x2000>,
+-		      <0x0 0xfffc6000 0x2000>;
++		reg = <0x0 0xfffc1000 0x0 0x1000>,
++		      <0x0 0xfffc2000 0x0 0x2000>,
++		      <0x0 0xfffc4000 0x0 0x2000>,
++		      <0x0 0xfffc6000 0x0 0x2000>;
+ 	};
+ 
+ 	soc {
+-- 
+2.19.0
+
diff --git a/patches/1635-arm64-dts-stratix10-add-ethernet-sdmmc-support-to-th.patch b/patches/1635-arm64-dts-stratix10-add-ethernet-sdmmc-support-to-th.patch
new file mode 100644
index 00000000000000..59159b58202550
--- /dev/null
+++ b/patches/1635-arm64-dts-stratix10-add-ethernet-sdmmc-support-to-th.patch
@@ -0,0 +1,70 @@
+From 0d94f51f12a13427887860d8fab90b495f382237 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Fri, 8 Sep 2017 10:14:18 -0500
+Subject: [PATCH 1635/1795] arm64: dts: stratix10: add ethernet/sdmmc support
+ to the S10 devkit
+
+Enable ethernet and sdmmc support on the Stratix10 devkit.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+---
+v2: Create a separate PHY node
+
+(cherry picked from commit 701e3a48772bae0f1181a7bb3ea7e23f17c03a82)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../dts/altera/socfpga_stratix10_socdk.dts    | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index 41ea2dba2fce..590758613677 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -34,6 +34,44 @@
+ 	};
+ };
+ 
++&gmac0 {
++	status = "okay";
++	phy-mode = "rgmii";
++	phy-handle = <&phy0>;
++
++	max-frame-size = <3800>;
++
++	mdio0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "snps,dwmac-mdio";
++		phy0: ethernet-phy@0 {
++			reg = <4>;
++
++			txd0-skew-ps = <0>; /* -420ps */
++			txd1-skew-ps = <0>; /* -420ps */
++			txd2-skew-ps = <0>; /* -420ps */
++			txd3-skew-ps = <0>; /* -420ps */
++			rxd0-skew-ps = <420>; /* 0ps */
++			rxd1-skew-ps = <420>; /* 0ps */
++			rxd2-skew-ps = <420>; /* 0ps */
++			rxd3-skew-ps = <420>; /* 0ps */
++			txen-skew-ps = <0>; /* -420ps */
++			txc-skew-ps = <1860>; /* 960ps */
++			rxdv-skew-ps = <420>; /* 0ps */
++			rxc-skew-ps = <1680>; /* 780ps */
++		};
++	};
++};
++
++&mmc {
++	status = "okay";
++	num-slots = <1>;
++	cap-sd-highspeed;
++	broken-cd;
++	bus-width = <4>;
++};
++
+ &uart0 {
+ 	status = "okay";
+ };
+-- 
+2.19.0
+
diff --git a/patches/1636-arm64-dts-stratix10-include-the-reset-manager-bindin.patch b/patches/1636-arm64-dts-stratix10-include-the-reset-manager-bindin.patch
new file mode 100644
index 00000000000000..45deaeaaf6d3e5
--- /dev/null
+++ b/patches/1636-arm64-dts-stratix10-include-the-reset-manager-bindin.patch
@@ -0,0 +1,45 @@
+From 90602cdeadb0be13e81a7135919afe51cdceeb31 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 20 Sep 2017 12:11:27 -0500
+Subject: [PATCH 1636/1795] arm64: dts: stratix10: include the reset manager
+ bindings
+
+Add the reset manager includes for Stratix10. Need to use the '#include'
+instead of '/include/' to avoid a DTC syntax error.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit e519922e30fb59f33766b49e3af67931be2858a6)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi      | 1 +
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 631e09aa1b48..f7fbc38d8fa6 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -15,6 +15,7 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+ 
+ / {
+ 	compatible = "altr,socfpga-stratix10";
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index 590758613677..46f27edaa08e 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -14,7 +14,7 @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+-/include/ "socfpga_stratix10.dtsi"
++#include "socfpga_stratix10.dtsi"
+ 
+ / {
+ 	model = "SoCFPGA Stratix 10 SoCDK";
+-- 
+2.19.0
+
diff --git a/patches/1637-arm64-dts-stratix10-add-the-altr-modrst-off-property.patch b/patches/1637-arm64-dts-stratix10-add-the-altr-modrst-off-property.patch
new file mode 100644
index 00000000000000..22ed0885bc18da
--- /dev/null
+++ b/patches/1637-arm64-dts-stratix10-add-the-altr-modrst-off-property.patch
@@ -0,0 +1,30 @@
+From 9b4a8cbf215df39759c5b053513e3407a9f4cdfe Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 20 Sep 2017 12:31:55 -0500
+Subject: [PATCH 1637/1795] arm64: dts: stratix10: add the 'altr,modrst-off'
+ property
+
+Update the Stratix10 reset manager with the 'altr,modrst-offset' property.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 7691d62689d3bee3db12251a51adc5a5acfef220)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index f7fbc38d8fa6..99e2afec0329 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -224,6 +224,7 @@
+ 			#reset-cells = <1>;
+ 			compatible = "altr,rst-mgr";
+ 			reg = <0xffd11000 0x1000>;
++			altr,modrst-offset = <0x20>;
+ 		};
+ 
+ 		spi0: spi@ffda4000 {
+-- 
+2.19.0
+
diff --git a/patches/1638-arm64-dts-stratix10-add-reset-property-for-various-p.patch b/patches/1638-arm64-dts-stratix10-add-reset-property-for-various-p.patch
new file mode 100644
index 00000000000000..4bb73cc6963ef9
--- /dev/null
+++ b/patches/1638-arm64-dts-stratix10-add-reset-property-for-various-p.patch
@@ -0,0 +1,180 @@
+From b8f6afc664fa3829ef34ed17f8d41322279c0984 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 20 Sep 2017 16:36:02 -0500
+Subject: [PATCH 1638/1795] arm64: dts: stratix10: add reset property for
+ various peripherals
+
+Add reset property for emac, gpio, i2c, sdmmc, timers, and watchdog.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 788251fa08118efa934ba2f54989997e7a5be679)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/altera/socfpga_stratix10.dtsi    | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 99e2afec0329..6804936f2459 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -101,6 +101,8 @@
+ 			interrupts = <0 90 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
++			resets = <&rst EMAC0_RESET>;
++			reset-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -110,6 +112,8 @@
+ 			interrupts = <0 91 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
++			resets = <&rst EMAC1_RESET>;
++			reset-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -119,6 +123,8 @@
+ 			interrupts = <0 92 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
++			resets = <&rst EMAC2_RESET>;
++			reset-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -127,6 +133,7 @@
+ 			#size-cells = <0>;
+ 			compatible = "snps,dw-apb-gpio";
+ 			reg = <0xffc03200 0x100>;
++			resets = <&rst GPIO0_RESET>;
+ 			status = "disabled";
+ 
+ 			porta: gpio-controller@0 {
+@@ -146,6 +153,7 @@
+ 			#size-cells = <0>;
+ 			compatible = "snps,dw-apb-gpio";
+ 			reg = <0xffc03300 0x100>;
++			resets = <&rst GPIO1_RESET>;
+ 			status = "disabled";
+ 
+ 			portb: gpio-controller@0 {
+@@ -166,6 +174,7 @@
+ 			compatible = "snps,designware-i2c";
+ 			reg = <0xffc02800 0x100>;
+ 			interrupts = <0 103 4>;
++			resets = <&rst I2C0_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -175,6 +184,7 @@
+ 			compatible = "snps,designware-i2c";
+ 			reg = <0xffc02900 0x100>;
+ 			interrupts = <0 104 4>;
++			resets = <&rst I2C1_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -184,6 +194,7 @@
+ 			compatible = "snps,designware-i2c";
+ 			reg = <0xffc02a00 0x100>;
+ 			interrupts = <0 105 4>;
++			resets = <&rst I2C2_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -193,6 +204,7 @@
+ 			compatible = "snps,designware-i2c";
+ 			reg = <0xffc02b00 0x100>;
+ 			interrupts = <0 106 4>;
++			resets = <&rst I2C3_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -202,6 +214,7 @@
+ 			compatible = "snps,designware-i2c";
+ 			reg = <0xffc02c00 0x100>;
+ 			interrupts = <0 107 4>;
++			resets = <&rst I2C4_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -212,6 +225,8 @@
+ 			reg = <0xff808000 0x1000>;
+ 			interrupts = <0 96 4>;
+ 			fifo-depth = <0x400>;
++			resets = <&rst SDMMC_RESET>;
++			reset-names = "reset";
+ 			status = "disabled";
+ 		};
+ 
+@@ -293,6 +308,7 @@
+ 			interrupts = <0 108 4>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			resets = <&rst UART0_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -302,6 +318,7 @@
+ 			interrupts = <0 109 4>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			resets = <&rst UART1_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -317,6 +334,8 @@
+ 			interrupts = <0 93 4>;
+ 			phys = <&usbphy0>;
+ 			phy-names = "usb2-phy";
++			resets = <&rst USB0_RESET>;
++			reset-names = "dwc2";
+ 			status = "disabled";
+ 		};
+ 
+@@ -326,6 +345,8 @@
+ 			interrupts = <0 94 4>;
+ 			phys = <&usbphy0>;
+ 			phy-names = "usb2-phy";
++			resets = <&rst USB1_RESET>;
++			reset-names = "dwc2";
+ 			status = "disabled";
+ 		};
+ 
+@@ -333,6 +354,7 @@
+ 			compatible = "snps,dw-wdt";
+ 			reg = <0xffd00200 0x100>;
+ 			interrupts = <0 117 4>;
++			resets = <&rst WATCHDOG0_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -340,6 +362,7 @@
+ 			compatible = "snps,dw-wdt";
+ 			reg = <0xffd00300 0x100>;
+ 			interrupts = <0 118 4>;
++			resets = <&rst WATCHDOG1_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -347,6 +370,7 @@
+ 			compatible = "snps,dw-wdt";
+ 			reg = <0xffd00400 0x100>;
+ 			interrupts = <0 125 4>;
++			resets = <&rst WATCHDOG2_RESET>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -354,6 +378,7 @@
+ 			compatible = "snps,dw-wdt";
+ 			reg = <0xffd00500 0x100>;
+ 			interrupts = <0 126 4>;
++			resets = <&rst WATCHDOG3_RESET>;
+ 			status = "disabled";
+ 		};
+ 	};
+-- 
+2.19.0
+
diff --git a/patches/1639-arm64-dts-stratix10-add-gpio-header.patch b/patches/1639-arm64-dts-stratix10-add-gpio-header.patch
new file mode 100644
index 00000000000000..35ea9917dff995
--- /dev/null
+++ b/patches/1639-arm64-dts-stratix10-add-gpio-header.patch
@@ -0,0 +1,30 @@
+From d07f13d92809c5a2b2267819c4f19d46bba563df Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Tue, 10 Oct 2017 16:25:37 -0500
+Subject: [PATCH 1639/1795] arm64: dts: stratix10: add gpio header
+
+Add the gpio header to the base stratix10 dtsi.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 5a0e622e499bfe34d3c12a8c7db997e770d1a7fd)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 6804936f2459..721b91abcd28 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -16,6 +16,7 @@
+ 
+ /dts-v1/;
+ #include <dt-bindings/reset/altr,rst-mgr-s10.h>
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	compatible = "altr,socfpga-stratix10";
+-- 
+2.19.0
+
diff --git a/patches/1640-arm64-dts-stratix10-enable-gpio-and-leds.patch b/patches/1640-arm64-dts-stratix10-enable-gpio-and-leds.patch
new file mode 100644
index 00000000000000..d957bff5435f8a
--- /dev/null
+++ b/patches/1640-arm64-dts-stratix10-enable-gpio-and-leds.patch
@@ -0,0 +1,64 @@
+From 7a61a7a5d4d0256bd7fc2e2ce240acf43cd23550 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Tue, 10 Oct 2017 16:25:38 -0500
+Subject: [PATCH 1640/1795] arm64: dts: stratix10: enable gpio and leds
+
+Enable gpio and leds for socdk OOBE daughtercard.
+
+pushbutton PB_SW0 = gpio1.io4
+pushbutton PB_SW1 = gpio1.io5
+LED HPS_LED0      = gpio1.io20
+LED HPS_LED1      = gpio1.io19
+LED HPS_LED2      = gpio1.io21
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit f850b5401cdfa6f5d03a62357211507d6ed72050)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../dts/altera/socfpga_stratix10_socdk.dts    | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index 46f27edaa08e..a37c46112876 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -27,6 +27,24 @@
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	leds {
++		compatible = "gpio-leds";
++		hps0 {
++			label = "hps_led0";
++			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
++		};
++
++		hps1 {
++			label = "hps_led1";
++			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
++		};
++
++		hps2 {
++			label = "hps_led2";
++			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
+ 	memory {
+ 		device_type = "memory";
+ 		/* We expect the bootloader to fill in the reg */
+@@ -34,6 +52,10 @@
+ 	};
+ };
+ 
++&gpio1 {
++	status = "okay";
++};
++
+ &gmac0 {
+ 	status = "okay";
+ 	phy-mode = "rgmii";
+-- 
+2.19.0
+
diff --git a/patches/1641-arm64-dts-stratix10-fix-interrupt-number-for-gpio1.patch b/patches/1641-arm64-dts-stratix10-fix-interrupt-number-for-gpio1.patch
new file mode 100644
index 00000000000000..5c96b269638d68
--- /dev/null
+++ b/patches/1641-arm64-dts-stratix10-fix-interrupt-number-for-gpio1.patch
@@ -0,0 +1,31 @@
+From 2d9be755a9fee72291c44c7f6581dfdf594750d1 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 11 Oct 2017 03:24:36 -0500
+Subject: [PATCH 1641/1795] arm64: dts: stratix10: fix interrupt number for
+ gpio1
+
+The gpio1 node's interrupt number should be 111.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit a067fb4290131b5b356dfcc464b5bff19a251791)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 721b91abcd28..7c9bdc7ab50b 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -165,7 +165,7 @@
+ 				reg = <0>;
+ 				interrupt-controller;
+ 				#interrupt-cells = <2>;
+-				interrupts = <0 110 4>;
++				interrupts = <0 111 4>;
+ 			};
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1642-arm64-dts-socfpga-add-missing-interrupt-parent.patch b/patches/1642-arm64-dts-socfpga-add-missing-interrupt-parent.patch
new file mode 100644
index 00000000000000..c8bdd780e88bf4
--- /dev/null
+++ b/patches/1642-arm64-dts-socfpga-add-missing-interrupt-parent.patch
@@ -0,0 +1,36 @@
+From d1615f7ec275641d23491c641402650ac8b70223 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 10 Jan 2018 22:04:16 +0100
+Subject: [PATCH 1642/1795] arm64: dts: socfpga: add missing interrupt-parent
+
+The PMU node has no working interrupt, as shown by this dtc warning:
+
+arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu
+
+This adds an interrupt-parent property so we can correct parse
+that interrupt number.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+(cherry picked from commit 69c4d8ed49568598f200b340b17e391c35be3d4b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 7c9bdc7ab50b..9db19314c60c 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -66,6 +66,7 @@
+ 				     <&cpu1>,
+ 				     <&cpu2>,
+ 				     <&cpu3>;
++		interrupt-parent = <&intc>;
+ 	};
+ 
+ 	psci {
+-- 
+2.19.0
+
diff --git a/patches/1643-arm64-dts-stratix10-enable-USB-on-the-devkit.patch b/patches/1643-arm64-dts-stratix10-enable-USB-on-the-devkit.patch
new file mode 100644
index 00000000000000..26a011414e8dfb
--- /dev/null
+++ b/patches/1643-arm64-dts-stratix10-enable-USB-on-the-devkit.patch
@@ -0,0 +1,29 @@
+From 7d505ca137687a0e6e3ab4851484470026a90b08 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Fri, 1 Dec 2017 11:14:24 -0600
+Subject: [PATCH 1643/1795] arm64: dts: stratix10: enable USB on the devkit
+
+Enable USB on the Stratix10 devkit.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 15a9b85d4bfab0d24745f5424bd0a159066bc46f)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index a37c46112876..000756429b77 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -97,3 +97,7 @@
+ &uart0 {
+ 	status = "okay";
+ };
++
++&usb0 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1644-arm64-dts-stratix10-add-USB-ECC-reset-bit.patch b/patches/1644-arm64-dts-stratix10-add-USB-ECC-reset-bit.patch
new file mode 100644
index 00000000000000..8fa6deb799b2d2
--- /dev/null
+++ b/patches/1644-arm64-dts-stratix10-add-USB-ECC-reset-bit.patch
@@ -0,0 +1,44 @@
+From 29df2e318c3b92ca7966b584525c23a2bda5cddb Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 13 Dec 2017 08:10:31 -0600
+Subject: [PATCH 1644/1795] arm64: dts: stratix10: add USB ECC reset bit
+
+The USB IP on the Stratix10 SoC needs the USB OCP(ecc) bit to get de-asserted
+as well for the USB IP to work properly.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 33af8ca0fd09514aa6a5600ae2aa455a30de5f43)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 9db19314c60c..16d47b9f17fe 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -336,8 +336,8 @@
+ 			interrupts = <0 93 4>;
+ 			phys = <&usbphy0>;
+ 			phy-names = "usb2-phy";
+-			resets = <&rst USB0_RESET>;
+-			reset-names = "dwc2";
++			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
++			reset-names = "dwc2", "dwc2-ecc";
+ 			status = "disabled";
+ 		};
+ 
+@@ -347,8 +347,8 @@
+ 			interrupts = <0 94 4>;
+ 			phys = <&usbphy0>;
+ 			phy-names = "usb2-phy";
+-			resets = <&rst USB1_RESET>;
+-			reset-names = "dwc2";
++			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
++			reset-names = "dwc2", "dwc2-ecc";
+ 			status = "disabled";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1645-arm64-dts-stratix10-fix-SPI-settings.patch b/patches/1645-arm64-dts-stratix10-fix-SPI-settings.patch
new file mode 100644
index 00000000000000..d286f08a3d0e10
--- /dev/null
+++ b/patches/1645-arm64-dts-stratix10-fix-SPI-settings.patch
@@ -0,0 +1,44 @@
+From 9c11968e219f7d863bebae26d9065623b918f55e Mon Sep 17 00:00:00 2001
+From: Thor Thayer <thor.thayer@linux.intel.com>
+Date: Tue, 16 Jan 2018 13:07:36 -0600
+Subject: [PATCH 1645/1795] arm64: dts: stratix10: fix SPI settings
+
+Correct the SPI Master node settings.
+
+Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 889d1509042096f6ccd082655997aeff8457fe1c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 16d47b9f17fe..c89d0c307f8d 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -249,7 +249,9 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0xffda4000 0x1000>;
+-			interrupts = <0 101 4>;
++			interrupts = <0 99 4>;
++			resets = <&rst SPIM0_RESET>;
++			reg-io-width = <4>;
+ 			num-chipselect = <4>;
+ 			bus-num = <0>;
+ 			status = "disabled";
+@@ -260,7 +262,9 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0xffda5000 0x1000>;
+-			interrupts = <0 102 4>;
++			interrupts = <0 100 4>;
++			resets = <&rst SPIM1_RESET>;
++			reg-io-width = <4>;
+ 			num-chipselect = <4>;
+ 			bus-num = <0>;
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/1646-arm64-dts-stratix10-remove-num-slots-property-for-dw.patch b/patches/1646-arm64-dts-stratix10-remove-num-slots-property-for-dw.patch
new file mode 100644
index 00000000000000..d0a953f5ff7877
--- /dev/null
+++ b/patches/1646-arm64-dts-stratix10-remove-num-slots-property-for-dw.patch
@@ -0,0 +1,33 @@
+From ab1d473834c22b219df0128b8c6e880e6179aaed Mon Sep 17 00:00:00 2001
+From: Jaehoon Chung <jh80.chung@samsung.com>
+Date: Fri, 23 Feb 2018 15:41:36 +0900
+Subject: [PATCH 1646/1795] arm64: dts: stratix10: remove 'num-slots' property
+ for dwmmc
+
+Since 'num-slots' had already deprecated, remove the property in
+device-tree file.
+
+Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
+Acked-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit a6306eb6a5f7038a8ba2eefb254efe4ead5ce05e)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index 000756429b77..51ce5832ee1d 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -88,7 +88,6 @@
+ 
+ &mmc {
+ 	status = "okay";
+-	num-slots = <1>;
+ 	cap-sd-highspeed;
+ 	broken-cd;
+ 	bus-width = <4>;
+-- 
+2.19.0
+
diff --git a/patches/1647-arm64-dts-stratix10-enable-watchdog-timer-on-the-S10.patch b/patches/1647-arm64-dts-stratix10-enable-watchdog-timer-on-the-S10.patch
new file mode 100644
index 00000000000000..665ba52daf32e5
--- /dev/null
+++ b/patches/1647-arm64-dts-stratix10-enable-watchdog-timer-on-the-S10.patch
@@ -0,0 +1,30 @@
+From 7e793ea045e3ecd02b20cea644499bf58ea48ede Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Mon, 5 Mar 2018 09:21:05 -0600
+Subject: [PATCH 1647/1795] arm64: dts: stratix10: enable watchdog timer on the
+ S10 devkit
+
+Enables the watchdog0 timer on the Stratix10 devkit.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 3b0fb63f25125939735d92a58b2b89b575501b9e)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index 51ce5832ee1d..e8eef799b867 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -100,3 +100,7 @@
+ &usb0 {
+ 	status = "okay";
+ };
++
++&watchdog0 {
++	status = "okay";
++};
+-- 
+2.19.0
+
diff --git a/patches/1648-arm64-dts-stratix10-disable-false-USB-overcurrent-on.patch b/patches/1648-arm64-dts-stratix10-disable-false-USB-overcurrent-on.patch
new file mode 100644
index 00000000000000..67fa2f10c212c2
--- /dev/null
+++ b/patches/1648-arm64-dts-stratix10-disable-false-USB-overcurrent-on.patch
@@ -0,0 +1,31 @@
+From fb472961bbbfabecb28de0a73bfb319ebc598167 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Mon, 12 Mar 2018 09:49:21 -0500
+Subject: [PATCH 1648/1795] arm64: dts: stratix10: disable false USB
+ overcurrent on devkit
+
+Disable the USB overcurrent condition that is falsely detected on the
+devkit.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 956c8cd692ba2ca2dea2bb34d4102268bb5460f2)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index e8eef799b867..eaf13fe29287 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -99,6 +99,7 @@
+ 
+ &usb0 {
+ 	status = "okay";
++	disable-over-current;
+ };
+ 
+ &watchdog0 {
+-- 
+2.19.0
+
diff --git a/patches/1649-arm64-dts-stratix10-use-clock-bindings-for-the-Strat.patch b/patches/1649-arm64-dts-stratix10-use-clock-bindings-for-the-Strat.patch
new file mode 100644
index 00000000000000..80486c2977bc55
--- /dev/null
+++ b/patches/1649-arm64-dts-stratix10-use-clock-bindings-for-the-Strat.patch
@@ -0,0 +1,191 @@
+From 8fbd05ee24eabbd431fdd07cf9dfe6d126090942 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 31 Jan 2018 14:58:02 -0600
+Subject: [PATCH 1649/1795] arm64: dts: stratix10: use clock bindings for the
+ Stratix10 platform
+
+Use the clock bindings for the Stratix10 SoC. This includes changing the old
+binding of "intc,clk-s10-mgr" to "intel,stratix10-clkmgr". The reason that
+this can be done is that there are currently no clock driver for Stratix10,
+thus there are no consumers of the old binding. So changing the binding will
+not break any legacy code.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+---
+v7:
+- move PLL out of clkmgr node and into DT root
+v6:
+- no changes
+v5:
+- no changes
+v4:
+- remove '_' in name of clock nodes
+- use clock-controller in SoCDK node in dts file
+v3:
+- use the correct vendor prefix
+- explain the binding change
+v2:
+- use a single clock binding for the clock controller
+
+(cherry picked from commit d93101abe41e9596555a0f7f6f775e543b71c441)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/altera/socfpga_stratix10.dtsi    | 47 ++++++++++++++++++-
+ .../dts/altera/socfpga_stratix10_socdk.dts    |  8 ++++
+ 2 files changed, 53 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index c89d0c307f8d..0e267c8c786d 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -17,6 +17,7 @@
+ /dts-v1/;
+ #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/clock/stratix10-clock.h>
+ 
+ / {
+ 	compatible = "altr,socfpga-stratix10";
+@@ -92,9 +93,32 @@
+ 		interrupt-parent = <&intc>;
+ 		ranges = <0 0 0 0xffffffff>;
+ 
+-		clkmgr@ffd1000 {
+-			compatible = "altr,clk-mgr";
++		clkmgr: clock-controller@ffd10000 {
++			compatible = "intel,stratix10-clkmgr";
+ 			reg = <0xffd10000 0x1000>;
++			#clock-cells = <1>;
++		};
++
++		clocks {
++			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
++				#clock-cells = <0>;
++				compatible = "fixed-clock";
++			};
++
++			cb_intosc_ls_clk: cb-intosc-ls-clk {
++				#clock-cells = <0>;
++				compatible = "fixed-clock";
++			};
++
++			f2s_free_clk: f2s-free-clk {
++				#clock-cells = <0>;
++				compatible = "fixed-clock";
++			};
++
++			osc1: osc1 {
++				#clock-cells = <0>;
++				compatible = "fixed-clock";
++			};
+ 		};
+ 
+ 		gmac0: ethernet@ff800000 {
+@@ -105,6 +129,8 @@
+ 			mac-address = [00 00 00 00 00 00];
+ 			resets = <&rst EMAC0_RESET>;
+ 			reset-names = "stmmaceth";
++			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
++			clock-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -116,6 +142,8 @@
+ 			mac-address = [00 00 00 00 00 00];
+ 			resets = <&rst EMAC1_RESET>;
+ 			reset-names = "stmmaceth";
++			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
++			clock-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -127,6 +155,8 @@
+ 			mac-address = [00 00 00 00 00 00];
+ 			resets = <&rst EMAC2_RESET>;
+ 			reset-names = "stmmaceth";
++			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
++			clock-names = "stmmaceth";
+ 			status = "disabled";
+ 		};
+ 
+@@ -229,6 +259,9 @@
+ 			fifo-depth = <0x400>;
+ 			resets = <&rst SDMMC_RESET>;
+ 			reset-names = "reset";
++			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
++				 <&clkmgr STRATIX10_SDMMC_CLK>;
++			clock-names = "biu", "ciu";
+ 			status = "disabled";
+ 		};
+ 
+@@ -288,24 +321,32 @@
+ 			compatible = "snps,dw-apb-timer";
+ 			interrupts = <0 113 4>;
+ 			reg = <0xffc03000 0x100>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
++			clock-names = "timer";
+ 		};
+ 
+ 		timer1: timer1@ffc03100 {
+ 			compatible = "snps,dw-apb-timer";
+ 			interrupts = <0 114 4>;
+ 			reg = <0xffc03100 0x100>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
++			clock-names = "timer";
+ 		};
+ 
+ 		timer2: timer2@ffd00000 {
+ 			compatible = "snps,dw-apb-timer";
+ 			interrupts = <0 115 4>;
+ 			reg = <0xffd00000 0x100>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
++			clock-names = "timer";
+ 		};
+ 
+ 		timer3: timer3@ffd00100 {
+ 			compatible = "snps,dw-apb-timer";
+ 			interrupts = <0 116 4>;
+ 			reg = <0xffd00100 0x100>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
++			clock-names = "timer";
+ 		};
+ 
+ 		uart0: serial0@ffc02000 {
+@@ -315,6 +356,7 @@
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
+ 			resets = <&rst UART0_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -325,6 +367,7 @@
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
+ 			resets = <&rst UART1_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index eaf13fe29287..bec15e8e6c42 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -50,6 +50,14 @@
+ 		/* We expect the bootloader to fill in the reg */
+ 		reg = <0 0 0 0>;
+ 	};
++
++	soc {
++		clocks {
++			osc1 {
++				clock-frequency = <25000000>;
++			};
++		};
++	};
+ };
+ 
+ &gpio1 {
+-- 
+2.19.0
+
diff --git a/patches/1650-arm64-dts-stratix10-enable-i2c-add-i2c-periperals.patch b/patches/1650-arm64-dts-stratix10-enable-i2c-add-i2c-periperals.patch
new file mode 100644
index 00000000000000..e3806f9b732c61
--- /dev/null
+++ b/patches/1650-arm64-dts-stratix10-enable-i2c-add-i2c-periperals.patch
@@ -0,0 +1,124 @@
+From 68cfc360bbdd8e5fe04df0dd13d2368421b2ff75 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 21 Feb 2018 14:25:41 -0600
+Subject: [PATCH 1650/1795] arm64: dts: stratix10: enable i2c, add i2c
+ periperals
+
+Add clock for i2c
+Enable i2c1
+Set the i2c bus speed to 100KHz
+Add the following i2c peripherals
+* ds1339 RTC
+* 24c32 EEPROM
+* max1619 temperature monitor
+* ltc2497 ADC
+  * Add a fixed regulator for the ADC's Vref.
+
+This requires Dinh Nguyen's Stratix10 clock driver
+("clk: socfpga: stratix10: add clock driver for Stratix10 platform")
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit eebee19e52c850856e219e124fdf4de6bacef9ff)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/altera/socfpga_stratix10.dtsi    |  5 +++
+ .../dts/altera/socfpga_stratix10_socdk.dts    | 34 +++++++++++++++++++
+ 2 files changed, 39 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 0e267c8c786d..21d906e164fa 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -207,6 +207,7 @@
+ 			reg = <0xffc02800 0x100>;
+ 			interrupts = <0 103 4>;
+ 			resets = <&rst I2C0_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -217,6 +218,7 @@
+ 			reg = <0xffc02900 0x100>;
+ 			interrupts = <0 104 4>;
+ 			resets = <&rst I2C1_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -227,6 +229,7 @@
+ 			reg = <0xffc02a00 0x100>;
+ 			interrupts = <0 105 4>;
+ 			resets = <&rst I2C2_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -237,6 +240,7 @@
+ 			reg = <0xffc02b00 0x100>;
+ 			interrupts = <0 106 4>;
+ 			resets = <&rst I2C3_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -247,6 +251,7 @@
+ 			reg = <0xffc02c00 0x100>;
+ 			interrupts = <0 107 4>;
+ 			resets = <&rst I2C4_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index bec15e8e6c42..d03df18ca967 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -51,6 +51,13 @@
+ 		reg = <0 0 0 0>;
+ 	};
+ 
++	ref_033v: 033-v-ref {
++		compatible = "regulator-fixed";
++		regulator-name = "0.33V";
++		regulator-min-microvolt = <330000>;
++		regulator-max-microvolt = <330000>;
++	};
++
+ 	soc {
+ 		clocks {
+ 			osc1 {
+@@ -113,3 +120,30 @@
+ &watchdog0 {
+ 	status = "okay";
+ };
++
++&i2c1 {
++	status = "okay";
++	clock-frequency = <100000>;
++
++	adc@14 {
++		compatible = "lltc,ltc2497";
++		reg = <0x14>;
++		vref-supply = <&ref_033v>;
++	};
++
++	temp@4c {
++		compatible = "maxim,max1619";
++		reg = <0x4c>;
++	};
++
++	eeprom@51 {
++		compatible = "atmel,24c32";
++		reg = <0x51>;
++		pagesize = <32>;
++	};
++
++	rtc@68 {
++		compatible = "dallas,ds1339";
++		reg = <0x68>;
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1651-arm64-dts-stratix10-Add-PL330-DMAC-to-Stratix10-dts.patch b/patches/1651-arm64-dts-stratix10-Add-PL330-DMAC-to-Stratix10-dts.patch
new file mode 100644
index 00000000000000..a9e68d64c743e3
--- /dev/null
+++ b/patches/1651-arm64-dts-stratix10-Add-PL330-DMAC-to-Stratix10-dts.patch
@@ -0,0 +1,50 @@
+From b8614a1b54c9b3a868502412377dd4a80fac7973 Mon Sep 17 00:00:00 2001
+From: Graham Moore <graham.moore@linux.intel.com>
+Date: Tue, 20 Feb 2018 09:38:47 -0600
+Subject: [PATCH 1651/1795] arm64: dts: stratix10: Add PL330 DMAC to Stratix10
+ dts
+
+The Stratix10 SoCFPGA uses the PL330 DMAC.  This patch adds the PL330
+DMAC to the Stratix10 device tree.
+
+Signed-off-by: Graham Moore <graham.moore@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit ab50a44404a53b12554005ed4c5a1b3547ac9492)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/altera/socfpga_stratix10.dtsi    | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 21d906e164fa..0b28f1fbe486 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -275,6 +275,25 @@
+ 			reg = <0xffe00000 0x100000>;
+ 		};
+ 
++		pdma: pdma@ffda0000 {
++			compatible = "arm,pl330", "arm,primecell";
++			reg = <0xffda0000 0x1000>;
++			interrupts = <0 81 4>,
++				     <0 82 4>,
++				     <0 83 4>,
++				     <0 84 4>,
++				     <0 85 4>,
++				     <0 86 4>,
++				     <0 87 4>,
++				     <0 88 4>,
++				     <0 89 4>;
++			#dma-cells = <1>;
++			#dma-channels = <8>;
++			#dma-requests = <32>;
++			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
++			clock-names = "apb_pclk";
++		};
++
+ 		rst: rstmgr@ffd11000 {
+ 			#reset-cells = <1>;
+ 			compatible = "altr,rst-mgr";
+-- 
+2.19.0
+
diff --git a/patches/1652-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch b/patches/1652-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch
new file mode 100644
index 00000000000000..e6c5528ba8c408
--- /dev/null
+++ b/patches/1652-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch
@@ -0,0 +1,35 @@
+From c0a7f08375194a66bc0b0c9289ee416e8066e623 Mon Sep 17 00:00:00 2001
+From: "Ooi, Joyce" <joyce.ooi@intel.com>
+Date: Tue, 24 Apr 2018 11:01:58 +0800
+Subject: [PATCH 1652/1795] arm64: dts: stratix10: Change pad skew values for
+ EMAC0 PHY driver
+
+The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
+drive strength has caused CE test to fail. This requires changes on the
+pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
+clock does not require the extra 0.96ns delay.
+
+Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit e8c622e2b51b9ad4a8cd3f153a2ca4f1b61cf165)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index d03df18ca967..f9b1ef12db48 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -94,7 +94,7 @@
+ 			rxd2-skew-ps = <420>; /* 0ps */
+ 			rxd3-skew-ps = <420>; /* 0ps */
+ 			txen-skew-ps = <0>; /* -420ps */
+-			txc-skew-ps = <1860>; /* 960ps */
++			txc-skew-ps = <900>; /* 0ps */
+ 			rxdv-skew-ps = <420>; /* 0ps */
+ 			rxc-skew-ps = <1680>; /* 780ps */
+ 		};
+-- 
+2.19.0
+
diff --git a/patches/1653-arm64-dts-stratix10-add-sdram-ecc.patch b/patches/1653-arm64-dts-stratix10-add-sdram-ecc.patch
new file mode 100644
index 00000000000000..ef3cc346237d49
--- /dev/null
+++ b/patches/1653-arm64-dts-stratix10-add-sdram-ecc.patch
@@ -0,0 +1,41 @@
+From 890e1fe595ca82dffceba9a4624e8fda4a4db043 Mon Sep 17 00:00:00 2001
+From: Thor Thayer <thor.thayer@linux.intel.com>
+Date: Tue, 8 May 2018 08:11:29 -0500
+Subject: [PATCH 1653/1795] arm64: dts: stratix10: add sdram ecc
+
+Add the Stratix10 ECC Manager and SDRAM EDAC nodes to the
+device tree.
+
+Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 91fdd8274f32987760bbdb2981b4a896e338c09e)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 0b28f1fbe486..e6b059378dc0 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -454,5 +454,17 @@
+ 			resets = <&rst WATCHDOG3_RESET>;
+ 			status = "disabled";
+ 		};
++
++		eccmgr {
++			compatible = "altr,socfpga-s10-ecc-manager";
++			interrupts = <0 15 4>, <0 95 4>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++
++			sdramedac {
++				compatible = "altr,sdram-edac-s10";
++				interrupts = <16 4>, <48 4>;
++			};
++		};
+ 	};
+ };
+-- 
+2.19.0
+
diff --git a/patches/1654-arm64-dts-stratix10-Fix-SPI-nodes-for-Stratix10.patch b/patches/1654-arm64-dts-stratix10-Fix-SPI-nodes-for-Stratix10.patch
new file mode 100644
index 00000000000000..944193de400043
--- /dev/null
+++ b/patches/1654-arm64-dts-stratix10-Fix-SPI-nodes-for-Stratix10.patch
@@ -0,0 +1,46 @@
+From f02f32de9111285c574be37f4c32a966d90a5595 Mon Sep 17 00:00:00 2001
+From: Thor Thayer <thor.thayer@linux.intel.com>
+Date: Fri, 22 Jun 2018 13:35:38 -0500
+Subject: [PATCH 1654/1795] arm64: dts: stratix10: Fix SPI nodes for Stratix10
+
+Remove the unused bus-num node and change num-chipselect
+to num-cs to match SPI bindings.
+
+Cc: stable@vger.kernel.org
+Fixes: 78cd6a9d8e154 ("arm64: dts: Add base stratix 10 dtsi")
+Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+(cherry picked from commit 4595299c5eaebbec0ca5822214ad1925a10b3876)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index e6b059378dc0..67dac595dc72 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -309,8 +309,7 @@
+ 			interrupts = <0 99 4>;
+ 			resets = <&rst SPIM0_RESET>;
+ 			reg-io-width = <4>;
+-			num-chipselect = <4>;
+-			bus-num = <0>;
++			num-cs = <4>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -322,8 +321,7 @@
+ 			interrupts = <0 100 4>;
+ 			resets = <&rst SPIM1_RESET>;
+ 			reg-io-width = <4>;
+-			num-chipselect = <4>;
+-			bus-num = <0>;
++			num-cs = <4>;
+ 			status = "disabled";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1655-arm64-dts-stratix10-Add-QSPI-support-for-Stratix10.patch b/patches/1655-arm64-dts-stratix10-Add-QSPI-support-for-Stratix10.patch
new file mode 100644
index 00000000000000..70078bedd02a73
--- /dev/null
+++ b/patches/1655-arm64-dts-stratix10-Add-QSPI-support-for-Stratix10.patch
@@ -0,0 +1,105 @@
+From 91dbfe393b3c11b294a2849ae14e882514f6fadb Mon Sep 17 00:00:00 2001
+From: Thor Thayer <thor.thayer@linux.intel.com>
+Date: Tue, 15 May 2018 17:26:27 -0500
+Subject: [PATCH 1655/1795] arm64: dts: stratix10: Add QSPI support for
+ Stratix10
+
+Add qspi_clock
+   The qspi_clk frequency is updated by U-Boot before starting Linux.
+Add QSPI interface node.
+Add QSPI flash memory child node.
+   Setup the QSPI memory in 2 partitions.
+
+Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 0cb140d07fc75fb40dc402ba7e6e8c3c3a6f9d71)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../boot/dts/altera/socfpga_stratix10.dtsi    | 21 +++++++++++
+ .../dts/altera/socfpga_stratix10_socdk.dts    | 35 +++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 67dac595dc72..47fa4b450324 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -119,6 +119,12 @@
+ 				#clock-cells = <0>;
+ 				compatible = "fixed-clock";
+ 			};
++
++			qspi_clk: qspi-clk {
++				#clock-cells = <0>;
++				compatible = "fixed-clock";
++				clock-frequency = <200000000>;
++			};
+ 		};
+ 
+ 		gmac0: ethernet@ff800000 {
+@@ -464,5 +470,20 @@
+ 				interrupts = <16 4>, <48 4>;
+ 			};
+ 		};
++
++		qspi: spi@ff8d2000 {
++			compatible = "cdns,qspi-nor";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0xff8d2000 0x100>,
++			      <0xff900000 0x100000>;
++			interrupts = <0 3 4>;
++			cdns,fifo-depth = <128>;
++			cdns,fifo-width = <4>;
++			cdns,trigger-address = <0x00000000>;
++			clocks = <&qspi_clk>;
++
++			status = "disabled";
++		};
+ 	};
+ };
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+index f9b1ef12db48..6edc4fa9fd42 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+@@ -147,3 +147,38 @@
+ 		reg = <0x68>;
+ 	};
+ };
++
++&qspi {
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "n25q00a";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++
++		m25p,fast-read;
++		cdns,page-size = <256>;
++		cdns,block-size = <16>;
++		cdns,read-delay = <1>;
++		cdns,tshsl-ns = <50>;
++		cdns,tsd2d-ns = <50>;
++		cdns,tchsh-ns = <4>;
++		cdns,tslch-ns = <4>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			qspi_boot: partition@0 {
++				label = "Boot and fpga data";
++				reg = <0x0 0x4000000>;
++			};
++
++			qspi_rootfs: partition@4000000 {
++				label = "Root Filesystem - JFFS2";
++				reg = <0x4000000 0x4000000>;
++			};
++		};
++	};
++};
+-- 
+2.19.0
+
diff --git a/patches/1656-arm64-dts-stratix10-fill-in-clocks-field-for-usb-and.patch b/patches/1656-arm64-dts-stratix10-fill-in-clocks-field-for-usb-and.patch
new file mode 100644
index 00000000000000..9d702a16c02260
--- /dev/null
+++ b/patches/1656-arm64-dts-stratix10-fill-in-clocks-field-for-usb-and.patch
@@ -0,0 +1,70 @@
+From ac1c3554fbb8fd0013f93056c27d099bda7fdfa8 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 6 Jun 2018 12:07:12 -0500
+Subject: [PATCH 1656/1795] arm64: dts: stratix10: fill in clocks field for usb
+ and watchdog
+
+Populate the clocks field for USB and watchdog.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 03761ab1b0ab134abcb900d23b32f7c0c615b360)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 47fa4b450324..1412e98fe4c4 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -413,6 +413,7 @@
+ 			phy-names = "usb2-phy";
+ 			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ 			reset-names = "dwc2", "dwc2-ecc";
++			clocks = <&clkmgr STRATIX10_USB_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -424,6 +425,7 @@
+ 			phy-names = "usb2-phy";
+ 			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+ 			reset-names = "dwc2", "dwc2-ecc";
++			clocks = <&clkmgr STRATIX10_USB_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -432,6 +434,7 @@
+ 			reg = <0xffd00200 0x100>;
+ 			interrupts = <0 117 4>;
+ 			resets = <&rst WATCHDOG0_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -440,6 +443,7 @@
+ 			reg = <0xffd00300 0x100>;
+ 			interrupts = <0 118 4>;
+ 			resets = <&rst WATCHDOG1_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -448,6 +452,7 @@
+ 			reg = <0xffd00400 0x100>;
+ 			interrupts = <0 125 4>;
+ 			resets = <&rst WATCHDOG2_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -456,6 +461,7 @@
+ 			reg = <0xffd00500 0x100>;
+ 			interrupts = <0 126 4>;
+ 			resets = <&rst WATCHDOG3_RESET>;
++			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1657-arm64-dts-stratix10-add-OCP-reset-property-for-ether.patch b/patches/1657-arm64-dts-stratix10-add-OCP-reset-property-for-ether.patch
new file mode 100644
index 00000000000000..85cb6617076844
--- /dev/null
+++ b/patches/1657-arm64-dts-stratix10-add-OCP-reset-property-for-ether.patch
@@ -0,0 +1,55 @@
+From 084b967dcc8fdfcfcb0cc14c3c26fec8f7e50b5e Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 6 Jun 2018 14:55:54 -0500
+Subject: [PATCH 1657/1795] arm64: dts: stratix10: add OCP reset property for
+ ethernet
+
+Add the additional OCP reset property for the ethernet nodes.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 05690e8ab29e9d144f634ffa65b8c7f765f627c9)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index 1412e98fe4c4..a77bde19a9d3 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -133,8 +133,8 @@
+ 			interrupts = <0 90 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
+-			resets = <&rst EMAC0_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
++			reset-names = "stmmaceth", "stmmaceth-ocp";
+ 			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
+ 			clock-names = "stmmaceth";
+ 			status = "disabled";
+@@ -146,8 +146,8 @@
+ 			interrupts = <0 91 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
+-			resets = <&rst EMAC1_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
++			reset-names = "stmmaceth", "stmmaceth-ocp";
+ 			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
+ 			clock-names = "stmmaceth";
+ 			status = "disabled";
+@@ -159,8 +159,8 @@
+ 			interrupts = <0 92 4>;
+ 			interrupt-names = "macirq";
+ 			mac-address = [00 00 00 00 00 00];
+-			resets = <&rst EMAC2_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
++			reset-names = "stmmaceth", "stmmaceth-ocp";
+ 			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
+ 			clock-names = "stmmaceth";
+ 			status = "disabled";
+-- 
+2.19.0
+
diff --git a/patches/1658-arm64-dts-stratix10-Add-SPI-node-clocks-for-Stratix1.patch b/patches/1658-arm64-dts-stratix10-Add-SPI-node-clocks-for-Stratix1.patch
new file mode 100644
index 00000000000000..bda2b32a3db72f
--- /dev/null
+++ b/patches/1658-arm64-dts-stratix10-Add-SPI-node-clocks-for-Stratix1.patch
@@ -0,0 +1,40 @@
+From 9fd5436adcf7afa491c10f6a23561f5a4c6cf76f Mon Sep 17 00:00:00 2001
+From: Thor Thayer <thor.thayer@linux.intel.com>
+Date: Wed, 27 Jun 2018 12:50:27 -0500
+Subject: [PATCH 1658/1795] arm64: dts: stratix10: Add SPI node clocks for
+ Stratix10
+
+Add the required clocks for the new Stratix10 clock bindings
+to the SPI nodes.
+
+Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+(cherry picked from commit 70455ac7ffb6b707af1e56e1993af82906fddaae)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+index a77bde19a9d3..d033da401c26 100644
+--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+@@ -316,6 +316,7 @@
+ 			resets = <&rst SPIM0_RESET>;
+ 			reg-io-width = <4>;
+ 			num-cs = <4>;
++			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -328,6 +329,7 @@
+ 			resets = <&rst SPIM1_RESET>;
+ 			reg-io-width = <4>;
+ 			num-cs = <4>;
++			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
+ 			status = "disabled";
+ 		};
+ 
+-- 
+2.19.0
+
diff --git a/patches/1659-MAINTAINERS-add-backup-FPGA-maintainer.patch b/patches/1659-MAINTAINERS-add-backup-FPGA-maintainer.patch
new file mode 100644
index 00000000000000..95b2d7ee7243cb
--- /dev/null
+++ b/patches/1659-MAINTAINERS-add-backup-FPGA-maintainer.patch
@@ -0,0 +1,32 @@
+From a9df20da8ec1fde56acdff258f0aa2c6690daef2 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Tue, 19 Sep 2017 18:25:06 -0500
+Subject: [PATCH 1659/1795] MAINTAINERS: add backup FPGA maintainer
+
+Add Moritz as a maintainer of the kernel FPGA framework.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit a120fbddd59a3d04a63800824ea032dbf1c21b83)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ MAINTAINERS | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index e2d8f38a5091..28af79cd07f8 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -5432,7 +5432,7 @@ K:	fmc_d.*register
+ 
+ FPGA MANAGER FRAMEWORK
+ M:	Alan Tull <atull@kernel.org>
+-R:	Moritz Fischer <mdf@kernel.org>
++M:	Moritz Fischer <mdf@kernel.org>
+ L:	linux-fpga@vger.kernel.org
+ S:	Maintained
+ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git
+-- 
+2.19.0
+
diff --git a/patches/1660-fpga-bridge-support-getting-bridge-from-device.patch b/patches/1660-fpga-bridge-support-getting-bridge-from-device.patch
new file mode 100644
index 00000000000000..f8b7239d190172
--- /dev/null
+++ b/patches/1660-fpga-bridge-support-getting-bridge-from-device.patch
@@ -0,0 +1,276 @@
+From 1ee1f4887a33f4bd55832abda5e23675f655c07c Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:11 -0600
+Subject: [PATCH 1660/1795] fpga: bridge: support getting bridge from device
+
+Add two functions for getting the FPGA bridge from the device
+rather than device tree node.  This is to enable writing code
+that will support using FPGA bridges without device tree.
+Rename one old function to make it clear that it is device
+tree-ish.  This leaves us with 3 functions for getting a bridge:
+
+* fpga_bridge_get
+  Get the bridge given the device.
+
+* fpga_bridges_get_to_list
+  Given the device, get the bridge and add it to a list.
+
+* of_fpga_bridges_get_to_list
+  Renamed from priviously existing fpga_bridges_get_to_list.
+  Given the device node, get the bridge and add it to a list.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 9c1c4b2753fea36a072e78a5efc82fca0d13b455)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-bridge.c       | 110 ++++++++++++++++++++++++-------
+ drivers/fpga/fpga-region.c       |  11 ++--
+ include/linux/fpga/fpga-bridge.h |  12 +++-
+ 3 files changed, 103 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 9651aa56244a..0dfe9d78cee2 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -2,6 +2,7 @@
+  * FPGA Bridge Framework Driver
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
++ *  Copyright (C) 2017 Intel Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms and conditions of the GNU General Public License,
+@@ -70,29 +71,12 @@ int fpga_bridge_disable(struct fpga_bridge *bridge)
+ }
+ EXPORT_SYMBOL_GPL(fpga_bridge_disable);
+ 
+-/**
+- * of_fpga_bridge_get - get an exclusive reference to a fpga bridge
+- *
+- * @np: node pointer of a FPGA bridge
+- * @info: fpga image specific information
+- *
+- * Return fpga_bridge struct if successful.
+- * Return -EBUSY if someone already has a reference to the bridge.
+- * Return -ENODEV if @np is not a FPGA Bridge.
+- */
+-struct fpga_bridge *of_fpga_bridge_get(struct device_node *np,
+-				       struct fpga_image_info *info)
+-
++static struct fpga_bridge *__fpga_bridge_get(struct device *dev,
++					     struct fpga_image_info *info)
+ {
+-	struct device *dev;
+ 	struct fpga_bridge *bridge;
+ 	int ret = -ENODEV;
+ 
+-	dev = class_find_device(fpga_bridge_class, NULL, np,
+-				fpga_bridge_of_node_match);
+-	if (!dev)
+-		goto err_dev;
+-
+ 	bridge = to_fpga_bridge(dev);
+ 	if (!bridge)
+ 		goto err_dev;
+@@ -117,8 +101,58 @@ struct fpga_bridge *of_fpga_bridge_get(struct device_node *np,
+ 	put_device(dev);
+ 	return ERR_PTR(ret);
+ }
++
++/**
++ * of_fpga_bridge_get - get an exclusive reference to a fpga bridge
++ *
++ * @np: node pointer of a FPGA bridge
++ * @info: fpga image specific information
++ *
++ * Return fpga_bridge struct if successful.
++ * Return -EBUSY if someone already has a reference to the bridge.
++ * Return -ENODEV if @np is not a FPGA Bridge.
++ */
++struct fpga_bridge *of_fpga_bridge_get(struct device_node *np,
++				       struct fpga_image_info *info)
++{
++	struct device *dev;
++
++	dev = class_find_device(fpga_bridge_class, NULL, np,
++				fpga_bridge_of_node_match);
++	if (!dev)
++		return ERR_PTR(-ENODEV);
++
++	return __fpga_bridge_get(dev, info);
++}
+ EXPORT_SYMBOL_GPL(of_fpga_bridge_get);
+ 
++static int fpga_bridge_dev_match(struct device *dev, const void *data)
++{
++	return dev->parent == data;
++}
++
++/**
++ * fpga_bridge_get - get an exclusive reference to a fpga bridge
++ * @dev:	parent device that fpga bridge was registered with
++ *
++ * Given a device, get an exclusive reference to a fpga bridge.
++ *
++ * Return: fpga manager struct or IS_ERR() condition containing error code.
++ */
++struct fpga_bridge *fpga_bridge_get(struct device *dev,
++				    struct fpga_image_info *info)
++{
++	struct device *bridge_dev;
++
++	bridge_dev = class_find_device(fpga_bridge_class, NULL, dev,
++				       fpga_bridge_dev_match);
++	if (!bridge_dev)
++		return ERR_PTR(-ENODEV);
++
++	return __fpga_bridge_get(bridge_dev, info);
++}
++EXPORT_SYMBOL_GPL(fpga_bridge_get);
++
+ /**
+  * fpga_bridge_put - release a reference to a bridge
+  *
+@@ -206,7 +240,7 @@ void fpga_bridges_put(struct list_head *bridge_list)
+ EXPORT_SYMBOL_GPL(fpga_bridges_put);
+ 
+ /**
+- * fpga_bridges_get_to_list - get a bridge, add it to a list
++ * of_fpga_bridge_get_to_list - get a bridge, add it to a list
+  *
+  * @np: node pointer of a FPGA bridge
+  * @info: fpga image specific information
+@@ -216,14 +250,44 @@ EXPORT_SYMBOL_GPL(fpga_bridges_put);
+  *
+  * Return 0 for success, error code from of_fpga_bridge_get() othewise.
+  */
+-int fpga_bridge_get_to_list(struct device_node *np,
++int of_fpga_bridge_get_to_list(struct device_node *np,
++			       struct fpga_image_info *info,
++			       struct list_head *bridge_list)
++{
++	struct fpga_bridge *bridge;
++	unsigned long flags;
++
++	bridge = of_fpga_bridge_get(np, info);
++	if (IS_ERR(bridge))
++		return PTR_ERR(bridge);
++
++	spin_lock_irqsave(&bridge_list_lock, flags);
++	list_add(&bridge->node, bridge_list);
++	spin_unlock_irqrestore(&bridge_list_lock, flags);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(of_fpga_bridge_get_to_list);
++
++/**
++ * fpga_bridge_get_to_list - given device, get a bridge, add it to a list
++ *
++ * @dev: FPGA bridge device
++ * @info: fpga image specific information
++ * @bridge_list: list of FPGA bridges
++ *
++ * Get an exclusive reference to the bridge and and it to the list.
++ *
++ * Return 0 for success, error code from fpga_bridge_get() othewise.
++ */
++int fpga_bridge_get_to_list(struct device *dev,
+ 			    struct fpga_image_info *info,
+ 			    struct list_head *bridge_list)
+ {
+ 	struct fpga_bridge *bridge;
+ 	unsigned long flags;
+ 
+-	bridge = of_fpga_bridge_get(np, info);
++	bridge = fpga_bridge_get(dev, info);
+ 	if (IS_ERR(bridge))
+ 		return PTR_ERR(bridge);
+ 
+@@ -381,7 +445,7 @@ static void __exit fpga_bridge_dev_exit(void)
+ }
+ 
+ MODULE_DESCRIPTION("FPGA Bridge Driver");
+-MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
++MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
+ MODULE_LICENSE("GPL v2");
+ 
+ subsys_initcall(fpga_bridge_dev_init);
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index e0c73ceba2ed..2f2a82e833ed 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -184,11 +184,14 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ 	int i, ret;
+ 
+ 	/* If parent is a bridge, add to list */
+-	ret = fpga_bridge_get_to_list(region_np->parent, region->info,
+-				      &region->bridge_list);
++	ret = of_fpga_bridge_get_to_list(region_np->parent, region->info,
++					 &region->bridge_list);
++
++	/* -EBUSY means parent is a bridge that is under use. Give up. */
+ 	if (ret == -EBUSY)
+ 		return ret;
+ 
++	/* Zero return code means parent was a bridge and was added to list. */
+ 	if (!ret)
+ 		parent_br = region_np->parent;
+ 
+@@ -213,8 +216,8 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ 		}
+ 
+ 		/* If node is a bridge, get it and add to list */
+-		ret = fpga_bridge_get_to_list(br, region->info,
+-					      &region->bridge_list);
++		ret = of_fpga_bridge_get_to_list(br, region->info,
++						 &region->bridge_list);
+ 		of_node_put(br);
+ 
+ 		/* If any of the bridges are in use, give up */
+diff --git a/include/linux/fpga/fpga-bridge.h b/include/linux/fpga/fpga-bridge.h
+index aa66c87c120b..6ca41f8f949f 100644
+--- a/include/linux/fpga/fpga-bridge.h
++++ b/include/linux/fpga/fpga-bridge.h
+@@ -1,10 +1,11 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+-#include <linux/device.h>
+-#include <linux/fpga/fpga-mgr.h>
+ 
+ #ifndef _LINUX_FPGA_BRIDGE_H
+ #define _LINUX_FPGA_BRIDGE_H
+ 
++#include <linux/device.h>
++#include <linux/fpga/fpga-mgr.h>
++
+ struct fpga_bridge;
+ 
+ /**
+@@ -43,6 +44,8 @@ struct fpga_bridge {
+ 
+ struct fpga_bridge *of_fpga_bridge_get(struct device_node *node,
+ 				       struct fpga_image_info *info);
++struct fpga_bridge *fpga_bridge_get(struct device *dev,
++				    struct fpga_image_info *info);
+ void fpga_bridge_put(struct fpga_bridge *bridge);
+ int fpga_bridge_enable(struct fpga_bridge *bridge);
+ int fpga_bridge_disable(struct fpga_bridge *bridge);
+@@ -50,9 +53,12 @@ int fpga_bridge_disable(struct fpga_bridge *bridge);
+ int fpga_bridges_enable(struct list_head *bridge_list);
+ int fpga_bridges_disable(struct list_head *bridge_list);
+ void fpga_bridges_put(struct list_head *bridge_list);
+-int fpga_bridge_get_to_list(struct device_node *np,
++int fpga_bridge_get_to_list(struct device *dev,
+ 			    struct fpga_image_info *info,
+ 			    struct list_head *bridge_list);
++int of_fpga_bridge_get_to_list(struct device_node *np,
++			       struct fpga_image_info *info,
++			       struct list_head *bridge_list);
+ 
+ int fpga_bridge_register(struct device *dev, const char *name,
+ 			 const struct fpga_bridge_ops *br_ops, void *priv);
+-- 
+2.19.0
+
diff --git a/patches/1661-fpga-mgr-API-change-to-replace-fpga-load-functions-w.patch b/patches/1661-fpga-mgr-API-change-to-replace-fpga-load-functions-w.patch
new file mode 100644
index 00000000000000..71b46fa11e9034
--- /dev/null
+++ b/patches/1661-fpga-mgr-API-change-to-replace-fpga-load-functions-w.patch
@@ -0,0 +1,678 @@
+From 3b97018383a87b459d887e0015fd88ec7a7a6f35 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:12 -0600
+Subject: [PATCH 1661/1795] fpga: mgr: API change to replace fpga load
+ functions with single function
+
+fpga-mgr has three methods for programming FPGAs, depending on
+whether the image is in a scatter gather list, a contiguous
+buffer, or a firmware file. This makes it difficult to write
+upper layers as the caller has to assume whether the FPGA image
+is in a sg table, as a single buffer, or a firmware file.
+This commit moves these parameters to struct fpga_image_info
+and adds a single function for programming fpgas.
+
+New functions:
+* fpga_mgr_load - given fpga manager and struct fpga_image_info,
+   program the fpga.
+
+* fpga_image_info_alloc - alloc a struct fpga_image_info.
+
+* fpga_image_info_free - free a struct fpga_image_info.
+
+These three functions are unexported:
+* fpga_mgr_buf_load_sg
+* fpga_mgr_buf_load
+* fpga_mgr_firmware_load
+
+Also use devm_kstrdup to copy firmware_name so we aren't making
+assumptions about where it comes from when allocing/freeing the
+struct fpga_image_info.
+
+API documentation has been updated and a new document for
+FPGA region has been added.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5cf0c7f6502f26332b46fa87914553a4d6ae75ac)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/fpga/fpga-mgr.txt    | 119 +++++++++++++----------------
+ Documentation/fpga/fpga-region.txt |  95 +++++++++++++++++++++++
+ Documentation/fpga/overview.txt    |  23 ++++++
+ drivers/fpga/fpga-mgr.c            |  68 ++++++++++++++---
+ drivers/fpga/fpga-region.c         |  43 +++++++----
+ include/linux/fpga/fpga-mgr.h      |  30 +++++---
+ 6 files changed, 273 insertions(+), 105 deletions(-)
+ create mode 100644 Documentation/fpga/fpga-region.txt
+ create mode 100644 Documentation/fpga/overview.txt
+
+diff --git a/Documentation/fpga/fpga-mgr.txt b/Documentation/fpga/fpga-mgr.txt
+index 78f197fadfd1..6ebc714f4b03 100644
+--- a/Documentation/fpga/fpga-mgr.txt
++++ b/Documentation/fpga/fpga-mgr.txt
+@@ -11,61 +11,53 @@ hidden away in a low level driver which registers a set of ops with the core.
+ The FPGA image data itself is very manufacturer specific, but for our purposes
+ it's just binary data.  The FPGA manager core won't parse it.
+ 
++The FPGA image to be programmed can be in a scatter gather list, a single
++contiguous buffer, or a firmware file.  Because allocating contiguous kernel
++memory for the buffer should be avoided, users are encouraged to use a scatter
++gather list instead if possible.
++
++The particulars for programming the image are presented in a structure (struct
++fpga_image_info).  This struct contains parameters such as pointers to the
++FPGA image as well as image-specific particulars such as whether the image was
++built for full or partial reconfiguration.
+ 
+ API Functions:
+ ==============
+ 
+-To program the FPGA from a file or from a buffer:
+--------------------------------------------------
+-
+-	int fpga_mgr_buf_load(struct fpga_manager *mgr,
+-			      struct fpga_image_info *info,
+-		              const char *buf, size_t count);
+-
+-Load the FPGA from an image which exists as a contiguous buffer in
+-memory. Allocating contiguous kernel memory for the buffer should be avoided,
+-users are encouraged to use the _sg interface instead of this.
+-
+-        int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
+-				 struct fpga_image_info *info,
+-				 struct sg_table *sgt);
++To program the FPGA:
++--------------------
+ 
+-Load the FPGA from an image from non-contiguous in memory. Callers can
+-construct a sg_table using alloc_page backed memory.
++	int fpga_mgr_load(struct fpga_manager *mgr,
++			  struct fpga_image_info *info);
+ 
+-	int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+-				   struct fpga_image_info *info,
+-		                   const char *image_name);
+-
+-Load the FPGA from an image which exists as a file.  The image file must be on
+-the firmware search path (see the firmware class documentation).  If successful,
++Load the FPGA from an image which is indicated in the info.  If successful,
+ the FPGA ends up in operating mode.  Return 0 on success or a negative error
+ code.
+ 
+-A FPGA design contained in a FPGA image file will likely have particulars that
+-affect how the image is programmed to the FPGA.  These are contained in struct
+-fpga_image_info.  Currently the only such particular is a single flag bit
+-indicating whether the image is for full or partial reconfiguration.
++To allocate or free a struct fpga_image_info:
++---------------------------------------------
++
++	struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
++
++	void fpga_image_info_free(struct fpga_image_info *info);
+ 
+ To get/put a reference to a FPGA manager:
+ -----------------------------------------
+ 
+ 	struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
+ 	struct fpga_manager *fpga_mgr_get(struct device *dev);
+-
+-Given a DT node or device, get an exclusive reference to a FPGA manager.
+-
+ 	void fpga_mgr_put(struct fpga_manager *mgr);
+ 
+-Release the reference.
++Given a DT node or device, get an exclusive reference to a FPGA manager.
++fpga_mgr_put releases the reference.
+ 
+ 
+ To register or unregister the low level FPGA-specific driver:
+ -------------------------------------------------------------
+ 
+ 	int fpga_mgr_register(struct device *dev, const char *name,
+-		              const struct fpga_manager_ops *mops,
+-		              void *priv);
++			      const struct fpga_manager_ops *mops,
++			      void *priv);
+ 
+ 	void fpga_mgr_unregister(struct device *dev);
+ 
+@@ -78,59 +70,50 @@ How to write an image buffer to a supported FPGA
+ /* Include to get the API */
+ #include <linux/fpga/fpga-mgr.h>
+ 
+-/* device node that specifies the FPGA manager to use */
+-struct device_node *mgr_node = ...
+-
+-/* FPGA image is in this buffer.  count is size of the buffer. */
+-char *buf = ...
+-int count = ...
++struct fpga_manager *mgr;
++struct fpga_image_info *info;
++int ret;
+ 
+ /* struct with information about the FPGA image to program. */
+-struct fpga_image_info info;
++info = fpga_image_info_alloc(dev);
+ 
+ /* flags indicates whether to do full or partial reconfiguration */
+-info.flags = 0;
+-
+-int ret;
++info->flags = FPGA_MGR_PARTIAL_RECONFIG;
+ 
+-/* Get exclusive control of FPGA manager */
+-struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node);
++/*
++ * At this point, indicate where the image is. This is pseudo-code; you're
++ * going to use one of these three.
++ */
++if (image is in a scatter gather table) {
+ 
+-/* Load the buffer to the FPGA */
+-ret = fpga_mgr_buf_load(mgr, &info, buf, count);
+-
+-/* Release the FPGA manager */
+-fpga_mgr_put(mgr);
++	info->sgt = [your scatter gather table]
+ 
++} else if (image is in a buffer) {
+ 
+-How to write an image file to a supported FPGA
+-==============================================
+-/* Include to get the API */
+-#include <linux/fpga/fpga-mgr.h>
++	info->buf = [your image buffer]
++	info->count = [image buffer size]
+ 
+-/* device node that specifies the FPGA manager to use */
+-struct device_node *mgr_node = ...
++} else if (image is in a firmware file) {
+ 
+-/* FPGA image is in this file which is in the firmware search path */
+-const char *path = "fpga-image-9.rbf"
++	info->firmware_name = devm_kstrdup(dev, firmware_name, GFP_KERNEL);
+ 
+-/* struct with information about the FPGA image to program. */
+-struct fpga_image_info info;
+-
+-/* flags indicates whether to do full or partial reconfiguration */
+-info.flags = 0;
+-
+-int ret;
++}
+ 
+-/* Get exclusive control of FPGA manager */
+-struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node);
++/*
++ * Get a reference to FPGA manager.  This example uses the  device node of the
++ * manager.  You could use fpga_mgr_get() instead if you have the device instead
++ * of the device node.
++ */
++mgr = of_fpga_mgr_get(mgr_node);
+ 
+-/* Get the firmware image (path) and load it to the FPGA */
+-ret = fpga_mgr_firmware_load(mgr, &info, path);
++/* Load the buffer to the FPGA */
++ret = fpga_mgr_buf_load(mgr, &info, buf, count);
+ 
+ /* Release the FPGA manager */
+ fpga_mgr_put(mgr);
+ 
++/* Deallocate the image info if you're done with it */
++fpga_image_info_free(info);
+ 
+ How to support a new FPGA device
+ ================================
+diff --git a/Documentation/fpga/fpga-region.txt b/Documentation/fpga/fpga-region.txt
+new file mode 100644
+index 000000000000..139a02ba1ff6
+--- /dev/null
++++ b/Documentation/fpga/fpga-region.txt
+@@ -0,0 +1,95 @@
++FPGA Regions
++
++Alan Tull 2017
++
++CONTENTS
++ - Introduction
++ - The FPGA region API
++ - Usage example
++
++Introduction
++============
++
++This document is meant to be an brief overview of the FPGA region API usage.  A
++more conceptual look at regions can be found in [1].
++
++For the purposes of this API document, let's just say that a region associates
++an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
++FPGA or the whole FPGA.  The API provides a way to register a region and to
++program a region.
++
++Currently the only layer above fpga-region.c in the kernel is the Device Tree
++support (of-fpga-region.c) described in [1].  The DT support layer uses regions
++to program the FPGA and then DT to handle enumeration.  The common region code
++is intended to be used by other schemes that have other ways of accomplishing
++enumeration after programming.
++
++An fpga-region can be set up to know the following things:
++* which FPGA manager to use to do the programming
++* which bridges to disable before programming and enable afterwards.
++
++Additional info needed to program the FPGA image is passed in the struct
++fpga_image_info [2] including:
++* pointers to the image as either a scatter-gather buffer, a contiguous
++  buffer, or the name of firmware file
++* flags indicating specifics such as whether the image if for partial
++  reconfiguration.
++
++===================
++The FPGA region API
++===================
++
++To register or unregister a region:
++-----------------------------------
++
++	int fpga_region_register(struct device *dev,
++				 struct fpga_region *region);
++	int fpga_region_unregister(struct fpga_region *region);
++
++An example of usage can be seen in the probe function of [3]
++
++To program an FPGA:
++-------------------
++	int fpga_region_program_fpga(struct fpga_region *region);
++
++This function operates on info passed in the fpga_image_info
++(region->info).
++
++This function will attempt to:
++ * lock the region's mutex
++ * lock the region's FPGA manager
++ * build a list of FPGA bridges if a method has been specified to do so
++ * disable the bridges
++ * program the FPGA
++ * re-enable the bridges
++ * release the locks
++
++=============
++Usage example
++=============
++
++First, allocate the info struct:
++
++	info = fpga_image_info_alloc(dev);
++	if (!info)
++		return -ENOMEM;
++
++Set flags as needed, i.e.
++
++	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
++
++Point to your FPGA image, such as:
++
++	info->sgt = &sgt;
++
++Add info to region and do the programming:
++
++	region->info = info;
++	ret = fpga_region_program_fpga(region);
++
++Then enumerate whatever hardware has appeared in the FPGA.
++
++--
++[1] ../devicetree/bindings/fpga/fpga-region.txt
++[2] ./fpga-mgr.txt
++[3] ../../drivers/fpga/of-fpga-region.c
+diff --git a/Documentation/fpga/overview.txt b/Documentation/fpga/overview.txt
+new file mode 100644
+index 000000000000..0f1236e7e675
+--- /dev/null
++++ b/Documentation/fpga/overview.txt
+@@ -0,0 +1,23 @@
++Linux kernel FPGA support
++
++Alan Tull 2017
++
++The main point of this project has been to separate the out the upper layers
++that know when to reprogram a FPGA from the lower layers that know how to
++reprogram a specific FPGA device.  The intention is to make this manufacturer
++agnostic, understanding that of course the FPGA images are very device specific
++themselves.
++
++The framework in the kernel includes:
++* low level FPGA manager drivers that know how to program a specific device
++* the fpga-mgr framework they are registered with
++* low level FPGA bridge drivers for hard/soft bridges which are intended to
++  be disable during FPGA programming
++* the fpga-bridge framework they are registered with
++* the fpga-region framework which associates and controls managers and bridges
++  as reconfigurable regions
++* the of-fpga-region support for reprogramming FPGAs when device tree overlays
++  are applied.
++
++I would encourage you the user to add code that creates FPGA regions rather
++that trying to control managers and bridges separately.
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 188ffefa3cc3..a8dd54945470 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -2,6 +2,7 @@
+  * FPGA Manager Core
+  *
+  *  Copyright (C) 2013-2015 Altera Corporation
++ *  Copyright (C) 2017 Intel Corporation
+  *
+  * With code from the mailing list:
+  * Copyright (C) 2013 Xilinx, Inc.
+@@ -31,6 +32,40 @@
+ static DEFINE_IDA(fpga_mgr_ida);
+ static struct class *fpga_mgr_class;
+ 
++struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
++{
++	struct fpga_image_info *info;
++
++	get_device(dev);
++
++	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
++	if (!info) {
++		put_device(dev);
++		return NULL;
++	}
++
++	info->dev = dev;
++
++	return info;
++}
++EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
++
++void fpga_image_info_free(struct fpga_image_info *info)
++{
++	struct device *dev;
++
++	if (!info)
++		return;
++
++	dev = info->dev;
++	if (info->firmware_name)
++		devm_kfree(dev, info->firmware_name);
++
++	devm_kfree(dev, info);
++	put_device(dev);
++}
++EXPORT_SYMBOL_GPL(fpga_image_info_free);
++
+ /*
+  * Call the low level driver's write_init function.  This will do the
+  * device-specific things to get the FPGA into the state where it is ready to
+@@ -137,8 +172,9 @@ static int fpga_mgr_write_complete(struct fpga_manager *mgr,
+  *
+  * Return: 0 on success, negative error code otherwise.
+  */
+-int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
+-			 struct sg_table *sgt)
++static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
++				struct fpga_image_info *info,
++				struct sg_table *sgt)
+ {
+ 	int ret;
+ 
+@@ -170,7 +206,6 @@ int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
+ 
+ 	return fpga_mgr_write_complete(mgr, info);
+ }
+-EXPORT_SYMBOL_GPL(fpga_mgr_buf_load_sg);
+ 
+ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
+ 				    struct fpga_image_info *info,
+@@ -210,8 +245,9 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
+  *
+  * Return: 0 on success, negative error code otherwise.
+  */
+-int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
+-		      const char *buf, size_t count)
++static int fpga_mgr_buf_load(struct fpga_manager *mgr,
++			     struct fpga_image_info *info,
++			     const char *buf, size_t count)
+ {
+ 	struct page **pages;
+ 	struct sg_table sgt;
+@@ -266,7 +302,6 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
+ 
+ 	return rc;
+ }
+-EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
+ 
+ /**
+  * fpga_mgr_firmware_load - request firmware and load to fpga
+@@ -282,9 +317,9 @@ EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
+  *
+  * Return: 0 on success, negative error code otherwise.
+  */
+-int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+-			   struct fpga_image_info *info,
+-			   const char *image_name)
++static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
++				  struct fpga_image_info *info,
++				  const char *image_name)
+ {
+ 	struct device *dev = &mgr->dev;
+ 	const struct firmware *fw;
+@@ -307,7 +342,18 @@ int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL_GPL(fpga_mgr_firmware_load);
++
++int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
++{
++	if (info->sgt)
++		return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
++	if (info->buf && info->count)
++		return fpga_mgr_buf_load(mgr, info, info->buf, info->count);
++	if (info->firmware_name)
++		return fpga_mgr_firmware_load(mgr, info, info->firmware_name);
++	return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(fpga_mgr_load);
+ 
+ static const char * const state_str[] = {
+ 	[FPGA_MGR_STATE_UNKNOWN] =		"unknown",
+@@ -578,7 +624,7 @@ static void __exit fpga_mgr_class_exit(void)
+ 	ida_destroy(&fpga_mgr_ida);
+ }
+ 
+-MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
++MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
+ MODULE_DESCRIPTION("FPGA manager framework");
+ MODULE_LICENSE("GPL v2");
+ 
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 2f2a82e833ed..5c107ac39796 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -233,14 +233,11 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ /**
+  * fpga_region_program_fpga - program FPGA
+  * @region: FPGA region
+- * @firmware_name: name of FPGA image firmware file
+  * @overlay: device node of the overlay
+- * Program an FPGA using information in the device tree.
+- * Function assumes that there is a firmware-name property.
++ * Program an FPGA using information in the region's fpga image info.
+  * Return 0 for success or negative error code.
+  */
+ static int fpga_region_program_fpga(struct fpga_region *region,
+-				    const char *firmware_name,
+ 				    struct device_node *overlay)
+ {
+ 	struct fpga_manager *mgr;
+@@ -271,7 +268,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_br;
+ 	}
+ 
+-	ret = fpga_mgr_firmware_load(mgr, region->info, firmware_name);
++	ret = fpga_mgr_load(mgr, region->info);
+ 	if (ret) {
+ 		pr_err("failed to load fpga image\n");
+ 		goto err_put_br;
+@@ -364,16 +361,15 @@ static int child_regions_with_firmware(struct device_node *overlay)
+ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 					struct of_overlay_notify_data *nd)
+ {
+-	const char *firmware_name = NULL;
++	struct device *dev = &region->dev;
+ 	struct fpga_image_info *info;
++	const char *firmware_name;
+ 	int ret;
+ 
+-	info = devm_kzalloc(&region->dev, sizeof(*info), GFP_KERNEL);
++	info = fpga_image_info_alloc(dev);
+ 	if (!info)
+ 		return -ENOMEM;
+ 
+-	region->info = info;
+-
+ 	/* Reject overlay if child FPGA Regions have firmware-name property */
+ 	ret = child_regions_with_firmware(nd->overlay);
+ 	if (ret)
+@@ -389,7 +385,13 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	if (of_property_read_bool(nd->overlay, "encrypted-fpga-config"))
+ 		info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
+ 
+-	of_property_read_string(nd->overlay, "firmware-name", &firmware_name);
++	if (!of_property_read_string(nd->overlay, "firmware-name",
++				     &firmware_name)) {
++		info->firmware_name = devm_kstrdup(dev, firmware_name,
++						   GFP_KERNEL);
++		if (!info->firmware_name)
++			return -ENOMEM;
++	}
+ 
+ 	of_property_read_u32(nd->overlay, "region-unfreeze-timeout-us",
+ 			     &info->enable_timeout_us);
+@@ -401,22 +403,33 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 			     &info->config_complete_timeout_us);
+ 
+ 	/* If FPGA was externally programmed, don't specify firmware */
+-	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
++	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && info->firmware_name) {
+ 		pr_err("error: specified firmware and external-fpga-config");
++		fpga_image_info_free(info);
+ 		return -EINVAL;
+ 	}
+ 
+ 	/* FPGA is already configured externally.  We're done. */
+-	if (info->flags & FPGA_MGR_EXTERNAL_CONFIG)
++	if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) {
++		fpga_image_info_free(info);
+ 		return 0;
++	}
+ 
+ 	/* If we got this far, we should be programming the FPGA */
+-	if (!firmware_name) {
++	if (!info->firmware_name) {
+ 		pr_err("should specify firmware-name or external-fpga-config\n");
++		fpga_image_info_free(info);
+ 		return -EINVAL;
+ 	}
+ 
+-	return fpga_region_program_fpga(region, firmware_name, nd->overlay);
++	region->info = info;
++	ret = fpga_region_program_fpga(region, nd->overlay);
++	if (ret) {
++		fpga_image_info_free(info);
++		region->info = NULL;
++	}
++
++	return ret;
+ }
+ 
+ /**
+@@ -433,7 +446,7 @@ static void fpga_region_notify_post_remove(struct fpga_region *region,
+ {
+ 	fpga_bridges_disable(&region->bridge_list);
+ 	fpga_bridges_put(&region->bridge_list);
+-	devm_kfree(&region->dev, region->info);
++	fpga_image_info_free(region->info);
+ 	region->info = NULL;
+ }
+ 
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index bfa14bc023fb..6b791348023b 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -1,7 +1,8 @@
+ /*
+  * FPGA Framework
+  *
+- *  Copyright (C) 2013-2015 Altera Corporation
++ *  Copyright (C) 2013-2016 Altera Corporation
++ *  Copyright (C) 2017 Intel Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms and conditions of the GNU General Public License,
+@@ -15,12 +16,12 @@
+  * You should have received a copy of the GNU General Public License along with
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-#include <linux/mutex.h>
+-#include <linux/platform_device.h>
+-
+ #ifndef _LINUX_FPGA_MGR_H
+ #define _LINUX_FPGA_MGR_H
+ 
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++
+ struct fpga_manager;
+ struct sg_table;
+ 
+@@ -83,12 +84,22 @@ enum fpga_mgr_states {
+  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+  * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+  *	   status in the write_complete op.
++ * @firmware_name: name of FPGA image firmware file
++ * @sgt: scatter/gather table containing FPGA image
++ * @buf: contiguous buffer containing FPGA image
++ * @count: size of buf
++ * @dev: device that owns this
+  */
+ struct fpga_image_info {
+ 	u32 flags;
+ 	u32 enable_timeout_us;
+ 	u32 disable_timeout_us;
+ 	u32 config_complete_timeout_us;
++	char *firmware_name;
++	struct sg_table *sgt;
++	const char *buf;
++	size_t count;
++	struct device *dev;
+ };
+ 
+ /**
+@@ -138,14 +149,11 @@ struct fpga_manager {
+ 
+ #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
+ 
+-int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
+-		      const char *buf, size_t count);
+-int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
+-			 struct sg_table *sgt);
++struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
++
++void fpga_image_info_free(struct fpga_image_info *info);
+ 
+-int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+-			   struct fpga_image_info *info,
+-			   const char *image_name);
++int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info);
+ 
+ struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1662-fpga-mgr-separate-getting-locking-FPGA-manager.patch b/patches/1662-fpga-mgr-separate-getting-locking-FPGA-manager.patch
new file mode 100644
index 00000000000000..e57f34d2be1ce3
--- /dev/null
+++ b/patches/1662-fpga-mgr-separate-getting-locking-FPGA-manager.patch
@@ -0,0 +1,279 @@
+From d8714bf1d966577e73aa48e6a2c1f9da5105d1aa Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:13 -0600
+Subject: [PATCH 1662/1795] fpga: mgr: separate getting/locking FPGA manager
+
+Previously when the user gets a FPGA manager, it was locked
+and nobody else could use it for programming.
+
+This commit makes it straightforward to save a reference to an
+FPGA manager and only lock it when programming the FPGA.
+
+Add functions that get an FPGA manager's mutex for exclusive use:
+* fpga_mgr_lock
+* fpga_mgr_unlock
+
+The following functions no longer lock an FPGA manager's mutex:
+* of_fpga_mgr_get
+* fpga_mgr_get
+* fpga_mgr_put
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ebf877a51ad7b65e4ab024f021b60a4f7928864a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/fpga/fpga-mgr.txt | 35 ++++++++++++++++------
+ drivers/fpga/fpga-mgr.c         | 52 +++++++++++++++++++++++----------
+ drivers/fpga/fpga-region.c      | 14 +++++++--
+ include/linux/fpga/fpga-mgr.h   |  3 ++
+ 4 files changed, 77 insertions(+), 27 deletions(-)
+
+diff --git a/Documentation/fpga/fpga-mgr.txt b/Documentation/fpga/fpga-mgr.txt
+index 6ebc714f4b03..cc6413ed6fc9 100644
+--- a/Documentation/fpga/fpga-mgr.txt
++++ b/Documentation/fpga/fpga-mgr.txt
+@@ -48,8 +48,20 @@ To get/put a reference to a FPGA manager:
+ 	struct fpga_manager *fpga_mgr_get(struct device *dev);
+ 	void fpga_mgr_put(struct fpga_manager *mgr);
+ 
+-Given a DT node or device, get an exclusive reference to a FPGA manager.
+-fpga_mgr_put releases the reference.
++Given a DT node or device, get a reference to a FPGA manager.  This pointer
++can be saved until you are ready to program the FPGA.  fpga_mgr_put releases
++the reference.
++
++
++To get exclusive control of a FPGA manager:
++-------------------------------------------
++
++	int fpga_mgr_lock(struct fpga_manager *mgr);
++	void fpga_mgr_unlock(struct fpga_manager *mgr);
++
++The user should call fpga_mgr_lock and verify that it returns 0 before
++attempting to program the FPGA.  Likewise, the user should call
++fpga_mgr_unlock when done programming the FPGA.
+ 
+ 
+ To register or unregister the low level FPGA-specific driver:
+@@ -67,13 +79,21 @@ device."
+ 
+ How to write an image buffer to a supported FPGA
+ ================================================
+-/* Include to get the API */
+ #include <linux/fpga/fpga-mgr.h>
+ 
+ struct fpga_manager *mgr;
+ struct fpga_image_info *info;
+ int ret;
+ 
++/*
++ * Get a reference to FPGA manager.  The manager is not locked, so you can
++ * hold onto this reference without it preventing programming.
++ *
++ * This example uses the device node of the manager.  Alternatively, use
++ * fpga_mgr_get(dev) instead if you have the device.
++ */
++mgr = of_fpga_mgr_get(mgr_node);
++
+ /* struct with information about the FPGA image to program. */
+ info = fpga_image_info_alloc(dev);
+ 
+@@ -99,17 +119,14 @@ if (image is in a scatter gather table) {
+ 
+ }
+ 
+-/*
+- * Get a reference to FPGA manager.  This example uses the  device node of the
+- * manager.  You could use fpga_mgr_get() instead if you have the device instead
+- * of the device node.
+- */
+-mgr = of_fpga_mgr_get(mgr_node);
++/* Get exclusive control of FPGA manager */
++ret = fpga_mgr_lock(mgr);
+ 
+ /* Load the buffer to the FPGA */
+ ret = fpga_mgr_buf_load(mgr, &info, buf, count);
+ 
+ /* Release the FPGA manager */
++fpga_mgr_unlock(mgr);
+ fpga_mgr_put(mgr);
+ 
+ /* Deallocate the image info if you're done with it */
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index a8dd54945470..d27e8d2a149c 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -410,28 +410,19 @@ ATTRIBUTE_GROUPS(fpga_mgr);
+ static struct fpga_manager *__fpga_mgr_get(struct device *dev)
+ {
+ 	struct fpga_manager *mgr;
+-	int ret = -ENODEV;
+ 
+ 	mgr = to_fpga_manager(dev);
+ 	if (!mgr)
+ 		goto err_dev;
+ 
+-	/* Get exclusive use of fpga manager */
+-	if (!mutex_trylock(&mgr->ref_mutex)) {
+-		ret = -EBUSY;
+-		goto err_dev;
+-	}
+-
+ 	if (!try_module_get(dev->parent->driver->owner))
+-		goto err_ll_mod;
++		goto err_dev;
+ 
+ 	return mgr;
+ 
+-err_ll_mod:
+-	mutex_unlock(&mgr->ref_mutex);
+ err_dev:
+ 	put_device(dev);
+-	return ERR_PTR(ret);
++	return ERR_PTR(-ENODEV);
+ }
+ 
+ static int fpga_mgr_dev_match(struct device *dev, const void *data)
+@@ -440,10 +431,10 @@ static int fpga_mgr_dev_match(struct device *dev, const void *data)
+ }
+ 
+ /**
+- * fpga_mgr_get - get an exclusive reference to a fpga mgr
++ * fpga_mgr_get - get a reference to a fpga mgr
+  * @dev:	parent device that fpga mgr was registered with
+  *
+- * Given a device, get an exclusive reference to a fpga mgr.
++ * Given a device, get a reference to a fpga mgr.
+  *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+@@ -464,10 +455,10 @@ static int fpga_mgr_of_node_match(struct device *dev, const void *data)
+ }
+ 
+ /**
+- * of_fpga_mgr_get - get an exclusive reference to a fpga mgr
++ * of_fpga_mgr_get - get a reference to a fpga mgr
+  * @node:	device node
+  *
+- * Given a device node, get an exclusive reference to a fpga mgr.
++ * Given a device node, get a reference to a fpga mgr.
+  *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+@@ -491,11 +482,40 @@ EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
+ void fpga_mgr_put(struct fpga_manager *mgr)
+ {
+ 	module_put(mgr->dev.parent->driver->owner);
+-	mutex_unlock(&mgr->ref_mutex);
+ 	put_device(&mgr->dev);
+ }
+ EXPORT_SYMBOL_GPL(fpga_mgr_put);
+ 
++/**
++ * fpga_mgr_lock - Lock FPGA manager for exclusive use
++ * @mgr:	fpga manager
++ *
++ * Given a pointer to FPGA Manager (from fpga_mgr_get() or
++ * of_fpga_mgr_put()) attempt to get the mutex.
++ *
++ * Return: 0 for success or -EBUSY
++ */
++int fpga_mgr_lock(struct fpga_manager *mgr)
++{
++	if (!mutex_trylock(&mgr->ref_mutex)) {
++		dev_err(&mgr->dev, "FPGA manager is in use.\n");
++		return -EBUSY;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(fpga_mgr_lock);
++
++/**
++ * fpga_mgr_unlock - Unlock FPGA manager
++ * @mgr:	fpga manager
++ */
++void fpga_mgr_unlock(struct fpga_manager *mgr)
++{
++	mutex_unlock(&mgr->ref_mutex);
++}
++EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
++
+ /**
+  * fpga_mgr_register - register a low level fpga manager driver
+  * @dev:	fpga manager device from pdev
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 5c107ac39796..e8daac3e3d37 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -125,7 +125,7 @@ static void fpga_region_put(struct fpga_region *region)
+ }
+ 
+ /**
+- * fpga_region_get_manager - get exclusive reference for FPGA manager
++ * fpga_region_get_manager - get reference for FPGA manager
+  * @region: FPGA region
+  *
+  * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
+@@ -240,6 +240,7 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ static int fpga_region_program_fpga(struct fpga_region *region,
+ 				    struct device_node *overlay)
+ {
++	struct device *dev = &region->dev;
+ 	struct fpga_manager *mgr;
+ 	int ret;
+ 
+@@ -256,10 +257,16 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_region;
+ 	}
+ 
++	ret = fpga_mgr_lock(mgr);
++	if (ret) {
++		dev_err(dev, "FPGA manager is busy\n");
++		goto err_put_mgr;
++	}
++
+ 	ret = fpga_region_get_bridges(region, overlay);
+ 	if (ret) {
+ 		pr_err("failed to get fpga region bridges\n");
+-		goto err_put_mgr;
++		goto err_unlock_mgr;
+ 	}
+ 
+ 	ret = fpga_bridges_disable(&region->bridge_list);
+@@ -280,6 +287,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_br;
+ 	}
+ 
++	fpga_mgr_unlock(mgr);
+ 	fpga_mgr_put(mgr);
+ 	fpga_region_put(region);
+ 
+@@ -287,6 +295,8 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 
+ err_put_br:
+ 	fpga_bridges_put(&region->bridge_list);
++err_unlock_mgr:
++	fpga_mgr_unlock(mgr);
+ err_put_mgr:
+ 	fpga_mgr_put(mgr);
+ err_put_region:
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index 6b791348023b..cb5615c87504 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -155,6 +155,9 @@ void fpga_image_info_free(struct fpga_image_info *info);
+ 
+ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info);
+ 
++int fpga_mgr_lock(struct fpga_manager *mgr);
++void fpga_mgr_unlock(struct fpga_manager *mgr);
++
+ struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
+ 
+ struct fpga_manager *fpga_mgr_get(struct device *dev);
+-- 
+2.19.0
+
diff --git a/patches/1663-fpga-region-use-dev_err-instead-of-pr_err.patch b/patches/1663-fpga-region-use-dev_err-instead-of-pr_err.patch
new file mode 100644
index 00000000000000..ced800977c70f3
--- /dev/null
+++ b/patches/1663-fpga-region-use-dev_err-instead-of-pr_err.patch
@@ -0,0 +1,108 @@
+From 0d01f0d153a38cc96bf984bede238a0e2fee159c Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:14 -0600
+Subject: [PATCH 1663/1795] fpga: region: use dev_err instead of pr_err
+
+Use dev_err messages instead of pr_err.
+
+Also s/&region->dev/dev/ in two places where we already
+have dev = &region->dev.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit c3d971ad32fc19af638ac6f6ffe041aa1ff722b5)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index e8daac3e3d37..1e4edac344ce 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -102,7 +102,7 @@ static struct fpga_region *fpga_region_get(struct fpga_region *region)
+ 		return ERR_PTR(-ENODEV);
+ 	}
+ 
+-	dev_dbg(&region->dev, "get\n");
++	dev_dbg(dev, "get\n");
+ 
+ 	return region;
+ }
+@@ -116,7 +116,7 @@ static void fpga_region_put(struct fpga_region *region)
+ {
+ 	struct device *dev = &region->dev;
+ 
+-	dev_dbg(&region->dev, "put\n");
++	dev_dbg(dev, "put\n");
+ 
+ 	module_put(dev->parent->driver->owner);
+ 	of_node_put(dev->of_node);
+@@ -246,13 +246,13 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 
+ 	region = fpga_region_get(region);
+ 	if (IS_ERR(region)) {
+-		pr_err("failed to get fpga region\n");
++		dev_err(dev, "failed to get FPGA region\n");
+ 		return PTR_ERR(region);
+ 	}
+ 
+ 	mgr = fpga_region_get_manager(region);
+ 	if (IS_ERR(mgr)) {
+-		pr_err("failed to get fpga region manager\n");
++		dev_err(dev, "failed to get FPGA manager\n");
+ 		ret = PTR_ERR(mgr);
+ 		goto err_put_region;
+ 	}
+@@ -265,25 +265,25 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 
+ 	ret = fpga_region_get_bridges(region, overlay);
+ 	if (ret) {
+-		pr_err("failed to get fpga region bridges\n");
++		dev_err(dev, "failed to get FPGA bridges\n");
+ 		goto err_unlock_mgr;
+ 	}
+ 
+ 	ret = fpga_bridges_disable(&region->bridge_list);
+ 	if (ret) {
+-		pr_err("failed to disable region bridges\n");
++		dev_err(dev, "failed to disable bridges\n");
+ 		goto err_put_br;
+ 	}
+ 
+ 	ret = fpga_mgr_load(mgr, region->info);
+ 	if (ret) {
+-		pr_err("failed to load fpga image\n");
++		dev_err(dev, "failed to load FPGA image\n");
+ 		goto err_put_br;
+ 	}
+ 
+ 	ret = fpga_bridges_enable(&region->bridge_list);
+ 	if (ret) {
+-		pr_err("failed to enable region bridges\n");
++		dev_err(dev, "failed to enable region bridges\n");
+ 		goto err_put_br;
+ 	}
+ 
+@@ -414,7 +414,7 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 
+ 	/* If FPGA was externally programmed, don't specify firmware */
+ 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && info->firmware_name) {
+-		pr_err("error: specified firmware and external-fpga-config");
++		dev_err(dev, "error: specified firmware and external-fpga-config");
+ 		fpga_image_info_free(info);
+ 		return -EINVAL;
+ 	}
+@@ -427,7 +427,7 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 
+ 	/* If we got this far, we should be programming the FPGA */
+ 	if (!info->firmware_name) {
+-		pr_err("should specify firmware-name or external-fpga-config\n");
++		dev_err(dev, "should specify firmware-name or external-fpga-config\n");
+ 		fpga_image_info_free(info);
+ 		return -EINVAL;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1664-fpga-region-remove-unneeded-of_node_get-and-put.patch b/patches/1664-fpga-region-remove-unneeded-of_node_get-and-put.patch
new file mode 100644
index 00000000000000..f6df4b1e913637
--- /dev/null
+++ b/patches/1664-fpga-region-remove-unneeded-of_node_get-and-put.patch
@@ -0,0 +1,44 @@
+From bc7a2bbba9c8b7c26ced439dbcc163c6243b75d5 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:15 -0600
+Subject: [PATCH 1664/1795] fpga: region: remove unneeded of_node_get and put
+
+Remove of_node_get/put in fpga_region_get/put.  Not
+needed and will get in the way when I separate out
+the common FPGA region code from Device Tree support
+code.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 08bcb4b1a7615762e1e2c87a5c8cc5d9709b60f6)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 1e4edac344ce..5741ad6af1d2 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -94,9 +94,7 @@ static struct fpga_region *fpga_region_get(struct fpga_region *region)
+ 	}
+ 
+ 	get_device(dev);
+-	of_node_get(dev->of_node);
+ 	if (!try_module_get(dev->parent->driver->owner)) {
+-		of_node_put(dev->of_node);
+ 		put_device(dev);
+ 		mutex_unlock(&region->mutex);
+ 		return ERR_PTR(-ENODEV);
+@@ -119,7 +117,6 @@ static void fpga_region_put(struct fpga_region *region)
+ 	dev_dbg(dev, "put\n");
+ 
+ 	module_put(dev->parent->driver->owner);
+-	of_node_put(dev->of_node);
+ 	put_device(dev);
+ 	mutex_unlock(&region->mutex);
+ }
+-- 
+2.19.0
+
diff --git a/patches/1665-fpga-region-get-mgr-early-on.patch b/patches/1665-fpga-region-get-mgr-early-on.patch
new file mode 100644
index 00000000000000..c61e790e1f198a
--- /dev/null
+++ b/patches/1665-fpga-region-get-mgr-early-on.patch
@@ -0,0 +1,161 @@
+From 2004199987c92dad3cd238b78b214ac33689373e Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:16 -0600
+Subject: [PATCH 1665/1795] fpga: region: get mgr early on
+
+Get the FPGA manager during region creation.
+
+This is a baby step in refactoring the FPGA region code to
+separate out common FPGA region code from FPGA region
+Device Tree overlay support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1df2dd7f587107ebf3c8e3733410627cf5c3b3ec)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 45 +++++++++++++++++++-------------------
+ 1 file changed, 23 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 5741ad6af1d2..8c0d7bc572ed 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -31,12 +31,14 @@
+  * @dev: FPGA Region device
+  * @mutex: enforces exclusive reference to region
+  * @bridge_list: list of FPGA bridges specified in region
++ * @mgr: FPGA manager
+  * @info: fpga image specific information
+  */
+ struct fpga_region {
+ 	struct device dev;
+ 	struct mutex mutex; /* for exclusive reference to region */
+ 	struct list_head bridge_list;
++	struct fpga_manager *mgr;
+ 	struct fpga_image_info *info;
+ };
+ 
+@@ -123,7 +125,7 @@ static void fpga_region_put(struct fpga_region *region)
+ 
+ /**
+  * fpga_region_get_manager - get reference for FPGA manager
+- * @region: FPGA region
++ * @np: device node of FPGA region
+  *
+  * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
+  *
+@@ -131,10 +133,8 @@ static void fpga_region_put(struct fpga_region *region)
+  *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+-static struct fpga_manager *fpga_region_get_manager(struct fpga_region *region)
++static struct fpga_manager *fpga_region_get_manager(struct device_node *np)
+ {
+-	struct device *dev = &region->dev;
+-	struct device_node *np = dev->of_node;
+ 	struct device_node  *mgr_node;
+ 	struct fpga_manager *mgr;
+ 
+@@ -238,7 +238,6 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 				    struct device_node *overlay)
+ {
+ 	struct device *dev = &region->dev;
+-	struct fpga_manager *mgr;
+ 	int ret;
+ 
+ 	region = fpga_region_get(region);
+@@ -247,17 +246,10 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		return PTR_ERR(region);
+ 	}
+ 
+-	mgr = fpga_region_get_manager(region);
+-	if (IS_ERR(mgr)) {
+-		dev_err(dev, "failed to get FPGA manager\n");
+-		ret = PTR_ERR(mgr);
+-		goto err_put_region;
+-	}
+-
+-	ret = fpga_mgr_lock(mgr);
++	ret = fpga_mgr_lock(region->mgr);
+ 	if (ret) {
+ 		dev_err(dev, "FPGA manager is busy\n");
+-		goto err_put_mgr;
++		goto err_put_region;
+ 	}
+ 
+ 	ret = fpga_region_get_bridges(region, overlay);
+@@ -272,7 +264,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_br;
+ 	}
+ 
+-	ret = fpga_mgr_load(mgr, region->info);
++	ret = fpga_mgr_load(region->mgr, region->info);
+ 	if (ret) {
+ 		dev_err(dev, "failed to load FPGA image\n");
+ 		goto err_put_br;
+@@ -284,8 +276,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_br;
+ 	}
+ 
+-	fpga_mgr_unlock(mgr);
+-	fpga_mgr_put(mgr);
++	fpga_mgr_unlock(region->mgr);
+ 	fpga_region_put(region);
+ 
+ 	return 0;
+@@ -293,9 +284,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ err_put_br:
+ 	fpga_bridges_put(&region->bridge_list);
+ err_unlock_mgr:
+-	fpga_mgr_unlock(mgr);
+-err_put_mgr:
+-	fpga_mgr_put(mgr);
++	fpga_mgr_unlock(region->mgr);
+ err_put_region:
+ 	fpga_region_put(region);
+ 
+@@ -524,11 +513,20 @@ static int fpga_region_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct fpga_region *region;
++	struct fpga_manager *mgr;
+ 	int id, ret = 0;
+ 
++	mgr = fpga_region_get_manager(np);
++	if (IS_ERR(mgr))
++		return -EPROBE_DEFER;
++
+ 	region = kzalloc(sizeof(*region), GFP_KERNEL);
+-	if (!region)
+-		return -ENOMEM;
++	if (!region) {
++		ret = -ENOMEM;
++		goto err_put_mgr;
++	}
++
++	region->mgr = mgr;
+ 
+ 	id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL);
+ 	if (id < 0) {
+@@ -564,6 +562,8 @@ static int fpga_region_probe(struct platform_device *pdev)
+ 	ida_simple_remove(&fpga_region_ida, id);
+ err_kfree:
+ 	kfree(region);
++err_put_mgr:
++	fpga_mgr_put(mgr);
+ 
+ 	return ret;
+ }
+@@ -573,6 +573,7 @@ static int fpga_region_remove(struct platform_device *pdev)
+ 	struct fpga_region *region = platform_get_drvdata(pdev);
+ 
+ 	device_unregister(&region->dev);
++	fpga_mgr_put(region->mgr);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1666-fpga-region-check-for-child-regions-before-allocing-.patch b/patches/1666-fpga-region-check-for-child-regions-before-allocing-.patch
new file mode 100644
index 00000000000000..56d9c95b4aab20
--- /dev/null
+++ b/patches/1666-fpga-region-check-for-child-regions-before-allocing-.patch
@@ -0,0 +1,56 @@
+From 0ccd9979d2a8dc42a4c4dba68e1116dd71c4bbab Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:17 -0600
+Subject: [PATCH 1666/1795] fpga: region: check for child regions before
+ allocing image info
+
+During a device tree overlay pre-apply notification, the check
+for child FPGA regions can happen slightly earlier.  This saves
+us from allocating the FPGA image info that just gets thrown
+away.
+
+This is a baby step in refactoring the FPGA region code to
+separate out common FPGA region code from FPGA region
+Device Tree overlay support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1743df83ae5a949037eb86a12f225abd4374d176)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 8c0d7bc572ed..a921c3c035db 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -362,15 +362,19 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	const char *firmware_name;
+ 	int ret;
+ 
+-	info = fpga_image_info_alloc(dev);
+-	if (!info)
+-		return -ENOMEM;
+-
+-	/* Reject overlay if child FPGA Regions have firmware-name property */
++	/*
++	 * Reject overlay if child FPGA Regions added in the overlay have
++	 * firmware-name property (would mean that an FPGA region that has
++	 * not been added to the live tree yet is doing FPGA programming).
++	 */
+ 	ret = child_regions_with_firmware(nd->overlay);
+ 	if (ret)
+ 		return ret;
+ 
++	info = fpga_image_info_alloc(dev);
++	if (!info)
++		return -ENOMEM;
++
+ 	/* Read FPGA region properties from the overlay */
+ 	if (of_property_read_bool(nd->overlay, "partial-fpga-config"))
+ 		info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
+-- 
+2.19.0
+
diff --git a/patches/1667-fpga-region-fix-slow-warning-with-more-than-one-over.patch b/patches/1667-fpga-region-fix-slow-warning-with-more-than-one-over.patch
new file mode 100644
index 00000000000000..29bde50410e862
--- /dev/null
+++ b/patches/1667-fpga-region-fix-slow-warning-with-more-than-one-over.patch
@@ -0,0 +1,47 @@
+From 2270e68a5295327d3501ac69ea241aaed7546d09 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:18 -0600
+Subject: [PATCH 1667/1795] fpga: region: fix slow warning with more than one
+ overlay
+
+When DT overlays are applied, each FPGA region keeps track of the fpga
+image info as region->info.  This pointer is assigned only if an
+overlay causes the FPGA to be programmed.  As it stands, this pointer
+can be overwritten, causing a slow warning later when overlays are
+removed.
+
+This patch fixes this by changing the allowed behaviour.  If a region
+has received an overlay that programmed the FPGA, reject other
+overlays that try to program the FPGA.  To reprogram the FPGA, first
+remove the overlay.  This makes sense as removing the overlay also
+removes the devices cleanly.  Note that overlays that make DT changes
+without reprogramming the FPGA are exempt from this restriction.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ed81f5fc3c35c22d0fc62813cfa4e11b6aea0a64)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index a921c3c035db..93e7ce9bc6e3 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -362,6 +362,11 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	const char *firmware_name;
+ 	int ret;
+ 
++	if (region->info) {
++		dev_err(dev, "Region already has overlay applied.\n");
++		return -EINVAL;
++	}
++
+ 	/*
+ 	 * Reject overlay if child FPGA Regions added in the overlay have
+ 	 * firmware-name property (would mean that an FPGA region that has
+-- 
+2.19.0
+
diff --git a/patches/1668-fpga-region-use-image-info-as-parameter-for-programm.patch b/patches/1668-fpga-region-use-image-info-as-parameter-for-programm.patch
new file mode 100644
index 00000000000000..0874978f4590fa
--- /dev/null
+++ b/patches/1668-fpga-region-use-image-info-as-parameter-for-programm.patch
@@ -0,0 +1,107 @@
+From f998b6775de00881f36cfd93614ba01228bf7cde Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:19 -0600
+Subject: [PATCH 1668/1795] fpga: region: use image info as parameter for
+ programming region
+
+Use FPGA image info (region->info) when region code is
+programming the FPGA to pass in multiple parameters.
+
+This is a baby step in refactoring the FPGA region code to
+separate out common FPGA region code from FPGA region
+Device Tree overlay support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 61c32102391ff38dfd4aba835dd0f99db6b46908)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c    | 16 +++++++++-------
+ include/linux/fpga/fpga-mgr.h |  4 ++++
+ 2 files changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 93e7ce9bc6e3..13aa08631f7a 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -230,14 +230,13 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ /**
+  * fpga_region_program_fpga - program FPGA
+  * @region: FPGA region
+- * @overlay: device node of the overlay
+- * Program an FPGA using information in the region's fpga image info.
++ * Program an FPGA using fpga image info (region->info).
+  * Return 0 for success or negative error code.
+  */
+-static int fpga_region_program_fpga(struct fpga_region *region,
+-				    struct device_node *overlay)
++static int fpga_region_program_fpga(struct fpga_region *region)
+ {
+ 	struct device *dev = &region->dev;
++	struct fpga_image_info *info = region->info;
+ 	int ret;
+ 
+ 	region = fpga_region_get(region);
+@@ -252,7 +251,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_region;
+ 	}
+ 
+-	ret = fpga_region_get_bridges(region, overlay);
++	ret = fpga_region_get_bridges(region, info->overlay);
+ 	if (ret) {
+ 		dev_err(dev, "failed to get FPGA bridges\n");
+ 		goto err_unlock_mgr;
+@@ -264,7 +263,7 @@ static int fpga_region_program_fpga(struct fpga_region *region,
+ 		goto err_put_br;
+ 	}
+ 
+-	ret = fpga_mgr_load(region->mgr, region->info);
++	ret = fpga_mgr_load(region->mgr, info);
+ 	if (ret) {
+ 		dev_err(dev, "failed to load FPGA image\n");
+ 		goto err_put_br;
+@@ -380,6 +379,8 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	if (!info)
+ 		return -ENOMEM;
+ 
++	info->overlay = nd->overlay;
++
+ 	/* Read FPGA region properties from the overlay */
+ 	if (of_property_read_bool(nd->overlay, "partial-fpga-config"))
+ 		info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
+@@ -428,7 +429,8 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	}
+ 
+ 	region->info = info;
+-	ret = fpga_region_program_fpga(region, nd->overlay);
++
++	ret = fpga_region_program_fpga(region);
+ 	if (ret) {
+ 		fpga_image_info_free(info);
+ 		region->info = NULL;
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index cb5615c87504..4fb706bd9aba 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -89,6 +89,7 @@ enum fpga_mgr_states {
+  * @buf: contiguous buffer containing FPGA image
+  * @count: size of buf
+  * @dev: device that owns this
++ * @overlay: Device Tree overlay
+  */
+ struct fpga_image_info {
+ 	u32 flags;
+@@ -100,6 +101,9 @@ struct fpga_image_info {
+ 	const char *buf;
+ 	size_t count;
+ 	struct device *dev;
++#ifdef CONFIG_OF
++	struct device_node *overlay;
++#endif
+ };
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1669-fpga-region-separate-out-code-that-parses-the-overla.patch b/patches/1669-fpga-region-separate-out-code-that-parses-the-overla.patch
new file mode 100644
index 00000000000000..bcf4ee7c5273c9
--- /dev/null
+++ b/patches/1669-fpga-region-separate-out-code-that-parses-the-overla.patch
@@ -0,0 +1,213 @@
+From a32d099c3653b110a5af7cb71c755423ba823f60 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:20 -0600
+Subject: [PATCH 1669/1795] fpga: region: separate out code that parses the
+ overlay
+
+New function of_fpga_region_parse_ov added, moving code
+from fpga_region_notify_pre_apply.  This function
+gets the FPGA image info from the overlay and is able
+to simplify some of the logic involved.
+
+This is a baby step in refactoring the FPGA region code to
+separate out common code from Device Tree overlay support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit c8898eda81e0b949ca214e1a45ce1b56677eb849)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 122 ++++++++++++++++++++++---------------
+ 1 file changed, 73 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 13aa08631f7a..435aab39c182 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -328,33 +328,22 @@ static int child_regions_with_firmware(struct device_node *overlay)
+ }
+ 
+ /**
+- * fpga_region_notify_pre_apply - pre-apply overlay notification
+- *
+- * @region: FPGA region that the overlay was applied to
+- * @nd: overlay notification data
+- *
+- * Called after when an overlay targeted to a FPGA Region is about to be
+- * applied.  Function will check the properties that will be added to the FPGA
+- * region.  If the checks pass, it will program the FPGA.
+- *
+- * The checks are:
+- * The overlay must add either firmware-name or external-fpga-config property
+- * to the FPGA Region.
+- *
+- *   firmware-name         : program the FPGA
+- *   external-fpga-config  : FPGA is already programmed
+- *   encrypted-fpga-config : FPGA bitstream is encrypted
++ * of_fpga_region_parse_ov - parse and check overlay applied to region
+  *
+- * The overlay can add other FPGA regions, but child FPGA regions cannot have a
+- * firmware-name property since those regions don't exist yet.
++ * @region: FPGA region
++ * @overlay: overlay applied to the FPGA region
+  *
+- * If the overlay that breaks the rules, notifier returns an error and the
+- * overlay is rejected before it goes into the main tree.
++ * Given an overlay applied to a FPGA region, parse the FPGA image specific
++ * info in the overlay and do some checking.
+  *
+- * Returns 0 for success or negative error code for failure.
++ * Returns:
++ *   NULL if overlay doesn't direct us to program the FPGA.
++ *   fpga_image_info struct if there is an image to program.
++ *   error code for invalid overlay.
+  */
+-static int fpga_region_notify_pre_apply(struct fpga_region *region,
+-					struct of_overlay_notify_data *nd)
++static struct fpga_image_info *of_fpga_region_parse_ov(
++						struct fpga_region *region,
++						struct device_node *overlay)
+ {
+ 	struct device *dev = &region->dev;
+ 	struct fpga_image_info *info;
+@@ -363,7 +352,7 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 
+ 	if (region->info) {
+ 		dev_err(dev, "Region already has overlay applied.\n");
+-		return -EINVAL;
++		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	/*
+@@ -371,67 +360,102 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	 * firmware-name property (would mean that an FPGA region that has
+ 	 * not been added to the live tree yet is doing FPGA programming).
+ 	 */
+-	ret = child_regions_with_firmware(nd->overlay);
++	ret = child_regions_with_firmware(overlay);
+ 	if (ret)
+-		return ret;
++		return ERR_PTR(ret);
+ 
+ 	info = fpga_image_info_alloc(dev);
+ 	if (!info)
+-		return -ENOMEM;
++		return ERR_PTR(-ENOMEM);
+ 
+-	info->overlay = nd->overlay;
++	info->overlay = overlay;
+ 
+ 	/* Read FPGA region properties from the overlay */
+-	if (of_property_read_bool(nd->overlay, "partial-fpga-config"))
++	if (of_property_read_bool(overlay, "partial-fpga-config"))
+ 		info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
+ 
+-	if (of_property_read_bool(nd->overlay, "external-fpga-config"))
++	if (of_property_read_bool(overlay, "external-fpga-config"))
+ 		info->flags |= FPGA_MGR_EXTERNAL_CONFIG;
+ 
+-	if (of_property_read_bool(nd->overlay, "encrypted-fpga-config"))
++	if (of_property_read_bool(overlay, "encrypted-fpga-config"))
+ 		info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
+ 
+-	if (!of_property_read_string(nd->overlay, "firmware-name",
++	if (!of_property_read_string(overlay, "firmware-name",
+ 				     &firmware_name)) {
+ 		info->firmware_name = devm_kstrdup(dev, firmware_name,
+ 						   GFP_KERNEL);
+ 		if (!info->firmware_name)
+-			return -ENOMEM;
++			return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	of_property_read_u32(nd->overlay, "region-unfreeze-timeout-us",
++	of_property_read_u32(overlay, "region-unfreeze-timeout-us",
+ 			     &info->enable_timeout_us);
+ 
+-	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
++	of_property_read_u32(overlay, "region-freeze-timeout-us",
+ 			     &info->disable_timeout_us);
+ 
+-	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
++	of_property_read_u32(overlay, "config-complete-timeout-us",
+ 			     &info->config_complete_timeout_us);
+ 
+-	/* If FPGA was externally programmed, don't specify firmware */
+-	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && info->firmware_name) {
+-		dev_err(dev, "error: specified firmware and external-fpga-config");
+-		fpga_image_info_free(info);
+-		return -EINVAL;
++	/* If overlay is not programming the FPGA, don't need FPGA image info */
++	if (!info->firmware_name) {
++		ret = 0;
++		goto ret_no_info;
+ 	}
+ 
+-	/* FPGA is already configured externally.  We're done. */
++	/*
++	 * If overlay informs us FPGA was externally programmed, specifying
++	 * firmware here would be ambiguous.
++	 */
+ 	if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) {
+-		fpga_image_info_free(info);
+-		return 0;
++		dev_err(dev, "error: specified firmware and external-fpga-config");
++		ret = -EINVAL;
++		goto ret_no_info;
+ 	}
+ 
+-	/* If we got this far, we should be programming the FPGA */
+-	if (!info->firmware_name) {
+-		dev_err(dev, "should specify firmware-name or external-fpga-config\n");
+-		fpga_image_info_free(info);
++	return info;
++ret_no_info:
++	fpga_image_info_free(info);
++	return ERR_PTR(ret);
++}
++
++/**
++ * fpga_region_notify_pre_apply - pre-apply overlay notification
++ *
++ * @region: FPGA region that the overlay was applied to
++ * @nd: overlay notification data
++ *
++ * Called when an overlay targeted to a FPGA Region is about to be applied.
++ * Parses the overlay for properties that influence how the FPGA will be
++ * programmed and does some checking. If the checks pass, programs the FPGA.
++ * If the checks fail, overlay is rejected and does not get added to the
++ * live tree.
++ *
++ * Returns 0 for success or negative error code for failure.
++ */
++static int fpga_region_notify_pre_apply(struct fpga_region *region,
++					struct of_overlay_notify_data *nd)
++{
++	struct device *dev = &region->dev;
++	struct fpga_image_info *info;
++	int ret;
++
++	if (region->info) {
++		dev_err(dev, "Region already has overlay applied.\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	region->info = info;
++	info = of_fpga_region_parse_ov(region, nd->overlay);
++	if (IS_ERR(info))
++		return PTR_ERR(info);
++
++	if (!info)
++		return 0;
+ 
++	region->info = info;
+ 	ret = fpga_region_program_fpga(region);
+ 	if (ret) {
++		/* error; reject overlay */
+ 		fpga_image_info_free(info);
+ 		region->info = NULL;
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1670-fpga-region-add-fpga-region.h-header.patch b/patches/1670-fpga-region-add-fpga-region.h-header.patch
new file mode 100644
index 00000000000000..e52c81ce826040
--- /dev/null
+++ b/patches/1670-fpga-region-add-fpga-region.h-header.patch
@@ -0,0 +1,121 @@
+From 998a488f5372a0ddde3baf9ca805ba2669fce0a0 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:21 -0600
+Subject: [PATCH 1670/1795] fpga: region: add fpga-region.h header
+
+* Create fpga-region.h.
+* Export fpga_region_program_fpga.
+* Move struct fpga_region and other things to the header.
+
+This is a step in separating FPGA region common code
+from Device Tree support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 59460a9305458ac3e7f2415b602dbaa6cfcb8a3b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c       | 24 ++++--------------------
+ include/linux/fpga/fpga-region.h | 28 ++++++++++++++++++++++++++++
+ 2 files changed, 32 insertions(+), 20 deletions(-)
+ create mode 100644 include/linux/fpga/fpga-region.h
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 435aab39c182..23527c1b2fa7 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -18,6 +18,7 @@
+ 
+ #include <linux/fpga/fpga-bridge.h>
+ #include <linux/fpga/fpga-mgr.h>
++#include <linux/fpga/fpga-region.h>
+ #include <linux/idr.h>
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+@@ -26,24 +27,6 @@
+ #include <linux/slab.h>
+ #include <linux/spinlock.h>
+ 
+-/**
+- * struct fpga_region - FPGA Region structure
+- * @dev: FPGA Region device
+- * @mutex: enforces exclusive reference to region
+- * @bridge_list: list of FPGA bridges specified in region
+- * @mgr: FPGA manager
+- * @info: fpga image specific information
+- */
+-struct fpga_region {
+-	struct device dev;
+-	struct mutex mutex; /* for exclusive reference to region */
+-	struct list_head bridge_list;
+-	struct fpga_manager *mgr;
+-	struct fpga_image_info *info;
+-};
+-
+-#define to_fpga_region(d) container_of(d, struct fpga_region, dev)
+-
+ static DEFINE_IDA(fpga_region_ida);
+ static struct class *fpga_region_class;
+ 
+@@ -233,7 +216,7 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+  * Program an FPGA using fpga image info (region->info).
+  * Return 0 for success or negative error code.
+  */
+-static int fpga_region_program_fpga(struct fpga_region *region)
++int fpga_region_program_fpga(struct fpga_region *region)
+ {
+ 	struct device *dev = &region->dev;
+ 	struct fpga_image_info *info = region->info;
+@@ -289,6 +272,7 @@ static int fpga_region_program_fpga(struct fpga_region *region)
+ 
+ 	return ret;
+ }
++EXPORT_SYMBOL_GPL(fpga_region_program_fpga);
+ 
+ /**
+  * child_regions_with_firmware
+@@ -674,5 +658,5 @@ subsys_initcall(fpga_region_init);
+ module_exit(fpga_region_exit);
+ 
+ MODULE_DESCRIPTION("FPGA Region");
+-MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
++MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
+ MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+new file mode 100644
+index 000000000000..8a355171406b
+--- /dev/null
++++ b/include/linux/fpga/fpga-region.h
+@@ -0,0 +1,28 @@
++#ifndef _FPGA_REGION_H
++#define _FPGA_REGION_H
++
++#include <linux/device.h>
++#include <linux/fpga/fpga-mgr.h>
++#include <linux/fpga/fpga-bridge.h>
++
++/**
++ * struct fpga_region - FPGA Region structure
++ * @dev: FPGA Region device
++ * @mutex: enforces exclusive reference to region
++ * @bridge_list: list of FPGA bridges specified in region
++ * @mgr: FPGA manager
++ * @info: FPGA image info
++ */
++struct fpga_region {
++	struct device dev;
++	struct mutex mutex; /* for exclusive reference to region */
++	struct list_head bridge_list;
++	struct fpga_manager *mgr;
++	struct fpga_image_info *info;
++};
++
++#define to_fpga_region(d) container_of(d, struct fpga_region, dev)
++
++int fpga_region_program_fpga(struct fpga_region *region);
++
++#endif /* _FPGA_REGION_H */
+-- 
+2.19.0
+
diff --git a/patches/1671-fpga-region-rename-some-functions-prior-to-moving.patch b/patches/1671-fpga-region-rename-some-functions-prior-to-moving.patch
new file mode 100644
index 00000000000000..847f2b65e6eb44
--- /dev/null
+++ b/patches/1671-fpga-region-rename-some-functions-prior-to-moving.patch
@@ -0,0 +1,254 @@
+From 5e61e32e22f5954465a560bdd559415fa7a9238f Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:22 -0600
+Subject: [PATCH 1671/1795] fpga: region: rename some functions prior to moving
+
+Rename some functions that will be moved to
+of-fpga-region.c.  Also change some parameters
+and export a function to help with refactoring.
+
+This is a step towards the larger goal of separating
+device tree support from FPGA region common code.
+
+* fpga_region_get_manager -> of_fpga_region_get_mgr
+
+* add 'of_' prefix to the following:
+  * fpga_region_find
+  * fpga_region_get_bridges
+  * fpga_region_notify_pre_apply
+  * fpga_region_notify_post_remove),
+  * fpga_region_probe/remove
+
+Parameter changes:
+* of_fpga_region_find
+  change parameter to be the device node of the region.
+* of_fpga_region_get_bridges
+  change second parameter to FPGA image info.
+
+Export of_fpga_region_find as well.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 3b49537f8084af15ccaac542eaf317e01c6869e6)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 60 ++++++++++++++++++++------------------
+ 1 file changed, 31 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 23527c1b2fa7..7ce9f37ac494 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -42,12 +42,14 @@ static int fpga_region_of_node_match(struct device *dev, const void *data)
+ }
+ 
+ /**
+- * fpga_region_find - find FPGA region
++ * of_fpga_region_find - find FPGA region
+  * @np: device node of FPGA Region
++ *
+  * Caller will need to put_device(&region->dev) when done.
++ *
+  * Returns FPGA Region struct or NULL
+  */
+-static struct fpga_region *fpga_region_find(struct device_node *np)
++static struct fpga_region *of_fpga_region_find(struct device_node *np)
+ {
+ 	struct device *dev;
+ 
+@@ -107,7 +109,7 @@ static void fpga_region_put(struct fpga_region *region)
+ }
+ 
+ /**
+- * fpga_region_get_manager - get reference for FPGA manager
++ * of_fpga_region_get_mgr - get reference for FPGA manager
+  * @np: device node of FPGA region
+  *
+  * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
+@@ -116,7 +118,7 @@ static void fpga_region_put(struct fpga_region *region)
+  *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+-static struct fpga_manager *fpga_region_get_manager(struct device_node *np)
++static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
+ {
+ 	struct device_node  *mgr_node;
+ 	struct fpga_manager *mgr;
+@@ -140,9 +142,9 @@ static struct fpga_manager *fpga_region_get_manager(struct device_node *np)
+ }
+ 
+ /**
+- * fpga_region_get_bridges - create a list of bridges
++ * of_fpga_region_get_bridges - create a list of bridges
+  * @region: FPGA region
+- * @overlay: device node of the overlay
++ * @info: FPGA image info
+  *
+  * Create a list of bridges including the parent bridge and the bridges
+  * specified by "fpga-bridges" property.  Note that the
+@@ -155,8 +157,8 @@ static struct fpga_manager *fpga_region_get_manager(struct device_node *np)
+  * Return 0 for success (even if there are no bridges specified)
+  * or -EBUSY if any of the bridges are in use.
+  */
+-static int fpga_region_get_bridges(struct fpga_region *region,
+-				   struct device_node *overlay)
++static int of_fpga_region_get_bridges(struct fpga_region *region,
++				      struct fpga_image_info *info)
+ {
+ 	struct device *dev = &region->dev;
+ 	struct device_node *region_np = dev->of_node;
+@@ -164,7 +166,7 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ 	int i, ret;
+ 
+ 	/* If parent is a bridge, add to list */
+-	ret = of_fpga_bridge_get_to_list(region_np->parent, region->info,
++	ret = of_fpga_bridge_get_to_list(region_np->parent, info,
+ 					 &region->bridge_list);
+ 
+ 	/* -EBUSY means parent is a bridge that is under use. Give up. */
+@@ -176,10 +178,10 @@ static int fpga_region_get_bridges(struct fpga_region *region,
+ 		parent_br = region_np->parent;
+ 
+ 	/* If overlay has a list of bridges, use it. */
+-	br = of_parse_phandle(overlay, "fpga-bridges", 0);
++	br = of_parse_phandle(info->overlay, "fpga-bridges", 0);
+ 	if (br) {
+ 		of_node_put(br);
+-		np = overlay;
++		np = info->overlay;
+ 	} else {
+ 		np = region_np;
+ 	}
+@@ -234,7 +236,7 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ 		goto err_put_region;
+ 	}
+ 
+-	ret = fpga_region_get_bridges(region, info->overlay);
++	ret = of_fpga_region_get_bridges(region, info);
+ 	if (ret) {
+ 		dev_err(dev, "failed to get FPGA bridges\n");
+ 		goto err_unlock_mgr;
+@@ -404,7 +406,7 @@ static struct fpga_image_info *of_fpga_region_parse_ov(
+ }
+ 
+ /**
+- * fpga_region_notify_pre_apply - pre-apply overlay notification
++ * of_fpga_region_notify_pre_apply - pre-apply overlay notification
+  *
+  * @region: FPGA region that the overlay was applied to
+  * @nd: overlay notification data
+@@ -417,8 +419,8 @@ static struct fpga_image_info *of_fpga_region_parse_ov(
+  *
+  * Returns 0 for success or negative error code for failure.
+  */
+-static int fpga_region_notify_pre_apply(struct fpga_region *region,
+-					struct of_overlay_notify_data *nd)
++static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
++					   struct of_overlay_notify_data *nd)
+ {
+ 	struct device *dev = &region->dev;
+ 	struct fpga_image_info *info;
+@@ -448,7 +450,7 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+ }
+ 
+ /**
+- * fpga_region_notify_post_remove - post-remove overlay notification
++ * of_fpga_region_notify_post_remove - post-remove overlay notification
+  *
+  * @region: FPGA region that was targeted by the overlay that was removed
+  * @nd: overlay notification data
+@@ -456,8 +458,8 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
+  * Called after an overlay has been removed if the overlay's target was a
+  * FPGA region.
+  */
+-static void fpga_region_notify_post_remove(struct fpga_region *region,
+-					   struct of_overlay_notify_data *nd)
++static void of_fpga_region_notify_post_remove(struct fpga_region *region,
++					      struct of_overlay_notify_data *nd)
+ {
+ 	fpga_bridges_disable(&region->bridge_list);
+ 	fpga_bridges_put(&region->bridge_list);
+@@ -500,18 +502,18 @@ static int of_fpga_region_notify(struct notifier_block *nb,
+ 		return NOTIFY_OK;
+ 	}
+ 
+-	region = fpga_region_find(nd->target);
++	region = of_fpga_region_find(nd->target);
+ 	if (!region)
+ 		return NOTIFY_OK;
+ 
+ 	ret = 0;
+ 	switch (action) {
+ 	case OF_OVERLAY_PRE_APPLY:
+-		ret = fpga_region_notify_pre_apply(region, nd);
++		ret = of_fpga_region_notify_pre_apply(region, nd);
+ 		break;
+ 
+ 	case OF_OVERLAY_POST_REMOVE:
+-		fpga_region_notify_post_remove(region, nd);
++		of_fpga_region_notify_post_remove(region, nd);
+ 		break;
+ 	}
+ 
+@@ -527,7 +529,7 @@ static struct notifier_block fpga_region_of_nb = {
+ 	.notifier_call = of_fpga_region_notify,
+ };
+ 
+-static int fpga_region_probe(struct platform_device *pdev)
++static int of_fpga_region_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+@@ -535,7 +537,7 @@ static int fpga_region_probe(struct platform_device *pdev)
+ 	struct fpga_manager *mgr;
+ 	int id, ret = 0;
+ 
+-	mgr = fpga_region_get_manager(np);
++	mgr = of_fpga_region_get_mgr(np);
+ 	if (IS_ERR(mgr))
+ 		return -EPROBE_DEFER;
+ 
+@@ -587,7 +589,7 @@ static int fpga_region_probe(struct platform_device *pdev)
+ 	return ret;
+ }
+ 
+-static int fpga_region_remove(struct platform_device *pdev)
++static int of_fpga_region_remove(struct platform_device *pdev)
+ {
+ 	struct fpga_region *region = platform_get_drvdata(pdev);
+ 
+@@ -597,9 +599,9 @@ static int fpga_region_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
+-static struct platform_driver fpga_region_driver = {
+-	.probe = fpga_region_probe,
+-	.remove = fpga_region_remove,
++static struct platform_driver of_fpga_region_driver = {
++	.probe = of_fpga_region_probe,
++	.remove = of_fpga_region_remove,
+ 	.driver = {
+ 		.name	= "fpga-region",
+ 		.of_match_table = of_match_ptr(fpga_region_of_match),
+@@ -632,7 +634,7 @@ static int __init fpga_region_init(void)
+ 	if (ret)
+ 		goto err_class;
+ 
+-	ret = platform_driver_register(&fpga_region_driver);
++	ret = platform_driver_register(&of_fpga_region_driver);
+ 	if (ret)
+ 		goto err_plat;
+ 
+@@ -648,7 +650,7 @@ static int __init fpga_region_init(void)
+ 
+ static void __exit fpga_region_exit(void)
+ {
+-	platform_driver_unregister(&fpga_region_driver);
++	platform_driver_unregister(&of_fpga_region_driver);
+ 	of_overlay_notifier_unregister(&fpga_region_of_nb);
+ 	class_destroy(fpga_region_class);
+ 	ida_destroy(&fpga_region_ida);
+-- 
+2.19.0
+
diff --git a/patches/1672-fpga-region-add-register-unregister-functions.patch b/patches/1672-fpga-region-add-register-unregister-functions.patch
new file mode 100644
index 00000000000000..862ef0364a85d1
--- /dev/null
+++ b/patches/1672-fpga-region-add-register-unregister-functions.patch
@@ -0,0 +1,249 @@
+From fa29a88c64c47c9abdcd43e49e64fce2c197fbf5 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:23 -0600
+Subject: [PATCH 1672/1795] fpga: region: add register/unregister functions
+
+Another step in separating common code from device tree specific
+code for FPGA regions.
+
+* add FPGA region register/unregister functions.
+* add the register/unregister functions to the header
+* use devm_kzalloc to alloc the region.
+* add a method for getting bridges to the region struct
+* add priv to the region struct
+* use region->info in of_fpga_region_get_bridges
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 52a3a7ccce07e73323fc1bae9eb0b0b63375391c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c       | 105 +++++++++++++++++++------------
+ include/linux/fpga/fpga-region.h |   7 +++
+ 2 files changed, 72 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 7ce9f37ac494..f06f74911313 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -144,7 +144,6 @@ static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
+ /**
+  * of_fpga_region_get_bridges - create a list of bridges
+  * @region: FPGA region
+- * @info: FPGA image info
+  *
+  * Create a list of bridges including the parent bridge and the bridges
+  * specified by "fpga-bridges" property.  Note that the
+@@ -157,11 +156,11 @@ static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
+  * Return 0 for success (even if there are no bridges specified)
+  * or -EBUSY if any of the bridges are in use.
+  */
+-static int of_fpga_region_get_bridges(struct fpga_region *region,
+-				      struct fpga_image_info *info)
++static int of_fpga_region_get_bridges(struct fpga_region *region)
+ {
+ 	struct device *dev = &region->dev;
+ 	struct device_node *region_np = dev->of_node;
++	struct fpga_image_info *info = region->info;
+ 	struct device_node *br, *np, *parent_br = NULL;
+ 	int i, ret;
+ 
+@@ -198,7 +197,7 @@ static int of_fpga_region_get_bridges(struct fpga_region *region,
+ 		}
+ 
+ 		/* If node is a bridge, get it and add to list */
+-		ret = of_fpga_bridge_get_to_list(br, region->info,
++		ret = of_fpga_bridge_get_to_list(br, info,
+ 						 &region->bridge_list);
+ 		of_node_put(br);
+ 
+@@ -236,10 +235,16 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ 		goto err_put_region;
+ 	}
+ 
+-	ret = of_fpga_region_get_bridges(region, info);
+-	if (ret) {
+-		dev_err(dev, "failed to get FPGA bridges\n");
+-		goto err_unlock_mgr;
++	/*
++	 * In some cases, we already have a list of bridges in the
++	 * fpga region struct.  Or we don't have any bridges.
++	 */
++	if (region->get_bridges) {
++		ret = region->get_bridges(region);
++		if (ret) {
++			dev_err(dev, "failed to get fpga region bridges\n");
++			goto err_unlock_mgr;
++		}
+ 	}
+ 
+ 	ret = fpga_bridges_disable(&region->bridge_list);
+@@ -266,7 +271,8 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ 	return 0;
+ 
+ err_put_br:
+-	fpga_bridges_put(&region->bridge_list);
++	if (region->get_bridges)
++		fpga_bridges_put(&region->bridge_list);
+ err_unlock_mgr:
+ 	fpga_mgr_unlock(region->mgr);
+ err_put_region:
+@@ -529,39 +535,20 @@ static struct notifier_block fpga_region_of_nb = {
+ 	.notifier_call = of_fpga_region_notify,
+ };
+ 
+-static int of_fpga_region_probe(struct platform_device *pdev)
++int fpga_region_register(struct device *dev, struct fpga_region *region)
+ {
+-	struct device *dev = &pdev->dev;
+-	struct device_node *np = dev->of_node;
+-	struct fpga_region *region;
+-	struct fpga_manager *mgr;
+ 	int id, ret = 0;
+ 
+-	mgr = of_fpga_region_get_mgr(np);
+-	if (IS_ERR(mgr))
+-		return -EPROBE_DEFER;
+-
+-	region = kzalloc(sizeof(*region), GFP_KERNEL);
+-	if (!region) {
+-		ret = -ENOMEM;
+-		goto err_put_mgr;
+-	}
+-
+-	region->mgr = mgr;
+-
+ 	id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL);
+-	if (id < 0) {
+-		ret = id;
+-		goto err_kfree;
+-	}
++	if (id < 0)
++		return id;
+ 
+ 	mutex_init(&region->mutex);
+ 	INIT_LIST_HEAD(&region->bridge_list);
+-
+ 	device_initialize(&region->dev);
+ 	region->dev.class = fpga_region_class;
+ 	region->dev.parent = dev;
+-	region->dev.of_node = np;
++	region->dev.of_node = dev->of_node;
+ 	region->dev.id = id;
+ 	dev_set_drvdata(dev, region);
+ 
+@@ -573,19 +560,58 @@ static int of_fpga_region_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		goto err_remove;
+ 
++	return 0;
++
++err_remove:
++	ida_simple_remove(&fpga_region_ida, id);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(fpga_region_register);
++
++int fpga_region_unregister(struct fpga_region *region)
++{
++	device_unregister(&region->dev);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(fpga_region_unregister);
++
++static int of_fpga_region_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct fpga_region *region;
++	struct fpga_manager *mgr;
++	int ret;
++
++	/* Find the FPGA mgr specified by region or parent region. */
++	mgr = of_fpga_region_get_mgr(np);
++	if (IS_ERR(mgr))
++		return -EPROBE_DEFER;
++
++	region = devm_kzalloc(dev, sizeof(*region), GFP_KERNEL);
++	if (!region) {
++		ret = -ENOMEM;
++		goto eprobe_mgr_put;
++	}
++
++	region->mgr = mgr;
++
++	/* Specify how to get bridges for this type of region. */
++	region->get_bridges = of_fpga_region_get_bridges;
++
++	ret = fpga_region_register(dev, region);
++	if (ret)
++		goto eprobe_mgr_put;
++
+ 	of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
+ 
+ 	dev_info(dev, "FPGA Region probed\n");
+ 
+ 	return 0;
+ 
+-err_remove:
+-	ida_simple_remove(&fpga_region_ida, id);
+-err_kfree:
+-	kfree(region);
+-err_put_mgr:
++eprobe_mgr_put:
+ 	fpga_mgr_put(mgr);
+-
+ 	return ret;
+ }
+ 
+@@ -593,7 +619,7 @@ static int of_fpga_region_remove(struct platform_device *pdev)
+ {
+ 	struct fpga_region *region = platform_get_drvdata(pdev);
+ 
+-	device_unregister(&region->dev);
++	fpga_region_unregister(region);
+ 	fpga_mgr_put(region->mgr);
+ 
+ 	return 0;
+@@ -613,7 +639,6 @@ static void fpga_region_dev_release(struct device *dev)
+ 	struct fpga_region *region = to_fpga_region(dev);
+ 
+ 	ida_simple_remove(&fpga_region_ida, region->dev.id);
+-	kfree(region);
+ }
+ 
+ /**
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index 8a355171406b..8c8a3249f96c 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -12,6 +12,8 @@
+  * @bridge_list: list of FPGA bridges specified in region
+  * @mgr: FPGA manager
+  * @info: FPGA image info
++ * @priv: private data
++ * @get_bridges: optional function to get bridges to a list
+  */
+ struct fpga_region {
+ 	struct device dev;
+@@ -19,10 +21,15 @@ struct fpga_region {
+ 	struct list_head bridge_list;
+ 	struct fpga_manager *mgr;
+ 	struct fpga_image_info *info;
++	void *priv;
++	int (*get_bridges)(struct fpga_region *region);
+ };
+ 
+ #define to_fpga_region(d) container_of(d, struct fpga_region, dev)
+ 
+ int fpga_region_program_fpga(struct fpga_region *region);
+ 
++int fpga_region_register(struct device *dev, struct fpga_region *region);
++int fpga_region_unregister(struct fpga_region *region);
++
+ #endif /* _FPGA_REGION_H */
+-- 
+2.19.0
+
diff --git a/patches/1673-fpga-region-add-fpga_region_class_find.patch b/patches/1673-fpga-region-add-fpga_region_class_find.patch
new file mode 100644
index 00000000000000..a74a5b5551f384
--- /dev/null
+++ b/patches/1673-fpga-region-add-fpga_region_class_find.patch
@@ -0,0 +1,82 @@
+From cac1292938148995fd6081d4de1c7b1fac74d67c Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:24 -0600
+Subject: [PATCH 1673/1795] fpga: region: add fpga_region_class_find
+
+Add a function for searching the fpga-region class.  This
+will be useful when device tree code is no longer in the
+same file that declares the fpga-region class.  Another
+step in separating common FPGA region code from device
+tree support.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 503d4b7a446b3838785fa7f21e339941a5d1c2d5)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c       | 23 +++++++++++++++--------
+ include/linux/fpga/fpga-region.h |  5 ++++-
+ 2 files changed, 19 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index f06f74911313..4e5580aacaee 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -30,6 +30,20 @@
+ static DEFINE_IDA(fpga_region_ida);
+ static struct class *fpga_region_class;
+ 
++struct fpga_region *fpga_region_class_find(
++	struct device *start, const void *data,
++	int (*match)(struct device *, const void *))
++{
++	struct device *dev;
++
++	dev = class_find_device(fpga_region_class, start, data, match);
++	if (!dev)
++		return NULL;
++
++	return to_fpga_region(dev);
++}
++EXPORT_SYMBOL_GPL(fpga_region_class_find);
++
+ static const struct of_device_id fpga_region_of_match[] = {
+ 	{ .compatible = "fpga-region", },
+ 	{},
+@@ -51,14 +65,7 @@ static int fpga_region_of_node_match(struct device *dev, const void *data)
+  */
+ static struct fpga_region *of_fpga_region_find(struct device_node *np)
+ {
+-	struct device *dev;
+-
+-	dev = class_find_device(fpga_region_class, NULL, np,
+-				fpga_region_of_node_match);
+-	if (!dev)
+-		return NULL;
+-
+-	return to_fpga_region(dev);
++	return fpga_region_class_find(NULL, np, fpga_region_of_node_match);
+ }
+ 
+ /**
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index 8c8a3249f96c..704844944631 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -27,8 +27,11 @@ struct fpga_region {
+ 
+ #define to_fpga_region(d) container_of(d, struct fpga_region, dev)
+ 
+-int fpga_region_program_fpga(struct fpga_region *region);
++struct fpga_region *fpga_region_class_find(
++	struct device *start, const void *data,
++	int (*match)(struct device *, const void *));
+ 
++int fpga_region_program_fpga(struct fpga_region *region);
+ int fpga_region_register(struct device *dev, struct fpga_region *region);
+ int fpga_region_unregister(struct fpga_region *region);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1674-fpga-region-move-device-tree-support-to-of-fpga-regi.patch b/patches/1674-fpga-region-move-device-tree-support-to-of-fpga-regi.patch
new file mode 100644
index 00000000000000..f6b6684475ab06
--- /dev/null
+++ b/patches/1674-fpga-region-move-device-tree-support-to-of-fpga-regi.patch
@@ -0,0 +1,1109 @@
+From 6547f28680d87e8e3d53b4192ef5443cec149352 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:25 -0600
+Subject: [PATCH 1674/1795] fpga: region: move device tree support to
+ of-fpga-region.c
+
+Create of-fpga-region.c and move the following functions without
+modification from fpga-region.c.
+
+* of_fpga_region_find
+* of_fpga_region_get_mgr
+* of_fpga_region_get_bridges
+* child_regions_with_firmware
+* of_fpga_region_parse_ov
+* of_fpga_region_notify_pre_apply
+* of_fpga_region_notify_post_remove
+* of_fpga_region_notify
+* of_fpga_region_probe
+* of_fpga_region_remove
+
+Create two new functions with some code from fpga_region_init/exit.
+
+* of_fpga_region_init
+* of_fpga_region_exit
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ef3acdd820752e0abb5f1ec899025967d0dccf3d)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig          |  15 +-
+ drivers/fpga/Makefile         |   1 +
+ drivers/fpga/fpga-region.c    | 459 +------------------------------
+ drivers/fpga/of-fpga-region.c | 496 ++++++++++++++++++++++++++++++++++
+ 4 files changed, 509 insertions(+), 462 deletions(-)
+ create mode 100644 drivers/fpga/of-fpga-region.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index ad5448f718b3..12bd1c760c32 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -13,10 +13,18 @@ if FPGA
+ 
+ config FPGA_REGION
+ 	tristate "FPGA Region"
+-	depends on OF && FPGA_BRIDGE
++	depends on FPGA_BRIDGE
++	help
++	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
++	  and the FPGA Bridges associated with either a reconfigurable
++	  region of an FPGA or a whole FPGA.
++
++config OF_FPGA_REGION
++	tristate "FPGA Region Device Tree Overlay Support"
++	depends on OF && FPGA_REGION
+ 	help
+-	  FPGA Regions allow loading FPGA images under control of
+-	  the Device Tree.
++	  Support for loading FPGA images by applying a Device Tree
++	  overlay.
+ 
+ config FPGA_MGR_ICE40_SPI
+ 	tristate "Lattice iCE40 SPI"
+@@ -74,7 +82,6 @@ config FPGA_MGR_ZYNQ_FPGA
+ 
+ config FPGA_BRIDGE
+ 	tristate "FPGA Bridge Framework"
+-	depends on OF
+ 	help
+ 	  Say Y here if you want to support bridges connected between host
+ 	  processors and FPGAs or between FPGAs.
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index f98dcf1d89e1..3cb276a0f88d 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -26,3 +26,4 @@ obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
+ 
+ # High Level Interfaces
+ obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
++obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 4e5580aacaee..afc61885a601 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -2,6 +2,7 @@
+  * FPGA Region - Device Tree support for FPGA programming under Linux
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation
++ *  Copyright (C) 2017 Intel Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms and conditions of the GNU General Public License,
+@@ -23,7 +24,6 @@
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+ #include <linux/module.h>
+-#include <linux/of_platform.h>
+ #include <linux/slab.h>
+ #include <linux/spinlock.h>
+ 
+@@ -44,30 +44,6 @@ struct fpga_region *fpga_region_class_find(
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_class_find);
+ 
+-static const struct of_device_id fpga_region_of_match[] = {
+-	{ .compatible = "fpga-region", },
+-	{},
+-};
+-MODULE_DEVICE_TABLE(of, fpga_region_of_match);
+-
+-static int fpga_region_of_node_match(struct device *dev, const void *data)
+-{
+-	return dev->of_node == data;
+-}
+-
+-/**
+- * of_fpga_region_find - find FPGA region
+- * @np: device node of FPGA Region
+- *
+- * Caller will need to put_device(&region->dev) when done.
+- *
+- * Returns FPGA Region struct or NULL
+- */
+-static struct fpga_region *of_fpga_region_find(struct device_node *np)
+-{
+-	return fpga_region_class_find(NULL, np, fpga_region_of_node_match);
+-}
+-
+ /**
+  * fpga_region_get - get an exclusive reference to a fpga region
+  * @region: FPGA Region struct
+@@ -115,109 +91,6 @@ static void fpga_region_put(struct fpga_region *region)
+ 	mutex_unlock(&region->mutex);
+ }
+ 
+-/**
+- * of_fpga_region_get_mgr - get reference for FPGA manager
+- * @np: device node of FPGA region
+- *
+- * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
+- *
+- * Caller should call fpga_mgr_put() when done with manager.
+- *
+- * Return: fpga manager struct or IS_ERR() condition containing error code.
+- */
+-static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
+-{
+-	struct device_node  *mgr_node;
+-	struct fpga_manager *mgr;
+-
+-	of_node_get(np);
+-	while (np) {
+-		if (of_device_is_compatible(np, "fpga-region")) {
+-			mgr_node = of_parse_phandle(np, "fpga-mgr", 0);
+-			if (mgr_node) {
+-				mgr = of_fpga_mgr_get(mgr_node);
+-				of_node_put(mgr_node);
+-				of_node_put(np);
+-				return mgr;
+-			}
+-		}
+-		np = of_get_next_parent(np);
+-	}
+-	of_node_put(np);
+-
+-	return ERR_PTR(-EINVAL);
+-}
+-
+-/**
+- * of_fpga_region_get_bridges - create a list of bridges
+- * @region: FPGA region
+- *
+- * Create a list of bridges including the parent bridge and the bridges
+- * specified by "fpga-bridges" property.  Note that the
+- * fpga_bridges_enable/disable/put functions are all fine with an empty list
+- * if that happens.
+- *
+- * Caller should call fpga_bridges_put(&region->bridge_list) when
+- * done with the bridges.
+- *
+- * Return 0 for success (even if there are no bridges specified)
+- * or -EBUSY if any of the bridges are in use.
+- */
+-static int of_fpga_region_get_bridges(struct fpga_region *region)
+-{
+-	struct device *dev = &region->dev;
+-	struct device_node *region_np = dev->of_node;
+-	struct fpga_image_info *info = region->info;
+-	struct device_node *br, *np, *parent_br = NULL;
+-	int i, ret;
+-
+-	/* If parent is a bridge, add to list */
+-	ret = of_fpga_bridge_get_to_list(region_np->parent, info,
+-					 &region->bridge_list);
+-
+-	/* -EBUSY means parent is a bridge that is under use. Give up. */
+-	if (ret == -EBUSY)
+-		return ret;
+-
+-	/* Zero return code means parent was a bridge and was added to list. */
+-	if (!ret)
+-		parent_br = region_np->parent;
+-
+-	/* If overlay has a list of bridges, use it. */
+-	br = of_parse_phandle(info->overlay, "fpga-bridges", 0);
+-	if (br) {
+-		of_node_put(br);
+-		np = info->overlay;
+-	} else {
+-		np = region_np;
+-	}
+-
+-	for (i = 0; ; i++) {
+-		br = of_parse_phandle(np, "fpga-bridges", i);
+-		if (!br)
+-			break;
+-
+-		/* If parent bridge is in list, skip it. */
+-		if (br == parent_br) {
+-			of_node_put(br);
+-			continue;
+-		}
+-
+-		/* If node is a bridge, get it and add to list */
+-		ret = of_fpga_bridge_get_to_list(br, info,
+-						 &region->bridge_list);
+-		of_node_put(br);
+-
+-		/* If any of the bridges are in use, give up */
+-		if (ret == -EBUSY) {
+-			fpga_bridges_put(&region->bridge_list);
+-			return -EBUSY;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+ /**
+  * fpga_region_program_fpga - program FPGA
+  * @region: FPGA region
+@@ -289,259 +162,6 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_program_fpga);
+ 
+-/**
+- * child_regions_with_firmware
+- * @overlay: device node of the overlay
+- *
+- * If the overlay adds child FPGA regions, they are not allowed to have
+- * firmware-name property.
+- *
+- * Return 0 for OK or -EINVAL if child FPGA region adds firmware-name.
+- */
+-static int child_regions_with_firmware(struct device_node *overlay)
+-{
+-	struct device_node *child_region;
+-	const char *child_firmware_name;
+-	int ret = 0;
+-
+-	of_node_get(overlay);
+-
+-	child_region = of_find_matching_node(overlay, fpga_region_of_match);
+-	while (child_region) {
+-		if (!of_property_read_string(child_region, "firmware-name",
+-					     &child_firmware_name)) {
+-			ret = -EINVAL;
+-			break;
+-		}
+-		child_region = of_find_matching_node(child_region,
+-						     fpga_region_of_match);
+-	}
+-
+-	of_node_put(child_region);
+-
+-	if (ret)
+-		pr_err("firmware-name not allowed in child FPGA region: %pOF",
+-		       child_region);
+-
+-	return ret;
+-}
+-
+-/**
+- * of_fpga_region_parse_ov - parse and check overlay applied to region
+- *
+- * @region: FPGA region
+- * @overlay: overlay applied to the FPGA region
+- *
+- * Given an overlay applied to a FPGA region, parse the FPGA image specific
+- * info in the overlay and do some checking.
+- *
+- * Returns:
+- *   NULL if overlay doesn't direct us to program the FPGA.
+- *   fpga_image_info struct if there is an image to program.
+- *   error code for invalid overlay.
+- */
+-static struct fpga_image_info *of_fpga_region_parse_ov(
+-						struct fpga_region *region,
+-						struct device_node *overlay)
+-{
+-	struct device *dev = &region->dev;
+-	struct fpga_image_info *info;
+-	const char *firmware_name;
+-	int ret;
+-
+-	if (region->info) {
+-		dev_err(dev, "Region already has overlay applied.\n");
+-		return ERR_PTR(-EINVAL);
+-	}
+-
+-	/*
+-	 * Reject overlay if child FPGA Regions added in the overlay have
+-	 * firmware-name property (would mean that an FPGA region that has
+-	 * not been added to the live tree yet is doing FPGA programming).
+-	 */
+-	ret = child_regions_with_firmware(overlay);
+-	if (ret)
+-		return ERR_PTR(ret);
+-
+-	info = fpga_image_info_alloc(dev);
+-	if (!info)
+-		return ERR_PTR(-ENOMEM);
+-
+-	info->overlay = overlay;
+-
+-	/* Read FPGA region properties from the overlay */
+-	if (of_property_read_bool(overlay, "partial-fpga-config"))
+-		info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
+-
+-	if (of_property_read_bool(overlay, "external-fpga-config"))
+-		info->flags |= FPGA_MGR_EXTERNAL_CONFIG;
+-
+-	if (of_property_read_bool(overlay, "encrypted-fpga-config"))
+-		info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
+-
+-	if (!of_property_read_string(overlay, "firmware-name",
+-				     &firmware_name)) {
+-		info->firmware_name = devm_kstrdup(dev, firmware_name,
+-						   GFP_KERNEL);
+-		if (!info->firmware_name)
+-			return ERR_PTR(-ENOMEM);
+-	}
+-
+-	of_property_read_u32(overlay, "region-unfreeze-timeout-us",
+-			     &info->enable_timeout_us);
+-
+-	of_property_read_u32(overlay, "region-freeze-timeout-us",
+-			     &info->disable_timeout_us);
+-
+-	of_property_read_u32(overlay, "config-complete-timeout-us",
+-			     &info->config_complete_timeout_us);
+-
+-	/* If overlay is not programming the FPGA, don't need FPGA image info */
+-	if (!info->firmware_name) {
+-		ret = 0;
+-		goto ret_no_info;
+-	}
+-
+-	/*
+-	 * If overlay informs us FPGA was externally programmed, specifying
+-	 * firmware here would be ambiguous.
+-	 */
+-	if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) {
+-		dev_err(dev, "error: specified firmware and external-fpga-config");
+-		ret = -EINVAL;
+-		goto ret_no_info;
+-	}
+-
+-	return info;
+-ret_no_info:
+-	fpga_image_info_free(info);
+-	return ERR_PTR(ret);
+-}
+-
+-/**
+- * of_fpga_region_notify_pre_apply - pre-apply overlay notification
+- *
+- * @region: FPGA region that the overlay was applied to
+- * @nd: overlay notification data
+- *
+- * Called when an overlay targeted to a FPGA Region is about to be applied.
+- * Parses the overlay for properties that influence how the FPGA will be
+- * programmed and does some checking. If the checks pass, programs the FPGA.
+- * If the checks fail, overlay is rejected and does not get added to the
+- * live tree.
+- *
+- * Returns 0 for success or negative error code for failure.
+- */
+-static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
+-					   struct of_overlay_notify_data *nd)
+-{
+-	struct device *dev = &region->dev;
+-	struct fpga_image_info *info;
+-	int ret;
+-
+-	if (region->info) {
+-		dev_err(dev, "Region already has overlay applied.\n");
+-		return -EINVAL;
+-	}
+-
+-	info = of_fpga_region_parse_ov(region, nd->overlay);
+-	if (IS_ERR(info))
+-		return PTR_ERR(info);
+-
+-	if (!info)
+-		return 0;
+-
+-	region->info = info;
+-	ret = fpga_region_program_fpga(region);
+-	if (ret) {
+-		/* error; reject overlay */
+-		fpga_image_info_free(info);
+-		region->info = NULL;
+-	}
+-
+-	return ret;
+-}
+-
+-/**
+- * of_fpga_region_notify_post_remove - post-remove overlay notification
+- *
+- * @region: FPGA region that was targeted by the overlay that was removed
+- * @nd: overlay notification data
+- *
+- * Called after an overlay has been removed if the overlay's target was a
+- * FPGA region.
+- */
+-static void of_fpga_region_notify_post_remove(struct fpga_region *region,
+-					      struct of_overlay_notify_data *nd)
+-{
+-	fpga_bridges_disable(&region->bridge_list);
+-	fpga_bridges_put(&region->bridge_list);
+-	fpga_image_info_free(region->info);
+-	region->info = NULL;
+-}
+-
+-/**
+- * of_fpga_region_notify - reconfig notifier for dynamic DT changes
+- * @nb:		notifier block
+- * @action:	notifier action
+- * @arg:	reconfig data
+- *
+- * This notifier handles programming a FPGA when a "firmware-name" property is
+- * added to a fpga-region.
+- *
+- * Returns NOTIFY_OK or error if FPGA programming fails.
+- */
+-static int of_fpga_region_notify(struct notifier_block *nb,
+-				 unsigned long action, void *arg)
+-{
+-	struct of_overlay_notify_data *nd = arg;
+-	struct fpga_region *region;
+-	int ret;
+-
+-	switch (action) {
+-	case OF_OVERLAY_PRE_APPLY:
+-		pr_debug("%s OF_OVERLAY_PRE_APPLY\n", __func__);
+-		break;
+-	case OF_OVERLAY_POST_APPLY:
+-		pr_debug("%s OF_OVERLAY_POST_APPLY\n", __func__);
+-		return NOTIFY_OK;       /* not for us */
+-	case OF_OVERLAY_PRE_REMOVE:
+-		pr_debug("%s OF_OVERLAY_PRE_REMOVE\n", __func__);
+-		return NOTIFY_OK;       /* not for us */
+-	case OF_OVERLAY_POST_REMOVE:
+-		pr_debug("%s OF_OVERLAY_POST_REMOVE\n", __func__);
+-		break;
+-	default:			/* should not happen */
+-		return NOTIFY_OK;
+-	}
+-
+-	region = of_fpga_region_find(nd->target);
+-	if (!region)
+-		return NOTIFY_OK;
+-
+-	ret = 0;
+-	switch (action) {
+-	case OF_OVERLAY_PRE_APPLY:
+-		ret = of_fpga_region_notify_pre_apply(region, nd);
+-		break;
+-
+-	case OF_OVERLAY_POST_REMOVE:
+-		of_fpga_region_notify_post_remove(region, nd);
+-		break;
+-	}
+-
+-	put_device(&region->dev);
+-
+-	if (ret)
+-		return notifier_from_errno(ret);
+-
+-	return NOTIFY_OK;
+-}
+-
+-static struct notifier_block fpga_region_of_nb = {
+-	.notifier_call = of_fpga_region_notify,
+-};
+-
+ int fpga_region_register(struct device *dev, struct fpga_region *region)
+ {
+ 	int id, ret = 0;
+@@ -583,64 +203,6 @@ int fpga_region_unregister(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_unregister);
+ 
+-static int of_fpga_region_probe(struct platform_device *pdev)
+-{
+-	struct device *dev = &pdev->dev;
+-	struct device_node *np = dev->of_node;
+-	struct fpga_region *region;
+-	struct fpga_manager *mgr;
+-	int ret;
+-
+-	/* Find the FPGA mgr specified by region or parent region. */
+-	mgr = of_fpga_region_get_mgr(np);
+-	if (IS_ERR(mgr))
+-		return -EPROBE_DEFER;
+-
+-	region = devm_kzalloc(dev, sizeof(*region), GFP_KERNEL);
+-	if (!region) {
+-		ret = -ENOMEM;
+-		goto eprobe_mgr_put;
+-	}
+-
+-	region->mgr = mgr;
+-
+-	/* Specify how to get bridges for this type of region. */
+-	region->get_bridges = of_fpga_region_get_bridges;
+-
+-	ret = fpga_region_register(dev, region);
+-	if (ret)
+-		goto eprobe_mgr_put;
+-
+-	of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
+-
+-	dev_info(dev, "FPGA Region probed\n");
+-
+-	return 0;
+-
+-eprobe_mgr_put:
+-	fpga_mgr_put(mgr);
+-	return ret;
+-}
+-
+-static int of_fpga_region_remove(struct platform_device *pdev)
+-{
+-	struct fpga_region *region = platform_get_drvdata(pdev);
+-
+-	fpga_region_unregister(region);
+-	fpga_mgr_put(region->mgr);
+-
+-	return 0;
+-}
+-
+-static struct platform_driver of_fpga_region_driver = {
+-	.probe = of_fpga_region_probe,
+-	.remove = of_fpga_region_remove,
+-	.driver = {
+-		.name	= "fpga-region",
+-		.of_match_table = of_match_ptr(fpga_region_of_match),
+-	},
+-};
+-
+ static void fpga_region_dev_release(struct device *dev)
+ {
+ 	struct fpga_region *region = to_fpga_region(dev);
+@@ -654,36 +216,17 @@ static void fpga_region_dev_release(struct device *dev)
+  */
+ static int __init fpga_region_init(void)
+ {
+-	int ret;
+-
+ 	fpga_region_class = class_create(THIS_MODULE, "fpga_region");
+ 	if (IS_ERR(fpga_region_class))
+ 		return PTR_ERR(fpga_region_class);
+ 
+ 	fpga_region_class->dev_release = fpga_region_dev_release;
+ 
+-	ret = of_overlay_notifier_register(&fpga_region_of_nb);
+-	if (ret)
+-		goto err_class;
+-
+-	ret = platform_driver_register(&of_fpga_region_driver);
+-	if (ret)
+-		goto err_plat;
+-
+ 	return 0;
+-
+-err_plat:
+-	of_overlay_notifier_unregister(&fpga_region_of_nb);
+-err_class:
+-	class_destroy(fpga_region_class);
+-	ida_destroy(&fpga_region_ida);
+-	return ret;
+ }
+ 
+ static void __exit fpga_region_exit(void)
+ {
+-	platform_driver_unregister(&of_fpga_region_driver);
+-	of_overlay_notifier_unregister(&fpga_region_of_nb);
+ 	class_destroy(fpga_region_class);
+ 	ida_destroy(&fpga_region_ida);
+ }
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+new file mode 100644
+index 000000000000..1533506ef0e4
+--- /dev/null
++++ b/drivers/fpga/of-fpga-region.c
+@@ -0,0 +1,496 @@
++/*
++ * FPGA Region - Device Tree support for FPGA programming under Linux
++ *
++ *  Copyright (C) 2013-2016 Altera Corporation
++ *  Copyright (C) 2017 Intel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fpga/fpga-bridge.h>
++#include <linux/fpga/fpga-mgr.h>
++#include <linux/fpga/fpga-region.h>
++#include <linux/idr.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++static const struct of_device_id fpga_region_of_match[] = {
++	{ .compatible = "fpga-region", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, fpga_region_of_match);
++
++static int fpga_region_of_node_match(struct device *dev, const void *data)
++{
++	return dev->of_node == data;
++}
++
++/**
++ * of_fpga_region_find - find FPGA region
++ * @np: device node of FPGA Region
++ *
++ * Caller will need to put_device(&region->dev) when done.
++ *
++ * Returns FPGA Region struct or NULL
++ */
++static struct fpga_region *of_fpga_region_find(struct device_node *np)
++{
++	return fpga_region_class_find(NULL, np, fpga_region_of_node_match);
++}
++
++/**
++ * of_fpga_region_get_mgr - get reference for FPGA manager
++ * @np: device node of FPGA region
++ *
++ * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
++ *
++ * Caller should call fpga_mgr_put() when done with manager.
++ *
++ * Return: fpga manager struct or IS_ERR() condition containing error code.
++ */
++static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
++{
++	struct device_node  *mgr_node;
++	struct fpga_manager *mgr;
++
++	of_node_get(np);
++	while (np) {
++		if (of_device_is_compatible(np, "fpga-region")) {
++			mgr_node = of_parse_phandle(np, "fpga-mgr", 0);
++			if (mgr_node) {
++				mgr = of_fpga_mgr_get(mgr_node);
++				of_node_put(np);
++				return mgr;
++			}
++		}
++		np = of_get_next_parent(np);
++	}
++	of_node_put(np);
++
++	return ERR_PTR(-EINVAL);
++}
++
++/**
++ * of_fpga_region_get_bridges - create a list of bridges
++ * @region: FPGA region
++ *
++ * Create a list of bridges including the parent bridge and the bridges
++ * specified by "fpga-bridges" property.  Note that the
++ * fpga_bridges_enable/disable/put functions are all fine with an empty list
++ * if that happens.
++ *
++ * Caller should call fpga_bridges_put(&region->bridge_list) when
++ * done with the bridges.
++ *
++ * Return 0 for success (even if there are no bridges specified)
++ * or -EBUSY if any of the bridges are in use.
++ */
++static int of_fpga_region_get_bridges(struct fpga_region *region)
++{
++	struct device *dev = &region->dev;
++	struct device_node *region_np = dev->of_node;
++	struct fpga_image_info *info = region->info;
++	struct device_node *br, *np, *parent_br = NULL;
++	int i, ret;
++
++	/* If parent is a bridge, add to list */
++	ret = of_fpga_bridge_get_to_list(region_np->parent, info,
++					 &region->bridge_list);
++
++	/* -EBUSY means parent is a bridge that is under use. Give up. */
++	if (ret == -EBUSY)
++		return ret;
++
++	/* Zero return code means parent was a bridge and was added to list. */
++	if (!ret)
++		parent_br = region_np->parent;
++
++	/* If overlay has a list of bridges, use it. */
++	if (of_parse_phandle(info->overlay, "fpga-bridges", 0))
++		np = info->overlay;
++	else
++		np = region_np;
++
++	for (i = 0; ; i++) {
++		br = of_parse_phandle(np, "fpga-bridges", i);
++		if (!br)
++			break;
++
++		/* If parent bridge is in list, skip it. */
++		if (br == parent_br)
++			continue;
++
++		/* If node is a bridge, get it and add to list */
++		ret = of_fpga_bridge_get_to_list(br, info,
++						 &region->bridge_list);
++
++		/* If any of the bridges are in use, give up */
++		if (ret == -EBUSY) {
++			fpga_bridges_put(&region->bridge_list);
++			return -EBUSY;
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * child_regions_with_firmware
++ * @overlay: device node of the overlay
++ *
++ * If the overlay adds child FPGA regions, they are not allowed to have
++ * firmware-name property.
++ *
++ * Return 0 for OK or -EINVAL if child FPGA region adds firmware-name.
++ */
++static int child_regions_with_firmware(struct device_node *overlay)
++{
++	struct device_node *child_region;
++	const char *child_firmware_name;
++	int ret = 0;
++
++	of_node_get(overlay);
++
++	child_region = of_find_matching_node(overlay, fpga_region_of_match);
++	while (child_region) {
++		if (!of_property_read_string(child_region, "firmware-name",
++					     &child_firmware_name)) {
++			ret = -EINVAL;
++			break;
++		}
++		child_region = of_find_matching_node(child_region,
++						     fpga_region_of_match);
++	}
++
++	of_node_put(child_region);
++
++	if (ret)
++		pr_err("firmware-name not allowed in child FPGA region: %pOF",
++		       child_region);
++
++	return ret;
++}
++
++/**
++ * of_fpga_region_parse_ov - parse and check overlay applied to region
++ *
++ * @region: FPGA region
++ * @overlay: overlay applied to the FPGA region
++ *
++ * Given an overlay applied to a FPGA region, parse the FPGA image specific
++ * info in the overlay and do some checking.
++ *
++ * Returns:
++ *   NULL if overlay doesn't direct us to program the FPGA.
++ *   fpga_image_info struct if there is an image to program.
++ *   error code for invalid overlay.
++ */
++static struct fpga_image_info *of_fpga_region_parse_ov(
++						struct fpga_region *region,
++						struct device_node *overlay)
++{
++	struct device *dev = &region->dev;
++	struct fpga_image_info *info;
++	const char *firmware_name;
++	int ret;
++
++	if (region->info) {
++		dev_err(dev, "Region already has overlay applied.\n");
++		return ERR_PTR(-EINVAL);
++	}
++
++	/*
++	 * Reject overlay if child FPGA Regions added in the overlay have
++	 * firmware-name property (would mean that an FPGA region that has
++	 * not been added to the live tree yet is doing FPGA programming).
++	 */
++	ret = child_regions_with_firmware(overlay);
++	if (ret)
++		return ERR_PTR(ret);
++
++	info = fpga_image_info_alloc(dev);
++	if (!info)
++		return ERR_PTR(-ENOMEM);
++
++	info->overlay = overlay;
++
++	/* Read FPGA region properties from the overlay */
++	if (of_property_read_bool(overlay, "partial-fpga-config"))
++		info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
++
++	if (of_property_read_bool(overlay, "external-fpga-config"))
++		info->flags |= FPGA_MGR_EXTERNAL_CONFIG;
++
++	if (of_property_read_bool(overlay, "encrypted-fpga-config"))
++		info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
++
++	if (!of_property_read_string(overlay, "firmware-name",
++				     &firmware_name)) {
++		info->firmware_name = devm_kstrdup(dev, firmware_name,
++						   GFP_KERNEL);
++		if (!info->firmware_name)
++			return ERR_PTR(-ENOMEM);
++	}
++
++	of_property_read_u32(overlay, "region-unfreeze-timeout-us",
++			     &info->enable_timeout_us);
++
++	of_property_read_u32(overlay, "region-freeze-timeout-us",
++			     &info->disable_timeout_us);
++
++	of_property_read_u32(overlay, "config-complete-timeout-us",
++			     &info->config_complete_timeout_us);
++
++	/* If overlay is not programming the FPGA, don't need FPGA image info */
++	if (!info->firmware_name) {
++		ret = 0;
++		goto ret_no_info;
++	}
++
++	/*
++	 * If overlay informs us FPGA was externally programmed, specifying
++	 * firmware here would be ambiguous.
++	 */
++	if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) {
++		dev_err(dev, "error: specified firmware and external-fpga-config");
++		ret = -EINVAL;
++		goto ret_no_info;
++	}
++
++	return info;
++ret_no_info:
++	fpga_image_info_free(info);
++	return ERR_PTR(ret);
++}
++
++/**
++ * of_fpga_region_notify_pre_apply - pre-apply overlay notification
++ *
++ * @region: FPGA region that the overlay was applied to
++ * @nd: overlay notification data
++ *
++ * Called when an overlay targeted to a FPGA Region is about to be applied.
++ * Parses the overlay for properties that influence how the FPGA will be
++ * programmed and does some checking. If the checks pass, programs the FPGA.
++ * If the checks fail, overlay is rejected and does not get added to the
++ * live tree.
++ *
++ * Returns 0 for success or negative error code for failure.
++ */
++static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
++					   struct of_overlay_notify_data *nd)
++{
++	struct device *dev = &region->dev;
++	struct fpga_image_info *info;
++	int ret;
++
++	if (region->info) {
++		dev_err(dev, "Region already has overlay applied.\n");
++		return -EINVAL;
++	}
++
++	info = of_fpga_region_parse_ov(region, nd->overlay);
++	if (IS_ERR(info))
++		return PTR_ERR(info);
++
++	if (!info)
++		return 0;
++
++	region->info = info;
++	ret = fpga_region_program_fpga(region);
++	if (ret) {
++		/* error; reject overlay */
++		fpga_image_info_free(info);
++		region->info = NULL;
++	}
++
++	return ret;
++}
++
++/**
++ * of_fpga_region_notify_post_remove - post-remove overlay notification
++ *
++ * @region: FPGA region that was targeted by the overlay that was removed
++ * @nd: overlay notification data
++ *
++ * Called after an overlay has been removed if the overlay's target was a
++ * FPGA region.
++ */
++static void of_fpga_region_notify_post_remove(struct fpga_region *region,
++					      struct of_overlay_notify_data *nd)
++{
++	fpga_bridges_disable(&region->bridge_list);
++	fpga_bridges_put(&region->bridge_list);
++	fpga_image_info_free(region->info);
++	region->info = NULL;
++}
++
++/**
++ * of_fpga_region_notify - reconfig notifier for dynamic DT changes
++ * @nb:		notifier block
++ * @action:	notifier action
++ * @arg:	reconfig data
++ *
++ * This notifier handles programming a FPGA when a "firmware-name" property is
++ * added to a fpga-region.
++ *
++ * Returns NOTIFY_OK or error if FPGA programming fails.
++ */
++static int of_fpga_region_notify(struct notifier_block *nb,
++				 unsigned long action, void *arg)
++{
++	struct of_overlay_notify_data *nd = arg;
++	struct fpga_region *region;
++	int ret;
++
++	switch (action) {
++	case OF_OVERLAY_PRE_APPLY:
++		pr_debug("%s OF_OVERLAY_PRE_APPLY\n", __func__);
++		break;
++	case OF_OVERLAY_POST_APPLY:
++		pr_debug("%s OF_OVERLAY_POST_APPLY\n", __func__);
++		return NOTIFY_OK;       /* not for us */
++	case OF_OVERLAY_PRE_REMOVE:
++		pr_debug("%s OF_OVERLAY_PRE_REMOVE\n", __func__);
++		return NOTIFY_OK;       /* not for us */
++	case OF_OVERLAY_POST_REMOVE:
++		pr_debug("%s OF_OVERLAY_POST_REMOVE\n", __func__);
++		break;
++	default:			/* should not happen */
++		return NOTIFY_OK;
++	}
++
++	region = of_fpga_region_find(nd->target);
++	if (!region)
++		return NOTIFY_OK;
++
++	ret = 0;
++	switch (action) {
++	case OF_OVERLAY_PRE_APPLY:
++		ret = of_fpga_region_notify_pre_apply(region, nd);
++		break;
++
++	case OF_OVERLAY_POST_REMOVE:
++		of_fpga_region_notify_post_remove(region, nd);
++		break;
++	}
++
++	put_device(&region->dev);
++
++	if (ret)
++		return notifier_from_errno(ret);
++
++	return NOTIFY_OK;
++}
++
++static struct notifier_block fpga_region_of_nb = {
++	.notifier_call = of_fpga_region_notify,
++};
++
++static int of_fpga_region_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct fpga_region *region;
++	struct fpga_manager *mgr;
++	int ret;
++
++	/* Find the FPGA mgr specified by region or parent region. */
++	mgr = of_fpga_region_get_mgr(np);
++	if (IS_ERR(mgr))
++		return -EPROBE_DEFER;
++
++	region = devm_kzalloc(dev, sizeof(*region), GFP_KERNEL);
++	if (!region) {
++		ret = -ENOMEM;
++		goto eprobe_mgr_put;
++	}
++
++	region->mgr = mgr;
++
++	/* Specify how to get bridges for this type of region. */
++	region->get_bridges = of_fpga_region_get_bridges;
++
++	ret = fpga_region_register(dev, region);
++	if (ret)
++		goto eprobe_mgr_put;
++
++	of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
++
++	dev_info(dev, "FPGA Region probed\n");
++
++	return 0;
++
++eprobe_mgr_put:
++	fpga_mgr_put(mgr);
++	return ret;
++}
++
++static int of_fpga_region_remove(struct platform_device *pdev)
++{
++	struct fpga_region *region = platform_get_drvdata(pdev);
++
++	fpga_region_unregister(region);
++	fpga_mgr_put(region->mgr);
++
++	return 0;
++}
++
++static struct platform_driver of_fpga_region_driver = {
++	.probe = of_fpga_region_probe,
++	.remove = of_fpga_region_remove,
++	.driver = {
++		.name	= "of-fpga-region",
++		.of_match_table = of_match_ptr(fpga_region_of_match),
++	},
++};
++
++/**
++ * fpga_region_init - init function for fpga_region class
++ * Creates the fpga_region class and registers a reconfig notifier.
++ */
++static int __init of_fpga_region_init(void)
++{
++	int ret;
++
++	ret = of_overlay_notifier_register(&fpga_region_of_nb);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&of_fpga_region_driver);
++	if (ret)
++		goto err_plat;
++
++	return 0;
++
++err_plat:
++	of_overlay_notifier_unregister(&fpga_region_of_nb);
++	return ret;
++}
++
++static void __exit of_fpga_region_exit(void)
++{
++	platform_driver_unregister(&of_fpga_region_driver);
++	of_overlay_notifier_unregister(&fpga_region_of_nb);
++}
++
++subsys_initcall(of_fpga_region_init);
++module_exit(of_fpga_region_exit);
++
++MODULE_DESCRIPTION("FPGA Region");
++MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.19.0
+
diff --git a/patches/1675-fpga-of-fpga-region-accept-overlays-that-don-t-progr.patch b/patches/1675-fpga-of-fpga-region-accept-overlays-that-don-t-progr.patch
new file mode 100644
index 00000000000000..ad878f0a8cb4ae
--- /dev/null
+++ b/patches/1675-fpga-of-fpga-region-accept-overlays-that-don-t-progr.patch
@@ -0,0 +1,52 @@
+From d6b4e837b8893976774e98ccba7a1887c7cd03f9 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:26 -0600
+Subject: [PATCH 1675/1795] fpga: of-fpga-region: accept overlays that don't
+ program FPGA
+
+The FPGA may already have a static image programmed when
+Linux boots.  In that case a DT overlay may be used to add
+the devices that already exist.  This commit allows that
+by shuffling the order of some checks.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 8a54167925341ab2a9c3133618dbddfc1a46f8aa)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/of-fpga-region.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+index 1533506ef0e4..c6b21194dcbc 100644
+--- a/drivers/fpga/of-fpga-region.c
++++ b/drivers/fpga/of-fpga-region.c
+@@ -298,18 +298,19 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
+ 	struct fpga_image_info *info;
+ 	int ret;
+ 
+-	if (region->info) {
+-		dev_err(dev, "Region already has overlay applied.\n");
+-		return -EINVAL;
+-	}
+-
+ 	info = of_fpga_region_parse_ov(region, nd->overlay);
+ 	if (IS_ERR(info))
+ 		return PTR_ERR(info);
+ 
++	/* If overlay doesn't program the FPGA, accept it anyway. */
+ 	if (!info)
+ 		return 0;
+ 
++	if (region->info) {
++		dev_err(dev, "Region already has overlay applied.\n");
++		return -EINVAL;
++	}
++
+ 	region->info = info;
+ 	ret = fpga_region_program_fpga(region);
+ 	if (ret) {
+-- 
+2.19.0
+
diff --git a/patches/1676-fpga-clean-up-fpga-Kconfig.patch b/patches/1676-fpga-clean-up-fpga-Kconfig.patch
new file mode 100644
index 00000000000000..95eb4f3852fb3a
--- /dev/null
+++ b/patches/1676-fpga-clean-up-fpga-Kconfig.patch
@@ -0,0 +1,202 @@
+From 2342d4915230c3ec67deb7194cf08770185d0148 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:27 -0600
+Subject: [PATCH 1676/1795] fpga: clean up fpga Kconfig
+
+The fpga menuconfig has gotten messy.  The bridges and managers are
+mixed together.
+
+* Separate the bridges and things dependent on CONFIG_FPGA_BRIDGE
+  from the managers.
+* Group the managers by vendor in order that they were added
+  to the kernel.
+
+The following is what the menuconfig ends up looking like more or less
+(platform dependencies are hiding some of these on any given
+platform).
+
+    --- FPGA Configuration Framework
+    <*>   Altera SOCFPGA FPGA Manager
+    <*>   Altera SoCFPGA Arria10
+    <*>   Altera Partial Reconfiguration IP Core
+    <*>     Platform support of Altera Partial Reconfiguration IP Core
+    <*>   Altera FPGA Passive Serial over SPI
+    <*>   Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager
+    <*>   Xilinx Zynq FPGA
+    <*>   Xilinx Configuration over Slave Serial (SPI)
+    <*>   Lattice iCE40 SPI
+    <*>   Technologic Systems TS-73xx SBC FPGA Manager
+    <*>   FPGA Bridge Framework
+    <*>     Altera SoCFPGA FPGA Bridges
+    <*>     Altera FPGA Freeze Bridge
+    <*>     Xilinx LogiCORE PR Decoupler
+    <*>     FPGA Region
+    <*>       FPGA Region Device Tree Overlay Support
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 84e93f1d4f45a510926cb9225e49a4ccff5dd868)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig | 108 +++++++++++++++++++++----------------------
+ 1 file changed, 54 insertions(+), 54 deletions(-)
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index 12bd1c760c32..f47ef848bcd0 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -11,33 +11,30 @@ menuconfig FPGA
+ 
+ if FPGA
+ 
+-config FPGA_REGION
+-	tristate "FPGA Region"
+-	depends on FPGA_BRIDGE
++config FPGA_MGR_SOCFPGA
++	tristate "Altera SOCFPGA FPGA Manager"
++	depends on ARCH_SOCFPGA || COMPILE_TEST
+ 	help
+-	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
+-	  and the FPGA Bridges associated with either a reconfigurable
+-	  region of an FPGA or a whole FPGA.
++	  FPGA manager driver support for Altera SOCFPGA.
+ 
+-config OF_FPGA_REGION
+-	tristate "FPGA Region Device Tree Overlay Support"
+-	depends on OF && FPGA_REGION
++config FPGA_MGR_SOCFPGA_A10
++	tristate "Altera SoCFPGA Arria10"
++	depends on ARCH_SOCFPGA || COMPILE_TEST
++	select REGMAP_MMIO
+ 	help
+-	  Support for loading FPGA images by applying a Device Tree
+-	  overlay.
++	  FPGA manager driver support for Altera Arria10 SoCFPGA.
+ 
+-config FPGA_MGR_ICE40_SPI
+-	tristate "Lattice iCE40 SPI"
+-	depends on OF && SPI
+-	help
+-	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
++config ALTERA_PR_IP_CORE
++        tristate "Altera Partial Reconfiguration IP Core"
++        help
++          Core driver support for Altera Partial Reconfiguration IP component
+ 
+-config FPGA_MGR_ALTERA_CVP
+-	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
+-	depends on PCI
++config ALTERA_PR_IP_CORE_PLAT
++	tristate "Platform support of Altera Partial Reconfiguration IP Core"
++	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+ 	help
+-	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
+-	  and Arria 10 Altera FPGAs using the CvP interface over PCIe.
++	  Platform driver support for Altera Partial Reconfiguration IP
++	  component
+ 
+ config FPGA_MGR_ALTERA_PS_SPI
+ 	tristate "Altera FPGA Passive Serial over SPI"
+@@ -46,25 +43,19 @@ config FPGA_MGR_ALTERA_PS_SPI
+ 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
+ 	  using the passive serial interface over SPI.
+ 
+-config FPGA_MGR_SOCFPGA
+-	tristate "Altera SOCFPGA FPGA Manager"
+-	depends on ARCH_SOCFPGA || COMPILE_TEST
+-	help
+-	  FPGA manager driver support for Altera SOCFPGA.
+-
+-config FPGA_MGR_SOCFPGA_A10
+-	tristate "Altera SoCFPGA Arria10"
+-	depends on ARCH_SOCFPGA || COMPILE_TEST
+-	select REGMAP_MMIO
++config FPGA_MGR_ALTERA_CVP
++	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
++	depends on PCI
+ 	help
+-	  FPGA manager driver support for Altera Arria10 SoCFPGA.
++	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
++	  and Arria 10 Altera FPGAs using the CvP interface over PCIe.
+ 
+-config FPGA_MGR_TS73XX
+-	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+-	depends on ARCH_EP93XX && MACH_TS72XX
++config FPGA_MGR_ZYNQ_FPGA
++	tristate "Xilinx Zynq FPGA"
++	depends on ARCH_ZYNQ || COMPILE_TEST
++	depends on HAS_DMA
+ 	help
+-	  FPGA manager driver support for the Altera Cyclone II FPGA
+-	  present on the TS-73xx SBC boards.
++	  FPGA manager driver support for Xilinx Zynq FPGAs.
+ 
+ config FPGA_MGR_XILINX_SPI
+ 	tristate "Xilinx Configuration over Slave Serial (SPI)"
+@@ -73,12 +64,18 @@ config FPGA_MGR_XILINX_SPI
+ 	  FPGA manager driver support for Xilinx FPGA configuration
+ 	  over slave serial interface.
+ 
+-config FPGA_MGR_ZYNQ_FPGA
+-	tristate "Xilinx Zynq FPGA"
+-	depends on ARCH_ZYNQ || COMPILE_TEST
+-	depends on HAS_DMA
++config FPGA_MGR_ICE40_SPI
++	tristate "Lattice iCE40 SPI"
++	depends on OF && SPI
+ 	help
+-	  FPGA manager driver support for Xilinx Zynq FPGAs.
++	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
++
++config FPGA_MGR_TS73XX
++	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
++	depends on ARCH_EP93XX && MACH_TS72XX
++	help
++	  FPGA manager driver support for the Altera Cyclone II FPGA
++	  present on the TS-73xx SBC boards.
+ 
+ config FPGA_BRIDGE
+ 	tristate "FPGA Bridge Framework"
+@@ -102,18 +99,6 @@ config ALTERA_FREEZE_BRIDGE
+ 	  isolate one region of the FPGA from the busses while that
+ 	  region is being reprogrammed.
+ 
+-config ALTERA_PR_IP_CORE
+-        tristate "Altera Partial Reconfiguration IP Core"
+-        help
+-          Core driver support for Altera Partial Reconfiguration IP component
+-
+-config ALTERA_PR_IP_CORE_PLAT
+-	tristate "Platform support of Altera Partial Reconfiguration IP Core"
+-	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+-	help
+-	  Platform driver support for Altera Partial Reconfiguration IP
+-	  component
+-
+ config XILINX_PR_DECOUPLER
+ 	tristate "Xilinx LogiCORE PR Decoupler"
+ 	depends on FPGA_BRIDGE
+@@ -124,4 +109,19 @@ config XILINX_PR_DECOUPLER
+ 	  region of the FPGA from the busses while that region is
+ 	  being reprogrammed during partial reconfig.
+ 
++config FPGA_REGION
++	tristate "FPGA Region"
++	depends on FPGA_BRIDGE
++	help
++	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
++	  and the FPGA Bridges associated with either a reconfigurable
++	  region of an FPGA or a whole FPGA.
++
++config OF_FPGA_REGION
++	tristate "FPGA Region Device Tree Overlay Support"
++	depends on OF && FPGA_REGION
++	help
++	  Support for loading FPGA images by applying a Device Tree
++	  overlay.
++
+ endif # FPGA
+-- 
+2.19.0
+
diff --git a/patches/1677-fpga-add-attribute-groups.patch b/patches/1677-fpga-add-attribute-groups.patch
new file mode 100644
index 00000000000000..60f748b62bfc32
--- /dev/null
+++ b/patches/1677-fpga-add-attribute-groups.patch
@@ -0,0 +1,122 @@
+From 237bcfff8cc5a7d5cf66a5a3e77c9a1b6e6dea68 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 15 Nov 2017 14:20:28 -0600
+Subject: [PATCH 1677/1795] fpga: add attribute groups
+
+Make it easy to add attributes to low level FPGA drivers the right
+way.  Add attribute groups pointers to structures that are used when
+registering a manager, bridge, or group.  When the low level driver
+registers, set the device attribute group.  The attributes are
+created in device_add.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 845089bbf589be75143d0c9fb326d5595c1b5787)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-bridge.c       | 1 +
+ drivers/fpga/fpga-mgr.c          | 1 +
+ drivers/fpga/fpga-region.c       | 1 +
+ include/linux/fpga/fpga-bridge.h | 2 ++
+ include/linux/fpga/fpga-mgr.h    | 2 ++
+ include/linux/fpga/fpga-region.h | 2 ++
+ 6 files changed, 9 insertions(+)
+
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 0dfe9d78cee2..e693c3607a14 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -367,6 +367,7 @@ int fpga_bridge_register(struct device *dev, const char *name,
+ 	bridge->priv = priv;
+ 
+ 	device_initialize(&bridge->dev);
++	bridge->dev.groups = br_ops->groups;
+ 	bridge->dev.class = fpga_bridge_class;
+ 	bridge->dev.parent = dev;
+ 	bridge->dev.of_node = dev->of_node;
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index d27e8d2a149c..223f2401939b 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -569,6 +569,7 @@ int fpga_mgr_register(struct device *dev, const char *name,
+ 
+ 	device_initialize(&mgr->dev);
+ 	mgr->dev.class = fpga_mgr_class;
++	mgr->dev.groups = mops->groups;
+ 	mgr->dev.parent = dev;
+ 	mgr->dev.of_node = dev->of_node;
+ 	mgr->dev.id = id;
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index afc61885a601..edab2a2e03ef 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -173,6 +173,7 @@ int fpga_region_register(struct device *dev, struct fpga_region *region)
+ 	mutex_init(&region->mutex);
+ 	INIT_LIST_HEAD(&region->bridge_list);
+ 	device_initialize(&region->dev);
++	region->dev.groups = region->groups;
+ 	region->dev.class = fpga_region_class;
+ 	region->dev.parent = dev;
+ 	region->dev.of_node = dev->of_node;
+diff --git a/include/linux/fpga/fpga-bridge.h b/include/linux/fpga/fpga-bridge.h
+index 6ca41f8f949f..3694821a6d2d 100644
+--- a/include/linux/fpga/fpga-bridge.h
++++ b/include/linux/fpga/fpga-bridge.h
+@@ -13,11 +13,13 @@ struct fpga_bridge;
+  * @enable_show: returns the FPGA bridge's status
+  * @enable_set: set a FPGA bridge as enabled or disabled
+  * @fpga_bridge_remove: set FPGA into a specific state during driver remove
++ * @groups: optional attribute groups.
+  */
+ struct fpga_bridge_ops {
+ 	int (*enable_show)(struct fpga_bridge *bridge);
+ 	int (*enable_set)(struct fpga_bridge *bridge, bool enable);
+ 	void (*fpga_bridge_remove)(struct fpga_bridge *bridge);
++	const struct attribute_group **groups;
+ };
+ 
+ /**
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index 4fb706bd9aba..3c6de23aabdf 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -115,6 +115,7 @@ struct fpga_image_info {
+  * @write_sg: write the scatter list of configuration data to the FPGA
+  * @write_complete: set FPGA to operating state after writing is done
+  * @fpga_remove: optional: Set FPGA into a specific state during driver remove
++ * @groups: optional attribute groups.
+  *
+  * fpga_manager_ops are the low level functions implemented by a specific
+  * fpga manager driver.  The optional ones are tested for NULL before being
+@@ -131,6 +132,7 @@ struct fpga_manager_ops {
+ 	int (*write_complete)(struct fpga_manager *mgr,
+ 			      struct fpga_image_info *info);
+ 	void (*fpga_remove)(struct fpga_manager *mgr);
++	const struct attribute_group **groups;
+ };
+ 
+ /**
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index 704844944631..b6520318ab9c 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -14,6 +14,7 @@
+  * @info: FPGA image info
+  * @priv: private data
+  * @get_bridges: optional function to get bridges to a list
++ * @groups: optional attribute groups.
+  */
+ struct fpga_region {
+ 	struct device dev;
+@@ -23,6 +24,7 @@ struct fpga_region {
+ 	struct fpga_image_info *info;
+ 	void *priv;
+ 	int (*get_bridges)(struct fpga_region *region);
++	const struct attribute_group **groups;
+ };
+ 
+ #define to_fpga_region(d) container_of(d, struct fpga_region, dev)
+-- 
+2.19.0
+
diff --git a/patches/1678-fpga-fpga-mgr-remove-unnecessary-code-in-__fpga_mgr_.patch b/patches/1678-fpga-fpga-mgr-remove-unnecessary-code-in-__fpga_mgr_.patch
new file mode 100644
index 00000000000000..6872d46ea7167d
--- /dev/null
+++ b/patches/1678-fpga-fpga-mgr-remove-unnecessary-code-in-__fpga_mgr_.patch
@@ -0,0 +1,39 @@
+From 3d9c71ca6f8c8c08b99758eba16f9749813b0748 Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
+Date: Wed, 15 Nov 2017 16:33:10 -0600
+Subject: [PATCH 1678/1795] fpga: fpga-mgr: remove unnecessary code in
+ __fpga_mgr_get
+
+Notice that mgr = to_fpga_manager(dev); expands to:
+
+mgr = container_of(dev, struct fpga_manager, dev);
+
+and container_of is never null, so this null check is
+unnecessary.
+
+Addresses-Coverity-ID: 1397916
+Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5f76c6f313bffbf372c0722582e7bd509f0d3510)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-mgr.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 223f2401939b..9939d2cbc9a6 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -412,8 +412,6 @@ static struct fpga_manager *__fpga_mgr_get(struct device *dev)
+ 	struct fpga_manager *mgr;
+ 
+ 	mgr = to_fpga_manager(dev);
+-	if (!mgr)
+-		goto err_dev;
+ 
+ 	if (!try_module_get(dev->parent->driver->owner))
+ 		goto err_dev;
+-- 
+2.19.0
+
diff --git a/patches/1679-fpga-fpga-bridge-remove-unnecessary-null-check-in-of.patch b/patches/1679-fpga-fpga-bridge-remove-unnecessary-null-check-in-of.patch
new file mode 100644
index 00000000000000..572758f10b23f9
--- /dev/null
+++ b/patches/1679-fpga-fpga-bridge-remove-unnecessary-null-check-in-of.patch
@@ -0,0 +1,41 @@
+From ecca9d548c287ec7b057d7fbe48a0430bf471d28 Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <garsilva@embeddedor.com>
+Date: Wed, 15 Nov 2017 16:33:11 -0600
+Subject: [PATCH 1679/1795] fpga: fpga-bridge: remove unnecessary null check in
+ of_fpga_bridge_get
+
+Notice that bridge = to_fpga_bridge(dev); expands to:
+
+bridge = container_of(dev, struct fpga_bridge, dev);
+
+and container_of is never null, so this null check is
+unnecessary.
+
+Addresses-Coverity-ID: 1397912
+Reported-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
+Reviewed-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 397f33cb0a7d60b3d061e70b66baee36a690351a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-bridge.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index e693c3607a14..31bd2c59c305 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -78,8 +78,6 @@ static struct fpga_bridge *__fpga_bridge_get(struct device *dev,
+ 	int ret = -ENODEV;
+ 
+ 	bridge = to_fpga_bridge(dev);
+-	if (!bridge)
+-		goto err_dev;
+ 
+ 	bridge->info = info;
+ 
+-- 
+2.19.0
+
diff --git a/patches/1680-fpga-region-release-of_parse_phandle-nodes-after-use.patch b/patches/1680-fpga-region-release-of_parse_phandle-nodes-after-use.patch
new file mode 100644
index 00000000000000..4290f7352e859c
--- /dev/null
+++ b/patches/1680-fpga-region-release-of_parse_phandle-nodes-after-use.patch
@@ -0,0 +1,70 @@
+From 4841952194efd15c5f2bfe695a400b476fd97053 Mon Sep 17 00:00:00 2001
+From: Ian Abbott <abbotti@mev.co.uk>
+Date: Wed, 15 Nov 2017 16:33:12 -0600
+Subject: [PATCH 1680/1795] fpga: region: release of_parse_phandle nodes after
+ use
+
+Both fpga_region_get_manager() and fpga_region_get_bridges() call
+of_parse_phandle(), but nothing calls of_node_put() on the returned
+struct device_node pointers.  Make sure to do that to stop their
+reference counters getting out of whack.
+
+Fixes: 0fa20cdfcc1f ("fpga: fpga-region: device tree control for FPGA")
+Cc: <stable@vger.kernel.org> # 4.10+
+Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 0f5eb1545907edeea7672a9c1652c4231150ff22)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/of-fpga-region.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+index c6b21194dcbc..119ff75522f1 100644
+--- a/drivers/fpga/of-fpga-region.c
++++ b/drivers/fpga/of-fpga-region.c
+@@ -73,6 +73,7 @@ static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
+ 			mgr_node = of_parse_phandle(np, "fpga-mgr", 0);
+ 			if (mgr_node) {
+ 				mgr = of_fpga_mgr_get(mgr_node);
++				of_node_put(mgr_node);
+ 				of_node_put(np);
+ 				return mgr;
+ 			}
+@@ -120,10 +121,13 @@ static int of_fpga_region_get_bridges(struct fpga_region *region)
+ 		parent_br = region_np->parent;
+ 
+ 	/* If overlay has a list of bridges, use it. */
+-	if (of_parse_phandle(info->overlay, "fpga-bridges", 0))
++	br = of_parse_phandle(info->overlay, "fpga-bridges", 0);
++	if (br) {
++		of_node_put(br);
+ 		np = info->overlay;
+-	else
++	} else {
+ 		np = region_np;
++	}
+ 
+ 	for (i = 0; ; i++) {
+ 		br = of_parse_phandle(np, "fpga-bridges", i);
+@@ -131,12 +135,15 @@ static int of_fpga_region_get_bridges(struct fpga_region *region)
+ 			break;
+ 
+ 		/* If parent bridge is in list, skip it. */
+-		if (br == parent_br)
++		if (br == parent_br) {
++			of_node_put(br);
+ 			continue;
++		}
+ 
+ 		/* If node is a bridge, get it and add to list */
+ 		ret = of_fpga_bridge_get_to_list(br, info,
+ 						 &region->bridge_list);
++		of_node_put(br);
+ 
+ 		/* If any of the bridges are in use, give up */
+ 		if (ret == -EBUSY) {
+-- 
+2.19.0
+
diff --git a/patches/1681-fpga-socfpga-a10-disable-clk-on-error-in-socfpga_a10.patch b/patches/1681-fpga-socfpga-a10-disable-clk-on-error-in-socfpga_a10.patch
new file mode 100644
index 00000000000000..69cdf8fe842f81
--- /dev/null
+++ b/patches/1681-fpga-socfpga-a10-disable-clk-on-error-in-socfpga_a10.patch
@@ -0,0 +1,43 @@
+From a2fc900d2c9441c2dcc5f907140c3298e5117f14 Mon Sep 17 00:00:00 2001
+From: Alexey Khoroshilov <khoroshilov@ispras.ru>
+Date: Fri, 8 Dec 2017 11:37:00 -0600
+Subject: [PATCH 1681/1795] fpga: socfpga-a10: disable clk on error in
+ socfpga_a10_fpga_probe()
+
+If fpga_mgr_register() fails, a clock is left undisabled.
+
+Found by Linux Driver Verification project (linuxtesting.org).
+
+Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
+Reviewed-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d9cc5a0edb705ced4ce91b4c6ee73ec6f5bfa49a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/socfpga-a10.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
+index f8770af0f6b5..a46e343a5b72 100644
+--- a/drivers/fpga/socfpga-a10.c
++++ b/drivers/fpga/socfpga-a10.c
+@@ -519,8 +519,14 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev)
+ 		return -EBUSY;
+ 	}
+ 
+-	return fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
++	ret = fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
+ 				 &socfpga_a10_fpga_mgr_ops, priv);
++	if (ret) {
++		clk_disable_unprepare(priv->clk);
++		return ret;
++	}
++
++	return 0;
+ }
+ 
+ static int socfpga_a10_fpga_remove(struct platform_device *pdev)
+-- 
+2.19.0
+
diff --git a/patches/1682-PCI-Add-Altera-vendor-ID.patch b/patches/1682-PCI-Add-Altera-vendor-ID.patch
new file mode 100644
index 00000000000000..5daaecaebeac50
--- /dev/null
+++ b/patches/1682-PCI-Add-Altera-vendor-ID.patch
@@ -0,0 +1,65 @@
+From 470951bcaf92be13ec39859bbfda5fb9f05fde96 Mon Sep 17 00:00:00 2001
+From: Johannes Thumshirn <jthumshirn@suse.de>
+Date: Mon, 12 Mar 2018 10:41:18 +0100
+Subject: [PATCH 1682/1795] PCI: Add Altera vendor ID
+
+Add the Altera PCI Vendor id to pci_ids.h and remove the private
+definitions from xillybus_pcie.c and altera-cvp.c.
+
+Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de>
+Cc: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Eli Billauer <eli.billauer@gmail.com>
+Cc: Anatolij Gustschin <agust@denx.de>
+Acked-by: Eli Billauer <eli.billauer@gmail.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit c4ccc893ce2ab819171f797e8b2c702cc87cb84a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/char/xillybus/xillybus_pcie.c | 1 -
+ drivers/fpga/altera-cvp.c             | 2 --
+ include/linux/pci_ids.h               | 2 ++
+ 3 files changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/char/xillybus/xillybus_pcie.c b/drivers/char/xillybus/xillybus_pcie.c
+index dff2d1538164..05e5324f60bd 100644
+--- a/drivers/char/xillybus/xillybus_pcie.c
++++ b/drivers/char/xillybus/xillybus_pcie.c
+@@ -24,7 +24,6 @@ MODULE_LICENSE("GPL v2");
+ 
+ #define PCI_DEVICE_ID_XILLYBUS		0xebeb
+ 
+-#define PCI_VENDOR_ID_ALTERA		0x1172
+ #define PCI_VENDOR_ID_ACTEL		0x11aa
+ #define PCI_VENDOR_ID_LATTICE		0x1204
+ 
+diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
+index 00e73d28077c..77b04e4b3254 100644
+--- a/drivers/fpga/altera-cvp.c
++++ b/drivers/fpga/altera-cvp.c
+@@ -384,8 +384,6 @@ static int altera_cvp_probe(struct pci_dev *pdev,
+ 			    const struct pci_device_id *dev_id);
+ static void altera_cvp_remove(struct pci_dev *pdev);
+ 
+-#define PCI_VENDOR_ID_ALTERA	0x1172
+-
+ static struct pci_device_id altera_cvp_id_tbl[] = {
+ 	{ PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
+ 	{ }
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 7fa3f1498b34..b9175f983c1d 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1559,6 +1559,8 @@
+ #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
+ #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
+ 
++#define PCI_VENDOR_ID_ALTERA		0x1172
++
+ #define PCI_VENDOR_ID_SBE		0x1176
+ #define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+ #define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+-- 
+2.19.0
+
diff --git a/patches/1683-fpga-Remove-depends-on-HAS_DMA-in-case-of-platform-d.patch b/patches/1683-fpga-Remove-depends-on-HAS_DMA-in-case-of-platform-d.patch
new file mode 100644
index 00000000000000..8a99c548cbae74
--- /dev/null
+++ b/patches/1683-fpga-Remove-depends-on-HAS_DMA-in-case-of-platform-d.patch
@@ -0,0 +1,43 @@
+From 0304ec809a41b83d1997f0a1a0239c9b799f4608 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 17 Apr 2018 19:49:06 +0200
+Subject: [PATCH 1683/1795] fpga: Remove depends on HAS_DMA in case of platform
+ dependency
+
+Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
+symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
+In most cases this other symbol is an architecture or platform specific
+symbol, or PCI.
+
+Generic symbols and drivers without platform dependencies keep their
+dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
+cannot work anyway.
+
+This simplifies the dependencies, and allows to improve compile-testing.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Reviewed-by: Mark Brown <broonie@kernel.org>
+Acked-by: Robin Murphy <robin.murphy@arm.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 84d84c5b8ff1a91bbd463a84df65b16ea60dff5d)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index f47ef848bcd0..fd539132542e 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -53,7 +53,6 @@ config FPGA_MGR_ALTERA_CVP
+ config FPGA_MGR_ZYNQ_FPGA
+ 	tristate "Xilinx Zynq FPGA"
+ 	depends on ARCH_ZYNQ || COMPILE_TEST
+-	depends on HAS_DMA
+ 	help
+ 	  FPGA manager driver support for Xilinx Zynq FPGAs.
+ 
+-- 
+2.19.0
+
diff --git a/patches/1684-fpga-lattice-machxo2-Add-Lattice-MachXO2-support.patch b/patches/1684-fpga-lattice-machxo2-Add-Lattice-MachXO2-support.patch
new file mode 100644
index 00000000000000..bc1026df95eb2c
--- /dev/null
+++ b/patches/1684-fpga-lattice-machxo2-Add-Lattice-MachXO2-support.patch
@@ -0,0 +1,468 @@
+From 0c9724e3df96a7d3739f1aefab0723ed87f9f0c0 Mon Sep 17 00:00:00 2001
+From: Paolo Pisati <p.pisati@gmail.com>
+Date: Mon, 16 Apr 2018 20:43:36 -0700
+Subject: [PATCH 1684/1795] fpga: lattice machxo2: Add Lattice MachXO2 support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds support to the FPGA manager for programming
+MachXO2 device’s internal flash memory, via slave SPI.
+
+Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
+[atull@kernel.org: use existing FPGA mgr API]
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+(cherry picked from commit 88fb3a0023307356a05f6b8e61a0ccddc6d32b2c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig       |   7 +
+ drivers/fpga/Makefile      |   1 +
+ drivers/fpga/machxo2-spi.c | 403 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 411 insertions(+)
+ create mode 100644 drivers/fpga/machxo2-spi.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index fd539132542e..ee9c5420c47f 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -69,6 +69,13 @@ config FPGA_MGR_ICE40_SPI
+ 	help
+ 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+ 
++config FPGA_MGR_MACHXO2_SPI
++	tristate "Lattice MachXO2 SPI"
++	depends on SPI
++	help
++	  FPGA manager driver support for Lattice MachXO2 configuration
++	  over slave SPI interface.
++
+ config FPGA_MGR_TS73XX
+ 	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ 	depends on ARCH_EP93XX && MACH_TS72XX
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 3cb276a0f88d..f9803dad6919 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
+ obj-$(CONFIG_FPGA_MGR_ALTERA_CVP)	+= altera-cvp.o
+ obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
+ obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
++obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)	+= machxo2-spi.o
+ obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
+ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
+ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
+diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c
+new file mode 100644
+index 000000000000..8e95ec9c5c9a
+--- /dev/null
++++ b/drivers/fpga/machxo2-spi.c
+@@ -0,0 +1,403 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Lattice MachXO2 Slave SPI Driver
++ *
++ * Manage Lattice FPGA firmware that is loaded over SPI using
++ * the slave serial configuration interface.
++ *
++ * Copyright (C) 2018 Paolo Pisati <p.pisati@gmail.com>
++ */
++
++#include <linux/delay.h>
++#include <linux/fpga/fpga-mgr.h>
++#include <linux/gpio/consumer.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/spi/spi.h>
++
++/* MachXO2 Programming Guide - sysCONFIG Programming Commands */
++#define IDCODE_PUB		{0xe0, 0x00, 0x00, 0x00}
++#define ISC_ENABLE		{0xc6, 0x08, 0x00, 0x00}
++#define ISC_ERASE		{0x0e, 0x04, 0x00, 0x00}
++#define ISC_PROGRAMDONE		{0x5e, 0x00, 0x00, 0x00}
++#define LSC_INITADDRESS		{0x46, 0x00, 0x00, 0x00}
++#define LSC_PROGINCRNV		{0x70, 0x00, 0x00, 0x01}
++#define LSC_READ_STATUS		{0x3c, 0x00, 0x00, 0x00}
++#define LSC_REFRESH		{0x79, 0x00, 0x00, 0x00}
++
++/*
++ * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
++ * Sheet' sysCONFIG Port Timing Specifications (3-36)
++ */
++#define MACHXO2_MAX_SPEED		66000000
++
++#define MACHXO2_LOW_DELAY_USEC		5
++#define MACHXO2_HIGH_DELAY_USEC		200
++#define MACHXO2_REFRESH_USEC		4800
++#define MACHXO2_MAX_BUSY_LOOP		128
++#define MACHXO2_MAX_REFRESH_LOOP	16
++
++#define MACHXO2_PAGE_SIZE		16
++#define MACHXO2_BUF_SIZE		(MACHXO2_PAGE_SIZE + 4)
++
++/* Status register bits, errors and error mask */
++#define BUSY	12
++#define DONE	8
++#define DVER	27
++#define ENAB	9
++#define ERRBITS	23
++#define ERRMASK	7
++#define FAIL	13
++
++#define ENOERR	0 /* no error */
++#define EID	1
++#define ECMD	2
++#define ECRC	3
++#define EPREAM	4 /* preamble error */
++#define EABRT	5 /* abort error */
++#define EOVERFL	6 /* overflow error */
++#define ESDMEOF	7 /* SDM EOF */
++
++static inline u8 get_err(unsigned long *status)
++{
++	return (*status >> ERRBITS) & ERRMASK;
++}
++
++static int get_status(struct spi_device *spi, unsigned long *status)
++{
++	struct spi_message msg;
++	struct spi_transfer rx, tx;
++	static const u8 cmd[] = LSC_READ_STATUS;
++	int ret;
++
++	memset(&rx, 0, sizeof(rx));
++	memset(&tx, 0, sizeof(tx));
++	tx.tx_buf = cmd;
++	tx.len = sizeof(cmd);
++	rx.rx_buf = status;
++	rx.len = 4;
++	spi_message_init(&msg);
++	spi_message_add_tail(&tx, &msg);
++	spi_message_add_tail(&rx, &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		return ret;
++
++	*status = be32_to_cpu(*status);
++
++	return 0;
++}
++
++#ifdef DEBUG
++static const char *get_err_string(u8 err)
++{
++	switch (err) {
++	case ENOERR:	return "No Error";
++	case EID:	return "ID ERR";
++	case ECMD:	return "CMD ERR";
++	case ECRC:	return "CRC ERR";
++	case EPREAM:	return "Preamble ERR";
++	case EABRT:	return "Abort ERR";
++	case EOVERFL:	return "Overflow ERR";
++	case ESDMEOF:	return "SDM EOF";
++	}
++
++	return "Default switch case";
++}
++#endif
++
++static void dump_status_reg(unsigned long *status)
++{
++#ifdef DEBUG
++	pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
++		 *status, test_bit(DONE, status), test_bit(ENAB, status),
++		 test_bit(BUSY, status), test_bit(FAIL, status),
++		 test_bit(DVER, status), get_err_string(get_err(status)));
++#endif
++}
++
++static int wait_until_not_busy(struct spi_device *spi)
++{
++	unsigned long status;
++	int ret, loop = 0;
++
++	do {
++		ret = get_status(spi, &status);
++		if (ret)
++			return ret;
++		if (++loop >= MACHXO2_MAX_BUSY_LOOP)
++			return -EBUSY;
++	} while (test_bit(BUSY, &status));
++
++	return 0;
++}
++
++static int machxo2_cleanup(struct fpga_manager *mgr)
++{
++	struct spi_device *spi = mgr->priv;
++	struct spi_message msg;
++	struct spi_transfer tx[2];
++	static const u8 erase[] = ISC_ERASE;
++	static const u8 refresh[] = LSC_REFRESH;
++	int ret;
++
++	memset(tx, 0, sizeof(tx));
++	spi_message_init(&msg);
++	tx[0].tx_buf = &erase;
++	tx[0].len = sizeof(erase);
++	spi_message_add_tail(&tx[0], &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		goto fail;
++
++	ret = wait_until_not_busy(spi);
++	if (ret)
++		goto fail;
++
++	spi_message_init(&msg);
++	tx[1].tx_buf = &refresh;
++	tx[1].len = sizeof(refresh);
++	tx[1].delay_usecs = MACHXO2_REFRESH_USEC;
++	spi_message_add_tail(&tx[1], &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		goto fail;
++
++	return 0;
++fail:
++	dev_err(&mgr->dev, "Cleanup failed\n");
++
++	return ret;
++}
++
++static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
++{
++	struct spi_device *spi = mgr->priv;
++	unsigned long status;
++
++	get_status(spi, &status);
++	if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
++	    get_err(&status) == ENOERR)
++		return FPGA_MGR_STATE_OPERATING;
++
++	return FPGA_MGR_STATE_UNKNOWN;
++}
++
++static int machxo2_write_init(struct fpga_manager *mgr,
++			      struct fpga_image_info *info,
++			      const char *buf, size_t count)
++{
++	struct spi_device *spi = mgr->priv;
++	struct spi_message msg;
++	struct spi_transfer tx[3];
++	static const u8 enable[] = ISC_ENABLE;
++	static const u8 erase[] = ISC_ERASE;
++	static const u8 initaddr[] = LSC_INITADDRESS;
++	unsigned long status;
++	int ret;
++
++	if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
++		dev_err(&mgr->dev,
++			"Partial reconfiguration is not supported\n");
++		return -ENOTSUPP;
++	}
++
++	get_status(spi, &status);
++	dump_status_reg(&status);
++	memset(tx, 0, sizeof(tx));
++	spi_message_init(&msg);
++	tx[0].tx_buf = &enable;
++	tx[0].len = sizeof(enable);
++	tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC;
++	spi_message_add_tail(&tx[0], &msg);
++
++	tx[1].tx_buf = &erase;
++	tx[1].len = sizeof(erase);
++	spi_message_add_tail(&tx[1], &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		goto fail;
++
++	ret = wait_until_not_busy(spi);
++	if (ret)
++		goto fail;
++
++	get_status(spi, &status);
++	if (test_bit(FAIL, &status))
++		goto fail;
++	dump_status_reg(&status);
++
++	spi_message_init(&msg);
++	tx[2].tx_buf = &initaddr;
++	tx[2].len = sizeof(initaddr);
++	spi_message_add_tail(&tx[2], &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		goto fail;
++
++	get_status(spi, &status);
++	dump_status_reg(&status);
++
++	return 0;
++fail:
++	dev_err(&mgr->dev, "Error during FPGA init.\n");
++
++	return ret;
++}
++
++static int machxo2_write(struct fpga_manager *mgr, const char *buf,
++			 size_t count)
++{
++	struct spi_device *spi = mgr->priv;
++	struct spi_message msg;
++	struct spi_transfer tx;
++	static const u8 progincr[] = LSC_PROGINCRNV;
++	u8 payload[MACHXO2_BUF_SIZE];
++	unsigned long status;
++	int i, ret;
++
++	if (count % MACHXO2_PAGE_SIZE != 0) {
++		dev_err(&mgr->dev, "Malformed payload.\n");
++		return -EINVAL;
++	}
++	get_status(spi, &status);
++	dump_status_reg(&status);
++	memcpy(payload, &progincr, sizeof(progincr));
++	for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
++		memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
++		memset(&tx, 0, sizeof(tx));
++		spi_message_init(&msg);
++		tx.tx_buf = payload;
++		tx.len = MACHXO2_BUF_SIZE;
++		tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC;
++		spi_message_add_tail(&tx, &msg);
++		ret = spi_sync(spi, &msg);
++		if (ret) {
++			dev_err(&mgr->dev, "Error loading the bitstream.\n");
++			return ret;
++		}
++	}
++	get_status(spi, &status);
++	dump_status_reg(&status);
++
++	return 0;
++}
++
++static int machxo2_write_complete(struct fpga_manager *mgr,
++				  struct fpga_image_info *info)
++{
++	struct spi_device *spi = mgr->priv;
++	struct spi_message msg;
++	struct spi_transfer tx[2];
++	static const u8 progdone[] = ISC_PROGRAMDONE;
++	static const u8 refresh[] = LSC_REFRESH;
++	unsigned long status;
++	int ret, refreshloop = 0;
++
++	memset(tx, 0, sizeof(tx));
++	spi_message_init(&msg);
++	tx[0].tx_buf = &progdone;
++	tx[0].len = sizeof(progdone);
++	spi_message_add_tail(&tx[0], &msg);
++	ret = spi_sync(spi, &msg);
++	if (ret)
++		goto fail;
++	ret = wait_until_not_busy(spi);
++	if (ret)
++		goto fail;
++
++	get_status(spi, &status);
++	dump_status_reg(&status);
++	if (!test_bit(DONE, &status)) {
++		machxo2_cleanup(mgr);
++		goto fail;
++	}
++
++	do {
++		spi_message_init(&msg);
++		tx[1].tx_buf = &refresh;
++		tx[1].len = sizeof(refresh);
++		tx[1].delay_usecs = MACHXO2_REFRESH_USEC;
++		spi_message_add_tail(&tx[1], &msg);
++		ret = spi_sync(spi, &msg);
++		if (ret)
++			goto fail;
++
++		/* check refresh status */
++		get_status(spi, &status);
++		dump_status_reg(&status);
++		if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
++		    get_err(&status) == ENOERR)
++			break;
++		if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
++			machxo2_cleanup(mgr);
++			goto fail;
++		}
++	} while (1);
++
++	get_status(spi, &status);
++	dump_status_reg(&status);
++
++	return 0;
++fail:
++	dev_err(&mgr->dev, "Refresh failed.\n");
++
++	return ret;
++}
++
++static const struct fpga_manager_ops machxo2_ops = {
++	.state = machxo2_spi_state,
++	.write_init = machxo2_write_init,
++	.write = machxo2_write,
++	.write_complete = machxo2_write_complete,
++};
++
++static int machxo2_spi_probe(struct spi_device *spi)
++{
++	struct device *dev = &spi->dev;
++
++	if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
++		dev_err(dev, "Speed is too high\n");
++		return -EINVAL;
++	}
++
++	return fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
++				 &machxo2_ops, spi);
++}
++
++static int machxo2_spi_remove(struct spi_device *spi)
++{
++	struct device *dev = &spi->dev;
++
++	fpga_mgr_unregister(dev);
++
++	return 0;
++}
++
++static const struct of_device_id of_match[] = {
++	{ .compatible = "lattice,machxo2-slave-spi", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, of_match);
++
++static const struct spi_device_id lattice_ids[] = {
++	{ "machxo2-slave-spi", 0 },
++	{ },
++};
++MODULE_DEVICE_TABLE(spi, lattice_ids);
++
++static struct spi_driver machxo2_spi_driver = {
++	.driver = {
++		.name = "machxo2-slave-spi",
++		.of_match_table = of_match_ptr(of_match),
++	},
++	.probe = machxo2_spi_probe,
++	.remove = machxo2_spi_remove,
++	.id_table = lattice_ids,
++};
++
++module_spi_driver(machxo2_spi_driver)
++
++MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>");
++MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
++MODULE_LICENSE("GPL v2");
+-- 
+2.19.0
+
diff --git a/patches/1685-fpga-fpga-region-comment-on-fpga_region_program_fpga.patch b/patches/1685-fpga-fpga-region-comment-on-fpga_region_program_fpga.patch
new file mode 100644
index 00000000000000..a790bf9b7c461b
--- /dev/null
+++ b/patches/1685-fpga-fpga-region-comment-on-fpga_region_program_fpga.patch
@@ -0,0 +1,37 @@
+From f8d3ac0e9280011f41563315eef360504d16c9a6 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Mon, 16 Apr 2018 20:43:37 -0700
+Subject: [PATCH 1685/1795] fpga: fpga-region: comment on
+ fpga_region_program_fpga locking
+
+Add a comment to the header of fpga_region_program_fpga()
+regarding locking of the bridges.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 093a89d4c21701e61025386a08a2d1ec5d97c805)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index edab2a2e03ef..cb0603e07ff8 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -95,6 +95,11 @@ static void fpga_region_put(struct fpga_region *region)
+  * fpga_region_program_fpga - program FPGA
+  * @region: FPGA region
+  * Program an FPGA using fpga image info (region->info).
++ * If the region has a get_bridges function, the exclusive reference for the
++ * bridges will be held if programming succeeds.  This is intended to prevent
++ * reprogramming the region until the caller considers it safe to do so.
++ * The caller will need to call fpga_bridges_put() before attempting to
++ * reprogram the region.
+  * Return 0 for success or negative error code.
+  */
+ int fpga_region_program_fpga(struct fpga_region *region)
+-- 
+2.19.0
+
diff --git a/patches/1686-fpga-region-don-t-use-drvdata-in-common-fpga-code.patch b/patches/1686-fpga-region-don-t-use-drvdata-in-common-fpga-code.patch
new file mode 100644
index 00000000000000..00e30164c034a7
--- /dev/null
+++ b/patches/1686-fpga-region-don-t-use-drvdata-in-common-fpga-code.patch
@@ -0,0 +1,51 @@
+From 732dc5dc0b45dbcc267b26be627b7e0aaa58839f Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:54 -0500
+Subject: [PATCH 1686/1795] fpga: region: don't use drvdata in common fpga code
+
+Changes to fpga_region_register function to not set drvdata.
+
+Setting drvdata is fine for DT based devices that will have one region
+per platform device.  However PCIe based devices may have multiple
+FPGA regions under one PCIe device.  Without these changes, the PCIe
+solution has to create an extra device for each child region to hold
+drvdata.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Reported-by: Jiuyue Ma <majiuyue@huawei.com>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit bbaa9cd3a605e337cefc566e5ac1b110763c8d1c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c    | 1 -
+ drivers/fpga/of-fpga-region.c | 1 +
+ 2 files changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index cb0603e07ff8..f634a8ed5e2c 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -183,7 +183,6 @@ int fpga_region_register(struct device *dev, struct fpga_region *region)
+ 	region->dev.parent = dev;
+ 	region->dev.of_node = dev->of_node;
+ 	region->dev.id = id;
+-	dev_set_drvdata(dev, region);
+ 
+ 	ret = dev_set_name(&region->dev, "region%d", id);
+ 	if (ret)
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+index 119ff75522f1..35e7e8c4a0cb 100644
+--- a/drivers/fpga/of-fpga-region.c
++++ b/drivers/fpga/of-fpga-region.c
+@@ -438,6 +438,7 @@ static int of_fpga_region_probe(struct platform_device *pdev)
+ 		goto eprobe_mgr_put;
+ 
+ 	of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
++	dev_set_drvdata(dev, region);
+ 
+ 	dev_info(dev, "FPGA Region probed\n");
+ 
+-- 
+2.19.0
+
diff --git a/patches/1687-fpga-manager-change-api-don-t-use-drvdata.patch b/patches/1687-fpga-manager-change-api-don-t-use-drvdata.patch
new file mode 100644
index 00000000000000..39979ac7c668fb
--- /dev/null
+++ b/patches/1687-fpga-manager-change-api-don-t-use-drvdata.patch
@@ -0,0 +1,716 @@
+From 2a248bb9cbcbeb29a7cef5ed71dd9d65a568ac94 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:55 -0500
+Subject: [PATCH 1687/1795] fpga: manager: change api, don't use drvdata
+
+Change fpga_mgr_register to not set or use drvdata.  This supports
+the case where a PCIe device has more than one manager.
+
+Add fpga_mgr_create/free functions.  Change fpga_mgr_register and
+fpga_mgr_unregister functions to take the mgr struct as their only
+parameter.
+
+  struct fpga_manager *fpga_mgr_create(struct device *dev,
+                const char *name,
+                const struct fpga_manager_ops *mops,
+                void *priv);
+  void fpga_mgr_free(struct fpga_manager *mgr);
+  int fpga_mgr_register(struct fpga_manager *mgr);
+  void fpga_mgr_unregister(struct fpga_manager *mgr);
+
+Update the drivers that call fpga_mgr_register with the new API.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+[Moritz: Fixup whitespace issue]
+Reported-by: Jiuyue Ma <majiuyue@huawei.com>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+(cherry picked from commit 7085e2a94f7df5f419e3cfb2fe809ce6564e9629)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/fpga/fpga-mgr.txt  | 35 ++++++++++----
+ drivers/fpga/altera-cvp.c        | 19 ++++++--
+ drivers/fpga/altera-pr-ip-core.c | 18 +++++++-
+ drivers/fpga/altera-ps-spi.c     | 20 ++++++--
+ drivers/fpga/fpga-mgr.c          | 78 +++++++++++++++++++++-----------
+ drivers/fpga/ice40-spi.c         | 21 +++++++--
+ drivers/fpga/machxo2-spi.c       | 20 ++++++--
+ drivers/fpga/socfpga-a10.c       | 14 ++++--
+ drivers/fpga/socfpga.c           | 19 ++++++--
+ drivers/fpga/ts73xx-fpga.c       | 20 ++++++--
+ drivers/fpga/xilinx-spi.c        | 20 ++++++--
+ drivers/fpga/zynq-fpga.c         | 14 ++++--
+ include/linux/fpga/fpga-mgr.h    | 10 ++--
+ 13 files changed, 237 insertions(+), 71 deletions(-)
+
+diff --git a/Documentation/fpga/fpga-mgr.txt b/Documentation/fpga/fpga-mgr.txt
+index cc6413ed6fc9..86b6df66a905 100644
+--- a/Documentation/fpga/fpga-mgr.txt
++++ b/Documentation/fpga/fpga-mgr.txt
+@@ -63,17 +63,23 @@ The user should call fpga_mgr_lock and verify that it returns 0 before
+ attempting to program the FPGA.  Likewise, the user should call
+ fpga_mgr_unlock when done programming the FPGA.
+ 
++To alloc/free a FPGA manager struct:
++------------------------------------
++
++	struct fpga_manager *fpga_mgr_create(struct device *dev,
++					     const char *name,
++					     const struct fpga_manager_ops *mops,
++					     void *priv);
++	void fpga_mgr_free(struct fpga_manager *mgr);
+ 
+ To register or unregister the low level FPGA-specific driver:
+ -------------------------------------------------------------
+ 
+-	int fpga_mgr_register(struct device *dev, const char *name,
+-			      const struct fpga_manager_ops *mops,
+-			      void *priv);
++	int fpga_mgr_register(struct fpga_manager *mgr);
+ 
+-	void fpga_mgr_unregister(struct device *dev);
++	void fpga_mgr_unregister(struct fpga_manager *mgr);
+ 
+-Use of these two functions is described below in "How To Support a new FPGA
++Use of these functions is described below in "How To Support a new FPGA
+ device."
+ 
+ 
+@@ -148,6 +154,7 @@ static int socfpga_fpga_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct socfpga_fpga_priv *priv;
++	struct fpga_manager *mgr;
+ 	int ret;
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+@@ -157,13 +164,25 @@ static int socfpga_fpga_probe(struct platform_device *pdev)
+ 	/* ... do ioremaps, get interrupts, etc. and save
+ 	   them in priv... */
+ 
+-	return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
+-				 &socfpga_fpga_ops, priv);
++	mgr = fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
++			      &socfpga_fpga_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int socfpga_fpga_remove(struct platform_device *pdev)
+ {
+-	fpga_mgr_unregister(&pdev->dev);
++	struct fpga_manager *mgr = platform_get_drvdata(pdev);
++
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
+index 77b04e4b3254..dd4edd8f22ce 100644
+--- a/drivers/fpga/altera-cvp.c
++++ b/drivers/fpga/altera-cvp.c
+@@ -401,6 +401,7 @@ static int altera_cvp_probe(struct pci_dev *pdev,
+ 			    const struct pci_device_id *dev_id)
+ {
+ 	struct altera_cvp_conf *conf;
++	struct fpga_manager *mgr;
+ 	u16 cmd, val;
+ 	int ret;
+ 
+@@ -452,16 +453,24 @@ static int altera_cvp_probe(struct pci_dev *pdev,
+ 	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
+ 		 ALTERA_CVP_MGR_NAME, pci_name(pdev));
+ 
+-	ret = fpga_mgr_register(&pdev->dev, conf->mgr_name,
+-				&altera_cvp_ops, conf);
+-	if (ret)
++	mgr = fpga_mgr_create(&pdev->dev, conf->mgr_name,
++			      &altera_cvp_ops, conf);
++	if (!mgr)
++		return -ENOMEM;
++
++	pci_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret) {
++		fpga_mgr_free(mgr);
+ 		goto err_unmap;
++	}
+ 
+ 	ret = driver_create_file(&altera_cvp_driver.driver,
+ 				 &driver_attr_chkcfg);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Can't create sysfs chkcfg file\n");
+-		fpga_mgr_unregister(&pdev->dev);
++		fpga_mgr_unregister(mgr);
+ 		goto err_unmap;
+ 	}
+ 
+@@ -483,7 +492,7 @@ static void altera_cvp_remove(struct pci_dev *pdev)
+ 	u16 cmd;
+ 
+ 	driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
+-	fpga_mgr_unregister(&pdev->dev);
++	fpga_mgr_unregister(mgr);
+ 	pci_iounmap(pdev, conf->map);
+ 	pci_release_region(pdev, CVP_BAR);
+ 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
+diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
+index a7b31f9797ce..eea521774cf6 100644
+--- a/drivers/fpga/altera-pr-ip-core.c
++++ b/drivers/fpga/altera-pr-ip-core.c
+@@ -187,6 +187,8 @@ static const struct fpga_manager_ops alt_pr_ops = {
+ int alt_pr_register(struct device *dev, void __iomem *reg_base)
+ {
+ 	struct alt_pr_priv *priv;
++	struct fpga_manager *mgr;
++	int ret;
+ 	u32 val;
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+@@ -201,15 +203,27 @@ int alt_pr_register(struct device *dev, void __iomem *reg_base)
+ 		(val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
+ 		(int)(val & ALT_PR_CSR_PR_START));
+ 
+-	return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
++	mgr = fpga_mgr_create(dev, dev_name(dev), &alt_pr_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	dev_set_drvdata(dev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ EXPORT_SYMBOL_GPL(alt_pr_register);
+ 
+ int alt_pr_unregister(struct device *dev)
+ {
++	struct fpga_manager *mgr = dev_get_drvdata(dev);
++
+ 	dev_dbg(dev, "%s\n", __func__);
+ 
+-	fpga_mgr_unregister(dev);
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
+index 06d212a3d49d..24b25c626036 100644
+--- a/drivers/fpga/altera-ps-spi.c
++++ b/drivers/fpga/altera-ps-spi.c
+@@ -238,6 +238,8 @@ static int altera_ps_probe(struct spi_device *spi)
+ {
+ 	struct altera_ps_conf *conf;
+ 	const struct of_device_id *of_id;
++	struct fpga_manager *mgr;
++	int ret;
+ 
+ 	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+ 	if (!conf)
+@@ -273,13 +275,25 @@ static int altera_ps_probe(struct spi_device *spi)
+ 	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
+ 		 dev_driver_string(&spi->dev), dev_name(&spi->dev));
+ 
+-	return fpga_mgr_register(&spi->dev, conf->mgr_name,
+-				 &altera_ps_ops, conf);
++	mgr = fpga_mgr_create(&spi->dev, conf->mgr_name,
++			      &altera_ps_ops, conf);
++	if (!mgr)
++		return -ENOMEM;
++
++	spi_set_drvdata(spi, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int altera_ps_remove(struct spi_device *spi)
+ {
+-	fpga_mgr_unregister(&spi->dev);
++	struct fpga_manager *mgr = spi_get_drvdata(spi);
++
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 9939d2cbc9a6..0a5181db3e2b 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -515,17 +515,17 @@ void fpga_mgr_unlock(struct fpga_manager *mgr)
+ EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
+ 
+ /**
+- * fpga_mgr_register - register a low level fpga manager driver
++ * fpga_mgr_create - create and initialize a FPGA manager struct
+  * @dev:	fpga manager device from pdev
+  * @name:	fpga manager name
+  * @mops:	pointer to structure of fpga manager ops
+  * @priv:	fpga manager private data
+  *
+- * Return: 0 on success, negative error code otherwise.
++ * Return: pointer to struct fpga_manager or NULL
+  */
+-int fpga_mgr_register(struct device *dev, const char *name,
+-		      const struct fpga_manager_ops *mops,
+-		      void *priv)
++struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
++				     const struct fpga_manager_ops *mops,
++				     void *priv)
+ {
+ 	struct fpga_manager *mgr;
+ 	int id, ret;
+@@ -534,17 +534,17 @@ int fpga_mgr_register(struct device *dev, const char *name,
+ 	    !mops->write_init || (!mops->write && !mops->write_sg) ||
+ 	    (mops->write && mops->write_sg)) {
+ 		dev_err(dev, "Attempt to register without fpga_manager_ops\n");
+-		return -EINVAL;
++		return NULL;
+ 	}
+ 
+ 	if (!name || !strlen(name)) {
+ 		dev_err(dev, "Attempt to register with no name!\n");
+-		return -EINVAL;
++		return NULL;
+ 	}
+ 
+ 	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
+ 	if (!mgr)
+-		return -ENOMEM;
++		return NULL;
+ 
+ 	id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
+ 	if (id < 0) {
+@@ -558,25 +558,56 @@ int fpga_mgr_register(struct device *dev, const char *name,
+ 	mgr->mops = mops;
+ 	mgr->priv = priv;
+ 
+-	/*
+-	 * Initialize framework state by requesting low level driver read state
+-	 * from device.  FPGA may be in reset mode or may have been programmed
+-	 * by bootloader or EEPROM.
+-	 */
+-	mgr->state = mgr->mops->state(mgr);
+-
+ 	device_initialize(&mgr->dev);
+ 	mgr->dev.class = fpga_mgr_class;
+ 	mgr->dev.groups = mops->groups;
+ 	mgr->dev.parent = dev;
+ 	mgr->dev.of_node = dev->of_node;
+ 	mgr->dev.id = id;
+-	dev_set_drvdata(dev, mgr);
+ 
+ 	ret = dev_set_name(&mgr->dev, "fpga%d", id);
+ 	if (ret)
+ 		goto error_device;
+ 
++	return mgr;
++
++error_device:
++	ida_simple_remove(&fpga_mgr_ida, id);
++error_kfree:
++	kfree(mgr);
++
++	return NULL;
++}
++EXPORT_SYMBOL_GPL(fpga_mgr_create);
++
++/**
++ * fpga_mgr_free - deallocate a FPGA manager
++ * @mgr:	fpga manager struct created by fpga_mgr_create
++ */
++void fpga_mgr_free(struct fpga_manager *mgr)
++{
++	ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
++	kfree(mgr);
++}
++EXPORT_SYMBOL_GPL(fpga_mgr_free);
++
++/**
++ * fpga_mgr_register - register a FPGA manager
++ * @mgr:	fpga manager struct created by fpga_mgr_create
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int fpga_mgr_register(struct fpga_manager *mgr)
++{
++	int ret;
++
++	/*
++	 * Initialize framework state by requesting low level driver read state
++	 * from device.  FPGA may be in reset mode or may have been programmed
++	 * by bootloader or EEPROM.
++	 */
++	mgr->state = mgr->mops->state(mgr);
++
+ 	ret = device_add(&mgr->dev);
+ 	if (ret)
+ 		goto error_device;
+@@ -586,22 +617,18 @@ int fpga_mgr_register(struct device *dev, const char *name,
+ 	return 0;
+ 
+ error_device:
+-	ida_simple_remove(&fpga_mgr_ida, id);
+-error_kfree:
+-	kfree(mgr);
++	ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
+ 
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(fpga_mgr_register);
+ 
+ /**
+- * fpga_mgr_unregister - unregister a low level fpga manager driver
+- * @dev:	fpga manager device from pdev
++ * fpga_mgr_unregister - unregister a FPGA manager
++ * @mgr:	fpga manager struct
+  */
+-void fpga_mgr_unregister(struct device *dev)
++void fpga_mgr_unregister(struct fpga_manager *mgr)
+ {
+-	struct fpga_manager *mgr = dev_get_drvdata(dev);
+-
+ 	dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
+ 
+ 	/*
+@@ -619,8 +646,7 @@ static void fpga_mgr_dev_release(struct device *dev)
+ {
+ 	struct fpga_manager *mgr = to_fpga_manager(dev);
+ 
+-	ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
+-	kfree(mgr);
++	fpga_mgr_free(mgr);
+ }
+ 
+ static int __init fpga_mgr_class_init(void)
+diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c
+index 7fca82023062..5981c7ee7a7d 100644
+--- a/drivers/fpga/ice40-spi.c
++++ b/drivers/fpga/ice40-spi.c
+@@ -133,6 +133,7 @@ static int ice40_fpga_probe(struct spi_device *spi)
+ {
+ 	struct device *dev = &spi->dev;
+ 	struct ice40_fpga_priv *priv;
++	struct fpga_manager *mgr;
+ 	int ret;
+ 
+ 	priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+@@ -174,14 +175,26 @@ static int ice40_fpga_probe(struct spi_device *spi)
+ 		return ret;
+ 	}
+ 
+-	/* Register with the FPGA manager */
+-	return fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
+-				 &ice40_fpga_ops, priv);
++	mgr = fpga_mgr_create(dev, "Lattice iCE40 FPGA Manager",
++			      &ice40_fpga_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	spi_set_drvdata(spi, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int ice40_fpga_remove(struct spi_device *spi)
+ {
+-	fpga_mgr_unregister(&spi->dev);
++	struct fpga_manager *mgr = spi_get_drvdata(spi);
++
++	fpga_mgr_unregister(mgr);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c
+index 8e95ec9c5c9a..a582e0000c97 100644
+--- a/drivers/fpga/machxo2-spi.c
++++ b/drivers/fpga/machxo2-spi.c
+@@ -355,21 +355,33 @@ static const struct fpga_manager_ops machxo2_ops = {
+ static int machxo2_spi_probe(struct spi_device *spi)
+ {
+ 	struct device *dev = &spi->dev;
++	struct fpga_manager *mgr;
++	int ret;
+ 
+ 	if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
+ 		dev_err(dev, "Speed is too high\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	return fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
+-				 &machxo2_ops, spi);
++	mgr = fpga_mgr_create(dev, "Lattice MachXO2 SPI FPGA Manager",
++			      &machxo2_ops, spi);
++	if (!mgr)
++		return -ENOMEM;
++
++	spi_set_drvdata(spi, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int machxo2_spi_remove(struct spi_device *spi)
+ {
+-	struct device *dev = &spi->dev;
++	struct fpga_manager *mgr = spi_get_drvdata(spi);
+ 
+-	fpga_mgr_unregister(dev);
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
+index a46e343a5b72..dec3db5cdab1 100644
+--- a/drivers/fpga/socfpga-a10.c
++++ b/drivers/fpga/socfpga-a10.c
+@@ -482,6 +482,7 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct a10_fpga_priv *priv;
+ 	void __iomem *reg_base;
++	struct fpga_manager *mgr;
+ 	struct resource *res;
+ 	int ret;
+ 
+@@ -519,9 +520,16 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev)
+ 		return -EBUSY;
+ 	}
+ 
+-	ret = fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
+-				 &socfpga_a10_fpga_mgr_ops, priv);
++	mgr = fpga_mgr_create(dev, "SoCFPGA Arria10 FPGA Manager",
++			      &socfpga_a10_fpga_mgr_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
+ 	if (ret) {
++		fpga_mgr_free(mgr);
+ 		clk_disable_unprepare(priv->clk);
+ 		return ret;
+ 	}
+@@ -534,7 +542,7 @@ static int socfpga_a10_fpga_remove(struct platform_device *pdev)
+ 	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+ 	struct a10_fpga_priv *priv = mgr->priv;
+ 
+-	fpga_mgr_unregister(&pdev->dev);
++	fpga_mgr_unregister(mgr);
+ 	clk_disable_unprepare(priv->clk);
+ 
+ 	return 0;
+diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
+index b6672e66cda6..51efaf9e0e03 100644
+--- a/drivers/fpga/socfpga.c
++++ b/drivers/fpga/socfpga.c
+@@ -555,6 +555,7 @@ static int socfpga_fpga_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct socfpga_fpga_priv *priv;
++	struct fpga_manager *mgr;
+ 	struct resource *res;
+ 	int ret;
+ 
+@@ -581,13 +582,25 @@ static int socfpga_fpga_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
+-				 &socfpga_fpga_ops, priv);
++	mgr = fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
++			      &socfpga_fpga_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int socfpga_fpga_remove(struct platform_device *pdev)
+ {
+-	fpga_mgr_unregister(&pdev->dev);
++	struct fpga_manager *mgr = platform_get_drvdata(pdev);
++
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
+index f6a96b42e2ca..08efd1895b1b 100644
+--- a/drivers/fpga/ts73xx-fpga.c
++++ b/drivers/fpga/ts73xx-fpga.c
+@@ -116,7 +116,9 @@ static int ts73xx_fpga_probe(struct platform_device *pdev)
+ {
+ 	struct device *kdev = &pdev->dev;
+ 	struct ts73xx_fpga_priv *priv;
++	struct fpga_manager *mgr;
+ 	struct resource *res;
++	int ret;
+ 
+ 	priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -131,13 +133,25 @@ static int ts73xx_fpga_probe(struct platform_device *pdev)
+ 		return PTR_ERR(priv->io_base);
+ 	}
+ 
+-	return fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+-				 &ts73xx_fpga_ops, priv);
++	mgr = fpga_mgr_create(kdev, "TS-73xx FPGA Manager",
++			      &ts73xx_fpga_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int ts73xx_fpga_remove(struct platform_device *pdev)
+ {
+-	fpga_mgr_unregister(&pdev->dev);
++	struct fpga_manager *mgr = platform_get_drvdata(pdev);
++
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
+index 9b62a4c2a3df..8d1945966533 100644
+--- a/drivers/fpga/xilinx-spi.c
++++ b/drivers/fpga/xilinx-spi.c
+@@ -143,6 +143,8 @@ static const struct fpga_manager_ops xilinx_spi_ops = {
+ static int xilinx_spi_probe(struct spi_device *spi)
+ {
+ 	struct xilinx_spi_conf *conf;
++	struct fpga_manager *mgr;
++	int ret;
+ 
+ 	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+ 	if (!conf)
+@@ -165,13 +167,25 @@ static int xilinx_spi_probe(struct spi_device *spi)
+ 		return PTR_ERR(conf->done);
+ 	}
+ 
+-	return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager",
+-				 &xilinx_spi_ops, conf);
++	mgr = fpga_mgr_create(&spi->dev, "Xilinx Slave Serial FPGA Manager",
++			      &xilinx_spi_ops, conf);
++	if (!mgr)
++		return -ENOMEM;
++
++	spi_set_drvdata(spi, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
+ }
+ 
+ static int xilinx_spi_remove(struct spi_device *spi)
+ {
+-	fpga_mgr_unregister(&spi->dev);
++	struct fpga_manager *mgr = spi_get_drvdata(spi);
++
++	fpga_mgr_unregister(mgr);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
+index 70b15b303471..3110e00121ca 100644
+--- a/drivers/fpga/zynq-fpga.c
++++ b/drivers/fpga/zynq-fpga.c
+@@ -558,6 +558,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct zynq_fpga_priv *priv;
++	struct fpga_manager *mgr;
+ 	struct resource *res;
+ 	int err;
+ 
+@@ -613,10 +614,17 @@ static int zynq_fpga_probe(struct platform_device *pdev)
+ 
+ 	clk_disable(priv->clk);
+ 
+-	err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
+-				&zynq_fpga_ops, priv);
++	mgr = fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
++			      &zynq_fpga_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	err = fpga_mgr_register(mgr);
+ 	if (err) {
+ 		dev_err(dev, "unable to register FPGA manager\n");
++		fpga_mgr_free(mgr);
+ 		clk_unprepare(priv->clk);
+ 		return err;
+ 	}
+@@ -632,7 +640,7 @@ static int zynq_fpga_remove(struct platform_device *pdev)
+ 	mgr = platform_get_drvdata(pdev);
+ 	priv = mgr->priv;
+ 
+-	fpga_mgr_unregister(&pdev->dev);
++	fpga_mgr_unregister(mgr);
+ 
+ 	clk_unprepare(priv->clk);
+ 
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index 3c6de23aabdf..1266c1108e70 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -170,9 +170,11 @@ struct fpga_manager *fpga_mgr_get(struct device *dev);
+ 
+ void fpga_mgr_put(struct fpga_manager *mgr);
+ 
+-int fpga_mgr_register(struct device *dev, const char *name,
+-		      const struct fpga_manager_ops *mops, void *priv);
+-
+-void fpga_mgr_unregister(struct device *dev);
++struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
++				     const struct fpga_manager_ops *mops,
++				     void *priv);
++void fpga_mgr_free(struct fpga_manager *mgr);
++int fpga_mgr_register(struct fpga_manager *mgr);
++void fpga_mgr_unregister(struct fpga_manager *mgr);
+ 
+ #endif /*_LINUX_FPGA_MGR_H */
+-- 
+2.19.0
+
diff --git a/patches/1688-fpga-bridge-change-api-don-t-use-drvdata.patch b/patches/1688-fpga-bridge-change-api-don-t-use-drvdata.patch
new file mode 100644
index 00000000000000..d358f5203b92f2
--- /dev/null
+++ b/patches/1688-fpga-bridge-change-api-don-t-use-drvdata.patch
@@ -0,0 +1,391 @@
+From 49b04199192128fa119302b0139de16880460c7f Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:56 -0500
+Subject: [PATCH 1688/1795] fpga: bridge: change api, don't use drvdata
+
+Change fpga_bridge_register to not set drvdata.  This is to support
+the case where a PCIe device can have more than one bridge.
+
+Add API functions to create/free the fpga bridge struct. Change
+fpga_bridge_register/unregister to take FPGA bridge struct as
+the only parameter.
+
+  struct fpga_bridge
+  *fpga_bridge_create(struct device *dev, const char *name,
+                      const struct fpga_bridge_ops *br_ops,
+                      void *priv);
+  void fpga_bridge_free(struct fpga_bridge *br);
+  int fpga_bridge_register(struct fpga_bridge *br);
+  void fpga_bridge_unregister(struct fpga_bridge *br);
+
+Update the drivers that call fpga_bridge_register with the new API.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Reported-by: Jiuyue Ma <majiuyue@huawei.com>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 371cd1b1fdabb33603340559049e46dfeae45b1e)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/altera-fpga2sdram.c    | 21 ++++++---
+ drivers/fpga/altera-freeze-bridge.c | 22 +++++++--
+ drivers/fpga/altera-hps2fpga.c      | 24 +++++++---
+ drivers/fpga/fpga-bridge.c          | 70 +++++++++++++++++++----------
+ drivers/fpga/xilinx-pr-decoupler.c  | 22 ++++++---
+ include/linux/fpga/fpga-bridge.h    |  9 ++--
+ 6 files changed, 123 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c
+index d4eeb74388da..5a29ab6e3b28 100644
+--- a/drivers/fpga/altera-fpga2sdram.c
++++ b/drivers/fpga/altera-fpga2sdram.c
+@@ -106,6 +106,7 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct alt_fpga2sdram_data *priv;
++	struct fpga_bridge *br;
+ 	u32 enable;
+ 	struct regmap *sysmgr;
+ 	int ret = 0;
+@@ -131,10 +132,18 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ 	/* Get f2s bridge configuration saved in handoff register */
+ 	regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask);
+ 
+-	ret = fpga_bridge_register(dev, F2S_BRIDGE_NAME,
+-				   &altera_fpga2sdram_br_ops, priv);
+-	if (ret)
++	br = fpga_bridge_create(dev, F2S_BRIDGE_NAME,
++				&altera_fpga2sdram_br_ops, priv);
++	if (!br)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, br);
++
++	ret = fpga_bridge_register(br);
++	if (ret) {
++		fpga_bridge_free(br);
+ 		return ret;
++	}
+ 
+ 	dev_info(dev, "driver initialized with handoff %08x\n", priv->mask);
+ 
+@@ -146,7 +155,7 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ 				 (enable ? "enabling" : "disabling"));
+ 			ret = _alt_fpga2sdram_enable_set(priv, enable);
+ 			if (ret) {
+-				fpga_bridge_unregister(&pdev->dev);
++				fpga_bridge_unregister(br);
+ 				return ret;
+ 			}
+ 		}
+@@ -157,7 +166,9 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ 
+ static int alt_fpga_bridge_remove(struct platform_device *pdev)
+ {
+-	fpga_bridge_unregister(&pdev->dev);
++	struct fpga_bridge *br = platform_get_drvdata(pdev);
++
++	fpga_bridge_unregister(br);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera-freeze-bridge.c
+index 6159cfcf78a2..fa4b693cf4be 100644
+--- a/drivers/fpga/altera-freeze-bridge.c
++++ b/drivers/fpga/altera-freeze-bridge.c
+@@ -221,8 +221,10 @@ static int altera_freeze_br_probe(struct platform_device *pdev)
+ 	struct device_node *np = pdev->dev.of_node;
+ 	void __iomem *base_addr;
+ 	struct altera_freeze_br_data *priv;
++	struct fpga_bridge *br;
+ 	struct resource *res;
+ 	u32 status, revision;
++	int ret;
+ 
+ 	if (!np)
+ 		return -ENODEV;
+@@ -254,13 +256,27 @@ static int altera_freeze_br_probe(struct platform_device *pdev)
+ 
+ 	priv->base_addr = base_addr;
+ 
+-	return fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
+-				    &altera_freeze_br_br_ops, priv);
++	br = fpga_bridge_create(dev, FREEZE_BRIDGE_NAME,
++				&altera_freeze_br_br_ops, priv);
++	if (!br)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, br);
++
++	ret = fpga_bridge_register(br);
++	if (ret) {
++		fpga_bridge_free(br);
++		return ret;
++	}
++
++	return 0;
+ }
+ 
+ static int altera_freeze_br_remove(struct platform_device *pdev)
+ {
+-	fpga_bridge_unregister(&pdev->dev);
++	struct fpga_bridge *br = platform_get_drvdata(pdev);
++
++	fpga_bridge_unregister(br);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera-hps2fpga.c
+index 406d2f10741f..e4d39f0a7572 100644
+--- a/drivers/fpga/altera-hps2fpga.c
++++ b/drivers/fpga/altera-hps2fpga.c
+@@ -139,6 +139,7 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct altera_hps2fpga_data *priv;
+ 	const struct of_device_id *of_id;
++	struct fpga_bridge *br;
+ 	u32 enable;
+ 	int ret;
+ 
+@@ -190,11 +191,24 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
+-	ret = fpga_bridge_register(dev, priv->name, &altera_hps2fpga_br_ops,
+-				   priv);
+-err:
++	br = fpga_bridge_create(dev, priv->name, &altera_hps2fpga_br_ops, priv);
++	if (!br) {
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	platform_set_drvdata(pdev, br);
++
++	ret = fpga_bridge_register(br);
+ 	if (ret)
+-		clk_disable_unprepare(priv->clk);
++		goto err_free;
++
++	return 0;
++
++err_free:
++	fpga_bridge_free(br);
++err:
++	clk_disable_unprepare(priv->clk);
+ 
+ 	return ret;
+ }
+@@ -204,7 +218,7 @@ static int alt_fpga_bridge_remove(struct platform_device *pdev)
+ 	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
+ 	struct altera_hps2fpga_data *priv = bridge->priv;
+ 
+-	fpga_bridge_unregister(&pdev->dev);
++	fpga_bridge_unregister(bridge);
+ 
+ 	clk_disable_unprepare(priv->clk);
+ 
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 31bd2c59c305..2db1573507eb 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -328,28 +328,29 @@ static struct attribute *fpga_bridge_attrs[] = {
+ ATTRIBUTE_GROUPS(fpga_bridge);
+ 
+ /**
+- * fpga_bridge_register - register a fpga bridge driver
++ * fpga_bridge_create - create and initialize a struct fpga_bridge
+  * @dev:	FPGA bridge device from pdev
+  * @name:	FPGA bridge name
+  * @br_ops:	pointer to structure of fpga bridge ops
+  * @priv:	FPGA bridge private data
+  *
+- * Return: 0 for success, error code otherwise.
++ * Return: struct fpga_bridge or NULL
+  */
+-int fpga_bridge_register(struct device *dev, const char *name,
+-			 const struct fpga_bridge_ops *br_ops, void *priv)
++struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name,
++				       const struct fpga_bridge_ops *br_ops,
++				       void *priv)
+ {
+ 	struct fpga_bridge *bridge;
+ 	int id, ret = 0;
+ 
+ 	if (!name || !strlen(name)) {
+ 		dev_err(dev, "Attempt to register with no name!\n");
+-		return -EINVAL;
++		return NULL;
+ 	}
+ 
+ 	bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
+ 	if (!bridge)
+-		return -ENOMEM;
++		return NULL;
+ 
+ 	id = ida_simple_get(&fpga_bridge_ida, 0, 0, GFP_KERNEL);
+ 	if (id < 0) {
+@@ -370,40 +371,62 @@ int fpga_bridge_register(struct device *dev, const char *name,
+ 	bridge->dev.parent = dev;
+ 	bridge->dev.of_node = dev->of_node;
+ 	bridge->dev.id = id;
+-	dev_set_drvdata(dev, bridge);
+ 
+ 	ret = dev_set_name(&bridge->dev, "br%d", id);
+ 	if (ret)
+ 		goto error_device;
+ 
+-	ret = device_add(&bridge->dev);
+-	if (ret)
+-		goto error_device;
+-
+-	of_platform_populate(dev->of_node, NULL, NULL, dev);
+-
+-	dev_info(bridge->dev.parent, "fpga bridge [%s] registered\n",
+-		 bridge->name);
+-
+-	return 0;
++	return bridge;
+ 
+ error_device:
+ 	ida_simple_remove(&fpga_bridge_ida, id);
+ error_kfree:
+ 	kfree(bridge);
+ 
+-	return ret;
++	return NULL;
++}
++EXPORT_SYMBOL_GPL(fpga_bridge_create);
++
++/**
++ * fpga_bridge_free - free a fpga bridge and its id
++ * @bridge:	FPGA bridge struct created by fpga_bridge_create
++ */
++void fpga_bridge_free(struct fpga_bridge *bridge)
++{
++	ida_simple_remove(&fpga_bridge_ida, bridge->dev.id);
++	kfree(bridge);
++}
++EXPORT_SYMBOL_GPL(fpga_bridge_free);
++
++/**
++ * fpga_bridge_register - register a fpga bridge
++ * @bridge:	FPGA bridge struct created by fpga_bridge_create
++ *
++ * Return: 0 for success, error code otherwise.
++ */
++int fpga_bridge_register(struct fpga_bridge *bridge)
++{
++	struct device *dev = &bridge->dev;
++	int ret;
++
++	ret = device_add(dev);
++	if (ret)
++		return ret;
++
++	of_platform_populate(dev->of_node, NULL, NULL, dev);
++
++	dev_info(dev->parent, "fpga bridge [%s] registered\n", bridge->name);
++
++	return 0;
+ }
+ EXPORT_SYMBOL_GPL(fpga_bridge_register);
+ 
+ /**
+  * fpga_bridge_unregister - unregister a fpga bridge driver
+- * @dev: FPGA bridge device from pdev
++ * @bridge:	FPGA bridge struct created by fpga_bridge_create
+  */
+-void fpga_bridge_unregister(struct device *dev)
++void fpga_bridge_unregister(struct fpga_bridge *bridge)
+ {
+-	struct fpga_bridge *bridge = dev_get_drvdata(dev);
+-
+ 	/*
+ 	 * If the low level driver provides a method for putting bridge into
+ 	 * a desired state upon unregister, do it.
+@@ -419,8 +442,7 @@ static void fpga_bridge_dev_release(struct device *dev)
+ {
+ 	struct fpga_bridge *bridge = to_fpga_bridge(dev);
+ 
+-	ida_simple_remove(&fpga_bridge_ida, bridge->dev.id);
+-	kfree(bridge);
++	fpga_bridge_free(bridge);
+ }
+ 
+ static int __init fpga_bridge_dev_init(void)
+diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
+index e359930bebc8..bd059c8c851f 100644
+--- a/drivers/fpga/xilinx-pr-decoupler.c
++++ b/drivers/fpga/xilinx-pr-decoupler.c
+@@ -94,6 +94,7 @@ MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
+ static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
+ {
+ 	struct xlnx_pr_decoupler_data *priv;
++	struct fpga_bridge *br;
+ 	int err;
+ 	struct resource *res;
+ 
+@@ -120,16 +121,27 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
+ 
+ 	clk_disable(priv->clk);
+ 
+-	err = fpga_bridge_register(&pdev->dev, "Xilinx PR Decoupler",
+-				   &xlnx_pr_decoupler_br_ops, priv);
++	br = fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
++				&xlnx_pr_decoupler_br_ops, priv);
++	if (!br) {
++		err = -ENOMEM;
++		goto err_clk;
++	}
++
++	platform_set_drvdata(pdev, br);
+ 
++	err = fpga_bridge_register(br);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
+-		clk_unprepare(priv->clk);
+-		return err;
++		goto err_clk;
+ 	}
+ 
+ 	return 0;
++
++err_clk:
++	clk_unprepare(priv->clk);
++
++	return err;
+ }
+ 
+ static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
+@@ -137,7 +149,7 @@ static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
+ 	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
+ 	struct xlnx_pr_decoupler_data *p = bridge->priv;
+ 
+-	fpga_bridge_unregister(&pdev->dev);
++	fpga_bridge_unregister(bridge);
+ 
+ 	clk_unprepare(p->clk);
+ 
+diff --git a/include/linux/fpga/fpga-bridge.h b/include/linux/fpga/fpga-bridge.h
+index 3694821a6d2d..ce550fcf6360 100644
+--- a/include/linux/fpga/fpga-bridge.h
++++ b/include/linux/fpga/fpga-bridge.h
+@@ -62,8 +62,11 @@ int of_fpga_bridge_get_to_list(struct device_node *np,
+ 			       struct fpga_image_info *info,
+ 			       struct list_head *bridge_list);
+ 
+-int fpga_bridge_register(struct device *dev, const char *name,
+-			 const struct fpga_bridge_ops *br_ops, void *priv);
+-void fpga_bridge_unregister(struct device *dev);
++struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name,
++				       const struct fpga_bridge_ops *br_ops,
++				       void *priv);
++void fpga_bridge_free(struct fpga_bridge *br);
++int fpga_bridge_register(struct fpga_bridge *br);
++void fpga_bridge_unregister(struct fpga_bridge *br);
+ 
+ #endif /* _LINUX_FPGA_BRIDGE_H */
+-- 
+2.19.0
+
diff --git a/patches/1689-fpga-region-change-api-add-fpga_region_create-free.patch b/patches/1689-fpga-region-change-api-add-fpga_region_create-free.patch
new file mode 100644
index 00000000000000..8f0cb6a15fef6b
--- /dev/null
+++ b/patches/1689-fpga-region-change-api-add-fpga_region_create-free.patch
@@ -0,0 +1,235 @@
+From 4405f8a50fd15b0022c920fee635ddb47c1664ec Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:57 -0500
+Subject: [PATCH 1689/1795] fpga: region: change api, add
+ fpga_region_create/free
+
+Add fpga_region_create/free API functions.
+
+Change fpga_region_register to take FPGA region struct as the only
+parameter.  Change fpga_region_unregister to return void.
+
+  struct fpga_region *fpga_region_create(struct device *dev,
+                        struct fpga_manager *mgr,
+                        int (*get_bridges)(struct fpga_region *));
+  void fpga_region_free(struct fpga_region *region);
+  int fpga_region_register(struct fpga_region *region);
+  void fpga_region_unregister(struct fpga_region *region);
+
+Remove groups storage from struct fpga_region, it's not
+needed.  Callers can just "region->dev.groups = groups;"
+after calling fpga_region_create.
+
+Update the drivers that call fpga_region_register with the new API.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 9f368977b4589e2fe0b9d3a4cbaf11ff6a58ecf5)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/fpga/fpga-region.txt |  3 +-
+ drivers/fpga/fpga-region.c         | 68 ++++++++++++++++++++++++------
+ drivers/fpga/of-fpga-region.c      | 13 +++---
+ include/linux/fpga/fpga-region.h   | 11 +++--
+ 4 files changed, 68 insertions(+), 27 deletions(-)
+
+diff --git a/Documentation/fpga/fpga-region.txt b/Documentation/fpga/fpga-region.txt
+index 139a02ba1ff6..d38fa3b4154a 100644
+--- a/Documentation/fpga/fpga-region.txt
++++ b/Documentation/fpga/fpga-region.txt
+@@ -42,8 +42,7 @@ The FPGA region API
+ To register or unregister a region:
+ -----------------------------------
+ 
+-	int fpga_region_register(struct device *dev,
+-				 struct fpga_region *region);
++	int fpga_region_register(struct fpga_region *region);
+ 	int fpga_region_unregister(struct fpga_region *region);
+ 
+ An example of usage can be seen in the probe function of [3]
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index f634a8ed5e2c..b3ba3e40c44b 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -167,18 +167,36 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_program_fpga);
+ 
+-int fpga_region_register(struct device *dev, struct fpga_region *region)
++/**
++ * fpga_region_create - alloc and init a struct fpga_region
++ * @dev: device parent
++ * @mgr: manager that programs this region
++ * @get_bridges: optional function to get bridges to a list
++ *
++ * Return: struct fpga_region or NULL
++ */
++struct fpga_region
++*fpga_region_create(struct device *dev,
++		    struct fpga_manager *mgr,
++		    int (*get_bridges)(struct fpga_region *))
+ {
++	struct fpga_region *region;
+ 	int id, ret = 0;
+ 
++	region = kzalloc(sizeof(*region), GFP_KERNEL);
++	if (!region)
++		return NULL;
++
+ 	id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL);
+ 	if (id < 0)
+-		return id;
++		goto err_free;
+ 
++	region->mgr = mgr;
++	region->get_bridges = get_bridges;
+ 	mutex_init(&region->mutex);
+ 	INIT_LIST_HEAD(&region->bridge_list);
++
+ 	device_initialize(&region->dev);
+-	region->dev.groups = region->groups;
+ 	region->dev.class = fpga_region_class;
+ 	region->dev.parent = dev;
+ 	region->dev.of_node = dev->of_node;
+@@ -188,23 +206,47 @@ int fpga_region_register(struct device *dev, struct fpga_region *region)
+ 	if (ret)
+ 		goto err_remove;
+ 
+-	ret = device_add(&region->dev);
+-	if (ret)
+-		goto err_remove;
+-
+-	return 0;
++	return region;
+ 
+ err_remove:
+ 	ida_simple_remove(&fpga_region_ida, id);
+-	return ret;
++err_free:
++	kfree(region);
++
++	return NULL;
++}
++EXPORT_SYMBOL_GPL(fpga_region_create);
++
++/**
++ * fpga_region_free - free a struct fpga_region
++ * @region: FPGA region created by fpga_region_create
++ */
++void fpga_region_free(struct fpga_region *region)
++{
++	ida_simple_remove(&fpga_region_ida, region->dev.id);
++	kfree(region);
++}
++EXPORT_SYMBOL_GPL(fpga_region_free);
++
++/*
++ * fpga_region_register - register a FPGA region
++ * @region: FPGA region created by fpga_region_create
++ * Return: 0 or -errno
++ */
++int fpga_region_register(struct fpga_region *region)
++{
++	return device_add(&region->dev);
++
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_register);
+ 
+-int fpga_region_unregister(struct fpga_region *region)
++/*
++ * fpga_region_unregister - unregister a FPGA region
++ * @region: FPGA region
++ */
++void fpga_region_unregister(struct fpga_region *region)
+ {
+ 	device_unregister(&region->dev);
+-
+-	return 0;
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_unregister);
+ 
+@@ -212,7 +254,7 @@ static void fpga_region_dev_release(struct device *dev)
+ {
+ 	struct fpga_region *region = to_fpga_region(dev);
+ 
+-	ida_simple_remove(&fpga_region_ida, region->dev.id);
++	fpga_region_free(region);
+ }
+ 
+ /**
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+index 35e7e8c4a0cb..9d681a1c5738 100644
+--- a/drivers/fpga/of-fpga-region.c
++++ b/drivers/fpga/of-fpga-region.c
+@@ -422,20 +422,15 @@ static int of_fpga_region_probe(struct platform_device *pdev)
+ 	if (IS_ERR(mgr))
+ 		return -EPROBE_DEFER;
+ 
+-	region = devm_kzalloc(dev, sizeof(*region), GFP_KERNEL);
++	region = fpga_region_create(dev, mgr, of_fpga_region_get_bridges);
+ 	if (!region) {
+ 		ret = -ENOMEM;
+ 		goto eprobe_mgr_put;
+ 	}
+ 
+-	region->mgr = mgr;
+-
+-	/* Specify how to get bridges for this type of region. */
+-	region->get_bridges = of_fpga_region_get_bridges;
+-
+-	ret = fpga_region_register(dev, region);
++	ret = fpga_region_register(region);
+ 	if (ret)
+-		goto eprobe_mgr_put;
++		goto eprobe_free;
+ 
+ 	of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
+ 	dev_set_drvdata(dev, region);
+@@ -444,6 +439,8 @@ static int of_fpga_region_probe(struct platform_device *pdev)
+ 
+ 	return 0;
+ 
++eprobe_free:
++	fpga_region_free(region);
+ eprobe_mgr_put:
+ 	fpga_mgr_put(mgr);
+ 	return ret;
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index b6520318ab9c..f2e215bd1330 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -14,7 +14,6 @@
+  * @info: FPGA image info
+  * @priv: private data
+  * @get_bridges: optional function to get bridges to a list
+- * @groups: optional attribute groups.
+  */
+ struct fpga_region {
+ 	struct device dev;
+@@ -24,7 +23,6 @@ struct fpga_region {
+ 	struct fpga_image_info *info;
+ 	void *priv;
+ 	int (*get_bridges)(struct fpga_region *region);
+-	const struct attribute_group **groups;
+ };
+ 
+ #define to_fpga_region(d) container_of(d, struct fpga_region, dev)
+@@ -34,7 +32,12 @@ struct fpga_region *fpga_region_class_find(
+ 	int (*match)(struct device *, const void *));
+ 
+ int fpga_region_program_fpga(struct fpga_region *region);
+-int fpga_region_register(struct device *dev, struct fpga_region *region);
+-int fpga_region_unregister(struct fpga_region *region);
++
++struct fpga_region
++*fpga_region_create(struct device *dev, struct fpga_manager *mgr,
++		    int (*get_bridges)(struct fpga_region *));
++void fpga_region_free(struct fpga_region *region);
++int fpga_region_register(struct fpga_region *region);
++void fpga_region_unregister(struct fpga_region *region);
+ 
+ #endif /* _FPGA_REGION_H */
+-- 
+2.19.0
+
diff --git a/patches/1690-fpga-use-SPDX.patch b/patches/1690-fpga-use-SPDX.patch
new file mode 100644
index 00000000000000..e382b48bb424c1
--- /dev/null
+++ b/patches/1690-fpga-use-SPDX.patch
@@ -0,0 +1,392 @@
+From 12b11e9cd4fac2f26df410e1c6766368422de277 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:58 -0500
+Subject: [PATCH 1690/1795] fpga: use SPDX
+
+Replace GPLv2 boilerplate with SPDX in FPGA code that came from me or
+from Altera.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 473f01f7e4b9fc53d44c446ad22b39070c65393f)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/altera-fpga2sdram.c       | 13 +------------
+ drivers/fpga/altera-freeze-bridge.c    | 13 +------------
+ drivers/fpga/altera-hps2fpga.c         | 13 +------------
+ drivers/fpga/altera-pr-ip-core-plat.c  | 13 +------------
+ drivers/fpga/altera-pr-ip-core.c       | 13 +------------
+ drivers/fpga/fpga-bridge.c             | 13 +------------
+ drivers/fpga/fpga-mgr.c                | 13 +------------
+ drivers/fpga/fpga-region.c             | 14 +-------------
+ drivers/fpga/of-fpga-region.c          | 14 +-------------
+ drivers/fpga/socfpga-a10.c             | 14 +-------------
+ drivers/fpga/socfpga.c                 | 13 +------------
+ include/linux/fpga/altera-pr-ip-core.h | 13 +------------
+ include/linux/fpga/fpga-mgr.h          | 13 +------------
+ include/linux/fpga/fpga-region.h       |  2 ++
+ 14 files changed, 15 insertions(+), 159 deletions(-)
+
+diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c
+index 5a29ab6e3b28..23660ccd634b 100644
+--- a/drivers/fpga/altera-fpga2sdram.c
++++ b/drivers/fpga/altera-fpga2sdram.c
+@@ -1,19 +1,8 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ /*
+diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera-freeze-bridge.c
+index fa4b693cf4be..ffd586c48ecf 100644
+--- a/drivers/fpga/altera-freeze-bridge.c
++++ b/drivers/fpga/altera-freeze-bridge.c
+@@ -1,19 +1,8 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Freeze Bridge Controller
+  *
+  *  Copyright (C) 2016 Altera Corporation. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/delay.h>
+ #include <linux/io.h>
+diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera-hps2fpga.c
+index e4d39f0a7572..a974d3f60321 100644
+--- a/drivers/fpga/altera-hps2fpga.c
++++ b/drivers/fpga/altera-hps2fpga.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
+  *
+@@ -6,18 +7,6 @@
+  * Includes this patch from the mailing list:
+  *   fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
+  *   Signed-off-by: Anatolij Gustschin <agust@denx.de>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ /*
+diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c
+index 8fb36b8b4648..b293d83143f1 100644
+--- a/drivers/fpga/altera-pr-ip-core-plat.c
++++ b/drivers/fpga/altera-pr-ip-core-plat.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for Altera Partial Reconfiguration IP Core
+  *
+@@ -5,18 +6,6 @@
+  *
+  * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+  *  by Alan Tull <atull@opensource.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/fpga/altera-pr-ip-core.h>
+ #include <linux/module.h>
+diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
+index eea521774cf6..65e0b6a2c031 100644
+--- a/drivers/fpga/altera-pr-ip-core.c
++++ b/drivers/fpga/altera-pr-ip-core.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Driver for Altera Partial Reconfiguration IP Core
+  *
+@@ -5,18 +6,6 @@
+  *
+  * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+  *  by Alan Tull <atull@opensource.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/delay.h>
+ #include <linux/fpga/altera-pr-ip-core.h>
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 2db1573507eb..164eb552da45 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -1,20 +1,9 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Bridge Framework Driver
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
+  *  Copyright (C) 2017 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/fpga/fpga-bridge.h>
+ #include <linux/idr.h>
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 0a5181db3e2b..151ac364be80 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Manager Core
+  *
+@@ -6,18 +7,6 @@
+  *
+  * With code from the mailing list:
+  * Copyright (C) 2013 Xilinx, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/firmware.h>
+ #include <linux/fpga/fpga-mgr.h>
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index b3ba3e40c44b..0878f62dd1fc 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -1,22 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Region - Device Tree support for FPGA programming under Linux
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation
+  *  Copyright (C) 2017 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-
+ #include <linux/fpga/fpga-bridge.h>
+ #include <linux/fpga/fpga-mgr.h>
+ #include <linux/fpga/fpga-region.h>
+diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
+index 9d681a1c5738..35fabb8083fb 100644
+--- a/drivers/fpga/of-fpga-region.c
++++ b/drivers/fpga/of-fpga-region.c
+@@ -1,22 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Region - Device Tree support for FPGA programming under Linux
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation
+  *  Copyright (C) 2017 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-
+ #include <linux/fpga/fpga-bridge.h>
+ #include <linux/fpga/fpga-mgr.h>
+ #include <linux/fpga/fpga-region.h>
+diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
+index dec3db5cdab1..be30c48eb6e4 100644
+--- a/drivers/fpga/socfpga-a10.c
++++ b/drivers/fpga/socfpga-a10.c
+@@ -1,21 +1,9 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Manager Driver for Altera Arria10 SoCFPGA
+  *
+  * Copyright (C) 2015-2016 Altera Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-
+ #include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
+diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
+index 51efaf9e0e03..959d71f26896 100644
+--- a/drivers/fpga/socfpga.c
++++ b/drivers/fpga/socfpga.c
+@@ -1,19 +1,8 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * FPGA Manager Driver for Altera SOCFPGA
+  *
+  *  Copyright (C) 2013-2015 Altera Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #include <linux/completion.h>
+ #include <linux/delay.h>
+diff --git a/include/linux/fpga/altera-pr-ip-core.h b/include/linux/fpga/altera-pr-ip-core.h
+index 3810a9033f49..7d4664730d60 100644
+--- a/include/linux/fpga/altera-pr-ip-core.h
++++ b/include/linux/fpga/altera-pr-ip-core.h
+@@ -1,3 +1,4 @@
++/* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * Driver for Altera Partial Reconfiguration IP Core
+  *
+@@ -5,18 +6,6 @@
+  *
+  * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+  *  by Alan Tull <atull@opensource.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ 
+ #ifndef _ALT_PR_IP_CORE_H
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index 1266c1108e70..eec7c2478b0d 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -1,20 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * FPGA Framework
+  *
+  *  Copyright (C) 2013-2016 Altera Corporation
+  *  Copyright (C) 2017 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+ #ifndef _LINUX_FPGA_MGR_H
+ #define _LINUX_FPGA_MGR_H
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index f2e215bd1330..d7071cddd727 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -1,3 +1,5 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
+ #ifndef _FPGA_REGION_H
+ #define _FPGA_REGION_H
+ 
+-- 
+2.19.0
+
diff --git a/patches/1691-fpga-mgr-kernel-doc-fixes.patch b/patches/1691-fpga-mgr-kernel-doc-fixes.patch
new file mode 100644
index 00000000000000..3dff23c69002b1
--- /dev/null
+++ b/patches/1691-fpga-mgr-kernel-doc-fixes.patch
@@ -0,0 +1,127 @@
+From 0c65a24953b622ac2f5f637cff13b5a811300c4e Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:49:59 -0500
+Subject: [PATCH 1691/1795] fpga: mgr: kernel-doc fixes
+
+Clean up the kernel-doc documentation in fpga-mgr.c and fix the
+following warnings when documentation is built:
+
+./drivers/fpga/fpga-mgr.c:252: warning: Function parameter or member
+'info' not described in 'fpga_mgr_buf_load'
+
+./drivers/fpga/fpga-mgr.c:252: warning: Excess function parameter
+'flags' description in 'fpga_mgr_buf_load'
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ff9da89c22379fc1b2d45cfc4430fa9168189080)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-mgr.c | 38 +++++++++++++++++++++++++++++---------
+ 1 file changed, 29 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 151ac364be80..5fffeeffed5f 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -21,6 +21,12 @@
+ static DEFINE_IDA(fpga_mgr_ida);
+ static struct class *fpga_mgr_class;
+ 
++/**
++ * fpga_image_info_alloc - Allocate a FPGA image info struct
++ * @dev: owning device
++ *
++ * Return: struct fpga_image_info or NULL
++ */
+ struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
+ {
+ 	struct fpga_image_info *info;
+@@ -39,6 +45,10 @@ struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
+ 
++/**
++ * fpga_image_info_free - Free a FPGA image info struct
++ * @info: FPGA image info struct to free
++ */
+ void fpga_image_info_free(struct fpga_image_info *info)
+ {
+ 	struct device *dev;
+@@ -223,7 +233,7 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
+ /**
+  * fpga_mgr_buf_load - load fpga from image in buffer
+  * @mgr:	fpga manager
+- * @flags:	flags setting fpga confuration modes
++ * @info:	fpga image info
+  * @buf:	buffer contain fpga image
+  * @count:	byte count of buf
+  *
+@@ -332,6 +342,16 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+ 	return ret;
+ }
+ 
++/**
++ * fpga_mgr_load - load FPGA from scatter/gather table, buffer, or firmware
++ * @mgr:	fpga manager
++ * @info:	fpga image information.
++ *
++ * Load the FPGA from an image which is indicated in @info.  If successful, the
++ * FPGA ends up in operating mode.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
+ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
+ {
+ 	if (info->sgt)
+@@ -418,11 +438,9 @@ static int fpga_mgr_dev_match(struct device *dev, const void *data)
+ }
+ 
+ /**
+- * fpga_mgr_get - get a reference to a fpga mgr
++ * fpga_mgr_get - Given a device, get a reference to a fpga mgr.
+  * @dev:	parent device that fpga mgr was registered with
+  *
+- * Given a device, get a reference to a fpga mgr.
+- *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+ struct fpga_manager *fpga_mgr_get(struct device *dev)
+@@ -442,10 +460,9 @@ static int fpga_mgr_of_node_match(struct device *dev, const void *data)
+ }
+ 
+ /**
+- * of_fpga_mgr_get - get a reference to a fpga mgr
+- * @node:	device node
++ * of_fpga_mgr_get - Given a device node, get a reference to a fpga mgr.
+  *
+- * Given a device node, get a reference to a fpga mgr.
++ * @node:	device node
+  *
+  * Return: fpga manager struct or IS_ERR() condition containing error code.
+  */
+@@ -478,7 +495,10 @@ EXPORT_SYMBOL_GPL(fpga_mgr_put);
+  * @mgr:	fpga manager
+  *
+  * Given a pointer to FPGA Manager (from fpga_mgr_get() or
+- * of_fpga_mgr_put()) attempt to get the mutex.
++ * of_fpga_mgr_put()) attempt to get the mutex. The user should call
++ * fpga_mgr_lock() and verify that it returns 0 before attempting to
++ * program the FPGA.  Likewise, the user should call fpga_mgr_unlock
++ * when done programming the FPGA.
+  *
+  * Return: 0 for success or -EBUSY
+  */
+@@ -494,7 +514,7 @@ int fpga_mgr_lock(struct fpga_manager *mgr)
+ EXPORT_SYMBOL_GPL(fpga_mgr_lock);
+ 
+ /**
+- * fpga_mgr_unlock - Unlock FPGA manager
++ * fpga_mgr_unlock - Unlock FPGA manager after done programming
+  * @mgr:	fpga manager
+  */
+ void fpga_mgr_unlock(struct fpga_manager *mgr)
+-- 
+2.19.0
+
diff --git a/patches/1692-fpga-bridge-kernel-doc-fixes.patch b/patches/1692-fpga-bridge-kernel-doc-fixes.patch
new file mode 100644
index 00000000000000..db0d9c432663cb
--- /dev/null
+++ b/patches/1692-fpga-bridge-kernel-doc-fixes.patch
@@ -0,0 +1,36 @@
+From 97089e51d8b1a258aa18b3aad6f88e2863a43bf6 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:00 -0500
+Subject: [PATCH 1692/1795] fpga: bridge: kernel-doc fixes
+
+Fix the following warnings when documentation is built:
+
+./drivers/fpga/fpga-bridge.c:143: warning: Function parameter or
+member 'info' not described in 'fpga_bridge_get'
+
+./drivers/fpga/fpga-bridge.c:1: warning: no structured comments found
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 060ac5c8fa7bae6a7a63953ecb48f6a42257ae64)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-bridge.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 164eb552da45..4b207a75b696 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -121,6 +121,7 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data)
+ /**
+  * fpga_bridge_get - get an exclusive reference to a fpga bridge
+  * @dev:	parent device that fpga bridge was registered with
++ * @info:	fpga manager info
+  *
+  * Given a device, get an exclusive reference to a fpga bridge.
+  *
+-- 
+2.19.0
+
diff --git a/patches/1693-fpga-region-kernel-doc-fixes.patch b/patches/1693-fpga-region-kernel-doc-fixes.patch
new file mode 100644
index 00000000000000..96bbb2e08502ef
--- /dev/null
+++ b/patches/1693-fpga-region-kernel-doc-fixes.patch
@@ -0,0 +1,59 @@
+From a6baf4aca312689c4ea97c65e4f05654c20f2e21 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:01 -0500
+Subject: [PATCH 1693/1795] fpga: region: kernel-doc fixes
+
+Fix formatting and some cleanup for the kernel-doc documentation in
+fpga-region.c
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 917a4304fe48c12d346f038c7d64da3f51bce53a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-region.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 0878f62dd1fc..112fa3a0f977 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -81,13 +81,16 @@ static void fpga_region_put(struct fpga_region *region)
+ 
+ /**
+  * fpga_region_program_fpga - program FPGA
++ *
+  * @region: FPGA region
++ *
+  * Program an FPGA using fpga image info (region->info).
+  * If the region has a get_bridges function, the exclusive reference for the
+  * bridges will be held if programming succeeds.  This is intended to prevent
+  * reprogramming the region until the caller considers it safe to do so.
+  * The caller will need to call fpga_bridges_put() before attempting to
+  * reprogram the region.
++ *
+  * Return 0 for success or negative error code.
+  */
+ int fpga_region_program_fpga(struct fpga_region *region)
+@@ -216,7 +219,7 @@ void fpga_region_free(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_free);
+ 
+-/*
++/**
+  * fpga_region_register - register a FPGA region
+  * @region: FPGA region created by fpga_region_create
+  * Return: 0 or -errno
+@@ -228,7 +231,7 @@ int fpga_region_register(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_register);
+ 
+-/*
++/**
+  * fpga_region_unregister - unregister a FPGA region
+  * @region: FPGA region
+  */
+-- 
+2.19.0
+
diff --git a/patches/1694-dt-bindings-documentation-add-clock-bindings-informa.patch b/patches/1694-dt-bindings-documentation-add-clock-bindings-informa.patch
new file mode 100644
index 00000000000000..b3f49ff5dee4b4
--- /dev/null
+++ b/patches/1694-dt-bindings-documentation-add-clock-bindings-informa.patch
@@ -0,0 +1,141 @@
+From a839bc54920cf6561fd27097e0bb667616a3139e Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 21 Mar 2018 09:20:10 -0500
+Subject: [PATCH 1694/1795] dt-bindings: documentation: add clock bindings
+ information for Stratix10
+
+Document that Stratix10 clock bindings, and add the clock header file. The
+clock header is an enumeration of all the different clocks on the Stratix10
+platform.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+(cherry picked from commit 89727949ea1e5f8ec481cba4d5c71c32d8bff3bc)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/clock/intc_stratix10.txt         | 20 +++++
+ include/dt-bindings/clock/stratix10-clock.h   | 84 +++++++++++++++++++
+ 2 files changed, 104 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/intc_stratix10.txt
+ create mode 100644 include/dt-bindings/clock/stratix10-clock.h
+
+diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
+new file mode 100644
+index 000000000000..9f4ec5cb5c6b
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
+@@ -0,0 +1,20 @@
++Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
++
++This binding uses the common clock binding[1].
++
++[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
++
++Required properties:
++- compatible : shall be
++	"intel,stratix10-clkmgr"
++
++- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
++
++- #clock-cells : from common clock binding, shall be set to 1.
++
++Example:
++	clkmgr: clock-controller@ffd10000 {
++		compatible = "intel,stratix10-clkmgr";
++		reg = <0xffd10000 0x1000>;
++		#clock-cells = <1>;
++	};
+diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h
+new file mode 100644
+index 000000000000..0ac1c90a18bf
+--- /dev/null
++++ b/include/dt-bindings/clock/stratix10-clock.h
+@@ -0,0 +1,84 @@
++/* SPDX-License-Identifier:	GPL-2.0 */
++/*
++ * Copyright (C) 2017, Intel Corporation
++ */
++
++#ifndef __STRATIX10_CLOCK_H
++#define __STRATIX10_CLOCK_H
++
++/* fixed rate clocks */
++#define STRATIX10_OSC1			0
++#define STRATIX10_CB_INTOSC_HS_DIV2_CLK	1
++#define STRATIX10_CB_INTOSC_LS_CLK	2
++#define STRATIX10_F2S_FREE_CLK		3
++
++/* fixed factor clocks */
++#define STRATIX10_L4_SYS_FREE_CLK	4
++#define STRATIX10_MPU_PERIPH_CLK	5
++#define STRATIX10_MPU_L2RAM_CLK		6
++#define STRATIX10_SDMMC_CIU_CLK		7
++
++/* PLL clocks */
++#define STRATIX10_MAIN_PLL_CLK		8
++#define STRATIX10_PERIPH_PLL_CLK	9
++#define STRATIX10_BOOT_CLK		10
++
++/* Periph clocks */
++#define STRATIX10_MAIN_MPU_BASE_CLK	11
++#define STRATIX10_MAIN_NOC_BASE_CLK	12
++#define STRATIX10_MAIN_EMACA_CLK	13
++#define STRATIX10_MAIN_EMACB_CLK	14
++#define STRATIX10_MAIN_EMAC_PTP_CLK	15
++#define STRATIX10_MAIN_GPIO_DB_CLK	16
++#define STRATIX10_MAIN_SDMMC_CLK	17
++#define STRATIX10_MAIN_S2F_USR0_CLK	18
++#define STRATIX10_MAIN_S2F_USR1_CLK	19
++#define STRATIX10_MAIN_PSI_REF_CLK	20
++
++#define STRATIX10_PERI_MPU_BASE_CLK	21
++#define STRATIX10_PERI_NOC_BASE_CLK	22
++#define STRATIX10_PERI_EMACA_CLK	23
++#define STRATIX10_PERI_EMACB_CLK	24
++#define STRATIX10_PERI_EMAC_PTP_CLK	25
++#define STRATIX10_PERI_GPIO_DB_CLK	26
++#define STRATIX10_PERI_SDMMC_CLK	27
++#define STRATIX10_PERI_S2F_USR0_CLK	28
++#define STRATIX10_PERI_S2F_USR1_CLK	29
++#define STRATIX10_PERI_PSI_REF_CLK	30
++
++#define STRATIX10_MPU_FREE_CLK		31
++#define STRATIX10_NOC_FREE_CLK		32
++#define STRATIX10_S2F_USR0_CLK		33
++#define STRATIX10_NOC_CLK		34
++#define STRATIX10_EMAC_A_FREE_CLK	35
++#define STRATIX10_EMAC_B_FREE_CLK	36
++#define STRATIX10_EMAC_PTP_FREE_CLK	37
++#define STRATIX10_GPIO_DB_FREE_CLK	38
++#define STRATIX10_SDMMC_FREE_CLK	39
++#define STRATIX10_S2F_USER1_FREE_CLK	40
++#define STRATIX10_PSI_REF_FREE_CLK	41
++
++/* Gate clocks */
++#define STRATIX10_MPU_CLK		42
++#define STRATIX10_L4_MAIN_CLK		43
++#define STRATIX10_L4_MP_CLK		44
++#define STRATIX10_L4_SP_CLK		45
++#define STRATIX10_CS_AT_CLK		46
++#define STRATIX10_CS_TRACE_CLK		47
++#define STRATIX10_CS_PDBG_CLK		48
++#define STRATIX10_CS_TIMER_CLK		49
++#define STRATIX10_S2F_USER0_CLK		50
++#define STRATIX10_S2F_USER1_CLK		51
++#define STRATIX10_EMAC0_CLK		52
++#define STRATIX10_EMAC1_CLK		53
++#define STRATIX10_EMAC2_CLK		54
++#define STRATIX10_EMAC_PTP_CLK		55
++#define STRATIX10_GPIO_DB_CLK		56
++#define STRATIX10_SDMMC_CLK		57
++#define STRATIX10_PSI_REF_CLK		58
++#define STRATIX10_USB_CLK		59
++#define STRATIX10_SPI_M_CLK		60
++#define STRATIX10_NAND_CLK		61
++#define STRATIX10_NUM_CLKS		62
++
++#endif	/* __STRATIX10_CLOCK_H */
+-- 
+2.19.0
+
diff --git a/patches/1695-Documentation-fpga-move-fpga-overview-to-driver-api.patch b/patches/1695-Documentation-fpga-move-fpga-overview-to-driver-api.patch
new file mode 100644
index 00000000000000..aa23049ab1f345
--- /dev/null
+++ b/patches/1695-Documentation-fpga-move-fpga-overview-to-driver-api.patch
@@ -0,0 +1,148 @@
+From e8f13f74d8b61f1a235653c2b7218c1e3ca48e25 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:02 -0500
+Subject: [PATCH 1695/1795] Documentation: fpga: move fpga overview to
+ driver-api
+
+Start of moving Documentation/fpga/*.txt to driver-api, including:
+ - Add new directory driver-api/fpga
+ - Add new file driver-api/fpga/index.rst
+ - Add driver-api/fpga to driver-api/index.rst
+ - Move Documentation/fpga/overview.txt to driver-api/fpga/intro.rst
+ - Formatting and rewrites so that intro.rst will build cleanly
+   and form a good introduction to the rest of the docs to be added.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 66c472cdb62d7b00de55722a772f7dfecf88abd1)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/fpga/index.rst | 10 +++++
+ Documentation/driver-api/fpga/intro.rst | 54 +++++++++++++++++++++++++
+ Documentation/driver-api/index.rst      |  1 +
+ Documentation/fpga/overview.txt         | 23 -----------
+ 4 files changed, 65 insertions(+), 23 deletions(-)
+ create mode 100644 Documentation/driver-api/fpga/index.rst
+ create mode 100644 Documentation/driver-api/fpga/intro.rst
+ delete mode 100644 Documentation/fpga/overview.txt
+
+diff --git a/Documentation/driver-api/fpga/index.rst b/Documentation/driver-api/fpga/index.rst
+new file mode 100644
+index 000000000000..71e568aea6cd
+--- /dev/null
++++ b/Documentation/driver-api/fpga/index.rst
+@@ -0,0 +1,10 @@
++==============
++FPGA Subsystem
++==============
++
++:Author: Alan Tull
++
++.. toctree::
++   :maxdepth: 2
++
++   intro
+diff --git a/Documentation/driver-api/fpga/intro.rst b/Documentation/driver-api/fpga/intro.rst
+new file mode 100644
+index 000000000000..51cd81dbb4dc
+--- /dev/null
++++ b/Documentation/driver-api/fpga/intro.rst
+@@ -0,0 +1,54 @@
++Introduction
++============
++
++The FPGA subsystem supports reprogramming FPGAs dynamically under
++Linux.  Some of the core intentions of the FPGA subsystems are:
++
++* The FPGA subsystem is vendor agnostic.
++
++* The FPGA subsystem separates upper layers (userspace interfaces and
++  enumeration) from lower layers that know how to program a specific
++  FPGA.
++
++* Code should not be shared between upper and lower layers.  This
++  should go without saying.  If that seems necessary, there's probably
++  framework functionality that that can be added that will benefit
++  other users.  Write the linux-fpga mailing list and maintainers and
++  seek out a solution that expands the framework for broad reuse.
++
++* Generally, when adding code, think of the future.  Plan for re-use.
++
++The framework in the kernel is divided into:
++
++FPGA Manager
++------------
++
++If you are adding a new FPGA or a new method of programming a FPGA,
++this is the subsystem for you.  Low level FPGA manager drivers contain
++the knowledge of how to program a specific device.  This subsystem
++includes the framework in fpga-mgr.c and the low level drivers that
++are registered with it.
++
++FPGA Bridge
++-----------
++
++FPGA Bridges prevent spurious signals from going out of a FPGA or a
++region of a FPGA during programming.  They are disabled before
++programming begins and re-enabled afterwards.  An FPGA bridge may be
++actual hard hardware that gates a bus to a cpu or a soft ("freeze")
++bridge in FPGA fabric that surrounds a partial reconfiguration region
++of an FPGA.  This subsystem includes fpga-bridge.c and the low level
++drivers that are registered with it.
++
++FPGA Region
++-----------
++
++If you are adding a new interface to the FPGA framework, add it on top
++of a FPGA region to allow the most reuse of your interface.
++
++The FPGA Region framework (fpga-region.c) associates managers and
++bridges as reconfigurable regions.  A region may refer to the whole
++FPGA in full reconfiguration or to a partial reconfiguration region.
++
++The Device Tree FPGA Region support (of-fpga-region.c) handles
++reprogramming FPGAs when device tree overlays are applied.
+diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
+index 9c20624842b7..d58ea64df66e 100644
+--- a/Documentation/driver-api/index.rst
++++ b/Documentation/driver-api/index.rst
+@@ -46,6 +46,7 @@ available subsections can be seen below.
+    pinctl
+    gpio
+    misc_devices
++   fpga/index
+ 
+ .. only::  subproject and html
+ 
+diff --git a/Documentation/fpga/overview.txt b/Documentation/fpga/overview.txt
+deleted file mode 100644
+index 0f1236e7e675..000000000000
+--- a/Documentation/fpga/overview.txt
++++ /dev/null
+@@ -1,23 +0,0 @@
+-Linux kernel FPGA support
+-
+-Alan Tull 2017
+-
+-The main point of this project has been to separate the out the upper layers
+-that know when to reprogram a FPGA from the lower layers that know how to
+-reprogram a specific FPGA device.  The intention is to make this manufacturer
+-agnostic, understanding that of course the FPGA images are very device specific
+-themselves.
+-
+-The framework in the kernel includes:
+-* low level FPGA manager drivers that know how to program a specific device
+-* the fpga-mgr framework they are registered with
+-* low level FPGA bridge drivers for hard/soft bridges which are intended to
+-  be disable during FPGA programming
+-* the fpga-bridge framework they are registered with
+-* the fpga-region framework which associates and controls managers and bridges
+-  as reconfigurable regions
+-* the of-fpga-region support for reprogramming FPGAs when device tree overlays
+-  are applied.
+-
+-I would encourage you the user to add code that creates FPGA regions rather
+-that trying to control managers and bridges separately.
+-- 
+2.19.0
+
diff --git a/patches/1696-documentation-fpga-move-fpga-mgr.txt-to-driver-api.patch b/patches/1696-documentation-fpga-move-fpga-mgr.txt-to-driver-api.patch
new file mode 100644
index 00000000000000..715e0b76622c78
--- /dev/null
+++ b/patches/1696-documentation-fpga-move-fpga-mgr.txt-to-driver-api.patch
@@ -0,0 +1,489 @@
+From 8315e661b3bcf4055c7f1cf2bf2e23dfdefb0844 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:03 -0500
+Subject: [PATCH 1696/1795] documentation: fpga: move fpga-mgr.txt to
+ driver-api
+
+Move Documentation/fpga/fpga-mgr.txt to driver-api/fpga/fpga-mgr.rst
+and:
+ - Add to driver-api/fpga/index.rst
+ - Format changes so documentation builds cleanly.
+ - Minor rewrites that make the doc flow better as ReST documentation.
+   - Such as moving API reference to end of doc
+ - Change API reference section to refer to kernel-doc documentation in
+   fpga-mgr.c driver code rather than statically defining each function.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 547b822c22b18e346ee1d562d1787486e5c88c3c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/fpga/fpga-mgr.rst | 220 +++++++++++++++++++++
+ Documentation/driver-api/fpga/index.rst    |   1 +
+ Documentation/fpga/fpga-mgr.txt            | 218 --------------------
+ 3 files changed, 221 insertions(+), 218 deletions(-)
+ create mode 100644 Documentation/driver-api/fpga/fpga-mgr.rst
+ delete mode 100644 Documentation/fpga/fpga-mgr.txt
+
+diff --git a/Documentation/driver-api/fpga/fpga-mgr.rst b/Documentation/driver-api/fpga/fpga-mgr.rst
+new file mode 100644
+index 000000000000..bcf2dd24e179
+--- /dev/null
++++ b/Documentation/driver-api/fpga/fpga-mgr.rst
+@@ -0,0 +1,220 @@
++FPGA Manager
++============
++
++Overview
++--------
++
++The FPGA manager core exports a set of functions for programming an FPGA with
++an image.  The API is manufacturer agnostic.  All manufacturer specifics are
++hidden away in a low level driver which registers a set of ops with the core.
++The FPGA image data itself is very manufacturer specific, but for our purposes
++it's just binary data.  The FPGA manager core won't parse it.
++
++The FPGA image to be programmed can be in a scatter gather list, a single
++contiguous buffer, or a firmware file.  Because allocating contiguous kernel
++memory for the buffer should be avoided, users are encouraged to use a scatter
++gather list instead if possible.
++
++The particulars for programming the image are presented in a structure (struct
++fpga_image_info).  This struct contains parameters such as pointers to the
++FPGA image as well as image-specific particulars such as whether the image was
++built for full or partial reconfiguration.
++
++How to support a new FPGA device
++--------------------------------
++
++To add another FPGA manager, write a driver that implements a set of ops.  The
++probe function calls fpga_mgr_register(), such as::
++
++	static const struct fpga_manager_ops socfpga_fpga_ops = {
++		.write_init = socfpga_fpga_ops_configure_init,
++		.write = socfpga_fpga_ops_configure_write,
++		.write_complete = socfpga_fpga_ops_configure_complete,
++		.state = socfpga_fpga_ops_state,
++	};
++
++	static int socfpga_fpga_probe(struct platform_device *pdev)
++	{
++		struct device *dev = &pdev->dev;
++		struct socfpga_fpga_priv *priv;
++		struct fpga_manager *mgr;
++		int ret;
++
++		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++		if (!priv)
++			return -ENOMEM;
++
++		/*
++		 * do ioremaps, get interrupts, etc. and save
++		 * them in priv
++		 */
++
++		mgr = fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
++				      &socfpga_fpga_ops, priv);
++		if (!mgr)
++			return -ENOMEM;
++
++		platform_set_drvdata(pdev, mgr);
++
++		ret = fpga_mgr_register(mgr);
++		if (ret)
++			fpga_mgr_free(mgr);
++
++		return ret;
++	}
++
++	static int socfpga_fpga_remove(struct platform_device *pdev)
++	{
++		struct fpga_manager *mgr = platform_get_drvdata(pdev);
++
++		fpga_mgr_unregister(mgr);
++
++		return 0;
++	}
++
++
++The ops will implement whatever device specific register writes are needed to
++do the programming sequence for this particular FPGA.  These ops return 0 for
++success or negative error codes otherwise.
++
++The programming sequence is::
++ 1. .write_init
++ 2. .write or .write_sg (may be called once or multiple times)
++ 3. .write_complete
++
++The .write_init function will prepare the FPGA to receive the image data.  The
++buffer passed into .write_init will be atmost .initial_header_size bytes long,
++if the whole bitstream is not immediately available then the core code will
++buffer up at least this much before starting.
++
++The .write function writes a buffer to the FPGA. The buffer may be contain the
++whole FPGA image or may be a smaller chunk of an FPGA image.  In the latter
++case, this function is called multiple times for successive chunks. This interface
++is suitable for drivers which use PIO.
++
++The .write_sg version behaves the same as .write except the input is a sg_table
++scatter list. This interface is suitable for drivers which use DMA.
++
++The .write_complete function is called after all the image has been written
++to put the FPGA into operating mode.
++
++The ops include a .state function which will read the hardware FPGA manager and
++return a code of type enum fpga_mgr_states.  It doesn't result in a change in
++hardware state.
++
++How to write an image buffer to a supported FPGA
++------------------------------------------------
++
++Some sample code::
++
++	#include <linux/fpga/fpga-mgr.h>
++
++	struct fpga_manager *mgr;
++	struct fpga_image_info *info;
++	int ret;
++
++	/*
++	 * Get a reference to FPGA manager.  The manager is not locked, so you can
++	 * hold onto this reference without it preventing programming.
++	 *
++	 * This example uses the device node of the manager.  Alternatively, use
++	 * fpga_mgr_get(dev) instead if you have the device.
++	 */
++	mgr = of_fpga_mgr_get(mgr_node);
++
++	/* struct with information about the FPGA image to program. */
++	info = fpga_image_info_alloc(dev);
++
++	/* flags indicates whether to do full or partial reconfiguration */
++	info->flags = FPGA_MGR_PARTIAL_RECONFIG;
++
++	/*
++	 * At this point, indicate where the image is. This is pseudo-code; you're
++	 * going to use one of these three.
++	 */
++	if (image is in a scatter gather table) {
++
++		info->sgt = [your scatter gather table]
++
++	} else if (image is in a buffer) {
++
++		info->buf = [your image buffer]
++		info->count = [image buffer size]
++
++	} else if (image is in a firmware file) {
++
++		info->firmware_name = devm_kstrdup(dev, firmware_name, GFP_KERNEL);
++
++	}
++
++	/* Get exclusive control of FPGA manager */
++	ret = fpga_mgr_lock(mgr);
++
++	/* Load the buffer to the FPGA */
++	ret = fpga_mgr_buf_load(mgr, &info, buf, count);
++
++	/* Release the FPGA manager */
++	fpga_mgr_unlock(mgr);
++	fpga_mgr_put(mgr);
++
++	/* Deallocate the image info if you're done with it */
++	fpga_image_info_free(info);
++
++API for implementing a new FPGA Manager driver
++----------------------------------------------
++
++.. kernel-doc:: include/linux/fpga/fpga-mgr.h
++   :functions: fpga_manager
++
++.. kernel-doc:: include/linux/fpga/fpga-mgr.h
++   :functions: fpga_manager_ops
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_create
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_free
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_register
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_unregister
++
++API for programming a FPGA
++--------------------------
++
++.. kernel-doc:: include/linux/fpga/fpga-mgr.h
++   :functions: fpga_image_info
++
++.. kernel-doc:: include/linux/fpga/fpga-mgr.h
++   :functions: fpga_mgr_states
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_image_info_alloc
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_image_info_free
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: of_fpga_mgr_get
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_get
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_put
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_lock
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_unlock
++
++.. kernel-doc:: include/linux/fpga/fpga-mgr.h
++   :functions: fpga_mgr_states
++
++Note - use :c:func:`fpga_region_program_fpga()` instead of :c:func:`fpga_mgr_load()`
++
++.. kernel-doc:: drivers/fpga/fpga-mgr.c
++   :functions: fpga_mgr_load
+diff --git a/Documentation/driver-api/fpga/index.rst b/Documentation/driver-api/fpga/index.rst
+index 71e568aea6cd..34b20754517f 100644
+--- a/Documentation/driver-api/fpga/index.rst
++++ b/Documentation/driver-api/fpga/index.rst
+@@ -8,3 +8,4 @@ FPGA Subsystem
+    :maxdepth: 2
+ 
+    intro
++   fpga-mgr
+diff --git a/Documentation/fpga/fpga-mgr.txt b/Documentation/fpga/fpga-mgr.txt
+deleted file mode 100644
+index 86b6df66a905..000000000000
+--- a/Documentation/fpga/fpga-mgr.txt
++++ /dev/null
+@@ -1,218 +0,0 @@
+-FPGA Manager Core
+-
+-Alan Tull 2015
+-
+-Overview
+-========
+-
+-The FPGA manager core exports a set of functions for programming an FPGA with
+-an image.  The API is manufacturer agnostic.  All manufacturer specifics are
+-hidden away in a low level driver which registers a set of ops with the core.
+-The FPGA image data itself is very manufacturer specific, but for our purposes
+-it's just binary data.  The FPGA manager core won't parse it.
+-
+-The FPGA image to be programmed can be in a scatter gather list, a single
+-contiguous buffer, or a firmware file.  Because allocating contiguous kernel
+-memory for the buffer should be avoided, users are encouraged to use a scatter
+-gather list instead if possible.
+-
+-The particulars for programming the image are presented in a structure (struct
+-fpga_image_info).  This struct contains parameters such as pointers to the
+-FPGA image as well as image-specific particulars such as whether the image was
+-built for full or partial reconfiguration.
+-
+-API Functions:
+-==============
+-
+-To program the FPGA:
+---------------------
+-
+-	int fpga_mgr_load(struct fpga_manager *mgr,
+-			  struct fpga_image_info *info);
+-
+-Load the FPGA from an image which is indicated in the info.  If successful,
+-the FPGA ends up in operating mode.  Return 0 on success or a negative error
+-code.
+-
+-To allocate or free a struct fpga_image_info:
+----------------------------------------------
+-
+-	struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
+-
+-	void fpga_image_info_free(struct fpga_image_info *info);
+-
+-To get/put a reference to a FPGA manager:
+------------------------------------------
+-
+-	struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
+-	struct fpga_manager *fpga_mgr_get(struct device *dev);
+-	void fpga_mgr_put(struct fpga_manager *mgr);
+-
+-Given a DT node or device, get a reference to a FPGA manager.  This pointer
+-can be saved until you are ready to program the FPGA.  fpga_mgr_put releases
+-the reference.
+-
+-
+-To get exclusive control of a FPGA manager:
+--------------------------------------------
+-
+-	int fpga_mgr_lock(struct fpga_manager *mgr);
+-	void fpga_mgr_unlock(struct fpga_manager *mgr);
+-
+-The user should call fpga_mgr_lock and verify that it returns 0 before
+-attempting to program the FPGA.  Likewise, the user should call
+-fpga_mgr_unlock when done programming the FPGA.
+-
+-To alloc/free a FPGA manager struct:
+-------------------------------------
+-
+-	struct fpga_manager *fpga_mgr_create(struct device *dev,
+-					     const char *name,
+-					     const struct fpga_manager_ops *mops,
+-					     void *priv);
+-	void fpga_mgr_free(struct fpga_manager *mgr);
+-
+-To register or unregister the low level FPGA-specific driver:
+--------------------------------------------------------------
+-
+-	int fpga_mgr_register(struct fpga_manager *mgr);
+-
+-	void fpga_mgr_unregister(struct fpga_manager *mgr);
+-
+-Use of these functions is described below in "How To Support a new FPGA
+-device."
+-
+-
+-How to write an image buffer to a supported FPGA
+-================================================
+-#include <linux/fpga/fpga-mgr.h>
+-
+-struct fpga_manager *mgr;
+-struct fpga_image_info *info;
+-int ret;
+-
+-/*
+- * Get a reference to FPGA manager.  The manager is not locked, so you can
+- * hold onto this reference without it preventing programming.
+- *
+- * This example uses the device node of the manager.  Alternatively, use
+- * fpga_mgr_get(dev) instead if you have the device.
+- */
+-mgr = of_fpga_mgr_get(mgr_node);
+-
+-/* struct with information about the FPGA image to program. */
+-info = fpga_image_info_alloc(dev);
+-
+-/* flags indicates whether to do full or partial reconfiguration */
+-info->flags = FPGA_MGR_PARTIAL_RECONFIG;
+-
+-/*
+- * At this point, indicate where the image is. This is pseudo-code; you're
+- * going to use one of these three.
+- */
+-if (image is in a scatter gather table) {
+-
+-	info->sgt = [your scatter gather table]
+-
+-} else if (image is in a buffer) {
+-
+-	info->buf = [your image buffer]
+-	info->count = [image buffer size]
+-
+-} else if (image is in a firmware file) {
+-
+-	info->firmware_name = devm_kstrdup(dev, firmware_name, GFP_KERNEL);
+-
+-}
+-
+-/* Get exclusive control of FPGA manager */
+-ret = fpga_mgr_lock(mgr);
+-
+-/* Load the buffer to the FPGA */
+-ret = fpga_mgr_buf_load(mgr, &info, buf, count);
+-
+-/* Release the FPGA manager */
+-fpga_mgr_unlock(mgr);
+-fpga_mgr_put(mgr);
+-
+-/* Deallocate the image info if you're done with it */
+-fpga_image_info_free(info);
+-
+-How to support a new FPGA device
+-================================
+-To add another FPGA manager, write a driver that implements a set of ops.  The
+-probe function calls fpga_mgr_register(), such as:
+-
+-static const struct fpga_manager_ops socfpga_fpga_ops = {
+-       .write_init = socfpga_fpga_ops_configure_init,
+-       .write = socfpga_fpga_ops_configure_write,
+-       .write_complete = socfpga_fpga_ops_configure_complete,
+-       .state = socfpga_fpga_ops_state,
+-};
+-
+-static int socfpga_fpga_probe(struct platform_device *pdev)
+-{
+-	struct device *dev = &pdev->dev;
+-	struct socfpga_fpga_priv *priv;
+-	struct fpga_manager *mgr;
+-	int ret;
+-
+-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	/* ... do ioremaps, get interrupts, etc. and save
+-	   them in priv... */
+-
+-	mgr = fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
+-			      &socfpga_fpga_ops, priv);
+-	if (!mgr)
+-		return -ENOMEM;
+-
+-	platform_set_drvdata(pdev, mgr);
+-
+-	ret = fpga_mgr_register(mgr);
+-	if (ret)
+-		fpga_mgr_free(mgr);
+-
+-	return ret;
+-}
+-
+-static int socfpga_fpga_remove(struct platform_device *pdev)
+-{
+-	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+-
+-	fpga_mgr_unregister(mgr);
+-
+-	return 0;
+-}
+-
+-
+-The ops will implement whatever device specific register writes are needed to
+-do the programming sequence for this particular FPGA.  These ops return 0 for
+-success or negative error codes otherwise.
+-
+-The programming sequence is:
+- 1. .write_init
+- 2. .write or .write_sg (may be called once or multiple times)
+- 3. .write_complete
+-
+-The .write_init function will prepare the FPGA to receive the image data.  The
+-buffer passed into .write_init will be atmost .initial_header_size bytes long,
+-if the whole bitstream is not immediately available then the core code will
+-buffer up at least this much before starting.
+-
+-The .write function writes a buffer to the FPGA. The buffer may be contain the
+-whole FPGA image or may be a smaller chunk of an FPGA image.  In the latter
+-case, this function is called multiple times for successive chunks. This interface
+-is suitable for drivers which use PIO.
+-
+-The .write_sg version behaves the same as .write except the input is a sg_table
+-scatter list. This interface is suitable for drivers which use DMA.
+-
+-The .write_complete function is called after all the image has been written
+-to put the FPGA into operating mode.
+-
+-The ops include a .state function which will read the hardware FPGA manager and
+-return a code of type enum fpga_mgr_states.  It doesn't result in a change in
+-hardware state.
+-- 
+2.19.0
+
diff --git a/patches/1697-documentation-fpga-add-bridge-document-to-driver-api.patch b/patches/1697-documentation-fpga-add-bridge-document-to-driver-api.patch
new file mode 100644
index 00000000000000..e24d0143432491
--- /dev/null
+++ b/patches/1697-documentation-fpga-add-bridge-document-to-driver-api.patch
@@ -0,0 +1,86 @@
+From 44b0f3d942d78ede17c67ab306e100c52cdf2fca Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:04 -0500
+Subject: [PATCH 1697/1795] documentation: fpga: add bridge document to
+ driver-api
+
+Add a new document to driver-api/fpga that documents the
+fpga bridge API and add it to driver-api/fpga/index.rst
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 9e4c36b1c9799de406a183c0fe946a614d97288c)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/fpga/fpga-bridge.rst | 49 +++++++++++++++++++
+ Documentation/driver-api/fpga/index.rst       |  1 +
+ 2 files changed, 50 insertions(+)
+ create mode 100644 Documentation/driver-api/fpga/fpga-bridge.rst
+
+diff --git a/Documentation/driver-api/fpga/fpga-bridge.rst b/Documentation/driver-api/fpga/fpga-bridge.rst
+new file mode 100644
+index 000000000000..2c2aaca894bf
+--- /dev/null
++++ b/Documentation/driver-api/fpga/fpga-bridge.rst
+@@ -0,0 +1,49 @@
++FPGA Bridge
++===========
++
++API to implement a new FPGA bridge
++~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++
++.. kernel-doc:: include/linux/fpga/fpga-bridge.h
++   :functions: fpga_bridge
++
++.. kernel-doc:: include/linux/fpga/fpga-bridge.h
++   :functions: fpga_bridge_ops
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_create
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_free
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_register
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_unregister
++
++API to control an FPGA bridge
++~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++
++You probably won't need these directly.  FPGA regions should handle this.
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: of_fpga_bridge_get
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_get
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_put
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_get_to_list
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: of_fpga_bridge_get_to_list
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_enable
++
++.. kernel-doc:: drivers/fpga/fpga-bridge.c
++   :functions: fpga_bridge_disable
+diff --git a/Documentation/driver-api/fpga/index.rst b/Documentation/driver-api/fpga/index.rst
+index 34b20754517f..968bbbfce0e8 100644
+--- a/Documentation/driver-api/fpga/index.rst
++++ b/Documentation/driver-api/fpga/index.rst
+@@ -9,3 +9,4 @@ FPGA Subsystem
+ 
+    intro
+    fpga-mgr
++   fpga-bridge
+-- 
+2.19.0
+
diff --git a/patches/1698-documentation-fpga-move-fpga-region.txt-to-driver-ap.patch b/patches/1698-documentation-fpga-move-fpga-region.txt-to-driver-ap.patch
new file mode 100644
index 00000000000000..19cd623b537e72
--- /dev/null
+++ b/patches/1698-documentation-fpga-move-fpga-region.txt-to-driver-ap.patch
@@ -0,0 +1,247 @@
+From 21a76390c6e05677ed6df25bca4453190c54ba9f Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:05 -0500
+Subject: [PATCH 1698/1795] documentation: fpga: move fpga-region.txt to
+ driver-api
+
+Move Documentation/fpga/fpga-region.txt to
+driver-api/fpga/fpga-region.rst.  Including:
+ - Add it to driver-api/fpga/index.rst
+ - Formatting changes to build cleanly as ReST documentation
+ - Some rewrites for better flow as a ReST doc such as moving
+   API reference to the end of the doc
+ - Rewrite API reference section to refer to kernel-doc
+   documentation in fpga-region.c driver code
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fcc803956a4725dac790ddfce27f519ca6d84c60)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/fpga/fpga-region.rst | 102 ++++++++++++++++++
+ Documentation/driver-api/fpga/index.rst       |   1 +
+ Documentation/fpga/fpga-region.txt            |  94 ----------------
+ 3 files changed, 103 insertions(+), 94 deletions(-)
+ create mode 100644 Documentation/driver-api/fpga/fpga-region.rst
+ delete mode 100644 Documentation/fpga/fpga-region.txt
+
+diff --git a/Documentation/driver-api/fpga/fpga-region.rst b/Documentation/driver-api/fpga/fpga-region.rst
+new file mode 100644
+index 000000000000..f89e4a311722
+--- /dev/null
++++ b/Documentation/driver-api/fpga/fpga-region.rst
+@@ -0,0 +1,102 @@
++FPGA Region
++===========
++
++Overview
++--------
++
++This document is meant to be an brief overview of the FPGA region API usage.  A
++more conceptual look at regions can be found in the Device Tree binding
++document [#f1]_.
++
++For the purposes of this API document, let's just say that a region associates
++an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
++FPGA or the whole FPGA.  The API provides a way to register a region and to
++program a region.
++
++Currently the only layer above fpga-region.c in the kernel is the Device Tree
++support (of-fpga-region.c) described in [#f1]_.  The DT support layer uses regions
++to program the FPGA and then DT to handle enumeration.  The common region code
++is intended to be used by other schemes that have other ways of accomplishing
++enumeration after programming.
++
++An fpga-region can be set up to know the following things:
++
++ * which FPGA manager to use to do the programming
++
++ * which bridges to disable before programming and enable afterwards.
++
++Additional info needed to program the FPGA image is passed in the struct
++fpga_image_info including:
++
++ * pointers to the image as either a scatter-gather buffer, a contiguous
++   buffer, or the name of firmware file
++
++ * flags indicating specifics such as whether the image if for partial
++   reconfiguration.
++
++How to program a FPGA using a region
++------------------------------------
++
++First, allocate the info struct::
++
++	info = fpga_image_info_alloc(dev);
++	if (!info)
++		return -ENOMEM;
++
++Set flags as needed, i.e.::
++
++	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
++
++Point to your FPGA image, such as::
++
++	info->sgt = &sgt;
++
++Add info to region and do the programming::
++
++	region->info = info;
++	ret = fpga_region_program_fpga(region);
++
++:c:func:`fpga_region_program_fpga()` operates on info passed in the
++fpga_image_info (region->info).  This function will attempt to:
++
++ * lock the region's mutex
++ * lock the region's FPGA manager
++ * build a list of FPGA bridges if a method has been specified to do so
++ * disable the bridges
++ * program the FPGA
++ * re-enable the bridges
++ * release the locks
++
++Then you will want to enumerate whatever hardware has appeared in the FPGA.
++
++How to add a new FPGA region
++----------------------------
++
++An example of usage can be seen in the probe function of [#f2]_.
++
++.. [#f1] ../devicetree/bindings/fpga/fpga-region.txt
++.. [#f2] ../../drivers/fpga/of-fpga-region.c
++
++API to program a FGPA
++---------------------
++
++.. kernel-doc:: drivers/fpga/fpga-region.c
++   :functions: fpga_region_program_fpga
++
++API to add a new FPGA region
++----------------------------
++
++.. kernel-doc:: include/linux/fpga/fpga-region.h
++   :functions: fpga_region
++
++.. kernel-doc:: drivers/fpga/fpga-region.c
++   :functions: fpga_region_create
++
++.. kernel-doc:: drivers/fpga/fpga-region.c
++   :functions: fpga_region_free
++
++.. kernel-doc:: drivers/fpga/fpga-region.c
++   :functions: fpga_region_register
++
++.. kernel-doc:: drivers/fpga/fpga-region.c
++   :functions: fpga_region_unregister
+diff --git a/Documentation/driver-api/fpga/index.rst b/Documentation/driver-api/fpga/index.rst
+index 968bbbfce0e8..c51e5ebd544a 100644
+--- a/Documentation/driver-api/fpga/index.rst
++++ b/Documentation/driver-api/fpga/index.rst
+@@ -10,3 +10,4 @@ FPGA Subsystem
+    intro
+    fpga-mgr
+    fpga-bridge
++   fpga-region
+diff --git a/Documentation/fpga/fpga-region.txt b/Documentation/fpga/fpga-region.txt
+deleted file mode 100644
+index d38fa3b4154a..000000000000
+--- a/Documentation/fpga/fpga-region.txt
++++ /dev/null
+@@ -1,94 +0,0 @@
+-FPGA Regions
+-
+-Alan Tull 2017
+-
+-CONTENTS
+- - Introduction
+- - The FPGA region API
+- - Usage example
+-
+-Introduction
+-============
+-
+-This document is meant to be an brief overview of the FPGA region API usage.  A
+-more conceptual look at regions can be found in [1].
+-
+-For the purposes of this API document, let's just say that a region associates
+-an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
+-FPGA or the whole FPGA.  The API provides a way to register a region and to
+-program a region.
+-
+-Currently the only layer above fpga-region.c in the kernel is the Device Tree
+-support (of-fpga-region.c) described in [1].  The DT support layer uses regions
+-to program the FPGA and then DT to handle enumeration.  The common region code
+-is intended to be used by other schemes that have other ways of accomplishing
+-enumeration after programming.
+-
+-An fpga-region can be set up to know the following things:
+-* which FPGA manager to use to do the programming
+-* which bridges to disable before programming and enable afterwards.
+-
+-Additional info needed to program the FPGA image is passed in the struct
+-fpga_image_info [2] including:
+-* pointers to the image as either a scatter-gather buffer, a contiguous
+-  buffer, or the name of firmware file
+-* flags indicating specifics such as whether the image if for partial
+-  reconfiguration.
+-
+-===================
+-The FPGA region API
+-===================
+-
+-To register or unregister a region:
+------------------------------------
+-
+-	int fpga_region_register(struct fpga_region *region);
+-	int fpga_region_unregister(struct fpga_region *region);
+-
+-An example of usage can be seen in the probe function of [3]
+-
+-To program an FPGA:
+--------------------
+-	int fpga_region_program_fpga(struct fpga_region *region);
+-
+-This function operates on info passed in the fpga_image_info
+-(region->info).
+-
+-This function will attempt to:
+- * lock the region's mutex
+- * lock the region's FPGA manager
+- * build a list of FPGA bridges if a method has been specified to do so
+- * disable the bridges
+- * program the FPGA
+- * re-enable the bridges
+- * release the locks
+-
+-=============
+-Usage example
+-=============
+-
+-First, allocate the info struct:
+-
+-	info = fpga_image_info_alloc(dev);
+-	if (!info)
+-		return -ENOMEM;
+-
+-Set flags as needed, i.e.
+-
+-	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
+-
+-Point to your FPGA image, such as:
+-
+-	info->sgt = &sgt;
+-
+-Add info to region and do the programming:
+-
+-	region->info = info;
+-	ret = fpga_region_program_fpga(region);
+-
+-Then enumerate whatever hardware has appeared in the FPGA.
+-
+---
+-[1] ../devicetree/bindings/fpga/fpga-region.txt
+-[2] ./fpga-mgr.txt
+-[3] ../../drivers/fpga/of-fpga-region.c
+-- 
+2.19.0
+
diff --git a/patches/1699-fpga-clarify-that-unregister-functions-also-free.patch b/patches/1699-fpga-clarify-that-unregister-functions-also-free.patch
new file mode 100644
index 00000000000000..d16b3127f8b3a6
--- /dev/null
+++ b/patches/1699-fpga-clarify-that-unregister-functions-also-free.patch
@@ -0,0 +1,63 @@
+From 1f49a01ce6191c33b646a18e579ea7b2f8d64c05 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:06 -0500
+Subject: [PATCH 1699/1795] fpga: clarify that unregister functions also free
+
+The following functions also free the struct.  Add that
+fact to the function documentation.
+ - fpga_mgr_free
+ - fpga_bridge_free
+ - fpga_region_free
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fdff4053d51be4850185aa895813405decd6e956)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/fpga-bridge.c | 2 +-
+ drivers/fpga/fpga-mgr.c    | 2 +-
+ drivers/fpga/fpga-region.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
+index 4b207a75b696..24b8f98b73ec 100644
+--- a/drivers/fpga/fpga-bridge.c
++++ b/drivers/fpga/fpga-bridge.c
+@@ -412,7 +412,7 @@ int fpga_bridge_register(struct fpga_bridge *bridge)
+ EXPORT_SYMBOL_GPL(fpga_bridge_register);
+ 
+ /**
+- * fpga_bridge_unregister - unregister a fpga bridge driver
++ * fpga_bridge_unregister - unregister and free a fpga bridge
+  * @bridge:	FPGA bridge struct created by fpga_bridge_create
+  */
+ void fpga_bridge_unregister(struct fpga_bridge *bridge)
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index 5fffeeffed5f..c1564cf827fe 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -633,7 +633,7 @@ int fpga_mgr_register(struct fpga_manager *mgr)
+ EXPORT_SYMBOL_GPL(fpga_mgr_register);
+ 
+ /**
+- * fpga_mgr_unregister - unregister a FPGA manager
++ * fpga_mgr_unregister - unregister and free a FPGA manager
+  * @mgr:	fpga manager struct
+  */
+ void fpga_mgr_unregister(struct fpga_manager *mgr)
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 112fa3a0f977..6d214d75c7be 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -232,7 +232,7 @@ int fpga_region_register(struct fpga_region *region)
+ EXPORT_SYMBOL_GPL(fpga_region_register);
+ 
+ /**
+- * fpga_region_unregister - unregister a FPGA region
++ * fpga_region_unregister - unregister and free a FPGA region
+  * @region: FPGA region
+  */
+ void fpga_region_unregister(struct fpga_region *region)
+-- 
+2.19.0
+
diff --git a/patches/1700-MAINTAINERS-Add-driver-api-fpga-path.patch b/patches/1700-MAINTAINERS-Add-driver-api-fpga-path.patch
new file mode 100644
index 00000000000000..c53f1d5f4992c3
--- /dev/null
+++ b/patches/1700-MAINTAINERS-Add-driver-api-fpga-path.patch
@@ -0,0 +1,31 @@
+From e5e6381917077fa70e66b5b42b5c03294621614c Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 16 May 2018 18:50:07 -0500
+Subject: [PATCH 1700/1795] MAINTAINERS: Add driver-api/fpga path
+
+Add Documentation/driver-api/fpga path to MAINTAINERS file
+for fpga.
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d6edc07cca93b8669512501f25d03187ca531f63)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ MAINTAINERS | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 28af79cd07f8..5cd120443c8f 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -5438,6 +5438,7 @@ S:	Maintained
+ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git
+ Q:	http://patchwork.kernel.org/project/linux-fpga/list/
+ F:	Documentation/fpga/
++F:	Documentation/driver-api/fpga/
+ F:	Documentation/devicetree/bindings/fpga/
+ F:	drivers/fpga/
+ F:	include/linux/fpga/
+-- 
+2.19.0
+
diff --git a/patches/1701-fpga-altera-cvp-Fix-an-error-handling-path-in-altera.patch b/patches/1701-fpga-altera-cvp-Fix-an-error-handling-path-in-altera.patch
new file mode 100644
index 00000000000000..a0de111b5accba
--- /dev/null
+++ b/patches/1701-fpga-altera-cvp-Fix-an-error-handling-path-in-altera.patch
@@ -0,0 +1,40 @@
+From 7494a68dbdbcb08e86e406c4c62bc79c216c8cc8 Mon Sep 17 00:00:00 2001
+From: Christophe Jaillet <christophe.jaillet@wanadoo.fr>
+Date: Wed, 27 Jun 2018 20:56:18 -0500
+Subject: [PATCH 1701/1795] fpga: altera-cvp: Fix an error handling path in
+ 'altera_cvp_probe()'
+
+If 'fpga_mgr_create()' fails, we should release some resources, as done
+in the other error handling path of the function.
+
+Fixes: 7085e2a94f7d ("fpga: manager: change api, don't use drvdata")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Moritz Fischer <mdf@kernel.org>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 122c5770cff2c1df1a2384b68285be2812cd72c1)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/altera-cvp.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
+index dd4edd8f22ce..7fa793672a7a 100644
+--- a/drivers/fpga/altera-cvp.c
++++ b/drivers/fpga/altera-cvp.c
+@@ -455,8 +455,10 @@ static int altera_cvp_probe(struct pci_dev *pdev,
+ 
+ 	mgr = fpga_mgr_create(&pdev->dev, conf->mgr_name,
+ 			      &altera_cvp_ops, conf);
+-	if (!mgr)
+-		return -ENOMEM;
++	if (!mgr) {
++		ret = -ENOMEM;
++		goto err_unmap;
++	}
+ 
+ 	pci_set_drvdata(pdev, mgr);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1702-Documentation-fpga-cleanup.patch b/patches/1702-Documentation-fpga-cleanup.patch
new file mode 100644
index 00000000000000..88ebb4492ec8ba
--- /dev/null
+++ b/patches/1702-Documentation-fpga-cleanup.patch
@@ -0,0 +1,152 @@
+From 922e493334607af188ce23578b1a887b2e66c9f5 Mon Sep 17 00:00:00 2001
+From: Alan Tull <atull@kernel.org>
+Date: Wed, 27 Jun 2018 20:56:19 -0500
+Subject: [PATCH 1702/1795] Documentation: fpga: cleanup
+
+Minor fixes including:
+
+* fix some typos
+* correct use of a/an
+* rephrase explanation of .state ops function
+* s/re-use/reuse/ (use only one spelling of 'reuse' in these docs)
+* s/cpu/CPU/
+
+Signed-off-by: Alan Tull <atull@kernel.org>
+Acked-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit a59f95c7a2c35031264eafc62e684df07f5f2a8f)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/driver-api/fpga/fpga-mgr.rst    | 12 ++++++------
+ Documentation/driver-api/fpga/fpga-region.rst | 12 ++++++------
+ Documentation/driver-api/fpga/intro.rst       | 14 +++++++-------
+ 3 files changed, 19 insertions(+), 19 deletions(-)
+
+diff --git a/Documentation/driver-api/fpga/fpga-mgr.rst b/Documentation/driver-api/fpga/fpga-mgr.rst
+index bcf2dd24e179..4b3825da48d9 100644
+--- a/Documentation/driver-api/fpga/fpga-mgr.rst
++++ b/Documentation/driver-api/fpga/fpga-mgr.rst
+@@ -83,7 +83,7 @@ The programming sequence is::
+  3. .write_complete
+ 
+ The .write_init function will prepare the FPGA to receive the image data.  The
+-buffer passed into .write_init will be atmost .initial_header_size bytes long,
++buffer passed into .write_init will be at most .initial_header_size bytes long;
+ if the whole bitstream is not immediately available then the core code will
+ buffer up at least this much before starting.
+ 
+@@ -98,9 +98,9 @@ scatter list. This interface is suitable for drivers which use DMA.
+ The .write_complete function is called after all the image has been written
+ to put the FPGA into operating mode.
+ 
+-The ops include a .state function which will read the hardware FPGA manager and
+-return a code of type enum fpga_mgr_states.  It doesn't result in a change in
+-hardware state.
++The ops include a .state function which will determine the state the FPGA is in
++and return a code of type enum fpga_mgr_states.  It doesn't result in a change
++in state.
+ 
+ How to write an image buffer to a supported FPGA
+ ------------------------------------------------
+@@ -181,8 +181,8 @@ API for implementing a new FPGA Manager driver
+ .. kernel-doc:: drivers/fpga/fpga-mgr.c
+    :functions: fpga_mgr_unregister
+ 
+-API for programming a FPGA
+---------------------------
++API for programming an FPGA
++---------------------------
+ 
+ .. kernel-doc:: include/linux/fpga/fpga-mgr.h
+    :functions: fpga_image_info
+diff --git a/Documentation/driver-api/fpga/fpga-region.rst b/Documentation/driver-api/fpga/fpga-region.rst
+index f89e4a311722..f30333ce828e 100644
+--- a/Documentation/driver-api/fpga/fpga-region.rst
++++ b/Documentation/driver-api/fpga/fpga-region.rst
+@@ -4,7 +4,7 @@ FPGA Region
+ Overview
+ --------
+ 
+-This document is meant to be an brief overview of the FPGA region API usage.  A
++This document is meant to be a brief overview of the FPGA region API usage.  A
+ more conceptual look at regions can be found in the Device Tree binding
+ document [#f1]_.
+ 
+@@ -31,11 +31,11 @@ fpga_image_info including:
+  * pointers to the image as either a scatter-gather buffer, a contiguous
+    buffer, or the name of firmware file
+ 
+- * flags indicating specifics such as whether the image if for partial
++ * flags indicating specifics such as whether the image is for partial
+    reconfiguration.
+ 
+-How to program a FPGA using a region
+-------------------------------------
++How to program an FPGA using a region
++-------------------------------------
+ 
+ First, allocate the info struct::
+ 
+@@ -77,8 +77,8 @@ An example of usage can be seen in the probe function of [#f2]_.
+ .. [#f1] ../devicetree/bindings/fpga/fpga-region.txt
+ .. [#f2] ../../drivers/fpga/of-fpga-region.c
+ 
+-API to program a FGPA
+----------------------
++API to program an FPGA
++----------------------
+ 
+ .. kernel-doc:: drivers/fpga/fpga-region.c
+    :functions: fpga_region_program_fpga
+diff --git a/Documentation/driver-api/fpga/intro.rst b/Documentation/driver-api/fpga/intro.rst
+index 51cd81dbb4dc..50d1cab84950 100644
+--- a/Documentation/driver-api/fpga/intro.rst
++++ b/Documentation/driver-api/fpga/intro.rst
+@@ -12,18 +12,18 @@ Linux.  Some of the core intentions of the FPGA subsystems are:
+ 
+ * Code should not be shared between upper and lower layers.  This
+   should go without saying.  If that seems necessary, there's probably
+-  framework functionality that that can be added that will benefit
++  framework functionality that can be added that will benefit
+   other users.  Write the linux-fpga mailing list and maintainers and
+   seek out a solution that expands the framework for broad reuse.
+ 
+-* Generally, when adding code, think of the future.  Plan for re-use.
++* Generally, when adding code, think of the future.  Plan for reuse.
+ 
+ The framework in the kernel is divided into:
+ 
+ FPGA Manager
+ ------------
+ 
+-If you are adding a new FPGA or a new method of programming a FPGA,
++If you are adding a new FPGA or a new method of programming an FPGA,
+ this is the subsystem for you.  Low level FPGA manager drivers contain
+ the knowledge of how to program a specific device.  This subsystem
+ includes the framework in fpga-mgr.c and the low level drivers that
+@@ -32,10 +32,10 @@ are registered with it.
+ FPGA Bridge
+ -----------
+ 
+-FPGA Bridges prevent spurious signals from going out of a FPGA or a
+-region of a FPGA during programming.  They are disabled before
++FPGA Bridges prevent spurious signals from going out of an FPGA or a
++region of an FPGA during programming.  They are disabled before
+ programming begins and re-enabled afterwards.  An FPGA bridge may be
+-actual hard hardware that gates a bus to a cpu or a soft ("freeze")
++actual hard hardware that gates a bus to a CPU or a soft ("freeze")
+ bridge in FPGA fabric that surrounds a partial reconfiguration region
+ of an FPGA.  This subsystem includes fpga-bridge.c and the low level
+ drivers that are registered with it.
+@@ -44,7 +44,7 @@ FPGA Region
+ -----------
+ 
+ If you are adding a new interface to the FPGA framework, add it on top
+-of a FPGA region to allow the most reuse of your interface.
++of an FPGA region to allow the most reuse of your interface.
+ 
+ The FPGA Region framework (fpga-region.c) associates managers and
+ bridges as reconfigurable regions.  A region may refer to the whole
+-- 
+2.19.0
+
diff --git a/patches/1703-fpga-mgr-add-region_id-to-fpga_image_info.patch b/patches/1703-fpga-mgr-add-region_id-to-fpga_image_info.patch
new file mode 100644
index 00000000000000..286f5943f4a9b7
--- /dev/null
+++ b/patches/1703-fpga-mgr-add-region_id-to-fpga_image_info.patch
@@ -0,0 +1,42 @@
+From 0ed39a042d750480945a2096d5f95205a63576d4 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:09 +0800
+Subject: [PATCH 1703/1795] fpga: mgr: add region_id to fpga_image_info
+
+This patch adds region_id to fpga_image_info data structure, it
+allows driver to pass region id information to fpga-mgr via
+fpga_image_info for fpga reconfiguration function.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 571d78bd458a831cf51dff2afa1dda3309bd82b2)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/fpga/fpga-mgr.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index eec7c2478b0d..3eb6b9d60d65 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -77,6 +77,7 @@ enum fpga_mgr_states {
+  * @sgt: scatter/gather table containing FPGA image
+  * @buf: contiguous buffer containing FPGA image
+  * @count: size of buf
++ * @region_id: id of target region
+  * @dev: device that owns this
+  * @overlay: Device Tree overlay
+  */
+@@ -89,6 +90,7 @@ struct fpga_image_info {
+ 	struct sg_table *sgt;
+ 	const char *buf;
+ 	size_t count;
++	int region_id;
+ 	struct device *dev;
+ #ifdef CONFIG_OF
+ 	struct device_node *overlay;
+-- 
+2.19.0
+
diff --git a/patches/1704-fpga-mgr-add-status-for-fpga-manager.patch b/patches/1704-fpga-mgr-add-status-for-fpga-manager.patch
new file mode 100644
index 00000000000000..89d42215534a18
--- /dev/null
+++ b/patches/1704-fpga-mgr-add-status-for-fpga-manager.patch
@@ -0,0 +1,142 @@
+From 0cbae715d3e981708a6edb52c8d32c88b89ace1e Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:10 +0800
+Subject: [PATCH 1704/1795] fpga: mgr: add status for fpga-manager
+
+This patch adds status sysfs interface for fpga manager, it's a
+read only interface which allows user to get fpga manager status,
+including full/partial reconfiguration error and other status
+information. It adds a status callback to fpga_manager_ops too,
+allows each fpga_manager driver to define its own method to
+collect latest status from hardware.
+
+The following sysfs file is created:
+* /sys/class/fpga_manager/<fpga>/status
+  Return status of fpga manager, including reconfiguration errors.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit ecb5fbe299dfaad778033259f35bc696fa1fb743)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-class-fpga-manager      | 24 ++++++++++++++++
+ drivers/fpga/fpga-mgr.c                       | 28 +++++++++++++++++++
+ include/linux/fpga/fpga-mgr.h                 |  9 ++++++
+ 3 files changed, 61 insertions(+)
+
+diff --git a/Documentation/ABI/testing/sysfs-class-fpga-manager b/Documentation/ABI/testing/sysfs-class-fpga-manager
+index 23056c532fdd..5284fa33d4c5 100644
+--- a/Documentation/ABI/testing/sysfs-class-fpga-manager
++++ b/Documentation/ABI/testing/sysfs-class-fpga-manager
+@@ -35,3 +35,27 @@ Description:	Read fpga manager state as a string.
+ 		* write complete	= Doing post programming steps
+ 		* write complete error	= Error while doing post programming
+ 		* operating		= FPGA is programmed and operating
++
++What:		/sys/class/fpga_manager/<fpga>/status
++Date:		June 2018
++KernelVersion:	4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read fpga manager status as a string.
++		If FPGA programming operation fails, it could be caused by crc
++		error or incompatible bitstream image. The intent of this
++		interface is to provide more detailed information for FPGA
++		programming errors to userspace. This is a list of strings for
++		the supported status.
++
++		* reconfig operation error 	- invalid operations detected by
++						  reconfiguration hardware.
++						  e.g. start reconfiguration
++						  with errors not cleared
++		* reconfig CRC error		- CRC error detected by
++						  reconfiguration hardware.
++		* reconfig incompatible image	- reconfiguration image is
++						  incompatible with hardware
++		* reconfig IP protocol error	- protocol errors detected by
++						  reconfiguration hardware
++		* reconfig fifo overflow error	- FIFO overflow detected by
++						  reconfiguration hardware
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
+index c1564cf827fe..a41b07e37884 100644
+--- a/drivers/fpga/fpga-mgr.c
++++ b/drivers/fpga/fpga-mgr.c
+@@ -406,12 +406,40 @@ static ssize_t state_show(struct device *dev,
+ 	return sprintf(buf, "%s\n", state_str[mgr->state]);
+ }
+ 
++static ssize_t status_show(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct fpga_manager *mgr = to_fpga_manager(dev);
++	u64 status;
++	int len = 0;
++
++	if (!mgr->mops->status)
++		return -ENOENT;
++
++	status = mgr->mops->status(mgr);
++
++	if (status & FPGA_MGR_STATUS_OPERATION_ERR)
++		len += sprintf(buf + len, "reconfig operation error\n");
++	if (status & FPGA_MGR_STATUS_CRC_ERR)
++		len += sprintf(buf + len, "reconfig CRC error\n");
++	if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR)
++		len += sprintf(buf + len, "reconfig incompatible image\n");
++	if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR)
++		len += sprintf(buf + len, "reconfig IP protocol error\n");
++	if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR)
++		len += sprintf(buf + len, "reconfig fifo overflow error\n");
++
++	return len;
++}
++
+ static DEVICE_ATTR_RO(name);
+ static DEVICE_ATTR_RO(state);
++static DEVICE_ATTR_RO(status);
+ 
+ static struct attribute *fpga_mgr_attrs[] = {
+ 	&dev_attr_name.attr,
+ 	&dev_attr_state.attr,
++	&dev_attr_status.attr,
+ 	NULL,
+ };
+ ATTRIBUTE_GROUPS(fpga_mgr);
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index 3eb6b9d60d65..e249b7250345 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -101,6 +101,7 @@ struct fpga_image_info {
+  * struct fpga_manager_ops - ops for low level fpga manager drivers
+  * @initial_header_size: Maximum number of bytes that should be passed into write_init
+  * @state: returns an enum value of the FPGA's state
++ * @status: returns status of the FPGA, including reconfiguration error code
+  * @write_init: prepare the FPGA to receive confuration data
+  * @write: write count bytes of configuration data to the FPGA
+  * @write_sg: write the scatter list of configuration data to the FPGA
+@@ -115,6 +116,7 @@ struct fpga_image_info {
+ struct fpga_manager_ops {
+ 	size_t initial_header_size;
+ 	enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
++	u64 (*status)(struct fpga_manager *mgr);
+ 	int (*write_init)(struct fpga_manager *mgr,
+ 			  struct fpga_image_info *info,
+ 			  const char *buf, size_t count);
+@@ -126,6 +128,13 @@ struct fpga_manager_ops {
+ 	const struct attribute_group **groups;
+ };
+ 
++/* FPGA manager status: Partial/Full Reconfiguration errors */
++#define FPGA_MGR_STATUS_OPERATION_ERR		BIT(0)
++#define FPGA_MGR_STATUS_CRC_ERR			BIT(1)
++#define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR	BIT(2)
++#define FPGA_MGR_STATUS_IP_PROTOCOL_ERR		BIT(3)
++#define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR	BIT(4)
++
+ /**
+  * struct fpga_manager - fpga manager structure
+  * @name: name of low level fpga manager
+-- 
+2.19.0
+
diff --git a/patches/1705-fpga-mgr-add-compat_id-support.patch b/patches/1705-fpga-mgr-add-compat_id-support.patch
new file mode 100644
index 00000000000000..25c50b3b41206f
--- /dev/null
+++ b/patches/1705-fpga-mgr-add-compat_id-support.patch
@@ -0,0 +1,60 @@
+From 86c687d1379955d95f762b643ae5b23648e4b5b3 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:11 +0800
+Subject: [PATCH 1705/1795] fpga: mgr: add compat_id support
+
+This patch introduces compat_id support to fpga manager, it adds
+a fpga_compat_id pointer to fpga manager data structure to allow
+fpga manager drivers to save the compatibility id. This compat_id
+could be used for compatibility checking before doing partial
+reconfiguration to associated fpga regions.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 99a560bde313892f87ca81db568a829d3d205882)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/fpga/fpga-mgr.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
+index e249b7250345..8942e61f0028 100644
+--- a/include/linux/fpga/fpga-mgr.h
++++ b/include/linux/fpga/fpga-mgr.h
+@@ -135,12 +135,24 @@ struct fpga_manager_ops {
+ #define FPGA_MGR_STATUS_IP_PROTOCOL_ERR		BIT(3)
+ #define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR	BIT(4)
+ 
++/**
++ * struct fpga_compat_id - id for compatibility check
++ *
++ * @id_h: high 64bit of the compat_id
++ * @id_l: low 64bit of the compat_id
++ */
++struct fpga_compat_id {
++	u64 id_h;
++	u64 id_l;
++};
++
+ /**
+  * struct fpga_manager - fpga manager structure
+  * @name: name of low level fpga manager
+  * @dev: fpga manager device
+  * @ref_mutex: only allows one reference to fpga manager
+  * @state: state of fpga manager
++ * @compat_id: FPGA manager id for compatibility check.
+  * @mops: pointer to struct of fpga manager ops
+  * @priv: low level driver private date
+  */
+@@ -149,6 +161,7 @@ struct fpga_manager {
+ 	struct device dev;
+ 	struct mutex ref_mutex;
+ 	enum fpga_mgr_states state;
++	struct fpga_compat_id *compat_id;
+ 	const struct fpga_manager_ops *mops;
+ 	void *priv;
+ };
+-- 
+2.19.0
+
diff --git a/patches/1706-fpga-region-add-compat_id-support.patch b/patches/1706-fpga-region-add-compat_id-support.patch
new file mode 100644
index 00000000000000..08c32e32de4a19
--- /dev/null
+++ b/patches/1706-fpga-region-add-compat_id-support.patch
@@ -0,0 +1,101 @@
+From d05c229ff779cce9a05db05c3fa4c74e72f75590 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:12 +0800
+Subject: [PATCH 1706/1795] fpga: region: add compat_id support
+
+This patch introduces a compat_id pointer member and sysfs interface
+for each fpga region, similar as compat_id for fpga manager, it allows
+applications to read the per region compat_id for compatibility
+checking before other actions on this fpga-region (e.g. PR).
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 41a8b2c56470b7e4e3e2db93324d50bbbf60cdc4)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-class-fpga-region       |  9 ++++++++
+ drivers/fpga/fpga-region.c                    | 22 +++++++++++++++++++
+ include/linux/fpga/fpga-region.h              |  2 ++
+ 3 files changed, 33 insertions(+)
+ create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-region
+
+diff --git a/Documentation/ABI/testing/sysfs-class-fpga-region b/Documentation/ABI/testing/sysfs-class-fpga-region
+new file mode 100644
+index 000000000000..bc7ec644acc9
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-class-fpga-region
+@@ -0,0 +1,9 @@
++What:		/sys/class/fpga_region/<region>/compat_id
++Date:		June 2018
++KernelVersion:	4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	FPGA region id for compatibility check, e.g. compatibility
++		of the FPGA reconfiguration hardware and image. This value
++		is defined or calculated by the layer that is creating the
++		FPGA region. This interface returns the compat_id value or
++		just error code -ENOENT in case compat_id is not used.
+diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
+index 6d214d75c7be..0d65220d5ec5 100644
+--- a/drivers/fpga/fpga-region.c
++++ b/drivers/fpga/fpga-region.c
+@@ -158,6 +158,27 @@ int fpga_region_program_fpga(struct fpga_region *region)
+ }
+ EXPORT_SYMBOL_GPL(fpga_region_program_fpga);
+ 
++static ssize_t compat_id_show(struct device *dev,
++			      struct device_attribute *attr, char *buf)
++{
++	struct fpga_region *region = to_fpga_region(dev);
++
++	if (!region->compat_id)
++		return -ENOENT;
++
++	return sprintf(buf, "%016llx%016llx\n",
++		       (unsigned long long)region->compat_id->id_h,
++		       (unsigned long long)region->compat_id->id_l);
++}
++
++static DEVICE_ATTR_RO(compat_id);
++
++static struct attribute *fpga_region_attrs[] = {
++	&dev_attr_compat_id.attr,
++	NULL,
++};
++ATTRIBUTE_GROUPS(fpga_region);
++
+ /**
+  * fpga_region_create - alloc and init a struct fpga_region
+  * @dev: device parent
+@@ -258,6 +279,7 @@ static int __init fpga_region_init(void)
+ 	if (IS_ERR(fpga_region_class))
+ 		return PTR_ERR(fpga_region_class);
+ 
++	fpga_region_class->dev_groups = fpga_region_groups;
+ 	fpga_region_class->dev_release = fpga_region_dev_release;
+ 
+ 	return 0;
+diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h
+index d7071cddd727..0521b7f577a4 100644
+--- a/include/linux/fpga/fpga-region.h
++++ b/include/linux/fpga/fpga-region.h
+@@ -14,6 +14,7 @@
+  * @bridge_list: list of FPGA bridges specified in region
+  * @mgr: FPGA manager
+  * @info: FPGA image info
++ * @compat_id: FPGA region id for compatibility check.
+  * @priv: private data
+  * @get_bridges: optional function to get bridges to a list
+  */
+@@ -23,6 +24,7 @@ struct fpga_region {
+ 	struct list_head bridge_list;
+ 	struct fpga_manager *mgr;
+ 	struct fpga_image_info *info;
++	struct fpga_compat_id *compat_id;
+ 	void *priv;
+ 	int (*get_bridges)(struct fpga_region *region);
+ };
+-- 
+2.19.0
+
diff --git a/patches/1707-fpga-add-device-feature-list-support.patch b/patches/1707-fpga-add-device-feature-list-support.patch
new file mode 100644
index 00000000000000..78d5c240736314
--- /dev/null
+++ b/patches/1707-fpga-add-device-feature-list-support.patch
@@ -0,0 +1,1110 @@
+From 341060ad4b8bc1fecfbfeba59bf51914c95980a1 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:13 +0800
+Subject: [PATCH 1707/1795] fpga: add device feature list support
+
+Device Feature List (DFL) defines a feature list structure that creates
+a linked list of feature headers within the MMIO space to provide an
+extensible way of adding features. This patch introduces a kernel module
+to provide basic infrastructure to support FPGA devices which implement
+the Device Feature List.
+
+Usually there will be different features and their sub features linked into
+the DFL. This code provides common APIs for feature enumeration, it creates
+a container device (FPGA base region), walks through the DFLs and creates
+platform devices for feature devices (Currently it only supports two
+different feature devices, FPGA Management Engine (FME) and Port which
+the Accelerator Function Unit (AFU) connected to). In order to enumerate
+the DFLs, the common APIs required low level driver to provide necessary
+enumeration information (e.g. address for each device feature list for
+given device) and fill it to the dfl_fpga_enum_info data structure. Please
+refer to below description for APIs added for enumeration.
+
+Functions for enumeration information preparation:
+ *dfl_fpga_enum_info_alloc
+   allocate enumeration information data structure.
+
+ *dfl_fpga_enum_info_add_dfl
+   add a device feature list to dfl_fpga_enum_info data structure.
+
+ *dfl_fpga_enum_info_free
+   free dfl_fpga_enum_info data structure and related resources.
+
+Functions for feature device enumeration:
+ *dfl_fpga_feature_devs_enumerate
+   enumerate feature devices and return container device.
+
+ *dfl_fpga_feature_devs_remove
+   remove feature devices under given container device.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 543be3d8c999b30e1e1c05d30c1ea3f2d922340b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig  |  16 +
+ drivers/fpga/Makefile |   3 +
+ drivers/fpga/dfl.c    | 721 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/fpga/dfl.h    | 279 ++++++++++++++++
+ 4 files changed, 1019 insertions(+)
+ create mode 100644 drivers/fpga/dfl.c
+ create mode 100644 drivers/fpga/dfl.h
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index ee9c5420c47f..4880fd676a19 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -130,4 +130,20 @@ config OF_FPGA_REGION
+ 	  Support for loading FPGA images by applying a Device Tree
+ 	  overlay.
+ 
++config FPGA_DFL
++	tristate "FPGA Device Feature List (DFL) support"
++	select FPGA_BRIDGE
++	select FPGA_REGION
++	help
++	  Device Feature List (DFL) defines a feature list structure that
++	  creates a linked list of feature headers within the MMIO space
++	  to provide an extensible way of adding features for FPGA.
++	  Driver can walk through the feature headers to enumerate feature
++	  devices (e.g. FPGA Management Engine, Port and Accelerator
++	  Function Unit) and their private features for target FPGA devices.
++
++	  Select this option to enable common support for Field-Programmable
++	  Gate Array (FPGA) solutions which implement Device Feature List.
++	  It provides enumeration APIs and feature device infrastructure.
++
+ endif # FPGA
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index f9803dad6919..7a7a11739e00 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -28,3 +28,6 @@ obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
+ # High Level Interfaces
+ obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
+ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
++
++# FPGA Device Feature List Support
++obj-$(CONFIG_FPGA_DFL)			+= dfl.o
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+new file mode 100644
+index 000000000000..d1dff360ea14
+--- /dev/null
++++ b/drivers/fpga/dfl.c
+@@ -0,0 +1,721 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Device Feature List (DFL) Support
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Zhang Yi <yi.z.zhang@intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ */
++#include <linux/module.h>
++
++#include "dfl.h"
++
++static DEFINE_MUTEX(dfl_id_mutex);
++
++/*
++ * when adding a new feature dev support in DFL framework, it's required to
++ * add a new item in enum dfl_id_type and provide related information in below
++ * dfl_devs table which is indexed by dfl_id_type, e.g. name string used for
++ * platform device creation (define name strings in dfl.h, as they could be
++ * reused by platform device drivers).
++ */
++enum dfl_id_type {
++	FME_ID,		/* fme id allocation and mapping */
++	PORT_ID,	/* port id allocation and mapping */
++	DFL_ID_MAX,
++};
++
++/**
++ * dfl_dev_info - dfl feature device information.
++ * @name: name string of the feature platform device.
++ * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec.
++ * @id: idr id of the feature dev.
++ */
++struct dfl_dev_info {
++	const char *name;
++	u32 dfh_id;
++	struct idr id;
++};
++
++/* it is indexed by dfl_id_type */
++static struct dfl_dev_info dfl_devs[] = {
++	{.name = DFL_FPGA_FEATURE_DEV_FME, .dfh_id = DFH_ID_FIU_FME},
++	{.name = DFL_FPGA_FEATURE_DEV_PORT, .dfh_id = DFH_ID_FIU_PORT},
++};
++
++static void dfl_ids_init(void)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
++		idr_init(&dfl_devs[i].id);
++}
++
++static void dfl_ids_destroy(void)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
++		idr_destroy(&dfl_devs[i].id);
++}
++
++static int dfl_id_alloc(enum dfl_id_type type, struct device *dev)
++{
++	int id;
++
++	WARN_ON(type >= DFL_ID_MAX);
++	mutex_lock(&dfl_id_mutex);
++	id = idr_alloc(&dfl_devs[type].id, dev, 0, 0, GFP_KERNEL);
++	mutex_unlock(&dfl_id_mutex);
++
++	return id;
++}
++
++static void dfl_id_free(enum dfl_id_type type, int id)
++{
++	WARN_ON(type >= DFL_ID_MAX);
++	mutex_lock(&dfl_id_mutex);
++	idr_remove(&dfl_devs[type].id, id);
++	mutex_unlock(&dfl_id_mutex);
++}
++
++static enum dfl_id_type feature_dev_id_type(struct platform_device *pdev)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
++		if (!strcmp(dfl_devs[i].name, pdev->name))
++			return i;
++
++	return DFL_ID_MAX;
++}
++
++static enum dfl_id_type dfh_id_to_type(u32 id)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dfl_devs); i++)
++		if (dfl_devs[i].dfh_id == id)
++			return i;
++
++	return DFL_ID_MAX;
++}
++
++/**
++ * struct build_feature_devs_info - info collected during feature dev build.
++ *
++ * @dev: device to enumerate.
++ * @cdev: the container device for all feature devices.
++ * @feature_dev: current feature device.
++ * @ioaddr: header register region address of feature device in enumeration.
++ * @sub_features: a sub features linked list for feature device in enumeration.
++ * @feature_num: number of sub features for feature device in enumeration.
++ */
++struct build_feature_devs_info {
++	struct device *dev;
++	struct dfl_fpga_cdev *cdev;
++	struct platform_device *feature_dev;
++	void __iomem *ioaddr;
++	struct list_head sub_features;
++	int feature_num;
++};
++
++/**
++ * struct dfl_feature_info - sub feature info collected during feature dev build
++ *
++ * @fid: id of this sub feature.
++ * @mmio_res: mmio resource of this sub feature.
++ * @ioaddr: mapped base address of mmio resource.
++ * @node: node in sub_features linked list.
++ */
++struct dfl_feature_info {
++	u64 fid;
++	struct resource mmio_res;
++	void __iomem *ioaddr;
++	struct list_head node;
++};
++
++static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev,
++				       struct platform_device *port)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&port->dev);
++
++	mutex_lock(&cdev->lock);
++	list_add(&pdata->node, &cdev->port_dev_list);
++	get_device(&pdata->dev->dev);
++	mutex_unlock(&cdev->lock);
++}
++
++/*
++ * register current feature device, it is called when we need to switch to
++ * another feature parsing or we have parsed all features on given device
++ * feature list.
++ */
++static int build_info_commit_dev(struct build_feature_devs_info *binfo)
++{
++	struct platform_device *fdev = binfo->feature_dev;
++	struct dfl_feature_platform_data *pdata;
++	struct dfl_feature_info *finfo, *p;
++	int ret, index = 0;
++
++	if (!fdev)
++		return 0;
++
++	/*
++	 * we do not need to care for the memory which is associated with
++	 * the platform device. After calling platform_device_unregister(),
++	 * it will be automatically freed by device's release() callback,
++	 * platform_device_release().
++	 */
++	pdata = kzalloc(dfl_feature_platform_data_size(binfo->feature_num),
++			GFP_KERNEL);
++	if (!pdata)
++		return -ENOMEM;
++
++	pdata->dev = fdev;
++	pdata->num = binfo->feature_num;
++	pdata->dfl_cdev = binfo->cdev;
++	mutex_init(&pdata->lock);
++
++	/*
++	 * the count should be initialized to 0 to make sure
++	 *__fpga_port_enable() following __fpga_port_disable()
++	 * works properly for port device.
++	 * and it should always be 0 for fme device.
++	 */
++	WARN_ON(pdata->disable_count);
++
++	fdev->dev.platform_data = pdata;
++
++	/* each sub feature has one MMIO resource */
++	fdev->num_resources = binfo->feature_num;
++	fdev->resource = kcalloc(binfo->feature_num, sizeof(*fdev->resource),
++				 GFP_KERNEL);
++	if (!fdev->resource)
++		return -ENOMEM;
++
++	/* fill features and resource information for feature dev */
++	list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
++		struct dfl_feature *feature = &pdata->features[index];
++
++		/* save resource information for each feature */
++		feature->id = finfo->fid;
++		feature->resource_index = index;
++		feature->ioaddr = finfo->ioaddr;
++		fdev->resource[index++] = finfo->mmio_res;
++
++		list_del(&finfo->node);
++		kfree(finfo);
++	}
++
++	ret = platform_device_add(binfo->feature_dev);
++	if (!ret) {
++		if (feature_dev_id_type(binfo->feature_dev) == PORT_ID)
++			dfl_fpga_cdev_add_port_dev(binfo->cdev,
++						   binfo->feature_dev);
++		else
++			binfo->cdev->fme_dev =
++					get_device(&binfo->feature_dev->dev);
++		/*
++		 * reset it to avoid build_info_free() freeing their resource.
++		 *
++		 * The resource of successfully registered feature devices
++		 * will be freed by platform_device_unregister(). See the
++		 * comments in build_info_create_dev().
++		 */
++		binfo->feature_dev = NULL;
++	}
++
++	return ret;
++}
++
++static int
++build_info_create_dev(struct build_feature_devs_info *binfo,
++		      enum dfl_id_type type, void __iomem *ioaddr)
++{
++	struct platform_device *fdev;
++	int ret;
++
++	if (type >= DFL_ID_MAX)
++		return -EINVAL;
++
++	/* we will create a new device, commit current device first */
++	ret = build_info_commit_dev(binfo);
++	if (ret)
++		return ret;
++
++	/*
++	 * we use -ENODEV as the initialization indicator which indicates
++	 * whether the id need to be reclaimed
++	 */
++	fdev = platform_device_alloc(dfl_devs[type].name, -ENODEV);
++	if (!fdev)
++		return -ENOMEM;
++
++	binfo->feature_dev = fdev;
++	binfo->feature_num = 0;
++	binfo->ioaddr = ioaddr;
++	INIT_LIST_HEAD(&binfo->sub_features);
++
++	fdev->id = dfl_id_alloc(type, &fdev->dev);
++	if (fdev->id < 0)
++		return fdev->id;
++
++	fdev->dev.parent = &binfo->cdev->region->dev;
++
++	return 0;
++}
++
++static void build_info_free(struct build_feature_devs_info *binfo)
++{
++	struct dfl_feature_info *finfo, *p;
++
++	/*
++	 * it is a valid id, free it. See comments in
++	 * build_info_create_dev()
++	 */
++	if (binfo->feature_dev && binfo->feature_dev->id >= 0) {
++		dfl_id_free(feature_dev_id_type(binfo->feature_dev),
++			    binfo->feature_dev->id);
++
++		list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
++			list_del(&finfo->node);
++			kfree(finfo);
++		}
++	}
++
++	platform_device_put(binfo->feature_dev);
++
++	devm_kfree(binfo->dev, binfo);
++}
++
++static inline u32 feature_size(void __iomem *start)
++{
++	u64 v = readq(start + DFH);
++	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
++	/* workaround for private features with invalid size, use 4K instead */
++	return ofst ? ofst : 4096;
++}
++
++static u64 feature_id(void __iomem *start)
++{
++	u64 v = readq(start + DFH);
++	u16 id = FIELD_GET(DFH_ID, v);
++	u8 type = FIELD_GET(DFH_TYPE, v);
++
++	if (type == DFH_TYPE_FIU)
++		return FEATURE_ID_FIU_HEADER;
++	else if (type == DFH_TYPE_PRIVATE)
++		return id;
++	else if (type == DFH_TYPE_AFU)
++		return FEATURE_ID_AFU;
++
++	WARN_ON(1);
++	return 0;
++}
++
++/*
++ * when create sub feature instances, for private features, it doesn't need
++ * to provide resource size and feature id as they could be read from DFH
++ * register. For afu sub feature, its register region only contains user
++ * defined registers, so never trust any information from it, just use the
++ * resource size information provided by its parent FIU.
++ */
++static int
++create_feature_instance(struct build_feature_devs_info *binfo,
++			struct dfl_fpga_enum_dfl *dfl, resource_size_t ofst,
++			resource_size_t size, u64 fid)
++{
++	struct dfl_feature_info *finfo;
++
++	/* read feature size and id if inputs are invalid */
++	size = size ? size : feature_size(dfl->ioaddr + ofst);
++	fid = fid ? fid : feature_id(dfl->ioaddr + ofst);
++
++	if (dfl->len - ofst < size)
++		return -EINVAL;
++
++	finfo = kzalloc(sizeof(*finfo), GFP_KERNEL);
++	if (!finfo)
++		return -ENOMEM;
++
++	finfo->fid = fid;
++	finfo->mmio_res.start = dfl->start + ofst;
++	finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
++	finfo->mmio_res.flags = IORESOURCE_MEM;
++	finfo->ioaddr = dfl->ioaddr + ofst;
++
++	list_add_tail(&finfo->node, &binfo->sub_features);
++	binfo->feature_num++;
++
++	return 0;
++}
++
++static int parse_feature_port_afu(struct build_feature_devs_info *binfo,
++				  struct dfl_fpga_enum_dfl *dfl,
++				  resource_size_t ofst)
++{
++	u64 v = readq(binfo->ioaddr + PORT_HDR_CAP);
++	u32 size = FIELD_GET(PORT_CAP_MMIO_SIZE, v) << 10;
++
++	WARN_ON(!size);
++
++	return create_feature_instance(binfo, dfl, ofst, size, FEATURE_ID_AFU);
++}
++
++static int parse_feature_afu(struct build_feature_devs_info *binfo,
++			     struct dfl_fpga_enum_dfl *dfl,
++			     resource_size_t ofst)
++{
++	if (!binfo->feature_dev) {
++		dev_err(binfo->dev, "this AFU does not belong to any FIU.\n");
++		return -EINVAL;
++	}
++
++	switch (feature_dev_id_type(binfo->feature_dev)) {
++	case PORT_ID:
++		return parse_feature_port_afu(binfo, dfl, ofst);
++	default:
++		dev_info(binfo->dev, "AFU belonging to FIU %s is not supported yet.\n",
++			 binfo->feature_dev->name);
++	}
++
++	return 0;
++}
++
++static int parse_feature_fiu(struct build_feature_devs_info *binfo,
++			     struct dfl_fpga_enum_dfl *dfl,
++			     resource_size_t ofst)
++{
++	u32 id, offset;
++	u64 v;
++	int ret = 0;
++
++	v = readq(dfl->ioaddr + ofst + DFH);
++	id = FIELD_GET(DFH_ID, v);
++
++	/* create platform device for dfl feature dev */
++	ret = build_info_create_dev(binfo, dfh_id_to_type(id),
++				    dfl->ioaddr + ofst);
++	if (ret)
++		return ret;
++
++	ret = create_feature_instance(binfo, dfl, ofst, 0, 0);
++	if (ret)
++		return ret;
++	/*
++	 * find and parse FIU's child AFU via its NEXT_AFU register.
++	 * please note that only Port has valid NEXT_AFU pointer per spec.
++	 */
++	v = readq(dfl->ioaddr + ofst + NEXT_AFU);
++
++	offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v);
++	if (offset)
++		return parse_feature_afu(binfo, dfl, ofst + offset);
++
++	dev_dbg(binfo->dev, "No AFUs detected on FIU %d\n", id);
++
++	return ret;
++}
++
++static int parse_feature_private(struct build_feature_devs_info *binfo,
++				 struct dfl_fpga_enum_dfl *dfl,
++				 resource_size_t ofst)
++{
++	if (!binfo->feature_dev) {
++		dev_err(binfo->dev, "the private feature %llx does not belong to any AFU.\n",
++			(unsigned long long)feature_id(dfl->ioaddr + ofst));
++		return -EINVAL;
++	}
++
++	return create_feature_instance(binfo, dfl, ofst, 0, 0);
++}
++
++/**
++ * parse_feature - parse a feature on given device feature list
++ *
++ * @binfo: build feature devices information.
++ * @dfl: device feature list to parse
++ * @ofst: offset to feature header on this device feature list
++ */
++static int parse_feature(struct build_feature_devs_info *binfo,
++			 struct dfl_fpga_enum_dfl *dfl, resource_size_t ofst)
++{
++	u64 v;
++	u32 type;
++
++	v = readq(dfl->ioaddr + ofst + DFH);
++	type = FIELD_GET(DFH_TYPE, v);
++
++	switch (type) {
++	case DFH_TYPE_AFU:
++		return parse_feature_afu(binfo, dfl, ofst);
++	case DFH_TYPE_PRIVATE:
++		return parse_feature_private(binfo, dfl, ofst);
++	case DFH_TYPE_FIU:
++		return parse_feature_fiu(binfo, dfl, ofst);
++	default:
++		dev_info(binfo->dev,
++			 "Feature Type %x is not supported.\n", type);
++	}
++
++	return 0;
++}
++
++static int parse_feature_list(struct build_feature_devs_info *binfo,
++			      struct dfl_fpga_enum_dfl *dfl)
++{
++	void __iomem *start = dfl->ioaddr;
++	void __iomem *end = dfl->ioaddr + dfl->len;
++	int ret = 0;
++	u32 ofst = 0;
++	u64 v;
++
++	/* walk through the device feature list via DFH's next DFH pointer. */
++	for (; start < end; start += ofst) {
++		if (end - start < DFH_SIZE) {
++			dev_err(binfo->dev, "The region is too small to contain a feature.\n");
++			return -EINVAL;
++		}
++
++		ret = parse_feature(binfo, dfl, start - dfl->ioaddr);
++		if (ret)
++			return ret;
++
++		v = readq(start + DFH);
++		ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
++
++		/* stop parsing if EOL(End of List) is set or offset is 0 */
++		if ((v & DFH_EOL) || !ofst)
++			break;
++	}
++
++	/* commit current feature device when reach the end of list */
++	return build_info_commit_dev(binfo);
++}
++
++struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev)
++{
++	struct dfl_fpga_enum_info *info;
++
++	get_device(dev);
++
++	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
++	if (!info) {
++		put_device(dev);
++		return NULL;
++	}
++
++	info->dev = dev;
++	INIT_LIST_HEAD(&info->dfls);
++
++	return info;
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_alloc);
++
++void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info)
++{
++	struct dfl_fpga_enum_dfl *tmp, *dfl;
++	struct device *dev;
++
++	if (!info)
++		return;
++
++	dev = info->dev;
++
++	/* remove all device feature lists in the list. */
++	list_for_each_entry_safe(dfl, tmp, &info->dfls, node) {
++		list_del(&dfl->node);
++		devm_kfree(dev, dfl);
++	}
++
++	devm_kfree(dev, info);
++	put_device(dev);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_free);
++
++/**
++ * dfl_fpga_enum_info_add_dfl - add info of a device feature list to enum info
++ *
++ * @info: ptr to dfl_fpga_enum_info
++ * @start: mmio resource address of the device feature list.
++ * @len: mmio resource length of the device feature list.
++ * @ioaddr: mapped mmio resource address of the device feature list.
++ *
++ * One FPGA device may have one or more Device Feature Lists (DFLs), use this
++ * function to add information of each DFL to common data structure for next
++ * step enumeration.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
++			       resource_size_t start, resource_size_t len,
++			       void __iomem *ioaddr)
++{
++	struct dfl_fpga_enum_dfl *dfl;
++
++	dfl = devm_kzalloc(info->dev, sizeof(*dfl), GFP_KERNEL);
++	if (!dfl)
++		return -ENOMEM;
++
++	dfl->start = start;
++	dfl->len = len;
++	dfl->ioaddr = ioaddr;
++
++	list_add_tail(&dfl->node, &info->dfls);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_add_dfl);
++
++static int remove_feature_dev(struct device *dev, void *data)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	enum dfl_id_type type = feature_dev_id_type(pdev);
++	int id = pdev->id;
++
++	platform_device_unregister(pdev);
++
++	dfl_id_free(type, id);
++
++	return 0;
++}
++
++static void remove_feature_devs(struct dfl_fpga_cdev *cdev)
++{
++	device_for_each_child(&cdev->region->dev, NULL, remove_feature_dev);
++}
++
++/**
++ * dfl_fpga_feature_devs_enumerate - enumerate feature devices
++ * @info: information for enumeration.
++ *
++ * This function creates a container device (base FPGA region), enumerates
++ * feature devices based on the enumeration info and creates platform devices
++ * under the container device.
++ *
++ * Return: dfl_fpga_cdev struct on success, -errno on failure
++ */
++struct dfl_fpga_cdev *
++dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
++{
++	struct build_feature_devs_info *binfo;
++	struct dfl_fpga_enum_dfl *dfl;
++	struct dfl_fpga_cdev *cdev;
++	int ret = 0;
++
++	if (!info->dev)
++		return ERR_PTR(-ENODEV);
++
++	cdev = devm_kzalloc(info->dev, sizeof(*cdev), GFP_KERNEL);
++	if (!cdev)
++		return ERR_PTR(-ENOMEM);
++
++	cdev->region = fpga_region_create(info->dev, NULL, NULL);
++	if (!cdev->region) {
++		ret = -ENOMEM;
++		goto free_cdev_exit;
++	}
++
++	cdev->parent = info->dev;
++	mutex_init(&cdev->lock);
++	INIT_LIST_HEAD(&cdev->port_dev_list);
++
++	ret = fpga_region_register(cdev->region);
++	if (ret)
++		goto free_region_exit;
++
++	/* create and init build info for enumeration */
++	binfo = devm_kzalloc(info->dev, sizeof(*binfo), GFP_KERNEL);
++	if (!binfo) {
++		ret = -ENOMEM;
++		goto unregister_region_exit;
++	}
++
++	binfo->dev = info->dev;
++	binfo->cdev = cdev;
++
++	/*
++	 * start enumeration for all feature devices based on Device Feature
++	 * Lists.
++	 */
++	list_for_each_entry(dfl, &info->dfls, node) {
++		ret = parse_feature_list(binfo, dfl);
++		if (ret) {
++			remove_feature_devs(cdev);
++			build_info_free(binfo);
++			goto unregister_region_exit;
++		}
++	}
++
++	build_info_free(binfo);
++
++	return cdev;
++
++unregister_region_exit:
++	fpga_region_unregister(cdev->region);
++free_region_exit:
++	fpga_region_free(cdev->region);
++free_cdev_exit:
++	devm_kfree(info->dev, cdev);
++	return ERR_PTR(ret);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_enumerate);
++
++/**
++ * dfl_fpga_feature_devs_remove - remove all feature devices
++ * @cdev: fpga container device.
++ *
++ * Remove the container device and all feature devices under given container
++ * devices.
++ */
++void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev)
++{
++	struct dfl_feature_platform_data *pdata, *ptmp;
++
++	remove_feature_devs(cdev);
++
++	mutex_lock(&cdev->lock);
++	if (cdev->fme_dev) {
++		/* the fme should be unregistered. */
++		WARN_ON(device_is_registered(cdev->fme_dev));
++		put_device(cdev->fme_dev);
++	}
++
++	list_for_each_entry_safe(pdata, ptmp, &cdev->port_dev_list, node) {
++		struct platform_device *port_dev = pdata->dev;
++
++		/* the port should be unregistered. */
++		WARN_ON(device_is_registered(&port_dev->dev));
++		list_del(&pdata->node);
++		put_device(&port_dev->dev);
++	}
++	mutex_unlock(&cdev->lock);
++
++	fpga_region_unregister(cdev->region);
++	devm_kfree(cdev->parent, cdev);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_remove);
++
++static int __init dfl_fpga_init(void)
++{
++	dfl_ids_init();
++
++	return 0;
++}
++
++static void __exit dfl_fpga_exit(void)
++{
++	dfl_ids_destroy();
++}
++
++module_init(dfl_fpga_init);
++module_exit(dfl_fpga_exit);
++
++MODULE_DESCRIPTION("FPGA Device Feature List (DFL) Support");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+new file mode 100644
+index 000000000000..47ecb3bb6f61
+--- /dev/null
++++ b/drivers/fpga/dfl.h
+@@ -0,0 +1,279 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Driver Header File for FPGA Device Feature List (DFL) Support
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Zhang Yi <yi.z.zhang@intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ */
++
++#ifndef __FPGA_DFL_H
++#define __FPGA_DFL_H
++
++#include <linux/bitfield.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/iopoll.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/uuid.h>
++#include <linux/fpga/fpga-region.h>
++
++/* maximum supported number of ports */
++#define MAX_DFL_FPGA_PORT_NUM 4
++/* plus one for fme device */
++#define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)
++
++/* Reserved 0x0 for Header Group Register and 0xff for AFU */
++#define FEATURE_ID_FIU_HEADER		0x0
++#define FEATURE_ID_AFU			0xff
++
++#define FME_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
++#define FME_FEATURE_ID_THERMAL_MGMT	0x1
++#define FME_FEATURE_ID_POWER_MGMT	0x2
++#define FME_FEATURE_ID_GLOBAL_IPERF	0x3
++#define FME_FEATURE_ID_GLOBAL_ERR	0x4
++#define FME_FEATURE_ID_PR_MGMT		0x5
++#define FME_FEATURE_ID_HSSI		0x6
++#define FME_FEATURE_ID_GLOBAL_DPERF	0x7
++
++#define PORT_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
++#define PORT_FEATURE_ID_AFU		FEATURE_ID_AFU
++#define PORT_FEATURE_ID_ERROR		0x10
++#define PORT_FEATURE_ID_UMSG		0x11
++#define PORT_FEATURE_ID_UINT		0x12
++#define PORT_FEATURE_ID_STP		0x13
++
++/*
++ * Device Feature Header Register Set
++ *
++ * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
++ * For AFUs, they have DFH + GUID as common header registers.
++ * For private features, they only have DFH register as common header.
++ */
++#define DFH			0x0
++#define GUID_L			0x8
++#define GUID_H			0x10
++#define NEXT_AFU		0x18
++
++#define DFH_SIZE		0x8
++
++/* Device Feature Header Register Bitfield */
++#define DFH_ID			GENMASK_ULL(11, 0)	/* Feature ID */
++#define DFH_ID_FIU_FME		0
++#define DFH_ID_FIU_PORT		1
++#define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
++#define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
++#define DFH_EOL			BIT_ULL(40)		/* End of list */
++#define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
++#define DFH_TYPE_AFU		1
++#define DFH_TYPE_PRIVATE	3
++#define DFH_TYPE_FIU		4
++
++/* Next AFU Register Bitfield */
++#define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */
++
++/* FME Header Register Set */
++#define FME_HDR_DFH		DFH
++#define FME_HDR_GUID_L		GUID_L
++#define FME_HDR_GUID_H		GUID_H
++#define FME_HDR_NEXT_AFU	NEXT_AFU
++#define FME_HDR_CAP		0x30
++#define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
++#define FME_HDR_BITSTREAM_ID	0x60
++#define FME_HDR_BITSTREAM_MD	0x68
++
++/* FME Fab Capability Register Bitfield */
++#define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */
++#define FME_CAP_SOCKET_ID	BIT_ULL(8)		/* Socket ID */
++#define FME_CAP_PCIE0_LINK_AVL	BIT_ULL(12)		/* PCIE0 Link */
++#define FME_CAP_PCIE1_LINK_AVL	BIT_ULL(13)		/* PCIE1 Link */
++#define FME_CAP_COHR_LINK_AVL	BIT_ULL(14)		/* Coherent Link */
++#define FME_CAP_IOMMU_AVL	BIT_ULL(16)		/* IOMMU available */
++#define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
++#define FME_CAP_ADDR_WIDTH	GENMASK_ULL(29, 24)	/* Address bus width */
++#define FME_CAP_CACHE_SIZE	GENMASK_ULL(43, 32)	/* cache size in KB */
++#define FME_CAP_CACHE_ASSOC	GENMASK_ULL(47, 44)	/* Associativity */
++
++/* FME Port Offset Register Bitfield */
++/* Offset to port device feature header */
++#define FME_PORT_OFST_DFH_OFST	GENMASK_ULL(23, 0)
++/* PCI Bar ID for this port */
++#define FME_PORT_OFST_BAR_ID	GENMASK_ULL(34, 32)
++/* AFU MMIO access permission. 1 - VF, 0 - PF. */
++#define FME_PORT_OFST_ACC_CTRL	BIT_ULL(55)
++#define FME_PORT_OFST_ACC_PF	0
++#define FME_PORT_OFST_ACC_VF	1
++#define FME_PORT_OFST_IMP	BIT_ULL(60)
++
++/* PORT Header Register Set */
++#define PORT_HDR_DFH		DFH
++#define PORT_HDR_GUID_L		GUID_L
++#define PORT_HDR_GUID_H		GUID_H
++#define PORT_HDR_NEXT_AFU	NEXT_AFU
++#define PORT_HDR_CAP		0x30
++#define PORT_HDR_CTRL		0x38
++
++/* Port Capability Register Bitfield */
++#define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
++#define PORT_CAP_MMIO_SIZE	GENMASK_ULL(23, 8)	/* MMIO size in KB */
++#define PORT_CAP_SUPP_INT_NUM	GENMASK_ULL(35, 32)	/* Interrupts num */
++
++/* Port Control Register Bitfield */
++#define PORT_CTRL_SFTRST	BIT_ULL(0)		/* Port soft reset */
++/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
++#define PORT_CTRL_LATENCY	BIT_ULL(2)
++#define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */
++
++/**
++ * struct dfl_feature - sub feature of the feature devices
++ *
++ * @id: sub feature id.
++ * @resource_index: each sub feature has one mmio resource for its registers.
++ *		    this index is used to find its mmio resource from the
++ *		    feature dev (platform device)'s reources.
++ * @ioaddr: mapped mmio resource address.
++ */
++struct dfl_feature {
++	u64 id;
++	int resource_index;
++	void __iomem *ioaddr;
++};
++
++/**
++ * struct dfl_feature_platform_data - platform data for feature devices
++ *
++ * @node: node to link feature devs to container device's port_dev_list.
++ * @lock: mutex to protect platform data.
++ * @dev: ptr to platform device linked with this platform data.
++ * @dfl_cdev: ptr to container device.
++ * @disable_count: count for port disable.
++ * @num: number for sub features.
++ * @features: sub features of this feature dev.
++ */
++struct dfl_feature_platform_data {
++	struct list_head node;
++	struct mutex lock;
++	struct platform_device *dev;
++	struct dfl_fpga_cdev *dfl_cdev;
++	unsigned int disable_count;
++
++	int num;
++	struct dfl_feature features[0];
++};
++
++#define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
++#define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"
++
++static inline int dfl_feature_platform_data_size(const int num)
++{
++	return sizeof(struct dfl_feature_platform_data) +
++		num * sizeof(struct dfl_feature);
++}
++
++#define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
++	for ((feature) = (pdata)->features;				    \
++	   (feature) < (pdata)->features + (pdata)->num; (feature)++)
++
++static inline
++struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
++	struct dfl_feature *feature;
++
++	dfl_fpga_dev_for_each_feature(pdata, feature)
++		if (feature->id == id)
++			return feature;
++
++	return NULL;
++}
++
++static inline
++void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
++{
++	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
++
++	if (feature && feature->ioaddr)
++		return feature->ioaddr;
++
++	WARN_ON(1);
++	return NULL;
++}
++
++static inline bool dfl_feature_is_fme(void __iomem *base)
++{
++	u64 v = readq(base + DFH);
++
++	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
++		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
++}
++
++static inline bool dfl_feature_is_port(void __iomem *base)
++{
++	u64 v = readq(base + DFH);
++
++	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
++		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
++}
++
++/**
++ * struct dfl_fpga_enum_info - DFL FPGA enumeration information
++ *
++ * @dev: parent device.
++ * @dfls: list of device feature lists.
++ */
++struct dfl_fpga_enum_info {
++	struct device *dev;
++	struct list_head dfls;
++};
++
++/**
++ * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
++ *
++ * @start: base address of this device feature list.
++ * @len: size of this device feature list.
++ * @ioaddr: mapped base address of this device feature list.
++ * @node: node in list of device feature lists.
++ */
++struct dfl_fpga_enum_dfl {
++	resource_size_t start;
++	resource_size_t len;
++
++	void __iomem *ioaddr;
++
++	struct list_head node;
++};
++
++struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
++int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
++			       resource_size_t start, resource_size_t len,
++			       void __iomem *ioaddr);
++void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
++
++/**
++ * struct dfl_fpga_cdev - container device of DFL based FPGA
++ *
++ * @parent: parent device of this container device.
++ * @region: base fpga region.
++ * @fme_dev: FME feature device under this container device.
++ * @lock: mutex lock to protect the port device list.
++ * @port_dev_list: list of all port feature devices under this container device.
++ */
++struct dfl_fpga_cdev {
++	struct device *parent;
++	struct fpga_region *region;
++	struct device *fme_dev;
++	struct mutex lock;
++	struct list_head port_dev_list;
++};
++
++struct dfl_fpga_cdev *
++dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
++void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
++
++#endif /* __FPGA_DFL_H */
+-- 
+2.19.0
+
diff --git a/patches/1708-fpga-dfl-add-chardev-support-for-feature-devices.patch b/patches/1708-fpga-dfl-add-chardev-support-for-feature-devices.patch
new file mode 100644
index 00000000000000..ccc0659e2736ce
--- /dev/null
+++ b/patches/1708-fpga-dfl-add-chardev-support-for-feature-devices.patch
@@ -0,0 +1,256 @@
+From e87f61db0e5ecdd0eb4a35a1e3886f0d3ffa94f5 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:14 +0800
+Subject: [PATCH 1708/1795] fpga: dfl: add chardev support for feature devices
+
+For feature devices drivers, both the FPGA Management Engine (FME) and
+Accelerated Function Unit (AFU) driver need to expose user interfaces via
+the device file, for example, mmap and ioctls.
+
+This patch adds chardev support in the dfl driver for feature devices,
+FME and AFU. It reserves the chardev regions for FME and AFU and provide
+interfaces for FME and AFU driver to register their device file operations.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit b16c5147dc3b1a03405f58f6864b56f29ab7aaf9)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl.c | 125 +++++++++++++++++++++++++++++++++++++++++++--
+ drivers/fpga/dfl.h |   8 +++
+ 2 files changed, 130 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index d1dff360ea14..b56933c64371 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -22,6 +22,11 @@ static DEFINE_MUTEX(dfl_id_mutex);
+  * dfl_devs table which is indexed by dfl_id_type, e.g. name string used for
+  * platform device creation (define name strings in dfl.h, as they could be
+  * reused by platform device drivers).
++ *
++ * if the new feature dev needs chardev support, then it's required to add
++ * a new item in dfl_chardevs table and configure dfl_devs[i].devt_type as
++ * index to dfl_chardevs table. If no chardev support just set devt_type
++ * as one invalid index (DFL_FPGA_DEVT_MAX).
+  */
+ enum dfl_id_type {
+ 	FME_ID,		/* fme id allocation and mapping */
+@@ -29,22 +34,48 @@ enum dfl_id_type {
+ 	DFL_ID_MAX,
+ };
+ 
++enum dfl_fpga_devt_type {
++	DFL_FPGA_DEVT_FME,
++	DFL_FPGA_DEVT_PORT,
++	DFL_FPGA_DEVT_MAX,
++};
++
+ /**
+  * dfl_dev_info - dfl feature device information.
+  * @name: name string of the feature platform device.
+  * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec.
+  * @id: idr id of the feature dev.
++ * @devt_type: index to dfl_chrdevs[].
+  */
+ struct dfl_dev_info {
+ 	const char *name;
+ 	u32 dfh_id;
+ 	struct idr id;
++	enum dfl_fpga_devt_type devt_type;
+ };
+ 
+ /* it is indexed by dfl_id_type */
+ static struct dfl_dev_info dfl_devs[] = {
+-	{.name = DFL_FPGA_FEATURE_DEV_FME, .dfh_id = DFH_ID_FIU_FME},
+-	{.name = DFL_FPGA_FEATURE_DEV_PORT, .dfh_id = DFH_ID_FIU_PORT},
++	{.name = DFL_FPGA_FEATURE_DEV_FME, .dfh_id = DFH_ID_FIU_FME,
++	 .devt_type = DFL_FPGA_DEVT_FME},
++	{.name = DFL_FPGA_FEATURE_DEV_PORT, .dfh_id = DFH_ID_FIU_PORT,
++	 .devt_type = DFL_FPGA_DEVT_PORT},
++};
++
++/**
++ * dfl_chardev_info - chardev information of dfl feature device
++ * @name: nmae string of the char device.
++ * @devt: devt of the char device.
++ */
++struct dfl_chardev_info {
++	const char *name;
++	dev_t devt;
++};
++
++/* indexed by enum dfl_fpga_devt_type */
++static struct dfl_chardev_info dfl_chrdevs[] = {
++	{.name = DFL_FPGA_FEATURE_DEV_FME},
++	{.name = DFL_FPGA_FEATURE_DEV_PORT},
+ };
+ 
+ static void dfl_ids_init(void)
+@@ -105,6 +136,86 @@ static enum dfl_id_type dfh_id_to_type(u32 id)
+ 	return DFL_ID_MAX;
+ }
+ 
++static void dfl_chardev_uinit(void)
++{
++	int i;
++
++	for (i = 0; i < DFL_FPGA_DEVT_MAX; i++)
++		if (MAJOR(dfl_chrdevs[i].devt)) {
++			unregister_chrdev_region(dfl_chrdevs[i].devt,
++						 MINORMASK);
++			dfl_chrdevs[i].devt = MKDEV(0, 0);
++		}
++}
++
++static int dfl_chardev_init(void)
++{
++	int i, ret;
++
++	for (i = 0; i < DFL_FPGA_DEVT_MAX; i++) {
++		ret = alloc_chrdev_region(&dfl_chrdevs[i].devt, 0, MINORMASK,
++					  dfl_chrdevs[i].name);
++		if (ret)
++			goto exit;
++	}
++
++	return 0;
++
++exit:
++	dfl_chardev_uinit();
++	return ret;
++}
++
++static dev_t dfl_get_devt(enum dfl_fpga_devt_type type, int id)
++{
++	if (type >= DFL_FPGA_DEVT_MAX)
++		return 0;
++
++	return MKDEV(MAJOR(dfl_chrdevs[type].devt), id);
++}
++
++/**
++ * dfl_fpga_dev_ops_register - register cdev ops for feature dev
++ *
++ * @pdev: feature dev.
++ * @fops: file operations for feature dev's cdev.
++ * @owner: owning module/driver.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int dfl_fpga_dev_ops_register(struct platform_device *pdev,
++			      const struct file_operations *fops,
++			      struct module *owner)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++
++	cdev_init(&pdata->cdev, fops);
++	pdata->cdev.owner = owner;
++
++	/*
++	 * set parent to the feature device so that its refcount is
++	 * decreased after the last refcount of cdev is gone, that
++	 * makes sure the feature device is valid during device
++	 * file's life-cycle.
++	 */
++	pdata->cdev.kobj.parent = &pdev->dev.kobj;
++
++	return cdev_add(&pdata->cdev, pdev->dev.devt, 1);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_dev_ops_register);
++
++/**
++ * dfl_fpga_dev_ops_unregister - unregister cdev ops for feature dev
++ * @pdev: feature dev.
++ */
++void dfl_fpga_dev_ops_unregister(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++
++	cdev_del(&pdata->cdev);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_dev_ops_unregister);
++
+ /**
+  * struct build_feature_devs_info - info collected during feature dev build.
+  *
+@@ -266,6 +377,7 @@ build_info_create_dev(struct build_feature_devs_info *binfo,
+ 		return fdev->id;
+ 
+ 	fdev->dev.parent = &binfo->cdev->region->dev;
++	fdev->dev.devt = dfl_get_devt(dfl_devs[type].devt_type, fdev->id);
+ 
+ 	return 0;
+ }
+@@ -703,13 +815,20 @@ EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_remove);
+ 
+ static int __init dfl_fpga_init(void)
+ {
++	int ret;
++
+ 	dfl_ids_init();
+ 
+-	return 0;
++	ret = dfl_chardev_init();
++	if (ret)
++		dfl_ids_destroy();
++
++	return ret;
+ }
+ 
+ static void __exit dfl_fpga_exit(void)
+ {
++	dfl_chardev_uinit();
+ 	dfl_ids_destroy();
+ }
+ 
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+index 47ecb3bb6f61..66c2ade5a06b 100644
+--- a/drivers/fpga/dfl.h
++++ b/drivers/fpga/dfl.h
+@@ -15,6 +15,7 @@
+ #define __FPGA_DFL_H
+ 
+ #include <linux/bitfield.h>
++#include <linux/cdev.h>
+ #include <linux/delay.h>
+ #include <linux/fs.h>
+ #include <linux/iopoll.h>
+@@ -150,6 +151,7 @@ struct dfl_feature {
+  *
+  * @node: node to link feature devs to container device's port_dev_list.
+  * @lock: mutex to protect platform data.
++ * @cdev: cdev of feature dev.
+  * @dev: ptr to platform device linked with this platform data.
+  * @dfl_cdev: ptr to container device.
+  * @disable_count: count for port disable.
+@@ -159,6 +161,7 @@ struct dfl_feature {
+ struct dfl_feature_platform_data {
+ 	struct list_head node;
+ 	struct mutex lock;
++	struct cdev cdev;
+ 	struct platform_device *dev;
+ 	struct dfl_fpga_cdev *dfl_cdev;
+ 	unsigned int disable_count;
+@@ -176,6 +179,11 @@ static inline int dfl_feature_platform_data_size(const int num)
+ 		num * sizeof(struct dfl_feature);
+ }
+ 
++int dfl_fpga_dev_ops_register(struct platform_device *pdev,
++			      const struct file_operations *fops,
++			      struct module *owner);
++void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
++
+ #define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
+ 	for ((feature) = (pdata)->features;				    \
+ 	   (feature) < (pdata)->features + (pdata)->num; (feature)++)
+-- 
+2.19.0
+
diff --git a/patches/1709-fpga-dfl-add-dfl_fpga_cdev_find_port.patch b/patches/1709-fpga-dfl-add-dfl_fpga_cdev_find_port.patch
new file mode 100644
index 00000000000000..9669fac141dcc5
--- /dev/null
+++ b/patches/1709-fpga-dfl-add-dfl_fpga_cdev_find_port.patch
@@ -0,0 +1,103 @@
+From cb6e0d97d6da4a207f86469e10d30f0eda4c8b90 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:15 +0800
+Subject: [PATCH 1709/1795] fpga: dfl: add dfl_fpga_cdev_find_port
+
+For feature devices, we need a method to find the port dedicated
+to the device. This patch adds a function dfl_fpga_cdev_find_port
+for this purpose. e.g. FPGA Management Engine (FME) Partial
+Reconfiguration sub feature, it uses this function to find
+dedicated port on the device for PR function implementation.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5d56e117001996766c3dab5767663b0c43b76639)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl.c | 32 ++++++++++++++++++++++++++++++++
+ drivers/fpga/dfl.h | 21 +++++++++++++++++++++
+ 2 files changed, 53 insertions(+)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index b56933c64371..68e0b45617b2 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -813,6 +813,38 @@ void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev)
+ }
+ EXPORT_SYMBOL_GPL(dfl_fpga_feature_devs_remove);
+ 
++/**
++ * __dfl_fpga_cdev_find_port - find a port under given container device
++ *
++ * @cdev: container device
++ * @data: data passed to match function
++ * @match: match function used to find specific port from the port device list
++ *
++ * Find a port device under container device. This function needs to be
++ * invoked with lock held.
++ *
++ * Return: pointer to port's platform device if successful, NULL otherwise.
++ *
++ * NOTE: you will need to drop the device reference with put_device() after use.
++ */
++struct platform_device *
++__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
++			  int (*match)(struct platform_device *, void *))
++{
++	struct dfl_feature_platform_data *pdata;
++	struct platform_device *port_dev;
++
++	list_for_each_entry(pdata, &cdev->port_dev_list, node) {
++		port_dev = pdata->dev;
++
++		if (match(port_dev, data) && get_device(&port_dev->dev))
++			return port_dev;
++	}
++
++	return NULL;
++}
++EXPORT_SYMBOL_GPL(__dfl_fpga_cdev_find_port);
++
+ static int __init dfl_fpga_init(void)
+ {
+ 	int ret;
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+index 66c2ade5a06b..b4f65250a29c 100644
+--- a/drivers/fpga/dfl.h
++++ b/drivers/fpga/dfl.h
+@@ -284,4 +284,25 @@ struct dfl_fpga_cdev *
+ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
+ void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
+ 
++/*
++ * need to drop the device reference with put_device() after use port platform
++ * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
++ * functions.
++ */
++struct platform_device *
++__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
++			  int (*match)(struct platform_device *, void *));
++
++static inline struct platform_device *
++dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
++			int (*match)(struct platform_device *, void *))
++{
++	struct platform_device *pdev;
++
++	mutex_lock(&cdev->lock);
++	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
++	mutex_unlock(&cdev->lock);
++
++	return pdev;
++}
+ #endif /* __FPGA_DFL_H */
+-- 
+2.19.0
+
diff --git a/patches/1710-fpga-dfl-add-feature-device-infrastructure.patch b/patches/1710-fpga-dfl-add-feature-device-infrastructure.patch
new file mode 100644
index 00000000000000..a6b9993ce8ec19
--- /dev/null
+++ b/patches/1710-fpga-dfl-add-feature-device-infrastructure.patch
@@ -0,0 +1,257 @@
+From 5805b20e5f2e5b0399692f6736dafac6d30fb632 Mon Sep 17 00:00:00 2001
+From: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Date: Sat, 30 Jun 2018 08:53:16 +0800
+Subject: [PATCH 1710/1795] fpga: dfl: add feature device infrastructure
+
+This patch abstracts the common operations of the sub features and defines
+the feature_ops data structure, including init, uinit and ioctl function
+pointers. And this patch adds some common helper functions for FME and AFU
+drivers, e.g. dfl_feature_dev_use_begin/end which are used to ensure
+exclusive usage of the feature device file.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Kang Luwei <luwei.kang@intel.com>
+Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5b57d02a2f94bb04c6b36932412f7f3b1bb38518)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl.c | 71 +++++++++++++++++++++++++++++++++++++++
+ drivers/fpga/dfl.h | 82 +++++++++++++++++++++++++++++++++++++++++++++-
+ 2 files changed, 152 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index 68e0b45617b2..e2c72c5dd9e6 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -136,6 +136,77 @@ static enum dfl_id_type dfh_id_to_type(u32 id)
+ 	return DFL_ID_MAX;
+ }
+ 
++/**
++ * dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
++ * @pdev: feature device.
++ */
++void dfl_fpga_dev_feature_uinit(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_feature *feature;
++
++	dfl_fpga_dev_for_each_feature(pdata, feature)
++		if (feature->ops) {
++			feature->ops->uinit(pdev, feature);
++			feature->ops = NULL;
++		}
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_dev_feature_uinit);
++
++static int dfl_feature_instance_init(struct platform_device *pdev,
++				     struct dfl_feature_platform_data *pdata,
++				     struct dfl_feature *feature,
++				     struct dfl_feature_driver *drv)
++{
++	int ret;
++
++	ret = drv->ops->init(pdev, feature);
++	if (ret)
++		return ret;
++
++	feature->ops = drv->ops;
++
++	return ret;
++}
++
++/**
++ * dfl_fpga_dev_feature_init - init for sub features of dfl feature device
++ * @pdev: feature device.
++ * @feature_drvs: drvs for sub features.
++ *
++ * This function will match sub features with given feature drvs list and
++ * use matched drv to init related sub feature.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int dfl_fpga_dev_feature_init(struct platform_device *pdev,
++			      struct dfl_feature_driver *feature_drvs)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_feature_driver *drv = feature_drvs;
++	struct dfl_feature *feature;
++	int ret;
++
++	while (drv->ops) {
++		dfl_fpga_dev_for_each_feature(pdata, feature) {
++			/* match feature and drv using id */
++			if (feature->id == drv->id) {
++				ret = dfl_feature_instance_init(pdev, pdata,
++								feature, drv);
++				if (ret)
++					goto exit;
++			}
++		}
++		drv++;
++	}
++
++	return 0;
++exit:
++	dfl_fpga_dev_feature_uinit(pdev);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_dev_feature_init);
++
+ static void dfl_chardev_uinit(void)
+ {
+ 	int i;
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+index b4f65250a29c..14d4731c13b0 100644
+--- a/drivers/fpga/dfl.h
++++ b/drivers/fpga/dfl.h
+@@ -131,6 +131,17 @@
+ #define PORT_CTRL_LATENCY	BIT_ULL(2)
+ #define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */
+ 
++/**
++ * struct dfl_feature_driver - sub feature's driver
++ *
++ * @id: sub feature id.
++ * @ops: ops of this sub feature.
++ */
++struct dfl_feature_driver {
++	u64 id;
++	const struct dfl_feature_ops *ops;
++};
++
+ /**
+  * struct dfl_feature - sub feature of the feature devices
+  *
+@@ -139,13 +150,17 @@
+  *		    this index is used to find its mmio resource from the
+  *		    feature dev (platform device)'s reources.
+  * @ioaddr: mapped mmio resource address.
++ * @ops: ops of this sub feature.
+  */
+ struct dfl_feature {
+ 	u64 id;
+ 	int resource_index;
+ 	void __iomem *ioaddr;
++	const struct dfl_feature_ops *ops;
+ };
+ 
++#define DEV_STATUS_IN_USE	0
++
+ /**
+  * struct dfl_feature_platform_data - platform data for feature devices
+  *
+@@ -156,6 +171,8 @@ struct dfl_feature {
+  * @dfl_cdev: ptr to container device.
+  * @disable_count: count for port disable.
+  * @num: number for sub features.
++ * @dev_status: dev status (e.g. DEV_STATUS_IN_USE).
++ * @private: ptr to feature dev private data.
+  * @features: sub features of this feature dev.
+  */
+ struct dfl_feature_platform_data {
+@@ -165,11 +182,49 @@ struct dfl_feature_platform_data {
+ 	struct platform_device *dev;
+ 	struct dfl_fpga_cdev *dfl_cdev;
+ 	unsigned int disable_count;
+-
++	unsigned long dev_status;
++	void *private;
+ 	int num;
+ 	struct dfl_feature features[0];
+ };
+ 
++static inline
++int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata)
++{
++	/* Test and set IN_USE flags to ensure file is exclusively used */
++	if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status))
++		return -EBUSY;
++
++	return 0;
++}
++
++static inline
++void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
++{
++	clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status);
++}
++
++static inline
++void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
++				void *private)
++{
++	pdata->private = private;
++}
++
++static inline
++void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
++{
++	return pdata->private;
++}
++
++struct dfl_feature_ops {
++	int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
++	void (*uinit)(struct platform_device *pdev,
++		      struct dfl_feature *feature);
++	long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
++		      unsigned int cmd, unsigned long arg);
++};
++
+ #define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
+ #define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"
+ 
+@@ -179,11 +234,25 @@ static inline int dfl_feature_platform_data_size(const int num)
+ 		num * sizeof(struct dfl_feature);
+ }
+ 
++void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
++int dfl_fpga_dev_feature_init(struct platform_device *pdev,
++			      struct dfl_feature_driver *feature_drvs);
++
+ int dfl_fpga_dev_ops_register(struct platform_device *pdev,
+ 			      const struct file_operations *fops,
+ 			      struct module *owner);
+ void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
+ 
++static inline
++struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
++{
++	struct dfl_feature_platform_data *pdata;
++
++	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
++			     cdev);
++	return pdata->dev;
++}
++
+ #define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
+ 	for ((feature) = (pdata)->features;				    \
+ 	   (feature) < (pdata)->features + (pdata)->num; (feature)++)
+@@ -213,6 +282,17 @@ void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
+ 	return NULL;
+ }
+ 
++static inline bool is_dfl_feature_present(struct device *dev, u64 id)
++{
++	return !!dfl_get_feature_ioaddr_by_id(dev, id);
++}
++
++static inline
++struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
++{
++	return pdata->dev->dev.parent->parent;
++}
++
+ static inline bool dfl_feature_is_fme(void __iomem *base)
+ {
+ 	u64 v = readq(base + DFH);
+-- 
+2.19.0
+
diff --git a/patches/1711-fpga-dfl-add-dfl_fpga_port_ops-support.patch b/patches/1711-fpga-dfl-add-dfl_fpga_port_ops-support.patch
new file mode 100644
index 00000000000000..dbc8df284ca2a5
--- /dev/null
+++ b/patches/1711-fpga-dfl-add-dfl_fpga_port_ops-support.patch
@@ -0,0 +1,163 @@
+From 8b22c9c9699b64e1d9b049f87f5bfc40992ce409 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:17 +0800
+Subject: [PATCH 1711/1795] fpga: dfl: add dfl_fpga_port_ops support.
+
+In some cases, other DFL driver modules may need to access some port
+operations, e.g. disable / enable port for partial reconfiguration in
+FME module. In order to avoid dependency between port and FME modules,
+this patch introduces the dfl_fpga_port_ops support in DFL framework.
+A global dfl_fpga_port_ops list is added in the DFL framework, and
+it allows other DFL modules to use these port operations registered
+to this list, even in virtualization case, the port platform device
+is turned into VF / guest VM and hidden in host, the registered
+port_ops is still usable. It resolves the dependency issues between
+modules, but once get port ops API returns a valid port ops, that
+means related port driver module has been module_get to prevent from
+unexpected unload, and put port ops API must be invoked after use.
+
+These APIs introduced by this patch is listed below:
+ * dfl_fpga_port_ops_add
+   add one port ops to the global list.
+
+ * dfl_fpga_port_ops_del
+   del one port ops from the global list.
+
+ * dfl_fpga_port_ops_get / dfl_fpga_port_ops_put
+   get/put the port ops before/after use.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 6e8fd6e493bfca83021cc6a8fd86d7f69bd14fc6)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/fpga/dfl.h | 21 ++++++++++++
+ 2 files changed, 100 insertions(+)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index e2c72c5dd9e6..421668ab613e 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -136,6 +136,85 @@ static enum dfl_id_type dfh_id_to_type(u32 id)
+ 	return DFL_ID_MAX;
+ }
+ 
++/*
++ * introduce a global port_ops list, it allows port drivers to register ops
++ * in such list, then other feature devices (e.g. FME), could use the port
++ * functions even related port platform device is hidden. Below is one example,
++ * in virtualization case of PCIe-based FPGA DFL device, when SRIOV is
++ * enabled, port (and it's AFU) is turned into VF and port platform device
++ * is hidden from system but it's still required to access port to finish FPGA
++ * reconfiguration function in FME.
++ */
++
++static DEFINE_MUTEX(dfl_port_ops_mutex);
++static LIST_HEAD(dfl_port_ops_list);
++
++/**
++ * dfl_fpga_port_ops_get - get matched port ops from the global list
++ * @pdev: platform device to match with associated port ops.
++ * Return: matched port ops on success, NULL otherwise.
++ *
++ * Please note that must dfl_fpga_port_ops_put after use the port_ops.
++ */
++struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev)
++{
++	struct dfl_fpga_port_ops *ops = NULL;
++
++	mutex_lock(&dfl_port_ops_mutex);
++	if (list_empty(&dfl_port_ops_list))
++		goto done;
++
++	list_for_each_entry(ops, &dfl_port_ops_list, node) {
++		/* match port_ops using the name of platform device */
++		if (!strcmp(pdev->name, ops->name)) {
++			if (!try_module_get(ops->owner))
++				ops = NULL;
++			goto done;
++		}
++	}
++
++	ops = NULL;
++done:
++	mutex_unlock(&dfl_port_ops_mutex);
++	return ops;
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_get);
++
++/**
++ * dfl_fpga_port_ops_put - put port ops
++ * @ops: port ops.
++ */
++void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops)
++{
++	if (ops && ops->owner)
++		module_put(ops->owner);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_put);
++
++/**
++ * dfl_fpga_port_ops_add - add port_ops to global list
++ * @ops: port ops to add.
++ */
++void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops)
++{
++	mutex_lock(&dfl_port_ops_mutex);
++	list_add_tail(&ops->node, &dfl_port_ops_list);
++	mutex_unlock(&dfl_port_ops_mutex);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_add);
++
++/**
++ * dfl_fpga_port_ops_del - remove port_ops from global list
++ * @ops: port ops to del.
++ */
++void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops)
++{
++	mutex_lock(&dfl_port_ops_mutex);
++	list_del(&ops->node);
++	mutex_unlock(&dfl_port_ops_mutex);
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_del);
++
+ /**
+  * dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
+  * @pdev: feature device.
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+index 14d4731c13b0..654e0f694a5f 100644
+--- a/drivers/fpga/dfl.h
++++ b/drivers/fpga/dfl.h
+@@ -130,6 +130,27 @@
+ /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
+ #define PORT_CTRL_LATENCY	BIT_ULL(2)
+ #define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */
++/**
++ * struct dfl_fpga_port_ops - port ops
++ *
++ * @name: name of this port ops, to match with port platform device.
++ * @owner: pointer to the module which owns this port ops.
++ * @node: node to link port ops to global list.
++ * @get_id: get port id from hardware.
++ * @enable_set: enable/disable the port.
++ */
++struct dfl_fpga_port_ops {
++	const char *name;
++	struct module *owner;
++	struct list_head node;
++	int (*get_id)(struct platform_device *pdev);
++	int (*enable_set)(struct platform_device *pdev, bool enable);
++};
++
++void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
++void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
++struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
++void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
+ 
+ /**
+  * struct dfl_feature_driver - sub feature's driver
+-- 
+2.19.0
+
diff --git a/patches/1712-fpga-dfl-add-dfl_fpga_check_port_id-function.patch b/patches/1712-fpga-dfl-add-dfl_fpga_check_port_id-function.patch
new file mode 100644
index 00000000000000..83fab8096e0eca
--- /dev/null
+++ b/patches/1712-fpga-dfl-add-dfl_fpga_check_port_id-function.patch
@@ -0,0 +1,68 @@
+From 4d471534e43faa65c85b446546503f92e9d632a6 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:18 +0800
+Subject: [PATCH 1712/1795] fpga: dfl: add dfl_fpga_check_port_id function.
+
+This patch adds one common function in DFL framework. It uses
+port_ops get_id callback to get port id and compare it with given
+value. This function could be used as match function of the
+dfl_fpga_cdev_find_port function.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d06b004b99c960828523e581a3b7d109dfc1329b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl.c | 22 ++++++++++++++++++++++
+ drivers/fpga/dfl.h |  1 +
+ 2 files changed, 23 insertions(+)
+
+diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
+index 421668ab613e..a9b521bccb06 100644
+--- a/drivers/fpga/dfl.c
++++ b/drivers/fpga/dfl.c
+@@ -215,6 +215,28 @@ void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops)
+ }
+ EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_del);
+ 
++/**
++ * dfl_fpga_check_port_id - check the port id
++ * @pdev: port platform device.
++ * @pport_id: port id to compare.
++ *
++ * Return: 1 if port device matches with given port id, otherwise 0.
++ */
++int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id)
++{
++	struct dfl_fpga_port_ops *port_ops = dfl_fpga_port_ops_get(pdev);
++	int port_id;
++
++	if (!port_ops || !port_ops->get_id)
++		return 0;
++
++	port_id = port_ops->get_id(pdev);
++	dfl_fpga_port_ops_put(port_ops);
++
++	return port_id == *(int *)pport_id;
++}
++EXPORT_SYMBOL_GPL(dfl_fpga_check_port_id);
++
+ /**
+  * dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
+  * @pdev: feature device.
+diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
+index 654e0f694a5f..a8b869e9e5b7 100644
+--- a/drivers/fpga/dfl.h
++++ b/drivers/fpga/dfl.h
+@@ -151,6 +151,7 @@ void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
+ void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
+ struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
+ void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
++int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
+ 
+ /**
+  * struct dfl_feature_driver - sub feature's driver
+-- 
+2.19.0
+
diff --git a/patches/1713-fpga-add-FPGA-DFL-PCIe-device-driver.patch b/patches/1713-fpga-add-FPGA-DFL-PCIe-device-driver.patch
new file mode 100644
index 00000000000000..22395a54a31092
--- /dev/null
+++ b/patches/1713-fpga-add-FPGA-DFL-PCIe-device-driver.patch
@@ -0,0 +1,177 @@
+From 7c5b1704ef0cd9a81a5ea268b4577c13ef3d8e85 Mon Sep 17 00:00:00 2001
+From: Zhang Yi <yi.z.zhang@intel.com>
+Date: Sat, 30 Jun 2018 08:53:19 +0800
+Subject: [PATCH 1713/1795] fpga: add FPGA DFL PCIe device driver
+
+This patch implements the basic framework of the driver for FPGA PCIe
+device which implements the Device Feature List (DFL) in its MMIO space.
+This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
+both integrated (e.g. Intel Server Platform with In-package FPGA) and
+discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 72ddd9f34040a49a221c0d5d1754061e007a10e6)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig   |  15 ++++++
+ drivers/fpga/Makefile  |   3 ++
+ drivers/fpga/dfl-pci.c | 103 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 121 insertions(+)
+ create mode 100644 drivers/fpga/dfl-pci.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index 4880fd676a19..f2659f10e92e 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -146,4 +146,19 @@ config FPGA_DFL
+ 	  Gate Array (FPGA) solutions which implement Device Feature List.
+ 	  It provides enumeration APIs and feature device infrastructure.
+ 
++config FPGA_DFL_PCI
++	tristate "FPGA DFL PCIe Device Driver"
++	depends on PCI && FPGA_DFL
++	help
++	  Select this option to enable PCIe driver for PCIe-based
++	  Field-Programmable Gate Array (FPGA) solutions which implement
++	  the Device Feature List (DFL). This driver provides interfaces
++	  for userspace applications to configure, enumerate, open and access
++	  FPGA accelerators on the FPGA DFL devices, enables system level
++	  management functions such as FPGA partial reconfiguration, power
++	  management and virtualization with DFL framework and DFL feature
++	  device drivers.
++
++	  To compile this as a module, choose M here.
++
+ endif # FPGA
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 7a7a11739e00..02e025398cd5 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -31,3 +31,6 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+ 
+ # FPGA Device Feature List Support
+ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
++
++# Drivers for FPGAs which implement DFL
++obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
+new file mode 100644
+index 000000000000..e1e1f0fbe98c
+--- /dev/null
++++ b/drivers/fpga/dfl-pci.c
+@@ -0,0 +1,103 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Device Feature List (DFL) PCIe device
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Zhang Yi <Yi.Z.Zhang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/pci.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/stddef.h>
++#include <linux/errno.h>
++#include <linux/aer.h>
++
++#define DRV_VERSION	"0.8"
++#define DRV_NAME	"dfl-pci"
++
++/* PCI Device ID */
++#define PCIE_DEVICE_ID_PF_INT_5_X	0xBCBD
++#define PCIE_DEVICE_ID_PF_INT_6_X	0xBCC0
++#define PCIE_DEVICE_ID_PF_DSC_1_X	0x09C4
++/* VF Device */
++#define PCIE_DEVICE_ID_VF_INT_5_X	0xBCBF
++#define PCIE_DEVICE_ID_VF_INT_6_X	0xBCC1
++#define PCIE_DEVICE_ID_VF_DSC_1_X	0x09C5
++
++static struct pci_device_id cci_pcie_id_tbl[] = {
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
++	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
++	{0,}
++};
++MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
++
++static
++int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
++{
++	int ret;
++
++	ret = pcim_enable_device(pcidev);
++	if (ret < 0) {
++		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
++		return ret;
++	}
++
++	ret = pci_enable_pcie_error_reporting(pcidev);
++	if (ret && ret != -EINVAL)
++		dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
++
++	pci_set_master(pcidev);
++
++	if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
++		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
++		if (ret)
++			goto disable_error_report_exit;
++	} else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
++		ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
++		if (ret)
++			goto disable_error_report_exit;
++	} else {
++		ret = -EIO;
++		dev_err(&pcidev->dev, "No suitable DMA support available.\n");
++		goto disable_error_report_exit;
++	}
++
++	/* TODO: create and add the platform device per feature list */
++	return 0;
++
++disable_error_report_exit:
++	pci_disable_pcie_error_reporting(pcidev);
++	return ret;
++}
++
++static void cci_pci_remove(struct pci_dev *pcidev)
++{
++	pci_disable_pcie_error_reporting(pcidev);
++}
++
++static struct pci_driver cci_pci_driver = {
++	.name = DRV_NAME,
++	.id_table = cci_pcie_id_tbl,
++	.probe = cci_pci_probe,
++	.remove = cci_pci_remove,
++};
++
++module_pci_driver(cci_pci_driver);
++
++MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
+-- 
+2.19.0
+
diff --git a/patches/1714-fpga-dfl-pci-add-enumeration-for-feature-devices.patch b/patches/1714-fpga-dfl-pci-add-enumeration-for-feature-devices.patch
new file mode 100644
index 00000000000000..a1c59e80a22af6
--- /dev/null
+++ b/patches/1714-fpga-dfl-pci-add-enumeration-for-feature-devices.patch
@@ -0,0 +1,208 @@
+From 8f830b841a8ef146c1199b57c26a105762c3df7a Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:20 +0800
+Subject: [PATCH 1714/1795] fpga: dfl-pci: add enumeration for feature devices
+
+The Device Feature List (DFL) is implemented in MMIO and features
+are linked via the DFLs. This patch enables pcie driver to prepare
+enumeration information (e.g. locations of all device feature lists
+in MMIO) and use common APIs provided by the Device Feature List
+framework to enumerate each feature device linked.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 968b8199e2585ac4435e2b73af81201e20859c36)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl-pci.c | 144 ++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 142 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
+index e1e1f0fbe98c..66b5720582bb 100644
+--- a/drivers/fpga/dfl-pci.c
++++ b/drivers/fpga/dfl-pci.c
+@@ -22,9 +22,23 @@
+ #include <linux/errno.h>
+ #include <linux/aer.h>
+ 
++#include "dfl.h"
++
+ #define DRV_VERSION	"0.8"
+ #define DRV_NAME	"dfl-pci"
+ 
++struct cci_drvdata {
++	struct dfl_fpga_cdev *cdev;	/* container device */
++};
++
++static void __iomem *cci_pci_ioremap_bar(struct pci_dev *pcidev, int bar)
++{
++	if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
++		return NULL;
++
++	return pcim_iomap_table(pcidev)[bar];
++}
++
+ /* PCI Device ID */
+ #define PCIE_DEVICE_ID_PF_INT_5_X	0xBCBD
+ #define PCIE_DEVICE_ID_PF_INT_6_X	0xBCC0
+@@ -45,6 +59,120 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
+ };
+ MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
+ 
++static int cci_init_drvdata(struct pci_dev *pcidev)
++{
++	struct cci_drvdata *drvdata;
++
++	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
++	if (!drvdata)
++		return -ENOMEM;
++
++	pci_set_drvdata(pcidev, drvdata);
++
++	return 0;
++}
++
++static void cci_remove_feature_devs(struct pci_dev *pcidev)
++{
++	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
++
++	/* remove all children feature devices */
++	dfl_fpga_feature_devs_remove(drvdata->cdev);
++}
++
++/* enumerate feature devices under pci device */
++static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
++{
++	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
++	struct dfl_fpga_enum_info *info;
++	struct dfl_fpga_cdev *cdev;
++	resource_size_t start, len;
++	int port_num, bar, i, ret = 0;
++	void __iomem *base;
++	u32 offset;
++	u64 v;
++
++	/* allocate enumeration info via pci_dev */
++	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
++	if (!info)
++		return -ENOMEM;
++
++	/* start to find Device Feature List from Bar 0 */
++	base = cci_pci_ioremap_bar(pcidev, 0);
++	if (!base) {
++		ret = -ENOMEM;
++		goto enum_info_free_exit;
++	}
++
++	/*
++	 * PF device has FME and Ports/AFUs, and VF device only has one
++	 * Port/AFU. Check them and add related "Device Feature List" info
++	 * for the next step enumeration.
++	 */
++	if (dfl_feature_is_fme(base)) {
++		start = pci_resource_start(pcidev, 0);
++		len = pci_resource_len(pcidev, 0);
++
++		dfl_fpga_enum_info_add_dfl(info, start, len, base);
++
++		/*
++		 * find more Device Feature Lists (e.g. Ports) per information
++		 * indicated by FME module.
++		 */
++		v = readq(base + FME_HDR_CAP);
++		port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
++
++		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
++
++		for (i = 0; i < port_num; i++) {
++			v = readq(base + FME_HDR_PORT_OFST(i));
++
++			/* skip ports which are not implemented. */
++			if (!(v & FME_PORT_OFST_IMP))
++				continue;
++
++			/*
++			 * add Port's Device Feature List information for next
++			 * step enumeration.
++			 */
++			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
++			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
++			base = cci_pci_ioremap_bar(pcidev, bar);
++			if (!base)
++				continue;
++
++			start = pci_resource_start(pcidev, bar) + offset;
++			len = pci_resource_len(pcidev, bar) - offset;
++
++			dfl_fpga_enum_info_add_dfl(info, start, len,
++						   base + offset);
++		}
++	} else if (dfl_feature_is_port(base)) {
++		start = pci_resource_start(pcidev, 0);
++		len = pci_resource_len(pcidev, 0);
++
++		dfl_fpga_enum_info_add_dfl(info, start, len, base);
++	} else {
++		ret = -ENODEV;
++		goto enum_info_free_exit;
++	}
++
++	/* start enumeration with prepared enumeration information */
++	cdev = dfl_fpga_feature_devs_enumerate(info);
++	if (IS_ERR(cdev)) {
++		dev_err(&pcidev->dev, "Enumeration failure\n");
++		ret = PTR_ERR(cdev);
++		goto enum_info_free_exit;
++	}
++
++	drvdata->cdev = cdev;
++
++enum_info_free_exit:
++	dfl_fpga_enum_info_free(info);
++
++	return ret;
++}
++
+ static
+ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
+ {
+@@ -76,8 +204,19 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
+ 		goto disable_error_report_exit;
+ 	}
+ 
+-	/* TODO: create and add the platform device per feature list */
+-	return 0;
++	ret = cci_init_drvdata(pcidev);
++	if (ret) {
++		dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
++		goto disable_error_report_exit;
++	}
++
++	ret = cci_enumerate_feature_devs(pcidev);
++	if (ret) {
++		dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
++		goto disable_error_report_exit;
++	}
++
++	return ret;
+ 
+ disable_error_report_exit:
+ 	pci_disable_pcie_error_reporting(pcidev);
+@@ -86,6 +225,7 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
+ 
+ static void cci_pci_remove(struct pci_dev *pcidev)
+ {
++	cci_remove_feature_devs(pcidev);
+ 	pci_disable_pcie_error_reporting(pcidev);
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1715-fpga-dfl-add-FPGA-Management-Engine-driver-basic-fra.patch b/patches/1715-fpga-dfl-add-FPGA-Management-Engine-driver-basic-fra.patch
new file mode 100644
index 00000000000000..8b7c44fe6aa846
--- /dev/null
+++ b/patches/1715-fpga-dfl-add-FPGA-Management-Engine-driver-basic-fra.patch
@@ -0,0 +1,237 @@
+From dc8ec1d86acdf4c1495afec06a73d2619d377c04 Mon Sep 17 00:00:00 2001
+From: Kang Luwei <luwei.kang@intel.com>
+Date: Sat, 30 Jun 2018 08:53:21 +0800
+Subject: [PATCH 1715/1795] fpga: dfl: add FPGA Management Engine driver basic
+ framework
+
+The FPGA Management Engine (FME) provides power, thermal management,
+performance counters, partial reconfiguration and other functions. For each
+function, it is packaged into a private feature linked to the FME feature
+device in the 'Device Feature List'. It's a platform device created by
+DFL framework.
+
+This patch adds the basic framework of FME platform driver. It defines
+sub feature drivers to handle the different sub features, including init,
+uinit and ioctl. It also registers the file operations for the device file.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Kang Luwei <luwei.kang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 322ddebe54ae2b18c86a3bffb2b76bc5e67762ac)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig        |  10 +++
+ drivers/fpga/Makefile       |   3 +
+ drivers/fpga/dfl-fme-main.c | 158 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 171 insertions(+)
+ create mode 100644 drivers/fpga/dfl-fme-main.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index f2659f10e92e..43803a10cdae 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -146,6 +146,16 @@ config FPGA_DFL
+ 	  Gate Array (FPGA) solutions which implement Device Feature List.
+ 	  It provides enumeration APIs and feature device infrastructure.
+ 
++config FPGA_DFL_FME
++	tristate "FPGA DFL FME Driver"
++	depends on FPGA_DFL
++	help
++	  The FPGA Management Engine (FME) is a feature device implemented
++	  under Device Feature List (DFL) framework. Select this option to
++	  enable the platform device driver for FME which implements all
++	  FPGA platform level management features. There shall be one FME
++	  per DFL based FPGA device.
++
+ config FPGA_DFL_PCI
+ 	tristate "FPGA DFL PCIe Device Driver"
+ 	depends on PCI && FPGA_DFL
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 02e025398cd5..db11f340ba0f 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -31,6 +31,9 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+ 
+ # FPGA Device Feature List Support
+ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
++obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
++
++dfl-fme-objs := dfl-fme-main.o
+ 
+ # Drivers for FPGAs which implement DFL
+ obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
+new file mode 100644
+index 000000000000..bdcfe951d939
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-main.c
+@@ -0,0 +1,158 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Management Engine (FME)
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++#include "dfl.h"
++
++static int fme_hdr_init(struct platform_device *pdev,
++			struct dfl_feature *feature)
++{
++	dev_dbg(&pdev->dev, "FME HDR Init.\n");
++
++	return 0;
++}
++
++static void fme_hdr_uinit(struct platform_device *pdev,
++			  struct dfl_feature *feature)
++{
++	dev_dbg(&pdev->dev, "FME HDR UInit.\n");
++}
++
++static const struct dfl_feature_ops fme_hdr_ops = {
++	.init = fme_hdr_init,
++	.uinit = fme_hdr_uinit,
++};
++
++static struct dfl_feature_driver fme_feature_drvs[] = {
++	{
++		.id = FME_FEATURE_ID_HEADER,
++		.ops = &fme_hdr_ops,
++	},
++	{
++		.ops = NULL,
++	},
++};
++
++static int fme_open(struct inode *inode, struct file *filp)
++{
++	struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
++	int ret;
++
++	if (WARN_ON(!pdata))
++		return -ENODEV;
++
++	ret = dfl_feature_dev_use_begin(pdata);
++	if (ret)
++		return ret;
++
++	dev_dbg(&fdev->dev, "Device File Open\n");
++	filp->private_data = pdata;
++
++	return 0;
++}
++
++static int fme_release(struct inode *inode, struct file *filp)
++{
++	struct dfl_feature_platform_data *pdata = filp->private_data;
++	struct platform_device *pdev = pdata->dev;
++
++	dev_dbg(&pdev->dev, "Device File Release\n");
++	dfl_feature_dev_use_end(pdata);
++
++	return 0;
++}
++
++static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	struct dfl_feature_platform_data *pdata = filp->private_data;
++	struct platform_device *pdev = pdata->dev;
++	struct dfl_feature *f;
++	long ret;
++
++	dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
++
++	switch (cmd) {
++	default:
++		/*
++		 * Let sub-feature's ioctl function to handle the cmd.
++		 * Sub-feature's ioctl returns -ENODEV when cmd is not
++		 * handled in this sub feature, and returns 0 or other
++		 * error code if cmd is handled.
++		 */
++		dfl_fpga_dev_for_each_feature(pdata, f) {
++			if (f->ops && f->ops->ioctl) {
++				ret = f->ops->ioctl(pdev, f, cmd, arg);
++				if (ret != -ENODEV)
++					return ret;
++			}
++		}
++	}
++
++	return -EINVAL;
++}
++
++static const struct file_operations fme_fops = {
++	.owner		= THIS_MODULE,
++	.open		= fme_open,
++	.release	= fme_release,
++	.unlocked_ioctl = fme_ioctl,
++};
++
++static int fme_probe(struct platform_device *pdev)
++{
++	int ret;
++
++	ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
++	if (ret)
++		goto exit;
++
++	ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
++	if (ret)
++		goto feature_uinit;
++
++	return 0;
++
++feature_uinit:
++	dfl_fpga_dev_feature_uinit(pdev);
++exit:
++	return ret;
++}
++
++static int fme_remove(struct platform_device *pdev)
++{
++	dfl_fpga_dev_ops_unregister(pdev);
++	dfl_fpga_dev_feature_uinit(pdev);
++
++	return 0;
++}
++
++static struct platform_driver fme_driver = {
++	.driver	= {
++		.name    = DFL_FPGA_FEATURE_DEV_FME,
++	},
++	.probe   = fme_probe,
++	.remove  = fme_remove,
++};
++
++module_platform_driver(fme_driver);
++
++MODULE_DESCRIPTION("FPGA Management Engine driver");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:dfl-fme");
+-- 
+2.19.0
+
diff --git a/patches/1716-fpga-dfl-fme-add-header-sub-feature-support.patch b/patches/1716-fpga-dfl-fme-add-header-sub-feature-support.patch
new file mode 100644
index 00000000000000..5fd97b821a230c
--- /dev/null
+++ b/patches/1716-fpga-dfl-fme-add-header-sub-feature-support.patch
@@ -0,0 +1,161 @@
+From 2cba53a5ed45af0204368cb7f07f1b7fc4d68dce Mon Sep 17 00:00:00 2001
+From: Kang Luwei <luwei.kang@intel.com>
+Date: Sat, 30 Jun 2018 08:53:22 +0800
+Subject: [PATCH 1716/1795] fpga: dfl: fme: add header sub feature support
+
+The Header Register set is always present for FPGA Management Engine (FME),
+this patch implements init and uinit function for header sub feature and
+introduces several read-only sysfs interfaces for the capability and
+status.
+
+Sysfs interfaces:
+* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num
+  Read-only. Number of ports implemented
+
+* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id
+  Read-only. Bitstream (static FPGA region) identifier number. It contains
+  the detailed version and other information of this static FPGA region.
+
+* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata
+  Read-only. Bitstream (static FPGA region) meta data. It contains the
+  synthesis date, seed and other information of this static FPGA region.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Kang Luwei <luwei.kang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 0a27ff24d59662b1ca8b3f7721a965918f115074)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-platform-dfl-fme        | 23 +++++++
+ drivers/fpga/dfl-fme-main.c                   | 68 +++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+ create mode 100644 Documentation/ABI/testing/sysfs-platform-dfl-fme
+
+diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme
+new file mode 100644
+index 000000000000..8fa4febfa4b2
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
+@@ -0,0 +1,23 @@
++What:		/sys/bus/platform/devices/dfl-fme.0/ports_num
++Date:		June 2018
++KernelVersion:  4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read-only. One DFL FPGA device may have more than 1
++		port/Accelerator Function Unit (AFU). It returns the
++		number of ports on the FPGA device when read it.
++
++What:		/sys/bus/platform/devices/dfl-fme.0/bitstream_id
++Date:		June 2018
++KernelVersion:  4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read-only. It returns Bitstream (static FPGA region)
++		identifier number, which includes the detailed version
++		and other information of this static FPGA region.
++
++What:		/sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
++Date:		June 2018
++KernelVersion:  4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read-only. It returns Bitstream (static FPGA region) meta
++		data, which includes the synthesis date, seed and other
++		information of this static FPGA region.
+diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
+index bdcfe951d939..c23c56fe3f4b 100644
+--- a/drivers/fpga/dfl-fme-main.c
++++ b/drivers/fpga/dfl-fme-main.c
+@@ -19,10 +19,77 @@
+ 
+ #include "dfl.h"
+ 
++static ssize_t ports_num_show(struct device *dev,
++			      struct device_attribute *attr, char *buf)
++{
++	void __iomem *base;
++	u64 v;
++
++	base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
++
++	v = readq(base + FME_HDR_CAP);
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
++}
++static DEVICE_ATTR_RO(ports_num);
++
++/*
++ * Bitstream (static FPGA region) identifier number. It contains the
++ * detailed version and other information of this static FPGA region.
++ */
++static ssize_t bitstream_id_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	void __iomem *base;
++	u64 v;
++
++	base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
++
++	v = readq(base + FME_HDR_BITSTREAM_ID);
++
++	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
++}
++static DEVICE_ATTR_RO(bitstream_id);
++
++/*
++ * Bitstream (static FPGA region) meta data. It contains the synthesis
++ * date, seed and other information of this static FPGA region.
++ */
++static ssize_t bitstream_metadata_show(struct device *dev,
++				       struct device_attribute *attr, char *buf)
++{
++	void __iomem *base;
++	u64 v;
++
++	base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
++
++	v = readq(base + FME_HDR_BITSTREAM_MD);
++
++	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
++}
++static DEVICE_ATTR_RO(bitstream_metadata);
++
++static const struct attribute *fme_hdr_attrs[] = {
++	&dev_attr_ports_num.attr,
++	&dev_attr_bitstream_id.attr,
++	&dev_attr_bitstream_metadata.attr,
++	NULL,
++};
++
+ static int fme_hdr_init(struct platform_device *pdev,
+ 			struct dfl_feature *feature)
+ {
++	void __iomem *base = feature->ioaddr;
++	int ret;
++
+ 	dev_dbg(&pdev->dev, "FME HDR Init.\n");
++	dev_dbg(&pdev->dev, "FME cap %llx.\n",
++		(unsigned long long)readq(base + FME_HDR_CAP));
++
++	ret = sysfs_create_files(&pdev->dev.kobj, fme_hdr_attrs);
++	if (ret)
++		return ret;
+ 
+ 	return 0;
+ }
+@@ -31,6 +98,7 @@ static void fme_hdr_uinit(struct platform_device *pdev,
+ 			  struct dfl_feature *feature)
+ {
+ 	dev_dbg(&pdev->dev, "FME HDR UInit.\n");
++	sysfs_remove_files(&pdev->dev.kobj, fme_hdr_attrs);
+ }
+ 
+ static const struct dfl_feature_ops fme_hdr_ops = {
+-- 
+2.19.0
+
diff --git a/patches/1717-fpga-dfl-fme-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch b/patches/1717-fpga-dfl-fme-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
new file mode 100644
index 00000000000000..269fc5ded483c9
--- /dev/null
+++ b/patches/1717-fpga-dfl-fme-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
@@ -0,0 +1,141 @@
+From 3269f4197392b513be98098fe564aa5fcadf1b91 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:23 +0800
+Subject: [PATCH 1717/1795] fpga: dfl: fme: add
+ DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support
+
+DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
+ones which need to be supported by all feature devices drivers including
+FME and AFU. Userspace application can use these ioctl interfaces to get
+the API info and check if specific extension is supported or not in
+current driver.
+
+This patch implements above 2 ioctls in FPGA Management Engine (FME)
+driver.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 620e1902f6fe57ddacdabd9e33fadbd290be9652)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/ioctl/ioctl-number.txt |  1 +
+ drivers/fpga/dfl-fme-main.c          | 12 +++++++
+ include/uapi/linux/fpga-dfl.h        | 50 ++++++++++++++++++++++++++++
+ 3 files changed, 63 insertions(+)
+ create mode 100644 include/uapi/linux/fpga-dfl.h
+
+diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
+index 3e3fdae5f3ed..91ad5734473a 100644
+--- a/Documentation/ioctl/ioctl-number.txt
++++ b/Documentation/ioctl/ioctl-number.txt
+@@ -324,6 +324,7 @@ Code  Seq#(hex)	Include File		Comments
+ 0xB3	00	linux/mmc/ioctl.h
+ 0xB4	00-0F	linux/gpio.h		<mailto:linux-gpio@vger.kernel.org>
+ 0xB5	00-0F	uapi/linux/rpmsg.h	<mailto:linux-remoteproc@vger.kernel.org>
++0xB6	all	linux/fpga-dfl.h
+ 0xC0	00-0F	linux/usb/iowarrior.h
+ 0xCA	00-0F	uapi/misc/cxl.h
+ 0xCA	80-BF	uapi/scsi/cxlflash_ioctl.h
+diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
+index c23c56fe3f4b..c83ff88e3bbb 100644
+--- a/drivers/fpga/dfl-fme-main.c
++++ b/drivers/fpga/dfl-fme-main.c
+@@ -16,6 +16,7 @@
+ 
+ #include <linux/kernel.h>
+ #include <linux/module.h>
++#include <linux/fpga-dfl.h>
+ 
+ #include "dfl.h"
+ 
+@@ -116,6 +117,13 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
+ 	},
+ };
+ 
++static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
++				      unsigned long arg)
++{
++	/* No extension support for now */
++	return 0;
++}
++
+ static int fme_open(struct inode *inode, struct file *filp)
+ {
+ 	struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
+@@ -156,6 +164,10 @@ static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 	dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
+ 
+ 	switch (cmd) {
++	case DFL_FPGA_GET_API_VERSION:
++		return DFL_FPGA_API_VERSION;
++	case DFL_FPGA_CHECK_EXTENSION:
++		return fme_ioctl_check_extension(pdata, arg);
+ 	default:
+ 		/*
+ 		 * Let sub-feature's ioctl function to handle the cmd.
+diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
+new file mode 100644
+index 000000000000..858e4437c31c
+--- /dev/null
++++ b/include/uapi/linux/fpga-dfl.h
+@@ -0,0 +1,50 @@
++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
++/*
++ * Header File for FPGA DFL User API
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Zhang Yi <yi.z.zhang@intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ */
++
++#ifndef _UAPI_LINUX_FPGA_DFL_H
++#define _UAPI_LINUX_FPGA_DFL_H
++
++#include <linux/ioctl.h>
++
++#define DFL_FPGA_API_VERSION 0
++
++/*
++ * The IOCTL interface for DFL based FPGA is designed for extensibility by
++ * embedding the structure length (argsz) and flags into structures passed
++ * between kernel and userspace. This design referenced the VFIO IOCTL
++ * interface (include/uapi/linux/vfio.h).
++ */
++
++#define DFL_FPGA_MAGIC 0xB6
++
++#define DFL_FPGA_BASE 0
++
++/**
++ * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
++ *
++ * Report the version of the driver API.
++ * Return: Driver API Version.
++ */
++
++#define DFL_FPGA_GET_API_VERSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
++
++/**
++ * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
++ *
++ * Check whether an extension is supported.
++ * Return: 0 if not supported, otherwise the extension is supported.
++ */
++
++#define DFL_FPGA_CHECK_EXTENSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
++
++#endif /* _UAPI_LINUX_FPGA_DFL_H */
+-- 
+2.19.0
+
diff --git a/patches/1718-fpga-dfl-fme-add-partial-reconfiguration-sub-feature.patch b/patches/1718-fpga-dfl-fme-add-partial-reconfiguration-sub-feature.patch
new file mode 100644
index 00000000000000..625cda6c53f99d
--- /dev/null
+++ b/patches/1718-fpga-dfl-fme-add-partial-reconfiguration-sub-feature.patch
@@ -0,0 +1,821 @@
+From 39274ef5da8a2d0735b0dd2b3b6195503f317fca Mon Sep 17 00:00:00 2001
+From: Kang Luwei <luwei.kang@intel.com>
+Date: Sat, 30 Jun 2018 08:53:24 +0800
+Subject: [PATCH 1718/1795] fpga: dfl: fme: add partial reconfiguration sub
+ feature support
+
+Partial Reconfiguration (PR) is the most important function for FME. It
+allows reconfiguration for given Port/Accelerated Function Unit (AFU).
+
+It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
+and invokes fpga-region's interface (fpga_region_program_fpga) for PR
+operation once PR request received via ioctl. Below user space interface
+is exposed by this sub feature.
+
+Ioctl interface:
+* DFL_FPGA_FME_PORT_PR
+  Do partial reconfiguration per information from userspace, including
+  target port(AFU), buffer size and address info. It returns error code
+  to userspace if failed. For detailed PR error information, user needs
+  to read fpga-mgr's status sysfs interface.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Kang Luwei <luwei.kang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 29de76240e861d52b75405166337e94184f1875d)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Makefile         |   2 +-
+ drivers/fpga/dfl-fme-main.c   |  43 ++-
+ drivers/fpga/dfl-fme-pr.c     | 479 ++++++++++++++++++++++++++++++++++
+ drivers/fpga/dfl-fme-pr.h     |  84 ++++++
+ drivers/fpga/dfl-fme.h        |  38 +++
+ include/uapi/linux/fpga-dfl.h |  27 ++
+ 6 files changed, 671 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/fpga/dfl-fme-pr.c
+ create mode 100644 drivers/fpga/dfl-fme-pr.h
+ create mode 100644 drivers/fpga/dfl-fme.h
+
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index db11f340ba0f..fd334d40aa1c 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -33,7 +33,7 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
+ obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
+ 
+-dfl-fme-objs := dfl-fme-main.o
++dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+ 
+ # Drivers for FPGAs which implement DFL
+ obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
+index c83ff88e3bbb..086ad2420ade 100644
+--- a/drivers/fpga/dfl-fme-main.c
++++ b/drivers/fpga/dfl-fme-main.c
+@@ -19,6 +19,7 @@
+ #include <linux/fpga-dfl.h>
+ 
+ #include "dfl.h"
++#include "dfl-fme.h"
+ 
+ static ssize_t ports_num_show(struct device *dev,
+ 			      struct device_attribute *attr, char *buf)
+@@ -112,6 +113,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
+ 		.id = FME_FEATURE_ID_HEADER,
+ 		.ops = &fme_hdr_ops,
+ 	},
++	{
++		.id = FME_FEATURE_ID_PR_MGMT,
++		.ops = &pr_mgmt_ops,
++	},
+ 	{
+ 		.ops = NULL,
+ 	},
+@@ -187,6 +192,35 @@ static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 	return -EINVAL;
+ }
+ 
++static int fme_dev_init(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_fme *fme;
++
++	fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
++	if (!fme)
++		return -ENOMEM;
++
++	fme->pdata = pdata;
++
++	mutex_lock(&pdata->lock);
++	dfl_fpga_pdata_set_private(pdata, fme);
++	mutex_unlock(&pdata->lock);
++
++	return 0;
++}
++
++static void fme_dev_destroy(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_fme *fme;
++
++	mutex_lock(&pdata->lock);
++	fme = dfl_fpga_pdata_get_private(pdata);
++	dfl_fpga_pdata_set_private(pdata, NULL);
++	mutex_unlock(&pdata->lock);
++}
++
+ static const struct file_operations fme_fops = {
+ 	.owner		= THIS_MODULE,
+ 	.open		= fme_open,
+@@ -198,10 +232,14 @@ static int fme_probe(struct platform_device *pdev)
+ {
+ 	int ret;
+ 
+-	ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
++	ret = fme_dev_init(pdev);
+ 	if (ret)
+ 		goto exit;
+ 
++	ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
++	if (ret)
++		goto dev_destroy;
++
+ 	ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
+ 	if (ret)
+ 		goto feature_uinit;
+@@ -210,6 +248,8 @@ static int fme_probe(struct platform_device *pdev)
+ 
+ feature_uinit:
+ 	dfl_fpga_dev_feature_uinit(pdev);
++dev_destroy:
++	fme_dev_destroy(pdev);
+ exit:
+ 	return ret;
+ }
+@@ -218,6 +258,7 @@ static int fme_remove(struct platform_device *pdev)
+ {
+ 	dfl_fpga_dev_ops_unregister(pdev);
+ 	dfl_fpga_dev_feature_uinit(pdev);
++	fme_dev_destroy(pdev);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
+new file mode 100644
+index 000000000000..fc9fd2d0482f
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-pr.c
+@@ -0,0 +1,479 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Management Engine (FME) Partial Reconfiguration
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Christopher Rauer <christopher.rauer@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/types.h>
++#include <linux/device.h>
++#include <linux/vmalloc.h>
++#include <linux/uaccess.h>
++#include <linux/fpga/fpga-mgr.h>
++#include <linux/fpga/fpga-bridge.h>
++#include <linux/fpga/fpga-region.h>
++#include <linux/fpga-dfl.h>
++
++#include "dfl.h"
++#include "dfl-fme.h"
++#include "dfl-fme-pr.h"
++
++static struct dfl_fme_region *
++dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
++{
++	struct dfl_fme_region *fme_region;
++
++	list_for_each_entry(fme_region, &fme->region_list, node)
++		if (fme_region->port_id == port_id)
++			return fme_region;
++
++	return NULL;
++}
++
++static int dfl_fme_region_match(struct device *dev, const void *data)
++{
++	return dev->parent == data;
++}
++
++static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
++{
++	struct dfl_fme_region *fme_region;
++	struct fpga_region *region;
++
++	fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
++	if (!fme_region)
++		return NULL;
++
++	region = fpga_region_class_find(NULL, &fme_region->region->dev,
++					dfl_fme_region_match);
++	if (!region)
++		return NULL;
++
++	return region;
++}
++
++static int fme_pr(struct platform_device *pdev, unsigned long arg)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	void __user *argp = (void __user *)arg;
++	struct dfl_fpga_fme_port_pr port_pr;
++	struct fpga_image_info *info;
++	struct fpga_region *region;
++	void __iomem *fme_hdr;
++	struct dfl_fme *fme;
++	unsigned long minsz;
++	void *buf = NULL;
++	int ret = 0;
++	u64 v;
++
++	minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
++
++	if (copy_from_user(&port_pr, argp, minsz))
++		return -EFAULT;
++
++	if (port_pr.argsz < minsz || port_pr.flags)
++		return -EINVAL;
++
++	if (!IS_ALIGNED(port_pr.buffer_size, 4))
++		return -EINVAL;
++
++	/* get fme header region */
++	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
++					       FME_FEATURE_ID_HEADER);
++
++	/* check port id */
++	v = readq(fme_hdr + FME_HDR_CAP);
++	if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
++		dev_dbg(&pdev->dev, "port number more than maximum\n");
++		return -EINVAL;
++	}
++
++	if (!access_ok(VERIFY_READ,
++		       (void __user *)(unsigned long)port_pr.buffer_address,
++		       port_pr.buffer_size))
++		return -EFAULT;
++
++	buf = vmalloc(port_pr.buffer_size);
++	if (!buf)
++		return -ENOMEM;
++
++	if (copy_from_user(buf,
++			   (void __user *)(unsigned long)port_pr.buffer_address,
++			   port_pr.buffer_size)) {
++		ret = -EFAULT;
++		goto free_exit;
++	}
++
++	/* prepare fpga_image_info for PR */
++	info = fpga_image_info_alloc(&pdev->dev);
++	if (!info) {
++		ret = -ENOMEM;
++		goto free_exit;
++	}
++
++	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
++
++	mutex_lock(&pdata->lock);
++	fme = dfl_fpga_pdata_get_private(pdata);
++	/* fme device has been unregistered. */
++	if (!fme) {
++		ret = -EINVAL;
++		goto unlock_exit;
++	}
++
++	region = dfl_fme_region_find(fme, port_pr.port_id);
++	if (!region) {
++		ret = -EINVAL;
++		goto unlock_exit;
++	}
++
++	fpga_image_info_free(region->info);
++
++	info->buf = buf;
++	info->count = port_pr.buffer_size;
++	info->region_id = port_pr.port_id;
++	region->info = info;
++
++	ret = fpga_region_program_fpga(region);
++
++	/*
++	 * it allows userspace to reset the PR region's logic by disabling and
++	 * reenabling the bridge to clear things out between accleration runs.
++	 * so no need to hold the bridges after partial reconfiguration.
++	 */
++	if (region->get_bridges)
++		fpga_bridges_put(&region->bridge_list);
++
++	put_device(&region->dev);
++unlock_exit:
++	mutex_unlock(&pdata->lock);
++free_exit:
++	vfree(buf);
++	if (copy_to_user((void __user *)arg, &port_pr, minsz))
++		return -EFAULT;
++
++	return ret;
++}
++
++/**
++ * dfl_fme_create_mgr - create fpga mgr platform device as child device
++ *
++ * @pdata: fme platform_device's pdata
++ *
++ * Return: mgr platform device if successful, and error code otherwise.
++ */
++static struct platform_device *
++dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
++		   struct dfl_feature *feature)
++{
++	struct platform_device *mgr, *fme = pdata->dev;
++	struct dfl_fme_mgr_pdata mgr_pdata;
++	int ret = -ENOMEM;
++
++	if (!feature->ioaddr)
++		return ERR_PTR(-ENODEV);
++
++	mgr_pdata.ioaddr = feature->ioaddr;
++
++	/*
++	 * Each FME has only one fpga-mgr, so allocate platform device using
++	 * the same FME platform device id.
++	 */
++	mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
++	if (!mgr)
++		return ERR_PTR(ret);
++
++	mgr->dev.parent = &fme->dev;
++
++	ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
++	if (ret)
++		goto create_mgr_err;
++
++	ret = platform_device_add(mgr);
++	if (ret)
++		goto create_mgr_err;
++
++	return mgr;
++
++create_mgr_err:
++	platform_device_put(mgr);
++	return ERR_PTR(ret);
++}
++
++/**
++ * dfl_fme_destroy_mgr - destroy fpga mgr platform device
++ * @pdata: fme platform device's pdata
++ */
++static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
++
++	platform_device_unregister(priv->mgr);
++}
++
++/**
++ * dfl_fme_create_bridge - create fme fpga bridge platform device as child
++ *
++ * @pdata: fme platform device's pdata
++ * @port_id: port id for the bridge to be created.
++ *
++ * Return: bridge platform device if successful, and error code otherwise.
++ */
++static struct dfl_fme_bridge *
++dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
++{
++	struct device *dev = &pdata->dev->dev;
++	struct dfl_fme_br_pdata br_pdata;
++	struct dfl_fme_bridge *fme_br;
++	int ret = -ENOMEM;
++
++	fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
++	if (!fme_br)
++		return ERR_PTR(ret);
++
++	br_pdata.cdev = pdata->dfl_cdev;
++	br_pdata.port_id = port_id;
++
++	fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
++					   PLATFORM_DEVID_AUTO);
++	if (!fme_br->br)
++		return ERR_PTR(ret);
++
++	fme_br->br->dev.parent = dev;
++
++	ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
++	if (ret)
++		goto create_br_err;
++
++	ret = platform_device_add(fme_br->br);
++	if (ret)
++		goto create_br_err;
++
++	return fme_br;
++
++create_br_err:
++	platform_device_put(fme_br->br);
++	return ERR_PTR(ret);
++}
++
++/**
++ * dfl_fme_destroy_bridge - destroy fpga bridge platform device
++ * @fme_br: fme bridge to destroy
++ */
++static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
++{
++	platform_device_unregister(fme_br->br);
++}
++
++/**
++ * dfl_fme_destroy_bridge - destroy all fpga bridge platform device
++ * @pdata: fme platform device's pdata
++ */
++static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
++	struct dfl_fme_bridge *fbridge, *tmp;
++
++	list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
++		list_del(&fbridge->node);
++		dfl_fme_destroy_bridge(fbridge);
++	}
++}
++
++/**
++ * dfl_fme_create_region - create fpga region platform device as child
++ *
++ * @pdata: fme platform device's pdata
++ * @mgr: mgr platform device needed for region
++ * @br: br platform device needed for region
++ * @port_id: port id
++ *
++ * Return: fme region if successful, and error code otherwise.
++ */
++static struct dfl_fme_region *
++dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
++		      struct platform_device *mgr,
++		      struct platform_device *br, int port_id)
++{
++	struct dfl_fme_region_pdata region_pdata;
++	struct device *dev = &pdata->dev->dev;
++	struct dfl_fme_region *fme_region;
++	int ret = -ENOMEM;
++
++	fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
++	if (!fme_region)
++		return ERR_PTR(ret);
++
++	region_pdata.mgr = mgr;
++	region_pdata.br = br;
++
++	/*
++	 * Each FPGA device may have more than one port, so allocate platform
++	 * device using the same port platform device id.
++	 */
++	fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
++	if (!fme_region->region)
++		return ERR_PTR(ret);
++
++	fme_region->region->dev.parent = dev;
++
++	ret = platform_device_add_data(fme_region->region, &region_pdata,
++				       sizeof(region_pdata));
++	if (ret)
++		goto create_region_err;
++
++	ret = platform_device_add(fme_region->region);
++	if (ret)
++		goto create_region_err;
++
++	fme_region->port_id = port_id;
++
++	return fme_region;
++
++create_region_err:
++	platform_device_put(fme_region->region);
++	return ERR_PTR(ret);
++}
++
++/**
++ * dfl_fme_destroy_region - destroy fme region
++ * @fme_region: fme region to destroy
++ */
++static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
++{
++	platform_device_unregister(fme_region->region);
++}
++
++/**
++ * dfl_fme_destroy_regions - destroy all fme regions
++ * @pdata: fme platform device's pdata
++ */
++static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
++	struct dfl_fme_region *fme_region, *tmp;
++
++	list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
++		list_del(&fme_region->node);
++		dfl_fme_destroy_region(fme_region);
++	}
++}
++
++static int pr_mgmt_init(struct platform_device *pdev,
++			struct dfl_feature *feature)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_fme_region *fme_region;
++	struct dfl_fme_bridge *fme_br;
++	struct platform_device *mgr;
++	struct dfl_fme *priv;
++	void __iomem *fme_hdr;
++	int ret = -ENODEV, i = 0;
++	u64 fme_cap, port_offset;
++
++	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
++					       FME_FEATURE_ID_HEADER);
++
++	mutex_lock(&pdata->lock);
++	priv = dfl_fpga_pdata_get_private(pdata);
++
++	/* Initialize the region and bridge sub device list */
++	INIT_LIST_HEAD(&priv->region_list);
++	INIT_LIST_HEAD(&priv->bridge_list);
++
++	/* Create fpga mgr platform device */
++	mgr = dfl_fme_create_mgr(pdata, feature);
++	if (IS_ERR(mgr)) {
++		dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
++		goto unlock;
++	}
++
++	priv->mgr = mgr;
++
++	/* Read capability register to check number of regions and bridges */
++	fme_cap = readq(fme_hdr + FME_HDR_CAP);
++	for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
++		port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
++		if (!(port_offset & FME_PORT_OFST_IMP))
++			continue;
++
++		/* Create bridge for each port */
++		fme_br = dfl_fme_create_bridge(pdata, i);
++		if (IS_ERR(fme_br)) {
++			ret = PTR_ERR(fme_br);
++			goto destroy_region;
++		}
++
++		list_add(&fme_br->node, &priv->bridge_list);
++
++		/* Create region for each port */
++		fme_region = dfl_fme_create_region(pdata, mgr,
++						   fme_br->br, i);
++		if (!fme_region) {
++			ret = PTR_ERR(fme_region);
++			goto destroy_region;
++		}
++
++		list_add(&fme_region->node, &priv->region_list);
++	}
++	mutex_unlock(&pdata->lock);
++
++	return 0;
++
++destroy_region:
++	dfl_fme_destroy_regions(pdata);
++	dfl_fme_destroy_bridges(pdata);
++	dfl_fme_destroy_mgr(pdata);
++unlock:
++	mutex_unlock(&pdata->lock);
++	return ret;
++}
++
++static void pr_mgmt_uinit(struct platform_device *pdev,
++			  struct dfl_feature *feature)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_fme *priv;
++
++	mutex_lock(&pdata->lock);
++	priv = dfl_fpga_pdata_get_private(pdata);
++
++	dfl_fme_destroy_regions(pdata);
++	dfl_fme_destroy_bridges(pdata);
++	dfl_fme_destroy_mgr(pdata);
++	mutex_unlock(&pdata->lock);
++}
++
++static long fme_pr_ioctl(struct platform_device *pdev,
++			 struct dfl_feature *feature,
++			 unsigned int cmd, unsigned long arg)
++{
++	long ret;
++
++	switch (cmd) {
++	case DFL_FPGA_FME_PORT_PR:
++		ret = fme_pr(pdev, arg);
++		break;
++	default:
++		ret = -ENODEV;
++	}
++
++	return ret;
++}
++
++const struct dfl_feature_ops pr_mgmt_ops = {
++	.init = pr_mgmt_init,
++	.uinit = pr_mgmt_uinit,
++	.ioctl = fme_pr_ioctl,
++};
+diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl-fme-pr.h
+new file mode 100644
+index 000000000000..096a699089d3
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-pr.h
+@@ -0,0 +1,84 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#ifndef __DFL_FME_PR_H
++#define __DFL_FME_PR_H
++
++#include <linux/platform_device.h>
++
++/**
++ * struct dfl_fme_region - FME fpga region data structure
++ *
++ * @region: platform device of the FPGA region.
++ * @node: used to link fme_region to a list.
++ * @port_id: indicate which port this region connected to.
++ */
++struct dfl_fme_region {
++	struct platform_device *region;
++	struct list_head node;
++	int port_id;
++};
++
++/**
++ * struct dfl_fme_region_pdata - platform data for FME region platform device.
++ *
++ * @mgr: platform device of the FPGA manager.
++ * @br: platform device of the FPGA bridge.
++ * @region_id: region id (same as port_id).
++ */
++struct dfl_fme_region_pdata {
++	struct platform_device *mgr;
++	struct platform_device *br;
++	int region_id;
++};
++
++/**
++ * struct dfl_fme_bridge - FME fpga bridge data structure
++ *
++ * @br: platform device of the FPGA bridge.
++ * @node: used to link fme_bridge to a list.
++ */
++struct dfl_fme_bridge {
++	struct platform_device *br;
++	struct list_head node;
++};
++
++/**
++ * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
++ *
++ * @cdev: container device.
++ * @port_id: port id.
++ */
++struct dfl_fme_br_pdata {
++	struct dfl_fpga_cdev *cdev;
++	int port_id;
++};
++
++/**
++ * struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
++ *
++ * @ioaddr: mapped io address for FME manager platform device.
++ */
++struct dfl_fme_mgr_pdata {
++	void __iomem *ioaddr;
++};
++
++#define DFL_FPGA_FME_MGR	"dfl-fme-mgr"
++#define DFL_FPGA_FME_BRIDGE	"dfl-fme-bridge"
++#define DFL_FPGA_FME_REGION	"dfl-fme-region"
++
++#endif /* __DFL_FME_PR_H */
+diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h
+new file mode 100644
+index 000000000000..5394a216c5c0
+--- /dev/null
++++ b/drivers/fpga/dfl-fme.h
+@@ -0,0 +1,38 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Header file for FPGA Management Engine (FME) Driver
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#ifndef __DFL_FME_H
++#define __DFL_FME_H
++
++/**
++ * struct dfl_fme - dfl fme private data
++ *
++ * @mgr: FME's FPGA manager platform device.
++ * @region_list: linked list of FME's FPGA regions.
++ * @bridge_list: linked list of FME's FPGA bridges.
++ * @pdata: fme platform device's pdata.
++ */
++struct dfl_fme {
++	struct platform_device *mgr;
++	struct list_head region_list;
++	struct list_head bridge_list;
++	struct dfl_feature_platform_data *pdata;
++};
++
++extern const struct dfl_feature_ops pr_mgmt_ops;
++
++#endif /* __DFL_FME_H */
+diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
+index 858e4437c31c..9666af85a8f5 100644
+--- a/include/uapi/linux/fpga-dfl.h
++++ b/include/uapi/linux/fpga-dfl.h
+@@ -14,6 +14,7 @@
+ #ifndef _UAPI_LINUX_FPGA_DFL_H
+ #define _UAPI_LINUX_FPGA_DFL_H
+ 
++#include <linux/types.h>
+ #include <linux/ioctl.h>
+ 
+ #define DFL_FPGA_API_VERSION 0
+@@ -28,6 +29,7 @@
+ #define DFL_FPGA_MAGIC 0xB6
+ 
+ #define DFL_FPGA_BASE 0
++#define DFL_FME_BASE 0x80
+ 
+ /**
+  * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
+@@ -47,4 +49,29 @@
+ 
+ #define DFL_FPGA_CHECK_EXTENSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
+ 
++/* IOCTLs for FME file descriptor */
++
++/**
++ * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
++ *						struct dfl_fpga_fme_port_pr)
++ *
++ * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
++ * provided by caller.
++ * Return: 0 on success, -errno on failure.
++ * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
++ * some errors during PR, under this case, the user can fetch HW error info
++ * from the status of FME's fpga manager.
++ */
++
++struct dfl_fpga_fme_port_pr {
++	/* Input */
++	__u32 argsz;		/* Structure length */
++	__u32 flags;		/* Zero for now */
++	__u32 port_id;
++	__u32 buffer_size;
++	__u64 buffer_address;	/* Userspace address to the buffer for PR */
++};
++
++#define DFL_FPGA_FME_PORT_PR	_IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
++
+ #endif /* _UAPI_LINUX_FPGA_DFL_H */
+-- 
+2.19.0
+
diff --git a/patches/1719-fpga-dfl-add-fpga-manager-platform-driver-for-FME.patch b/patches/1719-fpga-dfl-add-fpga-manager-platform-driver-for-FME.patch
new file mode 100644
index 00000000000000..7d601f76eb49d5
--- /dev/null
+++ b/patches/1719-fpga-dfl-add-fpga-manager-platform-driver-for-FME.patch
@@ -0,0 +1,398 @@
+From 4b9d565f4bec41c4e19bf0e819f18d5d65fdf739 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:25 +0800
+Subject: [PATCH 1719/1795] fpga: dfl: add fpga manager platform driver for FME
+
+This patch adds fpga manager driver for FPGA Management Engine (FME). It
+implements fpga_manager_ops for FPGA Partial Reconfiguration function.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Kang Luwei <luwei.kang@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit af275ec6160ba68714371cfe0575f9aa478ce02f)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig       |   6 +
+ drivers/fpga/Makefile      |   1 +
+ drivers/fpga/dfl-fme-mgr.c | 334 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 341 insertions(+)
+ create mode 100644 drivers/fpga/dfl-fme-mgr.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index 43803a10cdae..46b48e5164db 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -156,6 +156,12 @@ config FPGA_DFL_FME
+ 	  FPGA platform level management features. There shall be one FME
+ 	  per DFL based FPGA device.
+ 
++config FPGA_DFL_FME_MGR
++	tristate "FPGA DFL FME Manager Driver"
++	depends on FPGA_DFL_FME && HAS_IOMEM
++	help
++	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
++
+ config FPGA_DFL_PCI
+ 	tristate "FPGA DFL PCIe Device Driver"
+ 	depends on PCI && FPGA_DFL
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index fd334d40aa1c..23f41b02f894 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -32,6 +32,7 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+ # FPGA Device Feature List Support
+ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
+ obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
++obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+ 
+diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
+new file mode 100644
+index 000000000000..df843b51c663
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-mgr.c
+@@ -0,0 +1,334 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * FPGA Manager Driver for FPGA Management Engine (FME)
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Kang Luwei <luwei.kang@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Christopher Rauer <christopher.rauer@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/bitfield.h>
++#include <linux/module.h>
++#include <linux/iopoll.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/fpga/fpga-mgr.h>
++
++#include "dfl-fme-pr.h"
++
++/* FME Partial Reconfiguration Sub Feature Register Set */
++#define FME_PR_DFH		0x0
++#define FME_PR_CTRL		0x8
++#define FME_PR_STS		0x10
++#define FME_PR_DATA		0x18
++#define FME_PR_ERR		0x20
++#define FME_PR_INTFC_ID_H	0xA8
++#define FME_PR_INTFC_ID_L	0xB0
++
++/* FME PR Control Register Bitfield */
++#define FME_PR_CTRL_PR_RST	BIT_ULL(0)  /* Reset PR engine */
++#define FME_PR_CTRL_PR_RSTACK	BIT_ULL(4)  /* Ack for PR engine reset */
++#define FME_PR_CTRL_PR_RGN_ID	GENMASK_ULL(9, 7)       /* PR Region ID */
++#define FME_PR_CTRL_PR_START	BIT_ULL(12) /* Start to request PR service */
++#define FME_PR_CTRL_PR_COMPLETE	BIT_ULL(13) /* PR data push completion */
++
++/* FME PR Status Register Bitfield */
++/* Number of available entries in HW queue inside the PR engine. */
++#define FME_PR_STS_PR_CREDIT	GENMASK_ULL(8, 0)
++#define FME_PR_STS_PR_STS	BIT_ULL(16) /* PR operation status */
++#define FME_PR_STS_PR_STS_IDLE	0
++#define FME_PR_STS_PR_CTRLR_STS	GENMASK_ULL(22, 20)     /* Controller status */
++#define FME_PR_STS_PR_HOST_STS	GENMASK_ULL(27, 24)     /* PR host status */
++
++/* FME PR Data Register Bitfield */
++/* PR data from the raw-binary file. */
++#define FME_PR_DATA_PR_DATA_RAW	GENMASK_ULL(32, 0)
++
++/* FME PR Error Register */
++/* PR Operation errors detected. */
++#define FME_PR_ERR_OPERATION_ERR	BIT_ULL(0)
++/* CRC error detected. */
++#define FME_PR_ERR_CRC_ERR		BIT_ULL(1)
++/* Incompatible PR bitstream detected. */
++#define FME_PR_ERR_INCOMPATIBLE_BS	BIT_ULL(2)
++/* PR data push protocol violated. */
++#define FME_PR_ERR_PROTOCOL_ERR		BIT_ULL(3)
++/* PR data fifo overflow error detected */
++#define FME_PR_ERR_FIFO_OVERFLOW	BIT_ULL(4)
++
++#define PR_WAIT_TIMEOUT   8000000
++#define PR_HOST_STATUS_IDLE	0
++
++struct fme_mgr_priv {
++	void __iomem *ioaddr;
++	u64 pr_error;
++};
++
++static u64 pr_error_to_mgr_status(u64 err)
++{
++	u64 status = 0;
++
++	if (err & FME_PR_ERR_OPERATION_ERR)
++		status |= FPGA_MGR_STATUS_OPERATION_ERR;
++	if (err & FME_PR_ERR_CRC_ERR)
++		status |= FPGA_MGR_STATUS_CRC_ERR;
++	if (err & FME_PR_ERR_INCOMPATIBLE_BS)
++		status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
++	if (err & FME_PR_ERR_PROTOCOL_ERR)
++		status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
++	if (err & FME_PR_ERR_FIFO_OVERFLOW)
++		status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
++
++	return status;
++}
++
++static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
++{
++	u64 pr_status, pr_error;
++
++	pr_status = readq(fme_pr + FME_PR_STS);
++	if (!(pr_status & FME_PR_STS_PR_STS))
++		return 0;
++
++	pr_error = readq(fme_pr + FME_PR_ERR);
++	writeq(pr_error, fme_pr + FME_PR_ERR);
++
++	return pr_error;
++}
++
++static int fme_mgr_write_init(struct fpga_manager *mgr,
++			      struct fpga_image_info *info,
++			      const char *buf, size_t count)
++{
++	struct device *dev = &mgr->dev;
++	struct fme_mgr_priv *priv = mgr->priv;
++	void __iomem *fme_pr = priv->ioaddr;
++	u64 pr_ctrl, pr_status;
++
++	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
++		dev_err(dev, "only supports partial reconfiguration.\n");
++		return -EINVAL;
++	}
++
++	dev_dbg(dev, "resetting PR before initiated PR\n");
++
++	pr_ctrl = readq(fme_pr + FME_PR_CTRL);
++	pr_ctrl |= FME_PR_CTRL_PR_RST;
++	writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
++
++	if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
++			       pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
++			       PR_WAIT_TIMEOUT)) {
++		dev_err(dev, "PR Reset ACK timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	pr_ctrl = readq(fme_pr + FME_PR_CTRL);
++	pr_ctrl &= ~FME_PR_CTRL_PR_RST;
++	writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
++
++	dev_dbg(dev,
++		"waiting for PR resource in HW to be initialized and ready\n");
++
++	if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
++			       (pr_status & FME_PR_STS_PR_STS) ==
++			       FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
++		dev_err(dev, "PR Status timeout\n");
++		priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
++		return -ETIMEDOUT;
++	}
++
++	dev_dbg(dev, "check and clear previous PR error\n");
++	priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
++	if (priv->pr_error)
++		dev_dbg(dev, "previous PR error detected %llx\n",
++			(unsigned long long)priv->pr_error);
++
++	dev_dbg(dev, "set PR port ID\n");
++
++	pr_ctrl = readq(fme_pr + FME_PR_CTRL);
++	pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
++	pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
++	writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
++
++	return 0;
++}
++
++static int fme_mgr_write(struct fpga_manager *mgr,
++			 const char *buf, size_t count)
++{
++	struct device *dev = &mgr->dev;
++	struct fme_mgr_priv *priv = mgr->priv;
++	void __iomem *fme_pr = priv->ioaddr;
++	u64 pr_ctrl, pr_status, pr_data;
++	int delay = 0, pr_credit, i = 0;
++
++	dev_dbg(dev, "start request\n");
++
++	pr_ctrl = readq(fme_pr + FME_PR_CTRL);
++	pr_ctrl |= FME_PR_CTRL_PR_START;
++	writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
++
++	dev_dbg(dev, "pushing data from bitstream to HW\n");
++
++	/*
++	 * driver can push data to PR hardware using PR_DATA register once HW
++	 * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
++	 * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
++	 * to wait for enough pr_credit from hardware by polling.
++	 */
++	pr_status = readq(fme_pr + FME_PR_STS);
++	pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
++
++	while (count > 0) {
++		while (pr_credit <= 1) {
++			if (delay++ > PR_WAIT_TIMEOUT) {
++				dev_err(dev, "PR_CREDIT timeout\n");
++				return -ETIMEDOUT;
++			}
++			udelay(1);
++
++			pr_status = readq(fme_pr + FME_PR_STS);
++			pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
++		}
++
++		if (count < 4) {
++			dev_err(dev, "Invaild PR bitstream size\n");
++			return -EINVAL;
++		}
++
++		pr_data = 0;
++		pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
++				      *(((u32 *)buf) + i));
++		writeq(pr_data, fme_pr + FME_PR_DATA);
++		count -= 4;
++		pr_credit--;
++		i++;
++	}
++
++	return 0;
++}
++
++static int fme_mgr_write_complete(struct fpga_manager *mgr,
++				  struct fpga_image_info *info)
++{
++	struct device *dev = &mgr->dev;
++	struct fme_mgr_priv *priv = mgr->priv;
++	void __iomem *fme_pr = priv->ioaddr;
++	u64 pr_ctrl;
++
++	pr_ctrl = readq(fme_pr + FME_PR_CTRL);
++	pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
++	writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
++
++	dev_dbg(dev, "green bitstream push complete\n");
++	dev_dbg(dev, "waiting for HW to release PR resource\n");
++
++	if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
++			       !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
++			       PR_WAIT_TIMEOUT)) {
++		dev_err(dev, "PR Completion ACK timeout.\n");
++		return -ETIMEDOUT;
++	}
++
++	dev_dbg(dev, "PR operation complete, checking status\n");
++	priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
++	if (priv->pr_error) {
++		dev_dbg(dev, "PR error detected %llx\n",
++			(unsigned long long)priv->pr_error);
++		return -EIO;
++	}
++
++	dev_dbg(dev, "PR done successfully\n");
++
++	return 0;
++}
++
++static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
++{
++	return FPGA_MGR_STATE_UNKNOWN;
++}
++
++static u64 fme_mgr_status(struct fpga_manager *mgr)
++{
++	struct fme_mgr_priv *priv = mgr->priv;
++
++	return pr_error_to_mgr_status(priv->pr_error);
++}
++
++static const struct fpga_manager_ops fme_mgr_ops = {
++	.write_init = fme_mgr_write_init,
++	.write = fme_mgr_write,
++	.write_complete = fme_mgr_write_complete,
++	.state = fme_mgr_state,
++	.status = fme_mgr_status,
++};
++
++static int fme_mgr_probe(struct platform_device *pdev)
++{
++	struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
++	struct device *dev = &pdev->dev;
++	struct fme_mgr_priv *priv;
++	struct fpga_manager *mgr;
++	struct resource *res;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	if (pdata->ioaddr)
++		priv->ioaddr = pdata->ioaddr;
++
++	if (!priv->ioaddr) {
++		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++		priv->ioaddr = devm_ioremap_resource(dev, res);
++		if (IS_ERR(priv->ioaddr))
++			return PTR_ERR(priv->ioaddr);
++	}
++
++	mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
++			      &fme_mgr_ops, priv);
++	if (!mgr)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, mgr);
++
++	ret = fpga_mgr_register(mgr);
++	if (ret)
++		fpga_mgr_free(mgr);
++
++	return ret;
++}
++
++static int fme_mgr_remove(struct platform_device *pdev)
++{
++	struct fpga_manager *mgr = platform_get_drvdata(pdev);
++
++	fpga_mgr_unregister(mgr);
++
++	return 0;
++}
++
++static struct platform_driver fme_mgr_driver = {
++	.driver	= {
++		.name    = DFL_FPGA_FME_MGR,
++	},
++	.probe   = fme_mgr_probe,
++	.remove  = fme_mgr_remove,
++};
++
++module_platform_driver(fme_mgr_driver);
++
++MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:dfl-fme-mgr");
+-- 
+2.19.0
+
diff --git a/patches/1720-fpga-dfl-fme-mgr-add-compat_id-support.patch b/patches/1720-fpga-dfl-fme-mgr-add-compat_id-support.patch
new file mode 100644
index 00000000000000..31046cd7c268ba
--- /dev/null
+++ b/patches/1720-fpga-dfl-fme-mgr-add-compat_id-support.patch
@@ -0,0 +1,63 @@
+From 3f475698ae61f334fd20a7db2192b8bf6fe2fc84 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:26 +0800
+Subject: [PATCH 1720/1795] fpga: dfl: fme-mgr: add compat_id support
+
+This patch adds compat_id support to fme manager driver, it
+reads the ID from the hardware register. And it could be used
+for compatibility check before partial reconfiguration.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5ebae801d960d46e39574cb83ec24ab44d1a6c2a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl-fme-mgr.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
+index df843b51c663..b5ef405b6d88 100644
+--- a/drivers/fpga/dfl-fme-mgr.c
++++ b/drivers/fpga/dfl-fme-mgr.c
+@@ -272,9 +272,17 @@ static const struct fpga_manager_ops fme_mgr_ops = {
+ 	.status = fme_mgr_status,
+ };
+ 
++static void fme_mgr_get_compat_id(void __iomem *fme_pr,
++				  struct fpga_compat_id *id)
++{
++	id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
++	id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
++}
++
+ static int fme_mgr_probe(struct platform_device *pdev)
+ {
+ 	struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
++	struct fpga_compat_id *compat_id;
+ 	struct device *dev = &pdev->dev;
+ 	struct fme_mgr_priv *priv;
+ 	struct fpga_manager *mgr;
+@@ -295,11 +303,18 @@ static int fme_mgr_probe(struct platform_device *pdev)
+ 			return PTR_ERR(priv->ioaddr);
+ 	}
+ 
++	compat_id = devm_kzalloc(dev, sizeof(*compat_id), GFP_KERNEL);
++	if (!compat_id)
++		return -ENOMEM;
++
++	fme_mgr_get_compat_id(priv->ioaddr, compat_id);
++
+ 	mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
+ 			      &fme_mgr_ops, priv);
+ 	if (!mgr)
+ 		return -ENOMEM;
+ 
++	mgr->compat_id = compat_id;
+ 	platform_set_drvdata(pdev, mgr);
+ 
+ 	ret = fpga_mgr_register(mgr);
+-- 
+2.19.0
+
diff --git a/patches/1721-fpga-dfl-add-fpga-bridge-platform-driver-for-FME.patch b/patches/1721-fpga-dfl-add-fpga-bridge-platform-driver-for-FME.patch
new file mode 100644
index 00000000000000..878a238ebaaa1b
--- /dev/null
+++ b/patches/1721-fpga-dfl-add-fpga-bridge-platform-driver-for-FME.patch
@@ -0,0 +1,177 @@
+From 592b0e1d01dc8cb463e17a6a3989d02c93aeb032 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:27 +0800
+Subject: [PATCH 1721/1795] fpga: dfl: add fpga bridge platform driver for FME
+
+This patch adds fpga bridge platform driver for FPGA Management Engine.
+It implements the enable_set callback for fpga bridge.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit de892dff17b36d138ff41aeb46366d7c1ed4cd77)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig      |   6 ++
+ drivers/fpga/Makefile     |   1 +
+ drivers/fpga/dfl-fme-br.c | 114 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 121 insertions(+)
+ create mode 100644 drivers/fpga/dfl-fme-br.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index 46b48e5164db..11d1943b91d4 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -162,6 +162,12 @@ config FPGA_DFL_FME_MGR
+ 	help
+ 	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
+ 
++config FPGA_DFL_FME_BRIDGE
++	tristate "FPGA DFL FME Bridge Driver"
++	depends on FPGA_DFL_FME && HAS_IOMEM
++	help
++	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
++
+ config FPGA_DFL_PCI
+ 	tristate "FPGA DFL PCIe Device Driver"
+ 	depends on PCI && FPGA_DFL
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 23f41b02f894..cda05515ebfd 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
+ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
+ obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
+ obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
++obj-$(CONFIG_FPGA_DFL_FME_BRIDGE)	+= dfl-fme-br.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+ 
+diff --git a/drivers/fpga/dfl-fme-br.c b/drivers/fpga/dfl-fme-br.c
+new file mode 100644
+index 000000000000..7cc041def8b3
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-br.c
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * FPGA Bridge Driver for FPGA Management Engine (FME)
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/module.h>
++#include <linux/fpga/fpga-bridge.h>
++
++#include "dfl.h"
++#include "dfl-fme-pr.h"
++
++struct fme_br_priv {
++	struct dfl_fme_br_pdata *pdata;
++	struct dfl_fpga_port_ops *port_ops;
++	struct platform_device *port_pdev;
++};
++
++static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
++{
++	struct fme_br_priv *priv = bridge->priv;
++	struct platform_device *port_pdev;
++	struct dfl_fpga_port_ops *ops;
++
++	if (!priv->port_pdev) {
++		port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev,
++						    &priv->pdata->port_id,
++						    dfl_fpga_check_port_id);
++		if (!port_pdev)
++			return -ENODEV;
++
++		priv->port_pdev = port_pdev;
++	}
++
++	if (priv->port_pdev && !priv->port_ops) {
++		ops = dfl_fpga_port_ops_get(priv->port_pdev);
++		if (!ops || !ops->enable_set)
++			return -ENOENT;
++
++		priv->port_ops = ops;
++	}
++
++	return priv->port_ops->enable_set(priv->port_pdev, enable);
++}
++
++static const struct fpga_bridge_ops fme_bridge_ops = {
++	.enable_set = fme_bridge_enable_set,
++};
++
++static int fme_br_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct fme_br_priv *priv;
++	struct fpga_bridge *br;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->pdata = dev_get_platdata(dev);
++
++	br = fpga_bridge_create(dev, "DFL FPGA FME Bridge",
++				&fme_bridge_ops, priv);
++	if (!br)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, br);
++
++	ret = fpga_bridge_register(br);
++	if (ret)
++		fpga_bridge_free(br);
++
++	return ret;
++}
++
++static int fme_br_remove(struct platform_device *pdev)
++{
++	struct fpga_bridge *br = platform_get_drvdata(pdev);
++	struct fme_br_priv *priv = br->priv;
++
++	fpga_bridge_unregister(br);
++
++	if (priv->port_pdev)
++		put_device(&priv->port_pdev->dev);
++	if (priv->port_ops)
++		dfl_fpga_port_ops_put(priv->port_ops);
++
++	return 0;
++}
++
++static struct platform_driver fme_br_driver = {
++	.driver	= {
++		.name    = DFL_FPGA_FME_BRIDGE,
++	},
++	.probe   = fme_br_probe,
++	.remove  = fme_br_remove,
++};
++
++module_platform_driver(fme_br_driver);
++
++MODULE_DESCRIPTION("FPGA Bridge for DFL FPGA Management Engine");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:dfl-fme-bridge");
+-- 
+2.19.0
+
diff --git a/patches/1722-fpga-dfl-add-fpga-region-platform-driver-for-FME.patch b/patches/1722-fpga-dfl-add-fpga-region-platform-driver-for-FME.patch
new file mode 100644
index 00000000000000..1b604d3fd30320
--- /dev/null
+++ b/patches/1722-fpga-dfl-add-fpga-region-platform-driver-for-FME.patch
@@ -0,0 +1,151 @@
+From 8a00df91ae2b4b7ce1f5a3526d6d4a2c4a7fd0a7 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:28 +0800
+Subject: [PATCH 1722/1795] fpga: dfl: add fpga region platform driver for FME
+
+This patch adds fpga region platform driver for FPGA Management Engine.
+It register an fpga region with given fpga manager / bridge device.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit bb61b9be3e6b001f1571b230316bf3867dc41df3)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig          |  6 +++
+ drivers/fpga/Makefile         |  1 +
+ drivers/fpga/dfl-fme-region.c | 88 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 95 insertions(+)
+ create mode 100644 drivers/fpga/dfl-fme-region.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index 11d1943b91d4..f99f422feec9 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -168,6 +168,12 @@ config FPGA_DFL_FME_BRIDGE
+ 	help
+ 	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
+ 
++config FPGA_DFL_FME_REGION
++	tristate "FPGA DFL FME Region Driver"
++	depends on FPGA_DFL_FME && HAS_IOMEM
++	help
++	  Say Y to enable FPGA Region driver for FPGA Management Engine.
++
+ config FPGA_DFL_PCI
+ 	tristate "FPGA DFL PCIe Device Driver"
+ 	depends on PCI && FPGA_DFL
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index cda05515ebfd..637c27512c28 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_FPGA_DFL)			+= dfl.o
+ obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
+ obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
+ obj-$(CONFIG_FPGA_DFL_FME_BRIDGE)	+= dfl-fme-br.o
++obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+ 
+diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl-fme-region.c
+new file mode 100644
+index 000000000000..a6e0bde7cc31
+--- /dev/null
++++ b/drivers/fpga/dfl-fme-region.c
+@@ -0,0 +1,88 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * FPGA Region Driver for FPGA Management Engine (FME)
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Wu Hao <hao.wu@intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/module.h>
++#include <linux/fpga/fpga-region.h>
++
++#include "dfl-fme-pr.h"
++
++static int fme_region_get_bridges(struct fpga_region *region)
++{
++	struct dfl_fme_region_pdata *pdata = region->priv;
++	struct device *dev = &pdata->br->dev;
++
++	return fpga_bridge_get_to_list(dev, region->info, &region->bridge_list);
++}
++
++static int fme_region_probe(struct platform_device *pdev)
++{
++	struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev);
++	struct device *dev = &pdev->dev;
++	struct fpga_region *region;
++	struct fpga_manager *mgr;
++	int ret;
++
++	mgr = fpga_mgr_get(&pdata->mgr->dev);
++	if (IS_ERR(mgr))
++		return -EPROBE_DEFER;
++
++	region = fpga_region_create(dev, mgr, fme_region_get_bridges);
++	if (!region) {
++		ret = -ENOMEM;
++		goto eprobe_mgr_put;
++	}
++
++	region->priv = pdata;
++	platform_set_drvdata(pdev, region);
++
++	ret = fpga_region_register(region);
++	if (ret)
++		goto region_free;
++
++	dev_dbg(dev, "DFL FME FPGA Region probed\n");
++
++	return 0;
++
++region_free:
++	fpga_region_free(region);
++eprobe_mgr_put:
++	fpga_mgr_put(mgr);
++	return ret;
++}
++
++static int fme_region_remove(struct platform_device *pdev)
++{
++	struct fpga_region *region = dev_get_drvdata(&pdev->dev);
++
++	fpga_region_unregister(region);
++	fpga_mgr_put(region->mgr);
++
++	return 0;
++}
++
++static struct platform_driver fme_region_driver = {
++	.driver	= {
++		.name    = DFL_FPGA_FME_REGION,
++	},
++	.probe   = fme_region_probe,
++	.remove  = fme_region_remove,
++};
++
++module_platform_driver(fme_region_driver);
++
++MODULE_DESCRIPTION("FPGA Region for DFL FPGA Management Engine");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:dfl-fme-region");
+-- 
+2.19.0
+
diff --git a/patches/1723-fpga-dfl-fme-region-add-support-for-compat_id.patch b/patches/1723-fpga-dfl-fme-region-add-support-for-compat_id.patch
new file mode 100644
index 00000000000000..a0f306bba8b98a
--- /dev/null
+++ b/patches/1723-fpga-dfl-fme-region-add-support-for-compat_id.patch
@@ -0,0 +1,34 @@
+From 00b03b3742a51abd8d42cd80f72b39d6d482b055 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:29 +0800
+Subject: [PATCH 1723/1795] fpga: dfl: fme-region: add support for compat_id
+
+This patch adds compat_id support, it reuses fme manager's
+compat id, as the per region compat id is actually from the
+fme manager's register.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 7514a4249c479c0b56a112306496a9aa3bad312b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl-fme-region.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl-fme-region.c
+index a6e0bde7cc31..0b7e19c27c6d 100644
+--- a/drivers/fpga/dfl-fme-region.c
++++ b/drivers/fpga/dfl-fme-region.c
+@@ -45,6 +45,7 @@ static int fme_region_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	region->priv = pdata;
++	region->compat_id = mgr->compat_id;
+ 	platform_set_drvdata(pdev, region);
+ 
+ 	ret = fpga_region_register(region);
+-- 
+2.19.0
+
diff --git a/patches/1724-fpga-dfl-add-FPGA-Accelerated-Function-Unit-driver-b.patch b/patches/1724-fpga-dfl-add-FPGA-Accelerated-Function-Unit-driver-b.patch
new file mode 100644
index 00000000000000..8d23cdf8ef7d5a
--- /dev/null
+++ b/patches/1724-fpga-dfl-add-FPGA-Accelerated-Function-Unit-driver-b.patch
@@ -0,0 +1,239 @@
+From f411f2de4e6d5043882900de3ab9691984ef04e7 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:30 +0800
+Subject: [PATCH 1724/1795] fpga: dfl: add FPGA Accelerated Function Unit
+ driver basic framework
+
+On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
+reprogrammed for different functions. It connects to the FPGA
+infrastructure (static FPGA region) via a Port. Port CSRs are
+implemented separately from the AFU CSRs to provide control and
+status of the Port. Once valid PR bitstream is programmed into
+the AFU, it allows access to the AFU CSRs in the AFU MMIO space.
+
+This patch only implements basic driver framework for AFU, including
+device file operation framework.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 1a1527cf5ddacc6716a3cacfa232111d92ffd93b)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Kconfig        |   9 ++
+ drivers/fpga/Makefile       |   2 +
+ drivers/fpga/dfl-afu-main.c | 162 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 173 insertions(+)
+ create mode 100644 drivers/fpga/dfl-afu-main.c
+
+diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
+index f99f422feec9..1ebcef4bab5b 100644
+--- a/drivers/fpga/Kconfig
++++ b/drivers/fpga/Kconfig
+@@ -174,6 +174,15 @@ config FPGA_DFL_FME_REGION
+ 	help
+ 	  Say Y to enable FPGA Region driver for FPGA Management Engine.
+ 
++config FPGA_DFL_AFU
++	tristate "FPGA DFL AFU Driver"
++	depends on FPGA_DFL
++	help
++	  This is the driver for FPGA Accelerated Function Unit (AFU) which
++	  implements AFU and Port management features. A User AFU connects
++	  to the FPGA infrastructure via a Port. There may be more than one
++	  Port/AFU per DFL based FPGA device.
++
+ config FPGA_DFL_PCI
+ 	tristate "FPGA DFL PCIe Device Driver"
+ 	depends on PCI && FPGA_DFL
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 637c27512c28..1ac7749b2542 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -35,8 +35,10 @@ obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
+ obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
+ obj-$(CONFIG_FPGA_DFL_FME_BRIDGE)	+= dfl-fme-br.o
+ obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
++obj-$(CONFIG_FPGA_DFL_AFU)		+= dfl-afu.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
++dfl-afu-objs := dfl-afu-main.o
+ 
+ # Drivers for FPGAs which implement DFL
+ obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+new file mode 100644
+index 000000000000..08f88cdb3bfc
+--- /dev/null
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -0,0 +1,162 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Accelerated Function Unit (AFU)
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *   Joseph Grecco <joe.grecco@intel.com>
++ *   Enno Luebbers <enno.luebbers@intel.com>
++ *   Tim Whisonant <tim.whisonant@intel.com>
++ *   Ananda Ravuri <ananda.ravuri@intel.com>
++ *   Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++#include "dfl.h"
++
++static int port_hdr_init(struct platform_device *pdev,
++			 struct dfl_feature *feature)
++{
++	dev_dbg(&pdev->dev, "PORT HDR Init.\n");
++
++	return 0;
++}
++
++static void port_hdr_uinit(struct platform_device *pdev,
++			   struct dfl_feature *feature)
++{
++	dev_dbg(&pdev->dev, "PORT HDR UInit.\n");
++}
++
++static const struct dfl_feature_ops port_hdr_ops = {
++	.init = port_hdr_init,
++	.uinit = port_hdr_uinit,
++};
++
++static struct dfl_feature_driver port_feature_drvs[] = {
++	{
++		.id = PORT_FEATURE_ID_HEADER,
++		.ops = &port_hdr_ops,
++	},
++	{
++		.ops = NULL,
++	}
++};
++
++static int afu_open(struct inode *inode, struct file *filp)
++{
++	struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
++	struct dfl_feature_platform_data *pdata;
++	int ret;
++
++	pdata = dev_get_platdata(&fdev->dev);
++	if (WARN_ON(!pdata))
++		return -ENODEV;
++
++	ret = dfl_feature_dev_use_begin(pdata);
++	if (ret)
++		return ret;
++
++	dev_dbg(&fdev->dev, "Device File Open\n");
++	filp->private_data = fdev;
++
++	return 0;
++}
++
++static int afu_release(struct inode *inode, struct file *filp)
++{
++	struct platform_device *pdev = filp->private_data;
++	struct dfl_feature_platform_data *pdata;
++
++	dev_dbg(&pdev->dev, "Device File Release\n");
++
++	pdata = dev_get_platdata(&pdev->dev);
++
++	dfl_feature_dev_use_end(pdata);
++
++	return 0;
++}
++
++static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	struct platform_device *pdev = filp->private_data;
++	struct dfl_feature_platform_data *pdata;
++	struct dfl_feature *f;
++	long ret;
++
++	dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
++
++	pdata = dev_get_platdata(&pdev->dev);
++
++	switch (cmd) {
++	default:
++		/*
++		 * Let sub-feature's ioctl function to handle the cmd
++		 * Sub-feature's ioctl returns -ENODEV when cmd is not
++		 * handled in this sub feature, and returns 0 and other
++		 * error code if cmd is handled.
++		 */
++		dfl_fpga_dev_for_each_feature(pdata, f)
++			if (f->ops && f->ops->ioctl) {
++				ret = f->ops->ioctl(pdev, f, cmd, arg);
++				if (ret != -ENODEV)
++					return ret;
++			}
++	}
++
++	return -EINVAL;
++}
++
++static const struct file_operations afu_fops = {
++	.owner = THIS_MODULE,
++	.open = afu_open,
++	.release = afu_release,
++	.unlocked_ioctl = afu_ioctl,
++};
++
++static int afu_probe(struct platform_device *pdev)
++{
++	int ret;
++
++	dev_dbg(&pdev->dev, "%s\n", __func__);
++
++	ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs);
++	if (ret)
++		return ret;
++
++	ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE);
++	if (ret)
++		dfl_fpga_dev_feature_uinit(pdev);
++
++	return ret;
++}
++
++static int afu_remove(struct platform_device *pdev)
++{
++	dev_dbg(&pdev->dev, "%s\n", __func__);
++
++	dfl_fpga_dev_ops_unregister(pdev);
++	dfl_fpga_dev_feature_uinit(pdev);
++
++	return 0;
++}
++
++static struct platform_driver afu_driver = {
++	.driver	= {
++		.name    = DFL_FPGA_FEATURE_DEV_PORT,
++	},
++	.probe   = afu_probe,
++	.remove  = afu_remove,
++};
++
++module_platform_driver(afu_driver);
++
++MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver");
++MODULE_AUTHOR("Intel Corporation");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:dfl-port");
+-- 
+2.19.0
+
diff --git a/patches/1725-fpga-dfl-afu-add-port-ops-support.patch b/patches/1725-fpga-dfl-afu-add-port-ops-support.patch
new file mode 100644
index 00000000000000..f8835e0451e37f
--- /dev/null
+++ b/patches/1725-fpga-dfl-afu-add-port-ops-support.patch
@@ -0,0 +1,169 @@
+From 4fae1b27fca7ef39a8fbeca32d32e2498daaf7a3 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:31 +0800
+Subject: [PATCH 1725/1795] fpga: dfl: afu: add port ops support
+
+This patch registers the port ops into the global list in the DFL
+framework, and it allows other modules to use the port ops. And
+This patch includes the implementation of the get_id and enable_set
+ops too.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 47c1b19c160fe1641469c145dba78fbbe48b996a)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl-afu-main.c | 122 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 121 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+index 08f88cdb3bfc..a38d6a825e7e 100644
+--- a/drivers/fpga/dfl-afu-main.c
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -19,6 +19,83 @@
+ 
+ #include "dfl.h"
+ 
++/**
++ * port_enable - enable a port
++ * @pdev: port platform device.
++ *
++ * Enable Port by clear the port soft reset bit, which is set by default.
++ * The User AFU is unable to respond to any MMIO access while in reset.
++ * port_enable function should only be used after port_disable
++ * function.
++ */
++static void port_enable(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	void __iomem *base;
++	u64 v;
++
++	WARN_ON(!pdata->disable_count);
++
++	if (--pdata->disable_count != 0)
++		return;
++
++	base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
++
++	/* Clear port soft reset */
++	v = readq(base + PORT_HDR_CTRL);
++	v &= ~PORT_CTRL_SFTRST;
++	writeq(v, base + PORT_HDR_CTRL);
++}
++
++#define RST_POLL_INVL 10 /* us */
++#define RST_POLL_TIMEOUT 1000 /* us */
++
++/**
++ * port_disable - disable a port
++ * @pdev: port platform device.
++ *
++ * Disable Port by setting the port soft reset bit, it puts the port into
++ * reset.
++ */
++static int port_disable(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	void __iomem *base;
++	u64 v;
++
++	if (pdata->disable_count++ != 0)
++		return 0;
++
++	base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
++
++	/* Set port soft reset */
++	v = readq(base + PORT_HDR_CTRL);
++	v |= PORT_CTRL_SFTRST;
++	writeq(v, base + PORT_HDR_CTRL);
++
++	/*
++	 * HW sets ack bit to 1 when all outstanding requests have been drained
++	 * on this port and minimum soft reset pulse width has elapsed.
++	 * Driver polls port_soft_reset_ack to determine if reset done by HW.
++	 */
++	if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & PORT_CTRL_SFTRST,
++			       RST_POLL_INVL, RST_POLL_TIMEOUT)) {
++		dev_err(&pdev->dev, "timeout, fail to reset device\n");
++		return -ETIMEDOUT;
++	}
++
++	return 0;
++}
++
++static int port_get_id(struct platform_device *pdev)
++{
++	void __iomem *base;
++
++	base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
++
++	return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP));
++}
++
+ static int port_hdr_init(struct platform_device *pdev,
+ 			 struct dfl_feature *feature)
+ {
+@@ -119,6 +196,28 @@ static const struct file_operations afu_fops = {
+ 	.unlocked_ioctl = afu_ioctl,
+ };
+ 
++static int port_enable_set(struct platform_device *pdev, bool enable)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	int ret = 0;
++
++	mutex_lock(&pdata->lock);
++	if (enable)
++		port_enable(pdev);
++	else
++		ret = port_disable(pdev);
++	mutex_unlock(&pdata->lock);
++
++	return ret;
++}
++
++static struct dfl_fpga_port_ops afu_port_ops = {
++	.name = DFL_FPGA_FEATURE_DEV_PORT,
++	.owner = THIS_MODULE,
++	.get_id = port_get_id,
++	.enable_set = port_enable_set,
++};
++
+ static int afu_probe(struct platform_device *pdev)
+ {
+ 	int ret;
+@@ -154,7 +253,28 @@ static struct platform_driver afu_driver = {
+ 	.remove  = afu_remove,
+ };
+ 
+-module_platform_driver(afu_driver);
++static int __init afu_init(void)
++{
++	int ret;
++
++	dfl_fpga_port_ops_add(&afu_port_ops);
++
++	ret = platform_driver_register(&afu_driver);
++	if (ret)
++		dfl_fpga_port_ops_del(&afu_port_ops);
++
++	return ret;
++}
++
++static void __exit afu_exit(void)
++{
++	platform_driver_unregister(&afu_driver);
++
++	dfl_fpga_port_ops_del(&afu_port_ops);
++}
++
++module_init(afu_init);
++module_exit(afu_exit);
+ 
+ MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver");
+ MODULE_AUTHOR("Intel Corporation");
+-- 
+2.19.0
+
diff --git a/patches/1726-fpga-dfl-afu-add-header-sub-feature-support.patch b/patches/1726-fpga-dfl-afu-add-header-sub-feature-support.patch
new file mode 100644
index 00000000000000..8677b5056209bb
--- /dev/null
+++ b/patches/1726-fpga-dfl-afu-add-header-sub-feature-support.patch
@@ -0,0 +1,216 @@
+From 8de4c0a64c59bf7465f451e96fc28e9df24ff797 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:32 +0800
+Subject: [PATCH 1726/1795] fpga: dfl: afu: add header sub feature support
+
+The port header register set is always present for port, it is mainly
+for capability, control and status of the ports that AFU connected to.
+
+This patch implements header sub feature support. Below user interfaces
+are created by this patch.
+
+Sysfs interface:
+* /sys/class/fpga_region/<regionX>/<dfl-port.x>/id
+  Read-only. Port ID.
+
+Ioctl interface:
+* DFL_FPGA_PORT_RESET
+  Reset the FPGA Port and its AFU.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit e4664c0ee4ac44993c62d10b048ab0a960691da5)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-platform-dfl-port       |  7 ++
+ drivers/fpga/dfl-afu-main.c                   | 79 ++++++++++++++++++-
+ include/uapi/linux/fpga-dfl.h                 | 17 ++++
+ 3 files changed, 102 insertions(+), 1 deletion(-)
+ create mode 100644 Documentation/ABI/testing/sysfs-platform-dfl-port
+
+diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port
+new file mode 100644
+index 000000000000..cb91165f5397
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
+@@ -0,0 +1,7 @@
++What:		/sys/bus/platform/devices/dfl-port.0/id
++Date:		June 2018
++KernelVersion:	4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read-only. It returns id of this port. One DFL FPGA device
++		may have more than one port. Userspace could use this id to
++		distinguish different ports under same FPGA device.
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+index a38d6a825e7e..d36b3e9f3984 100644
+--- a/drivers/fpga/dfl-afu-main.c
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -16,6 +16,7 @@
+ 
+ #include <linux/kernel.h>
+ #include <linux/module.h>
++#include <linux/fpga-dfl.h>
+ 
+ #include "dfl.h"
+ 
+@@ -87,6 +88,41 @@ static int port_disable(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++/*
++ * This function resets the FPGA Port and its accelerator (AFU) by function
++ * __port_disable and __port_enable (set port soft reset bit and then clear
++ * it). Userspace can do Port reset at any time, e.g. during DMA or Partial
++ * Reconfiguration. But it should never cause any system level issue, only
++ * functional failure (e.g. DMA or PR operation failure) and be recoverable
++ * from the failure.
++ *
++ * Note: the accelerator (AFU) is not accessible when its port is in reset
++ * (disabled). Any attempts on MMIO access to AFU while in reset, will
++ * result errors reported via port error reporting sub feature (if present).
++ */
++static int __port_reset(struct platform_device *pdev)
++{
++	int ret;
++
++	ret = port_disable(pdev);
++	if (!ret)
++		port_enable(pdev);
++
++	return ret;
++}
++
++static int port_reset(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	int ret;
++
++	mutex_lock(&pdata->lock);
++	ret = __port_reset(pdev);
++	mutex_unlock(&pdata->lock);
++
++	return ret;
++}
++
+ static int port_get_id(struct platform_device *pdev)
+ {
+ 	void __iomem *base;
+@@ -96,23 +132,63 @@ static int port_get_id(struct platform_device *pdev)
+ 	return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP));
+ }
+ 
++static ssize_t
++id_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	int id = port_get_id(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%d\n", id);
++}
++static DEVICE_ATTR_RO(id);
++
++static const struct attribute *port_hdr_attrs[] = {
++	&dev_attr_id.attr,
++	NULL,
++};
++
+ static int port_hdr_init(struct platform_device *pdev,
+ 			 struct dfl_feature *feature)
+ {
+ 	dev_dbg(&pdev->dev, "PORT HDR Init.\n");
+ 
+-	return 0;
++	port_reset(pdev);
++
++	return sysfs_create_files(&pdev->dev.kobj, port_hdr_attrs);
+ }
+ 
+ static void port_hdr_uinit(struct platform_device *pdev,
+ 			   struct dfl_feature *feature)
+ {
+ 	dev_dbg(&pdev->dev, "PORT HDR UInit.\n");
++
++	sysfs_remove_files(&pdev->dev.kobj, port_hdr_attrs);
++}
++
++static long
++port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
++	       unsigned int cmd, unsigned long arg)
++{
++	long ret;
++
++	switch (cmd) {
++	case DFL_FPGA_PORT_RESET:
++		if (!arg)
++			ret = port_reset(pdev);
++		else
++			ret = -EINVAL;
++		break;
++	default:
++		dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
++		ret = -ENODEV;
++	}
++
++	return ret;
+ }
+ 
+ static const struct dfl_feature_ops port_hdr_ops = {
+ 	.init = port_hdr_init,
+ 	.uinit = port_hdr_uinit,
++	.ioctl = port_hdr_ioctl,
+ };
+ 
+ static struct dfl_feature_driver port_feature_drvs[] = {
+@@ -154,6 +230,7 @@ static int afu_release(struct inode *inode, struct file *filp)
+ 
+ 	pdata = dev_get_platdata(&pdev->dev);
+ 
++	port_reset(pdev);
+ 	dfl_feature_dev_use_end(pdata);
+ 
+ 	return 0;
+diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
+index 9666af85a8f5..e6b4dd26cc68 100644
+--- a/include/uapi/linux/fpga-dfl.h
++++ b/include/uapi/linux/fpga-dfl.h
+@@ -29,8 +29,11 @@
+ #define DFL_FPGA_MAGIC 0xB6
+ 
+ #define DFL_FPGA_BASE 0
++#define DFL_PORT_BASE 0x40
+ #define DFL_FME_BASE 0x80
+ 
++/* Common IOCTLs for both FME and AFU file descriptor */
++
+ /**
+  * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
+  *
+@@ -49,6 +52,20 @@
+ 
+ #define DFL_FPGA_CHECK_EXTENSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
+ 
++/* IOCTLs for AFU file descriptor */
++
++/**
++ * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
++ *
++ * Reset the FPGA Port and its AFU. No parameters are supported.
++ * Userspace can do Port reset at any time, e.g. during DMA or PR. But
++ * it should never cause any system level issue, only functional failure
++ * (e.g. DMA or PR operation failure) and be recoverable from the failure.
++ * Return: 0 on success, -errno of failure
++ */
++
++#define DFL_FPGA_PORT_RESET		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
++
+ /* IOCTLs for FME file descriptor */
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1727-fpga-dfl-afu-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch b/patches/1727-fpga-dfl-afu-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
new file mode 100644
index 00000000000000..33cd034f7bc885
--- /dev/null
+++ b/patches/1727-fpga-dfl-afu-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
@@ -0,0 +1,58 @@
+From 8f406e333f1cd2757d31b517e0c193d801710678 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:33 +0800
+Subject: [PATCH 1727/1795] fpga: dfl: afu: add
+ DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support
+
+DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
+ones which need to be supported by all feature devices drivers including
+FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated
+Function Unit (AFU) driver.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 6fd893c409e5939ea2145b27796c155535988734)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/dfl-afu-main.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+index d36b3e9f3984..4074b97122e2 100644
+--- a/drivers/fpga/dfl-afu-main.c
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -236,6 +236,13 @@ static int afu_release(struct inode *inode, struct file *filp)
+ 	return 0;
+ }
+ 
++static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
++				      unsigned long arg)
++{
++	/* No extension support for now */
++	return 0;
++}
++
+ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ {
+ 	struct platform_device *pdev = filp->private_data;
+@@ -248,6 +255,10 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 	pdata = dev_get_platdata(&pdev->dev);
+ 
+ 	switch (cmd) {
++	case DFL_FPGA_GET_API_VERSION:
++		return DFL_FPGA_API_VERSION;
++	case DFL_FPGA_CHECK_EXTENSION:
++		return afu_ioctl_check_extension(pdata, arg);
+ 	default:
+ 		/*
+ 		 * Let sub-feature's ioctl function to handle the cmd
+-- 
+2.19.0
+
diff --git a/patches/1728-fpga-dfl-afu-add-afu-sub-feature-support.patch b/patches/1728-fpga-dfl-afu-add-afu-sub-feature-support.patch
new file mode 100644
index 00000000000000..91d3847226fe95
--- /dev/null
+++ b/patches/1728-fpga-dfl-afu-add-afu-sub-feature-support.patch
@@ -0,0 +1,685 @@
+From f7bbb4a3cedaaeb6ff195c178a176cb0319c2111 Mon Sep 17 00:00:00 2001
+From: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Date: Sat, 30 Jun 2018 08:53:34 +0800
+Subject: [PATCH 1728/1795] fpga: dfl: afu: add afu sub feature support
+
+User Accelerated Function Unit sub feature exposes the MMIO region of
+the AFU. After valid PR bitstream is programmed and the port is enabled,
+then this MMIO region could be accessed.
+
+This patch adds support to enumerate the AFU MMIO region and expose it
+to userspace via mmap file operation. Below interfaces are exposed to user:
+
+Sysfs interface:
+* /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id
+  Read-only. Indicate which PR bitstream is programmed to this AFU.
+
+Ioctl interfaces:
+* DFL_FPGA_PORT_GET_INFO
+  Provide info to userspace on the number of supported region.
+  Only UAFU region is supported now.
+
+* DFL_FPGA_PORT_GET_REGION_INFO
+  Provide region information, including access permission, region size,
+  offset from the start of device fd.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 857a26222ff75eecf7d701ef0e91e4fbf6efa663)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../ABI/testing/sysfs-platform-dfl-port       |   9 +
+ drivers/fpga/Makefile                         |   2 +-
+ drivers/fpga/dfl-afu-main.c                   | 219 +++++++++++++++++-
+ drivers/fpga/dfl-afu-region.c                 | 166 +++++++++++++
+ drivers/fpga/dfl-afu.h                        |  71 ++++++
+ include/uapi/linux/fpga-dfl.h                 |  48 ++++
+ 6 files changed, 508 insertions(+), 7 deletions(-)
+ create mode 100644 drivers/fpga/dfl-afu-region.c
+ create mode 100644 drivers/fpga/dfl-afu.h
+
+diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port
+index cb91165f5397..6a92dda517b0 100644
+--- a/Documentation/ABI/testing/sysfs-platform-dfl-port
++++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
+@@ -5,3 +5,12 @@ Contact:	Wu Hao <hao.wu@intel.com>
+ Description:	Read-only. It returns id of this port. One DFL FPGA device
+ 		may have more than one port. Userspace could use this id to
+ 		distinguish different ports under same FPGA device.
++
++What:		/sys/bus/platform/devices/dfl-port.0/afu_id
++Date:		June 2018
++KernelVersion:	4.19
++Contact:	Wu Hao <hao.wu@intel.com>
++Description:	Read-only. User can program different PR bitstreams to FPGA
++		Accelerator Function Unit (AFU) for different functions. It
++		returns uuid which could be used to identify which PR bitstream
++		is programmed in this AFU.
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index 1ac7749b2542..a44d50dd0b70 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
+ obj-$(CONFIG_FPGA_DFL_AFU)		+= dfl-afu.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+-dfl-afu-objs := dfl-afu-main.o
++dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
+ 
+ # Drivers for FPGAs which implement DFL
+ obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+index 4074b97122e2..f67a78d7e9ad 100644
+--- a/drivers/fpga/dfl-afu-main.c
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -16,18 +16,18 @@
+ 
+ #include <linux/kernel.h>
+ #include <linux/module.h>
++#include <linux/uaccess.h>
+ #include <linux/fpga-dfl.h>
+ 
+-#include "dfl.h"
++#include "dfl-afu.h"
+ 
+ /**
+  * port_enable - enable a port
+  * @pdev: port platform device.
+  *
+  * Enable Port by clear the port soft reset bit, which is set by default.
+- * The User AFU is unable to respond to any MMIO access while in reset.
+- * port_enable function should only be used after port_disable
+- * function.
++ * The AFU is unable to respond to any MMIO access while in reset.
++ * port_enable function should only be used after port_disable function.
+  */
+ static void port_enable(struct platform_device *pdev)
+ {
+@@ -191,11 +191,74 @@ static const struct dfl_feature_ops port_hdr_ops = {
+ 	.ioctl = port_hdr_ioctl,
+ };
+ 
++static ssize_t
++afu_id_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
++	void __iomem *base;
++	u64 guidl, guidh;
++
++	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU);
++
++	mutex_lock(&pdata->lock);
++	if (pdata->disable_count) {
++		mutex_unlock(&pdata->lock);
++		return -EBUSY;
++	}
++
++	guidl = readq(base + GUID_L);
++	guidh = readq(base + GUID_H);
++	mutex_unlock(&pdata->lock);
++
++	return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl);
++}
++static DEVICE_ATTR_RO(afu_id);
++
++static const struct attribute *port_afu_attrs[] = {
++	&dev_attr_afu_id.attr,
++	NULL
++};
++
++static int port_afu_init(struct platform_device *pdev,
++			 struct dfl_feature *feature)
++{
++	struct resource *res = &pdev->resource[feature->resource_index];
++	int ret;
++
++	dev_dbg(&pdev->dev, "PORT AFU Init.\n");
++
++	ret = afu_mmio_region_add(dev_get_platdata(&pdev->dev),
++				  DFL_PORT_REGION_INDEX_AFU, resource_size(res),
++				  res->start, DFL_PORT_REGION_READ |
++				  DFL_PORT_REGION_WRITE | DFL_PORT_REGION_MMAP);
++	if (ret)
++		return ret;
++
++	return sysfs_create_files(&pdev->dev.kobj, port_afu_attrs);
++}
++
++static void port_afu_uinit(struct platform_device *pdev,
++			   struct dfl_feature *feature)
++{
++	dev_dbg(&pdev->dev, "PORT AFU UInit.\n");
++
++	sysfs_remove_files(&pdev->dev.kobj, port_afu_attrs);
++}
++
++static const struct dfl_feature_ops port_afu_ops = {
++	.init = port_afu_init,
++	.uinit = port_afu_uinit,
++};
++
+ static struct dfl_feature_driver port_feature_drvs[] = {
+ 	{
+ 		.id = PORT_FEATURE_ID_HEADER,
+ 		.ops = &port_hdr_ops,
+ 	},
++	{
++		.id = PORT_FEATURE_ID_AFU,
++		.ops = &port_afu_ops,
++	},
+ 	{
+ 		.ops = NULL,
+ 	}
+@@ -243,6 +306,64 @@ static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
+ 	return 0;
+ }
+ 
++static long
++afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg)
++{
++	struct dfl_fpga_port_info info;
++	struct dfl_afu *afu;
++	unsigned long minsz;
++
++	minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs);
++
++	if (copy_from_user(&info, arg, minsz))
++		return -EFAULT;
++
++	if (info.argsz < minsz)
++		return -EINVAL;
++
++	mutex_lock(&pdata->lock);
++	afu = dfl_fpga_pdata_get_private(pdata);
++	info.flags = 0;
++	info.num_regions = afu->num_regions;
++	info.num_umsgs = afu->num_umsgs;
++	mutex_unlock(&pdata->lock);
++
++	if (copy_to_user(arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
++
++static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata,
++				      void __user *arg)
++{
++	struct dfl_fpga_port_region_info rinfo;
++	struct dfl_afu_mmio_region region;
++	unsigned long minsz;
++	long ret;
++
++	minsz = offsetofend(struct dfl_fpga_port_region_info, offset);
++
++	if (copy_from_user(&rinfo, arg, minsz))
++		return -EFAULT;
++
++	if (rinfo.argsz < minsz || rinfo.padding)
++		return -EINVAL;
++
++	ret = afu_mmio_region_get_by_index(pdata, rinfo.index, &region);
++	if (ret)
++		return ret;
++
++	rinfo.flags = region.flags;
++	rinfo.size = region.size;
++	rinfo.offset = region.offset;
++
++	if (copy_to_user(arg, &rinfo, sizeof(rinfo)))
++		return -EFAULT;
++
++	return 0;
++}
++
+ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ {
+ 	struct platform_device *pdev = filp->private_data;
+@@ -259,6 +380,10 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 		return DFL_FPGA_API_VERSION;
+ 	case DFL_FPGA_CHECK_EXTENSION:
+ 		return afu_ioctl_check_extension(pdata, arg);
++	case DFL_FPGA_PORT_GET_INFO:
++		return afu_ioctl_get_info(pdata, (void __user *)arg);
++	case DFL_FPGA_PORT_GET_REGION_INFO:
++		return afu_ioctl_get_region_info(pdata, (void __user *)arg);
+ 	default:
+ 		/*
+ 		 * Let sub-feature's ioctl function to handle the cmd
+@@ -277,13 +402,83 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 	return -EINVAL;
+ }
+ 
++static int afu_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++	struct platform_device *pdev = filp->private_data;
++	struct dfl_feature_platform_data *pdata;
++	u64 size = vma->vm_end - vma->vm_start;
++	struct dfl_afu_mmio_region region;
++	u64 offset;
++	int ret;
++
++	if (!(vma->vm_flags & VM_SHARED))
++		return -EINVAL;
++
++	pdata = dev_get_platdata(&pdev->dev);
++
++	offset = vma->vm_pgoff << PAGE_SHIFT;
++	ret = afu_mmio_region_get_by_offset(pdata, offset, size, &region);
++	if (ret)
++		return ret;
++
++	if (!(region.flags & DFL_PORT_REGION_MMAP))
++		return -EINVAL;
++
++	if ((vma->vm_flags & VM_READ) && !(region.flags & DFL_PORT_REGION_READ))
++		return -EPERM;
++
++	if ((vma->vm_flags & VM_WRITE) &&
++	    !(region.flags & DFL_PORT_REGION_WRITE))
++		return -EPERM;
++
++	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++	return remap_pfn_range(vma, vma->vm_start,
++			(region.phys + (offset - region.offset)) >> PAGE_SHIFT,
++			size, vma->vm_page_prot);
++}
++
+ static const struct file_operations afu_fops = {
+ 	.owner = THIS_MODULE,
+ 	.open = afu_open,
+ 	.release = afu_release,
+ 	.unlocked_ioctl = afu_ioctl,
++	.mmap = afu_mmap,
+ };
+ 
++static int afu_dev_init(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_afu *afu;
++
++	afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL);
++	if (!afu)
++		return -ENOMEM;
++
++	afu->pdata = pdata;
++
++	mutex_lock(&pdata->lock);
++	dfl_fpga_pdata_set_private(pdata, afu);
++	afu_mmio_region_init(pdata);
++	mutex_unlock(&pdata->lock);
++
++	return 0;
++}
++
++static int afu_dev_destroy(struct platform_device *pdev)
++{
++	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct dfl_afu *afu;
++
++	mutex_lock(&pdata->lock);
++	afu = dfl_fpga_pdata_get_private(pdata);
++	afu_mmio_region_destroy(pdata);
++	dfl_fpga_pdata_set_private(pdata, NULL);
++	mutex_unlock(&pdata->lock);
++
++	return 0;
++}
++
+ static int port_enable_set(struct platform_device *pdev, bool enable)
+ {
+ 	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
+@@ -312,14 +507,25 @@ static int afu_probe(struct platform_device *pdev)
+ 
+ 	dev_dbg(&pdev->dev, "%s\n", __func__);
+ 
++	ret = afu_dev_init(pdev);
++	if (ret)
++		goto exit;
++
+ 	ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs);
+ 	if (ret)
+-		return ret;
++		goto dev_destroy;
+ 
+ 	ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE);
+-	if (ret)
++	if (ret) {
+ 		dfl_fpga_dev_feature_uinit(pdev);
++		goto dev_destroy;
++	}
++
++	return 0;
+ 
++dev_destroy:
++	afu_dev_destroy(pdev);
++exit:
+ 	return ret;
+ }
+ 
+@@ -329,6 +535,7 @@ static int afu_remove(struct platform_device *pdev)
+ 
+ 	dfl_fpga_dev_ops_unregister(pdev);
+ 	dfl_fpga_dev_feature_uinit(pdev);
++	afu_dev_destroy(pdev);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl-afu-region.c
+new file mode 100644
+index 000000000000..0804b7a0c298
+--- /dev/null
++++ b/drivers/fpga/dfl-afu-region.c
+@@ -0,0 +1,166 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Accelerated Function Unit (AFU) MMIO Region Management
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ */
++#include "dfl-afu.h"
++
++/**
++ * afu_mmio_region_init - init function for afu mmio region support
++ * @pdata: afu platform device's pdata.
++ */
++void afu_mmio_region_init(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++
++	INIT_LIST_HEAD(&afu->regions);
++}
++
++#define for_each_region(region, afu)	\
++	list_for_each_entry((region), &(afu)->regions, node)
++
++static struct dfl_afu_mmio_region *get_region_by_index(struct dfl_afu *afu,
++						       u32 region_index)
++{
++	struct dfl_afu_mmio_region *region;
++
++	for_each_region(region, afu)
++		if (region->index == region_index)
++			return region;
++
++	return NULL;
++}
++
++/**
++ * afu_mmio_region_add - add a mmio region to given feature dev.
++ *
++ * @region_index: region index.
++ * @region_size: region size.
++ * @phys: region's physical address of this region.
++ * @flags: region flags (access permission).
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int afu_mmio_region_add(struct dfl_feature_platform_data *pdata,
++			u32 region_index, u64 region_size, u64 phys, u32 flags)
++{
++	struct dfl_afu_mmio_region *region;
++	struct dfl_afu *afu;
++	int ret = 0;
++
++	region = devm_kzalloc(&pdata->dev->dev, sizeof(*region), GFP_KERNEL);
++	if (!region)
++		return -ENOMEM;
++
++	region->index = region_index;
++	region->size = region_size;
++	region->phys = phys;
++	region->flags = flags;
++
++	mutex_lock(&pdata->lock);
++
++	afu = dfl_fpga_pdata_get_private(pdata);
++
++	/* check if @index already exists */
++	if (get_region_by_index(afu, region_index)) {
++		mutex_unlock(&pdata->lock);
++		ret = -EEXIST;
++		goto exit;
++	}
++
++	region_size = PAGE_ALIGN(region_size);
++	region->offset = afu->region_cur_offset;
++	list_add(&region->node, &afu->regions);
++
++	afu->region_cur_offset += region_size;
++	afu->num_regions++;
++	mutex_unlock(&pdata->lock);
++
++	return 0;
++
++exit:
++	devm_kfree(&pdata->dev->dev, region);
++	return ret;
++}
++
++/**
++ * afu_mmio_region_destroy - destroy all mmio regions under given feature dev.
++ * @pdata: afu platform device's pdata.
++ */
++void afu_mmio_region_destroy(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++	struct dfl_afu_mmio_region *tmp, *region;
++
++	list_for_each_entry_safe(region, tmp, &afu->regions, node)
++		devm_kfree(&pdata->dev->dev, region);
++}
++
++/**
++ * afu_mmio_region_get_by_index - find an afu region by index.
++ * @pdata: afu platform device's pdata.
++ * @region_index: region index.
++ * @pregion: ptr to region for result.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata,
++				 u32 region_index,
++				 struct dfl_afu_mmio_region *pregion)
++{
++	struct dfl_afu_mmio_region *region;
++	struct dfl_afu *afu;
++	int ret = 0;
++
++	mutex_lock(&pdata->lock);
++	afu = dfl_fpga_pdata_get_private(pdata);
++	region = get_region_by_index(afu, region_index);
++	if (!region) {
++		ret = -EINVAL;
++		goto exit;
++	}
++	*pregion = *region;
++exit:
++	mutex_unlock(&pdata->lock);
++	return ret;
++}
++
++/**
++ * afu_mmio_region_get_by_offset - find an afu mmio region by offset and size
++ *
++ * @pdata: afu platform device's pdata.
++ * @offset: region offset from start of the device fd.
++ * @size: region size.
++ * @pregion: ptr to region for result.
++ *
++ * Find the region which fully contains the region described by input
++ * parameters (offset and size) from the feature dev's region linked list.
++ *
++ * Return: 0 on success, negative error code otherwise.
++ */
++int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata,
++				  u64 offset, u64 size,
++				  struct dfl_afu_mmio_region *pregion)
++{
++	struct dfl_afu_mmio_region *region;
++	struct dfl_afu *afu;
++	int ret = 0;
++
++	mutex_lock(&pdata->lock);
++	afu = dfl_fpga_pdata_get_private(pdata);
++	for_each_region(region, afu)
++		if (region->offset <= offset &&
++		    region->offset + region->size >= offset + size) {
++			*pregion = *region;
++			goto exit;
++		}
++	ret = -EINVAL;
++exit:
++	mutex_unlock(&pdata->lock);
++	return ret;
++}
+diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h
+new file mode 100644
+index 000000000000..11ce2cf99759
+--- /dev/null
++++ b/drivers/fpga/dfl-afu.h
+@@ -0,0 +1,71 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Header file for FPGA Accelerated Function Unit (AFU) Driver
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *     Wu Hao <hao.wu@intel.com>
++ *     Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ *     Joseph Grecco <joe.grecco@intel.com>
++ *     Enno Luebbers <enno.luebbers@intel.com>
++ *     Tim Whisonant <tim.whisonant@intel.com>
++ *     Ananda Ravuri <ananda.ravuri@intel.com>
++ *     Henry Mitchel <henry.mitchel@intel.com>
++ */
++
++#ifndef __DFL_AFU_H
++#define __DFL_AFU_H
++
++#include <linux/mm.h>
++
++#include "dfl.h"
++
++/**
++ * struct dfl_afu_mmio_region - afu mmio region data structure
++ *
++ * @index: region index.
++ * @flags: region flags (access permission).
++ * @size: region size.
++ * @offset: region offset from start of the device fd.
++ * @phys: region's physical address.
++ * @node: node to add to afu feature dev's region list.
++ */
++struct dfl_afu_mmio_region {
++	u32 index;
++	u32 flags;
++	u64 size;
++	u64 offset;
++	u64 phys;
++	struct list_head node;
++};
++
++/**
++ * struct dfl_afu - afu device data structure
++ *
++ * @region_cur_offset: current region offset from start to the device fd.
++ * @num_regions: num of mmio regions.
++ * @regions: the mmio region linked list of this afu feature device.
++ * @num_umsgs: num of umsgs.
++ * @pdata: afu platform device's pdata.
++ */
++struct dfl_afu {
++	u64 region_cur_offset;
++	int num_regions;
++	u8 num_umsgs;
++	struct list_head regions;
++
++	struct dfl_feature_platform_data *pdata;
++};
++
++void afu_mmio_region_init(struct dfl_feature_platform_data *pdata);
++int afu_mmio_region_add(struct dfl_feature_platform_data *pdata,
++			u32 region_index, u64 region_size, u64 phys, u32 flags);
++void afu_mmio_region_destroy(struct dfl_feature_platform_data *pdata);
++int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata,
++				 u32 region_index,
++				 struct dfl_afu_mmio_region *pregion);
++int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata,
++				  u64 offset, u64 size,
++				  struct dfl_afu_mmio_region *pregion);
++#endif
+diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
+index e6b4dd26cc68..a3ccdfb115a5 100644
+--- a/include/uapi/linux/fpga-dfl.h
++++ b/include/uapi/linux/fpga-dfl.h
+@@ -66,6 +66,54 @@
+ 
+ #define DFL_FPGA_PORT_RESET		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
+ 
++/**
++ * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
++ *						struct dfl_fpga_port_info)
++ *
++ * Retrieve information about the fpga port.
++ * Driver fills the info in provided struct dfl_fpga_port_info.
++ * Return: 0 on success, -errno on failure.
++ */
++struct dfl_fpga_port_info {
++	/* Input */
++	__u32 argsz;		/* Structure length */
++	/* Output */
++	__u32 flags;		/* Zero for now */
++	__u32 num_regions;	/* The number of supported regions */
++	__u32 num_umsgs;	/* The number of allocated umsgs */
++};
++
++#define DFL_FPGA_PORT_GET_INFO		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
++
++/**
++ * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2,
++ *					struct dfl_fpga_port_region_info)
++ *
++ * Retrieve information about a device memory region.
++ * Caller provides struct dfl_fpga_port_region_info with index value set.
++ * Driver returns the region info in other fields.
++ * Return: 0 on success, -errno on failure.
++ */
++struct dfl_fpga_port_region_info {
++	/* input */
++	__u32 argsz;		/* Structure length */
++	/* Output */
++	__u32 flags;		/* Access permission */
++#define DFL_PORT_REGION_READ	(1 << 0)	/* Region is readable */
++#define DFL_PORT_REGION_WRITE	(1 << 1)	/* Region is writable */
++#define DFL_PORT_REGION_MMAP	(1 << 2)	/* Can be mmaped to userspace */
++	/* Input */
++	__u32 index;		/* Region index */
++#define DFL_PORT_REGION_INDEX_AFU	0	/* AFU */
++#define DFL_PORT_REGION_INDEX_STP	1	/* Signal Tap */
++	__u32 padding;
++	/* Output */
++	__u64 size;		/* Region size (bytes) */
++	__u64 offset;		/* Region offset from start of device fd */
++};
++
++#define DFL_FPGA_PORT_GET_REGION_INFO	_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
++
+ /* IOCTLs for FME file descriptor */
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1729-fpga-dfl-afu-add-DFL_FPGA_PORT_DMA_MAP-UNMAP-ioctls-.patch b/patches/1729-fpga-dfl-afu-add-DFL_FPGA_PORT_DMA_MAP-UNMAP-ioctls-.patch
new file mode 100644
index 00000000000000..b3ac2c356ea30a
--- /dev/null
+++ b/patches/1729-fpga-dfl-afu-add-DFL_FPGA_PORT_DMA_MAP-UNMAP-ioctls-.patch
@@ -0,0 +1,734 @@
+From d7f76be7d2790d204ccb565b32cf000fc4faac0c Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:35 +0800
+Subject: [PATCH 1729/1795] fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP
+ ioctls support
+
+DMA memory regions are required for Accelerated Function Unit (AFU) usage.
+These two ioctls allow user space applications to map user memory regions
+for dma, and unmap them after use. Iova is returned from driver to user
+space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
+unmap it after use, otherwise, driver will unmap them in device file
+release operation.
+
+Each AFU has its own rb tree to keep track of its mapped DMA regions.
+
+Ioctl interfaces:
+* DFL_FPGA_PORT_DMA_MAP
+  Do the dma mapping per user_addr and length provided by user.
+  Return iova in provided struct dfl_fpga_port_dma_map.
+
+* DFL_FPGA_PORT_DMA_UNMAP
+  Unmap the dma region per iova provided by user.
+
+Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
+Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
+Signed-off-by: Shiva Rao <shiva.rao@intel.com>
+Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
+Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit fa8dda1edef9ebc3af467c644c5533ac97171e12)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/Makefile             |   2 +-
+ drivers/fpga/dfl-afu-dma-region.c | 463 ++++++++++++++++++++++++++++++
+ drivers/fpga/dfl-afu-main.c       |  61 +++-
+ drivers/fpga/dfl-afu.h            |  31 +-
+ include/uapi/linux/fpga-dfl.h     |  37 +++
+ 5 files changed, 591 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/fpga/dfl-afu-dma-region.c
+
+diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
+index a44d50dd0b70..7a2d73ba7122 100644
+--- a/drivers/fpga/Makefile
++++ b/drivers/fpga/Makefile
+@@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
+ obj-$(CONFIG_FPGA_DFL_AFU)		+= dfl-afu.o
+ 
+ dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
+-dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
++dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
+ 
+ # Drivers for FPGAs which implement DFL
+ obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o
+diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c
+new file mode 100644
+index 000000000000..0e81d33af856
+--- /dev/null
++++ b/drivers/fpga/dfl-afu-dma-region.c
+@@ -0,0 +1,463 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for FPGA Accelerated Function Unit (AFU) DMA Region Management
++ *
++ * Copyright (C) 2017-2018 Intel Corporation, Inc.
++ *
++ * Authors:
++ *   Wu Hao <hao.wu@intel.com>
++ *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/sched/signal.h>
++#include <linux/uaccess.h>
++
++#include "dfl-afu.h"
++
++static void put_all_pages(struct page **pages, int npages)
++{
++	int i;
++
++	for (i = 0; i < npages; i++)
++		if (pages[i])
++			put_page(pages[i]);
++}
++
++void afu_dma_region_init(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++
++	afu->dma_regions = RB_ROOT;
++}
++
++/**
++ * afu_dma_adjust_locked_vm - adjust locked memory
++ * @dev: port device
++ * @npages: number of pages
++ * @incr: increase or decrease locked memory
++ *
++ * Increase or decrease the locked memory size with npages input.
++ *
++ * Return 0 on success.
++ * Return -ENOMEM if locked memory size is over the limit and no CAP_IPC_LOCK.
++ */
++static int afu_dma_adjust_locked_vm(struct device *dev, long npages, bool incr)
++{
++	unsigned long locked, lock_limit;
++	int ret = 0;
++
++	/* the task is exiting. */
++	if (!current->mm)
++		return 0;
++
++	down_write(&current->mm->mmap_sem);
++
++	if (incr) {
++		locked = current->mm->locked_vm + npages;
++		lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
++
++		if (locked > lock_limit && !capable(CAP_IPC_LOCK))
++			ret = -ENOMEM;
++		else
++			current->mm->locked_vm += npages;
++	} else {
++		if (WARN_ON_ONCE(npages > current->mm->locked_vm))
++			npages = current->mm->locked_vm;
++		current->mm->locked_vm -= npages;
++	}
++
++	dev_dbg(dev, "[%d] RLIMIT_MEMLOCK %c%ld %ld/%ld%s\n", current->pid,
++		incr ? '+' : '-', npages << PAGE_SHIFT,
++		current->mm->locked_vm << PAGE_SHIFT, rlimit(RLIMIT_MEMLOCK),
++		ret ? "- execeeded" : "");
++
++	up_write(&current->mm->mmap_sem);
++
++	return ret;
++}
++
++/**
++ * afu_dma_pin_pages - pin pages of given dma memory region
++ * @pdata: feature device platform data
++ * @region: dma memory region to be pinned
++ *
++ * Pin all the pages of given dfl_afu_dma_region.
++ * Return 0 for success or negative error code.
++ */
++static int afu_dma_pin_pages(struct dfl_feature_platform_data *pdata,
++			     struct dfl_afu_dma_region *region)
++{
++	int npages = region->length >> PAGE_SHIFT;
++	struct device *dev = &pdata->dev->dev;
++	int ret, pinned;
++
++	ret = afu_dma_adjust_locked_vm(dev, npages, true);
++	if (ret)
++		return ret;
++
++	region->pages = kcalloc(npages, sizeof(struct page *), GFP_KERNEL);
++	if (!region->pages) {
++		ret = -ENOMEM;
++		goto unlock_vm;
++	}
++
++	pinned = get_user_pages_fast(region->user_addr, npages, 1,
++				     region->pages);
++	if (pinned < 0) {
++		ret = pinned;
++		goto put_pages;
++	} else if (pinned != npages) {
++		ret = -EFAULT;
++		goto free_pages;
++	}
++
++	dev_dbg(dev, "%d pages pinned\n", pinned);
++
++	return 0;
++
++put_pages:
++	put_all_pages(region->pages, pinned);
++free_pages:
++	kfree(region->pages);
++unlock_vm:
++	afu_dma_adjust_locked_vm(dev, npages, false);
++	return ret;
++}
++
++/**
++ * afu_dma_unpin_pages - unpin pages of given dma memory region
++ * @pdata: feature device platform data
++ * @region: dma memory region to be unpinned
++ *
++ * Unpin all the pages of given dfl_afu_dma_region.
++ * Return 0 for success or negative error code.
++ */
++static void afu_dma_unpin_pages(struct dfl_feature_platform_data *pdata,
++				struct dfl_afu_dma_region *region)
++{
++	long npages = region->length >> PAGE_SHIFT;
++	struct device *dev = &pdata->dev->dev;
++
++	put_all_pages(region->pages, npages);
++	kfree(region->pages);
++	afu_dma_adjust_locked_vm(dev, npages, false);
++
++	dev_dbg(dev, "%ld pages unpinned\n", npages);
++}
++
++/**
++ * afu_dma_check_continuous_pages - check if pages are continuous
++ * @region: dma memory region
++ *
++ * Return true if pages of given dma memory region have continuous physical
++ * address, otherwise return false.
++ */
++static bool afu_dma_check_continuous_pages(struct dfl_afu_dma_region *region)
++{
++	int npages = region->length >> PAGE_SHIFT;
++	int i;
++
++	for (i = 0; i < npages - 1; i++)
++		if (page_to_pfn(region->pages[i]) + 1 !=
++				page_to_pfn(region->pages[i + 1]))
++			return false;
++
++	return true;
++}
++
++/**
++ * dma_region_check_iova - check if memory area is fully contained in the region
++ * @region: dma memory region
++ * @iova: address of the dma memory area
++ * @size: size of the dma memory area
++ *
++ * Compare the dma memory area defined by @iova and @size with given dma region.
++ * Return true if memory area is fully contained in the region, otherwise false.
++ */
++static bool dma_region_check_iova(struct dfl_afu_dma_region *region,
++				  u64 iova, u64 size)
++{
++	if (!size && region->iova != iova)
++		return false;
++
++	return (region->iova <= iova) &&
++		(region->length + region->iova >= iova + size);
++}
++
++/**
++ * afu_dma_region_add - add given dma region to rbtree
++ * @pdata: feature device platform data
++ * @region: dma region to be added
++ *
++ * Return 0 for success, -EEXIST if dma region has already been added.
++ *
++ * Needs to be called with pdata->lock heold.
++ */
++static int afu_dma_region_add(struct dfl_feature_platform_data *pdata,
++			      struct dfl_afu_dma_region *region)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++	struct rb_node **new, *parent = NULL;
++
++	dev_dbg(&pdata->dev->dev, "add region (iova = %llx)\n",
++		(unsigned long long)region->iova);
++
++	new = &afu->dma_regions.rb_node;
++
++	while (*new) {
++		struct dfl_afu_dma_region *this;
++
++		this = container_of(*new, struct dfl_afu_dma_region, node);
++
++		parent = *new;
++
++		if (dma_region_check_iova(this, region->iova, region->length))
++			return -EEXIST;
++
++		if (region->iova < this->iova)
++			new = &((*new)->rb_left);
++		else if (region->iova > this->iova)
++			new = &((*new)->rb_right);
++		else
++			return -EEXIST;
++	}
++
++	rb_link_node(&region->node, parent, new);
++	rb_insert_color(&region->node, &afu->dma_regions);
++
++	return 0;
++}
++
++/**
++ * afu_dma_region_remove - remove given dma region from rbtree
++ * @pdata: feature device platform data
++ * @region: dma region to be removed
++ *
++ * Needs to be called with pdata->lock heold.
++ */
++static void afu_dma_region_remove(struct dfl_feature_platform_data *pdata,
++				  struct dfl_afu_dma_region *region)
++{
++	struct dfl_afu *afu;
++
++	dev_dbg(&pdata->dev->dev, "del region (iova = %llx)\n",
++		(unsigned long long)region->iova);
++
++	afu = dfl_fpga_pdata_get_private(pdata);
++	rb_erase(&region->node, &afu->dma_regions);
++}
++
++/**
++ * afu_dma_region_destroy - destroy all regions in rbtree
++ * @pdata: feature device platform data
++ *
++ * Needs to be called with pdata->lock heold.
++ */
++void afu_dma_region_destroy(struct dfl_feature_platform_data *pdata)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++	struct rb_node *node = rb_first(&afu->dma_regions);
++	struct dfl_afu_dma_region *region;
++
++	while (node) {
++		region = container_of(node, struct dfl_afu_dma_region, node);
++
++		dev_dbg(&pdata->dev->dev, "del region (iova = %llx)\n",
++			(unsigned long long)region->iova);
++
++		rb_erase(node, &afu->dma_regions);
++
++		if (region->iova)
++			dma_unmap_page(dfl_fpga_pdata_to_parent(pdata),
++				       region->iova, region->length,
++				       DMA_BIDIRECTIONAL);
++
++		if (region->pages)
++			afu_dma_unpin_pages(pdata, region);
++
++		node = rb_next(node);
++		kfree(region);
++	}
++}
++
++/**
++ * afu_dma_region_find - find the dma region from rbtree based on iova and size
++ * @pdata: feature device platform data
++ * @iova: address of the dma memory area
++ * @size: size of the dma memory area
++ *
++ * It finds the dma region from the rbtree based on @iova and @size:
++ * - if @size == 0, it finds the dma region which starts from @iova
++ * - otherwise, it finds the dma region which fully contains
++ *   [@iova, @iova+size)
++ * If nothing is matched returns NULL.
++ *
++ * Needs to be called with pdata->lock held.
++ */
++struct dfl_afu_dma_region *
++afu_dma_region_find(struct dfl_feature_platform_data *pdata, u64 iova, u64 size)
++{
++	struct dfl_afu *afu = dfl_fpga_pdata_get_private(pdata);
++	struct rb_node *node = afu->dma_regions.rb_node;
++	struct device *dev = &pdata->dev->dev;
++
++	while (node) {
++		struct dfl_afu_dma_region *region;
++
++		region = container_of(node, struct dfl_afu_dma_region, node);
++
++		if (dma_region_check_iova(region, iova, size)) {
++			dev_dbg(dev, "find region (iova = %llx)\n",
++				(unsigned long long)region->iova);
++			return region;
++		}
++
++		if (iova < region->iova)
++			node = node->rb_left;
++		else if (iova > region->iova)
++			node = node->rb_right;
++		else
++			/* the iova region is not fully covered. */
++			break;
++	}
++
++	dev_dbg(dev, "region with iova %llx and size %llx is not found\n",
++		(unsigned long long)iova, (unsigned long long)size);
++
++	return NULL;
++}
++
++/**
++ * afu_dma_region_find_iova - find the dma region from rbtree by iova
++ * @pdata: feature device platform data
++ * @iova: address of the dma region
++ *
++ * Needs to be called with pdata->lock held.
++ */
++static struct dfl_afu_dma_region *
++afu_dma_region_find_iova(struct dfl_feature_platform_data *pdata, u64 iova)
++{
++	return afu_dma_region_find(pdata, iova, 0);
++}
++
++/**
++ * afu_dma_map_region - map memory region for dma
++ * @pdata: feature device platform data
++ * @user_addr: address of the memory region
++ * @length: size of the memory region
++ * @iova: pointer of iova address
++ *
++ * Map memory region defined by @user_addr and @length, and return dma address
++ * of the memory region via @iova.
++ * Return 0 for success, otherwise error code.
++ */
++int afu_dma_map_region(struct dfl_feature_platform_data *pdata,
++		       u64 user_addr, u64 length, u64 *iova)
++{
++	struct dfl_afu_dma_region *region;
++	int ret;
++
++	/*
++	 * Check Inputs, only accept page-aligned user memory region with
++	 * valid length.
++	 */
++	if (!PAGE_ALIGNED(user_addr) || !PAGE_ALIGNED(length) || !length)
++		return -EINVAL;
++
++	/* Check overflow */
++	if (user_addr + length < user_addr)
++		return -EINVAL;
++
++	if (!access_ok(VERIFY_WRITE, (void __user *)(unsigned long)user_addr,
++		       length))
++		return -EINVAL;
++
++	region = kzalloc(sizeof(*region), GFP_KERNEL);
++	if (!region)
++		return -ENOMEM;
++
++	region->user_addr = user_addr;
++	region->length = length;
++
++	/* Pin the user memory region */
++	ret = afu_dma_pin_pages(pdata, region);
++	if (ret) {
++		dev_err(&pdata->dev->dev, "failed to pin memory region\n");
++		goto free_region;
++	}
++
++	/* Only accept continuous pages, return error else */
++	if (!afu_dma_check_continuous_pages(region)) {
++		dev_err(&pdata->dev->dev, "pages are not continuous\n");
++		ret = -EINVAL;
++		goto unpin_pages;
++	}
++
++	/* As pages are continuous then start to do DMA mapping */
++	region->iova = dma_map_page(dfl_fpga_pdata_to_parent(pdata),
++				    region->pages[0], 0,
++				    region->length,
++				    DMA_BIDIRECTIONAL);
++	if (dma_mapping_error(&pdata->dev->dev, region->iova)) {
++		dev_err(&pdata->dev->dev, "failed to map for dma\n");
++		ret = -EFAULT;
++		goto unpin_pages;
++	}
++
++	*iova = region->iova;
++
++	mutex_lock(&pdata->lock);
++	ret = afu_dma_region_add(pdata, region);
++	mutex_unlock(&pdata->lock);
++	if (ret) {
++		dev_err(&pdata->dev->dev, "failed to add dma region\n");
++		goto unmap_dma;
++	}
++
++	return 0;
++
++unmap_dma:
++	dma_unmap_page(dfl_fpga_pdata_to_parent(pdata),
++		       region->iova, region->length, DMA_BIDIRECTIONAL);
++unpin_pages:
++	afu_dma_unpin_pages(pdata, region);
++free_region:
++	kfree(region);
++	return ret;
++}
++
++/**
++ * afu_dma_unmap_region - unmap dma memory region
++ * @pdata: feature device platform data
++ * @iova: dma address of the region
++ *
++ * Unmap dma memory region based on @iova.
++ * Return 0 for success, otherwise error code.
++ */
++int afu_dma_unmap_region(struct dfl_feature_platform_data *pdata, u64 iova)
++{
++	struct dfl_afu_dma_region *region;
++
++	mutex_lock(&pdata->lock);
++	region = afu_dma_region_find_iova(pdata, iova);
++	if (!region) {
++		mutex_unlock(&pdata->lock);
++		return -EINVAL;
++	}
++
++	if (region->in_use) {
++		mutex_unlock(&pdata->lock);
++		return -EBUSY;
++	}
++
++	afu_dma_region_remove(pdata, region);
++	mutex_unlock(&pdata->lock);
++
++	dma_unmap_page(dfl_fpga_pdata_to_parent(pdata),
++		       region->iova, region->length, DMA_BIDIRECTIONAL);
++	afu_dma_unpin_pages(pdata, region);
++	kfree(region);
++
++	return 0;
++}
+diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
+index f67a78d7e9ad..02baa6a227c0 100644
+--- a/drivers/fpga/dfl-afu-main.c
++++ b/drivers/fpga/dfl-afu-main.c
+@@ -293,7 +293,11 @@ static int afu_release(struct inode *inode, struct file *filp)
+ 
+ 	pdata = dev_get_platdata(&pdev->dev);
+ 
+-	port_reset(pdev);
++	mutex_lock(&pdata->lock);
++	__port_reset(pdev);
++	afu_dma_region_destroy(pdata);
++	mutex_unlock(&pdata->lock);
++
+ 	dfl_feature_dev_use_end(pdata);
+ 
+ 	return 0;
+@@ -364,6 +368,55 @@ static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata,
+ 	return 0;
+ }
+ 
++static long
++afu_ioctl_dma_map(struct dfl_feature_platform_data *pdata, void __user *arg)
++{
++	struct dfl_fpga_port_dma_map map;
++	unsigned long minsz;
++	long ret;
++
++	minsz = offsetofend(struct dfl_fpga_port_dma_map, iova);
++
++	if (copy_from_user(&map, arg, minsz))
++		return -EFAULT;
++
++	if (map.argsz < minsz || map.flags)
++		return -EINVAL;
++
++	ret = afu_dma_map_region(pdata, map.user_addr, map.length, &map.iova);
++	if (ret)
++		return ret;
++
++	if (copy_to_user(arg, &map, sizeof(map))) {
++		afu_dma_unmap_region(pdata, map.iova);
++		return -EFAULT;
++	}
++
++	dev_dbg(&pdata->dev->dev, "dma map: ua=%llx, len=%llx, iova=%llx\n",
++		(unsigned long long)map.user_addr,
++		(unsigned long long)map.length,
++		(unsigned long long)map.iova);
++
++	return 0;
++}
++
++static long
++afu_ioctl_dma_unmap(struct dfl_feature_platform_data *pdata, void __user *arg)
++{
++	struct dfl_fpga_port_dma_unmap unmap;
++	unsigned long minsz;
++
++	minsz = offsetofend(struct dfl_fpga_port_dma_unmap, iova);
++
++	if (copy_from_user(&unmap, arg, minsz))
++		return -EFAULT;
++
++	if (unmap.argsz < minsz || unmap.flags)
++		return -EINVAL;
++
++	return afu_dma_unmap_region(pdata, unmap.iova);
++}
++
+ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ {
+ 	struct platform_device *pdev = filp->private_data;
+@@ -384,6 +437,10 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+ 		return afu_ioctl_get_info(pdata, (void __user *)arg);
+ 	case DFL_FPGA_PORT_GET_REGION_INFO:
+ 		return afu_ioctl_get_region_info(pdata, (void __user *)arg);
++	case DFL_FPGA_PORT_DMA_MAP:
++		return afu_ioctl_dma_map(pdata, (void __user *)arg);
++	case DFL_FPGA_PORT_DMA_UNMAP:
++		return afu_ioctl_dma_unmap(pdata, (void __user *)arg);
+ 	default:
+ 		/*
+ 		 * Let sub-feature's ioctl function to handle the cmd
+@@ -460,6 +517,7 @@ static int afu_dev_init(struct platform_device *pdev)
+ 	mutex_lock(&pdata->lock);
+ 	dfl_fpga_pdata_set_private(pdata, afu);
+ 	afu_mmio_region_init(pdata);
++	afu_dma_region_init(pdata);
+ 	mutex_unlock(&pdata->lock);
+ 
+ 	return 0;
+@@ -473,6 +531,7 @@ static int afu_dev_destroy(struct platform_device *pdev)
+ 	mutex_lock(&pdata->lock);
+ 	afu = dfl_fpga_pdata_get_private(pdata);
+ 	afu_mmio_region_destroy(pdata);
++	afu_dma_region_destroy(pdata);
+ 	dfl_fpga_pdata_set_private(pdata, NULL);
+ 	mutex_unlock(&pdata->lock);
+ 
+diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h
+index 11ce2cf99759..0c7630ae3cda 100644
+--- a/drivers/fpga/dfl-afu.h
++++ b/drivers/fpga/dfl-afu.h
+@@ -40,12 +40,32 @@ struct dfl_afu_mmio_region {
+ 	struct list_head node;
+ };
+ 
++/**
++ * struct fpga_afu_dma_region - afu DMA region data structure
++ *
++ * @user_addr: region userspace virtual address.
++ * @length: region length.
++ * @iova: region IO virtual address.
++ * @pages: ptr to pages of this region.
++ * @node: rb tree node.
++ * @in_use: flag to indicate if this region is in_use.
++ */
++struct dfl_afu_dma_region {
++	u64 user_addr;
++	u64 length;
++	u64 iova;
++	struct page **pages;
++	struct rb_node node;
++	bool in_use;
++};
++
+ /**
+  * struct dfl_afu - afu device data structure
+  *
+  * @region_cur_offset: current region offset from start to the device fd.
+  * @num_regions: num of mmio regions.
+  * @regions: the mmio region linked list of this afu feature device.
++ * @dma_regions: root of dma regions rb tree.
+  * @num_umsgs: num of umsgs.
+  * @pdata: afu platform device's pdata.
+  */
+@@ -54,6 +74,7 @@ struct dfl_afu {
+ 	int num_regions;
+ 	u8 num_umsgs;
+ 	struct list_head regions;
++	struct rb_root dma_regions;
+ 
+ 	struct dfl_feature_platform_data *pdata;
+ };
+@@ -68,4 +89,12 @@ int afu_mmio_region_get_by_index(struct dfl_feature_platform_data *pdata,
+ int afu_mmio_region_get_by_offset(struct dfl_feature_platform_data *pdata,
+ 				  u64 offset, u64 size,
+ 				  struct dfl_afu_mmio_region *pregion);
+-#endif
++void afu_dma_region_init(struct dfl_feature_platform_data *pdata);
++void afu_dma_region_destroy(struct dfl_feature_platform_data *pdata);
++int afu_dma_map_region(struct dfl_feature_platform_data *pdata,
++		       u64 user_addr, u64 length, u64 *iova);
++int afu_dma_unmap_region(struct dfl_feature_platform_data *pdata, u64 iova);
++struct dfl_afu_dma_region *
++afu_dma_region_find(struct dfl_feature_platform_data *pdata,
++		    u64 iova, u64 size);
++#endif /* __DFL_AFU_H */
+diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
+index a3ccdfb115a5..2e324e515c41 100644
+--- a/include/uapi/linux/fpga-dfl.h
++++ b/include/uapi/linux/fpga-dfl.h
+@@ -114,6 +114,43 @@ struct dfl_fpga_port_region_info {
+ 
+ #define DFL_FPGA_PORT_GET_REGION_INFO	_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
+ 
++/**
++ * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3,
++ *						struct dfl_fpga_port_dma_map)
++ *
++ * Map the dma memory per user_addr and length which are provided by caller.
++ * Driver fills the iova in provided struct afu_port_dma_map.
++ * This interface only accepts page-size aligned user memory for dma mapping.
++ * Return: 0 on success, -errno on failure.
++ */
++struct dfl_fpga_port_dma_map {
++	/* Input */
++	__u32 argsz;		/* Structure length */
++	__u32 flags;		/* Zero for now */
++	__u64 user_addr;        /* Process virtual address */
++	__u64 length;           /* Length of mapping (bytes)*/
++	/* Output */
++	__u64 iova;             /* IO virtual address */
++};
++
++#define DFL_FPGA_PORT_DMA_MAP		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
++
++/**
++ * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4,
++ *						struct dfl_fpga_port_dma_unmap)
++ *
++ * Unmap the dma memory per iova provided by caller.
++ * Return: 0 on success, -errno on failure.
++ */
++struct dfl_fpga_port_dma_unmap {
++	/* Input */
++	__u32 argsz;		/* Structure length */
++	__u32 flags;		/* Zero for now */
++	__u64 iova;		/* IO virtual address */
++};
++
++#define DFL_FPGA_PORT_DMA_UNMAP		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
++
+ /* IOCTLs for FME file descriptor */
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1730-MAINTAINERS-add-entry-for-FPGA-DFL-drivers.patch b/patches/1730-MAINTAINERS-add-entry-for-FPGA-DFL-drivers.patch
new file mode 100644
index 00000000000000..38dd084ed387b9
--- /dev/null
+++ b/patches/1730-MAINTAINERS-add-entry-for-FPGA-DFL-drivers.patch
@@ -0,0 +1,39 @@
+From 816c9a41e2ea7817583bd96f2ba2e73a53b8e201 Mon Sep 17 00:00:00 2001
+From: Wu Hao <hao.wu@intel.com>
+Date: Sat, 30 Jun 2018 08:53:36 +0800
+Subject: [PATCH 1730/1795] MAINTAINERS: add entry for FPGA DFL drivers
+
+Add entry for FPGA Device Feature List (DFL) drivers.
+
+Signed-off-by: Wu Hao <hao.wu@intel.com>
+Acked-by: Alan Tull <atull@kernel.org>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit 5d6bd30cc9c3fca974d554bcd7bbf5f77fbe3238)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ MAINTAINERS | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 5cd120443c8f..72429b928626 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -5444,6 +5444,14 @@ F:	drivers/fpga/
+ F:	include/linux/fpga/
+ W:	http://www.rocketboards.org
+ 
++FPGA DFL DRIVERS
++M:	Wu Hao <hao.wu@intel.com>
++L:	linux-fpga@vger.kernel.org
++S:	Maintained
++F:	Documentation/fpga/dfl.txt
++F:	include/uapi/linux/fpga-dfl.h
++F:	drivers/fpga/dfl*
++
+ FPU EMULATOR
+ M:	Bill Metzenthen <billm@melbpc.org.au>
+ W:	http://floatingpoint.sourceforge.net/emulator/index.html
+-- 
+2.19.0
+
diff --git a/patches/1731-dt-bindings-fpga-add-lattice-machxo2-slave-spi-bindi.patch b/patches/1731-dt-bindings-fpga-add-lattice-machxo2-slave-spi-bindi.patch
new file mode 100644
index 00000000000000..2745f39b4e9827
--- /dev/null
+++ b/patches/1731-dt-bindings-fpga-add-lattice-machxo2-slave-spi-bindi.patch
@@ -0,0 +1,59 @@
+From b02e277468134bb73447616cb3688e6b3ccd396e Mon Sep 17 00:00:00 2001
+From: Paolo Pisati <p.pisati@gmail.com>
+Date: Mon, 16 Apr 2018 20:43:35 -0700
+Subject: [PATCH 1731/1795] dt: bindings: fpga: add lattice machxo2 slave spi
+ binding description
+
+Add dt binding documentation details for Lattice MachXO2 FPGA configuration
+over Slave SPI interface.
+
+Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d549ac081c41d1925804bf73393aca8e3978b582)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ .../bindings/fpga/lattice-machxo2-spi.txt     | 29 +++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
+
+diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
+new file mode 100644
+index 000000000000..a8c362eb160c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
+@@ -0,0 +1,29 @@
++Lattice MachXO2 Slave SPI FPGA Manager
++
++Lattice MachXO2 FPGAs support a method of loading the bitstream over
++'slave SPI' interface.
++
++See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
++
++Required properties:
++- compatible: should contain "lattice,machxo2-slave-spi"
++- reg: spi chip select of the FPGA
++
++Example for full FPGA configuration:
++
++	fpga-region0 {
++		compatible = "fpga-region";
++		fpga-mgr = <&fpga_mgr_spi>;
++		#address-cells = <0x1>;
++		#size-cells = <0x1>;
++	};
++
++	spi1: spi@2000 {
++        ...
++
++		fpga_mgr_spi: fpga-mgr@0 {
++			compatible = "lattice,machxo2-slave-spi";
++			spi-max-frequency = <8000000>;
++			reg = <0>;
++		};
++	};
+-- 
+2.19.0
+
diff --git a/patches/1732-fpga-make-xlnx_pr_decoupler_br_ops-const.patch b/patches/1732-fpga-make-xlnx_pr_decoupler_br_ops-const.patch
new file mode 100644
index 00000000000000..e78a8196082dbf
--- /dev/null
+++ b/patches/1732-fpga-make-xlnx_pr_decoupler_br_ops-const.patch
@@ -0,0 +1,35 @@
+From 7aae19e6bd2fca783ea3abdf923f7a404a44b2cd Mon Sep 17 00:00:00 2001
+From: Bhumika Goyal <bhumirks@gmail.com>
+Date: Thu, 21 Sep 2017 09:52:41 -0500
+Subject: [PATCH 1732/1795] fpga: make xlnx_pr_decoupler_br_ops const
+
+Make this const as it is only passed to a const argument of the function
+fpga_bridge_register.
+
+Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
+Acked-by: Michal Simek <michal.simek@xilinx.com>
+Acked-by: Moritz Fischer <mdf@kernel.org>
+Signed-off-by: Alan Tull <atull@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+(cherry picked from commit d8d9d936464a9b61c0e6cb1ff7c831a9cbd2f228)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/fpga/xilinx-pr-decoupler.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
+index bd059c8c851f..07ba1539e82c 100644
+--- a/drivers/fpga/xilinx-pr-decoupler.c
++++ b/drivers/fpga/xilinx-pr-decoupler.c
+@@ -79,7 +79,7 @@ static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
+ 	return !status;
+ }
+ 
+-static struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
++static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
+ 	.enable_set = xlnx_pr_decoupler_enable_set,
+ 	.enable_show = xlnx_pr_decoupler_enable_show,
+ };
+-- 
+2.19.0
+
diff --git a/patches/1733-nios2-kconfig-Remove-blank-help-text.patch b/patches/1733-nios2-kconfig-Remove-blank-help-text.patch
new file mode 100644
index 00000000000000..1b7a61fd3ace4a
--- /dev/null
+++ b/patches/1733-nios2-kconfig-Remove-blank-help-text.patch
@@ -0,0 +1,37 @@
+From c5d6be735786fd878c1a954790d8f2d30eb3b994 Mon Sep 17 00:00:00 2001
+From: Ulf Magnusson <ulfalizer@gmail.com>
+Date: Wed, 31 Jan 2018 10:34:29 +0100
+Subject: [PATCH 1733/1795] nios2: kconfig: Remove blank help text
+
+Blank help texts are probably either a typo, a Kconfig misunderstanding,
+or some kind of half-committing to adding a help text (in which case a
+TODO comment would be clearer, if the help text really can't be added
+right away).
+
+Best to remove them, IMO.
+
+Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
+Acked-by: Randy Dunlap <rdunlap@infradead.org>
+Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+(cherry picked from commit e1916031369a60c935c6957a47618d304a9df9de)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/nios2/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
+index 60fae03dac79..3d4ec88f1db1 100644
+--- a/arch/nios2/Kconfig
++++ b/arch/nios2/Kconfig
+@@ -152,7 +152,6 @@ menu "Advanced setup"
+ 
+ config ADVANCED_OPTIONS
+ 	bool "Prompt for advanced kernel configuration options"
+-	help
+ 
+ comment "Default settings for advanced configuration options are used"
+ 	depends on !ADVANCED_OPTIONS
+-- 
+2.19.0
+
diff --git a/patches/1734-nios2-dts-Remove-leading-0x-and-0s-from-bindings-not.patch b/patches/1734-nios2-dts-Remove-leading-0x-and-0s-from-bindings-not.patch
new file mode 100644
index 00000000000000..fd82a704dea099
--- /dev/null
+++ b/patches/1734-nios2-dts-Remove-leading-0x-and-0s-from-bindings-not.patch
@@ -0,0 +1,117 @@
+From f317fe1a753007b9e8d2b295d5817111539bb4a6 Mon Sep 17 00:00:00 2001
+From: Mathieu Malaterre <malat@debian.org>
+Date: Sun, 11 Feb 2018 22:59:18 +0800
+Subject: [PATCH 1734/1795] nios2: dts: Remove leading 0x and 0s from bindings
+ notation
+
+Improve the DTS files by removing all the leading "0x" and zeros to fix the
+following dtc warnings:
+
+Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
+
+and
+
+Warning (unit_address_format): Node /XXX unit name should not have leading 0s
+
+Converted using the following command:
+
+find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -E -i -e "s/@0x([0-9a-fA-F\.]+)\s?\{/@\L\1 \{/g" -e "s/@0+([0-9a-fA-F\.]+)\s?\{/@\L\1 \{/g" {} +
+
+For simplicity, two sed expressions were used to solve each warnings separately.
+
+To make the regex expression more robust a few other issues were resolved,
+namely setting unit-address to lower case, and adding a whitespace before the
+the opening curly brace:
+
+https://elinux.org/Device_Tree_Linux#Linux_conventions
+
+This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
+
+Reported-by: David Daney <ddaney@caviumnetworks.com>
+Suggested-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Mathieu Malaterre <malat@debian.org>
+Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
+(cherry picked from commit 5d13c73179983f8692adf397e65f2f57c613a917)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/nios2/boot/dts/3c120_devboard.dts | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/nios2/boot/dts/3c120_devboard.dts b/arch/nios2/boot/dts/3c120_devboard.dts
+index 36ccdf05837d..56f4b5df6d65 100644
+--- a/arch/nios2/boot/dts/3c120_devboard.dts
++++ b/arch/nios2/boot/dts/3c120_devboard.dts
+@@ -29,7 +29,7 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		cpu: cpu@0x0 {
++		cpu: cpu@0 {
+ 			device_type = "cpu";
+ 			compatible = "altr,nios2-1.0";
+ 			reg = <0x00000000>;
+@@ -69,7 +69,7 @@
+ 		compatible = "altr,avalon", "simple-bus";
+ 		bus-frequency = <125000000>;
+ 
+-		pb_cpu_to_io: bridge@0x8000000 {
++		pb_cpu_to_io: bridge@8000000 {
+ 			compatible = "simple-bus";
+ 			reg = <0x08000000 0x00800000>;
+ 			#address-cells = <1>;
+@@ -83,7 +83,7 @@
+ 				<0x00008000 0x08008000 0x00000020>,
+ 				<0x00400000 0x08400000 0x00000020>;
+ 
+-			timer_1ms: timer@0x400000 {
++			timer_1ms: timer@400000 {
+ 				compatible = "altr,timer-1.0";
+ 				reg = <0x00400000 0x00000020>;
+ 				interrupt-parent = <&cpu>;
+@@ -91,7 +91,7 @@
+ 				clock-frequency = <125000000>;
+ 			};
+ 
+-			timer_0: timer@0x8000 {
++			timer_0: timer@8000 {
+ 				compatible = "altr,timer-1.0";
+ 				reg = < 0x00008000 0x00000020 >;
+ 				interrupt-parent = < &cpu >;
+@@ -99,14 +99,14 @@
+ 				clock-frequency = < 125000000 >;
+ 			};
+ 
+-			jtag_uart: serial@0x4d50 {
++			jtag_uart: serial@4d50 {
+ 				compatible = "altr,juart-1.0";
+ 				reg = <0x00004d50 0x00000008>;
+ 				interrupt-parent = <&cpu>;
+ 				interrupts = <1>;
+ 			};
+ 
+-			tse_mac: ethernet@0x4000 {
++			tse_mac: ethernet@4000 {
+ 				compatible = "altr,tse-1.0";
+ 				reg = <0x00004000 0x00000400>,
+ 					<0x00004400 0x00000040>,
+@@ -133,7 +133,7 @@
+ 				};
+ 			};
+ 
+-			uart: serial@0x4c80 {
++			uart: serial@4c80 {
+ 				compatible = "altr,uart-1.0";
+ 				reg = <0x00004c80 0x00000020>;
+ 				interrupt-parent = <&cpu>;
+@@ -143,7 +143,7 @@
+ 			};
+ 		};
+ 
+-		cfi_flash_64m: flash@0x0 {
++		cfi_flash_64m: flash@0 {
+ 			compatible = "cfi-flash";
+ 			reg = <0x00000000 0x04000000>;
+ 			bank-width = <2>;
+-- 
+2.19.0
+
diff --git a/patches/1735-nios2-defconfig-Cleanup-from-old-Kconfig-options.patch b/patches/1735-nios2-defconfig-Cleanup-from-old-Kconfig-options.patch
new file mode 100644
index 00000000000000..2422df60d7d7b2
--- /dev/null
+++ b/patches/1735-nios2-defconfig-Cleanup-from-old-Kconfig-options.patch
@@ -0,0 +1,44 @@
+From 33dcfde57024a478728069cf4b0f51d51e422306 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Sun, 11 Feb 2018 23:01:17 +0800
+Subject: [PATCH 1735/1795] nios2: defconfig: Cleanup from old Kconfig options
+
+Remove old, dead Kconfig option INET_LRO. It is gone since
+commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
+
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
+(cherry picked from commit e0691ebb33c12084ef11b6b59228c004e19f59c8)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/nios2/configs/10m50_defconfig | 1 -
+ arch/nios2/configs/3c120_defconfig | 1 -
+ 2 files changed, 2 deletions(-)
+
+diff --git a/arch/nios2/configs/10m50_defconfig b/arch/nios2/configs/10m50_defconfig
+index 8b2a30b3b34f..c601c8ff1ae6 100644
+--- a/arch/nios2/configs/10m50_defconfig
++++ b/arch/nios2/configs/10m50_defconfig
+@@ -33,7 +33,6 @@ CONFIG_IP_PNP_RARP=y
+ # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+ # CONFIG_INET_XFRM_MODE_TUNNEL is not set
+ # CONFIG_INET_XFRM_MODE_BEET is not set
+-# CONFIG_INET_LRO is not set
+ # CONFIG_IPV6 is not set
+ # CONFIG_WIRELESS is not set
+ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+diff --git a/arch/nios2/configs/3c120_defconfig b/arch/nios2/configs/3c120_defconfig
+index 9451940678a0..fce33588d55c 100644
+--- a/arch/nios2/configs/3c120_defconfig
++++ b/arch/nios2/configs/3c120_defconfig
+@@ -35,7 +35,6 @@ CONFIG_IP_PNP_RARP=y
+ # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+ # CONFIG_INET_XFRM_MODE_TUNNEL is not set
+ # CONFIG_INET_XFRM_MODE_BEET is not set
+-# CONFIG_INET_LRO is not set
+ # CONFIG_IPV6 is not set
+ # CONFIG_WIRELESS is not set
+ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+-- 
+2.19.0
+
diff --git a/patches/1736-nios2-add-ioremap_nocache-declaration-before-include.patch b/patches/1736-nios2-add-ioremap_nocache-declaration-before-include.patch
new file mode 100644
index 00000000000000..5d41e6fcd5dca3
--- /dev/null
+++ b/patches/1736-nios2-add-ioremap_nocache-declaration-before-include.patch
@@ -0,0 +1,35 @@
+From 7541e40463fe827669fee20452c543494b083aab Mon Sep 17 00:00:00 2001
+From: Greentime Hu <greentime@andestech.com>
+Date: Thu, 1 Mar 2018 10:55:54 +0800
+Subject: [PATCH 1736/1795] nios2: add ioremap_nocache declaration before
+ include asm-generic/io.h.
+
+A commit for the nds32 architecture bootstrap("asm-generic/io.h:
+move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
+CONFIG_MMU") will move the ioremap_nocache out of the CONFIG_MMU ifdef.
+This means that in order to suppress re-definition errors we need to
+setup #define's before importing asm-generic/io.h.
+
+Signed-off-by: Greentime Hu <greentime@andestech.com>
+Reviewed-by: Tobias Klauser <tklauser@distanz.ch>
+(cherry picked from commit c601a89115cbc3ccd51468295d28cfae47cc5410)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/nios2/include/asm/io.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
+index ce072ba0f8dd..9010243077ab 100644
+--- a/arch/nios2/include/asm/io.h
++++ b/arch/nios2/include/asm/io.h
+@@ -45,6 +45,7 @@ static inline void iounmap(void __iomem *addr)
+ 	__iounmap(addr);
+ }
+ 
++#define ioremap_nocache ioremap_nocache
+ #define ioremap_wc ioremap_nocache
+ #define ioremap_wt ioremap_nocache
+ 
+-- 
+2.19.0
+
diff --git a/patches/1737-nios2-Use-read_persistent_clock64-instead-of-read_pe.patch b/patches/1737-nios2-Use-read_persistent_clock64-instead-of-read_pe.patch
new file mode 100644
index 00000000000000..3d53c5ff061056
--- /dev/null
+++ b/patches/1737-nios2-Use-read_persistent_clock64-instead-of-read_pe.patch
@@ -0,0 +1,37 @@
+From 1163bebf9739d51e72175f5ba13d9bc6407c6d29 Mon Sep 17 00:00:00 2001
+From: Baolin Wang <baolin.wang@linaro.org>
+Date: Tue, 3 Apr 2018 00:36:02 +0800
+Subject: [PATCH 1737/1795] nios2: Use read_persistent_clock64() instead of
+ read_persistent_clock()
+
+Since struct timespec is not y2038 safe on 32bit machines, this patch
+converts read_persistent_clock() to read_persistent_clock64() using
+struct timespec64, as well as converting mktime() to mktime64().
+
+Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
+Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
+(cherry picked from commit 3d9644ef9a0f6c3ca0c1bd2aea1d82e7ea0a7f24)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ arch/nios2/kernel/time.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/nios2/kernel/time.c b/arch/nios2/kernel/time.c
+index 20e86209ef2e..ab88b6dd4679 100644
+--- a/arch/nios2/kernel/time.c
++++ b/arch/nios2/kernel/time.c
+@@ -336,9 +336,9 @@ static int __init nios2_time_init(struct device_node *timer)
+ 	return ret;
+ }
+ 
+-void read_persistent_clock(struct timespec *ts)
++void read_persistent_clock64(struct timespec64 *ts)
+ {
+-	ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0);
++	ts->tv_sec = mktime64(2007, 1, 1, 0, 0, 0);
+ 	ts->tv_nsec = 0;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1738-usb-dwc2-add-optional-usb-ecc-reset-bit.patch b/patches/1738-usb-dwc2-add-optional-usb-ecc-reset-bit.patch
new file mode 100644
index 00000000000000..5a30892990ae27
--- /dev/null
+++ b/patches/1738-usb-dwc2-add-optional-usb-ecc-reset-bit.patch
@@ -0,0 +1,61 @@
+From 0ea91b8916db050fb4d806630d4e429d3fe737fb Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 1 Nov 2017 10:34:53 -0500
+Subject: [PATCH 1738/1795] usb: dwc2: add optional usb ecc reset bit
+
+The dwc2 USB controller in Stratix10 has an additional ECC reset bit that
+needs to get de-asserted in order for the controller to work properly.
+
+Acked-by: John Youn <johnyoun@synopsys.com>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+(cherry picked from commit f2830ad455ec0fdc386baeb9d654f7095bf849da)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/usb/dwc2/core.h     |  1 +
+ drivers/usb/dwc2/platform.c | 10 ++++++++++
+ 2 files changed, 11 insertions(+)
+
+diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
+index 70cea7441650..f5166573a0c1 100644
+--- a/drivers/usb/dwc2/core.h
++++ b/drivers/usb/dwc2/core.h
+@@ -922,6 +922,7 @@ struct dwc2_hsotg {
+ 	int     irq;
+ 	struct clk *clk;
+ 	struct reset_control *reset;
++	struct reset_control *reset_ecc;
+ 
+ 	unsigned int queuing_high_bandwidth:1;
+ 	unsigned int srp_success:1;
+diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
+index 3e26550d13dd..4703478f702f 100644
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -221,6 +221,15 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ 
+ 	reset_control_deassert(hsotg->reset);
+ 
++	hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
++	if (IS_ERR(hsotg->reset_ecc)) {
++		ret = PTR_ERR(hsotg->reset_ecc);
++		dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
++		return ret;
++	}
++
++	reset_control_deassert(hsotg->reset_ecc);
++
+ 	/* Set default UTMI width */
+ 	hsotg->phyif = GUSBCFG_PHYIF16;
+ 
+@@ -319,6 +328,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
+ 		dwc2_lowlevel_hw_disable(hsotg);
+ 
+ 	reset_control_assert(hsotg->reset);
++	reset_control_assert(hsotg->reset_ecc);
+ 
+ 	return 0;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1739-reset-socfpga-build-the-reset-socfpga-for-Stratix10-.patch b/patches/1739-reset-socfpga-build-the-reset-socfpga-for-Stratix10-.patch
new file mode 100644
index 00000000000000..0da19a16a62982
--- /dev/null
+++ b/patches/1739-reset-socfpga-build-the-reset-socfpga-for-Stratix10-.patch
@@ -0,0 +1,32 @@
+From c1da1c5c28a4381ecd7f1b8d972a14ab1a1f8134 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Wed, 20 Sep 2017 10:25:41 -0500
+Subject: [PATCH 1739/1795] reset: socfpga: build the reset-socfpga for
+ Stratix10 SOC
+
+Enable the reset driver to get built for the Stratix10 platform.
+
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+(cherry picked from commit db21f9cfd5adf7544f64573c1ea4c4f3876d898e)
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/reset/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
+index e2baecbb9dd3..1c88af294724 100644
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -77,7 +77,7 @@ config RESET_PISTACHIO
+ 
+ config RESET_SOCFPGA
+ 	bool "SoCFPGA Reset Driver" if COMPILE_TEST
+-	default ARCH_SOCFPGA
++	default ARCH_SOCFPGA || ARCH_STRATIX10
+ 	help
+ 	  This enables the reset controller driver for Altera SoCFPGAs.
+ 
+-- 
+2.19.0
+
diff --git a/patches/1740-i2c-rcar-refactor-private-flags.patch b/patches/1740-i2c-rcar-refactor-private-flags.patch
new file mode 100644
index 00000000000000..99b1c4dde462cd
--- /dev/null
+++ b/patches/1740-i2c-rcar-refactor-private-flags.patch
@@ -0,0 +1,46 @@
+From 364d0bff29770418bf8d2d018f999b09ebe422b7 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 8 Aug 2018 09:59:27 +0200
+Subject: [PATCH 1740/1795] i2c: rcar: refactor private flags
+
+Use BIT macro to avoid shift-31-problem, indent a little more and use
+GENMASK to make it easier to add new flags.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit b07531acd55180efc95e334605f04ca1eaf4e003)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index e9fa7cdb83f0..16bdeb8713db 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -19,6 +19,7 @@
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  */
++#include <linux/bitops.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/dmaengine.h>
+@@ -112,9 +113,9 @@
+ #define ID_ARBLOST	(1 << 3)
+ #define ID_NACK		(1 << 4)
+ /* persistent flags */
+-#define ID_P_NO_RXDMA	(1 << 30) /* HW forbids RXDMA sometimes */
+-#define ID_P_PM_BLOCKED	(1 << 31)
+-#define ID_P_MASK	(ID_P_PM_BLOCKED | ID_P_NO_RXDMA)
++#define ID_P_NO_RXDMA		BIT(30) /* HW forbids RXDMA sometimes */
++#define ID_P_PM_BLOCKED		BIT(31)
++#define ID_P_MASK		GENMASK(31, 30)
+ 
+ enum rcar_i2c_type {
+ 	I2C_RCAR_GEN1,
+-- 
+2.19.0
+
diff --git a/patches/1741-i2c-rcar-implement-STOP-and-REP_START-according-to-d.patch b/patches/1741-i2c-rcar-implement-STOP-and-REP_START-according-to-d.patch
new file mode 100644
index 00000000000000..e55e4afa1bd5fb
--- /dev/null
+++ b/patches/1741-i2c-rcar-implement-STOP-and-REP_START-according-to-d.patch
@@ -0,0 +1,99 @@
+From 613e3ef06fef20762a140eda39ceb57cc0e7b990 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Date: Wed, 8 Aug 2018 09:59:28 +0200
+Subject: [PATCH 1741/1795] i2c: rcar: implement STOP and REP_START according
+ to docs
+
+When doing a REP_START after a read message, the driver used to trigger
+a STOP first which would then be overwritten by REP_START. This was the
+only stable method found when doing the last refactoring. However, this
+was not in accordance with the documentation.
+
+After research from our BSP team and myself, we now can implement a
+version which works and is according to the documentation. The new
+approach ensures the ICMCR register is only changed when really needed.
+
+Tested on a R-Car Gen2 (H2) and Gen3 with DMA (M3N).
+
+Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+(cherry picked from commit 19358d4488db7e6a04e940730cc75909d7d1e0d8)
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ drivers/i2c/busses/i2c-rcar.c | 34 ++++++++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 16bdeb8713db..32da864cbc0f 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -113,9 +113,10 @@
+ #define ID_ARBLOST	(1 << 3)
+ #define ID_NACK		(1 << 4)
+ /* persistent flags */
++#define ID_P_REP_AFTER_RD	BIT(29)
+ #define ID_P_NO_RXDMA		BIT(30) /* HW forbids RXDMA sometimes */
+ #define ID_P_PM_BLOCKED		BIT(31)
+-#define ID_P_MASK		GENMASK(31, 30)
++#define ID_P_MASK		GENMASK(31, 29)
+ 
+ enum rcar_i2c_type {
+ 	I2C_RCAR_GEN1,
+@@ -345,7 +346,10 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
+ 		rcar_i2c_write(priv, ICMSR, 0);
+ 		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
+ 	} else {
+-		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
++		if (priv->flags & ID_P_REP_AFTER_RD)
++			priv->flags &= ~ID_P_REP_AFTER_RD;
++		else
++			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
+ 		rcar_i2c_write(priv, ICMSR, 0);
+ 	}
+ 	rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
+@@ -550,15 +554,15 @@ static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
+ 		priv->pos++;
+ 	}
+ 
+-	/*
+-	 * If next received data is the _LAST_, go to STOP phase. Might be
+-	 * overwritten by REP START when setting up a new msg. Not elegant
+-	 * but the only stable sequence for REP START I have found so far.
+-	 * If you want to change this code, make sure sending one transfer with
+-	 * four messages (WR-RD-WR-RD) works!
+-	 */
+-	if (priv->pos + 1 >= msg->len)
+-		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
++	/* If next received data is the _LAST_, go to new phase. */
++	if (priv->pos + 1 == msg->len) {
++		if (priv->flags & ID_LAST_MSG) {
++			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
++		} else {
++			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
++			priv->flags |= ID_P_REP_AFTER_RD;
++		}
++	}
+ 
+ 	if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
+ 		rcar_i2c_next_msg(priv);
+@@ -626,9 +630,11 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
+ 	struct rcar_i2c_priv *priv = ptr;
+ 	u32 msr, val;
+ 
+-	/* Clear START or STOP as soon as we can */
+-	val = rcar_i2c_read(priv, ICMCR);
+-	rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
++	/* Clear START or STOP immediately, except for REPSTART after read */
++	if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
++		val = rcar_i2c_read(priv, ICMCR);
++		rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
++	}
+ 
+ 	msr = rcar_i2c_read(priv, ICMSR);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1742-tracing-Remove-redundant-unread-variable-ret.patch b/patches/1742-tracing-Remove-redundant-unread-variable-ret.patch
new file mode 100644
index 00000000000000..f9eca495c0857a
--- /dev/null
+++ b/patches/1742-tracing-Remove-redundant-unread-variable-ret.patch
@@ -0,0 +1,49 @@
+From 85f656863ccdf9f1598e5c4cb110a4e951782bf3 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Wed, 23 Aug 2017 12:23:09 +0100
+Subject: [PATCH 1742/1795] tracing: Remove redundant unread variable ret
+
+Integer ret is being assigned but never used and hence it is
+redundant. Remove it, fixes clang warning:
+
+trace_events_hist.c:1077:3: warning: Value stored to 'ret' is never read
+
+Link: http://lkml.kernel.org/r/20170823112309.19383-1-colin.king@canonical.com
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 6e7a2398114a2597a0995f96f44d908741ae5035)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 7eb975a2d0e1..121d56850f24 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -1062,7 +1062,7 @@ static void hist_trigger_show(struct seq_file *m,
+ 			      struct event_trigger_data *data, int n)
+ {
+ 	struct hist_trigger_data *hist_data;
+-	int n_entries, ret = 0;
++	int n_entries;
+ 
+ 	if (n > 0)
+ 		seq_puts(m, "\n\n");
+@@ -1073,10 +1073,8 @@ static void hist_trigger_show(struct seq_file *m,
+ 
+ 	hist_data = data->private_data;
+ 	n_entries = print_entries(m, hist_data);
+-	if (n_entries < 0) {
+-		ret = n_entries;
++	if (n_entries < 0)
+ 		n_entries = 0;
+-	}
+ 
+ 	seq_printf(m, "\nTotals:\n    Hits: %llu\n    Entries: %u\n    Dropped: %llu\n",
+ 		   (u64)atomic64_read(&hist_data->map->hits),
+-- 
+2.19.0
+
diff --git a/patches/1743-tracing-Clean-up-hist_field_flags-enum.patch b/patches/1743-tracing-Clean-up-hist_field_flags-enum.patch
new file mode 100644
index 00000000000000..517dc37386e17e
--- /dev/null
+++ b/patches/1743-tracing-Clean-up-hist_field_flags-enum.patch
@@ -0,0 +1,54 @@
+From d0f8fcaa0dd277727687ef60c78546ddef6f7744 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Fri, 22 Sep 2017 14:58:21 -0500
+Subject: [PATCH 1743/1795] tracing: Clean up hist_field_flags enum
+
+As we add more flags, specifying explicit integers for the flag values
+becomes more unwieldy and error-prone - switch them over to left-shift
+values.
+
+Link: http://lkml.kernel.org/r/e644e4fb7665aec015f4a2d84a2f990d3dd5b8a1.1506105045.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 0d7a8325bf3326c92da2d21b4496a9ddde896d4f)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 121d56850f24..0c7ec3048624 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -110,16 +110,16 @@ DEFINE_HIST_FIELD_FN(u8);
+ #define HIST_KEY_SIZE_MAX	(MAX_FILTER_STR_VAL + HIST_STACKTRACE_SIZE)
+ 
+ enum hist_field_flags {
+-	HIST_FIELD_FL_HITCOUNT		= 1,
+-	HIST_FIELD_FL_KEY		= 2,
+-	HIST_FIELD_FL_STRING		= 4,
+-	HIST_FIELD_FL_HEX		= 8,
+-	HIST_FIELD_FL_SYM		= 16,
+-	HIST_FIELD_FL_SYM_OFFSET	= 32,
+-	HIST_FIELD_FL_EXECNAME		= 64,
+-	HIST_FIELD_FL_SYSCALL		= 128,
+-	HIST_FIELD_FL_STACKTRACE	= 256,
+-	HIST_FIELD_FL_LOG2		= 512,
++	HIST_FIELD_FL_HITCOUNT		= 1 << 0,
++	HIST_FIELD_FL_KEY		= 1 << 1,
++	HIST_FIELD_FL_STRING		= 1 << 2,
++	HIST_FIELD_FL_HEX		= 1 << 3,
++	HIST_FIELD_FL_SYM		= 1 << 4,
++	HIST_FIELD_FL_SYM_OFFSET	= 1 << 5,
++	HIST_FIELD_FL_EXECNAME		= 1 << 6,
++	HIST_FIELD_FL_SYSCALL		= 1 << 7,
++	HIST_FIELD_FL_STACKTRACE	= 1 << 8,
++	HIST_FIELD_FL_LOG2		= 1 << 9,
+ };
+ 
+ struct hist_trigger_attrs {
+-- 
+2.19.0
+
diff --git a/patches/1744-tracing-Add-hist_field_name-accessor.patch b/patches/1744-tracing-Add-hist_field_name-accessor.patch
new file mode 100644
index 00000000000000..68c0d1bc2f8ba0
--- /dev/null
+++ b/patches/1744-tracing-Add-hist_field_name-accessor.patch
@@ -0,0 +1,185 @@
+From 7fe87ff3820776c03a392a4f37857ba8503f9d8b Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Fri, 22 Sep 2017 14:58:22 -0500
+Subject: [PATCH 1744/1795] tracing: Add hist_field_name() accessor
+
+In preparation for hist_fields that won't be strictly based on
+trace_event_fields, add a new hist_field_name() accessor to allow that
+flexibility and update associated users.
+
+Link: http://lkml.kernel.org/r/5b5a2d36dde067cbbe2434b10f06daac27b7dbd5.1506105045.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 85013256cf01629f72a327674c5d007b4a4b40da)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 67 +++++++++++++++++++++-----------
+ 1 file changed, 45 insertions(+), 22 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 0c7ec3048624..34edf5fd85fd 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -146,6 +146,23 @@ struct hist_trigger_data {
+ 	struct tracing_map		*map;
+ };
+ 
++static const char *hist_field_name(struct hist_field *field,
++				   unsigned int level)
++{
++	const char *field_name = "";
++
++	if (level > 1)
++		return field_name;
++
++	if (field->field)
++		field_name = field->field->name;
++
++	if (field_name == NULL)
++		field_name = "";
++
++	return field_name;
++}
++
+ static hist_field_fn_t select_value_fn(int field_size, int field_is_signed)
+ {
+ 	hist_field_fn_t fn = NULL;
+@@ -653,7 +670,6 @@ static int is_descending(const char *str)
+ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ {
+ 	char *fields_str = hist_data->attrs->sort_key_str;
+-	struct ftrace_event_field *field = NULL;
+ 	struct tracing_map_sort_key *sort_key;
+ 	int descending, ret = 0;
+ 	unsigned int i, j;
+@@ -670,7 +686,9 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 	}
+ 
+ 	for (i = 0; i < TRACING_MAP_SORT_KEYS_MAX; i++) {
++		struct hist_field *hist_field;
+ 		char *field_str, *field_name;
++		const char *test_name;
+ 
+ 		sort_key = &hist_data->sort_keys[i];
+ 
+@@ -703,8 +721,10 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 		}
+ 
+ 		for (j = 1; j < hist_data->n_fields; j++) {
+-			field = hist_data->fields[j]->field;
+-			if (field && (strcmp(field_name, field->name) == 0)) {
++			hist_field = hist_data->fields[j];
++			test_name = hist_field_name(hist_field, 0);
++
++			if (strcmp(field_name, test_name) == 0) {
+ 				sort_key->field_idx = j;
+ 				descending = is_descending(field_str);
+ 				if (descending < 0) {
+@@ -952,6 +972,7 @@ hist_trigger_entry_print(struct seq_file *m,
+ 	struct hist_field *key_field;
+ 	char str[KSYM_SYMBOL_LEN];
+ 	bool multiline = false;
++	const char *field_name;
+ 	unsigned int i;
+ 	u64 uval;
+ 
+@@ -963,26 +984,27 @@ hist_trigger_entry_print(struct seq_file *m,
+ 		if (i > hist_data->n_vals)
+ 			seq_puts(m, ", ");
+ 
++		field_name = hist_field_name(key_field, 0);
++
+ 		if (key_field->flags & HIST_FIELD_FL_HEX) {
+ 			uval = *(u64 *)(key + key_field->offset);
+-			seq_printf(m, "%s: %llx",
+-				   key_field->field->name, uval);
++			seq_printf(m, "%s: %llx", field_name, uval);
+ 		} else if (key_field->flags & HIST_FIELD_FL_SYM) {
+ 			uval = *(u64 *)(key + key_field->offset);
+ 			sprint_symbol_no_offset(str, uval);
+-			seq_printf(m, "%s: [%llx] %-45s",
+-				   key_field->field->name, uval, str);
++			seq_printf(m, "%s: [%llx] %-45s", field_name,
++				   uval, str);
+ 		} else if (key_field->flags & HIST_FIELD_FL_SYM_OFFSET) {
+ 			uval = *(u64 *)(key + key_field->offset);
+ 			sprint_symbol(str, uval);
+-			seq_printf(m, "%s: [%llx] %-55s",
+-				   key_field->field->name, uval, str);
++			seq_printf(m, "%s: [%llx] %-55s", field_name,
++				   uval, str);
+ 		} else if (key_field->flags & HIST_FIELD_FL_EXECNAME) {
+ 			char *comm = elt->private_data;
+ 
+ 			uval = *(u64 *)(key + key_field->offset);
+-			seq_printf(m, "%s: %-16s[%10llu]",
+-				   key_field->field->name, comm, uval);
++			seq_printf(m, "%s: %-16s[%10llu]", field_name,
++				   comm, uval);
+ 		} else if (key_field->flags & HIST_FIELD_FL_SYSCALL) {
+ 			const char *syscall_name;
+ 
+@@ -991,8 +1013,8 @@ hist_trigger_entry_print(struct seq_file *m,
+ 			if (!syscall_name)
+ 				syscall_name = "unknown_syscall";
+ 
+-			seq_printf(m, "%s: %-30s[%3llu]",
+-				   key_field->field->name, syscall_name, uval);
++			seq_printf(m, "%s: %-30s[%3llu]", field_name,
++				   syscall_name, uval);
+ 		} else if (key_field->flags & HIST_FIELD_FL_STACKTRACE) {
+ 			seq_puts(m, "stacktrace:\n");
+ 			hist_trigger_stacktrace_print(m,
+@@ -1000,15 +1022,14 @@ hist_trigger_entry_print(struct seq_file *m,
+ 						      HIST_STACKTRACE_DEPTH);
+ 			multiline = true;
+ 		} else if (key_field->flags & HIST_FIELD_FL_LOG2) {
+-			seq_printf(m, "%s: ~ 2^%-2llu", key_field->field->name,
++			seq_printf(m, "%s: ~ 2^%-2llu", field_name,
+ 				   *(u64 *)(key + key_field->offset));
+ 		} else if (key_field->flags & HIST_FIELD_FL_STRING) {
+-			seq_printf(m, "%s: %-50s", key_field->field->name,
++			seq_printf(m, "%s: %-50s", field_name,
+ 				   (char *)(key + key_field->offset));
+ 		} else {
+ 			uval = *(u64 *)(key + key_field->offset);
+-			seq_printf(m, "%s: %10llu", key_field->field->name,
+-				   uval);
++			seq_printf(m, "%s: %10llu", field_name, uval);
+ 		}
+ 	}
+ 
+@@ -1021,13 +1042,13 @@ hist_trigger_entry_print(struct seq_file *m,
+ 		   tracing_map_read_sum(elt, HITCOUNT_IDX));
+ 
+ 	for (i = 1; i < hist_data->n_vals; i++) {
++		field_name = hist_field_name(hist_data->fields[i], 0);
++
+ 		if (hist_data->fields[i]->flags & HIST_FIELD_FL_HEX) {
+-			seq_printf(m, "  %s: %10llx",
+-				   hist_data->fields[i]->field->name,
++			seq_printf(m, "  %s: %10llx", field_name,
+ 				   tracing_map_read_sum(elt, i));
+ 		} else {
+-			seq_printf(m, "  %s: %10llu",
+-				   hist_data->fields[i]->field->name,
++			seq_printf(m, "  %s: %10llu", field_name,
+ 				   tracing_map_read_sum(elt, i));
+ 		}
+ 	}
+@@ -1140,7 +1161,9 @@ static const char *get_hist_field_flags(struct hist_field *hist_field)
+ 
+ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ {
+-	seq_printf(m, "%s", hist_field->field->name);
++	const char *field_name = hist_field_name(hist_field, 0);
++
++	seq_printf(m, "%s", field_name);
+ 	if (hist_field->flags) {
+ 		const char *flags_str = get_hist_field_flags(hist_field);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1745-tracing-Reimplement-log2.patch b/patches/1745-tracing-Reimplement-log2.patch
new file mode 100644
index 00000000000000..1f28fbf254ecab
--- /dev/null
+++ b/patches/1745-tracing-Reimplement-log2.patch
@@ -0,0 +1,125 @@
+From 82cc9ce0e494a51282e849a2898c5611a8a6221f Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Fri, 22 Sep 2017 14:58:23 -0500
+Subject: [PATCH 1745/1795] tracing: Reimplement log2
+
+log2 as currently implemented applies only to u64 trace_event_field
+derived fields, and assumes that anything it's applied to is a u64
+field.
+
+To prepare for synthetic fields like latencies, log2 should be
+applicable to those as well, so take the opportunity now to fix the
+current problems as well as expand to more general uses.
+
+log2 should be thought of as a chaining function rather than a field
+type.  To enable this as well as possible future function
+implementations, add a hist_field operand array into the hist_field
+definition for this purpose, and make use of it to implement the log2
+'function'.
+
+Link: http://lkml.kernel.org/r/b47f93fc0b87b36eccf716b0c018f3a71e1f1111.1506105045.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 5819eaddf35b24d628ddfa4fbb5f8d4026e44b96)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 31 +++++++++++++++++++++++++++----
+ 1 file changed, 27 insertions(+), 4 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 34edf5fd85fd..1e1558c99d56 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -28,12 +28,16 @@ struct hist_field;
+ 
+ typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event);
+ 
++#define HIST_FIELD_OPERANDS_MAX	2
++
+ struct hist_field {
+ 	struct ftrace_event_field	*field;
+ 	unsigned long			flags;
+ 	hist_field_fn_t			fn;
+ 	unsigned int			size;
+ 	unsigned int			offset;
++	unsigned int                    is_signed;
++	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
+ };
+ 
+ static u64 hist_field_none(struct hist_field *field, void *event)
+@@ -71,7 +75,9 @@ static u64 hist_field_pstring(struct hist_field *hist_field, void *event)
+ 
+ static u64 hist_field_log2(struct hist_field *hist_field, void *event)
+ {
+-	u64 val = *(u64 *)(event + hist_field->field->offset);
++	struct hist_field *operand = hist_field->operands[0];
++
++	u64 val = operand->fn(operand, event);
+ 
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+@@ -156,6 +162,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 
+ 	if (field->field)
+ 		field_name = field->field->name;
++	else if (field->flags & HIST_FIELD_FL_LOG2)
++		field_name = hist_field_name(field->operands[0], ++level);
+ 
+ 	if (field_name == NULL)
+ 		field_name = "";
+@@ -357,8 +365,20 @@ static const struct tracing_map_ops hist_trigger_elt_comm_ops = {
+ 	.elt_init	= hist_trigger_elt_comm_init,
+ };
+ 
+-static void destroy_hist_field(struct hist_field *hist_field)
++static void destroy_hist_field(struct hist_field *hist_field,
++			       unsigned int level)
+ {
++	unsigned int i;
++
++	if (level > 2)
++		return;
++
++	if (!hist_field)
++		return;
++
++	for (i = 0; i < HIST_FIELD_OPERANDS_MAX; i++)
++		destroy_hist_field(hist_field->operands[i], level + 1);
++
+ 	kfree(hist_field);
+ }
+ 
+@@ -385,7 +405,10 @@ static struct hist_field *create_hist_field(struct ftrace_event_field *field,
+ 	}
+ 
+ 	if (flags & HIST_FIELD_FL_LOG2) {
++		unsigned long fl = flags & ~HIST_FIELD_FL_LOG2;
+ 		hist_field->fn = hist_field_log2;
++		hist_field->operands[0] = create_hist_field(field, fl);
++		hist_field->size = hist_field->operands[0]->size;
+ 		goto out;
+ 	}
+ 
+@@ -405,7 +428,7 @@ static struct hist_field *create_hist_field(struct ftrace_event_field *field,
+ 		hist_field->fn = select_value_fn(field->size,
+ 						 field->is_signed);
+ 		if (!hist_field->fn) {
+-			destroy_hist_field(hist_field);
++			destroy_hist_field(hist_field, 0);
+ 			return NULL;
+ 		}
+ 	}
+@@ -422,7 +445,7 @@ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ 
+ 	for (i = 0; i < TRACING_MAP_FIELDS_MAX; i++) {
+ 		if (hist_data->fields[i]) {
+-			destroy_hist_field(hist_data->fields[i]);
++			destroy_hist_field(hist_data->fields[i], 0);
+ 			hist_data->fields[i] = NULL;
+ 		}
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1746-tracing-Remove-code-which-merges-duplicates.patch b/patches/1746-tracing-Remove-code-which-merges-duplicates.patch
new file mode 100644
index 00000000000000..4c04a051265943
--- /dev/null
+++ b/patches/1746-tracing-Remove-code-which-merges-duplicates.patch
@@ -0,0 +1,203 @@
+From 06a7fa753bc7766bf10e071743189ed7bbd37426 Mon Sep 17 00:00:00 2001
+From: Vedang Patel <vedang.patel@intel.com>
+Date: Mon, 15 Jan 2018 20:51:38 -0600
+Subject: [PATCH 1746/1795] tracing: Remove code which merges duplicates
+
+We now have the logic to detect and remove duplicates in the
+tracing_map hash table. The code which merges duplicates in the
+histogram is redundant now. So, modify this code just to detect
+duplicates. The duplication detection code is still kept to ensure
+that any rare race condition which might cause duplicates does not go
+unnoticed.
+
+Link: http://lkml.kernel.org/r/55215cf59e2674391bdaf772fdafc4c393352b03.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Vedang Patel <vedang.patel@intel.com>
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit c193707dde77ace92a649cd59a17e105e2fbeaef)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 11 -----
+ kernel/trace/tracing_map.c       | 83 +++-----------------------------
+ kernel/trace/tracing_map.h       |  7 ---
+ 3 files changed, 6 insertions(+), 95 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 1e1558c99d56..712260e72be5 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -340,16 +340,6 @@ static int hist_trigger_elt_comm_alloc(struct tracing_map_elt *elt)
+ 	return 0;
+ }
+ 
+-static void hist_trigger_elt_comm_copy(struct tracing_map_elt *to,
+-				       struct tracing_map_elt *from)
+-{
+-	char *comm_from = from->private_data;
+-	char *comm_to = to->private_data;
+-
+-	if (comm_from)
+-		memcpy(comm_to, comm_from, TASK_COMM_LEN + 1);
+-}
+-
+ static void hist_trigger_elt_comm_init(struct tracing_map_elt *elt)
+ {
+ 	char *comm = elt->private_data;
+@@ -360,7 +350,6 @@ static void hist_trigger_elt_comm_init(struct tracing_map_elt *elt)
+ 
+ static const struct tracing_map_ops hist_trigger_elt_comm_ops = {
+ 	.elt_alloc	= hist_trigger_elt_comm_alloc,
+-	.elt_copy	= hist_trigger_elt_comm_copy,
+ 	.elt_free	= hist_trigger_elt_comm_free,
+ 	.elt_init	= hist_trigger_elt_comm_init,
+ };
+diff --git a/kernel/trace/tracing_map.c b/kernel/trace/tracing_map.c
+index 305039b122fa..8d9feee50dab 100644
+--- a/kernel/trace/tracing_map.c
++++ b/kernel/trace/tracing_map.c
+@@ -815,67 +815,15 @@ create_sort_entry(void *key, struct tracing_map_elt *elt)
+ 	return sort_entry;
+ }
+ 
+-static struct tracing_map_elt *copy_elt(struct tracing_map_elt *elt)
+-{
+-	struct tracing_map_elt *dup_elt;
+-	unsigned int i;
+-
+-	dup_elt = tracing_map_elt_alloc(elt->map);
+-	if (IS_ERR(dup_elt))
+-		return NULL;
+-
+-	if (elt->map->ops && elt->map->ops->elt_copy)
+-		elt->map->ops->elt_copy(dup_elt, elt);
+-
+-	dup_elt->private_data = elt->private_data;
+-	memcpy(dup_elt->key, elt->key, elt->map->key_size);
+-
+-	for (i = 0; i < elt->map->n_fields; i++) {
+-		atomic64_set(&dup_elt->fields[i].sum,
+-			     atomic64_read(&elt->fields[i].sum));
+-		dup_elt->fields[i].cmp_fn = elt->fields[i].cmp_fn;
+-	}
+-
+-	return dup_elt;
+-}
+-
+-static int merge_dup(struct tracing_map_sort_entry **sort_entries,
+-		     unsigned int target, unsigned int dup)
+-{
+-	struct tracing_map_elt *target_elt, *elt;
+-	bool first_dup = (target - dup) == 1;
+-	int i;
+-
+-	if (first_dup) {
+-		elt = sort_entries[target]->elt;
+-		target_elt = copy_elt(elt);
+-		if (!target_elt)
+-			return -ENOMEM;
+-		sort_entries[target]->elt = target_elt;
+-		sort_entries[target]->elt_copied = true;
+-	} else
+-		target_elt = sort_entries[target]->elt;
+-
+-	elt = sort_entries[dup]->elt;
+-
+-	for (i = 0; i < elt->map->n_fields; i++)
+-		atomic64_add(atomic64_read(&elt->fields[i].sum),
+-			     &target_elt->fields[i].sum);
+-
+-	sort_entries[dup]->dup = true;
+-
+-	return 0;
+-}
+-
+-static int merge_dups(struct tracing_map_sort_entry **sort_entries,
++static void detect_dups(struct tracing_map_sort_entry **sort_entries,
+ 		      int n_entries, unsigned int key_size)
+ {
+ 	unsigned int dups = 0, total_dups = 0;
+-	int err, i, j;
++	int i;
+ 	void *key;
+ 
+ 	if (n_entries < 2)
+-		return total_dups;
++		return;
+ 
+ 	sort(sort_entries, n_entries, sizeof(struct tracing_map_sort_entry *),
+ 	     (int (*)(const void *, const void *))cmp_entries_dup, NULL);
+@@ -884,30 +832,14 @@ static int merge_dups(struct tracing_map_sort_entry **sort_entries,
+ 	for (i = 1; i < n_entries; i++) {
+ 		if (!memcmp(sort_entries[i]->key, key, key_size)) {
+ 			dups++; total_dups++;
+-			err = merge_dup(sort_entries, i - dups, i);
+-			if (err)
+-				return err;
+ 			continue;
+ 		}
+ 		key = sort_entries[i]->key;
+ 		dups = 0;
+ 	}
+ 
+-	if (!total_dups)
+-		return total_dups;
+-
+-	for (i = 0, j = 0; i < n_entries; i++) {
+-		if (!sort_entries[i]->dup) {
+-			sort_entries[j] = sort_entries[i];
+-			if (j++ != i)
+-				sort_entries[i] = NULL;
+-		} else {
+-			destroy_sort_entry(sort_entries[i]);
+-			sort_entries[i] = NULL;
+-		}
+-	}
+-
+-	return total_dups;
++	WARN_ONCE(total_dups > 0,
++		  "Duplicates detected: %d\n", total_dups);
+ }
+ 
+ static bool is_key(struct tracing_map *map, unsigned int field_idx)
+@@ -1033,10 +965,7 @@ int tracing_map_sort_entries(struct tracing_map *map,
+ 		return 1;
+ 	}
+ 
+-	ret = merge_dups(entries, n_entries, map->key_size);
+-	if (ret < 0)
+-		goto free;
+-	n_entries -= ret;
++	detect_dups(entries, n_entries, map->key_size);
+ 
+ 	if (is_key(map, sort_keys[0].field_idx))
+ 		cmp_entries_fn = cmp_entries_key;
+diff --git a/kernel/trace/tracing_map.h b/kernel/trace/tracing_map.h
+index ab0ca77331d0..0de50bbc1c51 100644
+--- a/kernel/trace/tracing_map.h
++++ b/kernel/trace/tracing_map.h
+@@ -215,11 +215,6 @@ struct tracing_map {
+  *	Element allocation occurs before tracing begins, when the
+  *	tracing_map_init() call is made by client code.
+  *
+- * @elt_copy: At certain points in the lifetime of an element, it may
+- *	need to be copied.  The copy should include a copy of the
+- *	client-allocated data, which can be copied into the 'to'
+- *	element from the 'from' element.
+- *
+  * @elt_free: When a tracing_map_elt is freed, this function is called
+  *	and allows client-allocated per-element data to be freed.
+  *
+@@ -233,8 +228,6 @@ struct tracing_map {
+  */
+ struct tracing_map_ops {
+ 	int			(*elt_alloc)(struct tracing_map_elt *elt);
+-	void			(*elt_copy)(struct tracing_map_elt *to,
+-					    struct tracing_map_elt *from);
+ 	void			(*elt_free)(struct tracing_map_elt *elt);
+ 	void			(*elt_clear)(struct tracing_map_elt *elt);
+ 	void			(*elt_init)(struct tracing_map_elt *elt);
+-- 
+2.19.0
+
diff --git a/patches/1747-tracing-Give-event-triggers-access-to-ring_buffer_ev.patch b/patches/1747-tracing-Give-event-triggers-access-to-ring_buffer_ev.patch
new file mode 100644
index 00000000000000..654372057cebe5
--- /dev/null
+++ b/patches/1747-tracing-Give-event-triggers-access-to-ring_buffer_ev.patch
@@ -0,0 +1,317 @@
+From 08e3e5293631f9005b217d5b9d6c97d3c1262519 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:42 -0600
+Subject: [PATCH 1747/1795] tracing: Give event triggers access to
+ ring_buffer_event
+
+The ring_buffer event can provide a timestamp that may be useful to
+various triggers - pass it into the handlers for that purpose.
+
+Link: http://lkml.kernel.org/r/6de592683b59fa70ffa5d43d0109896623fc1367.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 1ac4f51c0eb518e04ff3455f0c7d17ad9187eb27)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/trace_events.h        | 14 +++++----
+ kernel/trace/trace.h                |  9 +++---
+ kernel/trace/trace_events_hist.c    | 11 ++++---
+ kernel/trace/trace_events_trigger.c | 47 ++++++++++++++++++-----------
+ 4 files changed, 49 insertions(+), 32 deletions(-)
+
+diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
+index 2bcb4dc6df1a..aefc80f2909b 100644
+--- a/include/linux/trace_events.h
++++ b/include/linux/trace_events.h
+@@ -402,11 +402,13 @@ enum event_trigger_type {
+ 
+ extern int filter_match_preds(struct event_filter *filter, void *rec);
+ 
+-extern enum event_trigger_type event_triggers_call(struct trace_event_file *file,
+-						   void *rec);
+-extern void event_triggers_post_call(struct trace_event_file *file,
+-				     enum event_trigger_type tt,
+-				     void *rec);
++extern enum event_trigger_type
++event_triggers_call(struct trace_event_file *file, void *rec,
++		    struct ring_buffer_event *event);
++extern void
++event_triggers_post_call(struct trace_event_file *file,
++			 enum event_trigger_type tt,
++			 void *rec, struct ring_buffer_event *event);
+ 
+ bool trace_event_ignore_this_pid(struct trace_event_file *trace_file);
+ 
+@@ -426,7 +428,7 @@ trace_trigger_soft_disabled(struct trace_event_file *file)
+ 
+ 	if (!(eflags & EVENT_FILE_FL_TRIGGER_COND)) {
+ 		if (eflags & EVENT_FILE_FL_TRIGGER_MODE)
+-			event_triggers_call(file, NULL);
++			event_triggers_call(file, NULL, NULL);
+ 		if (eflags & EVENT_FILE_FL_SOFT_DISABLED)
+ 			return true;
+ 		if (eflags & EVENT_FILE_FL_PID_FILTER)
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 851cd1605085..96c92f9c314c 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -1293,7 +1293,7 @@ __event_trigger_test_discard(struct trace_event_file *file,
+ 	unsigned long eflags = file->flags;
+ 
+ 	if (eflags & EVENT_FILE_FL_TRIGGER_COND)
+-		*tt = event_triggers_call(file, entry);
++		*tt = event_triggers_call(file, entry, event);
+ 
+ 	if (test_bit(EVENT_FILE_FL_SOFT_DISABLED_BIT, &file->flags) ||
+ 	    (unlikely(file->flags & EVENT_FILE_FL_FILTERED) &&
+@@ -1330,7 +1330,7 @@ event_trigger_unlock_commit(struct trace_event_file *file,
+ 		trace_buffer_unlock_commit(file->tr, buffer, event, irq_flags, pc);
+ 
+ 	if (tt)
+-		event_triggers_post_call(file, tt, entry);
++		event_triggers_post_call(file, tt, entry, event);
+ }
+ 
+ /**
+@@ -1363,7 +1363,7 @@ event_trigger_unlock_commit_regs(struct trace_event_file *file,
+ 						irq_flags, pc, regs);
+ 
+ 	if (tt)
+-		event_triggers_post_call(file, tt, entry);
++		event_triggers_post_call(file, tt, entry, event);
+ }
+ 
+ #define FILTER_PRED_INVALID	((unsigned short)-1)
+@@ -1588,7 +1588,8 @@ extern int register_trigger_hist_enable_disable_cmds(void);
+  */
+ struct event_trigger_ops {
+ 	void			(*func)(struct event_trigger_data *data,
+-					void *rec);
++					void *rec,
++					struct ring_buffer_event *rbe);
+ 	int			(*init)(struct event_trigger_ops *ops,
+ 					struct event_trigger_data *data);
+ 	void			(*free)(struct event_trigger_ops *ops,
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 712260e72be5..63a19123cf47 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -909,7 +909,8 @@ static inline void add_to_key(char *compound_key, void *key,
+ 	memcpy(compound_key + key_field->offset, key, size);
+ }
+ 
+-static void event_hist_trigger(struct event_trigger_data *data, void *rec)
++static void event_hist_trigger(struct event_trigger_data *data, void *rec,
++			       struct ring_buffer_event *event)
+ {
+ 	struct hist_trigger_data *hist_data = data->private_data;
+ 	bool use_compound_key = (hist_data->n_keys > 1);
+@@ -1658,7 +1659,8 @@ __init int register_trigger_hist_cmd(void)
+ }
+ 
+ static void
+-hist_enable_trigger(struct event_trigger_data *data, void *rec)
++hist_enable_trigger(struct event_trigger_data *data, void *rec,
++		    struct ring_buffer_event *event)
+ {
+ 	struct enable_trigger_data *enable_data = data->private_data;
+ 	struct event_trigger_data *test;
+@@ -1674,7 +1676,8 @@ hist_enable_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-hist_enable_count_trigger(struct event_trigger_data *data, void *rec)
++hist_enable_count_trigger(struct event_trigger_data *data, void *rec,
++			  struct ring_buffer_event *event)
+ {
+ 	if (!data->count)
+ 		return;
+@@ -1682,7 +1685,7 @@ hist_enable_count_trigger(struct event_trigger_data *data, void *rec)
+ 	if (data->count != -1)
+ 		(data->count)--;
+ 
+-	hist_enable_trigger(data, rec);
++	hist_enable_trigger(data, rec, event);
+ }
+ 
+ static struct event_trigger_ops hist_enable_trigger_ops = {
+diff --git a/kernel/trace/trace_events_trigger.c b/kernel/trace/trace_events_trigger.c
+index 43254c5e7e16..4c269f2e00a4 100644
+--- a/kernel/trace/trace_events_trigger.c
++++ b/kernel/trace/trace_events_trigger.c
+@@ -63,7 +63,8 @@ void trigger_data_free(struct event_trigger_data *data)
+  * any trigger that should be deferred, ETT_NONE if nothing to defer.
+  */
+ enum event_trigger_type
+-event_triggers_call(struct trace_event_file *file, void *rec)
++event_triggers_call(struct trace_event_file *file, void *rec,
++		    struct ring_buffer_event *event)
+ {
+ 	struct event_trigger_data *data;
+ 	enum event_trigger_type tt = ETT_NONE;
+@@ -76,7 +77,7 @@ event_triggers_call(struct trace_event_file *file, void *rec)
+ 		if (data->paused)
+ 			continue;
+ 		if (!rec) {
+-			data->ops->func(data, rec);
++			data->ops->func(data, rec, event);
+ 			continue;
+ 		}
+ 		filter = rcu_dereference_sched(data->filter);
+@@ -86,7 +87,7 @@ event_triggers_call(struct trace_event_file *file, void *rec)
+ 			tt |= data->cmd_ops->trigger_type;
+ 			continue;
+ 		}
+-		data->ops->func(data, rec);
++		data->ops->func(data, rec, event);
+ 	}
+ 	return tt;
+ }
+@@ -108,7 +109,7 @@ EXPORT_SYMBOL_GPL(event_triggers_call);
+ void
+ event_triggers_post_call(struct trace_event_file *file,
+ 			 enum event_trigger_type tt,
+-			 void *rec)
++			 void *rec, struct ring_buffer_event *event)
+ {
+ 	struct event_trigger_data *data;
+ 
+@@ -116,7 +117,7 @@ event_triggers_post_call(struct trace_event_file *file,
+ 		if (data->paused)
+ 			continue;
+ 		if (data->cmd_ops->trigger_type & tt)
+-			data->ops->func(data, rec);
++			data->ops->func(data, rec, event);
+ 	}
+ }
+ EXPORT_SYMBOL_GPL(event_triggers_post_call);
+@@ -915,7 +916,8 @@ void set_named_trigger_data(struct event_trigger_data *data,
+ }
+ 
+ static void
+-traceon_trigger(struct event_trigger_data *data, void *rec)
++traceon_trigger(struct event_trigger_data *data, void *rec,
++		struct ring_buffer_event *event)
+ {
+ 	if (tracing_is_on())
+ 		return;
+@@ -924,7 +926,8 @@ traceon_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-traceon_count_trigger(struct event_trigger_data *data, void *rec)
++traceon_count_trigger(struct event_trigger_data *data, void *rec,
++		      struct ring_buffer_event *event)
+ {
+ 	if (tracing_is_on())
+ 		return;
+@@ -939,7 +942,8 @@ traceon_count_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-traceoff_trigger(struct event_trigger_data *data, void *rec)
++traceoff_trigger(struct event_trigger_data *data, void *rec,
++		 struct ring_buffer_event *event)
+ {
+ 	if (!tracing_is_on())
+ 		return;
+@@ -948,7 +952,8 @@ traceoff_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-traceoff_count_trigger(struct event_trigger_data *data, void *rec)
++traceoff_count_trigger(struct event_trigger_data *data, void *rec,
++		       struct ring_buffer_event *event)
+ {
+ 	if (!tracing_is_on())
+ 		return;
+@@ -1045,7 +1050,8 @@ static struct event_command trigger_traceoff_cmd = {
+ 
+ #ifdef CONFIG_TRACER_SNAPSHOT
+ static void
+-snapshot_trigger(struct event_trigger_data *data, void *rec)
++snapshot_trigger(struct event_trigger_data *data, void *rec,
++		 struct ring_buffer_event *event)
+ {
+ 	struct trace_event_file *file = data->private_data;
+ 
+@@ -1056,7 +1062,8 @@ snapshot_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-snapshot_count_trigger(struct event_trigger_data *data, void *rec)
++snapshot_count_trigger(struct event_trigger_data *data, void *rec,
++		       struct ring_buffer_event *event)
+ {
+ 	if (!data->count)
+ 		return;
+@@ -1064,7 +1071,7 @@ snapshot_count_trigger(struct event_trigger_data *data, void *rec)
+ 	if (data->count != -1)
+ 		(data->count)--;
+ 
+-	snapshot_trigger(data, rec);
++	snapshot_trigger(data, rec, event);
+ }
+ 
+ static int
+@@ -1143,13 +1150,15 @@ static __init int register_trigger_snapshot_cmd(void) { return 0; }
+ #define STACK_SKIP 3
+ 
+ static void
+-stacktrace_trigger(struct event_trigger_data *data, void *rec)
++stacktrace_trigger(struct event_trigger_data *data, void *rec,
++		   struct ring_buffer_event *event)
+ {
+ 	trace_dump_stack(STACK_SKIP);
+ }
+ 
+ static void
+-stacktrace_count_trigger(struct event_trigger_data *data, void *rec)
++stacktrace_count_trigger(struct event_trigger_data *data, void *rec,
++			 struct ring_buffer_event *event)
+ {
+ 	if (!data->count)
+ 		return;
+@@ -1157,7 +1166,7 @@ stacktrace_count_trigger(struct event_trigger_data *data, void *rec)
+ 	if (data->count != -1)
+ 		(data->count)--;
+ 
+-	stacktrace_trigger(data, rec);
++	stacktrace_trigger(data, rec, event);
+ }
+ 
+ static int
+@@ -1219,7 +1228,8 @@ static __init void unregister_trigger_traceon_traceoff_cmds(void)
+ }
+ 
+ static void
+-event_enable_trigger(struct event_trigger_data *data, void *rec)
++event_enable_trigger(struct event_trigger_data *data, void *rec,
++		     struct ring_buffer_event *event)
+ {
+ 	struct enable_trigger_data *enable_data = data->private_data;
+ 
+@@ -1230,7 +1240,8 @@ event_enable_trigger(struct event_trigger_data *data, void *rec)
+ }
+ 
+ static void
+-event_enable_count_trigger(struct event_trigger_data *data, void *rec)
++event_enable_count_trigger(struct event_trigger_data *data, void *rec,
++			   struct ring_buffer_event *event)
+ {
+ 	struct enable_trigger_data *enable_data = data->private_data;
+ 
+@@ -1244,7 +1255,7 @@ event_enable_count_trigger(struct event_trigger_data *data, void *rec)
+ 	if (data->count != -1)
+ 		(data->count)--;
+ 
+-	event_enable_trigger(data, rec);
++	event_enable_trigger(data, rec, event);
+ }
+ 
+ int event_enable_trigger_print(struct seq_file *m,
+-- 
+2.19.0
+
diff --git a/patches/1748-tracing-Add-ring-buffer-event-param-to-hist-field-fu.patch b/patches/1748-tracing-Add-ring-buffer-event-param-to-hist-field-fu.patch
new file mode 100644
index 00000000000000..82007b5795a710
--- /dev/null
+++ b/patches/1748-tracing-Add-ring-buffer-event-param-to-hist-field-fu.patch
@@ -0,0 +1,150 @@
+From 71c9301e00046686250d0087c2bc780bf505656a Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:43 -0600
+Subject: [PATCH 1748/1795] tracing: Add ring buffer event param to hist field
+ functions
+
+Some events such as timestamps require access to a ring_buffer_event
+struct; add a param so that hist field functions can access that.
+
+Link: http://lkml.kernel.org/r/2ff4af18e72b6002eb86b26b2a7f39cef7d1dfe4.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit fbd302cbebe9408699fd11a4eb423d0a466058b9)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 39 ++++++++++++++++++++------------
+ 1 file changed, 24 insertions(+), 15 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 63a19123cf47..37f5acefdc6c 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -26,7 +26,8 @@
+ 
+ struct hist_field;
+ 
+-typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event);
++typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event,
++				struct ring_buffer_event *rbe);
+ 
+ #define HIST_FIELD_OPERANDS_MAX	2
+ 
+@@ -40,24 +41,28 @@ struct hist_field {
+ 	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
+ };
+ 
+-static u64 hist_field_none(struct hist_field *field, void *event)
++static u64 hist_field_none(struct hist_field *field, void *event,
++			   struct ring_buffer_event *rbe)
+ {
+ 	return 0;
+ }
+ 
+-static u64 hist_field_counter(struct hist_field *field, void *event)
++static u64 hist_field_counter(struct hist_field *field, void *event,
++			      struct ring_buffer_event *rbe)
+ {
+ 	return 1;
+ }
+ 
+-static u64 hist_field_string(struct hist_field *hist_field, void *event)
++static u64 hist_field_string(struct hist_field *hist_field, void *event,
++			     struct ring_buffer_event *rbe)
+ {
+ 	char *addr = (char *)(event + hist_field->field->offset);
+ 
+ 	return (u64)(unsigned long)addr;
+ }
+ 
+-static u64 hist_field_dynstring(struct hist_field *hist_field, void *event)
++static u64 hist_field_dynstring(struct hist_field *hist_field, void *event,
++				struct ring_buffer_event *rbe)
+ {
+ 	u32 str_item = *(u32 *)(event + hist_field->field->offset);
+ 	int str_loc = str_item & 0xffff;
+@@ -66,24 +71,28 @@ static u64 hist_field_dynstring(struct hist_field *hist_field, void *event)
+ 	return (u64)(unsigned long)addr;
+ }
+ 
+-static u64 hist_field_pstring(struct hist_field *hist_field, void *event)
++static u64 hist_field_pstring(struct hist_field *hist_field, void *event,
++			      struct ring_buffer_event *rbe)
+ {
+ 	char **addr = (char **)(event + hist_field->field->offset);
+ 
+ 	return (u64)(unsigned long)*addr;
+ }
+ 
+-static u64 hist_field_log2(struct hist_field *hist_field, void *event)
++static u64 hist_field_log2(struct hist_field *hist_field, void *event,
++			   struct ring_buffer_event *rbe)
+ {
+ 	struct hist_field *operand = hist_field->operands[0];
+ 
+-	u64 val = operand->fn(operand, event);
++	u64 val = operand->fn(operand, event, rbe);
+ 
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+ 
+ #define DEFINE_HIST_FIELD_FN(type)					\
+-static u64 hist_field_##type(struct hist_field *hist_field, void *event)\
++	static u64 hist_field_##type(struct hist_field *hist_field,	\
++				     void *event,			\
++				     struct ring_buffer_event *rbe)	\
+ {									\
+ 	type *addr = (type *)(event + hist_field->field->offset);	\
+ 									\
+@@ -871,8 +880,8 @@ create_hist_data(unsigned int map_bits,
+ }
+ 
+ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+-				    struct tracing_map_elt *elt,
+-				    void *rec)
++				    struct tracing_map_elt *elt, void *rec,
++				    struct ring_buffer_event *rbe)
+ {
+ 	struct hist_field *hist_field;
+ 	unsigned int i;
+@@ -880,7 +889,7 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 
+ 	for_each_hist_val_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+-		hist_val = hist_field->fn(hist_field, rec);
++		hist_val = hist_field->fn(hist_field, rec, rbe);
+ 		tracing_map_update_sum(elt, i, hist_val);
+ 	}
+ }
+@@ -910,7 +919,7 @@ static inline void add_to_key(char *compound_key, void *key,
+ }
+ 
+ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+-			       struct ring_buffer_event *event)
++			       struct ring_buffer_event *rbe)
+ {
+ 	struct hist_trigger_data *hist_data = data->private_data;
+ 	bool use_compound_key = (hist_data->n_keys > 1);
+@@ -939,7 +948,7 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 
+ 			key = entries;
+ 		} else {
+-			field_contents = key_field->fn(key_field, rec);
++			field_contents = key_field->fn(key_field, rec, rbe);
+ 			if (key_field->flags & HIST_FIELD_FL_STRING) {
+ 				key = (void *)(unsigned long)field_contents;
+ 				use_compound_key = true;
+@@ -956,7 +965,7 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 
+ 	elt = tracing_map_insert(hist_data->map, key);
+ 	if (elt)
+-		hist_trigger_elt_update(hist_data, elt, rec);
++		hist_trigger_elt_update(hist_data, elt, rec, rbe);
+ }
+ 
+ static void hist_trigger_stacktrace_print(struct seq_file *m,
+-- 
+2.19.0
+
diff --git a/patches/1749-tracing-Break-out-hist-trigger-assignment-parsing.patch b/patches/1749-tracing-Break-out-hist-trigger-assignment-parsing.patch
new file mode 100644
index 00000000000000..1dad7251ecfc9f
--- /dev/null
+++ b/patches/1749-tracing-Break-out-hist-trigger-assignment-parsing.patch
@@ -0,0 +1,119 @@
+From 42758f17c9dbdc0be30d5d7ff1c5df25b8d4e812 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:44 -0600
+Subject: [PATCH 1749/1795] tracing: Break out hist trigger assignment parsing
+
+This will make it easier to add variables, and makes the parsing code
+cleaner regardless.
+
+Link: http://lkml.kernel.org/r/e574b3291bbe15e35a4dfc87e5395aa715701c98.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Rajvi Jingar <rajvi.jingar@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 9b1ae035c9304ed1e183de3b3bb08eafd01a7553)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 72 ++++++++++++++++++++++----------
+ 1 file changed, 51 insertions(+), 21 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 37f5acefdc6c..e4368bb7ba30 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -251,6 +251,51 @@ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ 	kfree(attrs);
+ }
+ 
++static int parse_assignment(char *str, struct hist_trigger_attrs *attrs)
++{
++	int ret = 0;
++
++	if ((strncmp(str, "key=", strlen("key=")) == 0) ||
++	    (strncmp(str, "keys=", strlen("keys=")) == 0)) {
++		attrs->keys_str = kstrdup(str, GFP_KERNEL);
++		if (!attrs->keys_str) {
++			ret = -ENOMEM;
++			goto out;
++		}
++	} else if ((strncmp(str, "val=", strlen("val=")) == 0) ||
++		 (strncmp(str, "vals=", strlen("vals=")) == 0) ||
++		 (strncmp(str, "values=", strlen("values=")) == 0)) {
++		attrs->vals_str = kstrdup(str, GFP_KERNEL);
++		if (!attrs->vals_str) {
++			ret = -ENOMEM;
++			goto out;
++		}
++	} else if (strncmp(str, "sort=", strlen("sort=")) == 0) {
++		attrs->sort_key_str = kstrdup(str, GFP_KERNEL);
++		if (!attrs->sort_key_str) {
++			ret = -ENOMEM;
++			goto out;
++		}
++	} else if (strncmp(str, "name=", strlen("name=")) == 0) {
++		attrs->name = kstrdup(str, GFP_KERNEL);
++		if (!attrs->name) {
++			ret = -ENOMEM;
++			goto out;
++		}
++	} else if (strncmp(str, "size=", strlen("size=")) == 0) {
++		int map_bits = parse_map_size(str);
++
++		if (map_bits < 0) {
++			ret = map_bits;
++			goto out;
++		}
++		attrs->map_bits = map_bits;
++	} else
++		ret = -EINVAL;
++ out:
++	return ret;
++}
++
+ static struct hist_trigger_attrs *parse_hist_trigger_attrs(char *trigger_str)
+ {
+ 	struct hist_trigger_attrs *attrs;
+@@ -263,33 +308,18 @@ static struct hist_trigger_attrs *parse_hist_trigger_attrs(char *trigger_str)
+ 	while (trigger_str) {
+ 		char *str = strsep(&trigger_str, ":");
+ 
+-		if ((strncmp(str, "key=", strlen("key=")) == 0) ||
+-		    (strncmp(str, "keys=", strlen("keys=")) == 0))
+-			attrs->keys_str = kstrdup(str, GFP_KERNEL);
+-		else if ((strncmp(str, "val=", strlen("val=")) == 0) ||
+-			 (strncmp(str, "vals=", strlen("vals=")) == 0) ||
+-			 (strncmp(str, "values=", strlen("values=")) == 0))
+-			attrs->vals_str = kstrdup(str, GFP_KERNEL);
+-		else if (strncmp(str, "sort=", strlen("sort=")) == 0)
+-			attrs->sort_key_str = kstrdup(str, GFP_KERNEL);
+-		else if (strncmp(str, "name=", strlen("name=")) == 0)
+-			attrs->name = kstrdup(str, GFP_KERNEL);
+-		else if (strcmp(str, "pause") == 0)
++		if (strchr(str, '=')) {
++			ret = parse_assignment(str, attrs);
++			if (ret)
++				goto free;
++		} else if (strcmp(str, "pause") == 0)
+ 			attrs->pause = true;
+ 		else if ((strcmp(str, "cont") == 0) ||
+ 			 (strcmp(str, "continue") == 0))
+ 			attrs->cont = true;
+ 		else if (strcmp(str, "clear") == 0)
+ 			attrs->clear = true;
+-		else if (strncmp(str, "size=", strlen("size=")) == 0) {
+-			int map_bits = parse_map_size(str);
+-
+-			if (map_bits < 0) {
+-				ret = map_bits;
+-				goto free;
+-			}
+-			attrs->map_bits = map_bits;
+-		} else {
++		else {
+ 			ret = -EINVAL;
+ 			goto free;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/1750-ring-buffer-Rewrite-trace_recursive_-un-lock-to-be-s.patch b/patches/1750-ring-buffer-Rewrite-trace_recursive_-un-lock-to-be-s.patch
new file mode 100644
index 00000000000000..215426b73d6ba6
--- /dev/null
+++ b/patches/1750-ring-buffer-Rewrite-trace_recursive_-un-lock-to-be-s.patch
@@ -0,0 +1,124 @@
+From 9373c724d0d890b4015f4fe1146e251222c0b951 Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Fri, 22 Sep 2017 16:59:02 -0400
+Subject: [PATCH 1750/1795] ring-buffer: Rewrite trace_recursive_(un)lock() to
+ be simpler
+
+The current method to prevent the ring buffer from entering into a recursize
+loop is to use a bitmask and set the bit that maps to the current context
+(normal, softirq, irq or NMI), and if that bit was already set, it is
+considered a recursive loop.
+
+New code is being added that may require the ring buffer to be entered a
+second time in the current context. The recursive locking prevents that from
+happening. Instead of mapping a bitmask to the current context, just allow 4
+levels of nesting in the ring buffer. This matches the 4 context levels that
+it can already nest. It is highly unlikely to have more than two levels,
+thus it should be fine when we add the second entry into the ring buffer. If
+that proves to be a problem, we can always up the number to 8.
+
+An added benefit is that reading preempt_count() to get the current level
+adds a very slight but noticeable overhead. This removes that need.
+
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 1a149d7d3f45d311da1f63473736c05f30ae8a75)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/ring_buffer.c | 64 ++++++++++----------------------------
+ 1 file changed, 17 insertions(+), 47 deletions(-)
+
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index fd7809004297..c3b6b47fd44a 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -2545,61 +2545,29 @@ rb_wakeups(struct ring_buffer *buffer, struct ring_buffer_per_cpu *cpu_buffer)
+  * The lock and unlock are done within a preempt disable section.
+  * The current_context per_cpu variable can only be modified
+  * by the current task between lock and unlock. But it can
+- * be modified more than once via an interrupt. To pass this
+- * information from the lock to the unlock without having to
+- * access the 'in_interrupt()' functions again (which do show
+- * a bit of overhead in something as critical as function tracing,
+- * we use a bitmask trick.
++ * be modified more than once via an interrupt. There are four
++ * different contexts that we need to consider.
+  *
+- *  bit 0 =  NMI context
+- *  bit 1 =  IRQ context
+- *  bit 2 =  SoftIRQ context
+- *  bit 3 =  normal context.
++ *  Normal context.
++ *  SoftIRQ context
++ *  IRQ context
++ *  NMI context
+  *
+- * This works because this is the order of contexts that can
+- * preempt other contexts. A SoftIRQ never preempts an IRQ
+- * context.
+- *
+- * When the context is determined, the corresponding bit is
+- * checked and set (if it was set, then a recursion of that context
+- * happened).
+- *
+- * On unlock, we need to clear this bit. To do so, just subtract
+- * 1 from the current_context and AND it to itself.
+- *
+- * (binary)
+- *  101 - 1 = 100
+- *  101 & 100 = 100 (clearing bit zero)
+- *
+- *  1010 - 1 = 1001
+- *  1010 & 1001 = 1000 (clearing bit 1)
+- *
+- * The least significant bit can be cleared this way, and it
+- * just so happens that it is the same bit corresponding to
+- * the current context.
++ * If for some reason the ring buffer starts to recurse, we
++ * only allow that to happen at most 4 times (one for each
++ * context). If it happens 5 times, then we consider this a
++ * recusive loop and do not let it go further.
+  */
+ 
+ static __always_inline int
+ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ {
+-	unsigned int val = cpu_buffer->current_context;
+-	int bit;
+-
+-	if (in_interrupt()) {
+-		if (in_nmi())
+-			bit = RB_CTX_NMI;
+-		else if (in_irq())
+-			bit = RB_CTX_IRQ;
+-		else
+-			bit = RB_CTX_SOFTIRQ;
+-	} else
+-		bit = RB_CTX_NORMAL;
+-
+-	if (unlikely(val & (1 << bit)))
++	if (cpu_buffer->current_context >= 4)
+ 		return 1;
+ 
+-	val |= (1 << bit);
+-	cpu_buffer->current_context = val;
++	cpu_buffer->current_context++;
++	/* Interrupts must see this update */
++	barrier();
+ 
+ 	return 0;
+ }
+@@ -2607,7 +2575,9 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ static __always_inline void
+ trace_recursive_unlock(struct ring_buffer_per_cpu *cpu_buffer)
+ {
+-	cpu_buffer->current_context &= cpu_buffer->current_context - 1;
++	/* Don't let the dec leak out */
++	barrier();
++	cpu_buffer->current_context--;
+ }
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1751-ring-buffer-Bring-back-context-level-recursive-check.patch b/patches/1751-ring-buffer-Bring-back-context-level-recursive-check.patch
new file mode 100644
index 00000000000000..8d96005c96d7bf
--- /dev/null
+++ b/patches/1751-ring-buffer-Bring-back-context-level-recursive-check.patch
@@ -0,0 +1,134 @@
+From ada23368d7c34231796b9443d29f56f0b137d180 Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Mon, 15 Jan 2018 10:47:09 -0500
+Subject: [PATCH 1751/1795] ring-buffer: Bring back context level recursive
+ checks
+
+Commit 1a149d7d3f45 ("ring-buffer: Rewrite trace_recursive_(un)lock() to be
+simpler") replaced the context level recursion checks with a simple counter.
+This would prevent the ring buffer code from recursively calling itself more
+than the max number of contexts that exist (Normal, softirq, irq, nmi). But
+this change caused a lockup in a specific case, which was during suspend and
+resume using a global clock. Adding a stack dump to see where this occurred,
+the issue was in the trace global clock itself:
+
+  trace_buffer_lock_reserve+0x1c/0x50
+  __trace_graph_entry+0x2d/0x90
+  trace_graph_entry+0xe8/0x200
+  prepare_ftrace_return+0x69/0xc0
+  ftrace_graph_caller+0x78/0xa8
+  queued_spin_lock_slowpath+0x5/0x1d0
+  trace_clock_global+0xb0/0xc0
+  ring_buffer_lock_reserve+0xf9/0x390
+
+The function graph tracer traced queued_spin_lock_slowpath that was called
+by trace_clock_global. This pointed out that the trace_clock_global() is not
+reentrant, as it takes a spin lock. It depended on the ring buffer recursive
+lock from letting that happen.
+
+By removing the context detection and adding just a max number of allowable
+recursions, it allowed the trace_clock_global() to be entered again and try
+to retake the spinlock it already held, causing a deadlock.
+
+Fixes: 1a149d7d3f45 ("ring-buffer: Rewrite trace_recursive_(un)lock() to be simpler")
+Reported-by: David Weinehall <david.weinehall@gmail.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit a0e3a18f4baf8e3754ac1e56f0ade924d0c0c721)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/ring_buffer.c | 62 +++++++++++++++++++++++++++-----------
+ 1 file changed, 45 insertions(+), 17 deletions(-)
+
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index c3b6b47fd44a..5c4dc1c18519 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -2545,29 +2545,59 @@ rb_wakeups(struct ring_buffer *buffer, struct ring_buffer_per_cpu *cpu_buffer)
+  * The lock and unlock are done within a preempt disable section.
+  * The current_context per_cpu variable can only be modified
+  * by the current task between lock and unlock. But it can
+- * be modified more than once via an interrupt. There are four
+- * different contexts that we need to consider.
++ * be modified more than once via an interrupt. To pass this
++ * information from the lock to the unlock without having to
++ * access the 'in_interrupt()' functions again (which do show
++ * a bit of overhead in something as critical as function tracing,
++ * we use a bitmask trick.
+  *
+- *  Normal context.
+- *  SoftIRQ context
+- *  IRQ context
+- *  NMI context
++ *  bit 0 =  NMI context
++ *  bit 1 =  IRQ context
++ *  bit 2 =  SoftIRQ context
++ *  bit 3 =  normal context.
+  *
+- * If for some reason the ring buffer starts to recurse, we
+- * only allow that to happen at most 4 times (one for each
+- * context). If it happens 5 times, then we consider this a
+- * recusive loop and do not let it go further.
++ * This works because this is the order of contexts that can
++ * preempt other contexts. A SoftIRQ never preempts an IRQ
++ * context.
++ *
++ * When the context is determined, the corresponding bit is
++ * checked and set (if it was set, then a recursion of that context
++ * happened).
++ *
++ * On unlock, we need to clear this bit. To do so, just subtract
++ * 1 from the current_context and AND it to itself.
++ *
++ * (binary)
++ *  101 - 1 = 100
++ *  101 & 100 = 100 (clearing bit zero)
++ *
++ *  1010 - 1 = 1001
++ *  1010 & 1001 = 1000 (clearing bit 1)
++ *
++ * The least significant bit can be cleared this way, and it
++ * just so happens that it is the same bit corresponding to
++ * the current context.
+  */
+ 
+ static __always_inline int
+ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ {
+-	if (cpu_buffer->current_context >= 4)
++	unsigned int val = cpu_buffer->current_context;
++	unsigned long pc = preempt_count();
++	int bit;
++
++	if (!(pc & (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET)))
++		bit = RB_CTX_NORMAL;
++	else
++		bit = pc & NMI_MASK ? RB_CTX_NMI :
++			pc & HARDIRQ_MASK ? RB_CTX_IRQ :
++			pc & SOFTIRQ_OFFSET ? 2 : RB_CTX_SOFTIRQ;
++
++	if (unlikely(val & (1 << bit)))
+ 		return 1;
+ 
+-	cpu_buffer->current_context++;
+-	/* Interrupts must see this update */
+-	barrier();
++	val |= (1 << bit);
++	cpu_buffer->current_context = val;
+ 
+ 	return 0;
+ }
+@@ -2575,9 +2605,7 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ static __always_inline void
+ trace_recursive_unlock(struct ring_buffer_per_cpu *cpu_buffer)
+ {
+-	/* Don't let the dec leak out */
+-	barrier();
+-	cpu_buffer->current_context--;
++	cpu_buffer->current_context &= cpu_buffer->current_context - 1;
+ }
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1752-ring-buffer-Fix-duplicate-results-in-mapping-context.patch b/patches/1752-ring-buffer-Fix-duplicate-results-in-mapping-context.patch
new file mode 100644
index 00000000000000..10ee97b31c756b
--- /dev/null
+++ b/patches/1752-ring-buffer-Fix-duplicate-results-in-mapping-context.patch
@@ -0,0 +1,43 @@
+From a80b4e33952be0209ba984df1ff7464a72c353ad Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Thu, 18 Jan 2018 15:42:09 -0500
+Subject: [PATCH 1752/1795] ring-buffer: Fix duplicate results in mapping
+ context to bits in recursive lock
+
+In bringing back the context checks, the code checks first if its normal
+(non-interrupt) context, and then for NMI then IRQ then softirq. The final
+check is redundant. Since the if branch is only hit if the context is one of
+NMI, IRQ, or SOFTIRQ, if it's not NMI or IRQ there's no reason to check if
+it is SOFTIRQ. The current code returns the same result even if its not a
+SOFTIRQ. Which is confusing.
+
+  pc & SOFTIRQ_OFFSET ? 2 : RB_CTX_SOFTIRQ
+
+Is redundant as RB_CTX_SOFTIRQ *is* 2!
+
+Fixes: a0e3a18f4baf ("ring-buffer: Bring back context level recursive checks")
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 0164e0d7e803af3ee1c63770978c728f8778ad01)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/ring_buffer.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index 5c4dc1c18519..e3769d3c9bca 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -2590,8 +2590,7 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ 		bit = RB_CTX_NORMAL;
+ 	else
+ 		bit = pc & NMI_MASK ? RB_CTX_NMI :
+-			pc & HARDIRQ_MASK ? RB_CTX_IRQ :
+-			pc & SOFTIRQ_OFFSET ? 2 : RB_CTX_SOFTIRQ;
++			pc & HARDIRQ_MASK ? RB_CTX_IRQ : RB_CTX_SOFTIRQ;
+ 
+ 	if (unlikely(val & (1 << bit)))
+ 		return 1;
+-- 
+2.19.0
+
diff --git a/patches/1753-ring-buffer-Add-interface-for-setting-absolute-time-.patch b/patches/1753-ring-buffer-Add-interface-for-setting-absolute-time-.patch
new file mode 100644
index 00000000000000..74da00ac672896
--- /dev/null
+++ b/patches/1753-ring-buffer-Add-interface-for-setting-absolute-time-.patch
@@ -0,0 +1,145 @@
+From cf5a79a4fc58f655ef60463859926d360c048d1b Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:39 -0600
+Subject: [PATCH 1753/1795] ring-buffer: Add interface for setting absolute
+ time stamps
+
+Define a new function, tracing_set_time_stamp_abs(), which can be used
+to enable or disable the use of absolute timestamps rather than time
+deltas for a trace array.
+
+Only the interface is added here; a subsequent patch will add the
+underlying implementation.
+
+Link: http://lkml.kernel.org/r/ce96119de44c7fe0ee44786d15254e9b493040d3.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Baohong Liu <baohong.liu@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 00b4145298aeb05a2d110117ed18148cb21ebd14)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/ring_buffer.h |  2 ++
+ kernel/trace/ring_buffer.c  | 11 +++++++++++
+ kernel/trace/trace.c        | 33 ++++++++++++++++++++++++++++++++-
+ kernel/trace/trace.h        |  3 +++
+ 4 files changed, 48 insertions(+), 1 deletion(-)
+
+diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
+index 5caa062a02b2..adffb56bae8f 100644
+--- a/include/linux/ring_buffer.h
++++ b/include/linux/ring_buffer.h
+@@ -179,6 +179,8 @@ void ring_buffer_normalize_time_stamp(struct ring_buffer *buffer,
+ 				      int cpu, u64 *ts);
+ void ring_buffer_set_clock(struct ring_buffer *buffer,
+ 			   u64 (*clock)(void));
++void ring_buffer_set_time_stamp_abs(struct ring_buffer *buffer, bool abs);
++bool ring_buffer_time_stamp_abs(struct ring_buffer *buffer);
+ 
+ size_t ring_buffer_page_len(void *page);
+ 
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index e3769d3c9bca..eed0e343b008 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -488,6 +488,7 @@ struct ring_buffer {
+ 	u64				(*clock)(void);
+ 
+ 	struct rb_irq_work		irq_work;
++	bool				time_stamp_abs;
+ };
+ 
+ struct ring_buffer_iter {
+@@ -1387,6 +1388,16 @@ void ring_buffer_set_clock(struct ring_buffer *buffer,
+ 	buffer->clock = clock;
+ }
+ 
++void ring_buffer_set_time_stamp_abs(struct ring_buffer *buffer, bool abs)
++{
++	buffer->time_stamp_abs = abs;
++}
++
++bool ring_buffer_time_stamp_abs(struct ring_buffer *buffer)
++{
++	return buffer->time_stamp_abs;
++}
++
+ static void rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer);
+ 
+ static inline unsigned long rb_page_entries(struct buffer_page *bpage)
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index e9cbb96cd99e..0359ff7ba906 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -2275,7 +2275,7 @@ trace_event_buffer_lock_reserve(struct ring_buffer **current_rb,
+ 
+ 	*current_rb = trace_file->tr->trace_buffer.buffer;
+ 
+-	if ((trace_file->flags &
++	if (!ring_buffer_time_stamp_abs(*current_rb) && (trace_file->flags &
+ 	     (EVENT_FILE_FL_SOFT_DISABLED | EVENT_FILE_FL_FILTERED)) &&
+ 	    (entry = this_cpu_read(trace_buffered_event))) {
+ 		/* Try to use the per cpu buffer first */
+@@ -6298,6 +6298,37 @@ static int tracing_clock_open(struct inode *inode, struct file *file)
+ 	return ret;
+ }
+ 
++int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs)
++{
++	int ret = 0;
++
++	mutex_lock(&trace_types_lock);
++
++	if (abs && tr->time_stamp_abs_ref++)
++		goto out;
++
++	if (!abs) {
++		if (WARN_ON_ONCE(!tr->time_stamp_abs_ref)) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		if (--tr->time_stamp_abs_ref)
++			goto out;
++	}
++
++	ring_buffer_set_time_stamp_abs(tr->trace_buffer.buffer, abs);
++
++#ifdef CONFIG_TRACER_MAX_TRACE
++	if (tr->max_buffer.buffer)
++		ring_buffer_set_time_stamp_abs(tr->max_buffer.buffer, abs);
++#endif
++ out:
++	mutex_unlock(&trace_types_lock);
++
++	return ret;
++}
++
+ struct ftrace_buffer_info {
+ 	struct trace_iterator	iter;
+ 	void			*spare;
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 96c92f9c314c..5f1d4ae594e5 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -273,6 +273,7 @@ struct trace_array {
+ 	/* function tracing enabled */
+ 	int			function_enabled;
+ #endif
++	int			time_stamp_abs_ref;
+ };
+ 
+ enum {
+@@ -286,6 +287,8 @@ extern struct mutex trace_types_lock;
+ extern int trace_array_get(struct trace_array *tr);
+ extern void trace_array_put(struct trace_array *tr);
+ 
++extern int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs);
++
+ /*
+  * The global tracer (top) should be the first trace array added,
+  * but we check the flag anyway.
+-- 
+2.19.0
+
diff --git a/patches/1754-ring-buffer-Redefine-the-unimplemented-RINGBUF_TYPE_.patch b/patches/1754-ring-buffer-Redefine-the-unimplemented-RINGBUF_TYPE_.patch
new file mode 100644
index 00000000000000..8f5b1d02688809
--- /dev/null
+++ b/patches/1754-ring-buffer-Redefine-the-unimplemented-RINGBUF_TYPE_.patch
@@ -0,0 +1,331 @@
+From f3ebe874cc618df8a071d4a8dcfd7b754a8c2a51 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:40 -0600
+Subject: [PATCH 1754/1795] ring-buffer: Redefine the unimplemented
+ RINGBUF_TYPE_TIME_STAMP
+
+RINGBUF_TYPE_TIME_STAMP is defined but not used, and from what I can
+gather was reserved for something like an absolute timestamp feature
+for the ring buffer, if not a complete replacement of the current
+time_delta scheme.
+
+This code redefines RINGBUF_TYPE_TIME_STAMP to implement absolute time
+stamps.  Another way to look at it is that it essentially forces
+extended time_deltas for all events.
+
+The motivation for doing this is to enable time_deltas that aren't
+dependent on previous events in the ring buffer, making it feasible to
+use the ring_buffer_event timetamps in a more random-access way, for
+purposes other than serial event printing.
+
+To set/reset this mode, use tracing_set_timestamp_abs() from the
+previous interface patch.
+
+Link: http://lkml.kernel.org/r/477b362dba1ce7fab9889a1a8e885a62c472f041.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit dc4e2801d400b0346fb281ce9cf010d611e2243c)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/ring_buffer.h |  12 +++--
+ kernel/trace/ring_buffer.c  | 104 ++++++++++++++++++++++++++----------
+ 2 files changed, 83 insertions(+), 33 deletions(-)
+
+diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
+index adffb56bae8f..6c2a6b3f3c6d 100644
+--- a/include/linux/ring_buffer.h
++++ b/include/linux/ring_buffer.h
+@@ -34,10 +34,12 @@ struct ring_buffer_event {
+  *				 array[0] = time delta (28 .. 59)
+  *				 size = 8 bytes
+  *
+- * @RINGBUF_TYPE_TIME_STAMP:	Sync time stamp with external clock
+- *				 array[0]    = tv_nsec
+- *				 array[1..2] = tv_sec
+- *				 size = 16 bytes
++ * @RINGBUF_TYPE_TIME_STAMP:	Absolute timestamp
++ *				 Same format as TIME_EXTEND except that the
++ *				 value is an absolute timestamp, not a delta
++ *				 event.time_delta contains bottom 27 bits
++ *				 array[0] = top (28 .. 59) bits
++ *				 size = 8 bytes
+  *
+  * <= @RINGBUF_TYPE_DATA_TYPE_LEN_MAX:
+  *				Data record
+@@ -54,12 +56,12 @@ enum ring_buffer_type {
+ 	RINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,
+ 	RINGBUF_TYPE_PADDING,
+ 	RINGBUF_TYPE_TIME_EXTEND,
+-	/* FIXME: RINGBUF_TYPE_TIME_STAMP not implemented */
+ 	RINGBUF_TYPE_TIME_STAMP,
+ };
+ 
+ unsigned ring_buffer_event_length(struct ring_buffer_event *event);
+ void *ring_buffer_event_data(struct ring_buffer_event *event);
++u64 ring_buffer_event_time_stamp(struct ring_buffer_event *event);
+ 
+ /*
+  * ring_buffer_discard_commit will remove an event that has not
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index eed0e343b008..45fc91559aa6 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -41,6 +41,8 @@ int ring_buffer_print_entry_header(struct trace_seq *s)
+ 			 RINGBUF_TYPE_PADDING);
+ 	trace_seq_printf(s, "\ttime_extend : type == %d\n",
+ 			 RINGBUF_TYPE_TIME_EXTEND);
++	trace_seq_printf(s, "\ttime_stamp : type == %d\n",
++			 RINGBUF_TYPE_TIME_STAMP);
+ 	trace_seq_printf(s, "\tdata max type_len  == %d\n",
+ 			 RINGBUF_TYPE_DATA_TYPE_LEN_MAX);
+ 
+@@ -140,12 +142,15 @@ int ring_buffer_print_entry_header(struct trace_seq *s)
+ 
+ enum {
+ 	RB_LEN_TIME_EXTEND = 8,
+-	RB_LEN_TIME_STAMP = 16,
++	RB_LEN_TIME_STAMP =  8,
+ };
+ 
+ #define skip_time_extend(event) \
+ 	((struct ring_buffer_event *)((char *)event + RB_LEN_TIME_EXTEND))
+ 
++#define extended_time(event) \
++	(event->type_len >= RINGBUF_TYPE_TIME_EXTEND)
++
+ static inline int rb_null_event(struct ring_buffer_event *event)
+ {
+ 	return event->type_len == RINGBUF_TYPE_PADDING && !event->time_delta;
+@@ -209,7 +214,7 @@ rb_event_ts_length(struct ring_buffer_event *event)
+ {
+ 	unsigned len = 0;
+ 
+-	if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) {
++	if (extended_time(event)) {
+ 		/* time extends include the data event after it */
+ 		len = RB_LEN_TIME_EXTEND;
+ 		event = skip_time_extend(event);
+@@ -231,7 +236,7 @@ unsigned ring_buffer_event_length(struct ring_buffer_event *event)
+ {
+ 	unsigned length;
+ 
+-	if (event->type_len == RINGBUF_TYPE_TIME_EXTEND)
++	if (extended_time(event))
+ 		event = skip_time_extend(event);
+ 
+ 	length = rb_event_length(event);
+@@ -248,7 +253,7 @@ EXPORT_SYMBOL_GPL(ring_buffer_event_length);
+ static __always_inline void *
+ rb_event_data(struct ring_buffer_event *event)
+ {
+-	if (event->type_len == RINGBUF_TYPE_TIME_EXTEND)
++	if (extended_time(event))
+ 		event = skip_time_extend(event);
+ 	BUG_ON(event->type_len > RINGBUF_TYPE_DATA_TYPE_LEN_MAX);
+ 	/* If length is in len field, then array[0] has the data */
+@@ -275,6 +280,27 @@ EXPORT_SYMBOL_GPL(ring_buffer_event_data);
+ #define TS_MASK		((1ULL << TS_SHIFT) - 1)
+ #define TS_DELTA_TEST	(~TS_MASK)
+ 
++/**
++ * ring_buffer_event_time_stamp - return the event's extended timestamp
++ * @event: the event to get the timestamp of
++ *
++ * Returns the extended timestamp associated with a data event.
++ * An extended time_stamp is a 64-bit timestamp represented
++ * internally in a special way that makes the best use of space
++ * contained within a ring buffer event.  This function decodes
++ * it and maps it to a straight u64 value.
++ */
++u64 ring_buffer_event_time_stamp(struct ring_buffer_event *event)
++{
++	u64 ts;
++
++	ts = event->array[0];
++	ts <<= TS_SHIFT;
++	ts += event->time_delta;
++
++	return ts;
++}
++
+ /* Flag when events were overwritten */
+ #define RB_MISSED_EVENTS	(1 << 31)
+ /* Missed count stored at end */
+@@ -2228,12 +2254,15 @@ rb_move_tail(struct ring_buffer_per_cpu *cpu_buffer,
+ 
+ /* Slow path, do not inline */
+ static noinline struct ring_buffer_event *
+-rb_add_time_stamp(struct ring_buffer_event *event, u64 delta)
++rb_add_time_stamp(struct ring_buffer_event *event, u64 delta, bool abs)
+ {
+-	event->type_len = RINGBUF_TYPE_TIME_EXTEND;
++	if (abs)
++		event->type_len = RINGBUF_TYPE_TIME_STAMP;
++	else
++		event->type_len = RINGBUF_TYPE_TIME_EXTEND;
+ 
+-	/* Not the first event on the page? */
+-	if (rb_event_index(event)) {
++	/* Not the first event on the page, or not delta? */
++	if (abs || rb_event_index(event)) {
+ 		event->time_delta = delta & TS_MASK;
+ 		event->array[0] = delta >> TS_SHIFT;
+ 	} else {
+@@ -2276,7 +2305,9 @@ rb_update_event(struct ring_buffer_per_cpu *cpu_buffer,
+ 	 * add it to the start of the resevered space.
+ 	 */
+ 	if (unlikely(info->add_timestamp)) {
+-		event = rb_add_time_stamp(event, delta);
++		bool abs = ring_buffer_time_stamp_abs(cpu_buffer->buffer);
++
++		event = rb_add_time_stamp(event, info->delta, abs);
+ 		length -= RB_LEN_TIME_EXTEND;
+ 		delta = 0;
+ 	}
+@@ -2464,7 +2495,7 @@ static __always_inline void rb_end_commit(struct ring_buffer_per_cpu *cpu_buffer
+ 
+ static inline void rb_event_discard(struct ring_buffer_event *event)
+ {
+-	if (event->type_len == RINGBUF_TYPE_TIME_EXTEND)
++	if (extended_time(event))
+ 		event = skip_time_extend(event);
+ 
+ 	/* array[0] holds the actual length for the discarded event */
+@@ -2508,10 +2539,11 @@ rb_update_write_stamp(struct ring_buffer_per_cpu *cpu_buffer,
+ 			cpu_buffer->write_stamp =
+ 				cpu_buffer->commit_page->page->time_stamp;
+ 		else if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) {
+-			delta = event->array[0];
+-			delta <<= TS_SHIFT;
+-			delta += event->time_delta;
++			delta = ring_buffer_event_time_stamp(event);
+ 			cpu_buffer->write_stamp += delta;
++		} else if (event->type_len == RINGBUF_TYPE_TIME_STAMP) {
++			delta = ring_buffer_event_time_stamp(event);
++			cpu_buffer->write_stamp = delta;
+ 		} else
+ 			cpu_buffer->write_stamp += event->time_delta;
+ 	}
+@@ -2691,7 +2723,7 @@ __rb_reserve_next(struct ring_buffer_per_cpu *cpu_buffer,
+ 	 * If this is the first commit on the page, then it has the same
+ 	 * timestamp as the page itself.
+ 	 */
+-	if (!tail)
++	if (!tail && !ring_buffer_time_stamp_abs(cpu_buffer->buffer))
+ 		info->delta = 0;
+ 
+ 	/* See if we shot pass the end of this buffer page */
+@@ -2768,8 +2800,11 @@ rb_reserve_next_event(struct ring_buffer *buffer,
+ 	/* make sure this diff is calculated here */
+ 	barrier();
+ 
+-	/* Did the write stamp get updated already? */
+-	if (likely(info.ts >= cpu_buffer->write_stamp)) {
++	if (ring_buffer_time_stamp_abs(buffer)) {
++		info.delta = info.ts;
++		rb_handle_timestamp(cpu_buffer, &info);
++	} else /* Did the write stamp get updated already? */
++		if (likely(info.ts >= cpu_buffer->write_stamp)) {
+ 		info.delta = diff;
+ 		if (unlikely(test_time_stamp(info.delta)))
+ 			rb_handle_timestamp(cpu_buffer, &info);
+@@ -3467,14 +3502,13 @@ rb_update_read_stamp(struct ring_buffer_per_cpu *cpu_buffer,
+ 		return;
+ 
+ 	case RINGBUF_TYPE_TIME_EXTEND:
+-		delta = event->array[0];
+-		delta <<= TS_SHIFT;
+-		delta += event->time_delta;
++		delta = ring_buffer_event_time_stamp(event);
+ 		cpu_buffer->read_stamp += delta;
+ 		return;
+ 
+ 	case RINGBUF_TYPE_TIME_STAMP:
+-		/* FIXME: not implemented */
++		delta = ring_buffer_event_time_stamp(event);
++		cpu_buffer->read_stamp = delta;
+ 		return;
+ 
+ 	case RINGBUF_TYPE_DATA:
+@@ -3498,14 +3532,13 @@ rb_update_iter_read_stamp(struct ring_buffer_iter *iter,
+ 		return;
+ 
+ 	case RINGBUF_TYPE_TIME_EXTEND:
+-		delta = event->array[0];
+-		delta <<= TS_SHIFT;
+-		delta += event->time_delta;
++		delta = ring_buffer_event_time_stamp(event);
+ 		iter->read_stamp += delta;
+ 		return;
+ 
+ 	case RINGBUF_TYPE_TIME_STAMP:
+-		/* FIXME: not implemented */
++		delta = ring_buffer_event_time_stamp(event);
++		iter->read_stamp = delta;
+ 		return;
+ 
+ 	case RINGBUF_TYPE_DATA:
+@@ -3729,6 +3762,8 @@ rb_buffer_peek(struct ring_buffer_per_cpu *cpu_buffer, u64 *ts,
+ 	struct buffer_page *reader;
+ 	int nr_loops = 0;
+ 
++	if (ts)
++		*ts = 0;
+  again:
+ 	/*
+ 	 * We repeat when a time extend is encountered.
+@@ -3765,12 +3800,17 @@ rb_buffer_peek(struct ring_buffer_per_cpu *cpu_buffer, u64 *ts,
+ 		goto again;
+ 
+ 	case RINGBUF_TYPE_TIME_STAMP:
+-		/* FIXME: not implemented */
++		if (ts) {
++			*ts = ring_buffer_event_time_stamp(event);
++			ring_buffer_normalize_time_stamp(cpu_buffer->buffer,
++							 cpu_buffer->cpu, ts);
++		}
++		/* Internal data, OK to advance */
+ 		rb_advance_reader(cpu_buffer);
+ 		goto again;
+ 
+ 	case RINGBUF_TYPE_DATA:
+-		if (ts) {
++		if (ts && !(*ts)) {
+ 			*ts = cpu_buffer->read_stamp + event->time_delta;
+ 			ring_buffer_normalize_time_stamp(cpu_buffer->buffer,
+ 							 cpu_buffer->cpu, ts);
+@@ -3795,6 +3835,9 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts)
+ 	struct ring_buffer_event *event;
+ 	int nr_loops = 0;
+ 
++	if (ts)
++		*ts = 0;
++
+ 	cpu_buffer = iter->cpu_buffer;
+ 	buffer = cpu_buffer->buffer;
+ 
+@@ -3847,12 +3890,17 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts)
+ 		goto again;
+ 
+ 	case RINGBUF_TYPE_TIME_STAMP:
+-		/* FIXME: not implemented */
++		if (ts) {
++			*ts = ring_buffer_event_time_stamp(event);
++			ring_buffer_normalize_time_stamp(cpu_buffer->buffer,
++							 cpu_buffer->cpu, ts);
++		}
++		/* Internal data, OK to advance */
+ 		rb_advance_iter(iter);
+ 		goto again;
+ 
+ 	case RINGBUF_TYPE_DATA:
+-		if (ts) {
++		if (ts && !(*ts)) {
+ 			*ts = iter->read_stamp + event->time_delta;
+ 			ring_buffer_normalize_time_stamp(buffer,
+ 							 cpu_buffer->cpu, ts);
+-- 
+2.19.0
+
diff --git a/patches/1755-tracing-Add-hist-trigger-timestamp-support.patch b/patches/1755-tracing-Add-hist-trigger-timestamp-support.patch
new file mode 100644
index 00000000000000..ef92a2542ee909
--- /dev/null
+++ b/patches/1755-tracing-Add-hist-trigger-timestamp-support.patch
@@ -0,0 +1,253 @@
+From c23c45a9f29dd91e0fb2a07cde51f9fabff898ad Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:45 -0600
+Subject: [PATCH 1755/1795] tracing: Add hist trigger timestamp support
+
+Add support for a timestamp event field.  This is actually a 'pseudo-'
+event field in that it behaves like it's part of the event record, but
+is really part of the corresponding ring buffer event.
+
+To make use of the timestamp field, users can specify
+"common_timestamp" as a field name for any histogram.  Note that this
+doesn't make much sense on its own either as either a key or value,
+but needs to be supported even so, since follow-on patches will add
+support for making use of this field in time deltas.  The
+common_timestamp 'field' is not a bona fide event field - so you won't
+find it in the event description - but rather it's a synthetic field
+that can be used like a real field.
+
+Note that the use of this field requires the ring buffer be put into
+'absolute timestamp' mode, which saves the complete timestamp for each
+event rather than an offset.  This mode will be enabled if and only if
+a histogram makes use of the "common_timestamp" field.
+
+Link: http://lkml.kernel.org/r/97afbd646ed146e26271f3458b4b33e16d7817c2.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Baohong Liu <baohong.liu@intel.com>
+[kasan use-after-free fix]
+Signed-off-by: Vedang Patel <vedang.patel@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit ad42febe51ae0a2e875f507a37a6329277f75fdd)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 94 ++++++++++++++++++++++++--------
+ 1 file changed, 71 insertions(+), 23 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index e4368bb7ba30..a793f8c04830 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -89,6 +89,12 @@ static u64 hist_field_log2(struct hist_field *hist_field, void *event,
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+ 
++static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
++				struct ring_buffer_event *rbe)
++{
++	return ring_buffer_event_time_stamp(rbe);
++}
++
+ #define DEFINE_HIST_FIELD_FN(type)					\
+ 	static u64 hist_field_##type(struct hist_field *hist_field,	\
+ 				     void *event,			\
+@@ -135,6 +141,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_SYSCALL		= 1 << 7,
+ 	HIST_FIELD_FL_STACKTRACE	= 1 << 8,
+ 	HIST_FIELD_FL_LOG2		= 1 << 9,
++	HIST_FIELD_FL_TIMESTAMP		= 1 << 10,
+ };
+ 
+ struct hist_trigger_attrs {
+@@ -159,6 +166,7 @@ struct hist_trigger_data {
+ 	struct trace_event_file		*event_file;
+ 	struct hist_trigger_attrs	*attrs;
+ 	struct tracing_map		*map;
++	bool				enable_timestamps;
+ };
+ 
+ static const char *hist_field_name(struct hist_field *field,
+@@ -173,6 +181,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 		field_name = field->field->name;
+ 	else if (field->flags & HIST_FIELD_FL_LOG2)
+ 		field_name = hist_field_name(field->operands[0], ++level);
++	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
++		field_name = "common_timestamp";
+ 
+ 	if (field_name == NULL)
+ 		field_name = "";
+@@ -440,6 +450,12 @@ static struct hist_field *create_hist_field(struct ftrace_event_field *field,
+ 		goto out;
+ 	}
+ 
++	if (flags & HIST_FIELD_FL_TIMESTAMP) {
++		hist_field->fn = hist_field_timestamp;
++		hist_field->size = sizeof(u64);
++		goto out;
++	}
++
+ 	if (WARN_ON_ONCE(!field))
+ 		goto out;
+ 
+@@ -517,10 +533,15 @@ static int create_val_field(struct hist_trigger_data *hist_data,
+ 		}
+ 	}
+ 
+-	field = trace_find_event_field(file->event_call, field_name);
+-	if (!field || !field->size) {
+-		ret = -EINVAL;
+-		goto out;
++	if (strcmp(field_name, "common_timestamp") == 0) {
++		flags |= HIST_FIELD_FL_TIMESTAMP;
++		hist_data->enable_timestamps = true;
++	} else {
++		field = trace_find_event_field(file->event_call, field_name);
++		if (!field || !field->size) {
++			ret = -EINVAL;
++			goto out;
++		}
+ 	}
+ 
+ 	hist_data->fields[val_idx] = create_hist_field(field, flags);
+@@ -615,16 +636,22 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 			}
+ 		}
+ 
+-		field = trace_find_event_field(file->event_call, field_name);
+-		if (!field || !field->size) {
+-			ret = -EINVAL;
+-			goto out;
+-		}
++		if (strcmp(field_name, "common_timestamp") == 0) {
++			flags |= HIST_FIELD_FL_TIMESTAMP;
++			hist_data->enable_timestamps = true;
++			key_size = sizeof(u64);
++		} else {
++			field = trace_find_event_field(file->event_call, field_name);
++			if (!field || !field->size) {
++				ret = -EINVAL;
++				goto out;
++			}
+ 
+-		if (is_string_field(field))
+-			key_size = MAX_FILTER_STR_VAL;
+-		else
+-			key_size = field->size;
++			if (is_string_field(field))
++				key_size = MAX_FILTER_STR_VAL;
++			else
++				key_size = field->size;
++		}
+ 	}
+ 
+ 	hist_data->fields[key_idx] = create_hist_field(field, flags);
+@@ -820,6 +847,9 @@ static int create_tracing_map_fields(struct hist_trigger_data *hist_data)
+ 
+ 			if (hist_field->flags & HIST_FIELD_FL_STACKTRACE)
+ 				cmp_fn = tracing_map_cmp_none;
++			else if (!field)
++				cmp_fn = tracing_map_cmp_num(hist_field->size,
++							     hist_field->is_signed);
+ 			else if (is_string_field(field))
+ 				cmp_fn = tracing_map_cmp_string;
+ 			else
+@@ -1215,7 +1245,11 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ {
+ 	const char *field_name = hist_field_name(hist_field, 0);
+ 
+-	seq_printf(m, "%s", field_name);
++	if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
++		seq_puts(m, "common_timestamp");
++	else if (field_name)
++		seq_printf(m, "%s", field_name);
++
+ 	if (hist_field->flags) {
+ 		const char *flags_str = get_hist_field_flags(hist_field);
+ 
+@@ -1266,27 +1300,25 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 
+ 	for (i = 0; i < hist_data->n_sort_keys; i++) {
+ 		struct tracing_map_sort_key *sort_key;
++		unsigned int idx;
+ 
+ 		sort_key = &hist_data->sort_keys[i];
++		idx = sort_key->field_idx;
++
++		if (WARN_ON(idx >= TRACING_MAP_FIELDS_MAX))
++			return -EINVAL;
+ 
+ 		if (i > 0)
+ 			seq_puts(m, ",");
+ 
+-		if (sort_key->field_idx == HITCOUNT_IDX)
++		if (idx == HITCOUNT_IDX)
+ 			seq_puts(m, "hitcount");
+-		else {
+-			unsigned int idx = sort_key->field_idx;
+-
+-			if (WARN_ON(idx >= TRACING_MAP_FIELDS_MAX))
+-				return -EINVAL;
+-
++		else
+ 			hist_field_print(m, hist_data->fields[idx]);
+-		}
+ 
+ 		if (sort_key->descending)
+ 			seq_puts(m, ".descending");
+ 	}
+-
+ 	seq_printf(m, ":size=%u", (1 << hist_data->map->map_bits));
+ 
+ 	if (data->filter_str)
+@@ -1454,6 +1486,10 @@ static bool hist_trigger_match(struct event_trigger_data *data,
+ 			return false;
+ 		if (key_field->offset != key_field_test->offset)
+ 			return false;
++		if (key_field->size != key_field_test->size)
++			return false;
++		if (key_field->is_signed != key_field_test->is_signed)
++			return false;
+ 	}
+ 
+ 	for (i = 0; i < hist_data->n_sort_keys; i++) {
+@@ -1536,6 +1572,9 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 
+ 	update_cond_flag(file);
+ 
++	if (hist_data->enable_timestamps)
++		tracing_set_time_stamp_abs(file->tr, true);
++
+ 	if (trace_event_trigger_enable_disable(file, 1) < 0) {
+ 		list_del_rcu(&data->list);
+ 		update_cond_flag(file);
+@@ -1570,17 +1609,26 @@ static void hist_unregister_trigger(char *glob, struct event_trigger_ops *ops,
+ 
+ 	if (unregistered && test->ops->free)
+ 		test->ops->free(test->ops, test);
++
++	if (hist_data->enable_timestamps) {
++		if (unregistered)
++			tracing_set_time_stamp_abs(file->tr, false);
++	}
+ }
+ 
+ static void hist_unreg_all(struct trace_event_file *file)
+ {
+ 	struct event_trigger_data *test, *n;
++	struct hist_trigger_data *hist_data;
+ 
+ 	list_for_each_entry_safe(test, n, &file->triggers, list) {
+ 		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			hist_data = test->private_data;
+ 			list_del_rcu(&test->list);
+ 			trace_event_trigger_enable_disable(file, 0);
+ 			update_cond_flag(file);
++			if (hist_data->enable_timestamps)
++				tracing_set_time_stamp_abs(file->tr, false);
+ 			if (test->ops->free)
+ 				test->ops->free(test->ops, test);
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/1756-tracing-Add-hist_data-member-to-hist_field.patch b/patches/1756-tracing-Add-hist_data-member-to-hist_field.patch
new file mode 100644
index 00000000000000..3b23151331e718
--- /dev/null
+++ b/patches/1756-tracing-Add-hist_data-member-to-hist_field.patch
@@ -0,0 +1,89 @@
+From defffbae522d8faf0748571e0b99fdbebe70dda5 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:47 -0600
+Subject: [PATCH 1756/1795] tracing: Add hist_data member to hist_field
+
+Allow hist_data access via hist_field.  Some users of hist_fields
+require or will require more access to the associated hist_data.
+
+Link: http://lkml.kernel.org/r/d04cd0768f5228ebb4ac0ba4a847bc4d14d4826f.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit b559d003a226911979ceb8469db4c9b621c3bc09)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index a793f8c04830..77ebe6b410ba 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -39,6 +39,7 @@ struct hist_field {
+ 	unsigned int			offset;
+ 	unsigned int                    is_signed;
+ 	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
++	struct hist_trigger_data	*hist_data;
+ };
+ 
+ static u64 hist_field_none(struct hist_field *field, void *event,
+@@ -420,7 +421,8 @@ static void destroy_hist_field(struct hist_field *hist_field,
+ 	kfree(hist_field);
+ }
+ 
+-static struct hist_field *create_hist_field(struct ftrace_event_field *field,
++static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
++					    struct ftrace_event_field *field,
+ 					    unsigned long flags)
+ {
+ 	struct hist_field *hist_field;
+@@ -432,6 +434,8 @@ static struct hist_field *create_hist_field(struct ftrace_event_field *field,
+ 	if (!hist_field)
+ 		return NULL;
+ 
++	hist_field->hist_data = hist_data;
++
+ 	if (flags & HIST_FIELD_FL_HITCOUNT) {
+ 		hist_field->fn = hist_field_counter;
+ 		goto out;
+@@ -445,7 +449,7 @@ static struct hist_field *create_hist_field(struct ftrace_event_field *field,
+ 	if (flags & HIST_FIELD_FL_LOG2) {
+ 		unsigned long fl = flags & ~HIST_FIELD_FL_LOG2;
+ 		hist_field->fn = hist_field_log2;
+-		hist_field->operands[0] = create_hist_field(field, fl);
++		hist_field->operands[0] = create_hist_field(hist_data, field, fl);
+ 		hist_field->size = hist_field->operands[0]->size;
+ 		goto out;
+ 	}
+@@ -498,7 +502,7 @@ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ {
+ 	hist_data->fields[HITCOUNT_IDX] =
+-		create_hist_field(NULL, HIST_FIELD_FL_HITCOUNT);
++		create_hist_field(hist_data, NULL, HIST_FIELD_FL_HITCOUNT);
+ 	if (!hist_data->fields[HITCOUNT_IDX])
+ 		return -ENOMEM;
+ 
+@@ -544,7 +548,7 @@ static int create_val_field(struct hist_trigger_data *hist_data,
+ 		}
+ 	}
+ 
+-	hist_data->fields[val_idx] = create_hist_field(field, flags);
++	hist_data->fields[val_idx] = create_hist_field(hist_data, field, flags);
+ 	if (!hist_data->fields[val_idx]) {
+ 		ret = -ENOMEM;
+ 		goto out;
+@@ -654,7 +658,7 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 		}
+ 	}
+ 
+-	hist_data->fields[key_idx] = create_hist_field(field, flags);
++	hist_data->fields[key_idx] = create_hist_field(hist_data, field, flags);
+ 	if (!hist_data->fields[key_idx]) {
+ 		ret = -ENOMEM;
+ 		goto out;
+-- 
+2.19.0
+
diff --git a/patches/1757-tracing-Move-hist-trigger-Documentation-to-histogram.patch b/patches/1757-tracing-Move-hist-trigger-Documentation-to-histogram.patch
new file mode 100644
index 00000000000000..be6a67c92e1771
--- /dev/null
+++ b/patches/1757-tracing-Move-hist-trigger-Documentation-to-histogram.patch
@@ -0,0 +1,3155 @@
+From ed385b9608bf268a570bad75dc4070b403a22b32 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:35 -0600
+Subject: [PATCH 1757/1795] tracing: Move hist trigger Documentation to
+ histogram.txt
+
+The hist trigger Documentation takes up a large part of events.txt -
+since it will be getting even larger, move it to a separate file.
+
+Link: http://lkml.kernel.org/r/92761155ea4f529e590821b1e02207fe8619f248.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit b8df4a3634e08ad5fcba248c67941bac3b167ef3)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/events.txt    | 1548 +---------------------------
+ Documentation/trace/histogram.txt | 1568 +++++++++++++++++++++++++++++
+ 2 files changed, 1569 insertions(+), 1547 deletions(-)
+ create mode 100644 Documentation/trace/histogram.txt
+
+diff --git a/Documentation/trace/events.txt b/Documentation/trace/events.txt
+index 2cc08d4a326e..e28f7f29f2b3 100644
+--- a/Documentation/trace/events.txt
++++ b/Documentation/trace/events.txt
+@@ -517,1550 +517,4 @@ The following commands are supported:
+   totals derived from one or more trace event format fields and/or
+   event counts (hitcount).
+ 
+-  The format of a hist trigger is as follows:
+-
+-        hist:keys=<field1[,field2,...]>[:values=<field1[,field2,...]>]
+-          [:sort=<field1[,field2,...]>][:size=#entries][:pause][:continue]
+-          [:clear][:name=histname1] [if <filter>]
+-
+-  When a matching event is hit, an entry is added to a hash table
+-  using the key(s) and value(s) named.  Keys and values correspond to
+-  fields in the event's format description.  Values must correspond to
+-  numeric fields - on an event hit, the value(s) will be added to a
+-  sum kept for that field.  The special string 'hitcount' can be used
+-  in place of an explicit value field - this is simply a count of
+-  event hits.  If 'values' isn't specified, an implicit 'hitcount'
+-  value will be automatically created and used as the only value.
+-  Keys can be any field, or the special string 'stacktrace', which
+-  will use the event's kernel stacktrace as the key.  The keywords
+-  'keys' or 'key' can be used to specify keys, and the keywords
+-  'values', 'vals', or 'val' can be used to specify values.  Compound
+-  keys consisting of up to two fields can be specified by the 'keys'
+-  keyword.  Hashing a compound key produces a unique entry in the
+-  table for each unique combination of component keys, and can be
+-  useful for providing more fine-grained summaries of event data.
+-  Additionally, sort keys consisting of up to two fields can be
+-  specified by the 'sort' keyword.  If more than one field is
+-  specified, the result will be a 'sort within a sort': the first key
+-  is taken to be the primary sort key and the second the secondary
+-  key.  If a hist trigger is given a name using the 'name' parameter,
+-  its histogram data will be shared with other triggers of the same
+-  name, and trigger hits will update this common data.  Only triggers
+-  with 'compatible' fields can be combined in this way; triggers are
+-  'compatible' if the fields named in the trigger share the same
+-  number and type of fields and those fields also have the same names.
+-  Note that any two events always share the compatible 'hitcount' and
+-  'stacktrace' fields and can therefore be combined using those
+-  fields, however pointless that may be.
+-
+-  'hist' triggers add a 'hist' file to each event's subdirectory.
+-  Reading the 'hist' file for the event will dump the hash table in
+-  its entirety to stdout.  If there are multiple hist triggers
+-  attached to an event, there will be a table for each trigger in the
+-  output.  The table displayed for a named trigger will be the same as
+-  any other instance having the same name. Each printed hash table
+-  entry is a simple list of the keys and values comprising the entry;
+-  keys are printed first and are delineated by curly braces, and are
+-  followed by the set of value fields for the entry.  By default,
+-  numeric fields are displayed as base-10 integers.  This can be
+-  modified by appending any of the following modifiers to the field
+-  name:
+-
+-        .hex        display a number as a hex value
+-	.sym        display an address as a symbol
+-	.sym-offset display an address as a symbol and offset
+-	.syscall    display a syscall id as a system call name
+-	.execname   display a common_pid as a program name
+-
+-  Note that in general the semantics of a given field aren't
+-  interpreted when applying a modifier to it, but there are some
+-  restrictions to be aware of in this regard:
+-
+-    - only the 'hex' modifier can be used for values (because values
+-      are essentially sums, and the other modifiers don't make sense
+-      in that context).
+-    - the 'execname' modifier can only be used on a 'common_pid'.  The
+-      reason for this is that the execname is simply the 'comm' value
+-      saved for the 'current' process when an event was triggered,
+-      which is the same as the common_pid value saved by the event
+-      tracing code.  Trying to apply that comm value to other pid
+-      values wouldn't be correct, and typically events that care save
+-      pid-specific comm fields in the event itself.
+-
+-  A typical usage scenario would be the following to enable a hist
+-  trigger, read its current contents, and then turn it off:
+-
+-  # echo 'hist:keys=skbaddr.hex:vals=len' > \
+-    /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+-
+-  # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+-
+-  # echo '!hist:keys=skbaddr.hex:vals=len' > \
+-    /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+-
+-  The trigger file itself can be read to show the details of the
+-  currently attached hist trigger.  This information is also displayed
+-  at the top of the 'hist' file when read.
+-
+-  By default, the size of the hash table is 2048 entries.  The 'size'
+-  parameter can be used to specify more or fewer than that.  The units
+-  are in terms of hashtable entries - if a run uses more entries than
+-  specified, the results will show the number of 'drops', the number
+-  of hits that were ignored.  The size should be a power of 2 between
+-  128 and 131072 (any non- power-of-2 number specified will be rounded
+-  up).
+-
+-  The 'sort' parameter can be used to specify a value field to sort
+-  on.  The default if unspecified is 'hitcount' and the default sort
+-  order is 'ascending'.  To sort in the opposite direction, append
+-  .descending' to the sort key.
+-
+-  The 'pause' parameter can be used to pause an existing hist trigger
+-  or to start a hist trigger but not log any events until told to do
+-  so.  'continue' or 'cont' can be used to start or restart a paused
+-  hist trigger.
+-
+-  The 'clear' parameter will clear the contents of a running hist
+-  trigger and leave its current paused/active state.
+-
+-  Note that the 'pause', 'cont', and 'clear' parameters should be
+-  applied using 'append' shell operator ('>>') if applied to an
+-  existing trigger, rather than via the '>' operator, which will cause
+-  the trigger to be removed through truncation.
+-
+-- enable_hist/disable_hist
+-
+-  The enable_hist and disable_hist triggers can be used to have one
+-  event conditionally start and stop another event's already-attached
+-  hist trigger.  Any number of enable_hist and disable_hist triggers
+-  can be attached to a given event, allowing that event to kick off
+-  and stop aggregations on a host of other events.
+-
+-  The format is very similar to the enable/disable_event triggers:
+-
+-      enable_hist:<system>:<event>[:count]
+-      disable_hist:<system>:<event>[:count]
+-
+-  Instead of enabling or disabling the tracing of the target event
+-  into the trace buffer as the enable/disable_event triggers do, the
+-  enable/disable_hist triggers enable or disable the aggregation of
+-  the target event into a hash table.
+-
+-  A typical usage scenario for the enable_hist/disable_hist triggers
+-  would be to first set up a paused hist trigger on some event,
+-  followed by an enable_hist/disable_hist pair that turns the hist
+-  aggregation on and off when conditions of interest are hit:
+-
+-  # echo 'hist:keys=skbaddr.hex:vals=len:pause' > \
+-    /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-
+-  # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
+-    /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+-
+-  # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
+-    /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+-
+-  The above sets up an initially paused hist trigger which is unpaused
+-  and starts aggregating events when a given program is executed, and
+-  which stops aggregating when the process exits and the hist trigger
+-  is paused again.
+-
+-  The examples below provide a more concrete illustration of the
+-  concepts and typical usage patterns discussed above.
+-
+-
+-6.2 'hist' trigger examples
+----------------------------
+-
+-  The first set of examples creates aggregations using the kmalloc
+-  event.  The fields that can be used for the hist trigger are listed
+-  in the kmalloc event's format file:
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/format
+-    name: kmalloc
+-    ID: 374
+-    format:
+-	field:unsigned short common_type;	offset:0;	size:2;	signed:0;
+-	field:unsigned char common_flags;	offset:2;	size:1;	signed:0;
+-	field:unsigned char common_preempt_count;		offset:3;	size:1;	signed:0;
+-	field:int common_pid;					offset:4;	size:4;	signed:1;
+-
+-	field:unsigned long call_site;				offset:8;	size:8;	signed:0;
+-	field:const void * ptr;					offset:16;	size:8;	signed:0;
+-	field:size_t bytes_req;					offset:24;	size:8;	signed:0;
+-	field:size_t bytes_alloc;				offset:32;	size:8;	signed:0;
+-	field:gfp_t gfp_flags;					offset:40;	size:4;	signed:0;
+-
+-  We'll start by creating a hist trigger that generates a simple table
+-  that lists the total number of bytes requested for each function in
+-  the kernel that made one or more calls to kmalloc:
+-
+-    # echo 'hist:key=call_site:val=bytes_req' > \
+-            /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-  This tells the tracing system to create a 'hist' trigger using the
+-  call_site field of the kmalloc event as the key for the table, which
+-  just means that each unique call_site address will have an entry
+-  created for it in the table.  The 'val=bytes_req' parameter tells
+-  the hist trigger that for each unique entry (call_site) in the
+-  table, it should keep a running total of the number of bytes
+-  requested by that call_site.
+-
+-  We'll let it run for awhile and then dump the contents of the 'hist'
+-  file in the kmalloc event's subdirectory (for readability, a number
+-  of entries have been omitted):
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
+-
+-    { call_site: 18446744072106379007 } hitcount:          1  bytes_req:        176
+-    { call_site: 18446744071579557049 } hitcount:          1  bytes_req:       1024
+-    { call_site: 18446744071580608289 } hitcount:          1  bytes_req:      16384
+-    { call_site: 18446744071581827654 } hitcount:          1  bytes_req:         24
+-    { call_site: 18446744071580700980 } hitcount:          1  bytes_req:          8
+-    { call_site: 18446744071579359876 } hitcount:          1  bytes_req:        152
+-    { call_site: 18446744071580795365 } hitcount:          3  bytes_req:        144
+-    { call_site: 18446744071581303129 } hitcount:          3  bytes_req:        144
+-    { call_site: 18446744071580713234 } hitcount:          4  bytes_req:       2560
+-    { call_site: 18446744071580933750 } hitcount:          4  bytes_req:        736
+-    .
+-    .
+-    .
+-    { call_site: 18446744072106047046 } hitcount:         69  bytes_req:       5576
+-    { call_site: 18446744071582116407 } hitcount:         73  bytes_req:       2336
+-    { call_site: 18446744072106054684 } hitcount:        136  bytes_req:     140504
+-    { call_site: 18446744072106224230 } hitcount:        136  bytes_req:      19584
+-    { call_site: 18446744072106078074 } hitcount:        153  bytes_req:       2448
+-    { call_site: 18446744072106062406 } hitcount:        153  bytes_req:      36720
+-    { call_site: 18446744071582507929 } hitcount:        153  bytes_req:      37088
+-    { call_site: 18446744072102520590 } hitcount:        273  bytes_req:      10920
+-    { call_site: 18446744071582143559 } hitcount:        358  bytes_req:        716
+-    { call_site: 18446744072106465852 } hitcount:        417  bytes_req:      56712
+-    { call_site: 18446744072102523378 } hitcount:        485  bytes_req:      27160
+-    { call_site: 18446744072099568646 } hitcount:       1676  bytes_req:      33520
+-
+-    Totals:
+-        Hits: 4610
+-        Entries: 45
+-        Dropped: 0
+-
+-  The output displays a line for each entry, beginning with the key
+-  specified in the trigger, followed by the value(s) also specified in
+-  the trigger.  At the beginning of the output is a line that displays
+-  the trigger info, which can also be displayed by reading the
+-  'trigger' file:
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-    hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
+-
+-  At the end of the output are a few lines that display the overall
+-  totals for the run.  The 'Hits' field shows the total number of
+-  times the event trigger was hit, the 'Entries' field shows the total
+-  number of used entries in the hash table, and the 'Dropped' field
+-  shows the number of hits that were dropped because the number of
+-  used entries for the run exceeded the maximum number of entries
+-  allowed for the table (normally 0, but if not a hint that you may
+-  want to increase the size of the table using the 'size' parameter).
+-
+-  Notice in the above output that there's an extra field, 'hitcount',
+-  which wasn't specified in the trigger.  Also notice that in the
+-  trigger info output, there's a parameter, 'sort=hitcount', which
+-  wasn't specified in the trigger either.  The reason for that is that
+-  every trigger implicitly keeps a count of the total number of hits
+-  attributed to a given entry, called the 'hitcount'.  That hitcount
+-  information is explicitly displayed in the output, and in the
+-  absence of a user-specified sort parameter, is used as the default
+-  sort field.
+-
+-  The value 'hitcount' can be used in place of an explicit value in
+-  the 'values' parameter if you don't really need to have any
+-  particular field summed and are mainly interested in hit
+-  frequencies.
+-
+-  To turn the hist trigger off, simply call up the trigger in the
+-  command history and re-execute it with a '!' prepended:
+-
+-    # echo '!hist:key=call_site:val=bytes_req' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-  Finally, notice that the call_site as displayed in the output above
+-  isn't really very useful.  It's an address, but normally addresses
+-  are displayed in hex.  To have a numeric field displayed as a hex
+-  value, simply append '.hex' to the field name in the trigger:
+-
+-    # echo 'hist:key=call_site.hex:val=bytes_req' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site.hex:vals=bytes_req:sort=hitcount:size=2048 [active]
+-
+-    { call_site: ffffffffa026b291 } hitcount:          1  bytes_req:        433
+-    { call_site: ffffffffa07186ff } hitcount:          1  bytes_req:        176
+-    { call_site: ffffffff811ae721 } hitcount:          1  bytes_req:      16384
+-    { call_site: ffffffff811c5134 } hitcount:          1  bytes_req:          8
+-    { call_site: ffffffffa04a9ebb } hitcount:          1  bytes_req:        511
+-    { call_site: ffffffff8122e0a6 } hitcount:          1  bytes_req:         12
+-    { call_site: ffffffff8107da84 } hitcount:          1  bytes_req:        152
+-    { call_site: ffffffff812d8246 } hitcount:          1  bytes_req:         24
+-    { call_site: ffffffff811dc1e5 } hitcount:          3  bytes_req:        144
+-    { call_site: ffffffffa02515e8 } hitcount:          3  bytes_req:        648
+-    { call_site: ffffffff81258159 } hitcount:          3  bytes_req:        144
+-    { call_site: ffffffff811c80f4 } hitcount:          4  bytes_req:        544
+-    .
+-    .
+-    .
+-    { call_site: ffffffffa06c7646 } hitcount:        106  bytes_req:       8024
+-    { call_site: ffffffffa06cb246 } hitcount:        132  bytes_req:      31680
+-    { call_site: ffffffffa06cef7a } hitcount:        132  bytes_req:       2112
+-    { call_site: ffffffff8137e399 } hitcount:        132  bytes_req:      23232
+-    { call_site: ffffffffa06c941c } hitcount:        185  bytes_req:     171360
+-    { call_site: ffffffffa06f2a66 } hitcount:        185  bytes_req:      26640
+-    { call_site: ffffffffa036a70e } hitcount:        265  bytes_req:      10600
+-    { call_site: ffffffff81325447 } hitcount:        292  bytes_req:        584
+-    { call_site: ffffffffa072da3c } hitcount:        446  bytes_req:      60656
+-    { call_site: ffffffffa036b1f2 } hitcount:        526  bytes_req:      29456
+-    { call_site: ffffffffa0099c06 } hitcount:       1780  bytes_req:      35600
+-
+-    Totals:
+-        Hits: 4775
+-        Entries: 46
+-        Dropped: 0
+-
+-  Even that's only marginally more useful - while hex values do look
+-  more like addresses, what users are typically more interested in
+-  when looking at text addresses are the corresponding symbols
+-  instead.  To have an address displayed as symbolic value instead,
+-  simply append '.sym' or '.sym-offset' to the field name in the
+-  trigger:
+-
+-    # echo 'hist:key=call_site.sym:val=bytes_req' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=hitcount:size=2048 [active]
+-
+-    { call_site: [ffffffff810adcb9] syslog_print_all                              } hitcount:          1  bytes_req:       1024
+-    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8
+-    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7
+-    { call_site: [ffffffff8154acbe] usb_alloc_urb                                 } hitcount:          1  bytes_req:        192
+-    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7
+-    { call_site: [ffffffff811e3a25] __seq_open_private                            } hitcount:          1  bytes_req:         40
+-    { call_site: [ffffffff8109524a] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128
+-    { call_site: [ffffffff811febd5] fsnotify_alloc_group                          } hitcount:          2  bytes_req:        528
+-    { call_site: [ffffffff81440f58] __tty_buffer_request_room                     } hitcount:          2  bytes_req:       2624
+-    { call_site: [ffffffff81200ba6] inotify_new_group                             } hitcount:          2  bytes_req:         96
+-    { call_site: [ffffffffa05e19af] ieee80211_start_tx_ba_session [mac80211]      } hitcount:          2  bytes_req:        464
+-    { call_site: [ffffffff81672406] tcp_get_metrics                               } hitcount:          2  bytes_req:        304
+-    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128
+-    { call_site: [ffffffff81089b05] sched_create_group                            } hitcount:          2  bytes_req:       1424
+-    .
+-    .
+-    .
+-    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:       1185  bytes_req:     123240
+-    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm]                } hitcount:       1185  bytes_req:     104280
+-    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:       1402  bytes_req:     190672
+-    { call_site: [ffffffff812891ca] ext4_find_extent                              } hitcount:       1518  bytes_req:     146208
+-    { call_site: [ffffffffa029070e] drm_vma_node_allow [drm]                      } hitcount:       1746  bytes_req:      69840
+-    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       2021  bytes_req:     792312
+-    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       2592  bytes_req:     145152
+-    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       2629  bytes_req:     378576
+-    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       2629  bytes_req:    3783248
+-    { call_site: [ffffffff81325607] apparmor_file_alloc_security                  } hitcount:       5192  bytes_req:      10384
+-    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       5529  bytes_req:     110584
+-    { call_site: [ffffffff8131ebf7] aa_alloc_task_context                         } hitcount:      21943  bytes_req:     702176
+-    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:      55759  bytes_req:    5074265
+-
+-    Totals:
+-        Hits: 109928
+-        Entries: 71
+-        Dropped: 0
+-
+-  Because the default sort key above is 'hitcount', the above shows a
+-  the list of call_sites by increasing hitcount, so that at the bottom
+-  we see the functions that made the most kmalloc calls during the
+-  run.  If instead we we wanted to see the top kmalloc callers in
+-  terms of the number of bytes requested rather than the number of
+-  calls, and we wanted the top caller to appear at the top, we can use
+-  the 'sort' parameter, along with the 'descending' modifier:
+-
+-    # echo 'hist:key=call_site.sym:val=bytes_req:sort=bytes_req.descending' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
+-
+-    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       2186  bytes_req:    3397464
+-    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       1790  bytes_req:     712176
+-    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:       8132  bytes_req:     513135
+-    { call_site: [ffffffff811e2a1b] seq_buf_alloc                                 } hitcount:        106  bytes_req:     440128
+-    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       2186  bytes_req:     314784
+-    { call_site: [ffffffff812891ca] ext4_find_extent                              } hitcount:       2174  bytes_req:     208992
+-    { call_site: [ffffffff811ae8e1] __kmalloc                                     } hitcount:          8  bytes_req:     131072
+-    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:        859  bytes_req:     116824
+-    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       1834  bytes_req:     102704
+-    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:        972  bytes_req:     101088
+-    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm]                } hitcount:        972  bytes_req:      85536
+-    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       3333  bytes_req:      66664
+-    { call_site: [ffffffff8137e559] sg_kmalloc                                    } hitcount:        209  bytes_req:      61632
+-    .
+-    .
+-    .
+-    { call_site: [ffffffff81095225] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128
+-    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128
+-    { call_site: [ffffffff812d8406] copy_semundo                                  } hitcount:          2  bytes_req:         48
+-    { call_site: [ffffffff81200ba6] inotify_new_group                             } hitcount:          1  bytes_req:         48
+-    { call_site: [ffffffffa027121a] drm_getmagic [drm]                            } hitcount:          1  bytes_req:         48
+-    { call_site: [ffffffff811e3a25] __seq_open_private                            } hitcount:          1  bytes_req:         40
+-    { call_site: [ffffffff811c52f4] bprm_change_interp                            } hitcount:          2  bytes_req:         16
+-    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8
+-    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7
+-    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7
+-
+-    Totals:
+-        Hits: 32133
+-        Entries: 81
+-        Dropped: 0
+-
+-  To display the offset and size information in addition to the symbol
+-  name, just use 'sym-offset' instead:
+-
+-    # echo 'hist:key=call_site.sym-offset:val=bytes_req:sort=bytes_req.descending' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site.sym-offset:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
+-
+-    { call_site: [ffffffffa046041c] i915_gem_execbuffer2+0x6c/0x2c0 [i915]                  } hitcount:       4569  bytes_req:    3163720
+-    { call_site: [ffffffffa0489a66] intel_ring_begin+0xc6/0x1f0 [i915]                      } hitcount:       4569  bytes_req:     657936
+-    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23+0x694/0x1020 [i915]      } hitcount:       1519  bytes_req:     472936
+-    { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23+0x516/0x1020 [i915]      } hitcount:       3050  bytes_req:     211832
+-    { call_site: [ffffffff811e2a1b] seq_buf_alloc+0x1b/0x50                                 } hitcount:         34  bytes_req:     148384
+-    { call_site: [ffffffffa04a580c] intel_crtc_page_flip+0xbc/0x870 [i915]                  } hitcount:       1385  bytes_req:     144040
+-    { call_site: [ffffffff811ae8e1] __kmalloc+0x191/0x1b0                                   } hitcount:          8  bytes_req:     131072
+-    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl+0x282/0x360 [drm]              } hitcount:       1385  bytes_req:     121880
+-    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc+0x32/0x100 [drm]                  } hitcount:       1848  bytes_req:     103488
+-    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state+0x2c/0xa0 [i915]            } hitcount:        461  bytes_req:      62696
+-    { call_site: [ffffffffa029070e] drm_vma_node_allow+0x2e/0xd0 [drm]                      } hitcount:       1541  bytes_req:      61640
+-    { call_site: [ffffffff815f8d7b] sk_prot_alloc+0xcb/0x1b0                                } hitcount:         57  bytes_req:      57456
+-    .
+-    .
+-    .
+-    { call_site: [ffffffff8109524a] alloc_fair_sched_group+0x5a/0x1a0                       } hitcount:          2  bytes_req:        128
+-    { call_site: [ffffffffa027b921] drm_vm_open_locked+0x31/0xa0 [drm]                      } hitcount:          3  bytes_req:         96
+-    { call_site: [ffffffff8122e266] proc_self_follow_link+0x76/0xb0                         } hitcount:          8  bytes_req:         96
+-    { call_site: [ffffffff81213e80] load_elf_binary+0x240/0x1650                            } hitcount:          3  bytes_req:         84
+-    { call_site: [ffffffff8154bc62] usb_control_msg+0x42/0x110                              } hitcount:          1  bytes_req:          8
+-    { call_site: [ffffffffa00bf6fe] hidraw_send_report+0x7e/0x1a0 [hid]                     } hitcount:          1  bytes_req:          7
+-    { call_site: [ffffffffa00bf1ca] hidraw_report_event+0x8a/0x120 [hid]                    } hitcount:          1  bytes_req:          7
+-
+-    Totals:
+-        Hits: 26098
+-        Entries: 64
+-        Dropped: 0
+-
+-  We can also add multiple fields to the 'values' parameter.  For
+-  example, we might want to see the total number of bytes allocated
+-  alongside bytes requested, and display the result sorted by bytes
+-  allocated in a descending order:
+-
+-    # echo 'hist:keys=call_site.sym:values=bytes_req,bytes_alloc:sort=bytes_alloc.descending' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=call_site.sym:vals=bytes_req,bytes_alloc:sort=bytes_alloc.descending:size=2048 [active]
+-
+-    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       7403  bytes_req:    4084360  bytes_alloc:    5958016
+-    { call_site: [ffffffff811e2a1b] seq_buf_alloc                                 } hitcount:        541  bytes_req:    2213968  bytes_alloc:    2228224
+-    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       7404  bytes_req:    1066176  bytes_alloc:    1421568
+-    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       1565  bytes_req:     557368  bytes_alloc:    1037760
+-    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:       9557  bytes_req:     595778  bytes_alloc:     695744
+-    { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       5839  bytes_req:     430680  bytes_alloc:     470400
+-    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:       2388  bytes_req:     324768  bytes_alloc:     458496
+-    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       3911  bytes_req:     219016  bytes_alloc:     250304
+-    { call_site: [ffffffff815f8d7b] sk_prot_alloc                                 } hitcount:        235  bytes_req:     236880  bytes_alloc:     240640
+-    { call_site: [ffffffff8137e559] sg_kmalloc                                    } hitcount:        557  bytes_req:     169024  bytes_alloc:     221760
+-    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       9378  bytes_req:     187548  bytes_alloc:     206312
+-    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:       1519  bytes_req:     157976  bytes_alloc:     194432
+-    .
+-    .
+-    .
+-    { call_site: [ffffffff8109bd3b] sched_autogroup_create_attach                 } hitcount:          2  bytes_req:        144  bytes_alloc:        192
+-    { call_site: [ffffffff81097ee8] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128  bytes_alloc:        128
+-    { call_site: [ffffffff8109524a] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128  bytes_alloc:        128
+-    { call_site: [ffffffff81095225] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128  bytes_alloc:        128
+-    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128  bytes_alloc:        128
+-    { call_site: [ffffffff81213e80] load_elf_binary                               } hitcount:          3  bytes_req:         84  bytes_alloc:         96
+-    { call_site: [ffffffff81079a2e] kthread_create_on_node                        } hitcount:          1  bytes_req:         56  bytes_alloc:         64
+-    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7  bytes_alloc:          8
+-    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8  bytes_alloc:          8
+-    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7  bytes_alloc:          8
+-
+-    Totals:
+-        Hits: 66598
+-        Entries: 65
+-        Dropped: 0
+-
+-  Finally, to finish off our kmalloc example, instead of simply having
+-  the hist trigger display symbolic call_sites, we can have the hist
+-  trigger additionally display the complete set of kernel stack traces
+-  that led to each call_site.  To do that, we simply use the special
+-  value 'stacktrace' for the key parameter:
+-
+-    # echo 'hist:keys=stacktrace:values=bytes_req,bytes_alloc:sort=bytes_alloc' > \
+-           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+-
+-  The above trigger will use the kernel stack trace in effect when an
+-  event is triggered as the key for the hash table.  This allows the
+-  enumeration of every kernel callpath that led up to a particular
+-  event, along with a running total of any of the event fields for
+-  that event.  Here we tally bytes requested and bytes allocated for
+-  every callpath in the system that led up to a kmalloc (in this case
+-  every callpath to a kmalloc for a kernel compile):
+-
+-    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+-    # trigger info: hist:keys=stacktrace:vals=bytes_req,bytes_alloc:sort=bytes_alloc:size=2048 [active]
+-
+-    { stacktrace:
+-         __kmalloc_track_caller+0x10b/0x1a0
+-         kmemdup+0x20/0x50
+-         hidraw_report_event+0x8a/0x120 [hid]
+-         hid_report_raw_event+0x3ea/0x440 [hid]
+-         hid_input_report+0x112/0x190 [hid]
+-         hid_irq_in+0xc2/0x260 [usbhid]
+-         __usb_hcd_giveback_urb+0x72/0x120
+-         usb_giveback_urb_bh+0x9e/0xe0
+-         tasklet_hi_action+0xf8/0x100
+-         __do_softirq+0x114/0x2c0
+-         irq_exit+0xa5/0xb0
+-         do_IRQ+0x5a/0xf0
+-         ret_from_intr+0x0/0x30
+-         cpuidle_enter+0x17/0x20
+-         cpu_startup_entry+0x315/0x3e0
+-         rest_init+0x7c/0x80
+-    } hitcount:          3  bytes_req:         21  bytes_alloc:         24
+-    { stacktrace:
+-         __kmalloc_track_caller+0x10b/0x1a0
+-         kmemdup+0x20/0x50
+-         hidraw_report_event+0x8a/0x120 [hid]
+-         hid_report_raw_event+0x3ea/0x440 [hid]
+-         hid_input_report+0x112/0x190 [hid]
+-         hid_irq_in+0xc2/0x260 [usbhid]
+-         __usb_hcd_giveback_urb+0x72/0x120
+-         usb_giveback_urb_bh+0x9e/0xe0
+-         tasklet_hi_action+0xf8/0x100
+-         __do_softirq+0x114/0x2c0
+-         irq_exit+0xa5/0xb0
+-         do_IRQ+0x5a/0xf0
+-         ret_from_intr+0x0/0x30
+-    } hitcount:          3  bytes_req:         21  bytes_alloc:         24
+-    { stacktrace:
+-         kmem_cache_alloc_trace+0xeb/0x150
+-         aa_alloc_task_context+0x27/0x40
+-         apparmor_cred_prepare+0x1f/0x50
+-         security_prepare_creds+0x16/0x20
+-         prepare_creds+0xdf/0x1a0
+-         SyS_capset+0xb5/0x200
+-         system_call_fastpath+0x12/0x6a
+-    } hitcount:          1  bytes_req:         32  bytes_alloc:         32
+-    .
+-    .
+-    .
+-    { stacktrace:
+-         __kmalloc+0x11b/0x1b0
+-         i915_gem_execbuffer2+0x6c/0x2c0 [i915]
+-         drm_ioctl+0x349/0x670 [drm]
+-         do_vfs_ioctl+0x2f0/0x4f0
+-         SyS_ioctl+0x81/0xa0
+-         system_call_fastpath+0x12/0x6a
+-    } hitcount:      17726  bytes_req:   13944120  bytes_alloc:   19593808
+-    { stacktrace:
+-         __kmalloc+0x11b/0x1b0
+-         load_elf_phdrs+0x76/0xa0
+-         load_elf_binary+0x102/0x1650
+-         search_binary_handler+0x97/0x1d0
+-         do_execveat_common.isra.34+0x551/0x6e0
+-         SyS_execve+0x3a/0x50
+-         return_from_execve+0x0/0x23
+-    } hitcount:      33348  bytes_req:   17152128  bytes_alloc:   20226048
+-    { stacktrace:
+-         kmem_cache_alloc_trace+0xeb/0x150
+-         apparmor_file_alloc_security+0x27/0x40
+-         security_file_alloc+0x16/0x20
+-         get_empty_filp+0x93/0x1c0
+-         path_openat+0x31/0x5f0
+-         do_filp_open+0x3a/0x90
+-         do_sys_open+0x128/0x220
+-         SyS_open+0x1e/0x20
+-         system_call_fastpath+0x12/0x6a
+-    } hitcount:    4766422  bytes_req:    9532844  bytes_alloc:   38131376
+-    { stacktrace:
+-         __kmalloc+0x11b/0x1b0
+-         seq_buf_alloc+0x1b/0x50
+-         seq_read+0x2cc/0x370
+-         proc_reg_read+0x3d/0x80
+-         __vfs_read+0x28/0xe0
+-         vfs_read+0x86/0x140
+-         SyS_read+0x46/0xb0
+-         system_call_fastpath+0x12/0x6a
+-    } hitcount:      19133  bytes_req:   78368768  bytes_alloc:   78368768
+-
+-    Totals:
+-        Hits: 6085872
+-        Entries: 253
+-        Dropped: 0
+-
+-  If you key a hist trigger on common_pid, in order for example to
+-  gather and display sorted totals for each process, you can use the
+-  special .execname modifier to display the executable names for the
+-  processes in the table rather than raw pids.  The example below
+-  keeps a per-process sum of total bytes read:
+-
+-    # echo 'hist:key=common_pid.execname:val=count:sort=count.descending' > \
+-           /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/hist
+-    # trigger info: hist:keys=common_pid.execname:vals=count:sort=count.descending:size=2048 [active]
+-
+-    { common_pid: gnome-terminal  [      3196] } hitcount:        280  count:    1093512
+-    { common_pid: Xorg            [      1309] } hitcount:        525  count:     256640
+-    { common_pid: compiz          [      2889] } hitcount:         59  count:     254400
+-    { common_pid: bash            [      8710] } hitcount:          3  count:      66369
+-    { common_pid: dbus-daemon-lau [      8703] } hitcount:         49  count:      47739
+-    { common_pid: irqbalance      [      1252] } hitcount:         27  count:      27648
+-    { common_pid: 01ifupdown      [      8705] } hitcount:          3  count:      17216
+-    { common_pid: dbus-daemon     [       772] } hitcount:         10  count:      12396
+-    { common_pid: Socket Thread   [      8342] } hitcount:         11  count:      11264
+-    { common_pid: nm-dhcp-client. [      8701] } hitcount:          6  count:       7424
+-    { common_pid: gmain           [      1315] } hitcount:         18  count:       6336
+-    .
+-    .
+-    .
+-    { common_pid: postgres        [      1892] } hitcount:          2  count:         32
+-    { common_pid: postgres        [      1891] } hitcount:          2  count:         32
+-    { common_pid: gmain           [      8704] } hitcount:          2  count:         32
+-    { common_pid: upstart-dbus-br [      2740] } hitcount:         21  count:         21
+-    { common_pid: nm-dispatcher.a [      8696] } hitcount:          1  count:         16
+-    { common_pid: indicator-datet [      2904] } hitcount:          1  count:         16
+-    { common_pid: gdbus           [      2998] } hitcount:          1  count:         16
+-    { common_pid: rtkit-daemon    [      2052] } hitcount:          1  count:          8
+-    { common_pid: init            [         1] } hitcount:          2  count:          2
+-
+-    Totals:
+-        Hits: 2116
+-        Entries: 51
+-        Dropped: 0
+-
+-  Similarly, if you key a hist trigger on syscall id, for example to
+-  gather and display a list of systemwide syscall hits, you can use
+-  the special .syscall modifier to display the syscall names rather
+-  than raw ids.  The example below keeps a running total of syscall
+-  counts for the system during the run:
+-
+-    # echo 'hist:key=id.syscall:val=hitcount' > \
+-           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+-    # trigger info: hist:keys=id.syscall:vals=hitcount:sort=hitcount:size=2048 [active]
+-
+-    { id: sys_fsync                     [ 74] } hitcount:          1
+-    { id: sys_newuname                  [ 63] } hitcount:          1
+-    { id: sys_prctl                     [157] } hitcount:          1
+-    { id: sys_statfs                    [137] } hitcount:          1
+-    { id: sys_symlink                   [ 88] } hitcount:          1
+-    { id: sys_sendmmsg                  [307] } hitcount:          1
+-    { id: sys_semctl                    [ 66] } hitcount:          1
+-    { id: sys_readlink                  [ 89] } hitcount:          3
+-    { id: sys_bind                      [ 49] } hitcount:          3
+-    { id: sys_getsockname               [ 51] } hitcount:          3
+-    { id: sys_unlink                    [ 87] } hitcount:          3
+-    { id: sys_rename                    [ 82] } hitcount:          4
+-    { id: unknown_syscall               [ 58] } hitcount:          4
+-    { id: sys_connect                   [ 42] } hitcount:          4
+-    { id: sys_getpid                    [ 39] } hitcount:          4
+-    .
+-    .
+-    .
+-    { id: sys_rt_sigprocmask            [ 14] } hitcount:        952
+-    { id: sys_futex                     [202] } hitcount:       1534
+-    { id: sys_write                     [  1] } hitcount:       2689
+-    { id: sys_setitimer                 [ 38] } hitcount:       2797
+-    { id: sys_read                      [  0] } hitcount:       3202
+-    { id: sys_select                    [ 23] } hitcount:       3773
+-    { id: sys_writev                    [ 20] } hitcount:       4531
+-    { id: sys_poll                      [  7] } hitcount:       8314
+-    { id: sys_recvmsg                   [ 47] } hitcount:      13738
+-    { id: sys_ioctl                     [ 16] } hitcount:      21843
+-
+-    Totals:
+-        Hits: 67612
+-        Entries: 72
+-        Dropped: 0
+-
+-    The syscall counts above provide a rough overall picture of system
+-    call activity on the system; we can see for example that the most
+-    popular system call on this system was the 'sys_ioctl' system call.
+-
+-    We can use 'compound' keys to refine that number and provide some
+-    further insight as to which processes exactly contribute to the
+-    overall ioctl count.
+-
+-    The command below keeps a hitcount for every unique combination of
+-    system call id and pid - the end result is essentially a table
+-    that keeps a per-pid sum of system call hits.  The results are
+-    sorted using the system call id as the primary key, and the
+-    hitcount sum as the secondary key:
+-
+-    # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount' > \
+-           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+-    # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 [active]
+-
+-    { id: sys_read                      [  0], common_pid: rtkit-daemon    [      1877] } hitcount:          1
+-    { id: sys_read                      [  0], common_pid: gdbus           [      2976] } hitcount:          1
+-    { id: sys_read                      [  0], common_pid: console-kit-dae [      3400] } hitcount:          1
+-    { id: sys_read                      [  0], common_pid: postgres        [      1865] } hitcount:          1
+-    { id: sys_read                      [  0], common_pid: deja-dup-monito [      3543] } hitcount:          2
+-    { id: sys_read                      [  0], common_pid: NetworkManager  [       890] } hitcount:          2
+-    { id: sys_read                      [  0], common_pid: evolution-calen [      3048] } hitcount:          2
+-    { id: sys_read                      [  0], common_pid: postgres        [      1864] } hitcount:          2
+-    { id: sys_read                      [  0], common_pid: nm-applet       [      3022] } hitcount:          2
+-    { id: sys_read                      [  0], common_pid: whoopsie        [      1212] } hitcount:          2
+-    .
+-    .
+-    .
+-    { id: sys_ioctl                     [ 16], common_pid: bash            [      8479] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: bash            [      3472] } hitcount:         12
+-    { id: sys_ioctl                     [ 16], common_pid: gnome-terminal  [      3199] } hitcount:         16
+-    { id: sys_ioctl                     [ 16], common_pid: Xorg            [      1267] } hitcount:       1808
+-    { id: sys_ioctl                     [ 16], common_pid: compiz          [      2994] } hitcount:       5580
+-    .
+-    .
+-    .
+-    { id: sys_waitid                    [247], common_pid: upstart-dbus-br [      2690] } hitcount:          3
+-    { id: sys_waitid                    [247], common_pid: upstart-dbus-br [      2688] } hitcount:         16
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [       975] } hitcount:          2
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3204] } hitcount:          4
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      2888] } hitcount:          4
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3003] } hitcount:          4
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      2873] } hitcount:          4
+-    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3196] } hitcount:          6
+-    { id: sys_openat                    [257], common_pid: java            [      2623] } hitcount:          2
+-    { id: sys_eventfd2                  [290], common_pid: ibus-ui-gtk3    [      2760] } hitcount:          4
+-    { id: sys_eventfd2                  [290], common_pid: compiz          [      2994] } hitcount:          6
+-
+-    Totals:
+-        Hits: 31536
+-        Entries: 323
+-        Dropped: 0
+-
+-    The above list does give us a breakdown of the ioctl syscall by
+-    pid, but it also gives us quite a bit more than that, which we
+-    don't really care about at the moment.  Since we know the syscall
+-    id for sys_ioctl (16, displayed next to the sys_ioctl name), we
+-    can use that to filter out all the other syscalls:
+-
+-    # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount if id == 16' > \
+-           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+-    # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 if id == 16 [active]
+-
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2769] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: evolution-addre [      8571] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      3003] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2781] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2829] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: bash            [      8726] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: bash            [      8508] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2970] } hitcount:          1
+-    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2768] } hitcount:          1
+-    .
+-    .
+-    .
+-    { id: sys_ioctl                     [ 16], common_pid: pool            [      8559] } hitcount:         45
+-    { id: sys_ioctl                     [ 16], common_pid: pool            [      8555] } hitcount:         48
+-    { id: sys_ioctl                     [ 16], common_pid: pool            [      8551] } hitcount:         48
+-    { id: sys_ioctl                     [ 16], common_pid: avahi-daemon    [       896] } hitcount:         66
+-    { id: sys_ioctl                     [ 16], common_pid: Xorg            [      1267] } hitcount:      26674
+-    { id: sys_ioctl                     [ 16], common_pid: compiz          [      2994] } hitcount:      73443
+-
+-    Totals:
+-        Hits: 101162
+-        Entries: 103
+-        Dropped: 0
+-
+-    The above output shows that 'compiz' and 'Xorg' are far and away
+-    the heaviest ioctl callers (which might lead to questions about
+-    whether they really need to be making all those calls and to
+-    possible avenues for further investigation.)
+-
+-    The compound key examples used a key and a sum value (hitcount) to
+-    sort the output, but we can just as easily use two keys instead.
+-    Here's an example where we use a compound key composed of the the
+-    common_pid and size event fields.  Sorting with pid as the primary
+-    key and 'size' as the secondary key allows us to display an
+-    ordered summary of the recvfrom sizes, with counts, received by
+-    each process:
+-
+-    # echo 'hist:key=common_pid.execname,size:val=hitcount:sort=common_pid,size' > \
+-           /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/hist
+-    # trigger info: hist:keys=common_pid.execname,size:vals=hitcount:sort=common_pid.execname,size:size=2048 [active]
+-
+-    { common_pid: smbd            [       784], size:          4 } hitcount:          1
+-    { common_pid: dnsmasq         [      1412], size:       4096 } hitcount:        672
+-    { common_pid: postgres        [      1796], size:       1000 } hitcount:          6
+-    { common_pid: postgres        [      1867], size:       1000 } hitcount:         10
+-    { common_pid: bamfdaemon      [      2787], size:         28 } hitcount:          2
+-    { common_pid: bamfdaemon      [      2787], size:      14360 } hitcount:          1
+-    { common_pid: compiz          [      2994], size:          8 } hitcount:          1
+-    { common_pid: compiz          [      2994], size:         20 } hitcount:         11
+-    { common_pid: gnome-terminal  [      3199], size:          4 } hitcount:          2
+-    { common_pid: firefox         [      8817], size:          4 } hitcount:          1
+-    { common_pid: firefox         [      8817], size:          8 } hitcount:          5
+-    { common_pid: firefox         [      8817], size:        588 } hitcount:          2
+-    { common_pid: firefox         [      8817], size:        628 } hitcount:          1
+-    { common_pid: firefox         [      8817], size:       6944 } hitcount:          1
+-    { common_pid: firefox         [      8817], size:     408880 } hitcount:          2
+-    { common_pid: firefox         [      8822], size:          8 } hitcount:          2
+-    { common_pid: firefox         [      8822], size:        160 } hitcount:          2
+-    { common_pid: firefox         [      8822], size:        320 } hitcount:          2
+-    { common_pid: firefox         [      8822], size:        352 } hitcount:          1
+-    .
+-    .
+-    .
+-    { common_pid: pool            [      8923], size:       1960 } hitcount:         10
+-    { common_pid: pool            [      8923], size:       2048 } hitcount:         10
+-    { common_pid: pool            [      8924], size:       1960 } hitcount:         10
+-    { common_pid: pool            [      8924], size:       2048 } hitcount:         10
+-    { common_pid: pool            [      8928], size:       1964 } hitcount:          4
+-    { common_pid: pool            [      8928], size:       1965 } hitcount:          2
+-    { common_pid: pool            [      8928], size:       2048 } hitcount:          6
+-    { common_pid: pool            [      8929], size:       1982 } hitcount:          1
+-    { common_pid: pool            [      8929], size:       2048 } hitcount:          1
+-
+-    Totals:
+-        Hits: 2016
+-        Entries: 224
+-        Dropped: 0
+-
+-  The above example also illustrates the fact that although a compound
+-  key is treated as a single entity for hashing purposes, the sub-keys
+-  it's composed of can be accessed independently.
+-
+-  The next example uses a string field as the hash key and
+-  demonstrates how you can manually pause and continue a hist trigger.
+-  In this example, we'll aggregate fork counts and don't expect a
+-  large number of entries in the hash table, so we'll drop it to a
+-  much smaller number, say 256:
+-
+-    # echo 'hist:key=child_comm:val=hitcount:size=256' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+-    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
+-
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: ibus-daemon                         } hitcount:          1
+-    { child_comm: whoopsie                            } hitcount:          1
+-    { child_comm: smbd                                } hitcount:          1
+-    { child_comm: gdbus                               } hitcount:          1
+-    { child_comm: kthreadd                            } hitcount:          1
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: evolution-alarm                     } hitcount:          2
+-    { child_comm: Socket Thread                       } hitcount:          2
+-    { child_comm: postgres                            } hitcount:          2
+-    { child_comm: bash                                } hitcount:          3
+-    { child_comm: compiz                              } hitcount:          3
+-    { child_comm: evolution-sourc                     } hitcount:          4
+-    { child_comm: dhclient                            } hitcount:          4
+-    { child_comm: pool                                } hitcount:          5
+-    { child_comm: nm-dispatcher.a                     } hitcount:          8
+-    { child_comm: firefox                             } hitcount:          8
+-    { child_comm: dbus-daemon                         } hitcount:          8
+-    { child_comm: glib-pacrunner                      } hitcount:         10
+-    { child_comm: evolution                           } hitcount:         23
+-
+-    Totals:
+-        Hits: 89
+-        Entries: 20
+-        Dropped: 0
+-
+-  If we want to pause the hist trigger, we can simply append :pause to
+-  the command that started the trigger.  Notice that the trigger info
+-  displays as [paused]:
+-
+-    # echo 'hist:key=child_comm:val=hitcount:size=256:pause' >> \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+-    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [paused]
+-
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: kthreadd                            } hitcount:          1
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: gdbus                               } hitcount:          1
+-    { child_comm: ibus-daemon                         } hitcount:          1
+-    { child_comm: Socket Thread                       } hitcount:          2
+-    { child_comm: evolution-alarm                     } hitcount:          2
+-    { child_comm: smbd                                } hitcount:          2
+-    { child_comm: bash                                } hitcount:          3
+-    { child_comm: whoopsie                            } hitcount:          3
+-    { child_comm: compiz                              } hitcount:          3
+-    { child_comm: evolution-sourc                     } hitcount:          4
+-    { child_comm: pool                                } hitcount:          5
+-    { child_comm: postgres                            } hitcount:          6
+-    { child_comm: firefox                             } hitcount:          8
+-    { child_comm: dhclient                            } hitcount:         10
+-    { child_comm: emacs                               } hitcount:         12
+-    { child_comm: dbus-daemon                         } hitcount:         20
+-    { child_comm: nm-dispatcher.a                     } hitcount:         20
+-    { child_comm: evolution                           } hitcount:         35
+-    { child_comm: glib-pacrunner                      } hitcount:         59
+-
+-    Totals:
+-        Hits: 199
+-        Entries: 21
+-        Dropped: 0
+-
+-  To manually continue having the trigger aggregate events, append
+-  :cont instead.  Notice that the trigger info displays as [active]
+-  again, and the data has changed:
+-
+-    # echo 'hist:key=child_comm:val=hitcount:size=256:cont' >> \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+-    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
+-
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: dconf worker                        } hitcount:          1
+-    { child_comm: kthreadd                            } hitcount:          1
+-    { child_comm: gdbus                               } hitcount:          1
+-    { child_comm: ibus-daemon                         } hitcount:          1
+-    { child_comm: Socket Thread                       } hitcount:          2
+-    { child_comm: evolution-alarm                     } hitcount:          2
+-    { child_comm: smbd                                } hitcount:          2
+-    { child_comm: whoopsie                            } hitcount:          3
+-    { child_comm: compiz                              } hitcount:          3
+-    { child_comm: evolution-sourc                     } hitcount:          4
+-    { child_comm: bash                                } hitcount:          5
+-    { child_comm: pool                                } hitcount:          5
+-    { child_comm: postgres                            } hitcount:          6
+-    { child_comm: firefox                             } hitcount:          8
+-    { child_comm: dhclient                            } hitcount:         11
+-    { child_comm: emacs                               } hitcount:         12
+-    { child_comm: dbus-daemon                         } hitcount:         22
+-    { child_comm: nm-dispatcher.a                     } hitcount:         22
+-    { child_comm: evolution                           } hitcount:         35
+-    { child_comm: glib-pacrunner                      } hitcount:         59
+-
+-    Totals:
+-        Hits: 206
+-        Entries: 21
+-        Dropped: 0
+-
+-  The previous example showed how to start and stop a hist trigger by
+-  appending 'pause' and 'continue' to the hist trigger command.  A
+-  hist trigger can also be started in a paused state by initially
+-  starting the trigger with ':pause' appended.  This allows you to
+-  start the trigger only when you're ready to start collecting data
+-  and not before.  For example, you could start the trigger in a
+-  paused state, then unpause it and do something you want to measure,
+-  then pause the trigger again when done.
+-
+-  Of course, doing this manually can be difficult and error-prone, but
+-  it is possible to automatically start and stop a hist trigger based
+-  on some condition, via the enable_hist and disable_hist triggers.
+-
+-  For example, suppose we wanted to take a look at the relative
+-  weights in terms of skb length for each callpath that leads to a
+-  netif_receieve_skb event when downloading a decent-sized file using
+-  wget.
+-
+-  First we set up an initially paused stacktrace trigger on the
+-  netif_receive_skb event:
+-
+-    # echo 'hist:key=stacktrace:vals=len:pause' > \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-
+-  Next, we set up an 'enable_hist' trigger on the sched_process_exec
+-  event, with an 'if filename==/usr/bin/wget' filter.  The effect of
+-  this new trigger is that it will 'unpause' the hist trigger we just
+-  set up on netif_receive_skb if and only if it sees a
+-  sched_process_exec event with a filename of '/usr/bin/wget'.  When
+-  that happens, all netif_receive_skb events are aggregated into a
+-  hash table keyed on stacktrace:
+-
+-    # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+-
+-  The aggregation continues until the netif_receive_skb is paused
+-  again, which is what the following disable_hist event does by
+-  creating a similar setup on the sched_process_exit event, using the
+-  filter 'comm==wget':
+-
+-    # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+-
+-  Whenever a process exits and the comm field of the disable_hist
+-  trigger filter matches 'comm==wget', the netif_receive_skb hist
+-  trigger is disabled.
+-
+-  The overall effect is that netif_receive_skb events are aggregated
+-  into the hash table for only the duration of the wget.  Executing a
+-  wget command and then listing the 'hist' file will display the
+-  output generated by the wget command:
+-
+-    $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
+-
+-    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+-    # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
+-
+-    { stacktrace:
+-         __netif_receive_skb_core+0x46d/0x990
+-         __netif_receive_skb+0x18/0x60
+-         netif_receive_skb_internal+0x23/0x90
+-         napi_gro_receive+0xc8/0x100
+-         ieee80211_deliver_skb+0xd6/0x270 [mac80211]
+-         ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
+-         ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
+-         ieee80211_rx+0x31d/0x900 [mac80211]
+-         iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
+-         iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
+-         iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
+-         irq_thread_fn+0x20/0x50
+-         irq_thread+0x11f/0x150
+-         kthread+0xd2/0xf0
+-         ret_from_fork+0x42/0x70
+-    } hitcount:         85  len:      28884
+-    { stacktrace:
+-         __netif_receive_skb_core+0x46d/0x990
+-         __netif_receive_skb+0x18/0x60
+-         netif_receive_skb_internal+0x23/0x90
+-         napi_gro_complete+0xa4/0xe0
+-         dev_gro_receive+0x23a/0x360
+-         napi_gro_receive+0x30/0x100
+-         ieee80211_deliver_skb+0xd6/0x270 [mac80211]
+-         ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
+-         ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
+-         ieee80211_rx+0x31d/0x900 [mac80211]
+-         iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
+-         iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
+-         iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
+-         irq_thread_fn+0x20/0x50
+-         irq_thread+0x11f/0x150
+-         kthread+0xd2/0xf0
+-    } hitcount:         98  len:     664329
+-    { stacktrace:
+-         __netif_receive_skb_core+0x46d/0x990
+-         __netif_receive_skb+0x18/0x60
+-         process_backlog+0xa8/0x150
+-         net_rx_action+0x15d/0x340
+-         __do_softirq+0x114/0x2c0
+-         do_softirq_own_stack+0x1c/0x30
+-         do_softirq+0x65/0x70
+-         __local_bh_enable_ip+0xb5/0xc0
+-         ip_finish_output+0x1f4/0x840
+-         ip_output+0x6b/0xc0
+-         ip_local_out_sk+0x31/0x40
+-         ip_send_skb+0x1a/0x50
+-         udp_send_skb+0x173/0x2a0
+-         udp_sendmsg+0x2bf/0x9f0
+-         inet_sendmsg+0x64/0xa0
+-         sock_sendmsg+0x3d/0x50
+-    } hitcount:        115  len:      13030
+-    { stacktrace:
+-         __netif_receive_skb_core+0x46d/0x990
+-         __netif_receive_skb+0x18/0x60
+-         netif_receive_skb_internal+0x23/0x90
+-         napi_gro_complete+0xa4/0xe0
+-         napi_gro_flush+0x6d/0x90
+-         iwl_pcie_irq_handler+0x92a/0x12f0 [iwlwifi]
+-         irq_thread_fn+0x20/0x50
+-         irq_thread+0x11f/0x150
+-         kthread+0xd2/0xf0
+-         ret_from_fork+0x42/0x70
+-    } hitcount:        934  len:    5512212
+-
+-    Totals:
+-        Hits: 1232
+-        Entries: 4
+-        Dropped: 0
+-
+-  The above shows all the netif_receive_skb callpaths and their total
+-  lengths for the duration of the wget command.
+-
+-  The 'clear' hist trigger param can be used to clear the hash table.
+-  Suppose we wanted to try another run of the previous example but
+-  this time also wanted to see the complete list of events that went
+-  into the histogram.  In order to avoid having to set everything up
+-  again, we can just clear the histogram first:
+-
+-    # echo 'hist:key=stacktrace:vals=len:clear' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-
+-  Just to verify that it is in fact cleared, here's what we now see in
+-  the hist file:
+-
+-    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+-    # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
+-
+-    Totals:
+-        Hits: 0
+-        Entries: 0
+-        Dropped: 0
+-
+-  Since we want to see the detailed list of every netif_receive_skb
+-  event occurring during the new run, which are in fact the same
+-  events being aggregated into the hash table, we add some additional
+-  'enable_event' events to the triggering sched_process_exec and
+-  sched_process_exit events as such:
+-
+-    # echo 'enable_event:net:netif_receive_skb if filename==/usr/bin/wget' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+-
+-    # echo 'disable_event:net:netif_receive_skb if comm==wget' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+-
+-  If you read the trigger files for the sched_process_exec and
+-  sched_process_exit triggers, you should see two triggers for each:
+-  one enabling/disabling the hist aggregation and the other
+-  enabling/disabling the logging of events:
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+-    enable_event:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
+-    enable_hist:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+-    enable_event:net:netif_receive_skb:unlimited if comm==wget
+-    disable_hist:net:netif_receive_skb:unlimited if comm==wget
+-
+-  In other words, whenever either of the sched_process_exec or
+-  sched_process_exit events is hit and matches 'wget', it enables or
+-  disables both the histogram and the event log, and what you end up
+-  with is a hash table and set of events just covering the specified
+-  duration.  Run the wget command again:
+-
+-    $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
+-
+-  Displaying the 'hist' file should show something similar to what you
+-  saw in the last run, but this time you should also see the
+-  individual events in the trace file:
+-
+-    # cat /sys/kernel/debug/tracing/trace
+-
+-    # tracer: nop
+-    #
+-    # entries-in-buffer/entries-written: 183/1426   #P:4
+-    #
+-    #                              _-----=> irqs-off
+-    #                             / _----=> need-resched
+-    #                            | / _---=> hardirq/softirq
+-    #                            || / _--=> preempt-depth
+-    #                            ||| /     delay
+-    #           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
+-    #              | |       |   ||||       |         |
+-                wget-15108 [000] ..s1 31769.606929: netif_receive_skb: dev=lo skbaddr=ffff88009c353100 len=60
+-                wget-15108 [000] ..s1 31769.606999: netif_receive_skb: dev=lo skbaddr=ffff88009c353200 len=60
+-             dnsmasq-1382  [000] ..s1 31769.677652: netif_receive_skb: dev=lo skbaddr=ffff88009c352b00 len=130
+-             dnsmasq-1382  [000] ..s1 31769.685917: netif_receive_skb: dev=lo skbaddr=ffff88009c352200 len=138
+-    ##### CPU 2 buffer started ####
+-      irq/29-iwlwifi-559   [002] ..s. 31772.031529: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433d00 len=2948
+-      irq/29-iwlwifi-559   [002] ..s. 31772.031572: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432200 len=1500
+-      irq/29-iwlwifi-559   [002] ..s. 31772.032196: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433100 len=2948
+-      irq/29-iwlwifi-559   [002] ..s. 31772.032761: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433000 len=2948
+-      irq/29-iwlwifi-559   [002] ..s. 31772.033220: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432e00 len=1500
+-    .
+-    .
+-    .
+-
+-  The following example demonstrates how multiple hist triggers can be
+-  attached to a given event.  This capability can be useful for
+-  creating a set of different summaries derived from the same set of
+-  events, or for comparing the effects of different filters, among
+-  other things.
+-
+-    # echo 'hist:keys=skbaddr.hex:vals=len if len < 0' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-    # echo 'hist:keys=skbaddr.hex:vals=len if len > 4096' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-    # echo 'hist:keys=skbaddr.hex:vals=len if len == 256' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-    # echo 'hist:keys=skbaddr.hex:vals=len' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-    # echo 'hist:keys=len:vals=common_preempt_count' >> \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-
+-  The above set of commands create four triggers differing only in
+-  their filters, along with a completely different though fairly
+-  nonsensical trigger.  Note that in order to append multiple hist
+-  triggers to the same file, you should use the '>>' operator to
+-  append them ('>' will also add the new hist trigger, but will remove
+-  any existing hist triggers beforehand).
+-
+-  Displaying the contents of the 'hist' file for the event shows the
+-  contents of all five histograms:
+-
+-    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:keys=len:vals=hitcount,common_preempt_count:sort=hitcount:size=2048 [active]
+-    #
+-
+-    { len:        176 } hitcount:          1  common_preempt_count:          0
+-    { len:        223 } hitcount:          1  common_preempt_count:          0
+-    { len:       4854 } hitcount:          1  common_preempt_count:          0
+-    { len:        395 } hitcount:          1  common_preempt_count:          0
+-    { len:        177 } hitcount:          1  common_preempt_count:          0
+-    { len:        446 } hitcount:          1  common_preempt_count:          0
+-    { len:       1601 } hitcount:          1  common_preempt_count:          0
+-    .
+-    .
+-    .
+-    { len:       1280 } hitcount:         66  common_preempt_count:          0
+-    { len:        116 } hitcount:         81  common_preempt_count:         40
+-    { len:        708 } hitcount:        112  common_preempt_count:          0
+-    { len:         46 } hitcount:        221  common_preempt_count:          0
+-    { len:       1264 } hitcount:        458  common_preempt_count:          0
+-
+-    Totals:
+-        Hits: 1428
+-        Entries: 147
+-        Dropped: 0
+-
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+-    #
+-
+-    { skbaddr: ffff8800baee5e00 } hitcount:          1  len:        130
+-    { skbaddr: ffff88005f3d5600 } hitcount:          1  len:       1280
+-    { skbaddr: ffff88005f3d4900 } hitcount:          1  len:       1280
+-    { skbaddr: ffff88009fed6300 } hitcount:          1  len:        115
+-    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:        115
+-    { skbaddr: ffff88008cdb1900 } hitcount:          1  len:         46
+-    { skbaddr: ffff880064b5ef00 } hitcount:          1  len:        118
+-    { skbaddr: ffff880044e3c700 } hitcount:          1  len:         60
+-    { skbaddr: ffff880100065900 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d46bd500 } hitcount:          1  len:        116
+-    { skbaddr: ffff88005f3d5f00 } hitcount:          1  len:       1280
+-    { skbaddr: ffff880100064700 } hitcount:          1  len:        365
+-    { skbaddr: ffff8800badb6f00 } hitcount:          1  len:         60
+-    .
+-    .
+-    .
+-    { skbaddr: ffff88009fe0be00 } hitcount:         27  len:      24677
+-    { skbaddr: ffff88009fe0a400 } hitcount:         27  len:      23052
+-    { skbaddr: ffff88009fe0b700 } hitcount:         31  len:      25589
+-    { skbaddr: ffff88009fe0b600 } hitcount:         32  len:      27326
+-    { skbaddr: ffff88006a462800 } hitcount:         68  len:      71678
+-    { skbaddr: ffff88006a463700 } hitcount:         70  len:      72678
+-    { skbaddr: ffff88006a462b00 } hitcount:         71  len:      77589
+-    { skbaddr: ffff88006a463600 } hitcount:         73  len:      71307
+-    { skbaddr: ffff88006a462200 } hitcount:         81  len:      81032
+-
+-    Totals:
+-        Hits: 1451
+-        Entries: 318
+-        Dropped: 0
+-
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len == 256 [active]
+-    #
+-
+-
+-    Totals:
+-        Hits: 0
+-        Entries: 0
+-        Dropped: 0
+-
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len > 4096 [active]
+-    #
+-
+-    { skbaddr: ffff88009fd2c300 } hitcount:          1  len:       7212
+-    { skbaddr: ffff8800d2bcce00 } hitcount:          1  len:       7212
+-    { skbaddr: ffff8800d2bcd700 } hitcount:          1  len:       7212
+-    { skbaddr: ffff8800d2bcda00 } hitcount:          1  len:      21492
+-    { skbaddr: ffff8800ae2e2d00 } hitcount:          1  len:       7212
+-    { skbaddr: ffff8800d2bcdb00 } hitcount:          1  len:       7212
+-    { skbaddr: ffff88006a4df500 } hitcount:          1  len:       4854
+-    { skbaddr: ffff88008ce47b00 } hitcount:          1  len:      18636
+-    { skbaddr: ffff8800ae2e2200 } hitcount:          1  len:      12924
+-    { skbaddr: ffff88005f3e1000 } hitcount:          1  len:       4356
+-    { skbaddr: ffff8800d2bcdc00 } hitcount:          2  len:      24420
+-    { skbaddr: ffff8800d2bcc200 } hitcount:          2  len:      12996
+-
+-    Totals:
+-        Hits: 14
+-        Entries: 12
+-        Dropped: 0
+-
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len < 0 [active]
+-    #
+-
+-
+-    Totals:
+-        Hits: 0
+-        Entries: 0
+-        Dropped: 0
+-
+-  Named triggers can be used to have triggers share a common set of
+-  histogram data.  This capability is mostly useful for combining the
+-  output of events generated by tracepoints contained inside inline
+-  functions, but names can be used in a hist trigger on any event.
+-  For example, these two triggers when hit will update the same 'len'
+-  field in the shared 'foo' histogram data:
+-
+-    # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
+-           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+-    # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
+-           /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+-
+-  You can see that they're updating common histogram data by reading
+-  each event's hist files at the same time:
+-
+-    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist;
+-      cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+-    #
+-
+-    { skbaddr: ffff88000ad53500 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800af5a1500 } hitcount:          1  len:         76
+-    { skbaddr: ffff8800d62a1900 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bccb00 } hitcount:          1  len:        468
+-    { skbaddr: ffff8800d3c69900 } hitcount:          1  len:         46
+-    { skbaddr: ffff88009ff09100 } hitcount:          1  len:         52
+-    { skbaddr: ffff88010f13ab00 } hitcount:          1  len:        168
+-    { skbaddr: ffff88006a54f400 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcc500 } hitcount:          1  len:        260
+-    { skbaddr: ffff880064505000 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800baf24e00 } hitcount:          1  len:         32
+-    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d3edff00 } hitcount:          1  len:         44
+-    { skbaddr: ffff88009fe0b400 } hitcount:          1  len:        168
+-    { skbaddr: ffff8800a1c55a00 } hitcount:          1  len:         40
+-    { skbaddr: ffff8800d2bcd100 } hitcount:          1  len:         40
+-    { skbaddr: ffff880064505f00 } hitcount:          1  len:        174
+-    { skbaddr: ffff8800a8bff200 } hitcount:          1  len:        160
+-    { skbaddr: ffff880044e3cc00 } hitcount:          1  len:         76
+-    { skbaddr: ffff8800a8bfe700 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcdc00 } hitcount:          1  len:         32
+-    { skbaddr: ffff8800a1f64800 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcde00 } hitcount:          1  len:        988
+-    { skbaddr: ffff88006a5dea00 } hitcount:          1  len:         46
+-    { skbaddr: ffff88002e37a200 } hitcount:          1  len:         44
+-    { skbaddr: ffff8800a1f32c00 } hitcount:          2  len:        676
+-    { skbaddr: ffff88000ad52600 } hitcount:          2  len:        107
+-    { skbaddr: ffff8800a1f91e00 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800af5a0200 } hitcount:          2  len:        142
+-    { skbaddr: ffff8800d2bcc600 } hitcount:          2  len:        220
+-    { skbaddr: ffff8800ba36f500 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800d021f800 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800a1f33600 } hitcount:          2  len:        675
+-    { skbaddr: ffff8800a8bfff00 } hitcount:          3  len:        138
+-    { skbaddr: ffff8800d62a1300 } hitcount:          3  len:        138
+-    { skbaddr: ffff88002e37a100 } hitcount:          4  len:        184
+-    { skbaddr: ffff880064504400 } hitcount:          4  len:        184
+-    { skbaddr: ffff8800a8bfec00 } hitcount:          4  len:        184
+-    { skbaddr: ffff88000ad53700 } hitcount:          5  len:        230
+-    { skbaddr: ffff8800d2bcdb00 } hitcount:          5  len:        196
+-    { skbaddr: ffff8800a1f90000 } hitcount:          6  len:        276
+-    { skbaddr: ffff88006a54f900 } hitcount:          6  len:        276
+-
+-    Totals:
+-        Hits: 81
+-        Entries: 42
+-        Dropped: 0
+-    # event histogram
+-    #
+-    # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+-    #
+-
+-    { skbaddr: ffff88000ad53500 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800af5a1500 } hitcount:          1  len:         76
+-    { skbaddr: ffff8800d62a1900 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bccb00 } hitcount:          1  len:        468
+-    { skbaddr: ffff8800d3c69900 } hitcount:          1  len:         46
+-    { skbaddr: ffff88009ff09100 } hitcount:          1  len:         52
+-    { skbaddr: ffff88010f13ab00 } hitcount:          1  len:        168
+-    { skbaddr: ffff88006a54f400 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcc500 } hitcount:          1  len:        260
+-    { skbaddr: ffff880064505000 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800baf24e00 } hitcount:          1  len:         32
+-    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d3edff00 } hitcount:          1  len:         44
+-    { skbaddr: ffff88009fe0b400 } hitcount:          1  len:        168
+-    { skbaddr: ffff8800a1c55a00 } hitcount:          1  len:         40
+-    { skbaddr: ffff8800d2bcd100 } hitcount:          1  len:         40
+-    { skbaddr: ffff880064505f00 } hitcount:          1  len:        174
+-    { skbaddr: ffff8800a8bff200 } hitcount:          1  len:        160
+-    { skbaddr: ffff880044e3cc00 } hitcount:          1  len:         76
+-    { skbaddr: ffff8800a8bfe700 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcdc00 } hitcount:          1  len:         32
+-    { skbaddr: ffff8800a1f64800 } hitcount:          1  len:         46
+-    { skbaddr: ffff8800d2bcde00 } hitcount:          1  len:        988
+-    { skbaddr: ffff88006a5dea00 } hitcount:          1  len:         46
+-    { skbaddr: ffff88002e37a200 } hitcount:          1  len:         44
+-    { skbaddr: ffff8800a1f32c00 } hitcount:          2  len:        676
+-    { skbaddr: ffff88000ad52600 } hitcount:          2  len:        107
+-    { skbaddr: ffff8800a1f91e00 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800af5a0200 } hitcount:          2  len:        142
+-    { skbaddr: ffff8800d2bcc600 } hitcount:          2  len:        220
+-    { skbaddr: ffff8800ba36f500 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800d021f800 } hitcount:          2  len:         92
+-    { skbaddr: ffff8800a1f33600 } hitcount:          2  len:        675
+-    { skbaddr: ffff8800a8bfff00 } hitcount:          3  len:        138
+-    { skbaddr: ffff8800d62a1300 } hitcount:          3  len:        138
+-    { skbaddr: ffff88002e37a100 } hitcount:          4  len:        184
+-    { skbaddr: ffff880064504400 } hitcount:          4  len:        184
+-    { skbaddr: ffff8800a8bfec00 } hitcount:          4  len:        184
+-    { skbaddr: ffff88000ad53700 } hitcount:          5  len:        230
+-    { skbaddr: ffff8800d2bcdb00 } hitcount:          5  len:        196
+-    { skbaddr: ffff8800a1f90000 } hitcount:          6  len:        276
+-    { skbaddr: ffff88006a54f900 } hitcount:          6  len:        276
+-
+-    Totals:
+-        Hits: 81
+-        Entries: 42
+-        Dropped: 0
+-
+-  And here's an example that shows how to combine histogram data from
+-  any two events even if they don't share any 'compatible' fields
+-  other than 'hitcount' and 'stacktrace'.  These commands create a
+-  couple of triggers named 'bar' using those fields:
+-
+-    # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
+-           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+-    # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
+-          /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+-
+-  And displaying the output of either shows some interesting if
+-  somewhat confusing output:
+-
+-    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+-    # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+-
+-    # event histogram
+-    #
+-    # trigger info: hist:name=bar:keys=stacktrace:vals=hitcount:sort=hitcount:size=2048 [active]
+-    #
+-
+-    { stacktrace:
+-             _do_fork+0x18e/0x330
+-             kernel_thread+0x29/0x30
+-             kthreadd+0x154/0x1b0
+-             ret_from_fork+0x3f/0x70
+-    } hitcount:          1
+-    { stacktrace:
+-             netif_rx_internal+0xb2/0xd0
+-             netif_rx_ni+0x20/0x70
+-             dev_loopback_xmit+0xaa/0xd0
+-             ip_mc_output+0x126/0x240
+-             ip_local_out_sk+0x31/0x40
+-             igmp_send_report+0x1e9/0x230
+-             igmp_timer_expire+0xe9/0x120
+-             call_timer_fn+0x39/0xf0
+-             run_timer_softirq+0x1e1/0x290
+-             __do_softirq+0xfd/0x290
+-             irq_exit+0x98/0xb0
+-             smp_apic_timer_interrupt+0x4a/0x60
+-             apic_timer_interrupt+0x6d/0x80
+-             cpuidle_enter+0x17/0x20
+-             call_cpuidle+0x3b/0x60
+-             cpu_startup_entry+0x22d/0x310
+-    } hitcount:          1
+-    { stacktrace:
+-             netif_rx_internal+0xb2/0xd0
+-             netif_rx_ni+0x20/0x70
+-             dev_loopback_xmit+0xaa/0xd0
+-             ip_mc_output+0x17f/0x240
+-             ip_local_out_sk+0x31/0x40
+-             ip_send_skb+0x1a/0x50
+-             udp_send_skb+0x13e/0x270
+-             udp_sendmsg+0x2bf/0x980
+-             inet_sendmsg+0x67/0xa0
+-             sock_sendmsg+0x38/0x50
+-             SYSC_sendto+0xef/0x170
+-             SyS_sendto+0xe/0x10
+-             entry_SYSCALL_64_fastpath+0x12/0x6a
+-    } hitcount:          2
+-    { stacktrace:
+-             netif_rx_internal+0xb2/0xd0
+-             netif_rx+0x1c/0x60
+-             loopback_xmit+0x6c/0xb0
+-             dev_hard_start_xmit+0x219/0x3a0
+-             __dev_queue_xmit+0x415/0x4f0
+-             dev_queue_xmit_sk+0x13/0x20
+-             ip_finish_output2+0x237/0x340
+-             ip_finish_output+0x113/0x1d0
+-             ip_output+0x66/0xc0
+-             ip_local_out_sk+0x31/0x40
+-             ip_send_skb+0x1a/0x50
+-             udp_send_skb+0x16d/0x270
+-             udp_sendmsg+0x2bf/0x980
+-             inet_sendmsg+0x67/0xa0
+-             sock_sendmsg+0x38/0x50
+-             ___sys_sendmsg+0x14e/0x270
+-    } hitcount:         76
+-    { stacktrace:
+-             netif_rx_internal+0xb2/0xd0
+-             netif_rx+0x1c/0x60
+-             loopback_xmit+0x6c/0xb0
+-             dev_hard_start_xmit+0x219/0x3a0
+-             __dev_queue_xmit+0x415/0x4f0
+-             dev_queue_xmit_sk+0x13/0x20
+-             ip_finish_output2+0x237/0x340
+-             ip_finish_output+0x113/0x1d0
+-             ip_output+0x66/0xc0
+-             ip_local_out_sk+0x31/0x40
+-             ip_send_skb+0x1a/0x50
+-             udp_send_skb+0x16d/0x270
+-             udp_sendmsg+0x2bf/0x980
+-             inet_sendmsg+0x67/0xa0
+-             sock_sendmsg+0x38/0x50
+-             ___sys_sendmsg+0x269/0x270
+-    } hitcount:         77
+-    { stacktrace:
+-             netif_rx_internal+0xb2/0xd0
+-             netif_rx+0x1c/0x60
+-             loopback_xmit+0x6c/0xb0
+-             dev_hard_start_xmit+0x219/0x3a0
+-             __dev_queue_xmit+0x415/0x4f0
+-             dev_queue_xmit_sk+0x13/0x20
+-             ip_finish_output2+0x237/0x340
+-             ip_finish_output+0x113/0x1d0
+-             ip_output+0x66/0xc0
+-             ip_local_out_sk+0x31/0x40
+-             ip_send_skb+0x1a/0x50
+-             udp_send_skb+0x16d/0x270
+-             udp_sendmsg+0x2bf/0x980
+-             inet_sendmsg+0x67/0xa0
+-             sock_sendmsg+0x38/0x50
+-             SYSC_sendto+0xef/0x170
+-    } hitcount:         88
+-    { stacktrace:
+-             _do_fork+0x18e/0x330
+-             SyS_clone+0x19/0x20
+-             entry_SYSCALL_64_fastpath+0x12/0x6a
+-    } hitcount:        244
+-
+-    Totals:
+-        Hits: 489
+-        Entries: 7
+-        Dropped: 0
++  See Documentation/trace/histogram.txt for details and examples.
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+new file mode 100644
+index 000000000000..b2145f44b190
+--- /dev/null
++++ b/Documentation/trace/histogram.txt
+@@ -0,0 +1,1568 @@
++			     Event Histograms
++
++		    Documentation written by Tom Zanussi
++
++1. Introduction
++===============
++
++  Histogram triggers are special event triggers that can be used to
++  aggregate trace event data into histograms.  For information on
++  trace events and event triggers, see Documentation/trace/events.txt.
++
++
++2. Histogram Trigger Command
++============================
++
++  A histogram trigger command is an event trigger command that
++  aggregates event hits into a hash table keyed on one or more trace
++  event format fields (or stacktrace) and a set of running totals
++  derived from one or more trace event format fields and/or event
++  counts (hitcount).
++
++  The format of a hist trigger is as follows:
++
++        hist:keys=<field1[,field2,...]>[:values=<field1[,field2,...]>]
++          [:sort=<field1[,field2,...]>][:size=#entries][:pause][:continue]
++          [:clear][:name=histname1] [if <filter>]
++
++  When a matching event is hit, an entry is added to a hash table
++  using the key(s) and value(s) named.  Keys and values correspond to
++  fields in the event's format description.  Values must correspond to
++  numeric fields - on an event hit, the value(s) will be added to a
++  sum kept for that field.  The special string 'hitcount' can be used
++  in place of an explicit value field - this is simply a count of
++  event hits.  If 'values' isn't specified, an implicit 'hitcount'
++  value will be automatically created and used as the only value.
++  Keys can be any field, or the special string 'stacktrace', which
++  will use the event's kernel stacktrace as the key.  The keywords
++  'keys' or 'key' can be used to specify keys, and the keywords
++  'values', 'vals', or 'val' can be used to specify values.  Compound
++  keys consisting of up to two fields can be specified by the 'keys'
++  keyword.  Hashing a compound key produces a unique entry in the
++  table for each unique combination of component keys, and can be
++  useful for providing more fine-grained summaries of event data.
++  Additionally, sort keys consisting of up to two fields can be
++  specified by the 'sort' keyword.  If more than one field is
++  specified, the result will be a 'sort within a sort': the first key
++  is taken to be the primary sort key and the second the secondary
++  key.  If a hist trigger is given a name using the 'name' parameter,
++  its histogram data will be shared with other triggers of the same
++  name, and trigger hits will update this common data.  Only triggers
++  with 'compatible' fields can be combined in this way; triggers are
++  'compatible' if the fields named in the trigger share the same
++  number and type of fields and those fields also have the same names.
++  Note that any two events always share the compatible 'hitcount' and
++  'stacktrace' fields and can therefore be combined using those
++  fields, however pointless that may be.
++
++  'hist' triggers add a 'hist' file to each event's subdirectory.
++  Reading the 'hist' file for the event will dump the hash table in
++  its entirety to stdout.  If there are multiple hist triggers
++  attached to an event, there will be a table for each trigger in the
++  output.  The table displayed for a named trigger will be the same as
++  any other instance having the same name. Each printed hash table
++  entry is a simple list of the keys and values comprising the entry;
++  keys are printed first and are delineated by curly braces, and are
++  followed by the set of value fields for the entry.  By default,
++  numeric fields are displayed as base-10 integers.  This can be
++  modified by appending any of the following modifiers to the field
++  name:
++
++        .hex        display a number as a hex value
++	.sym        display an address as a symbol
++	.sym-offset display an address as a symbol and offset
++	.syscall    display a syscall id as a system call name
++	.execname   display a common_pid as a program name
++
++  Note that in general the semantics of a given field aren't
++  interpreted when applying a modifier to it, but there are some
++  restrictions to be aware of in this regard:
++
++    - only the 'hex' modifier can be used for values (because values
++      are essentially sums, and the other modifiers don't make sense
++      in that context).
++    - the 'execname' modifier can only be used on a 'common_pid'.  The
++      reason for this is that the execname is simply the 'comm' value
++      saved for the 'current' process when an event was triggered,
++      which is the same as the common_pid value saved by the event
++      tracing code.  Trying to apply that comm value to other pid
++      values wouldn't be correct, and typically events that care save
++      pid-specific comm fields in the event itself.
++
++  A typical usage scenario would be the following to enable a hist
++  trigger, read its current contents, and then turn it off:
++
++  # echo 'hist:keys=skbaddr.hex:vals=len' > \
++    /sys/kernel/debug/tracing/events/net/netif_rx/trigger
++
++  # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
++
++  # echo '!hist:keys=skbaddr.hex:vals=len' > \
++    /sys/kernel/debug/tracing/events/net/netif_rx/trigger
++
++  The trigger file itself can be read to show the details of the
++  currently attached hist trigger.  This information is also displayed
++  at the top of the 'hist' file when read.
++
++  By default, the size of the hash table is 2048 entries.  The 'size'
++  parameter can be used to specify more or fewer than that.  The units
++  are in terms of hashtable entries - if a run uses more entries than
++  specified, the results will show the number of 'drops', the number
++  of hits that were ignored.  The size should be a power of 2 between
++  128 and 131072 (any non- power-of-2 number specified will be rounded
++  up).
++
++  The 'sort' parameter can be used to specify a value field to sort
++  on.  The default if unspecified is 'hitcount' and the default sort
++  order is 'ascending'.  To sort in the opposite direction, append
++  .descending' to the sort key.
++
++  The 'pause' parameter can be used to pause an existing hist trigger
++  or to start a hist trigger but not log any events until told to do
++  so.  'continue' or 'cont' can be used to start or restart a paused
++  hist trigger.
++
++  The 'clear' parameter will clear the contents of a running hist
++  trigger and leave its current paused/active state.
++
++  Note that the 'pause', 'cont', and 'clear' parameters should be
++  applied using 'append' shell operator ('>>') if applied to an
++  existing trigger, rather than via the '>' operator, which will cause
++  the trigger to be removed through truncation.
++
++- enable_hist/disable_hist
++
++  The enable_hist and disable_hist triggers can be used to have one
++  event conditionally start and stop another event's already-attached
++  hist trigger.  Any number of enable_hist and disable_hist triggers
++  can be attached to a given event, allowing that event to kick off
++  and stop aggregations on a host of other events.
++
++  The format is very similar to the enable/disable_event triggers:
++
++      enable_hist:<system>:<event>[:count]
++      disable_hist:<system>:<event>[:count]
++
++  Instead of enabling or disabling the tracing of the target event
++  into the trace buffer as the enable/disable_event triggers do, the
++  enable/disable_hist triggers enable or disable the aggregation of
++  the target event into a hash table.
++
++  A typical usage scenario for the enable_hist/disable_hist triggers
++  would be to first set up a paused hist trigger on some event,
++  followed by an enable_hist/disable_hist pair that turns the hist
++  aggregation on and off when conditions of interest are hit:
++
++  # echo 'hist:keys=skbaddr.hex:vals=len:pause' > \
++    /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++
++  # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
++    /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
++
++  # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
++    /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
++
++  The above sets up an initially paused hist trigger which is unpaused
++  and starts aggregating events when a given program is executed, and
++  which stops aggregating when the process exits and the hist trigger
++  is paused again.
++
++  The examples below provide a more concrete illustration of the
++  concepts and typical usage patterns discussed above.
++
++
++6.2 'hist' trigger examples
++---------------------------
++
++  The first set of examples creates aggregations using the kmalloc
++  event.  The fields that can be used for the hist trigger are listed
++  in the kmalloc event's format file:
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/format
++    name: kmalloc
++    ID: 374
++    format:
++	field:unsigned short common_type;	offset:0;	size:2;	signed:0;
++	field:unsigned char common_flags;	offset:2;	size:1;	signed:0;
++	field:unsigned char common_preempt_count;		offset:3;	size:1;	signed:0;
++	field:int common_pid;					offset:4;	size:4;	signed:1;
++
++	field:unsigned long call_site;				offset:8;	size:8;	signed:0;
++	field:const void * ptr;					offset:16;	size:8;	signed:0;
++	field:size_t bytes_req;					offset:24;	size:8;	signed:0;
++	field:size_t bytes_alloc;				offset:32;	size:8;	signed:0;
++	field:gfp_t gfp_flags;					offset:40;	size:4;	signed:0;
++
++  We'll start by creating a hist trigger that generates a simple table
++  that lists the total number of bytes requested for each function in
++  the kernel that made one or more calls to kmalloc:
++
++    # echo 'hist:key=call_site:val=bytes_req' > \
++            /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++  This tells the tracing system to create a 'hist' trigger using the
++  call_site field of the kmalloc event as the key for the table, which
++  just means that each unique call_site address will have an entry
++  created for it in the table.  The 'val=bytes_req' parameter tells
++  the hist trigger that for each unique entry (call_site) in the
++  table, it should keep a running total of the number of bytes
++  requested by that call_site.
++
++  We'll let it run for awhile and then dump the contents of the 'hist'
++  file in the kmalloc event's subdirectory (for readability, a number
++  of entries have been omitted):
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
++
++    { call_site: 18446744072106379007 } hitcount:          1  bytes_req:        176
++    { call_site: 18446744071579557049 } hitcount:          1  bytes_req:       1024
++    { call_site: 18446744071580608289 } hitcount:          1  bytes_req:      16384
++    { call_site: 18446744071581827654 } hitcount:          1  bytes_req:         24
++    { call_site: 18446744071580700980 } hitcount:          1  bytes_req:          8
++    { call_site: 18446744071579359876 } hitcount:          1  bytes_req:        152
++    { call_site: 18446744071580795365 } hitcount:          3  bytes_req:        144
++    { call_site: 18446744071581303129 } hitcount:          3  bytes_req:        144
++    { call_site: 18446744071580713234 } hitcount:          4  bytes_req:       2560
++    { call_site: 18446744071580933750 } hitcount:          4  bytes_req:        736
++    .
++    .
++    .
++    { call_site: 18446744072106047046 } hitcount:         69  bytes_req:       5576
++    { call_site: 18446744071582116407 } hitcount:         73  bytes_req:       2336
++    { call_site: 18446744072106054684 } hitcount:        136  bytes_req:     140504
++    { call_site: 18446744072106224230 } hitcount:        136  bytes_req:      19584
++    { call_site: 18446744072106078074 } hitcount:        153  bytes_req:       2448
++    { call_site: 18446744072106062406 } hitcount:        153  bytes_req:      36720
++    { call_site: 18446744071582507929 } hitcount:        153  bytes_req:      37088
++    { call_site: 18446744072102520590 } hitcount:        273  bytes_req:      10920
++    { call_site: 18446744071582143559 } hitcount:        358  bytes_req:        716
++    { call_site: 18446744072106465852 } hitcount:        417  bytes_req:      56712
++    { call_site: 18446744072102523378 } hitcount:        485  bytes_req:      27160
++    { call_site: 18446744072099568646 } hitcount:       1676  bytes_req:      33520
++
++    Totals:
++        Hits: 4610
++        Entries: 45
++        Dropped: 0
++
++  The output displays a line for each entry, beginning with the key
++  specified in the trigger, followed by the value(s) also specified in
++  the trigger.  At the beginning of the output is a line that displays
++  the trigger info, which can also be displayed by reading the
++  'trigger' file:
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++    hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
++
++  At the end of the output are a few lines that display the overall
++  totals for the run.  The 'Hits' field shows the total number of
++  times the event trigger was hit, the 'Entries' field shows the total
++  number of used entries in the hash table, and the 'Dropped' field
++  shows the number of hits that were dropped because the number of
++  used entries for the run exceeded the maximum number of entries
++  allowed for the table (normally 0, but if not a hint that you may
++  want to increase the size of the table using the 'size' parameter).
++
++  Notice in the above output that there's an extra field, 'hitcount',
++  which wasn't specified in the trigger.  Also notice that in the
++  trigger info output, there's a parameter, 'sort=hitcount', which
++  wasn't specified in the trigger either.  The reason for that is that
++  every trigger implicitly keeps a count of the total number of hits
++  attributed to a given entry, called the 'hitcount'.  That hitcount
++  information is explicitly displayed in the output, and in the
++  absence of a user-specified sort parameter, is used as the default
++  sort field.
++
++  The value 'hitcount' can be used in place of an explicit value in
++  the 'values' parameter if you don't really need to have any
++  particular field summed and are mainly interested in hit
++  frequencies.
++
++  To turn the hist trigger off, simply call up the trigger in the
++  command history and re-execute it with a '!' prepended:
++
++    # echo '!hist:key=call_site:val=bytes_req' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++  Finally, notice that the call_site as displayed in the output above
++  isn't really very useful.  It's an address, but normally addresses
++  are displayed in hex.  To have a numeric field displayed as a hex
++  value, simply append '.hex' to the field name in the trigger:
++
++    # echo 'hist:key=call_site.hex:val=bytes_req' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site.hex:vals=bytes_req:sort=hitcount:size=2048 [active]
++
++    { call_site: ffffffffa026b291 } hitcount:          1  bytes_req:        433
++    { call_site: ffffffffa07186ff } hitcount:          1  bytes_req:        176
++    { call_site: ffffffff811ae721 } hitcount:          1  bytes_req:      16384
++    { call_site: ffffffff811c5134 } hitcount:          1  bytes_req:          8
++    { call_site: ffffffffa04a9ebb } hitcount:          1  bytes_req:        511
++    { call_site: ffffffff8122e0a6 } hitcount:          1  bytes_req:         12
++    { call_site: ffffffff8107da84 } hitcount:          1  bytes_req:        152
++    { call_site: ffffffff812d8246 } hitcount:          1  bytes_req:         24
++    { call_site: ffffffff811dc1e5 } hitcount:          3  bytes_req:        144
++    { call_site: ffffffffa02515e8 } hitcount:          3  bytes_req:        648
++    { call_site: ffffffff81258159 } hitcount:          3  bytes_req:        144
++    { call_site: ffffffff811c80f4 } hitcount:          4  bytes_req:        544
++    .
++    .
++    .
++    { call_site: ffffffffa06c7646 } hitcount:        106  bytes_req:       8024
++    { call_site: ffffffffa06cb246 } hitcount:        132  bytes_req:      31680
++    { call_site: ffffffffa06cef7a } hitcount:        132  bytes_req:       2112
++    { call_site: ffffffff8137e399 } hitcount:        132  bytes_req:      23232
++    { call_site: ffffffffa06c941c } hitcount:        185  bytes_req:     171360
++    { call_site: ffffffffa06f2a66 } hitcount:        185  bytes_req:      26640
++    { call_site: ffffffffa036a70e } hitcount:        265  bytes_req:      10600
++    { call_site: ffffffff81325447 } hitcount:        292  bytes_req:        584
++    { call_site: ffffffffa072da3c } hitcount:        446  bytes_req:      60656
++    { call_site: ffffffffa036b1f2 } hitcount:        526  bytes_req:      29456
++    { call_site: ffffffffa0099c06 } hitcount:       1780  bytes_req:      35600
++
++    Totals:
++        Hits: 4775
++        Entries: 46
++        Dropped: 0
++
++  Even that's only marginally more useful - while hex values do look
++  more like addresses, what users are typically more interested in
++  when looking at text addresses are the corresponding symbols
++  instead.  To have an address displayed as symbolic value instead,
++  simply append '.sym' or '.sym-offset' to the field name in the
++  trigger:
++
++    # echo 'hist:key=call_site.sym:val=bytes_req' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=hitcount:size=2048 [active]
++
++    { call_site: [ffffffff810adcb9] syslog_print_all                              } hitcount:          1  bytes_req:       1024
++    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8
++    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7
++    { call_site: [ffffffff8154acbe] usb_alloc_urb                                 } hitcount:          1  bytes_req:        192
++    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7
++    { call_site: [ffffffff811e3a25] __seq_open_private                            } hitcount:          1  bytes_req:         40
++    { call_site: [ffffffff8109524a] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128
++    { call_site: [ffffffff811febd5] fsnotify_alloc_group                          } hitcount:          2  bytes_req:        528
++    { call_site: [ffffffff81440f58] __tty_buffer_request_room                     } hitcount:          2  bytes_req:       2624
++    { call_site: [ffffffff81200ba6] inotify_new_group                             } hitcount:          2  bytes_req:         96
++    { call_site: [ffffffffa05e19af] ieee80211_start_tx_ba_session [mac80211]      } hitcount:          2  bytes_req:        464
++    { call_site: [ffffffff81672406] tcp_get_metrics                               } hitcount:          2  bytes_req:        304
++    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128
++    { call_site: [ffffffff81089b05] sched_create_group                            } hitcount:          2  bytes_req:       1424
++    .
++    .
++    .
++    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:       1185  bytes_req:     123240
++    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm]                } hitcount:       1185  bytes_req:     104280
++    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:       1402  bytes_req:     190672
++    { call_site: [ffffffff812891ca] ext4_find_extent                              } hitcount:       1518  bytes_req:     146208
++    { call_site: [ffffffffa029070e] drm_vma_node_allow [drm]                      } hitcount:       1746  bytes_req:      69840
++    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       2021  bytes_req:     792312
++    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       2592  bytes_req:     145152
++    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       2629  bytes_req:     378576
++    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       2629  bytes_req:    3783248
++    { call_site: [ffffffff81325607] apparmor_file_alloc_security                  } hitcount:       5192  bytes_req:      10384
++    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       5529  bytes_req:     110584
++    { call_site: [ffffffff8131ebf7] aa_alloc_task_context                         } hitcount:      21943  bytes_req:     702176
++    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:      55759  bytes_req:    5074265
++
++    Totals:
++        Hits: 109928
++        Entries: 71
++        Dropped: 0
++
++  Because the default sort key above is 'hitcount', the above shows a
++  the list of call_sites by increasing hitcount, so that at the bottom
++  we see the functions that made the most kmalloc calls during the
++  run.  If instead we we wanted to see the top kmalloc callers in
++  terms of the number of bytes requested rather than the number of
++  calls, and we wanted the top caller to appear at the top, we can use
++  the 'sort' parameter, along with the 'descending' modifier:
++
++    # echo 'hist:key=call_site.sym:val=bytes_req:sort=bytes_req.descending' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
++
++    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       2186  bytes_req:    3397464
++    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       1790  bytes_req:     712176
++    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:       8132  bytes_req:     513135
++    { call_site: [ffffffff811e2a1b] seq_buf_alloc                                 } hitcount:        106  bytes_req:     440128
++    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       2186  bytes_req:     314784
++    { call_site: [ffffffff812891ca] ext4_find_extent                              } hitcount:       2174  bytes_req:     208992
++    { call_site: [ffffffff811ae8e1] __kmalloc                                     } hitcount:          8  bytes_req:     131072
++    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:        859  bytes_req:     116824
++    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       1834  bytes_req:     102704
++    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:        972  bytes_req:     101088
++    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm]                } hitcount:        972  bytes_req:      85536
++    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       3333  bytes_req:      66664
++    { call_site: [ffffffff8137e559] sg_kmalloc                                    } hitcount:        209  bytes_req:      61632
++    .
++    .
++    .
++    { call_site: [ffffffff81095225] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128
++    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128
++    { call_site: [ffffffff812d8406] copy_semundo                                  } hitcount:          2  bytes_req:         48
++    { call_site: [ffffffff81200ba6] inotify_new_group                             } hitcount:          1  bytes_req:         48
++    { call_site: [ffffffffa027121a] drm_getmagic [drm]                            } hitcount:          1  bytes_req:         48
++    { call_site: [ffffffff811e3a25] __seq_open_private                            } hitcount:          1  bytes_req:         40
++    { call_site: [ffffffff811c52f4] bprm_change_interp                            } hitcount:          2  bytes_req:         16
++    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8
++    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7
++    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7
++
++    Totals:
++        Hits: 32133
++        Entries: 81
++        Dropped: 0
++
++  To display the offset and size information in addition to the symbol
++  name, just use 'sym-offset' instead:
++
++    # echo 'hist:key=call_site.sym-offset:val=bytes_req:sort=bytes_req.descending' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site.sym-offset:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
++
++    { call_site: [ffffffffa046041c] i915_gem_execbuffer2+0x6c/0x2c0 [i915]                  } hitcount:       4569  bytes_req:    3163720
++    { call_site: [ffffffffa0489a66] intel_ring_begin+0xc6/0x1f0 [i915]                      } hitcount:       4569  bytes_req:     657936
++    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23+0x694/0x1020 [i915]      } hitcount:       1519  bytes_req:     472936
++    { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23+0x516/0x1020 [i915]      } hitcount:       3050  bytes_req:     211832
++    { call_site: [ffffffff811e2a1b] seq_buf_alloc+0x1b/0x50                                 } hitcount:         34  bytes_req:     148384
++    { call_site: [ffffffffa04a580c] intel_crtc_page_flip+0xbc/0x870 [i915]                  } hitcount:       1385  bytes_req:     144040
++    { call_site: [ffffffff811ae8e1] __kmalloc+0x191/0x1b0                                   } hitcount:          8  bytes_req:     131072
++    { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl+0x282/0x360 [drm]              } hitcount:       1385  bytes_req:     121880
++    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc+0x32/0x100 [drm]                  } hitcount:       1848  bytes_req:     103488
++    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state+0x2c/0xa0 [i915]            } hitcount:        461  bytes_req:      62696
++    { call_site: [ffffffffa029070e] drm_vma_node_allow+0x2e/0xd0 [drm]                      } hitcount:       1541  bytes_req:      61640
++    { call_site: [ffffffff815f8d7b] sk_prot_alloc+0xcb/0x1b0                                } hitcount:         57  bytes_req:      57456
++    .
++    .
++    .
++    { call_site: [ffffffff8109524a] alloc_fair_sched_group+0x5a/0x1a0                       } hitcount:          2  bytes_req:        128
++    { call_site: [ffffffffa027b921] drm_vm_open_locked+0x31/0xa0 [drm]                      } hitcount:          3  bytes_req:         96
++    { call_site: [ffffffff8122e266] proc_self_follow_link+0x76/0xb0                         } hitcount:          8  bytes_req:         96
++    { call_site: [ffffffff81213e80] load_elf_binary+0x240/0x1650                            } hitcount:          3  bytes_req:         84
++    { call_site: [ffffffff8154bc62] usb_control_msg+0x42/0x110                              } hitcount:          1  bytes_req:          8
++    { call_site: [ffffffffa00bf6fe] hidraw_send_report+0x7e/0x1a0 [hid]                     } hitcount:          1  bytes_req:          7
++    { call_site: [ffffffffa00bf1ca] hidraw_report_event+0x8a/0x120 [hid]                    } hitcount:          1  bytes_req:          7
++
++    Totals:
++        Hits: 26098
++        Entries: 64
++        Dropped: 0
++
++  We can also add multiple fields to the 'values' parameter.  For
++  example, we might want to see the total number of bytes allocated
++  alongside bytes requested, and display the result sorted by bytes
++  allocated in a descending order:
++
++    # echo 'hist:keys=call_site.sym:values=bytes_req,bytes_alloc:sort=bytes_alloc.descending' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=call_site.sym:vals=bytes_req,bytes_alloc:sort=bytes_alloc.descending:size=2048 [active]
++
++    { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915]                   } hitcount:       7403  bytes_req:    4084360  bytes_alloc:    5958016
++    { call_site: [ffffffff811e2a1b] seq_buf_alloc                                 } hitcount:        541  bytes_req:    2213968  bytes_alloc:    2228224
++    { call_site: [ffffffffa0489a66] intel_ring_begin [i915]                       } hitcount:       7404  bytes_req:    1066176  bytes_alloc:    1421568
++    { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       1565  bytes_req:     557368  bytes_alloc:    1037760
++    { call_site: [ffffffff8125847d] ext4_htree_store_dirent                       } hitcount:       9557  bytes_req:     595778  bytes_alloc:     695744
++    { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23 [i915]         } hitcount:       5839  bytes_req:     430680  bytes_alloc:     470400
++    { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915]            } hitcount:       2388  bytes_req:     324768  bytes_alloc:     458496
++    { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm]                   } hitcount:       3911  bytes_req:     219016  bytes_alloc:     250304
++    { call_site: [ffffffff815f8d7b] sk_prot_alloc                                 } hitcount:        235  bytes_req:     236880  bytes_alloc:     240640
++    { call_site: [ffffffff8137e559] sg_kmalloc                                    } hitcount:        557  bytes_req:     169024  bytes_alloc:     221760
++    { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid]                    } hitcount:       9378  bytes_req:     187548  bytes_alloc:     206312
++    { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915]                   } hitcount:       1519  bytes_req:     157976  bytes_alloc:     194432
++    .
++    .
++    .
++    { call_site: [ffffffff8109bd3b] sched_autogroup_create_attach                 } hitcount:          2  bytes_req:        144  bytes_alloc:        192
++    { call_site: [ffffffff81097ee8] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128  bytes_alloc:        128
++    { call_site: [ffffffff8109524a] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128  bytes_alloc:        128
++    { call_site: [ffffffff81095225] alloc_fair_sched_group                        } hitcount:          2  bytes_req:        128  bytes_alloc:        128
++    { call_site: [ffffffff81097ec2] alloc_rt_sched_group                          } hitcount:          2  bytes_req:        128  bytes_alloc:        128
++    { call_site: [ffffffff81213e80] load_elf_binary                               } hitcount:          3  bytes_req:         84  bytes_alloc:         96
++    { call_site: [ffffffff81079a2e] kthread_create_on_node                        } hitcount:          1  bytes_req:         56  bytes_alloc:         64
++    { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid]                      } hitcount:          1  bytes_req:          7  bytes_alloc:          8
++    { call_site: [ffffffff8154bc62] usb_control_msg                               } hitcount:          1  bytes_req:          8  bytes_alloc:          8
++    { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid]                     } hitcount:          1  bytes_req:          7  bytes_alloc:          8
++
++    Totals:
++        Hits: 66598
++        Entries: 65
++        Dropped: 0
++
++  Finally, to finish off our kmalloc example, instead of simply having
++  the hist trigger display symbolic call_sites, we can have the hist
++  trigger additionally display the complete set of kernel stack traces
++  that led to each call_site.  To do that, we simply use the special
++  value 'stacktrace' for the key parameter:
++
++    # echo 'hist:keys=stacktrace:values=bytes_req,bytes_alloc:sort=bytes_alloc' > \
++           /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
++
++  The above trigger will use the kernel stack trace in effect when an
++  event is triggered as the key for the hash table.  This allows the
++  enumeration of every kernel callpath that led up to a particular
++  event, along with a running total of any of the event fields for
++  that event.  Here we tally bytes requested and bytes allocated for
++  every callpath in the system that led up to a kmalloc (in this case
++  every callpath to a kmalloc for a kernel compile):
++
++    # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
++    # trigger info: hist:keys=stacktrace:vals=bytes_req,bytes_alloc:sort=bytes_alloc:size=2048 [active]
++
++    { stacktrace:
++         __kmalloc_track_caller+0x10b/0x1a0
++         kmemdup+0x20/0x50
++         hidraw_report_event+0x8a/0x120 [hid]
++         hid_report_raw_event+0x3ea/0x440 [hid]
++         hid_input_report+0x112/0x190 [hid]
++         hid_irq_in+0xc2/0x260 [usbhid]
++         __usb_hcd_giveback_urb+0x72/0x120
++         usb_giveback_urb_bh+0x9e/0xe0
++         tasklet_hi_action+0xf8/0x100
++         __do_softirq+0x114/0x2c0
++         irq_exit+0xa5/0xb0
++         do_IRQ+0x5a/0xf0
++         ret_from_intr+0x0/0x30
++         cpuidle_enter+0x17/0x20
++         cpu_startup_entry+0x315/0x3e0
++         rest_init+0x7c/0x80
++    } hitcount:          3  bytes_req:         21  bytes_alloc:         24
++    { stacktrace:
++         __kmalloc_track_caller+0x10b/0x1a0
++         kmemdup+0x20/0x50
++         hidraw_report_event+0x8a/0x120 [hid]
++         hid_report_raw_event+0x3ea/0x440 [hid]
++         hid_input_report+0x112/0x190 [hid]
++         hid_irq_in+0xc2/0x260 [usbhid]
++         __usb_hcd_giveback_urb+0x72/0x120
++         usb_giveback_urb_bh+0x9e/0xe0
++         tasklet_hi_action+0xf8/0x100
++         __do_softirq+0x114/0x2c0
++         irq_exit+0xa5/0xb0
++         do_IRQ+0x5a/0xf0
++         ret_from_intr+0x0/0x30
++    } hitcount:          3  bytes_req:         21  bytes_alloc:         24
++    { stacktrace:
++         kmem_cache_alloc_trace+0xeb/0x150
++         aa_alloc_task_context+0x27/0x40
++         apparmor_cred_prepare+0x1f/0x50
++         security_prepare_creds+0x16/0x20
++         prepare_creds+0xdf/0x1a0
++         SyS_capset+0xb5/0x200
++         system_call_fastpath+0x12/0x6a
++    } hitcount:          1  bytes_req:         32  bytes_alloc:         32
++    .
++    .
++    .
++    { stacktrace:
++         __kmalloc+0x11b/0x1b0
++         i915_gem_execbuffer2+0x6c/0x2c0 [i915]
++         drm_ioctl+0x349/0x670 [drm]
++         do_vfs_ioctl+0x2f0/0x4f0
++         SyS_ioctl+0x81/0xa0
++         system_call_fastpath+0x12/0x6a
++    } hitcount:      17726  bytes_req:   13944120  bytes_alloc:   19593808
++    { stacktrace:
++         __kmalloc+0x11b/0x1b0
++         load_elf_phdrs+0x76/0xa0
++         load_elf_binary+0x102/0x1650
++         search_binary_handler+0x97/0x1d0
++         do_execveat_common.isra.34+0x551/0x6e0
++         SyS_execve+0x3a/0x50
++         return_from_execve+0x0/0x23
++    } hitcount:      33348  bytes_req:   17152128  bytes_alloc:   20226048
++    { stacktrace:
++         kmem_cache_alloc_trace+0xeb/0x150
++         apparmor_file_alloc_security+0x27/0x40
++         security_file_alloc+0x16/0x20
++         get_empty_filp+0x93/0x1c0
++         path_openat+0x31/0x5f0
++         do_filp_open+0x3a/0x90
++         do_sys_open+0x128/0x220
++         SyS_open+0x1e/0x20
++         system_call_fastpath+0x12/0x6a
++    } hitcount:    4766422  bytes_req:    9532844  bytes_alloc:   38131376
++    { stacktrace:
++         __kmalloc+0x11b/0x1b0
++         seq_buf_alloc+0x1b/0x50
++         seq_read+0x2cc/0x370
++         proc_reg_read+0x3d/0x80
++         __vfs_read+0x28/0xe0
++         vfs_read+0x86/0x140
++         SyS_read+0x46/0xb0
++         system_call_fastpath+0x12/0x6a
++    } hitcount:      19133  bytes_req:   78368768  bytes_alloc:   78368768
++
++    Totals:
++        Hits: 6085872
++        Entries: 253
++        Dropped: 0
++
++  If you key a hist trigger on common_pid, in order for example to
++  gather and display sorted totals for each process, you can use the
++  special .execname modifier to display the executable names for the
++  processes in the table rather than raw pids.  The example below
++  keeps a per-process sum of total bytes read:
++
++    # echo 'hist:key=common_pid.execname:val=count:sort=count.descending' > \
++           /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
++
++    # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/hist
++    # trigger info: hist:keys=common_pid.execname:vals=count:sort=count.descending:size=2048 [active]
++
++    { common_pid: gnome-terminal  [      3196] } hitcount:        280  count:    1093512
++    { common_pid: Xorg            [      1309] } hitcount:        525  count:     256640
++    { common_pid: compiz          [      2889] } hitcount:         59  count:     254400
++    { common_pid: bash            [      8710] } hitcount:          3  count:      66369
++    { common_pid: dbus-daemon-lau [      8703] } hitcount:         49  count:      47739
++    { common_pid: irqbalance      [      1252] } hitcount:         27  count:      27648
++    { common_pid: 01ifupdown      [      8705] } hitcount:          3  count:      17216
++    { common_pid: dbus-daemon     [       772] } hitcount:         10  count:      12396
++    { common_pid: Socket Thread   [      8342] } hitcount:         11  count:      11264
++    { common_pid: nm-dhcp-client. [      8701] } hitcount:          6  count:       7424
++    { common_pid: gmain           [      1315] } hitcount:         18  count:       6336
++    .
++    .
++    .
++    { common_pid: postgres        [      1892] } hitcount:          2  count:         32
++    { common_pid: postgres        [      1891] } hitcount:          2  count:         32
++    { common_pid: gmain           [      8704] } hitcount:          2  count:         32
++    { common_pid: upstart-dbus-br [      2740] } hitcount:         21  count:         21
++    { common_pid: nm-dispatcher.a [      8696] } hitcount:          1  count:         16
++    { common_pid: indicator-datet [      2904] } hitcount:          1  count:         16
++    { common_pid: gdbus           [      2998] } hitcount:          1  count:         16
++    { common_pid: rtkit-daemon    [      2052] } hitcount:          1  count:          8
++    { common_pid: init            [         1] } hitcount:          2  count:          2
++
++    Totals:
++        Hits: 2116
++        Entries: 51
++        Dropped: 0
++
++  Similarly, if you key a hist trigger on syscall id, for example to
++  gather and display a list of systemwide syscall hits, you can use
++  the special .syscall modifier to display the syscall names rather
++  than raw ids.  The example below keeps a running total of syscall
++  counts for the system during the run:
++
++    # echo 'hist:key=id.syscall:val=hitcount' > \
++           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
++
++    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
++    # trigger info: hist:keys=id.syscall:vals=hitcount:sort=hitcount:size=2048 [active]
++
++    { id: sys_fsync                     [ 74] } hitcount:          1
++    { id: sys_newuname                  [ 63] } hitcount:          1
++    { id: sys_prctl                     [157] } hitcount:          1
++    { id: sys_statfs                    [137] } hitcount:          1
++    { id: sys_symlink                   [ 88] } hitcount:          1
++    { id: sys_sendmmsg                  [307] } hitcount:          1
++    { id: sys_semctl                    [ 66] } hitcount:          1
++    { id: sys_readlink                  [ 89] } hitcount:          3
++    { id: sys_bind                      [ 49] } hitcount:          3
++    { id: sys_getsockname               [ 51] } hitcount:          3
++    { id: sys_unlink                    [ 87] } hitcount:          3
++    { id: sys_rename                    [ 82] } hitcount:          4
++    { id: unknown_syscall               [ 58] } hitcount:          4
++    { id: sys_connect                   [ 42] } hitcount:          4
++    { id: sys_getpid                    [ 39] } hitcount:          4
++    .
++    .
++    .
++    { id: sys_rt_sigprocmask            [ 14] } hitcount:        952
++    { id: sys_futex                     [202] } hitcount:       1534
++    { id: sys_write                     [  1] } hitcount:       2689
++    { id: sys_setitimer                 [ 38] } hitcount:       2797
++    { id: sys_read                      [  0] } hitcount:       3202
++    { id: sys_select                    [ 23] } hitcount:       3773
++    { id: sys_writev                    [ 20] } hitcount:       4531
++    { id: sys_poll                      [  7] } hitcount:       8314
++    { id: sys_recvmsg                   [ 47] } hitcount:      13738
++    { id: sys_ioctl                     [ 16] } hitcount:      21843
++
++    Totals:
++        Hits: 67612
++        Entries: 72
++        Dropped: 0
++
++    The syscall counts above provide a rough overall picture of system
++    call activity on the system; we can see for example that the most
++    popular system call on this system was the 'sys_ioctl' system call.
++
++    We can use 'compound' keys to refine that number and provide some
++    further insight as to which processes exactly contribute to the
++    overall ioctl count.
++
++    The command below keeps a hitcount for every unique combination of
++    system call id and pid - the end result is essentially a table
++    that keeps a per-pid sum of system call hits.  The results are
++    sorted using the system call id as the primary key, and the
++    hitcount sum as the secondary key:
++
++    # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount' > \
++           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
++
++    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
++    # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 [active]
++
++    { id: sys_read                      [  0], common_pid: rtkit-daemon    [      1877] } hitcount:          1
++    { id: sys_read                      [  0], common_pid: gdbus           [      2976] } hitcount:          1
++    { id: sys_read                      [  0], common_pid: console-kit-dae [      3400] } hitcount:          1
++    { id: sys_read                      [  0], common_pid: postgres        [      1865] } hitcount:          1
++    { id: sys_read                      [  0], common_pid: deja-dup-monito [      3543] } hitcount:          2
++    { id: sys_read                      [  0], common_pid: NetworkManager  [       890] } hitcount:          2
++    { id: sys_read                      [  0], common_pid: evolution-calen [      3048] } hitcount:          2
++    { id: sys_read                      [  0], common_pid: postgres        [      1864] } hitcount:          2
++    { id: sys_read                      [  0], common_pid: nm-applet       [      3022] } hitcount:          2
++    { id: sys_read                      [  0], common_pid: whoopsie        [      1212] } hitcount:          2
++    .
++    .
++    .
++    { id: sys_ioctl                     [ 16], common_pid: bash            [      8479] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: bash            [      3472] } hitcount:         12
++    { id: sys_ioctl                     [ 16], common_pid: gnome-terminal  [      3199] } hitcount:         16
++    { id: sys_ioctl                     [ 16], common_pid: Xorg            [      1267] } hitcount:       1808
++    { id: sys_ioctl                     [ 16], common_pid: compiz          [      2994] } hitcount:       5580
++    .
++    .
++    .
++    { id: sys_waitid                    [247], common_pid: upstart-dbus-br [      2690] } hitcount:          3
++    { id: sys_waitid                    [247], common_pid: upstart-dbus-br [      2688] } hitcount:         16
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [       975] } hitcount:          2
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3204] } hitcount:          4
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      2888] } hitcount:          4
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3003] } hitcount:          4
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      2873] } hitcount:          4
++    { id: sys_inotify_add_watch         [254], common_pid: gmain           [      3196] } hitcount:          6
++    { id: sys_openat                    [257], common_pid: java            [      2623] } hitcount:          2
++    { id: sys_eventfd2                  [290], common_pid: ibus-ui-gtk3    [      2760] } hitcount:          4
++    { id: sys_eventfd2                  [290], common_pid: compiz          [      2994] } hitcount:          6
++
++    Totals:
++        Hits: 31536
++        Entries: 323
++        Dropped: 0
++
++    The above list does give us a breakdown of the ioctl syscall by
++    pid, but it also gives us quite a bit more than that, which we
++    don't really care about at the moment.  Since we know the syscall
++    id for sys_ioctl (16, displayed next to the sys_ioctl name), we
++    can use that to filter out all the other syscalls:
++
++    # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount if id == 16' > \
++           /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
++
++    # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
++    # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 if id == 16 [active]
++
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2769] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: evolution-addre [      8571] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      3003] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2781] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2829] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: bash            [      8726] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: bash            [      8508] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2970] } hitcount:          1
++    { id: sys_ioctl                     [ 16], common_pid: gmain           [      2768] } hitcount:          1
++    .
++    .
++    .
++    { id: sys_ioctl                     [ 16], common_pid: pool            [      8559] } hitcount:         45
++    { id: sys_ioctl                     [ 16], common_pid: pool            [      8555] } hitcount:         48
++    { id: sys_ioctl                     [ 16], common_pid: pool            [      8551] } hitcount:         48
++    { id: sys_ioctl                     [ 16], common_pid: avahi-daemon    [       896] } hitcount:         66
++    { id: sys_ioctl                     [ 16], common_pid: Xorg            [      1267] } hitcount:      26674
++    { id: sys_ioctl                     [ 16], common_pid: compiz          [      2994] } hitcount:      73443
++
++    Totals:
++        Hits: 101162
++        Entries: 103
++        Dropped: 0
++
++    The above output shows that 'compiz' and 'Xorg' are far and away
++    the heaviest ioctl callers (which might lead to questions about
++    whether they really need to be making all those calls and to
++    possible avenues for further investigation.)
++
++    The compound key examples used a key and a sum value (hitcount) to
++    sort the output, but we can just as easily use two keys instead.
++    Here's an example where we use a compound key composed of the the
++    common_pid and size event fields.  Sorting with pid as the primary
++    key and 'size' as the secondary key allows us to display an
++    ordered summary of the recvfrom sizes, with counts, received by
++    each process:
++
++    # echo 'hist:key=common_pid.execname,size:val=hitcount:sort=common_pid,size' > \
++           /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/trigger
++
++    # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/hist
++    # trigger info: hist:keys=common_pid.execname,size:vals=hitcount:sort=common_pid.execname,size:size=2048 [active]
++
++    { common_pid: smbd            [       784], size:          4 } hitcount:          1
++    { common_pid: dnsmasq         [      1412], size:       4096 } hitcount:        672
++    { common_pid: postgres        [      1796], size:       1000 } hitcount:          6
++    { common_pid: postgres        [      1867], size:       1000 } hitcount:         10
++    { common_pid: bamfdaemon      [      2787], size:         28 } hitcount:          2
++    { common_pid: bamfdaemon      [      2787], size:      14360 } hitcount:          1
++    { common_pid: compiz          [      2994], size:          8 } hitcount:          1
++    { common_pid: compiz          [      2994], size:         20 } hitcount:         11
++    { common_pid: gnome-terminal  [      3199], size:          4 } hitcount:          2
++    { common_pid: firefox         [      8817], size:          4 } hitcount:          1
++    { common_pid: firefox         [      8817], size:          8 } hitcount:          5
++    { common_pid: firefox         [      8817], size:        588 } hitcount:          2
++    { common_pid: firefox         [      8817], size:        628 } hitcount:          1
++    { common_pid: firefox         [      8817], size:       6944 } hitcount:          1
++    { common_pid: firefox         [      8817], size:     408880 } hitcount:          2
++    { common_pid: firefox         [      8822], size:          8 } hitcount:          2
++    { common_pid: firefox         [      8822], size:        160 } hitcount:          2
++    { common_pid: firefox         [      8822], size:        320 } hitcount:          2
++    { common_pid: firefox         [      8822], size:        352 } hitcount:          1
++    .
++    .
++    .
++    { common_pid: pool            [      8923], size:       1960 } hitcount:         10
++    { common_pid: pool            [      8923], size:       2048 } hitcount:         10
++    { common_pid: pool            [      8924], size:       1960 } hitcount:         10
++    { common_pid: pool            [      8924], size:       2048 } hitcount:         10
++    { common_pid: pool            [      8928], size:       1964 } hitcount:          4
++    { common_pid: pool            [      8928], size:       1965 } hitcount:          2
++    { common_pid: pool            [      8928], size:       2048 } hitcount:          6
++    { common_pid: pool            [      8929], size:       1982 } hitcount:          1
++    { common_pid: pool            [      8929], size:       2048 } hitcount:          1
++
++    Totals:
++        Hits: 2016
++        Entries: 224
++        Dropped: 0
++
++  The above example also illustrates the fact that although a compound
++  key is treated as a single entity for hashing purposes, the sub-keys
++  it's composed of can be accessed independently.
++
++  The next example uses a string field as the hash key and
++  demonstrates how you can manually pause and continue a hist trigger.
++  In this example, we'll aggregate fork counts and don't expect a
++  large number of entries in the hash table, so we'll drop it to a
++  much smaller number, say 256:
++
++    # echo 'hist:key=child_comm:val=hitcount:size=256' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
++    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
++
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: ibus-daemon                         } hitcount:          1
++    { child_comm: whoopsie                            } hitcount:          1
++    { child_comm: smbd                                } hitcount:          1
++    { child_comm: gdbus                               } hitcount:          1
++    { child_comm: kthreadd                            } hitcount:          1
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: evolution-alarm                     } hitcount:          2
++    { child_comm: Socket Thread                       } hitcount:          2
++    { child_comm: postgres                            } hitcount:          2
++    { child_comm: bash                                } hitcount:          3
++    { child_comm: compiz                              } hitcount:          3
++    { child_comm: evolution-sourc                     } hitcount:          4
++    { child_comm: dhclient                            } hitcount:          4
++    { child_comm: pool                                } hitcount:          5
++    { child_comm: nm-dispatcher.a                     } hitcount:          8
++    { child_comm: firefox                             } hitcount:          8
++    { child_comm: dbus-daemon                         } hitcount:          8
++    { child_comm: glib-pacrunner                      } hitcount:         10
++    { child_comm: evolution                           } hitcount:         23
++
++    Totals:
++        Hits: 89
++        Entries: 20
++        Dropped: 0
++
++  If we want to pause the hist trigger, we can simply append :pause to
++  the command that started the trigger.  Notice that the trigger info
++  displays as [paused]:
++
++    # echo 'hist:key=child_comm:val=hitcount:size=256:pause' >> \
++           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
++    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [paused]
++
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: kthreadd                            } hitcount:          1
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: gdbus                               } hitcount:          1
++    { child_comm: ibus-daemon                         } hitcount:          1
++    { child_comm: Socket Thread                       } hitcount:          2
++    { child_comm: evolution-alarm                     } hitcount:          2
++    { child_comm: smbd                                } hitcount:          2
++    { child_comm: bash                                } hitcount:          3
++    { child_comm: whoopsie                            } hitcount:          3
++    { child_comm: compiz                              } hitcount:          3
++    { child_comm: evolution-sourc                     } hitcount:          4
++    { child_comm: pool                                } hitcount:          5
++    { child_comm: postgres                            } hitcount:          6
++    { child_comm: firefox                             } hitcount:          8
++    { child_comm: dhclient                            } hitcount:         10
++    { child_comm: emacs                               } hitcount:         12
++    { child_comm: dbus-daemon                         } hitcount:         20
++    { child_comm: nm-dispatcher.a                     } hitcount:         20
++    { child_comm: evolution                           } hitcount:         35
++    { child_comm: glib-pacrunner                      } hitcount:         59
++
++    Totals:
++        Hits: 199
++        Entries: 21
++        Dropped: 0
++
++  To manually continue having the trigger aggregate events, append
++  :cont instead.  Notice that the trigger info displays as [active]
++  again, and the data has changed:
++
++    # echo 'hist:key=child_comm:val=hitcount:size=256:cont' >> \
++           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
++    # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
++
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: dconf worker                        } hitcount:          1
++    { child_comm: kthreadd                            } hitcount:          1
++    { child_comm: gdbus                               } hitcount:          1
++    { child_comm: ibus-daemon                         } hitcount:          1
++    { child_comm: Socket Thread                       } hitcount:          2
++    { child_comm: evolution-alarm                     } hitcount:          2
++    { child_comm: smbd                                } hitcount:          2
++    { child_comm: whoopsie                            } hitcount:          3
++    { child_comm: compiz                              } hitcount:          3
++    { child_comm: evolution-sourc                     } hitcount:          4
++    { child_comm: bash                                } hitcount:          5
++    { child_comm: pool                                } hitcount:          5
++    { child_comm: postgres                            } hitcount:          6
++    { child_comm: firefox                             } hitcount:          8
++    { child_comm: dhclient                            } hitcount:         11
++    { child_comm: emacs                               } hitcount:         12
++    { child_comm: dbus-daemon                         } hitcount:         22
++    { child_comm: nm-dispatcher.a                     } hitcount:         22
++    { child_comm: evolution                           } hitcount:         35
++    { child_comm: glib-pacrunner                      } hitcount:         59
++
++    Totals:
++        Hits: 206
++        Entries: 21
++        Dropped: 0
++
++  The previous example showed how to start and stop a hist trigger by
++  appending 'pause' and 'continue' to the hist trigger command.  A
++  hist trigger can also be started in a paused state by initially
++  starting the trigger with ':pause' appended.  This allows you to
++  start the trigger only when you're ready to start collecting data
++  and not before.  For example, you could start the trigger in a
++  paused state, then unpause it and do something you want to measure,
++  then pause the trigger again when done.
++
++  Of course, doing this manually can be difficult and error-prone, but
++  it is possible to automatically start and stop a hist trigger based
++  on some condition, via the enable_hist and disable_hist triggers.
++
++  For example, suppose we wanted to take a look at the relative
++  weights in terms of skb length for each callpath that leads to a
++  netif_receieve_skb event when downloading a decent-sized file using
++  wget.
++
++  First we set up an initially paused stacktrace trigger on the
++  netif_receive_skb event:
++
++    # echo 'hist:key=stacktrace:vals=len:pause' > \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++
++  Next, we set up an 'enable_hist' trigger on the sched_process_exec
++  event, with an 'if filename==/usr/bin/wget' filter.  The effect of
++  this new trigger is that it will 'unpause' the hist trigger we just
++  set up on netif_receive_skb if and only if it sees a
++  sched_process_exec event with a filename of '/usr/bin/wget'.  When
++  that happens, all netif_receive_skb events are aggregated into a
++  hash table keyed on stacktrace:
++
++    # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
++
++  The aggregation continues until the netif_receive_skb is paused
++  again, which is what the following disable_hist event does by
++  creating a similar setup on the sched_process_exit event, using the
++  filter 'comm==wget':
++
++    # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
++
++  Whenever a process exits and the comm field of the disable_hist
++  trigger filter matches 'comm==wget', the netif_receive_skb hist
++  trigger is disabled.
++
++  The overall effect is that netif_receive_skb events are aggregated
++  into the hash table for only the duration of the wget.  Executing a
++  wget command and then listing the 'hist' file will display the
++  output generated by the wget command:
++
++    $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
++
++    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
++    # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
++
++    { stacktrace:
++         __netif_receive_skb_core+0x46d/0x990
++         __netif_receive_skb+0x18/0x60
++         netif_receive_skb_internal+0x23/0x90
++         napi_gro_receive+0xc8/0x100
++         ieee80211_deliver_skb+0xd6/0x270 [mac80211]
++         ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
++         ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
++         ieee80211_rx+0x31d/0x900 [mac80211]
++         iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
++         iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
++         iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
++         irq_thread_fn+0x20/0x50
++         irq_thread+0x11f/0x150
++         kthread+0xd2/0xf0
++         ret_from_fork+0x42/0x70
++    } hitcount:         85  len:      28884
++    { stacktrace:
++         __netif_receive_skb_core+0x46d/0x990
++         __netif_receive_skb+0x18/0x60
++         netif_receive_skb_internal+0x23/0x90
++         napi_gro_complete+0xa4/0xe0
++         dev_gro_receive+0x23a/0x360
++         napi_gro_receive+0x30/0x100
++         ieee80211_deliver_skb+0xd6/0x270 [mac80211]
++         ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
++         ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
++         ieee80211_rx+0x31d/0x900 [mac80211]
++         iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
++         iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
++         iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
++         irq_thread_fn+0x20/0x50
++         irq_thread+0x11f/0x150
++         kthread+0xd2/0xf0
++    } hitcount:         98  len:     664329
++    { stacktrace:
++         __netif_receive_skb_core+0x46d/0x990
++         __netif_receive_skb+0x18/0x60
++         process_backlog+0xa8/0x150
++         net_rx_action+0x15d/0x340
++         __do_softirq+0x114/0x2c0
++         do_softirq_own_stack+0x1c/0x30
++         do_softirq+0x65/0x70
++         __local_bh_enable_ip+0xb5/0xc0
++         ip_finish_output+0x1f4/0x840
++         ip_output+0x6b/0xc0
++         ip_local_out_sk+0x31/0x40
++         ip_send_skb+0x1a/0x50
++         udp_send_skb+0x173/0x2a0
++         udp_sendmsg+0x2bf/0x9f0
++         inet_sendmsg+0x64/0xa0
++         sock_sendmsg+0x3d/0x50
++    } hitcount:        115  len:      13030
++    { stacktrace:
++         __netif_receive_skb_core+0x46d/0x990
++         __netif_receive_skb+0x18/0x60
++         netif_receive_skb_internal+0x23/0x90
++         napi_gro_complete+0xa4/0xe0
++         napi_gro_flush+0x6d/0x90
++         iwl_pcie_irq_handler+0x92a/0x12f0 [iwlwifi]
++         irq_thread_fn+0x20/0x50
++         irq_thread+0x11f/0x150
++         kthread+0xd2/0xf0
++         ret_from_fork+0x42/0x70
++    } hitcount:        934  len:    5512212
++
++    Totals:
++        Hits: 1232
++        Entries: 4
++        Dropped: 0
++
++  The above shows all the netif_receive_skb callpaths and their total
++  lengths for the duration of the wget command.
++
++  The 'clear' hist trigger param can be used to clear the hash table.
++  Suppose we wanted to try another run of the previous example but
++  this time also wanted to see the complete list of events that went
++  into the histogram.  In order to avoid having to set everything up
++  again, we can just clear the histogram first:
++
++    # echo 'hist:key=stacktrace:vals=len:clear' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++
++  Just to verify that it is in fact cleared, here's what we now see in
++  the hist file:
++
++    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
++    # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
++
++    Totals:
++        Hits: 0
++        Entries: 0
++        Dropped: 0
++
++  Since we want to see the detailed list of every netif_receive_skb
++  event occurring during the new run, which are in fact the same
++  events being aggregated into the hash table, we add some additional
++  'enable_event' events to the triggering sched_process_exec and
++  sched_process_exit events as such:
++
++    # echo 'enable_event:net:netif_receive_skb if filename==/usr/bin/wget' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
++
++    # echo 'disable_event:net:netif_receive_skb if comm==wget' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
++
++  If you read the trigger files for the sched_process_exec and
++  sched_process_exit triggers, you should see two triggers for each:
++  one enabling/disabling the hist aggregation and the other
++  enabling/disabling the logging of events:
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
++    enable_event:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
++    enable_hist:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
++    enable_event:net:netif_receive_skb:unlimited if comm==wget
++    disable_hist:net:netif_receive_skb:unlimited if comm==wget
++
++  In other words, whenever either of the sched_process_exec or
++  sched_process_exit events is hit and matches 'wget', it enables or
++  disables both the histogram and the event log, and what you end up
++  with is a hash table and set of events just covering the specified
++  duration.  Run the wget command again:
++
++    $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
++
++  Displaying the 'hist' file should show something similar to what you
++  saw in the last run, but this time you should also see the
++  individual events in the trace file:
++
++    # cat /sys/kernel/debug/tracing/trace
++
++    # tracer: nop
++    #
++    # entries-in-buffer/entries-written: 183/1426   #P:4
++    #
++    #                              _-----=> irqs-off
++    #                             / _----=> need-resched
++    #                            | / _---=> hardirq/softirq
++    #                            || / _--=> preempt-depth
++    #                            ||| /     delay
++    #           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
++    #              | |       |   ||||       |         |
++                wget-15108 [000] ..s1 31769.606929: netif_receive_skb: dev=lo skbaddr=ffff88009c353100 len=60
++                wget-15108 [000] ..s1 31769.606999: netif_receive_skb: dev=lo skbaddr=ffff88009c353200 len=60
++             dnsmasq-1382  [000] ..s1 31769.677652: netif_receive_skb: dev=lo skbaddr=ffff88009c352b00 len=130
++             dnsmasq-1382  [000] ..s1 31769.685917: netif_receive_skb: dev=lo skbaddr=ffff88009c352200 len=138
++    ##### CPU 2 buffer started ####
++      irq/29-iwlwifi-559   [002] ..s. 31772.031529: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433d00 len=2948
++      irq/29-iwlwifi-559   [002] ..s. 31772.031572: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432200 len=1500
++      irq/29-iwlwifi-559   [002] ..s. 31772.032196: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433100 len=2948
++      irq/29-iwlwifi-559   [002] ..s. 31772.032761: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433000 len=2948
++      irq/29-iwlwifi-559   [002] ..s. 31772.033220: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432e00 len=1500
++    .
++    .
++    .
++
++  The following example demonstrates how multiple hist triggers can be
++  attached to a given event.  This capability can be useful for
++  creating a set of different summaries derived from the same set of
++  events, or for comparing the effects of different filters, among
++  other things.
++
++    # echo 'hist:keys=skbaddr.hex:vals=len if len < 0' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++    # echo 'hist:keys=skbaddr.hex:vals=len if len > 4096' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++    # echo 'hist:keys=skbaddr.hex:vals=len if len == 256' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++    # echo 'hist:keys=skbaddr.hex:vals=len' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++    # echo 'hist:keys=len:vals=common_preempt_count' >> \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++
++  The above set of commands create four triggers differing only in
++  their filters, along with a completely different though fairly
++  nonsensical trigger.  Note that in order to append multiple hist
++  triggers to the same file, you should use the '>>' operator to
++  append them ('>' will also add the new hist trigger, but will remove
++  any existing hist triggers beforehand).
++
++  Displaying the contents of the 'hist' file for the event shows the
++  contents of all five histograms:
++
++    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
++
++    # event histogram
++    #
++    # trigger info: hist:keys=len:vals=hitcount,common_preempt_count:sort=hitcount:size=2048 [active]
++    #
++
++    { len:        176 } hitcount:          1  common_preempt_count:          0
++    { len:        223 } hitcount:          1  common_preempt_count:          0
++    { len:       4854 } hitcount:          1  common_preempt_count:          0
++    { len:        395 } hitcount:          1  common_preempt_count:          0
++    { len:        177 } hitcount:          1  common_preempt_count:          0
++    { len:        446 } hitcount:          1  common_preempt_count:          0
++    { len:       1601 } hitcount:          1  common_preempt_count:          0
++    .
++    .
++    .
++    { len:       1280 } hitcount:         66  common_preempt_count:          0
++    { len:        116 } hitcount:         81  common_preempt_count:         40
++    { len:        708 } hitcount:        112  common_preempt_count:          0
++    { len:         46 } hitcount:        221  common_preempt_count:          0
++    { len:       1264 } hitcount:        458  common_preempt_count:          0
++
++    Totals:
++        Hits: 1428
++        Entries: 147
++        Dropped: 0
++
++
++    # event histogram
++    #
++    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
++    #
++
++    { skbaddr: ffff8800baee5e00 } hitcount:          1  len:        130
++    { skbaddr: ffff88005f3d5600 } hitcount:          1  len:       1280
++    { skbaddr: ffff88005f3d4900 } hitcount:          1  len:       1280
++    { skbaddr: ffff88009fed6300 } hitcount:          1  len:        115
++    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:        115
++    { skbaddr: ffff88008cdb1900 } hitcount:          1  len:         46
++    { skbaddr: ffff880064b5ef00 } hitcount:          1  len:        118
++    { skbaddr: ffff880044e3c700 } hitcount:          1  len:         60
++    { skbaddr: ffff880100065900 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d46bd500 } hitcount:          1  len:        116
++    { skbaddr: ffff88005f3d5f00 } hitcount:          1  len:       1280
++    { skbaddr: ffff880100064700 } hitcount:          1  len:        365
++    { skbaddr: ffff8800badb6f00 } hitcount:          1  len:         60
++    .
++    .
++    .
++    { skbaddr: ffff88009fe0be00 } hitcount:         27  len:      24677
++    { skbaddr: ffff88009fe0a400 } hitcount:         27  len:      23052
++    { skbaddr: ffff88009fe0b700 } hitcount:         31  len:      25589
++    { skbaddr: ffff88009fe0b600 } hitcount:         32  len:      27326
++    { skbaddr: ffff88006a462800 } hitcount:         68  len:      71678
++    { skbaddr: ffff88006a463700 } hitcount:         70  len:      72678
++    { skbaddr: ffff88006a462b00 } hitcount:         71  len:      77589
++    { skbaddr: ffff88006a463600 } hitcount:         73  len:      71307
++    { skbaddr: ffff88006a462200 } hitcount:         81  len:      81032
++
++    Totals:
++        Hits: 1451
++        Entries: 318
++        Dropped: 0
++
++
++    # event histogram
++    #
++    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len == 256 [active]
++    #
++
++
++    Totals:
++        Hits: 0
++        Entries: 0
++        Dropped: 0
++
++
++    # event histogram
++    #
++    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len > 4096 [active]
++    #
++
++    { skbaddr: ffff88009fd2c300 } hitcount:          1  len:       7212
++    { skbaddr: ffff8800d2bcce00 } hitcount:          1  len:       7212
++    { skbaddr: ffff8800d2bcd700 } hitcount:          1  len:       7212
++    { skbaddr: ffff8800d2bcda00 } hitcount:          1  len:      21492
++    { skbaddr: ffff8800ae2e2d00 } hitcount:          1  len:       7212
++    { skbaddr: ffff8800d2bcdb00 } hitcount:          1  len:       7212
++    { skbaddr: ffff88006a4df500 } hitcount:          1  len:       4854
++    { skbaddr: ffff88008ce47b00 } hitcount:          1  len:      18636
++    { skbaddr: ffff8800ae2e2200 } hitcount:          1  len:      12924
++    { skbaddr: ffff88005f3e1000 } hitcount:          1  len:       4356
++    { skbaddr: ffff8800d2bcdc00 } hitcount:          2  len:      24420
++    { skbaddr: ffff8800d2bcc200 } hitcount:          2  len:      12996
++
++    Totals:
++        Hits: 14
++        Entries: 12
++        Dropped: 0
++
++
++    # event histogram
++    #
++    # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len < 0 [active]
++    #
++
++
++    Totals:
++        Hits: 0
++        Entries: 0
++        Dropped: 0
++
++  Named triggers can be used to have triggers share a common set of
++  histogram data.  This capability is mostly useful for combining the
++  output of events generated by tracepoints contained inside inline
++  functions, but names can be used in a hist trigger on any event.
++  For example, these two triggers when hit will update the same 'len'
++  field in the shared 'foo' histogram data:
++
++    # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
++           /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
++    # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
++           /sys/kernel/debug/tracing/events/net/netif_rx/trigger
++
++  You can see that they're updating common histogram data by reading
++  each event's hist files at the same time:
++
++    # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist;
++      cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
++
++    # event histogram
++    #
++    # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
++    #
++
++    { skbaddr: ffff88000ad53500 } hitcount:          1  len:         46
++    { skbaddr: ffff8800af5a1500 } hitcount:          1  len:         76
++    { skbaddr: ffff8800d62a1900 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bccb00 } hitcount:          1  len:        468
++    { skbaddr: ffff8800d3c69900 } hitcount:          1  len:         46
++    { skbaddr: ffff88009ff09100 } hitcount:          1  len:         52
++    { skbaddr: ffff88010f13ab00 } hitcount:          1  len:        168
++    { skbaddr: ffff88006a54f400 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcc500 } hitcount:          1  len:        260
++    { skbaddr: ffff880064505000 } hitcount:          1  len:         46
++    { skbaddr: ffff8800baf24e00 } hitcount:          1  len:         32
++    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d3edff00 } hitcount:          1  len:         44
++    { skbaddr: ffff88009fe0b400 } hitcount:          1  len:        168
++    { skbaddr: ffff8800a1c55a00 } hitcount:          1  len:         40
++    { skbaddr: ffff8800d2bcd100 } hitcount:          1  len:         40
++    { skbaddr: ffff880064505f00 } hitcount:          1  len:        174
++    { skbaddr: ffff8800a8bff200 } hitcount:          1  len:        160
++    { skbaddr: ffff880044e3cc00 } hitcount:          1  len:         76
++    { skbaddr: ffff8800a8bfe700 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcdc00 } hitcount:          1  len:         32
++    { skbaddr: ffff8800a1f64800 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcde00 } hitcount:          1  len:        988
++    { skbaddr: ffff88006a5dea00 } hitcount:          1  len:         46
++    { skbaddr: ffff88002e37a200 } hitcount:          1  len:         44
++    { skbaddr: ffff8800a1f32c00 } hitcount:          2  len:        676
++    { skbaddr: ffff88000ad52600 } hitcount:          2  len:        107
++    { skbaddr: ffff8800a1f91e00 } hitcount:          2  len:         92
++    { skbaddr: ffff8800af5a0200 } hitcount:          2  len:        142
++    { skbaddr: ffff8800d2bcc600 } hitcount:          2  len:        220
++    { skbaddr: ffff8800ba36f500 } hitcount:          2  len:         92
++    { skbaddr: ffff8800d021f800 } hitcount:          2  len:         92
++    { skbaddr: ffff8800a1f33600 } hitcount:          2  len:        675
++    { skbaddr: ffff8800a8bfff00 } hitcount:          3  len:        138
++    { skbaddr: ffff8800d62a1300 } hitcount:          3  len:        138
++    { skbaddr: ffff88002e37a100 } hitcount:          4  len:        184
++    { skbaddr: ffff880064504400 } hitcount:          4  len:        184
++    { skbaddr: ffff8800a8bfec00 } hitcount:          4  len:        184
++    { skbaddr: ffff88000ad53700 } hitcount:          5  len:        230
++    { skbaddr: ffff8800d2bcdb00 } hitcount:          5  len:        196
++    { skbaddr: ffff8800a1f90000 } hitcount:          6  len:        276
++    { skbaddr: ffff88006a54f900 } hitcount:          6  len:        276
++
++    Totals:
++        Hits: 81
++        Entries: 42
++        Dropped: 0
++    # event histogram
++    #
++    # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
++    #
++
++    { skbaddr: ffff88000ad53500 } hitcount:          1  len:         46
++    { skbaddr: ffff8800af5a1500 } hitcount:          1  len:         76
++    { skbaddr: ffff8800d62a1900 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bccb00 } hitcount:          1  len:        468
++    { skbaddr: ffff8800d3c69900 } hitcount:          1  len:         46
++    { skbaddr: ffff88009ff09100 } hitcount:          1  len:         52
++    { skbaddr: ffff88010f13ab00 } hitcount:          1  len:        168
++    { skbaddr: ffff88006a54f400 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcc500 } hitcount:          1  len:        260
++    { skbaddr: ffff880064505000 } hitcount:          1  len:         46
++    { skbaddr: ffff8800baf24e00 } hitcount:          1  len:         32
++    { skbaddr: ffff88009fe0ad00 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d3edff00 } hitcount:          1  len:         44
++    { skbaddr: ffff88009fe0b400 } hitcount:          1  len:        168
++    { skbaddr: ffff8800a1c55a00 } hitcount:          1  len:         40
++    { skbaddr: ffff8800d2bcd100 } hitcount:          1  len:         40
++    { skbaddr: ffff880064505f00 } hitcount:          1  len:        174
++    { skbaddr: ffff8800a8bff200 } hitcount:          1  len:        160
++    { skbaddr: ffff880044e3cc00 } hitcount:          1  len:         76
++    { skbaddr: ffff8800a8bfe700 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcdc00 } hitcount:          1  len:         32
++    { skbaddr: ffff8800a1f64800 } hitcount:          1  len:         46
++    { skbaddr: ffff8800d2bcde00 } hitcount:          1  len:        988
++    { skbaddr: ffff88006a5dea00 } hitcount:          1  len:         46
++    { skbaddr: ffff88002e37a200 } hitcount:          1  len:         44
++    { skbaddr: ffff8800a1f32c00 } hitcount:          2  len:        676
++    { skbaddr: ffff88000ad52600 } hitcount:          2  len:        107
++    { skbaddr: ffff8800a1f91e00 } hitcount:          2  len:         92
++    { skbaddr: ffff8800af5a0200 } hitcount:          2  len:        142
++    { skbaddr: ffff8800d2bcc600 } hitcount:          2  len:        220
++    { skbaddr: ffff8800ba36f500 } hitcount:          2  len:         92
++    { skbaddr: ffff8800d021f800 } hitcount:          2  len:         92
++    { skbaddr: ffff8800a1f33600 } hitcount:          2  len:        675
++    { skbaddr: ffff8800a8bfff00 } hitcount:          3  len:        138
++    { skbaddr: ffff8800d62a1300 } hitcount:          3  len:        138
++    { skbaddr: ffff88002e37a100 } hitcount:          4  len:        184
++    { skbaddr: ffff880064504400 } hitcount:          4  len:        184
++    { skbaddr: ffff8800a8bfec00 } hitcount:          4  len:        184
++    { skbaddr: ffff88000ad53700 } hitcount:          5  len:        230
++    { skbaddr: ffff8800d2bcdb00 } hitcount:          5  len:        196
++    { skbaddr: ffff8800a1f90000 } hitcount:          6  len:        276
++    { skbaddr: ffff88006a54f900 } hitcount:          6  len:        276
++
++    Totals:
++        Hits: 81
++        Entries: 42
++        Dropped: 0
++
++  And here's an example that shows how to combine histogram data from
++  any two events even if they don't share any 'compatible' fields
++  other than 'hitcount' and 'stacktrace'.  These commands create a
++  couple of triggers named 'bar' using those fields:
++
++    # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
++           /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
++    # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
++          /sys/kernel/debug/tracing/events/net/netif_rx/trigger
++
++  And displaying the output of either shows some interesting if
++  somewhat confusing output:
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
++    # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
++
++    # event histogram
++    #
++    # trigger info: hist:name=bar:keys=stacktrace:vals=hitcount:sort=hitcount:size=2048 [active]
++    #
++
++    { stacktrace:
++             _do_fork+0x18e/0x330
++             kernel_thread+0x29/0x30
++             kthreadd+0x154/0x1b0
++             ret_from_fork+0x3f/0x70
++    } hitcount:          1
++    { stacktrace:
++             netif_rx_internal+0xb2/0xd0
++             netif_rx_ni+0x20/0x70
++             dev_loopback_xmit+0xaa/0xd0
++             ip_mc_output+0x126/0x240
++             ip_local_out_sk+0x31/0x40
++             igmp_send_report+0x1e9/0x230
++             igmp_timer_expire+0xe9/0x120
++             call_timer_fn+0x39/0xf0
++             run_timer_softirq+0x1e1/0x290
++             __do_softirq+0xfd/0x290
++             irq_exit+0x98/0xb0
++             smp_apic_timer_interrupt+0x4a/0x60
++             apic_timer_interrupt+0x6d/0x80
++             cpuidle_enter+0x17/0x20
++             call_cpuidle+0x3b/0x60
++             cpu_startup_entry+0x22d/0x310
++    } hitcount:          1
++    { stacktrace:
++             netif_rx_internal+0xb2/0xd0
++             netif_rx_ni+0x20/0x70
++             dev_loopback_xmit+0xaa/0xd0
++             ip_mc_output+0x17f/0x240
++             ip_local_out_sk+0x31/0x40
++             ip_send_skb+0x1a/0x50
++             udp_send_skb+0x13e/0x270
++             udp_sendmsg+0x2bf/0x980
++             inet_sendmsg+0x67/0xa0
++             sock_sendmsg+0x38/0x50
++             SYSC_sendto+0xef/0x170
++             SyS_sendto+0xe/0x10
++             entry_SYSCALL_64_fastpath+0x12/0x6a
++    } hitcount:          2
++    { stacktrace:
++             netif_rx_internal+0xb2/0xd0
++             netif_rx+0x1c/0x60
++             loopback_xmit+0x6c/0xb0
++             dev_hard_start_xmit+0x219/0x3a0
++             __dev_queue_xmit+0x415/0x4f0
++             dev_queue_xmit_sk+0x13/0x20
++             ip_finish_output2+0x237/0x340
++             ip_finish_output+0x113/0x1d0
++             ip_output+0x66/0xc0
++             ip_local_out_sk+0x31/0x40
++             ip_send_skb+0x1a/0x50
++             udp_send_skb+0x16d/0x270
++             udp_sendmsg+0x2bf/0x980
++             inet_sendmsg+0x67/0xa0
++             sock_sendmsg+0x38/0x50
++             ___sys_sendmsg+0x14e/0x270
++    } hitcount:         76
++    { stacktrace:
++             netif_rx_internal+0xb2/0xd0
++             netif_rx+0x1c/0x60
++             loopback_xmit+0x6c/0xb0
++             dev_hard_start_xmit+0x219/0x3a0
++             __dev_queue_xmit+0x415/0x4f0
++             dev_queue_xmit_sk+0x13/0x20
++             ip_finish_output2+0x237/0x340
++             ip_finish_output+0x113/0x1d0
++             ip_output+0x66/0xc0
++             ip_local_out_sk+0x31/0x40
++             ip_send_skb+0x1a/0x50
++             udp_send_skb+0x16d/0x270
++             udp_sendmsg+0x2bf/0x980
++             inet_sendmsg+0x67/0xa0
++             sock_sendmsg+0x38/0x50
++             ___sys_sendmsg+0x269/0x270
++    } hitcount:         77
++    { stacktrace:
++             netif_rx_internal+0xb2/0xd0
++             netif_rx+0x1c/0x60
++             loopback_xmit+0x6c/0xb0
++             dev_hard_start_xmit+0x219/0x3a0
++             __dev_queue_xmit+0x415/0x4f0
++             dev_queue_xmit_sk+0x13/0x20
++             ip_finish_output2+0x237/0x340
++             ip_finish_output+0x113/0x1d0
++             ip_output+0x66/0xc0
++             ip_local_out_sk+0x31/0x40
++             ip_send_skb+0x1a/0x50
++             udp_send_skb+0x16d/0x270
++             udp_sendmsg+0x2bf/0x980
++             inet_sendmsg+0x67/0xa0
++             sock_sendmsg+0x38/0x50
++             SYSC_sendto+0xef/0x170
++    } hitcount:         88
++    { stacktrace:
++             _do_fork+0x18e/0x330
++             SyS_clone+0x19/0x20
++             entry_SYSCALL_64_fastpath+0x12/0x6a
++    } hitcount:        244
++
++    Totals:
++        Hits: 489
++        Entries: 7
++        Dropped: 0
+-- 
+2.19.0
+
diff --git a/patches/1758-tracing-Add-Documentation-for-log2-modifier.patch b/patches/1758-tracing-Add-Documentation-for-log2-modifier.patch
new file mode 100644
index 00000000000000..e30a746f6620a8
--- /dev/null
+++ b/patches/1758-tracing-Add-Documentation-for-log2-modifier.patch
@@ -0,0 +1,34 @@
+From f841d937da8f4656644c5f39e598cc180e5694ac Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:36 -0600
+Subject: [PATCH 1758/1795] tracing: Add Documentation for log2 modifier
+
+Add a line for the log2 modifier, to keep it aligned with
+tracing/README.
+
+Link: http://lkml.kernel.org/r/a419028bccab155749a4b8702d5b97af75f1578f.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 442c9484619085bd2b7c92efad5189dadd71ab2a)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index b2145f44b190..a4143f04a097 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -73,6 +73,7 @@
+ 	.sym-offset display an address as a symbol and offset
+ 	.syscall    display a syscall id as a system call name
+ 	.execname   display a common_pid as a program name
++	.log2       display log2 value rather than raw number
+ 
+   Note that in general the semantics of a given field aren't
+   interpreted when applying a modifier to it, but there are some
+-- 
+2.19.0
+
diff --git a/patches/1759-tracing-Add-usecs-modifier-for-hist-trigger-timestam.patch b/patches/1759-tracing-Add-usecs-modifier-for-hist-trigger-timestam.patch
new file mode 100644
index 00000000000000..8c6b8bc422d879
--- /dev/null
+++ b/patches/1759-tracing-Add-usecs-modifier-for-hist-trigger-timestam.patch
@@ -0,0 +1,171 @@
+From d498eca487ed0db484db90e7bb9b412202638853 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:48 -0600
+Subject: [PATCH 1759/1795] tracing: Add usecs modifier for hist trigger
+ timestamps
+
+Appending .usecs onto a common_timestamp field will cause the
+timestamp value to be in microseconds instead of the default
+nanoseconds.  A typical latency histogram using usecs would look like
+this:
+
+   # echo 'hist:keys=pid,prio:ts0=common_timestamp.usecs ...
+   # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0 ...
+
+This also adds an external trace_clock_in_ns() to trace.c for the
+timestamp conversion.
+
+Link: http://lkml.kernel.org/r/4e813705a170b3e13e97dc3135047362fb1a39f3.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 860f9f6b02e9e846c4cfb3505efed331a910d0b7)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt |  1 +
+ kernel/trace/trace.c              | 13 +++++++++++--
+ kernel/trace/trace.h              |  2 ++
+ kernel/trace/trace_events_hist.c  | 28 ++++++++++++++++++++++------
+ 4 files changed, 36 insertions(+), 8 deletions(-)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index a4143f04a097..25c94730d3fe 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -74,6 +74,7 @@
+ 	.syscall    display a syscall id as a system call name
+ 	.execname   display a common_pid as a program name
+ 	.log2       display log2 value rather than raw number
++	.usecs      display a common_timestamp in microseconds
+ 
+   Note that in general the semantics of a given field aren't
+   interpreted when applying a modifier to it, but there are some
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index 0359ff7ba906..0c8a697d8442 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -1170,6 +1170,14 @@ static struct {
+ 	ARCH_TRACE_CLOCKS
+ };
+ 
++bool trace_clock_in_ns(struct trace_array *tr)
++{
++	if (trace_clocks[tr->clock_id].in_ns)
++		return true;
++
++	return false;
++}
++
+ /*
+  * trace_parser_get_init - gets the buffer for trace parser
+  */
+@@ -4707,8 +4715,9 @@ static const char readme_msg[] =
+ 	"\t            .sym        display an address as a symbol\n"
+ 	"\t            .sym-offset display an address as a symbol and offset\n"
+ 	"\t            .execname   display a common_pid as a program name\n"
+-	"\t            .syscall    display a syscall id as a syscall name\n\n"
+-	"\t            .log2       display log2 value rather than raw number\n\n"
++	"\t            .syscall    display a syscall id as a syscall name\n"
++	"\t            .log2       display log2 value rather than raw number\n"
++	"\t            .usecs      display a common_timestamp in microseconds\n\n"
+ 	"\t    The 'pause' parameter can be used to pause an existing hist\n"
+ 	"\t    trigger or to start a hist trigger but not log any events\n"
+ 	"\t    until told to do so.  'continue' can be used to start or\n"
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 5f1d4ae594e5..a94cc69b8a4a 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -289,6 +289,8 @@ extern void trace_array_put(struct trace_array *tr);
+ 
+ extern int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs);
+ 
++extern bool trace_clock_in_ns(struct trace_array *tr);
++
+ /*
+  * The global tracer (top) should be the first trace array added,
+  * but we check the flag anyway.
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 77ebe6b410ba..7f5f0b8f6558 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -90,12 +90,6 @@ static u64 hist_field_log2(struct hist_field *hist_field, void *event,
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+ 
+-static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
+-				struct ring_buffer_event *rbe)
+-{
+-	return ring_buffer_event_time_stamp(rbe);
+-}
+-
+ #define DEFINE_HIST_FIELD_FN(type)					\
+ 	static u64 hist_field_##type(struct hist_field *hist_field,	\
+ 				     void *event,			\
+@@ -143,6 +137,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_STACKTRACE	= 1 << 8,
+ 	HIST_FIELD_FL_LOG2		= 1 << 9,
+ 	HIST_FIELD_FL_TIMESTAMP		= 1 << 10,
++	HIST_FIELD_FL_TIMESTAMP_USECS	= 1 << 11,
+ };
+ 
+ struct hist_trigger_attrs {
+@@ -153,6 +148,7 @@ struct hist_trigger_attrs {
+ 	bool		pause;
+ 	bool		cont;
+ 	bool		clear;
++	bool		ts_in_usecs;
+ 	unsigned int	map_bits;
+ };
+ 
+@@ -170,6 +166,20 @@ struct hist_trigger_data {
+ 	bool				enable_timestamps;
+ };
+ 
++static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
++				struct ring_buffer_event *rbe)
++{
++	struct hist_trigger_data *hist_data = hist_field->hist_data;
++	struct trace_array *tr = hist_data->event_file->tr;
++
++	u64 ts = ring_buffer_event_time_stamp(rbe);
++
++	if (hist_data->attrs->ts_in_usecs && trace_clock_in_ns(tr))
++		ts = ns2usecs(ts);
++
++	return ts;
++}
++
+ static const char *hist_field_name(struct hist_field *field,
+ 				   unsigned int level)
+ {
+@@ -634,6 +644,8 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 				flags |= HIST_FIELD_FL_SYSCALL;
+ 			else if (strcmp(field_str, "log2") == 0)
+ 				flags |= HIST_FIELD_FL_LOG2;
++			else if (strcmp(field_str, "usecs") == 0)
++				flags |= HIST_FIELD_FL_TIMESTAMP_USECS;
+ 			else {
+ 				ret = -EINVAL;
+ 				goto out;
+@@ -643,6 +655,8 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 		if (strcmp(field_name, "common_timestamp") == 0) {
+ 			flags |= HIST_FIELD_FL_TIMESTAMP;
+ 			hist_data->enable_timestamps = true;
++			if (flags & HIST_FIELD_FL_TIMESTAMP_USECS)
++				hist_data->attrs->ts_in_usecs = true;
+ 			key_size = sizeof(u64);
+ 		} else {
+ 			field = trace_find_event_field(file->event_call, field_name);
+@@ -1241,6 +1255,8 @@ static const char *get_hist_field_flags(struct hist_field *hist_field)
+ 		flags_str = "syscall";
+ 	else if (hist_field->flags & HIST_FIELD_FL_LOG2)
+ 		flags_str = "log2";
++	else if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP_USECS)
++		flags_str = "usecs";
+ 
+ 	return flags_str;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1760-tracing-Add-per-element-variable-support-to-tracing_.patch b/patches/1760-tracing-Add-per-element-variable-support-to-tracing_.patch
new file mode 100644
index 00000000000000..336cf2965dacc9
--- /dev/null
+++ b/patches/1760-tracing-Add-per-element-variable-support-to-tracing_.patch
@@ -0,0 +1,233 @@
+From 8fcb5a950ff67b15c0f4b7f23d7719ce165047dd Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:46 -0600
+Subject: [PATCH 1760/1795] tracing: Add per-element variable support to
+ tracing_map
+
+In order to allow information to be passed between trace events, add
+support for per-element variables to tracing_map.  This provides a
+means for histograms to associate a value or values with an entry when
+it's saved or updated, and retrieved by a subsequent event occurrences.
+
+Variables can be set using tracing_map_set_var() and read using
+tracing_map_read_var().  tracing_map_var_set() returns true or false
+depending on whether or not the variable has been set or not, which is
+important for event-matching applications.
+
+tracing_map_read_var_once() reads the variable and resets it to the
+'unset' state, implementing read-once variables, which are also
+important for event-matching uses.
+
+Link: http://lkml.kernel.org/r/7fa001108252556f0c6dd9d63145eabfe3370d1a.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 2734b629525a9dae5bf217cbf0a9651da93d2108)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/tracing_map.c | 108 +++++++++++++++++++++++++++++++++++++
+ kernel/trace/tracing_map.h |  11 ++++
+ 2 files changed, 119 insertions(+)
+
+diff --git a/kernel/trace/tracing_map.c b/kernel/trace/tracing_map.c
+index 8d9feee50dab..28e4200a3401 100644
+--- a/kernel/trace/tracing_map.c
++++ b/kernel/trace/tracing_map.c
+@@ -66,6 +66,73 @@ u64 tracing_map_read_sum(struct tracing_map_elt *elt, unsigned int i)
+ 	return (u64)atomic64_read(&elt->fields[i].sum);
+ }
+ 
++/**
++ * tracing_map_set_var - Assign a tracing_map_elt's variable field
++ * @elt: The tracing_map_elt
++ * @i: The index of the given variable associated with the tracing_map_elt
++ * @n: The value to assign
++ *
++ * Assign n to variable i associated with the specified tracing_map_elt
++ * instance.  The index i is the index returned by the call to
++ * tracing_map_add_var() when the tracing map was set up.
++ */
++void tracing_map_set_var(struct tracing_map_elt *elt, unsigned int i, u64 n)
++{
++	atomic64_set(&elt->vars[i], n);
++	elt->var_set[i] = true;
++}
++
++/**
++ * tracing_map_var_set - Return whether or not a variable has been set
++ * @elt: The tracing_map_elt
++ * @i: The index of the given variable associated with the tracing_map_elt
++ *
++ * Return true if the variable has been set, false otherwise.  The
++ * index i is the index returned by the call to tracing_map_add_var()
++ * when the tracing map was set up.
++ */
++bool tracing_map_var_set(struct tracing_map_elt *elt, unsigned int i)
++{
++	return elt->var_set[i];
++}
++
++/**
++ * tracing_map_read_var - Return the value of a tracing_map_elt's variable field
++ * @elt: The tracing_map_elt
++ * @i: The index of the given variable associated with the tracing_map_elt
++ *
++ * Retrieve the value of the variable i associated with the specified
++ * tracing_map_elt instance.  The index i is the index returned by the
++ * call to tracing_map_add_var() when the tracing map was set
++ * up.
++ *
++ * Return: The variable value associated with field i for elt.
++ */
++u64 tracing_map_read_var(struct tracing_map_elt *elt, unsigned int i)
++{
++	return (u64)atomic64_read(&elt->vars[i]);
++}
++
++/**
++ * tracing_map_read_var_once - Return and reset a tracing_map_elt's variable field
++ * @elt: The tracing_map_elt
++ * @i: The index of the given variable associated with the tracing_map_elt
++ *
++ * Retrieve the value of the variable i associated with the specified
++ * tracing_map_elt instance, and reset the variable to the 'not set'
++ * state.  The index i is the index returned by the call to
++ * tracing_map_add_var() when the tracing map was set up.  The reset
++ * essentially makes the variable a read-once variable if it's only
++ * accessed using this function.
++ *
++ * Return: The variable value associated with field i for elt.
++ */
++u64 tracing_map_read_var_once(struct tracing_map_elt *elt, unsigned int i)
++{
++	elt->var_set[i] = false;
++	return (u64)atomic64_read(&elt->vars[i]);
++}
++
+ int tracing_map_cmp_string(void *val_a, void *val_b)
+ {
+ 	char *a = val_a;
+@@ -170,6 +237,28 @@ int tracing_map_add_sum_field(struct tracing_map *map)
+ 	return tracing_map_add_field(map, tracing_map_cmp_atomic64);
+ }
+ 
++/**
++ * tracing_map_add_var - Add a field describing a tracing_map var
++ * @map: The tracing_map
++ *
++ * Add a var to the map and return the index identifying it in the map
++ * and associated tracing_map_elts.  This is the index used for
++ * instance to update a var for a particular tracing_map_elt using
++ * tracing_map_update_var() or reading it via tracing_map_read_var().
++ *
++ * Return: The index identifying the var in the map and associated
++ * tracing_map_elts, or -EINVAL on error.
++ */
++int tracing_map_add_var(struct tracing_map *map)
++{
++	int ret = -EINVAL;
++
++	if (map->n_vars < TRACING_MAP_VARS_MAX)
++		ret = map->n_vars++;
++
++	return ret;
++}
++
+ /**
+  * tracing_map_add_key_field - Add a field describing a tracing_map key
+  * @map: The tracing_map
+@@ -280,6 +369,11 @@ static void tracing_map_elt_clear(struct tracing_map_elt *elt)
+ 		if (elt->fields[i].cmp_fn == tracing_map_cmp_atomic64)
+ 			atomic64_set(&elt->fields[i].sum, 0);
+ 
++	for (i = 0; i < elt->map->n_vars; i++) {
++		atomic64_set(&elt->vars[i], 0);
++		elt->var_set[i] = false;
++	}
++
+ 	if (elt->map->ops && elt->map->ops->elt_clear)
+ 		elt->map->ops->elt_clear(elt);
+ }
+@@ -306,6 +400,8 @@ static void tracing_map_elt_free(struct tracing_map_elt *elt)
+ 	if (elt->map->ops && elt->map->ops->elt_free)
+ 		elt->map->ops->elt_free(elt);
+ 	kfree(elt->fields);
++	kfree(elt->vars);
++	kfree(elt->var_set);
+ 	kfree(elt->key);
+ 	kfree(elt);
+ }
+@@ -333,6 +429,18 @@ static struct tracing_map_elt *tracing_map_elt_alloc(struct tracing_map *map)
+ 		goto free;
+ 	}
+ 
++	elt->vars = kcalloc(map->n_vars, sizeof(*elt->vars), GFP_KERNEL);
++	if (!elt->vars) {
++		err = -ENOMEM;
++		goto free;
++	}
++
++	elt->var_set = kcalloc(map->n_vars, sizeof(*elt->var_set), GFP_KERNEL);
++	if (!elt->var_set) {
++		err = -ENOMEM;
++		goto free;
++	}
++
+ 	tracing_map_elt_init_fields(elt);
+ 
+ 	if (map->ops && map->ops->elt_alloc) {
+diff --git a/kernel/trace/tracing_map.h b/kernel/trace/tracing_map.h
+index 0de50bbc1c51..9a063dfb2fff 100644
+--- a/kernel/trace/tracing_map.h
++++ b/kernel/trace/tracing_map.h
+@@ -10,6 +10,7 @@
+ #define TRACING_MAP_VALS_MAX		3
+ #define TRACING_MAP_FIELDS_MAX		(TRACING_MAP_KEYS_MAX + \
+ 					 TRACING_MAP_VALS_MAX)
++#define TRACING_MAP_VARS_MAX		16
+ #define TRACING_MAP_SORT_KEYS_MAX	2
+ 
+ typedef int (*tracing_map_cmp_fn_t) (void *val_a, void *val_b);
+@@ -137,6 +138,8 @@ struct tracing_map_field {
+ struct tracing_map_elt {
+ 	struct tracing_map		*map;
+ 	struct tracing_map_field	*fields;
++	atomic64_t			*vars;
++	bool				*var_set;
+ 	void				*key;
+ 	void				*private_data;
+ };
+@@ -192,6 +195,7 @@ struct tracing_map {
+ 	int				key_idx[TRACING_MAP_KEYS_MAX];
+ 	unsigned int			n_keys;
+ 	struct tracing_map_sort_key	sort_key;
++	unsigned int			n_vars;
+ 	atomic64_t			hits;
+ 	atomic64_t			drops;
+ };
+@@ -241,6 +245,7 @@ tracing_map_create(unsigned int map_bits,
+ extern int tracing_map_init(struct tracing_map *map);
+ 
+ extern int tracing_map_add_sum_field(struct tracing_map *map);
++extern int tracing_map_add_var(struct tracing_map *map);
+ extern int tracing_map_add_key_field(struct tracing_map *map,
+ 				     unsigned int offset,
+ 				     tracing_map_cmp_fn_t cmp_fn);
+@@ -260,7 +265,13 @@ extern int tracing_map_cmp_none(void *val_a, void *val_b);
+ 
+ extern void tracing_map_update_sum(struct tracing_map_elt *elt,
+ 				   unsigned int i, u64 n);
++extern void tracing_map_set_var(struct tracing_map_elt *elt,
++				unsigned int i, u64 n);
++extern bool tracing_map_var_set(struct tracing_map_elt *elt, unsigned int i);
+ extern u64 tracing_map_read_sum(struct tracing_map_elt *elt, unsigned int i);
++extern u64 tracing_map_read_var(struct tracing_map_elt *elt, unsigned int i);
++extern u64 tracing_map_read_var_once(struct tracing_map_elt *elt, unsigned int i);
++
+ extern void tracing_map_set_field_descr(struct tracing_map *map,
+ 					unsigned int i,
+ 					unsigned int key_offset,
+-- 
+2.19.0
+
diff --git a/patches/1761-tracing-Add-variable-support-to-hist-triggers.patch b/patches/1761-tracing-Add-variable-support-to-hist-triggers.patch
new file mode 100644
index 00000000000000..afe2c124db30b7
--- /dev/null
+++ b/patches/1761-tracing-Add-variable-support-to-hist-triggers.patch
@@ -0,0 +1,789 @@
+From 45cd773351076eb70a415adca2cafa1d5f18a050 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:49 -0600
+Subject: [PATCH 1761/1795] tracing: Add variable support to hist triggers
+
+Add support for saving the value of a current event's event field by
+assigning it to a variable that can be read by a subsequent event.
+
+The basic syntax for saving a variable is to simply prefix a unique
+variable name not corresponding to any keyword along with an '=' sign
+to any event field.
+
+Both keys and values can be saved and retrieved in this way:
+
+    # echo 'hist:keys=next_pid:vals=$ts0:ts0=common_timestamp ...
+    # echo 'hist:timer_pid=common_pid:key=$timer_pid ...'
+
+If a variable isn't a key variable or prefixed with 'vals=', the
+associated event field will be saved in a variable but won't be summed
+as a value:
+
+    # echo 'hist:keys=next_pid:ts1=common_timestamp:...
+
+Multiple variables can be assigned at the same time:
+
+    # echo 'hist:keys=pid:vals=$ts0,$b,field2:ts0=common_timestamp,b=field1 ...
+
+Multiple (or single) variables can also be assigned at the same time
+using separate assignments:
+
+    # echo 'hist:keys=pid:vals=$ts0:ts0=common_timestamp:b=field1:c=field2 ...
+
+Variables set as above can be used by being referenced from another
+event, as described in a subsequent patch.
+
+Link: http://lkml.kernel.org/r/fc93c4944d9719dbcb1d0067be627d44e98e2adc.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Baohong Liu <baohong.liu@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 30350d65ac5676c6d08d4fc935bc9a9cb0fd4ed3)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 370 +++++++++++++++++++++++++++----
+ 1 file changed, 331 insertions(+), 39 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 7f5f0b8f6558..8f43f24bf49c 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -30,6 +30,13 @@ typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event,
+ 				struct ring_buffer_event *rbe);
+ 
+ #define HIST_FIELD_OPERANDS_MAX	2
++#define HIST_FIELDS_MAX		(TRACING_MAP_FIELDS_MAX + TRACING_MAP_VARS_MAX)
++
++struct hist_var {
++	char				*name;
++	struct hist_trigger_data	*hist_data;
++	unsigned int			idx;
++};
+ 
+ struct hist_field {
+ 	struct ftrace_event_field	*field;
+@@ -40,6 +47,7 @@ struct hist_field {
+ 	unsigned int                    is_signed;
+ 	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
+ 	struct hist_trigger_data	*hist_data;
++	struct hist_var			var;
+ };
+ 
+ static u64 hist_field_none(struct hist_field *field, void *event,
+@@ -138,6 +146,13 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_LOG2		= 1 << 9,
+ 	HIST_FIELD_FL_TIMESTAMP		= 1 << 10,
+ 	HIST_FIELD_FL_TIMESTAMP_USECS	= 1 << 11,
++	HIST_FIELD_FL_VAR		= 1 << 12,
++};
++
++struct var_defs {
++	unsigned int	n_vars;
++	char		*name[TRACING_MAP_VARS_MAX];
++	char		*expr[TRACING_MAP_VARS_MAX];
+ };
+ 
+ struct hist_trigger_attrs {
+@@ -150,13 +165,19 @@ struct hist_trigger_attrs {
+ 	bool		clear;
+ 	bool		ts_in_usecs;
+ 	unsigned int	map_bits;
++
++	char		*assignment_str[TRACING_MAP_VARS_MAX];
++	unsigned int	n_assignments;
++
++	struct var_defs	var_defs;
+ };
+ 
+ struct hist_trigger_data {
+-	struct hist_field               *fields[TRACING_MAP_FIELDS_MAX];
++	struct hist_field               *fields[HIST_FIELDS_MAX];
+ 	unsigned int			n_vals;
+ 	unsigned int			n_keys;
+ 	unsigned int			n_fields;
++	unsigned int			n_vars;
+ 	unsigned int			key_size;
+ 	struct tracing_map_sort_key	sort_keys[TRACING_MAP_SORT_KEYS_MAX];
+ 	unsigned int			n_sort_keys;
+@@ -164,6 +185,7 @@ struct hist_trigger_data {
+ 	struct hist_trigger_attrs	*attrs;
+ 	struct tracing_map		*map;
+ 	bool				enable_timestamps;
++	bool				remove;
+ };
+ 
+ static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
+@@ -180,6 +202,48 @@ static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
+ 	return ts;
+ }
+ 
++static struct hist_field *find_var_field(struct hist_trigger_data *hist_data,
++					 const char *var_name)
++{
++	struct hist_field *hist_field, *found = NULL;
++	int i;
++
++	for_each_hist_field(i, hist_data) {
++		hist_field = hist_data->fields[i];
++		if (hist_field && hist_field->flags & HIST_FIELD_FL_VAR &&
++		    strcmp(hist_field->var.name, var_name) == 0) {
++			found = hist_field;
++			break;
++		}
++	}
++
++	return found;
++}
++
++static struct hist_field *find_var(struct hist_trigger_data *hist_data,
++				   struct trace_event_file *file,
++				   const char *var_name)
++{
++	struct hist_trigger_data *test_data;
++	struct event_trigger_data *test;
++	struct hist_field *hist_field;
++
++	hist_field = find_var_field(hist_data, var_name);
++	if (hist_field)
++		return hist_field;
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			test_data = test->private_data;
++			hist_field = find_var_field(test_data, var_name);
++			if (hist_field)
++				return hist_field;
++		}
++	}
++
++	return NULL;
++}
++
+ static const char *hist_field_name(struct hist_field *field,
+ 				   unsigned int level)
+ {
+@@ -262,9 +326,14 @@ static int parse_map_size(char *str)
+ 
+ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ {
++	unsigned int i;
++
+ 	if (!attrs)
+ 		return;
+ 
++	for (i = 0; i < attrs->n_assignments; i++)
++		kfree(attrs->assignment_str[i]);
++
+ 	kfree(attrs->name);
+ 	kfree(attrs->sort_key_str);
+ 	kfree(attrs->keys_str);
+@@ -311,8 +380,22 @@ static int parse_assignment(char *str, struct hist_trigger_attrs *attrs)
+ 			goto out;
+ 		}
+ 		attrs->map_bits = map_bits;
+-	} else
+-		ret = -EINVAL;
++	} else {
++		char *assignment;
++
++		if (attrs->n_assignments == TRACING_MAP_VARS_MAX) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		assignment = kstrdup(str, GFP_KERNEL);
++		if (!assignment) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		attrs->assignment_str[attrs->n_assignments++] = assignment;
++	}
+  out:
+ 	return ret;
+ }
+@@ -428,12 +511,15 @@ static void destroy_hist_field(struct hist_field *hist_field,
+ 	for (i = 0; i < HIST_FIELD_OPERANDS_MAX; i++)
+ 		destroy_hist_field(hist_field->operands[i], level + 1);
+ 
++	kfree(hist_field->var.name);
++
+ 	kfree(hist_field);
+ }
+ 
+ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 					    struct ftrace_event_field *field,
+-					    unsigned long flags)
++					    unsigned long flags,
++					    char *var_name)
+ {
+ 	struct hist_field *hist_field;
+ 
+@@ -459,7 +545,7 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 	if (flags & HIST_FIELD_FL_LOG2) {
+ 		unsigned long fl = flags & ~HIST_FIELD_FL_LOG2;
+ 		hist_field->fn = hist_field_log2;
+-		hist_field->operands[0] = create_hist_field(hist_data, field, fl);
++		hist_field->operands[0] = create_hist_field(hist_data, field, fl, NULL);
+ 		hist_field->size = hist_field->operands[0]->size;
+ 		goto out;
+ 	}
+@@ -494,14 +580,23 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 	hist_field->field = field;
+ 	hist_field->flags = flags;
+ 
++	if (var_name) {
++		hist_field->var.name = kstrdup(var_name, GFP_KERNEL);
++		if (!hist_field->var.name)
++			goto free;
++	}
++
+ 	return hist_field;
++ free:
++	destroy_hist_field(hist_field, 0);
++	return NULL;
+ }
+ 
+ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ {
+ 	unsigned int i;
+ 
+-	for (i = 0; i < TRACING_MAP_FIELDS_MAX; i++) {
++	for (i = 0; i < HIST_FIELDS_MAX; i++) {
+ 		if (hist_data->fields[i]) {
+ 			destroy_hist_field(hist_data->fields[i], 0);
+ 			hist_data->fields[i] = NULL;
+@@ -512,11 +607,12 @@ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ {
+ 	hist_data->fields[HITCOUNT_IDX] =
+-		create_hist_field(hist_data, NULL, HIST_FIELD_FL_HITCOUNT);
++		create_hist_field(hist_data, NULL, HIST_FIELD_FL_HITCOUNT, NULL);
+ 	if (!hist_data->fields[HITCOUNT_IDX])
+ 		return -ENOMEM;
+ 
+ 	hist_data->n_vals++;
++	hist_data->n_fields++;
+ 
+ 	if (WARN_ON(hist_data->n_vals > TRACING_MAP_VALS_MAX))
+ 		return -EINVAL;
+@@ -524,19 +620,16 @@ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ 	return 0;
+ }
+ 
+-static int create_val_field(struct hist_trigger_data *hist_data,
+-			    unsigned int val_idx,
+-			    struct trace_event_file *file,
+-			    char *field_str)
++static int __create_val_field(struct hist_trigger_data *hist_data,
++			      unsigned int val_idx,
++			      struct trace_event_file *file,
++			      char *var_name, char *field_str,
++			      unsigned long flags)
+ {
+ 	struct ftrace_event_field *field = NULL;
+-	unsigned long flags = 0;
+ 	char *field_name;
+ 	int ret = 0;
+ 
+-	if (WARN_ON(val_idx >= TRACING_MAP_VALS_MAX))
+-		return -EINVAL;
+-
+ 	field_name = strsep(&field_str, ".");
+ 	if (field_str) {
+ 		if (strcmp(field_str, "hex") == 0)
+@@ -558,25 +651,58 @@ static int create_val_field(struct hist_trigger_data *hist_data,
+ 		}
+ 	}
+ 
+-	hist_data->fields[val_idx] = create_hist_field(hist_data, field, flags);
++	hist_data->fields[val_idx] = create_hist_field(hist_data, field, flags, var_name);
+ 	if (!hist_data->fields[val_idx]) {
+ 		ret = -ENOMEM;
+ 		goto out;
+ 	}
+ 
+ 	++hist_data->n_vals;
++	++hist_data->n_fields;
+ 
+-	if (WARN_ON(hist_data->n_vals > TRACING_MAP_VALS_MAX))
++	if (WARN_ON(hist_data->n_vals > TRACING_MAP_VALS_MAX + TRACING_MAP_VARS_MAX))
+ 		ret = -EINVAL;
+  out:
+ 	return ret;
+ }
+ 
++static int create_val_field(struct hist_trigger_data *hist_data,
++			    unsigned int val_idx,
++			    struct trace_event_file *file,
++			    char *field_str)
++{
++	if (WARN_ON(val_idx >= TRACING_MAP_VALS_MAX))
++		return -EINVAL;
++
++	return __create_val_field(hist_data, val_idx, file, NULL, field_str, 0);
++}
++
++static int create_var_field(struct hist_trigger_data *hist_data,
++			    unsigned int val_idx,
++			    struct trace_event_file *file,
++			    char *var_name, char *expr_str)
++{
++	unsigned long flags = 0;
++
++	if (WARN_ON(val_idx >= TRACING_MAP_VALS_MAX + TRACING_MAP_VARS_MAX))
++		return -EINVAL;
++	if (find_var(hist_data, file, var_name) && !hist_data->remove) {
++		return -EINVAL;
++	}
++
++	flags |= HIST_FIELD_FL_VAR;
++	hist_data->n_vars++;
++	if (WARN_ON(hist_data->n_vars > TRACING_MAP_VARS_MAX))
++		return -EINVAL;
++
++	return __create_val_field(hist_data, val_idx, file, var_name, expr_str, flags);
++}
++
+ static int create_val_fields(struct hist_trigger_data *hist_data,
+ 			     struct trace_event_file *file)
+ {
+ 	char *fields_str, *field_str;
+-	unsigned int i, j;
++	unsigned int i, j = 1;
+ 	int ret;
+ 
+ 	ret = create_hitcount_val(hist_data);
+@@ -596,12 +722,15 @@ static int create_val_fields(struct hist_trigger_data *hist_data,
+ 		field_str = strsep(&fields_str, ",");
+ 		if (!field_str)
+ 			break;
++
+ 		if (strcmp(field_str, "hitcount") == 0)
+ 			continue;
++
+ 		ret = create_val_field(hist_data, j++, file, field_str);
+ 		if (ret)
+ 			goto out;
+ 	}
++
+ 	if (fields_str && (strcmp(fields_str, "hitcount") != 0))
+ 		ret = -EINVAL;
+  out:
+@@ -615,11 +744,12 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 			    char *field_str)
+ {
+ 	struct ftrace_event_field *field = NULL;
++	struct hist_field *hist_field = NULL;
+ 	unsigned long flags = 0;
+ 	unsigned int key_size;
+ 	int ret = 0;
+ 
+-	if (WARN_ON(key_idx >= TRACING_MAP_FIELDS_MAX))
++	if (WARN_ON(key_idx >= HIST_FIELDS_MAX))
+ 		return -EINVAL;
+ 
+ 	flags |= HIST_FIELD_FL_KEY;
+@@ -627,6 +757,7 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 	if (strcmp(field_str, "stacktrace") == 0) {
+ 		flags |= HIST_FIELD_FL_STACKTRACE;
+ 		key_size = sizeof(unsigned long) * HIST_STACKTRACE_DEPTH;
++		hist_field = create_hist_field(hist_data, NULL, flags, NULL);
+ 	} else {
+ 		char *field_name = strsep(&field_str, ".");
+ 
+@@ -672,7 +803,7 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 		}
+ 	}
+ 
+-	hist_data->fields[key_idx] = create_hist_field(hist_data, field, flags);
++	hist_data->fields[key_idx] = create_hist_field(hist_data, field, flags, NULL);
+ 	if (!hist_data->fields[key_idx]) {
+ 		ret = -ENOMEM;
+ 		goto out;
+@@ -688,6 +819,7 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 	}
+ 
+ 	hist_data->n_keys++;
++	hist_data->n_fields++;
+ 
+ 	if (WARN_ON(hist_data->n_keys > TRACING_MAP_KEYS_MAX))
+ 		return -EINVAL;
+@@ -731,21 +863,111 @@ static int create_key_fields(struct hist_trigger_data *hist_data,
+ 	return ret;
+ }
+ 
++static int create_var_fields(struct hist_trigger_data *hist_data,
++			     struct trace_event_file *file)
++{
++	unsigned int i, j = hist_data->n_vals;
++	int ret = 0;
++
++	unsigned int n_vars = hist_data->attrs->var_defs.n_vars;
++
++	for (i = 0; i < n_vars; i++) {
++		char *var_name = hist_data->attrs->var_defs.name[i];
++		char *expr = hist_data->attrs->var_defs.expr[i];
++
++		ret = create_var_field(hist_data, j++, file, var_name, expr);
++		if (ret)
++			goto out;
++	}
++ out:
++	return ret;
++}
++
++static void free_var_defs(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->attrs->var_defs.n_vars; i++) {
++		kfree(hist_data->attrs->var_defs.name[i]);
++		kfree(hist_data->attrs->var_defs.expr[i]);
++	}
++
++	hist_data->attrs->var_defs.n_vars = 0;
++}
++
++static int parse_var_defs(struct hist_trigger_data *hist_data)
++{
++	char *s, *str, *var_name, *field_str;
++	unsigned int i, j, n_vars = 0;
++	int ret = 0;
++
++	for (i = 0; i < hist_data->attrs->n_assignments; i++) {
++		str = hist_data->attrs->assignment_str[i];
++		for (j = 0; j < TRACING_MAP_VARS_MAX; j++) {
++			field_str = strsep(&str, ",");
++			if (!field_str)
++				break;
++
++			var_name = strsep(&field_str, "=");
++			if (!var_name || !field_str) {
++				ret = -EINVAL;
++				goto free;
++			}
++
++			if (n_vars == TRACING_MAP_VARS_MAX) {
++				ret = -EINVAL;
++				goto free;
++			}
++
++			s = kstrdup(var_name, GFP_KERNEL);
++			if (!s) {
++				ret = -ENOMEM;
++				goto free;
++			}
++			hist_data->attrs->var_defs.name[n_vars] = s;
++
++			s = kstrdup(field_str, GFP_KERNEL);
++			if (!s) {
++				kfree(hist_data->attrs->var_defs.name[n_vars]);
++				ret = -ENOMEM;
++				goto free;
++			}
++			hist_data->attrs->var_defs.expr[n_vars++] = s;
++
++			hist_data->attrs->var_defs.n_vars = n_vars;
++		}
++	}
++
++	return ret;
++ free:
++	free_var_defs(hist_data);
++
++	return ret;
++}
++
+ static int create_hist_fields(struct hist_trigger_data *hist_data,
+ 			      struct trace_event_file *file)
+ {
+ 	int ret;
+ 
++	ret = parse_var_defs(hist_data);
++	if (ret)
++		goto out;
++
+ 	ret = create_val_fields(hist_data, file);
+ 	if (ret)
+ 		goto out;
+ 
+-	ret = create_key_fields(hist_data, file);
++	ret = create_var_fields(hist_data, file);
+ 	if (ret)
+ 		goto out;
+ 
+-	hist_data->n_fields = hist_data->n_vals + hist_data->n_keys;
++	ret = create_key_fields(hist_data, file);
++	if (ret)
++		goto out;
+  out:
++	free_var_defs(hist_data);
++
+ 	return ret;
+ }
+ 
+@@ -768,7 +990,7 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 	char *fields_str = hist_data->attrs->sort_key_str;
+ 	struct tracing_map_sort_key *sort_key;
+ 	int descending, ret = 0;
+-	unsigned int i, j;
++	unsigned int i, j, k;
+ 
+ 	hist_data->n_sort_keys = 1; /* we always have at least one, hitcount */
+ 
+@@ -816,12 +1038,19 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 			continue;
+ 		}
+ 
+-		for (j = 1; j < hist_data->n_fields; j++) {
++		for (j = 1, k = 1; j < hist_data->n_fields; j++) {
++			unsigned int idx;
++
+ 			hist_field = hist_data->fields[j];
++			if (hist_field->flags & HIST_FIELD_FL_VAR)
++				continue;
++
++			idx = k++;
++
+ 			test_name = hist_field_name(hist_field, 0);
+ 
+ 			if (strcmp(field_name, test_name) == 0) {
+-				sort_key->field_idx = j;
++				sort_key->field_idx = idx;
+ 				descending = is_descending(field_str);
+ 				if (descending < 0) {
+ 					ret = descending;
+@@ -836,6 +1065,7 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 			break;
+ 		}
+ 	}
++
+ 	hist_data->n_sort_keys = i;
+  out:
+ 	return ret;
+@@ -876,12 +1106,19 @@ static int create_tracing_map_fields(struct hist_trigger_data *hist_data)
+ 			idx = tracing_map_add_key_field(map,
+ 							hist_field->offset,
+ 							cmp_fn);
+-
+-		} else
++		} else if (!(hist_field->flags & HIST_FIELD_FL_VAR))
+ 			idx = tracing_map_add_sum_field(map);
+ 
+ 		if (idx < 0)
+ 			return idx;
++
++		if (hist_field->flags & HIST_FIELD_FL_VAR) {
++			idx = tracing_map_add_var(map);
++			if (idx < 0)
++				return idx;
++			hist_field->var.idx = idx;
++			hist_field->var.hist_data = hist_data;
++		}
+ 	}
+ 
+ 	return 0;
+@@ -905,7 +1142,8 @@ static bool need_tracing_map_ops(struct hist_trigger_data *hist_data)
+ static struct hist_trigger_data *
+ create_hist_data(unsigned int map_bits,
+ 		 struct hist_trigger_attrs *attrs,
+-		 struct trace_event_file *file)
++		 struct trace_event_file *file,
++		 bool remove)
+ {
+ 	const struct tracing_map_ops *map_ops = NULL;
+ 	struct hist_trigger_data *hist_data;
+@@ -916,6 +1154,7 @@ create_hist_data(unsigned int map_bits,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	hist_data->attrs = attrs;
++	hist_data->remove = remove;
+ 
+ 	ret = create_hist_fields(hist_data, file);
+ 	if (ret)
+@@ -962,14 +1201,28 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 				    struct ring_buffer_event *rbe)
+ {
+ 	struct hist_field *hist_field;
+-	unsigned int i;
++	unsigned int i, var_idx;
+ 	u64 hist_val;
+ 
+ 	for_each_hist_val_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+ 		hist_val = hist_field->fn(hist_field, rec, rbe);
++		if (hist_field->flags & HIST_FIELD_FL_VAR) {
++			var_idx = hist_field->var.idx;
++			tracing_map_set_var(elt, var_idx, hist_val);
++			continue;
++		}
+ 		tracing_map_update_sum(elt, i, hist_val);
+ 	}
++
++	for_each_hist_key_field(i, hist_data) {
++		hist_field = hist_data->fields[i];
++		if (hist_field->flags & HIST_FIELD_FL_VAR) {
++			hist_val = hist_field->fn(hist_field, rec, rbe);
++			var_idx = hist_field->var.idx;
++			tracing_map_set_var(elt, var_idx, hist_val);
++		}
++	}
+ }
+ 
+ static inline void add_to_key(char *compound_key, void *key,
+@@ -1144,6 +1397,9 @@ hist_trigger_entry_print(struct seq_file *m,
+ 	for (i = 1; i < hist_data->n_vals; i++) {
+ 		field_name = hist_field_name(hist_data->fields[i], 0);
+ 
++		if (hist_data->fields[i]->flags & HIST_FIELD_FL_VAR)
++			continue;
++
+ 		if (hist_data->fields[i]->flags & HIST_FIELD_FL_HEX) {
+ 			seq_printf(m, "  %s: %10llx", field_name,
+ 				   tracing_map_read_sum(elt, i));
+@@ -1265,6 +1521,9 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ {
+ 	const char *field_name = hist_field_name(hist_field, 0);
+ 
++	if (hist_field->var.name)
++		seq_printf(m, "%s=", hist_field->var.name);
++
+ 	if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		seq_puts(m, "common_timestamp");
+ 	else if (field_name)
+@@ -1283,7 +1542,8 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 				    struct event_trigger_data *data)
+ {
+ 	struct hist_trigger_data *hist_data = data->private_data;
+-	struct hist_field *key_field;
++	struct hist_field *field;
++	bool have_var = false;
+ 	unsigned int i;
+ 
+ 	seq_puts(m, "hist:");
+@@ -1294,25 +1554,47 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 	seq_puts(m, "keys=");
+ 
+ 	for_each_hist_key_field(i, hist_data) {
+-		key_field = hist_data->fields[i];
++		field = hist_data->fields[i];
+ 
+ 		if (i > hist_data->n_vals)
+ 			seq_puts(m, ",");
+ 
+-		if (key_field->flags & HIST_FIELD_FL_STACKTRACE)
++		if (field->flags & HIST_FIELD_FL_STACKTRACE)
+ 			seq_puts(m, "stacktrace");
+ 		else
+-			hist_field_print(m, key_field);
++			hist_field_print(m, field);
+ 	}
+ 
+ 	seq_puts(m, ":vals=");
+ 
+ 	for_each_hist_val_field(i, hist_data) {
++		field = hist_data->fields[i];
++		if (field->flags & HIST_FIELD_FL_VAR) {
++			have_var = true;
++			continue;
++		}
++
+ 		if (i == HITCOUNT_IDX)
+ 			seq_puts(m, "hitcount");
+ 		else {
+ 			seq_puts(m, ",");
+-			hist_field_print(m, hist_data->fields[i]);
++			hist_field_print(m, field);
++		}
++	}
++
++	if (have_var) {
++		unsigned int n = 0;
++
++		seq_puts(m, ":");
++
++		for_each_hist_val_field(i, hist_data) {
++			field = hist_data->fields[i];
++
++			if (field->flags & HIST_FIELD_FL_VAR) {
++				if (n++)
++					seq_puts(m, ",");
++				hist_field_print(m, field);
++			}
+ 		}
+ 	}
+ 
+@@ -1320,7 +1602,10 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 
+ 	for (i = 0; i < hist_data->n_sort_keys; i++) {
+ 		struct tracing_map_sort_key *sort_key;
+-		unsigned int idx;
++		unsigned int idx, first_key_idx;
++
++		/* skip VAR vals */
++		first_key_idx = hist_data->n_vals - hist_data->n_vars;
+ 
+ 		sort_key = &hist_data->sort_keys[i];
+ 		idx = sort_key->field_idx;
+@@ -1333,8 +1618,11 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 
+ 		if (idx == HITCOUNT_IDX)
+ 			seq_puts(m, "hitcount");
+-		else
++		else {
++			if (idx >= first_key_idx)
++				idx += hist_data->n_vars;
+ 			hist_field_print(m, hist_data->fields[idx]);
++		}
+ 
+ 		if (sort_key->descending)
+ 			seq_puts(m, ".descending");
+@@ -1631,7 +1919,7 @@ static void hist_unregister_trigger(char *glob, struct event_trigger_ops *ops,
+ 		test->ops->free(test->ops, test);
+ 
+ 	if (hist_data->enable_timestamps) {
+-		if (unregistered)
++		if (!hist_data->remove || unregistered)
+ 			tracing_set_time_stamp_abs(file->tr, false);
+ 	}
+ }
+@@ -1664,12 +1952,16 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	struct hist_trigger_attrs *attrs;
+ 	struct event_trigger_ops *trigger_ops;
+ 	struct hist_trigger_data *hist_data;
++	bool remove = false;
+ 	char *trigger;
+ 	int ret = 0;
+ 
+ 	if (!param)
+ 		return -EINVAL;
+ 
++	if (glob[0] == '!')
++		remove = true;
++
+ 	/* separate the trigger from the filter (k:v [if filter]) */
+ 	trigger = strsep(&param, " \t");
+ 	if (!trigger)
+@@ -1682,7 +1974,7 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	if (attrs->map_bits)
+ 		hist_trigger_bits = attrs->map_bits;
+ 
+-	hist_data = create_hist_data(hist_trigger_bits, attrs, file);
++	hist_data = create_hist_data(hist_trigger_bits, attrs, file, remove);
+ 	if (IS_ERR(hist_data)) {
+ 		destroy_hist_trigger_attrs(attrs);
+ 		return PTR_ERR(hist_data);
+@@ -1711,7 +2003,7 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 			goto out_free;
+ 	}
+ 
+-	if (glob[0] == '!') {
++	if (remove) {
+ 		cmd_ops->unreg(glob+1, trigger_ops, trigger_data, file);
+ 		ret = 0;
+ 		goto out_free;
+-- 
+2.19.0
+
diff --git a/patches/1762-tracing-Account-for-variables-in-named-trigger-compa.patch b/patches/1762-tracing-Account-for-variables-in-named-trigger-compa.patch
new file mode 100644
index 00000000000000..64b25bc0545186
--- /dev/null
+++ b/patches/1762-tracing-Account-for-variables-in-named-trigger-compa.patch
@@ -0,0 +1,52 @@
+From d06760f7d99fc58ac4587eab8fd2480cad54d83d Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:50 -0600
+Subject: [PATCH 1762/1795] tracing: Account for variables in named trigger
+ compatibility
+
+Named triggers must also have the same set of variables in order to be
+considered compatible - update the trigger match test to account for
+that.
+
+The reason for this requirement is that named triggers with variables
+are meant to allow one or more events to set the same variable.
+
+Link: http://lkml.kernel.org/r/a17eae6328a99917f9d5c66129c9fcd355279ee9.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 1a361dfcf261d68f081a12133aa8d0d6d6cca34f)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 8f43f24bf49c..ba326260c034 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -1610,7 +1610,7 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 		sort_key = &hist_data->sort_keys[i];
+ 		idx = sort_key->field_idx;
+ 
+-		if (WARN_ON(idx >= TRACING_MAP_FIELDS_MAX))
++		if (WARN_ON(idx >= HIST_FIELDS_MAX))
+ 			return -EINVAL;
+ 
+ 		if (i > 0)
+@@ -1798,6 +1798,11 @@ static bool hist_trigger_match(struct event_trigger_data *data,
+ 			return false;
+ 		if (key_field->is_signed != key_field_test->is_signed)
+ 			return false;
++		if (!!key_field->var.name != !!key_field_test->var.name)
++			return false;
++		if (key_field->var.name &&
++		    strcmp(key_field->var.name, key_field_test->var.name) != 0)
++			return false;
+ 	}
+ 
+ 	for (i = 0; i < hist_data->n_sort_keys; i++) {
+-- 
+2.19.0
+
diff --git a/patches/1763-tracing-Move-get_hist_field_flags.patch b/patches/1763-tracing-Move-get_hist_field_flags.patch
new file mode 100644
index 00000000000000..bb0638d8f659e8
--- /dev/null
+++ b/patches/1763-tracing-Move-get_hist_field_flags.patch
@@ -0,0 +1,84 @@
+From 73ad6a69a393317c3888eefdb871ca6406aac740 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:51 -0600
+Subject: [PATCH 1763/1795] tracing: Move get_hist_field_flags()
+
+Move get_hist_field_flags() to make it more easily accessible for new
+code (and keep the move separate from new functionality).
+
+Link: http://lkml.kernel.org/r/32470f0a7047ec7a6e84ba5ec89d6142cc6ede7d.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 2ece94fbd25c70543dd073d10569e08c3e3b4a7f)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 44 ++++++++++++++++----------------
+ 1 file changed, 22 insertions(+), 22 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index ba326260c034..a81a709dc703 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -497,6 +497,28 @@ static const struct tracing_map_ops hist_trigger_elt_comm_ops = {
+ 	.elt_init	= hist_trigger_elt_comm_init,
+ };
+ 
++static const char *get_hist_field_flags(struct hist_field *hist_field)
++{
++	const char *flags_str = NULL;
++
++	if (hist_field->flags & HIST_FIELD_FL_HEX)
++		flags_str = "hex";
++	else if (hist_field->flags & HIST_FIELD_FL_SYM)
++		flags_str = "sym";
++	else if (hist_field->flags & HIST_FIELD_FL_SYM_OFFSET)
++		flags_str = "sym-offset";
++	else if (hist_field->flags & HIST_FIELD_FL_EXECNAME)
++		flags_str = "execname";
++	else if (hist_field->flags & HIST_FIELD_FL_SYSCALL)
++		flags_str = "syscall";
++	else if (hist_field->flags & HIST_FIELD_FL_LOG2)
++		flags_str = "log2";
++	else if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP_USECS)
++		flags_str = "usecs";
++
++	return flags_str;
++}
++
+ static void destroy_hist_field(struct hist_field *hist_field,
+ 			       unsigned int level)
+ {
+@@ -1495,28 +1517,6 @@ const struct file_operations event_hist_fops = {
+ 	.release = single_release,
+ };
+ 
+-static const char *get_hist_field_flags(struct hist_field *hist_field)
+-{
+-	const char *flags_str = NULL;
+-
+-	if (hist_field->flags & HIST_FIELD_FL_HEX)
+-		flags_str = "hex";
+-	else if (hist_field->flags & HIST_FIELD_FL_SYM)
+-		flags_str = "sym";
+-	else if (hist_field->flags & HIST_FIELD_FL_SYM_OFFSET)
+-		flags_str = "sym-offset";
+-	else if (hist_field->flags & HIST_FIELD_FL_EXECNAME)
+-		flags_str = "execname";
+-	else if (hist_field->flags & HIST_FIELD_FL_SYSCALL)
+-		flags_str = "syscall";
+-	else if (hist_field->flags & HIST_FIELD_FL_LOG2)
+-		flags_str = "log2";
+-	else if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP_USECS)
+-		flags_str = "usecs";
+-
+-	return flags_str;
+-}
+-
+ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ {
+ 	const char *field_name = hist_field_name(hist_field, 0);
+-- 
+2.19.0
+
diff --git a/patches/1764-tracing-Add-simple-expression-support-to-hist-trigge.patch b/patches/1764-tracing-Add-simple-expression-support-to-hist-trigge.patch
new file mode 100644
index 00000000000000..2703de1099f5fc
--- /dev/null
+++ b/patches/1764-tracing-Add-simple-expression-support-to-hist-trigge.patch
@@ -0,0 +1,636 @@
+From 3236cc5c97f0ae3b93ea7aaf2d256fd87641502d Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:52 -0600
+Subject: [PATCH 1764/1795] tracing: Add simple expression support to hist
+ triggers
+
+Add support for simple addition, subtraction, and unary expressions
+(-(expr) and expr, where expr = b-a, a+b, a+b+c) to hist triggers, in
+order to support a minimal set of useful inter-event calculations.
+
+These operations are needed for calculating latencies between events
+(timestamp1-timestamp0) and for combined latencies (latencies over 3
+or more events).
+
+In the process, factor out some common code from key and value
+parsing.
+
+Link: http://lkml.kernel.org/r/9a9308ead4fe32a433d9c7e95921fb798394f6b2.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+[kbuild test robot fix, add static to parse_atom()]
+Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
+[ Replaced '//' comments with normal /* */ comments ]
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 100719dcef447aa0c90301f919e81ae477b32bf2)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 487 ++++++++++++++++++++++++++-----
+ 1 file changed, 413 insertions(+), 74 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index a81a709dc703..4c3c7d784bfd 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -32,6 +32,13 @@ typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event,
+ #define HIST_FIELD_OPERANDS_MAX	2
+ #define HIST_FIELDS_MAX		(TRACING_MAP_FIELDS_MAX + TRACING_MAP_VARS_MAX)
+ 
++enum field_op_id {
++	FIELD_OP_NONE,
++	FIELD_OP_PLUS,
++	FIELD_OP_MINUS,
++	FIELD_OP_UNARY_MINUS,
++};
++
+ struct hist_var {
+ 	char				*name;
+ 	struct hist_trigger_data	*hist_data;
+@@ -48,6 +55,8 @@ struct hist_field {
+ 	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
+ 	struct hist_trigger_data	*hist_data;
+ 	struct hist_var			var;
++	enum field_op_id		operator;
++	char				*name;
+ };
+ 
+ static u64 hist_field_none(struct hist_field *field, void *event,
+@@ -98,6 +107,41 @@ static u64 hist_field_log2(struct hist_field *hist_field, void *event,
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+ 
++static u64 hist_field_plus(struct hist_field *hist_field, void *event,
++			   struct ring_buffer_event *rbe)
++{
++	struct hist_field *operand1 = hist_field->operands[0];
++	struct hist_field *operand2 = hist_field->operands[1];
++
++	u64 val1 = operand1->fn(operand1, event, rbe);
++	u64 val2 = operand2->fn(operand2, event, rbe);
++
++	return val1 + val2;
++}
++
++static u64 hist_field_minus(struct hist_field *hist_field, void *event,
++			    struct ring_buffer_event *rbe)
++{
++	struct hist_field *operand1 = hist_field->operands[0];
++	struct hist_field *operand2 = hist_field->operands[1];
++
++	u64 val1 = operand1->fn(operand1, event, rbe);
++	u64 val2 = operand2->fn(operand2, event, rbe);
++
++	return val1 - val2;
++}
++
++static u64 hist_field_unary_minus(struct hist_field *hist_field, void *event,
++				  struct ring_buffer_event *rbe)
++{
++	struct hist_field *operand = hist_field->operands[0];
++
++	s64 sval = (s64)operand->fn(operand, event, rbe);
++	u64 val = (u64)-sval;
++
++	return val;
++}
++
+ #define DEFINE_HIST_FIELD_FN(type)					\
+ 	static u64 hist_field_##type(struct hist_field *hist_field,	\
+ 				     void *event,			\
+@@ -147,6 +191,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_TIMESTAMP		= 1 << 10,
+ 	HIST_FIELD_FL_TIMESTAMP_USECS	= 1 << 11,
+ 	HIST_FIELD_FL_VAR		= 1 << 12,
++	HIST_FIELD_FL_EXPR		= 1 << 13,
+ };
+ 
+ struct var_defs {
+@@ -258,6 +303,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 		field_name = hist_field_name(field->operands[0], ++level);
+ 	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		field_name = "common_timestamp";
++	else if (field->flags & HIST_FIELD_FL_EXPR)
++		field_name = field->name;
+ 
+ 	if (field_name == NULL)
+ 		field_name = "";
+@@ -519,12 +566,104 @@ static const char *get_hist_field_flags(struct hist_field *hist_field)
+ 	return flags_str;
+ }
+ 
++static void expr_field_str(struct hist_field *field, char *expr)
++{
++	strcat(expr, hist_field_name(field, 0));
++
++	if (field->flags) {
++		const char *flags_str = get_hist_field_flags(field);
++
++		if (flags_str) {
++			strcat(expr, ".");
++			strcat(expr, flags_str);
++		}
++	}
++}
++
++static char *expr_str(struct hist_field *field, unsigned int level)
++{
++	char *expr;
++
++	if (level > 1)
++		return NULL;
++
++	expr = kzalloc(MAX_FILTER_STR_VAL, GFP_KERNEL);
++	if (!expr)
++		return NULL;
++
++	if (!field->operands[0]) {
++		expr_field_str(field, expr);
++		return expr;
++	}
++
++	if (field->operator == FIELD_OP_UNARY_MINUS) {
++		char *subexpr;
++
++		strcat(expr, "-(");
++		subexpr = expr_str(field->operands[0], ++level);
++		if (!subexpr) {
++			kfree(expr);
++			return NULL;
++		}
++		strcat(expr, subexpr);
++		strcat(expr, ")");
++
++		kfree(subexpr);
++
++		return expr;
++	}
++
++	expr_field_str(field->operands[0], expr);
++
++	switch (field->operator) {
++	case FIELD_OP_MINUS:
++		strcat(expr, "-");
++		break;
++	case FIELD_OP_PLUS:
++		strcat(expr, "+");
++		break;
++	default:
++		kfree(expr);
++		return NULL;
++	}
++
++	expr_field_str(field->operands[1], expr);
++
++	return expr;
++}
++
++static int contains_operator(char *str)
++{
++	enum field_op_id field_op = FIELD_OP_NONE;
++	char *op;
++
++	op = strpbrk(str, "+-");
++	if (!op)
++		return FIELD_OP_NONE;
++
++	switch (*op) {
++	case '-':
++		if (*str == '-')
++			field_op = FIELD_OP_UNARY_MINUS;
++		else
++			field_op = FIELD_OP_MINUS;
++		break;
++	case '+':
++		field_op = FIELD_OP_PLUS;
++		break;
++	default:
++		break;
++	}
++
++	return field_op;
++}
++
+ static void destroy_hist_field(struct hist_field *hist_field,
+ 			       unsigned int level)
+ {
+ 	unsigned int i;
+ 
+-	if (level > 2)
++	if (level > 3)
+ 		return;
+ 
+ 	if (!hist_field)
+@@ -534,6 +673,7 @@ static void destroy_hist_field(struct hist_field *hist_field,
+ 		destroy_hist_field(hist_field->operands[i], level + 1);
+ 
+ 	kfree(hist_field->var.name);
++	kfree(hist_field->name);
+ 
+ 	kfree(hist_field);
+ }
+@@ -554,6 +694,9 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 
+ 	hist_field->hist_data = hist_data;
+ 
++	if (flags & HIST_FIELD_FL_EXPR)
++		goto out; /* caller will populate */
++
+ 	if (flags & HIST_FIELD_FL_HITCOUNT) {
+ 		hist_field->fn = hist_field_counter;
+ 		goto out;
+@@ -626,6 +769,257 @@ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ 	}
+ }
+ 
++static struct ftrace_event_field *
++parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
++	    char *field_str, unsigned long *flags)
++{
++	struct ftrace_event_field *field = NULL;
++	char *field_name, *modifier, *str;
++
++	modifier = str = kstrdup(field_str, GFP_KERNEL);
++	if (!modifier)
++		return ERR_PTR(-ENOMEM);
++
++	field_name = strsep(&modifier, ".");
++	if (modifier) {
++		if (strcmp(modifier, "hex") == 0)
++			*flags |= HIST_FIELD_FL_HEX;
++		else if (strcmp(modifier, "sym") == 0)
++			*flags |= HIST_FIELD_FL_SYM;
++		else if (strcmp(modifier, "sym-offset") == 0)
++			*flags |= HIST_FIELD_FL_SYM_OFFSET;
++		else if ((strcmp(modifier, "execname") == 0) &&
++			 (strcmp(field_name, "common_pid") == 0))
++			*flags |= HIST_FIELD_FL_EXECNAME;
++		else if (strcmp(modifier, "syscall") == 0)
++			*flags |= HIST_FIELD_FL_SYSCALL;
++		else if (strcmp(modifier, "log2") == 0)
++			*flags |= HIST_FIELD_FL_LOG2;
++		else if (strcmp(modifier, "usecs") == 0)
++			*flags |= HIST_FIELD_FL_TIMESTAMP_USECS;
++		else {
++			field = ERR_PTR(-EINVAL);
++			goto out;
++		}
++	}
++
++	if (strcmp(field_name, "common_timestamp") == 0) {
++		*flags |= HIST_FIELD_FL_TIMESTAMP;
++		hist_data->enable_timestamps = true;
++		if (*flags & HIST_FIELD_FL_TIMESTAMP_USECS)
++			hist_data->attrs->ts_in_usecs = true;
++	} else {
++		field = trace_find_event_field(file->event_call, field_name);
++		if (!field || !field->size) {
++			field = ERR_PTR(-EINVAL);
++			goto out;
++		}
++	}
++ out:
++	kfree(str);
++
++	return field;
++}
++
++static struct hist_field *parse_atom(struct hist_trigger_data *hist_data,
++				     struct trace_event_file *file, char *str,
++				     unsigned long *flags, char *var_name)
++{
++	struct ftrace_event_field *field = NULL;
++	struct hist_field *hist_field = NULL;
++	int ret = 0;
++
++	field = parse_field(hist_data, file, str, flags);
++	if (IS_ERR(field)) {
++		ret = PTR_ERR(field);
++		goto out;
++	}
++
++	hist_field = create_hist_field(hist_data, field, *flags, var_name);
++	if (!hist_field) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	return hist_field;
++ out:
++	return ERR_PTR(ret);
++}
++
++static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
++				     struct trace_event_file *file,
++				     char *str, unsigned long flags,
++				     char *var_name, unsigned int level);
++
++static struct hist_field *parse_unary(struct hist_trigger_data *hist_data,
++				      struct trace_event_file *file,
++				      char *str, unsigned long flags,
++				      char *var_name, unsigned int level)
++{
++	struct hist_field *operand1, *expr = NULL;
++	unsigned long operand_flags;
++	int ret = 0;
++	char *s;
++
++	/* we support only -(xxx) i.e. explicit parens required */
++
++	if (level > 3) {
++		ret = -EINVAL;
++		goto free;
++	}
++
++	str++; /* skip leading '-' */
++
++	s = strchr(str, '(');
++	if (s)
++		str++;
++	else {
++		ret = -EINVAL;
++		goto free;
++	}
++
++	s = strrchr(str, ')');
++	if (s)
++		*s = '\0';
++	else {
++		ret = -EINVAL; /* no closing ')' */
++		goto free;
++	}
++
++	flags |= HIST_FIELD_FL_EXPR;
++	expr = create_hist_field(hist_data, NULL, flags, var_name);
++	if (!expr) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	operand_flags = 0;
++	operand1 = parse_expr(hist_data, file, str, operand_flags, NULL, ++level);
++	if (IS_ERR(operand1)) {
++		ret = PTR_ERR(operand1);
++		goto free;
++	}
++
++	expr->flags |= operand1->flags &
++		(HIST_FIELD_FL_TIMESTAMP | HIST_FIELD_FL_TIMESTAMP_USECS);
++	expr->fn = hist_field_unary_minus;
++	expr->operands[0] = operand1;
++	expr->operator = FIELD_OP_UNARY_MINUS;
++	expr->name = expr_str(expr, 0);
++
++	return expr;
++ free:
++	destroy_hist_field(expr, 0);
++	return ERR_PTR(ret);
++}
++
++static int check_expr_operands(struct hist_field *operand1,
++			       struct hist_field *operand2)
++{
++	unsigned long operand1_flags = operand1->flags;
++	unsigned long operand2_flags = operand2->flags;
++
++	if ((operand1_flags & HIST_FIELD_FL_TIMESTAMP_USECS) !=
++	    (operand2_flags & HIST_FIELD_FL_TIMESTAMP_USECS))
++		return -EINVAL;
++
++	return 0;
++}
++
++static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
++				     struct trace_event_file *file,
++				     char *str, unsigned long flags,
++				     char *var_name, unsigned int level)
++{
++	struct hist_field *operand1 = NULL, *operand2 = NULL, *expr = NULL;
++	unsigned long operand_flags;
++	int field_op, ret = -EINVAL;
++	char *sep, *operand1_str;
++
++	if (level > 3)
++		return ERR_PTR(-EINVAL);
++
++	field_op = contains_operator(str);
++
++	if (field_op == FIELD_OP_NONE)
++		return parse_atom(hist_data, file, str, &flags, var_name);
++
++	if (field_op == FIELD_OP_UNARY_MINUS)
++		return parse_unary(hist_data, file, str, flags, var_name, ++level);
++
++	switch (field_op) {
++	case FIELD_OP_MINUS:
++		sep = "-";
++		break;
++	case FIELD_OP_PLUS:
++		sep = "+";
++		break;
++	default:
++		goto free;
++	}
++
++	operand1_str = strsep(&str, sep);
++	if (!operand1_str || !str)
++		goto free;
++
++	operand_flags = 0;
++	operand1 = parse_atom(hist_data, file, operand1_str,
++			      &operand_flags, NULL);
++	if (IS_ERR(operand1)) {
++		ret = PTR_ERR(operand1);
++		operand1 = NULL;
++		goto free;
++	}
++
++	/* rest of string could be another expression e.g. b+c in a+b+c */
++	operand_flags = 0;
++	operand2 = parse_expr(hist_data, file, str, operand_flags, NULL, ++level);
++	if (IS_ERR(operand2)) {
++		ret = PTR_ERR(operand2);
++		operand2 = NULL;
++		goto free;
++	}
++
++	ret = check_expr_operands(operand1, operand2);
++	if (ret)
++		goto free;
++
++	flags |= HIST_FIELD_FL_EXPR;
++
++	flags |= operand1->flags &
++		(HIST_FIELD_FL_TIMESTAMP | HIST_FIELD_FL_TIMESTAMP_USECS);
++
++	expr = create_hist_field(hist_data, NULL, flags, var_name);
++	if (!expr) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	expr->operands[0] = operand1;
++	expr->operands[1] = operand2;
++	expr->operator = field_op;
++	expr->name = expr_str(expr, 0);
++
++	switch (field_op) {
++	case FIELD_OP_MINUS:
++		expr->fn = hist_field_minus;
++		break;
++	case FIELD_OP_PLUS:
++		expr->fn = hist_field_plus;
++		break;
++	default:
++		goto free;
++	}
++
++	return expr;
++ free:
++	destroy_hist_field(operand1, 0);
++	destroy_hist_field(operand2, 0);
++	destroy_hist_field(expr, 0);
++
++	return ERR_PTR(ret);
++}
++
+ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ {
+ 	hist_data->fields[HITCOUNT_IDX] =
+@@ -648,37 +1042,17 @@ static int __create_val_field(struct hist_trigger_data *hist_data,
+ 			      char *var_name, char *field_str,
+ 			      unsigned long flags)
+ {
+-	struct ftrace_event_field *field = NULL;
+-	char *field_name;
++	struct hist_field *hist_field;
+ 	int ret = 0;
+ 
+-	field_name = strsep(&field_str, ".");
+-	if (field_str) {
+-		if (strcmp(field_str, "hex") == 0)
+-			flags |= HIST_FIELD_FL_HEX;
+-		else {
+-			ret = -EINVAL;
+-			goto out;
+-		}
+-	}
+-
+-	if (strcmp(field_name, "common_timestamp") == 0) {
+-		flags |= HIST_FIELD_FL_TIMESTAMP;
+-		hist_data->enable_timestamps = true;
+-	} else {
+-		field = trace_find_event_field(file->event_call, field_name);
+-		if (!field || !field->size) {
+-			ret = -EINVAL;
+-			goto out;
+-		}
+-	}
+-
+-	hist_data->fields[val_idx] = create_hist_field(hist_data, field, flags, var_name);
+-	if (!hist_data->fields[val_idx]) {
+-		ret = -ENOMEM;
++	hist_field = parse_expr(hist_data, file, field_str, flags, var_name, 0);
++	if (IS_ERR(hist_field)) {
++		ret = PTR_ERR(hist_field);
+ 		goto out;
+ 	}
+ 
++	hist_data->fields[val_idx] = hist_field;
++
+ 	++hist_data->n_vals;
+ 	++hist_data->n_fields;
+ 
+@@ -765,8 +1139,8 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 			    struct trace_event_file *file,
+ 			    char *field_str)
+ {
+-	struct ftrace_event_field *field = NULL;
+ 	struct hist_field *hist_field = NULL;
++
+ 	unsigned long flags = 0;
+ 	unsigned int key_size;
+ 	int ret = 0;
+@@ -781,60 +1155,24 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 		key_size = sizeof(unsigned long) * HIST_STACKTRACE_DEPTH;
+ 		hist_field = create_hist_field(hist_data, NULL, flags, NULL);
+ 	} else {
+-		char *field_name = strsep(&field_str, ".");
+-
+-		if (field_str) {
+-			if (strcmp(field_str, "hex") == 0)
+-				flags |= HIST_FIELD_FL_HEX;
+-			else if (strcmp(field_str, "sym") == 0)
+-				flags |= HIST_FIELD_FL_SYM;
+-			else if (strcmp(field_str, "sym-offset") == 0)
+-				flags |= HIST_FIELD_FL_SYM_OFFSET;
+-			else if ((strcmp(field_str, "execname") == 0) &&
+-				 (strcmp(field_name, "common_pid") == 0))
+-				flags |= HIST_FIELD_FL_EXECNAME;
+-			else if (strcmp(field_str, "syscall") == 0)
+-				flags |= HIST_FIELD_FL_SYSCALL;
+-			else if (strcmp(field_str, "log2") == 0)
+-				flags |= HIST_FIELD_FL_LOG2;
+-			else if (strcmp(field_str, "usecs") == 0)
+-				flags |= HIST_FIELD_FL_TIMESTAMP_USECS;
+-			else {
+-				ret = -EINVAL;
+-				goto out;
+-			}
++		hist_field = parse_expr(hist_data, file, field_str, flags,
++					NULL, 0);
++		if (IS_ERR(hist_field)) {
++			ret = PTR_ERR(hist_field);
++			goto out;
+ 		}
+ 
+-		if (strcmp(field_name, "common_timestamp") == 0) {
+-			flags |= HIST_FIELD_FL_TIMESTAMP;
+-			hist_data->enable_timestamps = true;
+-			if (flags & HIST_FIELD_FL_TIMESTAMP_USECS)
+-				hist_data->attrs->ts_in_usecs = true;
+-			key_size = sizeof(u64);
+-		} else {
+-			field = trace_find_event_field(file->event_call, field_name);
+-			if (!field || !field->size) {
+-				ret = -EINVAL;
+-				goto out;
+-			}
+-
+-			if (is_string_field(field))
+-				key_size = MAX_FILTER_STR_VAL;
+-			else
+-				key_size = field->size;
+-		}
++		key_size = hist_field->size;
+ 	}
+ 
+-	hist_data->fields[key_idx] = create_hist_field(hist_data, field, flags, NULL);
+-	if (!hist_data->fields[key_idx]) {
+-		ret = -ENOMEM;
+-		goto out;
+-	}
++	hist_data->fields[key_idx] = hist_field;
+ 
+ 	key_size = ALIGN(key_size, sizeof(u64));
+ 	hist_data->fields[key_idx]->size = key_size;
+ 	hist_data->fields[key_idx]->offset = key_offset;
++
+ 	hist_data->key_size += key_size;
++
+ 	if (hist_data->key_size > HIST_KEY_SIZE_MAX) {
+ 		ret = -EINVAL;
+ 		goto out;
+@@ -1419,7 +1757,8 @@ hist_trigger_entry_print(struct seq_file *m,
+ 	for (i = 1; i < hist_data->n_vals; i++) {
+ 		field_name = hist_field_name(hist_data->fields[i], 0);
+ 
+-		if (hist_data->fields[i]->flags & HIST_FIELD_FL_VAR)
++		if (hist_data->fields[i]->flags & HIST_FIELD_FL_VAR ||
++		    hist_data->fields[i]->flags & HIST_FIELD_FL_EXPR)
+ 			continue;
+ 
+ 		if (hist_data->fields[i]->flags & HIST_FIELD_FL_HEX) {
+-- 
+2.19.0
+
diff --git a/patches/1765-tracing-Generalize-per-element-hist-trigger-data.patch b/patches/1765-tracing-Generalize-per-element-hist-trigger-data.patch
new file mode 100644
index 00000000000000..0ee0b16d6c3192
--- /dev/null
+++ b/patches/1765-tracing-Generalize-per-element-hist-trigger-data.patch
@@ -0,0 +1,165 @@
+From 4d5065bbd407b1f48ed2f655ef708671a725bba0 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:53 -0600
+Subject: [PATCH 1765/1795] tracing: Generalize per-element hist trigger data
+
+Up until now, hist triggers only needed per-element support for saving
+'comm' data, which was saved directly as a private data pointer.
+
+In anticipation of the need to save other data besides 'comm', add a
+new hist_elt_data struct for the purpose, and switch the current
+'comm'-related code over to that.
+
+Link: http://lkml.kernel.org/r/4502c338c965ddf5fc19fb1ec4764391e001ed4b.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit af6a29bcaf8ff260222a953536c13c167d5c4649)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 76 ++++++++++++++++++--------------
+ 1 file changed, 43 insertions(+), 33 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 4c3c7d784bfd..f072ed3122c8 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -289,6 +289,10 @@ static struct hist_field *find_var(struct hist_trigger_data *hist_data,
+ 	return NULL;
+ }
+ 
++struct hist_elt_data {
++	char *comm;
++};
++
+ static const char *hist_field_name(struct hist_field *field,
+ 				   unsigned int level)
+ {
+@@ -503,45 +507,61 @@ static inline void save_comm(char *comm, struct task_struct *task)
+ 	memcpy(comm, task->comm, TASK_COMM_LEN);
+ }
+ 
+-static void hist_trigger_elt_comm_free(struct tracing_map_elt *elt)
++static void hist_elt_data_free(struct hist_elt_data *elt_data)
++{
++	kfree(elt_data->comm);
++	kfree(elt_data);
++}
++
++static void hist_trigger_elt_data_free(struct tracing_map_elt *elt)
+ {
+-	kfree((char *)elt->private_data);
++	struct hist_elt_data *elt_data = elt->private_data;
++
++	hist_elt_data_free(elt_data);
+ }
+ 
+-static int hist_trigger_elt_comm_alloc(struct tracing_map_elt *elt)
++static int hist_trigger_elt_data_alloc(struct tracing_map_elt *elt)
+ {
+ 	struct hist_trigger_data *hist_data = elt->map->private_data;
++	unsigned int size = TASK_COMM_LEN;
++	struct hist_elt_data *elt_data;
+ 	struct hist_field *key_field;
+ 	unsigned int i;
+ 
++	elt_data = kzalloc(sizeof(*elt_data), GFP_KERNEL);
++	if (!elt_data)
++		return -ENOMEM;
++
+ 	for_each_hist_key_field(i, hist_data) {
+ 		key_field = hist_data->fields[i];
+ 
+ 		if (key_field->flags & HIST_FIELD_FL_EXECNAME) {
+-			unsigned int size = TASK_COMM_LEN + 1;
+-
+-			elt->private_data = kzalloc(size, GFP_KERNEL);
+-			if (!elt->private_data)
++			elt_data->comm = kzalloc(size, GFP_KERNEL);
++			if (!elt_data->comm) {
++				kfree(elt_data);
+ 				return -ENOMEM;
++			}
+ 			break;
+ 		}
+ 	}
+ 
++	elt->private_data = elt_data;
++
+ 	return 0;
+ }
+ 
+-static void hist_trigger_elt_comm_init(struct tracing_map_elt *elt)
++static void hist_trigger_elt_data_init(struct tracing_map_elt *elt)
+ {
+-	char *comm = elt->private_data;
++	struct hist_elt_data *elt_data = elt->private_data;
+ 
+-	if (comm)
+-		save_comm(comm, current);
++	if (elt_data->comm)
++		save_comm(elt_data->comm, current);
+ }
+ 
+-static const struct tracing_map_ops hist_trigger_elt_comm_ops = {
+-	.elt_alloc	= hist_trigger_elt_comm_alloc,
+-	.elt_free	= hist_trigger_elt_comm_free,
+-	.elt_init	= hist_trigger_elt_comm_init,
++static const struct tracing_map_ops hist_trigger_elt_data_ops = {
++	.elt_alloc	= hist_trigger_elt_data_alloc,
++	.elt_free	= hist_trigger_elt_data_free,
++	.elt_init	= hist_trigger_elt_data_init,
+ };
+ 
+ static const char *get_hist_field_flags(struct hist_field *hist_field)
+@@ -1484,21 +1504,6 @@ static int create_tracing_map_fields(struct hist_trigger_data *hist_data)
+ 	return 0;
+ }
+ 
+-static bool need_tracing_map_ops(struct hist_trigger_data *hist_data)
+-{
+-	struct hist_field *key_field;
+-	unsigned int i;
+-
+-	for_each_hist_key_field(i, hist_data) {
+-		key_field = hist_data->fields[i];
+-
+-		if (key_field->flags & HIST_FIELD_FL_EXECNAME)
+-			return true;
+-	}
+-
+-	return false;
+-}
+-
+ static struct hist_trigger_data *
+ create_hist_data(unsigned int map_bits,
+ 		 struct hist_trigger_attrs *attrs,
+@@ -1524,8 +1529,7 @@ create_hist_data(unsigned int map_bits,
+ 	if (ret)
+ 		goto free;
+ 
+-	if (need_tracing_map_ops(hist_data))
+-		map_ops = &hist_trigger_elt_comm_ops;
++	map_ops = &hist_trigger_elt_data_ops;
+ 
+ 	hist_data->map = tracing_map_create(map_bits, hist_data->key_size,
+ 					    map_ops, hist_data);
+@@ -1713,7 +1717,13 @@ hist_trigger_entry_print(struct seq_file *m,
+ 			seq_printf(m, "%s: [%llx] %-55s", field_name,
+ 				   uval, str);
+ 		} else if (key_field->flags & HIST_FIELD_FL_EXECNAME) {
+-			char *comm = elt->private_data;
++			struct hist_elt_data *elt_data = elt->private_data;
++			char *comm;
++
++			if (WARN_ON_ONCE(!elt_data))
++				return;
++
++			comm = elt_data->comm;
+ 
+ 			uval = *(u64 *)(key + key_field->offset);
+ 			seq_printf(m, "%s: %-16s[%10llu]", field_name,
+-- 
+2.19.0
+
diff --git a/patches/1766-tracing-Pass-tracing_map_elt-to-hist_field-accessor-.patch b/patches/1766-tracing-Pass-tracing_map_elt-to-hist_field-accessor-.patch
new file mode 100644
index 00000000000000..d155bd86a6f17e
--- /dev/null
+++ b/patches/1766-tracing-Pass-tracing_map_elt-to-hist_field-accessor-.patch
@@ -0,0 +1,232 @@
+From 074707e24a5ac30dee3a357ef3def76575311fba Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:54 -0600
+Subject: [PATCH 1766/1795] tracing: Pass tracing_map_elt to hist_field
+ accessor functions
+
+Some accessor functions, such as for variable references, require
+access to a corrsponding tracing_map_elt.
+
+Add a tracing_map_elt param to the function signature and update the
+accessor functions accordingly.
+
+Link: http://lkml.kernel.org/r/e0f292b068e9e4948da1d5af21b5ae0efa9b5717.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit df35d93bbff0297617edf105e6b4057a3953a1a9)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 91 ++++++++++++++++++++------------
+ 1 file changed, 57 insertions(+), 34 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index f072ed3122c8..7a54ab50176b 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -26,8 +26,10 @@
+ 
+ struct hist_field;
+ 
+-typedef u64 (*hist_field_fn_t) (struct hist_field *field, void *event,
+-				struct ring_buffer_event *rbe);
++typedef u64 (*hist_field_fn_t) (struct hist_field *field,
++				struct tracing_map_elt *elt,
++				struct ring_buffer_event *rbe,
++				void *event);
+ 
+ #define HIST_FIELD_OPERANDS_MAX	2
+ #define HIST_FIELDS_MAX		(TRACING_MAP_FIELDS_MAX + TRACING_MAP_VARS_MAX)
+@@ -59,28 +61,36 @@ struct hist_field {
+ 	char				*name;
+ };
+ 
+-static u64 hist_field_none(struct hist_field *field, void *event,
+-			   struct ring_buffer_event *rbe)
++static u64 hist_field_none(struct hist_field *field,
++			   struct tracing_map_elt *elt,
++			   struct ring_buffer_event *rbe,
++			   void *event)
+ {
+ 	return 0;
+ }
+ 
+-static u64 hist_field_counter(struct hist_field *field, void *event,
+-			      struct ring_buffer_event *rbe)
++static u64 hist_field_counter(struct hist_field *field,
++			      struct tracing_map_elt *elt,
++			      struct ring_buffer_event *rbe,
++			      void *event)
+ {
+ 	return 1;
+ }
+ 
+-static u64 hist_field_string(struct hist_field *hist_field, void *event,
+-			     struct ring_buffer_event *rbe)
++static u64 hist_field_string(struct hist_field *hist_field,
++			     struct tracing_map_elt *elt,
++			     struct ring_buffer_event *rbe,
++			     void *event)
+ {
+ 	char *addr = (char *)(event + hist_field->field->offset);
+ 
+ 	return (u64)(unsigned long)addr;
+ }
+ 
+-static u64 hist_field_dynstring(struct hist_field *hist_field, void *event,
+-				struct ring_buffer_event *rbe)
++static u64 hist_field_dynstring(struct hist_field *hist_field,
++				struct tracing_map_elt *elt,
++				struct ring_buffer_event *rbe,
++				void *event)
+ {
+ 	u32 str_item = *(u32 *)(event + hist_field->field->offset);
+ 	int str_loc = str_item & 0xffff;
+@@ -89,54 +99,64 @@ static u64 hist_field_dynstring(struct hist_field *hist_field, void *event,
+ 	return (u64)(unsigned long)addr;
+ }
+ 
+-static u64 hist_field_pstring(struct hist_field *hist_field, void *event,
+-			      struct ring_buffer_event *rbe)
++static u64 hist_field_pstring(struct hist_field *hist_field,
++			      struct tracing_map_elt *elt,
++			      struct ring_buffer_event *rbe,
++			      void *event)
+ {
+ 	char **addr = (char **)(event + hist_field->field->offset);
+ 
+ 	return (u64)(unsigned long)*addr;
+ }
+ 
+-static u64 hist_field_log2(struct hist_field *hist_field, void *event,
+-			   struct ring_buffer_event *rbe)
++static u64 hist_field_log2(struct hist_field *hist_field,
++			   struct tracing_map_elt *elt,
++			   struct ring_buffer_event *rbe,
++			   void *event)
+ {
+ 	struct hist_field *operand = hist_field->operands[0];
+ 
+-	u64 val = operand->fn(operand, event, rbe);
++	u64 val = operand->fn(operand, elt, rbe, event);
+ 
+ 	return (u64) ilog2(roundup_pow_of_two(val));
+ }
+ 
+-static u64 hist_field_plus(struct hist_field *hist_field, void *event,
+-			   struct ring_buffer_event *rbe)
++static u64 hist_field_plus(struct hist_field *hist_field,
++			   struct tracing_map_elt *elt,
++			   struct ring_buffer_event *rbe,
++			   void *event)
+ {
+ 	struct hist_field *operand1 = hist_field->operands[0];
+ 	struct hist_field *operand2 = hist_field->operands[1];
+ 
+-	u64 val1 = operand1->fn(operand1, event, rbe);
+-	u64 val2 = operand2->fn(operand2, event, rbe);
++	u64 val1 = operand1->fn(operand1, elt, rbe, event);
++	u64 val2 = operand2->fn(operand2, elt, rbe, event);
+ 
+ 	return val1 + val2;
+ }
+ 
+-static u64 hist_field_minus(struct hist_field *hist_field, void *event,
+-			    struct ring_buffer_event *rbe)
++static u64 hist_field_minus(struct hist_field *hist_field,
++			    struct tracing_map_elt *elt,
++			    struct ring_buffer_event *rbe,
++			    void *event)
+ {
+ 	struct hist_field *operand1 = hist_field->operands[0];
+ 	struct hist_field *operand2 = hist_field->operands[1];
+ 
+-	u64 val1 = operand1->fn(operand1, event, rbe);
+-	u64 val2 = operand2->fn(operand2, event, rbe);
++	u64 val1 = operand1->fn(operand1, elt, rbe, event);
++	u64 val2 = operand2->fn(operand2, elt, rbe, event);
+ 
+ 	return val1 - val2;
+ }
+ 
+-static u64 hist_field_unary_minus(struct hist_field *hist_field, void *event,
+-				  struct ring_buffer_event *rbe)
++static u64 hist_field_unary_minus(struct hist_field *hist_field,
++				  struct tracing_map_elt *elt,
++				  struct ring_buffer_event *rbe,
++				  void *event)
+ {
+ 	struct hist_field *operand = hist_field->operands[0];
+ 
+-	s64 sval = (s64)operand->fn(operand, event, rbe);
++	s64 sval = (s64)operand->fn(operand, elt, rbe, event);
+ 	u64 val = (u64)-sval;
+ 
+ 	return val;
+@@ -144,8 +164,9 @@ static u64 hist_field_unary_minus(struct hist_field *hist_field, void *event,
+ 
+ #define DEFINE_HIST_FIELD_FN(type)					\
+ 	static u64 hist_field_##type(struct hist_field *hist_field,	\
+-				     void *event,			\
+-				     struct ring_buffer_event *rbe)	\
++				     struct tracing_map_elt *elt,	\
++				     struct ring_buffer_event *rbe,	\
++				     void *event)			\
+ {									\
+ 	type *addr = (type *)(event + hist_field->field->offset);	\
+ 									\
+@@ -233,8 +254,10 @@ struct hist_trigger_data {
+ 	bool				remove;
+ };
+ 
+-static u64 hist_field_timestamp(struct hist_field *hist_field, void *event,
+-				struct ring_buffer_event *rbe)
++static u64 hist_field_timestamp(struct hist_field *hist_field,
++				struct tracing_map_elt *elt,
++				struct ring_buffer_event *rbe,
++				void *event)
+ {
+ 	struct hist_trigger_data *hist_data = hist_field->hist_data;
+ 	struct trace_array *tr = hist_data->event_file->tr;
+@@ -1570,7 +1593,7 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 
+ 	for_each_hist_val_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+-		hist_val = hist_field->fn(hist_field, rec, rbe);
++		hist_val = hist_field->fn(hist_field, elt, rbe, rec);
+ 		if (hist_field->flags & HIST_FIELD_FL_VAR) {
+ 			var_idx = hist_field->var.idx;
+ 			tracing_map_set_var(elt, var_idx, hist_val);
+@@ -1582,7 +1605,7 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 	for_each_hist_key_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+ 		if (hist_field->flags & HIST_FIELD_FL_VAR) {
+-			hist_val = hist_field->fn(hist_field, rec, rbe);
++			hist_val = hist_field->fn(hist_field, elt, rbe, rec);
+ 			var_idx = hist_field->var.idx;
+ 			tracing_map_set_var(elt, var_idx, hist_val);
+ 		}
+@@ -1620,9 +1643,9 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 	bool use_compound_key = (hist_data->n_keys > 1);
+ 	unsigned long entries[HIST_STACKTRACE_DEPTH];
+ 	char compound_key[HIST_KEY_SIZE_MAX];
++	struct tracing_map_elt *elt = NULL;
+ 	struct stack_trace stacktrace;
+ 	struct hist_field *key_field;
+-	struct tracing_map_elt *elt;
+ 	u64 field_contents;
+ 	void *key = NULL;
+ 	unsigned int i;
+@@ -1643,7 +1666,7 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 
+ 			key = entries;
+ 		} else {
+-			field_contents = key_field->fn(key_field, rec, rbe);
++			field_contents = key_field->fn(key_field, elt, rbe, rec);
+ 			if (key_field->flags & HIST_FIELD_FL_STRING) {
+ 				key = (void *)(unsigned long)field_contents;
+ 				use_compound_key = true;
+-- 
+2.19.0
+
diff --git a/patches/1767-tracing-Add-hist_field-type-field.patch b/patches/1767-tracing-Add-hist_field-type-field.patch
new file mode 100644
index 00000000000000..241db194cb4d93
--- /dev/null
+++ b/patches/1767-tracing-Add-hist_field-type-field.patch
@@ -0,0 +1,124 @@
+From 304ee6184a35c98f91df8cb1d33d0a946087e596 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:55 -0600
+Subject: [PATCH 1767/1795] tracing: Add hist_field 'type' field
+
+Future support for synthetic events requires hist_field 'type'
+information, so add a field for that.
+
+Also, make other hist_field attribute usage consistent (size,
+is_signed, etc).
+
+Link: http://lkml.kernel.org/r/3fd12a2e86316b05151ba0d7c68268e780af2c9d.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 19a9facd0fe33a3e376923383958b2c86cbd3994)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 33 ++++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 7a54ab50176b..e30bd86bee8e 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -54,6 +54,7 @@ struct hist_field {
+ 	unsigned int			size;
+ 	unsigned int			offset;
+ 	unsigned int                    is_signed;
++	const char			*type;
+ 	struct hist_field		*operands[HIST_FIELD_OPERANDS_MAX];
+ 	struct hist_trigger_data	*hist_data;
+ 	struct hist_var			var;
+@@ -717,6 +718,7 @@ static void destroy_hist_field(struct hist_field *hist_field,
+ 
+ 	kfree(hist_field->var.name);
+ 	kfree(hist_field->name);
++	kfree(hist_field->type);
+ 
+ 	kfree(hist_field);
+ }
+@@ -742,6 +744,10 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 
+ 	if (flags & HIST_FIELD_FL_HITCOUNT) {
+ 		hist_field->fn = hist_field_counter;
++		hist_field->size = sizeof(u64);
++		hist_field->type = kstrdup("u64", GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
+ 		goto out;
+ 	}
+ 
+@@ -755,12 +761,18 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 		hist_field->fn = hist_field_log2;
+ 		hist_field->operands[0] = create_hist_field(hist_data, field, fl, NULL);
+ 		hist_field->size = hist_field->operands[0]->size;
++		hist_field->type = kstrdup(hist_field->operands[0]->type, GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
+ 		goto out;
+ 	}
+ 
+ 	if (flags & HIST_FIELD_FL_TIMESTAMP) {
+ 		hist_field->fn = hist_field_timestamp;
+ 		hist_field->size = sizeof(u64);
++		hist_field->type = kstrdup("u64", GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
+ 		goto out;
+ 	}
+ 
+@@ -770,6 +782,11 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 	if (is_string_field(field)) {
+ 		flags |= HIST_FIELD_FL_STRING;
+ 
++		hist_field->size = MAX_FILTER_STR_VAL;
++		hist_field->type = kstrdup(field->type, GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
++
+ 		if (field->filter_type == FILTER_STATIC_STRING)
+ 			hist_field->fn = hist_field_string;
+ 		else if (field->filter_type == FILTER_DYN_STRING)
+@@ -777,6 +794,12 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 		else
+ 			hist_field->fn = hist_field_pstring;
+ 	} else {
++		hist_field->size = field->size;
++		hist_field->is_signed = field->is_signed;
++		hist_field->type = kstrdup(field->type, GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
++
+ 		hist_field->fn = select_value_fn(field->size,
+ 						 field->is_signed);
+ 		if (!hist_field->fn) {
+@@ -949,6 +972,11 @@ static struct hist_field *parse_unary(struct hist_trigger_data *hist_data,
+ 	expr->operands[0] = operand1;
+ 	expr->operator = FIELD_OP_UNARY_MINUS;
+ 	expr->name = expr_str(expr, 0);
++	expr->type = kstrdup(operand1->type, GFP_KERNEL);
++	if (!expr->type) {
++		ret = -ENOMEM;
++		goto free;
++	}
+ 
+ 	return expr;
+  free:
+@@ -1042,6 +1070,11 @@ static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
+ 	expr->operands[1] = operand2;
+ 	expr->operator = field_op;
+ 	expr->name = expr_str(expr, 0);
++	expr->type = kstrdup(operand1->type, GFP_KERNEL);
++	if (!expr->type) {
++		ret = -ENOMEM;
++		goto free;
++	}
+ 
+ 	switch (field_op) {
+ 	case FIELD_OP_MINUS:
+-- 
+2.19.0
+
diff --git a/patches/1768-tracing-Add-variable-reference-handling-to-hist-trig.patch b/patches/1768-tracing-Add-variable-reference-handling-to-hist-trig.patch
new file mode 100644
index 00000000000000..a2b564f7de5e2e
--- /dev/null
+++ b/patches/1768-tracing-Add-variable-reference-handling-to-hist-trig.patch
@@ -0,0 +1,968 @@
+From c263537fef6a398d9ec58206a4e0eb91dd933412 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:56 -0600
+Subject: [PATCH 1768/1795] tracing: Add variable reference handling to hist
+ triggers
+
+Add the necessary infrastructure to allow the variables defined on one
+event to be referenced in another.  This allows variables set by a
+previous event to be referenced and used in expressions combining the
+variable values saved by that previous event and the event fields of
+the current event.  For example, here's how a latency can be
+calculated and saved into yet another variable named 'wakeup_lat':
+
+    # echo 'hist:keys=pid,prio:ts0=common_timestamp ...
+    # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp-$ts0 ...
+
+In the first event, the event's timetamp is saved into the variable
+ts0.  In the next line, ts0 is subtracted from the second event's
+timestamp to produce the latency.
+
+Further users of variable references will be described in subsequent
+patches, such as for instance how the 'wakeup_lat' variable above can
+be displayed in a latency histogram.
+
+Link: http://lkml.kernel.org/r/b1d3e6975374e34d501ff417c20189c3f9b2c7b8.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 067fe038e70f6e64960d26a79c4df5f1413d0f13)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace.c                |   2 +
+ kernel/trace/trace.h                |   3 +
+ kernel/trace/trace_events_hist.c    | 661 +++++++++++++++++++++++++++-
+ kernel/trace/trace_events_trigger.c |   6 +
+ 4 files changed, 656 insertions(+), 16 deletions(-)
+
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index 0c8a697d8442..e487a2bf4520 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -7756,6 +7756,7 @@ static int instance_mkdir(const char *name)
+ 
+ 	INIT_LIST_HEAD(&tr->systems);
+ 	INIT_LIST_HEAD(&tr->events);
++	INIT_LIST_HEAD(&tr->hist_vars);
+ 
+ 	if (allocate_trace_buffers(tr, trace_buf_size) < 0)
+ 		goto out_free_tr;
+@@ -8415,6 +8416,7 @@ __init static int tracer_alloc_buffers(void)
+ 
+ 	INIT_LIST_HEAD(&global_trace.systems);
+ 	INIT_LIST_HEAD(&global_trace.events);
++	INIT_LIST_HEAD(&global_trace.hist_vars);
+ 	list_add(&global_trace.list, &ftrace_trace_arrays);
+ 
+ 	apply_trace_boot_options();
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index a94cc69b8a4a..630a341f9b99 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -274,6 +274,7 @@ struct trace_array {
+ 	int			function_enabled;
+ #endif
+ 	int			time_stamp_abs_ref;
++	struct list_head	hist_vars;
+ };
+ 
+ enum {
+@@ -1550,6 +1551,8 @@ extern void pause_named_trigger(struct event_trigger_data *data);
+ extern void unpause_named_trigger(struct event_trigger_data *data);
+ extern void set_named_trigger_data(struct event_trigger_data *data,
+ 				   struct event_trigger_data *named_data);
++extern struct event_trigger_data *
++get_named_trigger_data(struct event_trigger_data *data);
+ extern int register_event_command(struct event_command *cmd);
+ extern int unregister_event_command(struct event_command *cmd);
+ extern int register_trigger_hist_enable_disable_cmds(void);
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index e30bd86bee8e..dbcdd2ff76a4 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -59,7 +59,12 @@ struct hist_field {
+ 	struct hist_trigger_data	*hist_data;
+ 	struct hist_var			var;
+ 	enum field_op_id		operator;
++	char				*system;
++	char				*event_name;
+ 	char				*name;
++	unsigned int			var_idx;
++	unsigned int			var_ref_idx;
++	bool                            read_once;
+ };
+ 
+ static u64 hist_field_none(struct hist_field *field,
+@@ -214,6 +219,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_TIMESTAMP_USECS	= 1 << 11,
+ 	HIST_FIELD_FL_VAR		= 1 << 12,
+ 	HIST_FIELD_FL_EXPR		= 1 << 13,
++	HIST_FIELD_FL_VAR_REF		= 1 << 14,
+ };
+ 
+ struct var_defs {
+@@ -253,6 +259,8 @@ struct hist_trigger_data {
+ 	struct tracing_map		*map;
+ 	bool				enable_timestamps;
+ 	bool				remove;
++	struct hist_field               *var_refs[TRACING_MAP_VARS_MAX];
++	unsigned int			n_var_refs;
+ };
+ 
+ static u64 hist_field_timestamp(struct hist_field *hist_field,
+@@ -271,6 +279,214 @@ static u64 hist_field_timestamp(struct hist_field *hist_field,
+ 	return ts;
+ }
+ 
++struct hist_var_data {
++	struct list_head list;
++	struct hist_trigger_data *hist_data;
++};
++
++static struct hist_field *
++check_field_for_var_ref(struct hist_field *hist_field,
++			struct hist_trigger_data *var_data,
++			unsigned int var_idx)
++{
++	struct hist_field *found = NULL;
++
++	if (hist_field && hist_field->flags & HIST_FIELD_FL_VAR_REF) {
++		if (hist_field->var.idx == var_idx &&
++		    hist_field->var.hist_data == var_data) {
++			found = hist_field;
++		}
++	}
++
++	return found;
++}
++
++static struct hist_field *
++check_field_for_var_refs(struct hist_trigger_data *hist_data,
++			 struct hist_field *hist_field,
++			 struct hist_trigger_data *var_data,
++			 unsigned int var_idx,
++			 unsigned int level)
++{
++	struct hist_field *found = NULL;
++	unsigned int i;
++
++	if (level > 3)
++		return found;
++
++	if (!hist_field)
++		return found;
++
++	found = check_field_for_var_ref(hist_field, var_data, var_idx);
++	if (found)
++		return found;
++
++	for (i = 0; i < HIST_FIELD_OPERANDS_MAX; i++) {
++		struct hist_field *operand;
++
++		operand = hist_field->operands[i];
++		found = check_field_for_var_refs(hist_data, operand, var_data,
++						 var_idx, level + 1);
++		if (found)
++			return found;
++	}
++
++	return found;
++}
++
++static struct hist_field *find_var_ref(struct hist_trigger_data *hist_data,
++				       struct hist_trigger_data *var_data,
++				       unsigned int var_idx)
++{
++	struct hist_field *hist_field, *found = NULL;
++	unsigned int i;
++
++	for_each_hist_field(i, hist_data) {
++		hist_field = hist_data->fields[i];
++		found = check_field_for_var_refs(hist_data, hist_field,
++						 var_data, var_idx, 0);
++		if (found)
++			return found;
++	}
++
++	return found;
++}
++
++static struct hist_field *find_any_var_ref(struct hist_trigger_data *hist_data,
++					   unsigned int var_idx)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_field *found = NULL;
++	struct hist_var_data *var_data;
++
++	list_for_each_entry(var_data, &tr->hist_vars, list) {
++		if (var_data->hist_data == hist_data)
++			continue;
++		found = find_var_ref(var_data->hist_data, hist_data, var_idx);
++		if (found)
++			break;
++	}
++
++	return found;
++}
++
++static bool check_var_refs(struct hist_trigger_data *hist_data)
++{
++	struct hist_field *field;
++	bool found = false;
++	int i;
++
++	for_each_hist_field(i, hist_data) {
++		field = hist_data->fields[i];
++		if (field && field->flags & HIST_FIELD_FL_VAR) {
++			if (find_any_var_ref(hist_data, field->var.idx)) {
++				found = true;
++				break;
++			}
++		}
++	}
++
++	return found;
++}
++
++static struct hist_var_data *find_hist_vars(struct hist_trigger_data *hist_data)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_var_data *var_data, *found = NULL;
++
++	list_for_each_entry(var_data, &tr->hist_vars, list) {
++		if (var_data->hist_data == hist_data) {
++			found = var_data;
++			break;
++		}
++	}
++
++	return found;
++}
++
++static bool field_has_hist_vars(struct hist_field *hist_field,
++				unsigned int level)
++{
++	int i;
++
++	if (level > 3)
++		return false;
++
++	if (!hist_field)
++		return false;
++
++	if (hist_field->flags & HIST_FIELD_FL_VAR ||
++	    hist_field->flags & HIST_FIELD_FL_VAR_REF)
++		return true;
++
++	for (i = 0; i < HIST_FIELD_OPERANDS_MAX; i++) {
++		struct hist_field *operand;
++
++		operand = hist_field->operands[i];
++		if (field_has_hist_vars(operand, level + 1))
++			return true;
++	}
++
++	return false;
++}
++
++static bool has_hist_vars(struct hist_trigger_data *hist_data)
++{
++	struct hist_field *hist_field;
++	int i;
++
++	for_each_hist_field(i, hist_data) {
++		hist_field = hist_data->fields[i];
++		if (field_has_hist_vars(hist_field, 0))
++			return true;
++	}
++
++	return false;
++}
++
++static int save_hist_vars(struct hist_trigger_data *hist_data)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_var_data *var_data;
++
++	var_data = find_hist_vars(hist_data);
++	if (var_data)
++		return 0;
++
++	if (trace_array_get(tr) < 0)
++		return -ENODEV;
++
++	var_data = kzalloc(sizeof(*var_data), GFP_KERNEL);
++	if (!var_data) {
++		trace_array_put(tr);
++		return -ENOMEM;
++	}
++
++	var_data->hist_data = hist_data;
++	list_add(&var_data->list, &tr->hist_vars);
++
++	return 0;
++}
++
++static void remove_hist_vars(struct hist_trigger_data *hist_data)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_var_data *var_data;
++
++	var_data = find_hist_vars(hist_data);
++	if (!var_data)
++		return;
++
++	if (WARN_ON(check_var_refs(hist_data)))
++		return;
++
++	list_del(&var_data->list);
++
++	kfree(var_data);
++
++	trace_array_put(tr);
++}
++
+ static struct hist_field *find_var_field(struct hist_trigger_data *hist_data,
+ 					 const char *var_name)
+ {
+@@ -313,10 +529,137 @@ static struct hist_field *find_var(struct hist_trigger_data *hist_data,
+ 	return NULL;
+ }
+ 
++static struct trace_event_file *find_var_file(struct trace_array *tr,
++					      char *system,
++					      char *event_name,
++					      char *var_name)
++{
++	struct hist_trigger_data *var_hist_data;
++	struct hist_var_data *var_data;
++	struct trace_event_file *file, *found = NULL;
++
++	if (system)
++		return find_event_file(tr, system, event_name);
++
++	list_for_each_entry(var_data, &tr->hist_vars, list) {
++		var_hist_data = var_data->hist_data;
++		file = var_hist_data->event_file;
++		if (file == found)
++			continue;
++
++		if (find_var_field(var_hist_data, var_name)) {
++			if (found)
++				return NULL;
++
++			found = file;
++		}
++	}
++
++	return found;
++}
++
++static struct hist_field *find_file_var(struct trace_event_file *file,
++					const char *var_name)
++{
++	struct hist_trigger_data *test_data;
++	struct event_trigger_data *test;
++	struct hist_field *hist_field;
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			test_data = test->private_data;
++			hist_field = find_var_field(test_data, var_name);
++			if (hist_field)
++				return hist_field;
++		}
++	}
++
++	return NULL;
++}
++
++static struct hist_field *find_event_var(struct hist_trigger_data *hist_data,
++					 char *system,
++					 char *event_name,
++					 char *var_name)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_field *hist_field = NULL;
++	struct trace_event_file *file;
++
++	file = find_var_file(tr, system, event_name, var_name);
++	if (!file)
++		return NULL;
++
++	hist_field = find_file_var(file, var_name);
++
++	return hist_field;
++}
++
+ struct hist_elt_data {
+ 	char *comm;
++	u64 *var_ref_vals;
+ };
+ 
++static u64 hist_field_var_ref(struct hist_field *hist_field,
++			      struct tracing_map_elt *elt,
++			      struct ring_buffer_event *rbe,
++			      void *event)
++{
++	struct hist_elt_data *elt_data;
++	u64 var_val = 0;
++
++	elt_data = elt->private_data;
++	var_val = elt_data->var_ref_vals[hist_field->var_ref_idx];
++
++	return var_val;
++}
++
++static bool resolve_var_refs(struct hist_trigger_data *hist_data, void *key,
++			     u64 *var_ref_vals, bool self)
++{
++	struct hist_trigger_data *var_data;
++	struct tracing_map_elt *var_elt;
++	struct hist_field *hist_field;
++	unsigned int i, var_idx;
++	bool resolved = true;
++	u64 var_val = 0;
++
++	for (i = 0; i < hist_data->n_var_refs; i++) {
++		hist_field = hist_data->var_refs[i];
++		var_idx = hist_field->var.idx;
++		var_data = hist_field->var.hist_data;
++
++		if (var_data == NULL) {
++			resolved = false;
++			break;
++		}
++
++		if ((self && var_data != hist_data) ||
++		    (!self && var_data == hist_data))
++			continue;
++
++		var_elt = tracing_map_lookup(var_data->map, key);
++		if (!var_elt) {
++			resolved = false;
++			break;
++		}
++
++		if (!tracing_map_var_set(var_elt, var_idx)) {
++			resolved = false;
++			break;
++		}
++
++		if (self || !hist_field->read_once)
++			var_val = tracing_map_read_var(var_elt, var_idx);
++		else
++			var_val = tracing_map_read_var_once(var_elt, var_idx);
++
++		var_ref_vals[i] = var_val;
++	}
++
++	return resolved;
++}
++
+ static const char *hist_field_name(struct hist_field *field,
+ 				   unsigned int level)
+ {
+@@ -331,8 +674,20 @@ static const char *hist_field_name(struct hist_field *field,
+ 		field_name = hist_field_name(field->operands[0], ++level);
+ 	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		field_name = "common_timestamp";
+-	else if (field->flags & HIST_FIELD_FL_EXPR)
+-		field_name = field->name;
++	else if (field->flags & HIST_FIELD_FL_EXPR ||
++		 field->flags & HIST_FIELD_FL_VAR_REF) {
++		if (field->system) {
++			static char full_name[MAX_FILTER_STR_VAL];
++
++			strcat(full_name, field->system);
++			strcat(full_name, ".");
++			strcat(full_name, field->event_name);
++			strcat(full_name, ".");
++			strcat(full_name, field->name);
++			field_name = full_name;
++		} else
++			field_name = field->name;
++	}
+ 
+ 	if (field_name == NULL)
+ 		field_name = "";
+@@ -612,6 +967,9 @@ static const char *get_hist_field_flags(struct hist_field *hist_field)
+ 
+ static void expr_field_str(struct hist_field *field, char *expr)
+ {
++	if (field->flags & HIST_FIELD_FL_VAR_REF)
++		strcat(expr, "$");
++
+ 	strcat(expr, hist_field_name(field, 0));
+ 
+ 	if (field->flags) {
+@@ -742,6 +1100,11 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 	if (flags & HIST_FIELD_FL_EXPR)
+ 		goto out; /* caller will populate */
+ 
++	if (flags & HIST_FIELD_FL_VAR_REF) {
++		hist_field->fn = hist_field_var_ref;
++		goto out;
++	}
++
+ 	if (flags & HIST_FIELD_FL_HITCOUNT) {
+ 		hist_field->fn = hist_field_counter;
+ 		hist_field->size = sizeof(u64);
+@@ -835,6 +1198,144 @@ static void destroy_hist_fields(struct hist_trigger_data *hist_data)
+ 	}
+ }
+ 
++static int init_var_ref(struct hist_field *ref_field,
++			struct hist_field *var_field,
++			char *system, char *event_name)
++{
++	int err = 0;
++
++	ref_field->var.idx = var_field->var.idx;
++	ref_field->var.hist_data = var_field->hist_data;
++	ref_field->size = var_field->size;
++	ref_field->is_signed = var_field->is_signed;
++	ref_field->flags |= var_field->flags &
++		(HIST_FIELD_FL_TIMESTAMP | HIST_FIELD_FL_TIMESTAMP_USECS);
++
++	if (system) {
++		ref_field->system = kstrdup(system, GFP_KERNEL);
++		if (!ref_field->system)
++			return -ENOMEM;
++	}
++
++	if (event_name) {
++		ref_field->event_name = kstrdup(event_name, GFP_KERNEL);
++		if (!ref_field->event_name) {
++			err = -ENOMEM;
++			goto free;
++		}
++	}
++
++	ref_field->name = kstrdup(var_field->var.name, GFP_KERNEL);
++	if (!ref_field->name) {
++		err = -ENOMEM;
++		goto free;
++	}
++
++	ref_field->type = kstrdup(var_field->type, GFP_KERNEL);
++	if (!ref_field->type) {
++		err = -ENOMEM;
++		goto free;
++	}
++ out:
++	return err;
++ free:
++	kfree(ref_field->system);
++	kfree(ref_field->event_name);
++	kfree(ref_field->name);
++
++	goto out;
++}
++
++static struct hist_field *create_var_ref(struct hist_field *var_field,
++					 char *system, char *event_name)
++{
++	unsigned long flags = HIST_FIELD_FL_VAR_REF;
++	struct hist_field *ref_field;
++
++	ref_field = create_hist_field(var_field->hist_data, NULL, flags, NULL);
++	if (ref_field) {
++		if (init_var_ref(ref_field, var_field, system, event_name)) {
++			destroy_hist_field(ref_field, 0);
++			return NULL;
++		}
++	}
++
++	return ref_field;
++}
++
++static bool is_var_ref(char *var_name)
++{
++	if (!var_name || strlen(var_name) < 2 || var_name[0] != '$')
++		return false;
++
++	return true;
++}
++
++static char *field_name_from_var(struct hist_trigger_data *hist_data,
++				 char *var_name)
++{
++	char *name, *field;
++	unsigned int i;
++
++	for (i = 0; i < hist_data->attrs->var_defs.n_vars; i++) {
++		name = hist_data->attrs->var_defs.name[i];
++
++		if (strcmp(var_name, name) == 0) {
++			field = hist_data->attrs->var_defs.expr[i];
++			if (contains_operator(field) || is_var_ref(field))
++				continue;
++			return field;
++		}
++	}
++
++	return NULL;
++}
++
++static char *local_field_var_ref(struct hist_trigger_data *hist_data,
++				 char *system, char *event_name,
++				 char *var_name)
++{
++	struct trace_event_call *call;
++
++	if (system && event_name) {
++		call = hist_data->event_file->event_call;
++
++		if (strcmp(system, call->class->system) != 0)
++			return NULL;
++
++		if (strcmp(event_name, trace_event_name(call)) != 0)
++			return NULL;
++	}
++
++	if (!!system != !!event_name)
++		return NULL;
++
++	if (!is_var_ref(var_name))
++		return NULL;
++
++	var_name++;
++
++	return field_name_from_var(hist_data, var_name);
++}
++
++static struct hist_field *parse_var_ref(struct hist_trigger_data *hist_data,
++					char *system, char *event_name,
++					char *var_name)
++{
++	struct hist_field *var_field = NULL, *ref_field = NULL;
++
++	if (!is_var_ref(var_name))
++		return NULL;
++
++	var_name++;
++
++	var_field = find_event_var(hist_data, system, event_name, var_name);
++	if (var_field)
++		ref_field = create_var_ref(var_field, system, event_name);
++
++	return ref_field;
++}
++
+ static struct ftrace_event_field *
+ parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
+ 	    char *field_str, unsigned long *flags)
+@@ -891,10 +1392,40 @@ static struct hist_field *parse_atom(struct hist_trigger_data *hist_data,
+ 				     struct trace_event_file *file, char *str,
+ 				     unsigned long *flags, char *var_name)
+ {
++	char *s, *ref_system = NULL, *ref_event = NULL, *ref_var = str;
+ 	struct ftrace_event_field *field = NULL;
+ 	struct hist_field *hist_field = NULL;
+ 	int ret = 0;
+ 
++	s = strchr(str, '.');
++	if (s) {
++		s = strchr(++s, '.');
++		if (s) {
++			ref_system = strsep(&str, ".");
++			if (!str) {
++				ret = -EINVAL;
++				goto out;
++			}
++			ref_event = strsep(&str, ".");
++			if (!str) {
++				ret = -EINVAL;
++				goto out;
++			}
++			ref_var = str;
++		}
++	}
++
++	s = local_field_var_ref(hist_data, ref_system, ref_event, ref_var);
++	if (!s) {
++		hist_field = parse_var_ref(hist_data, ref_system, ref_event, ref_var);
++		if (hist_field) {
++			hist_data->var_refs[hist_data->n_var_refs] = hist_field;
++			hist_field->var_ref_idx = hist_data->n_var_refs++;
++			return hist_field;
++		}
++	} else
++		str = s;
++
+ 	field = parse_field(hist_data, file, str, flags);
+ 	if (IS_ERR(field)) {
+ 		ret = PTR_ERR(field);
+@@ -1066,6 +1597,9 @@ static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
+ 		goto free;
+ 	}
+ 
++	operand1->read_once = true;
++	operand2->read_once = true;
++
+ 	expr->operands[0] = operand1;
+ 	expr->operands[1] = operand2;
+ 	expr->operator = field_op;
+@@ -1238,6 +1772,12 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 			goto out;
+ 		}
+ 
++		if (hist_field->flags & HIST_FIELD_FL_VAR_REF) {
++			destroy_hist_field(hist_field, 0);
++			ret = -EINVAL;
++			goto out;
++		}
++
+ 		key_size = hist_field->size;
+ 	}
+ 
+@@ -1576,6 +2116,7 @@ create_hist_data(unsigned int map_bits,
+ 
+ 	hist_data->attrs = attrs;
+ 	hist_data->remove = remove;
++	hist_data->event_file = file;
+ 
+ 	ret = create_hist_fields(hist_data, file);
+ 	if (ret)
+@@ -1598,12 +2139,6 @@ create_hist_data(unsigned int map_bits,
+ 	ret = create_tracing_map_fields(hist_data);
+ 	if (ret)
+ 		goto free;
+-
+-	ret = tracing_map_init(hist_data->map);
+-	if (ret)
+-		goto free;
+-
+-	hist_data->event_file = file;
+  out:
+ 	return hist_data;
+  free:
+@@ -1618,12 +2153,17 @@ create_hist_data(unsigned int map_bits,
+ 
+ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 				    struct tracing_map_elt *elt, void *rec,
+-				    struct ring_buffer_event *rbe)
++				    struct ring_buffer_event *rbe,
++				    u64 *var_ref_vals)
+ {
++	struct hist_elt_data *elt_data;
+ 	struct hist_field *hist_field;
+ 	unsigned int i, var_idx;
+ 	u64 hist_val;
+ 
++	elt_data = elt->private_data;
++	elt_data->var_ref_vals = var_ref_vals;
++
+ 	for_each_hist_val_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+ 		hist_val = hist_field->fn(hist_field, elt, rbe, rec);
+@@ -1675,6 +2215,7 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 	struct hist_trigger_data *hist_data = data->private_data;
+ 	bool use_compound_key = (hist_data->n_keys > 1);
+ 	unsigned long entries[HIST_STACKTRACE_DEPTH];
++	u64 var_ref_vals[TRACING_MAP_VARS_MAX];
+ 	char compound_key[HIST_KEY_SIZE_MAX];
+ 	struct tracing_map_elt *elt = NULL;
+ 	struct stack_trace stacktrace;
+@@ -1714,9 +2255,15 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 	if (use_compound_key)
+ 		key = compound_key;
+ 
++	if (hist_data->n_var_refs &&
++	    !resolve_var_refs(hist_data, key, var_ref_vals, false))
++		return;
++
+ 	elt = tracing_map_insert(hist_data->map, key);
+-	if (elt)
+-		hist_trigger_elt_update(hist_data, elt, rec, rbe);
++	if (!elt)
++		return;
++
++	hist_trigger_elt_update(hist_data, elt, rec, rbe, var_ref_vals);
+ }
+ 
+ static void hist_trigger_stacktrace_print(struct seq_file *m,
+@@ -1931,8 +2478,11 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ 
+ 	if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		seq_puts(m, "common_timestamp");
+-	else if (field_name)
++	else if (field_name) {
++		if (hist_field->flags & HIST_FIELD_FL_VAR_REF)
++			seq_putc(m, '$');
+ 		seq_printf(m, "%s", field_name);
++	}
+ 
+ 	if (hist_field->flags) {
+ 		const char *flags_str = get_hist_field_flags(hist_field);
+@@ -2072,7 +2622,11 @@ static void event_hist_trigger_free(struct event_trigger_ops *ops,
+ 	if (!data->ref) {
+ 		if (data->name)
+ 			del_named_trigger(data);
++
+ 		trigger_data_free(data);
++
++		remove_hist_vars(hist_data);
++
+ 		destroy_hist_data(hist_data);
+ 	}
+ }
+@@ -2285,23 +2839,55 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 			goto out;
+ 	}
+ 
+-	list_add_rcu(&data->list, &file->triggers);
+ 	ret++;
+ 
+-	update_cond_flag(file);
+-
+ 	if (hist_data->enable_timestamps)
+ 		tracing_set_time_stamp_abs(file->tr, true);
++ out:
++	return ret;
++}
++
++static int hist_trigger_enable(struct event_trigger_data *data,
++			       struct trace_event_file *file)
++{
++	int ret = 0;
++
++	list_add_tail_rcu(&data->list, &file->triggers);
++
++	update_cond_flag(file);
+ 
+ 	if (trace_event_trigger_enable_disable(file, 1) < 0) {
+ 		list_del_rcu(&data->list);
+ 		update_cond_flag(file);
+ 		ret--;
+ 	}
+- out:
++
+ 	return ret;
+ }
+ 
++static bool hist_trigger_check_refs(struct event_trigger_data *data,
++				    struct trace_event_file *file)
++{
++	struct hist_trigger_data *hist_data = data->private_data;
++	struct event_trigger_data *test, *named_data = NULL;
++
++	if (hist_data->attrs->name)
++		named_data = find_named_trigger(hist_data->attrs->name);
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			if (!hist_trigger_match(data, test, named_data, false))
++				continue;
++			hist_data = test->private_data;
++			if (check_var_refs(hist_data))
++				return true;
++			break;
++		}
++	}
++
++	return false;
++}
++
+ static void hist_unregister_trigger(char *glob, struct event_trigger_ops *ops,
+ 				    struct event_trigger_data *data,
+ 				    struct trace_event_file *file)
+@@ -2334,11 +2920,30 @@ static void hist_unregister_trigger(char *glob, struct event_trigger_ops *ops,
+ 	}
+ }
+ 
++static bool hist_file_check_refs(struct trace_event_file *file)
++{
++	struct hist_trigger_data *hist_data;
++	struct event_trigger_data *test;
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			hist_data = test->private_data;
++			if (check_var_refs(hist_data))
++				return true;
++		}
++	}
++
++	return false;
++}
++
+ static void hist_unreg_all(struct trace_event_file *file)
+ {
+ 	struct event_trigger_data *test, *n;
+ 	struct hist_trigger_data *hist_data;
+ 
++	if (hist_file_check_refs(file))
++		return;
++
+ 	list_for_each_entry_safe(test, n, &file->triggers, list) {
+ 		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
+ 			hist_data = test->private_data;
+@@ -2414,6 +3019,11 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	}
+ 
+ 	if (remove) {
++		if (hist_trigger_check_refs(trigger_data, file)) {
++			ret = -EBUSY;
++			goto out_free;
++		}
++
+ 		cmd_ops->unreg(glob+1, trigger_ops, trigger_data, file);
+ 		ret = 0;
+ 		goto out_free;
+@@ -2431,14 +3041,33 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 		goto out_free;
+ 	} else if (ret < 0)
+ 		goto out_free;
++
++	if (get_named_trigger_data(trigger_data))
++		goto enable;
++
++	if (has_hist_vars(hist_data))
++		save_hist_vars(hist_data);
++
++	ret = tracing_map_init(hist_data->map);
++	if (ret)
++		goto out_unreg;
++enable:
++	ret = hist_trigger_enable(trigger_data, file);
++	if (ret)
++		goto out_unreg;
++
+ 	/* Just return zero, not the number of registered triggers */
+ 	ret = 0;
+  out:
+ 	return ret;
++ out_unreg:
++	cmd_ops->unreg(glob+1, trigger_ops, trigger_data, file);
+  out_free:
+ 	if (cmd_ops->set_filter)
+ 		cmd_ops->set_filter(NULL, trigger_data, NULL);
+ 
++	remove_hist_vars(hist_data);
++
+ 	kfree(trigger_data);
+ 
+ 	destroy_hist_data(hist_data);
+diff --git a/kernel/trace/trace_events_trigger.c b/kernel/trace/trace_events_trigger.c
+index 4c269f2e00a4..24d42350d738 100644
+--- a/kernel/trace/trace_events_trigger.c
++++ b/kernel/trace/trace_events_trigger.c
+@@ -915,6 +915,12 @@ void set_named_trigger_data(struct event_trigger_data *data,
+ 	data->named_data = named_data;
+ }
+ 
++struct event_trigger_data *
++get_named_trigger_data(struct event_trigger_data *data)
++{
++	return data->named_data;
++}
++
+ static void
+ traceon_trigger(struct event_trigger_data *data, void *rec,
+ 		struct ring_buffer_event *event)
+-- 
+2.19.0
+
diff --git a/patches/1769-tracing-Add-hist-trigger-action-hook.patch b/patches/1769-tracing-Add-hist-trigger-action-hook.patch
new file mode 100644
index 00000000000000..125ce14628924a
--- /dev/null
+++ b/patches/1769-tracing-Add-hist-trigger-action-hook.patch
@@ -0,0 +1,222 @@
+From 530958fd375270ea3e3473ccd8e304e7f997d5c3 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:57 -0600
+Subject: [PATCH 1769/1795] tracing: Add hist trigger action hook
+
+Add a hook for executing extra actions whenever a histogram entry is
+added or updated.
+
+The default 'action' when a hist entry is added to a histogram is to
+update the set of values associated with it.  Some applications may
+want to perform additional actions at that point, such as generate
+another event, or compare and save a maximum.
+
+Add a simple framework for doing that; specific actions will be
+implemented on top of it in later patches.
+
+Link: http://lkml.kernel.org/r/9482ba6a3eaf5ca6e60954314beacd0e25c05b24.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 0212e2aa30e112363aa559f30f6c24ae095f3e78)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 106 ++++++++++++++++++++++++++++++-
+ 1 file changed, 104 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index dbcdd2ff76a4..68b9d6d396a6 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -33,6 +33,7 @@ typedef u64 (*hist_field_fn_t) (struct hist_field *field,
+ 
+ #define HIST_FIELD_OPERANDS_MAX	2
+ #define HIST_FIELDS_MAX		(TRACING_MAP_FIELDS_MAX + TRACING_MAP_VARS_MAX)
++#define HIST_ACTIONS_MAX	8
+ 
+ enum field_op_id {
+ 	FIELD_OP_NONE,
+@@ -242,6 +243,9 @@ struct hist_trigger_attrs {
+ 	char		*assignment_str[TRACING_MAP_VARS_MAX];
+ 	unsigned int	n_assignments;
+ 
++	char		*action_str[HIST_ACTIONS_MAX];
++	unsigned int	n_actions;
++
+ 	struct var_defs	var_defs;
+ };
+ 
+@@ -261,6 +265,21 @@ struct hist_trigger_data {
+ 	bool				remove;
+ 	struct hist_field               *var_refs[TRACING_MAP_VARS_MAX];
+ 	unsigned int			n_var_refs;
++
++	struct action_data		*actions[HIST_ACTIONS_MAX];
++	unsigned int			n_actions;
++};
++
++struct action_data;
++
++typedef void (*action_fn_t) (struct hist_trigger_data *hist_data,
++			     struct tracing_map_elt *elt, void *rec,
++			     struct ring_buffer_event *rbe,
++			     struct action_data *data, u64 *var_ref_vals);
++
++struct action_data {
++	action_fn_t		fn;
++	unsigned int		var_ref_idx;
+ };
+ 
+ static u64 hist_field_timestamp(struct hist_field *hist_field,
+@@ -764,6 +783,9 @@ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ 	for (i = 0; i < attrs->n_assignments; i++)
+ 		kfree(attrs->assignment_str[i]);
+ 
++	for (i = 0; i < attrs->n_actions; i++)
++		kfree(attrs->action_str[i]);
++
+ 	kfree(attrs->name);
+ 	kfree(attrs->sort_key_str);
+ 	kfree(attrs->keys_str);
+@@ -771,6 +793,16 @@ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ 	kfree(attrs);
+ }
+ 
++static int parse_action(char *str, struct hist_trigger_attrs *attrs)
++{
++	int ret = 0;
++
++	if (attrs->n_actions >= HIST_ACTIONS_MAX)
++		return ret;
++
++	return ret;
++}
++
+ static int parse_assignment(char *str, struct hist_trigger_attrs *attrs)
+ {
+ 	int ret = 0;
+@@ -854,8 +886,9 @@ static struct hist_trigger_attrs *parse_hist_trigger_attrs(char *trigger_str)
+ 		else if (strcmp(str, "clear") == 0)
+ 			attrs->clear = true;
+ 		else {
+-			ret = -EINVAL;
+-			goto free;
++			ret = parse_action(str, attrs);
++			if (ret)
++				goto free;
+ 		}
+ 	}
+ 
+@@ -2047,11 +2080,55 @@ static int create_sort_keys(struct hist_trigger_data *hist_data)
+ 	return ret;
+ }
+ 
++static void destroy_actions(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		struct action_data *data = hist_data->actions[i];
++
++		kfree(data);
++	}
++}
++
++static int parse_actions(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++	int ret = 0;
++	char *str;
++
++	for (i = 0; i < hist_data->attrs->n_actions; i++) {
++		str = hist_data->attrs->action_str[i];
++	}
++
++	return ret;
++}
++
++static int create_actions(struct hist_trigger_data *hist_data,
++			  struct trace_event_file *file)
++{
++	struct action_data *data;
++	unsigned int i;
++	int ret = 0;
++
++	for (i = 0; i < hist_data->attrs->n_actions; i++) {
++		data = hist_data->actions[i];
++	}
++
++	return ret;
++}
++
+ static void destroy_hist_data(struct hist_trigger_data *hist_data)
+ {
++	if (!hist_data)
++		return;
++
+ 	destroy_hist_trigger_attrs(hist_data->attrs);
+ 	destroy_hist_fields(hist_data);
+ 	tracing_map_destroy(hist_data->map);
++
++	destroy_actions(hist_data);
++
+ 	kfree(hist_data);
+ }
+ 
+@@ -2118,6 +2195,10 @@ create_hist_data(unsigned int map_bits,
+ 	hist_data->remove = remove;
+ 	hist_data->event_file = file;
+ 
++	ret = parse_actions(hist_data);
++	if (ret)
++		goto free;
++
+ 	ret = create_hist_fields(hist_data, file);
+ 	if (ret)
+ 		goto free;
+@@ -2209,6 +2290,20 @@ static inline void add_to_key(char *compound_key, void *key,
+ 	memcpy(compound_key + key_field->offset, key, size);
+ }
+ 
++static void
++hist_trigger_actions(struct hist_trigger_data *hist_data,
++		     struct tracing_map_elt *elt, void *rec,
++		     struct ring_buffer_event *rbe, u64 *var_ref_vals)
++{
++	struct action_data *data;
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		data = hist_data->actions[i];
++		data->fn(hist_data, elt, rec, rbe, data, var_ref_vals);
++	}
++}
++
+ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 			       struct ring_buffer_event *rbe)
+ {
+@@ -2264,6 +2359,9 @@ static void event_hist_trigger(struct event_trigger_data *data, void *rec,
+ 		return;
+ 
+ 	hist_trigger_elt_update(hist_data, elt, rec, rbe, var_ref_vals);
++
++	if (resolve_var_refs(hist_data, key, var_ref_vals, true))
++		hist_trigger_actions(hist_data, elt, rec, rbe, var_ref_vals);
+ }
+ 
+ static void hist_trigger_stacktrace_print(struct seq_file *m,
+@@ -3048,6 +3146,10 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	if (has_hist_vars(hist_data))
+ 		save_hist_vars(hist_data);
+ 
++	ret = create_actions(hist_data, file);
++	if (ret)
++		goto out_unreg;
++
+ 	ret = tracing_map_init(hist_data->map);
+ 	if (ret)
+ 		goto out_unreg;
+-- 
+2.19.0
+
diff --git a/patches/1770-tracing-Make-traceprobe-parsing-code-reusable.patch b/patches/1770-tracing-Make-traceprobe-parsing-code-reusable.patch
new file mode 100644
index 00000000000000..317aa4c631e1b7
--- /dev/null
+++ b/patches/1770-tracing-Make-traceprobe-parsing-code-reusable.patch
@@ -0,0 +1,338 @@
+From b3576ef6aa2a20ca333d4f249b346eb021ef25b6 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Fri, 22 Sep 2017 14:58:20 -0500
+Subject: [PATCH 1770/1795] tracing: Make traceprobe parsing code reusable
+
+traceprobe_probes_write() and traceprobe_command() actually contain
+nothing that ties them to kprobes - the code is generically useful for
+similar types of parsing elsewhere, so separate it out and move it to
+trace.c/trace.h.
+
+Other than moving it, the only change is in naming:
+traceprobe_probes_write() becomes trace_parse_run_command() and
+traceprobe_command() becomes trace_run_command().
+
+Link: http://lkml.kernel.org/r/ae5c26ea40c196a8986854d921eb6e713ede7e3f.1506105045.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 7e465baa80293ed5f87fdf6405391d6f02110d4e)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace.c        | 86 +++++++++++++++++++++++++++++++++++++
+ kernel/trace/trace.h        |  7 +++
+ kernel/trace/trace_kprobe.c | 18 ++++----
+ kernel/trace/trace_probe.c  | 86 -------------------------------------
+ kernel/trace/trace_probe.h  |  7 ---
+ kernel/trace/trace_uprobe.c |  2 +-
+ 6 files changed, 103 insertions(+), 103 deletions(-)
+
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index e487a2bf4520..101addc0f4ea 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -8316,6 +8316,92 @@ void ftrace_dump(enum ftrace_dump_mode oops_dump_mode)
+ }
+ EXPORT_SYMBOL_GPL(ftrace_dump);
+ 
++int trace_run_command(const char *buf, int (*createfn)(int, char **))
++{
++	char **argv;
++	int argc, ret;
++
++	argc = 0;
++	ret = 0;
++	argv = argv_split(GFP_KERNEL, buf, &argc);
++	if (!argv)
++		return -ENOMEM;
++
++	if (argc)
++		ret = createfn(argc, argv);
++
++	argv_free(argv);
++
++	return ret;
++}
++
++#define WRITE_BUFSIZE  4096
++
++ssize_t trace_parse_run_command(struct file *file, const char __user *buffer,
++				size_t count, loff_t *ppos,
++				int (*createfn)(int, char **))
++{
++	char *kbuf, *buf, *tmp;
++	int ret = 0;
++	size_t done = 0;
++	size_t size;
++
++	kbuf = kmalloc(WRITE_BUFSIZE, GFP_KERNEL);
++	if (!kbuf)
++		return -ENOMEM;
++
++	while (done < count) {
++		size = count - done;
++
++		if (size >= WRITE_BUFSIZE)
++			size = WRITE_BUFSIZE - 1;
++
++		if (copy_from_user(kbuf, buffer + done, size)) {
++			ret = -EFAULT;
++			goto out;
++		}
++		kbuf[size] = '\0';
++		buf = kbuf;
++		do {
++			tmp = strchr(buf, '\n');
++			if (tmp) {
++				*tmp = '\0';
++				size = tmp - buf + 1;
++			} else {
++				size = strlen(buf);
++				if (done + size < count) {
++					if (buf != kbuf)
++						break;
++					/* This can accept WRITE_BUFSIZE - 2 ('\n' + '\0') */
++					pr_warn("Line length is too long: Should be less than %d\n",
++						WRITE_BUFSIZE - 2);
++					ret = -EINVAL;
++					goto out;
++				}
++			}
++			done += size;
++
++			/* Remove comments */
++			tmp = strchr(buf, '#');
++
++			if (tmp)
++				*tmp = '\0';
++
++			ret = trace_run_command(buf, createfn);
++			if (ret)
++				goto out;
++			buf += size;
++
++		} while (done < count);
++	}
++	ret = done;
++
++out:
++	kfree(kbuf);
++
++	return ret;
++}
++
+ __init static int tracer_alloc_buffers(void)
+ {
+ 	int ring_buf_size;
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 630a341f9b99..5975d5f5c4bc 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -1764,6 +1764,13 @@ void trace_printk_start_comm(void);
+ int trace_keep_overwrite(struct tracer *tracer, u32 mask, int set);
+ int set_tracer_flag(struct trace_array *tr, unsigned int mask, int enabled);
+ 
++#define MAX_EVENT_NAME_LEN	64
++
++extern int trace_run_command(const char *buf, int (*createfn)(int, char**));
++extern ssize_t trace_parse_run_command(struct file *file,
++		const char __user *buffer, size_t count, loff_t *ppos,
++		int (*createfn)(int, char**));
++
+ /*
+  * Normal trace_printk() and friends allocates special buffers
+  * to do the manipulation, as well as saves the print formats
+diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c
+index ea20274a105a..3c40d4174052 100644
+--- a/kernel/trace/trace_kprobe.c
++++ b/kernel/trace/trace_kprobe.c
+@@ -918,8 +918,8 @@ static int probes_open(struct inode *inode, struct file *file)
+ static ssize_t probes_write(struct file *file, const char __user *buffer,
+ 			    size_t count, loff_t *ppos)
+ {
+-	return traceprobe_probes_write(file, buffer, count, ppos,
+-			create_trace_kprobe);
++	return trace_parse_run_command(file, buffer, count, ppos,
++				       create_trace_kprobe);
+ }
+ 
+ static const struct file_operations kprobe_events_ops = {
+@@ -1444,9 +1444,9 @@ static __init int kprobe_trace_self_tests_init(void)
+ 
+ 	pr_info("Testing kprobe tracing: ");
+ 
+-	ret = traceprobe_command("p:testprobe kprobe_trace_selftest_target "
+-				  "$stack $stack0 +0($stack)",
+-				  create_trace_kprobe);
++	ret = trace_run_command("p:testprobe kprobe_trace_selftest_target "
++				"$stack $stack0 +0($stack)",
++				create_trace_kprobe);
+ 	if (WARN_ON_ONCE(ret)) {
+ 		pr_warn("error on probing function entry.\n");
+ 		warn++;
+@@ -1466,8 +1466,8 @@ static __init int kprobe_trace_self_tests_init(void)
+ 		}
+ 	}
+ 
+-	ret = traceprobe_command("r:testprobe2 kprobe_trace_selftest_target "
+-				  "$retval", create_trace_kprobe);
++	ret = trace_run_command("r:testprobe2 kprobe_trace_selftest_target "
++				"$retval", create_trace_kprobe);
+ 	if (WARN_ON_ONCE(ret)) {
+ 		pr_warn("error on probing function return.\n");
+ 		warn++;
+@@ -1537,13 +1537,13 @@ static __init int kprobe_trace_self_tests_init(void)
+ 			disable_trace_kprobe(tk, file);
+ 	}
+ 
+-	ret = traceprobe_command("-:testprobe", create_trace_kprobe);
++	ret = trace_run_command("-:testprobe", create_trace_kprobe);
+ 	if (WARN_ON_ONCE(ret)) {
+ 		pr_warn("error on deleting a probe.\n");
+ 		warn++;
+ 	}
+ 
+-	ret = traceprobe_command("-:testprobe2", create_trace_kprobe);
++	ret = trace_run_command("-:testprobe2", create_trace_kprobe);
+ 	if (WARN_ON_ONCE(ret)) {
+ 		pr_warn("error on deleting a probe.\n");
+ 		warn++;
+diff --git a/kernel/trace/trace_probe.c b/kernel/trace/trace_probe.c
+index fe4513330412..daf54bda4dc8 100644
+--- a/kernel/trace/trace_probe.c
++++ b/kernel/trace/trace_probe.c
+@@ -621,92 +621,6 @@ void traceprobe_free_probe_arg(struct probe_arg *arg)
+ 	kfree(arg->comm);
+ }
+ 
+-int traceprobe_command(const char *buf, int (*createfn)(int, char **))
+-{
+-	char **argv;
+-	int argc, ret;
+-
+-	argc = 0;
+-	ret = 0;
+-	argv = argv_split(GFP_KERNEL, buf, &argc);
+-	if (!argv)
+-		return -ENOMEM;
+-
+-	if (argc)
+-		ret = createfn(argc, argv);
+-
+-	argv_free(argv);
+-
+-	return ret;
+-}
+-
+-#define WRITE_BUFSIZE  4096
+-
+-ssize_t traceprobe_probes_write(struct file *file, const char __user *buffer,
+-				size_t count, loff_t *ppos,
+-				int (*createfn)(int, char **))
+-{
+-	char *kbuf, *buf, *tmp;
+-	int ret = 0;
+-	size_t done = 0;
+-	size_t size;
+-
+-	kbuf = kmalloc(WRITE_BUFSIZE, GFP_KERNEL);
+-	if (!kbuf)
+-		return -ENOMEM;
+-
+-	while (done < count) {
+-		size = count - done;
+-
+-		if (size >= WRITE_BUFSIZE)
+-			size = WRITE_BUFSIZE - 1;
+-
+-		if (copy_from_user(kbuf, buffer + done, size)) {
+-			ret = -EFAULT;
+-			goto out;
+-		}
+-		kbuf[size] = '\0';
+-		buf = kbuf;
+-		do {
+-			tmp = strchr(buf, '\n');
+-			if (tmp) {
+-				*tmp = '\0';
+-				size = tmp - buf + 1;
+-			} else {
+-				size = strlen(buf);
+-				if (done + size < count) {
+-					if (buf != kbuf)
+-						break;
+-					/* This can accept WRITE_BUFSIZE - 2 ('\n' + '\0') */
+-					pr_warn("Line length is too long: Should be less than %d\n",
+-						WRITE_BUFSIZE - 2);
+-					ret = -EINVAL;
+-					goto out;
+-				}
+-			}
+-			done += size;
+-
+-			/* Remove comments */
+-			tmp = strchr(buf, '#');
+-
+-			if (tmp)
+-				*tmp = '\0';
+-
+-			ret = traceprobe_command(buf, createfn);
+-			if (ret)
+-				goto out;
+-			buf += size;
+-
+-		} while (done < count);
+-	}
+-	ret = done;
+-
+-out:
+-	kfree(kbuf);
+-
+-	return ret;
+-}
+-
+ static int __set_print_fmt(struct trace_probe *tp, char *buf, int len,
+ 			   bool is_return)
+ {
+diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h
+index dc39472ca9e4..a0d750e3d17c 100644
+--- a/kernel/trace/trace_probe.h
++++ b/kernel/trace/trace_probe.h
+@@ -42,7 +42,6 @@
+ 
+ #define MAX_TRACE_ARGS		128
+ #define MAX_ARGSTR_LEN		63
+-#define MAX_EVENT_NAME_LEN	64
+ #define MAX_STRING_SIZE		PATH_MAX
+ 
+ /* Reserved field names */
+@@ -356,12 +355,6 @@ extern void traceprobe_free_probe_arg(struct probe_arg *arg);
+ 
+ extern int traceprobe_split_symbol_offset(char *symbol, long *offset);
+ 
+-extern ssize_t traceprobe_probes_write(struct file *file,
+-		const char __user *buffer, size_t count, loff_t *ppos,
+-		int (*createfn)(int, char**));
+-
+-extern int traceprobe_command(const char *buf, int (*createfn)(int, char**));
+-
+ /* Sum up total data length for dynamic arraies (strings) */
+ static nokprobe_inline int
+ __get_data_size(struct trace_probe *tp, struct pt_regs *regs)
+diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c
+index ea0d90a31fc9..2ccfbb8efeb2 100644
+--- a/kernel/trace/trace_uprobe.c
++++ b/kernel/trace/trace_uprobe.c
+@@ -647,7 +647,7 @@ static int probes_open(struct inode *inode, struct file *file)
+ static ssize_t probes_write(struct file *file, const char __user *buffer,
+ 			    size_t count, loff_t *ppos)
+ {
+-	return traceprobe_probes_write(file, buffer, count, ppos, create_trace_uprobe);
++	return trace_parse_run_command(file, buffer, count, ppos, create_trace_uprobe);
+ }
+ 
+ static const struct file_operations uprobe_events_ops = {
+-- 
+2.19.0
+
diff --git a/patches/1771-tracing-Add-support-for-synthetic-events.patch b/patches/1771-tracing-Add-support-for-synthetic-events.patch
new file mode 100644
index 00000000000000..d39c32bb41cada
--- /dev/null
+++ b/patches/1771-tracing-Add-support-for-synthetic-events.patch
@@ -0,0 +1,1048 @@
+From 7b6cbe966903572cee7e9457cf63633751f2af18 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:58 -0600
+Subject: [PATCH 1771/1795] tracing: Add support for 'synthetic' events
+
+Synthetic events are user-defined events generated from hist trigger
+variables saved from one or more other events.
+
+To define a synthetic event, the user writes a simple specification
+consisting of the name of the new event along with one or more
+variables and their type(s), to the tracing/synthetic_events file.
+
+For instance, the following creates a new event named 'wakeup_latency'
+with 3 fields: lat, pid, and prio:
+
+    # echo 'wakeup_latency u64 lat; pid_t pid; int prio' >> \
+      /sys/kernel/debug/tracing/synthetic_events
+
+Reading the tracing/synthetic_events file lists all the
+currently-defined synthetic events, in this case the event we defined
+above:
+
+    # cat /sys/kernel/debug/tracing/synthetic_events
+    wakeup_latency u64 lat; pid_t pid; int prio
+
+At this point, the synthetic event is ready to use, and a histogram
+can be defined using it:
+
+    # echo 'hist:keys=pid,prio,lat.log2:sort=pid,lat' >> \
+    /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/trigger
+
+The new event is created under the tracing/events/synthetic/ directory
+and looks and behaves just like any other event:
+
+    # ls /sys/kernel/debug/tracing/events/synthetic/wakeup_latency
+      enable  filter  format  hist  id  trigger
+
+Although a histogram can be defined for it, nothing will happen until
+an action tracing that event via the trace_synth() function occurs.
+The trace_synth() function is very similar to all the other trace_*
+invocations spread throughout the kernel, except in this case the
+trace_ function and its corresponding tracepoint isn't statically
+generated but defined by the user at run-time.
+
+How this can be automatically hooked up via a hist trigger 'action' is
+discussed in a subsequent patch.
+
+Link: http://lkml.kernel.org/r/c68df2284b7d172669daf9be29db62ad49bbc559.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+[fix noderef.cocci warnings, sizeof pointer for kcalloc of event->fields]
+Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 4b147936fa509650beaf638b331573c23ba4d609)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 895 ++++++++++++++++++++++++++++++-
+ 1 file changed, 893 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 68b9d6d396a6..80d16d33ad5e 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -20,10 +20,16 @@
+ #include <linux/slab.h>
+ #include <linux/stacktrace.h>
+ #include <linux/rculist.h>
++#include <linux/tracefs.h>
+ 
+ #include "tracing_map.h"
+ #include "trace.h"
+ 
++#define SYNTH_SYSTEM		"synthetic"
++#define SYNTH_FIELDS_MAX	16
++
++#define STR_VAR_LEN_MAX		32 /* must be multiple of sizeof(u64) */
++
+ struct hist_field;
+ 
+ typedef u64 (*hist_field_fn_t) (struct hist_field *field,
+@@ -270,6 +276,26 @@ struct hist_trigger_data {
+ 	unsigned int			n_actions;
+ };
+ 
++struct synth_field {
++	char *type;
++	char *name;
++	size_t size;
++	bool is_signed;
++	bool is_string;
++};
++
++struct synth_event {
++	struct list_head			list;
++	int					ref;
++	char					*name;
++	struct synth_field			**fields;
++	unsigned int				n_fields;
++	unsigned int				n_u64;
++	struct trace_event_class		class;
++	struct trace_event_call			call;
++	struct tracepoint			*tp;
++};
++
+ struct action_data;
+ 
+ typedef void (*action_fn_t) (struct hist_trigger_data *hist_data,
+@@ -282,6 +308,790 @@ struct action_data {
+ 	unsigned int		var_ref_idx;
+ };
+ 
++static LIST_HEAD(synth_event_list);
++static DEFINE_MUTEX(synth_event_mutex);
++
++struct synth_trace_event {
++	struct trace_entry	ent;
++	u64			fields[];
++};
++
++static int synth_event_define_fields(struct trace_event_call *call)
++{
++	struct synth_trace_event trace;
++	int offset = offsetof(typeof(trace), fields);
++	struct synth_event *event = call->data;
++	unsigned int i, size, n_u64;
++	char *name, *type;
++	bool is_signed;
++	int ret = 0;
++
++	for (i = 0, n_u64 = 0; i < event->n_fields; i++) {
++		size = event->fields[i]->size;
++		is_signed = event->fields[i]->is_signed;
++		type = event->fields[i]->type;
++		name = event->fields[i]->name;
++		ret = trace_define_field(call, type, name, offset, size,
++					 is_signed, FILTER_OTHER);
++		if (ret)
++			break;
++
++		if (event->fields[i]->is_string) {
++			offset += STR_VAR_LEN_MAX;
++			n_u64 += STR_VAR_LEN_MAX / sizeof(u64);
++		} else {
++			offset += sizeof(u64);
++			n_u64++;
++		}
++	}
++
++	event->n_u64 = n_u64;
++
++	return ret;
++}
++
++static bool synth_field_signed(char *type)
++{
++	if (strncmp(type, "u", 1) == 0)
++		return false;
++
++	return true;
++}
++
++static int synth_field_is_string(char *type)
++{
++	if (strstr(type, "char[") != NULL)
++		return true;
++
++	return false;
++}
++
++static int synth_field_string_size(char *type)
++{
++	char buf[4], *end, *start;
++	unsigned int len;
++	int size, err;
++
++	start = strstr(type, "char[");
++	if (start == NULL)
++		return -EINVAL;
++	start += strlen("char[");
++
++	end = strchr(type, ']');
++	if (!end || end < start)
++		return -EINVAL;
++
++	len = end - start;
++	if (len > 3)
++		return -EINVAL;
++
++	strncpy(buf, start, len);
++	buf[len] = '\0';
++
++	err = kstrtouint(buf, 0, &size);
++	if (err)
++		return err;
++
++	if (size > STR_VAR_LEN_MAX)
++		return -EINVAL;
++
++	return size;
++}
++
++static int synth_field_size(char *type)
++{
++	int size = 0;
++
++	if (strcmp(type, "s64") == 0)
++		size = sizeof(s64);
++	else if (strcmp(type, "u64") == 0)
++		size = sizeof(u64);
++	else if (strcmp(type, "s32") == 0)
++		size = sizeof(s32);
++	else if (strcmp(type, "u32") == 0)
++		size = sizeof(u32);
++	else if (strcmp(type, "s16") == 0)
++		size = sizeof(s16);
++	else if (strcmp(type, "u16") == 0)
++		size = sizeof(u16);
++	else if (strcmp(type, "s8") == 0)
++		size = sizeof(s8);
++	else if (strcmp(type, "u8") == 0)
++		size = sizeof(u8);
++	else if (strcmp(type, "char") == 0)
++		size = sizeof(char);
++	else if (strcmp(type, "unsigned char") == 0)
++		size = sizeof(unsigned char);
++	else if (strcmp(type, "int") == 0)
++		size = sizeof(int);
++	else if (strcmp(type, "unsigned int") == 0)
++		size = sizeof(unsigned int);
++	else if (strcmp(type, "long") == 0)
++		size = sizeof(long);
++	else if (strcmp(type, "unsigned long") == 0)
++		size = sizeof(unsigned long);
++	else if (strcmp(type, "pid_t") == 0)
++		size = sizeof(pid_t);
++	else if (synth_field_is_string(type))
++		size = synth_field_string_size(type);
++
++	return size;
++}
++
++static const char *synth_field_fmt(char *type)
++{
++	const char *fmt = "%llu";
++
++	if (strcmp(type, "s64") == 0)
++		fmt = "%lld";
++	else if (strcmp(type, "u64") == 0)
++		fmt = "%llu";
++	else if (strcmp(type, "s32") == 0)
++		fmt = "%d";
++	else if (strcmp(type, "u32") == 0)
++		fmt = "%u";
++	else if (strcmp(type, "s16") == 0)
++		fmt = "%d";
++	else if (strcmp(type, "u16") == 0)
++		fmt = "%u";
++	else if (strcmp(type, "s8") == 0)
++		fmt = "%d";
++	else if (strcmp(type, "u8") == 0)
++		fmt = "%u";
++	else if (strcmp(type, "char") == 0)
++		fmt = "%d";
++	else if (strcmp(type, "unsigned char") == 0)
++		fmt = "%u";
++	else if (strcmp(type, "int") == 0)
++		fmt = "%d";
++	else if (strcmp(type, "unsigned int") == 0)
++		fmt = "%u";
++	else if (strcmp(type, "long") == 0)
++		fmt = "%ld";
++	else if (strcmp(type, "unsigned long") == 0)
++		fmt = "%lu";
++	else if (strcmp(type, "pid_t") == 0)
++		fmt = "%d";
++	else if (synth_field_is_string(type))
++		fmt = "%s";
++
++	return fmt;
++}
++
++static enum print_line_t print_synth_event(struct trace_iterator *iter,
++					   int flags,
++					   struct trace_event *event)
++{
++	struct trace_array *tr = iter->tr;
++	struct trace_seq *s = &iter->seq;
++	struct synth_trace_event *entry;
++	struct synth_event *se;
++	unsigned int i, n_u64;
++	char print_fmt[32];
++	const char *fmt;
++
++	entry = (struct synth_trace_event *)iter->ent;
++	se = container_of(event, struct synth_event, call.event);
++
++	trace_seq_printf(s, "%s: ", se->name);
++
++	for (i = 0, n_u64 = 0; i < se->n_fields; i++) {
++		if (trace_seq_has_overflowed(s))
++			goto end;
++
++		fmt = synth_field_fmt(se->fields[i]->type);
++
++		/* parameter types */
++		if (tr->trace_flags & TRACE_ITER_VERBOSE)
++			trace_seq_printf(s, "%s ", fmt);
++
++		snprintf(print_fmt, sizeof(print_fmt), "%%s=%s%%s", fmt);
++
++		/* parameter values */
++		if (se->fields[i]->is_string) {
++			trace_seq_printf(s, print_fmt, se->fields[i]->name,
++					 (char *)&entry->fields[n_u64],
++					 i == se->n_fields - 1 ? "" : " ");
++			n_u64 += STR_VAR_LEN_MAX / sizeof(u64);
++		} else {
++			trace_seq_printf(s, print_fmt, se->fields[i]->name,
++					 entry->fields[n_u64],
++					 i == se->n_fields - 1 ? "" : " ");
++			n_u64++;
++		}
++	}
++end:
++	trace_seq_putc(s, '\n');
++
++	return trace_handle_return(s);
++}
++
++static struct trace_event_functions synth_event_funcs = {
++	.trace		= print_synth_event
++};
++
++static notrace void trace_event_raw_event_synth(void *__data,
++						u64 *var_ref_vals,
++						unsigned int var_ref_idx)
++{
++	struct trace_event_file *trace_file = __data;
++	struct synth_trace_event *entry;
++	struct trace_event_buffer fbuffer;
++	struct synth_event *event;
++	unsigned int i, n_u64;
++	int fields_size = 0;
++
++	event = trace_file->event_call->data;
++
++	if (trace_trigger_soft_disabled(trace_file))
++		return;
++
++	fields_size = event->n_u64 * sizeof(u64);
++
++	entry = trace_event_buffer_reserve(&fbuffer, trace_file,
++					   sizeof(*entry) + fields_size);
++	if (!entry)
++		return;
++
++	for (i = 0, n_u64 = 0; i < event->n_fields; i++) {
++		if (event->fields[i]->is_string) {
++			char *str_val = (char *)(long)var_ref_vals[var_ref_idx + i];
++			char *str_field = (char *)&entry->fields[n_u64];
++
++			strncpy(str_field, str_val, STR_VAR_LEN_MAX);
++			n_u64 += STR_VAR_LEN_MAX / sizeof(u64);
++		} else {
++			entry->fields[n_u64] = var_ref_vals[var_ref_idx + i];
++			n_u64++;
++		}
++	}
++
++	trace_event_buffer_commit(&fbuffer);
++}
++
++static void free_synth_event_print_fmt(struct trace_event_call *call)
++{
++	if (call) {
++		kfree(call->print_fmt);
++		call->print_fmt = NULL;
++	}
++}
++
++static int __set_synth_event_print_fmt(struct synth_event *event,
++				       char *buf, int len)
++{
++	const char *fmt;
++	int pos = 0;
++	int i;
++
++	/* When len=0, we just calculate the needed length */
++#define LEN_OR_ZERO (len ? len - pos : 0)
++
++	pos += snprintf(buf + pos, LEN_OR_ZERO, "\"");
++	for (i = 0; i < event->n_fields; i++) {
++		fmt = synth_field_fmt(event->fields[i]->type);
++		pos += snprintf(buf + pos, LEN_OR_ZERO, "%s=%s%s",
++				event->fields[i]->name, fmt,
++				i == event->n_fields - 1 ? "" : ", ");
++	}
++	pos += snprintf(buf + pos, LEN_OR_ZERO, "\"");
++
++	for (i = 0; i < event->n_fields; i++) {
++		pos += snprintf(buf + pos, LEN_OR_ZERO,
++				", REC->%s", event->fields[i]->name);
++	}
++
++#undef LEN_OR_ZERO
++
++	/* return the length of print_fmt */
++	return pos;
++}
++
++static int set_synth_event_print_fmt(struct trace_event_call *call)
++{
++	struct synth_event *event = call->data;
++	char *print_fmt;
++	int len;
++
++	/* First: called with 0 length to calculate the needed length */
++	len = __set_synth_event_print_fmt(event, NULL, 0);
++
++	print_fmt = kmalloc(len + 1, GFP_KERNEL);
++	if (!print_fmt)
++		return -ENOMEM;
++
++	/* Second: actually write the @print_fmt */
++	__set_synth_event_print_fmt(event, print_fmt, len + 1);
++	call->print_fmt = print_fmt;
++
++	return 0;
++}
++
++static void free_synth_field(struct synth_field *field)
++{
++	kfree(field->type);
++	kfree(field->name);
++	kfree(field);
++}
++
++static struct synth_field *parse_synth_field(char *field_type,
++					     char *field_name)
++{
++	struct synth_field *field;
++	int len, ret = 0;
++	char *array;
++
++	if (field_type[0] == ';')
++		field_type++;
++
++	len = strlen(field_name);
++	if (field_name[len - 1] == ';')
++		field_name[len - 1] = '\0';
++
++	field = kzalloc(sizeof(*field), GFP_KERNEL);
++	if (!field)
++		return ERR_PTR(-ENOMEM);
++
++	len = strlen(field_type) + 1;
++	array = strchr(field_name, '[');
++	if (array)
++		len += strlen(array);
++	field->type = kzalloc(len, GFP_KERNEL);
++	if (!field->type) {
++		ret = -ENOMEM;
++		goto free;
++	}
++	strcat(field->type, field_type);
++	if (array) {
++		strcat(field->type, array);
++		*array = '\0';
++	}
++
++	field->size = synth_field_size(field->type);
++	if (!field->size) {
++		ret = -EINVAL;
++		goto free;
++	}
++
++	if (synth_field_is_string(field->type))
++		field->is_string = true;
++
++	field->is_signed = synth_field_signed(field->type);
++
++	field->name = kstrdup(field_name, GFP_KERNEL);
++	if (!field->name) {
++		ret = -ENOMEM;
++		goto free;
++	}
++ out:
++	return field;
++ free:
++	free_synth_field(field);
++	field = ERR_PTR(ret);
++	goto out;
++}
++
++static void free_synth_tracepoint(struct tracepoint *tp)
++{
++	if (!tp)
++		return;
++
++	kfree(tp->name);
++	kfree(tp);
++}
++
++static struct tracepoint *alloc_synth_tracepoint(char *name)
++{
++	struct tracepoint *tp;
++
++	tp = kzalloc(sizeof(*tp), GFP_KERNEL);
++	if (!tp)
++		return ERR_PTR(-ENOMEM);
++
++	tp->name = kstrdup(name, GFP_KERNEL);
++	if (!tp->name) {
++		kfree(tp);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	return tp;
++}
++
++typedef void (*synth_probe_func_t) (void *__data, u64 *var_ref_vals,
++				    unsigned int var_ref_idx);
++
++static inline void trace_synth(struct synth_event *event, u64 *var_ref_vals,
++			       unsigned int var_ref_idx)
++{
++	struct tracepoint *tp = event->tp;
++
++	if (unlikely(atomic_read(&tp->key.enabled) > 0)) {
++		struct tracepoint_func *probe_func_ptr;
++		synth_probe_func_t probe_func;
++		void *__data;
++
++		if (!(cpu_online(raw_smp_processor_id())))
++			return;
++
++		probe_func_ptr = rcu_dereference_sched((tp)->funcs);
++		if (probe_func_ptr) {
++			do {
++				probe_func = probe_func_ptr->func;
++				__data = probe_func_ptr->data;
++				probe_func(__data, var_ref_vals, var_ref_idx);
++			} while ((++probe_func_ptr)->func);
++		}
++	}
++}
++
++static struct synth_event *find_synth_event(const char *name)
++{
++	struct synth_event *event;
++
++	list_for_each_entry(event, &synth_event_list, list) {
++		if (strcmp(event->name, name) == 0)
++			return event;
++	}
++
++	return NULL;
++}
++
++static int register_synth_event(struct synth_event *event)
++{
++	struct trace_event_call *call = &event->call;
++	int ret = 0;
++
++	event->call.class = &event->class;
++	event->class.system = kstrdup(SYNTH_SYSTEM, GFP_KERNEL);
++	if (!event->class.system) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	event->tp = alloc_synth_tracepoint(event->name);
++	if (IS_ERR(event->tp)) {
++		ret = PTR_ERR(event->tp);
++		event->tp = NULL;
++		goto out;
++	}
++
++	INIT_LIST_HEAD(&call->class->fields);
++	call->event.funcs = &synth_event_funcs;
++	call->class->define_fields = synth_event_define_fields;
++
++	ret = register_trace_event(&call->event);
++	if (!ret) {
++		ret = -ENODEV;
++		goto out;
++	}
++	call->flags = TRACE_EVENT_FL_TRACEPOINT;
++	call->class->reg = trace_event_reg;
++	call->class->probe = trace_event_raw_event_synth;
++	call->data = event;
++	call->tp = event->tp;
++
++	ret = trace_add_event_call(call);
++	if (ret) {
++		pr_warn("Failed to register synthetic event: %s\n",
++			trace_event_name(call));
++		goto err;
++	}
++
++	ret = set_synth_event_print_fmt(call);
++	if (ret < 0) {
++		trace_remove_event_call(call);
++		goto err;
++	}
++ out:
++	return ret;
++ err:
++	unregister_trace_event(&call->event);
++	goto out;
++}
++
++static int unregister_synth_event(struct synth_event *event)
++{
++	struct trace_event_call *call = &event->call;
++	int ret;
++
++	ret = trace_remove_event_call(call);
++
++	return ret;
++}
++
++static void free_synth_event(struct synth_event *event)
++{
++	unsigned int i;
++
++	if (!event)
++		return;
++
++	for (i = 0; i < event->n_fields; i++)
++		free_synth_field(event->fields[i]);
++
++	kfree(event->fields);
++	kfree(event->name);
++	kfree(event->class.system);
++	free_synth_tracepoint(event->tp);
++	free_synth_event_print_fmt(&event->call);
++	kfree(event);
++}
++
++static struct synth_event *alloc_synth_event(char *event_name, int n_fields,
++					     struct synth_field **fields)
++{
++	struct synth_event *event;
++	unsigned int i;
++
++	event = kzalloc(sizeof(*event), GFP_KERNEL);
++	if (!event) {
++		event = ERR_PTR(-ENOMEM);
++		goto out;
++	}
++
++	event->name = kstrdup(event_name, GFP_KERNEL);
++	if (!event->name) {
++		kfree(event);
++		event = ERR_PTR(-ENOMEM);
++		goto out;
++	}
++
++	event->fields = kcalloc(n_fields, sizeof(*event->fields), GFP_KERNEL);
++	if (!event->fields) {
++		free_synth_event(event);
++		event = ERR_PTR(-ENOMEM);
++		goto out;
++	}
++
++	for (i = 0; i < n_fields; i++)
++		event->fields[i] = fields[i];
++
++	event->n_fields = n_fields;
++ out:
++	return event;
++}
++
++static void add_or_delete_synth_event(struct synth_event *event, int delete)
++{
++	if (delete)
++		free_synth_event(event);
++	else {
++		mutex_lock(&synth_event_mutex);
++		if (!find_synth_event(event->name))
++			list_add(&event->list, &synth_event_list);
++		else
++			free_synth_event(event);
++		mutex_unlock(&synth_event_mutex);
++	}
++}
++
++static int create_synth_event(int argc, char **argv)
++{
++	struct synth_field *field, *fields[SYNTH_FIELDS_MAX];
++	struct synth_event *event = NULL;
++	bool delete_event = false;
++	int i, n_fields = 0, ret = 0;
++	char *name;
++
++	mutex_lock(&synth_event_mutex);
++
++	/*
++	 * Argument syntax:
++	 *  - Add synthetic event: <event_name> field[;field] ...
++	 *  - Remove synthetic event: !<event_name> field[;field] ...
++	 *      where 'field' = type field_name
++	 */
++	if (argc < 1) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	name = argv[0];
++	if (name[0] == '!') {
++		delete_event = true;
++		name++;
++	}
++
++	event = find_synth_event(name);
++	if (event) {
++		if (delete_event) {
++			if (event->ref) {
++				event = NULL;
++				ret = -EBUSY;
++				goto out;
++			}
++			list_del(&event->list);
++			goto out;
++		}
++		event = NULL;
++		ret = -EEXIST;
++		goto out;
++	} else if (delete_event)
++		goto out;
++
++	if (argc < 2) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	for (i = 1; i < argc - 1; i++) {
++		if (strcmp(argv[i], ";") == 0)
++			continue;
++		if (n_fields == SYNTH_FIELDS_MAX) {
++			ret = -EINVAL;
++			goto err;
++		}
++
++		field = parse_synth_field(argv[i], argv[i + 1]);
++		if (IS_ERR(field)) {
++			ret = PTR_ERR(field);
++			goto err;
++		}
++		fields[n_fields] = field;
++		i++; n_fields++;
++	}
++
++	if (i < argc) {
++		ret = -EINVAL;
++		goto err;
++	}
++
++	event = alloc_synth_event(name, n_fields, fields);
++	if (IS_ERR(event)) {
++		ret = PTR_ERR(event);
++		event = NULL;
++		goto err;
++	}
++ out:
++	mutex_unlock(&synth_event_mutex);
++
++	if (event) {
++		if (delete_event) {
++			ret = unregister_synth_event(event);
++			add_or_delete_synth_event(event, !ret);
++		} else {
++			ret = register_synth_event(event);
++			add_or_delete_synth_event(event, ret);
++		}
++	}
++
++	return ret;
++ err:
++	mutex_unlock(&synth_event_mutex);
++
++	for (i = 0; i < n_fields; i++)
++		free_synth_field(fields[i]);
++	free_synth_event(event);
++
++	return ret;
++}
++
++static int release_all_synth_events(void)
++{
++	struct list_head release_events;
++	struct synth_event *event, *e;
++	int ret = 0;
++
++	INIT_LIST_HEAD(&release_events);
++
++	mutex_lock(&synth_event_mutex);
++
++	list_for_each_entry(event, &synth_event_list, list) {
++		if (event->ref) {
++			mutex_unlock(&synth_event_mutex);
++			return -EBUSY;
++		}
++	}
++
++	list_splice_init(&event->list, &release_events);
++
++	mutex_unlock(&synth_event_mutex);
++
++	list_for_each_entry_safe(event, e, &release_events, list) {
++		list_del(&event->list);
++
++		ret = unregister_synth_event(event);
++		add_or_delete_synth_event(event, !ret);
++	}
++
++	return ret;
++}
++
++
++static void *synth_events_seq_start(struct seq_file *m, loff_t *pos)
++{
++	mutex_lock(&synth_event_mutex);
++
++	return seq_list_start(&synth_event_list, *pos);
++}
++
++static void *synth_events_seq_next(struct seq_file *m, void *v, loff_t *pos)
++{
++	return seq_list_next(v, &synth_event_list, pos);
++}
++
++static void synth_events_seq_stop(struct seq_file *m, void *v)
++{
++	mutex_unlock(&synth_event_mutex);
++}
++
++static int synth_events_seq_show(struct seq_file *m, void *v)
++{
++	struct synth_field *field;
++	struct synth_event *event = v;
++	unsigned int i;
++
++	seq_printf(m, "%s\t", event->name);
++
++	for (i = 0; i < event->n_fields; i++) {
++		field = event->fields[i];
++
++		/* parameter values */
++		seq_printf(m, "%s %s%s", field->type, field->name,
++			   i == event->n_fields - 1 ? "" : "; ");
++	}
++
++	seq_putc(m, '\n');
++
++	return 0;
++}
++
++static const struct seq_operations synth_events_seq_op = {
++	.start  = synth_events_seq_start,
++	.next   = synth_events_seq_next,
++	.stop   = synth_events_seq_stop,
++	.show   = synth_events_seq_show
++};
++
++static int synth_events_open(struct inode *inode, struct file *file)
++{
++	int ret;
++
++	if ((file->f_mode & FMODE_WRITE) && (file->f_flags & O_TRUNC)) {
++		ret = release_all_synth_events();
++		if (ret < 0)
++			return ret;
++	}
++
++	return seq_open(file, &synth_events_seq_op);
++}
++
++static ssize_t synth_events_write(struct file *file,
++				  const char __user *buffer,
++				  size_t count, loff_t *ppos)
++{
++	return trace_parse_run_command(file, buffer, count, ppos,
++				       create_synth_event);
++}
++
++static const struct file_operations synth_events_fops = {
++	.open           = synth_events_open,
++	.write		= synth_events_write,
++	.read           = seq_read,
++	.llseek         = seq_lseek,
++	.release        = seq_release,
++};
++
+ static u64 hist_field_timestamp(struct hist_field *hist_field,
+ 				struct tracing_map_elt *elt,
+ 				struct ring_buffer_event *rbe,
+@@ -2963,6 +3773,28 @@ static int hist_trigger_enable(struct event_trigger_data *data,
+ 	return ret;
+ }
+ 
++static bool have_hist_trigger_match(struct event_trigger_data *data,
++				    struct trace_event_file *file)
++{
++	struct hist_trigger_data *hist_data = data->private_data;
++	struct event_trigger_data *test, *named_data = NULL;
++	bool match = false;
++
++	if (hist_data->attrs->name)
++		named_data = find_named_trigger(hist_data->attrs->name);
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			if (hist_trigger_match(data, test, named_data, false)) {
++				match = true;
++				break;
++			}
++		}
++	}
++
++	return match;
++}
++
+ static bool hist_trigger_check_refs(struct event_trigger_data *data,
+ 				    struct trace_event_file *file)
+ {
+@@ -3038,6 +3870,8 @@ static void hist_unreg_all(struct trace_event_file *file)
+ {
+ 	struct event_trigger_data *test, *n;
+ 	struct hist_trigger_data *hist_data;
++	struct synth_event *se;
++	const char *se_name;
+ 
+ 	if (hist_file_check_refs(file))
+ 		return;
+@@ -3047,6 +3881,14 @@ static void hist_unreg_all(struct trace_event_file *file)
+ 			hist_data = test->private_data;
+ 			list_del_rcu(&test->list);
+ 			trace_event_trigger_enable_disable(file, 0);
++
++			mutex_lock(&synth_event_mutex);
++			se_name = trace_event_name(file->event_call);
++			se = find_synth_event(se_name);
++			if (se)
++				se->ref--;
++			mutex_unlock(&synth_event_mutex);
++
+ 			update_cond_flag(file);
+ 			if (hist_data->enable_timestamps)
+ 				tracing_set_time_stamp_abs(file->tr, false);
+@@ -3065,6 +3907,8 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	struct hist_trigger_attrs *attrs;
+ 	struct event_trigger_ops *trigger_ops;
+ 	struct hist_trigger_data *hist_data;
++	struct synth_event *se;
++	const char *se_name;
+ 	bool remove = false;
+ 	char *trigger;
+ 	int ret = 0;
+@@ -3095,10 +3939,11 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 
+ 	trigger_ops = cmd_ops->get_trigger_ops(cmd, trigger);
+ 
+-	ret = -ENOMEM;
+ 	trigger_data = kzalloc(sizeof(*trigger_data), GFP_KERNEL);
+-	if (!trigger_data)
++	if (!trigger_data) {
++		ret = -ENOMEM;
+ 		goto out_free;
++	}
+ 
+ 	trigger_data->count = -1;
+ 	trigger_data->ops = trigger_ops;
+@@ -3117,12 +3962,23 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	}
+ 
+ 	if (remove) {
++		if (!have_hist_trigger_match(trigger_data, file))
++			goto out_free;
++
+ 		if (hist_trigger_check_refs(trigger_data, file)) {
+ 			ret = -EBUSY;
+ 			goto out_free;
+ 		}
+ 
+ 		cmd_ops->unreg(glob+1, trigger_ops, trigger_data, file);
++
++		mutex_lock(&synth_event_mutex);
++		se_name = trace_event_name(file->event_call);
++		se = find_synth_event(se_name);
++		if (se)
++			se->ref--;
++		mutex_unlock(&synth_event_mutex);
++
+ 		ret = 0;
+ 		goto out_free;
+ 	}
+@@ -3158,6 +4014,13 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	if (ret)
+ 		goto out_unreg;
+ 
++	mutex_lock(&synth_event_mutex);
++	se_name = trace_event_name(file->event_call);
++	se = find_synth_event(se_name);
++	if (se)
++		se->ref++;
++	mutex_unlock(&synth_event_mutex);
++
+ 	/* Just return zero, not the number of registered triggers */
+ 	ret = 0;
+  out:
+@@ -3330,3 +4193,31 @@ __init int register_trigger_hist_enable_disable_cmds(void)
+ 
+ 	return ret;
+ }
++
++static __init int trace_events_hist_init(void)
++{
++	struct dentry *entry = NULL;
++	struct dentry *d_tracer;
++	int err = 0;
++
++	d_tracer = tracing_init_dentry();
++	if (IS_ERR(d_tracer)) {
++		err = PTR_ERR(d_tracer);
++		goto err;
++	}
++
++	entry = tracefs_create_file("synthetic_events", 0644, d_tracer,
++				    NULL, &synth_events_fops);
++	if (!entry) {
++		err = -ENODEV;
++		goto err;
++	}
++
++	return err;
++ err:
++	pr_warn("Could not create tracefs 'synthetic_events' entry\n");
++
++	return err;
++}
++
++fs_initcall(trace_events_hist_init);
+-- 
+2.19.0
+
diff --git a/patches/1772-tracing-Add-support-for-field-variables.patch b/patches/1772-tracing-Add-support-for-field-variables.patch
new file mode 100644
index 00000000000000..087b28d3e90fdc
--- /dev/null
+++ b/patches/1772-tracing-Add-support-for-field-variables.patch
@@ -0,0 +1,673 @@
+From c8c072b0c5467110bb974729f2eb51242f095081 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:51:59 -0600
+Subject: [PATCH 1772/1795] tracing: Add support for 'field variables'
+
+Users should be able to directly specify event fields in hist trigger
+'actions' rather than being forced to explicitly create a variable for
+that purpose.
+
+Add support allowing fields to be used directly in actions, which
+essentially does just that - creates 'invisible' variables for each
+bare field specified in an action.  If a bare field refers to a field
+on another (matching) event, it even creates a special histogram for
+the purpose (since variables can't be defined on an existing histogram
+after histogram creation).
+
+Here's a simple example that demonstrates both.  Basically the
+onmatch() action creates a list of variables corresponding to the
+parameters of the synthetic event to be generated, and then uses those
+values to generate the event.  So for the wakeup_latency synthetic
+event 'call' below the first param, $wakeup_lat, is a variable defined
+explicitly on sched_switch, where 'next_pid' is just a normal field on
+sched_switch, and prio is a normal field on sched_waking.
+
+Since the mechanism works on variables, those two normal fields just
+have 'invisible' variables created internally for them.  In the case of
+'prio', which is on another event, we actually need to create an
+additional hist trigger and define the invisible variable on that, since
+once a hist trigger is defined, variables can't be added to it later.
+
+  echo 'wakeup_latency u64 lat; pid_t pid; int prio' >>
+       /sys/kernel/debug/tracing/synthetic_events
+
+  echo 'hist:keys=pid:ts0=common_timestamp.usecs >>
+       /sys/kernel/debug/tracing/events/sched/sched_waking/trigger
+
+echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0:
+      onmatch(sched.sched_waking).wakeup_latency($wakeup_lat,next_pid,prio)
+            >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+Link: http://lkml.kernel.org/r/8e8dcdac1ea180ed7a3689e1caeeccede9dc42b3.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 02205a6752f223779a1b0e9e8ffacbea6e717851)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 531 ++++++++++++++++++++++++++++++-
+ 1 file changed, 530 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 80d16d33ad5e..ad96fd110707 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -255,6 +255,16 @@ struct hist_trigger_attrs {
+ 	struct var_defs	var_defs;
+ };
+ 
++struct field_var {
++	struct hist_field	*var;
++	struct hist_field	*val;
++};
++
++struct field_var_hist {
++	struct hist_trigger_data	*hist_data;
++	char				*cmd;
++};
++
+ struct hist_trigger_data {
+ 	struct hist_field               *fields[HIST_FIELDS_MAX];
+ 	unsigned int			n_vals;
+@@ -274,6 +284,12 @@ struct hist_trigger_data {
+ 
+ 	struct action_data		*actions[HIST_ACTIONS_MAX];
+ 	unsigned int			n_actions;
++
++	struct field_var		*field_vars[SYNTH_FIELDS_MAX];
++	unsigned int			n_field_vars;
++	unsigned int			n_field_var_str;
++	struct field_var_hist		*field_var_hists[SYNTH_FIELDS_MAX];
++	unsigned int			n_field_var_hists;
+ };
+ 
+ struct synth_field {
+@@ -1427,6 +1443,7 @@ static struct hist_field *find_event_var(struct hist_trigger_data *hist_data,
+ struct hist_elt_data {
+ 	char *comm;
+ 	u64 *var_ref_vals;
++	char *field_var_str[SYNTH_FIELDS_MAX];
+ };
+ 
+ static u64 hist_field_var_ref(struct hist_field *hist_field,
+@@ -1731,6 +1748,11 @@ static inline void save_comm(char *comm, struct task_struct *task)
+ 
+ static void hist_elt_data_free(struct hist_elt_data *elt_data)
+ {
++	unsigned int i;
++
++	for (i = 0; i < SYNTH_FIELDS_MAX; i++)
++		kfree(elt_data->field_var_str[i]);
++
+ 	kfree(elt_data->comm);
+ 	kfree(elt_data);
+ }
+@@ -1748,7 +1770,7 @@ static int hist_trigger_elt_data_alloc(struct tracing_map_elt *elt)
+ 	unsigned int size = TASK_COMM_LEN;
+ 	struct hist_elt_data *elt_data;
+ 	struct hist_field *key_field;
+-	unsigned int i;
++	unsigned int i, n_str;
+ 
+ 	elt_data = kzalloc(sizeof(*elt_data), GFP_KERNEL);
+ 	if (!elt_data)
+@@ -1767,6 +1789,18 @@ static int hist_trigger_elt_data_alloc(struct tracing_map_elt *elt)
+ 		}
+ 	}
+ 
++	n_str = hist_data->n_field_var_str;
++
++	size = STR_VAR_LEN_MAX;
++
++	for (i = 0; i < n_str; i++) {
++		elt_data->field_var_str[i] = kzalloc(size, GFP_KERNEL);
++		if (!elt_data->field_var_str[i]) {
++			hist_elt_data_free(elt_data);
++			return -ENOMEM;
++		}
++	}
++
+ 	elt->private_data = elt_data;
+ 
+ 	return 0;
+@@ -2473,6 +2507,470 @@ static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
+ 	return ERR_PTR(ret);
+ }
+ 
++static char *find_trigger_filter(struct hist_trigger_data *hist_data,
++				 struct trace_event_file *file)
++{
++	struct event_trigger_data *test;
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			if (test->private_data == hist_data)
++				return test->filter_str;
++		}
++	}
++
++	return NULL;
++}
++
++static struct event_command trigger_hist_cmd;
++static int event_hist_trigger_func(struct event_command *cmd_ops,
++				   struct trace_event_file *file,
++				   char *glob, char *cmd, char *param);
++
++static bool compatible_keys(struct hist_trigger_data *target_hist_data,
++			    struct hist_trigger_data *hist_data,
++			    unsigned int n_keys)
++{
++	struct hist_field *target_hist_field, *hist_field;
++	unsigned int n, i, j;
++
++	if (hist_data->n_fields - hist_data->n_vals != n_keys)
++		return false;
++
++	i = hist_data->n_vals;
++	j = target_hist_data->n_vals;
++
++	for (n = 0; n < n_keys; n++) {
++		hist_field = hist_data->fields[i + n];
++		target_hist_field = target_hist_data->fields[j + n];
++
++		if (strcmp(hist_field->type, target_hist_field->type) != 0)
++			return false;
++		if (hist_field->size != target_hist_field->size)
++			return false;
++		if (hist_field->is_signed != target_hist_field->is_signed)
++			return false;
++	}
++
++	return true;
++}
++
++static struct hist_trigger_data *
++find_compatible_hist(struct hist_trigger_data *target_hist_data,
++		     struct trace_event_file *file)
++{
++	struct hist_trigger_data *hist_data;
++	struct event_trigger_data *test;
++	unsigned int n_keys;
++
++	n_keys = target_hist_data->n_fields - target_hist_data->n_vals;
++
++	list_for_each_entry_rcu(test, &file->triggers, list) {
++		if (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {
++			hist_data = test->private_data;
++
++			if (compatible_keys(target_hist_data, hist_data, n_keys))
++				return hist_data;
++		}
++	}
++
++	return NULL;
++}
++
++static struct trace_event_file *event_file(struct trace_array *tr,
++					   char *system, char *event_name)
++{
++	struct trace_event_file *file;
++
++	file = find_event_file(tr, system, event_name);
++	if (!file)
++		return ERR_PTR(-EINVAL);
++
++	return file;
++}
++
++static struct hist_field *
++find_synthetic_field_var(struct hist_trigger_data *target_hist_data,
++			 char *system, char *event_name, char *field_name)
++{
++	struct hist_field *event_var;
++	char *synthetic_name;
++
++	synthetic_name = kzalloc(MAX_FILTER_STR_VAL, GFP_KERNEL);
++	if (!synthetic_name)
++		return ERR_PTR(-ENOMEM);
++
++	strcpy(synthetic_name, "synthetic_");
++	strcat(synthetic_name, field_name);
++
++	event_var = find_event_var(target_hist_data, system, event_name, synthetic_name);
++
++	kfree(synthetic_name);
++
++	return event_var;
++}
++
++/**
++ * create_field_var_hist - Automatically create a histogram and var for a field
++ * @target_hist_data: The target hist trigger
++ * @subsys_name: Optional subsystem name
++ * @event_name: Optional event name
++ * @field_name: The name of the field (and the resulting variable)
++ *
++ * Hist trigger actions fetch data from variables, not directly from
++ * events.  However, for convenience, users are allowed to directly
++ * specify an event field in an action, which will be automatically
++ * converted into a variable on their behalf.
++
++ * If a user specifies a field on an event that isn't the event the
++ * histogram currently being defined (the target event histogram), the
++ * only way that can be accomplished is if a new hist trigger is
++ * created and the field variable defined on that.
++ *
++ * This function creates a new histogram compatible with the target
++ * event (meaning a histogram with the same key as the target
++ * histogram), and creates a variable for the specified field, but
++ * with 'synthetic_' prepended to the variable name in order to avoid
++ * collision with normal field variables.
++ *
++ * Return: The variable created for the field.
++ */
++struct hist_field *
++create_field_var_hist(struct hist_trigger_data *target_hist_data,
++		      char *subsys_name, char *event_name, char *field_name)
++{
++	struct trace_array *tr = target_hist_data->event_file->tr;
++	struct hist_field *event_var = ERR_PTR(-EINVAL);
++	struct hist_trigger_data *hist_data;
++	unsigned int i, n, first = true;
++	struct field_var_hist *var_hist;
++	struct trace_event_file *file;
++	struct hist_field *key_field;
++	char *saved_filter;
++	char *cmd;
++	int ret;
++
++	if (target_hist_data->n_field_var_hists >= SYNTH_FIELDS_MAX)
++		return ERR_PTR(-EINVAL);
++
++	file = event_file(tr, subsys_name, event_name);
++
++	if (IS_ERR(file)) {
++		ret = PTR_ERR(file);
++		return ERR_PTR(ret);
++	}
++
++	/*
++	 * Look for a histogram compatible with target.  We'll use the
++	 * found histogram specification to create a new matching
++	 * histogram with our variable on it.  target_hist_data is not
++	 * yet a registered histogram so we can't use that.
++	 */
++	hist_data = find_compatible_hist(target_hist_data, file);
++	if (!hist_data)
++		return ERR_PTR(-EINVAL);
++
++	/* See if a synthetic field variable has already been created */
++	event_var = find_synthetic_field_var(target_hist_data, subsys_name,
++					     event_name, field_name);
++	if (!IS_ERR_OR_NULL(event_var))
++		return event_var;
++
++	var_hist = kzalloc(sizeof(*var_hist), GFP_KERNEL);
++	if (!var_hist)
++		return ERR_PTR(-ENOMEM);
++
++	cmd = kzalloc(MAX_FILTER_STR_VAL, GFP_KERNEL);
++	if (!cmd) {
++		kfree(var_hist);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* Use the same keys as the compatible histogram */
++	strcat(cmd, "keys=");
++
++	for_each_hist_key_field(i, hist_data) {
++		key_field = hist_data->fields[i];
++		if (!first)
++			strcat(cmd, ",");
++		strcat(cmd, key_field->field->name);
++		first = false;
++	}
++
++	/* Create the synthetic field variable specification */
++	strcat(cmd, ":synthetic_");
++	strcat(cmd, field_name);
++	strcat(cmd, "=");
++	strcat(cmd, field_name);
++
++	/* Use the same filter as the compatible histogram */
++	saved_filter = find_trigger_filter(hist_data, file);
++	if (saved_filter) {
++		strcat(cmd, " if ");
++		strcat(cmd, saved_filter);
++	}
++
++	var_hist->cmd = kstrdup(cmd, GFP_KERNEL);
++	if (!var_hist->cmd) {
++		kfree(cmd);
++		kfree(var_hist);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* Save the compatible histogram information */
++	var_hist->hist_data = hist_data;
++
++	/* Create the new histogram with our variable */
++	ret = event_hist_trigger_func(&trigger_hist_cmd, file,
++				      "", "hist", cmd);
++	if (ret) {
++		kfree(cmd);
++		kfree(var_hist->cmd);
++		kfree(var_hist);
++		return ERR_PTR(ret);
++	}
++
++	kfree(cmd);
++
++	/* If we can't find the variable, something went wrong */
++	event_var = find_synthetic_field_var(target_hist_data, subsys_name,
++					     event_name, field_name);
++	if (IS_ERR_OR_NULL(event_var)) {
++		kfree(var_hist->cmd);
++		kfree(var_hist);
++		return ERR_PTR(-EINVAL);
++	}
++
++	n = target_hist_data->n_field_var_hists;
++	target_hist_data->field_var_hists[n] = var_hist;
++	target_hist_data->n_field_var_hists++;
++
++	return event_var;
++}
++
++struct hist_field *
++find_target_event_var(struct hist_trigger_data *hist_data,
++		      char *subsys_name, char *event_name, char *var_name)
++{
++	struct trace_event_file *file = hist_data->event_file;
++	struct hist_field *hist_field = NULL;
++
++	if (subsys_name) {
++		struct trace_event_call *call;
++
++		if (!event_name)
++			return NULL;
++
++		call = file->event_call;
++
++		if (strcmp(subsys_name, call->class->system) != 0)
++			return NULL;
++
++		if (strcmp(event_name, trace_event_name(call)) != 0)
++			return NULL;
++	}
++
++	hist_field = find_var_field(hist_data, var_name);
++
++	return hist_field;
++}
++
++static inline void __update_field_vars(struct tracing_map_elt *elt,
++				       struct ring_buffer_event *rbe,
++				       void *rec,
++				       struct field_var **field_vars,
++				       unsigned int n_field_vars,
++				       unsigned int field_var_str_start)
++{
++	struct hist_elt_data *elt_data = elt->private_data;
++	unsigned int i, j, var_idx;
++	u64 var_val;
++
++	for (i = 0, j = field_var_str_start; i < n_field_vars; i++) {
++		struct field_var *field_var = field_vars[i];
++		struct hist_field *var = field_var->var;
++		struct hist_field *val = field_var->val;
++
++		var_val = val->fn(val, elt, rbe, rec);
++		var_idx = var->var.idx;
++
++		if (val->flags & HIST_FIELD_FL_STRING) {
++			char *str = elt_data->field_var_str[j++];
++			char *val_str = (char *)(uintptr_t)var_val;
++
++			strncpy(str, val_str, STR_VAR_LEN_MAX);
++			var_val = (u64)(uintptr_t)str;
++		}
++		tracing_map_set_var(elt, var_idx, var_val);
++	}
++}
++
++static void update_field_vars(struct hist_trigger_data *hist_data,
++			      struct tracing_map_elt *elt,
++			      struct ring_buffer_event *rbe,
++			      void *rec)
++{
++	__update_field_vars(elt, rbe, rec, hist_data->field_vars,
++			    hist_data->n_field_vars, 0);
++}
++
++static struct hist_field *create_var(struct hist_trigger_data *hist_data,
++				     struct trace_event_file *file,
++				     char *name, int size, const char *type)
++{
++	struct hist_field *var;
++	int idx;
++
++	if (find_var(hist_data, file, name) && !hist_data->remove) {
++		var = ERR_PTR(-EINVAL);
++		goto out;
++	}
++
++	var = kzalloc(sizeof(struct hist_field), GFP_KERNEL);
++	if (!var) {
++		var = ERR_PTR(-ENOMEM);
++		goto out;
++	}
++
++	idx = tracing_map_add_var(hist_data->map);
++	if (idx < 0) {
++		kfree(var);
++		var = ERR_PTR(-EINVAL);
++		goto out;
++	}
++
++	var->flags = HIST_FIELD_FL_VAR;
++	var->var.idx = idx;
++	var->var.hist_data = var->hist_data = hist_data;
++	var->size = size;
++	var->var.name = kstrdup(name, GFP_KERNEL);
++	var->type = kstrdup(type, GFP_KERNEL);
++	if (!var->var.name || !var->type) {
++		kfree(var->var.name);
++		kfree(var->type);
++		kfree(var);
++		var = ERR_PTR(-ENOMEM);
++	}
++ out:
++	return var;
++}
++
++static struct field_var *create_field_var(struct hist_trigger_data *hist_data,
++					  struct trace_event_file *file,
++					  char *field_name)
++{
++	struct hist_field *val = NULL, *var = NULL;
++	unsigned long flags = HIST_FIELD_FL_VAR;
++	struct field_var *field_var;
++	int ret = 0;
++
++	if (hist_data->n_field_vars >= SYNTH_FIELDS_MAX) {
++		ret = -EINVAL;
++		goto err;
++	}
++
++	val = parse_atom(hist_data, file, field_name, &flags, NULL);
++	if (IS_ERR(val)) {
++		ret = PTR_ERR(val);
++		goto err;
++	}
++
++	var = create_var(hist_data, file, field_name, val->size, val->type);
++	if (IS_ERR(var)) {
++		kfree(val);
++		ret = PTR_ERR(var);
++		goto err;
++	}
++
++	field_var = kzalloc(sizeof(struct field_var), GFP_KERNEL);
++	if (!field_var) {
++		kfree(val);
++		kfree(var);
++		ret =  -ENOMEM;
++		goto err;
++	}
++
++	field_var->var = var;
++	field_var->val = val;
++ out:
++	return field_var;
++ err:
++	field_var = ERR_PTR(ret);
++	goto out;
++}
++
++/**
++ * create_target_field_var - Automatically create a variable for a field
++ * @target_hist_data: The target hist trigger
++ * @subsys_name: Optional subsystem name
++ * @event_name: Optional event name
++ * @var_name: The name of the field (and the resulting variable)
++ *
++ * Hist trigger actions fetch data from variables, not directly from
++ * events.  However, for convenience, users are allowed to directly
++ * specify an event field in an action, which will be automatically
++ * converted into a variable on their behalf.
++
++ * This function creates a field variable with the name var_name on
++ * the hist trigger currently being defined on the target event.  If
++ * subsys_name and event_name are specified, this function simply
++ * verifies that they do in fact match the target event subsystem and
++ * event name.
++ *
++ * Return: The variable created for the field.
++ */
++struct field_var *
++create_target_field_var(struct hist_trigger_data *target_hist_data,
++			char *subsys_name, char *event_name, char *var_name)
++{
++	struct trace_event_file *file = target_hist_data->event_file;
++
++	if (subsys_name) {
++		struct trace_event_call *call;
++
++		if (!event_name)
++			return NULL;
++
++		call = file->event_call;
++
++		if (strcmp(subsys_name, call->class->system) != 0)
++			return NULL;
++
++		if (strcmp(event_name, trace_event_name(call)) != 0)
++			return NULL;
++	}
++
++	return create_field_var(target_hist_data, file, var_name);
++}
++
++static void destroy_field_var(struct field_var *field_var)
++{
++	if (!field_var)
++		return;
++
++	destroy_hist_field(field_var->var, 0);
++	destroy_hist_field(field_var->val, 0);
++
++	kfree(field_var);
++}
++
++static void destroy_field_vars(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_field_vars; i++)
++		destroy_field_var(hist_data->field_vars[i]);
++}
++
++void save_field_var(struct hist_trigger_data *hist_data,
++		    struct field_var *field_var)
++{
++	hist_data->field_vars[hist_data->n_field_vars++] = field_var;
++
++	if (field_var->val->flags & HIST_FIELD_FL_STRING)
++		hist_data->n_field_var_str++;
++}
++
+ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ {
+ 	hist_data->fields[HITCOUNT_IDX] =
+@@ -2928,6 +3426,16 @@ static int create_actions(struct hist_trigger_data *hist_data,
+ 	return ret;
+ }
+ 
++static void destroy_field_var_hists(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_field_var_hists; i++) {
++		kfree(hist_data->field_var_hists[i]->cmd);
++		kfree(hist_data->field_var_hists[i]);
++	}
++}
++
+ static void destroy_hist_data(struct hist_trigger_data *hist_data)
+ {
+ 	if (!hist_data)
+@@ -2938,6 +3446,8 @@ static void destroy_hist_data(struct hist_trigger_data *hist_data)
+ 	tracing_map_destroy(hist_data->map);
+ 
+ 	destroy_actions(hist_data);
++	destroy_field_vars(hist_data);
++	destroy_field_var_hists(hist_data);
+ 
+ 	kfree(hist_data);
+ }
+@@ -3074,6 +3584,8 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data,
+ 			tracing_map_set_var(elt, var_idx, hist_val);
+ 		}
+ 	}
++
++	update_field_vars(hist_data, elt, rbe, rec);
+ }
+ 
+ static inline void add_to_key(char *compound_key, void *key,
+@@ -3518,6 +4030,21 @@ static int event_hist_trigger_init(struct event_trigger_ops *ops,
+ 	return 0;
+ }
+ 
++static void unregister_field_var_hists(struct hist_trigger_data *hist_data)
++{
++	struct trace_event_file *file;
++	unsigned int i;
++	char *cmd;
++	int ret;
++
++	for (i = 0; i < hist_data->n_field_var_hists; i++) {
++		file = hist_data->field_var_hists[i]->hist_data->event_file;
++		cmd = hist_data->field_var_hists[i]->cmd;
++		ret = event_hist_trigger_func(&trigger_hist_cmd, file,
++					      "!hist", "hist", cmd);
++	}
++}
++
+ static void event_hist_trigger_free(struct event_trigger_ops *ops,
+ 				    struct event_trigger_data *data)
+ {
+@@ -3535,6 +4062,8 @@ static void event_hist_trigger_free(struct event_trigger_ops *ops,
+ 
+ 		remove_hist_vars(hist_data);
+ 
++		unregister_field_var_hists(hist_data);
++
+ 		destroy_hist_data(hist_data);
+ 	}
+ }
+-- 
+2.19.0
+
diff --git a/patches/1773-tracing-Add-onmatch-hist-trigger-action-support.patch b/patches/1773-tracing-Add-onmatch-hist-trigger-action-support.patch
new file mode 100644
index 00000000000000..9e9af8a54b0bd0
--- /dev/null
+++ b/patches/1773-tracing-Add-onmatch-hist-trigger-action-support.patch
@@ -0,0 +1,694 @@
+From 3a7e6b8cbda85b5dce88051f41737f5e76861079 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:00 -0600
+Subject: [PATCH 1773/1795] tracing: Add 'onmatch' hist trigger action support
+
+Add an 'onmatch(matching.event).<synthetic_event_name>(param list)'
+hist trigger action which is invoked with the set of variables or
+event fields named in the 'param list'.  The result is the generation
+of a synthetic event that consists of the values contained in those
+variables and/or fields at the time the invoking event was hit.
+
+As an example the below defines a simple synthetic event using a
+variable defined on the sched_wakeup_new event, and shows the event
+definition with unresolved fields, since the sched_wakeup_new event
+with the testpid variable hasn't been defined yet:
+
+    # echo 'wakeup_new_test pid_t pid; int prio' >> \
+      /sys/kernel/debug/tracing/synthetic_events
+
+    # cat /sys/kernel/debug/tracing/synthetic_events
+      wakeup_new_test pid_t pid; int prio
+
+The following hist trigger both defines a testpid variable and
+specifies an onmatch() trace action that uses that variable along with
+a non-variable field to generate a wakeup_new_test synthetic event
+whenever a sched_wakeup_new event occurs, which because of the 'if
+comm == "cyclictest"' filter only happens when the executable is
+cyclictest:
+
+    # echo 'hist:testpid=pid:keys=$testpid:\
+      onmatch(sched.sched_wakeup_new).wakeup_new_test($testpid, prio) \
+        if comm=="cyclictest"' >> \
+      /sys/kernel/debug/tracing/events/sched/sched_wakeup_new/trigger
+
+Creating and displaying a histogram based on those events is now just
+a matter of using the fields and new synthetic event in the
+tracing/events/synthetic directory, as usual:
+
+    # echo 'hist:keys=pid,prio:sort=pid,prio' >> \
+      /sys/kernel/debug/tracing/events/synthetic/wakeup_new_test/trigger
+
+Link: http://lkml.kernel.org/r/8c2a574bcb7530c876629c901ecd23911b14afe8.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Rajvi Jingar <rajvi.jingar@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit c282a386a39771588fe4cfdc01bbb8a255092e38)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 488 ++++++++++++++++++++++++++++++-
+ 1 file changed, 475 insertions(+), 13 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index ad96fd110707..9ac6089b7513 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -285,6 +285,8 @@ struct hist_trigger_data {
+ 	struct action_data		*actions[HIST_ACTIONS_MAX];
+ 	unsigned int			n_actions;
+ 
++	struct hist_field               *synth_var_refs[SYNTH_FIELDS_MAX];
++	unsigned int                    n_synth_var_refs;
+ 	struct field_var		*field_vars[SYNTH_FIELDS_MAX];
+ 	unsigned int			n_field_vars;
+ 	unsigned int			n_field_var_str;
+@@ -321,7 +323,18 @@ typedef void (*action_fn_t) (struct hist_trigger_data *hist_data,
+ 
+ struct action_data {
+ 	action_fn_t		fn;
+-	unsigned int		var_ref_idx;
++	unsigned int		n_params;
++	char			*params[SYNTH_FIELDS_MAX];
++
++	union {
++		struct {
++			unsigned int		var_ref_idx;
++			char			*match_event;
++			char			*match_event_system;
++			char			*synth_event_name;
++			struct synth_event	*synth_event;
++		} onmatch;
++	};
+ };
+ 
+ static LIST_HEAD(synth_event_list);
+@@ -887,6 +900,21 @@ static struct synth_event *alloc_synth_event(char *event_name, int n_fields,
+ 	return event;
+ }
+ 
++static void action_trace(struct hist_trigger_data *hist_data,
++			 struct tracing_map_elt *elt, void *rec,
++			 struct ring_buffer_event *rbe,
++			 struct action_data *data, u64 *var_ref_vals)
++{
++	struct synth_event *event = data->onmatch.synth_event;
++
++	trace_synth(event, var_ref_vals, data->onmatch.var_ref_idx);
++}
++
++struct hist_var_data {
++	struct list_head list;
++	struct hist_trigger_data *hist_data;
++};
++
+ static void add_or_delete_synth_event(struct synth_event *event, int delete)
+ {
+ 	if (delete)
+@@ -1124,11 +1152,6 @@ static u64 hist_field_timestamp(struct hist_field *hist_field,
+ 	return ts;
+ }
+ 
+-struct hist_var_data {
+-	struct list_head list;
+-	struct hist_trigger_data *hist_data;
+-};
+-
+ static struct hist_field *
+ check_field_for_var_ref(struct hist_field *hist_field,
+ 			struct hist_trigger_data *var_data,
+@@ -1194,6 +1217,14 @@ static struct hist_field *find_var_ref(struct hist_trigger_data *hist_data,
+ 			return found;
+ 	}
+ 
++	for (i = 0; i < hist_data->n_synth_var_refs; i++) {
++		hist_field = hist_data->synth_var_refs[i];
++		found = check_field_for_var_refs(hist_data, hist_field,
++						 var_data, var_idx, 0);
++		if (found)
++			return found;
++	}
++
+ 	return found;
+ }
+ 
+@@ -1422,6 +1453,37 @@ static struct hist_field *find_file_var(struct trace_event_file *file,
+ 	return NULL;
+ }
+ 
++static struct hist_field *
++find_match_var(struct hist_trigger_data *hist_data, char *var_name)
++{
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct hist_field *hist_field, *found = NULL;
++	struct trace_event_file *file;
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		struct action_data *data = hist_data->actions[i];
++
++		if (data->fn == action_trace) {
++			char *system = data->onmatch.match_event_system;
++			char *event_name = data->onmatch.match_event;
++
++			file = find_var_file(tr, system, event_name, var_name);
++			if (!file)
++				continue;
++			hist_field = find_file_var(file, var_name);
++			if (hist_field) {
++				if (found) {
++					return ERR_PTR(-EINVAL);
++				}
++
++				found = hist_field;
++			}
++		}
++	}
++	return found;
++}
++
+ static struct hist_field *find_event_var(struct hist_trigger_data *hist_data,
+ 					 char *system,
+ 					 char *event_name,
+@@ -1431,6 +1493,14 @@ static struct hist_field *find_event_var(struct hist_trigger_data *hist_data,
+ 	struct hist_field *hist_field = NULL;
+ 	struct trace_event_file *file;
+ 
++	if (!system || !event_name) {
++		hist_field = find_match_var(hist_data, var_name);
++		if (IS_ERR(hist_field))
++			return NULL;
++		if (hist_field)
++			return hist_field;
++	}
++
+ 	file = find_var_file(tr, system, event_name, var_name);
+ 	if (!file)
+ 		return NULL;
+@@ -1622,11 +1692,21 @@ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ 
+ static int parse_action(char *str, struct hist_trigger_attrs *attrs)
+ {
+-	int ret = 0;
++	int ret = -EINVAL;
+ 
+ 	if (attrs->n_actions >= HIST_ACTIONS_MAX)
+ 		return ret;
+ 
++	if ((strncmp(str, "onmatch(", strlen("onmatch(")) == 0)) {
++		attrs->action_str[attrs->n_actions] = kstrdup(str, GFP_KERNEL);
++		if (!attrs->action_str[attrs->n_actions]) {
++			ret = -ENOMEM;
++			return ret;
++		}
++		attrs->n_actions++;
++		ret = 0;
++	}
++
+ 	return ret;
+ }
+ 
+@@ -2635,7 +2715,7 @@ find_synthetic_field_var(struct hist_trigger_data *target_hist_data,
+  *
+  * Return: The variable created for the field.
+  */
+-struct hist_field *
++static struct hist_field *
+ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 		      char *subsys_name, char *event_name, char *field_name)
+ {
+@@ -2748,7 +2828,7 @@ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 	return event_var;
+ }
+ 
+-struct hist_field *
++static struct hist_field *
+ find_target_event_var(struct hist_trigger_data *hist_data,
+ 		      char *subsys_name, char *event_name, char *var_name)
+ {
+@@ -2919,7 +2999,7 @@ static struct field_var *create_field_var(struct hist_trigger_data *hist_data,
+  *
+  * Return: The variable created for the field.
+  */
+-struct field_var *
++static struct field_var *
+ create_target_field_var(struct hist_trigger_data *target_hist_data,
+ 			char *subsys_name, char *event_name, char *var_name)
+ {
+@@ -2943,6 +3023,27 @@ create_target_field_var(struct hist_trigger_data *target_hist_data,
+ 	return create_field_var(target_hist_data, file, var_name);
+ }
+ 
++static void onmatch_destroy(struct action_data *data)
++{
++	unsigned int i;
++
++	mutex_lock(&synth_event_mutex);
++
++	kfree(data->onmatch.match_event);
++	kfree(data->onmatch.match_event_system);
++	kfree(data->onmatch.synth_event_name);
++
++	for (i = 0; i < data->n_params; i++)
++		kfree(data->params[i]);
++
++	if (data->onmatch.synth_event)
++		data->onmatch.synth_event->ref--;
++
++	kfree(data);
++
++	mutex_unlock(&synth_event_mutex);
++}
++
+ static void destroy_field_var(struct field_var *field_var)
+ {
+ 	if (!field_var)
+@@ -2962,8 +3063,8 @@ static void destroy_field_vars(struct hist_trigger_data *hist_data)
+ 		destroy_field_var(hist_data->field_vars[i]);
+ }
+ 
+-void save_field_var(struct hist_trigger_data *hist_data,
+-		    struct field_var *field_var)
++static void save_field_var(struct hist_trigger_data *hist_data,
++			   struct field_var *field_var)
+ {
+ 	hist_data->field_vars[hist_data->n_field_vars++] = field_var;
+ 
+@@ -2971,6 +3072,304 @@ void save_field_var(struct hist_trigger_data *hist_data,
+ 		hist_data->n_field_var_str++;
+ }
+ 
++
++static void destroy_synth_var_refs(struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_synth_var_refs; i++)
++		destroy_hist_field(hist_data->synth_var_refs[i], 0);
++}
++
++static void save_synth_var_ref(struct hist_trigger_data *hist_data,
++			 struct hist_field *var_ref)
++{
++	hist_data->synth_var_refs[hist_data->n_synth_var_refs++] = var_ref;
++
++	hist_data->var_refs[hist_data->n_var_refs] = var_ref;
++	var_ref->var_ref_idx = hist_data->n_var_refs++;
++}
++
++static int check_synth_field(struct synth_event *event,
++			     struct hist_field *hist_field,
++			     unsigned int field_pos)
++{
++	struct synth_field *field;
++
++	if (field_pos >= event->n_fields)
++		return -EINVAL;
++
++	field = event->fields[field_pos];
++
++	if (strcmp(field->type, hist_field->type) != 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int parse_action_params(char *params, struct action_data *data)
++{
++	char *param, *saved_param;
++	int ret = 0;
++
++	while (params) {
++		if (data->n_params >= SYNTH_FIELDS_MAX)
++			goto out;
++
++		param = strsep(&params, ",");
++		if (!param) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		param = strstrip(param);
++		if (strlen(param) < 2) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		saved_param = kstrdup(param, GFP_KERNEL);
++		if (!saved_param) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		data->params[data->n_params++] = saved_param;
++	}
++ out:
++	return ret;
++}
++
++static struct hist_field *
++onmatch_find_var(struct hist_trigger_data *hist_data, struct action_data *data,
++		 char *system, char *event, char *var)
++{
++	struct hist_field *hist_field;
++
++	var++; /* skip '$' */
++
++	hist_field = find_target_event_var(hist_data, system, event, var);
++	if (!hist_field) {
++		if (!system) {
++			system = data->onmatch.match_event_system;
++			event = data->onmatch.match_event;
++		}
++
++		hist_field = find_event_var(hist_data, system, event, var);
++	}
++
++	return hist_field;
++}
++
++static struct hist_field *
++onmatch_create_field_var(struct hist_trigger_data *hist_data,
++			 struct action_data *data, char *system,
++			 char *event, char *var)
++{
++	struct hist_field *hist_field = NULL;
++	struct field_var *field_var;
++
++	/*
++	 * First try to create a field var on the target event (the
++	 * currently being defined).  This will create a variable for
++	 * unqualified fields on the target event, or if qualified,
++	 * target fields that have qualified names matching the target.
++	 */
++	field_var = create_target_field_var(hist_data, system, event, var);
++
++	if (field_var && !IS_ERR(field_var)) {
++		save_field_var(hist_data, field_var);
++		hist_field = field_var->var;
++	} else {
++		field_var = NULL;
++		/*
++		 * If no explicit system.event is specfied, default to
++		 * looking for fields on the onmatch(system.event.xxx)
++		 * event.
++		 */
++		if (!system) {
++			system = data->onmatch.match_event_system;
++			event = data->onmatch.match_event;
++		}
++
++		/*
++		 * At this point, we're looking at a field on another
++		 * event.  Because we can't modify a hist trigger on
++		 * another event to add a variable for a field, we need
++		 * to create a new trigger on that event and create the
++		 * variable at the same time.
++		 */
++		hist_field = create_field_var_hist(hist_data, system, event, var);
++		if (IS_ERR(hist_field))
++			goto free;
++	}
++ out:
++	return hist_field;
++ free:
++	destroy_field_var(field_var);
++	hist_field = NULL;
++	goto out;
++}
++
++static int onmatch_create(struct hist_trigger_data *hist_data,
++			  struct trace_event_file *file,
++			  struct action_data *data)
++{
++	char *event_name, *param, *system = NULL;
++	struct hist_field *hist_field, *var_ref;
++	unsigned int i, var_ref_idx;
++	unsigned int field_pos = 0;
++	struct synth_event *event;
++	int ret = 0;
++
++	mutex_lock(&synth_event_mutex);
++	event = find_synth_event(data->onmatch.synth_event_name);
++	if (!event) {
++		mutex_unlock(&synth_event_mutex);
++		return -EINVAL;
++	}
++	event->ref++;
++	mutex_unlock(&synth_event_mutex);
++
++	var_ref_idx = hist_data->n_var_refs;
++
++	for (i = 0; i < data->n_params; i++) {
++		char *p;
++
++		p = param = kstrdup(data->params[i], GFP_KERNEL);
++		if (!param) {
++			ret = -ENOMEM;
++			goto err;
++		}
++
++		system = strsep(&param, ".");
++		if (!param) {
++			param = (char *)system;
++			system = event_name = NULL;
++		} else {
++			event_name = strsep(&param, ".");
++			if (!param) {
++				kfree(p);
++				ret = -EINVAL;
++				goto err;
++			}
++		}
++
++		if (param[0] == '$')
++			hist_field = onmatch_find_var(hist_data, data, system,
++						      event_name, param);
++		else
++			hist_field = onmatch_create_field_var(hist_data, data,
++							      system,
++							      event_name,
++							      param);
++
++		if (!hist_field) {
++			kfree(p);
++			ret = -EINVAL;
++			goto err;
++		}
++
++		if (check_synth_field(event, hist_field, field_pos) == 0) {
++			var_ref = create_var_ref(hist_field, system, event_name);
++			if (!var_ref) {
++				kfree(p);
++				ret = -ENOMEM;
++				goto err;
++			}
++
++			save_synth_var_ref(hist_data, var_ref);
++			field_pos++;
++			kfree(p);
++			continue;
++		}
++
++		kfree(p);
++		ret = -EINVAL;
++		goto err;
++	}
++
++	if (field_pos != event->n_fields) {
++		ret = -EINVAL;
++		goto err;
++	}
++
++	data->fn = action_trace;
++	data->onmatch.synth_event = event;
++	data->onmatch.var_ref_idx = var_ref_idx;
++ out:
++	return ret;
++ err:
++	mutex_lock(&synth_event_mutex);
++	event->ref--;
++	mutex_unlock(&synth_event_mutex);
++
++	goto out;
++}
++
++static struct action_data *onmatch_parse(struct trace_array *tr, char *str)
++{
++	char *match_event, *match_event_system;
++	char *synth_event_name, *params;
++	struct action_data *data;
++	int ret = -EINVAL;
++
++	data = kzalloc(sizeof(*data), GFP_KERNEL);
++	if (!data)
++		return ERR_PTR(-ENOMEM);
++
++	match_event = strsep(&str, ")");
++	if (!match_event || !str)
++		goto free;
++
++	match_event_system = strsep(&match_event, ".");
++	if (!match_event)
++		goto free;
++
++	if (IS_ERR(event_file(tr, match_event_system, match_event)))
++		goto free;
++
++	data->onmatch.match_event = kstrdup(match_event, GFP_KERNEL);
++	if (!data->onmatch.match_event) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	data->onmatch.match_event_system = kstrdup(match_event_system, GFP_KERNEL);
++	if (!data->onmatch.match_event_system) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	strsep(&str, ".");
++	if (!str)
++		goto free;
++
++	synth_event_name = strsep(&str, "(");
++	if (!synth_event_name || !str)
++		goto free;
++
++	data->onmatch.synth_event_name = kstrdup(synth_event_name, GFP_KERNEL);
++	if (!data->onmatch.synth_event_name) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	params = strsep(&str, ")");
++	if (!params || !str || (str && strlen(str)))
++		goto free;
++
++	ret = parse_action_params(params, data);
++	if (ret)
++		goto free;
++ out:
++	return data;
++ free:
++	onmatch_destroy(data);
++	data = ERR_PTR(ret);
++	goto out;
++}
++
+ static int create_hitcount_val(struct hist_trigger_data *hist_data)
+ {
+ 	hist_data->fields[HITCOUNT_IDX] =
+@@ -3395,18 +3794,39 @@ static void destroy_actions(struct hist_trigger_data *hist_data)
+ 	for (i = 0; i < hist_data->n_actions; i++) {
+ 		struct action_data *data = hist_data->actions[i];
+ 
+-		kfree(data);
++		if (data->fn == action_trace)
++			onmatch_destroy(data);
++		else
++			kfree(data);
+ 	}
+ }
+ 
+ static int parse_actions(struct hist_trigger_data *hist_data)
+ {
++	struct trace_array *tr = hist_data->event_file->tr;
++	struct action_data *data;
+ 	unsigned int i;
+ 	int ret = 0;
+ 	char *str;
+ 
+ 	for (i = 0; i < hist_data->attrs->n_actions; i++) {
+ 		str = hist_data->attrs->action_str[i];
++
++		if (strncmp(str, "onmatch(", strlen("onmatch(")) == 0) {
++			char *action_str = str + strlen("onmatch(");
++
++			data = onmatch_parse(tr, action_str);
++			if (IS_ERR(data)) {
++				ret = PTR_ERR(data);
++				break;
++			}
++			data->fn = action_trace;
++		} else {
++			ret = -EINVAL;
++			break;
++		}
++
++		hist_data->actions[hist_data->n_actions++] = data;
+ 	}
+ 
+ 	return ret;
+@@ -3421,11 +3841,50 @@ static int create_actions(struct hist_trigger_data *hist_data,
+ 
+ 	for (i = 0; i < hist_data->attrs->n_actions; i++) {
+ 		data = hist_data->actions[i];
++
++		if (data->fn == action_trace) {
++			ret = onmatch_create(hist_data, file, data);
++			if (ret)
++				return ret;
++		}
+ 	}
+ 
+ 	return ret;
+ }
+ 
++static void print_onmatch_spec(struct seq_file *m,
++			       struct hist_trigger_data *hist_data,
++			       struct action_data *data)
++{
++	unsigned int i;
++
++	seq_printf(m, ":onmatch(%s.%s).", data->onmatch.match_event_system,
++		   data->onmatch.match_event);
++
++	seq_printf(m, "%s(", data->onmatch.synth_event->name);
++
++	for (i = 0; i < data->n_params; i++) {
++		if (i)
++			seq_puts(m, ",");
++		seq_printf(m, "%s", data->params[i]);
++	}
++
++	seq_puts(m, ")");
++}
++
++static void print_actions_spec(struct seq_file *m,
++			       struct hist_trigger_data *hist_data)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		struct action_data *data = hist_data->actions[i];
++
++		if (data->fn == action_trace)
++			print_onmatch_spec(m, hist_data, data);
++	}
++}
++
+ static void destroy_field_var_hists(struct hist_trigger_data *hist_data)
+ {
+ 	unsigned int i;
+@@ -3448,6 +3907,7 @@ static void destroy_hist_data(struct hist_trigger_data *hist_data)
+ 	destroy_actions(hist_data);
+ 	destroy_field_vars(hist_data);
+ 	destroy_field_var_hists(hist_data);
++	destroy_synth_var_refs(hist_data);
+ 
+ 	kfree(hist_data);
+ }
+@@ -4004,6 +4464,8 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 	}
+ 	seq_printf(m, ":size=%u", (1 << hist_data->map->map_bits));
+ 
++	print_actions_spec(m, hist_data);
++
+ 	if (data->filter_str)
+ 		seq_printf(m, " if %s", data->filter_str);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1774-tracing-Add-onmax-hist-trigger-action-support.patch b/patches/1774-tracing-Add-onmax-hist-trigger-action-support.patch
new file mode 100644
index 00000000000000..eb5a0db993dd86
--- /dev/null
+++ b/patches/1774-tracing-Add-onmax-hist-trigger-action-support.patch
@@ -0,0 +1,493 @@
+From 5c63bde74b269a12037b619b4731bfa1eb9d7488 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:01 -0600
+Subject: [PATCH 1774/1795] tracing: Add 'onmax' hist trigger action support
+
+Add an 'onmax(var).save(field,...)' hist trigger action which is
+invoked whenever an event exceeds the current maximum.
+
+The end result is that the trace event fields or variables specified
+as the onmax.save() params will be saved if 'var' exceeds the current
+maximum for that hist trigger entry.  This allows context from the
+event that exhibited the new maximum to be saved for later reference.
+When the histogram is displayed, additional fields displaying the
+saved values will be printed.
+
+As an example the below defines a couple of hist triggers, one for
+sched_wakeup and another for sched_switch, keyed on pid.  Whenever a
+sched_wakeup occurs, the timestamp is saved in the entry corresponding
+to the current pid, and when the scheduler switches back to that pid,
+the timestamp difference is calculated.  If the resulting latency
+exceeds the current maximum latency, the specified save() values are
+saved:
+
+    # echo 'hist:keys=pid:ts0=common_timestamp.usecs \
+        if comm=="cyclictest"' >> \
+      /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+
+    # echo 'hist:keys=next_pid:\
+      wakeup_lat=common_timestamp.usecs-$ts0:\
+      onmax($wakeup_lat).save(next_comm,prev_pid,prev_prio,prev_comm) \
+        if next_comm=="cyclictest"' >> \
+      /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+When the histogram is displayed, the max value and the saved values
+corresponding to the max are displayed following the rest of the
+fields:
+
+    # cat /sys/kernel/debug/tracing/events/sched/sched_switch/hist
+
+      { next_pid:       3728 } hitcount:        199 \
+        max:        123  next_comm: cyclictest  prev_pid:          0 \
+	prev_prio:        120  prev_comm: swapper/3
+      { next_pid:       3730 } hitcount:       1321 \
+        max:         15  next_comm: cyclictest  prev_pid:          0 \
+	prev_prio:        120  prev_comm: swapper/1
+      { next_pid:       3729 } hitcount:       1973\
+        max:         25  next_comm: cyclictest  prev_pid:          0  \
+	prev_prio:        120  prev_comm: swapper/0
+
+    Totals:
+        Hits: 3493
+        Entries: 3
+	Dropped: 0
+
+Link: http://lkml.kernel.org/r/006907f71b1e839bb059337ec3c496f84fcb71de.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 50450603ec9cb808d39b1461fe67a81d82b37129)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 331 +++++++++++++++++++++++++++----
+ 1 file changed, 296 insertions(+), 35 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 9ac6089b7513..7bcc32a7e266 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -292,6 +292,10 @@ struct hist_trigger_data {
+ 	unsigned int			n_field_var_str;
+ 	struct field_var_hist		*field_var_hists[SYNTH_FIELDS_MAX];
+ 	unsigned int			n_field_var_hists;
++
++	struct field_var		*max_vars[SYNTH_FIELDS_MAX];
++	unsigned int			n_max_vars;
++	unsigned int			n_max_var_str;
+ };
+ 
+ struct synth_field {
+@@ -334,6 +338,14 @@ struct action_data {
+ 			char			*synth_event_name;
+ 			struct synth_event	*synth_event;
+ 		} onmatch;
++
++		struct {
++			char			*var_str;
++			char			*fn_name;
++			unsigned int		max_var_ref_idx;
++			struct hist_field	*max_var;
++			struct hist_field	*var;
++		} onmax;
+ 	};
+ };
+ 
+@@ -1697,7 +1709,8 @@ static int parse_action(char *str, struct hist_trigger_attrs *attrs)
+ 	if (attrs->n_actions >= HIST_ACTIONS_MAX)
+ 		return ret;
+ 
+-	if ((strncmp(str, "onmatch(", strlen("onmatch(")) == 0)) {
++	if ((strncmp(str, "onmatch(", strlen("onmatch(")) == 0) ||
++	    (strncmp(str, "onmax(", strlen("onmax(")) == 0)) {
+ 		attrs->action_str[attrs->n_actions] = kstrdup(str, GFP_KERNEL);
+ 		if (!attrs->action_str[attrs->n_actions]) {
+ 			ret = -ENOMEM;
+@@ -1869,7 +1882,7 @@ static int hist_trigger_elt_data_alloc(struct tracing_map_elt *elt)
+ 		}
+ 	}
+ 
+-	n_str = hist_data->n_field_var_str;
++	n_str = hist_data->n_field_var_str + hist_data->n_max_var_str;
+ 
+ 	size = STR_VAR_LEN_MAX;
+ 
+@@ -2894,6 +2907,15 @@ static void update_field_vars(struct hist_trigger_data *hist_data,
+ 			    hist_data->n_field_vars, 0);
+ }
+ 
++static void update_max_vars(struct hist_trigger_data *hist_data,
++			    struct tracing_map_elt *elt,
++			    struct ring_buffer_event *rbe,
++			    void *rec)
++{
++	__update_field_vars(elt, rbe, rec, hist_data->max_vars,
++			    hist_data->n_max_vars, hist_data->n_field_var_str);
++}
++
+ static struct hist_field *create_var(struct hist_trigger_data *hist_data,
+ 				     struct trace_event_file *file,
+ 				     char *name, int size, const char *type)
+@@ -3023,6 +3045,227 @@ create_target_field_var(struct hist_trigger_data *target_hist_data,
+ 	return create_field_var(target_hist_data, file, var_name);
+ }
+ 
++static void onmax_print(struct seq_file *m,
++			struct hist_trigger_data *hist_data,
++			struct tracing_map_elt *elt,
++			struct action_data *data)
++{
++	unsigned int i, save_var_idx, max_idx = data->onmax.max_var->var.idx;
++
++	seq_printf(m, "\n\tmax: %10llu", tracing_map_read_var(elt, max_idx));
++
++	for (i = 0; i < hist_data->n_max_vars; i++) {
++		struct hist_field *save_val = hist_data->max_vars[i]->val;
++		struct hist_field *save_var = hist_data->max_vars[i]->var;
++		u64 val;
++
++		save_var_idx = save_var->var.idx;
++
++		val = tracing_map_read_var(elt, save_var_idx);
++
++		if (save_val->flags & HIST_FIELD_FL_STRING) {
++			seq_printf(m, "  %s: %-32s", save_var->var.name,
++				   (char *)(uintptr_t)(val));
++		} else
++			seq_printf(m, "  %s: %10llu", save_var->var.name, val);
++	}
++}
++
++static void onmax_save(struct hist_trigger_data *hist_data,
++		       struct tracing_map_elt *elt, void *rec,
++		       struct ring_buffer_event *rbe,
++		       struct action_data *data, u64 *var_ref_vals)
++{
++	unsigned int max_idx = data->onmax.max_var->var.idx;
++	unsigned int max_var_ref_idx = data->onmax.max_var_ref_idx;
++
++	u64 var_val, max_val;
++
++	var_val = var_ref_vals[max_var_ref_idx];
++	max_val = tracing_map_read_var(elt, max_idx);
++
++	if (var_val <= max_val)
++		return;
++
++	tracing_map_set_var(elt, max_idx, var_val);
++
++	update_max_vars(hist_data, elt, rbe, rec);
++}
++
++static void onmax_destroy(struct action_data *data)
++{
++	unsigned int i;
++
++	destroy_hist_field(data->onmax.max_var, 0);
++	destroy_hist_field(data->onmax.var, 0);
++
++	kfree(data->onmax.var_str);
++	kfree(data->onmax.fn_name);
++
++	for (i = 0; i < data->n_params; i++)
++		kfree(data->params[i]);
++
++	kfree(data);
++}
++
++static int onmax_create(struct hist_trigger_data *hist_data,
++			struct action_data *data)
++{
++	struct trace_event_file *file = hist_data->event_file;
++	struct hist_field *var_field, *ref_field, *max_var;
++	unsigned int var_ref_idx = hist_data->n_var_refs;
++	struct field_var *field_var;
++	char *onmax_var_str, *param;
++	unsigned long flags;
++	unsigned int i;
++	int ret = 0;
++
++	onmax_var_str = data->onmax.var_str;
++	if (onmax_var_str[0] != '$')
++		return -EINVAL;
++	onmax_var_str++;
++
++	var_field = find_target_event_var(hist_data, NULL, NULL, onmax_var_str);
++	if (!var_field)
++		return -EINVAL;
++
++	flags = HIST_FIELD_FL_VAR_REF;
++	ref_field = create_hist_field(hist_data, NULL, flags, NULL);
++	if (!ref_field)
++		return -ENOMEM;
++
++	if (init_var_ref(ref_field, var_field, NULL, NULL)) {
++		destroy_hist_field(ref_field, 0);
++		ret = -ENOMEM;
++		goto out;
++	}
++	hist_data->var_refs[hist_data->n_var_refs] = ref_field;
++	ref_field->var_ref_idx = hist_data->n_var_refs++;
++	data->onmax.var = ref_field;
++
++	data->fn = onmax_save;
++	data->onmax.max_var_ref_idx = var_ref_idx;
++	max_var = create_var(hist_data, file, "max", sizeof(u64), "u64");
++	if (IS_ERR(max_var)) {
++		ret = PTR_ERR(max_var);
++		goto out;
++	}
++	data->onmax.max_var = max_var;
++
++	for (i = 0; i < data->n_params; i++) {
++		param = kstrdup(data->params[i], GFP_KERNEL);
++		if (!param) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		field_var = create_target_field_var(hist_data, NULL, NULL, param);
++		if (IS_ERR(field_var)) {
++			ret = PTR_ERR(field_var);
++			kfree(param);
++			goto out;
++		}
++
++		hist_data->max_vars[hist_data->n_max_vars++] = field_var;
++		if (field_var->val->flags & HIST_FIELD_FL_STRING)
++			hist_data->n_max_var_str++;
++
++		kfree(param);
++	}
++ out:
++	return ret;
++}
++
++static int parse_action_params(char *params, struct action_data *data)
++{
++	char *param, *saved_param;
++	int ret = 0;
++
++	while (params) {
++		if (data->n_params >= SYNTH_FIELDS_MAX)
++			goto out;
++
++		param = strsep(&params, ",");
++		if (!param) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		param = strstrip(param);
++		if (strlen(param) < 2) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		saved_param = kstrdup(param, GFP_KERNEL);
++		if (!saved_param) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		data->params[data->n_params++] = saved_param;
++	}
++ out:
++	return ret;
++}
++
++static struct action_data *onmax_parse(char *str)
++{
++	char *onmax_fn_name, *onmax_var_str;
++	struct action_data *data;
++	int ret = -EINVAL;
++
++	data = kzalloc(sizeof(*data), GFP_KERNEL);
++	if (!data)
++		return ERR_PTR(-ENOMEM);
++
++	onmax_var_str = strsep(&str, ")");
++	if (!onmax_var_str || !str) {
++		ret = -EINVAL;
++		goto free;
++	}
++
++	data->onmax.var_str = kstrdup(onmax_var_str, GFP_KERNEL);
++	if (!data->onmax.var_str) {
++		ret = -ENOMEM;
++		goto free;
++	}
++
++	strsep(&str, ".");
++	if (!str)
++		goto free;
++
++	onmax_fn_name = strsep(&str, "(");
++	if (!onmax_fn_name || !str)
++		goto free;
++
++	if (strncmp(onmax_fn_name, "save", strlen("save")) == 0) {
++		char *params = strsep(&str, ")");
++
++		if (!params) {
++			ret = -EINVAL;
++			goto free;
++		}
++
++		ret = parse_action_params(params, data);
++		if (ret)
++			goto free;
++	} else
++		goto free;
++
++	data->onmax.fn_name = kstrdup(onmax_fn_name, GFP_KERNEL);
++	if (!data->onmax.fn_name) {
++		ret = -ENOMEM;
++		goto free;
++	}
++ out:
++	return data;
++ free:
++	onmax_destroy(data);
++	data = ERR_PTR(ret);
++	goto out;
++}
++
+ static void onmatch_destroy(struct action_data *data)
+ {
+ 	unsigned int i;
+@@ -3107,39 +3350,6 @@ static int check_synth_field(struct synth_event *event,
+ 	return 0;
+ }
+ 
+-static int parse_action_params(char *params, struct action_data *data)
+-{
+-	char *param, *saved_param;
+-	int ret = 0;
+-
+-	while (params) {
+-		if (data->n_params >= SYNTH_FIELDS_MAX)
+-			goto out;
+-
+-		param = strsep(&params, ",");
+-		if (!param) {
+-			ret = -EINVAL;
+-			goto out;
+-		}
+-
+-		param = strstrip(param);
+-		if (strlen(param) < 2) {
+-			ret = -EINVAL;
+-			goto out;
+-		}
+-
+-		saved_param = kstrdup(param, GFP_KERNEL);
+-		if (!saved_param) {
+-			ret = -ENOMEM;
+-			goto out;
+-		}
+-
+-		data->params[data->n_params++] = saved_param;
+-	}
+- out:
+-	return ret;
+-}
+-
+ static struct hist_field *
+ onmatch_find_var(struct hist_trigger_data *hist_data, struct action_data *data,
+ 		 char *system, char *event, char *var)
+@@ -3796,6 +4006,8 @@ static void destroy_actions(struct hist_trigger_data *hist_data)
+ 
+ 		if (data->fn == action_trace)
+ 			onmatch_destroy(data);
++		else if (data->fn == onmax_save)
++			onmax_destroy(data);
+ 		else
+ 			kfree(data);
+ 	}
+@@ -3821,6 +4033,15 @@ static int parse_actions(struct hist_trigger_data *hist_data)
+ 				break;
+ 			}
+ 			data->fn = action_trace;
++		} else if (strncmp(str, "onmax(", strlen("onmax(")) == 0) {
++			char *action_str = str + strlen("onmax(");
++
++			data = onmax_parse(action_str);
++			if (IS_ERR(data)) {
++				ret = PTR_ERR(data);
++				break;
++			}
++			data->fn = onmax_save;
+ 		} else {
+ 			ret = -EINVAL;
+ 			break;
+@@ -3846,12 +4067,48 @@ static int create_actions(struct hist_trigger_data *hist_data,
+ 			ret = onmatch_create(hist_data, file, data);
+ 			if (ret)
+ 				return ret;
++		} else if (data->fn == onmax_save) {
++			ret = onmax_create(hist_data, data);
++			if (ret)
++				return ret;
+ 		}
+ 	}
+ 
+ 	return ret;
+ }
+ 
++static void print_actions(struct seq_file *m,
++			  struct hist_trigger_data *hist_data,
++			  struct tracing_map_elt *elt)
++{
++	unsigned int i;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		struct action_data *data = hist_data->actions[i];
++
++		if (data->fn == onmax_save)
++			onmax_print(m, hist_data, elt, data);
++	}
++}
++
++static void print_onmax_spec(struct seq_file *m,
++			     struct hist_trigger_data *hist_data,
++			     struct action_data *data)
++{
++	unsigned int i;
++
++	seq_puts(m, ":onmax(");
++	seq_printf(m, "%s", data->onmax.var_str);
++	seq_printf(m, ").%s(", data->onmax.fn_name);
++
++	for (i = 0; i < hist_data->n_max_vars; i++) {
++		seq_printf(m, "%s", hist_data->max_vars[i]->var->var.name);
++		if (i < hist_data->n_max_vars - 1)
++			seq_puts(m, ",");
++	}
++	seq_puts(m, ")");
++}
++
+ static void print_onmatch_spec(struct seq_file *m,
+ 			       struct hist_trigger_data *hist_data,
+ 			       struct action_data *data)
+@@ -3882,6 +4139,8 @@ static void print_actions_spec(struct seq_file *m,
+ 
+ 		if (data->fn == action_trace)
+ 			print_onmatch_spec(m, hist_data, data);
++		else if (data->fn == onmax_save)
++			print_onmax_spec(m, hist_data, data);
+ 	}
+ }
+ 
+@@ -4263,6 +4522,8 @@ hist_trigger_entry_print(struct seq_file *m,
+ 		}
+ 	}
+ 
++	print_actions(m, hist_data, elt);
++
+ 	seq_puts(m, "\n");
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1775-tracing-Allow-whitespace-to-surround-hist-trigger-fi.patch b/patches/1775-tracing-Allow-whitespace-to-surround-hist-trigger-fi.patch
new file mode 100644
index 00000000000000..cd774268bb7572
--- /dev/null
+++ b/patches/1775-tracing-Allow-whitespace-to-surround-hist-trigger-fi.patch
@@ -0,0 +1,82 @@
+From 82b5a04d74f9ba46f1d06b6b1583145f7210a9e9 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:02 -0600
+Subject: [PATCH 1775/1795] tracing: Allow whitespace to surround hist trigger
+ filter
+
+The existing code only allows for one space before and after the 'if'
+specifying the filter for a hist trigger.  Add code to make that more
+permissive as far as whitespace goes.  Specifically, we want to allow
+spaces in the trigger itself now that we have additional syntax
+(onmatch/onmax) where spaces are more natural e.g. spaces after commas
+in param lists.
+
+Link: http://lkml.kernel.org/r/1053090c3c308d4f431accdeb59dff4b511d4554.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit ec5ce0987541087dbea5af346bdb85eb04b0f0a2)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 37 +++++++++++++++++++++++++++-----
+ 1 file changed, 32 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 7bcc32a7e266..7e88daae85b6 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -5162,7 +5162,7 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	struct synth_event *se;
+ 	const char *se_name;
+ 	bool remove = false;
+-	char *trigger;
++	char *trigger, *p;
+ 	int ret = 0;
+ 
+ 	if (!param)
+@@ -5171,10 +5171,37 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	if (glob[0] == '!')
+ 		remove = true;
+ 
+-	/* separate the trigger from the filter (k:v [if filter]) */
+-	trigger = strsep(&param, " \t");
+-	if (!trigger)
+-		return -EINVAL;
++	/*
++	 * separate the trigger from the filter (k:v [if filter])
++	 * allowing for whitespace in the trigger
++	 */
++	p = trigger = param;
++	do {
++		p = strstr(p, "if");
++		if (!p)
++			break;
++		if (p == param)
++			return -EINVAL;
++		if (*(p - 1) != ' ' && *(p - 1) != '\t') {
++			p++;
++			continue;
++		}
++		if (p >= param + strlen(param) - strlen("if") - 1)
++			return -EINVAL;
++		if (*(p + strlen("if")) != ' ' && *(p + strlen("if")) != '\t') {
++			p++;
++			continue;
++		}
++		break;
++	} while (p);
++
++	if (!p)
++		param = NULL;
++	else {
++		*(p - 1) = '\0';
++		param = strstrip(p);
++		trigger = strstrip(trigger);
++	}
+ 
+ 	attrs = parse_hist_trigger_attrs(trigger);
+ 	if (IS_ERR(attrs))
+-- 
+2.19.0
+
diff --git a/patches/1776-tracing-Add-cpu-field-for-hist-triggers.patch b/patches/1776-tracing-Add-cpu-field-for-hist-triggers.patch
new file mode 100644
index 00000000000000..1cc67e6a718f00
--- /dev/null
+++ b/patches/1776-tracing-Add-cpu-field-for-hist-triggers.patch
@@ -0,0 +1,123 @@
+From 48e6bf50c935e33015ef25319b8b8ee15169e128 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:03 -0600
+Subject: [PATCH 1776/1795] tracing: Add cpu field for hist triggers
+
+A common key to use in a histogram is the cpuid - add a new cpu
+'synthetic' field named 'cpu' for that purpose.
+
+Link: http://lkml.kernel.org/r/89537645bfc957e0d76e2cacf5f0ada88691a6cc.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 8b7622bf94a44b3f912e6492bf500e86171300b8)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt | 15 +++++++++++++++
+ kernel/trace/trace_events_hist.c  | 28 +++++++++++++++++++++++++++-
+ 2 files changed, 42 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index 25c94730d3fe..be612ca79455 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -172,6 +172,21 @@
+   The examples below provide a more concrete illustration of the
+   concepts and typical usage patterns discussed above.
+ 
++  'special' event fields
++  ------------------------
++
++  There are a number of 'special event fields' available for use as
++  keys or values in a hist trigger.  These look like and behave as if
++  they were actual event fields, but aren't really part of the event's
++  field definition or format file.  They are however available for any
++  event, and can be used anywhere an actual event field could be.
++  They are:
++
++    common_timestamp       u64 - timestamp (from ring buffer) associated
++                                 with the event, in nanoseconds.  May be
++				 modified by .usecs to have timestamps
++				 interpreted as microseconds.
++    cpu                    int - the cpu on which the event occurred.
+ 
+ 6.2 'hist' trigger examples
+ ---------------------------
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 7e88daae85b6..98be6ad883eb 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -227,6 +227,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_VAR		= 1 << 12,
+ 	HIST_FIELD_FL_EXPR		= 1 << 13,
+ 	HIST_FIELD_FL_VAR_REF		= 1 << 14,
++	HIST_FIELD_FL_CPU		= 1 << 15,
+ };
+ 
+ struct var_defs {
+@@ -1164,6 +1165,16 @@ static u64 hist_field_timestamp(struct hist_field *hist_field,
+ 	return ts;
+ }
+ 
++static u64 hist_field_cpu(struct hist_field *hist_field,
++			  struct tracing_map_elt *elt,
++			  struct ring_buffer_event *rbe,
++			  void *event)
++{
++	int cpu = smp_processor_id();
++
++	return cpu;
++}
++
+ static struct hist_field *
+ check_field_for_var_ref(struct hist_field *hist_field,
+ 			struct hist_trigger_data *var_data,
+@@ -1602,6 +1613,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 		field_name = hist_field_name(field->operands[0], ++level);
+ 	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		field_name = "common_timestamp";
++	else if (field->flags & HIST_FIELD_FL_CPU)
++		field_name = "cpu";
+ 	else if (field->flags & HIST_FIELD_FL_EXPR ||
+ 		 field->flags & HIST_FIELD_FL_VAR_REF) {
+ 		if (field->system) {
+@@ -2109,6 +2122,15 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 		goto out;
+ 	}
+ 
++	if (flags & HIST_FIELD_FL_CPU) {
++		hist_field->fn = hist_field_cpu;
++		hist_field->size = sizeof(int);
++		hist_field->type = kstrdup("unsigned int", GFP_KERNEL);
++		if (!hist_field->type)
++			goto free;
++		goto out;
++	}
++
+ 	if (WARN_ON_ONCE(!field))
+ 		goto out;
+ 
+@@ -2345,7 +2367,9 @@ parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
+ 		hist_data->enable_timestamps = true;
+ 		if (*flags & HIST_FIELD_FL_TIMESTAMP_USECS)
+ 			hist_data->attrs->ts_in_usecs = true;
+-	} else {
++	} else if (strcmp(field_name, "cpu") == 0)
++		*flags |= HIST_FIELD_FL_CPU;
++	else {
+ 		field = trace_find_event_field(file->event_call, field_name);
+ 		if (!field || !field->size) {
+ 			field = ERR_PTR(-EINVAL);
+@@ -4619,6 +4643,8 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ 
+ 	if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		seq_puts(m, "common_timestamp");
++	else if (hist_field->flags & HIST_FIELD_FL_CPU)
++		seq_puts(m, "cpu");
+ 	else if (field_name) {
+ 		if (hist_field->flags & HIST_FIELD_FL_VAR_REF)
+ 			seq_putc(m, '$');
+-- 
+2.19.0
+
diff --git a/patches/1777-tracing-Add-hist-trigger-support-for-variable-refere.patch b/patches/1777-tracing-Add-hist-trigger-support-for-variable-refere.patch
new file mode 100644
index 00000000000000..0e61cf37e9150b
--- /dev/null
+++ b/patches/1777-tracing-Add-hist-trigger-support-for-variable-refere.patch
@@ -0,0 +1,171 @@
+From c79c4ea38f50526c20ef77299da8e8b14b697f8b Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:04 -0600
+Subject: [PATCH 1777/1795] tracing: Add hist trigger support for variable
+ reference aliases
+
+Add support for alias=$somevar where alias can be used as
+onmatch.xxx($alias).
+
+Aliases are a way of creating a new name for an existing variable, for
+flexibly in making naming more clear in certain cases.  For example in
+the below the user perhaps feels that using $new_lat in the synthetic
+event invocation is opaque or doesn't fit well stylistically with
+previous triggers, so creates an alias of $new_lat named $latency and
+uses that in the call instead:
+
+  # echo 'hist:keys=next_pid:new_lat=common_timestamp.usecs' >
+    /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+  # echo 'hist:keys=pid:latency=$new_lat:
+    onmatch(sched.sched_switch).wake2($latency,pid)' >
+    /sys/kernel/debug/tracing/events/synthetic/wake1/trigger
+
+Link: http://lkml.kernel.org/r/ef20a65d921af3a873a6f1e8c71407c926d5586f.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 7e8b88a30b085d4205b6afcc5e577604978b1268)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 74 +++++++++++++++++++++++++++++---
+ 1 file changed, 67 insertions(+), 7 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 98be6ad883eb..32af523501bc 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -228,6 +228,7 @@ enum hist_field_flags {
+ 	HIST_FIELD_FL_EXPR		= 1 << 13,
+ 	HIST_FIELD_FL_VAR_REF		= 1 << 14,
+ 	HIST_FIELD_FL_CPU		= 1 << 15,
++	HIST_FIELD_FL_ALIAS		= 1 << 16,
+ };
+ 
+ struct var_defs {
+@@ -1609,7 +1610,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 
+ 	if (field->field)
+ 		field_name = field->field->name;
+-	else if (field->flags & HIST_FIELD_FL_LOG2)
++	else if (field->flags & HIST_FIELD_FL_LOG2 ||
++		 field->flags & HIST_FIELD_FL_ALIAS)
+ 		field_name = hist_field_name(field->operands[0], ++level);
+ 	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		field_name = "common_timestamp";
+@@ -2080,7 +2082,7 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data,
+ 
+ 	hist_field->hist_data = hist_data;
+ 
+-	if (flags & HIST_FIELD_FL_EXPR)
++	if (flags & HIST_FIELD_FL_EXPR || flags & HIST_FIELD_FL_ALIAS)
+ 		goto out; /* caller will populate */
+ 
+ 	if (flags & HIST_FIELD_FL_VAR_REF) {
+@@ -2217,10 +2219,18 @@ static int init_var_ref(struct hist_field *ref_field,
+ 		}
+ 	}
+ 
+-	ref_field->name = kstrdup(var_field->var.name, GFP_KERNEL);
+-	if (!ref_field->name) {
+-		err = -ENOMEM;
+-		goto free;
++	if (var_field->var.name) {
++		ref_field->name = kstrdup(var_field->var.name, GFP_KERNEL);
++		if (!ref_field->name) {
++			err = -ENOMEM;
++			goto free;
++		}
++	} else if (var_field->name) {
++		ref_field->name = kstrdup(var_field->name, GFP_KERNEL);
++		if (!ref_field->name) {
++			err = -ENOMEM;
++			goto free;
++		}
+ 	}
+ 
+ 	ref_field->type = kstrdup(var_field->type, GFP_KERNEL);
+@@ -2382,6 +2392,28 @@ parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
+ 	return field;
+ }
+ 
++static struct hist_field *create_alias(struct hist_trigger_data *hist_data,
++				       struct hist_field *var_ref,
++				       char *var_name)
++{
++	struct hist_field *alias = NULL;
++	unsigned long flags = HIST_FIELD_FL_ALIAS | HIST_FIELD_FL_VAR;
++
++	alias = create_hist_field(hist_data, NULL, flags, var_name);
++	if (!alias)
++		return NULL;
++
++	alias->fn = var_ref->fn;
++	alias->operands[0] = var_ref;
++
++	if (init_var_ref(alias, var_ref, var_ref->system, var_ref->event_name)) {
++		destroy_hist_field(alias, 0);
++		return NULL;
++	}
++
++	return alias;
++}
++
+ static struct hist_field *parse_atom(struct hist_trigger_data *hist_data,
+ 				     struct trace_event_file *file, char *str,
+ 				     unsigned long *flags, char *var_name)
+@@ -2415,6 +2447,13 @@ static struct hist_field *parse_atom(struct hist_trigger_data *hist_data,
+ 		if (hist_field) {
+ 			hist_data->var_refs[hist_data->n_var_refs] = hist_field;
+ 			hist_field->var_ref_idx = hist_data->n_var_refs++;
++			if (var_name) {
++				hist_field = create_alias(hist_data, hist_field, var_name);
++				if (!hist_field) {
++					ret = -ENOMEM;
++					goto out;
++				}
++			}
+ 			return hist_field;
+ 		}
+ 	} else
+@@ -2515,6 +2554,26 @@ static int check_expr_operands(struct hist_field *operand1,
+ 	unsigned long operand1_flags = operand1->flags;
+ 	unsigned long operand2_flags = operand2->flags;
+ 
++	if ((operand1_flags & HIST_FIELD_FL_VAR_REF) ||
++	    (operand1_flags & HIST_FIELD_FL_ALIAS)) {
++		struct hist_field *var;
++
++		var = find_var_field(operand1->var.hist_data, operand1->name);
++		if (!var)
++			return -EINVAL;
++		operand1_flags = var->flags;
++	}
++
++	if ((operand2_flags & HIST_FIELD_FL_VAR_REF) ||
++	    (operand2_flags & HIST_FIELD_FL_ALIAS)) {
++		struct hist_field *var;
++
++		var = find_var_field(operand2->var.hist_data, operand2->name);
++		if (!var)
++			return -EINVAL;
++		operand2_flags = var->flags;
++	}
++
+ 	if ((operand1_flags & HIST_FIELD_FL_TIMESTAMP_USECS) !=
+ 	    (operand2_flags & HIST_FIELD_FL_TIMESTAMP_USECS))
+ 		return -EINVAL;
+@@ -4646,7 +4705,8 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ 	else if (hist_field->flags & HIST_FIELD_FL_CPU)
+ 		seq_puts(m, "cpu");
+ 	else if (field_name) {
+-		if (hist_field->flags & HIST_FIELD_FL_VAR_REF)
++		if (hist_field->flags & HIST_FIELD_FL_VAR_REF ||
++		    hist_field->flags & HIST_FIELD_FL_ALIAS)
+ 			seq_putc(m, '$');
+ 		seq_printf(m, "%s", field_name);
+ 	}
+-- 
+2.19.0
+
diff --git a/patches/1778-tracing-Add-last-error-error-facility-for-hist-trigg.patch b/patches/1778-tracing-Add-last-error-error-facility-for-hist-trigg.patch
new file mode 100644
index 00000000000000..53aef6a8c8c64a
--- /dev/null
+++ b/patches/1778-tracing-Add-last-error-error-facility-for-hist-trigg.patch
@@ -0,0 +1,511 @@
+From 6a33091126efc52fc11218a6d118b7c7d4ec6f54 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:05 -0600
+Subject: [PATCH 1778/1795] tracing: Add 'last error' error facility for hist
+ triggers
+
+With the addition of variables and actions, it's become necessary to
+provide more detailed error information to users about syntax errors.
+
+Add a 'last error' facility accessible via the erroring event's 'hist'
+file.  Reading the hist file after an error will display more detailed
+information about what went wrong, if information is available.  This
+extended error information will be available until the next hist
+trigger command for that event.
+
+  # echo xxx > /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  echo: write error: Invalid argument
+
+  # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/hist
+
+  ERROR: Couldn't yyy: zzz
+  Last command: xxx
+
+Also add specific error messages for variable and action errors.
+
+Link: http://lkml.kernel.org/r/64e9c422fc8aeafcc2f7a3b4328c0cffe7969129.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit f404da6e1d46ced7d3b53377f1e140c486ea7350)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt |  20 ++++
+ kernel/trace/trace_events_hist.c  | 164 +++++++++++++++++++++++++++---
+ 2 files changed, 170 insertions(+), 14 deletions(-)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index be612ca79455..0aec2d8e166b 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -188,6 +188,26 @@
+ 				 interpreted as microseconds.
+     cpu                    int - the cpu on which the event occurred.
+ 
++  Extended error information
++  --------------------------
++
++  For some error conditions encountered when invoking a hist trigger
++  command, extended error information is available via the
++  corresponding event's 'hist' file.  Reading the hist file after an
++  error will display more detailed information about what went wrong,
++  if information is available.  This extended error information will
++  be available until the next hist trigger command for that event.
++
++  If available for a given error condition, the extended error
++  information and usage takes the following form:
++
++    # echo xxx > /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
++    echo: write error: Invalid argument
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/hist
++    ERROR: Couldn't yyy: zzz
++      Last command: xxx
++
+ 6.2 'hist' trigger examples
+ ---------------------------
+ 
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 32af523501bc..8719b0ea672f 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -351,6 +351,65 @@ struct action_data {
+ 	};
+ };
+ 
++
++static char last_hist_cmd[MAX_FILTER_STR_VAL];
++static char hist_err_str[MAX_FILTER_STR_VAL];
++
++static void last_cmd_set(char *str)
++{
++	if (!str)
++		return;
++
++	strncpy(last_hist_cmd, str, MAX_FILTER_STR_VAL - 1);
++}
++
++static void hist_err(char *str, char *var)
++{
++	int maxlen = MAX_FILTER_STR_VAL - 1;
++
++	if (!str)
++		return;
++
++	if (strlen(hist_err_str))
++		return;
++
++	if (!var)
++		var = "";
++
++	if (strlen(hist_err_str) + strlen(str) + strlen(var) > maxlen)
++		return;
++
++	strcat(hist_err_str, str);
++	strcat(hist_err_str, var);
++}
++
++static void hist_err_event(char *str, char *system, char *event, char *var)
++{
++	char err[MAX_FILTER_STR_VAL];
++
++	if (system && var)
++		snprintf(err, MAX_FILTER_STR_VAL, "%s.%s.%s", system, event, var);
++	else if (system)
++		snprintf(err, MAX_FILTER_STR_VAL, "%s.%s", system, event);
++	else
++		strncpy(err, var, MAX_FILTER_STR_VAL);
++
++	hist_err(str, err);
++}
++
++static void hist_err_clear(void)
++{
++	hist_err_str[0] = '\0';
++}
++
++static bool have_hist_err(void)
++{
++	if (strlen(hist_err_str))
++		return true;
++
++	return false;
++}
++
+ static LIST_HEAD(synth_event_list);
+ static DEFINE_MUTEX(synth_event_mutex);
+ 
+@@ -1448,8 +1507,10 @@ static struct trace_event_file *find_var_file(struct trace_array *tr,
+ 			continue;
+ 
+ 		if (find_var_field(var_hist_data, var_name)) {
+-			if (found)
++			if (found) {
++				hist_err_event("Variable name not unique, need to use fully qualified name (subsys.event.var) for variable: ", system, event_name, var_name);
+ 				return NULL;
++			}
+ 
+ 			found = file;
+ 		}
+@@ -1498,6 +1559,7 @@ find_match_var(struct hist_trigger_data *hist_data, char *var_name)
+ 			hist_field = find_file_var(file, var_name);
+ 			if (hist_field) {
+ 				if (found) {
++					hist_err_event("Variable name not unique, need to use fully qualified name (subsys.event.var) for variable: ", system, event_name, var_name);
+ 					return ERR_PTR(-EINVAL);
+ 				}
+ 
+@@ -1781,6 +1843,7 @@ static int parse_assignment(char *str, struct hist_trigger_attrs *attrs)
+ 		char *assignment;
+ 
+ 		if (attrs->n_assignments == TRACING_MAP_VARS_MAX) {
++			hist_err("Too many variables defined: ", str);
+ 			ret = -EINVAL;
+ 			goto out;
+ 		}
+@@ -2335,6 +2398,10 @@ static struct hist_field *parse_var_ref(struct hist_trigger_data *hist_data,
+ 	if (var_field)
+ 		ref_field = create_var_ref(var_field, system, event_name);
+ 
++	if (!ref_field)
++		hist_err_event("Couldn't find variable: $",
++			       system, event_name, var_name);
++
+ 	return ref_field;
+ }
+ 
+@@ -2494,6 +2561,7 @@ static struct hist_field *parse_unary(struct hist_trigger_data *hist_data,
+ 	/* we support only -(xxx) i.e. explicit parens required */
+ 
+ 	if (level > 3) {
++		hist_err("Too many subexpressions (3 max): ", str);
+ 		ret = -EINVAL;
+ 		goto free;
+ 	}
+@@ -2575,8 +2643,10 @@ static int check_expr_operands(struct hist_field *operand1,
+ 	}
+ 
+ 	if ((operand1_flags & HIST_FIELD_FL_TIMESTAMP_USECS) !=
+-	    (operand2_flags & HIST_FIELD_FL_TIMESTAMP_USECS))
++	    (operand2_flags & HIST_FIELD_FL_TIMESTAMP_USECS)) {
++		hist_err("Timestamp units in expression don't match", NULL);
+ 		return -EINVAL;
++	}
+ 
+ 	return 0;
+ }
+@@ -2591,8 +2661,10 @@ static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
+ 	int field_op, ret = -EINVAL;
+ 	char *sep, *operand1_str;
+ 
+-	if (level > 3)
++	if (level > 3) {
++		hist_err("Too many subexpressions (3 max): ", str);
+ 		return ERR_PTR(-EINVAL);
++	}
+ 
+ 	field_op = contains_operator(str);
+ 
+@@ -2826,12 +2898,17 @@ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 	char *cmd;
+ 	int ret;
+ 
+-	if (target_hist_data->n_field_var_hists >= SYNTH_FIELDS_MAX)
++	if (target_hist_data->n_field_var_hists >= SYNTH_FIELDS_MAX) {
++		hist_err_event("onmatch: Too many field variables defined: ",
++			       subsys_name, event_name, field_name);
+ 		return ERR_PTR(-EINVAL);
++	}
+ 
+ 	file = event_file(tr, subsys_name, event_name);
+ 
+ 	if (IS_ERR(file)) {
++		hist_err_event("onmatch: Event file not found: ",
++			       subsys_name, event_name, field_name);
+ 		ret = PTR_ERR(file);
+ 		return ERR_PTR(ret);
+ 	}
+@@ -2843,8 +2920,11 @@ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 	 * yet a registered histogram so we can't use that.
+ 	 */
+ 	hist_data = find_compatible_hist(target_hist_data, file);
+-	if (!hist_data)
++	if (!hist_data) {
++		hist_err_event("onmatch: Matching event histogram not found: ",
++			       subsys_name, event_name, field_name);
+ 		return ERR_PTR(-EINVAL);
++	}
+ 
+ 	/* See if a synthetic field variable has already been created */
+ 	event_var = find_synthetic_field_var(target_hist_data, subsys_name,
+@@ -2903,6 +2983,8 @@ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 		kfree(cmd);
+ 		kfree(var_hist->cmd);
+ 		kfree(var_hist);
++		hist_err_event("onmatch: Couldn't create histogram for field: ",
++			       subsys_name, event_name, field_name);
+ 		return ERR_PTR(ret);
+ 	}
+ 
+@@ -2914,6 +2996,8 @@ create_field_var_hist(struct hist_trigger_data *target_hist_data,
+ 	if (IS_ERR_OR_NULL(event_var)) {
+ 		kfree(var_hist->cmd);
+ 		kfree(var_hist);
++		hist_err_event("onmatch: Couldn't find synthetic variable: ",
++			       subsys_name, event_name, field_name);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+@@ -3050,18 +3134,21 @@ static struct field_var *create_field_var(struct hist_trigger_data *hist_data,
+ 	int ret = 0;
+ 
+ 	if (hist_data->n_field_vars >= SYNTH_FIELDS_MAX) {
++		hist_err("Too many field variables defined: ", field_name);
+ 		ret = -EINVAL;
+ 		goto err;
+ 	}
+ 
+ 	val = parse_atom(hist_data, file, field_name, &flags, NULL);
+ 	if (IS_ERR(val)) {
++		hist_err("Couldn't parse field variable: ", field_name);
+ 		ret = PTR_ERR(val);
+ 		goto err;
+ 	}
+ 
+ 	var = create_var(hist_data, file, field_name, val->size, val->type);
+ 	if (IS_ERR(var)) {
++		hist_err("Couldn't create or find variable: ", field_name);
+ 		kfree(val);
+ 		ret = PTR_ERR(var);
+ 		goto err;
+@@ -3204,13 +3291,17 @@ static int onmax_create(struct hist_trigger_data *hist_data,
+ 	int ret = 0;
+ 
+ 	onmax_var_str = data->onmax.var_str;
+-	if (onmax_var_str[0] != '$')
++	if (onmax_var_str[0] != '$') {
++		hist_err("onmax: For onmax(x), x must be a variable: ", onmax_var_str);
+ 		return -EINVAL;
++	}
+ 	onmax_var_str++;
+ 
+ 	var_field = find_target_event_var(hist_data, NULL, NULL, onmax_var_str);
+-	if (!var_field)
++	if (!var_field) {
++		hist_err("onmax: Couldn't find onmax variable: ", onmax_var_str);
+ 		return -EINVAL;
++	}
+ 
+ 	flags = HIST_FIELD_FL_VAR_REF;
+ 	ref_field = create_hist_field(hist_data, NULL, flags, NULL);
+@@ -3230,6 +3321,7 @@ static int onmax_create(struct hist_trigger_data *hist_data,
+ 	data->onmax.max_var_ref_idx = var_ref_idx;
+ 	max_var = create_var(hist_data, file, "max", sizeof(u64), "u64");
+ 	if (IS_ERR(max_var)) {
++		hist_err("onmax: Couldn't create onmax variable: ", "max");
+ 		ret = PTR_ERR(max_var);
+ 		goto out;
+ 	}
+@@ -3244,6 +3336,7 @@ static int onmax_create(struct hist_trigger_data *hist_data,
+ 
+ 		field_var = create_target_field_var(hist_data, NULL, NULL, param);
+ 		if (IS_ERR(field_var)) {
++			hist_err("onmax: Couldn't create field variable: ", param);
+ 			ret = PTR_ERR(field_var);
+ 			kfree(param);
+ 			goto out;
+@@ -3276,6 +3369,7 @@ static int parse_action_params(char *params, struct action_data *data)
+ 
+ 		param = strstrip(param);
+ 		if (strlen(param) < 2) {
++			hist_err("Invalid action param: ", param);
+ 			ret = -EINVAL;
+ 			goto out;
+ 		}
+@@ -3451,6 +3545,9 @@ onmatch_find_var(struct hist_trigger_data *hist_data, struct action_data *data,
+ 		hist_field = find_event_var(hist_data, system, event, var);
+ 	}
+ 
++	if (!hist_field)
++		hist_err_event("onmatch: Couldn't find onmatch param: $", system, event, var);
++
+ 	return hist_field;
+ }
+ 
+@@ -3518,6 +3615,7 @@ static int onmatch_create(struct hist_trigger_data *hist_data,
+ 	mutex_lock(&synth_event_mutex);
+ 	event = find_synth_event(data->onmatch.synth_event_name);
+ 	if (!event) {
++		hist_err("onmatch: Couldn't find synthetic event: ", data->onmatch.synth_event_name);
+ 		mutex_unlock(&synth_event_mutex);
+ 		return -EINVAL;
+ 	}
+@@ -3577,12 +3675,15 @@ static int onmatch_create(struct hist_trigger_data *hist_data,
+ 			continue;
+ 		}
+ 
++		hist_err_event("onmatch: Param type doesn't match synthetic event field type: ",
++			       system, event_name, param);
+ 		kfree(p);
+ 		ret = -EINVAL;
+ 		goto err;
+ 	}
+ 
+ 	if (field_pos != event->n_fields) {
++		hist_err("onmatch: Param count doesn't match synthetic event field count: ", event->name);
+ 		ret = -EINVAL;
+ 		goto err;
+ 	}
+@@ -3612,15 +3713,22 @@ static struct action_data *onmatch_parse(struct trace_array *tr, char *str)
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	match_event = strsep(&str, ")");
+-	if (!match_event || !str)
++	if (!match_event || !str) {
++		hist_err("onmatch: Missing closing paren: ", match_event);
+ 		goto free;
++	}
+ 
+ 	match_event_system = strsep(&match_event, ".");
+-	if (!match_event)
++	if (!match_event) {
++		hist_err("onmatch: Missing subsystem for match event: ", match_event_system);
+ 		goto free;
++	}
+ 
+-	if (IS_ERR(event_file(tr, match_event_system, match_event)))
++	if (IS_ERR(event_file(tr, match_event_system, match_event))) {
++		hist_err_event("onmatch: Invalid subsystem or event name: ",
++			       match_event_system, match_event, NULL);
+ 		goto free;
++	}
+ 
+ 	data->onmatch.match_event = kstrdup(match_event, GFP_KERNEL);
+ 	if (!data->onmatch.match_event) {
+@@ -3635,12 +3743,16 @@ static struct action_data *onmatch_parse(struct trace_array *tr, char *str)
+ 	}
+ 
+ 	strsep(&str, ".");
+-	if (!str)
++	if (!str) {
++		hist_err("onmatch: Missing . after onmatch(): ", str);
+ 		goto free;
++	}
+ 
+ 	synth_event_name = strsep(&str, "(");
+-	if (!synth_event_name || !str)
++	if (!synth_event_name || !str) {
++		hist_err("onmatch: Missing opening paramlist paren: ", synth_event_name);
+ 		goto free;
++	}
+ 
+ 	data->onmatch.synth_event_name = kstrdup(synth_event_name, GFP_KERNEL);
+ 	if (!data->onmatch.synth_event_name) {
+@@ -3649,8 +3761,10 @@ static struct action_data *onmatch_parse(struct trace_array *tr, char *str)
+ 	}
+ 
+ 	params = strsep(&str, ")");
+-	if (!params || !str || (str && strlen(str)))
++	if (!params || !str || (str && strlen(str))) {
++		hist_err("onmatch: Missing closing paramlist paren: ", params);
+ 		goto free;
++	}
+ 
+ 	ret = parse_action_params(params, data);
+ 	if (ret)
+@@ -3725,7 +3839,9 @@ static int create_var_field(struct hist_trigger_data *hist_data,
+ 
+ 	if (WARN_ON(val_idx >= TRACING_MAP_VALS_MAX + TRACING_MAP_VARS_MAX))
+ 		return -EINVAL;
++
+ 	if (find_var(hist_data, file, var_name) && !hist_data->remove) {
++		hist_err("Variable already defined: ", var_name);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -3806,6 +3922,7 @@ static int create_key_field(struct hist_trigger_data *hist_data,
+ 		}
+ 
+ 		if (hist_field->flags & HIST_FIELD_FL_VAR_REF) {
++			hist_err("Using variable references as keys not supported: ", field_str);
+ 			destroy_hist_field(hist_field, 0);
+ 			ret = -EINVAL;
+ 			goto out;
+@@ -3919,11 +4036,13 @@ static int parse_var_defs(struct hist_trigger_data *hist_data)
+ 
+ 			var_name = strsep(&field_str, "=");
+ 			if (!var_name || !field_str) {
++				hist_err("Malformed assignment: ", var_name);
+ 				ret = -EINVAL;
+ 				goto free;
+ 			}
+ 
+ 			if (n_vars == TRACING_MAP_VARS_MAX) {
++				hist_err("Too many variables defined: ", var_name);
+ 				ret = -EINVAL;
+ 				goto free;
+ 			}
+@@ -4675,6 +4794,11 @@ static int hist_show(struct seq_file *m, void *v)
+ 			hist_trigger_show(m, data, n++);
+ 	}
+ 
++	if (have_hist_err()) {
++		seq_printf(m, "\nERROR: %s\n", hist_err_str);
++		seq_printf(m, "  Last command: %s\n", last_hist_cmd);
++	}
++
+  out_unlock:
+ 	mutex_unlock(&event_mutex);
+ 
+@@ -5039,6 +5163,7 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 		if (named_data) {
+ 			if (!hist_trigger_match(data, named_data, named_data,
+ 						true)) {
++				hist_err("Named hist trigger doesn't match existing named trigger (includes variables): ", hist_data->attrs->name);
+ 				ret = -EINVAL;
+ 				goto out;
+ 			}
+@@ -5058,13 +5183,16 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 				test->paused = false;
+ 			else if (hist_data->attrs->clear)
+ 				hist_clear(test);
+-			else
++			else {
++				hist_err("Hist trigger already exists", NULL);
+ 				ret = -EEXIST;
++			}
+ 			goto out;
+ 		}
+ 	}
+  new:
+ 	if (hist_data->attrs->cont || hist_data->attrs->clear) {
++		hist_err("Can't clear or continue a nonexistent hist trigger", NULL);
+ 		ret = -ENOENT;
+ 		goto out;
+ 	}
+@@ -5251,6 +5379,11 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	char *trigger, *p;
+ 	int ret = 0;
+ 
++	if (glob && strlen(glob)) {
++		last_cmd_set(param);
++		hist_err_clear();
++	}
++
+ 	if (!param)
+ 		return -EINVAL;
+ 
+@@ -5389,6 +5522,9 @@ static int event_hist_trigger_func(struct event_command *cmd_ops,
+ 	/* Just return zero, not the number of registered triggers */
+ 	ret = 0;
+  out:
++	if (ret == 0)
++		hist_err_clear();
++
+ 	return ret;
+  out_unreg:
+ 	cmd_ops->unreg(glob+1, trigger_ops, trigger_data, file);
+-- 
+2.19.0
+
diff --git a/patches/1779-tracing-Add-inter-event-hist-trigger-Documentation.patch b/patches/1779-tracing-Add-inter-event-hist-trigger-Documentation.patch
new file mode 100644
index 00000000000000..f359883d7e9a50
--- /dev/null
+++ b/patches/1779-tracing-Add-inter-event-hist-trigger-Documentation.patch
@@ -0,0 +1,412 @@
+From 693c76cc46ff78192a3e52007e1c4bf5862f3696 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:06 -0600
+Subject: [PATCH 1779/1795] tracing: Add inter-event hist trigger Documentation
+
+Add background and details on inter-event hist triggers, including
+hist variables, synthetic events, and actions.
+
+Link: http://lkml.kernel.org/r/b0414efb66535aa52aa7411f58c3d56724027fce.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Baohong Liu <baohong.liu@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 033cbceefa9d439a15f59263327812dfabfbdc6c)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt | 381 ++++++++++++++++++++++++++++++
+ 1 file changed, 381 insertions(+)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index 0aec2d8e166b..df08882d091c 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -1603,3 +1603,384 @@
+         Hits: 489
+         Entries: 7
+         Dropped: 0
++
++
++2.2 Inter-event hist triggers
++-----------------------------
++
++Inter-event hist triggers are hist triggers that combine values from
++one or more other events and create a histogram using that data.  Data
++from an inter-event histogram can in turn become the source for
++further combined histograms, thus providing a chain of related
++histograms, which is important for some applications.
++
++The most important example of an inter-event quantity that can be used
++in this manner is latency, which is simply a difference in timestamps
++between two events.  Although latency is the most important
++inter-event quantity, note that because the support is completely
++general across the trace event subsystem, any event field can be used
++in an inter-event quantity.
++
++An example of a histogram that combines data from other histograms
++into a useful chain would be a 'wakeupswitch latency' histogram that
++combines a 'wakeup latency' histogram and a 'switch latency'
++histogram.
++
++Normally, a hist trigger specification consists of a (possibly
++compound) key along with one or more numeric values, which are
++continually updated sums associated with that key.  A histogram
++specification in this case consists of individual key and value
++specifications that refer to trace event fields associated with a
++single event type.
++
++The inter-event hist trigger extension allows fields from multiple
++events to be referenced and combined into a multi-event histogram
++specification.  In support of this overall goal, a few enabling
++features have been added to the hist trigger support:
++
++  - In order to compute an inter-event quantity, a value from one
++    event needs to saved and then referenced from another event.  This
++    requires the introduction of support for histogram 'variables'.
++
++  - The computation of inter-event quantities and their combination
++    require some minimal amount of support for applying simple
++    expressions to variables (+ and -).
++
++  - A histogram consisting of inter-event quantities isn't logically a
++    histogram on either event (so having the 'hist' file for either
++    event host the histogram output doesn't really make sense).  To
++    address the idea that the histogram is associated with a
++    combination of events, support is added allowing the creation of
++    'synthetic' events that are events derived from other events.
++    These synthetic events are full-fledged events just like any other
++    and can be used as such, as for instance to create the
++    'combination' histograms mentioned previously.
++
++  - A set of 'actions' can be associated with histogram entries -
++    these can be used to generate the previously mentioned synthetic
++    events, but can also be used for other purposes, such as for
++    example saving context when a 'max' latency has been hit.
++
++  - Trace events don't have a 'timestamp' associated with them, but
++    there is an implicit timestamp saved along with an event in the
++    underlying ftrace ring buffer.  This timestamp is now exposed as a
++    a synthetic field named 'common_timestamp' which can be used in
++    histograms as if it were any other event field; it isn't an actual
++    field in the trace format but rather is a synthesized value that
++    nonetheless can be used as if it were an actual field.  By default
++    it is in units of nanoseconds; appending '.usecs' to a
++    common_timestamp field changes the units to microseconds.
++
++These features are decribed in more detail in the following sections.
++
++2.2.1 Histogram Variables
++-------------------------
++
++Variables are simply named locations used for saving and retrieving
++values between matching events.  A 'matching' event is defined as an
++event that has a matching key - if a variable is saved for a histogram
++entry corresponding to that key, any subsequent event with a matching
++key can access that variable.
++
++A variable's value is normally available to any subsequent event until
++it is set to something else by a subsequent event.  The one exception
++to that rule is that any variable used in an expression is essentially
++'read-once' - once it's used by an expression in a subsequent event,
++it's reset to its 'unset' state, which means it can't be used again
++unless it's set again.  This ensures not only that an event doesn't
++use an uninitialized variable in a calculation, but that that variable
++is used only once and not for any unrelated subsequent match.
++
++The basic syntax for saving a variable is to simply prefix a unique
++variable name not corresponding to any keyword along with an '=' sign
++to any event field.
++
++Either keys or values can be saved and retrieved in this way.  This
++creates a variable named 'ts0' for a histogram entry with the key
++'next_pid':
++
++  # echo 'hist:keys=next_pid:vals=$ts0:ts0=common_timestamp ... >> \
++	event/trigger
++
++The ts0 variable can be accessed by any subsequent event having the
++same pid as 'next_pid'.
++
++Variable references are formed by prepending the variable name with
++the '$' sign.  Thus for example, the ts0 variable above would be
++referenced as '$ts0' in expressions.
++
++Because 'vals=' is used, the common_timestamp variable value above
++will also be summed as a normal histogram value would (though for a
++timestamp it makes little sense).
++
++The below shows that a key value can also be saved in the same way:
++
++  # echo 'hist:timer_pid=common_pid:key=timer_pid ...' >> event/trigger
++
++If a variable isn't a key variable or prefixed with 'vals=', the
++associated event field will be saved in a variable but won't be summed
++as a value:
++
++  # echo 'hist:keys=next_pid:ts1=common_timestamp ... >> event/trigger
++
++Multiple variables can be assigned at the same time.  The below would
++result in both ts0 and b being created as variables, with both
++common_timestamp and field1 additionally being summed as values:
++
++  # echo 'hist:keys=pid:vals=$ts0,$b:ts0=common_timestamp,b=field1 ... >> \
++	event/trigger
++
++Note that variable assignments can appear either preceding or
++following their use.  The command below behaves identically to the
++command above:
++
++  # echo 'hist:keys=pid:ts0=common_timestamp,b=field1:vals=$ts0,$b ... >> \
++	event/trigger
++
++Any number of variables not bound to a 'vals=' prefix can also be
++assigned by simply separating them with colons.  Below is the same
++thing but without the values being summed in the histogram:
++
++  # echo 'hist:keys=pid:ts0=common_timestamp:b=field1 ... >> event/trigger
++
++Variables set as above can be referenced and used in expressions on
++another event.
++
++For example, here's how a latency can be calculated:
++
++  # echo 'hist:keys=pid,prio:ts0=common_timestamp ... >> event1/trigger
++  # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp-$ts0 ... >> event2/trigger
++
++In the first line above, the event's timetamp is saved into the
++variable ts0.  In the next line, ts0 is subtracted from the second
++event's timestamp to produce the latency, which is then assigned into
++yet another variable, 'wakeup_lat'.  The hist trigger below in turn
++makes use of the wakeup_lat variable to compute a combined latency
++using the same key and variable from yet another event:
++
++  # echo 'hist:key=pid:wakeupswitch_lat=$wakeup_lat+$switchtime_lat ... >> event3/trigger
++
++2.2.2 Synthetic Events
++----------------------
++
++Synthetic events are user-defined events generated from hist trigger
++variables or fields associated with one or more other events.  Their
++purpose is to provide a mechanism for displaying data spanning
++multiple events consistent with the existing and already familiar
++usage for normal events.
++
++To define a synthetic event, the user writes a simple specification
++consisting of the name of the new event along with one or more
++variables and their types, which can be any valid field type,
++separated by semicolons, to the tracing/synthetic_events file.
++
++For instance, the following creates a new event named 'wakeup_latency'
++with 3 fields: lat, pid, and prio.  Each of those fields is simply a
++variable reference to a variable on another event:
++
++  # echo 'wakeup_latency \
++          u64 lat; \
++          pid_t pid; \
++	  int prio' >> \
++	  /sys/kernel/debug/tracing/synthetic_events
++
++Reading the tracing/synthetic_events file lists all the currently
++defined synthetic events, in this case the event defined above:
++
++  # cat /sys/kernel/debug/tracing/synthetic_events
++    wakeup_latency u64 lat; pid_t pid; int prio
++
++An existing synthetic event definition can be removed by prepending
++the command that defined it with a '!':
++
++  # echo '!wakeup_latency u64 lat pid_t pid int prio' >> \
++    /sys/kernel/debug/tracing/synthetic_events
++
++At this point, there isn't yet an actual 'wakeup_latency' event
++instantiated in the event subsytem - for this to happen, a 'hist
++trigger action' needs to be instantiated and bound to actual fields
++and variables defined on other events (see Section 6.3.3 below).
++
++Once that is done, an event instance is created, and a histogram can
++be defined using it:
++
++  # echo 'hist:keys=pid,prio,lat.log2:sort=pid,lat' >> \
++        /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/trigger
++
++The new event is created under the tracing/events/synthetic/ directory
++and looks and behaves just like any other event:
++
++  # ls /sys/kernel/debug/tracing/events/synthetic/wakeup_latency
++        enable  filter  format  hist  id  trigger
++
++Like any other event, once a histogram is enabled for the event, the
++output can be displayed by reading the event's 'hist' file.
++
++2.2.3 Hist trigger 'actions'
++----------------------------
++
++A hist trigger 'action' is a function that's executed whenever a
++histogram entry is added or updated.
++
++The default 'action' if no special function is explicity specified is
++as it always has been, to simply update the set of values associated
++with an entry.  Some applications, however, may want to perform
++additional actions at that point, such as generate another event, or
++compare and save a maximum.
++
++The following additional actions are available.  To specify an action
++for a given event, simply specify the action between colons in the
++hist trigger specification.
++
++  - onmatch(matching.event).<synthetic_event_name>(param list)
++
++    The 'onmatch(matching.event).<synthetic_event_name>(params)' hist
++    trigger action is invoked whenever an event matches and the
++    histogram entry would be added or updated.  It causes the named
++    synthetic event to be generated with the values given in the
++    'param list'.  The result is the generation of a synthetic event
++    that consists of the values contained in those variables at the
++    time the invoking event was hit.
++
++    The 'param list' consists of one or more parameters which may be
++    either variables or fields defined on either the 'matching.event'
++    or the target event.  The variables or fields specified in the
++    param list may be either fully-qualified or unqualified.  If a
++    variable is specified as unqualified, it must be unique between
++    the two events.  A field name used as a param can be unqualified
++    if it refers to the target event, but must be fully qualified if
++    it refers to the matching event.  A fully-qualified name is of the
++    form 'system.event_name.$var_name' or 'system.event_name.field'.
++
++    The 'matching.event' specification is simply the fully qualified
++    event name of the event that matches the target event for the
++    onmatch() functionality, in the form 'system.event_name'.
++
++    Finally, the number and type of variables/fields in the 'param
++    list' must match the number and types of the fields in the
++    synthetic event being generated.
++
++    As an example the below defines a simple synthetic event and uses
++    a variable defined on the sched_wakeup_new event as a parameter
++    when invoking the synthetic event.  Here we define the synthetic
++    event:
++
++    # echo 'wakeup_new_test pid_t pid' >> \
++           /sys/kernel/debug/tracing/synthetic_events
++
++    # cat /sys/kernel/debug/tracing/synthetic_events
++          wakeup_new_test pid_t pid
++
++    The following hist trigger both defines the missing testpid
++    variable and specifies an onmatch() action that generates a
++    wakeup_new_test synthetic event whenever a sched_wakeup_new event
++    occurs, which because of the 'if comm == "cyclictest"' filter only
++    happens when the executable is cyclictest:
++
++    # echo 'hist:keys=$testpid:testpid=pid:onmatch(sched.sched_wakeup_new).\
++            wakeup_new_test($testpid) if comm=="cyclictest"' >> \
++            /sys/kernel/debug/tracing/events/sched/sched_wakeup_new/trigger
++
++    Creating and displaying a histogram based on those events is now
++    just a matter of using the fields and new synthetic event in the
++    tracing/events/synthetic directory, as usual:
++
++    # echo 'hist:keys=pid:sort=pid' >> \
++           /sys/kernel/debug/tracing/events/synthetic/wakeup_new_test/trigger
++
++    Running 'cyclictest' should cause wakeup_new events to generate
++    wakeup_new_test synthetic events which should result in histogram
++    output in the wakeup_new_test event's hist file:
++
++    # cat /sys/kernel/debug/tracing/events/synthetic/wakeup_new_test/hist
++
++    A more typical usage would be to use two events to calculate a
++    latency.  The following example uses a set of hist triggers to
++    produce a 'wakeup_latency' histogram:
++
++    First, we define a 'wakeup_latency' synthetic event:
++
++    # echo 'wakeup_latency u64 lat; pid_t pid; int prio' >> \
++            /sys/kernel/debug/tracing/synthetic_events
++
++    Next, we specify that whenever we see a sched_waking event for a
++    cyclictest thread, save the timestamp in a 'ts0' variable:
++
++    # echo 'hist:keys=$saved_pid:saved_pid=pid:ts0=common_timestamp.usecs \
++            if comm=="cyclictest"' >> \
++	    /sys/kernel/debug/tracing/events/sched/sched_waking/trigger
++
++    Then, when the corresponding thread is actually scheduled onto the
++    CPU by a sched_switch event, calculate the latency and use that
++    along with another variable and an event field to generate a
++    wakeup_latency synthetic event:
++
++    # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0:\
++            onmatch(sched.sched_waking).wakeup_latency($wakeup_lat,\
++	            $saved_pid,next_prio) if next_comm=="cyclictest"' >> \
++	    /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
++
++    We also need to create a histogram on the wakeup_latency synthetic
++    event in order to aggregate the generated synthetic event data:
++
++    # echo 'hist:keys=pid,prio,lat:sort=pid,lat' >> \
++            /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/trigger
++
++    Finally, once we've run cyclictest to actually generate some
++    events, we can see the output by looking at the wakeup_latency
++    synthetic event's hist file:
++
++    # cat /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/hist
++
++  - onmax(var).save(field,..	.)
++
++    The 'onmax(var).save(field,...)' hist trigger action is invoked
++    whenever the value of 'var' associated with a histogram entry
++    exceeds the current maximum contained in that variable.
++
++    The end result is that the trace event fields specified as the
++    onmax.save() params will be saved if 'var' exceeds the current
++    maximum for that hist trigger entry.  This allows context from the
++    event that exhibited the new maximum to be saved for later
++    reference.  When the histogram is displayed, additional fields
++    displaying the saved values will be printed.
++
++    As an example the below defines a couple of hist triggers, one for
++    sched_waking and another for sched_switch, keyed on pid.  Whenever
++    a sched_waking occurs, the timestamp is saved in the entry
++    corresponding to the current pid, and when the scheduler switches
++    back to that pid, the timestamp difference is calculated.  If the
++    resulting latency, stored in wakeup_lat, exceeds the current
++    maximum latency, the values specified in the save() fields are
++    recoreded:
++
++    # echo 'hist:keys=pid:ts0=common_timestamp.usecs \
++            if comm=="cyclictest"' >> \
++            /sys/kernel/debug/tracing/events/sched/sched_waking/trigger
++
++    # echo 'hist:keys=next_pid:\
++            wakeup_lat=common_timestamp.usecs-$ts0:\
++            onmax($wakeup_lat).save(next_comm,prev_pid,prev_prio,prev_comm) \
++            if next_comm=="cyclictest"' >> \
++            /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
++
++    When the histogram is displayed, the max value and the saved
++    values corresponding to the max are displayed following the rest
++    of the fields:
++
++    # cat /sys/kernel/debug/tracing/events/sched/sched_switch/hist
++      { next_pid:       2255 } hitcount:        239
++        common_timestamp-ts0:          0
++        max:         27
++	next_comm: cyclictest
++        prev_pid:          0  prev_prio:        120  prev_comm: swapper/1
++
++      { next_pid:       2256 } hitcount:       2355
++        common_timestamp-ts0: 0
++        max:         49  next_comm: cyclictest
++        prev_pid:          0  prev_prio:        120  prev_comm: swapper/0
++
++      Totals:
++          Hits: 12970
++          Entries: 2
++          Dropped: 0
+-- 
+2.19.0
+
diff --git a/patches/1780-tracing-Make-tracing_set_clock-non-static.patch b/patches/1780-tracing-Make-tracing_set_clock-non-static.patch
new file mode 100644
index 00000000000000..b5ee59ef978aec
--- /dev/null
+++ b/patches/1780-tracing-Make-tracing_set_clock-non-static.patch
@@ -0,0 +1,52 @@
+From 032809b958e27166572f5960846e339214b59a2c Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:07 -0600
+Subject: [PATCH 1780/1795] tracing: Make tracing_set_clock() non-static
+
+Allow tracing code outside of trace.c to access tracing_set_clock().
+
+Some applications may require a particular clock in order to function
+properly, such as latency calculations.
+
+Also, add an accessor returning the current clock string.
+
+Link: http://lkml.kernel.org/r/6d1c53e9ee2163f54e1849f5376573f54f0e6009.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit d71bd34d78bb78b9e6f8a0be3952d5fa470a260a)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace.c | 2 +-
+ kernel/trace/trace.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index 101addc0f4ea..952a3a6a8d51 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -6227,7 +6227,7 @@ static int tracing_clock_show(struct seq_file *m, void *v)
+ 	return 0;
+ }
+ 
+-static int tracing_set_clock(struct trace_array *tr, const char *clockstr)
++int tracing_set_clock(struct trace_array *tr, const char *clockstr)
+ {
+ 	int i;
+ 
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 5975d5f5c4bc..0b8af849dc75 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -289,6 +289,7 @@ extern int trace_array_get(struct trace_array *tr);
+ extern void trace_array_put(struct trace_array *tr);
+ 
+ extern int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs);
++extern int tracing_set_clock(struct trace_array *tr, const char *clockstr);
+ 
+ extern bool trace_clock_in_ns(struct trace_array *tr);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1781-tracing-Add-a-clock-attribute-for-hist-triggers.patch b/patches/1781-tracing-Add-a-clock-attribute-for-hist-triggers.patch
new file mode 100644
index 00000000000000..3ec0b4f24fec8f
--- /dev/null
+++ b/patches/1781-tracing-Add-a-clock-attribute-for-hist-triggers.patch
@@ -0,0 +1,146 @@
+From a81209c4f617b02a7045f693592a5633675b7943 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Mon, 15 Jan 2018 20:52:08 -0600
+Subject: [PATCH 1781/1795] tracing: Add a clock attribute for hist triggers
+
+The default clock if timestamps are used in a histogram is "global".
+If timestamps aren't used, the clock is irrelevant.
+
+Use the "clock=" param only if you want to override the default
+"global" clock for a histogram with timestamps.
+
+Link: http://lkml.kernel.org/r/427bed1389c5d22aa40c3e0683e30cc3d151e260.1516069914.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Rajvi Jingar <rajvi.jingar@intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit a4072fe85ba3671720cab0788291af953db27318)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ Documentation/trace/histogram.txt | 11 +++++++-
+ kernel/trace/trace_events_hist.c  | 42 ++++++++++++++++++++++++++++---
+ 2 files changed, 49 insertions(+), 4 deletions(-)
+
+diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
+index df08882d091c..6e05510afc28 100644
+--- a/Documentation/trace/histogram.txt
++++ b/Documentation/trace/histogram.txt
+@@ -1671,7 +1671,16 @@ features have been added to the hist trigger support:
+     it is in units of nanoseconds; appending '.usecs' to a
+     common_timestamp field changes the units to microseconds.
+ 
+-These features are decribed in more detail in the following sections.
++A note on inter-event timestamps: If common_timestamp is used in a
++histogram, the trace buffer is automatically switched over to using
++absolute timestamps and the "global" trace clock, in order to avoid
++bogus timestamp differences with other clocks that aren't coherent
++across CPUs.  This can be overridden by specifying one of the other
++trace clocks instead, using the "clock=XXX" hist trigger attribute,
++where XXX is any of the clocks listed in the tracing/trace_clock
++pseudo-file.
++
++These features are described in more detail in the following sections.
+ 
+ 2.2.1 Histogram Variables
+ -------------------------
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 8719b0ea672f..f7d0da20c5c8 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -242,6 +242,7 @@ struct hist_trigger_attrs {
+ 	char		*vals_str;
+ 	char		*sort_key_str;
+ 	char		*name;
++	char		*clock;
+ 	bool		pause;
+ 	bool		cont;
+ 	bool		clear;
+@@ -1776,6 +1777,7 @@ static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
+ 	kfree(attrs->sort_key_str);
+ 	kfree(attrs->keys_str);
+ 	kfree(attrs->vals_str);
++	kfree(attrs->clock);
+ 	kfree(attrs);
+ }
+ 
+@@ -1831,6 +1833,19 @@ static int parse_assignment(char *str, struct hist_trigger_attrs *attrs)
+ 			ret = -ENOMEM;
+ 			goto out;
+ 		}
++	} else if (strncmp(str, "clock=", strlen("clock=")) == 0) {
++		strsep(&str, "=");
++		if (!str) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		str = strstrip(str);
++		attrs->clock = kstrdup(str, GFP_KERNEL);
++		if (!attrs->clock) {
++			ret = -ENOMEM;
++			goto out;
++		}
+ 	} else if (strncmp(str, "size=", strlen("size=")) == 0) {
+ 		int map_bits = parse_map_size(str);
+ 
+@@ -1895,6 +1910,14 @@ static struct hist_trigger_attrs *parse_hist_trigger_attrs(char *trigger_str)
+ 		goto free;
+ 	}
+ 
++	if (!attrs->clock) {
++		attrs->clock = kstrdup("global", GFP_KERNEL);
++		if (!attrs->clock) {
++			ret = -ENOMEM;
++			goto free;
++		}
++	}
++
+ 	return attrs;
+  free:
+ 	destroy_hist_trigger_attrs(attrs);
+@@ -4934,6 +4957,8 @@ static int event_hist_trigger_print(struct seq_file *m,
+ 			seq_puts(m, ".descending");
+ 	}
+ 	seq_printf(m, ":size=%u", (1 << hist_data->map->map_bits));
++	if (hist_data->enable_timestamps)
++		seq_printf(m, ":clock=%s", hist_data->attrs->clock);
+ 
+ 	print_actions_spec(m, hist_data);
+ 
+@@ -5201,7 +5226,6 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 		data->paused = true;
+ 
+ 	if (named_data) {
+-		destroy_hist_data(data->private_data);
+ 		data->private_data = named_data->private_data;
+ 		set_named_trigger_data(data, named_data);
+ 		data->ops = &event_hist_trigger_named_ops;
+@@ -5213,10 +5237,22 @@ static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
+ 			goto out;
+ 	}
+ 
+-	ret++;
++	if (hist_data->enable_timestamps) {
++		char *clock = hist_data->attrs->clock;
++
++		ret = tracing_set_clock(file->tr, hist_data->attrs->clock);
++		if (ret) {
++			hist_err("Couldn't set trace_clock: ", clock);
++			goto out;
++		}
+ 
+-	if (hist_data->enable_timestamps)
+ 		tracing_set_time_stamp_abs(file->tr, true);
++	}
++
++	if (named_data)
++		destroy_hist_data(hist_data);
++
++	ret++;
+  out:
+ 	return ret;
+ }
+-- 
+2.19.0
+
diff --git a/patches/1782-ring-buffer-Add-nesting-for-adding-events-within-eve.patch b/patches/1782-ring-buffer-Add-nesting-for-adding-events-within-eve.patch
new file mode 100644
index 00000000000000..a784d068148872
--- /dev/null
+++ b/patches/1782-ring-buffer-Add-nesting-for-adding-events-within-eve.patch
@@ -0,0 +1,128 @@
+From f4d52627764ace111263b1f8fa1177a65588a65f Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Wed, 7 Feb 2018 17:26:32 -0500
+Subject: [PATCH 1782/1795] ring-buffer: Add nesting for adding events within
+ events
+
+The ring-buffer code has recusion protection in case tracing ends up tracing
+itself, the ring-buffer will detect that it was called at the same context
+(normal, softirq, interrupt or NMI), and not continue to record the event.
+
+With the histogram synthetic events, they are called while tracing another
+event at the same context. The recusion protection triggers because it
+detects tracing at the same context and stops it.
+
+Add ring_buffer_nest_start() and ring_buffer_nest_end() that will notify the
+ring buffer that a trace is about to happen within another trace and that it
+is intended, and not to trigger the recursion blocking.
+
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 8e012066fe0de5ff5be606836f9075511bce5604)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ include/linux/ring_buffer.h |  3 ++
+ kernel/trace/ring_buffer.c  | 57 +++++++++++++++++++++++++++++++++++--
+ 2 files changed, 57 insertions(+), 3 deletions(-)
+
+diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
+index 6c2a6b3f3c6d..abce5f5325e1 100644
+--- a/include/linux/ring_buffer.h
++++ b/include/linux/ring_buffer.h
+@@ -117,6 +117,9 @@ int ring_buffer_unlock_commit(struct ring_buffer *buffer,
+ int ring_buffer_write(struct ring_buffer *buffer,
+ 		      unsigned long length, void *data);
+ 
++void ring_buffer_nest_start(struct ring_buffer *buffer);
++void ring_buffer_nest_end(struct ring_buffer *buffer);
++
+ struct ring_buffer_event *
+ ring_buffer_peek(struct ring_buffer *buffer, int cpu, u64 *ts,
+ 		 unsigned long *lost_events);
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index 45fc91559aa6..75fea9321ffb 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -477,6 +477,7 @@ struct ring_buffer_per_cpu {
+ 	struct buffer_page		*reader_page;
+ 	unsigned long			lost_events;
+ 	unsigned long			last_overrun;
++	unsigned long			nest;
+ 	local_t				entries_bytes;
+ 	local_t				entries;
+ 	local_t				overrun;
+@@ -2635,10 +2636,10 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ 		bit = pc & NMI_MASK ? RB_CTX_NMI :
+ 			pc & HARDIRQ_MASK ? RB_CTX_IRQ : RB_CTX_SOFTIRQ;
+ 
+-	if (unlikely(val & (1 << bit)))
++	if (unlikely(val & (1 << (bit + cpu_buffer->nest))))
+ 		return 1;
+ 
+-	val |= (1 << bit);
++	val |= (1 << (bit + cpu_buffer->nest));
+ 	cpu_buffer->current_context = val;
+ 
+ 	return 0;
+@@ -2647,7 +2648,57 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
+ static __always_inline void
+ trace_recursive_unlock(struct ring_buffer_per_cpu *cpu_buffer)
+ {
+-	cpu_buffer->current_context &= cpu_buffer->current_context - 1;
++	cpu_buffer->current_context &=
++		cpu_buffer->current_context - (1 << cpu_buffer->nest);
++}
++
++/* The recursive locking above uses 4 bits */
++#define NESTED_BITS 4
++
++/**
++ * ring_buffer_nest_start - Allow to trace while nested
++ * @buffer: The ring buffer to modify
++ *
++ * The ring buffer has a safty mechanism to prevent recursion.
++ * But there may be a case where a trace needs to be done while
++ * tracing something else. In this case, calling this function
++ * will allow this function to nest within a currently active
++ * ring_buffer_lock_reserve().
++ *
++ * Call this function before calling another ring_buffer_lock_reserve() and
++ * call ring_buffer_nest_end() after the nested ring_buffer_unlock_commit().
++ */
++void ring_buffer_nest_start(struct ring_buffer *buffer)
++{
++	struct ring_buffer_per_cpu *cpu_buffer;
++	int cpu;
++
++	/* Enabled by ring_buffer_nest_end() */
++	preempt_disable_notrace();
++	cpu = raw_smp_processor_id();
++	cpu_buffer = buffer->buffers[cpu];
++	/* This is the shift value for the above recusive locking */
++	cpu_buffer->nest += NESTED_BITS;
++}
++
++/**
++ * ring_buffer_nest_end - Allow to trace while nested
++ * @buffer: The ring buffer to modify
++ *
++ * Must be called after ring_buffer_nest_start() and after the
++ * ring_buffer_unlock_commit().
++ */
++void ring_buffer_nest_end(struct ring_buffer *buffer)
++{
++	struct ring_buffer_per_cpu *cpu_buffer;
++	int cpu;
++
++	/* disabled by ring_buffer_nest_start() */
++	cpu = raw_smp_processor_id();
++	cpu_buffer = buffer->buffers[cpu];
++	/* This is the shift value for the above recusive locking */
++	cpu_buffer->nest -= NESTED_BITS;
++	preempt_enable_notrace();
+ }
+ 
+ /**
+-- 
+2.19.0
+
diff --git a/patches/1783-tracing-Use-the-ring-buffer-nesting-to-allow-synthet.patch b/patches/1783-tracing-Use-the-ring-buffer-nesting-to-allow-synthet.patch
new file mode 100644
index 00000000000000..c28105159fc00a
--- /dev/null
+++ b/patches/1783-tracing-Use-the-ring-buffer-nesting-to-allow-synthet.patch
@@ -0,0 +1,61 @@
+From 24f95a38b181a938486680417ab66e7226de67dd Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Wed, 7 Feb 2018 17:29:46 -0500
+Subject: [PATCH 1783/1795] tracing: Use the ring-buffer nesting to allow
+ synthetic events to be traced
+
+Synthetic events can be done within the recording of other events. Notify
+the ring buffer via ring_buffer_nest_start() and ring_buffer_nest_end() that
+this is intended and not to block it due to its recursion protection.
+
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 4708abc6c68b41a656afb431818d5c57d7fdfd24)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index f7d0da20c5c8..4f027642ceef 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -640,6 +640,7 @@ static notrace void trace_event_raw_event_synth(void *__data,
+ 	struct trace_event_file *trace_file = __data;
+ 	struct synth_trace_event *entry;
+ 	struct trace_event_buffer fbuffer;
++	struct ring_buffer *buffer;
+ 	struct synth_event *event;
+ 	unsigned int i, n_u64;
+ 	int fields_size = 0;
+@@ -651,10 +652,17 @@ static notrace void trace_event_raw_event_synth(void *__data,
+ 
+ 	fields_size = event->n_u64 * sizeof(u64);
+ 
++	/*
++	 * Avoid ring buffer recursion detection, as this event
++	 * is being performed within another event.
++	 */
++	buffer = trace_file->tr->trace_buffer.buffer;
++	ring_buffer_nest_start(buffer);
++
+ 	entry = trace_event_buffer_reserve(&fbuffer, trace_file,
+ 					   sizeof(*entry) + fields_size);
+ 	if (!entry)
+-		return;
++		goto out;
+ 
+ 	for (i = 0, n_u64 = 0; i < event->n_fields; i++) {
+ 		if (event->fields[i]->is_string) {
+@@ -670,6 +678,8 @@ static notrace void trace_event_raw_event_synth(void *__data,
+ 	}
+ 
+ 	trace_event_buffer_commit(&fbuffer);
++out:
++	ring_buffer_nest_end(buffer);
+ }
+ 
+ static void free_synth_event_print_fmt(struct trace_event_call *call)
+-- 
+2.19.0
+
diff --git a/patches/1784-tracing-Fix-a-potential-NULL-dereference.patch b/patches/1784-tracing-Fix-a-potential-NULL-dereference.patch
new file mode 100644
index 00000000000000..599a84e4ddcdde
--- /dev/null
+++ b/patches/1784-tracing-Fix-a-potential-NULL-dereference.patch
@@ -0,0 +1,36 @@
+From 1691563a36be565713d39812eaeb708dcfd24911 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Fri, 23 Mar 2018 14:37:36 +0300
+Subject: [PATCH 1784/1795] tracing: Fix a potential NULL dereference
+
+We forgot to set the error code on this path so we return ERR_PTR(0)
+which is NULL.  It results in a NULL dereference in the caller.
+
+Link: http://lkml.kernel.org/r/20180323113735.GC28518@mwanda
+
+Fixes: 100719dcef44 ("tracing: Add simple expression support to hist triggers")
+Acked-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 5e4cf2bf6d1c198a90ccc0df5ffd8e0d4ea36b48)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 4f027642ceef..a02bc09d765a 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -2776,6 +2776,7 @@ static struct hist_field *parse_expr(struct hist_trigger_data *hist_data,
+ 		expr->fn = hist_field_plus;
+ 		break;
+ 	default:
++		ret = -EINVAL;
+ 		goto free;
+ 	}
+ 
+-- 
+2.19.0
+
diff --git a/patches/1785-tracing-Fix-display-of-hist-trigger-expressions-cont.patch b/patches/1785-tracing-Fix-display-of-hist-trigger-expressions-cont.patch
new file mode 100644
index 00000000000000..c6961fbc360114
--- /dev/null
+++ b/patches/1785-tracing-Fix-display-of-hist-trigger-expressions-cont.patch
@@ -0,0 +1,87 @@
+From 014f6dc0b3e164425bc948470b023b0fb1ec58da Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Wed, 28 Mar 2018 15:10:53 -0500
+Subject: [PATCH 1785/1795] tracing: Fix display of hist trigger expressions
+ containing timestamps
+
+When displaying hist triggers, variable references that have the
+timestamp field flag set are erroneously displayed as common_timestamp
+rather than the variable reference.  Additionally, timestamp
+expressions are displayed in the same way.  Fix this by forcing the
+timestamp flag handling to follow variable reference and expression
+handling.
+
+Before:
+
+  # cat /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  hist:keys=next_pid:vals=hitcount:wakeup_lat=common_timestamp.usecs:...
+
+After:
+
+  # cat /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  hist:keys=next_pid:vals=hitcount:wakeup_lat=common_timestamp.usecs-$ts0.usecs:...
+
+Link: http://lkml.kernel.org/r/92746b06be67499c2a6217bd55395b350ad18fad.1522256721.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 0ae7961e75c3fe3383796323d5342cbda8f82536)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 19 +++++--------------
+ 1 file changed, 5 insertions(+), 14 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index a02bc09d765a..4f4792f4c83f 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -1686,8 +1686,6 @@ static const char *hist_field_name(struct hist_field *field,
+ 	else if (field->flags & HIST_FIELD_FL_LOG2 ||
+ 		 field->flags & HIST_FIELD_FL_ALIAS)
+ 		field_name = hist_field_name(field->operands[0], ++level);
+-	else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
+-		field_name = "common_timestamp";
+ 	else if (field->flags & HIST_FIELD_FL_CPU)
+ 		field_name = "cpu";
+ 	else if (field->flags & HIST_FIELD_FL_EXPR ||
+@@ -1703,7 +1701,8 @@ static const char *hist_field_name(struct hist_field *field,
+ 			field_name = full_name;
+ 		} else
+ 			field_name = field->name;
+-	}
++	} else if (field->flags & HIST_FIELD_FL_TIMESTAMP)
++		field_name = "common_timestamp";
+ 
+ 	if (field_name == NULL)
+ 		field_name = "";
+@@ -4858,23 +4857,15 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ 	if (hist_field->var.name)
+ 		seq_printf(m, "%s=", hist_field->var.name);
+ 
+-	if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
+-		seq_puts(m, "common_timestamp");
+-	else if (hist_field->flags & HIST_FIELD_FL_CPU)
++	if (hist_field->flags & HIST_FIELD_FL_CPU)
+ 		seq_puts(m, "cpu");
+ 	else if (field_name) {
+ 		if (hist_field->flags & HIST_FIELD_FL_VAR_REF ||
+ 		    hist_field->flags & HIST_FIELD_FL_ALIAS)
+ 			seq_putc(m, '$');
+ 		seq_printf(m, "%s", field_name);
+-	}
+-
+-	if (hist_field->flags) {
+-		const char *flags_str = get_hist_field_flags(hist_field);
+-
+-		if (flags_str)
+-			seq_printf(m, ".%s", flags_str);
+-	}
++	} else if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
++		seq_puts(m, "common_timestamp");
+ }
+ 
+ static int event_hist_trigger_print(struct seq_file *m,
+-- 
+2.19.0
+
diff --git a/patches/1786-tracing-Don-t-add-flag-strings-when-displaying-varia.patch b/patches/1786-tracing-Don-t-add-flag-strings-when-displaying-varia.patch
new file mode 100644
index 00000000000000..6204acd89872f2
--- /dev/null
+++ b/patches/1786-tracing-Don-t-add-flag-strings-when-displaying-varia.patch
@@ -0,0 +1,45 @@
+From 5de139eba902db71a738b78441a39a5f8a594fdd Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Wed, 28 Mar 2018 15:10:54 -0500
+Subject: [PATCH 1786/1795] tracing: Don't add flag strings when displaying
+ variable references
+
+Variable references should never have flags appended when displayed -
+prevent that from happening.
+
+Before:
+
+  # cat /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  hist:keys=next_pid:vals=hitcount:wakeup_lat=common_timestamp.usecs-$ts0.usecs:...
+
+After:
+
+  hist:keys=next_pid:vals=hitcount:wakeup_lat=common_timestamp.usecs-$ts0:...
+
+Link: http://lkml.kernel.org/r/913318a5610ef6b24af2522575f671fa6ee19b6b.1522256721.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 76690945f59e2f329f148e1266d9d13800629463)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 4f4792f4c83f..d867502a56ba 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -2052,7 +2052,7 @@ static void expr_field_str(struct hist_field *field, char *expr)
+ 
+ 	strcat(expr, hist_field_name(field, 0));
+ 
+-	if (field->flags) {
++	if (field->flags && !(field->flags & HIST_FIELD_FL_VAR_REF)) {
+ 		const char *flags_str = get_hist_field_flags(field);
+ 
+ 		if (flags_str) {
+-- 
+2.19.0
+
diff --git a/patches/1787-tracing-Add-action-comparisons-when-testing-matching.patch b/patches/1787-tracing-Add-action-comparisons-when-testing-matching.patch
new file mode 100644
index 00000000000000..6efe998df6c28b
--- /dev/null
+++ b/patches/1787-tracing-Add-action-comparisons-when-testing-matching.patch
@@ -0,0 +1,125 @@
+From 351de5a22676f480141ad0ee84acbaaf6f563b4f Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Wed, 28 Mar 2018 15:10:55 -0500
+Subject: [PATCH 1787/1795] tracing: Add action comparisons when testing
+ matching hist triggers
+
+Actions also need to be considered when checking for matching triggers
+- triggers differing only by action should be allowed, but currently
+aren't because the matching check ignores the action and erroneously
+returns -EEXIST.
+
+Add and call an actions_match() function to address that.
+
+Here's an example using onmatch() actions.  The first -EEXIST shouldn't
+occur because the onmatch() is different in the second wakeup_latency()
+param.  The second -EEXIST shouldn't occur because it's a different
+action (in this case, it doesn't have an action, so shouldn't be seen
+as being the same and therefore rejected).
+
+In the after case, both are correctly accepted (and trying to add one of
+them again returns -EEXIST as it should).
+
+before:
+
+  # echo 'wakeup_latency u64 lat; pid_t pid' >> /sys/kernel/debug/tracing/synthetic_events
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs if comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0 if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  # echo 'hist:keys=next_pid:onmatch(sched.sched_wakeup).wakeup_latency(sched.sched_switch.$wakeup_lat,next_pid) if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  # echo 'hist:keys=next_pid:onmatch(sched.sched_wakeup).wakeup_latency(sched.sched_switch.$wakeup_lat,prev_pid) if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+-su: echo: write error: File exists
+  # echo 'hist:keys=next_pid if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+-su: echo: write error: File exists
+
+after:
+
+  # echo 'wakeup_latency u64 lat; pid_t pid' >> /sys/kernel/debug/tracing/synthetic_events
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs if comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0 if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  # echo 'hist:keys=next_pid:onmatch(sched.sched_wakeup).wakeup_latency(sched.sched_switch.$wakeup_lat,next_pid) if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  # echo 'hist:keys=next_pid:onmatch(sched.sched_wakeup).wakeup_latency(sched.sched_switch.$wakeup_lat,prev_pid) if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  # echo 'hist:keys=next_pid if next_comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+Link: http://lkml.kernel.org/r/a7fd668b87ec10736c8f016ac4279c8480d50c2b.1522256721.git.tom.zanussi@linux.intel.com
+
+Tested-by: Masami Hiramatsu <mhiramat@kernel.org>
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 48f794731e4ca7b83b8b22a48bfc8641fa77dd09)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 50 ++++++++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index d867502a56ba..6114939f065a 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -4364,6 +4364,53 @@ static void print_onmatch_spec(struct seq_file *m,
+ 	seq_puts(m, ")");
+ }
+ 
++static bool actions_match(struct hist_trigger_data *hist_data,
++			  struct hist_trigger_data *hist_data_test)
++{
++	unsigned int i, j;
++
++	if (hist_data->n_actions != hist_data_test->n_actions)
++		return false;
++
++	for (i = 0; i < hist_data->n_actions; i++) {
++		struct action_data *data = hist_data->actions[i];
++		struct action_data *data_test = hist_data_test->actions[i];
++
++		if (data->fn != data_test->fn)
++			return false;
++
++		if (data->n_params != data_test->n_params)
++			return false;
++
++		for (j = 0; j < data->n_params; j++) {
++			if (strcmp(data->params[j], data_test->params[j]) != 0)
++				return false;
++		}
++
++		if (data->fn == action_trace) {
++			if (strcmp(data->onmatch.synth_event_name,
++				   data_test->onmatch.synth_event_name) != 0)
++				return false;
++			if (strcmp(data->onmatch.match_event_system,
++				   data_test->onmatch.match_event_system) != 0)
++				return false;
++			if (strcmp(data->onmatch.match_event,
++				   data_test->onmatch.match_event) != 0)
++				return false;
++		} else if (data->fn == onmax_save) {
++			if (strcmp(data->onmax.var_str,
++				   data_test->onmax.var_str) != 0)
++				return false;
++			if (strcmp(data->onmax.fn_name,
++				   data_test->onmax.fn_name) != 0)
++				return false;
++		}
++	}
++
++	return true;
++}
++
++
+ static void print_actions_spec(struct seq_file *m,
+ 			       struct hist_trigger_data *hist_data)
+ {
+@@ -5174,6 +5221,9 @@ static bool hist_trigger_match(struct event_trigger_data *data,
+ 	    (strcmp(data->filter_str, data_test->filter_str) != 0))
+ 		return false;
+ 
++	if (!actions_match(hist_data, hist_data_test))
++		return false;
++
+ 	return true;
+ }
+ 
+-- 
+2.19.0
+
diff --git a/patches/1788-tracing-Make-sure-variable-string-fields-are-NULL-te.patch b/patches/1788-tracing-Make-sure-variable-string-fields-are-NULL-te.patch
new file mode 100644
index 00000000000000..57df0a03cb092c
--- /dev/null
+++ b/patches/1788-tracing-Make-sure-variable-string-fields-are-NULL-te.patch
@@ -0,0 +1,47 @@
+From 6cc5c2d96a226e42bcefbb443923960247dc2270 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Wed, 28 Mar 2018 15:10:56 -0500
+Subject: [PATCH 1788/1795] tracing: Make sure variable string fields are
+ NULL-terminated
+
+The strncpy() currently being used for variable string fields can
+result in a lack of termination if the string length is equal to the
+field size.  Use the safer strscpy() instead, which will guarantee
+termination.
+
+Link: http://lkml.kernel.org/r/fb97c1e518fb358c12a4057d7445ba2c46956cd7.1522256721.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit ad452870c66e05819a99b491b500a13989a1c502)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 6114939f065a..15ea11c29a51 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -669,7 +669,7 @@ static notrace void trace_event_raw_event_synth(void *__data,
+ 			char *str_val = (char *)(long)var_ref_vals[var_ref_idx + i];
+ 			char *str_field = (char *)&entry->fields[n_u64];
+ 
+-			strncpy(str_field, str_val, STR_VAR_LEN_MAX);
++			strscpy(str_field, str_val, STR_VAR_LEN_MAX);
+ 			n_u64 += STR_VAR_LEN_MAX / sizeof(u64);
+ 		} else {
+ 			entry->fields[n_u64] = var_ref_vals[var_ref_idx + i];
+@@ -3091,7 +3091,7 @@ static inline void __update_field_vars(struct tracing_map_elt *elt,
+ 			char *str = elt_data->field_var_str[j++];
+ 			char *val_str = (char *)(uintptr_t)var_val;
+ 
+-			strncpy(str, val_str, STR_VAR_LEN_MAX);
++			strscpy(str, val_str, STR_VAR_LEN_MAX);
+ 			var_val = (u64)(uintptr_t)str;
+ 		}
+ 		tracing_map_set_var(elt, var_idx, var_val);
+-- 
+2.19.0
+
diff --git a/patches/1789-tracing-Uninitialized-variable-in-create_tracing_map.patch b/patches/1789-tracing-Uninitialized-variable-in-create_tracing_map.patch
new file mode 100644
index 00000000000000..1e1462753631e5
--- /dev/null
+++ b/patches/1789-tracing-Uninitialized-variable-in-create_tracing_map.patch
@@ -0,0 +1,40 @@
+From 50b5c3c8be0cee58a5855d7ebdd211d2692ad8a6 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Wed, 28 Mar 2018 14:48:15 +0300
+Subject: [PATCH 1789/1795] tracing: Uninitialized variable in
+ create_tracing_map_fields()
+
+Smatch complains that idx can be used uninitialized when we check if
+(idx < 0).  It has to be the first iteration through the loop and the
+HIST_FIELD_FL_STACKTRACE bit has to be clear and the HIST_FIELD_FL_VAR
+bit has to be set to reach the bug.
+
+Link: http://lkml.kernel.org/r/20180328114815.GC29050@mwanda
+
+Fixes: 30350d65ac56 ("tracing: Add variable support to hist triggers")
+Acked-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit b28d7b2dc27f0eef1ae608b49d6860f2463910f1)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 15ea11c29a51..0d7b3ffbecc2 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -4458,7 +4458,7 @@ static int create_tracing_map_fields(struct hist_trigger_data *hist_data)
+ 	struct tracing_map *map = hist_data->map;
+ 	struct ftrace_event_field *field;
+ 	struct hist_field *hist_field;
+-	int i, idx;
++	int i, idx = 0;
+ 
+ 	for_each_hist_field(i, hist_data) {
+ 		hist_field = hist_data->fields[i];
+-- 
+2.19.0
+
diff --git a/patches/1790-tracing-Restore-proper-field-flag-printing-when-disp.patch b/patches/1790-tracing-Restore-proper-field-flag-printing-when-disp.patch
new file mode 100644
index 00000000000000..35abc1643db293
--- /dev/null
+++ b/patches/1790-tracing-Restore-proper-field-flag-printing-when-disp.patch
@@ -0,0 +1,69 @@
+From dff1664d32c425be8d25027a3c53a2a0a895fb3a Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Thu, 26 Apr 2018 20:04:47 -0500
+Subject: [PATCH 1790/1795] tracing: Restore proper field flag printing when
+ displaying triggers
+
+The flag-printing code used when displaying hist triggers somehow got
+dropped during refactoring of the inter-event patchset.  This restores
+it.
+
+Below are a couple examples - in the first case, .usecs wasn't being
+displayed properly for common_timestamps and the second illustrates
+the same for other flags such as .execname.
+
+Before:
+
+  # echo 'hist:key=common_pid.execname:val=count:sort=count' > /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+  # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+  hist:keys=common_pid:vals=hitcount,count:sort=count:size=2048 [active]
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs if comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  hist:keys=pid:vals=hitcount:ts0=common_timestamp:sort=hitcount:size=2048:clock=global if comm=="cyclictest" [active]
+
+After:
+
+  # echo 'hist:key=common_pid.execname:val=count:sort=count' > /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+  # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+  hist:keys=common_pid.execname:vals=hitcount,count:sort=count:size=2048 [active]
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs if comm=="cyclictest"' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  hist:keys=pid:vals=hitcount:ts0=common_timestamp.usecs:sort=hitcount:size=2048:clock=global if comm=="cyclictest" [active]
+
+Link: http://lkml.kernel.org/r/492bab42ff21806600af98a8ea901af10efbee0c.1524790601.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 608940dabe1bd2ce4c97524004ec86637cf80f2c)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 0d7b3ffbecc2..66c87be4ebb2 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -4913,6 +4913,16 @@ static void hist_field_print(struct seq_file *m, struct hist_field *hist_field)
+ 		seq_printf(m, "%s", field_name);
+ 	} else if (hist_field->flags & HIST_FIELD_FL_TIMESTAMP)
+ 		seq_puts(m, "common_timestamp");
++
++	if (hist_field->flags) {
++		if (!(hist_field->flags & HIST_FIELD_FL_VAR_REF) &&
++		    !(hist_field->flags & HIST_FIELD_FL_EXPR)) {
++			const char *flags = get_hist_field_flags(hist_field);
++
++			if (flags)
++				seq_printf(m, ".%s", flags);
++		}
++	}
+ }
+ 
+ static int event_hist_trigger_print(struct seq_file *m,
+-- 
+2.19.0
+
diff --git a/patches/1791-tracing-Add-field-parsing-hist-error-for-hist-trigge.patch b/patches/1791-tracing-Add-field-parsing-hist-error-for-hist-trigge.patch
new file mode 100644
index 00000000000000..d1127b2d2dc30f
--- /dev/null
+++ b/patches/1791-tracing-Add-field-parsing-hist-error-for-hist-trigge.patch
@@ -0,0 +1,54 @@
+From 4e87ade7a2d9c753bf5c65e4a5b969695fefd1f2 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Thu, 26 Apr 2018 20:04:48 -0500
+Subject: [PATCH 1791/1795] tracing: Add field parsing hist error for hist
+ triggers
+
+If the user specifies a nonexistent field for a hist trigger, the
+current code correctly flags that as an error, but doesn't tell the
+user what happened.
+
+Fix this by invoking hist_err() with an appropriate message when
+nonexistent fields are specified.
+
+Before:
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  -su: echo: write error: Invalid argument
+  # cat /sys/kernel/debug/tracing/events/sched/sched_switch/hist
+
+After:
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.usecs' >> /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+  -su: echo: write error: Invalid argument
+  # cat /sys/kernel/debug/tracing/events/sched/sched_switch/hist
+  ERROR: Couldn't find field: pid
+    Last command: keys=pid:ts0=common_timestamp.usecs
+
+Link: http://lkml.kernel.org/r/fdc8746969d16906120f162b99dd71c741e0b62c.1524790601.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Reported-by: Masami Hiramatsu <mhiramat@kernel.org>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 5ec432d7bf9dd3b4a2b84f8974e3adb71f45fb1d)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index 66c87be4ebb2..f231fa2a3dcd 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -2481,6 +2481,7 @@ parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
+ 	else {
+ 		field = trace_find_event_field(file->event_call, field_name);
+ 		if (!field || !field->size) {
++			hist_err("Couldn't find field: ", field_name);
+ 			field = ERR_PTR(-EINVAL);
+ 			goto out;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/1792-tracing-Add-field-modifier-parsing-hist-error-for-hi.patch b/patches/1792-tracing-Add-field-modifier-parsing-hist-error-for-hi.patch
new file mode 100644
index 00000000000000..ac2f8276fa36d2
--- /dev/null
+++ b/patches/1792-tracing-Add-field-modifier-parsing-hist-error-for-hi.patch
@@ -0,0 +1,53 @@
+From 55443a9304a873513df075e97895a9bdc04a1be2 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@linux.intel.com>
+Date: Thu, 26 Apr 2018 20:04:49 -0500
+Subject: [PATCH 1792/1795] tracing: Add field modifier parsing hist error for
+ hist triggers
+
+If the user specifies an invalid field modifier for a hist trigger,
+the current code correctly flags that as an error, but doesn't tell
+the user what happened.
+
+Fix this by invoking hist_err() with an appropriate message when
+invalid modifiers are specified.
+
+Before:
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.junkusecs' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  -su: echo: write error: Invalid argument
+  # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/hist
+
+After:
+
+  # echo 'hist:keys=pid:ts0=common_timestamp.junkusecs' >> /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+  -su: echo: write error: Invalid argument
+  # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/hist
+  ERROR: Invalid field modifier: junkusecs
+    Last command: keys=pid:ts0=common_timestamp.junkusecs
+
+Link: http://lkml.kernel.org/r/b043c59fa79acd06a5f14a1d44dee9e5a3cd1248.1524790601.git.tom.zanussi@linux.intel.com
+
+Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit dcf234577cd31fa16874e828b90659166ad6b80d)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index f231fa2a3dcd..b9061ed59bbd 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -2466,6 +2466,7 @@ parse_field(struct hist_trigger_data *hist_data, struct trace_event_file *file,
+ 		else if (strcmp(modifier, "usecs") == 0)
+ 			*flags |= HIST_FIELD_FL_TIMESTAMP_USECS;
+ 		else {
++			hist_err("Invalid field modifier: ", modifier);
+ 			field = ERR_PTR(-EINVAL);
+ 			goto out;
+ 		}
+-- 
+2.19.0
+
diff --git a/patches/1793-tracing-Add-__find_event_file-to-find-event-files-wi.patch b/patches/1793-tracing-Add-__find_event_file-to-find-event-files-wi.patch
new file mode 100644
index 00000000000000..ebf1dd1fd6882e
--- /dev/null
+++ b/patches/1793-tracing-Add-__find_event_file-to-find-event-files-wi.patch
@@ -0,0 +1,91 @@
+From 0b1f600ab3f1cfe3c0d1e0a6eeb5356ea51da3ac Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Tue, 8 May 2018 15:06:38 -0400
+Subject: [PATCH 1793/1795] tracing: Add __find_event_file() to find event
+ files without restrictions
+
+By adding the function __find_event_file() that can search for files without
+restrictions, such as if the event associated with the file has a reg
+function, or if it has the "ignore" flag set, the files that are associated
+to ftrace internal events (like trace_marker and function events) can be
+found and used.
+
+find_event_file() still returns a "filtered" file, as most callers need a
+valid trace event file. One created by the trace_events.h macros and not one
+created for parsing ftrace specific events.
+
+Reviewed-by: Namhyung Kim <namhyung@kernel.org>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 3c96529c0739959e2aa235d44e47f5c68c1e40de)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace.h        |  3 +++
+ kernel/trace/trace_events.c | 22 +++++++++++++++++-----
+ 2 files changed, 20 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
+index 0b8af849dc75..267ffa24e866 100644
+--- a/kernel/trace/trace.h
++++ b/kernel/trace/trace.h
+@@ -1461,6 +1461,9 @@ extern void trace_event_enable_tgid_record(bool enable);
+ extern int event_trace_add_tracer(struct dentry *parent, struct trace_array *tr);
+ extern int event_trace_del_tracer(struct trace_array *tr);
+ 
++extern struct trace_event_file *__find_event_file(struct trace_array *tr,
++						  const char *system,
++						  const char *event);
+ extern struct trace_event_file *find_event_file(struct trace_array *tr,
+ 						const char *system,
+ 						const char *event);
+diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
+index d53268a4e167..4076f143acda 100644
+--- a/kernel/trace/trace_events.c
++++ b/kernel/trace/trace_events.c
+@@ -2475,8 +2475,9 @@ __trace_add_event_dirs(struct trace_array *tr)
+ 	}
+ }
+ 
++/* Returns any file that matches the system and event */
+ struct trace_event_file *
+-find_event_file(struct trace_array *tr, const char *system,  const char *event)
++__find_event_file(struct trace_array *tr, const char *system, const char *event)
+ {
+ 	struct trace_event_file *file;
+ 	struct trace_event_call *call;
+@@ -2487,10 +2488,7 @@ find_event_file(struct trace_array *tr, const char *system,  const char *event)
+ 		call = file->event_call;
+ 		name = trace_event_name(call);
+ 
+-		if (!name || !call->class || !call->class->reg)
+-			continue;
+-
+-		if (call->flags & TRACE_EVENT_FL_IGNORE_ENABLE)
++		if (!name || !call->class)
+ 			continue;
+ 
+ 		if (strcmp(event, name) == 0 &&
+@@ -2500,6 +2498,20 @@ find_event_file(struct trace_array *tr, const char *system,  const char *event)
+ 	return NULL;
+ }
+ 
++/* Returns valid trace event files that match system and event */
++struct trace_event_file *
++find_event_file(struct trace_array *tr, const char *system, const char *event)
++{
++	struct trace_event_file *file;
++
++	file = __find_event_file(tr, system, event);
++	if (!file || !file->event_call->class->reg ||
++	    file->event_call->flags & TRACE_EVENT_FL_IGNORE_ENABLE)
++		return NULL;
++
++	return file;
++}
++
+ #ifdef CONFIG_DYNAMIC_FTRACE
+ 
+ /* Avoid typos */
+-- 
+2.19.0
+
diff --git a/patches/1794-tracing-Allow-histogram-triggers-to-access-ftrace-in.patch b/patches/1794-tracing-Allow-histogram-triggers-to-access-ftrace-in.patch
new file mode 100644
index 00000000000000..07159e9ea54697
--- /dev/null
+++ b/patches/1794-tracing-Allow-histogram-triggers-to-access-ftrace-in.patch
@@ -0,0 +1,36 @@
+From a63ab34a41a1128305cfa737309dc34a26a4a373 Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Thu, 10 May 2018 12:42:10 -0400
+Subject: [PATCH 1794/1795] tracing: Allow histogram triggers to access ftrace
+ internal events
+
+Now that trace_marker can have triggers, including a histogram triggers, the
+onmatch() and onmax() access the trace event. To do so, the search routine
+to find the event file needs to use the raw __find_event_file() that does
+not filter out ftrace events.
+
+Reviewed-by: Namhyung Kim <namhyung@kernel.org>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 3be4c1e52aa5a917aacb1c3829c2d89096b30230)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace_events_hist.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
+index b9061ed59bbd..046c716a6536 100644
+--- a/kernel/trace/trace_events_hist.c
++++ b/kernel/trace/trace_events_hist.c
+@@ -2865,7 +2865,7 @@ static struct trace_event_file *event_file(struct trace_array *tr,
+ {
+ 	struct trace_event_file *file;
+ 
+-	file = find_event_file(tr, system, event_name);
++	file = __find_event_file(tr, system, event_name);
+ 	if (!file)
+ 		return ERR_PTR(-EINVAL);
+ 
+-- 
+2.19.0
+
diff --git a/patches/1795-tracing-Fix-code-comments-in-trace.c.patch b/patches/1795-tracing-Fix-code-comments-in-trace.c.patch
new file mode 100644
index 00000000000000..2d83949a71457d
--- /dev/null
+++ b/patches/1795-tracing-Fix-code-comments-in-trace.c.patch
@@ -0,0 +1,70 @@
+From 5e0addee631183fc060c2d8d7728a8bd7cc20e72 Mon Sep 17 00:00:00 2001
+From: Chunyu Hu <chuhu@redhat.com>
+Date: Thu, 19 Oct 2017 14:32:33 +0800
+Subject: [PATCH 1795/1795] tracing: Fix code comments in trace.c
+
+Naming in code comments for tracing_snapshot, tracing_snapshot_alloc
+and trace_pid_filter_add_remove_task don't match the real function
+names.  And latency_trace has been removed from tracing directory.
+Fix them.
+
+Link: http://lkml.kernel.org/r/1508394753-20887-1-git-send-email-chuhu@redhat.com
+
+Fixes: cab5037 ("tracing/ftrace: Enable snapshot function trigger")
+Fixes: 886b5b7 ("tracing: remove /debug/tracing/latency_trace")
+Signed-off-by: Chunyu Hu <chuhu@redhat.com>
+[ Replaced /sys/kernel/debug/tracing with /sys/kerne/tracing ]
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+(cherry picked from commit 5a93bae2c382c588f437ce0395e8032ae287dc36)
+Signed-off-by: Hirotaka MOTAI <Motai.Hirotaka@aj.MitsubishiElectric.co.jp>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+---
+ kernel/trace/trace.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index 952a3a6a8d51..651e181436e6 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -362,7 +362,7 @@ trace_ignore_this_task(struct trace_pid_list *filtered_pids, struct task_struct
+ }
+ 
+ /**
+- * trace_pid_filter_add_remove - Add or remove a task from a pid_list
++ * trace_pid_filter_add_remove_task - Add or remove a task from a pid_list
+  * @pid_list: The list to modify
+  * @self: The current task for fork or NULL for exit
+  * @task: The task to add or remove
+@@ -925,7 +925,7 @@ void tracing_snapshot_instance(struct trace_array *tr)
+ }
+ 
+ /**
+- * trace_snapshot - take a snapshot of the current buffer.
++ * tracing_snapshot - take a snapshot of the current buffer.
+  *
+  * This causes a swap between the snapshot buffer and the current live
+  * tracing buffer. You can use this to take snapshots of the live
+@@ -1004,9 +1004,9 @@ int tracing_alloc_snapshot(void)
+ EXPORT_SYMBOL_GPL(tracing_alloc_snapshot);
+ 
+ /**
+- * trace_snapshot_alloc - allocate and take a snapshot of the current buffer.
++ * tracing_snapshot_alloc - allocate and take a snapshot of the current buffer.
+  *
+- * This is similar to trace_snapshot(), but it will allocate the
++ * This is similar to tracing_snapshot(), but it will allocate the
+  * snapshot buffer if it isn't already allocated. Use this only
+  * where it is safe to sleep, as the allocation may sleep.
+  *
+@@ -1311,7 +1311,7 @@ unsigned long __read_mostly	tracing_thresh;
+ /*
+  * Copy the new maximum trace into the separate maximum-trace
+  * structure. (this way the maximum trace is permanently saved,
+- * for later retrieval via /sys/kernel/debug/tracing/latency_trace)
++ * for later retrieval via /sys/kernel/tracing/tracing_max_latency)
+  */
+ static void
+ __update_max_tr(struct trace_array *tr, struct task_struct *tsk, int cpu)
+-- 
+2.19.0
+
diff --git a/series b/series
index 51efefb250c5a3..db5a933717c228 100644
--- a/series
+++ b/series
@@ -17,3 +17,1806 @@ patches.ltsi/ltsi-makefile-addition.patch
 #
 
 
+#############################################################################
+# Patches!
+#
+# All lumped together at the moment, no need to break things out just yet as no
+# one ever looks here...
+#
+patches/0001-drm-bridge-adv7511-Properly-update-EDID-when-no-EDID.patch
+patches/0002-drm-bridge-adv7511-Remove-private-copy-of-the-EDID.patch
+patches/0003-drm-bridge-adv7511-Enable-connector-polling-when-no-.patch
+patches/0004-drm-bridge-adv7511-Constify-HDMI-CODEC-platform-data.patch
+patches/0005-drm-adv7511-33-add-HDMI-CEC-support.patch
+patches/0006-drm-bridge-adv7511-Fix-a-use-after-free.patch
+patches/0007-drm-bridge-adv7511-33-Fix-adv7511_cec_init-failure-h.patch
+patches/0008-arm_arch_timer-Expose-event-stream-status.patch
+patches/0009-dt-bindings-display-renesas-dw-hdmi-Drop-bogus-node-.patch
+patches/0010-drm-bridge-synopsys-dw-hdmi-Enable-cec-clock.patch
+patches/0011-ASoC-fsi-Use-of_device_get_match_data-helper.patch
+patches/0012-arm64-defconfig-Enable-Renesas-R8A77995-SoC.patch
+patches/0013-ARM-shmobile-Document-R-Car-V3M-SoC-DT-bindings.patch
+patches/0014-arm64-dts-renesas-r8a7795-es1-Drop-extra-zero-from-u.patch
+patches/0015-arm64-dts-renesas-r8a7796-Add-FDP1-instance.patch
+patches/0016-arm64-dts-renesas-r8a77995-update-PFC-node-name-to-p.patch
+patches/0017-arm64-dts-renesas-ulcb-Enable-display-output.patch
+patches/0018-arm64-dts-renesas-r8a7795-Drop-bogus-HDMI-node-names.patch
+patches/0019-arm64-dts-renesas-r8a77995-Use-r8a7795-sysc-binding-.patch
+patches/0020-arm64-dts-renesas-r8a77995-Use-r8a7795-cpg-mssr-bind.patch
+patches/0021-arm64-dts-renesas-r8a77995-add-GPIO-device-nodes.patch
+patches/0022-arm64-dts-renesas-r8a77995-Add-EthernetAVB-device-no.patch
+patches/0023-arm64-dts-renesas-initial-R8A77970-SoC-device-tree.patch
+patches/0024-arm64-dts-renesas-r8a77970-add-SYS-DMAC-support.patch
+patches/0025-arm64-dts-renesas-r8a77970-add-H-SCIF-support.patch
+patches/0026-arm64-dts-renesas-r8a77970-add-EtherAVB-support.patch
+patches/0027-arm64-dts-draak-Add-serial-console-pins.patch
+patches/0028-arm64-defconfig-enable-thermal-driver-for-Renesas-R-.patch
+patches/0029-arm64-defconfig-enable-the-Marvell-10G-PHY-as-a-modu.patch
+patches/0030-arm64-defconfig-enable-Marvell-CP110-comphy.patch
+patches/0031-arm-shmobile-Document-Kingfisher-board-DT-bindings.patch
+patches/0032-arm64-dts-renesas-r8a77995-Add-USB2.0-PHY-device-nod.patch
+patches/0033-arm64-dts-renesas-r8a77995-add-USB2.0-Host-EHCI-OHCI.patch
+patches/0034-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-PHY.patch
+patches/0035-arm64-renesas-document-Eagle-board-bindings.patch
+patches/0036-arm64-dts-renesas-r8a77995-draak-enable-USB2.0-Host-.patch
+patches/0037-ARM-shmobile-remove-inconsistent-from-documentation.patch
+patches/0038-arm64-dts-renesas-r8a77995-draak-enable-EthernetAVB.patch
+patches/0039-arm64-dts-renesas-r8a7795-add-USB3.0-peripheral-devi.patch
+patches/0040-arm64-dts-renesas-r8a7796-add-USB3.0-peripheral-devi.patch
+patches/0041-arm64-defconfig-enable-R8A77970-SoC.patch
+patches/0042-arm64-defconfig-enable-NAND-on-Armada-7K-8K-SoCs.patch
+patches/0043-arm64-dts-renesas-salvator-common-drop-avb_phy_int-f.patch
+patches/0044-arm64-dts-renesas-ulcb-drop-avb_phy_int-from-avb_pin.patch
+patches/0045-arm64-dts-renesas-r8a77995-draak-drop-avb_phy_int-fr.patch
+patches/0046-arm64-dts-renesas-initial-Eagle-board-device-tree.patch
+patches/0047-arm64-dts-renesas-salvator-common-add-pfc-node-for-U.patch
+patches/0048-arm64-dts-renesas-r8a77995-add-PWM-device-nodes.patch
+patches/0049-arm64-dts-renesas-r8a77995-draak-enable-PWM-channel-.patch
+patches/0050-arm64-dts-ulcb-kf-initial-device-tree.patch
+patches/0051-arm64-dts-m3ulcb-kf-initial-device-tree.patch
+patches/0052-arm64-dts-h3ulcb-kf-ES1.x-SoC-initial-device-tree.patch
+patches/0053-arm64-dts-h3ulcb-kf-ES2.0-SoC-initial-device-tree.patch
+patches/0054-arm64-dts-ulcb-kf-enable-SCIF1.patch
+patches/0055-arm64-dts-ulcb-kf-enable-CAN0-1.patch
+patches/0056-arm64-dts-ulcb-kf-enable-HSUSB.patch
+patches/0057-arm64-dts-ulcb-kf-enable-USB2.0-Host-channel-0.patch
+patches/0058-arm64-dts-ulcb-kf-enable-PCIE0-1.patch
+patches/0059-arm64-dts-ulcb-kf-enable-USB3.0-Host.patch
+patches/0060-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C2.patch
+patches/0061-arm64-dts-ulcb-kf-enable-TCA9539-on-I2C4.patch
+patches/0062-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C2.patch
+patches/0063-arm64-dts-ulcb-kf-enable-PCA9548-on-I2C4.patch
+patches/0064-arm64-dts-ulcb-kf-hog-USB3-hub-control-gpios.patch
+patches/0065-arm64-dts-r8a7796-Add-INTC-EX-device-node.patch
+patches/0066-arm64-dts-r8a77970-Add-INTC-EX-device-node.patch
+patches/0067-arm64-dts-r8a77995-Add-INTC-EX-device-node.patch
+patches/0068-arm64-dts-renesas-eagle-add-EtherAVB-support.patch
+patches/0069-arm64-defconfig-Enable-hisilicon-hibmc-drm-driver.patch
+patches/0070-arm64-defconfig-Enable-QCOM_IOMMU.patch
+patches/0071-arm64-defconfig-enable-RTC-on-Armada-7K-8K-SoCs.patch
+patches/0072-arm64-renesas-salvator-common-fixup-audio_clkout.patch
+patches/0073-arm64-renesas-ulcb-fixup-audio_clkout.patch
+patches/0074-arm64-dts-r8a7795-Use-R-Car-GPIO-Gen3-fallback-compa.patch
+patches/0075-arm64-dts-r8a7796-Use-R-Car-GPIO-Gen3-fallback-compa.patch
+patches/0076-arm64-defconfig-re-enable-Qualcomm-DB410c-USB.patch
+patches/0077-arm64-defconfig-Enable-Tegra-PCI-controller.patch
+patches/0078-arm64-Add-ThunderX-drivers-to-defconfig.patch
+patches/0079-arm64-dts-renesas-salvator-common-add-dr_mode-proper.patch
+patches/0080-arm64-defconfig-enable-CONFIG_GPIO_UNIPHIER.patch
+patches/0081-kbuild-clean-up-.dtb-and-.dtb.S-patterns-from-top-le.patch
+patches/0082-arm64-dts-renesas-salvator-x-Remove-renesas-no-ether.patch
+patches/0083-pinctrl-gpio-Unify-namespace-for-cross-calls.patch
+patches/0084-Input-gpio-keys-convert-timers-to-use-timer_setup.patch
+patches/0085-gpio-rcar-Use-of_device_get_match_data-helper.patch
+patches/0086-gpio-rcar-document-R8A77970-bindings.patch
+patches/0087-gpio-rcar-use-devm_ioremap_resource.patch
+patches/0088-gpio-rcar-Add-r8a77995-R-Car-D3-support.patch
+patches/0089-i2c-rcar-document-R8A77970-bindings.patch
+patches/0090-i2c-riic-remove-clock-and-frequency-restrictions.patch
+patches/0091-i2c-sh_mobile-Use-of_device_get_match_data-helper.patch
+patches/0092-iommu-io-pgtable-arm-Convert-to-IOMMU-API-TLB-sync.patch
+patches/0093-dt-bindings-iommu-ipmmu-vmsa-Use-generic-node-name.patch
+patches/0094-iommu-ipmmu-vmsa-Fix-return-value-check-in-ipmmu_fin.patch
+patches/0095-iommu-ipmmu-vmsa-Unify-domain-alloc-free.patch
+patches/0096-iommu-ipmmu-vmsa-Simplify-group-allocation.patch
+patches/0097-iommu-ipmmu-vmsa-Clean-up-struct-ipmmu_vmsa_iommu_pr.patch
+patches/0098-iommu-ipmmu-vmsa-Unify-ipmmu_ops.patch
+patches/0099-iommu-ipmmu-vmsa-Introduce-features-break-out-alias.patch
+patches/0100-iommu-ipmmu-vmsa-Add-optional-root-device-feature.patch
+patches/0101-iommu-ipmmu-vmsa-Enable-multi-context-support.patch
+patches/0102-iommu-ipmmu-vmsa-Make-use-of-IOMMU_OF_DECLARE.patch
+patches/0103-iommu-ipmmu-vmsa-IPMMU-device-is-40-bit-bus-master.patch
+patches/0104-iommu-ipmmu-vmsa-Write-IMCTR-twice.patch
+patches/0105-iommu-ipmmu-vmsa-Make-IMBUSCTR-setup-optional.patch
+patches/0106-iommu-ipmmu-vmsa-Allow-two-bit-SL0.patch
+patches/0107-iommu-ipmmu-vmsa-Hook-up-r8a7795-DT-matching-code.patch
+patches/0108-irqchip-gic-Deal-with-broken-firmware-exposing-only-.patch
+patches/0109-KVM-arm-arm64-Check-that-system-supports-split-eoi-d.patch
+patches/0110-irqchip-renesas-intc-irqpin-Use-of_device_get_match_.patch
+patches/0111-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-W.patch
+patches/0112-mtd-spi-nor-Add-support-for-mr25h128.patch
+patches/0113-net-phy-micrel-check-return-code-in-flp-center-funct.patch
+patches/0114-phy-rcar-gen2-Add-r8a7743-5-support.patch
+patches/0115-phy-rcar-gen3-usb2-select-USB_COMMON.patch
+patches/0116-extcon-Split-out-extcon-header-file-for-consumer-and.patch
+patches/0117-phy-rcar-gen3-usb2-check-dr_mode-for-otg-mode.patch
+patches/0118-phy-rcar-gen3-usb2-use-enum-phy_mode-in-the-role_sto.patch
+patches/0119-phy-rcar-gen3-usb2-add-SoC-specific-parameter-for-de.patch
+patches/0120-phy-rcar-gen3-usb2-add-binding-for-r8a77995.patch
+patches/0121-dt-bindings-pwm-Add-R-Car-D3-device-tree-bindings.patch
+patches/0122-ravb-document-R8A77970-bindings.patch
+patches/0123-dt-bindings-net-renesas-ravb-Add-support-for-R8A7799.patch
+patches/0124-ravb-RX-checksum-offload.patch
+patches/0125-ravb-Consolidate-clock-handling.patch
+patches/0126-Revert-ravb-add-workaround-for-clock-when-resuming-w.patch
+patches/0127-drm-rcar-du-Use-drm_gem_fb_create.patch
+patches/0128-media-drivers-remove-from-non-kernel-doc-comments.patch
+patches/0129-thermal-rcar_gen3_thermal-fix-initialization-sequenc.patch
+patches/0130-iio-adc-drop-assign-iio_info.driver_module-and-iio_t.patch
+patches/0131-iio-adc-rcar-gyroadc-Cast-pointer-to-uintptr_t-to-fi.patch
+patches/0132-iio-adc-rcar-gyroadc-Use-of_device_get_match_data-he.patch
+patches/0133-media-rcar_jpu-fix-two-kernel-doc-markups.patch
+patches/0134-soc-renesas-rcar-rst-add-R8A77970-support.patch
+patches/0135-ASoC-rsnd-add-rsnd_dma_alloc.patch
+patches/0136-ASoC-rcar-skip-disabled-SSI-nodes.patch
+patches/0137-ASoC-rsnd-add-generic-rsnd_flags_xxx-macro.patch
+patches/0138-ASoC-rsnd-use-generic-rsnd_flags_xxx-macro-on-ADG.patch
+patches/0139-ASoC-rsnd-DVC-kctrl-sets-once.patch
+patches/0140-ASoC-rsnd-CTU-kctrl-sets-once.patch
+patches/0141-ASoC-rsnd-makes-volume-ramp-rate-list-generic.patch
+patches/0142-ASoC-rsnd-add-MIX-Volume-Ramp-support.patch
+patches/0143-ASoC-rsnd-add-rsnd_kctrl_xxx-macro.patch
+patches/0144-ASoC-rsnd-more-clear-ADG-clock-debug-info.patch
+patches/0145-ASoC-rsnd-don-t-use-io-mod-directly.patch
+patches/0146-ASoC-rsnd-tidyup-rsnd_mod_next-for-loop-method.patch
+patches/0147-ASoC-rsnd-NULL-check-is-not-needed-for-clk_unprepare.patch
+patches/0148-ASoC-rsnd-use-snd_pcm_running-in-rsnd_io_is_working.patch
+patches/0149-ASoC-rsnd-Don-t-check-SSISR-DIRQ-when-Capture.patch
+patches/0150-ASoC-rsnd-remove-NULL-check-from-rsnd_mod_name-rsnd_.patch
+patches/0151-ASoC-rsnd-return-EIO-if-rsnd_dmaen_request_channel-f.patch
+patches/0152-ASoC-rcar-revert-IOMMU-support-so-far.patch
+patches/0153-ASoC-rsnd-ssiu-clear-SSI_MODE-for-non-TDM-Extended-m.patch
+patches/0154-dt-bindings-mmc-renesas_sdhi-provide-example-in-bind.patch
+patches/0155-dt-bindings-mmc-renesas_sdhi-add-R-Car-Gen-123-fallb.patch
+patches/0156-mmc-renesas_sdhi-implement-R-Car-Gen-123-fallback-co.patch
+patches/0157-mmc-tmio-Use-common-error-handling-code-in-tmio_mmc_.patch
+patches/0158-mmc-tmio-Replace-msleep-of-20ms-or-less-with-usleep_.patch
+patches/0159-soc-renesas-identify-R-Car-V3M.patch
+patches/0160-spi-rspi-Add-r8a7743-5-to-the-compatible-list.patch
+patches/0161-spi-rspi-Use-of_device_get_match_data-helper.patch
+patches/0162-spi-rspi-Do-not-set-SPCR_SPE-in-qspi_set_config_regi.patch
+patches/0163-pinctrl-rza1-Add-support-for-RZ-A1L.patch
+patches/0164-dt-bindings-pinctrl-Add-support-for-RZ-A1M-and-RZ-A1.patch
+patches/0165-ata-sata_rcar-Use-of_device_get_match_data-helper.patch
+patches/0166-tty-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
+patches/0167-tty-serial-Remove-redundant-license-text.patch
+patches/0168-clocksource-drivers-sh_cmt-Use-0x3f-mask-for-SH_CMT_.patch
+patches/0169-clocksource-drivers-sh_cmt-Support-separate-R-Car-Ge.patch
+patches/0170-clocksource-drivers-sh_cmt-Remove-support-for-renesa.patch
+patches/0171-clocksource-drivers-sh_cmt-Mark-renesas-cmt-48-gen2-.patch
+patches/0172-clocksource-drivers-sh_cmt-Remove-unused-renesas-cha.patch
+patches/0173-clocksource-drivers-sh_cmt-Use-of_device_get_match_d.patch
+patches/0174-sh-make-dma_cache_sync-a-no-op.patch
+patches/0175-dt-bindings-net-sh_eth-add-R-Car-Gen-12-fallback-com.patch
+patches/0176-net-sh_eth-rename-name-structures-as-rcar_gen-12-_.patch
+patches/0177-net-sh_eth-implement-R-Car-Gen-12-fallback-compatibi.patch
+patches/0178-net-sh_eth-use-correct-struct-device-when-calling-DM.patch
+patches/0179-net-sh_eth-don-t-use-NULL-as-struct-device-for-the-D.patch
+patches/0180-net-sh_eth-do-not-advertise-Gigabit-capabilities-whe.patch
+patches/0181-sh_eth-fix-TXALCR1-offsets.patch
+patches/0182-sh_eth-fix-dumping-ARSTR.patch
+patches/0183-mtd-nand-sh_flctl-Use-of_device_get_match_data-helpe.patch
+patches/0184-spi-sh-msiof-Add-compatible-strings-for-r8a774-35.patch
+patches/0185-spi-sh-msiof-Add-r8a774-35-to-the-compatible-list.patch
+patches/0186-spi-sh-msiof-Use-of_device_get_match_data-helper.patch
+patches/0187-spi-sh-msiof-remove-redundant-pointer-dev.patch
+patches/0188-pinctrl-sh-pfc-r8a7795-Add-SDHI0-3-support.patch
+patches/0189-pinctrl-sh-pfc-r8a7795-Re-add-DRIF-support.patch
+patches/0190-pinctrl-sh-pfc-r8a77995-Add-EthernetAVB-pins-groups-.patch
+patches/0191-pinctrl-sh-pfc-r8a77995-Add-USB2.0-host-support.patch
+patches/0192-pinctrl-sh-pfc-r8a7795-es1-Add-USB3.0-host-support.patch
+patches/0193-pinctrl-sh-pfc-r8a7795-Add-USB3.0-host-support.patch
+patches/0194-pinctrl-sh-pfc-r8a7795-Add-Audio-clock-pin-support.patch
+patches/0195-pinctrl-sh-pfc-r8a7795-Add-Audio-SSI-pin-support.patch
+patches/0196-pinctrl-sh-pfc-r8a77995-Add-PWM-pins-groups-and-func.patch
+patches/0197-pinctrl-sh-pfc-r8a7795-Add-I2C-pin-support.patch
+patches/0198-pinctrl-sh-pfc-r8a7795-es1-Restore-sort-order.patch
+patches/0199-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch
+patches/0200-pinctrl-sh-pfc-r8a7795-Add-INTC-EX-pins-groups-and-f.patch
+patches/0201-pinctrl-sh-pfc-r8a7796-Add-support-for-INTC-EX-IRQ-p.patch
+patches/0202-pinctrl-sh-pfc-r8a7795-Add-HSCIF-pins-groups-and-fun.patch
+patches/0203-pinctrl-sh-pfc-r8a7795-Fix-trivial-typo-in-comment.patch
+patches/0204-pinctrl-sh-pfc-r8a7795-es1-Fix-trivial-typo-in-comme.patch
+patches/0205-pinctrl-sh-pfc-r8a7796-Fix-trivial-typo-in-comment.patch
+patches/0206-pinctrl-sh-pfc-r8a77995-Add-Audio-clock-pin-support.patch
+patches/0207-pinctrl-sh-pfc-r8a77995-Add-Audio-SSI-pin-support.patch
+patches/0208-pinctrl-sh-pfc-r8a77995-Remove-USB0_IDIN-and-USB0_ID.patch
+patches/0209-pinctrl-sh-pfc-r8a7745-Implement-voltage-switching-f.patch
+patches/0210-pinctrl-sh-pfc-Remove-matching-on-plain-sh-pfc-platf.patch
+patches/0211-pinctrl-sh-pfc-Drop-width-parameter-of-sh_pfc_-read-.patch
+patches/0212-pinctrl-sh-pfc-Add-generic-bias-register-description.patch
+patches/0213-pinctrl-sh-pfc-Add-sh_pfc_pin_to_bias_reg-helper.patch
+patches/0214-pinctrl-sh-pfc-r8a7795-es1-Use-generic-bias-register.patch
+patches/0215-pinctrl-sh-pfc-r8a7795-Use-generic-bias-register-des.patch
+patches/0216-pinctrl-sh-pfc-r8a7796-Use-generic-bias-register-des.patch
+patches/0217-pinctrl-sh-pfc-r8a7778-Use-generic-bias-register-des.patch
+patches/0218-pinctrl-sh-pfc-Remove-obsolete-sh_pfc_pin_to_bias_in.patch
+patches/0219-pinctrl-sh-pfc-Add-generic-IOCTRL-register-descripti.patch
+patches/0220-pinctrl-sh-pfc-r8a7795-es1-Use-generic-IOCTRL-regist.patch
+patches/0221-pinctrl-sh-pfc-r8a7795-Use-generic-IOCTRL-register-d.patch
+patches/0222-pinctrl-sh-pfc-r8a7796-Use-generic-IOCTRL-register-d.patch
+patches/0223-pinctrl-sh-pfc-Save-restore-registers-for-PSCI-syste.patch
+patches/0224-serial-sh-sci-Support-for-variable-HSCIF-hardware-RX.patch
+patches/0225-serial-sh-sci-Use-of_device_get_match_data-helper.patch
+patches/0226-serial-sh-sci-Fix-init-data-attribute-for-struct-por.patch
+patches/0227-serial-sh-sci-Fix-unlocked-access-to-SCSCR-register.patch
+patches/0228-Input-st1232-remove-obsolete-platform-device-support.patch
+patches/0229-usb-gadget-udc-renesas_usb3-move-pm_runtime_-en-dis-.patch
+patches/0230-usb-gadget-udc-renesas_usb3-Add-suspend-resume-funct.patch
+patches/0231-usb-gadget-udc-renesas_usb3-add-support-for-generic-.patch
+patches/0232-usb-gadget-udc-renesas_usb3-Use-of_device_get_match_.patch
+patches/0233-usb-gadget-udc-renesas_usb3-make-const-array-max_pac.patch
+patches/0234-USB-add-SPDX-identifiers-to-all-remaining-files-in-d.patch
+patches/0235-USB-gadget-udc-Remove-redundant-license-text.patch
+patches/0236-usb-renesas_usbhs-unify-Gen2-3-pipe_config-setting.patch
+patches/0237-usb-renesas_usbhs-add-support-for-R-Car-D3.patch
+patches/0238-usb-renesas_usbhs-Use-of_device_get_match_data-helpe.patch
+patches/0239-usb-renesas_usbhs-Add-compatible-string-for-r8a7743-.patch
+patches/0240-renesas_usbhs-use-renesas_usbhs_get_info.patch
+patches/0241-USB-renesas_usbhs-Remove-redundant-license-text.patch
+patches/0242-USB-renesas_usbhs-rcar-.h-add-SPDX-tags.patch
+patches/0243-mmc-usdhi6rol0-catch-all-errors-when-getting-regulat.patch
+patches/0244-v4l-vsp1-Use-generic-node-name.patch
+patches/0245-media-vsp1-add-a-missing-kernel-doc-parameter.patch
+patches/0246-usb-host-xhci-support-option-to-disable-the-xHCI-USB.patch
+patches/0247-xhci-add-port-speed-ID-to-portsc-tracing.patch
+patches/0248-usb-xhci-Add-debugfs-interface-for-xHCI-driver.patch
+patches/0249-usb-xhci-Fix-memory-leak-when-xhci_disable_slot-retu.patch
+patches/0250-usb-xhci-Remove-xhci-mutex-from-xhci_alloc_dev.patch
+patches/0251-usb-xhci-Handle-USB-transaction-error-on-address-com.patch
+patches/0252-usb-xhci-reduce-device-initiated-resume-time-varianc.patch
+patches/0253-xhci-allow-TRACE-to-work-with-EVENT-ring-dequeue.patch
+patches/0254-xhci-trace-slot-context-when-calling-xhci_configure_.patch
+patches/0255-usb-host-xhci-plat-Use-of_device_get_match_data-help.patch
+patches/0256-xhci-Convert-timers-to-use-timer_setup.patch
+patches/0257-usb-host-xhci-mark-expected-switch-fall-through.patch
+patches/0258-usb-host-xhci-mem-mark-expected-switch-fall-through.patch
+patches/0259-usb-host-xhci-hub-mark-expected-switch-fall-through.patch
+patches/0260-USB-host-xhci-Remove-redundant-license-text.patch
+patches/0261-xhci-Fix-xhci-debugfs-NULL-pointer-dereference-in-re.patch
+patches/0262-media-v4l-fwnode-Support-generic-parsing-of-graph-en.patch
+patches/0263-media-rcar-vin-Use-generic-parser-for-parsing-fwnode.patch
+patches/0264-of-pci-Add-of_pci_dma_range_parser_init-for-dma-rang.patch
+patches/0265-PCI-Use-of_pci_dma_range_parser_init-to-reduce-dupli.patch
+patches/0266-dt-bindings-PCI-rcar-Correct-example-to-match-realit.patch
+patches/0267-dt-bindings-clock-Add-R8A77970-CPG-core-clock-defini.patch
+patches/0268-clk-renesas-cpg-mssr-Add-R8A77970-support.patch
+patches/0269-clk-renesas-mstp-Delete-error-messages-for-failed-me.patch
+patches/0270-clk-renesas-rcar-gen2-Delete-error-message-for-faile.patch
+patches/0271-clk-renesas-r8a7795-Correct-parent-clock-of-INTC-AP.patch
+patches/0272-clk-renesas-r8a7796-Correct-parent-clock-of-INTC-AP.patch
+patches/0273-clk-renesas-r8a77995-Correct-parent-clock-of-INTC-AP.patch
+patches/0274-dt-bindings-clk-r7s72100-Add-missing-I-and-G-clocks.patch
+patches/0275-clk-renesas-rz-clk-rz-is-meant-for-RZ-A1.patch
+patches/0276-clk-renesas-cpg-mssr-Add-du1-clock-to-R8A7745.patch
+patches/0277-clk-renesas-cpg-mssr-Restore-module-clocks-during-re.patch
+patches/0278-clk-renesas-cpg-mssr-Add-support-to-restore-core-clo.patch
+patches/0279-clk-renesas-div6-Restore-clock-state-during-resume.patch
+patches/0280-clk-renesas-rcar-gen3-Restore-SDHI-clocks-during-res.patch
+patches/0281-clk-renesas-rcar-gen3-Restore-R-clock-during-resume.patch
+patches/0282-dt-bindings-power-add-R8A77970-SYSC-power-domain-def.patch
+patches/0283-soc-renesas-rcar-sysc-add-R8A77970-support.patch
+patches/0284-arm64-renesas-Add-Renesas-R8A77970-Kconfig-support.patch
+patches/0285-media-v4l-async-Remove-re-probing-support.patch
+patches/0286-media-v4l-async-Don-t-set-sd-dev-NULL-in-v4l2_async_.patch
+patches/0287-media-v4l-async-fix-unbind-error-in-v4l2_async_notif.patch
+patches/0288-media-v4l-async-Fix-notifier-complete-callback-error.patch
+patches/0289-media-v4l-async-Correctly-serialise-async-sub-device.patch
+patches/0290-media-v4l-async-Use-more-intuitive-names-for-interna.patch
+patches/0291-media-v4l-async-Move-async-subdev-notifier-operation.patch
+patches/0292-media-v4l-async-Introduce-helpers-for-calling-async-.patch
+patches/0293-media-v4l-async-Register-sub-devices-before-calling-.patch
+patches/0294-media-v4l-async-Allow-async-notifier-register-call-s.patch
+patches/0295-media-v4l-async-Prepare-for-async-sub-device-notifie.patch
+patches/0296-media-v4l-async-Allow-binding-notifiers-to-sub-devic.patch
+patches/0297-PM-Domains-Allow-genpd-users-to-specify-default-acti.patch
+patches/0298-dt-bindings-apmu-Document-r8a7745-support.patch
+patches/0299-ARM-dts-r8a7790-Convert-to-new-CPG-MSSR-bindings.patch
+patches/0300-ARM-dts-r8a7792-Convert-to-new-CPG-MSSR-bindings.patch
+patches/0301-ARM-dts-r8a7793-Convert-to-new-CPG-MSSR-bindings.patch
+patches/0302-ARM-dts-r8a7794-Convert-to-new-CPG-MSSR-bindings.patch
+patches/0303-ARM-dts-r8a7790-Stop-grouping-clocks-under-a-clocks-.patch
+patches/0304-ARM-dts-r8a7793-Stop-grouping-clocks-under-a-clocks-.patch
+patches/0305-ARM-dts-r8a7794-Stop-grouping-clocks-under-a-clocks-.patch
+patches/0306-ARM-dts-r8a7743-Add-SDHI-controllers.patch
+patches/0307-ARM-dts-iwg20m-Enable-SDHI0-controller.patch
+patches/0308-ARM-Add-definition-for-monitor-mode.patch
+patches/0309-ARM-shmobile-rcar-gen2-Make-sure-CNTVOFF-is-initiali.patch
+patches/0310-ARM-dts-iwg20d-q7-Add-SDHI1-support.patch
+patches/0311-ARM-dts-r8a7745-Add-GPIO-support.patch
+patches/0312-ARM-dts-iwg22m-Add-iWave-RZG1E-SODIMM-SOM.patch
+patches/0313-ARM-dts-iwg22d-sodimm-Add-support-for-iWave-G22D-SOD.patch
+patches/0314-ARM-dts-r8a7745-Add-I2C-DT-support.patch
+patches/0315-ARM-dts-r8a7745-Add-MMC-interface-support.patch
+patches/0316-ARM-dts-iwg22m-Add-eMMC-support.patch
+patches/0317-ARM-dts-iwg22m-Add-RTC-support.patch
+patches/0318-ARM-dts-r8a7791-Convert-to-new-CPG-MSSR-bindings.patch
+patches/0319-ARM-dts-r8a7791-Stop-grouping-clocks-under-a-clocks-.patch
+patches/0320-ARM-dts-gr-peach-Remove-empty-line.patch
+patches/0321-ARM-dts-gr-peach-Add-SCIF2-pin-group.patch
+patches/0322-ARM-dts-gr-peach-Add-user-led-device-nodes.patch
+patches/0323-ARM-dts-r8a7745-Add-Ethernet-AVB-support.patch
+patches/0324-ARM-dts-iwg20d-q7-Add-chosen-node.patch
+patches/0325-ARM-dts-iwg20d-q7-Add-RTC-support.patch
+patches/0326-ARM-dts-iwg22d-sodimm-Add-pinctl-support-for-scif4.patch
+patches/0327-ARM-dts-iwg22d-sodimm-Add-Ethernet-AVB-support.patch
+patches/0328-ARM-dts-r8a7743-Add-internal-PCI-bridge-nodes.patch
+patches/0329-ARM-dts-r8a7743-Add-USB-PHY-DT-support.patch
+patches/0330-ARM-dts-r8a7743-Link-PCI-USB-devices-to-USB-PHY.patch
+patches/0331-ARM-dts-iwg20d-q7-Enable-internal-PCI.patch
+patches/0332-ARM-dts-iwg20d-q7-Enable-USB-PHY.patch
+patches/0333-ARM-dts-alt-use-correct-logic-for-SD-WP-pins.patch
+patches/0334-ARM-dts-r8a7743-Add-IIC-cores-to-dtsi.patch
+patches/0335-ARM-dts-r8a7790-Add-reset-control-properties.patch
+patches/0336-ARM-dts-r8a7791-Add-reset-control-properties.patch
+patches/0337-ARM-dts-r8a7792-Add-reset-control-properties.patch
+patches/0338-ARM-dts-r8a7793-Add-reset-control-properties.patch
+patches/0339-ARM-dts-r8a7794-Add-reset-control-properties.patch
+patches/0340-ARM-dts-r8a7745-Add-SDHI-controllers.patch
+patches/0341-ARM-dts-iwg22m-Enable-SDHI1-controller.patch
+patches/0342-ARM-dts-r8a7743-Add-QSPI-support.patch
+patches/0343-ARM-dts-iwg20m-Add-SPI-NOR-support.patch
+patches/0344-ARM-dts-r8a7745-Add-QSPI-support.patch
+patches/0345-ARM-dts-iwg22m-Add-SPI-NOR-support.patch
+patches/0346-ARM-dts-iwg22d-Enable-SDHI0-controller.patch
+patches/0347-ARM-dts-r8a7745-Add-MSIOF-012-support.patch
+patches/0348-ARM-dts-r8a7743-Add-MSIOF-012-support.patch
+patches/0349-ARM-dts-gr-peach-Fix-leds-node-name-indent.patch
+patches/0350-ARM-dts-gr-peach-Enable-MTU2-timer-pulse-unit.patch
+patches/0351-ARM-dts-r8a7790-Use-generic-node-name-for-VSP1-nodes.patch
+patches/0352-ARM-dts-r8a7791-Use-generic-node-name-for-VSP1-nodes.patch
+patches/0353-ARM-dts-r8a7792-Use-generic-node-name-for-VSP1-nodes.patch
+patches/0354-ARM-dts-r8a7794-Use-generic-node-name-for-VSP1-nodes.patch
+patches/0355-ARM-dts-iwg20d-q7-Rework-DT-architecture.patch
+patches/0356-ARM-dts-iwg20d-q7-dbcm-ca-Add-device-trees-for-camer.patch
+patches/0357-ARM-shmobile-rcar-gen2-fix-non-SMP-build.patch
+patches/0358-ARM-dts-r8a7790-add-cpu-capacity-dmips-mhz-informati.patch
+patches/0359-ARM-dts-r8a7745-Add-internal-PCI-bridge-nodes.patch
+patches/0360-ARM-dts-r8a7745-Add-USB-PHY-DT-support.patch
+patches/0361-ARM-dts-r8a7745-Link-PCI-USB-devices-to-USB-PHY.patch
+patches/0362-ARM-dts-iwg22d-sodimm-Enable-internal-PCI.patch
+patches/0363-ARM-dts-iwg22d-sodimm-Enable-USB-PHY.patch
+patches/0364-ARM-dts-r8a7743-Add-HS-USB-device-node.patch
+patches/0365-ARM-dts-iwg20d-q7-Enable-HS-USB.patch
+patches/0366-ARM-dts-r8a7743-Add-USB-DMAC-device-nodes.patch
+patches/0367-ARM-dts-r8a7743-Enable-DMA-for-HSUSB.patch
+patches/0368-ARM-dts-gr-peach-Add-ETHER-pin-group.patch
+patches/0369-ARM-dts-gr-peach-Enable-ostm0-and-ostm1-timers.patch
+patches/0370-ARM-dts-r8a7778-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
+patches/0371-ARM-dts-r8a7779-Use-R-Car-GPIO-Gen1-fallback-compat-.patch
+patches/0372-ARM-dts-r8a7743-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0373-ARM-dts-r8a7790-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0374-ARM-dts-r8a7791-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0375-ARM-dts-r8a7792-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0376-ARM-dts-r8a7793-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0377-ARM-dts-r8a7794-Use-R-Car-GPIO-Gen2-fallback-compat-.patch
+patches/0378-ARM-dts-r8a73a4-Add-clock-for-CA15-CPU0-core.patch
+patches/0379-ARM-dts-r8a7743-Add-missing-clock-for-secondary-CA15.patch
+patches/0380-ARM-dts-r8a7778-Add-clock-for-CA9-CPU-core.patch
+patches/0381-ARM-dts-r8a7779-Add-clocks-for-CA9-CPU-cores.patch
+patches/0382-ARM-dts-r8a7790-Add-missing-clocks-for-secondary-CA1.patch
+patches/0383-ARM-dts-r8a7790-Add-clocks-for-CA7-CPU-cores.patch
+patches/0384-ARM-dts-r8a7791-Add-missing-clock-for-secondary-CA15.patch
+patches/0385-ARM-dts-r8a7792-Add-missing-clock-for-secondary-CA15.patch
+patches/0386-ARM-dts-r8a7793-Add-missing-clock-for-secondary-CA15.patch
+patches/0387-ARM-dts-r8a7794-Add-missing-clock-for-secondary-CA7-.patch
+patches/0388-ARM-dts-sh73a0-Add-clocks-for-CA9-CPU-cores.patch
+patches/0389-ARM-dts-r7s72100-Add-clock-for-CA9-CPU-core.patch
+patches/0390-ARM-dts-r8a7743-Add-xhci-support-to-SoC-dtsi.patch
+patches/0391-ARM-shmobile-pm-rmobile-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
+patches/0392-ARM-dts-r8a779x-Add-reset-cells-in-cpg-mssr.patch
+patches/0393-i2c-gpio-Convert-to-use-descriptors.patch
+patches/0394-gpio-Make-it-possible-for-consumers-to-enforce-open-.patch
+patches/0395-i2c-gpio-Enforce-open-drain-through-gpiolib.patch
+patches/0396-i2c-gpio-Augment-all-boardfiles-to-use-open-drain.patch
+patches/0397-i2c-gpio-Local-vars-in-probe.patch
+patches/0398-dt-bindings-i2c-i2c-gpio-Add-support-for-named-gpios.patch
+patches/0399-i2c-gpio-Add-support-for-named-gpios-in-DT.patch
+patches/0400-ARM-sa1100-simpad-Correct-I2C-GPIO-offsets.patch
+patches/0401-lib-dma-debug.c-fix-incorrect-pfn-calculation.patch
+patches/0402-include-linux-slab.h-add-kmalloc_array_node-and-kcal.patch
+patches/0403-gpio-pca953x-fix-vendor-prefix-for-PCA9654.patch
+patches/0404-i2c-generic-recovery-check-SCL-before-SDA.patch
+patches/0405-soc-mediatek-Use-GENPD_FLAG_ACTIVE_WAKEUP.patch
+patches/0406-soc-rockchip-power-domain-Use-GENPD_FLAG_ACTIVE_WAKE.patch
+patches/0407-PM-Domains-Remove-gpd_dev_ops.active_wakeup-callback.patch
+patches/0408-PM-runtime-Drop-children-check-from-__pm_runtime_set.patch
+patches/0409-dt-bindings-add-eeprom-size-property.patch
+patches/0410-dt-bindings-eeprom-rename-to-at24.txt.patch
+patches/0411-dt-bindings-add-eeprom-no-read-rollover-property.patch
+patches/0412-dt-bindings-at24-new-optional-property-wp-gpios.patch
+patches/0413-dt-bindings-at24-consistently-document-the-compatibl.patch
+patches/0414-dt-bindings-at24-fix-formatting-and-style.patch
+patches/0415-dt-bindings-at24-extend-the-list-of-supported-chips.patch
+patches/0416-dt-bindings-at24-sort-manufacturers-alphabetically.patch
+patches/0417-drm-drivers-drop-redundant-drm_edid_to_eld-calls.patch
+patches/0418-i2c-sh_mobile-remove-redundant-initialization.patch
+patches/0419-i2c-sh_mobile-remove-redundant-deinitialization.patch
+patches/0420-i2c-sh_mobile-manually-inline-two-short-functions.patch
+patches/0421-i2c-sh_mobile-use-direct-writes-when-accessing-ICE-b.patch
+patches/0422-i2c-sh_mobile-shorten-exit-of-xfer-routine.patch
+patches/0423-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
+patches/0424-i2c-sh_mobile-avoid-unnecessary-register-read.patch
+patches/0425-i2c-sh_mobile-send-STOP-according-to-datasheet.patch
+patches/0426-i2c-sh_mobile-make-sure-to-not-accidently-trigger-ST.patch
+patches/0427-iommu-ipmmu-vmsa-Add-r8a7796-DT-binding.patch
+patches/0428-iommu-ipmmu-vmsa-Add-r8a779-70-95-DT-bindings.patch
+patches/0429-iommu-ipmmu-vmsa-Remove-redundant-of_iommu_init_fn-h.patch
+patches/0430-dt-bindings-irqchip-renesas-irqc-Document-R-Car-M3-N.patch
+patches/0431-PCI-Remove-PCI_REASSIGN_ALL_RSRC-use-on-arm-and-arm6.patch
+patches/0432-net-phy-micrel-Use-strlcpy-for-ethtool-get_strings.patch
+patches/0433-ravb-kill-redundant-check-in-the-probe-method.patch
+patches/0434-ravb-Remove-obsolete-explicit-clock-handling-for-WoL.patch
+patches/0435-DT-net-renesas-ravb-document-R8A77980-bindings.patch
+patches/0436-dt-bindings-net-renesas-ravb-Make-stream-buffer-opti.patch
+patches/0437-dt-bindings-can-rcar_can-document-r8a774-35-can-supp.patch
+patches/0438-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch
+patches/0439-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch
+patches/0440-dmaengine-rcar-dmac-Make-DMAC-reinit-during-system-r.patch
+patches/0441-dt-bindings-display-rcar-du-Document-R8A774-35-DU.patch
+patches/0442-drm-rcar-du-Add-R8A7743-support.patch
+patches/0443-drm-rcar-du-Add-R8A7745-support.patch
+patches/0444-drm-rcar-du-Don-t-set-connector-DPMS-property.patch
+patches/0445-drm-rcar-du-Implement-system-suspend-resume-support.patch
+patches/0446-drm-rcar-du-Remove-unused-CRTC-suspend-resume-functi.patch
+patches/0447-drm-rcar-du-Share-plane-atomic-check-code-between-Ge.patch
+patches/0448-dt-bindings-thermal-rcar-Add-device-tree-support-for.patch
+patches/0449-mmc-tmio-use-usleep_range-consistently.patch
+patches/0450-dt-bindings-mmc-renesas_sdhi-Add-r8a77995-support.patch
+patches/0451-mmc-renesas_sdhi-enable-R-Car-D3-r8a77995-support.patch
+patches/0452-mmc-tmio-use-ioread-for-repeated-access-to-a-registe.patch
+patches/0453-mmc-renesas_sdhi-remove-eprobe-jump-label.patch
+patches/0454-mmc-tmio-set-tmio_mmc_host-to-driver-data.patch
+patches/0455-mmc-tmio-use-devm_ioremap_resource-instead-of-devm_i.patch
+patches/0456-mmc-tmio-move-mmc_host_ops-to-struct-tmio_mmc_host-f.patch
+patches/0457-mmc-tmio-renesas_sdhi-set-mmc_host_ops-hooks-directl.patch
+patches/0458-mmc-tmio-move-mmc_gpio_request_cd-before-mmc_add_hos.patch
+patches/0459-mmc-renesas_sdhi-remove-always-false-condition.patch
+patches/0460-mmc-tmio-renesas_sdhi-move-struct-tmio_mmc_dma-to-re.patch
+patches/0461-mmc-tmio-renesas_sdhi-move-Renesas-specific-DMA-data.patch
+patches/0462-mmc-tmio-renesas_sdhi-move-ssc_tappos-to-renesas_sdh.patch
+patches/0463-mmc-tmio-change-bus_shift-to-unsigned-int.patch
+patches/0464-mmc-tmio-use-io-accessors-consistently.patch
+patches/0465-mfd-tmio-Move-register-macros-to-tmio_core.c.patch
+patches/0466-mmc-tmio-renesas_sdhi-Remove-unneeded-NULL-check.patch
+patches/0467-mmc-tmio-use-mmc_can_gpio_cd-instead-of-checking-TMI.patch
+patches/0468-mmc-tmio-ioremap-memory-resource-in-tmio_mmc_host_al.patch
+patches/0469-mmc-tmio-move-clk_enable-disable-out-of-tmio_mmc_hos.patch
+patches/0470-mmc-tmio-move-tmio_-mmc_of_parse-to-tmio_mmc_host_al.patch
+patches/0471-mmc-tmio-remove-dma_ops-from-tmio_mmc_host_probe-arg.patch
+patches/0472-soc-renesas-Identify-R-Car-M3-W-ES1.1.patch
+patches/0473-sata_rcar-Reset-SATA-PHY-when-Salvator-X-board-resum.patch
+patches/0474-ata-sata_rcar-Remove-unused-variable-in-sata_rcar_in.patch
+patches/0475-cpufreq-Add-and-use-cpufreq_for_each_-valid_-entry_i.patch
+patches/0476-sh_eth-kill-redundant-check-in-the-probe-method.patch
+patches/0477-sh_eth-remove-sh_eth_plat_data-edmac_endian.patch
+patches/0478-sh_eth-gather-all-TSU-init-code-in-one-place.patch
+patches/0479-sh_eth-get-Ether-port-only-when-needed.patch
+patches/0480-sh_eth-Remove-obsolete-explicit-clock-handling-for-W.patch
+patches/0481-sh_eth-uninline-TSU-register-accessors.patch
+patches/0482-mmc-sh_mmcif-remove-redundant-initialization-of-opc.patch
+patches/0483-media-v4l-sh_mobile_ceu-Return-buffers-on-streamoff.patch
+patches/0484-pinctrl-sh-pfc-r8a7745-Add-CAN-01-support.patch
+patches/0485-pinctrl-sh-pfc-r8a7795-Add-CAN-support.patch
+patches/0486-pinctrl-sh-pfc-r8a7795-Add-CAN-FD-support.patch
+patches/0487-pinctrl-sh-pfc-Add-PORT_GP_CFG_-6-22-helper-macros.patch
+patches/0488-pinctrl-sh-pfc-Add-R8A77970-PFC-support.patch
+patches/0489-pinctrl-sh-pfc-r8a7794-Add-can_clk-function.patch
+patches/0490-pinctrl-sh-pfc-r8a77995-Add-missing-pins-SCL0-and-SD.patch
+patches/0491-pinctrl-sh-pfc-r8a7795-Add-GP-1-28-port-pin-support.patch
+patches/0492-pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu.patch
+patches/0493-pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu.patch
+patches/0494-pinctrl-sh-pfc-r8a7795-Rename-RTS-0-1-3-4-pin-functi.patch
+patches/0495-pinctrl-sh-pfc-r8a7796-Rename-RTS-0-1-3-4-pin-functi.patch
+patches/0496-pinctrl-sh-pfc-r8a77995-Add-CAN-support.patch
+patches/0497-pinctrl-sh-pfc-r8a77995-Add-CAN-FD-support.patch
+patches/0498-pinctrl-sh-pfc-r8a7794-Add-PWM-0123456-support.patch
+patches/0499-pinctrl-sh-pfc-r8a7794-Add-tpu-groups-and-function.patch
+patches/0500-pinctrl-sh-pfc-r8a7794-Add-i2c5-pin-groups-and-funct.patch
+patches/0501-pinctrl-sh-pfc-r8a7791-Add-tpu-groups-and-function.patch
+patches/0502-pinctrl-sh-pfc-r8a7795-Add-SATA-pins-groups-and-func.patch
+patches/0503-pinctrl-sh-pfc-r8a7795-remove-duplicate-of-CLKOUT-pi.patch
+patches/0504-treewide-Use-DEVICE_ATTR_RW.patch
+patches/0505-usb-gadget-udc-renesas_usb3-fix-oops-in-renesas_usb3.patch
+patches/0506-usb-gadget-udc-renesas_usb3-add-binging-for-r8a77965.patch
+patches/0507-usb-renesas_usbhs-remove-redundant-polling-in-usbhsf.patch
+patches/0508-usb-renesas_usbhs-add-usbhs_pipe_clear_without_seque.patch
+patches/0509-usb-renesas_usbhs-use-PIPEnCLR.ACLRM-instead-of-C-Dn.patch
+patches/0510-usb-renesas_usbhs-Add-a-function-to-write-the-UGCTRL.patch
+patches/0511-usb-renesas_usbhs-add-a-new-callback-for-extcon-noti.patch
+patches/0512-usb-renesas_usbhs-set-the-mode-by-using-extcon-state.patch
+patches/0513-usb-renesas_usbhs-add-extcon-notifier-to-set-mode-fo.patch
+patches/0514-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
+patches/0515-dt-bindings-usb-renesas_usbhs-Add-support-for-RZ-A1.patch
+patches/0516-usb-renesas_usbhs-add-binding-for-r8a77965.patch
+patches/0517-v4l-vsp1-Start-and-stop-DRM-pipeline-independently-o.patch
+patches/0518-dt-bindings-watchdog-renesas-wdt-Add-support-for-the.patch
+patches/0519-usb-xhci-remove-unused-variable-last_freed_endpoint.patch
+patches/0520-usb-xhci-remove-unused-variable-ep.patch
+patches/0521-usb-xhci-remove-unused-variable-urb_priv.patch
+patches/0522-usb-xhci-remove-unused-variable-ep_ring.patch
+patches/0523-dt-bindings-usb-xhci-Document-r8a7743-support.patch
+patches/0524-xhci-add-helper-to-allocate-command-with-input-conte.patch
+patches/0525-xhci-remove-unnecessary-boolean-parameter-from-xhci_.patch
+patches/0526-usb-xhci-Make-some-static-functions-global.patch
+patches/0527-usb-xhci-Add-DbC-support-in-xHCI-driver.patch
+patches/0528-usb-xhci-Cleanup-printk-debug-message-for-registers.patch
+patches/0529-usb-xhci-Cleanup-printk-debug-message-for-ERST.patch
+patches/0530-usb-xhci-allow-imod-interval-to-be-configurable.patch
+patches/0531-xhci-add-port-status-tracing-for-Get-Port-Status-hub.patch
+patches/0532-xhci-add-port-status-tracing-for-Get-Hub-Status-requ.patch
+patches/0533-USB-host-Use-zeroing-memory-allocator-rather-than-al.patch
+patches/0534-xhci-Don-t-print-a-warning-when-setting-link-state-f.patch
+patches/0535-xhci-Fix-xhci-debugfs-devices-node-disappearance-aft.patch
+patches/0536-xhci-xhci-debugfs-device-nodes-weren-t-removed-after.patch
+patches/0537-xhci-fix-xhci-debugfs-errors-in-xhci_stop.patch
+patches/0538-drm-Check-crtc_state-enable-rather-than-crtc-enabled.patch
+patches/0539-drm-Move-drm_plane_helper_check_state-into-drm_atomi.patch
+patches/0540-drm-rcar-du-Clip-planes-to-screen-boundaries.patch
+patches/0541-i2c-add-helpers-to-ease-DMA-handling.patch
+patches/0542-i2c-add-a-message-flag-for-DMA-safe-buffers.patch
+patches/0543-i2c-sh_mobile-use-core-helper-to-decide-when-to-use-.patch
+patches/0544-i2c-sh_mobile-move-type-detection-upwards.patch
+patches/0545-i2c-sh_mobile-allow-setup-callback-to-return-errno.patch
+patches/0546-i2c-sh_mobile-require-setup-callback.patch
+patches/0547-i2c-sh_mobile-let-RuntimePM-do-the-clock-handling.patch
+patches/0548-i2c-sh_mobile-add-helper-to-check-frequency-calculat.patch
+patches/0549-i2c-sh_mobile-add-new-frequency-calculation-for-late.patch
+patches/0550-i2c-sh_mobile-let-r8a7790-R-Car-H2-use-the-new-formu.patch
+patches/0551-mmc-slot-gpio-add-a-helper-to-check-capability-of-GP.patch
+patches/0552-mmc-tmio-refactor-.get_ro-hook.patch
+patches/0553-mmc-tmio-hide-unused-tmio_mmc_clk_disable-tmio_mmc_c.patch
+patches/0554-net-phy-Add-general-dummy-stubs-for-MMD-register-acc.patch
+patches/0555-net-phy-micrel-Use-the-general-dummy-stubs-for-MMD-r.patch
+patches/0556-ALSA-add-snd_card_disconnect_sync.patch
+patches/0557-ASoC-soc-core-add-component-lookup-functions.patch
+patches/0558-ASoC-add-snd_soc_disconnect_sync.patch
+patches/0559-ASoC-soc-core-add-missing-EXPORT_SYMBOL_GPL-for-snd_.patch
+patches/0560-ASoC-rsnd-call-snd_soc_disconnect_sync-when-remove.patch
+patches/0561-ASoC-rsnd-TDM-6ch-needs-8ch-clock-for-hw-refine.patch
+patches/0562-ASoC-rsnd-dma.c-spin-lock-is-no-longer-needed-in-IRQ.patch
+patches/0563-ASoC-rsnd-ssi-remove-unnesessary-period_pos.patch
+patches/0564-ASoC-rsnd-more-clear-rsnd_get_dalign-for-DALIGN.patch
+patches/0565-ASoC-rsnd-don-t-use-runtime-sample_bits.patch
+patches/0566-ASoC-rsnd-PIO-related-function-cleanup.patch
+patches/0567-ASoC-rsnd-remove-unneeded-is_graph-from-__rsnd_dai_p.patch
+patches/0568-ASoC-rsnd-Add-device-tree-support-for-r8a774-35.patch
+patches/0569-ASoC-rcar-tidyup-simple-card-example-for-CPU-node.patch
+patches/0570-mtd-spi-nor-add-spi_nor_init-function.patch
+patches/0571-mtd-spi-nor-add-an-API-to-restore-the-status-of-SPI-.patch
+patches/0572-mtd-m25p80-restore-the-status-of-SPI-flash-when-exit.patch
+patches/0573-tty-serial-sh-sci-Hide-number-of-ports-config-questi.patch
+patches/0574-tty-serial-sh-sci-Hide-serial-console-config-questio.patch
+patches/0575-tty-serial-sh-sci-Hide-earlycon-config-question.patch
+patches/0576-tty-serial-sh-sci-Hide-DMA-config-question.patch
+patches/0577-tty-serial-sh-sci-Add-default-for-number-of-ports-fo.patch
+patches/0578-ARM-shmobile-Document-Renesas-M3-W-based-Salvator-XS.patch
+patches/0579-arm64-dts-renesas-salvator-set-driver-type-for-eMMC.patch
+patches/0580-arm64-dts-renesas-r8a7795-Use-R-Car-SDHI-Gen3-fallba.patch
+patches/0581-arm64-dts-renesas-r8a7796-Use-R-Car-SDHI-Gen3-fallba.patch
+patches/0582-arm64-dts-renesas-r8a77970-Add-RWDT-node.patch
+patches/0583-arm64-dts-renesas-eagle-Move-avb-node-to-preserve-so.patch
+patches/0584-arm64-dts-renesas-eagle-Enable-watchdog-timer.patch
+patches/0585-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
+patches/0586-arm64-dts-renesas-r8a7796-Add-IPMMU-device-nodes.patch
+patches/0587-arm64-dts-renesas-r8a7796-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
+patches/0588-arm64-dts-renesas-r8a7796-Tie-Audio-DMAC-to-IPMMU-MP.patch
+patches/0589-arm64-dts-renesas-r8a7796-Point-FDP1-via-FCPF-to-IPM.patch
+patches/0590-arm64-dts-renesas-r8a7796-Point-VSPI-via-FCPVI-to-IP.patch
+patches/0591-arm64-dts-renesas-r8a7796-Connect-Ethernet-AVB-to-IP.patch
+patches/0592-arm64-dts-renesas-r8a7796-Enable-IPMMU-DS0-DS1-MP-VI.patch
+patches/0593-arm64-dts-renesas-ulcb-kf-enable-USB2-PHY-of-channel.patch
+patches/0594-arm64-dts-renesas-ulcb-kf-add-dr_mode-property-for-U.patch
+patches/0595-arm64-dts-renesas-r8a77995-add-SYS-DMAC-nodes.patch
+patches/0596-arm64-dts-renesas-r8a77995-Add-SDHI-MMC-support.patch
+patches/0597-arm64-dts-renesas-r8a7795-Add-IPMMU-device-nodes.patch
+patches/0598-arm64-dts-renesas-r8a7795-es1-Add-IPMMU-device-nodes.patch
+patches/0599-arm64-dts-renesas-r8a7795-Tie-SYS-DMAC-to-IPMMU-DS0-.patch
+patches/0600-arm64-dts-renesas-r8a7795-Tie-Audio-DMAC-to-IPMMU-MP.patch
+patches/0601-arm64-dts-renesas-r8a7795-Point-DU-VSPD-via-FCPVD-to.patch
+patches/0602-arm64-dts-renesas-r8a7795-es1-Point-DU-VSPD-via-FCPV.patch
+patches/0603-arm64-dts-renesas-r8a7795-Point-FDP1-via-FCPF-to-IPM.patch
+patches/0604-arm64-dts-renesas-r8a7795-es1-Point-FDP1-via-FCPF-to.patch
+patches/0605-arm64-dts-renesas-r8a7795-Point-VSPBC-VSPBD-via-FCPV.patch
+patches/0606-arm64-dts-renesas-r8a7795-Point-VSPI-via-FCPVI-to-IP.patch
+patches/0607-arm64-dts-renesas-r8a7795-es1-Point-VSPI-via-FCPVI-t.patch
+patches/0608-arm64-dts-renesas-r8a7795-Connect-Ethernet-AVB-to-IP.patch
+patches/0609-arm64-dts-renesas-r8a7795-Connect-SATA-to-IPMMU-HC.patch
+patches/0610-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-MP1.patch
+patches/0611-arm64-dts-renesas-r8a7795-Enable-IPMMU-VI0-VP1-DS0-D.patch
+patches/0612-arm64-dts-renesas-salvator-common-Add-BD9571-PMIC.patch
+patches/0613-arm64-dts-renesas-r8a7795-es1-salvator-x-Add-SoC-nam.patch
+patches/0614-arm64-dts-renesas-r8a7795-salvator-x-Add-SoC-name-to.patch
+patches/0615-arm64-dts-renesas-r8a7796-salvator-x-Add-SoC-name-to.patch
+patches/0616-arm64-dts-renesas-r8a7795-salvator-xs-Add-SoC-name-t.patch
+patches/0617-arm64-dts-renesas-r8a77995-Add-CAN-external-clock-su.patch
+patches/0618-arm64-dts-renesas-r8a77995-Add-CAN-support.patch
+patches/0619-arm64-dts-renesas-r8a77995-Add-CAN-FD-support.patch
+patches/0620-arm64-dts-renesas-r8a7795-Increase-the-number-of-GPI.patch
+patches/0621-arm64-dts-renesas-r8a77970-sort-includes.patch
+patches/0622-arm64-dts-renesas-r8a77995-add-DMA-for-SCIF2.patch
+patches/0623-arm64-dts-renesas-r8a77970-Add-IPMMU-device-nodes.patch
+patches/0624-arm64-dts-renesas-r8a77970-Tie-SYS-DMAC-to-IPMMU-DS1.patch
+patches/0625-arm64-dts-renesas-r8a77970-Connect-Ethernet-AVB-to-I.patch
+patches/0626-arm64-dts-renesas-r8a77970-Enable-IPMMU-DS1-RT-and-M.patch
+patches/0627-arm64-dts-renesas-r8a77995-Add-IPMMU-device-nodes.patch
+patches/0628-arm64-dts-renesas-r8a77995-Connect-Ethernet-AVB-to-I.patch
+patches/0629-arm64-renesas-document-V3MSK-board-bindings.patch
+patches/0630-arm64-dts-renesas-initial-V3MSK-board-device-tree.patch
+patches/0631-arm64-dts-renesas-v3msk-add-EtherAVB-support.patch
+patches/0632-arm64-dts-renesas-r8a77970-use-CPG-core-clock-macros.patch
+patches/0633-arm64-dts-renesas-r8a77970-use-SYSC-power-domain-mac.patch
+patches/0634-arm64-defconfig-enable-MUSB-HDRC-along-with-Allwinne.patch
+patches/0635-arm64-dts-renesas-r8a7795-Move-nodes-which-have-no-r.patch
+patches/0636-arm64-dts-renesas-ulcb-Add-EthernetAVB-PHY-reset.patch
+patches/0637-arm64-dts-renesas-r8a7795-sort-subnodes-of-root-node.patch
+patches/0638-arm64-dts-renesas-r8a7796-sort-subnodes-of-root-node.patch
+patches/0639-arm64-dts-renesas-r8a7796-move-nodes-which-have-no-r.patch
+patches/0640-arm64-dts-renesas-r8a7796-add-reg-properties-to-pcie.patch
+patches/0641-arm64-dts-renesas-r8a7795-add-usb3_phy-node.patch
+patches/0642-arm64-dts-renesas-r8a7796-add-usb3_phy-node.patch
+patches/0643-arm64-dts-renesas-salvator-common-enable-usb3_phy0-n.patch
+patches/0644-arm64-dts-renesas-salvator-common-enable-usb3_peri0.patch
+patches/0645-arm64-defconfig-enable-ARM_ARMADA_37XX_CPUFREQ.patch
+patches/0646-arm64-defconfig-enable-new-trigger-modes-for-leds.patch
+patches/0647-arm64-defconfig-enable-CONFIG_UNIPHIER_EFUSE.patch
+patches/0648-arm64-defconfig-remove-CONFIG_USB_EHCI_MSM.patch
+patches/0649-arm64-defconfig-remove-CONFIG_USB_MSM_OTG.patch
+patches/0650-arm64-defconfig-remove-CONFIG_USB_QCOM_8X16_PHY.patch
+patches/0651-mtd-nand-use-reworked-NAND-controller-driver-with-Ma.patch
+patches/0652-arm64-defconfig-enable-CONFIG_ACPI_APEI_MEMORY_FAILU.patch
+patches/0653-arm64-defconfig-enable-EDAC-GHES-option.patch
+patches/0654-arm64-defconfig-enable-CONFIG_ACPI_APEI_EINJ.patch
+patches/0655-soc-renesas-rcar-sysc-Keep-wakeup-sources-active-dur.patch
+patches/0656-ARM-Fix-i2c-gpio-GPIO-descriptor-tables.patch
+patches/0657-MIPS-pb44-Fix-i2c-gpio-GPIO-descriptor-table.patch
+patches/0658-i2c-gpio-initialize-SCL-to-HIGH-again.patch
+patches/0659-ARM-dts-r8a7743-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0660-ARM-dts-r8a7745-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0661-ARM-dts-r8a7778-Use-R-Car-Gen1-Ether-fallback-compat.patch
+patches/0662-ARM-dts-r8a7790-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0663-ARM-dts-r8a7791-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0664-ARM-dts-r8a7793-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0665-ARM-dts-r8a7794-Use-R-Car-Gen2-Ether-fallback-compat.patch
+patches/0666-ARM-dts-r8a7743-Add-DU-support.patch
+patches/0667-ARM-dts-iwg22d-Use-dev-ttySC3-as-debug-console.patch
+patches/0668-ARM-dts-iwg22d-Add-dev-ttySC5-support.patch
+patches/0669-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-device-tree-for-HD.patch
+patches/0670-ARM-dts-iwg22d-sodimm-sort-dt-nodes.patch
+patches/0671-ARM-dts-r8a7745-Add-HS-USB-device-node.patch
+patches/0672-ARM-dts-r8a7745-Add-USB-DMAC-device-nodes.patch
+patches/0673-ARM-dts-r8a7745-Enable-DMA-for-HSUSB.patch
+patches/0674-ARM-dts-iwg22d-sodimm-Enable-HS-USB.patch
+patches/0675-ARM-dts-r8a7745-Add-IIC-cores-to-dtsi.patch
+patches/0676-ARM-dts-r8a7743-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0677-ARM-dts-r8a7745-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0678-ARM-dts-r8a7778-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
+patches/0679-ARM-dts-r8a7779-Use-R-Car-SDHI-Gen1-fallback-compat-.patch
+patches/0680-ARM-dts-r8a7790-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0681-ARM-dts-r8a7791-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0682-ARM-dts-r8a7792-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0683-ARM-dts-r8a7793-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0684-ARM-dts-r8a7794-Use-R-Car-SDHI-Gen2-fallback-compat-.patch
+patches/0685-ARM-dts-iwg20d-q7-Add-support-for-ttySC3.patch
+patches/0686-ARM-dts-r8a7745-Add-DU-support.patch
+patches/0687-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-HDMI-video-output.patch
+patches/0688-ARM-dts-r8a7745-Add-CAN-01-SoC-support.patch
+patches/0689-ARM-dts-iwg22d-sodimm-Add-can0-support-to-carrier-bo.patch
+patches/0690-ARM-dts-iwg22d-sodimm-dbhd-ca-Add-can1-support-to-HD.patch
+patches/0691-ARM-dts-r8a7743-Add-CAN-01-SoC-support.patch
+patches/0692-ARM-dts-iwg20d-q7-common-Add-can0-support-to-carrier.patch
+patches/0693-ARM-dts-r8a7743-Add-default-PCIe-bus-clock.patch
+patches/0694-ARM-dts-r8a7743-Add-PCIe-Controller-device-node.patch
+patches/0695-ARM-dts-iwg20d-q7-Enable-PCIe-Controller.patch
+patches/0696-ARM-dts-r8a7743-add-VIN-dt-support.patch
+patches/0697-ARM-dts-r8a7745-add-VIN-dt-support.patch
+patches/0698-ARM-dts-koelsch-Correct-primary-compatible-value-for.patch
+patches/0699-ARM-dts-genmai-Correct-primary-compatible-value-for-.patch
+patches/0700-ARM-dts-r8a7794-Add-SMP-support.patch
+patches/0701-ARM-dts-r8a73a4-Update-CMT-compat-string.patch
+patches/0702-ARM-dts-r8a7790-Update-CMT-compat-strings.patch
+patches/0703-ARM-dts-r8a7791-Update-CMT-compat-strings.patch
+patches/0704-ARM-dts-r8a7793-Update-CMT-compat-strings.patch
+patches/0705-ARM-dts-r8a7794-Update-CMT-compat-strings.patch
+patches/0706-ARM-dts-r8a73a4-Remove-CMT-renesas-channels-mask.patch
+patches/0707-ARM-dts-r8a7740-Remove-CMT-renesas-channels-mask.patch
+patches/0708-ARM-dts-r8a7790-Remove-CMT-renesas-channels-mask.patch
+patches/0709-ARM-dts-r8a7791-Remove-CMT-renesas-channels-mask.patch
+patches/0710-ARM-dts-r8a7793-Remove-CMT-renesas-channels-mask.patch
+patches/0711-ARM-dts-r8a7794-Remove-CMT-renesas-channels-mask.patch
+patches/0712-ARM-dts-sh73a0-Remove-CMT-renesas-channels-mask.patch
+patches/0713-ARM-dts-armadillo800eva-Convert-to-named-i2c-gpio-bi.patch
+patches/0714-ARM-dts-lager-Convert-to-named-i2c-gpio-bindings.patch
+patches/0715-ARM-dts-koelsch-Convert-to-named-i2c-gpio-bindings.patch
+patches/0716-ARM-dts-alt-Convert-to-named-i2c-gpio-bindings.patch
+patches/0717-ARM-dts-r8a7745-Add-APMU-node-and-second-CPU-core.patch
+patches/0718-ARM-shmobile-defconfig-Enable-SGTL5000-audio-codec.patch
+patches/0719-ARM-dts-r8a7743-Add-audio-clocks.patch
+patches/0720-ARM-dts-r8a7743-Add-audio-DMAC-support.patch
+patches/0721-ARM-dts-r8a7743-Add-sound-support.patch
+patches/0722-ARM-dts-r8a7790-Correct-critical-CPU-temperature.patch
+patches/0723-ARM-dts-r8a7791-Correct-critical-CPU-temperature.patch
+patches/0724-ARM-dts-r8a7793-Correct-critical-CPU-temperature.patch
+patches/0725-ARM-shmobile-defconfig-Enable-PWM.patch
+patches/0726-ARM-dts-r8a7743-Add-PWM-SoC-support.patch
+patches/0727-ARM-dts-r8a7743-Add-TPU-support.patch
+patches/0728-ARM-dts-r8a7743-Add-thermal-device-to-DT.patch
+patches/0729-ARM-dts-r8a7745-Add-PWM-SoC-support.patch
+patches/0730-ARM-dts-r8a7745-Add-TPU-support.patch
+patches/0731-ARM-dts-r8a7743-Add-CMT-SoC-specific-support.patch
+patches/0732-ARM-dts-r8a7745-Add-CMT-SoC-specific-support.patch
+patches/0733-ARM-dts-r8a7745-sort-root-sub-nodes-alphabetically.patch
+patches/0734-ARM-dts-r8a7745-move-timer-node-out-of-bus.patch
+patches/0735-ARM-dts-r8a7792-sort-root-sub-nodes-alphabetically.patch
+patches/0736-ARM-dts-r8a7792-move-timer-node-out-of-bus.patch
+patches/0737-ARM-dts-iwg20d-q7-common-Enable-SGTL5000-audio-codec.patch
+patches/0738-ARM-dts-iwg20d-q7-common-Sound-PIO-support.patch
+patches/0739-ARM-dts-iwg20d-q7-common-Sound-DMA-support-on-DTS.patch
+patches/0740-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-BUSIF.patch
+patches/0741-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-SRC-o.patch
+patches/0742-ARM-dts-iwg20d-q7-common-Sound-DMA-support-via-DVC-o.patch
+patches/0743-ARM-dts-r8a7743-sort-root-sub-nodes-alphabetically.patch
+patches/0744-ARM-dts-r8a7743-move-timer-and-thermal-zones-nodes-o.patch
+patches/0745-ARM-dts-r8a7740-Correct-TPU-register-block-size.patch
+patches/0746-ARM-dts-r8a7745-Add-audio-clocks.patch
+patches/0747-ARM-dts-r8a7745-Add-audio-DMAC-support.patch
+patches/0748-ARM-dts-r8a7745-Add-sound-support.patch
+patches/0749-ARM-dts-iwg22d-sodimm-Enable-SGTL5000-audio-codec.patch
+patches/0750-ARM-dts-iwg22d-sodimm-Sound-PIO-support.patch
+patches/0751-ARM-dts-iwg22d-sodimm-Sound-DMA-support-on-DTS.patch
+patches/0752-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-BUSIF-on.patch
+patches/0753-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-SRC-on-D.patch
+patches/0754-ARM-dts-iwg22d-sodimm-Sound-DMA-support-via-DVC-on-D.patch
+patches/0755-ARM-dts-r8a7745-Add-missing-clock-for-secondary-CA7-.patch
+patches/0756-macb-Kill-PHY-reset-code.patch
+patches/0757-phylib-Add-device-reset-GPIO-support.patch
+patches/0758-net-mdio-Only-perform-gpio-reset-for-PHYs.patch
+patches/0759-net-phy-Handle-not-having-GPIO-enabled-in-the-kernel.patch
+patches/0760-PCI-OF-Add-generic-function-to-parse-and-allocate-PC.patch
+patches/0761-PM-domains-Don-t-skip-driver-s-suspend-resume_noirq-.patch
+patches/0762-PM-genpd-Stop-start-devices-without-pm_runtime_force.patch
+patches/0763-PM-wakeup-Add-device_set_wakeup_path-helper-to-contr.patch
+patches/0764-dt-bindings-gpio-rcar-Correct-SoC-family-name-for-R8.patch
+patches/0765-gpio-rcar-Use-wakeup_path-i.s.o.-explicit-clock-hand.patch
+patches/0766-clk-renesas-r8a77970-Add-LVDS-clock.patch
+patches/0767-clk-renesas-mstp-Keep-wakeup-sources-active-during-s.patch
+patches/0768-clk-renesas-cpg-mssr-Keep-wakeup-sources-active-duri.patch
+patches/0769-clk-renesas-r8a7796-Add-FDP-clock.patch
+patches/0770-i2c-Switch-to-using-gpiod-interface-for-gpio-bus-rec.patch
+patches/0771-i2c-make-kerneldoc-about-bus-recovery-more-precise.patch
+patches/0772-i2c-add-identifier-in-declarations-for-i2c_bus_recov.patch
+patches/0773-i2c-add-set_sda-to-bus_recovery_info.patch
+patches/0774-i2c-ensure-SDA-is-released-in-recovery-if-SDA-is-con.patch
+patches/0775-i2c-send-STOP-after-successful-bus-recovery.patch
+patches/0776-i2c-core-fix-compile-issue-related-to-incorrect-gpio.patch
+patches/0777-i2c-rcar-skip-DMA-if-buffer-is-not-safe.patch
+patches/0778-i2c-rcar-implement-bus-recovery.patch
+patches/0779-i2c-rcar-fix-some-trivial-typos-in-comments.patch
+patches/0780-dt-bindings-at24-add-compatible-for-nxp-se97b.patch
+patches/0781-dt-bindings-at24-add-bindings-for-Rohm-BR24T01.patch
+patches/0782-dt-bindings-at24-add-Renesas-R1EX24128.patch
+patches/0783-drm-bridge-synopsys-dw-hdmi-Export-some-PHY-related-.patch
+patches/0784-drm-bridge-synopsys-dw-hdmi-don-t-clobber-drvdata.patch
+patches/0785-gpio-em-Use-the-right-include.patch
+patches/0786-Input-gpio-keys-add-support-for-wakeup-event-action.patch
+patches/0787-regulator-dt-regulator-name-is-required-property.patch
+patches/0788-regulator-giving-regulator-controlling-gpios-a-non-e.patch
+patches/0789-dt-bindings-i2c-sh_mobile-Document-R-Car-M3-N-suppor.patch
+patches/0790-dt-bindings-iommu-ipmmu-vmsa-Add-device-tree-support.patch
+patches/0791-irqchip-gic-v2-Reset-APRn-registers-at-boot-time.patch
+patches/0792-irqchip-gic-Loudly-complain-about-the-use-of-IRQ_TYP.patch
+patches/0793-irqchip-gic-Update-supports_deactivate-static-key-to.patch
+patches/0794-PCI-rcar-gen2-Remove-duplicated-bit-wise-or-of-RCAR_.patch
+patches/0795-dt-bindings-PCI-rcar-Add-device-tree-support-for-r8a.patch
+patches/0796-PCI-rcar-Remove-unnecessary-semicolon.patch
+patches/0797-net-phy-micrel-add-125MHz-reference-clock-workaround.patch
+patches/0798-dt-bindings-rcar-gen3-phy-usb2-Add-bindings-for-r8a7.patch
+patches/0799-phy-rcar-gen3-usb2-Add-support-for-r8a77965.patch
+patches/0800-dt-bindings-pwm-rcar-Document-r8a774-35-PWM-bindings.patch
+patches/0801-dt-bindings-pwm-rcar-Add-bindings-for-R-Car-M3N-supp.patch
+patches/0802-pwm-rcar-Use-PM-Runtime-to-control-module-clock.patch
+patches/0803-pwm-rcar-Add-suspend-resume-support.patch
+patches/0804-dt-bindings-pwm-renesas-tpu-Document-r8a774-35-suppo.patch
+patches/0805-dt-bindings-pwm-renesas-tpu-Correct-example-TPU-regi.patch
+patches/0806-dt-bindings-pwm-renesas-tpu-Correct-SoC-part-numbers.patch
+patches/0807-ravb-add-support-for-changing-MTU.patch
+patches/0808-ravb-remove-erroneous-comment.patch
+patches/0809-dt-bindings-net-renesas-ravb-Add-support-for-r8a7747.patch
+patches/0810-dt-bindings-net-ravb-Add-support-for-r8a77965-SoC.patch
+patches/0811-dt-bindings-can-rcar_can-Fix-R8A7796-SoC-name.patch
+patches/0812-DT-net-can-rcar_canfd-document-R8A77970-bindings.patch
+patches/0813-DT-net-can-rcar_canfd-document-R8A77980-bindings.patch
+patches/0814-DT-dmaengine-renesas-rcar-dmac-document-R8A77980-sup.patch
+patches/0815-dmaengine-rcar-dmac-Fix-too-early-late-system-suspen.patch
+patches/0816-dt-bindings-rcar-dmac-Document-r8a77470-support.patch
+patches/0817-soc-renesas-rcar-rst-add-R8A77980-support.patch
+patches/0818-soc-renesas-rcar-rst-Enable-watchdog-as-reset-trigge.patch
+patches/0819-soc-renesas-rcar-rst-Add-support-for-R-Car-M3-N.patch
+patches/0820-media-dt-bindings-media-rcar_vin-Use-status-okay.patch
+patches/0821-media-rcar-vin-allocate-a-scratch-buffer-at-stream-s.patch
+patches/0822-media-rcar-vin-use-scratch-buffer-and-always-run-in-.patch
+patches/0823-mmc-renesas_sdhi-use-MMC_CAP2_NO_WRITE_PROTECT-inste.patch
+patches/0824-mmc-tmio-use-MMC_CAP2_NO_WRITE_PROTECT-instead-of-TM.patch
+patches/0825-mmc-tmio-remove-TMIO_MMC_WRPROTECT_DISABLE.patch
+patches/0826-mmc-tmio-deprecate-toshiba-mmc-wrprotect-disable-DT-.patch
+patches/0827-mmc-tmio-support-IP-builtin-card-detection-logic.patch
+patches/0828-mmc-tmio-fix-never-detected-card-insertion-bug.patch
+patches/0829-mmc-tmio-move-TMIO_MASK_-READOP-WRITEOP-handling-to-.patch
+patches/0830-mmc-tmio-clear-force_pio-flag-before-starting-data-t.patch
+patches/0831-mmc-tmio-remove-useless-TMIO_MASK_CMD-handling-in-tm.patch
+patches/0832-mmc-renesas_sdhi-fix-WP-detection.patch
+patches/0833-mmc-renesas_sdhi-replace-EXT_ACC-with-HOST_MODE.patch
+patches/0834-mmc-renesas_sdhi_internal_dmac-limit-DMA-RX-for-old-.patch
+patches/0835-soc-renesas-identify-R-Car-V3H.patch
+patches/0836-soc-renesas-Identify-R-Car-M3-N.patch
+patches/0837-spi-rspi-use-correct-enum-for-DMA-transfer-direction.patch
+patches/0838-sh_eth-simplify-sh_eth_check_reset.patch
+patches/0839-sh_eth-TSU_QTAG0-1-registers-the-same-as-TSU_QTAGM0-.patch
+patches/0840-sh_eth-add-sh_eth_cpu_data-soft_reset-method.patch
+patches/0841-sh_eth-add-sh_eth_cpu_data-edtrr_trns-value.patch
+patches/0842-sh_eth-add-sh_eth_cpu_data-xdfar_rw-flag.patch
+patches/0843-sh_eth-add-sh_eth_cpu_data-no_tx_cntrs-flag.patch
+patches/0844-sh_eth-add-sh_eth_cpu_data-cexcr-flag.patch
+patches/0845-sh_eth-add-sh_eth_cpu_data-no_xdfar-flag.patch
+patches/0846-sh_eth-kill-useless-check-in-__sh_eth_get_regs.patch
+patches/0847-sh_eth-Change-platform-check-to-CONFIG_ARCH_RENESAS.patch
+patches/0848-mmc-sh_mmcif-remove-some-cruft.patch
+patches/0849-spi-sh-msiof-Use-correct-enum-for-DMA-transfer-direc.patch
+patches/0850-spi-sh-msiof-Document-R-Car-M3-N-support.patch
+patches/0851-dt-bindings-pinctrl-sh-pfc-Correct-SoC-family-name-f.patch
+patches/0852-pinctrl-sh-pfc-Use-seq_puts-in-sh_pfc_pin_dbg_show.patch
+patches/0853-pinctrl-sh-pfc-r8a77995-Add-DU-pins-groups-and-funct.patch
+patches/0854-pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi.patch
+patches/0855-pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register.patch
+patches/0856-pinctrl-sh-pfc-r8a7795-Add-HDMI-pins-groups-and-func.patch
+patches/0857-pinctrl-sh-pfc-r8a7795-es1-Add-HDMI-pins-groups-and-.patch
+patches/0858-pinctrl-sh-pfc-r8a7796-Add-HDMI-pins-groups-and-func.patch
+patches/0859-pinctrl-sh-pfc-r8a7795-Add-TMU-pins-groups-and-funct.patch
+patches/0860-pinctrl-sh-pfc-r8a7795-es1-Add-TMU-pins-groups-and-f.patch
+patches/0861-pinctrl-sh-pfc-r8a7796-Add-TMU-pins-groups-and-funct.patch
+patches/0862-pinctrl-sh-pfc-Initial-R-Car-M3-N-support.patch
+patches/0863-pinctrl-sh-pfc-r8a77965-Add-SCIFs-groups-functions.patch
+patches/0864-pinctrl-sh-pfc-r8a77965-Add-EtherAVB-groups-function.patch
+patches/0865-pinctrl-sh-pfc-r8a7796-Add-VIN4-VIN5-pins-groups-and.patch
+patches/0866-pinctrl-sh-pfc-r8a7795-Add-VIN4-VIN5-pins-groups-and.patch
+patches/0867-pinctrl-sh-pfc-r8a77995-Add-VIN4-pins-groups-and-fun.patch
+patches/0868-pinctrl-sh-pfc-r8a77965-Add-support-for-INTC-EX-IRQ-.patch
+patches/0869-pinctrl-sh-pfc-r8a77965-Add-USB2.0-host-pins-groups-.patch
+patches/0870-pinctrl-sh-pfc-r8a77965-Add-USB3.0-host-pins-groups-.patch
+patches/0871-pinctrl-sh-pfc-Add-PORT_GP_CFG_25-helper-macro.patch
+patches/0872-pinctrl-sh-pfc-Add-R8A77980-PFC-support.patch
+patches/0873-pinctrl-sh-pfc-r8a77970-Add-EtherAVB-pin-groups.patch
+patches/0874-pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_.patch
+patches/0875-pinctrl-sh-pfc-Add-SH_PFC_PIN_GROUP_ALIAS.patch
+patches/0876-pinctrl-sh-pfc-r8a7795-Rename-EtherAVB-mdc-pin-group.patch
+patches/0877-pinctrl-sh-pfc-r8a7795-es1-Rename-EtherAVB-mdc-pin-g.patch
+patches/0878-pinctrl-sh-pfc-r8a7796-Rename-EtherAVB-mdc-pin-group.patch
+patches/0879-pinctrl-sh-pfc-r8a77965-Rename-EtherAVB-mdc-pin-grou.patch
+patches/0880-pinctrl-sh-pfc-r8a77995-Rename-EtherAVB-mdc-pin-grou.patch
+patches/0881-pinctrl-sh-pfc-r8a7795-Correct-VIN4-18-bit-pins.patch
+patches/0882-pinctrl-sh-pfc-r8a7796-Correct-VIN4-18-bit-pins.patch
+patches/0883-pinctrl-sh-pfc-r8a77995-Correct-VIN4-18-bit-pins.patch
+patches/0884-pinctrl-sh-pfc-r8a7795-Deduplicate-VIN4-pin-definiti.patch
+patches/0885-pinctrl-sh-pfc-r8a7796-Deduplicate-VIN4-pin-definiti.patch
+patches/0886-pinctrl-sh-pfc-r8a77995-Deduplicate-VIN4-pin-definit.patch
+patches/0887-media-v4l-vsp1-Print-the-correct-blending-unit-name-.patch
+patches/0888-media-v4l-vsp1-Fix-mask-creation-for-MULT_ALPHA_RATI.patch
+patches/0889-media-v4l-vsp1-Fix-video-output-on-R8A77970.patch
+patches/0890-watchdog-renesas_wdt-Add-suspend-resume-support.patch
+patches/0891-watchdog-renesas_wdt-Add-R-Car-Gen2-support.patch
+patches/0892-watchdog-renesas_wdt-Add-restart-handler.patch
+patches/0893-watchdog-renesas-wdt-Add-support-for-WDIOF_CARDRESET.patch
+patches/0894-usb-add-a-flag-to-skip-PHY-initialization-to-struct-.patch
+patches/0895-usb-xhci-Remove-ep_trb-from-xhci_cleanup_halted_endp.patch
+patches/0896-usb-xhci-Remove-ep_trb-from-finish_td.patch
+patches/0897-xhci-Don-t-always-run-the-default-stop-endpoint-comm.patch
+patches/0898-xhci-refactor-xhci_urb_enqueue-a-bit-with-minor-chan.patch
+patches/0899-xhci-Clear-the-host-side-toggle-manually-when-endpoi.patch
+patches/0900-xhci-Add-Intel-extended-cap-otg-phy-mux-handling.patch
+patches/0901-usb-host-xhci-plat-Remove-useless-test-before-clk_di.patch
+patches/0902-usb-host-xhci-plat-Fix-clock-resource-by-adding-a-re.patch
+patches/0903-of-unittest-Remove-redundant-OF_DETACHED-flag-settin.patch
+patches/0904-of-overlay-fix-memory-leak-related-to-duplicated-pro.patch
+patches/0905-of-overlay.c-Remove-comments-that-state-the-obvious-.patch
+patches/0906-of-overlay.c-Convert-comparisons-to-zero-or-NULL-to-.patch
+patches/0907-of-overlay-rename-identifiers-to-more-reflect-what-t.patch
+patches/0908-of-overlay-rename-identifiers-in-dup_and_fixup_symbo.patch
+patches/0909-of-overlay-minor-restructuring.patch
+patches/0910-of-overlay-detect-cases-where-device-tree-may-become.patch
+patches/0911-of-overlay-expand-check-of-whether-overlay-changeset.patch
+patches/0912-of-overlay-loosen-overly-strict-phandle-clash-check.patch
+patches/0913-of-overlay-avoid-race-condition-between-applying-mul.patch
+patches/0914-of-overlay-simplify-applying-symbols-from-an-overlay.patch
+patches/0915-of-overlay-remove-a-dependency-on-device-node-full_n.patch
+patches/0916-of-overlay-remove-unneeded-check-for-NULL-kbasename.patch
+patches/0917-of-overlay-pr_err-from-return-NOTIFY_OK-to-overlay-a.patch
+patches/0918-of-overlay-make-pr_err-string-unique.patch
+patches/0919-of-Spelling-s-changset-changeset.patch
+patches/0920-of-overlay-Remove-else-after-goto.patch
+patches/0921-of-overlay-Fix-memory-leak-in-of_overlay_apply-error.patch
+patches/0922-of-overlay-Fix-un-locking-in-of_overlay_apply.patch
+patches/0923-of-overlay-Fix-out-of-bounds-write-in-init_overlay_c.patch
+patches/0924-of-overlay-Make-node-skipping-in-init_overlay_change.patch
+patches/0925-ASoC-rsnd-indicate-IRQ-error-status-for-debug.patch
+patches/0926-ASoC-rsnd-suppress-rsnd_dai_call-debug-message.patch
+patches/0927-ASoC-rsnd-Document-R-Car-M3-W-support.patch
+patches/0928-ASoC-rsnd-set-pm_ops-in-hibernate-compatible-way.patch
+patches/0929-ASoC-rsnd-mark-PM-functions-__maybe_unused.patch
+patches/0930-drm-bridge-synopsys-dw-hdmi-fix-dw_hdmi_setup_rx_sen.patch
+patches/0931-drm-tilcdc-Remove-redundant-OF_DETACHED-flag-setting.patch
+patches/0932-drm-tilcdc-Remove-obsolete-ti-tilcdc-slave-dts-bindi.patch
+patches/0933-of-unittest-refactor-Makefile.patch
+patches/0934-of-fdt-use-memblock_virt_alloc-for-early-alloc.patch
+patches/0935-of-fdt-Fix-ifdef-dependency-of-early-flattree-declar.patch
+patches/0936-of-change-overlay-apply-input-data-from-unflattened-.patch
+patches/0937-of-improve-reporting-invalid-overlay-target-path.patch
+patches/0938-of-overlay-Fix-forgotten-reference-to-of_overlay_app.patch
+patches/0939-of-overlay-Stop-leaking-resources-on-overlay-removal.patch
+patches/0940-treewide-setup_timer-timer_setup.patch
+patches/0941-DT-serial-renesas-sci-serial-document-R8A77980-bindi.patch
+patches/0942-serial-sh-sci-use-hrtimer-for-receive-timeout.patch
+patches/0943-serial-sh-sci-Document-r8a77470-bindings.patch
+patches/0944-dt-bindings-arm-document-R8A77980-SoC-bindings.patch
+patches/0945-arm64-defconfig-enable-R8A77980-SoC.patch
+patches/0946-arm64-dts-renesas-r8a7795-move-scif-node-into-alphab.patch
+patches/0947-arm64-dts-renesas-r8a7795-Add-OPPs-table-for-cpu-dev.patch
+patches/0948-arm64-dts-renesas-r8a7796-Add-OPPs-table-for-cpu-dev.patch
+patches/0949-arm64-dts-renesas-r8a7796-add-thermal-cooling-manage.patch
+patches/0950-arm64-dts-renesas-r8a7795-add-thermal-cooling-manage.patch
+patches/0951-arm64-dts-renesas-salvator-common-add-GPIO-extender.patch
+patches/0952-arm64-dts-renesas-r8a77970-move-node-which-has-no-re.patch
+patches/0953-arm64-dts-renesas-r8a77995-move-nodes-which-have-no-.patch
+patches/0954-arm64-dts-renesas-r8a7795-update-register-size-for-t.patch
+patches/0955-arm64-dts-renesas-r8a7796-update-register-size-for-t.patch
+patches/0956-arm64-dts-renesas-r8a77995-add-I2C-support.patch
+patches/0957-arm64-dts-renesas-draak-enable-I2C-controller-0-and-.patch
+patches/0958-arm64-dts-renesas-draak-enable-I2C-controller-1.patch
+patches/0959-arm64-dts-renesas-initial-R8A77980-SoC-device-tree.patch
+patches/0960-arm64-dts-renesas-r8a77980-add-SYS-DMAC-support.patch
+patches/0961-arm64-dts-renesas-r8a77970-Remove-non-existing-STBE-.patch
+patches/0962-arm64-dts-renesas-r8a77995-Remove-non-existing-STBE-.patch
+patches/0963-arm64-defconfig-enable-MESON-EFUSE.patch
+patches/0964-arm64-dts-renesas-r8a77970-add-PFC-support.patch
+patches/0965-arm64-dts-renesas-eagle-add-SCIF0-pins.patch
+patches/0966-arm64-dts-renesas-r8a77970-add-GPIO-support.patch
+patches/0967-arm64-dts-renesas-eagle-specify-EtherAVB-PHY-IRQ.patch
+patches/0968-arm64-dts-renesas-r8a77995-add-FCPV-nodes.patch
+patches/0969-arm64-dts-renesas-r8a77995-add-VSP-instances.patch
+patches/0970-arm64-dts-renesas-draak-enable-SDHI2.patch
+patches/0971-arm64-dts-renesas-r8a77995-add-DU-support.patch
+patches/0972-arm64-dts-renesas-r8a7795-es1-Fix-register-mappings-.patch
+patches/0973-arm64-dts-renesas-r8a7795-Fix-register-mappings-on-V.patch
+patches/0974-arm64-dts-renesas-r8a7796-Fix-register-mappings-on-V.patch
+patches/0975-arm64-dts-renesas-draak-Enable-DU.patch
+patches/0976-dt-bindings-arm-document-Condor-board-bindings.patch
+patches/0977-dt-bindings-arm-Document-Renesas-H2-based-Stout-DT-b.patch
+patches/0978-dt-bindings-arm-Document-R-Car-M3-N-SoC-DT-bindings.patch
+patches/0979-arm64-defconfig-Enable-PWM-and-USB-for-R-Car.patch
+patches/0980-arm64-dts-renesas-r8a77980-add-H-SCIF-support.patch
+patches/0981-arm64-dts-renesas-r8a77980-add-EtherAVB-support.patch
+patches/0982-arm64-dts-renesas-initial-Condor-board-device-tree.patch
+patches/0983-arm64-dts-renesas-condor-add-EtherAVB-support.patch
+patches/0984-arm64-defconfig-enable-R8A77965-SoC.patch
+patches/0985-dt-bindings-arm-Document-SoC-compatible-value-for-Ar.patch
+patches/0986-dt-bindings-arm-Document-Renesas-V3MSK-and-Wheat-boa.patch
+patches/0987-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
+patches/0988-dt-bindings-arm-Document-Renesas-R-Car-M3-N-based-Sa.patch
+patches/0989-arm64-defconfig-enable-IOSCHED_DEADLINE.patch
+patches/0990-arm64-defconfig-add-newly-added-accelerated-crypto-m.patch
+patches/0991-arm64-defconfig-add-support-for-Socionext-SynQuacer-.patch
+patches/0992-arm64-defconfig-Enable-NVIDIA-Tegra194-support.patch
+patches/0993-arm64-defconfig-Enable-the-APCS-IPC-driver-on-Qualco.patch
+patches/0994-arm64-defconfig-enable-thermal-sensor-on-QCOM-platfo.patch
+patches/0995-arm64-defconfig-enable-more-cpufreq-governors.patch
+patches/0996-arm64-defconfig-Enable-CONFIG_ARM_TEGRA186_CPUFREQ.patch
+patches/0997-arm64-defconfig-Enable-CONFIG_TEGRA_BPMP_THERMAL.patch
+patches/0998-arm64-dts-renesas-r8a7796-Update-OPPs-to-support-CA5.patch
+patches/0999-arm64-dts-renesas-r8a7795-Update-OPPs-to-support-CA5.patch
+patches/1000-arm64-dts-renesas-initial-R8A77965-SoC-device-tree.patch
+patches/1001-arm64-dts-renesas-Add-R-Car-Salvator-x-M3-N-support.patch
+patches/1002-arm64-dts-renesas-r8a77965-Add-dmac-device-nods.patch
+patches/1003-arm64-dts-renesas-r8a77965-Add-SCIF-device-nodes.patch
+patches/1004-arm64-dts-renesas-r8a77965-Add-GPIO-nodes.patch
+patches/1005-arm64-dts-renesas-r8a77965-Add-reg-properties.patch
+patches/1006-arm64-dts-renesas-r8a77965-Add-address-cells-and-siz.patch
+patches/1007-arm64-dts-renesas-r8a77965-Remove-stale-reg-property.patch
+patches/1008-arm64-dts-renesas-r8a77965-Add-phy-cells-property.patch
+patches/1009-arm64-dts-renesas-r8a77965-Add-pwm-cells-property.patch
+patches/1010-arm64-dts-renesas-r8a77965-Add-interrupt-cells-prope.patch
+patches/1011-arm64-dts-renesas-r8a77965-Move-usb2_phy1-up.patch
+patches/1012-arm64-dts-renesas-Add-support-for-Salvator-XS-with-R.patch
+patches/1013-arm64-dts-renesas-r8a77965-Add-IIC-DVFS-device-node.patch
+patches/1014-arm64-dts-renesas-r8a77965-Add-INTC-EX-device-node.patch
+patches/1015-arm64-dts-renesas-salvator-common-Override-EtherAVB-.patch
+patches/1016-arm64-dts-renesas-ulcb-Override-EtherAVB-phy-mode.patch
+patches/1017-arm64-dts-renesas-draak-Override-EtherAVB-phy-mode.patch
+patches/1018-arm64-dts-renesas-eagle-Override-EtherAVB-phy-mode.patch
+patches/1019-arm64-dts-renesas-v3msk-Override-EtherAVB-phy-mode.patch
+patches/1020-arm64-dts-renesas-r8a7796-Set-EtherAVB-phy-mode-to-r.patch
+patches/1021-arm64-dts-renesas-r8a7795-Set-EtherAVB-phy-mode-to-r.patch
+patches/1022-arm64-dts-renesas-r8a77995-Set-EtherAVB-phy-mode-to-.patch
+patches/1023-arm64-dts-renesas-r8a77970-Set-EtherAVB-phy-mode-to-.patch
+patches/1024-arm64-dts-renesas-r8a77965-Add-EtherAVB-device-node.patch
+patches/1025-arm64-dts-renesas-r8a77965-salvator-xs-Add-SoC-name-.patch
+patches/1026-arm64-dts-renesas-r8a77970-add-I2C-support.patch
+patches/1027-arm64-dts-renesas-eagle-add-I2C0-support.patch
+patches/1028-arm64-dts-renesas-r8a77970-sort-subnodes-of-root-nod.patch
+patches/1029-arm64-dts-renesas-r8a7795-Add-IPMMU-PV1-device-node.patch
+patches/1030-arm64-dts-renesas-r8a7795-Add-missing-SYS-DMAC2-dmas.patch
+patches/1031-arm64-defconfig-Enable-the-Tegra-SMMU-by-default.patch
+patches/1032-arm64-dts-renesas-v3msk-add-SCIF0-pins.patch
+patches/1033-arm64-defconfig-enable-stmmac-ethernet-to-defconfig.patch
+patches/1034-arm64-defconfig-add-CONFIG_UNIPHIER_THERMAL-and-CONF.patch
+patches/1035-arm64-add-Renesas-R8A77965-support.patch
+patches/1036-arm64-add-Renesas-R8A77980-support.patch
+patches/1037-drm-rcar-du-dw-hdmi-Fix-compilation.patch
+patches/1038-drm-rcar-du-Use-drm_mode_get_hv_timing-to-populate-p.patch
+patches/1039-drm-rcar-du-Remove-zpos-field-from-rcar_du_vsp_plane.patch
+patches/1040-drm-rcar-du-Use-1000-to-avoid-misunderstanding-in-rc.patch
+patches/1041-drm-rcar-du-Calculate-DPLLCR-to-be-more-small-jitter.patch
+patches/1042-drm-rcar-du-Enable-VSP-compositor-by-default-on-Gen3.patch
+patches/1043-drm-rcar-du-lvds-Fix-LVDCR1-for-R-Car-gen3.patch
+patches/1044-drm-rcar-du-lvds-Fix-LVDS-clock-frequency-range.patch
+patches/1045-drm-rcar-du-lvds-Refactor-LVDS-startup.patch
+patches/1046-dt-bindings-display-renesas-Add-R-Car-LVDS-encoder-D.patch
+patches/1047-dt-bindings-display-renesas-Deprecate-LVDS-support-i.patch
+patches/1048-drm-rcar-du-Fix-legacy-DT-to-create-LVDS-encoder-nod.patch
+patches/1049-drm-rcar-du-Convert-LVDS-encoder-code-to-bridge-driv.patch
+patches/1050-dt-bindings-display-renesas-du-Document-R8A77970-bin.patch
+patches/1051-dt-bindings-display-renesas-lvds-Document-R8A77970-b.patch
+patches/1052-drm-rcar-du-Add-R8A77970-support.patch
+patches/1053-drm-rcar-du-lvds-Add-R8A77970-support.patch
+patches/1054-dt-bindings-display-renesas-du-Document-r8a77995-bin.patch
+patches/1055-dt-bindings-display-renesas-lvds-Document-r8a77995-b.patch
+patches/1056-drm-rcar-du-lvds-Fix-crash-in-.atomic_check-when-dis.patch
+patches/1057-soc-renesas-rcar-sysc-Mark-rcar_sysc_matches-__initc.patch
+patches/1058-soc-renesas-r8a77970-sysc-fix-power-area-parents.patch
+patches/1059-dt-bindings-power-add-R8A77980-SYSC-power-domain-def.patch
+patches/1060-soc-renesas-rcar-sysc-add-R8A77980-support.patch
+patches/1061-soc-renesas-rcar-sysc-Add-R-Car-M3-N-support.patch
+patches/1062-ARM-dts-r8a7790-Reduce-size-of-thermal-registers.patch
+patches/1063-ARM-dts-r8a7791-Reduce-size-of-thermal-registers.patch
+patches/1064-ARM-dts-r8a7793-Reduce-size-of-thermal-registers.patch
+patches/1065-ARM-dts-lager-Add-CEC-clock-for-HDMI-transmitter.patch
+patches/1066-ARM-dts-iwg20m-Enable-cmt0.patch
+patches/1067-ARM-dts-iwg22m-Enable-cmt0.patch
+patches/1068-ARM-dts-r8a7790-consistently-use-single-space-after.patch
+patches/1069-ARM-dts-r8a7790-add-soc-node.patch
+patches/1070-ARM-dts-r8a7790-sort-subnodes-of-soc-node.patch
+patches/1071-ARM-dts-r8a7790-sort-subnodes-of-root-node.patch
+patches/1072-ARM-dts-r8a7791-consistently-use-single-space-after.patch
+patches/1073-ARM-dts-r8a7791-add-soc-node.patch
+patches/1074-ARM-dts-r8a7791-sort-subnodes-of-root-node.patch
+patches/1075-ARM-dts-r8a7792-sort-subnodes-of-soc-node.patch
+patches/1076-ARM-dts-r8a7793-consistently-use-single-space-after.patch
+patches/1077-ARM-dts-r8a7793-add-soc-node.patch
+patches/1078-ARM-dts-r8a7793-sort-subnodes-of-soc-node.patch
+patches/1079-ARM-dts-r8a7793-sort-subnodes-of-root-node.patch
+patches/1080-ARM-dts-r8a7794-consistently-use-single-space-after.patch
+patches/1081-ARM-dts-r8a7794-add-soc-node.patch
+patches/1082-ARM-dts-r8a7794-sort-subnodes-of-soc-node.patch
+patches/1083-ARM-dts-r8a7794-sort-subnodes-of-root-node.patch
+patches/1084-ARM-dts-r8a7790-consistently-use-single-space-before.patch
+patches/1085-ARM-dts-r8a7791-consistently-use-single-space-before.patch
+patches/1086-ARM-dts-r8a7793-consistently-use-single-space-before.patch
+patches/1087-ARM-dts-r8a7743-sort-subnodes-of-soc-node.patch
+patches/1088-ARM-dts-r8a7745-sort-subnodes-of-soc-node.patch
+patches/1089-ARM-dts-r8a7743-Add-IPMMU-DT-nodes.patch
+patches/1090-ARM-dts-r8a7745-Add-IPMMU-DT-nodes.patch
+patches/1091-ARM-dts-r8a7743-Add-VSP-support.patch
+patches/1092-ARM-dts-r8a7745-Add-VSP-support.patch
+patches/1093-ARM-dts-lager-use-demuxer-for-IIC2-I2C2.patch
+patches/1094-ARM-dts-lager-use-demuxer-for-IIC3-I2C3.patch
+patches/1095-ARM-dts-koelsch-use-demuxer-for-I2C2.patch
+patches/1096-ARM-dts-koelsch-use-demuxer-for-I2C4.patch
+patches/1097-ARM-dts-porter-use-demuxer-for-I2C2.patch
+patches/1098-ARM-dts-alt-use-demuxer-for-I2C1.patch
+patches/1099-ARM-dts-silk-use-demuxer-for-I2C1.patch
+patches/1100-ARM-dts-gose-use-demuxer-for-I2C2.patch
+patches/1101-ARM-dts-gose-use-demuxer-for-I2C4.patch
+patches/1102-ARM-shmobile-Enable-RZA1-pin-controller.patch
+patches/1103-ARM-shmobile-stout-enable-R-Car-Gen2-regulator-quirk.patch
+patches/1104-ARM-shmobile-rcar-gen2-Fix-error-check-in-regulator-.patch
+patches/1105-ARM-shmobile-defconfig-Refresh.patch
+patches/1106-ARM-shmobile-defconfig-Disable-CONFIG_EMBEDDED.patch
+patches/1107-ARM-shmobile-Add-watchdog-support.patch
+patches/1108-ARM-shmobile-rcar-gen2-Add-watchdog-support.patch
+patches/1109-ARM-dts-kzm9d-Fix-debounce-interval-property-misspel.patch
+patches/1110-ARM-dts-lager-Move-cec_clock-to-root-node.patch
+patches/1111-ARM-dts-stout-Initial-r8a7790-Stout-board-support.patch
+patches/1112-ARM-dts-marzen-Add-SDHI0-VCCQ-Regulator.patch
+patches/1113-ARM-dts-silk-Add-r1ex24002-EEPROM-to-DT.patch
+patches/1114-ARM-dts-silk-Add-GPIO-keys-to-DT.patch
+patches/1115-ARM-dts-r8a7790-Convert-to-new-LVDS-DT-bindings.patch
+patches/1116-ARM-dts-r8a7791-Convert-to-new-LVDS-DT-bindings.patch
+patches/1117-ARM-dts-r8a7793-Convert-to-new-LVDS-DT-bindings.patch
+patches/1118-media-v4l2-common-create-v4l2_g-s_parm_cap-helpers.patch
+patches/1119-media-dt-bindings-media-Add-Renesas-CEU-bindings.patch
+patches/1120-media-include-media-Add-Renesas-CEU-driver-interface.patch
+patches/1121-media-platform-Add-Renesas-CEU-driver.patch
+patches/1122-media-platform-renesas-ceu-Fix-CSTRST_CPON-mask.patch
+patches/1123-media-renesas-ceu-mark-PM-functions-as-__maybe_unuse.patch
+patches/1124-gpio-pca953x-add-compatibility-for-pcal6524-and-pcal.patch
+patches/1125-irqchip-renesas-irqc-Use-wakeup_path-i.s.o.-explicit.patch
+patches/1126-irqchip-renesas-intc-irqpin-Use-wakeup_path-i.s.o.-e.patch
+patches/1127-gpio-gpio-rcar-Support-S2RAM.patch
+patches/1128-clk-renesas-Stop-enabling-legacy-DT-clock-support-by.patch
+patches/1129-clk-renesas-rcar-gen3-Add-Z-clock-divider-support.patch
+patches/1130-clk-renesas-rcar-gen3-Add-Z2-clock-divider-support.patch
+patches/1131-clk-renesas-r8a7795-Add-Z-clock.patch
+patches/1132-clk-renesas-r8a7795-Add-Z2-clock.patch
+patches/1133-clk-renesas-r8a7796-Add-Z-clock.patch
+patches/1134-clk-renesas-r8a7796-Add-Z2-clock.patch
+patches/1135-clk-renesas-r8a7743-Add-rwdt-clock.patch
+patches/1136-clk-renesas-r8a7745-Add-rwdt-clock.patch
+patches/1137-clk-renesas-r8a7790-Add-rwdt-clock.patch
+patches/1138-clk-renesas-r8a7791-r8a7793-Add-rwdt-clock.patch
+patches/1139-clk-renesas-r8a7794-Add-rwdt-clock.patch
+patches/1140-clk-renesas-r8a7792-Add-rwdt-clock.patch
+patches/1141-dt-bindings-clock-add-R8A77980-CPG-core-clock-defini.patch
+patches/1142-clk-renesas-cpg-mssr-add-R8A77980-support.patch
+patches/1143-clk-renesas-cpg-mssr-Add-support-for-R-Car-M3-N.patch
+patches/1144-clk-renesas-r8a77965-Replace-DU2-clock.patch
+patches/1145-clk-renesas-div6-Always-use-readl-writel.patch
+patches/1146-clk-renesas-mstp-Always-use-readl-writel.patch
+patches/1147-clk-renesas-r8a73a4-Always-use-readl-writel.patch
+patches/1148-clk-renesas-r8a7740-Always-use-readl-writel.patch
+patches/1149-clk-renesas-rcar-gen2-Always-use-readl-writel.patch
+patches/1150-clk-renesas-rza1-Always-use-readl-writel.patch
+patches/1151-clk-renesas-sh73a0-Always-use-readl-writel.patch
+patches/1152-clk-renesas-rcar-gen3-Always-use-readl-writel.patch
+patches/1153-clk-renesas-cpg-mssr-Adjust-r8a77980-ifdef.patch
+patches/1154-drivers-base-Unified-device-connection-lookup.patch
+patches/1155-usb-common-Small-class-for-USB-role-switches.patch
+patches/1156-dt-bindings-i2c-document-R8A77995-bindings.patch
+patches/1157-dt-bindings-i2c-document-R8A77965-bindings.patch
+patches/1158-i2c-rcar-fix-mask-value-of-prohibited-bit.patch
+patches/1159-drm-adv7511-Add-support-for-i2c_new_secondary_device.patch
+patches/1160-drm-bridge-adv7511-fix-mode_valid-s-return-type.patch
+patches/1161-drm-bridge-adv7511-fix-spelling-of-driver-name-in-Kc.patch
+patches/1162-gpu-drm-bridge-adv7511-Replace-mdelay-with-usleep_ra.patch
+patches/1163-media-adv7511-fix-clearing-of-the-CEC-receive-buffer.patch
+patches/1164-media-adv7511-fix-incorrect-clear-of-CEC-receive-int.patch
+patches/1165-dt-bindings-display-renesas-Add-R-Car-M3-N-HDMI-TX-D.patch
+patches/1166-ASoC-sh-Drop-SUPERH-platform-dependency.patch
+patches/1167-ASoC-sh-Update-menu-title-and-platform-dependency.patch
+patches/1168-i2c-busses-remove-superfluous-ignoring-of-children-f.patch
+patches/1169-dt-bindings-net-ravb-Add-support-for-r8a77990-SoC.patch
+patches/1170-dmaengine-rcar-dmac-Document-R-Car-D3-bindings.patch
+patches/1171-media-v4l-vsp1-Don-t-start-stop-media-pipeline-for-D.patch
+patches/1172-media-v4l-vsp1-Remove-unused-field-from-vsp1_drm_pip.patch
+patches/1173-media-v4l-vsp1-Store-pipeline-pointer-in-vsp1_entity.patch
+patches/1174-media-v4l-vsp1-Use-vsp1_entity.pipe-to-check-if-enti.patch
+patches/1175-media-v4l-vsp1-Share-duplicated-DRM-pipeline-configu.patch
+patches/1176-media-v4l-vsp1-Move-DRM-atomic-commit-pipeline-setup.patch
+patches/1177-media-v4l-vsp1-Setup-BRU-at-atomic-commit-time.patch
+patches/1178-media-v4l-vsp1-Replace-manual-DRM-pipeline-input-set.patch
+patches/1179-media-v4l-vsp1-Move-DRM-pipeline-output-setup-code-t.patch
+patches/1180-media-v4l-vsp1-Turn-frame-end-completion-status-into.patch
+patches/1181-media-v4l-vsp1-Add-per-display-list-internal-complet.patch
+patches/1182-media-v4l-vsp1-Generalize-detection-of-entity-remova.patch
+patches/1183-media-v4l-vsp1-Assign-BRU-and-BRS-to-pipelines-dynam.patch
+patches/1184-media-v4l-vsp1-Add-BRx-dynamic-assignment-debugging-.patch
+patches/1185-media-v4l-vsp1-Rename-BRU-to-BRx.patch
+patches/1186-media-v4l-vsp1-Use-SPDX-license-headers.patch
+patches/1187-media-v4l-vsp1-Share-the-CLU-LIF-and-LUT-set_fmt-pad.patch
+patches/1188-media-v4l-vsp1-Reset-the-crop-and-compose-rectangles.patch
+patches/1189-media-v4l-vsp1-Document-the-vsp1_du_atomic_config-st.patch
+patches/1190-media-v4l-vsp1-Extend-the-DU-API-to-support-CRC-comp.patch
+patches/1191-media-v4l-vsp1-Add-support-for-the-DISCOM-entity.patch
+patches/1192-media-v4l-vsp1-Integrate-DISCOM-in-display-pipeline.patch
+patches/1193-media-vsp1-Move-video-suspend-resume-handling-to-vid.patch
+patches/1194-media-vsp1-Reword-uses-of-fragment-as-body.patch
+patches/1195-media-vsp1-Protect-bodies-against-overflow.patch
+patches/1196-media-vsp1-Provide-a-body-pool.patch
+patches/1197-media-vsp1-Convert-display-lists-to-use-new-body-poo.patch
+patches/1198-media-vsp1-Use-reference-counting-for-bodies.patch
+patches/1199-media-vsp1-Refactor-display-list-configure-operation.patch
+patches/1200-media-vsp1-Adapt-entities-to-configure-into-a-body.patch
+patches/1201-media-vsp1-Move-video-configuration-to-a-cached-dlb.patch
+patches/1202-dt-bindings-thermal-rcar-gen3-thermal-update-registe.patch
+patches/1203-thermal-rcar_gen3_thermal-Update-calculation-formula.patch
+patches/1204-thermal-rcar_gen3_thermal-update-max-temperature-cla.patch
+patches/1205-dt-bindings-thermal-rcar-gen3-thermal-add-r8a77965.patch
+patches/1206-thermal-rcar_gen3_thermal-add-r8a77965-support.patch
+patches/1207-soc-renesas-rcar-rst-Add-support-for-RZ-G1C.patch
+patches/1208-soc-renesas-rcar-rst-Add-support-for-R-Car-E3.patch
+patches/1209-ASoC-rsnd-makes-rsnd_cmd_mod_get-static.patch
+patches/1210-ASoC-rsnd-add-RSND_GEN3-for-R-Car-Gen3.patch
+patches/1211-ASoC-rsnd-don-t-assume-node-full-path-name-for-HDMI-.patch
+patches/1212-ASoC-rsnd-Enable-IPMMU-v2.patch
+patches/1213-ASoC-rsnd-ssi-wait-maximum-5ms-for-status-check.patch
+patches/1214-dt-bindings-thermal-rcar-thermal-add-R8A77995-suppor.patch
+patches/1215-thermal-rcar_thermal-add-r8a77995-support.patch
+patches/1216-dt-bindings-more-status-property-removal-from-exampl.patch
+patches/1217-mmc-renesas_sdhi-use-helpers-to-access-struct-scatte.patch
+patches/1218-mmc-renesas_sdhi-Fix-alignment-check-of-sg-buffer.patch
+patches/1219-mmc-renesas_sdhi_internal_dmac-use-more-generic-whit.patch
+patches/1220-mmc-renesas_sdhi_internal_dmac-remove-superfluous-WA.patch
+patches/1221-mmc-dt-tmio_mmc-document-R8A77980-bindings.patch
+patches/1222-mmc-renesas_sdhi_internal_dmac-add-R8A77980-to-white.patch
+patches/1223-mmc-renesas_sdhi-Add-r8a77965-support.patch
+patches/1224-mmc-renesas_sdhi-really-fix-WP-logic-regressions.patch
+patches/1225-soc-renesas-Identify-RZ-G1C.patch
+patches/1226-soc-renesas-identify-R-Car-E3.patch
+patches/1227-dt-bindings-timer-renesas-cmt-Document-r8a774-35-CMT.patch
+patches/1228-dmaengine-shdmac-Change-platform-check-to-CONFIG_ARC.patch
+patches/1229-sh_eth-use-TSU-register-accessors-for-TSU_POST-n.patch
+patches/1230-sh_eth-WARN_ON-access-to-unimplemented-TSU-register.patch
+patches/1231-sh_eth-add-RGMII-support.patch
+patches/1232-sh_eth-add-EDMR.NBST-support.patch
+patches/1233-sh_eth-add-R8A77980-support.patch
+patches/1234-sh_eth-fix-typo-in-EESR.TRO-bit-name.patch
+patches/1235-sh_eth-fix-comment-grammar-in-struct-sh_eth_cpu_data.patch
+patches/1236-sh_eth-fix-typo-in-comment-to-BCULR-write.patch
+patches/1237-sh_eth-make-sh_eth_soft_swap-work-on-ARM.patch
+patches/1238-sh_eth-uninline-sh_eth_soft_swap.patch
+patches/1239-sh_eth-use-DIV_ROUND_UP-in-sh_eth_soft_swap.patch
+patches/1240-net-Remove-depends-on-HAS_DMA-in-case-of-platform-de.patch
+patches/1241-spi-sh-msiof-Simplify-calculation-of-divisors-for-tr.patch
+patches/1242-pinctrl-sh-pfc-r8a77965-Add-MSIOF-pins-groups-and-fu.patch
+patches/1243-pinctrl-sh-pfc-r8a7795-Fix-comment-for-MSIOF3-SS2_E-.patch
+patches/1244-pinctrl-sh-pfc-r8a7796-Fix-comment-for-MSIOF3-SS2_E-.patch
+patches/1245-pinctrl-sh-pfc-r8a77965-Add-PWM-pins-groups-and-func.patch
+patches/1246-dt-bindings-pinctrl-sh-pfc-Document-r8a77470-PFC-sup.patch
+patches/1247-pinctrl-sh-pfc-r8a77980-Add-pin-I-O-voltage-control-.patch
+patches/1248-pinctrl-sh-pfc-r8a77970-Fix-pin-I-O-voltage-control-.patch
+patches/1249-pinctrl-sh-pfc-r8a77965-Fixup-incorrect-SPDX-identif.patch
+patches/1250-pinctrl-sh-pfc-r8a77965-Add-DU-RGB-output-pins-group.patch
+patches/1251-pinctrl-sh-pfc-r8a77965-Add-SDHI-pins-groups-and-fun.patch
+patches/1252-pinctrl-sh-pfc-Add-r8a77470-PFC-support.patch
+patches/1253-pinctrl-sh-pfc-Add-PORT_GP_11-helper-macro.patch
+patches/1254-pinctrl-sh-pfc-Initial-R8A77990-PFC-support.patch
+patches/1255-pinctrl-sh-pfc-r8a77990-Add-bias-pinconf-support.patch
+patches/1256-pinctrl-sh-pfc-r8a77990-Add-SCIF-pins-groups-and-fun.patch
+patches/1257-pinctrl-sh-pfc-r8a77990-Add-I2C-1-2-4-5-6-7-pins-gro.patch
+patches/1258-pinctrl-sh-pfc-r8a77990-Add-EthernetAVB-pins-groups-.patch
+patches/1259-pinctrl-sh-pfc-r8a77965-Add-I2C-pin-support.patch
+patches/1260-pinctrl-sh-pfc-rcar-gen3-Fix-grammar-in-static-pin-c.patch
+patches/1261-rtc-simplify-getting-.drvdata.patch
+patches/1262-serial-sh-sci-Add-support-for-dynamic-instances.patch
+patches/1263-serial-sh-sci-Support-for-HSCIF-RX-sampling-point-ad.patch
+patches/1264-staging-board-Replace-license-boilerplate-with-SPDX-.patch
+patches/1265-usb-gadget-udc-renesas_usb3-should-call-pm_runtime_e.patch
+patches/1266-usb-gadget-udc-renesas_usb3-should-call-devm_phy_get.patch
+patches/1267-usb-gadget-udc-renesas_usb3-should-fail-if-devm_phy_.patch
+patches/1268-usb-gadget-udc-renesas_usb3-fix-double-phy_put.patch
+patches/1269-USB-gadget-udc-renesas_usb3-no-need-to-check-return-.patch
+patches/1270-USB-renesas_usbhs-drop-unused-legacy-phy-support.patch
+patches/1271-watchdog-renesas-wdt-Remove-R-Car-M2-W-ES2.x-from-bl.patch
+patches/1272-watchdog-renesas-wdt-Add-support-for-the-R8A77965-WD.patch
+patches/1273-dt-bindings-watchdog-renesas-wdt-Add-R-Car-Gen2-supp.patch
+patches/1274-spi-Expose-spi_-map-unmap-_buf-for-internal-use.patch
+patches/1275-spi-Add-an-helper-to-flush-the-message-queue.patch
+patches/1276-spi-Extend-the-core-to-ease-integration-of-SPI-memor.patch
+patches/1277-mtd-spi-nor-Use-the-spi_mem_xx-API.patch
+patches/1278-mtd-devices-m25p80-Use-spi_mem_set_drvdata-instead-o.patch
+patches/1279-media-rcar-vin-Fix-image-alignment-for-setting-pre-c.patch
+patches/1280-media-dt-bindings-media-rcar_vin-Reverse-SoC-part-nu.patch
+patches/1281-media-dt-bindings-media-rcar_vin-add-device-tree-sup.patch
+patches/1282-media-rcar-vin-add-Gen3-devicetree-bindings-document.patch
+patches/1283-media-rcar-vin-rename-poorly-named-initialize-and-cl.patch
+patches/1284-media-rcar-vin-unregister-video-device-on-driver-rem.patch
+patches/1285-media-rcar-vin-move-subdevice-handling-to-async-call.patch
+patches/1286-media-rcar-vin-move-model-information-to-own-struct.patch
+patches/1287-media-rcar-vin-move-max-width-and-height-information.patch
+patches/1288-media-rcar-vin-move-functions-regarding-scaling.patch
+patches/1289-media-rcar-vin-all-Gen2-boards-can-scale-simplify-lo.patch
+patches/1290-media-rcar-vin-set-a-default-field-to-fallback-on.patch
+patches/1291-media-rcar-vin-fix-handling-of-single-field-frames-t.patch
+patches/1292-media-rcar-vin-update-bytesperline-and-sizeimage-cal.patch
+patches/1293-media-rcar-vin-align-pixelformat-check.patch
+patches/1294-media-rcar-vin-break-out-format-alignment-and-checki.patch
+patches/1295-media-rcar-vin-simplify-how-formats-are-set-and-rese.patch
+patches/1296-media-rcar-vin-cache-video-standard.patch
+patches/1297-media-rcar-vin-move-media-bus-configuration-to-struc.patch
+patches/1298-media-rcar-vin-enable-Gen3-hardware-configuration.patch
+patches/1299-media-rcar-vin-add-function-to-manipulate-Gen3-chsel.patch
+patches/1300-media-rcar-vin-add-flag-to-switch-to-media-controlle.patch
+patches/1301-media-rcar-vin-use-different-v4l2-operations-in-medi.patch
+patches/1302-media-rcar-vin-force-default-colorspace-for-media-ce.patch
+patches/1303-media-rcar-vin-prepare-for-media-controller-mode-ini.patch
+patches/1304-media-rcar-vin-add-group-allocator-functions.patch
+patches/1305-media-rcar-vin-change-name-of-video-device.patch
+patches/1306-media-rcar-vin-add-chsel-information-to-rvin_info.patch
+patches/1307-media-rcar-vin-parse-Gen3-OF-and-setup-media-graph.patch
+patches/1308-media-rcar-vin-add-link-notify-for-Gen3.patch
+patches/1309-media-rcar-vin-extend-start-stop-_streaming-to-work-.patch
+patches/1310-media-rcar-vin-enable-support-for-r8a7795.patch
+patches/1311-media-rcar-vin-enable-support-for-r8a7796.patch
+patches/1312-media-rcar-vin-enable-support-for-r8a77970.patch
+patches/1313-media-rcar-vin-remove-generic-gen3-compatible-string.patch
+patches/1314-media-rcar-vin-fix-null-pointer-dereference-in-rvin_.patch
+patches/1315-media-rcar-vin-add-support-for-MEDIA_BUS_FMT_UYVY8_1.patch
+patches/1316-media-rcar-vin-enable-field-toggle-after-a-set-numbe.patch
+patches/1317-media-Revert-media-rcar-vin-enable-field-toggle-afte.patch
+patches/1318-media-rcar-vin-fix-crop-and-compose-handling-for-Gen.patch
+patches/1319-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
+patches/1320-media-rcar-csi2-add-Renesas-R-Car-MIPI-CSI-2-receive.patch
+patches/1321-media-rcar-csi2-set-default-format-if-a-unsupported-.patch
+patches/1322-drm-Fix-modifiers_property-kernel-doc.patch
+patches/1323-drm-Add-drm_mode_config-normalize_zpos-boolean.patch
+patches/1324-drm-blend-Add-a-generic-alpha-property.patch
+patches/1325-drm-rcar-du-Let-core-take-care-of-normalizing-the-zp.patch
+patches/1326-drm-rcar-du-Convert-to-the-new-generic-alpha-propert.patch
+patches/1327-drm-rcar-du-Zero-out-sg_tables-when-duplicating-plan.patch
+patches/1328-drm-rcar-du-of-Include-header-to-define-prototypes.patch
+patches/1329-drm-rcar-du-Use-NULL-for-table-initialisation.patch
+patches/1330-dt-bindings-display-renesas-du-Increase-indent-in-ou.patch
+patches/1331-dt-bindings-display-renesas-du-Document-the-r8a77965.patch
+patches/1332-drm-rcar-du-Use-the-correct-naming-for-ODPM-fields-i.patch
+patches/1333-drm-rcar-du-Split-CRTC-handling-to-support-hardware-.patch
+patches/1334-drm-rcar-du-Allow-DU-groups-to-work-with-hardware-in.patch
+patches/1335-drm-rcar-du-Add-R8A77965-support.patch
+patches/1336-drm-rcar-du-Track-dma-buf-fences.patch
+patches/1337-drm-rcar-du-Fix-rcar_du_of_init-stub.patch
+patches/1338-drm-rcar-du-Fix-build-failure.patch
+patches/1339-media-drm-rcar-du-Add-support-for-CRC-computation.patch
+patches/1340-soc-renesas-rcar-sysc-Add-r8a77470-support.patch
+patches/1341-soc-renesas-Add-r8a77990-SYSC-PM-Domain-Binding-Defi.patch
+patches/1342-soc-renesas-r8a77995-sysc-Cleanups.patch
+patches/1343-soc-renesas-rcar-sysc-Add-support-for-R-Car-E3-power.patch
+patches/1344-soc-renesas-r8a77990-sysc-Add-workaround-for-3DG-A-B.patch
+patches/1345-soc-renesas-rcar-sysc-Make-PM-domain-initialization-.patch
+patches/1346-ARM-smp-Add-initialization-of-CNTVOFF.patch
+patches/1347-ARM-Always-build-secure_cntvoff.S-on-ARM-V7-to-fix-s.patch
+patches/1348-ARM-shmobile-r8a77470-basic-SoC-support.patch
+patches/1349-ARM-shmobile-Add-the-RZ-N1-arch-to-the-shmobile-Kcon.patch
+patches/1350-ARM-dts-r7s72100-add-USB-device-to-device-tree.patch
+patches/1351-ARM-dts-r7s72100-add-soc-node.patch
+patches/1352-ARM-dts-r7s72100-sort-subnodes-of-soc-node.patch
+patches/1353-ARM-dts-r7s72100-stop-grouping-clocks-under-a-clocks.patch
+patches/1354-ARM-dts-r7s72100-sort-subnodes-of-root-node.patch
+patches/1355-ARM-dts-r8a77470-Initial-SoC-device-tree.patch
+patches/1356-ARM-dts-iwg23s-sbc-Add-support-for-iWave-G23S-SBC-ba.patch
+patches/1357-dt-bindings-arm-Document-iW-RainboW-G23S-single-boar.patch
+patches/1358-dt-bindings-arm-Document-R-Car-E3-SoC-DT-bindings.patch
+patches/1359-dt-bindings-arm-Document-Renesas-Ebisu-board-DT-bind.patch
+patches/1360-ARM-shmobile-defconfig-Enable-r8a77470-SoC.patch
+patches/1361-ARM-dts-wheat-Fix-ADV7513-address-usage.patch
+patches/1362-ARM-dts-renesas-replace-toshiba-mmc-wrprotect-disabl.patch
+patches/1363-arm-shmobile-Add-the-RZ-N1D-R9A06G032-to-the-shmobil.patch
+patches/1364-ARM-shmobile-defconfig-Disable-CONFIG_FB_SH_MOBILE_M.patch
+patches/1365-ARM-dts-renesas-r8a7791-Add-FDP1-instances.patch
+patches/1366-ARM-dts-renesas-r8a7793-Add-FDP1-instances.patch
+patches/1367-ARM-dts-renesas-r8a7794-Add-FDP1-instances.patch
+patches/1368-ARM-dts-r8a77470-Add-SYS-DMAC-support.patch
+patches/1369-ARM-dts-r8a77470-Add-IRQC-support.patch
+patches/1370-ARM-dts-r7s72100-Add-Capture-Engine-Unit-CEU.patch
+patches/1371-ARM-dts-r8a7743-Adjust-SMP-routine-size.patch
+patches/1372-ARM-dts-r8a7745-Adjust-SMP-routine-size.patch
+patches/1373-ARM-dts-r8a7790-Adjust-SMP-routine-size.patch
+patches/1374-ARM-dts-r8a7791-Adjust-SMP-routine-size.patch
+patches/1375-ARM-dts-r8a7792-Adjust-SMP-routine-size.patch
+patches/1376-ARM-dts-r8a7793-Adjust-SMP-routine-size.patch
+patches/1377-ARM-dts-r8a7794-Adjust-SMP-routine-size.patch
+patches/1378-ARM-dts-r8a7743-Add-watchdog-support-to-SoC-dtsi.patch
+patches/1379-ARM-dts-r8a7745-Add-watchdog-support-to-SoC-dtsi.patch
+patches/1380-ARM-dts-r8a7790-Add-watchdog-support-to-SoC-dtsi.patch
+patches/1381-ARM-dts-r8a7791-Add-watchdog-support-to-SoC-dtsi.patch
+patches/1382-ARM-dts-r8a7794-Add-watchdog-support-to-SoC-dtsi.patch
+patches/1383-ARM-dts-iwg20m-Add-watchdog-support-to-SoM-dtsi.patch
+patches/1384-ARM-dts-iwg22m-Add-watchdog-support-to-SoM-dtsi.patch
+patches/1385-ARM-dts-r8a7792-Add-RWDT-node.patch
+patches/1386-ARM-dts-r8a7793-Add-RWDT-node.patch
+patches/1387-ARM-dts-lager-Enable-watchdog-support.patch
+patches/1388-ARM-dts-koelsch-Enable-watchdog-support.patch
+patches/1389-ARM-dts-porter-Enable-watchdog-support.patch
+patches/1390-ARM-dts-blanche-Enable-watchdog-support.patch
+patches/1391-ARM-dts-wheat-Enable-watchdog-support.patch
+patches/1392-ARM-dts-gose-Enable-watchdog-support.patch
+patches/1393-ARM-dts-alt-Enable-watchdog-support.patch
+patches/1394-ARM-dts-silk-Enable-watchdog-support.patch
+patches/1395-ARM-dts-r8a77470-Add-SCIF-support.patch
+patches/1396-ARM-dts-r8a77470-Add-SCIF-DMA-support.patch
+patches/1397-ARM-dts-renesas-r8a7790-Add-FDP1-instances.patch
+patches/1398-ARM-dts-r8a77470-Add-EtherAVB-support.patch
+patches/1399-ARM-dts-iwg23s-sbc-Add-EtherAVB-support.patch
+patches/1400-ARM-dts-r8a7790-Fix-sort-order-of-VSP1-FDP1-nodes.patch
+patches/1401-dt-bindings-arm-consistently-name-r8a77965-as-M3-N.patch
+patches/1402-ARM-dts-lager-Drop-unnecessary-address-properties-fr.patch
+patches/1403-ARM-dts-porter-Drop-unnecessary-address-properties-f.patch
+patches/1404-ARM-dts-gose-Drop-unnecessary-address-properties-fro.patch
+patches/1405-ARM-dts-koelsch-Drop-unnecessary-address-properties-.patch
+patches/1406-ARM-dts-alt-Drop-unnecessary-address-properties-from.patch
+patches/1407-ARM-dts-silk-Drop-unnecessary-address-properties-fro.patch
+patches/1408-ARM-dts-kzm9d-Drop-unnecessary-address-properties-fr.patch
+patches/1409-ARM-shmobile-Convert-file-to-use-cntvoff.patch
+patches/1410-ARM-shmobile-r8a7794-alt-add-EEPROM-to-DTS.patch
+patches/1411-ARM-dts-r8a7790-Correct-mask-for-GIC-PPI-interrupts.patch
+patches/1412-ARM-dts-r8a73a4-Correct-mask-for-GIC-PPI-interrupts.patch
+patches/1413-ARM-dts-r7s72100-Correct-watchdog-timer-interrupt-ty.patch
+patches/1414-ARM-dts-r7s72100-Correct-RTC-interrupt-types.patch
+patches/1415-ARM-dts-r7s72100-Add-PMU-device-node.patch
+patches/1416-ARM-dts-r8a7790-Add-PMU-device-nodes.patch
+patches/1417-ARM-dts-r8a7791-Add-PMU-device-node.patch
+patches/1418-ARM-dts-r8a7792-Add-PMU-device-node.patch
+patches/1419-ARM-dts-r8a7793-Add-PMU-device-node.patch
+patches/1420-ARM-dts-r8a7794-Add-PMU-device-node.patch
+patches/1421-ARM-dts-r8a7743-Add-PMU-device-node.patch
+patches/1422-ARM-dts-r8a7745-Add-PMU-device-node.patch
+patches/1423-dt-bindings-arm-document-Renesas-V3HSK-board-binding.patch
+patches/1424-ARM-dts-r8a7740-Add-CEU0.patch
+patches/1425-ARM-dts-r8a7740-Add-CEU1.patch
+patches/1426-ARM-shmobile-defconfig-Enable-RENESAS_WDT_GEN.patch
+patches/1427-PCI-rcar-Use-runtime-PM-to-control-controller-clock.patch
+patches/1428-PCI-rcar-Clean-up-the-macros.patch
+patches/1429-PCI-rcar-Poll-PHYRDY-in-rcar_pcie_hw_init.patch
+patches/1430-PCI-rcar-Remove-PHYRDY-polling-from-rcar_pcie_hw_ini.patch
+patches/1431-PCI-rcar-Add-R-Car-gen3-PHY-support.patch
+patches/1432-PCI-rcar-Factor-out-rcar_pcie_hw_init-call.patch
+patches/1433-DT-pci-rcar-pci-document-R8A77980-bindings.patch
+patches/1434-PCI-rcar-Reuse-generic-pci_parse_request_of_pci_rang.patch
+patches/1435-PCI-rcar-Poll-more-often-in-rcar_pcie_wait_for_dl.patch
+patches/1436-PCI-rcar-Pull-bus-clock-enable-disable-from-rcar_pci.patch
+patches/1437-PCI-rcar-Add-missing-irq_dispose_mapping-into-failpa.patch
+patches/1438-PCI-rcar-Teardown-MSI-setup-if-rcar_pcie_enable-fail.patch
+patches/1439-PCI-rcar-Remove-IRQ-mappings-in-rcar_pcie_enable_msi.patch
+patches/1440-xhci-Create-new-structures-to-store-xhci-port-inform.patch
+patches/1441-xhci-set-hcd-pointers-for-xhci-usb2-and-usb3-roothub.patch
+patches/1442-xhci-Add-helper-to-get-xhci-roothub-from-hcd.patch
+patches/1443-xhci-xhci-hub-use-new-port-structures-to-get-port-ad.patch
+patches/1444-xhci-xhci-hub-use-new-port-structures-for-cas-and-wa.patch
+patches/1445-xhci-xhci-ring-use-port-structures-for-port-event-ha.patch
+patches/1446-xhci-rename-faked_port_index-to-hcd_portnum.patch
+patches/1447-xhci-change-xhci_set_link_state-to-work-with-port-st.patch
+patches/1448-xhci-change-xhci_test_and_clear_bit-to-use-new-port-.patch
+patches/1449-xhci-use-port-structures-instead-of-port-arrays-in-x.patch
+patches/1450-xhci-xhci-hub-use-port-structure-members-instead-of-.patch
+patches/1451-usb-xhci-force-all-memory-allocations-to-node.patch
+patches/1452-xhci-Allow-more-than-32-quirks.patch
+patches/1453-xhci-Add-quirk-to-zero-64bit-registers-on-Renesas-PC.patch
+patches/1454-xhci-Fix-perceived-dead-host-due-to-runtime-suspend-.patch
+patches/1455-drm-shmobile-remove-unused-MERAM-support.patch
+patches/1456-video-fbdev-sh_mobile_lcdcfb-remove-unused-MERAM-sup.patch
+patches/1457-video-fbdev-remove-unused-sh_mobile_meram-driver.patch
+patches/1458-arm64-dts-renesas-r8a77965-add-usb2_phy-nodes.patch
+patches/1459-arm64-dts-renesas-r8a77965-add-usb3_phy-node.patch
+patches/1460-arm64-dts-renesas-r8a77965-add-USB-2.0-host-nodes.patch
+patches/1461-arm64-dts-renesas-r8a77965-add-usb_dmac-nodes.patch
+patches/1462-arm64-dts-renesas-r8a77965-add-HS-USB-node.patch
+patches/1463-arm64-dts-renesas-r8a77965-add-USB-3.0-host-node.patch
+patches/1464-arm64-dts-renesas-r8a77965-add-USB-3.0-peripheral-no.patch
+patches/1465-arm64-dts-renesas-r8a77970-Update-IPMMU-DS1-bit-numb.patch
+patches/1466-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-root-.patch
+patches/1467-arm64-dts-renesas-r8a7796-sort-subnodes-of-the-soc-n.patch
+patches/1468-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-root-.patch
+patches/1469-arm64-dts-renesas-r8a7795-sort-subnodes-of-the-soc-n.patch
+patches/1470-arm64-dts-renesas-r8a77965-Add-all-MSIOF-device-node.patch
+patches/1471-arm64-dts-renesas-r8a77965-Add-PWM-device-nodes.patch
+patches/1472-arm64-dts-renesas-r8a77970-add-FCPVD-support.patch
+patches/1473-arm64-defconfig-makes-SND_SIMPLE_CARD-to-module.patch
+patches/1474-arm64-defconfig-Enable-CONFIG_SND_AUDIO_GRAPH_CARD.patch
+patches/1475-arm64-dts-renesas-r8a7795-decrease-temperature-hyste.patch
+patches/1476-arm64-dts-renesas-r8a7796-decrease-temperature-hyste.patch
+patches/1477-arm64-dts-renesas-r8a77970-add-VSPD-support.patch
+patches/1478-arm64-dts-renesas-r8a77970-add-DU-support.patch
+patches/1479-arm64-dts-renesas-r8a77970-add-LVDS-support.patch
+patches/1480-arm64-dts-renesas-eagle-Enable-HDMI-output.patch
+patches/1481-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-root.patch
+patches/1482-arm64-dts-renesas-r8a77995-sort-subnodes-of-the-soc-.patch
+patches/1483-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-root.patch
+patches/1484-arm64-dts-renesas-r8a77965-sort-subnodes-of-the-soc-.patch
+patches/1485-arm64-dts-renesas-r8a77970-sort-subnodes-of-the-soc-.patch
+patches/1486-arm64-dts-renesas-Add-Renesas-R8A77990-SoC-support.patch
+patches/1487-arm64-dts-renesas-Add-Renesas-Ebisu-board-support.patch
+patches/1488-arm64-dts-renesas-r8a7795-Enable-IPMMU-devices.patch
+patches/1489-arm64-dts-renesas-r8a7796-Enable-IPMMU-devices.patch
+patches/1490-arm64-dts-renesas-r8a77970-Enable-IPMMU-devices.patch
+patches/1491-arm64-dts-renesas-r8a77995-Enable-IPMMU-devices.patch
+patches/1492-arm64-dts-renesas-draak-Rename-EtherAVB-mdc-pin-grou.patch
+patches/1493-arm64-dts-renesas-salvator-common-Rename-EtherAVB-md.patch
+patches/1494-arm64-dts-renesas-ulcb-Rename-EtherAVB-mdc-pin-group.patch
+patches/1495-arm64-dts-renesas-eagle-add-EtherAVB-pins.patch
+patches/1496-arm64-dts-renesas-v3msk-add-EtherAVB-pins.patch
+patches/1497-arm64-dts-renesas-r8a77980-add-PFC-support.patch
+patches/1498-arm64-dts-renesas-condor-add-SCIF0-pins.patch
+patches/1499-arm64-dts-renesas-condor-add-EtherAVB-pins.patch
+patches/1500-arm64-dts-renesas-r8a77980-add-MMC-support.patch
+patches/1501-arm64-dts-renesas-r8a7795-add-HDMI-sound-support.patch
+patches/1502-arm64-dts-renesas-r8a7796-add-HDMI-sound-support.patch
+patches/1503-arm64-dts-renesas-r8a7795-es1-salvator-x-enable-HDMI.patch
+patches/1504-arm64-dts-renesas-r8a7795-salvator-xs-enable-HDMI-so.patch
+patches/1505-arm64-dts-renesas-r8a7796-salvator-xs-enable-HDMI-so.patch
+patches/1506-arm64-dts-renesas-r8a7795-salvator-x-enable-HDMI-sou.patch
+patches/1507-arm64-dts-renesas-r8a7796-salvator-x-enable-HDMI-sou.patch
+patches/1508-arm64-dts-renesas-r8a7795-es1-Enable-IPMMU-devices.patch
+patches/1509-arm64-dts-renesas-r8a77990-Revise-the-psci-node.patch
+patches/1510-arm64-dts-renesas-r8a77990-Revise-the-cache-controll.patch
+patches/1511-arm64-dts-renesas-r8a77965-Add-FCPF-and-FCPV-instanc.patch
+patches/1512-arm64-dts-renesas-r8a77965-Add-VSP-instances.patch
+patches/1513-arm64-dts-renesas-r8a77965-Populate-the-DU-instance-.patch
+patches/1514-arm64-dts-renesas-r8a77965-Add-HDMI-encoder-instance.patch
+patches/1515-arm64-dts-renesas-r8a77965-salvator-x-Enable-DU-exte.patch
+patches/1516-arm64-dts-renesas-r8a77965-salvator-xs-Enable-DU-ext.patch
+patches/1517-arm64-dts-renesas-condor-add-eMMC-support.patch
+patches/1518-arm64-dts-renesas-v3msk-add-DU-LVDS-HDMI-support.patch
+patches/1519-arm64-dts-renesas-r8a7795-Add-address-properties-to-.patch
+patches/1520-arm64-dts-renesas-r8a7796-Add-address-properties-to-.patch
+patches/1521-arm64-dts-renesas-r8a77965-Add-address-properties-to.patch
+patches/1522-arm64-dts-renesas-r8a77980-use-CPG-core-clock-macros.patch
+patches/1523-arm64-dts-renesas-r8a77980-use-SYSC-power-domain-mac.patch
+patches/1524-arm64-dts-renesas-r8a77965-use-r8a77965-sysc-binding.patch
+patches/1525-arm64-dts-renesas-r8a77965-Add-R-Car-Gen3-thermal-su.patch
+patches/1526-arm64-dts-renesas-r8a77970-add-CAN-FD-support.patch
+patches/1527-arm64-dts-renesas-eagle-add-CAN-FD-support.patch
+patches/1528-arm64-dts-renesas-r8a77980-add-CAN-FD-support.patch
+patches/1529-arm64-dts-renesas-condor-add-CAN-FD-support.patch
+patches/1530-arm64-dts-renesas-salvator-common-add-eeprom.patch
+patches/1531-arm64-dts-renesas-r8a7795-salvator-xs-enable-usb2_ph.patch
+patches/1532-arm64-dts-renesas-r8a7795-salvator-xs-enable-hsusb-c.patch
+patches/1533-arm64-dts-renesas-r8a7795-salvator-xs-enable-USB2.0-.patch
+patches/1534-arm64-dts-renesas-r8a7795-Correct-whitespace.patch
+patches/1535-arm64-dts-renesas-r8a7796-Correct-whitespace.patch
+patches/1536-arm64-dts-renesas-r8a77965-Correct-whitespace.patch
+patches/1537-arm64-dts-renesas-ulcb-Add-BD9571-PMIC.patch
+patches/1538-arm64-dts-renesas-salvator-common-Add-PMIC-DDR-Backu.patch
+patches/1539-arm64-dts-renesas-ulcb-Add-PMIC-DDR-Backup-Power-con.patch
+patches/1540-arm64-dts-renesas-r8a77965-Add-SDHI-device-nodes.patch
+patches/1541-arm64-dts-renesas-r8a77970-Add-secondary-CA53-CPU-co.patch
+patches/1542-arm64-dts-renesas-r8a77970-Add-Cortex-A53-PMU-node.patch
+patches/1543-arm64-dts-renesas-r8a77980-add-resets-property-to-CA.patch
+patches/1544-arm64-dts-renesas-r8a77995-Add-VIN4.patch
+patches/1545-arm64-dts-renesas-r8a77970-disable-EtherAVB.patch
+patches/1546-arm64-dts-renesas-r8a77980-disable-EtherAVB.patch
+patches/1547-arm64-dts-renesas-initial-V3HSK-board-device-tree.patch
+patches/1548-arm64-dts-renesas-r8a77990-Add-PFC-device-node.patch
+patches/1549-arm64-dts-renesas-r8a77990-Add-GPIO-device-nodes.patch
+patches/1550-arm64-dts-renesas-r8a77990-Add-EthernetAVB-device-no.patch
+patches/1551-arm64-dts-renesas-r8a77990-ebisu-Enable-EthernetAVB.patch
+patches/1552-arm64-dts-renesas-r8a77965-add-I2C-support.patch
+patches/1553-arm64-dts-renesas-r8a7795-add-VIN-and-CSI-2-nodes.patch
+patches/1554-arm64-dts-renesas-r8a7795-es1-add-CSI-2-node.patch
+patches/1555-arm64-dts-renesas-r8a7796-add-VIN-and-CSI-2-nodes.patch
+patches/1556-arm64-dts-renesas-r8a77965-add-VIN-and-CSI-2-nodes.patch
+patches/1557-arm64-dts-renesas-r8a77970-add-VIN-and-CSI-2-nodes.patch
+patches/1558-arm64-dts-renesas-salvator-common-enable-VIN.patch
+patches/1559-arm64-defconfig-enable-R8A77990-SoC.patch
+patches/1560-arm64-dts-renesas-salvator-common-Add-ADV7482-suppor.patch
+patches/1561-arm64-dts-renesas-Add-Renesas-R8A77990-Kconfig-suppo.patch
+patches/1562-PCI-rcar-Shut-the-PHY-down-in-failpath.patch
+patches/1563-PCI-rcar-Clean-up-PHY-init-on-failure.patch
+patches/1564-media-renesas-ceu-Set-mbus_fmt-on-subdev-operations.patch
+patches/1565-media-dt-bindings-media-renesas-ceu-Add-R-Mobile-R8A.patch
+patches/1566-media-renesas-ceu-fix-compiler-warning.patch
+patches/1567-mmc-renesas_sdhi_internal_dmac-Fix-missing-unmap-in-.patch
+patches/1568-mmc-renesas_sdhi_internal_dmac-Cannot-clear-the-RX_I.patch
+patches/1569-ravb-simplify-link-auto-negotiation-by-ethtool.patch
+patches/1570-ravb-remove-custom-.nway_reset-from-ethtool-ops.patch
+patches/1571-ravb-remove-useless-serialization-in-ravb_get_link_k.patch
+patches/1572-ravb-remove-custom-.get_link_ksettings-from-ethtool-.patch
+patches/1573-ravb-remove-custom-.set_link_ksettings-from-ethtool-.patch
+patches/1574-sh_eth-simplify-link-auto-negotiation-by-ethtool.patch
+patches/1575-sh_eth-remove-custom-.nway_reset-from-ethtool-ops.patch
+patches/1576-sh_eth-remove-useless-serialization-in-sh_eth_get_li.patch
+patches/1577-sh_eth-remove-custom-.get_link_ksettings-from-ethtoo.patch
+patches/1578-sh_eth-remove-custom-.set_link_ksettings-from-ethtoo.patch
+patches/1579-pinctrl-sh-pfc-r8a77970-remove-SH_PFC_PIN_CFG_DRIVE_.patch
+patches/1580-gpio-pca953x-Use-of_device_get_match_data.patch
+patches/1581-gpio-pca953x-convert-register-constants-to-hex.patch
+patches/1582-gpio-pca953x-add-more-register-definitions-for-pcal9.patch
+patches/1583-gpio-pca953x-add-more-register-definitions-for-pcal6.patch
+patches/1584-DTS-Bindings-pca953x-add-an-optional-vcc-supply-prop.patch
+patches/1585-pca953x-add-example-how-to-use-interrupt-controller-.patch
+patches/1586-gpio-pca953x-Clear-irq-trigger-type-on-irq-shutdown.patch
+patches/1587-gpio-pca953x-set-the-PCA_PCAL-flag-also-when-matchin.patch
+patches/1588-gpio-pca953x-define-masks-for-addressing-common-and-.patch
+patches/1589-gpio-pca953x-fix-address-calculation-for-pcal6524.patch
+patches/1590-gpio-pca953x-Include-the-right-header.patch
+patches/1591-usb-xhci-Fix-memory-leak-in-xhci_endpoint_reset.patch
+patches/1592-media-v4l-vsp1-Fix-deadlock-in-VSPDL-DRM-pipelines.patch
+patches/1593-dt-bindings-gpio-rcar-Add-r8a77470-RZ-G1C-support.patch
+patches/1594-dt-bindings-gpio-Add-support-for-r8a77965.patch
+patches/1595-gpio-rcar-Add-DT-binding-for-r8a77990.patch
+patches/1596-clk-renesas-r8a77965-Add-MSIOF-controller-clocks.patch
+patches/1597-clk-renesas-Add-r8a77470-CPG-Core-Clock-Definitions.patch
+patches/1598-clk-renesas-cpg-mssr-Add-r8a77470-support.patch
+patches/1599-clk-renesas-r8a7743-Fix-LB-clock-divider.patch
+patches/1600-clk-renesas-r8a7745-Fix-LB-clock-divider.patch
+patches/1601-clk-renesas-r8a7791-r8a7793-Fix-LB-clock-divider.patch
+patches/1602-clk-renesas-r8a7792-Fix-LB-clock-divider.patch
+patches/1603-clk-renesas-r8a7794-Fix-LB-clock-divider.patch
+patches/1604-clk-renesas-r8a77980-Correct-parent-clock-of-PCIEC0.patch
+patches/1605-clk-renesas-rcar-gen2-Centralize-quirks-handling.patch
+patches/1606-clk-renesas-Add-r8a77990-CPG-Core-Clock-Definitions.patch
+patches/1607-clk-renesas-cpg-mssr-Add-support-for-R-Car-E3.patch
+patches/1608-i2c-recovery-if-possible-send-STOP-with-recovery-pul.patch
+patches/1609-i2c-rcar-enhance-comment-to-avoid-regressions.patch
+patches/1610-i2c-rcar-document-R8A77980-bindings.patch
+patches/1611-i2c-rcar-handle-RXDMA-HW-behaviour-on-Gen3.patch
+patches/1612-dmaengine-rcar-dmac-Document-R8A77990-bindings.patch
+patches/1613-dmaengine-rcar-dmac-don-t-use-DMAC-error-interrupt.patch
+patches/1614-dmaengine-rcar-dmac-convert-to-SPDX-identifiers.patch
+patches/1615-dmaengine-rcar-dmac-Disable-interrupts-while-stoppin.patch
+patches/1616-dmaengine-rcar-dmac-clear-channel-register-when-erro.patch
+patches/1617-dmaengine-sh-rcar-dmac-avoid-to-write-CHCR.TE-to-1-i.patch
+patches/1618-dmaengine-sh-rcar-dmac-add-a-new-function-to-clear-C.patch
+patches/1619-dmaengine-sh-rcar-dmac-Add-dma_pause-operation.patch
+patches/1620-dmaengine-sh-rcar-dmac-Should-not-stop-the-DMAC-by-r.patch
+patches/1621-thermal-rcar_thermal-avoid-NULL-dereference-in-absen.patch
+patches/1622-usb-gadget-udc-renesas_usb3-Add-register-of-usb-role.patch
+patches/1623-i2c-recovery-require-either-get_sda-or-set_sda.patch
+patches/1624-i2c-recovery-refactor-recovery-function.patch
+patches/1625-i2c-recovery-add-get_bus_free-callback.patch
+patches/1626-i2c-recovery-rename-variable-for-easier-understandin.patch
+patches/1627-i2c-recovery-make-pin-init-look-like-STOP.patch
+patches/1628-i2c-rcar-use-the-new-get_bus_free-callback.patch
+patches/1629-clk-socfpga-stratix10-add-clock-driver-for-Stratix10.patch
+patches/1630-clk-socfpga-stratix10-use-platform-driver-APIs.patch
+patches/1631-clk-socfpga-stratix10-suppress-unbinding-platform-s-.patch
+patches/1632-clk-socfpga-stratix10-fix-the-parents-of-mpu_free_cl.patch
+patches/1633-clk-socfpga-stratix10-fix-the-sdmmc_free_clk-mux.patch
+patches/1634-arm64-dts-stratix10-fix-up-the-gic-register-for-the-.patch
+patches/1635-arm64-dts-stratix10-add-ethernet-sdmmc-support-to-th.patch
+patches/1636-arm64-dts-stratix10-include-the-reset-manager-bindin.patch
+patches/1637-arm64-dts-stratix10-add-the-altr-modrst-off-property.patch
+patches/1638-arm64-dts-stratix10-add-reset-property-for-various-p.patch
+patches/1639-arm64-dts-stratix10-add-gpio-header.patch
+patches/1640-arm64-dts-stratix10-enable-gpio-and-leds.patch
+patches/1641-arm64-dts-stratix10-fix-interrupt-number-for-gpio1.patch
+patches/1642-arm64-dts-socfpga-add-missing-interrupt-parent.patch
+patches/1643-arm64-dts-stratix10-enable-USB-on-the-devkit.patch
+patches/1644-arm64-dts-stratix10-add-USB-ECC-reset-bit.patch
+patches/1645-arm64-dts-stratix10-fix-SPI-settings.patch
+patches/1646-arm64-dts-stratix10-remove-num-slots-property-for-dw.patch
+patches/1647-arm64-dts-stratix10-enable-watchdog-timer-on-the-S10.patch
+patches/1648-arm64-dts-stratix10-disable-false-USB-overcurrent-on.patch
+patches/1649-arm64-dts-stratix10-use-clock-bindings-for-the-Strat.patch
+patches/1650-arm64-dts-stratix10-enable-i2c-add-i2c-periperals.patch
+patches/1651-arm64-dts-stratix10-Add-PL330-DMAC-to-Stratix10-dts.patch
+patches/1652-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch
+patches/1653-arm64-dts-stratix10-add-sdram-ecc.patch
+patches/1654-arm64-dts-stratix10-Fix-SPI-nodes-for-Stratix10.patch
+patches/1655-arm64-dts-stratix10-Add-QSPI-support-for-Stratix10.patch
+patches/1656-arm64-dts-stratix10-fill-in-clocks-field-for-usb-and.patch
+patches/1657-arm64-dts-stratix10-add-OCP-reset-property-for-ether.patch
+patches/1658-arm64-dts-stratix10-Add-SPI-node-clocks-for-Stratix1.patch
+patches/1659-MAINTAINERS-add-backup-FPGA-maintainer.patch
+patches/1660-fpga-bridge-support-getting-bridge-from-device.patch
+patches/1661-fpga-mgr-API-change-to-replace-fpga-load-functions-w.patch
+patches/1662-fpga-mgr-separate-getting-locking-FPGA-manager.patch
+patches/1663-fpga-region-use-dev_err-instead-of-pr_err.patch
+patches/1664-fpga-region-remove-unneeded-of_node_get-and-put.patch
+patches/1665-fpga-region-get-mgr-early-on.patch
+patches/1666-fpga-region-check-for-child-regions-before-allocing-.patch
+patches/1667-fpga-region-fix-slow-warning-with-more-than-one-over.patch
+patches/1668-fpga-region-use-image-info-as-parameter-for-programm.patch
+patches/1669-fpga-region-separate-out-code-that-parses-the-overla.patch
+patches/1670-fpga-region-add-fpga-region.h-header.patch
+patches/1671-fpga-region-rename-some-functions-prior-to-moving.patch
+patches/1672-fpga-region-add-register-unregister-functions.patch
+patches/1673-fpga-region-add-fpga_region_class_find.patch
+patches/1674-fpga-region-move-device-tree-support-to-of-fpga-regi.patch
+patches/1675-fpga-of-fpga-region-accept-overlays-that-don-t-progr.patch
+patches/1676-fpga-clean-up-fpga-Kconfig.patch
+patches/1677-fpga-add-attribute-groups.patch
+patches/1678-fpga-fpga-mgr-remove-unnecessary-code-in-__fpga_mgr_.patch
+patches/1679-fpga-fpga-bridge-remove-unnecessary-null-check-in-of.patch
+patches/1680-fpga-region-release-of_parse_phandle-nodes-after-use.patch
+patches/1681-fpga-socfpga-a10-disable-clk-on-error-in-socfpga_a10.patch
+patches/1682-PCI-Add-Altera-vendor-ID.patch
+patches/1683-fpga-Remove-depends-on-HAS_DMA-in-case-of-platform-d.patch
+patches/1684-fpga-lattice-machxo2-Add-Lattice-MachXO2-support.patch
+patches/1685-fpga-fpga-region-comment-on-fpga_region_program_fpga.patch
+patches/1686-fpga-region-don-t-use-drvdata-in-common-fpga-code.patch
+patches/1687-fpga-manager-change-api-don-t-use-drvdata.patch
+patches/1688-fpga-bridge-change-api-don-t-use-drvdata.patch
+patches/1689-fpga-region-change-api-add-fpga_region_create-free.patch
+patches/1690-fpga-use-SPDX.patch
+patches/1691-fpga-mgr-kernel-doc-fixes.patch
+patches/1692-fpga-bridge-kernel-doc-fixes.patch
+patches/1693-fpga-region-kernel-doc-fixes.patch
+patches/1694-dt-bindings-documentation-add-clock-bindings-informa.patch
+patches/1695-Documentation-fpga-move-fpga-overview-to-driver-api.patch
+patches/1696-documentation-fpga-move-fpga-mgr.txt-to-driver-api.patch
+patches/1697-documentation-fpga-add-bridge-document-to-driver-api.patch
+patches/1698-documentation-fpga-move-fpga-region.txt-to-driver-ap.patch
+patches/1699-fpga-clarify-that-unregister-functions-also-free.patch
+patches/1700-MAINTAINERS-Add-driver-api-fpga-path.patch
+patches/1701-fpga-altera-cvp-Fix-an-error-handling-path-in-altera.patch
+patches/1702-Documentation-fpga-cleanup.patch
+patches/1703-fpga-mgr-add-region_id-to-fpga_image_info.patch
+patches/1704-fpga-mgr-add-status-for-fpga-manager.patch
+patches/1705-fpga-mgr-add-compat_id-support.patch
+patches/1706-fpga-region-add-compat_id-support.patch
+patches/1707-fpga-add-device-feature-list-support.patch
+patches/1708-fpga-dfl-add-chardev-support-for-feature-devices.patch
+patches/1709-fpga-dfl-add-dfl_fpga_cdev_find_port.patch
+patches/1710-fpga-dfl-add-feature-device-infrastructure.patch
+patches/1711-fpga-dfl-add-dfl_fpga_port_ops-support.patch
+patches/1712-fpga-dfl-add-dfl_fpga_check_port_id-function.patch
+patches/1713-fpga-add-FPGA-DFL-PCIe-device-driver.patch
+patches/1714-fpga-dfl-pci-add-enumeration-for-feature-devices.patch
+patches/1715-fpga-dfl-add-FPGA-Management-Engine-driver-basic-fra.patch
+patches/1716-fpga-dfl-fme-add-header-sub-feature-support.patch
+patches/1717-fpga-dfl-fme-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
+patches/1718-fpga-dfl-fme-add-partial-reconfiguration-sub-feature.patch
+patches/1719-fpga-dfl-add-fpga-manager-platform-driver-for-FME.patch
+patches/1720-fpga-dfl-fme-mgr-add-compat_id-support.patch
+patches/1721-fpga-dfl-add-fpga-bridge-platform-driver-for-FME.patch
+patches/1722-fpga-dfl-add-fpga-region-platform-driver-for-FME.patch
+patches/1723-fpga-dfl-fme-region-add-support-for-compat_id.patch
+patches/1724-fpga-dfl-add-FPGA-Accelerated-Function-Unit-driver-b.patch
+patches/1725-fpga-dfl-afu-add-port-ops-support.patch
+patches/1726-fpga-dfl-afu-add-header-sub-feature-support.patch
+patches/1727-fpga-dfl-afu-add-DFL_FPGA_GET_API_VERSION-CHECK_EXTE.patch
+patches/1728-fpga-dfl-afu-add-afu-sub-feature-support.patch
+patches/1729-fpga-dfl-afu-add-DFL_FPGA_PORT_DMA_MAP-UNMAP-ioctls-.patch
+patches/1730-MAINTAINERS-add-entry-for-FPGA-DFL-drivers.patch
+patches/1731-dt-bindings-fpga-add-lattice-machxo2-slave-spi-bindi.patch
+patches/1732-fpga-make-xlnx_pr_decoupler_br_ops-const.patch
+patches/1733-nios2-kconfig-Remove-blank-help-text.patch
+patches/1734-nios2-dts-Remove-leading-0x-and-0s-from-bindings-not.patch
+patches/1735-nios2-defconfig-Cleanup-from-old-Kconfig-options.patch
+patches/1736-nios2-add-ioremap_nocache-declaration-before-include.patch
+patches/1737-nios2-Use-read_persistent_clock64-instead-of-read_pe.patch
+patches/1738-usb-dwc2-add-optional-usb-ecc-reset-bit.patch
+patches/1739-reset-socfpga-build-the-reset-socfpga-for-Stratix10-.patch
+patches/1740-i2c-rcar-refactor-private-flags.patch
+patches/1741-i2c-rcar-implement-STOP-and-REP_START-according-to-d.patch
+patches/1742-tracing-Remove-redundant-unread-variable-ret.patch
+patches/1743-tracing-Clean-up-hist_field_flags-enum.patch
+patches/1744-tracing-Add-hist_field_name-accessor.patch
+patches/1745-tracing-Reimplement-log2.patch
+patches/1746-tracing-Remove-code-which-merges-duplicates.patch
+patches/1747-tracing-Give-event-triggers-access-to-ring_buffer_ev.patch
+patches/1748-tracing-Add-ring-buffer-event-param-to-hist-field-fu.patch
+patches/1749-tracing-Break-out-hist-trigger-assignment-parsing.patch
+patches/1750-ring-buffer-Rewrite-trace_recursive_-un-lock-to-be-s.patch
+patches/1751-ring-buffer-Bring-back-context-level-recursive-check.patch
+patches/1752-ring-buffer-Fix-duplicate-results-in-mapping-context.patch
+patches/1753-ring-buffer-Add-interface-for-setting-absolute-time-.patch
+patches/1754-ring-buffer-Redefine-the-unimplemented-RINGBUF_TYPE_.patch
+patches/1755-tracing-Add-hist-trigger-timestamp-support.patch
+patches/1756-tracing-Add-hist_data-member-to-hist_field.patch
+patches/1757-tracing-Move-hist-trigger-Documentation-to-histogram.patch
+patches/1758-tracing-Add-Documentation-for-log2-modifier.patch
+patches/1759-tracing-Add-usecs-modifier-for-hist-trigger-timestam.patch
+patches/1760-tracing-Add-per-element-variable-support-to-tracing_.patch
+patches/1761-tracing-Add-variable-support-to-hist-triggers.patch
+patches/1762-tracing-Account-for-variables-in-named-trigger-compa.patch
+patches/1763-tracing-Move-get_hist_field_flags.patch
+patches/1764-tracing-Add-simple-expression-support-to-hist-trigge.patch
+patches/1765-tracing-Generalize-per-element-hist-trigger-data.patch
+patches/1766-tracing-Pass-tracing_map_elt-to-hist_field-accessor-.patch
+patches/1767-tracing-Add-hist_field-type-field.patch
+patches/1768-tracing-Add-variable-reference-handling-to-hist-trig.patch
+patches/1769-tracing-Add-hist-trigger-action-hook.patch
+patches/1770-tracing-Make-traceprobe-parsing-code-reusable.patch
+patches/1771-tracing-Add-support-for-synthetic-events.patch
+patches/1772-tracing-Add-support-for-field-variables.patch
+patches/1773-tracing-Add-onmatch-hist-trigger-action-support.patch
+patches/1774-tracing-Add-onmax-hist-trigger-action-support.patch
+patches/1775-tracing-Allow-whitespace-to-surround-hist-trigger-fi.patch
+patches/1776-tracing-Add-cpu-field-for-hist-triggers.patch
+patches/1777-tracing-Add-hist-trigger-support-for-variable-refere.patch
+patches/1778-tracing-Add-last-error-error-facility-for-hist-trigg.patch
+patches/1779-tracing-Add-inter-event-hist-trigger-Documentation.patch
+patches/1780-tracing-Make-tracing_set_clock-non-static.patch
+patches/1781-tracing-Add-a-clock-attribute-for-hist-triggers.patch
+patches/1782-ring-buffer-Add-nesting-for-adding-events-within-eve.patch
+patches/1783-tracing-Use-the-ring-buffer-nesting-to-allow-synthet.patch
+patches/1784-tracing-Fix-a-potential-NULL-dereference.patch
+patches/1785-tracing-Fix-display-of-hist-trigger-expressions-cont.patch
+patches/1786-tracing-Don-t-add-flag-strings-when-displaying-varia.patch
+patches/1787-tracing-Add-action-comparisons-when-testing-matching.patch
+patches/1788-tracing-Make-sure-variable-string-fields-are-NULL-te.patch
+patches/1789-tracing-Uninitialized-variable-in-create_tracing_map.patch
+patches/1790-tracing-Restore-proper-field-flag-printing-when-disp.patch
+patches/1791-tracing-Add-field-parsing-hist-error-for-hist-trigge.patch
+patches/1792-tracing-Add-field-modifier-parsing-hist-error-for-hi.patch
+patches/1793-tracing-Add-__find_event_file-to-find-event-files-wi.patch
+patches/1794-tracing-Allow-histogram-triggers-to-access-ftrace-in.patch
+patches/1795-tracing-Fix-code-comments-in-trace.c.patch
+
+