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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-26 18:42:48 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:18:23 +0100 |
| commit | 4917409d61a7351fb19c283cf30bcbde95ccfc76 (patch) | |
| tree | f849226138762ee51e54780f301a08c0c4e1b88e | |
| parent | 7ca998978cb8aaf64b69dd0c8ca86867f4cfe1a3 (diff) | |
| download | linux-cip-4917409d61a7351fb19c283cf30bcbde95ccfc76.tar.gz | |
ARM: dts: r8a7743: Add Inter Connect RAM
RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 06278baa1b08f2b2ae26d5b2394b779ed82f3dfa)
(sorted icram nodes)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 551ce1c15cf7e0..c13802718a4aef 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -268,6 +268,21 @@ }; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |