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| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-07-26 15:28:06 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:06:51 +0100 |
| commit | 3b5e9d5243f90d022ba9f5e6e9cf049dfe41d7f0 (patch) | |
| tree | a646bc9c1a34eae3eaa58c2305fd712aca4b46f9 | |
| parent | a5c67506ac6274764f0f1b09914dbba1d2f93626 (diff) | |
| download | linux-cip-3b5e9d5243f90d022ba9f5e6e9cf049dfe41d7f0.tar.gz | |
ARM: dts: r8a7745: Add CMT SoC specific support
Add CMT[01] support to SoC DT.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 9680c97b516cbb70efe73dde05d497b1203bde6d)
(updated clocks and power-domains properties. removed resets property.
added renesas,channels-mask property. updated compatible strings)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 0335e4574654a5..46fb0461339c5c 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1062,6 +1062,38 @@ }; }; + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-r8a7745", + "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7745_CLK_CMT0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + renesas,channels-mask = <0x60>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a7745", + "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7745_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + renesas,channels-mask = <0xff>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; |