tci6614: update pd/lpsc based on spec update

As per verion v0.8 the psc/lpsc spec there are many PD and LPSC
definitions changed. This patch udpates the same in the Linux
psc code

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>

2 files changed, 64 insertions, 71 deletions

diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index afa2938e080329..a03b8ba6af9a3c 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -232,7 +232,7 @@
 #define TCI6614_LPSC_MODRST0			0
 #define TCI6614_LPSC_SRC3_PWR			1
 #define TCI6614_LPSC_EMIF4F			2
-#define TCI6614_LPSC_TCP3E			3
+#define TCI6614_LPSC_VUSR			3
 #define TCI6614_LPSC_VCP2_A			4
 #define TCI6614_LPSC_DEBUGSS_TRC		5
 #define TCI6614_LPSC_TETB_TRC			6
@@ -241,44 +241,43 @@
 #define TCI6614_LPSC_CRYPTO			9
 #define TCI6614_LPSC_PCIEX			10
 #define TCI6614_LPSC_SRIO			11
-#define TCI6614_LPSC_VUSR			12
+#define TCI6614_LPSC_BCP			12
+#define TCI6614_LPSC_MONZA_RST_CTRL		13
 #define TCI6614_LPSC_MSMCSRAM			14
 #define TCI6614_LPSC_RAC			15
 #define TCI6614_LPSC_TAC			16
 #define TCI6614_LPSC_FFTC			17
-#define TCI6614_LPSC_DRFE			18
+#define TCI6614_LPSC_AIF2			18
 #define TCI6614_LPSC_TCP3D			19
 #define TCI6614_LPSC_VCP2_B			20
 #define TCI6614_LPSC_VCP2_C			21
 #define TCI6614_LPSC_VCP2_D			22
-#define TCI6614_LPSC_BCP			23
+#define TCI6614_LPSC_GEM0			23
 #define TCI6614_LPSC_GEM1			24
 #define TCI6614_LPSC_RSAX2_1			25
-#define TCI6614_LPSC_GEM0			26
+#define TCI6614_LPSC_GEM2			26
 #define TCI6614_LPSC_RSAX2_0			27
-#define TCI6614_LPSC_ARM			28
-#define TCI6614_LPSC_TCP2			29
-#define TCI6614_LPSC_DXB			30
+#define TCI6614_LPSC_GEM3			28
+#define TCI6614_LPSC_TCP3D_B			29
 
 #define TCI6614_PD_ALWAYSON			0
 #define TCI6614_PD_DEBUG_TRC			1
 #define TCI6614_PD_PASS				2
 #define TCI6614_PD_PCIEX			3
 #define TCI6614_PD_SRIO				4
-#define TCI6614_PD_HYPERBRIDGE			5
-#define TCI6614_PD_L2SRAM			6
+#define TCI6614_PD_BCP				5
+#define TCI6614_PD_MONZA_RST_CTRL		6
 #define TCI6614_PD_MSMCSRAM			7
 #define TCI6614_PD_RAC_TAC			8
 #define TCI6614_PD_FFTC				9
-#define TCI6614_PD_DRFE				10
+#define TCI6614_PD_AIF2				10
 #define TCI6614_PD_TCP3D			11
 #define TCI6614_PD_VCP_BCD			12
-#define TCI6614_PD_BCP				13
+#define TCI6614_PD_GEM0				13
 #define TCI6614_PD_GEM1				14
 #define TCI6614_PD_GEM2				15
-#define TCI6614_PD_ARM				16
-#define TCI6614_PD_TCP2				17
-#define TCI6614_PD_DXB				18
+#define TCI6614_PD_GEM3				16
+#define TCI6614_PD_TCP3D_B			17
 
 
 /* PSC register offsets */
diff --git a/arch/arm/mach-davinci/tci6614.c b/arch/arm/mach-davinci/tci6614.c
index 25e363a8dd4130..f42d7c3dc7414d 100644
--- a/arch/arm/mach-davinci/tci6614.c
+++ b/arch/arm/mach-davinci/tci6614.c
@@ -177,61 +177,53 @@ define_pll_div_clk(main_pll, 13, main_div_chip_dftclk8);
 
 
 /* Alawys on domains */
-lpsc_clk_enabled(modrst0,	main_div_chip_clk6, MODRST0);
-lpsc_clk_enabled(src3_pwr,	main_div_chip_smreflex_clk, SRC3_PWR);
+lpsc_clk_enabled(modrst0,		main_div_chip_clk6, MODRST0);
+lpsc_clk_enabled(src3_pwr,		main_div_chip_smreflex_clk, SRC3_PWR);
+lpsc_clk_enabled(emif4f,		main_div_chip_clk1, EMIF4F);
+lpsc_clk_enabled(monza_rst_ctrl,	main_div_chip_clk1, MONZA_RST_CTRL);
 
 /* There are 2 more clocks coming to some of the modules below and only
  * one of the clock is mentioned as parent clock. Assume they are
  * automatically enabled by gpsc
  */
-lpsc_clk_enabled(emif4f,	main_div_chip_clk1, EMIF4F);
-lpsc_clk_enabled(timer0,	clk_modrst0, MODRST0);
-lpsc_clk_enabled(timer1,	clk_modrst0, MODRST0);
-lpsc_clk_enabled(uart0,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(uart1,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(aemif,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(i2c,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(spi,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(gpio,		clk_modrst0, MODRST0);
-lpsc_clk_enabled(key_mgr,	clk_modrst0, MODRST0);
-lpsc_clk_enabled(arm,		main_div_chip_clk1, ARM);
+lpsc_clk_enabled(timer0,		clk_modrst0, MODRST0);
+lpsc_clk_enabled(timer1,		clk_modrst0, MODRST0);
+lpsc_clk_enabled(uart0,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(uart1,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(aemif,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(usim,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(i2c,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(spi,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(gpio,			clk_modrst0, MODRST0);
+lpsc_clk_enabled(key_mgr,		clk_modrst0, MODRST0);
 
 /* SW controlled domains */
-lpsc_clk(vcp2_a,	main_div_chip_clk3, VCP2_A, ALWAYSON);
-lpsc_clk(debugss_trc,	main_div_chip_clk3, DEBUGSS_TRC, DEBUG_TRC);
-lpsc_clk(tetb_trc,	main_div_chip_clk6, TETB_TRC, DEBUG_TRC);
-lpsc_clk(pktproc,	main_div_chip_clk3, PKTPROC, PASS);
-lpsc_clk(cpgmac,	main_div_chip_clk3, CPGMAC, PASS);
-lpsc_clk(crypto,	main_div_chip_clk1, CRYPTO, PASS);
-/* TODO showing as clk2/dftclk4 */
-lpsc_clk(pciex,		main_div_chip_clk2, PCIEX, PCIEX);
-lpsc_clk(srio,		main_div_chip_clk3_srio, SRIO, SRIO);
-lpsc_clk(vusr,		main_div_chip_clk2, VUSR, HYPERBRIDGE);
-lpsc_clk(msmcsram,	main_div_chip_clk2, MSMCSRAM, MSMCSRAM);
-lpsc_clk(rac,		main_div_chip_clk1, RAC, RAC_TAC);
-lpsc_clk(tac,		main_div_chip_clk3, TAC, RAC_TAC);
-lpsc_clk(fftc,		main_div_chip_clk3, FFTC, FFTC);
-/* TODO can't find the block in the clock distribution schematics.
- * Is this same as AF?
- */
-lpsc_clk(drfe,		main_div_chip_clk3, DRFE, DRFE);
-lpsc_clk(tcp3d,		main_div_chip_clk2, TCP3D, TCP3D);
-/* TODO only one VCP block shown in the schmatics */
-lpsc_clk(vcp2_b,	main_div_chip_clk3, VCP2_B, VCP_BCD);
-lpsc_clk(vcp2_c,	main_div_chip_clk3, VCP2_C, VCP_BCD);
-lpsc_clk(vcp2_d,	main_div_chip_clk3, VCP2_D, VCP_BCD);
-lpsc_clk(bcp,		main_div_chip_clk3, BCP,  BCP);
-lpsc_clk(gem1,		main_div_chip_clk1, GEM1, GEM1);
-lpsc_clk(rsax2_1,	main_div_chip_clk1, RSAX2_1, GEM1);
-lpsc_clk(gem0,		main_div_chip_clk1, GEM0, GEM2);
-lpsc_clk(rsax2_0,	main_div_chip_clk1, RSAX2_0, GEM2);
-lpsc_clk(tcp2,		main_div_chip_clk2, TCP2, TCP2);
-/* TODO can't find the block in the clock distribution schematics.
- * Same as BCP??
- */
-lpsc_clk(dxb,		main_div_chip_clk3, DXB, DXB);
-
-
+lpsc_clk(vusr,				main_div_chip_clk2, VUSR, ALWAYSON);
+lpsc_clk(vcp2_a,			main_div_chip_clk3, VCP2_A, ALWAYSON);
+lpsc_clk(debugss_trc,			main_div_chip_clk3, DEBUGSS_TRC, DEBUG_TRC);
+lpsc_clk(tetb_trc,			main_div_chip_clk3, TETB_TRC, DEBUG_TRC);
+lpsc_clk(pktproc,			main_div_chip_clk3, PKTPROC, PASS);
+lpsc_clk(cpgmac,			main_div_chip_clk3, CPGMAC, PASS);
+lpsc_clk(crypto,			main_div_chip_clk1, CRYPTO, PASS);
+lpsc_clk(pciex,				main_div_chip_clk2, PCIEX, PCIEX);
+lpsc_clk(srio,				main_div_chip_clk3_srio, SRIO, SRIO);
+lpsc_clk(bcp,				main_div_chip_clk3, BCP,  BCP);
+lpsc_clk(msmcsram,			main_div_chip_clk2, MSMCSRAM, MSMCSRAM);
+lpsc_clk(rac,				main_div_chip_clk1, RAC, RAC_TAC);
+lpsc_clk(tac,				main_div_chip_clk3, TAC, RAC_TAC);
+lpsc_clk(fftc,				main_div_chip_clk3, FFTC, FFTC);
+lpsc_clk(aif2,				main_div_chip_clk3, AIF2, AIF2);
+lpsc_clk(tcp3d,				main_div_chip_clk2, TCP3D, TCP3D);
+lpsc_clk(vcp2_b,			main_div_chip_clk3, VCP2_B, VCP_BCD);
+lpsc_clk(vcp2_c,			main_div_chip_clk3, VCP2_C, VCP_BCD);
+lpsc_clk(vcp2_d,			main_div_chip_clk3, VCP2_D, VCP_BCD);
+lpsc_clk(gem0,				main_div_chip_clk1, GEM0, GEM0);
+lpsc_clk(gem1,				main_div_chip_clk1, GEM1, GEM1);
+lpsc_clk(rsax2_1,			main_div_chip_clk1, RSAX2_1, GEM1);
+lpsc_clk(gem2,				main_div_chip_clk1, GEM2, GEM2);
+lpsc_clk(rsax2_0,			main_div_chip_clk1, RSAX2_0, GEM2);
+lpsc_clk(gem3,				main_div_chip_clk1, GEM3, GEM3);
+lpsc_clk(tcp3d_b,			main_div_chip_clk2, TCP3D_B, TCP3D_B);
 
 static struct clk_lookup clks[] = {
 	CLK(NULL, "ref_clk",			&ref_clk),
@@ -254,6 +246,7 @@ static struct clk_lookup clks[] = {
 	CLK(NULL,		"clk_modrst0",		&clk_modrst0),
 	CLK(NULL,		"clk_src3_pwr",		&clk_src3_pwr),
 	CLK(NULL,		"clk_emif4f",		&clk_emif4f),
+	CLK(NULL,		"clk_vusr",		&clk_vusr),
 	CLK(NULL,		"clk_vcp2_a",		&clk_vcp2_a),
 	CLK(NULL,		"clk_debugss_trc",	&clk_debugss_trc),
 	CLK(NULL,		"clk_tetb_trc",		&clk_tetb_trc),
@@ -262,30 +255,31 @@ static struct clk_lookup clks[] = {
 	CLK(NULL,		"clk_crypto",		&clk_crypto),
 	CLK(NULL,		"clk_pciex",		&clk_pciex),
 	CLK(NULL,		"clk_srio",		&clk_srio),
-	CLK(NULL,		"clk_vusr",		&clk_vusr),
+	CLK(NULL,		"clk_bcp",		&clk_bcp),
+	CLK(NULL,		"clk_monza_rst_ctrl",	&clk_monza_rst_ctrl),
 	CLK(NULL,		"clk_msmcsram",		&clk_msmcsram),
 	CLK(NULL,		"clk_rac",		&clk_rac),
 	CLK(NULL,		"clk_tac",		&clk_tac),
 	CLK(NULL,		"clk_fftc",		&clk_fftc),
-	CLK(NULL,		"clk_drfe",		&clk_drfe),
+	CLK(NULL,		"clk_aif2",		&clk_aif2),
 	CLK(NULL,		"clk_tcp3d",		&clk_tcp3d),
 	CLK(NULL,		"clk_vcp2_b",		&clk_vcp2_b),
 	CLK(NULL,		"clk_vcp2_c",		&clk_vcp2_c),
 	CLK(NULL,		"clk_vcp2_d",		&clk_vcp2_d),
-	CLK(NULL,		"clk_bcp",		&clk_bcp),
-	CLK(NULL,		"clk_gem1",		&clk_gem1),
+	CLK("keystone-rproc.0",	NULL,                   &clk_gem0),
+	CLK("keystone-rproc.1",	NULL,                   &clk_gem1),
+	CLK("keystone-rproc.2",	NULL,                   &clk_gem2),
+	CLK("keystone-rproc.3",	NULL,                   &clk_gem3),
 	CLK(NULL,		"clk_rsax2_1",		&clk_rsax2_1),
-	CLK(NULL,		"clk_gem0",		&clk_gem0),
 	CLK(NULL,		"clk_rsax2_0",		&clk_rsax2_0),
-	CLK(NULL,		"clk_arm",		&clk_arm),
-	CLK(NULL,		"clk_tcp2",		&clk_tcp2),
-	CLK(NULL,		"clk_dxb",		&clk_dxb),
+	CLK(NULL,		"clk_tcp3d_b",		&clk_tcp3d_b),
 
 	CLK(NULL,		"timer0",		&clk_timer0),
 	CLK("watchdog",		NULL,			&clk_timer1),
 	CLK(NULL,		"uart0",		&clk_uart0),
 	CLK(NULL,		"uart1",		&clk_uart1),
 	CLK(NULL,		"aemif",		&clk_aemif),
+	CLK(NULL,		"usim",			&clk_usim),
 	CLK("i2c_davinci.1",	NULL,			&clk_i2c),
 	CLK("spi_davinci.0",	NULL,			&clk_spi),
 	CLK(NULL,		"gpio",			&clk_gpio),