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authorBen Hutchings <ben@decadent.org.uk>2020-05-20 16:47:41 +0100
committerBen Hutchings <ben@decadent.org.uk>2020-05-20 16:47:41 +0100
commit7115c6e58ca32b75f1991493cb307606169bcd5a (patch)
tree9f3077e772f8f2646d068cc925aee372a7e30bb4
parent8a0edd061294a4e379d79be4dd73495b20842530 (diff)
downloadlinux-stable-queue-7115c6e58ca32b75f1991493cb307606169bcd5a.tar.gz
Drop clk-tegra patch which breaks the build
CLK_IS_CRITICAL is not implemented here.
-rw-r--r--queue-3.16/clk-tegra-mark-fuse-clock-as-critical.patch39
-rw-r--r--queue-3.16/series1
2 files changed, 0 insertions, 40 deletions
diff --git a/queue-3.16/clk-tegra-mark-fuse-clock-as-critical.patch b/queue-3.16/clk-tegra-mark-fuse-clock-as-critical.patch
deleted file mode 100644
index 1a633668..00000000
--- a/queue-3.16/clk-tegra-mark-fuse-clock-as-critical.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From: Stephen Warren <swarren@nvidia.com>
-Date: Thu, 3 Oct 2019 14:50:30 -0600
-Subject: clk: tegra: Mark fuse clock as critical
-
-commit bf83b96f87ae2abb1e535306ea53608e8de5dfbb upstream.
-
-For a little over a year, U-Boot on Tegra124 has configured the flow
-controller to perform automatic RAM re-repair on off->on power
-transitions of the CPU rail[1]. This is mandatory for correct operation
-of Tegra124. However, RAM re-repair relies on certain clocks, which the
-kernel must enable and leave running. The fuse clock is one of those
-clocks. Mark this clock as critical so that LP1 power mode (system
-suspend) operates correctly.
-
-[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
-
-Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
-Signed-off-by: Stephen Warren <swarren@nvidia.com>
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
----
- drivers/clk/tegra/clk-tegra-periph.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/tegra/clk-tegra-periph.c
-+++ b/drivers/clk/tegra/clk-tegra-periph.c
-@@ -517,7 +517,11 @@ static struct tegra_periph_init_data gat
- GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
- GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
- GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
-- GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
-+ /*
-+ * Critical for RAM re-repair operation, which must occur on resume
-+ * from LP1 system suspend and as part of CCPLEX cluster switching.
-+ */
-+ GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
- GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
- GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
- GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
diff --git a/queue-3.16/series b/queue-3.16/series
index 43cf85f5..07ef8422 100644
--- a/queue-3.16/series
+++ b/queue-3.16/series
@@ -34,7 +34,6 @@ rtc-hym8563-return-einval-if-the-time-is-known-to-be-invalid.patch
gianfar-fix-tx-timestamping-with-a-stacked-dsa-driver.patch
pxa168fb-fix-the-function-used-to-release-some-memory-in-an-error.patch
alsa-sh-fix-compile-warning-wrt-const.patch
-clk-tegra-mark-fuse-clock-as-critical.patch
arm-tegra-enable-pllp-bypass-during-tegra124-lp1.patch
media-iguanair-add-sanity-checks.patch
media-iguanair-fix-endpoint-sanity-check.patch