diff options
| author | Shuai Xue <xueshuai@linux.alibaba.com> | 2022-08-19 22:07:53 +0800 |
|---|---|---|
| committer | Shuai Xue <xueshuai@linux.alibaba.com> | 2022-08-25 10:43:33 +0800 |
| commit | adbf8b3f6959f0eefbf89c3cb6775c4782d58140 (patch) | |
| tree | 4e2973efa898d1ece3563432cff56f012a06268b | |
| parent | 449c7138938b5e0ade28e8db73bcdb1e6bd144e2 (diff) | |
| download | ras-tools-adbf8b3f6959f0eefbf89c3cb6775c4782d58140.tar.gz | |
einj_mem_uc: add explicitly str, strb and strh case for Arm64
Add cases to explicitly trigger write with STR, STRB, and STRH
instruction on Arm64 platform.
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
| -rw-r--r-- | einj_mem_uc.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/einj_mem_uc.c b/einj_mem_uc.c index adfd630..e1b3e83 100644 --- a/einj_mem_uc.c +++ b/einj_mem_uc.c @@ -376,6 +376,56 @@ int trigger_write(char *addr) return 0; } +#ifdef __aarch64__ +#define __put_mem_asm(store, reg, x, addr) \ + asm volatile( \ + store " " reg "0, [%1]\n" \ + : \ + : "r" (x), "r" (addr)) + +int trigger_write_byte(char *addr) +{ + int8_t __pu_val = 0x1E; + char *target = addr + write_offset; + + PRINT_TRIGGERING; + __put_mem_asm("strb", "%w", __pu_val, target); + + return 0; +} + +int trigger_write_word(char *addr) +{ + int16_t __pu_val = 0x1EFF; + char *target = addr + write_offset; + + PRINT_TRIGGERING; + __put_mem_asm("strh", "%w", __pu_val, target); + + return 0; +} + +int trigger_write_dword(char *addr) +{ + int32_t __pu_val = 0x1FFFEEEE; + char *target = addr + write_offset; + + PRINT_TRIGGERING; + __put_mem_asm("str", "%w", __pu_val, target); + return 0; +} + +int trigger_write_qword(char *addr) +{ + int64_t __pu_val = 0x1EEEFFFFFEEEE; + char *target = addr + write_offset; + + PRINT_TRIGGERING; + __put_mem_asm("str", "%x", __pu_val, target); + return 0; +} +#endif + /* * parameters to the memcpy and copyin tests. */ @@ -552,6 +602,24 @@ struct test { "store", "Write to target address. Should generate a UCNA/CMCI", data_alloc, inject_uc, 1, trigger_write, F_CMCI, }, +#ifdef __aarch64__ + { + "strbyte", "Write to target address. Should generate a UCNA/CMCI", + data_alloc, inject_uc, 1, trigger_write_byte, F_CMCI, + }, + { + "strword", "Write to target address. Should generate a UCNA/CMCI", + data_alloc, inject_uc, 1, trigger_write_word, F_CMCI, + }, + { + "strdword", "Write to target address. Should generate a UCNA/CMCI", + data_alloc, inject_uc, 1, trigger_write_dword, F_CMCI, + }, + { + "strqword", "Write to target address. Should generate a UCNA/CMCI", + data_alloc, inject_uc, 1, trigger_write_qword, F_CMCI, + }, +#endif { "memcpy", "Streaming read from target address. Probably fatal", data_alloc, inject_uc, 1, trigger_memcpy, F_MCE|F_CMCI|F_SIGBUS|F_FATAL, |