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authorMathieu Desnoyers <mathieu.desnoyers@efficios.com>2024-03-04 11:50:11 -0500
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>2024-03-04 11:50:11 -0500
commitf6ddbd31f450ec045c06a72e40b1af7dfc72ae0d (patch)
tree2ee22143165658d43786355c54641e38499df79f
parentd9342e955cef6b3ce2183d9782a55ff172ba9d76 (diff)
downloadlibrseq-f6ddbd31f450ec045c06a72e40b1af7dfc72ae0d.tar.gz
Rename RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV to rseq_arch_has_load_add_load_load_add_store
Fix param test to use rseq_arch_has_load_add_load_load_add_store rather than rseq_arch_has_load_cbne_load_add_store. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Change-Id: I373c91dc9178dd69ed159d568090e8c732cf4485
-rw-r--r--include/rseq/arch/riscv/bits.h2
-rw-r--r--include/rseq/arch/x86/bits.h2
-rw-r--r--include/rseq/rseq.h2
-rw-r--r--tests/param_test.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/include/rseq/arch/riscv/bits.h b/include/rseq/arch/riscv/bits.h
index f5213e0..e9525c0 100644
--- a/include/rseq/arch/riscv/bits.h
+++ b/include/rseq/arch/riscv/bits.h
@@ -229,7 +229,7 @@ error3:
#endif
}
-#define RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV
+#define rseq_arch_has_load_add_load_load_add_store
static inline __attribute__((always_inline))
int RSEQ_TEMPLATE_IDENTIFIER(rseq_load_add_load_load_add_store__ptr)(intptr_t *ptr, off_t off, intptr_t inc, int cpu)
diff --git a/include/rseq/arch/x86/bits.h b/include/rseq/arch/x86/bits.h
index f5511b6..df30fc6 100644
--- a/include/rseq/arch/x86/bits.h
+++ b/include/rseq/arch/x86/bits.h
@@ -196,7 +196,7 @@ error1:
#endif
}
-#define RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV
+#define rseq_arch_has_load_add_load_load_add_store
static inline __attribute__((always_inline))
int RSEQ_TEMPLATE_IDENTIFIER(rseq_load_add_load_load_add_store__ptr)(intptr_t *ptr, long off, intptr_t inc, int cpu)
diff --git a/include/rseq/rseq.h b/include/rseq/rseq.h
index b672468..ea795c4 100644
--- a/include/rseq/rseq.h
+++ b/include/rseq/rseq.h
@@ -273,7 +273,7 @@ int rseq_load_add_store__ptr(enum rseq_mo rseq_mo, enum rseq_percpu_mode percpu_
}
}
-#ifdef RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV
+#ifdef rseq_arch_has_load_add_load_load_add_store
static inline __attribute__((always_inline))
int rseq_load_add_load_load_add_store__ptr(enum rseq_mo rseq_mo, enum rseq_percpu_mode percpu_mode,
intptr_t *ptr, long off, intptr_t inc, int cpu)
diff --git a/tests/param_test.c b/tests/param_test.c
index 252a0a7..76ab763 100644
--- a/tests/param_test.c
+++ b/tests/param_test.c
@@ -297,7 +297,7 @@ static int sys_membarrier(int cmd, int flags, int cpu_id)
return syscall(__NR_membarrier, cmd, flags, cpu_id);
}
-#ifdef rseq_arch_has_load_cbne_load_add_store
+#ifdef rseq_arch_has_load_add_load_load_add_store
#define TEST_MEMBARRIER
#endif