diff options
| author | Mathieu Desnoyers <mathieu.desnoyers@efficios.com> | 2024-03-05 10:10:53 -0500 |
|---|---|---|
| committer | Mathieu Desnoyers <mathieu.desnoyers@efficios.com> | 2024-03-05 10:37:24 -0500 |
| commit | 0f963443529cf64515af5f9ec90dec7b754880dc (patch) | |
| tree | d7e39f795a8aa9b28fd16c27c0ca7aa99b26da19 | |
| parent | 25e59085d045d1a13b1b140d012541b30897b531 (diff) | |
| download | librseq-0f963443529cf64515af5f9ec90dec7b754880dc.tar.gz | |
Remove riscv has_load_add_load_load_add_store implementation
The implementation is currently buggy: RSEQ_ASM_OP_R_DEREF_ADDV()
should increment the address _target_ as a final store, not just the
address within the temporary register.
Remove it for now.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0f2a854cec4ab5e58ea6cbb74d40ca29b256d27e
| -rw-r--r-- | include/rseq/arch/riscv.h | 11 | ||||
| -rw-r--r-- | include/rseq/arch/riscv/bits.h | 45 |
2 files changed, 0 insertions, 56 deletions
diff --git a/include/rseq/arch/riscv.h b/include/rseq/arch/riscv.h index eceaf2f..c6adc7f 100644 --- a/include/rseq/arch/riscv.h +++ b/include/rseq/arch/riscv.h @@ -207,17 +207,6 @@ do { \ "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ "333:\n" -/* - * Load pointer address from @ptr. Add @off to offset from this pointer. - * Add @inc to the resulting address as an end-of-sequence store. - */ -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \ - "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ - RSEQ_ASM_OP_R_ADD(off) \ - RSEQ_ASM_REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \ - RSEQ_ASM_OP_R_ADD(inc) \ - __rseq_str(post_commit_label) ":\n" - /* Per-cpu-id indexing. */ #define RSEQ_TEMPLATE_INDEX_CPU_ID diff --git a/include/rseq/arch/riscv/bits.h b/include/rseq/arch/riscv/bits.h index e9525c0..799e5b9 100644 --- a/include/rseq/arch/riscv/bits.h +++ b/include/rseq/arch/riscv/bits.h @@ -229,51 +229,6 @@ error3: #endif } -#define rseq_arch_has_load_add_load_load_add_store - -static inline __attribute__((always_inline)) -int RSEQ_TEMPLATE_IDENTIFIER(rseq_load_add_load_load_add_store__ptr)(intptr_t *ptr, off_t off, intptr_t inc, int cpu) -{ - RSEQ_INJECT_C(9) - - __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) -#ifdef RSEQ_COMPARE_TWICE - RSEQ_ASM_DEFINE_EXIT_POINT(2f, "%l[error1]") -#endif - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) - RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, 4f) - RSEQ_INJECT_ASM(3) -#ifdef RSEQ_COMPARE_TWICE - RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") -#endif - RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3) - RSEQ_INJECT_ASM(4) - RSEQ_ASM_DEFINE_ABORT(4, "", abort) - : /* gcc asm goto does not allow outputs */ - : [cpu_id] "r" (cpu), - [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_INDEX_CPU_ID_FIELD), - [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr), - [ptr] "r" (ptr), - [off] "er" (off), - [inc] "er" (inc) - RSEQ_INJECT_INPUT - : "memory", RSEQ_ASM_TMP_REG_1 - RSEQ_INJECT_CLOBBER - : abort -#ifdef RSEQ_COMPARE_TWICE - , error1 -#endif - ); - return 0; -abort: - RSEQ_INJECT_FAILED - return -1; -#ifdef RSEQ_COMPARE_TWICE -error1: - rseq_bug("cpu_id comparison failed"); -#endif -} - #endif /* #if defined(RSEQ_TEMPLATE_MO_RELAXED) && (defined(RSEQ_TEMPLATE_INDEX_CPU_ID) || defined(RSEQ_TEMPLATE_INDEX_MM_CID)) */ |