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path: root/target-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-23riscv: G extension implies Zicsr & ZifenceiLuc Van Oostenryck1-1/+1
2024-01-23riscv: V extension implies F & DLuc Van Oostenryck1-1/+1
2024-01-23riscv: add predefines for v_min_vlen, v_elen & v_elen_fpLuc Van Oostenryck1-1/+5
2024-01-21RISC-V: Add basic support for the vector extensionConor Dooley1-0/+4
2023-12-18RISC-V: Add support for the zihintpause extensionPalmer Dabbelt1-0/+4
2023-12-18RISC-V: Add support for the zicbom extensionPalmer Dabbelt1-0/+4
2022-06-05RISC-V: Remove "g" from the extension listPalmer Dabbelt1-1/+0
2022-06-05RISC-V: Remove the unimplemented ISA extensionsPalmer Dabbelt1-10/+0
2022-06-05RISC-V: Match GCC's semantics for multiple -march instancesPalmer Dabbelt1-0/+3
2022-06-05RISC-V: don't die() on -march errors, just warnPalmer Dabbelt1-2/+6
2022-05-21RISC-V: Add the Zifencei extensionPalmer Dabbelt1-0/+4
2022-05-21RISC-V: Add the Zicsr extensionPalmer Dabbelt1-2/+6
2020-07-14arch: add predefines __INT_FAST${N}_TYPE__Luc Van Oostenryck1-1/+11
2020-07-07riscv: add the predefines for the extensionsLuc Van Oostenryck1-0/+19
2020-07-08riscv: parse '-march=....'Luc Van Oostenryck1-0/+80
2020-07-06predefine: avoid add_pre_buffer() for targetsLuc Van Oostenryck1-1/+1
2019-12-16arch: use arch_target for INT128's predefineLuc Van Oostenryck1-0/+1
2019-12-16arch: move cmodel predefines to the target files.Luc Van Oostenryck1-0/+10
2019-12-16arch: move target-specific predefines to the target files.Luc Van Oostenryck1-0/+8
2019-12-16arch: move handle_arch_finalize() into target_init()Luc Van Oostenryck1-0/+12
2019-12-16arch: move arch-specificities to their own filesLuc Van Oostenryck1-0/+22