diff options
| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-10 20:31:38 -0700 |
|---|---|---|
| committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2023-12-18 13:38:50 +0100 |
| commit | 7058eaf5677ff4b0f253d2985333d312e3d542ba (patch) | |
| tree | 503d88cdf95cd1068964a4377021ef5fa3c8404a | |
| parent | eac793a4ec5e4647e8301ddeb7c13ac78cb54fe1 (diff) | |
| download | sparse-7058eaf5677ff4b0f253d2985333d312e3d542ba.tar.gz | |
RISC-V: Add support for the zicbom extension
This was recently added to binutils and with any luck will soon be in
Linux, without it sparse will fail when trying to build new kernels on
systems with new toolchains.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
| -rw-r--r-- | target-riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-riscv.c b/target-riscv.c index 217ab7e8..db0f7e57 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -19,6 +19,7 @@ #define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU) #define RISCV_ZICSR (1 << 10) #define RISCV_ZIFENCEI (1 << 11) +#define RISCV_ZICBOM (1 << 12) static unsigned int riscv_flags; @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg) { "c", RISCV_COMP }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, + { "_zicbom", RISCV_ZICBOM }, }; int i; @@ -131,6 +133,8 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_zicsr", 1, "1"); if (riscv_flags & RISCV_ZIFENCEI) predefine("__riscv_zifencei", 1, "1"); + if (riscv_flags & RISCV_ZICBOM) + predefine("__riscv_zicbom", 1, "1"); if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); |