struct nand_sdr_timings — SDR NAND chip timings


struct nand_sdr_timings {
  u32 tBERS_max;
  u32 tCCS_min;
  u32 tPROG_max;
  u32 tR_max;
  u32 tALH_min;
  u32 tADL_min;
  u32 tALS_min;
  u32 tAR_min;
  u32 tCEA_max;
  u32 tCEH_min;
  u32 tCH_min;
  u32 tCHZ_max;
  u32 tCLH_min;
  u32 tCLR_min;
  u32 tCLS_min;
  u32 tCOH_min;
  u32 tCS_min;
  u32 tDH_min;
  u32 tDS_min;
  u32 tFEAT_max;
  u32 tIR_min;
  u32 tITC_max;
  u32 tRC_min;
  u32 tREA_max;
  u32 tREH_min;
  u32 tRHOH_min;
  u32 tRHW_min;
  u32 tRHZ_max;
  u32 tRLOH_min;
  u32 tRP_min;
  u32 tRR_min;
  u64 tRST_max;
  u32 tWB_max;
  u32 tWC_min;
  u32 tWH_min;
  u32 tWHR_min;
  u32 tWP_min;
  u32 tWW_min;


u32 tBERS_max

Block erase time

u32 tCCS_min

Change column setup time

u32 tPROG_max

Page program time

u32 tR_max

Page read time

u32 tALH_min

ALE hold time

u32 tADL_min

ALE to data loading time

u32 tALS_min

ALE setup time

u32 tAR_min

ALE to RE# delay

u32 tCEA_max

CE# access time

u32 tCEH_min

CE# high hold time

u32 tCH_min

CE# hold time

u32 tCHZ_max

CE# high to output hi-Z

u32 tCLH_min

CLE hold time

u32 tCLR_min

CLE to RE# delay

u32 tCLS_min

CLE setup time

u32 tCOH_min

CE# high to output hold

u32 tCS_min

CE# setup time

u32 tDH_min

Data hold time

u32 tDS_min

Data setup time

u32 tFEAT_max

Busy time for Set Features and Get Features

u32 tIR_min

Output hi-Z to RE# low

u32 tITC_max

Interface and Timing Mode Change time

u32 tRC_min

RE# cycle time

u32 tREA_max

RE# access time

u32 tREH_min

RE# high hold time

u32 tRHOH_min

RE# high to output hold

u32 tRHW_min

RE# high to WE# low

u32 tRHZ_max

RE# high to output hi-Z

u32 tRLOH_min

RE# low to output hold

u32 tRP_min

RE# pulse width

u32 tRR_min

Ready to RE# low (data only)

u64 tRST_max

Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#.

u32 tWB_max

WE# high to SR[6] low

u32 tWC_min

WE# cycle time

u32 tWH_min

WE# high hold time

u32 tWHR_min

WE# high to RE# low

u32 tWP_min

WE# pulse width

u32 tWW_min

WP# transition to WE# low


This struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: (chapter 4.15 Timing Parameters)

All these timings are expressed in picoseconds.