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2014-11-03Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into stagingPeter Maydell3-12/+74
2014-11-03target-xtensa: fix build for cores w/o windowed registersMax Filippov1-12/+19
2014-11-03target-xtensa: add core importing scriptMax Filippov1-0/+53
2014-11-03target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov2-0/+2
2014-11-02target-xtensa: mark XtensaConfig structs as unusedPeter Maydell3-3/+3
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-25target-xtensa: Use cpu_exec_interrupt qom hookRichard Henderson3-0/+12
2014-09-12cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell3-4/+5
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini2-1/+2
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+1
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2-1/+1
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini3-6/+7
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson4-9/+4
2014-05-26target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov1-2/+2
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-4/+4
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+3
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-4/+6
2014-03-13cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber1-1/+1
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-3/+6
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2-4/+6
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2-10/+14
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-7/+8
2014-03-13target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber2-2/+4
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov4-3/+21
2014-02-24target-xtensa: refactor standard core configurationMax Filippov4-21/+13
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov3-0/+33
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov1-0/+38
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov1-0/+9
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
2014-02-11exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias1-1/+2
2013-11-08target-xtensa: add missing DEBUG section to dc233c configMax Filippov1-0/+1
2013-10-15target-xtensa: add in_asm loggingMax Filippov1-0/+8
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+1
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-1/+1
2013-08-05Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori3-23/+53
2013-07-29target-xtensa: check register window inlineMax Filippov1-8/+25
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov1-13/+18
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov3-2/+8
2013-07-29target-xtensa: add fallthrough markersMax Filippov1-0/+2
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-0/+2
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+14
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-6/+8
2013-07-27target-xtensa: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+100
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber2-0/+11
2013-07-26target-xtensa: Introduce XtensaCPU subclassesAndreas Färber3-12/+47
2013-07-23exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber1-5/+5
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber4-5/+10
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber1-4/+5
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber1-2/+3
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-3/+0
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber4-3/+10
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-2/+7
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-1/+4
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+1
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson1-16/+13
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson1-14/+6
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber3-13/+9
2013-02-16target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber3-1/+18
2013-02-01target-xtensa: Mark as unmigratableAndreas Färber3-39/+9
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov1-1/+5
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini7-7/+7
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini8-19/+19
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-12/+2
2012-12-15target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov1-1/+2
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
2012-12-08target-xtensa: implement MISC SRMax Filippov3-0/+6
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov1-19/+30
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov3-105/+130
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov5-1/+25
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov7-14/+131
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl1-5/+5
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-28target-xtensa: rename helper flagsAurelien Jarno1-8/+8
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity2-4/+4
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno1-20/+2
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov2-0/+43
2012-09-22target-xtensa: implement FP1 groupMax Filippov3-1/+135
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov3-0/+89
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov3-1/+104
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov1-4/+54
2012-09-22target-xtensa: add FP registersMax Filippov4-7/+63
2012-09-22target-xtensa: handle boolean option in overlaysMax Filippov1-0/+1
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov1-1/+3
2012-09-21target-xtensa: fix extui shift amountMax Filippov1-3/+21
2012-09-08target-xtensa: fix missing errno codes for mingw32Max Filippov1-0/+6
2012-09-05target-xtensa: convert host errno values to guestMax Filippov1-8/+98
2012-09-01target-xtensa: return ENOSYS for unimplemented simcallsMax Filippov1-0/+2
2012-08-09Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl1-7/+1
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov1-0/+6
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
2012-06-25target-xtensa: drop usage of prev_debug_excp_handlerIgor Mammedov1-7/+1
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov4-154/+151
2012-06-10target-xtensa: add attributes to helper functionsMax Filippov1-8/+8
2012-06-10target-xtensa: remove unnecessary include of dyngen-exec.hPeter Portante1-1/+0
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov1-0/+2
2012-06-09target-xtensa: control page table lookup explicitlyMax Filippov1-5/+5
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov3-27/+35
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov2-4/+14
2012-06-09target-xtensa: update EXCVADDR in case of page table lookupMax Filippov1-0/+1
2012-06-09target-xtensa: flush TLB page for new MMU mappingMax Filippov1-0/+1
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-0/+3
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2-0/+228
2012-06-04Kill off cpu_state_reset()Andreas Färber1-5/+0
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber3-6/+16
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
2012-04-15target-xtensa: add license to core-fsf.cMax Filippov1-0/+27
2012-04-15target-xtensa: add license to core-dc232b.cMax Filippov1-0/+27
2012-04-15target-xtensa: add dc233c coreMax Filippov3-0/+674
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov2-11/+20
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+4
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber2-1/+9
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber3-14/+14
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber4-1/+153
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova3-4/+4
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber4-68/+68
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-1/+1
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl3-3/+0
2012-02-28target-xtensa: Clean includesStefan Weil3-3/+0
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov3-0/+7
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov5-0/+147
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2-1/+54
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov5-3/+119
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2-0/+21
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov2-0/+68
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov1-2/+16
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov2-2/+2
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov1-0/+6
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
2011-10-16target-xtensa: add fsf coreMax Filippov2-0/+383
2011-10-16target-xtensa: add dc232b coreMax Filippov3-0/+712
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov3-860/+2
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov2-8/+12
2011-10-15target-xtensa: implement MAC16 optionMax Filippov2-1/+137
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov2-15/+4
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-2/+3
2011-09-10target-xtensa: add dc232b core and boardMax Filippov2-0/+429
2011-09-10target-xtensa: implement boolean optionMax Filippov2-24/+86
2011-09-10target-xtensa: implement memory protection optionsMax Filippov5-13/+782
2011-09-10target-xtensa: add gdb supportMax Filippov3-0/+400
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov3-2/+19
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov2-0/+9
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
2011-09-10target-xtensa: implement interrupt optionMax Filippov5-12/+335
2011-09-10target-xtensa: implement SIMCALLMax Filippov2-1/+9
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov3-4/+73
2011-09-10target-xtensa: implement extended L32RMax Filippov3-4/+40
2011-09-10target-xtensa: implement loop optionMax Filippov4-9/+93
2011-09-10target-xtensa: implement windowed registersMax Filippov5-9/+345
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov1-1/+76
2011-09-10target-xtensa: implement exceptionsMax Filippov5-6/+236
2011-09-10target-xtensa: add PS register and access controlMax Filippov3-6/+77
2011-09-10target-xtensa: implement CACHE groupMax Filippov1-1/+94
2011-09-10target-xtensa: implement SYNC groupMax Filippov1-1/+30
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov1-1/+109
2011-09-10target-xtensa: implement LSAI groupMax Filippov2-0/+90
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov4-0/+262
2011-09-10target-xtensa: implement RST3 groupMax Filippov1-0/+161
2011-09-10target-xtensa: add special and user registersMax Filippov2-2/+54
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov1-0/+43
2011-09-10target-xtensa: implement conditional jumpsMax Filippov1-0/+164
2011-09-10target-xtensa: implement RT0 groupMax Filippov1-0/+19
2011-09-10target-xtensa: implement narrow instructionsMax Filippov1-0/+54
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov5-2/+556
2011-09-10target-xtensa: add target stubsMax Filippov5-0/+326
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-22 12:35:11 +0000