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2014-11-03target-mips: add MSA support to mips32r5-genericYongbok Kim1-2/+2
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim3-5/+131
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim3-0/+621
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim3-0/+265
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim3-0/+1699
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim3-0/+290
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim3-0/+963
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim3-0/+297
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim3-0/+232
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim3-2/+156
2014-11-03target-mips: add MSA branch instructionsYongbok Kim1-114/+220
2014-11-03target-mips: add msa_helper.cYongbok Kim2-1/+50
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim2-0/+90
2014-11-03target-mips: add MSA opcode enumYongbok Kim1-0/+245
2014-11-03target-mips: stop translation after ctc1Yongbok Kim1-0/+6
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim3-9/+6
2014-11-03target-mips: add MSA exceptionsYongbok Kim1-0/+10
2014-11-03target-mips: add MSA defines and data structureYongbok Kim3-2/+52
2014-11-03target-mips: enable features in MIPS64R6-generic CPULeon Alrae1-2/+9
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae1-278/+260
2014-11-03target-mips: add restrictions for possible values in registersLeon Alrae1-17/+53
2014-11-03target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae1-1/+2
2014-11-03target-mips: implement forbidden slotLeon Alrae2-36/+76
2014-11-03target-mips: add Config5.SBRILeon Alrae2-3/+32
2014-11-03target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2-2/+26
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae4-11/+133
2014-11-03target-mips: add TLBINV supportLeon Alrae6-8/+92
2014-11-03target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2-2/+28
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae5-5/+57
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae3-1/+29
2014-11-03target-mips: distinguish between data load and instruction fetchLeon Alrae1-11/+10
2014-11-03target-mips: add KScratch registersLeon Alrae2-0/+47
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae1-6/+6
2014-10-14target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell1-19/+1
2014-10-14target-mips/dsp_helper.c: Add ifdef guards around various functionsPeter Maydell1-1/+16
2014-10-14target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell1-0/+2
2014-10-14target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell1-1/+0
2014-10-14target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()Peter Maydell1-9/+0
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim2-188/+123
2014-10-14target-mips/translate.c: Update OPC_SYNCIDongxue Zhang1-1/+6
2014-10-14target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae1-0/+30
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim1-2/+16
2014-10-14target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae1-0/+6
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim3-2/+342
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae3-44/+521
2014-10-14target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae1-14/+189
2014-10-13target-mips: add compact and CP1 branchesYongbok Kim1-14/+459
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim3-12/+136
2014-10-13target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2-9/+15
2014-10-13target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae1-59/+62
2014-10-13target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae1-21/+322
2014-10-13target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae1-1/+28
2014-10-13target-mips: signal RI Exception on DSP and Loongson instructionsLeon Alrae1-97/+98
2014-10-13target-mips: split decode_opc_special* into *_r6 and *_legacyLeon Alrae1-68/+160
2014-10-13target-mips: extract decode_opc_special* from decode_opcLeon Alrae1-805/+845
2014-10-13target-mips: move LL and SC instructionsLeon Alrae1-2/+26
2014-10-13target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae1-2/+16
2014-10-13target-mips: signal RI Exception on instructions removed in R6Leon Alrae1-8/+56
2014-10-13target-mips: define ISA_MIPS64R6Leon Alrae1-9/+19
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-25target-mips: Use cpu_exec_interrupt qom hookRichard Henderson3-0/+19
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-08-07target-mips: Ignore unassigned accesses with KVMJames Hogan1-0/+11
2014-07-28target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang1-0/+3
2014-07-09mips/kvm: Disable FPU on reset with KVMJames Hogan1-0/+7
2014-07-05mips/kvm: Init EBase to correct KSEG0James Hogan1-1/+7
2014-06-20target-mips: copy CP0_Config1 into DisasContextAurelien Jarno1-9/+11
2014-06-20Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell6-13/+758
2014-06-18target-mips: implement UserLocal RegisterPetar Jovanovic4-13/+83
2014-06-18target-mips: Enable KVM support in build systemSanjay Lal1-0/+1
2014-06-18target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()James Hogan1-0/+8
2014-06-18target-mips: kvm: Add main KVM support for MIPSSanjay Lal2-0/+709
2014-06-18target-mips: get_physical_address: Add KVM awarenessJames Hogan1-7/+26
2014-06-18target-mips: get_physical_address: Add defines for segment basesJames Hogan1-6/+12
2014-06-18target-mips: Reset CPU timer consistentlyJames Hogan1-0/+2
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini2-5/+2
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2-1/+1
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini3-6/+8
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson5-12/+5
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell4-17/+17
2014-03-25target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic1-35/+44
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber3-3/+6
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-2/+6
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber2-3/+12
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-3/+4
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber3-3/+4
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber3-20/+24
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber4-11/+16
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-28/+30
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic4-10/+56
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic5-3/+40
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic5-3/+31
2014-02-10target-mips: add CPU definition for MIPS32R5Petar Jovanovic2-0/+33
2013-12-21target-mips: Use new qemu_ld/st opcodesAurelien Jarno1-67/+52
2013-12-09target-mips: Use macro ARRAY_SIZE where possibleStefan Weil1-18/+12
2013-12-09target-mips: fix 64-bit FPU config for user-mode emulationPetar Jovanovic1-2/+5
2013-12-02misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil1-1/+1
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2-10/+6
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-6/+6
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-1/+0
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-6/+4
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-08-28target-mips: fix get_physical_address() #if 0 build errorJames Hogan1-1/+1
2013-08-06target-mips: fix decoding of microMIPS POOL32Axf instructionsLeon Alrae1-6/+54
2013-08-03target-mips: fix 34Kf configuration for DSP ASEYongbok Kim1-4/+3
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-2/+3
2013-07-29target-mips: fix mipsdsp_mul_q31_q31Petar Jovanovic1-1/+1
2013-07-29target-mips: Remove assignment to a variable which is never usedStefan Weil1-1/+0
2013-07-29target-mips: fix mipsdsp_trunc16_sat16_roundPetar Jovanovic1-5/+11
2013-07-28target-mips: fix branch in likely delay slot tcg assertJames Hogan1-45/+17
2013-07-28target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15Petar Jovanovic1-2/+2
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+15
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-14/+17
2013-07-26target-mips: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+144
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+2
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber3-3/+10
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-4/+7
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2-7/+11
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+14
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber1-5/+0
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber2-2/+2
2013-07-09target-mips: Change gen_intermediate_code_internal() argument to MIPSCPUAndreas Färber1-4/+5
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-13/+12
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-13/+0
2013-06-28cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber3-6/+13
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-1/+0
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber3-2/+7
2013-05-20linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung2-2/+3
2013-05-20target-mips: clean-up in BIT_INSVPetar Jovanovic1-10/+6
2013-05-19target-mips: set carry bit correctly in DSPControl registerPetar Jovanovic1-3/+4
2013-05-19target-mips: fix EXTPDP and setting up pos field in the DSPControl regPetar Jovanovic1-5/+5
2013-05-17target-mips: fix incorrect behaviour for EXTPPetar Jovanovic1-2/+1
2013-05-08target-mips: fix incorrect behaviour for INSVPetar Jovanovic1-2/+2
2013-05-08target-mips: add missing check_dspr2 for multiply instructionsPetar Jovanovic1-0/+1
2013-05-03target-mips: fix calculation of overflow for SHLL.PH and SHLL.QBPetar Jovanovic1-24/+6
2013-04-15target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHRPetar Jovanovic1-13/+1
2013-03-17target-mips: fix rndrashift_short_acc and code for EXTR_ instructionsPetar Jovanovic1-14/+9
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-3/+7
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-4/+4
2013-03-12exec: Pass CPUState to cpu_reset_interrupt()Andreas Färber1-3/+2
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber3-7/+11
2013-03-05mips64-linux-user: Enable 64-bit address mode and fpuRichard Henderson1-0/+12
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson2-3/+16
2013-03-05target-mips: Fix accumulator selection for MIPS16 and microMIPSRichard Sandiford1-84/+64
2013-03-04target-mips: fix DSP overflow macro and affected routinesPetar Jovanovic1-42/+48
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+1
2013-02-23target-mips: fix for sign-issue in MULQ_W helperPetar Jovanovic1-1/+1
2013-02-23target-mips: fix for incorrect multiplication with MULQ_S.PHPetar Jovanovic1-1/+1
2013-02-23target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson3-42/+20
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber3-2/+6
2013-02-16target-mips: Introduce QOM realizefn for MIPSCPUAndreas Färber3-2/+20
2013-01-31target-mips: enable access to DSP ASE if implementedPetar Jovanovic1-4/+2
2013-01-31target-mips: Unfuse {,N}M{ADD,SUB}.fmtRichard Sandiford1-8/+17
2013-01-31target-mips: Sign-extend the result of LWRRichard Sandiford1-0/+1
2013-01-31target-mips: Fix signedness of loads in MIPS16 RESTOREsRichard Sandiford1-1/+1
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno3-126/+87
2013-01-31target-mips: use DSP unions for reduction add instructionsAurelien Jarno1-16/+14
2013-01-31target-mips: use DSP unions for unary DSP operatorsAurelien Jarno1-82/+42
2013-01-31target-mips: use DSP unions for binary DSP operatorsAurelien Jarno1-268/+116
2013-01-31target-mips: add unions to access DSP elementsAurelien Jarno1-0/+22
2013-01-31target-mips: generate a reserved instruction exception on CPU without DSPAurelien Jarno1-2/+10
2013-01-31target-mips: copy insn_flags in DisasContextAurelien Jarno1-381/+381
2013-01-31target-mips: fix DSP loads with rd = 0Aurelien Jarno1-5/+0
2013-01-15exec: Return CPUState from qemu_get_cpu()Andreas Färber1-3/+8
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber2-10/+15
2013-01-15target-mips: Clean up mips_cpu_map_tc() documentationAndreas Färber1-5/+9
2013-01-15cpu: Move nr_{cores,threads} fields to CPUStateAndreas Färber1-3/+5
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic1-1/+1
2013-01-08target-mips: Replace macros by inline functionsStefan Weil1-18/+24
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson1-1/+1
2013-01-01target-mips: Use EXCP_SC rather than a magic number陳韋任 (Wei-Ren Chen)1-3/+2
2013-01-01target-mips: Make repl_ph to sign extend to target-longJovanovic, Petar1-1/+2
2013-01-01Fix my email addressDongxue Zhang1-1/+1
2013-01-01target-mips: Remove semicolon from macro definitionStefan Weil1-1/+1
2013-01-01target-mips: Fix for helpers for EXTR_* instructionsPetar Jovanovic1-35/+10
2013-01-01target-mips: Fix incorrect reads and writes to DSPControl registerPetar Jovanovic1-0/+8
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini4-11/+11
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-7/+1
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl1-9/+10
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-06target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic1-8/+9
2012-12-06target-mips: Fix incorrect code and test for INSVPetar Jovanovic1-1/+1
2012-11-24target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno1-1/+0
2012-11-24target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)1-7/+17
2012-11-24target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)1-0/+17
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-22 05:19:38 +0000