aboutsummaryrefslogtreecommitdiffstats
path: root/target-arm
AgeCommit message (Expand)AuthorFilesLines
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell1-2/+2
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2-24/+41
2014-11-04target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell1-6/+5
2014-11-04target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell1-44/+50
2014-11-04target-arm/translate.c: Don't use IS_M()Peter Maydell1-8/+11
2014-11-04target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell1-60/+80
2014-11-04target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell1-8/+8
2014-11-02target-arm: A64: remove redundant storeAlex Bennée1-1/+0
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler2-2/+12
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler1-9/+20
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows8-47/+50
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov1-0/+2
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler1-0/+47
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler2-4/+4
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell1-0/+3
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell1-1/+1
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell2-3/+3
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring9-3/+301
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell3-11/+104
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell2-9/+12
2014-10-24target-arm: add missing PSCI constants needed for PSCI emulationArd Biesheuvel1-0/+40
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring4-6/+6
2014-10-24target-arm: add powered off cpu stateRob Herring3-3/+12
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias5-14/+76
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2-0/+27
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias7-0/+51
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias4-0/+4
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias7-10/+81
2014-09-29target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias1-4/+3
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias1-0/+7
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2-5/+17
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias3-11/+33
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias2-3/+51
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias2-0/+70
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell6-30/+44
2014-09-29target-arm: Implement handling of breakpoint firingPeter Maydell2-15/+66
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell5-2/+136
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson3-0/+36
2014-09-12target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell1-12/+89
2014-09-12target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell1-47/+55
2014-09-12target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell1-0/+19
2014-09-12target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell1-3/+1
2014-09-12target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell1-0/+26
2014-09-12target-arm: Implement handling of fired watchpointsPeter Maydell4-1/+204
2014-09-12target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell2-11/+11
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell5-3/+149
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan1-1/+1
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan1-10/+22
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis1-0/+9
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis1-23/+4
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis2-0/+34
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis1-0/+12
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2-8/+42
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite1-1/+10
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2-11/+10
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell1-1/+2
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell1-1/+8
2014-08-19arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite1-2/+2
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall1-0/+27
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall1-11/+11
2014-08-19target-arm: Implement MDSCR_EL1 as having statePeter Maydell1-1/+3
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2-2/+95
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell6-5/+131
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell1-2/+3
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2-0/+81
2014-08-19target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell1-0/+4
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell3-9/+18
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell4-7/+31
2014-08-19target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell1-14/+20
2014-08-19target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell1-3/+8
2014-08-19target-arm: Collect up the debug cp register definitionsPeter Maydell1-32/+53
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell1-1/+1
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2-0/+5
2014-08-04target-arm: A64: fix TLB flush instructionsAlex Bennée1-2/+8
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée1-2/+2
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil1-1/+1
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2-1/+7
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2-1/+9
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias4-10/+10
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias1-2/+2
2014-08-04target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias1-1/+1
2014-08-04target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias3-24/+24
2014-07-08target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell2-18/+5
2014-06-24Fix new typos (found by codespell)Stefan Weil1-1/+1
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar4-0/+9
2014-06-19target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar1-0/+4
2014-06-19target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possiblePranavkumar Sawargaonkar2-0/+6
2014-06-19target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar5-12/+44
2014-06-19target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell1-1/+1
2014-06-19target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell1-1/+2
2014-06-19target-arm: Add ULL suffix to calculation of page sizePeter Maydell1-1/+1
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2-18/+60
2014-06-16target-arm: Use Common Tables in AES InstructionsTom Musta1-75/+4
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell3-13/+0
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell1-1/+44
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell1-1/+50
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2-19/+16
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell3-1/+85
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell2-4/+1
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2-4/+14
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell2-4/+0
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell1-1/+1
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell7-33/+60
2014-06-09target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell1-12/+12
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel5-7/+347
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
2014-06-09target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell1-0/+1
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini3-4/+3
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini5-22/+50
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson9-16/+10
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2-1/+6
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2-1/+22
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias1-1/+1
2014-05-27target-arm: A64: Generalize update_spsel for the various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Generalize ERET to various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias1-0/+4
2014-05-27target-arm: A64: Forbid ERET to higher or unimplemented ELsEdgar E. Iglesias1-2/+6
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Add a feature flag for EL3Edgar E. Iglesias1-0/+1
2014-05-27target-arm: Add a feature flag for EL2Edgar E. Iglesias1-0/+1
2014-05-27target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias3-2/+17
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias4-6/+12
2014-05-27target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2-4/+4
2014-05-27target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2-4/+4
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias3-5/+5
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias3-8/+8
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias6-10/+11
2014-05-27target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias2-9/+5
2014-05-27target-arm: A32: Use get_mem_index for load/storesEdgar E. Iglesias1-106/+106
2014-05-27target-arm/translate.c: Use get_mem_index() for SRS memory accessesPeter Maydell1-2/+2
2014-05-27target-arm/translate.c: Clean up mmu index handling for ldrt/strtPeter Maydell1-12/+17
2014-05-27target-arm: Move get_mem_index to translate.hEdgar E. Iglesias2-9/+9
2014-05-27target-arm: implement CPACR register logic for ARMv7Fabian Aggeler1-4/+28
2014-05-27target-arm: Fix segfault on startup when KVM enabledChristoffer Dall1-1/+1
2014-05-15Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513'...Peter Maydell2-5/+7
2014-05-13target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell1-0/+7
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela1-5/+0
2014-05-13kvm: reset state from the CPU's reset methodPaolo Bonzini4-4/+17
2014-05-05vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/Michael S. Tsirkin1-1/+1
2014-05-01target-arm: Correct a comment refering to EL0Edgar E. Iglesias1-1/+1
2014-05-01target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias1-12/+12
2014-05-01target-arm: A64: Handle blr lrEdgar E. Iglesias1-1/+2
2014-05-01target-arm: Make vbar_write 64bit friendly on 32bit hostsEdgar E. Iglesias1-1/+1
2014-05-01target-arm: implement WFE/YIELD as a yield for AArch64Rob Herring1-0/+6
2014-05-01target-arm: Implement XScale cache lockdown operations as NOPsPeter Maydell1-0/+15
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée1-1/+1
2014-04-17arm: translate.c: Fix smlald InstructionPeter Crosthwaite1-11/+23
2014-04-17target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang1-2/+0
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell4-3/+13
2014-04-17target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell1-4/+8
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell1-1/+1
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell5-9/+42
2014-04-17target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell1-0/+55
2014-04-17target-arm: Implement RVBAR registerPeter Maydell3-0/+16
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell2-31/+25
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell1-0/+9
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell1-5/+91
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell1-18/+43
2014-04-17target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell1-1/+0
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell1-0/+18
2014-04-17target-arm: Implement AArch64 view of ACTLRPeter Maydell1-1/+2
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell2-16/+19
2014-04-17target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell1-29/+44
2014-04-17target-arm: Add Cortex-A57 processorPeter Maydell1-0/+43
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell5-2/+23
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring6-0/+143
2014-04-17target-arm: Move arm_log_exception() into internals.hPeter Maydell2-31/+31
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell5-11/+40
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell6-7/+100
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell4-4/+24
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring3-18/+29
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell2-10/+16
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell6-6/+128
2014-04-17target-arm: Don't mention PMU in debug feature registerPeter Maydell1-1/+6
2014-04-17target-arm: Add v8 mmu translation supportRob Herring1-32/+77
2014-04-17target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell2-1/+40
2014-04-17target-arm: A64: Add assertion that FP access was checkedPeter Maydell2-24/+59
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell5-6/+320
2014-04-17target-arm: Provide syndrome information for MMU faultsRob Herring2-0/+25
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell6-54/+140
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell5-7/+184
2014-04-17target-arm: Define exception record for AArch64 exceptionsPeter Maydell3-9/+32
2014-04-17target-arm: Implement AArch64 DAIF system registerPeter Maydell2-1/+21
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell8-20/+55
2014-03-27target-arm: Add missing 'static' attributeStefan Weil1-1/+1
2014-03-24target-arm: Fix A64 Neon MLSPeter Maydell1-1/+1
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée3-10/+284
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée3-12/+75
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée4-37/+140
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell3-1/+43
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée1-7/+28
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée1-90/+90
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée4-42/+195
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-22 10:01:23 +0000