diff options
Diffstat (limited to 'lib/header.h')
| -rw-r--r-- | lib/header.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/lib/header.h b/lib/header.h index 63fbb92..2bace93 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1076,7 +1076,7 @@ #define PCI_DVSEC_ID_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */ /* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */ -#define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */ +#define PCI_CXL_DEV_LEN 0x3c /* CXL Device DVSEC Length */ #define PCI_CXL_DEV_CAP 0x0a /* CXL Capability Register */ #define PCI_CXL_DEV_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ #define PCI_CXL_DEV_CAP_IO 0x0002 /* CXL.io Protocol Support */ @@ -1094,6 +1094,12 @@ #define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ #define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */ #define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ +#define PCI_CXL_DEV_CTRL2 0x10 /* CXL Control Register 2 */ +#define PCI_CXL_DEV_CTRL2_DISABLE_CACHING 0x0001 +#define PCI_CXL_DEV_CTRL2_INIT_WB_INVAL 0x0002 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST 0x0003 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN 0x0004 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST 0x0005 #define PCI_CXL_DEV_STATUS2 0x12 #define PCI_CXL_DEV_STATUS_CACHE_INV 0x0001 #define PCI_CXL_DEV_STATUS_RC 0x0002 /* Device Reset Complete */ @@ -1117,6 +1123,13 @@ #define PCI_CXL_DEV_RANGE2_SIZE_LO 0x2c #define PCI_CXL_DEV_RANGE2_BASE_HI 0x30 #define PCI_CXL_DEV_RANGE2_BASE_LO 0x34 +/* From Rev2 */ +#define PCI_CXL_DEV_CAP3 0x38 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD 0x0001 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM 0x0002 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT 0x0003 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG 0x0004 + /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */ #define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */ @@ -1199,6 +1212,7 @@ #define PCI_CXL_FB_PORT_CTRL2 0x18 /* CXL Flex Bus Port Control2 Register */ #define PCI_CXL_FB_CTRL2_NOP_HINT 0x01 /* NOP Hint Enable */ #define PCI_CXL_FB_PORT_STATUS2 0x1c /* CXL Flex Bus Port Status2 Register */ +#define PCI_CXL_FB_NEXT_UNSUPPORTED 0x20 /* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */ #define PCI_CXL_MLD_LEN 0x10 |