diff options
| -rw-r--r-- | lib/header.h | 1 | ||||
| -rw-r--r-- | ls-ecaps.c | 13 | ||||
| -rw-r--r-- | tests/cap-ide | 12 |
3 files changed, 16 insertions, 10 deletions
diff --git a/lib/header.h b/lib/header.h index 0b0ed9a..031912f 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1464,6 +1464,7 @@ #define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ #define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ #define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */ +#define PCI_IDE_SEL_CTL_CFG_EN 0x200 /* Selective IDE for Configuration Requests Enable */ #define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ #define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ #define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ @@ -1512,7 +1512,7 @@ static void cap_ide(struct device *d, int where) { const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" }; - const char *stream_state[] = { "insecure", "secure" }; + const char *stream_state[] = { "insecure", "reserved", "secure" }; const char *aggr[] = { "-", "=2", "=4", "=8" }; u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j; char buf1[16], buf2[16], offs[16]; @@ -1613,7 +1613,7 @@ cap_ide(struct device *d, int where) // Selective IDE Stream Control Register l = get_conf_long(d, off); - printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n", + printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n", offstr(offs, off), i, FLAG(l, PCI_IDE_SEL_CTL_EN), @@ -1621,6 +1621,7 @@ cap_ide(struct device *d, int where) aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)], aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)], FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN), + FLAG(l, PCI_IDE_SEL_CTL_CFG_EN), TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1), ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)), PCI_IDE_SEL_CTL_TC(l), @@ -1664,14 +1665,18 @@ cap_ide(struct device *d, int where) l = get_conf_long(d, off); limit = get_conf_long(d, off + 4); + limit <<= 32; + limit |= (PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l) << 20) | 0xFFFFF; base = get_conf_long(d, off + 8); + base <<= 32; + base |= PCI_IDE_SEL_ADDR_1_BASE_LOW(l) << 20; printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n", offstr(offs, off), i, j, FLAG(l, PCI_IDE_SEL_ADDR_1_VALID), - (base << 32) | PCI_IDE_SEL_ADDR_1_BASE_LOW(l), - (limit << 32) | PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l)); + base, + limit); off += 12; } } diff --git a/tests/cap-ide b/tests/cap-ide index 01a9e09..edae551 100644 --- a/tests/cap-ide +++ b/tests/cap-ide @@ -79,10 +79,10 @@ e1:00.0 Class 0800: Device aaaa:bbbb IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+ IDECtl: FTEn- SelectiveIDE#0 Cap: RID#=1 - SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 - SelectiveIDE#0 Sta: insecure RecvChkFail- - SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0 - SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0 + SelectiveIDE#0 Ctl: En+ NPR- PR- CPL- PCRC- CFG- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 Default + SelectiveIDE#0 Sta: secure RecvChkFail- + SelectiveIDE#0 RID: Valid+ Base=0 Limit=ffff SegBase=0 + SelectiveIDE#0 RID#0: Valid+ Base=0 Limit=ffffffffffffffff Capabilities: [e00 v2] Data Object Exchange DOECap: IntSup- DOECtl: IntEn- @@ -219,8 +219,8 @@ f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 820: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 830: 30 00 01 e0 42 e0 00 01 00 00 00 00 01 00 00 00 -840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +840: 01 00 40 00 02 00 00 00 00 ff ff 00 01 00 00 00 +850: 01 00 f0 ff ff ff ff ff 00 00 00 00 00 00 00 00 860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |