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authorBjorn Helgaas <bhelgaas@google.com>2020-05-21 17:40:29 -0500
committerMartin Mares <mj@ucw.cz>2020-05-25 11:41:14 +0200
commit623ed0e1afa959013f4d7e507dd12cb9e4811577 (patch)
treef3332cc740663df11c1ac87abc7bdaa7dcfaccb1
parent36111a627565f6fa04039aa674abcdaece1aa39e (diff)
downloadpciutils-623ed0e1afa959013f4d7e507dd12cb9e4811577.tar.gz
lspci: Decode PCIe Link Capabilities 2, expand Link Status 2
Decode Link Capabilities 2, which includes the Supported Link Speeds Vector, and decode more fields of Link Status 2. The test case (data from https://bugzilla.kernel.org/show_bug.cgi?id=206837 comment #21) includes a Thunderbolt Downstream Port that advertises 2.5-8GT/s support in Link Capabilities 2. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat
-rw-r--r--lib/header.h10
-rw-r--r--ls-caps.c93
-rw-r--r--tests/cap-exp-lnkcap21317
3 files changed, 1418 insertions, 2 deletions
diff --git a/lib/header.h b/lib/header.h
index bfdcc80..93a6e4f 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -901,6 +901,11 @@
#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
+#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f)
+#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink Supported */
+#define PCI_EXP_LNKCAP2_RETIMER 0x00800000 /* Retimer Supported */
+#define PCI_EXP_LNKCAP2_2RETIMERS 0x01000000 /* 2 Retimers Supported */
+#define PCI_EXP_LNKCAP2_DRS 0x80000000 /* Device Readiness Status */
#define PCI_EXP_LNKCTL2 0x30 /* Link Control */
#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */
@@ -917,6 +922,11 @@
#define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Successful */
#define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Successful */
#define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request */
+#define PCI_EXP_LINKSTA2_RETIMER 0x0040 /* Retimer Detected */
+#define PCI_EXP_LINKSTA2_2RETIMERS 0x0080 /* 2 Retimers Detected */
+#define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */
+#define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */
+#define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */
#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
diff --git a/ls-caps.c b/ls-caps.c
index a6705eb..c8a8bd6 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -649,6 +649,13 @@ cap_msi(struct device *d, int where, int cap)
}
}
+static int exp_downstream_port(int type)
+{
+ return type == PCI_EXP_TYPE_ROOT_PORT ||
+ type == PCI_EXP_TYPE_DOWNSTREAM ||
+ type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
+}
+
static float power_limit(int value, int scale)
{
static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
@@ -1151,6 +1158,29 @@ static void cap_express_dev2(struct device *d, int where, int type)
}
}
+static const char *cap_express_link2_speed_cap(int vector)
+{
+ /*
+ * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
+ * permitted to skip support for any data rates between 2.5GT/s and the
+ * highest supported rate.
+ */
+ if (vector & 0x60)
+ return "RsvdP";
+ if (vector & 0x10)
+ return "2.5-32GT/s";
+ if (vector & 0x08)
+ return "2.5-16GT/s";
+ if (vector & 0x04)
+ return "2.5-8GT/s";
+ if (vector & 0x02)
+ return "2.5-5GT/s";
+ if (vector & 0x01)
+ return "2.5GT/s";
+
+ return "Unknown";
+}
+
static const char *cap_express_link2_speed(int type)
{
switch (type)
@@ -1202,12 +1232,59 @@ static const char *cap_express_link2_transmargin(int type)
}
}
+static const char *cap_express_link2_crosslink_res(int crosslink)
+{
+ switch (crosslink)
+ {
+ case 0:
+ return "unsupported";
+ case 1:
+ return "Upstream Port";
+ case 2:
+ return "Downstream Port";
+ default:
+ return "incomplete";
+ }
+}
+
+static const char *cap_express_link2_component(int presence)
+{
+ switch (presence)
+ {
+ case 0:
+ return "Link Down - Not Determined";
+ case 1:
+ return "Link Down - Not Present";
+ case 2:
+ return "Link Down - Present";
+ case 4:
+ return "Link Up - Present";
+ case 5:
+ return "Link Up - Present and DRS Received";
+ default:
+ return "Reserved";
+ }
+}
+
static void cap_express_link2(struct device *d, int where, int type)
{
+ u32 l = 0;
u16 w;
if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
(d->dev->dev != 0 || d->dev->func != 0))) {
+ /* Link Capabilities 2 was reserved before PCIe r3.0 */
+ l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
+ if (l) {
+ printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
+ "Retimer%c 2Retimers%c DRS%c\n",
+ cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
+ FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
+ FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
+ FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
+ FLAG(l, PCI_EXP_LNKCAP2_DRS));
+ }
+
w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
@@ -1227,13 +1304,25 @@ static void cap_express_link2(struct device *d, int where, int type)
w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
- "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
+ "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n"
+ "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
- FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
+ FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
+ FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
+ FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
+ cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
+
+ if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
+ printf(", DRS%c\n"
+ "\t\t\t DownstreamComp: %s\n",
+ FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
+ cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
+ } else
+ printf("\n");
}
static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
diff --git a/tests/cap-exp-lnkcap2 b/tests/cap-exp-lnkcap2
new file mode 100644
index 0000000..d7b159c
--- /dev/null
+++ b/tests/cap-exp-lnkcap2
@@ -0,0 +1,1317 @@
+00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port #1 (rev f1) (prog-if 00 [Normal decode])
+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 255
+ Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
+ I/O behind bridge: 0000d000-0000dfff [size=4K]
+ Memory behind bridge: e8000000-e8ffffff [size=16M]
+ Prefetchable memory behind bridge: 0000000070000000-0000000081ffffff [size=288M]
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+ BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag- RBE+
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 256 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
+ LnkCap: Port #1, Speed 8GT/s, Width x4, ASPM not supported
+ ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s (ok), Width x4 (ok)
+ TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 25.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet+ LinkState+
+ RootCap: CRSVisible-
+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+
+ AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
+ AtomicOpsCtl: ReqEn- EgressBlck-
+ LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+ Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
+ Address: fee00238 Data: 0000
+ Capabilities: [90] Subsystem: Lenovo Device 225a
+ Capabilities: [a0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ RootCmd: CERptEn- NFERptEn- FERptEn-
+ RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
+ FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
+ ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
+ Capabilities: [140 v1] Access Control Services
+ ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
+ ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+ Capabilities: [200 v1] L1 PM Substates
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=40us PortTPowerOnTime=44us
+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
+ T_CommonMode=255us LTR1.2_Threshold=163840ns
+ L1SubCtl2: T_PwrOn=44us
+ Capabilities: [220 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+ LaneErrStat: 0
+00: 86 80 10 9d 07 04 10 00 f1 00 04 06 00 00 81 00
+10: 00 00 00 00 00 00 00 00 00 02 02 00 d0 d0 00 20
+20: 00 e8 f0 e8 01 70 f1 81 00 00 00 00 00 00 00 00
+30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 02 00
+40: 10 80 42 01 01 80 00 00 20 00 10 00 43 40 72 01
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+60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00
+70: 03 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
+80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00
+90: 0d a0 00 00 aa 17 5a 22 00 00 00 00 00 00 00 00
+a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00
+b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+d0: 11 10 00 07 42 18 00 00 08 00 9e 09 00 00 00 00
+e0: 00 f7 f3 00 00 00 00 00 06 80 12 00 00 00 00 00
+f0: 50 01 00 00 00 03 00 40 b3 0f 41 08 04 c0 00 01
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+8b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+900: 06 b0 c4 0c 96 0f 64 07 00 00 00 00 00 00 00 00
+910: 00 00 00 00 00 00 00 00 00 00 06 40 00 00 00 00
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+
+02:00.0 3D controller: NVIDIA Corporation GP108M [GeForce MX150] (rev a1)
+ Subsystem: Lenovo Device 225b
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 255
+ Region 0: Memory at e8000000 (32-bit, non-prefetchable)
+ Region 1: Memory at 70000000 (64-bit, prefetchable)
+ Region 3: Memory at 80000000 (64-bit, prefetchable)
+ Region 5: I/O ports at d000 [disabled]
+ Expansion ROM at fff80000 [disabled]
+ Capabilities: [60] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [68] MSI: Enable- Count=1/1 Maskable- 64bit+
+ Address: 0000000000000000 Data: 0000
+ Capabilities: [78] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 <64us
+ ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
+ MaxPayload 256 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
+ ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s (ok), Width x4 (ok)
+ TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range AB, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Via message, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, TPHComp-, ExtTPHComp-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
+ AtomicOpsCtl: ReqEn-
+ LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+ Capabilities: [100 v1] Virtual Channel
+ Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
+ Arb: Fixed- WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+ Status: NegoPending- InProgress-
+ Capabilities: [250 v1] Latency Tolerance Reporting
+ Max snoop latency: 3145728ns
+ Max no snoop latency: 3145728ns
+ Capabilities: [258 v1] L1 PM Substates
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=255us PortTPowerOnTime=10us
+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
+ T_CommonMode=0us LTR1.2_Threshold=0ns
+ L1SubCtl2: T_PwrOn=10us
+ Capabilities: [128 v1] Power Budgeting <?>
+ Capabilities: [420 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [600 v1] Vendor Specific Information: ID=0001 Rev=1 Len=024 <?>
+ Capabilities: [900 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+ LaneErrStat: 0
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+
+08:00.0 PCI bridge: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] (rev 01) (prog-if 00 [Normal decode])
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 128 bytes
+ Interrupt: pin A routed to IRQ 255
+ Bus: primary=08, secondary=09, subordinate=09, sec-latency=0
+ I/O behind bridge: [disabled]
+ Memory behind bridge: e6000000-e60fffff [size=1M]
+ Prefetchable memory behind bridge: [disabled]
+ Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
+ BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
+ PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+
+ Address: 00000000fee002b8 Data: 0000
+ Capabilities: [ac] Subsystem: Device 2222:1111
+ Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0
+ ExtTag+ RBE+
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us
+ ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
+ LnkCtl: ASPM Disabled; Disabled- CommClk+
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s (ok), Width x4 (ok)
+ TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+ Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+ Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet+ LinkState-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis-, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, ARIFwd-
+ AtomicOpsCap: Routing-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
+ AtomicOpsCtl: EgressBlck-
+ LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [100 v1] Device Serial Number 21-df-cc-fa-34-c9-a0-00
+ Capabilities: [200 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [300 v1] Virtual Channel
+ Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
+ Arb: Fixed- WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+ Status: NegoPending- InProgress-
+ Capabilities: [400 v1] Power Budgeting <?>
+ Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=0e0 <?>
+ Capabilities: [700 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+ LaneErrStat: 0
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+
+09:00.0 System peripheral: Intel Corporation JHL6240 Thunderbolt 3 NHI (Low Power) [Alpine Ridge LP 2016] (rev 01)
+ Subsystem: Device 2222:1111
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 128 bytes
+ Interrupt: pin A routed to IRQ 255
+ Region 0: Memory at e6000000 (32-bit, non-prefetchable)
+ Region 1: Memory at e6040000 (32-bit, non-prefetchable)
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [88] MSI: Enable- Count=1/1 Maskable- 64bit+
+ Address: 0000000000000000 Data: 0000
+ Capabilities: [c0] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 <8us
+ ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us
+ ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s (ok), Width x4 (ok)
+ TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range B, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, TPHComp-, ExtTPHComp-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
+ AtomicOpsCtl: ReqEn-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
+ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+ Capabilities: [a0] MSI-X: Enable+ Count=16 Masked-
+ Vector table: BAR=1 offset=00000000
+ PBA: BAR=1 offset=00000fa0
+ Capabilities: [100 v1] Device Serial Number 21-df-cc-fa-34-c9-a0-00
+ Capabilities: [200 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [300 v1] Virtual Channel
+ Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
+ Arb: Fixed- WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+ Status: NegoPending- InProgress-
+ Capabilities: [400 v1] Power Budgeting <?>
+ Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=088 <?>
+ Capabilities: [600 v1] Latency Tolerance Reporting
+ Max snoop latency: 3145728ns
+ Max no snoop latency: 3145728ns
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generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-23 10:04:53 +0000