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author | Pali Rohár <pali@kernel.org> | 2021-12-27 00:34:08 +0100 |
---|---|---|
committer | Martin Mares <mj@ucw.cz> | 2021-12-27 00:55:40 +0100 |
commit | 41e49114068eb53a7a46d2ecd46f755962c41f1a (patch) | |
tree | 0dc11a5b54aa7479e3fa9a7e7ae85e25fecaa880 | |
parent | 1eb437a40746c1791e7248193a17f92ddbabdd21 (diff) | |
download | pciutils-41e49114068eb53a7a46d2ecd46f755962c41f1a.tar.gz |
lspci: Show Slot Power Limit values above EFh
PCI Express Base Specification rev. 3.0 has the following definition for
the Slot Power Limit Value:
=======================================================================
When the Slot Power Limit Scale field equals 00b (1.0x) and Slot Power
Limit Value exceeds EFh, the following alternative encodings are used:
F0h = 250 W Slot Power Limit
F1h = 275 W Slot Power Limit
F2h = 300 W Slot Power Limit
F3h to FFh = Reserved for Slot Power Limit values above 300 W
=======================================================================
Replace function power_limit() by show_power_limit() which also prints
power limit value. Show reserved value as string ">300W".
-rw-r--r-- | ls-caps.c | 30 |
1 files changed, 22 insertions, 8 deletions
@@ -656,10 +656,22 @@ static int exp_downstream_port(int type) type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */ } -static float power_limit(int value, int scale) +static void show_power_limit(int value, int scale) { static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 }; - return value * scales[scale]; + static const int scale0_values[3] = { 250, 275, 300 }; + + if (scale == 0 && value >= 0xF0) + { + /* F3h to FFh = Reserved for Slot Power Limit values above 300 W */ + if (value >= 0xF3) + { + printf(">300W"); + return; + } + value = scale0_values[value - 0xF0]; + } + printf("%gW", value * scales[scale]); } static const char *latency_l0s(int value) @@ -701,9 +713,10 @@ static void cap_express_dev(struct device *d, int where, int type) FLAG(t, PCI_EXP_DEVCAP_FLRESET)); if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) - printf(" SlotPowerLimit %.3fW", - power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, - (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); + { + printf(" SlotPowerLimit "); + show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26); + } printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL); @@ -871,9 +884,10 @@ static void cap_express_slot(struct device *d, int where) FLAG(t, PCI_EXP_SLTCAP_PWRI), FLAG(t, PCI_EXP_SLTCAP_HPC), FLAG(t, PCI_EXP_SLTCAP_HPS)); - printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n", - (t & PCI_EXP_SLTCAP_PSN) >> 19, - power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15), + printf("\t\t\tSlot #%d, PowerLimit ", + (t & PCI_EXP_SLTCAP_PSN) >> 19); + show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15); + printf("; Interlock%c NoCompl%c\n", FLAG(t, PCI_EXP_SLTCAP_INTERLOCK), FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP)); |