diff options
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 8 | ||||
| -rw-r--r-- | include/asm-ppc/pgtable.h | 5 |
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 86bc7271fc326..402158d9e4b96 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -443,6 +443,10 @@ DataStoreTLBMiss: * above. */ rlwimi r21, r20, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. + * It is bit 25 in the Linux PTE and bit 30 in the TWC + */ + rlwimi r21, r20, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 @@ -579,6 +583,10 @@ DARFixed: * It is bit 27 of both the Linux PTE and the TWC */ rlwimi r21, r20, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. + * It is bit 25 in the Linux PTE and bit 30 in the TWC + */ + rlwimi r21, r20, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 mfspr r21, MD_TWC /* get the pte address again */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 2ba37d3ccfbf7..6cfc5fc57138b 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -298,12 +298,13 @@ extern unsigned long vmalloc_start; #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ -/* These three software bits must be masked out when the entry is loaded - * into the TLB, 2 SW bits free. +/* These four software bits must be masked out when the entry is loaded + * into the TLB, 1 SW bits left(0x0080). */ #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ +#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ /* Setting any bits in the nibble with the follow two controls will * require a TLB exception handler change. It is assumed unused bits |