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| author | Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | 2011-10-10 13:30:16 +0200 |
|---|---|---|
| committer | Willy Tarreau <w@1wt.eu> | 2012-04-09 15:02:40 +0200 |
| commit | cbd2de43d233e2f85c866855d68e72311abc5749 (patch) | |
| tree | a42be4989e79795acf47503d6a57b42e5511dbb4 | |
| parent | c6f1e91508e7f6141531bdee1d900f83ff86f7bf (diff) | |
| download | linux-2.4-cbd2de43d233e2f85c866855d68e72311abc5749.tar.gz | |
8xx: Set correct HW pte flags in DTLB Error too
DTLB Error needs to adjust the HW PTE bits as DTLB Miss
does.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Willy Tarreau <w@1wt.eu>
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 402158d9e4b96e..4bcd9b3d87a99a 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -592,7 +592,12 @@ DARFixed: mfspr r21, MD_TWC /* get the pte address again */ ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE stw r20, 0(r21) /* and update pte in table */ - xori r20, r20, _PAGE_RW /* RW bit is inverted */ + rlwimi r20, r20, 32-2, _PAGE_USER>>2 /* Copy USER to Encoding */ + /* r21 = (r20 & _PAGE_RW) >> 1 */ + rlwinm r21, r20, 32-1, _PAGE_RW>>1 + or r20, r21, r20 + /* invert RW and 0x200 bits */ + xori r20, r20, _PAGE_RW | 0x200 b finish_DTLB 2: mfspr r20, M_TW /* Restore registers */ |