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authorAnup Patel <apatel@ventanamicro.com>2023-11-28 20:26:26 +0530
committerWill Deacon <will@kernel.org>2024-02-09 15:45:22 +0000
commit8cd71ca57fb01ad880524496bfed06d3ae421ea3 (patch)
tree3d90374af6b57c6a42ec619a5de6dc0e0759e46e
parent8d02d5a895c30d679d2ec0f235a98ee324972cef (diff)
downloadkvmtool-8cd71ca57fb01ad880524496bfed06d3ae421ea3.tar.gz
riscv: Add Zicond extension support
When the Zicond extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20231128145628.413414-9-apatel@ventanamicro.com Signed-off-by: Will Deacon <will@kernel.org>
-rw-r--r--riscv/fdt.c1
-rw-r--r--riscv/include/kvm/kvm-config-arch.h3
2 files changed, 4 insertions, 0 deletions
diff --git a/riscv/fdt.c b/riscv/fdt.c
index 0fe0f0ba..1124fa12 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -28,6 +28,7 @@ struct isa_ext_info isa_info_arr[] = {
{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
+ {"zicond", KVM_RISCV_ISA_EXT_ZICOND},
{"zicsr", KVM_RISCV_ISA_EXT_ZICSR},
{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 49eb3e68..48d07700 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -61,6 +61,9 @@ struct kvm_config_arch {
OPT_BOOLEAN('\0', "disable-zicntr", \
&(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR], \
"Disable Zicntr Extension"), \
+ OPT_BOOLEAN('\0', "disable-zicond", \
+ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICOND], \
+ "Disable Zicond Extension"), \
OPT_BOOLEAN('\0', "disable-zicsr", \
&(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICSR], \
"Disable Zicsr Extension"), \