aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/cxl/acpi.c
AgeCommit message (Expand)AuthorFilesLines
2024-05-01cxl/acpi: Cleanup __cxl_parse_cfmws()Dan Williams1-42/+51
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-1/+1
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang1-12/+1
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang1-3/+5
2024-02-20cxl/acpi: Fix load failures due to single window creation failureDan Williams1-18/+28
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-4/+2
2023-12-22cxl: Store the access coordinates for the generic portsDave Jiang1-0/+25
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-3/+129
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+3
2023-09-22cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook1-2/+2
2023-07-18cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao1-1/+1
2023-07-18cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao1-2/+1
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-90/+116
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-1/+1
2023-06-25cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter1-28/+63
2023-06-25cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter1-45/+45
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-30/+21
2023-02-10Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-1/+2
2023-02-10cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-1/+2
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-1/+1
2023-01-26cxl: fix spelling mistakesRandy Dunlap1-1/+1
2023-01-25cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams1-1/+0
2022-12-05cxl: update names for interleave ways conversion macrosDave Jiang1-3/+3
2022-12-05cxl: update names for interleave granularity conversion macrosDave Jiang1-2/+2
2022-12-05cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter1-1/+2
2022-12-05cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield1-0/+5
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-3/+134
2022-12-03cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield1-3/+134
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-5/+46
2022-12-02cxl/ACPI: Register CXL host ports by bridge deviceRobert Richter1-18/+20
2022-12-02tools/testing/cxl: Make mock CEDT parsing more robustDan Williams1-0/+4
2022-12-02cxl/acpi: Move rescan to the workqueueDan Williams1-2/+15
2022-12-01cxl/acpi: Simplify cxl_nvdimm_bridge probingDan Williams1-0/+1
2022-11-14cxl/acpi: Improve debug messages in cxl_acpi_probe()Robert Richter1-4/+8
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-5/+2
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter1-2/+0
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams1-0/+6
2022-08-01cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams1-0/+7
2022-07-21cxl/port: Record parent dport when adding portsDan Williams1-2/+1
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams1-4/+36
2022-07-21cxl/acpi: Track CXL resources in iomem_resourceDan Williams1-3/+141
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-1/+3
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams1-15/+19
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-7/+10
2022-04-28cxl/acpi: Add root device lockdep validationDan Williams1-0/+13
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams1-1/+1
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky1-1/+2
2022-02-08cxl/core/port: Add switch port enumerationDan Williams1-16/+1
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-1/+1
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-25/+1
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-28/+15
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-59/+8
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams1-1/+1
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams1-0/+2
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams1-5/+9
2022-02-08cxl: Prove CXL lockingDan Williams1-5/+5
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky1-5/+0
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky1-2/+2
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky1-14/+8
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky1-2/+11
2021-11-15ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield1-1/+2
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-0/+2
2021-11-15cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams1-147/+87
2021-10-08cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBSAlison Schofield1-4/+6
2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams1-24/+60
2021-09-21cxl/bus: Populate the target list at decoder createDan Williams1-1/+12
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-15/+21
2021-09-07cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield1-4/+8
2021-06-17cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield1-0/+122
2021-06-17cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield1-5/+95
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams1-2/+35
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams1-1/+19
2021-06-09cxl/acpi: Enumerate host bridge root portsDan Williams1-1/+92
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-1/+42
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+39
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-26 14:55:36 +0000