Age | Commit message (Expand) | Author | Files | Lines |
2023-09-12 | clk: tegra: fix error return case for recalc_rate | Timo Alho | 1 | -1/+1 |
2023-08-30 | Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ... | Stephen Boyd | 1 | -4/+2 |
2023-08-04 | clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() | Andy Shevchenko | 1 | -4/+2 |
2023-07-19 | clk: Explicitly include correct DT includes | Rob Herring | 5 | -5/+3 |
2023-07-04 | clk: tegra: Avoid calling an uninitialized function | Thierry Reding | 1 | -3/+12 |
2023-06-26 | Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', 'cl... | Stephen Boyd | 1 | -0/+2 |
2023-06-14 | clk: tegra: tegra124-emc: Fix potential memory leak | Yuan Can | 1 | -0/+2 |
2023-06-08 | clk: tegra: super: Switch to determine_rate | Maxime Ripard | 1 | -4/+11 |
2023-06-08 | clk: tegra: periph: Switch to determine_rate | Maxime Ripard | 1 | -5/+11 |
2023-06-08 | clk: tegra: periph: Add a determine_rate hook | Maxime Ripard | 1 | -0/+1 |
2023-06-08 | clk: tegra: super: Add a determine_rate hook | Maxime Ripard | 1 | -0/+1 |
2023-06-08 | clk: tegra: bpmp: Add a determine_rate hook | Maxime Ripard | 1 | -0/+1 |
2023-04-25 | Merge branches 'clk-xilinx', 'clk-broadcom' and 'clk-platform' into clk-next | Stephen Boyd | 2 | -10/+12 |
2023-03-29 | clk: tegra20: fix gcc-7 constant overflow warning | Arnd Bergmann | 1 | -14/+14 |
2023-03-28 | clk: tegra: Convert to platform remove callback returning void | Uwe Kleine-König | 1 | -5/+3 |
2023-03-28 | clk: tegra: Don't warn three times about failure to unregister | Uwe Kleine-König | 2 | -6/+10 |
2022-11-19 | clk: tegra: Support BPMP-FW ABI deny flags | Peter De Schrijver | 1 | -3/+34 |
2022-10-14 | clk: tegra: Fix Tegra PWM parent clock | Jon Hunter | 5 | -0/+5 |
2022-10-04 | Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'c... | Stephen Boyd | 6 | -1/+6 |
2022-08-22 | clk: tegra20: Fix refcount leak in tegra20_clock_init | Miaoqian Lin | 1 | -0/+1 |
2022-08-22 | clk: tegra: Fix refcount leak in tegra114_clock_init | Miaoqian Lin | 1 | -0/+1 |
2022-08-22 | clk: tegra: Fix refcount leak in tegra210_clock_init | Miaoqian Lin | 1 | -0/+1 |
2022-08-22 | clk: move from strlcpy with unused retval to strscpy | Wolfram Sang | 1 | -1/+1 |
2022-08-19 | clk: tegra: Add missing of_node_put() | Liang He | 2 | -0/+2 |
2022-05-06 | clk: tegra: Update kerneldoc to match prototypes | Thierry Reding | 1 | -4/+4 |
2022-05-04 | clk: tegra: Replace .round_rate() with .determine_rate() | Rajkumar Kasirajan | 1 | -5/+10 |
2022-05-04 | clk: tegra: Register clocks from root to leaf | Timo Alho | 1 | -16/+56 |
2022-05-04 | clk: tegra: Add missing reset deassertion | Diogo Ivo | 1 | -0/+12 |
2022-03-11 | clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver | Miaoqian Lin | 1 | -0/+1 |
2021-12-15 | clk: tegra: Support runtime PM and power domain | Dmitry Osipenko | 8 | -54/+420 |
2021-12-15 | clk: tegra: Make vde a child of pll_p on tegra114 | Dmitry Osipenko | 1 | -1/+1 |
2021-09-02 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2 | -6/+2 |
2021-08-29 | clk: tegra: fix old-style declaration | Arnd Bergmann | 1 | -1/+1 |
2021-08-11 | clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock | Dmitry Osipenko | 1 | -5/+1 |
2021-07-27 | clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops | Dmitry Osipenko | 1 | -0/+10 |
2021-06-25 | clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator | Alexandru Ardelean | 1 | -2/+2 |
2021-06-02 | clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing() | Yang Yingliang | 1 | -1/+3 |
2021-05-31 | clk: tegra: Don't deassert reset on enabling clocks | Dmitry Osipenko | 3 | -13/+1 |
2021-05-31 | clk: tegra: Mark external clocks as not having reset control | Dmitry Osipenko | 1 | -3/+3 |
2021-05-31 | clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling | Dmitry Osipenko | 2 | -3/+15 |
2021-05-31 | clk: tegra: Don't allow zero clock rate for PLLs | Dmitry Osipenko | 1 | -0/+3 |
2021-05-31 | clk: tegra: Halve SCLK rate on Tegra20 | Dmitry Osipenko | 1 | -3/+3 |
2021-05-31 | clk: tegra: Ensure that PLLU configuration is applied properly | Dmitry Osipenko | 1 | -5/+4 |
2021-05-31 | clk: tegra: Fix refcounting of gate clocks | Dmitry Osipenko | 2 | -25/+58 |
2021-05-31 | clk: tegra30: Use 300MHz for video decoder by default | Dmitry Osipenko | 1 | -1/+1 |
2021-03-24 | clk: tegra: Don't enable PLLE HW sequencer at init | JC Kuo | 1 | -12/+0 |
2021-03-24 | clk: tegra: Add PLLE HW power sequencer control | JC Kuo | 1 | -1/+52 |
2021-02-22 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2 | -4/+2 |
2021-02-20 | Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Linus Torvalds | 5 | -15/+75 |
2021-02-11 | clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s... | Lee Jones | 1 | -0/+1 |
2021-02-11 | clk: tegra: clk-tegra30: Remove unused variable 'reg' | Lee Jones | 1 | -4/+1 |
2021-01-12 | clk: tegra30: Add hda clock default rates to clock driver | Peter Geis | 1 | -0/+2 |
2021-01-05 | memory: tegra124-emc: Make driver modular | Dmitry Osipenko | 5 | -15/+75 |
2020-12-21 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 4 | -6/+7 |
2020-12-10 | clk: tegra: Fix duplicated SE clock entry | Dmitry Osipenko | 2 | -1/+2 |
2020-11-26 | clk: tegra: bpmp: Clamp clock rates on requests | Sivaram Nair | 1 | -3/+3 |
2020-11-20 | clk: tegra: Do not return 0 on failure | Nicolin Chen | 1 | -2/+2 |
2020-11-06 | clk: tegra: Export Tegra20 EMC kernel symbols | Dmitry Osipenko | 1 | -0/+3 |
2020-10-22 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -1/+1 |
2020-09-23 | clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() | Stephen Boyd | 1 | -1/+1 |
2020-09-21 | clk: tegra: Fix missing prototype for tegra210_clk_register_emc() | Thierry Reding | 1 | -0/+2 |
2020-09-21 | clk: tegra: Always program PLL_E when enabled | Thierry Reding | 1 | -3/+0 |
2020-09-21 | clk: tegra: Capitalization fixes | Thierry Reding | 1 | -2/+2 |
2020-07-27 | clk: tegra: pll: Improve PLLM enable-state detection | Dmitry Osipenko | 1 | -5/+15 |
2020-06-10 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 10 | -32/+700 |
2020-05-12 | clk: tegra: Fix initial rate for pll_a on Tegra124 | Thierry Reding | 1 | -1/+1 |
2020-05-12 | clk: tegra: Add Tegra210 CSI TPG clock gate | Sowjanya Komatineni | 1 | -0/+7 |
2020-05-12 | clk: tegra30: Use custom CCLK implementation | Dmitry Osipenko | 1 | -2/+4 |
2020-05-12 | clk: tegra20: Use custom CCLK implementation | Dmitry Osipenko | 1 | -2/+5 |
2020-05-12 | clk: tegra: cclk: Add helpers for handling PLLX rate changes | Dmitry Osipenko | 2 | -0/+36 |
2020-05-12 | clk: tegra: pll: Add pre/post rate-change hooks | Dmitry Osipenko | 2 | -1/+17 |
2020-05-12 | clk: tegra: Add custom CCLK implementation | Dmitry Osipenko | 3 | -2/+188 |
2020-05-12 | clk: tegra: Remove the old emc_mux clock for Tegra210 | Joseph Lo | 1 | -19/+31 |
2020-05-12 | clk: tegra: Implement Tegra210 EMC clock | Joseph Lo | 3 | -0/+373 |
2020-05-12 | clk: tegra: Export functions for EMC clock scaling | Joseph Lo | 1 | -0/+26 |
2020-05-12 | clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 | Joseph Lo | 1 | -0/+11 |
2020-05-12 | clk: tegra: Rename Tegra124 EMC clock source file | Thierry Reding | 4 | -6/+2 |
2020-03-24 | clk: tegra: Use NULL for pointer initialization | Stephen Boyd | 1 | -1/+1 |
2020-03-12 | clk: tegra: Remove audio clocks configuration from clock driver | Sowjanya Komatineni | 5 | -15/+10 |
2020-03-12 | clk: tegra: Remove tegra_pmc_clk_init along with clk ids | Sowjanya Komatineni | 9 | -201/+19 |
2020-03-12 | clk: tegra: Remove CLK_M_DIV fixed clocks | Sowjanya Komatineni | 6 | -45/+0 |
2020-03-12 | clk: tegra: Fix Tegra PMC clock out parents | Sowjanya Komatineni | 1 | -6/+6 |
2020-03-12 | clk: tegra: Add Tegra OSC to clock lookup | Sowjanya Komatineni | 6 | -0/+14 |
2020-03-12 | clk: tegra: Add support for OSC_DIV fixed clocks | Sowjanya Komatineni | 6 | -0/+34 |
2020-01-31 | Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '... | Stephen Boyd | 5 | -11/+15 |
2020-01-10 | clk: tegra20/30: Explicitly set parent clock for Video Decoder | Dmitry Osipenko | 2 | -2/+2 |
2020-01-10 | clk: tegra20/30: Don't pre-initialize displays parent clock | Dmitry Osipenko | 2 | -4/+0 |
2020-01-10 | clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul... | Dmitry Osipenko | 1 | -2/+7 |
2020-01-10 | clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() | Sowjanya Komatineni | 1 | -2/+1 |
2020-01-08 | clk: tegra: Mark fuse clock as critical | Stephen Warren | 1 | -1/+5 |
2019-12-24 | clk: tegra: Fix double-free in tegra_clk_init() | Dmitry Osipenko | 1 | -1/+3 |
2019-11-13 | clk: tegra: Use match_string() helper to simplify the code | YueHaibing | 1 | -8/+4 |
2019-11-11 | clk: tegra: Fix build error without CONFIG_PM_SLEEP | YueHaibing | 1 | -0/+2 |
2019-11-11 | clk: tegra: Optimize PLLX restore on Tegra20/30 | Dmitry Osipenko | 2 | -18/+32 |
2019-11-11 | clk: tegra: Add suspend and resume support on Tegra210 | Sowjanya Komatineni | 3 | -4/+163 |
2019-11-11 | clk: tegra: Share clk and rst register defines with Tegra clock driver | Sowjanya Komatineni | 2 | -45/+45 |
2019-11-11 | clk: tegra: Use fence_udelay() during PLLU init | Sowjanya Komatineni | 1 | -4/+4 |
2019-11-11 | clk: tegra: clk-dfll: Add suspend and resume support | Sowjanya Komatineni | 3 | -0/+59 |
2019-11-11 | clk: tegra: clk-super: Add restore-context support | Sowjanya Komatineni | 1 | -0/+27 |
2019-11-11 | clk: tegra: clk-super: Fix to enable PLLP branches to CPU | Sowjanya Komatineni | 4 | -1/+39 |
2019-11-11 | clk: tegra: periph: Add restore_context support | Sowjanya Komatineni | 2 | -0/+37 |
2019-11-11 | clk: tegra: Support for OSC context save and restore | Sowjanya Komatineni | 2 | -0/+16 |
2019-11-11 | clk: tegra: pll: Save and restore pll context | Sowjanya Komatineni | 1 | -32/+54 |
2019-11-11 | clk: tegra: pllout: Save and restore pllout context | Sowjanya Komatineni | 1 | -0/+9 |
2019-11-11 | clk: tegra: divider: Save and restore divider rate | Sowjanya Komatineni | 1 | -0/+11 |
2019-11-11 | clk: tegra: Reimplement SOR clocks on Tegra210 | Thierry Reding | 1 | -16/+55 |
2019-11-11 | clk: tegra: Reimplement SOR clock on Tegra124 | Thierry Reding | 1 | -9/+13 |
2019-11-11 | clk: tegra: Rename sor0_lvds to sor0_out | Thierry Reding | 3 | -8/+8 |
2019-11-11 | clk: tegra: Move SOR0 implementation to Tegra124 | Thierry Reding | 2 | -8/+49 |
2019-11-11 | clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC | Thierry Reding | 2 | -2/+2 |
2019-11-11 | clk: tegra: Add Tegra20/30 EMC clock implementation | Dmitry Osipenko | 5 | -52/+339 |
2019-07-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -8/+12 |
2019-06-28 | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds | 1 | -0/+2 |
2019-06-25 | clk: tegra: Do not enable PLL_RE_VCO on Tegra210 | Thierry Reding | 1 | -1/+0 |
2019-06-25 | clk: tegra: Warn if an enabled PLL is in IDDQ | Thierry Reding | 1 | -1/+5 |
2019-06-25 | clk: tegra: Do not warn unnecessarily | Thierry Reding | 1 | -2/+3 |
2019-06-25 | clk: tegra210: fix PLLU and PLLU_OUT1 | JC Kuo | 1 | -4/+4 |
2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner | 1 | -4/+1 |
2019-06-14 | clk: tegra210: Fix default rates for HDA clocks | Jon Hunter | 1 | -0/+2 |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner | 1 | -9/+1 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner | 20 | -240/+20 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 5 | -49/+5 |
2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 1 | -0/+1 |
2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 4 | -0/+4 |
2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd | 4 | -40/+77 |
2019-05-07 | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-... | Stephen Boyd | 1 | -1/+1 |
2019-04-25 | clk: tegra: divider: Mark Memory Controller clock as read-only | Dmitry Osipenko | 1 | -1/+2 |
2019-04-25 | clk: tegra: emc: Replace BUG() with WARN_ONCE() | Dmitry Osipenko | 1 | -1/+4 |
2019-04-25 | clk: tegra: emc: Fix EMC max-rate clamping | Dmitry Osipenko | 1 | -7/+10 |
2019-04-25 | clk: tegra: emc: Support multiple RAM codes | Dmitry Osipenko | 1 | -14/+23 |
2019-04-25 | clk: tegra: emc: Don't enable EMC clock manually | Dmitry Osipenko | 1 | -2/+0 |
2019-04-25 | clk: tegra124: Remove lock-enable bit from PLLM | Dmitry Osipenko | 1 | -2/+1 |
2019-04-25 | clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider | Dmitry Osipenko | 1 | -2/+2 |
2019-04-23 | clk: core: replace clk_{readl,writel} with {readl,writel} | Jonas Gorski | 2 | -5/+5 |
2019-04-19 | clk: tegra: Don't enable already enabled PLLs | Dmitry Osipenko | 1 | -13/+37 |
2019-04-11 | clk: tegra: Make tegra_clk_super_mux_ops static | YueHaibing | 1 | -1/+1 |
2019-03-14 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -9/+9 |
2019-03-08 | Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ... | Stephen Boyd | 1 | -9/+9 |
2019-02-22 | clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings | YueHaibing | 1 | -9/+9 |
2019-02-18 | clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static | Wei Yongjun | 1 | -1/+1 |
2019-02-15 | Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Arnd Bergmann | 7 | -98/+913 |
2019-02-06 | clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 | Peter De Schrijver | 2 | -1/+6 |
2019-02-06 | clk: tegra: dfll: add CVB tables for Tegra210 | Joseph Lo | 2 | -0/+427 |
2019-02-06 | clk: tegra: dfll: round down voltages based on alignment | Joseph Lo | 1 | -8/+13 |
2019-02-06 | clk: tegra: dfll: support PWM regulator control | Joseph Lo | 1 | -67/+377 |
2019-02-06 | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 4 | -14/+59 |
2019-02-06 | clk: tegra: dfll: registration for multiple SoCs | Peter De Schrijver | 1 | -11/+34 |
2019-01-09 | clk: tegra: dfll: Fix a potential Oop in remove() | Dan Carpenter | 1 | -1/+3 |
2018-12-14 | Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '... | Stephen Boyd | 10 | -32/+80 |
2018-12-14 | clk: tegra: Return the exact clock rate from clk_round_rate | Robert Yang | 1 | -3/+4 |
2018-12-14 | clk: tegra30: Use Tegra CPU powergate helper function | Jon Hunter | 1 | -3/+3 |
2018-12-14 | clk: tegra: Fix maximum audio sync clock for Tegra124/210 | Jon Hunter | 7 | -13/+37 |
2018-12-14 | clk: tegra: get rid of duplicate defines | Marcel Ziswiler | 1 | -3/+0 |
2018-11-28 | clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro | Yangtao Li | 1 | -11/+1 |
2018-11-08 | clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC | Dmitry Osipenko | 1 | -0/+10 |
2018-11-08 | clk: tegra20: Turn EMC clock gate into divider | Dmitry Osipenko | 1 | -10/+26 |
2018-10-16 | clk: tegra210: Include size.h for compilation ease | Stephen Boyd | 1 | -0/+1 |
2018-10-16 | clk: tegra: Fixes for MBIST work around | Joseph Lo | 1 | -3/+3 |
2018-10-16 | clk: tegra: probe deferral error reporting | Marcel Ziswiler | 1 | -2/+6 |
2018-08-14 | Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',... | Stephen Boyd | 8 | -40/+343 |
2018-08-14 | Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te... | Stephen Boyd | 4 | -7/+15 |
2018-07-25 | clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks | Peter De-Schrijver | 3 | -15/+12 |
2018-07-25 | clk: tegra: Add sdmmc mux divider clock | Peter De-Schrijver | 3 | -0/+278 |
2018-07-25 | clk: tegra: Refactor fractional divider calculation | Peter De Schrijver | 4 | -25/+52 |
2018-07-25 | clk: tegra: Fix includes required by fence_udelay() | Aapo Vienamo | 1 | -0/+1 |
2018-07-08 | clk: tegra: emc: Avoid out-of-bounds bug | Dmitry Osipenko | 1 | -1/+1 |
2018-07-08 | clk: tegra: Mark Memory Controller clock as critical | Dmitry Osipenko | 1 | -2/+3 |
2018-07-08 | clk: tegra: Make vde a child of pll_c3 | Thierry Reding | 1 | -1/+1 |
2018-07-08 | clk: tegra: Make vic03 a child of pll_c3 | Thierry Reding | 1 | -0/+1 |
2018-07-08 | clk: tegra: bpmp: Don't crash when a clock fails to register | Mikko Perttunen | 1 | -3/+9 |
2018-06-12 | treewide: kzalloc() -> kcalloc() | Kees Cook | 1 | -3/+4 |
2018-06-04 | Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and... | Stephen Boyd | 1 | -31/+11 |
2018-06-01 | clk: tegra: no need to check return value of debugfs_create functions | Greg Kroah-Hartman | 1 | -31/+11 |
2018-05-18 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 | Dmitry Osipenko | 7 | -8/+39 |
2018-05-18 | clk: tegra20: Correct parents of CDEV1/2 clocks | Dmitry Osipenko | 1 | -4/+2 |
2018-05-18 | clk: tegra20: Add DEV1/DEV2 OSC dividers | Dmitry Osipenko | 1 | -0/+14 |
2018-03-12 | clk: tegra: Fix pll_u rate configuration | Marcel Ziswiler | 1 | -0/+2 |
2018-03-12 | clk: tegra: Specify VDE clock rate | Dmitry Osipenko | 4 | -1/+4 |
2018-03-12 | clk: tegra20: Correct PLL_C_OUT1 setup | Dmitry Osipenko | 1 | -3/+3 |
2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | Dmitry Osipenko | 8 | -36/+26 |
2018-03-08 | clk: tegra: MBIST work around for Tegra210 | Peter De Schrijver | 1 | -2/+342 |
2018-03-08 | clk: tegra: add fence_delay for clock registers | Peter De Schrijver | 1 | -0/+7 |
2018-03-08 | clk: tegra: Add la clock for Tegra210 | Peter De Schrijver | 1 | -0/+14 |
2017-11-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 13 | -66/+102 |
2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 2 | -0/+2 |
2017-11-01 | clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() | Nicolin Chen | 1 | -2/+2 |
2017-11-01 | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen | 3 | -13/+11 |
2017-11-01 | clk: tegra: Fix cclk_lp divisor register | Michał Mirosław | 1 | -1/+1 |
2017-11-01 | clk: tegra: Bump SCLK clock rate to 216 MHz | Dmitry Osipenko | 1 | -1/+1 |
2017-11-01 | clk: tegra: Use common definition of APBDMA clock gate | Dmitry Osipenko | 1 | -5/+1 |
2017-11-01 | clk: tegra: Correct parent of the APBDMA clock | Dmitry Osipenko | 1 | -1/+1 |
2017-11-01 | clk: tegra: Add AHB DMA clock entry | Dmitry Osipenko | 4 | -0/+4 |
2017-11-01 | clk: tegra: Mark APB clock as critical | Jon Hunter | 1 | -1/+1 |
2017-10-19 | clk: tegra: Make tegra_clk_pll_params __ro_after_init | Bhumika Goyal | 1 | -8/+8 |
2017-10-19 | clk: tegra: Fix sor1_out clock implementation | Thierry Reding | 2 | -16/+47 |
2017-10-19 | clk: tegra: Use tegra_clk_register_periph_data() | Thierry Reding | 4 | -13/+4 |
2017-10-19 | clk: tegra: Add peripheral clock registration helper | Thierry Reding | 2 | -0/+11 |
2017-10-19 | clk: tegra: Check BPMP response return code | Timo Alho | 1 | -5/+10 |
2017-08-23 | clk: tegra: Fix Tegra210 PLLU initialization | Alex Frid | 1 | -2/+4 |
2017-08-23 | clk: tegra: Correct Tegra210 UTMIPLL poweron delay | Alex Frid | 1 | -3/+3 |