aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra
AgeCommit message (Expand)AuthorFilesLines
2023-09-12clk: tegra: fix error return case for recalc_rateTimo Alho1-1/+1
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd1-4/+2
2023-08-04clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()Andy Shevchenko1-4/+2
2023-07-19clk: Explicitly include correct DT includesRob Herring5-5/+3
2023-07-04clk: tegra: Avoid calling an uninitialized functionThierry Reding1-3/+12
2023-06-26Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', 'cl...Stephen Boyd1-0/+2
2023-06-14clk: tegra: tegra124-emc: Fix potential memory leakYuan Can1-0/+2
2023-06-08clk: tegra: super: Switch to determine_rateMaxime Ripard1-4/+11
2023-06-08clk: tegra: periph: Switch to determine_rateMaxime Ripard1-5/+11
2023-06-08clk: tegra: periph: Add a determine_rate hookMaxime Ripard1-0/+1
2023-06-08clk: tegra: super: Add a determine_rate hookMaxime Ripard1-0/+1
2023-06-08clk: tegra: bpmp: Add a determine_rate hookMaxime Ripard1-0/+1
2023-04-25Merge branches 'clk-xilinx', 'clk-broadcom' and 'clk-platform' into clk-nextStephen Boyd2-10/+12
2023-03-29clk: tegra20: fix gcc-7 constant overflow warningArnd Bergmann1-14/+14
2023-03-28clk: tegra: Convert to platform remove callback returning voidUwe Kleine-König1-5/+3
2023-03-28clk: tegra: Don't warn three times about failure to unregisterUwe Kleine-König2-6/+10
2022-11-19clk: tegra: Support BPMP-FW ABI deny flagsPeter De Schrijver1-3/+34
2022-10-14clk: tegra: Fix Tegra PWM parent clockJon Hunter5-0/+5
2022-10-04Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'c...Stephen Boyd6-1/+6
2022-08-22clk: tegra20: Fix refcount leak in tegra20_clock_initMiaoqian Lin1-0/+1
2022-08-22clk: tegra: Fix refcount leak in tegra114_clock_initMiaoqian Lin1-0/+1
2022-08-22clk: tegra: Fix refcount leak in tegra210_clock_initMiaoqian Lin1-0/+1
2022-08-22clk: move from strlcpy with unused retval to strscpyWolfram Sang1-1/+1
2022-08-19clk: tegra: Add missing of_node_put()Liang He2-0/+2
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding1-4/+4
2022-05-04clk: tegra: Replace .round_rate() with .determine_rate()Rajkumar Kasirajan1-5/+10
2022-05-04clk: tegra: Register clocks from root to leafTimo Alho1-16/+56
2022-05-04clk: tegra: Add missing reset deassertionDiogo Ivo1-0/+12
2022-03-11clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driverMiaoqian Lin1-0/+1
2021-12-15clk: tegra: Support runtime PM and power domainDmitry Osipenko8-54/+420
2021-12-15clk: tegra: Make vde a child of pll_p on tegra114Dmitry Osipenko1-1/+1
2021-09-02Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-6/+2
2021-08-29clk: tegra: fix old-style declarationArnd Bergmann1-1/+1
2021-08-11clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko1-5/+1
2021-07-27clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko1-0/+10
2021-06-25clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean1-2/+2
2021-06-02clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang1-1/+3
2021-05-31clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko3-13/+1
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko1-3/+3
2021-05-31clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2-3/+15
2021-05-31clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko1-0/+3
2021-05-31clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko1-3/+3
2021-05-31clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-05-31clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
2021-05-31clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
2021-03-24clk: tegra: Don't enable PLLE HW sequencer at initJC Kuo1-12/+0
2021-03-24clk: tegra: Add PLLE HW power sequencer controlJC Kuo1-1/+52
2021-02-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-4/+2
2021-02-20Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds5-15/+75
2021-02-11clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s...Lee Jones1-0/+1
2021-02-11clk: tegra: clk-tegra30: Remove unused variable 'reg'Lee Jones1-4/+1
2021-01-12clk: tegra30: Add hda clock default rates to clock driverPeter Geis1-0/+2
2021-01-05memory: tegra124-emc: Make driver modularDmitry Osipenko5-15/+75
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds4-6/+7
2020-12-10clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2-1/+2
2020-11-26clk: tegra: bpmp: Clamp clock rates on requestsSivaram Nair1-3/+3
2020-11-20clk: tegra: Do not return 0 on failureNicolin Chen1-2/+2
2020-11-06clk: tegra: Export Tegra20 EMC kernel symbolsDmitry Osipenko1-0/+3
2020-10-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-1/+1
2020-09-23clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd1-1/+1
2020-09-21clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding1-0/+2
2020-09-21clk: tegra: Always program PLL_E when enabledThierry Reding1-3/+0
2020-09-21clk: tegra: Capitalization fixesThierry Reding1-2/+2
2020-07-27clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko1-5/+15
2020-06-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds10-32/+700
2020-05-12clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding1-1/+1
2020-05-12clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni1-0/+7
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko1-2/+4
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko1-2/+5
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2-0/+36
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2-1/+17
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko3-2/+188
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo1-19/+31
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo3-0/+373
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo1-0/+26
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo1-0/+11
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding4-6/+2
2020-03-24clk: tegra: Use NULL for pointer initializationStephen Boyd1-1/+1
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni5-15/+10
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni9-201/+19
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni6-45/+0
2020-03-12clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni1-6/+6
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni6-0/+14
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni6-0/+34
2020-01-31Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '...Stephen Boyd5-11/+15
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko2-2/+2
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko2-4/+0
2020-01-10clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko1-2/+7
2020-01-10clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni1-2/+1
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren1-1/+5
2019-12-24clk: tegra: Fix double-free in tegra_clk_init()Dmitry Osipenko1-1/+3
2019-11-13clk: tegra: Use match_string() helper to simplify the codeYueHaibing1-8/+4
2019-11-11clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing1-0/+2
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2-18/+32
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni3-4/+163
2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2-45/+45
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni1-4/+4
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni3-0/+59
2019-11-11clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni1-0/+27
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni4-1/+39
2019-11-11clk: tegra: periph: Add restore_context supportSowjanya Komatineni2-0/+37
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2-0/+16
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni1-32/+54
2019-11-11clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni1-0/+9
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni1-0/+11
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding1-16/+55
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding1-9/+13
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding3-8/+8
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2-8/+49
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding2-2/+2
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko5-52/+339
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-8/+12
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+2
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding1-1/+0
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding1-1/+5
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding1-2/+3
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo1-4/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter1-0/+2
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner20-240/+20
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner5-49/+5
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd4-40/+77
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd1-1/+1
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko1-1/+2
2019-04-25clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko1-1/+4
2019-04-25clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko1-7/+10
2019-04-25clk: tegra: emc: Support multiple RAM codesDmitry Osipenko1-14/+23
2019-04-25clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko1-2/+0
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko1-2/+1
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko1-2/+2
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2-5/+5
2019-04-19clk: tegra: Don't enable already enabled PLLsDmitry Osipenko1-13/+37
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing1-1/+1
2019-03-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-9/+9
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd1-9/+9
2019-02-22clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing1-9/+9
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann7-98/+913
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2-0/+427
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo1-8/+13
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo1-67/+377
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo4-14/+59
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver1-11/+34
2019-01-09clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter1-1/+3
2018-12-14Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd10-32/+80
2018-12-14clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang1-3/+4
2018-12-14clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter1-3/+3
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter7-13/+37
2018-12-14clk: tegra: get rid of duplicate definesMarcel Ziswiler1-3/+0
2018-11-28clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li1-11/+1
2018-11-08clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko1-0/+10
2018-11-08clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko1-10/+26
2018-10-16clk: tegra210: Include size.h for compilation easeStephen Boyd1-0/+1
2018-10-16clk: tegra: Fixes for MBIST work aroundJoseph Lo1-3/+3
2018-10-16clk: tegra: probe deferral error reportingMarcel Ziswiler1-2/+6
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd8-40/+343
2018-08-14Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd4-7/+15
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver3-15/+12
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver3-0/+278
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver4-25/+52
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo1-0/+1
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
2018-06-12treewide: kzalloc() -> kcalloc()Kees Cook1-3/+4
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Stephen Boyd1-31/+11
2018-06-01clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-31/+11
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko7-8/+39
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko1-4/+2
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko1-0/+14
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler1-0/+2
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko4-1/+4
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko1-3/+3
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko8-36/+26
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver1-2/+342
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver1-0/+7
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver1-0/+14
2017-11-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds13-66/+102
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2-0/+2
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen3-13/+11
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko1-5/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko4-0/+4
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter1-1/+1
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal1-8/+8
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding2-16/+47
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding4-13/+4
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding2-0/+11
2017-10-19clk: tegra: Check BPMP response return codeTimo Alho1-5/+10
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid1-3/+3