kernel/git/torvalds/linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author	Files	Lines
2024-04-25	clk: renesas: r9a08g045: Add support for power domains	Claudiu Beznea	1	-0/+41
2024-04-25	clk: renesas: rzg2l: Extend power domain support	Claudiu Beznea	2	-14/+252
2024-04-25	clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT	Geert Uytterhoeven	3	-6/+0
2024-04-25	clk: renesas: r8a7740: Remove unused div4_clk.flags field	Christophe JAILLET	1	-13/+12
2024-04-23	clk: renesas: r9a07g043: Add clock and reset entry for PLIC	Lad Prabhakar	1	-0/+9
2024-04-23	clk: renesas: r8a779h0: Add INTC-EX clock	Cong Dang	1	-0/+1
2024-04-23	clk: renesas: r8a779h0: Add MSIOF clocks	Cong Dang	1	-0/+6
2024-04-23	clk: renesas: r8a779a0: Fix CANFD parent clock	Geert Uytterhoeven	1	-1/+1
2024-04-08	clk: renesas: r8a779h0: Add timer clocks	Thanh Quan	1	-0/+9
2024-04-02	clk: renesas: r8a779h0: Add SCIF clocks	Geert Uytterhoeven	1	-0/+4
2024-03-26	clk: renesas: r9a07g044: Mark resets array as const	Paul Barker	1	-1/+1
2024-03-26	clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const	Paul Barker	1	-2/+2
2024-03-26	clk: renesas: r8a779h0: Add thermal clock	Geert Uytterhoeven	1	-0/+1
2024-02-20	clk: renesas: r8a779h0: Add RPC-IF clock	Cong Dang	1	-0/+1
2024-02-20	clk: renesas: r8a779h0: Add SYS-DMAC clocks	Cong Dang	1	-0/+2
2024-02-20	clk: renesas: r8a779h0: Add SDHI clock	Cong Dang	1	-0/+1
2024-02-20	clk: renesas: r8a779h0: Add EtherAVB clocks	Cong Dang	1	-0/+3
2024-02-13	clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable	Claudiu Beznea	2	-6/+6
2024-02-13	clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux	Claudiu Beznea	2	-2/+2
2024-02-13	clk: renesas: r8a779f0: Correct PFC/GPIO parent clock	Geert Uytterhoeven	1	-1/+1
2024-02-13	clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks	Geert Uytterhoeven	1	-5/+6
2024-02-06	clk: renesas: r8a779h0: Add I2C clocks	Cong Dang	1	-0/+4
2024-02-06	clk: renesas: r8a779h0: Add watchdog clock	Cong Dang	1	-0/+1
2024-02-06	clk: renesas: r8a779h0: Add PFC/GPIO clocks	Cong Dang	1	-0/+3
2024-01-31	clk: renesas: r8a779g0: Fix PCIe clock name	Geert Uytterhoeven	1	-1/+1
2024-01-31	clk: renesas: cpg-mssr: Add support for R-Car V4M	Cong Dang	5	-0/+254
2024-01-31	clk: renesas: rcar-gen4: Add support for FRQCRC1	Geert Uytterhoeven	1	-2/+8
2024-01-31	clk: renesas: r9a07g043: Add clock and reset entries for CRU	Biju Das	1	-0/+31
2024-01-31	clk: renesas: r9a08g045: Add clock and reset support for watchdog	Claudiu Beznea	1	-0/+3
2024-01-23	clk: renesas: mstp: Remove obsolete clkdev registration	Geert Uytterhoeven	1	-13/+3
2024-01-23	clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system	Kuninori Morimoto	1	-7/+104
2023-12-13	clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1	Claudiu Beznea	1	-0/+10
2023-12-13	clk: renesas: rzg2l: Check reset monitor registers	Claudiu Beznea	1	-15/+44
2023-12-13	clk: renesas: r9a08g045: Add IA55 pclk and its reset	Claudiu Beznea	1	-0/+3
2023-11-27	clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()	Claudiu Beznea	1	-23/+15
2023-11-20	clk: renesas: r8a779g0: Add PCIe clocks	Yoshihiro Shimoda	1	-0/+2
2023-11-20	clk: renesas: r8a779g0: Add EtherTSN clock	Niklas Söderlund	1	-0/+1
2023-10-12	clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2	Claudiu Beznea	1	-0/+34
2023-10-12	clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()	Claudiu Beznea	1	-1/+1
2023-10-10	clk: renesas: Add minimal boot support for RZ/G3S SoC	Claudiu Beznea	5	-1/+228
2023-10-10	clk: renesas: rzg2l: Add divider clock for RZ/G3S	Claudiu Beznea	2	-0/+197
2023-10-10	clk: renesas: rzg2l: Refactor SD mux driver	Claudiu Beznea	4	-51/+139
2023-10-05	clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header	Claudiu Beznea	3	-4/+14
2023-10-05	clk: renesas: rzg2l: Add struct clk_hw_data	Claudiu Beznea	1	-18/+34
2023-10-05	clk: renesas: rzg2l: Add support for RZ/G3S PLL	Claudiu Beznea	2	-4/+48
2023-10-05	clk: renesas: rzg2l: Remove critical area	Claudiu Beznea	1	-4/+1
2023-10-05	clk: renesas: rzg2l: Fix computation formula	Claudiu Beznea	1	-6/+6
2023-10-05	clk: renesas: rzg2l: Trust value returned by hardware	Claudiu Beznea	1	-7/+1
2023-10-05	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	2	-11/+14
2023-10-05	clk: renesas: rzg2l: Wait for status bit of SD mux before continuing	Claudiu Beznea	1	-7/+10
2023-10-05	clk: renesas: rcar-gen3: Extend SDnH divider table	Dirk Behme	1	-1/+14
2023-09-26	clk: renesas: r8a7795: Constify r8a7795_*_clks	Marek Vasut	1	-2/+2
2023-09-18	clk: renesas: r9a06g032: Name anonymous structs	Ralph Siemsen	1	-30/+33
2023-09-18	clk: renesas: r9a06g032: Fix kerneldoc warning	Ralph Siemsen	1	-0/+1
2023-09-18	clk: renesas: rzg2l: Use u32 for flag and mux_flags	Claudiu Beznea	1	-2/+2
2023-09-18	clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields	Claudiu Beznea	1	-5/+5
2023-09-18	clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()	Claudiu Beznea	1	-3/+2
2023-09-18	clk: renesas: rzg2l: Use core->name for clock name	Claudiu Beznea	1	-1/+1
2023-09-11	clk: renesas: r9a06g032: Use for_each_compatible_node()	Yang Yingliang	1	-3/+2
2023-08-30	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...	Stephen Boyd	17	-19/+73
2023-08-15	clk: renesas: rcar-gen3: Add ADG clocks	Kuninori Morimoto	9	-1/+9
2023-07-27	clk: renesas: r8a77965: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: r8a7796: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: r8a7795: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: emev2: Remove obsolete clkdev registration	Geert Uytterhoeven	1	-3/+0
2023-07-25	clk: renesas: r9a07g043: Add MTU3a clock and reset entry	Biju Das	1	-0/+3
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	3	-4/+1
2023-07-11	clk: renesas: rzg2l: Simplify .determine_rate()	Christophe JAILLET	1	-7/+1
2023-07-10	clk: renesas: r9a09g011: Add CSI related clocks	Fabrizio Castro	1	-0/+15
2023-07-10	clk: renesas: r8a774b1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774e1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774a1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: rcar-gen3: Add support for ZG clock	Adam Ford	2	-4/+32
2023-06-26	Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...	Stephen Boyd	6	-49/+27
2023-06-08	clk: renesas: r9a06g032: Add a determine_rate hook	Maxime Ripard	1	-0/+1
2023-06-05	clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+5
2023-06-05	clk: renesas: mstp: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+7
2023-06-05	clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-20/+11
2023-05-23	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	2	-7/+2
2023-05-08	clk: renesas: r8a779a0: Add PWM clock	Wolfram Sang	1	-0/+1
2023-04-29	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	7	-204/+591
2023-04-13	clk: renesas: remove MODULE_LICENSE in non-modules	Nick Alcock	2	-2/+0
2023-03-30	clk: renesas: r8a77980: Add I2C5 clock	Nikita Yushchenko	1	-0/+1
2023-03-16	clk: renesas: Convert to platform remove callback returning void	Uwe Kleine-König	1	-4/+2
2023-03-10	clk: renesas: r9a06g032: Improve clock tables	Ralph Siemsen	1	-153/+407
2023-03-10	clk: renesas: r9a06g032: Document structs	Ralph Siemsen	1	-1/+49
2023-03-10	clk: renesas: r9a06g032: Drop unused fields	Ralph Siemsen	1	-5/+10
2023-03-10	clk: renesas: r9a06g032: Improve readability	Ralph Siemsen	1	-41/+80
2023-03-10	clk: renesas: r8a77980: Add Z2 clock	Geert Uytterhoeven	1	-0/+1
2023-03-10	clk: renesas: r8a77970: Add Z2 clock	Geert Uytterhoeven	1	-0/+1
2023-03-06	clk: renesas: r8a77995: Fix VIN parent clock	Geert Uytterhoeven	1	-1/+1
2023-03-06	clk: renesas: r8a77980: Add VIN clocks	Niklas Söderlund	1	-0/+16
2023-03-06	clk: renesas: r8a779g0: Add VIN clocks	Niklas Söderlund	1	-0/+16
2023-03-06	clk: renesas: r8a779g0: Add ISPCS clocks	Niklas Söderlund	1	-0/+2
2023-03-06	clk: renesas: r8a779g0: Add CSI-2 clocks	Niklas Söderlund	1	-0/+3
2023-03-06	clk: renesas: r8a779g0: Add thermal clock	Geert Uytterhoeven	1	-0/+1
2023-03-06	clk: renesas: r8a779g0: Add Audio clocks	Kuninori Morimoto	1	-0/+2
2023-03-06	clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H	Takeshi Kihara	1	-4/+4
2023-02-10	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	Wolfram Sang	5	-173/+13
2023-01-26	clk: renesas: r8a779g0: Add CAN-FD clocks	Geert Uytterhoeven	1	-0/+2
2023-01-26	clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC	Kuninori Morimoto	1	-2/+2
2023-01-26	clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC	Kuninori Morimoto	1	-2/+2
2023-01-24	clk: renesas: r8a779g0: Add custom clock for PLL2	Geert Uytterhoeven	3	-7/+164
2023-01-23	clk: renesas: cpg-mssr: Remove superfluous check in resume code	Geert Uytterhoeven	1	-3/+2
2023-01-23	clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence	Herve Codina	1	-0/+28
2023-01-12	clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed	Alexey Khoroshilov	1	-1/+2
2023-01-12	clk: renesas: r9a07g044: Add clock and reset entries for CRU	Lad Prabhakar	1	-1/+25
2022-12-27	clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries	Phil Edworthy	1	-0/+20
2022-12-27	clk: renesas: r9a09g011: Add USB clock and reset entries	Biju Das	1	-0/+21
2022-12-27	clk: renesas: r9a09g011: Add TIM clock and reset entries	Biju Das	1	-0/+22
2022-12-26	clk: renesas: r8a779g0: Add display related clocks	Tomi Valkeinen	1	-0/+9
2022-12-26	clk: renesas: rcar-gen4: Restore PLL enum sort order	Geert Uytterhoeven	1	-1/+1
2022-12-26	clk: renesas: r8a779g0: Fix OSC predividers	Geert Uytterhoeven	1	-4/+4
2022-12-26	clk: renesas: r9a09g011: Add PWM clock and reset entries	Biju Das	1	-0/+10
2022-11-16	clk: renesas: r8a779f0: Fix Ethernet Switch clocks	Geert Uytterhoeven	1	-2/+2
2022-11-15	clk: renesas: r8a779g0: Add Z0 clock support	Geert Uytterhoeven	1	-0/+1
2022-11-08	clk: renesas: r8a779g0: Add CMT clocks	Wolfram Sang	1	-0/+4
2022-11-08	clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks	Wolfram Sang	1	-0/+6
2022-11-08	clk: renesas: r8a779f0: Fix SCIF parent clocks	Wolfram Sang	1	-4/+4
2022-11-08	clk: renesas: r8a779f0: Fix HSCIF parent clocks	Wolfram Sang	1	-4/+4
2022-11-01	clk: renesas: r9a06g032: Repair grave increment error	Marek Vasut	1	-2/+1
2022-10-28	clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM	Lad Prabhakar	2	-15/+28
2022-10-26	clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc	Lad Prabhakar	1	-1/+1
2022-10-26	clk: renesas: r8a779a0: Fix SD0H clock name	Wolfram Sang	1	-1/+1
2022-10-26	clk: renesas: r8a779g0: Add RPC-IF clock	Geert Uytterhoeven	1	-1/+2
2022-10-26	clk: renesas: r8a779g0: Add SDHI clocks	Geert Uytterhoeven	1	-1/+3
2022-10-26	clk: renesas: r8a779f0: Add SASYNCPER internal clock	Geert Uytterhoeven	1	-3/+5
2022-10-26	clk: renesas: r8a779f0: Fix SD0H clock name	Geert Uytterhoeven	1	-1/+1
2022-10-26	clk: renesas: r9a07g043: Drop WDT2 clock and reset entry	Lad Prabhakar	1	-5/+0
2022-10-26	clk: renesas: r9a07g044: Drop WDT2 clock and reset entry	Lad Prabhakar	1	-6/+1
2022-10-26	clk: renesas: r8a779g0: Add TPU clock	Geert Uytterhoeven	1	-0/+1
2022-10-26	clk: renesas: r8a779g0: Add PWM clock	Geert Uytterhoeven	1	-0/+1
2022-10-26	clk: renesas: r8a779g0: Add SCIF clocks	Geert Uytterhoeven	1	-0/+4
2022-10-26	Merge tag 'renesas-clk-fixes-for-v6.1-tag1'	Geert Uytterhoeven	1	-4/+9
2022-10-26	clk: renesas: r8a779g0: Fix HSCIF parent clocks	Geert Uytterhoeven	1	-4/+4
2022-10-18	clk: renesas: r8a779g0: Add SASYNCPER clocks	Geert Uytterhoeven	1	-0/+5
2022-10-17	clk: renesas: r9a07g044: Add MTU3a clock and reset entry	Biju Das	1	-1/+4
2022-10-17	clk: renesas: r8a779g0: Add INTC-EX clock	Geert Uytterhoeven	1	-0/+1
2022-10-17	clk: renesas: r8a779g0: Add MSIOF clocks	Geert Uytterhoeven	1	-0/+6
2022-10-17	clk: renesas: r8a779g0: Add SYS-DMAC clocks	Geert Uytterhoeven	1	-0/+2
2022-10-17	clk: renesas: r8a779f0: Add Ethernet Switch clocks	Yoshihiro Shimoda	1	-0/+2
2022-10-17	clk: renesas: rzg2l: Fix typo in function name	Lad Prabhakar	1	-3/+3
2022-10-17	clk: renesas: rzg2l: Support sd clk mux round operation	Biju Das	1	-1/+1
2022-09-18	clk: renesas: r8a779g0: Add EtherAVB clocks	Geert Uytterhoeven	1	-0/+3
2022-09-18	clk: renesas: r8a779g0: Add PFC/GPIO clocks	Geert Uytterhoeven	1	-0/+4
2022-09-18	clk: renesas: r8a779g0: Add I2C clocks	Geert Uytterhoeven	1	-0/+6
2022-09-18	clk: renesas: r8a779g0: Add watchdog clock	Geert Uytterhoeven	1	-0/+1
2022-08-29	clk: renesas: r8a779f0: Add MSIOF clocks	Wolfram Sang	1	-0/+4
2022-08-29	clk: renesas: r9a09g011: Add IIC clock and reset entries	Phil Edworthy	1	-0/+4
2022-08-22	clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info	Biju Das	1	-0/+2
2022-08-22	clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks	Wolfram Sang	1	-0/+10
2022-08-15	clk: renesas: r8a779f0: Add CMT clocks	Wolfram Sang	1	-0/+4
2022-08-15	clk: renesas: r8a779f0: Add SDH0 clock	Wolfram Sang	1	-1/+2
2022-07-05	clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config	Andi Kleen	1	-1/+1
2022-07-05	clk: renesas: r9a07g043: Add support for RZ/Five SoC	Lad Prabhakar	1	-0/+32
2022-06-17	clk: renesas: r8a779f0: Add HSCIF clocks	Wolfram Sang	1	-0/+4
2022-06-17	clk: renesas: r8a779f0: Add PCIe clocks	Yoshihiro Shimoda	1	-0/+2
2022-06-17	clk: renesas: r8a779f0: Add Z0 and Z1 clock support	Geert Uytterhoeven	1	-0/+2
2022-06-13	clk: renesas: rza1: Remove struct rz_cpg	Geert Uytterhoeven	1	-18/+15
2022-06-13	clk: renesas: r8a7779: Remove struct r8a7779_cpg	Geert Uytterhoeven	1	-18/+9
2022-06-13	clk: renesas: r8a7778: Remove struct r8a7778_cpg	Geert Uytterhoeven	1	-22/+9
2022-06-13	clk: renesas: sh73a0: Remove sh73a0_cpg.reg	Geert Uytterhoeven	1	-13/+13
2022-06-13	clk: renesas: r8a7740: Remove r8a7740_cpg.reg	Geert Uytterhoeven	1	-10/+10
2022-06-13	clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg	Geert Uytterhoeven	1	-11/+11
2022-06-13	clk: renesas: r8a779f0: Add SDHI0 clock	Wolfram Sang	1	-0/+1
2022-06-13	clk: renesas: r8a779f0: Add thermal clock	Wolfram Sang	1	-0/+1
2022-06-07	clk: renesas: rzg2l: Fix reset status function	Biju Das	1	-1/+1
2022-06-06	clk: renesas: r9a06g032: Fix UART clkgrp bitsel	Ralph Siemsen	1	-4/+4
2022-06-06	clk: renesas: r9a06g032: Drop some unused fields	Ralph Siemsen	1	-13/+11
2022-06-06	clk: renesas: r9a09g011: Add WDT clock and reset entries	Phil Edworthy	1	-0/+3
2022-06-06	clk: renesas: r9a09g011: Add PFC clock and reset entries	Phil Edworthy	1	-0/+2
2022-06-06	clk: renesas: r9a07g044: Add POEG clock and reset entries	Biju Das	1	-1/+13
2022-06-06	clk: renesas: r9a07g044: Add GPT clock and reset entry	Biju Das	1	-1/+4
2022-05-29	Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-1/+39
2022-05-19	clk: renesas: r9a06g032: Probe possible children	Miquel Raynal	1	-0/+5
2022-05-19	clk: renesas: r9a06g032: Export function to set dmamux	Miquel Raynal	1	-1/+34
2022-05-06	clk: renesas: r9a09g011: Add eth clock and reset entries	Phil Edworthy	1	-5/+9
2022-05-06	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	5	-0/+181
2022-05-05	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	2	-3/+17
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	4	-1/+16
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	3	-31/+19
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	3	-6/+12
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	3	-22/+19
2022-05-05	clk: renesas: r9a07g044: Fix OSTM1 module clock name	Geert Uytterhoeven	1	-1/+1
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for ADC	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add TSU clock and reset entry	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add RSPI clock and reset entries	Biju Das	1	-0/+9
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...	Biju Das	1	-0/+18
2022-05-05	clk: renesas: r9a07g044: Add DSI clock and reset entries	Biju Das	1	-1/+16
2022-05-05	clk: renesas: r9a07g044: Add LCDC clock and reset entries	Biju Das	1	-1/+8
2022-05-05	clk: renesas: r9a07g044: Add M4 Clock support	Biju Das	1	-1/+18
2022-05-05	clk: renesas: r9a07g044: Add M3 Clock support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add M1 clock support	Biju Das	1	-1/+10
2022-05-05	clk: renesas: rzg2l: Add DSI divider clk support	Biju Das	2	-0/+136
2022-05-05	clk: renesas: rzg2l: Add PLL5_4 clk mux support	Biju Das	2	-0/+103
2022-05-05	clk: renesas: rzg2l: Add FOUTPOSTDIV clk support	Biju Das	2	-0/+235
2022-04-29	clk: renesas: cpg-mssr: Add support for R-Car V4H	Yoshihiro Shimoda	5	-0/+231
2022-04-29	clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4	Yoshihiro Shimoda	4	-16/+24
2022-04-28	clk: renesas: r9a07g043: Add WDT clock and reset entries	Biju Das	1	-0/+10