tools/power/turbostat: Adjust cstate for models with .has_nhm_msrs set

Enable CC1/CC3/CC6 for platforms with .has_nhm_msrs set.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>

1 files changed, 28 insertions, 5 deletions

diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 6a49eb941fe0c..c7345e0c5185e 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -416,6 +416,7 @@ static const struct platform_features nhm_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_133MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_NHM,
 	.trl_msrs = TRL_BASE,
 };
@@ -424,6 +425,7 @@ static const struct platform_features nhx_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_133MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_NHM,
 };
 
@@ -432,6 +434,7 @@ static const struct platform_features snb_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SNB,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -442,6 +445,7 @@ static const struct platform_features snx_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SNB,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
@@ -453,6 +457,7 @@ static const struct platform_features ivb_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SNB,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -463,6 +468,7 @@ static const struct platform_features ivx_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SNB,
 	.trl_msrs = TRL_BASE | TRL_LIMIT1,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
@@ -474,6 +480,7 @@ static const struct platform_features hsw_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -486,6 +493,7 @@ static const struct platform_features hsx_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE | TRL_LIMIT1 | TRL_LIMIT2,
 	.plr_msrs = PLR_CORE | PLR_RING,
@@ -499,6 +507,7 @@ static const struct platform_features hswl_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -511,6 +520,7 @@ static const struct platform_features hswg_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -523,6 +533,7 @@ static const struct platform_features bdw_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -534,6 +545,7 @@ static const struct platform_features bdwg_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -545,6 +557,7 @@ static const struct platform_features bdx_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.has_cst_auto_convension = 1,
 	.trl_msrs = TRL_BASE,
@@ -559,6 +572,7 @@ static const struct platform_features skl_features = {
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
 	.crystal_freq = 24000000,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.tcc_offset_bits = 6,
@@ -572,6 +586,7 @@ static const struct platform_features cnl_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_HSW,
 	.trl_msrs = TRL_BASE,
 	.tcc_offset_bits = 6,
@@ -585,6 +600,7 @@ static const struct platform_features skx_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SKX,
 	.has_cst_auto_convension = 1,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
@@ -598,6 +614,7 @@ static const struct platform_features icx_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_ICX,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
@@ -610,6 +627,7 @@ static const struct platform_features spr_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SKX,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
@@ -618,6 +636,7 @@ static const struct platform_features spr_features = {
 static const struct platform_features slv_features = {
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_SLV,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SLV,
 	.trl_msrs = TRL_ATOM,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE,
@@ -629,6 +648,7 @@ static const struct platform_features slvd_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_SLV,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_SLV,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_CORE,
@@ -638,6 +658,7 @@ static const struct platform_features slvd_features = {
 static const struct platform_features amt_features = {
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_133MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_AMT,
 	.trl_msrs = TRL_BASE,
 };
@@ -647,6 +668,7 @@ static const struct platform_features gmt_features = {
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
 	.crystal_freq = 19200000,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_GMT,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
 	.rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
@@ -657,6 +679,7 @@ static const struct platform_features gmtd_features = {
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
 	.crystal_freq = 25000000,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_GMT,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_CORE_ENERGY_STATUS,
@@ -667,6 +690,7 @@ static const struct platform_features gmtp_features = {
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
 	.crystal_freq = 19200000,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_GMT,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
@@ -676,6 +700,7 @@ static const struct platform_features tmt_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_GMT,
 	.trl_msrs = TRL_BASE,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
@@ -686,6 +711,7 @@ static const struct platform_features tmtd_features = {
 	.has_msr_misc_pwr_mgmt = 1,
 	.has_nhm_msrs = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_GMT,
 	.trl_msrs = TRL_BASE | TRL_CORECOUNT,
 	.rapl_msrs = RAPL_PKG_ALL,
@@ -696,6 +722,7 @@ static const struct platform_features knl_features = {
 	.has_nhm_msrs = 1,
 	.has_config_tdp = 1,
 	.bclk_freq = BCLK_100MHZ,
+	.supported_cstates = CC1 | CC3 | CC6,
 	.cst_limit = CST_LIMIT_KNL,
 	.trl_msrs = TRL_KNL,
 	.rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
@@ -5797,12 +5824,8 @@ void process_cpuid()
 
 	probe_cstates();
 
-	if (platform->has_nhm_msrs) {
-		BIC_PRESENT(BIC_CPU_c1);
-		BIC_PRESENT(BIC_CPU_c3);
-		BIC_PRESENT(BIC_CPU_c6);
+	if (platform->has_nhm_msrs)
 		BIC_PRESENT(BIC_SMI);
-	}
 	probe_bclk();
 	do_snb_cstates = has_snb_msrs(family, model);