diff options
| author | Andrew Victor <andrew@sanpeople.com> | 2006-01-10 16:59:27 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-10 16:59:27 +0000 |
| commit | 1e6c9c2878c9c1f301449c78551e0b7c5f3e3ae5 (patch) | |
| tree | b53b95a16a4f5ee22b5ccb9a8fecbc771b9d566f /include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h | |
| parent | 977127174a7dff52d17faeeb4c4949a54221881f (diff) | |
| download | linux-1e6c9c2878c9c1f301449c78551e0b7c5f3e3ae5.tar.gz | |
[ARM] 3242/2: AT91RM9200 support for 2.6 (Serial)
Patch from Andrew Victor
This patch adds support to the 2.6 kernel series for the Atmel
AT91RM9200 processor.
This patch is the Serial driver.
This version uses the newly re-written GPL'ed hardware headers.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h')
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h new file mode 100644 index 0000000000000..ce1150d4438d4 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h @@ -0,0 +1,36 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Peripheral Data Controller (PDC) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_PDC_H +#define AT91RM9200_PDC_H + +#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ +#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ +#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ +#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ +#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ + +#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ +#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ +#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ +#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ +#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ + +#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ + +#endif |