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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2023-11-23 17:17:42 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2023-11-30 12:05:21 +0100 |
| commit | 6341e97b52b6238ed06dddc7ec22d025a9346a1e (patch) | |
| tree | e95df148dc3e7cf79e7156eefe4bf5b4737681c5 /drivers/pmdomain | |
| parent | e22fd8d5ca4a22126b1387b8b0bd2f5ff11925cf (diff) | |
| download | linux-6341e97b52b6238ed06dddc7ec22d025a9346a1e.tar.gz | |
pmdomain: amlogic: meson-ee-pwrc: add support for G12A ISP power domain
Add entries for the ISP power domain found in the Amlogic G12B SoC
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Tested-by: Daniel Scally <dan.scally@ideasonboard.com>
Link: https://lore.kernel.org/r/20231123-topic-amlogic-upstream-isp-pmdomain-v2-2-61f2fcf709e5@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/pmdomain')
| -rw-r--r-- | drivers/pmdomain/amlogic/meson-ee-pwrc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/pmdomain/amlogic/meson-ee-pwrc.c b/drivers/pmdomain/amlogic/meson-ee-pwrc.c index 0dd71cd814c52f..fcec6eb610e4ae 100644 --- a/drivers/pmdomain/amlogic/meson-ee-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-ee-pwrc.c @@ -47,6 +47,8 @@ #define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) #define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) +#define G12A_HHI_ISP_MEM_PD_REG0 (0x45 << 2) +#define G12A_HHI_ISP_MEM_PD_REG1 (0x46 << 2) struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -115,6 +117,13 @@ static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { .iso_mask = BIT(16) | BIT(17), }; +static struct meson_ee_pwrc_top_domain g12a_pwrc_isp = { + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, + .sleep_mask = BIT(18) | BIT(19), + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, + .iso_mask = BIT(18) | BIT(19), +}; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -231,6 +240,11 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_isp[] = { + { G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_ISP_MEM_PD_REG1, GENMASK(31, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -269,6 +283,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, pwrc_ee_is_powered_off), + [PWRC_G12A_ISP_ID] = TOP_PD("ISP", &g12a_pwrc_isp, g12a_pwrc_mem_isp, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { |