diff options
| author | Cong Dang <cong.dang.xn@renesas.com> | 2024-01-26 11:44:05 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-20 11:43:48 +0100 |
| commit | fbaff0364a42e3160c0fbc56087c4348434066d1 (patch) | |
| tree | 25155b975fc954ae85b1c451e037e25723ce0645 /drivers/pinctrl | |
| parent | bc56b11cd734a7c640a6e434cb40cd0c52da9376 (diff) | |
| download | linux-fbaff0364a42e3160c0fbc56087c4348434066d1.tar.gz | |
pinctrl: renesas: r8a779h0: Add SCIF_CLK pins, groups, functions
Add pins, groups and functions for the baud rate generation clock pins
(SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ee056d78d3a339bdbcca2cc5281f1fe01bbc3953.1706264667.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a779h0.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index 543beff4effe9f..c7c3e68ca77abf 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -1642,6 +1642,23 @@ static const unsigned int scif4_ctrl_mux[] = { RTS4_N_MARK, CTS4_N_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +static const unsigned int scif_clk2_pins[] = { + /* SCIF_CLK2 */ + RCAR_GP_PIN(4, 11), +}; +static const unsigned int scif_clk2_mux[] = { + SCIF_CLK2_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), @@ -1706,6 +1723,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif4_data), SH_PFC_PIN_GROUP(scif4_clk), SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk2), }; static const char * const avb0_groups[] = { @@ -1796,6 +1815,14 @@ static const char * const scif4_groups[] = { "scif4_ctrl", }; +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const scif_clk2_groups[] = { + "scif_clk2", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), @@ -1810,6 +1837,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif_clk2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { |