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| author | renjun wang <renjunw0@foxmail.com> | 2023-12-16 12:18:05 +0800 |
|---|---|---|
| committer | Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2024-02-05 12:57:44 +0100 |
| commit | c82523aca798e891fd1d29fce24c4d394fd64483 (patch) | |
| tree | 82f6843a32ed71132f79a09e8b013f5fad95acea /drivers/media | |
| parent | fd4f587389e1202ab5737977c11f09ea56bbd1b2 (diff) | |
| download | linux-c82523aca798e891fd1d29fce24c4d394fd64483.tar.gz | |
media: verisilicon: Fix some typos
Function hantro_g1_h264_dec_prepare_table() does not exist,
should be replaced with hantro_h264_dec_init().
The register name av1_ulticore_tile_col confused sometimes,
although not be used corrently. The correct name should be
av1_multicore_tile_col.
Signed-off-by: renjun wang <renjunw0@foxmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'drivers/media')
3 files changed, 3 insertions, 3 deletions
diff --git a/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c b/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c index 9de7f05eff2a6f..ad5c1a6634f5c8 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c +++ b/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c @@ -243,7 +243,7 @@ static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV); } - /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ + /* Auxiliary buffer prepared in hantro_h264_dec_init(). */ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE); } diff --git a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c index 46c1a83bcc4e00..6da87f5184bcbc 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c @@ -460,7 +460,7 @@ static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE); } - /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ + /* Auxiliary buffer prepared in hantro_h264_dec_init(). */ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); } diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h index 182e6c830ff696..850ff0f844248d 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h @@ -118,7 +118,7 @@ #define av1_mcomp_filt_type AV1_DEC_REG(11, 8, 0x7) #define av1_multicore_expect_context_update AV1_DEC_REG(11, 11, 0x1) #define av1_multicore_sbx_offset AV1_DEC_REG(11, 12, 0x7f) -#define av1_ulticore_tile_col AV1_DEC_REG(11, 19, 0x7f) +#define av1_multicore_tile_col AV1_DEC_REG(11, 19, 0x7f) #define av1_transform_mode AV1_DEC_REG(11, 27, 0x7) #define av1_dec_tile_size_mag AV1_DEC_REG(11, 30, 0x3) |