diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2024-02-13 18:12:30 +0000 |
|---|---|---|
| committer | Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2024-02-15 10:57:54 +0100 |
| commit | 9c7fa014ca320b0eb95062922a73563aa9734cd0 (patch) | |
| tree | 147ff8846465dc5ce3d82071ebffb2652d69f8f5 /drivers/media | |
| parent | f243df0a0be0bee39d60136a8f2d1616c63deb1c (diff) | |
| download | linux-9c7fa014ca320b0eb95062922a73563aa9734cd0.tar.gz | |
media: platform: rzg2l-cru: rzg2l-ip: Add delay after D-PHY reset
As per section 35.3.1 Starting Reception for the MIPI CSI-2 Input on the
latest hardware manual (R01UH0914EJ0140 Rev.1.40) it is mentioned that
after DPHY reset, we need to wait for 1 msec or more before start
receiving data from the sensor. So add a delay after pre_streamon().
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20240213181233.242316-3-biju.das.jz@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 9f351a05893e6c..8466b4e5590983 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +#include <linux/delay.h> #include "rzg2l-cru.h" struct rzg2l_cru_ip_format { @@ -71,6 +72,8 @@ static int rzg2l_cru_ip_s_stream(struct v4l2_subdev *sd, int enable) if (ret) return ret; + fsleep(1000); + ret = rzg2l_cru_start_image_processing(cru); if (ret) { v4l2_subdev_call(cru->ip.remote, video, post_streamoff); |