diff options
| author | Guanjun <guanjun@linux.alibaba.com> | 2023-12-11 13:37:04 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-12-11 11:52:16 +0530 |
| commit | 0c154698a0fc32957d00c6009d5389e086dc8acf (patch) | |
| tree | 0494c8a4610853a938eadd9f5910d9dca7a51071 /drivers/dma | |
| parent | 778dfacc903d4b1ef5b7a9726e3a36bc15913d29 (diff) | |
| download | linux-0c154698a0fc32957d00c6009d5389e086dc8acf.tar.gz | |
dmaengine: idxd: Fix incorrect descriptions for GRPCFG register
Fix incorrect descriptions for the GRPCFG register which has three
sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG).
No functional changes
Signed-off-by: Guanjun <guanjun@linux.alibaba.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fenghua Yu <fenghua.yu@intel.com>
Acked-by: Lijun Pan <lijun.pan@intel.com>
Link: https://lore.kernel.org/r/20231211053704.2725417-3-guanjun@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/idxd/registers.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea135..315c004f58e475 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,14 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to access. + * The GRPCFG register block is divided into three sub-registers, which + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move + * to the register block that contains the three sub-registers. + * Each register block is 64bits. And the ofs gives us the offset + * within the GRPWQCFG register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) |