diff options
| author | Fabrice Gasnier <fabrice.gasnier@foss.st.com> | 2022-11-23 14:36:09 +0100 |
|---|---|---|
| committer | William Breathitt Gray <william.gray@linaro.org> | 2022-11-26 16:49:28 -0500 |
| commit | fd5ac974fc25feed084c2d1599d0dddb4e0556bc (patch) | |
| tree | d1254320c7b9f41c43c02f2bab5ccba550ed31b9 /drivers/counter | |
| parent | 30a0b95b1335e12efef89dd78518ed3e4a71a763 (diff) | |
| download | linux-fd5ac974fc25feed084c2d1599d0dddb4e0556bc.tar.gz | |
counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update
The ARR (auto reload register) and CMP (compare) registers are
successively written. The status bits to check the update of these
registers are polled together with regmap_read_poll_timeout().
The condition to end the loop may become true, even if one of the register
isn't correctly updated.
So ensure both status bits are set before clearing them.
Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Diffstat (limited to 'drivers/counter')
| -rw-r--r-- | drivers/counter/stm32-lptimer-cnt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c index d6b80b6dfc287..8439755559b21 100644 --- a/drivers/counter/stm32-lptimer-cnt.c +++ b/drivers/counter/stm32-lptimer-cnt.c @@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv, /* ensure CMP & ARR registers are properly written */ ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, - (val & STM32_LPTIM_CMPOK_ARROK), + (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) return ret; |