diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-01-31 12:37:27 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-02-07 12:14:48 -0600 |
| commit | bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2 (patch) | |
| tree | b864bf25843835c2a10929038605b375e9ec60fc /drivers/clk | |
| parent | 286ffaafa6dcf91d1c119d8e2d59be303fadb8fc (diff) | |
| download | linux-bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2.tar.gz | |
clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks
Add missing QREF clocks for UFS MEM and UFS CARD controllers.
Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-sc8180x.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 1351c52bcacb4d..c72e3dbc6f88aa 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { }, }; +static struct clk_branch gcc_ufs_card_clkref_en = { + .halt_reg = 0x8c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_card_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_card_ahb_clk = { .halt_reg = 0x75014, .halt_check = BRANCH_HALT, @@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { }, }; +static struct clk_branch gcc_ufs_mem_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_mem_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk = { .halt_reg = 0x77014, .halt_check = BRANCH_HALT, @@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, + [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, @@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, + [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, |