diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2024-01-03 21:20:18 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-02-16 11:43:05 -0600 |
| commit | 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 (patch) | |
| tree | fd464febb3ef71e9576426245d37329bcec056fd /drivers/clk | |
| parent | 6624b25c206e8cce6b93ef3e24d95b3d6e0c52d5 (diff) | |
| download | linux-117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82.tar.gz | |
clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
SDM845 downstream uses non-default values for GDSC internal waits.
Program them accordingly to avoid surprises.
Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6
Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/dispcc-sdm845.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 501dc29f8054c..b84fdd17c3d8c 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { static struct gdsc mdss_gdsc = { .gdscr = 0x3000, + .en_few_wait_val = 0x6, + .en_rest_wait_val = 0x5, .pd = { .name = "mdss_gdsc", }, |