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| author | Vineet Gupta <vgupta@kernel.org> | 2024-03-27 22:19:25 -0700 |
|---|---|---|
| committer | Vineet Gupta <vgupta@kernel.org> | 2024-04-01 18:40:39 -0700 |
| commit | d5272aaa8257920c7b398f953ada65e25c248f9a (patch) | |
| tree | 9d0318884cfe44c0761fc81d7acdadf7f5abf85b /arch | |
| parent | db70d9f9dcf8d5cda86303eeb381b1213a2ab191 (diff) | |
| download | linux-d5272aaa8257920c7b398f953ada65e25c248f9a.tar.gz | |
ARC: mm: fix new code about cache aliasing
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) [1] however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
[1] http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Acked-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arc/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arc/include/asm/cachetype.h | 9 |
2 files changed, 0 insertions, 10 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 99d2845f3feb95..4092bec198beca 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -6,7 +6,6 @@ config ARC def_bool y select ARC_TIMERS - select ARCH_HAS_CPU_CACHE_ALIASING select ARCH_HAS_CACHE_LINE_SIZE select ARCH_HAS_DEBUG_VM_PGTABLE select ARCH_HAS_DMA_PREP_COHERENT diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h deleted file mode 100644 index 05fc7ed5971258..00000000000000 --- a/arch/arc/include/asm/cachetype.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARC_CACHETYPE_H -#define __ASM_ARC_CACHETYPE_H - -#include <linux/types.h> - -#define cpu_dcache_is_aliasing() true - -#endif |