diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2024-02-13 19:04:00 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-03-06 20:53:32 +0530 |
| commit | d808f0b1be4888a87524164bc7dad2242734de38 (patch) | |
| tree | af81b59f1c491397e593924b53965081f17b2ab1 /arch/riscv | |
| parent | d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d (diff) | |
| download | linux-d808f0b1be4888a87524164bc7dad2242734de38.tar.gz | |
RISC-V: KVM: Forward SEED CSR access to user space
The SEED CSR access from VS/VU mode (guest) will always trap to
HS-mode (KVM) when Zkr extension is available to the Guest/VM.
Forward this CSR access to KVM user space so that it can be
emulated based on the method chosen by VMM.
Fixes: f370b4e668f0 ("RISC-V: KVM: Allow scalar crypto extensions for Guest/VM")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kvm/vcpu_insn.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 7a6abed41bc17..ee7215f4071f5 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -7,6 +7,8 @@ #include <linux/bitops.h> #include <linux/kvm_host.h> +#include <asm/cpufeature.h> + #define INSN_OPCODE_MASK 0x007c #define INSN_OPCODE_SHIFT 2 #define INSN_OPCODE_SYSTEM 28 @@ -213,9 +215,20 @@ struct csr_func { unsigned long wr_mask); }; +static int seed_csr_rmw(struct kvm_vcpu *vcpu, unsigned int csr_num, + unsigned long *val, unsigned long new_val, + unsigned long wr_mask) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, ZKR)) + return KVM_INSN_ILLEGAL_TRAP; + + return KVM_INSN_EXIT_TO_USER_SPACE; +} + static const struct csr_func csr_funcs[] = { KVM_RISCV_VCPU_AIA_CSR_FUNCS KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS + { .base = CSR_SEED, .count = 1, .func = seed_csr_rmw }, }; /** |