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| author | Chen Wang <unicorn_wang@outlook.com> | 2024-01-30 09:50:51 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@outlook.com> | 2024-02-23 12:38:03 +0800 |
| commit | 08573ba006ab7bc29c183e0b3c362a0b34f1d87b (patch) | |
| tree | 96f207606b7d237d429549ee4373f2e5224379c8 /arch/riscv | |
| parent | 1ce7587e507e1762df1dadc22affcd41376040d5 (diff) | |
| download | linux-08573ba006ab7bc29c183e0b3c362a0b34f1d87b.tar.gz | |
riscv: dts: add resets property for uart node
Add resets property for uart0 for completeness, although it is
deasserted by default.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://lore.kernel.org/r/807f75e433a0f900da40ebb6a448349c98580072.1706577450.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index eeb341e16bfd6..81fda312f988c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -343,6 +343,7 @@ clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; }; |