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| author | Johan Hovold <johan+linaro@kernel.org> | 2024-03-06 10:56:47 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2024-03-08 17:05:46 +0100 |
| commit | c8073025c0e4d4b441b83950a7fcc2e5cb44eb5d (patch) | |
| tree | 8e08a0a82b29831a23680a65e4b13b9cd32f28a4 /Documentation | |
| parent | 544e8f96efc08134454e8513667f59be1f2e3c57 (diff) | |
| download | linux-c8073025c0e4d4b441b83950a7fcc2e5cb44eb5d.tar.gz | |
dt-bindings: PCI: qcom: Allow 'required-opps'
Some Qualcomm SoCs require a minimum performance level for the power
domain so add 'required-opps' to the binding.
Link: https://lore.kernel.org/r/20240306095651.4551-2-johan+linaro@kernel.org
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 3 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 125136176f9305..8d570669650ad1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -59,6 +59,9 @@ properties: power-domains: maxItems: 1 + required-opps: + maxItems: 1 + resets: minItems: 1 maxItems: 12 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index aedd23a71c708d..df3a183ca5a0c5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -105,6 +105,9 @@ properties: description: GPIO controlled connection to PERST# signal maxItems: 1 + required-opps: + maxItems: 1 + wake-gpios: description: GPIO controlled connection to WAKE# signal maxItems: 1 |