diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:40 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:13 -0700 |
| commit | b88727d554f0fb826e0608192f59542497ba19c5 (patch) | |
| tree | 2a9db15e143dee39ce9468a4a67ed52b301ae8b2 /Documentation | |
| parent | be5e8872b3fbc74b4a58a7e6a7e9fb7e8509eaf8 (diff) | |
| download | linux-b88727d554f0fb826e0608192f59542497ba19c5.tar.gz | |
dt-bindings: riscv: Add Andes interrupt controller compatible string
Add "andestech,cpu-intc" compatible string to indicate that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
which can be handled in supervisor mode:
- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt
These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-5-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 9d8670c00e3b3b..6ccd75cbbc59d1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -106,7 +106,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true |