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| author | Mark Brown <broonie@kernel.org> | 2023-09-15 13:18:06 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-09-29 15:56:17 +0100 |
| commit | 5d5b4e8c2d9ec12a5cc013b82c1873cd387e0ddf (patch) | |
| tree | f7705ca29fb1e96d692e1e69e2fbe56ab2dcfd42 /Documentation/arch | |
| parent | 6465e260f48790807eef06b583b38ca9789b6072 (diff) | |
| download | linux-5d5b4e8c2d9ec12a5cc013b82c1873cd387e0ddf.tar.gz | |
arm64/sve: Report FEAT_SVE_B16B16 to userspace
SVE 2.1 introduced a new feature FEAT_SVE_B16B16 which adds instructions
supporting the BFloat16 floating point format. Report this to userspace
through the ID registers and hwcap.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230915-arm64-zfr-b16b16-el0-v1-1-f9aba807bdb5@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arch')
| -rw-r--r-- | Documentation/arch/arm64/cpu-feature-registers.rst | 2 | ||||
| -rw-r--r-- | Documentation/arch/arm64/elf_hwcaps.rst | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index de6d8a4790e2b..44f9bd78539d3 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -268,6 +268,8 @@ infrastructure: +------------------------------+---------+---------+ | SHA3 | [35-32] | y | +------------------------------+---------+---------+ + | B16B16 | [27-24] | y | + +------------------------------+---------+---------+ | BF16 | [23-20] | y | +------------------------------+---------+---------+ | BitPerm | [19-16] | y | diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 76ff9d7398fda..2ad0a369d96a9 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -308,6 +308,9 @@ HWCAP2_MOPS HWCAP2_HBC Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001. +HWCAP2_SVE_B16B16 + Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- |