diff options
| author | Ard Biesheuvel <ardb@kernel.org> | 2024-04-15 09:54:14 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-04-18 18:00:37 +0100 |
| commit | 2b504e1620376052744ebee408a84394bdaef40a (patch) | |
| tree | cc412fa40a6e2fb4b3a6ae5d50a81253de4c1718 | |
| parent | 015a12a4a6708d9cadcaea8334e270747923394c (diff) | |
| download | linux-2b504e1620376052744ebee408a84394bdaef40a.tar.gz | |
arm64/head: Drop unnecessary pre-disable-MMU workaround
The Falkor erratum that results in the need for an ISB before clearing
the M bit in SCTLR_ELx only applies to execution at exception level x,
and so the workaround is not needed when disabling the EL1 MMU while
running at EL2.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240415075412.2347624-5-ardb+git@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/kernel/head.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 06234c3a15f3db..b8bbd72cb1944f 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -323,13 +323,11 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) cbz x0, 2f /* Set a sane SCTLR_EL1, the VHE way */ - pre_disable_mmu_workaround msr_s SYS_SCTLR_EL12, x1 mov x2, #BOOT_CPU_FLAG_E2H b 3f 2: - pre_disable_mmu_workaround msr sctlr_el1, x1 mov x2, xzr 3: |