diff options
Diffstat (limited to 'arch/sparc64/kernel/head.S')
| -rw-r--r-- | arch/sparc64/kernel/head.S | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S index 0d6f58dad2db7..954093551597f 100644 --- a/arch/sparc64/kernel/head.S +++ b/arch/sparc64/kernel/head.S @@ -89,8 +89,8 @@ sparc_ramdisk_image64: * PROM entry point is on %o4 */ sparc64_boot: - BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_boot) - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_boot) + BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) ba,pt %xcc, spitfire_boot nop @@ -103,11 +103,11 @@ cheetah_boot: mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 wr %g1, %asr18 - sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 - or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 - sllx %g5, 32, %g5 - or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5 - stxa %g5, [%g0] ASI_DCU_CONTROL_REG + sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 + or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 + sllx %g7, 32, %g7 + or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7 + stxa %g7, [%g0] ASI_DCU_CONTROL_REG membar #Sync cheetah_generic_boot: @@ -492,7 +492,7 @@ sun4u_init: stxa %g3, [%g2] ASI_DMMU membar #Sync - BRANCH_IF_ANY_CHEETAH(g1,g5,cheetah_tlb_fixup) + BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup) ba,pt %xcc, spitfire_tlb_fixup nop @@ -520,8 +520,8 @@ cheetah_tlb_fixup: mov 1, %g2 /* Set TLB type to cheetah. */ -1: sethi %hi(tlb_type), %g5 - stw %g2, [%g5 + %lo(tlb_type)] +1: sethi %hi(tlb_type), %g1 + stw %g2, [%g1 + %lo(tlb_type)] BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) ba,pt %xcc, 2f @@ -567,8 +567,8 @@ spitfire_tlb_fixup: /* Set TLB type to spitfire. */ mov 0, %g2 - sethi %hi(tlb_type), %g5 - stw %g2, [%g5 + %lo(tlb_type)] + sethi %hi(tlb_type), %g1 + stw %g2, [%g1 + %lo(tlb_type)] tlb_fixup_done: sethi %hi(init_thread_union), %g6 @@ -596,12 +596,18 @@ tlb_fixup_done: #endif wr %g0, ASI_P, %asi - mov 1, %g5 - sllx %g5, THREAD_SHIFT, %g5 - sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 - add %g6, %g5, %sp + mov 1, %g1 + sllx %g1, THREAD_SHIFT, %g1 + sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 + add %g6, %g1, %sp mov 0, %fp + /* Set per-cpu pointer initially to zero, this makes + * the boot-cpu use the in-kernel-image per-cpu areas + * before setup_per_cpu_area() is invoked. + */ + clr %g5 + wrpr %g0, 0, %wstate wrpr %g0, 0x0, %tl @@ -637,8 +643,8 @@ setup_tba: /* i0 = is_starfire */ rdpr %pstate, %o1 mov %g6, %o2 wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate - sethi %hi(sparc64_ttable_tl0), %g5 - wrpr %g5, %tba + sethi %hi(sparc64_ttable_tl0), %g1 + wrpr %g1, %tba mov %o2, %g6 /* Set up MMU globals */ |