diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2004-08-01 06:43:47 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-08-01 06:43:47 -0700 |
| commit | f059989bca20a55ccfc4bc8b9283e837874e605c (patch) | |
| tree | eceb9315c89e53c84af4b686e2bb24aab8ec752d /include | |
| parent | be55649e00e02405019f9bc3bb15f5a57255272b (diff) | |
| download | history-f059989bca20a55ccfc4bc8b9283e837874e605c.tar.gz | |
[PATCH] ppc32: Workaround new MPC745x CPU erratas
The latest versions of Motorola erratas for the MPC745x CPUs (and 744x)
adds a couple of nasty ones for which we really want workarounds in the
kernel. One is to disable the BTIC branch target cache on some revs
(too bad for performances...) and the other one is to force cacheable
memory pages to always be marked as SMP coherent even on UP systems (I
didn't measure significant perfs impact with this one).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/cputable.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h index 4c07a0cac979c5..fcdb87db389bcd 100644 --- a/include/asm-ppc/cputable.h +++ b/include/asm-ppc/cputable.h @@ -76,6 +76,7 @@ extern struct cpu_spec *cur_cpu_spec[]; #define CPU_FTR_NO_DPM 0x00008000 #define CPU_FTR_HAS_HIGH_BATS 0x00010000 #define CPU_FTR_NEED_COHERENT 0x00020000 +#define CPU_FTR_NO_BTIC 0x00040000 #ifdef __ASSEMBLY__ |